1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2024 Intel Corporation. */ 3 4 #include <linux/types.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/netdevice.h> 8 #include <linux/vmalloc.h> 9 #include <linux/string.h> 10 #include <linux/in.h> 11 #include <linux/interrupt.h> 12 #include <linux/ip.h> 13 #include <linux/tcp.h> 14 #include <linux/sctp.h> 15 #include <linux/pkt_sched.h> 16 #include <linux/ipv6.h> 17 #include <linux/slab.h> 18 #include <net/checksum.h> 19 #include <net/ip6_checksum.h> 20 #include <linux/etherdevice.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/if_macvlan.h> 25 #include <linux/if_bridge.h> 26 #include <linux/prefetch.h> 27 #include <linux/bpf.h> 28 #include <linux/bpf_trace.h> 29 #include <linux/atomic.h> 30 #include <linux/numa.h> 31 #include <generated/utsrelease.h> 32 #include <scsi/fc/fc_fcoe.h> 33 #include <net/udp_tunnel.h> 34 #include <net/pkt_cls.h> 35 #include <net/tc_act/tc_gact.h> 36 #include <net/tc_act/tc_mirred.h> 37 #include <net/vxlan.h> 38 #include <net/mpls.h> 39 #include <net/netdev_queues.h> 40 #include <net/xdp_sock_drv.h> 41 #include <net/xfrm.h> 42 43 #include "ixgbe.h" 44 #include "ixgbe_common.h" 45 #include "ixgbe_e610.h" 46 #include "ixgbe_dcb_82599.h" 47 #include "ixgbe_mbx.h" 48 #include "ixgbe_phy.h" 49 #include "ixgbe_sriov.h" 50 #include "ixgbe_model.h" 51 #include "ixgbe_txrx_common.h" 52 53 char ixgbe_driver_name[] = "ixgbe"; 54 static const char ixgbe_driver_string[] = 55 "Intel(R) 10 Gigabit PCI Express Network Driver"; 56 #ifdef IXGBE_FCOE 57 char ixgbe_default_device_descr[] = 58 "Intel(R) 10 Gigabit Network Connection"; 59 #else 60 static char ixgbe_default_device_descr[] = 61 "Intel(R) 10 Gigabit Network Connection"; 62 #endif 63 static const char ixgbe_copyright[] = 64 "Copyright (c) 1999-2016 Intel Corporation."; 65 66 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 67 68 static const struct ixgbe_info *ixgbe_info_tbl[] = { 69 [board_82598] = &ixgbe_82598_info, 70 [board_82599] = &ixgbe_82599_info, 71 [board_X540] = &ixgbe_X540_info, 72 [board_X550] = &ixgbe_X550_info, 73 [board_X550EM_x] = &ixgbe_X550EM_x_info, 74 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info, 75 [board_x550em_a] = &ixgbe_x550em_a_info, 76 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info, 77 [board_e610] = &ixgbe_e610_info, 78 }; 79 80 /* ixgbe_pci_tbl - PCI Device ID Table 81 * 82 * Wildcard entries (PCI_ANY_ID) should come last 83 * Last entry must be all 0s 84 * 85 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 86 * Class, Class Mask, private data (not used) } 87 */ 88 static const struct pci_device_id ixgbe_pci_tbl[] = { 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550}, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x}, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw}, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a }, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a }, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a }, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a }, 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a}, 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a }, 134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw }, 135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw }, 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_E610_BACKPLANE), board_e610}, 137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_E610_SFP), board_e610}, 138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_E610_10G_T), board_e610}, 139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_E610_2_5G_T), board_e610}, 140 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_E610_SGMII), board_e610}, 141 /* required last entry */ 142 {0, } 143 }; 144 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 145 146 #ifdef CONFIG_IXGBE_DCA 147 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 148 void *p); 149 static struct notifier_block dca_notifier = { 150 .notifier_call = ixgbe_notify_dca, 151 .next = NULL, 152 .priority = 0 153 }; 154 #endif 155 156 #ifdef CONFIG_PCI_IOV 157 static unsigned int max_vfs; 158 module_param(max_vfs, uint, 0); 159 MODULE_PARM_DESC(max_vfs, 160 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 161 #endif /* CONFIG_PCI_IOV */ 162 163 static bool allow_unsupported_sfp; 164 module_param(allow_unsupported_sfp, bool, 0444); 165 MODULE_PARM_DESC(allow_unsupported_sfp, 166 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 167 168 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 169 static int debug = -1; 170 module_param(debug, int, 0); 171 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 172 173 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 174 MODULE_LICENSE("GPL v2"); 175 176 DEFINE_STATIC_KEY_FALSE(ixgbe_xdp_locking_key); 177 EXPORT_SYMBOL(ixgbe_xdp_locking_key); 178 179 static struct workqueue_struct *ixgbe_wq; 180 181 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 182 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *); 183 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *); 184 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *); 185 186 static const struct net_device_ops ixgbe_netdev_ops; 187 188 static bool netif_is_ixgbe(struct net_device *dev) 189 { 190 return dev && (dev->netdev_ops == &ixgbe_netdev_ops); 191 } 192 193 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 194 u32 reg, u16 *value) 195 { 196 struct pci_dev *parent_dev; 197 struct pci_bus *parent_bus; 198 199 parent_bus = adapter->pdev->bus->parent; 200 if (!parent_bus) 201 return -1; 202 203 parent_dev = parent_bus->self; 204 if (!parent_dev) 205 return -1; 206 207 if (!pci_is_pcie(parent_dev)) 208 return -1; 209 210 pcie_capability_read_word(parent_dev, reg, value); 211 if (*value == IXGBE_FAILED_READ_CFG_WORD && 212 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 213 return -1; 214 return 0; 215 } 216 217 static int ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 218 { 219 struct ixgbe_hw *hw = &adapter->hw; 220 u16 link_status = 0; 221 int err; 222 223 hw->bus.type = ixgbe_bus_type_pci_express; 224 225 /* Get the negotiated link width and speed from PCI config space of the 226 * parent, as this device is behind a switch 227 */ 228 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 229 230 /* assume caller will handle error case */ 231 if (err) 232 return err; 233 234 hw->bus.width = ixgbe_convert_bus_width(link_status); 235 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 236 237 return 0; 238 } 239 240 /** 241 * ixgbe_pcie_from_parent - Determine whether PCIe info should come from parent 242 * @hw: hw specific details 243 * 244 * This function is used by probe to determine whether a device's PCI-Express 245 * bandwidth details should be gathered from the parent bus instead of from the 246 * device. Used to ensure that various locations all have the correct device ID 247 * checks. 248 * 249 * Return: true if information should be collected from the parent bus, false 250 * otherwise 251 */ 252 static bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 253 { 254 switch (hw->device_id) { 255 case IXGBE_DEV_ID_82599_SFP_SF_QP: 256 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 257 return true; 258 default: 259 return false; 260 } 261 } 262 263 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 264 int expected_gts) 265 { 266 struct ixgbe_hw *hw = &adapter->hw; 267 struct pci_dev *pdev; 268 269 /* Some devices are not connected over PCIe and thus do not negotiate 270 * speed. These devices do not have valid bus info, and thus any report 271 * we generate may not be correct. 272 */ 273 if (hw->bus.type == ixgbe_bus_type_internal) 274 return; 275 276 /* determine whether to use the parent device */ 277 if (ixgbe_pcie_from_parent(&adapter->hw)) 278 pdev = adapter->pdev->bus->parent->self; 279 else 280 pdev = adapter->pdev; 281 282 pcie_print_link_status(pdev); 283 } 284 285 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 286 { 287 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 288 !test_bit(__IXGBE_REMOVING, &adapter->state) && 289 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 290 queue_work(ixgbe_wq, &adapter->service_task); 291 } 292 293 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 294 { 295 struct ixgbe_adapter *adapter = hw->back; 296 297 if (!hw->hw_addr) 298 return; 299 hw->hw_addr = NULL; 300 e_dev_err("Adapter removed\n"); 301 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 302 ixgbe_service_event_schedule(adapter); 303 } 304 305 static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 306 { 307 u8 __iomem *reg_addr; 308 u32 value; 309 int i; 310 311 reg_addr = READ_ONCE(hw->hw_addr); 312 if (ixgbe_removed(reg_addr)) 313 return IXGBE_FAILED_READ_REG; 314 315 /* Register read of 0xFFFFFFF can indicate the adapter has been removed, 316 * so perform several status register reads to determine if the adapter 317 * has been removed. 318 */ 319 for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) { 320 value = readl(reg_addr + IXGBE_STATUS); 321 if (value != IXGBE_FAILED_READ_REG) 322 break; 323 mdelay(3); 324 } 325 326 if (value == IXGBE_FAILED_READ_REG) 327 ixgbe_remove_adapter(hw); 328 else 329 value = readl(reg_addr + reg); 330 return value; 331 } 332 333 /** 334 * ixgbe_read_reg - Read from device register 335 * @hw: hw specific details 336 * @reg: offset of register to read 337 * 338 * Returns : value read or IXGBE_FAILED_READ_REG if removed 339 * 340 * This function is used to read device registers. It checks for device 341 * removal by confirming any read that returns all ones by checking the 342 * status register value for all ones. This function avoids reading from 343 * the hardware if a removal was previously detected in which case it 344 * returns IXGBE_FAILED_READ_REG (all ones). 345 */ 346 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 347 { 348 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr); 349 u32 value; 350 351 if (ixgbe_removed(reg_addr)) 352 return IXGBE_FAILED_READ_REG; 353 if (unlikely(hw->phy.nw_mng_if_sel & 354 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) { 355 struct ixgbe_adapter *adapter; 356 int i; 357 358 for (i = 0; i < 200; ++i) { 359 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); 360 if (likely(!value)) 361 goto writes_completed; 362 if (value == IXGBE_FAILED_READ_REG) { 363 ixgbe_remove_adapter(hw); 364 return IXGBE_FAILED_READ_REG; 365 } 366 udelay(5); 367 } 368 369 adapter = hw->back; 370 e_warn(hw, "register writes incomplete %08x\n", value); 371 } 372 373 writes_completed: 374 value = readl(reg_addr + reg); 375 if (unlikely(value == IXGBE_FAILED_READ_REG)) 376 value = ixgbe_check_remove(hw, reg); 377 return value; 378 } 379 380 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 381 { 382 u16 value; 383 384 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 385 if (value == IXGBE_FAILED_READ_CFG_WORD) { 386 ixgbe_remove_adapter(hw); 387 return true; 388 } 389 return false; 390 } 391 392 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 393 { 394 struct ixgbe_adapter *adapter = hw->back; 395 u16 value; 396 397 if (ixgbe_removed(hw->hw_addr)) 398 return IXGBE_FAILED_READ_CFG_WORD; 399 pci_read_config_word(adapter->pdev, reg, &value); 400 if (value == IXGBE_FAILED_READ_CFG_WORD && 401 ixgbe_check_cfg_remove(hw, adapter->pdev)) 402 return IXGBE_FAILED_READ_CFG_WORD; 403 return value; 404 } 405 406 #ifdef CONFIG_PCI_IOV 407 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 408 { 409 struct ixgbe_adapter *adapter = hw->back; 410 u32 value; 411 412 if (ixgbe_removed(hw->hw_addr)) 413 return IXGBE_FAILED_READ_CFG_DWORD; 414 pci_read_config_dword(adapter->pdev, reg, &value); 415 if (value == IXGBE_FAILED_READ_CFG_DWORD && 416 ixgbe_check_cfg_remove(hw, adapter->pdev)) 417 return IXGBE_FAILED_READ_CFG_DWORD; 418 return value; 419 } 420 #endif /* CONFIG_PCI_IOV */ 421 422 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 423 { 424 struct ixgbe_adapter *adapter = hw->back; 425 426 if (ixgbe_removed(hw->hw_addr)) 427 return; 428 pci_write_config_word(adapter->pdev, reg, value); 429 } 430 431 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 432 { 433 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 434 435 /* flush memory to make sure state is correct before next watchdog */ 436 smp_mb__before_atomic(); 437 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 438 } 439 440 struct ixgbe_reg_info { 441 u32 ofs; 442 char *name; 443 }; 444 445 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 446 447 /* General Registers */ 448 {IXGBE_CTRL, "CTRL"}, 449 {IXGBE_STATUS, "STATUS"}, 450 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 451 452 /* Interrupt Registers */ 453 {IXGBE_EICR, "EICR"}, 454 455 /* RX Registers */ 456 {IXGBE_SRRCTL(0), "SRRCTL"}, 457 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 458 {IXGBE_RDLEN(0), "RDLEN"}, 459 {IXGBE_RDH(0), "RDH"}, 460 {IXGBE_RDT(0), "RDT"}, 461 {IXGBE_RXDCTL(0), "RXDCTL"}, 462 {IXGBE_RDBAL(0), "RDBAL"}, 463 {IXGBE_RDBAH(0), "RDBAH"}, 464 465 /* TX Registers */ 466 {IXGBE_TDBAL(0), "TDBAL"}, 467 {IXGBE_TDBAH(0), "TDBAH"}, 468 {IXGBE_TDLEN(0), "TDLEN"}, 469 {IXGBE_TDH(0), "TDH"}, 470 {IXGBE_TDT(0), "TDT"}, 471 {IXGBE_TXDCTL(0), "TXDCTL"}, 472 473 /* List Terminator */ 474 { .name = NULL } 475 }; 476 477 478 /* 479 * ixgbe_regdump - register printout routine 480 */ 481 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 482 { 483 int i; 484 char rname[16]; 485 u32 regs[64]; 486 487 switch (reginfo->ofs) { 488 case IXGBE_SRRCTL(0): 489 for (i = 0; i < 64; i++) 490 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 491 break; 492 case IXGBE_DCA_RXCTRL(0): 493 for (i = 0; i < 64; i++) 494 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 495 break; 496 case IXGBE_RDLEN(0): 497 for (i = 0; i < 64; i++) 498 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 499 break; 500 case IXGBE_RDH(0): 501 for (i = 0; i < 64; i++) 502 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 503 break; 504 case IXGBE_RDT(0): 505 for (i = 0; i < 64; i++) 506 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 507 break; 508 case IXGBE_RXDCTL(0): 509 for (i = 0; i < 64; i++) 510 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 511 break; 512 case IXGBE_RDBAL(0): 513 for (i = 0; i < 64; i++) 514 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 515 break; 516 case IXGBE_RDBAH(0): 517 for (i = 0; i < 64; i++) 518 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 519 break; 520 case IXGBE_TDBAL(0): 521 for (i = 0; i < 64; i++) 522 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 523 break; 524 case IXGBE_TDBAH(0): 525 for (i = 0; i < 64; i++) 526 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 527 break; 528 case IXGBE_TDLEN(0): 529 for (i = 0; i < 64; i++) 530 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 531 break; 532 case IXGBE_TDH(0): 533 for (i = 0; i < 64; i++) 534 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 535 break; 536 case IXGBE_TDT(0): 537 for (i = 0; i < 64; i++) 538 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 539 break; 540 case IXGBE_TXDCTL(0): 541 for (i = 0; i < 64; i++) 542 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 543 break; 544 default: 545 pr_info("%-15s %08x\n", 546 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs)); 547 return; 548 } 549 550 i = 0; 551 while (i < 64) { 552 int j; 553 char buf[9 * 8 + 1]; 554 char *p = buf; 555 556 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7); 557 for (j = 0; j < 8; j++) 558 p += sprintf(p, " %08x", regs[i++]); 559 pr_err("%-15s%s\n", rname, buf); 560 } 561 562 } 563 564 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n) 565 { 566 struct ixgbe_tx_buffer *tx_buffer; 567 568 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean]; 569 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 570 n, ring->next_to_use, ring->next_to_clean, 571 (u64)dma_unmap_addr(tx_buffer, dma), 572 dma_unmap_len(tx_buffer, len), 573 tx_buffer->next_to_watch, 574 (u64)tx_buffer->time_stamp); 575 } 576 577 /* 578 * ixgbe_dump - Print registers, tx-rings and rx-rings 579 */ 580 static void ixgbe_dump(struct ixgbe_adapter *adapter) 581 { 582 struct net_device *netdev = adapter->netdev; 583 struct ixgbe_hw *hw = &adapter->hw; 584 struct ixgbe_reg_info *reginfo; 585 int n = 0; 586 struct ixgbe_ring *ring; 587 struct ixgbe_tx_buffer *tx_buffer; 588 union ixgbe_adv_tx_desc *tx_desc; 589 struct my_u0 { u64 a; u64 b; } *u0; 590 struct ixgbe_ring *rx_ring; 591 union ixgbe_adv_rx_desc *rx_desc; 592 struct ixgbe_rx_buffer *rx_buffer_info; 593 int i = 0; 594 595 if (!netif_msg_hw(adapter)) 596 return; 597 598 /* Print netdevice Info */ 599 if (netdev) { 600 dev_info(&adapter->pdev->dev, "Net device Info\n"); 601 pr_info("Device Name state " 602 "trans_start\n"); 603 pr_info("%-15s %016lX %016lX\n", 604 netdev->name, 605 netdev->state, 606 dev_trans_start(netdev)); 607 } 608 609 /* Print Registers */ 610 dev_info(&adapter->pdev->dev, "Register Dump\n"); 611 pr_info(" Register Name Value\n"); 612 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 613 reginfo->name; reginfo++) { 614 ixgbe_regdump(hw, reginfo); 615 } 616 617 /* Print TX Ring Summary */ 618 if (!netdev || !netif_running(netdev)) 619 return; 620 621 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 622 pr_info(" %s %s %s %s\n", 623 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 624 "leng", "ntw", "timestamp"); 625 for (n = 0; n < adapter->num_tx_queues; n++) { 626 ring = adapter->tx_ring[n]; 627 ixgbe_print_buffer(ring, n); 628 } 629 630 for (n = 0; n < adapter->num_xdp_queues; n++) { 631 ring = adapter->xdp_ring[n]; 632 ixgbe_print_buffer(ring, n); 633 } 634 635 /* Print TX Rings */ 636 if (!netif_msg_tx_done(adapter)) 637 goto rx_ring_summary; 638 639 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 640 641 /* Transmit Descriptor Formats 642 * 643 * 82598 Advanced Transmit Descriptor 644 * +--------------------------------------------------------------+ 645 * 0 | Buffer Address [63:0] | 646 * +--------------------------------------------------------------+ 647 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 648 * +--------------------------------------------------------------+ 649 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 650 * 651 * 82598 Advanced Transmit Descriptor (Write-Back Format) 652 * +--------------------------------------------------------------+ 653 * 0 | RSV [63:0] | 654 * +--------------------------------------------------------------+ 655 * 8 | RSV | STA | NXTSEQ | 656 * +--------------------------------------------------------------+ 657 * 63 36 35 32 31 0 658 * 659 * 82599+ Advanced Transmit Descriptor 660 * +--------------------------------------------------------------+ 661 * 0 | Buffer Address [63:0] | 662 * +--------------------------------------------------------------+ 663 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 664 * +--------------------------------------------------------------+ 665 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 666 * 667 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 668 * +--------------------------------------------------------------+ 669 * 0 | RSV [63:0] | 670 * +--------------------------------------------------------------+ 671 * 8 | RSV | STA | RSV | 672 * +--------------------------------------------------------------+ 673 * 63 36 35 32 31 0 674 */ 675 676 for (n = 0; n < adapter->num_tx_queues; n++) { 677 ring = adapter->tx_ring[n]; 678 pr_info("------------------------------------\n"); 679 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index); 680 pr_info("------------------------------------\n"); 681 pr_info("%s%s %s %s %s %s\n", 682 "T [desc] [address 63:0 ] ", 683 "[PlPOIdStDDt Ln] [bi->dma ] ", 684 "leng", "ntw", "timestamp", "bi->skb"); 685 686 for (i = 0; ring->desc && (i < ring->count); i++) { 687 tx_desc = IXGBE_TX_DESC(ring, i); 688 tx_buffer = &ring->tx_buffer_info[i]; 689 u0 = (struct my_u0 *)tx_desc; 690 if (dma_unmap_len(tx_buffer, len) > 0) { 691 const char *ring_desc; 692 693 if (i == ring->next_to_use && 694 i == ring->next_to_clean) 695 ring_desc = " NTC/U"; 696 else if (i == ring->next_to_use) 697 ring_desc = " NTU"; 698 else if (i == ring->next_to_clean) 699 ring_desc = " NTC"; 700 else 701 ring_desc = ""; 702 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s", 703 i, 704 le64_to_cpu((__force __le64)u0->a), 705 le64_to_cpu((__force __le64)u0->b), 706 (u64)dma_unmap_addr(tx_buffer, dma), 707 dma_unmap_len(tx_buffer, len), 708 tx_buffer->next_to_watch, 709 (u64)tx_buffer->time_stamp, 710 tx_buffer->skb, 711 ring_desc); 712 713 if (netif_msg_pktdata(adapter) && 714 tx_buffer->skb) 715 print_hex_dump(KERN_INFO, "", 716 DUMP_PREFIX_ADDRESS, 16, 1, 717 tx_buffer->skb->data, 718 dma_unmap_len(tx_buffer, len), 719 true); 720 } 721 } 722 } 723 724 /* Print RX Rings Summary */ 725 rx_ring_summary: 726 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 727 pr_info("Queue [NTU] [NTC]\n"); 728 for (n = 0; n < adapter->num_rx_queues; n++) { 729 rx_ring = adapter->rx_ring[n]; 730 pr_info("%5d %5X %5X\n", 731 n, rx_ring->next_to_use, rx_ring->next_to_clean); 732 } 733 734 /* Print RX Rings */ 735 if (!netif_msg_rx_status(adapter)) 736 return; 737 738 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 739 740 /* Receive Descriptor Formats 741 * 742 * 82598 Advanced Receive Descriptor (Read) Format 743 * 63 1 0 744 * +-----------------------------------------------------+ 745 * 0 | Packet Buffer Address [63:1] |A0/NSE| 746 * +----------------------------------------------+------+ 747 * 8 | Header Buffer Address [63:1] | DD | 748 * +-----------------------------------------------------+ 749 * 750 * 751 * 82598 Advanced Receive Descriptor (Write-Back) Format 752 * 753 * 63 48 47 32 31 30 21 20 16 15 4 3 0 754 * +------------------------------------------------------+ 755 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 756 * | Packet | IP | | | | Type | Type | 757 * | Checksum | Ident | | | | | | 758 * +------------------------------------------------------+ 759 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 760 * +------------------------------------------------------+ 761 * 63 48 47 32 31 20 19 0 762 * 763 * 82599+ Advanced Receive Descriptor (Read) Format 764 * 63 1 0 765 * +-----------------------------------------------------+ 766 * 0 | Packet Buffer Address [63:1] |A0/NSE| 767 * +----------------------------------------------+------+ 768 * 8 | Header Buffer Address [63:1] | DD | 769 * +-----------------------------------------------------+ 770 * 771 * 772 * 82599+ Advanced Receive Descriptor (Write-Back) Format 773 * 774 * 63 48 47 32 31 30 21 20 17 16 4 3 0 775 * +------------------------------------------------------+ 776 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 777 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 778 * |/ Flow Dir Flt ID | | | | | | 779 * +------------------------------------------------------+ 780 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 781 * +------------------------------------------------------+ 782 * 63 48 47 32 31 20 19 0 783 */ 784 785 for (n = 0; n < adapter->num_rx_queues; n++) { 786 rx_ring = adapter->rx_ring[n]; 787 pr_info("------------------------------------\n"); 788 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 789 pr_info("------------------------------------\n"); 790 pr_info("%s%s%s\n", 791 "R [desc] [ PktBuf A0] ", 792 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 793 "<-- Adv Rx Read format"); 794 pr_info("%s%s%s\n", 795 "RWB[desc] [PcsmIpSHl PtRs] ", 796 "[vl er S cks ln] ---------------- [bi->skb ] ", 797 "<-- Adv Rx Write-Back format"); 798 799 for (i = 0; i < rx_ring->count; i++) { 800 const char *ring_desc; 801 802 if (i == rx_ring->next_to_use) 803 ring_desc = " NTU"; 804 else if (i == rx_ring->next_to_clean) 805 ring_desc = " NTC"; 806 else 807 ring_desc = ""; 808 809 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 810 rx_desc = IXGBE_RX_DESC(rx_ring, i); 811 u0 = (struct my_u0 *)rx_desc; 812 if (rx_desc->wb.upper.length) { 813 /* Descriptor Done */ 814 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n", 815 i, 816 le64_to_cpu((__force __le64)u0->a), 817 le64_to_cpu((__force __le64)u0->b), 818 rx_buffer_info->skb, 819 ring_desc); 820 } else { 821 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n", 822 i, 823 le64_to_cpu((__force __le64)u0->a), 824 le64_to_cpu((__force __le64)u0->b), 825 (u64)rx_buffer_info->dma, 826 rx_buffer_info->skb, 827 ring_desc); 828 829 if (netif_msg_pktdata(adapter) && 830 rx_buffer_info->dma) { 831 print_hex_dump(KERN_INFO, "", 832 DUMP_PREFIX_ADDRESS, 16, 1, 833 page_address(rx_buffer_info->page) + 834 rx_buffer_info->page_offset, 835 ixgbe_rx_bufsz(rx_ring), true); 836 } 837 } 838 } 839 } 840 } 841 842 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 843 { 844 u32 ctrl_ext; 845 846 /* Let firmware take over control of h/w */ 847 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 848 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 849 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 850 } 851 852 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 853 { 854 u32 ctrl_ext; 855 856 /* Let firmware know the driver has taken over */ 857 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 858 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 859 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 860 } 861 862 /** 863 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 864 * @adapter: pointer to adapter struct 865 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 866 * @queue: queue to map the corresponding interrupt to 867 * @msix_vector: the vector to map to the corresponding queue 868 * 869 */ 870 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 871 u8 queue, u8 msix_vector) 872 { 873 u32 ivar, index; 874 struct ixgbe_hw *hw = &adapter->hw; 875 switch (hw->mac.type) { 876 case ixgbe_mac_82598EB: 877 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 878 if (direction == -1) 879 direction = 0; 880 index = (((direction * 64) + queue) >> 2) & 0x1F; 881 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 882 ivar &= ~(0xFF << (8 * (queue & 0x3))); 883 ivar |= (msix_vector << (8 * (queue & 0x3))); 884 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 885 break; 886 case ixgbe_mac_82599EB: 887 case ixgbe_mac_X540: 888 case ixgbe_mac_X550: 889 case ixgbe_mac_X550EM_x: 890 case ixgbe_mac_x550em_a: 891 case ixgbe_mac_e610: 892 if (direction == -1) { 893 /* other causes */ 894 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 895 index = ((queue & 1) * 8); 896 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 897 ivar &= ~(0xFF << index); 898 ivar |= (msix_vector << index); 899 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 900 break; 901 } else { 902 /* tx or rx causes */ 903 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 904 index = ((16 * (queue & 1)) + (8 * direction)); 905 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 906 ivar &= ~(0xFF << index); 907 ivar |= (msix_vector << index); 908 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 909 break; 910 } 911 default: 912 break; 913 } 914 } 915 916 void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 917 u64 qmask) 918 { 919 u32 mask; 920 921 switch (adapter->hw.mac.type) { 922 case ixgbe_mac_82598EB: 923 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 924 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 925 break; 926 case ixgbe_mac_82599EB: 927 case ixgbe_mac_X540: 928 case ixgbe_mac_X550: 929 case ixgbe_mac_X550EM_x: 930 case ixgbe_mac_x550em_a: 931 case ixgbe_mac_e610: 932 mask = (qmask & 0xFFFFFFFF); 933 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 934 mask = (qmask >> 32); 935 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 936 break; 937 default: 938 break; 939 } 940 } 941 942 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 943 { 944 struct ixgbe_hw *hw = &adapter->hw; 945 struct ixgbe_hw_stats *hwstats = &adapter->stats; 946 int i; 947 u32 data; 948 949 if ((hw->fc.current_mode != ixgbe_fc_full) && 950 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 951 return; 952 953 switch (hw->mac.type) { 954 case ixgbe_mac_82598EB: 955 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 956 break; 957 default: 958 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 959 } 960 hwstats->lxoffrxc += data; 961 962 /* refill credits (no tx hang) if we received xoff */ 963 if (!data) 964 return; 965 966 for (i = 0; i < adapter->num_tx_queues; i++) 967 clear_bit(__IXGBE_HANG_CHECK_ARMED, 968 &adapter->tx_ring[i]->state); 969 970 for (i = 0; i < adapter->num_xdp_queues; i++) 971 clear_bit(__IXGBE_HANG_CHECK_ARMED, 972 &adapter->xdp_ring[i]->state); 973 } 974 975 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 976 { 977 struct ixgbe_hw *hw = &adapter->hw; 978 struct ixgbe_hw_stats *hwstats = &adapter->stats; 979 u32 xoff[8] = {0}; 980 u8 tc; 981 int i; 982 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 983 984 if (adapter->ixgbe_ieee_pfc) 985 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 986 987 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 988 ixgbe_update_xoff_rx_lfc(adapter); 989 return; 990 } 991 992 /* update stats for each tc, only valid with PFC enabled */ 993 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 994 u32 pxoffrxc; 995 996 switch (hw->mac.type) { 997 case ixgbe_mac_82598EB: 998 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 999 break; 1000 default: 1001 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 1002 } 1003 hwstats->pxoffrxc[i] += pxoffrxc; 1004 /* Get the TC for given UP */ 1005 tc = netdev_get_prio_tc_map(adapter->netdev, i); 1006 xoff[tc] += pxoffrxc; 1007 } 1008 1009 /* disarm tx queues that have received xoff frames */ 1010 for (i = 0; i < adapter->num_tx_queues; i++) { 1011 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 1012 1013 tc = tx_ring->dcb_tc; 1014 if (xoff[tc]) 1015 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1016 } 1017 1018 for (i = 0; i < adapter->num_xdp_queues; i++) { 1019 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 1020 1021 tc = xdp_ring->dcb_tc; 1022 if (xoff[tc]) 1023 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state); 1024 } 1025 } 1026 1027 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1028 { 1029 return ring->stats.packets; 1030 } 1031 1032 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1033 { 1034 unsigned int head, tail; 1035 1036 head = ring->next_to_clean; 1037 tail = ring->next_to_use; 1038 1039 return ((head <= tail) ? tail : tail + ring->count) - head; 1040 } 1041 1042 static bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1043 { 1044 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1045 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1046 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1047 1048 clear_check_for_tx_hang(tx_ring); 1049 1050 /* 1051 * Check for a hung queue, but be thorough. This verifies 1052 * that a transmit has been completed since the previous 1053 * check AND there is at least one packet pending. The 1054 * ARMED bit is set to indicate a potential hang. The 1055 * bit is cleared if a pause frame is received to remove 1056 * false hang detection due to PFC or 802.3x frames. By 1057 * requiring this to fail twice we avoid races with 1058 * pfc clearing the ARMED bit and conditions where we 1059 * run the check_tx_hang logic with a transmit completion 1060 * pending but without time to complete it yet. 1061 */ 1062 if (tx_done_old == tx_done && tx_pending) 1063 /* make sure it is true for two checks in a row */ 1064 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1065 &tx_ring->state); 1066 /* update completed stats and continue */ 1067 tx_ring->tx_stats.tx_done_old = tx_done; 1068 /* reset the countdown */ 1069 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1070 1071 return false; 1072 } 1073 1074 /** 1075 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1076 * @adapter: driver private struct 1077 **/ 1078 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1079 { 1080 1081 /* Do the reset outside of interrupt context */ 1082 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1083 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 1084 e_warn(drv, "initiating reset due to tx timeout\n"); 1085 ixgbe_service_event_schedule(adapter); 1086 } 1087 } 1088 1089 /** 1090 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate 1091 * @netdev: network interface device structure 1092 * @queue_index: Tx queue to set 1093 * @maxrate: desired maximum transmit bitrate 1094 **/ 1095 static int ixgbe_tx_maxrate(struct net_device *netdev, 1096 int queue_index, u32 maxrate) 1097 { 1098 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1099 struct ixgbe_hw *hw = &adapter->hw; 1100 u32 bcnrc_val = ixgbe_link_mbps(adapter); 1101 1102 if (!maxrate) 1103 return 0; 1104 1105 /* Calculate the rate factor values to set */ 1106 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; 1107 bcnrc_val /= maxrate; 1108 1109 /* clear everything but the rate factor */ 1110 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | 1111 IXGBE_RTTBCNRC_RF_DEC_MASK; 1112 1113 /* enable the rate scheduler */ 1114 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; 1115 1116 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); 1117 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 1118 1119 return 0; 1120 } 1121 1122 /** 1123 * ixgbe_update_tx_ring_stats - Update Tx ring specific counters 1124 * @tx_ring: ring to update 1125 * @q_vector: queue vector ring belongs to 1126 * @pkts: number of processed packets 1127 * @bytes: number of processed bytes 1128 */ 1129 void ixgbe_update_tx_ring_stats(struct ixgbe_ring *tx_ring, 1130 struct ixgbe_q_vector *q_vector, u64 pkts, 1131 u64 bytes) 1132 { 1133 u64_stats_update_begin(&tx_ring->syncp); 1134 tx_ring->stats.bytes += bytes; 1135 tx_ring->stats.packets += pkts; 1136 u64_stats_update_end(&tx_ring->syncp); 1137 q_vector->tx.total_bytes += bytes; 1138 q_vector->tx.total_packets += pkts; 1139 } 1140 1141 /** 1142 * ixgbe_update_rx_ring_stats - Update Rx ring specific counters 1143 * @rx_ring: ring to update 1144 * @q_vector: queue vector ring belongs to 1145 * @pkts: number of processed packets 1146 * @bytes: number of processed bytes 1147 */ 1148 void ixgbe_update_rx_ring_stats(struct ixgbe_ring *rx_ring, 1149 struct ixgbe_q_vector *q_vector, u64 pkts, 1150 u64 bytes) 1151 { 1152 u64_stats_update_begin(&rx_ring->syncp); 1153 rx_ring->stats.bytes += bytes; 1154 rx_ring->stats.packets += pkts; 1155 u64_stats_update_end(&rx_ring->syncp); 1156 q_vector->rx.total_bytes += bytes; 1157 q_vector->rx.total_packets += pkts; 1158 } 1159 1160 /** 1161 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1162 * @q_vector: structure containing interrupt and ring information 1163 * @tx_ring: tx ring to clean 1164 * @napi_budget: Used to determine if we are in netpoll 1165 **/ 1166 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1167 struct ixgbe_ring *tx_ring, int napi_budget) 1168 { 1169 struct ixgbe_adapter *adapter = q_vector->adapter; 1170 struct ixgbe_tx_buffer *tx_buffer; 1171 union ixgbe_adv_tx_desc *tx_desc; 1172 unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0; 1173 unsigned int budget = q_vector->tx.work_limit; 1174 unsigned int i = tx_ring->next_to_clean; 1175 struct netdev_queue *txq; 1176 1177 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1178 return true; 1179 1180 tx_buffer = &tx_ring->tx_buffer_info[i]; 1181 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1182 i -= tx_ring->count; 1183 1184 do { 1185 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1186 1187 /* if next_to_watch is not set then there is no work pending */ 1188 if (!eop_desc) 1189 break; 1190 1191 /* prevent any other reads prior to eop_desc */ 1192 smp_rmb(); 1193 1194 /* if DD is not set pending work has not been completed */ 1195 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1196 break; 1197 1198 /* clear next_to_watch to prevent false hangs */ 1199 tx_buffer->next_to_watch = NULL; 1200 1201 /* update the statistics for this packet */ 1202 total_bytes += tx_buffer->bytecount; 1203 total_packets += tx_buffer->gso_segs; 1204 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC) 1205 total_ipsec++; 1206 1207 /* free the skb */ 1208 if (ring_is_xdp(tx_ring)) 1209 xdp_return_frame(tx_buffer->xdpf); 1210 else 1211 napi_consume_skb(tx_buffer->skb, napi_budget); 1212 1213 /* unmap skb header data */ 1214 dma_unmap_single(tx_ring->dev, 1215 dma_unmap_addr(tx_buffer, dma), 1216 dma_unmap_len(tx_buffer, len), 1217 DMA_TO_DEVICE); 1218 1219 /* clear tx_buffer data */ 1220 dma_unmap_len_set(tx_buffer, len, 0); 1221 1222 /* unmap remaining buffers */ 1223 while (tx_desc != eop_desc) { 1224 tx_buffer++; 1225 tx_desc++; 1226 i++; 1227 if (unlikely(!i)) { 1228 i -= tx_ring->count; 1229 tx_buffer = tx_ring->tx_buffer_info; 1230 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1231 } 1232 1233 /* unmap any remaining paged data */ 1234 if (dma_unmap_len(tx_buffer, len)) { 1235 dma_unmap_page(tx_ring->dev, 1236 dma_unmap_addr(tx_buffer, dma), 1237 dma_unmap_len(tx_buffer, len), 1238 DMA_TO_DEVICE); 1239 dma_unmap_len_set(tx_buffer, len, 0); 1240 } 1241 } 1242 1243 /* move us one more past the eop_desc for start of next pkt */ 1244 tx_buffer++; 1245 tx_desc++; 1246 i++; 1247 if (unlikely(!i)) { 1248 i -= tx_ring->count; 1249 tx_buffer = tx_ring->tx_buffer_info; 1250 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1251 } 1252 1253 /* issue prefetch for next Tx descriptor */ 1254 prefetch(tx_desc); 1255 1256 /* update budget accounting */ 1257 budget--; 1258 } while (likely(budget)); 1259 1260 i += tx_ring->count; 1261 tx_ring->next_to_clean = i; 1262 ixgbe_update_tx_ring_stats(tx_ring, q_vector, total_packets, 1263 total_bytes); 1264 adapter->tx_ipsec += total_ipsec; 1265 1266 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1267 /* schedule immediate reset if we believe we hung */ 1268 struct ixgbe_hw *hw = &adapter->hw; 1269 e_err(drv, "Detected Tx Unit Hang %s\n" 1270 " Tx Queue <%d>\n" 1271 " TDH, TDT <%x>, <%x>\n" 1272 " next_to_use <%x>\n" 1273 " next_to_clean <%x>\n" 1274 "tx_buffer_info[next_to_clean]\n" 1275 " time_stamp <%lx>\n" 1276 " jiffies <%lx>\n", 1277 ring_is_xdp(tx_ring) ? "(XDP)" : "", 1278 tx_ring->queue_index, 1279 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1280 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1281 tx_ring->next_to_use, i, 1282 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1283 1284 if (!ring_is_xdp(tx_ring)) 1285 netif_stop_subqueue(tx_ring->netdev, 1286 tx_ring->queue_index); 1287 1288 e_info(probe, 1289 "tx hang %d detected on queue %d, resetting adapter\n", 1290 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1291 1292 /* schedule immediate reset if we believe we hung */ 1293 ixgbe_tx_timeout_reset(adapter); 1294 1295 /* the adapter is about to reset, no point in enabling stuff */ 1296 return true; 1297 } 1298 1299 if (ring_is_xdp(tx_ring)) 1300 return !!budget; 1301 1302 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1303 txq = netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 1304 if (!__netif_txq_completed_wake(txq, total_packets, total_bytes, 1305 ixgbe_desc_unused(tx_ring), 1306 TX_WAKE_THRESHOLD, 1307 !netif_carrier_ok(tx_ring->netdev) || 1308 test_bit(__IXGBE_DOWN, &adapter->state))) 1309 ++tx_ring->tx_stats.restart_queue; 1310 1311 return !!budget; 1312 } 1313 1314 #ifdef CONFIG_IXGBE_DCA 1315 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1316 struct ixgbe_ring *tx_ring, 1317 int cpu) 1318 { 1319 struct ixgbe_hw *hw = &adapter->hw; 1320 u32 txctrl = 0; 1321 u16 reg_offset; 1322 1323 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1324 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1325 1326 switch (hw->mac.type) { 1327 case ixgbe_mac_82598EB: 1328 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1329 break; 1330 case ixgbe_mac_82599EB: 1331 case ixgbe_mac_X540: 1332 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1333 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1334 break; 1335 default: 1336 /* for unknown hardware do not write register */ 1337 return; 1338 } 1339 1340 /* 1341 * We can enable relaxed ordering for reads, but not writes when 1342 * DCA is enabled. This is due to a known issue in some chipsets 1343 * which will cause the DCA tag to be cleared. 1344 */ 1345 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1346 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1347 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1348 1349 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1350 } 1351 1352 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1353 struct ixgbe_ring *rx_ring, 1354 int cpu) 1355 { 1356 struct ixgbe_hw *hw = &adapter->hw; 1357 u32 rxctrl = 0; 1358 u8 reg_idx = rx_ring->reg_idx; 1359 1360 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1361 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1362 1363 switch (hw->mac.type) { 1364 case ixgbe_mac_82599EB: 1365 case ixgbe_mac_X540: 1366 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1367 break; 1368 default: 1369 break; 1370 } 1371 1372 /* 1373 * We can enable relaxed ordering for reads, but not writes when 1374 * DCA is enabled. This is due to a known issue in some chipsets 1375 * which will cause the DCA tag to be cleared. 1376 */ 1377 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1378 IXGBE_DCA_RXCTRL_DATA_DCA_EN | 1379 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1380 1381 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1382 } 1383 1384 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1385 { 1386 struct ixgbe_adapter *adapter = q_vector->adapter; 1387 struct ixgbe_ring *ring; 1388 int cpu = get_cpu(); 1389 1390 if (q_vector->cpu == cpu) 1391 goto out_no_update; 1392 1393 ixgbe_for_each_ring(ring, q_vector->tx) 1394 ixgbe_update_tx_dca(adapter, ring, cpu); 1395 1396 ixgbe_for_each_ring(ring, q_vector->rx) 1397 ixgbe_update_rx_dca(adapter, ring, cpu); 1398 1399 q_vector->cpu = cpu; 1400 out_no_update: 1401 put_cpu(); 1402 } 1403 1404 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1405 { 1406 int i; 1407 1408 /* always use CB2 mode, difference is masked in the CB driver */ 1409 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1410 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1411 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1412 else 1413 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1414 IXGBE_DCA_CTRL_DCA_DISABLE); 1415 1416 for (i = 0; i < adapter->num_q_vectors; i++) { 1417 adapter->q_vector[i]->cpu = -1; 1418 ixgbe_update_dca(adapter->q_vector[i]); 1419 } 1420 } 1421 1422 static int __ixgbe_notify_dca(struct device *dev, void *data) 1423 { 1424 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1425 unsigned long event = *(unsigned long *)data; 1426 1427 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1428 return 0; 1429 1430 switch (event) { 1431 case DCA_PROVIDER_ADD: 1432 /* if we're already enabled, don't do it again */ 1433 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1434 break; 1435 if (dca_add_requester(dev) == 0) { 1436 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1437 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1438 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1439 break; 1440 } 1441 fallthrough; /* DCA is disabled. */ 1442 case DCA_PROVIDER_REMOVE: 1443 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1444 dca_remove_requester(dev); 1445 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1446 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1447 IXGBE_DCA_CTRL_DCA_DISABLE); 1448 } 1449 break; 1450 } 1451 1452 return 0; 1453 } 1454 1455 #endif /* CONFIG_IXGBE_DCA */ 1456 1457 #define IXGBE_RSS_L4_TYPES_MASK \ 1458 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1459 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1460 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1461 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1462 1463 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1464 union ixgbe_adv_rx_desc *rx_desc, 1465 struct sk_buff *skb) 1466 { 1467 u16 rss_type; 1468 1469 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1470 return; 1471 1472 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1473 IXGBE_RXDADV_RSSTYPE_MASK; 1474 1475 if (!rss_type) 1476 return; 1477 1478 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1479 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1480 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1481 } 1482 1483 #ifdef IXGBE_FCOE 1484 /** 1485 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1486 * @ring: structure containing ring specific data 1487 * @rx_desc: advanced rx descriptor 1488 * 1489 * Returns : true if it is FCoE pkt 1490 */ 1491 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1492 union ixgbe_adv_rx_desc *rx_desc) 1493 { 1494 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1495 1496 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1497 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1498 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1499 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1500 } 1501 1502 #endif /* IXGBE_FCOE */ 1503 /** 1504 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1505 * @ring: structure containing ring specific data 1506 * @rx_desc: current Rx descriptor being processed 1507 * @skb: skb currently being received and modified 1508 **/ 1509 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1510 union ixgbe_adv_rx_desc *rx_desc, 1511 struct sk_buff *skb) 1512 { 1513 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1514 bool encap_pkt = false; 1515 1516 skb_checksum_none_assert(skb); 1517 1518 /* Rx csum disabled */ 1519 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1520 return; 1521 1522 /* check for VXLAN and Geneve packets */ 1523 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) { 1524 encap_pkt = true; 1525 skb->encapsulation = 1; 1526 } 1527 1528 /* if IP and error */ 1529 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1530 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1531 ring->rx_stats.csum_err++; 1532 return; 1533 } 1534 1535 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1536 return; 1537 1538 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1539 /* 1540 * 82599 errata, UDP frames with a 0 checksum can be marked as 1541 * checksum errors. 1542 */ 1543 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1544 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1545 return; 1546 1547 ring->rx_stats.csum_err++; 1548 return; 1549 } 1550 1551 /* It must be a TCP or UDP packet with a valid checksum */ 1552 skb->ip_summed = CHECKSUM_UNNECESSARY; 1553 if (encap_pkt) { 1554 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1555 return; 1556 1557 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1558 skb->ip_summed = CHECKSUM_NONE; 1559 return; 1560 } 1561 /* If we checked the outer header let the stack know */ 1562 skb->csum_level = 1; 1563 } 1564 } 1565 1566 static unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring) 1567 { 1568 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0; 1569 } 1570 1571 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1572 struct ixgbe_rx_buffer *bi) 1573 { 1574 struct page *page = bi->page; 1575 dma_addr_t dma; 1576 1577 /* since we are recycling buffers we should seldom need to alloc */ 1578 if (likely(page)) 1579 return true; 1580 1581 /* alloc new page for storage */ 1582 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1583 if (unlikely(!page)) { 1584 rx_ring->rx_stats.alloc_rx_page_failed++; 1585 return false; 1586 } 1587 1588 /* map page for use */ 1589 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1590 ixgbe_rx_pg_size(rx_ring), 1591 DMA_FROM_DEVICE, 1592 IXGBE_RX_DMA_ATTR); 1593 1594 /* 1595 * if mapping failed free memory back to system since 1596 * there isn't much point in holding memory we can't use 1597 */ 1598 if (dma_mapping_error(rx_ring->dev, dma)) { 1599 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1600 1601 rx_ring->rx_stats.alloc_rx_page_failed++; 1602 return false; 1603 } 1604 1605 bi->dma = dma; 1606 bi->page = page; 1607 bi->page_offset = rx_ring->rx_offset; 1608 page_ref_add(page, USHRT_MAX - 1); 1609 bi->pagecnt_bias = USHRT_MAX; 1610 rx_ring->rx_stats.alloc_rx_page++; 1611 1612 return true; 1613 } 1614 1615 /** 1616 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1617 * @rx_ring: ring to place buffers on 1618 * @cleaned_count: number of buffers to replace 1619 **/ 1620 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1621 { 1622 union ixgbe_adv_rx_desc *rx_desc; 1623 struct ixgbe_rx_buffer *bi; 1624 u16 i = rx_ring->next_to_use; 1625 u16 bufsz; 1626 1627 /* nothing to do */ 1628 if (!cleaned_count) 1629 return; 1630 1631 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1632 bi = &rx_ring->rx_buffer_info[i]; 1633 i -= rx_ring->count; 1634 1635 bufsz = ixgbe_rx_bufsz(rx_ring); 1636 1637 do { 1638 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1639 break; 1640 1641 /* sync the buffer for use by the device */ 1642 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1643 bi->page_offset, bufsz, 1644 DMA_FROM_DEVICE); 1645 1646 /* 1647 * Refresh the desc even if buffer_addrs didn't change 1648 * because each write-back erases this info. 1649 */ 1650 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1651 1652 rx_desc++; 1653 bi++; 1654 i++; 1655 if (unlikely(!i)) { 1656 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1657 bi = rx_ring->rx_buffer_info; 1658 i -= rx_ring->count; 1659 } 1660 1661 /* clear the length for the next_to_use descriptor */ 1662 rx_desc->wb.upper.length = 0; 1663 1664 cleaned_count--; 1665 } while (cleaned_count); 1666 1667 i += rx_ring->count; 1668 1669 if (rx_ring->next_to_use != i) { 1670 rx_ring->next_to_use = i; 1671 1672 /* update next to alloc since we have filled the ring */ 1673 rx_ring->next_to_alloc = i; 1674 1675 /* Force memory writes to complete before letting h/w 1676 * know there are new descriptors to fetch. (Only 1677 * applicable for weak-ordered memory model archs, 1678 * such as IA-64). 1679 */ 1680 wmb(); 1681 writel(i, rx_ring->tail); 1682 } 1683 } 1684 1685 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1686 struct sk_buff *skb) 1687 { 1688 u16 hdr_len = skb_headlen(skb); 1689 1690 /* set gso_size to avoid messing up TCP MSS */ 1691 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1692 IXGBE_CB(skb)->append_cnt); 1693 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1694 } 1695 1696 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1697 struct sk_buff *skb) 1698 { 1699 /* if append_cnt is 0 then frame is not RSC */ 1700 if (!IXGBE_CB(skb)->append_cnt) 1701 return; 1702 1703 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1704 rx_ring->rx_stats.rsc_flush++; 1705 1706 ixgbe_set_rsc_gso_size(rx_ring, skb); 1707 1708 /* gso_size is computed using append_cnt so always clear it last */ 1709 IXGBE_CB(skb)->append_cnt = 0; 1710 } 1711 1712 /** 1713 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1714 * @rx_ring: rx descriptor ring packet is being transacted on 1715 * @rx_desc: pointer to the EOP Rx descriptor 1716 * @skb: pointer to current skb being populated 1717 * 1718 * This function checks the ring, descriptor, and packet information in 1719 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1720 * other fields within the skb. 1721 **/ 1722 void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1723 union ixgbe_adv_rx_desc *rx_desc, 1724 struct sk_buff *skb) 1725 { 1726 struct net_device *dev = rx_ring->netdev; 1727 u32 flags = rx_ring->q_vector->adapter->flags; 1728 1729 ixgbe_update_rsc_stats(rx_ring, skb); 1730 1731 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1732 1733 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1734 1735 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) 1736 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 1737 1738 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1739 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1740 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1741 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1742 } 1743 1744 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP)) 1745 ixgbe_ipsec_rx(rx_ring, rx_desc, skb); 1746 1747 /* record Rx queue, or update MACVLAN statistics */ 1748 if (netif_is_ixgbe(dev)) 1749 skb_record_rx_queue(skb, rx_ring->queue_index); 1750 else 1751 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true, 1752 false); 1753 1754 skb->protocol = eth_type_trans(skb, dev); 1755 } 1756 1757 void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1758 struct sk_buff *skb) 1759 { 1760 napi_gro_receive(&q_vector->napi, skb); 1761 } 1762 1763 /** 1764 * ixgbe_is_non_eop - process handling of non-EOP buffers 1765 * @rx_ring: Rx ring being processed 1766 * @rx_desc: Rx descriptor for current buffer 1767 * @skb: Current socket buffer containing buffer in progress 1768 * 1769 * This function updates next to clean. If the buffer is an EOP buffer 1770 * this function exits returning false, otherwise it will place the 1771 * sk_buff in the next buffer to be chained and return true indicating 1772 * that this is in fact a non-EOP buffer. 1773 **/ 1774 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1775 union ixgbe_adv_rx_desc *rx_desc, 1776 struct sk_buff *skb) 1777 { 1778 u32 ntc = rx_ring->next_to_clean + 1; 1779 1780 /* fetch, update, and store next to clean */ 1781 ntc = (ntc < rx_ring->count) ? ntc : 0; 1782 rx_ring->next_to_clean = ntc; 1783 1784 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1785 1786 /* update RSC append count if present */ 1787 if (ring_is_rsc_enabled(rx_ring)) { 1788 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1789 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1790 1791 if (unlikely(rsc_enabled)) { 1792 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1793 1794 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1795 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1796 1797 /* update ntc based on RSC value */ 1798 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1799 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1800 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1801 } 1802 } 1803 1804 /* if we are the last buffer then there is nothing else to do */ 1805 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1806 return false; 1807 1808 /* place skb in next buffer to be received */ 1809 rx_ring->rx_buffer_info[ntc].skb = skb; 1810 rx_ring->rx_stats.non_eop_descs++; 1811 1812 return true; 1813 } 1814 1815 /** 1816 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1817 * @rx_ring: rx descriptor ring packet is being transacted on 1818 * @skb: pointer to current skb being adjusted 1819 * 1820 * This function is an ixgbe specific version of __pskb_pull_tail. The 1821 * main difference between this version and the original function is that 1822 * this function can make several assumptions about the state of things 1823 * that allow for significant optimizations versus the standard function. 1824 * As a result we can do things like drop a frag and maintain an accurate 1825 * truesize for the skb. 1826 */ 1827 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1828 struct sk_buff *skb) 1829 { 1830 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 1831 unsigned char *va; 1832 unsigned int pull_len; 1833 1834 /* 1835 * it is valid to use page_address instead of kmap since we are 1836 * working with pages allocated out of the lomem pool per 1837 * alloc_page(GFP_ATOMIC) 1838 */ 1839 va = skb_frag_address(frag); 1840 1841 /* 1842 * we need the header to contain the greater of either ETH_HLEN or 1843 * 60 bytes if the skb->len is less than 60 for skb_pad. 1844 */ 1845 pull_len = eth_get_headlen(skb->dev, va, IXGBE_RX_HDR_SIZE); 1846 1847 /* align pull length to size of long to optimize memcpy performance */ 1848 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1849 1850 /* update all of the pointers */ 1851 skb_frag_size_sub(frag, pull_len); 1852 skb_frag_off_add(frag, pull_len); 1853 skb->data_len -= pull_len; 1854 skb->tail += pull_len; 1855 } 1856 1857 /** 1858 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1859 * @rx_ring: rx descriptor ring packet is being transacted on 1860 * @skb: pointer to current skb being updated 1861 * 1862 * This function provides a basic DMA sync up for the first fragment of an 1863 * skb. The reason for doing this is that the first fragment cannot be 1864 * unmapped until we have reached the end of packet descriptor for a buffer 1865 * chain. 1866 */ 1867 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1868 struct sk_buff *skb) 1869 { 1870 if (ring_uses_build_skb(rx_ring)) { 1871 unsigned long mask = (unsigned long)ixgbe_rx_pg_size(rx_ring) - 1; 1872 unsigned long offset = (unsigned long)(skb->data) & mask; 1873 1874 dma_sync_single_range_for_cpu(rx_ring->dev, 1875 IXGBE_CB(skb)->dma, 1876 offset, 1877 skb_headlen(skb), 1878 DMA_FROM_DEVICE); 1879 } else { 1880 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 1881 1882 dma_sync_single_range_for_cpu(rx_ring->dev, 1883 IXGBE_CB(skb)->dma, 1884 skb_frag_off(frag), 1885 skb_frag_size(frag), 1886 DMA_FROM_DEVICE); 1887 } 1888 1889 /* If the page was released, just unmap it. */ 1890 if (unlikely(IXGBE_CB(skb)->page_released)) { 1891 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma, 1892 ixgbe_rx_pg_size(rx_ring), 1893 DMA_FROM_DEVICE, 1894 IXGBE_RX_DMA_ATTR); 1895 } 1896 } 1897 1898 /** 1899 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1900 * @rx_ring: rx descriptor ring packet is being transacted on 1901 * @rx_desc: pointer to the EOP Rx descriptor 1902 * @skb: pointer to current skb being fixed 1903 * 1904 * Check if the skb is valid in the XDP case it will be an error pointer. 1905 * Return true in this case to abort processing and advance to next 1906 * descriptor. 1907 * 1908 * Check for corrupted packet headers caused by senders on the local L2 1909 * embedded NIC switch not setting up their Tx Descriptors right. These 1910 * should be very rare. 1911 * 1912 * Also address the case where we are pulling data in on pages only 1913 * and as such no data is present in the skb header. 1914 * 1915 * In addition if skb is not at least 60 bytes we need to pad it so that 1916 * it is large enough to qualify as a valid Ethernet frame. 1917 * 1918 * Returns true if an error was encountered and skb was freed. 1919 **/ 1920 bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1921 union ixgbe_adv_rx_desc *rx_desc, 1922 struct sk_buff *skb) 1923 { 1924 struct net_device *netdev = rx_ring->netdev; 1925 1926 /* Verify netdev is present, and that packet does not have any 1927 * errors that would be unacceptable to the netdev. 1928 */ 1929 if (!netdev || 1930 (unlikely(ixgbe_test_staterr(rx_desc, 1931 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1932 !(netdev->features & NETIF_F_RXALL)))) { 1933 dev_kfree_skb_any(skb); 1934 return true; 1935 } 1936 1937 /* place header in linear portion of buffer */ 1938 if (!skb_headlen(skb)) 1939 ixgbe_pull_tail(rx_ring, skb); 1940 1941 #ifdef IXGBE_FCOE 1942 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1943 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1944 return false; 1945 1946 #endif 1947 /* if eth_skb_pad returns an error the skb was freed */ 1948 if (eth_skb_pad(skb)) 1949 return true; 1950 1951 return false; 1952 } 1953 1954 /** 1955 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1956 * @rx_ring: rx descriptor ring to store buffers on 1957 * @old_buff: donor buffer to have page reused 1958 * 1959 * Synchronizes page for reuse by the adapter 1960 **/ 1961 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1962 struct ixgbe_rx_buffer *old_buff) 1963 { 1964 struct ixgbe_rx_buffer *new_buff; 1965 u16 nta = rx_ring->next_to_alloc; 1966 1967 new_buff = &rx_ring->rx_buffer_info[nta]; 1968 1969 /* update, and store next to alloc */ 1970 nta++; 1971 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1972 1973 /* Transfer page from old buffer to new buffer. 1974 * Move each member individually to avoid possible store 1975 * forwarding stalls and unnecessary copy of skb. 1976 */ 1977 new_buff->dma = old_buff->dma; 1978 new_buff->page = old_buff->page; 1979 new_buff->page_offset = old_buff->page_offset; 1980 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1981 } 1982 1983 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer, 1984 int rx_buffer_pgcnt) 1985 { 1986 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1987 struct page *page = rx_buffer->page; 1988 1989 /* avoid re-using remote and pfmemalloc pages */ 1990 if (!dev_page_is_reusable(page)) 1991 return false; 1992 1993 #if (PAGE_SIZE < 8192) 1994 /* if we are only owner of page we can reuse it */ 1995 if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1)) 1996 return false; 1997 #else 1998 /* The last offset is a bit aggressive in that we assume the 1999 * worst case of FCoE being enabled and using a 3K buffer. 2000 * However this should have minimal impact as the 1K extra is 2001 * still less than one buffer in size. 2002 */ 2003 #define IXGBE_LAST_OFFSET \ 2004 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K) 2005 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET) 2006 return false; 2007 #endif 2008 2009 /* If we have drained the page fragment pool we need to update 2010 * the pagecnt_bias and page count so that we fully restock the 2011 * number of references the driver holds. 2012 */ 2013 if (unlikely(pagecnt_bias == 1)) { 2014 page_ref_add(page, USHRT_MAX - 1); 2015 rx_buffer->pagecnt_bias = USHRT_MAX; 2016 } 2017 2018 return true; 2019 } 2020 2021 /** 2022 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 2023 * @rx_ring: rx descriptor ring to transact packets on 2024 * @rx_buffer: buffer containing page to add 2025 * @skb: sk_buff to place the data into 2026 * @size: size of data in rx_buffer 2027 * 2028 * This function will add the data contained in rx_buffer->page to the skb. 2029 * This is done either through a direct copy if the data in the buffer is 2030 * less than the skb header size, otherwise it will just attach the page as 2031 * a frag to the skb. 2032 * 2033 * The function will then update the page offset if necessary and return 2034 * true if the buffer can be reused by the adapter. 2035 **/ 2036 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 2037 struct ixgbe_rx_buffer *rx_buffer, 2038 struct sk_buff *skb, 2039 unsigned int size) 2040 { 2041 #if (PAGE_SIZE < 8192) 2042 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2043 #else 2044 unsigned int truesize = rx_ring->rx_offset ? 2045 SKB_DATA_ALIGN(rx_ring->rx_offset + size) : 2046 SKB_DATA_ALIGN(size); 2047 #endif 2048 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 2049 rx_buffer->page_offset, size, truesize); 2050 #if (PAGE_SIZE < 8192) 2051 rx_buffer->page_offset ^= truesize; 2052 #else 2053 rx_buffer->page_offset += truesize; 2054 #endif 2055 } 2056 2057 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring, 2058 union ixgbe_adv_rx_desc *rx_desc, 2059 struct sk_buff **skb, 2060 const unsigned int size, 2061 int *rx_buffer_pgcnt) 2062 { 2063 struct ixgbe_rx_buffer *rx_buffer; 2064 2065 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 2066 *rx_buffer_pgcnt = 2067 #if (PAGE_SIZE < 8192) 2068 page_count(rx_buffer->page); 2069 #else 2070 0; 2071 #endif 2072 prefetchw(rx_buffer->page); 2073 *skb = rx_buffer->skb; 2074 2075 /* Delay unmapping of the first packet. It carries the header 2076 * information, HW may still access the header after the writeback. 2077 * Only unmap it when EOP is reached 2078 */ 2079 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) { 2080 if (!*skb) 2081 goto skip_sync; 2082 } else { 2083 if (*skb) 2084 ixgbe_dma_sync_frag(rx_ring, *skb); 2085 } 2086 2087 /* we are reusing so sync this buffer for CPU use */ 2088 dma_sync_single_range_for_cpu(rx_ring->dev, 2089 rx_buffer->dma, 2090 rx_buffer->page_offset, 2091 size, 2092 DMA_FROM_DEVICE); 2093 skip_sync: 2094 rx_buffer->pagecnt_bias--; 2095 2096 return rx_buffer; 2097 } 2098 2099 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring, 2100 struct ixgbe_rx_buffer *rx_buffer, 2101 struct sk_buff *skb, 2102 int rx_buffer_pgcnt) 2103 { 2104 if (ixgbe_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) { 2105 /* hand second half of page back to the ring */ 2106 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2107 } else { 2108 if (skb && IXGBE_CB(skb)->dma == rx_buffer->dma) { 2109 /* the page has been released from the ring */ 2110 IXGBE_CB(skb)->page_released = true; 2111 } else { 2112 /* we are not reusing the buffer so unmap it */ 2113 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2114 ixgbe_rx_pg_size(rx_ring), 2115 DMA_FROM_DEVICE, 2116 IXGBE_RX_DMA_ATTR); 2117 } 2118 __page_frag_cache_drain(rx_buffer->page, 2119 rx_buffer->pagecnt_bias); 2120 } 2121 2122 /* clear contents of rx_buffer */ 2123 rx_buffer->page = NULL; 2124 rx_buffer->skb = NULL; 2125 } 2126 2127 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring, 2128 struct ixgbe_rx_buffer *rx_buffer, 2129 struct xdp_buff *xdp, 2130 union ixgbe_adv_rx_desc *rx_desc) 2131 { 2132 unsigned int size = xdp->data_end - xdp->data; 2133 #if (PAGE_SIZE < 8192) 2134 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2135 #else 2136 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 2137 xdp->data_hard_start); 2138 #endif 2139 struct sk_buff *skb; 2140 2141 /* prefetch first cache line of first page */ 2142 net_prefetch(xdp->data); 2143 2144 /* Note, we get here by enabling legacy-rx via: 2145 * 2146 * ethtool --set-priv-flags <dev> legacy-rx on 2147 * 2148 * In this mode, we currently get 0 extra XDP headroom as 2149 * opposed to having legacy-rx off, where we process XDP 2150 * packets going to stack via ixgbe_build_skb(). The latter 2151 * provides us currently with 192 bytes of headroom. 2152 * 2153 * For ixgbe_construct_skb() mode it means that the 2154 * xdp->data_meta will always point to xdp->data, since 2155 * the helper cannot expand the head. Should this ever 2156 * change in future for legacy-rx mode on, then lets also 2157 * add xdp->data_meta handling here. 2158 */ 2159 2160 /* allocate a skb to store the frags */ 2161 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE); 2162 if (unlikely(!skb)) 2163 return NULL; 2164 2165 if (size > IXGBE_RX_HDR_SIZE) { 2166 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2167 IXGBE_CB(skb)->dma = rx_buffer->dma; 2168 2169 skb_add_rx_frag(skb, 0, rx_buffer->page, 2170 xdp->data - page_address(rx_buffer->page), 2171 size, truesize); 2172 #if (PAGE_SIZE < 8192) 2173 rx_buffer->page_offset ^= truesize; 2174 #else 2175 rx_buffer->page_offset += truesize; 2176 #endif 2177 } else { 2178 memcpy(__skb_put(skb, size), 2179 xdp->data, ALIGN(size, sizeof(long))); 2180 rx_buffer->pagecnt_bias++; 2181 } 2182 2183 return skb; 2184 } 2185 2186 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring, 2187 struct ixgbe_rx_buffer *rx_buffer, 2188 struct xdp_buff *xdp, 2189 union ixgbe_adv_rx_desc *rx_desc) 2190 { 2191 unsigned int metasize = xdp->data - xdp->data_meta; 2192 #if (PAGE_SIZE < 8192) 2193 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2194 #else 2195 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 2196 SKB_DATA_ALIGN(xdp->data_end - 2197 xdp->data_hard_start); 2198 #endif 2199 struct sk_buff *skb; 2200 2201 /* Prefetch first cache line of first page. If xdp->data_meta 2202 * is unused, this points extactly as xdp->data, otherwise we 2203 * likely have a consumer accessing first few bytes of meta 2204 * data, and then actual data. 2205 */ 2206 net_prefetch(xdp->data_meta); 2207 2208 /* build an skb to around the page buffer */ 2209 skb = napi_build_skb(xdp->data_hard_start, truesize); 2210 if (unlikely(!skb)) 2211 return NULL; 2212 2213 /* update pointers within the skb to store the data */ 2214 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2215 __skb_put(skb, xdp->data_end - xdp->data); 2216 if (metasize) 2217 skb_metadata_set(skb, metasize); 2218 2219 /* record DMA address if this is the start of a chain of buffers */ 2220 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2221 IXGBE_CB(skb)->dma = rx_buffer->dma; 2222 2223 /* update buffer offset */ 2224 #if (PAGE_SIZE < 8192) 2225 rx_buffer->page_offset ^= truesize; 2226 #else 2227 rx_buffer->page_offset += truesize; 2228 #endif 2229 2230 return skb; 2231 } 2232 2233 static int ixgbe_run_xdp(struct ixgbe_adapter *adapter, 2234 struct ixgbe_ring *rx_ring, 2235 struct xdp_buff *xdp) 2236 { 2237 int err, result = IXGBE_XDP_PASS; 2238 struct bpf_prog *xdp_prog; 2239 struct ixgbe_ring *ring; 2240 struct xdp_frame *xdpf; 2241 u32 act; 2242 2243 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2244 2245 if (!xdp_prog) 2246 goto xdp_out; 2247 2248 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 2249 2250 act = bpf_prog_run_xdp(xdp_prog, xdp); 2251 switch (act) { 2252 case XDP_PASS: 2253 break; 2254 case XDP_TX: 2255 xdpf = xdp_convert_buff_to_frame(xdp); 2256 if (unlikely(!xdpf)) 2257 goto out_failure; 2258 ring = ixgbe_determine_xdp_ring(adapter); 2259 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 2260 spin_lock(&ring->tx_lock); 2261 result = ixgbe_xmit_xdp_ring(ring, xdpf); 2262 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 2263 spin_unlock(&ring->tx_lock); 2264 if (result == IXGBE_XDP_CONSUMED) 2265 goto out_failure; 2266 break; 2267 case XDP_REDIRECT: 2268 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 2269 if (err) 2270 goto out_failure; 2271 result = IXGBE_XDP_REDIR; 2272 break; 2273 default: 2274 bpf_warn_invalid_xdp_action(rx_ring->netdev, xdp_prog, act); 2275 fallthrough; 2276 case XDP_ABORTED: 2277 out_failure: 2278 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2279 fallthrough; /* handle aborts by dropping packet */ 2280 case XDP_DROP: 2281 result = IXGBE_XDP_CONSUMED; 2282 break; 2283 } 2284 xdp_out: 2285 return result; 2286 } 2287 2288 static unsigned int ixgbe_rx_frame_truesize(struct ixgbe_ring *rx_ring, 2289 unsigned int size) 2290 { 2291 unsigned int truesize; 2292 2293 #if (PAGE_SIZE < 8192) 2294 truesize = ixgbe_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 2295 #else 2296 truesize = rx_ring->rx_offset ? 2297 SKB_DATA_ALIGN(rx_ring->rx_offset + size) + 2298 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 2299 SKB_DATA_ALIGN(size); 2300 #endif 2301 return truesize; 2302 } 2303 2304 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring, 2305 struct ixgbe_rx_buffer *rx_buffer, 2306 unsigned int size) 2307 { 2308 unsigned int truesize = ixgbe_rx_frame_truesize(rx_ring, size); 2309 #if (PAGE_SIZE < 8192) 2310 rx_buffer->page_offset ^= truesize; 2311 #else 2312 rx_buffer->page_offset += truesize; 2313 #endif 2314 } 2315 2316 /** 2317 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2318 * @q_vector: structure containing interrupt and ring information 2319 * @rx_ring: rx descriptor ring to transact packets on 2320 * @budget: Total limit on number of packets to process 2321 * 2322 * This function provides a "bounce buffer" approach to Rx interrupt 2323 * processing. The advantage to this is that on systems that have 2324 * expensive overhead for IOMMU access this provides a means of avoiding 2325 * it by maintaining the mapping of the page to the syste. 2326 * 2327 * Returns amount of work completed 2328 **/ 2329 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2330 struct ixgbe_ring *rx_ring, 2331 const int budget) 2332 { 2333 unsigned int total_rx_bytes = 0, total_rx_packets = 0, frame_sz = 0; 2334 struct ixgbe_adapter *adapter = q_vector->adapter; 2335 #ifdef IXGBE_FCOE 2336 int ddp_bytes; 2337 unsigned int mss = 0; 2338 #endif /* IXGBE_FCOE */ 2339 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2340 unsigned int offset = rx_ring->rx_offset; 2341 unsigned int xdp_xmit = 0; 2342 struct xdp_buff xdp; 2343 int xdp_res = 0; 2344 2345 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 2346 #if (PAGE_SIZE < 8192) 2347 frame_sz = ixgbe_rx_frame_truesize(rx_ring, 0); 2348 #endif 2349 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 2350 2351 while (likely(total_rx_packets < budget)) { 2352 union ixgbe_adv_rx_desc *rx_desc; 2353 struct ixgbe_rx_buffer *rx_buffer; 2354 struct sk_buff *skb; 2355 int rx_buffer_pgcnt; 2356 unsigned int size; 2357 2358 /* return some buffers to hardware, one at a time is too slow */ 2359 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2360 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2361 cleaned_count = 0; 2362 } 2363 2364 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2365 size = le16_to_cpu(rx_desc->wb.upper.length); 2366 if (!size) 2367 break; 2368 2369 /* This memory barrier is needed to keep us from reading 2370 * any other fields out of the rx_desc until we know the 2371 * descriptor has been written back 2372 */ 2373 dma_rmb(); 2374 2375 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size, &rx_buffer_pgcnt); 2376 2377 /* retrieve a buffer from the ring */ 2378 if (!skb) { 2379 unsigned char *hard_start; 2380 2381 hard_start = page_address(rx_buffer->page) + 2382 rx_buffer->page_offset - offset; 2383 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 2384 xdp_buff_clear_frags_flag(&xdp); 2385 #if (PAGE_SIZE > 4096) 2386 /* At larger PAGE_SIZE, frame_sz depend on len size */ 2387 xdp.frame_sz = ixgbe_rx_frame_truesize(rx_ring, size); 2388 #endif 2389 xdp_res = ixgbe_run_xdp(adapter, rx_ring, &xdp); 2390 } 2391 2392 if (xdp_res) { 2393 if (xdp_res & (IXGBE_XDP_TX | IXGBE_XDP_REDIR)) { 2394 xdp_xmit |= xdp_res; 2395 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size); 2396 } else { 2397 rx_buffer->pagecnt_bias++; 2398 } 2399 total_rx_packets++; 2400 total_rx_bytes += size; 2401 } else if (skb) { 2402 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size); 2403 } else if (ring_uses_build_skb(rx_ring)) { 2404 skb = ixgbe_build_skb(rx_ring, rx_buffer, 2405 &xdp, rx_desc); 2406 } else { 2407 skb = ixgbe_construct_skb(rx_ring, rx_buffer, 2408 &xdp, rx_desc); 2409 } 2410 2411 /* exit if we failed to retrieve a buffer */ 2412 if (!xdp_res && !skb) { 2413 rx_ring->rx_stats.alloc_rx_buff_failed++; 2414 rx_buffer->pagecnt_bias++; 2415 break; 2416 } 2417 2418 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt); 2419 cleaned_count++; 2420 2421 /* place incomplete frames back on ring for completion */ 2422 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2423 continue; 2424 2425 /* verify the packet layout is correct */ 2426 if (xdp_res || ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2427 continue; 2428 2429 /* probably a little skewed due to removing CRC */ 2430 total_rx_bytes += skb->len; 2431 2432 /* populate checksum, timestamp, VLAN, and protocol */ 2433 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2434 2435 #ifdef IXGBE_FCOE 2436 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2437 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2438 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2439 /* include DDPed FCoE data */ 2440 if (ddp_bytes > 0) { 2441 if (!mss) { 2442 mss = rx_ring->netdev->mtu - 2443 sizeof(struct fcoe_hdr) - 2444 sizeof(struct fc_frame_header) - 2445 sizeof(struct fcoe_crc_eof); 2446 if (mss > 512) 2447 mss &= ~511; 2448 } 2449 total_rx_bytes += ddp_bytes; 2450 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2451 mss); 2452 } 2453 if (!ddp_bytes) { 2454 dev_kfree_skb_any(skb); 2455 continue; 2456 } 2457 } 2458 2459 #endif /* IXGBE_FCOE */ 2460 ixgbe_rx_skb(q_vector, skb); 2461 2462 /* update budget accounting */ 2463 total_rx_packets++; 2464 } 2465 2466 if (xdp_xmit & IXGBE_XDP_REDIR) 2467 xdp_do_flush(); 2468 2469 if (xdp_xmit & IXGBE_XDP_TX) { 2470 struct ixgbe_ring *ring = ixgbe_determine_xdp_ring(adapter); 2471 2472 ixgbe_xdp_ring_update_tail_locked(ring); 2473 } 2474 2475 ixgbe_update_rx_ring_stats(rx_ring, q_vector, total_rx_packets, 2476 total_rx_bytes); 2477 2478 return total_rx_packets; 2479 } 2480 2481 /** 2482 * ixgbe_configure_msix - Configure MSI-X hardware 2483 * @adapter: board private structure 2484 * 2485 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2486 * interrupts. 2487 **/ 2488 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2489 { 2490 struct ixgbe_q_vector *q_vector; 2491 int v_idx; 2492 u32 mask; 2493 2494 /* Populate MSIX to EITR Select */ 2495 if (adapter->num_vfs > 32) { 2496 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; 2497 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2498 } 2499 2500 /* 2501 * Populate the IVAR table and set the ITR values to the 2502 * corresponding register. 2503 */ 2504 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2505 struct ixgbe_ring *ring; 2506 q_vector = adapter->q_vector[v_idx]; 2507 2508 ixgbe_for_each_ring(ring, q_vector->rx) 2509 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2510 2511 ixgbe_for_each_ring(ring, q_vector->tx) 2512 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2513 2514 ixgbe_write_eitr(q_vector); 2515 } 2516 2517 switch (adapter->hw.mac.type) { 2518 case ixgbe_mac_82598EB: 2519 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2520 v_idx); 2521 break; 2522 case ixgbe_mac_82599EB: 2523 case ixgbe_mac_X540: 2524 case ixgbe_mac_X550: 2525 case ixgbe_mac_X550EM_x: 2526 case ixgbe_mac_x550em_a: 2527 case ixgbe_mac_e610: 2528 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2529 break; 2530 default: 2531 break; 2532 } 2533 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2534 2535 /* set up to autoclear timer, and the vectors */ 2536 mask = IXGBE_EIMS_ENABLE_MASK; 2537 mask &= ~(IXGBE_EIMS_OTHER | 2538 IXGBE_EIMS_MAILBOX | 2539 IXGBE_EIMS_LSC); 2540 2541 if (adapter->hw.mac.type == ixgbe_mac_e610) 2542 mask &= ~IXGBE_EIMS_FW_EVENT; 2543 2544 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2545 } 2546 2547 /** 2548 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2549 * @q_vector: structure containing interrupt and ring information 2550 * @ring_container: structure containing ring performance data 2551 * 2552 * Stores a new ITR value based on packets and byte 2553 * counts during the last interrupt. The advantage of per interrupt 2554 * computation is faster updates and more accurate ITR for the current 2555 * traffic pattern. Constants in this function were computed 2556 * based on theoretical maximum wire speed and thresholds were set based 2557 * on testing data as well as attempting to minimize response time 2558 * while increasing bulk throughput. 2559 **/ 2560 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2561 struct ixgbe_ring_container *ring_container) 2562 { 2563 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS | 2564 IXGBE_ITR_ADAPTIVE_LATENCY; 2565 unsigned int avg_wire_size, packets, bytes; 2566 unsigned long next_update = jiffies; 2567 2568 /* If we don't have any rings just leave ourselves set for maximum 2569 * possible latency so we take ourselves out of the equation. 2570 */ 2571 if (!ring_container->ring) 2572 return; 2573 2574 /* If we didn't update within up to 1 - 2 jiffies we can assume 2575 * that either packets are coming in so slow there hasn't been 2576 * any work, or that there is so much work that NAPI is dealing 2577 * with interrupt moderation and we don't need to do anything. 2578 */ 2579 if (time_after(next_update, ring_container->next_update)) 2580 goto clear_counts; 2581 2582 packets = ring_container->total_packets; 2583 2584 /* We have no packets to actually measure against. This means 2585 * either one of the other queues on this vector is active or 2586 * we are a Tx queue doing TSO with too high of an interrupt rate. 2587 * 2588 * When this occurs just tick up our delay by the minimum value 2589 * and hope that this extra delay will prevent us from being called 2590 * without any work on our queue. 2591 */ 2592 if (!packets) { 2593 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2594 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2595 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2596 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY; 2597 goto clear_counts; 2598 } 2599 2600 bytes = ring_container->total_bytes; 2601 2602 /* If packets are less than 4 or bytes are less than 9000 assume 2603 * insufficient data to use bulk rate limiting approach. We are 2604 * likely latency driven. 2605 */ 2606 if (packets < 4 && bytes < 9000) { 2607 itr = IXGBE_ITR_ADAPTIVE_LATENCY; 2608 goto adjust_by_size; 2609 } 2610 2611 /* Between 4 and 48 we can assume that our current interrupt delay 2612 * is only slightly too low. As such we should increase it by a small 2613 * fixed amount. 2614 */ 2615 if (packets < 48) { 2616 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2617 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2618 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2619 goto clear_counts; 2620 } 2621 2622 /* Between 48 and 96 is our "goldilocks" zone where we are working 2623 * out "just right". Just report that our current ITR is good for us. 2624 */ 2625 if (packets < 96) { 2626 itr = q_vector->itr >> 2; 2627 goto clear_counts; 2628 } 2629 2630 /* If packet count is 96 or greater we are likely looking at a slight 2631 * overrun of the delay we want. Try halving our delay to see if that 2632 * will cut the number of packets in half per interrupt. 2633 */ 2634 if (packets < 256) { 2635 itr = q_vector->itr >> 3; 2636 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS) 2637 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS; 2638 goto clear_counts; 2639 } 2640 2641 /* The paths below assume we are dealing with a bulk ITR since number 2642 * of packets is 256 or greater. We are just going to have to compute 2643 * a value and try to bring the count under control, though for smaller 2644 * packet sizes there isn't much we can do as NAPI polling will likely 2645 * be kicking in sooner rather than later. 2646 */ 2647 itr = IXGBE_ITR_ADAPTIVE_BULK; 2648 2649 adjust_by_size: 2650 /* If packet counts are 256 or greater we can assume we have a gross 2651 * overestimation of what the rate should be. Instead of trying to fine 2652 * tune it just use the formula below to try and dial in an exact value 2653 * give the current packet size of the frame. 2654 */ 2655 avg_wire_size = bytes / packets; 2656 2657 /* The following is a crude approximation of: 2658 * wmem_default / (size + overhead) = desired_pkts_per_int 2659 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 2660 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 2661 * 2662 * Assuming wmem_default is 212992 and overhead is 640 bytes per 2663 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 2664 * formula down to 2665 * 2666 * (170 * (size + 24)) / (size + 640) = ITR 2667 * 2668 * We first do some math on the packet size and then finally bitshift 2669 * by 8 after rounding up. We also have to account for PCIe link speed 2670 * difference as ITR scales based on this. 2671 */ 2672 if (avg_wire_size <= 60) { 2673 /* Start at 50k ints/sec */ 2674 avg_wire_size = 5120; 2675 } else if (avg_wire_size <= 316) { 2676 /* 50K ints/sec to 16K ints/sec */ 2677 avg_wire_size *= 40; 2678 avg_wire_size += 2720; 2679 } else if (avg_wire_size <= 1084) { 2680 /* 16K ints/sec to 9.2K ints/sec */ 2681 avg_wire_size *= 15; 2682 avg_wire_size += 11452; 2683 } else if (avg_wire_size < 1968) { 2684 /* 9.2K ints/sec to 8K ints/sec */ 2685 avg_wire_size *= 5; 2686 avg_wire_size += 22420; 2687 } else { 2688 /* plateau at a limit of 8K ints/sec */ 2689 avg_wire_size = 32256; 2690 } 2691 2692 /* If we are in low latency mode half our delay which doubles the rate 2693 * to somewhere between 100K to 16K ints/sec 2694 */ 2695 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY) 2696 avg_wire_size >>= 1; 2697 2698 /* Resultant value is 256 times larger than it needs to be. This 2699 * gives us room to adjust the value as needed to either increase 2700 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc. 2701 * 2702 * Use addition as we have already recorded the new latency flag 2703 * for the ITR value. 2704 */ 2705 switch (q_vector->adapter->link_speed) { 2706 case IXGBE_LINK_SPEED_10GB_FULL: 2707 case IXGBE_LINK_SPEED_100_FULL: 2708 default: 2709 itr += DIV_ROUND_UP(avg_wire_size, 2710 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) * 2711 IXGBE_ITR_ADAPTIVE_MIN_INC; 2712 break; 2713 case IXGBE_LINK_SPEED_2_5GB_FULL: 2714 case IXGBE_LINK_SPEED_1GB_FULL: 2715 case IXGBE_LINK_SPEED_10_FULL: 2716 if (avg_wire_size > 8064) 2717 avg_wire_size = 8064; 2718 itr += DIV_ROUND_UP(avg_wire_size, 2719 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) * 2720 IXGBE_ITR_ADAPTIVE_MIN_INC; 2721 break; 2722 } 2723 2724 clear_counts: 2725 /* write back value */ 2726 ring_container->itr = itr; 2727 2728 /* next update should occur within next jiffy */ 2729 ring_container->next_update = next_update + 1; 2730 2731 ring_container->total_bytes = 0; 2732 ring_container->total_packets = 0; 2733 } 2734 2735 /** 2736 * ixgbe_write_eitr - write EITR register in hardware specific way 2737 * @q_vector: structure containing interrupt and ring information 2738 * 2739 * This function is made to be called by ethtool and by the driver 2740 * when it needs to update EITR registers at runtime. Hardware 2741 * specific quirks/differences are taken care of here. 2742 */ 2743 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2744 { 2745 struct ixgbe_adapter *adapter = q_vector->adapter; 2746 struct ixgbe_hw *hw = &adapter->hw; 2747 int v_idx = q_vector->v_idx; 2748 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2749 2750 switch (adapter->hw.mac.type) { 2751 case ixgbe_mac_82598EB: 2752 /* must write high and low 16 bits to reset counter */ 2753 itr_reg |= (itr_reg << 16); 2754 break; 2755 case ixgbe_mac_82599EB: 2756 case ixgbe_mac_X540: 2757 case ixgbe_mac_X550: 2758 case ixgbe_mac_X550EM_x: 2759 case ixgbe_mac_x550em_a: 2760 case ixgbe_mac_e610: 2761 /* 2762 * set the WDIS bit to not clear the timer bits and cause an 2763 * immediate assertion of the interrupt 2764 */ 2765 itr_reg |= IXGBE_EITR_CNT_WDIS; 2766 break; 2767 default: 2768 break; 2769 } 2770 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2771 } 2772 2773 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2774 { 2775 u32 new_itr; 2776 2777 ixgbe_update_itr(q_vector, &q_vector->tx); 2778 ixgbe_update_itr(q_vector, &q_vector->rx); 2779 2780 /* use the smallest value of new ITR delay calculations */ 2781 new_itr = min(q_vector->rx.itr, q_vector->tx.itr); 2782 2783 /* Clear latency flag if set, shift into correct position */ 2784 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY; 2785 new_itr <<= 2; 2786 2787 if (new_itr != q_vector->itr) { 2788 /* save the algorithm value here */ 2789 q_vector->itr = new_itr; 2790 2791 ixgbe_write_eitr(q_vector); 2792 } 2793 } 2794 2795 /** 2796 * ixgbe_check_overtemp_subtask - check for over temperature 2797 * @adapter: pointer to adapter 2798 **/ 2799 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2800 { 2801 struct ixgbe_hw *hw = &adapter->hw; 2802 u32 eicr = adapter->interrupt_event; 2803 2804 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2805 return; 2806 2807 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2808 return; 2809 2810 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2811 2812 switch (hw->device_id) { 2813 case IXGBE_DEV_ID_82599_T3_LOM: 2814 /* 2815 * Since the warning interrupt is for both ports 2816 * we don't have to check if: 2817 * - This interrupt wasn't for our port. 2818 * - We may have missed the interrupt so always have to 2819 * check if we got a LSC 2820 */ 2821 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2822 !(eicr & IXGBE_EICR_LSC)) 2823 return; 2824 2825 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2826 u32 speed; 2827 bool link_up = false; 2828 2829 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2830 2831 if (link_up) 2832 return; 2833 } 2834 2835 /* Check if this is not due to overtemp */ 2836 if (!hw->phy.ops.check_overtemp(hw)) 2837 return; 2838 2839 break; 2840 case IXGBE_DEV_ID_X550EM_A_1G_T: 2841 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2842 if (!hw->phy.ops.check_overtemp(hw)) 2843 return; 2844 break; 2845 default: 2846 if (adapter->hw.mac.type >= ixgbe_mac_X540) 2847 return; 2848 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 2849 return; 2850 break; 2851 } 2852 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2853 2854 adapter->interrupt_event = 0; 2855 } 2856 2857 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2858 { 2859 struct ixgbe_hw *hw = &adapter->hw; 2860 2861 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2862 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2863 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2864 /* write to clear the interrupt */ 2865 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2866 } 2867 } 2868 2869 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2870 { 2871 struct ixgbe_hw *hw = &adapter->hw; 2872 2873 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2874 return; 2875 2876 switch (adapter->hw.mac.type) { 2877 case ixgbe_mac_82599EB: 2878 /* 2879 * Need to check link state so complete overtemp check 2880 * on service task 2881 */ 2882 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 2883 (eicr & IXGBE_EICR_LSC)) && 2884 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2885 adapter->interrupt_event = eicr; 2886 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2887 ixgbe_service_event_schedule(adapter); 2888 return; 2889 } 2890 return; 2891 case ixgbe_mac_x550em_a: 2892 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) { 2893 adapter->interrupt_event = eicr; 2894 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2895 ixgbe_service_event_schedule(adapter); 2896 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 2897 IXGBE_EICR_GPI_SDP0_X550EM_a); 2898 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR, 2899 IXGBE_EICR_GPI_SDP0_X550EM_a); 2900 } 2901 return; 2902 case ixgbe_mac_X550: 2903 case ixgbe_mac_X540: 2904 if (!(eicr & IXGBE_EICR_TS)) 2905 return; 2906 break; 2907 default: 2908 return; 2909 } 2910 2911 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2912 } 2913 2914 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 2915 { 2916 switch (hw->mac.type) { 2917 case ixgbe_mac_82598EB: 2918 if (hw->phy.type == ixgbe_phy_nl) 2919 return true; 2920 return false; 2921 case ixgbe_mac_82599EB: 2922 case ixgbe_mac_X550EM_x: 2923 case ixgbe_mac_x550em_a: 2924 switch (hw->mac.ops.get_media_type(hw)) { 2925 case ixgbe_media_type_fiber: 2926 case ixgbe_media_type_fiber_qsfp: 2927 return true; 2928 default: 2929 return false; 2930 } 2931 default: 2932 return false; 2933 } 2934 } 2935 2936 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2937 { 2938 struct ixgbe_hw *hw = &adapter->hw; 2939 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); 2940 2941 if (!ixgbe_is_sfp(hw)) 2942 return; 2943 2944 /* Later MAC's use different SDP */ 2945 if (hw->mac.type >= ixgbe_mac_X540) 2946 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2947 2948 if (eicr & eicr_mask) { 2949 /* Clear the interrupt */ 2950 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2951 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2952 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2953 adapter->sfp_poll_time = 0; 2954 ixgbe_service_event_schedule(adapter); 2955 } 2956 } 2957 2958 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 2959 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2960 /* Clear the interrupt */ 2961 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2962 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2963 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2964 ixgbe_service_event_schedule(adapter); 2965 } 2966 } 2967 } 2968 2969 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2970 { 2971 struct ixgbe_hw *hw = &adapter->hw; 2972 2973 adapter->lsc_int++; 2974 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2975 adapter->link_check_timeout = jiffies; 2976 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2977 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2978 IXGBE_WRITE_FLUSH(hw); 2979 ixgbe_service_event_schedule(adapter); 2980 } 2981 } 2982 2983 /** 2984 * ixgbe_check_phy_fw_load - check if PHY FW load failed 2985 * @adapter: pointer to adapter structure 2986 * @link_cfg_err: bitmap from the link info structure 2987 * 2988 * Check if external PHY FW load failed and print an error message if it did. 2989 */ 2990 static void ixgbe_check_phy_fw_load(struct ixgbe_adapter *adapter, 2991 u8 link_cfg_err) 2992 { 2993 if (!(link_cfg_err & IXGBE_ACI_LINK_EXTERNAL_PHY_LOAD_FAILURE)) { 2994 adapter->flags2 &= ~IXGBE_FLAG2_PHY_FW_LOAD_FAILED; 2995 return; 2996 } 2997 2998 if (adapter->flags2 & IXGBE_FLAG2_PHY_FW_LOAD_FAILED) 2999 return; 3000 3001 if (link_cfg_err & IXGBE_ACI_LINK_EXTERNAL_PHY_LOAD_FAILURE) { 3002 netdev_err(adapter->netdev, "Device failed to load the FW for the external PHY. Please download and install the latest NVM for your device and try again\n"); 3003 adapter->flags2 |= IXGBE_FLAG2_PHY_FW_LOAD_FAILED; 3004 } 3005 } 3006 3007 /** 3008 * ixgbe_check_module_power - check module power level 3009 * @adapter: pointer to adapter structure 3010 * @link_cfg_err: bitmap from the link info structure 3011 * 3012 * Check module power level returned by a previous call to aci_get_link_info 3013 * and print error messages if module power level is not supported. 3014 */ 3015 static void ixgbe_check_module_power(struct ixgbe_adapter *adapter, 3016 u8 link_cfg_err) 3017 { 3018 /* If module power level is supported, clear the flag. */ 3019 if (!(link_cfg_err & (IXGBE_ACI_LINK_INVAL_MAX_POWER_LIMIT | 3020 IXGBE_ACI_LINK_MODULE_POWER_UNSUPPORTED))) { 3021 adapter->flags2 &= ~IXGBE_FLAG2_MOD_POWER_UNSUPPORTED; 3022 return; 3023 } 3024 3025 /* If IXGBE_FLAG2_MOD_POWER_UNSUPPORTED was previously set and the 3026 * above block didn't clear this bit, there's nothing to do. 3027 */ 3028 if (adapter->flags2 & IXGBE_FLAG2_MOD_POWER_UNSUPPORTED) 3029 return; 3030 3031 if (link_cfg_err & IXGBE_ACI_LINK_INVAL_MAX_POWER_LIMIT) { 3032 netdev_err(adapter->netdev, "The installed module is incompatible with the device's NVM image. Cannot start link.\n"); 3033 adapter->flags2 |= IXGBE_FLAG2_MOD_POWER_UNSUPPORTED; 3034 } else if (link_cfg_err & IXGBE_ACI_LINK_MODULE_POWER_UNSUPPORTED) { 3035 netdev_err(adapter->netdev, "The module's power requirements exceed the device's power supply. Cannot start link.\n"); 3036 adapter->flags2 |= IXGBE_FLAG2_MOD_POWER_UNSUPPORTED; 3037 } 3038 } 3039 3040 /** 3041 * ixgbe_check_link_cfg_err - check if link configuration failed 3042 * @adapter: pointer to adapter structure 3043 * @link_cfg_err: bitmap from the link info structure 3044 * 3045 * Print if any link configuration failure happens due to the value in the 3046 * link_cfg_err parameter in the link info structure. 3047 */ 3048 static void ixgbe_check_link_cfg_err(struct ixgbe_adapter *adapter, 3049 u8 link_cfg_err) 3050 { 3051 ixgbe_check_module_power(adapter, link_cfg_err); 3052 ixgbe_check_phy_fw_load(adapter, link_cfg_err); 3053 } 3054 3055 /** 3056 * ixgbe_process_link_status_event - process the link event 3057 * @adapter: pointer to adapter structure 3058 * @link_up: true if the physical link is up and false if it is down 3059 * @link_speed: current link speed received from the link event 3060 * 3061 * Return: 0 on success or negative value on failure. 3062 */ 3063 static int 3064 ixgbe_process_link_status_event(struct ixgbe_adapter *adapter, bool link_up, 3065 u16 link_speed) 3066 { 3067 struct ixgbe_hw *hw = &adapter->hw; 3068 int status; 3069 3070 /* Update the link info structures and re-enable link events, 3071 * don't bail on failure due to other book keeping needed. 3072 */ 3073 status = ixgbe_update_link_info(hw); 3074 if (status) 3075 e_dev_err("Failed to update link status, err %d aq_err %d\n", 3076 status, hw->aci.last_status); 3077 3078 ixgbe_check_link_cfg_err(adapter, hw->link.link_info.link_cfg_err); 3079 3080 /* Check if the link state is up after updating link info, and treat 3081 * this event as an UP event since the link is actually UP now. 3082 */ 3083 if (hw->link.link_info.link_info & IXGBE_ACI_LINK_UP) 3084 link_up = true; 3085 3086 /* Turn off PHY if media was removed. */ 3087 if (!(adapter->flags2 & IXGBE_FLAG2_NO_MEDIA) && 3088 !(hw->link.link_info.link_info & IXGBE_ACI_MEDIA_AVAILABLE)) 3089 adapter->flags2 |= IXGBE_FLAG2_NO_MEDIA; 3090 3091 if (link_up == adapter->link_up && 3092 link_up == netif_carrier_ok(adapter->netdev) && 3093 link_speed == adapter->link_speed) 3094 return 0; 3095 3096 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 3097 adapter->link_check_timeout = jiffies; 3098 ixgbe_watchdog_update_link(adapter); 3099 3100 if (link_up) 3101 ixgbe_watchdog_link_is_up(adapter); 3102 else 3103 ixgbe_watchdog_link_is_down(adapter); 3104 3105 return 0; 3106 } 3107 3108 /** 3109 * ixgbe_handle_link_status_event - handle link status event via ACI 3110 * @adapter: pointer to adapter structure 3111 * @e: event structure containing link status info 3112 */ 3113 static void 3114 ixgbe_handle_link_status_event(struct ixgbe_adapter *adapter, 3115 struct ixgbe_aci_event *e) 3116 { 3117 struct ixgbe_aci_cmd_get_link_status_data *link_data; 3118 u16 link_speed; 3119 bool link_up; 3120 3121 link_data = (struct ixgbe_aci_cmd_get_link_status_data *)e->msg_buf; 3122 3123 link_up = !!(link_data->link_info & IXGBE_ACI_LINK_UP); 3124 link_speed = le16_to_cpu(link_data->link_speed); 3125 3126 if (ixgbe_process_link_status_event(adapter, link_up, link_speed)) 3127 e_dev_warn("Could not process link status event"); 3128 } 3129 3130 /** 3131 * ixgbe_schedule_fw_event - schedule Firmware event 3132 * @adapter: pointer to the adapter structure 3133 * 3134 * If the adapter is not in down, removing or resetting state, 3135 * an event is scheduled. 3136 */ 3137 static void ixgbe_schedule_fw_event(struct ixgbe_adapter *adapter) 3138 { 3139 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 3140 !test_bit(__IXGBE_REMOVING, &adapter->state) && 3141 !test_bit(__IXGBE_RESETTING, &adapter->state)) { 3142 adapter->flags2 |= IXGBE_FLAG2_FW_ASYNC_EVENT; 3143 ixgbe_service_event_schedule(adapter); 3144 } 3145 } 3146 3147 /** 3148 * ixgbe_aci_event_cleanup - release msg_buf memory 3149 * @event: pointer to the event holding msg_buf to be released 3150 * 3151 * Clean memory allocated for event's msg_buf. Implements auto memory cleanup. 3152 */ 3153 static void ixgbe_aci_event_cleanup(struct ixgbe_aci_event *event) 3154 { 3155 kfree(event->msg_buf); 3156 } 3157 3158 /** 3159 * ixgbe_handle_fw_event - handle Firmware event 3160 * @adapter: pointer to the adapter structure 3161 * 3162 * Obtain an event from the ACI and then and then process it according to the 3163 * type of the event and the opcode. 3164 */ 3165 static void ixgbe_handle_fw_event(struct ixgbe_adapter *adapter) 3166 { 3167 struct ixgbe_aci_event event __cleanup(ixgbe_aci_event_cleanup); 3168 struct ixgbe_hw *hw = &adapter->hw; 3169 bool pending = false; 3170 int err; 3171 3172 if (adapter->flags2 & IXGBE_FLAG2_FW_ASYNC_EVENT) 3173 adapter->flags2 &= ~IXGBE_FLAG2_FW_ASYNC_EVENT; 3174 event.buf_len = IXGBE_ACI_MAX_BUFFER_SIZE; 3175 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL); 3176 if (!event.msg_buf) 3177 return; 3178 3179 do { 3180 err = ixgbe_aci_get_event(hw, &event, &pending); 3181 if (err) 3182 break; 3183 3184 switch (le16_to_cpu(event.desc.opcode)) { 3185 case ixgbe_aci_opc_get_link_status: 3186 ixgbe_handle_link_status_event(adapter, &event); 3187 break; 3188 case ixgbe_aci_opc_temp_tca_event: 3189 e_crit(drv, "%s\n", ixgbe_overheat_msg); 3190 ixgbe_down(adapter); 3191 break; 3192 default: 3193 e_warn(hw, "unknown FW async event captured\n"); 3194 break; 3195 } 3196 } while (pending); 3197 } 3198 3199 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 3200 u64 qmask) 3201 { 3202 struct ixgbe_hw *hw = &adapter->hw; 3203 u32 mask; 3204 3205 switch (hw->mac.type) { 3206 case ixgbe_mac_82598EB: 3207 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 3208 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 3209 break; 3210 case ixgbe_mac_82599EB: 3211 case ixgbe_mac_X540: 3212 case ixgbe_mac_X550: 3213 case ixgbe_mac_X550EM_x: 3214 case ixgbe_mac_x550em_a: 3215 case ixgbe_mac_e610: 3216 mask = (qmask & 0xFFFFFFFF); 3217 if (mask) 3218 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 3219 mask = (qmask >> 32); 3220 if (mask) 3221 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 3222 break; 3223 default: 3224 break; 3225 } 3226 /* skip the flush */ 3227 } 3228 3229 /** 3230 * ixgbe_irq_enable - Enable default interrupt generation settings 3231 * @adapter: board private structure 3232 * @queues: enable irqs for queues 3233 * @flush: flush register write 3234 **/ 3235 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 3236 bool flush) 3237 { 3238 struct ixgbe_hw *hw = &adapter->hw; 3239 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 3240 3241 /* don't reenable LSC while waiting for link */ 3242 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 3243 mask &= ~IXGBE_EIMS_LSC; 3244 3245 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 3246 switch (adapter->hw.mac.type) { 3247 case ixgbe_mac_82599EB: 3248 mask |= IXGBE_EIMS_GPI_SDP0(hw); 3249 break; 3250 case ixgbe_mac_X540: 3251 case ixgbe_mac_X550: 3252 case ixgbe_mac_X550EM_x: 3253 case ixgbe_mac_x550em_a: 3254 mask |= IXGBE_EIMS_TS; 3255 break; 3256 default: 3257 break; 3258 } 3259 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 3260 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3261 switch (adapter->hw.mac.type) { 3262 case ixgbe_mac_82599EB: 3263 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3264 mask |= IXGBE_EIMS_GPI_SDP2(hw); 3265 fallthrough; 3266 case ixgbe_mac_X540: 3267 case ixgbe_mac_X550: 3268 case ixgbe_mac_X550EM_x: 3269 case ixgbe_mac_e610: 3270 mask |= IXGBE_EIMS_FW_EVENT; 3271 fallthrough; 3272 case ixgbe_mac_x550em_a: 3273 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || 3274 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || 3275 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) 3276 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); 3277 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 3278 mask |= IXGBE_EICR_GPI_SDP0_X540; 3279 mask |= IXGBE_EIMS_ECC; 3280 mask |= IXGBE_EIMS_MAILBOX; 3281 break; 3282 default: 3283 break; 3284 } 3285 3286 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 3287 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 3288 mask |= IXGBE_EIMS_FLOW_DIR; 3289 3290 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 3291 if (queues) 3292 ixgbe_irq_enable_queues(adapter, ~0); 3293 if (flush) 3294 IXGBE_WRITE_FLUSH(&adapter->hw); 3295 } 3296 3297 static irqreturn_t ixgbe_msix_other(int irq, void *data) 3298 { 3299 struct ixgbe_adapter *adapter = data; 3300 struct ixgbe_hw *hw = &adapter->hw; 3301 u32 eicr; 3302 3303 /* 3304 * Workaround for Silicon errata. Use clear-by-write instead 3305 * of clear-by-read. Reading with EICS will return the 3306 * interrupt causes without clearing, which later be done 3307 * with the write to EICR. 3308 */ 3309 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 3310 3311 /* The lower 16bits of the EICR register are for the queue interrupts 3312 * which should be masked here in order to not accidentally clear them if 3313 * the bits are high when ixgbe_msix_other is called. There is a race 3314 * condition otherwise which results in possible performance loss 3315 * especially if the ixgbe_msix_other interrupt is triggering 3316 * consistently (as it would when PPS is turned on for the X540 device) 3317 */ 3318 eicr &= 0xFFFF0000; 3319 3320 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 3321 3322 if (eicr & IXGBE_EICR_LSC) 3323 ixgbe_check_lsc(adapter); 3324 3325 if (eicr & IXGBE_EICR_MAILBOX) 3326 ixgbe_msg_task(adapter); 3327 3328 if (eicr & IXGBE_EICR_FW_EVENT) 3329 ixgbe_schedule_fw_event(adapter); 3330 3331 switch (hw->mac.type) { 3332 case ixgbe_mac_82599EB: 3333 case ixgbe_mac_X540: 3334 case ixgbe_mac_X550: 3335 case ixgbe_mac_X550EM_x: 3336 case ixgbe_mac_x550em_a: 3337 case ixgbe_mac_e610: 3338 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 3339 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 3340 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 3341 ixgbe_service_event_schedule(adapter); 3342 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3343 IXGBE_EICR_GPI_SDP0_X540); 3344 } 3345 if (eicr & IXGBE_EICR_ECC) { 3346 e_info(link, "Received ECC Err, initiating reset\n"); 3347 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3348 ixgbe_service_event_schedule(adapter); 3349 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3350 } 3351 /* Handle Flow Director Full threshold interrupt */ 3352 if (eicr & IXGBE_EICR_FLOW_DIR) { 3353 int reinit_count = 0; 3354 int i; 3355 for (i = 0; i < adapter->num_tx_queues; i++) { 3356 struct ixgbe_ring *ring = adapter->tx_ring[i]; 3357 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 3358 &ring->state)) 3359 reinit_count++; 3360 } 3361 if (reinit_count) { 3362 /* no more flow director interrupts until after init */ 3363 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 3364 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 3365 ixgbe_service_event_schedule(adapter); 3366 } 3367 } 3368 ixgbe_check_sfp_event(adapter, eicr); 3369 ixgbe_check_overtemp_event(adapter, eicr); 3370 break; 3371 default: 3372 break; 3373 } 3374 3375 ixgbe_check_fan_failure(adapter, eicr); 3376 3377 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3378 ixgbe_ptp_check_pps_event(adapter); 3379 3380 /* re-enable the original interrupt state, no lsc, no queues */ 3381 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3382 ixgbe_irq_enable(adapter, false, false); 3383 3384 return IRQ_HANDLED; 3385 } 3386 3387 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 3388 { 3389 struct ixgbe_q_vector *q_vector = data; 3390 3391 /* EIAM disabled interrupts (on this vector) for us */ 3392 3393 if (q_vector->rx.ring || q_vector->tx.ring) 3394 napi_schedule_irqoff(&q_vector->napi); 3395 3396 return IRQ_HANDLED; 3397 } 3398 3399 /** 3400 * ixgbe_poll - NAPI Rx polling callback 3401 * @napi: structure for representing this polling device 3402 * @budget: how many packets driver is allowed to clean 3403 * 3404 * This function is used for legacy and MSI, NAPI mode 3405 **/ 3406 int ixgbe_poll(struct napi_struct *napi, int budget) 3407 { 3408 struct ixgbe_q_vector *q_vector = 3409 container_of(napi, struct ixgbe_q_vector, napi); 3410 struct ixgbe_adapter *adapter = q_vector->adapter; 3411 struct ixgbe_ring *ring; 3412 int per_ring_budget, work_done = 0; 3413 bool clean_complete = true; 3414 3415 #ifdef CONFIG_IXGBE_DCA 3416 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 3417 ixgbe_update_dca(q_vector); 3418 #endif 3419 3420 ixgbe_for_each_ring(ring, q_vector->tx) { 3421 bool wd = ring->xsk_pool ? 3422 ixgbe_clean_xdp_tx_irq(q_vector, ring, budget) : 3423 ixgbe_clean_tx_irq(q_vector, ring, budget); 3424 3425 if (!wd) 3426 clean_complete = false; 3427 } 3428 3429 /* Exit if we are called by netpoll */ 3430 if (budget <= 0) 3431 return budget; 3432 3433 /* attempt to distribute budget to each queue fairly, but don't allow 3434 * the budget to go below 1 because we'll exit polling */ 3435 if (q_vector->rx.count > 1) 3436 per_ring_budget = max(budget/q_vector->rx.count, 1); 3437 else 3438 per_ring_budget = budget; 3439 3440 ixgbe_for_each_ring(ring, q_vector->rx) { 3441 int cleaned = ring->xsk_pool ? 3442 ixgbe_clean_rx_irq_zc(q_vector, ring, 3443 per_ring_budget) : 3444 ixgbe_clean_rx_irq(q_vector, ring, 3445 per_ring_budget); 3446 3447 work_done += cleaned; 3448 if (cleaned >= per_ring_budget) 3449 clean_complete = false; 3450 } 3451 3452 /* If all work not completed, return budget and keep polling */ 3453 if (!clean_complete) 3454 return budget; 3455 3456 /* all work done, exit the polling mode */ 3457 if (likely(napi_complete_done(napi, work_done))) { 3458 if (adapter->rx_itr_setting & 1) 3459 ixgbe_set_itr(q_vector); 3460 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3461 ixgbe_irq_enable_queues(adapter, 3462 BIT_ULL(q_vector->v_idx)); 3463 } 3464 3465 return min(work_done, budget - 1); 3466 } 3467 3468 /** 3469 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 3470 * @adapter: board private structure 3471 * 3472 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 3473 * interrupts from the kernel. 3474 **/ 3475 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 3476 { 3477 struct net_device *netdev = adapter->netdev; 3478 unsigned int ri = 0, ti = 0; 3479 int vector, err; 3480 3481 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3482 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3483 struct msix_entry *entry = &adapter->msix_entries[vector]; 3484 3485 if (q_vector->tx.ring && q_vector->rx.ring) { 3486 snprintf(q_vector->name, sizeof(q_vector->name), 3487 "%s-TxRx-%u", netdev->name, ri++); 3488 ti++; 3489 } else if (q_vector->rx.ring) { 3490 snprintf(q_vector->name, sizeof(q_vector->name), 3491 "%s-rx-%u", netdev->name, ri++); 3492 } else if (q_vector->tx.ring) { 3493 snprintf(q_vector->name, sizeof(q_vector->name), 3494 "%s-tx-%u", netdev->name, ti++); 3495 } else { 3496 /* skip this unused q_vector */ 3497 continue; 3498 } 3499 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 3500 q_vector->name, q_vector); 3501 if (err) { 3502 e_err(probe, "request_irq failed for MSIX interrupt " 3503 "Error: %d\n", err); 3504 goto free_queue_irqs; 3505 } 3506 /* If Flow Director is enabled, set interrupt affinity */ 3507 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3508 /* assign the mask for this irq */ 3509 irq_update_affinity_hint(entry->vector, 3510 &q_vector->affinity_mask); 3511 } 3512 } 3513 3514 err = request_irq(adapter->msix_entries[vector].vector, 3515 ixgbe_msix_other, 0, netdev->name, adapter); 3516 if (err) { 3517 e_err(probe, "request_irq for msix_other failed: %d\n", err); 3518 goto free_queue_irqs; 3519 } 3520 3521 return 0; 3522 3523 free_queue_irqs: 3524 while (vector) { 3525 vector--; 3526 irq_update_affinity_hint(adapter->msix_entries[vector].vector, 3527 NULL); 3528 free_irq(adapter->msix_entries[vector].vector, 3529 adapter->q_vector[vector]); 3530 } 3531 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 3532 pci_disable_msix(adapter->pdev); 3533 kfree(adapter->msix_entries); 3534 adapter->msix_entries = NULL; 3535 return err; 3536 } 3537 3538 /** 3539 * ixgbe_intr - legacy mode Interrupt Handler 3540 * @irq: interrupt number 3541 * @data: pointer to a network interface device structure 3542 **/ 3543 static irqreturn_t ixgbe_intr(int irq, void *data) 3544 { 3545 struct ixgbe_adapter *adapter = data; 3546 struct ixgbe_hw *hw = &adapter->hw; 3547 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3548 u32 eicr; 3549 3550 /* 3551 * Workaround for silicon errata #26 on 82598. Mask the interrupt 3552 * before the read of EICR. 3553 */ 3554 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 3555 3556 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 3557 * therefore no explicit interrupt disable is necessary */ 3558 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3559 if (!eicr) { 3560 /* 3561 * shared interrupt alert! 3562 * make sure interrupts are enabled because the read will 3563 * have disabled interrupts due to EIAM 3564 * finish the workaround of silicon errata on 82598. Unmask 3565 * the interrupt that we masked before the EICR read. 3566 */ 3567 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3568 ixgbe_irq_enable(adapter, true, true); 3569 return IRQ_NONE; /* Not our interrupt */ 3570 } 3571 3572 if (eicr & IXGBE_EICR_LSC) 3573 ixgbe_check_lsc(adapter); 3574 3575 if (eicr & IXGBE_EICR_FW_EVENT) 3576 ixgbe_schedule_fw_event(adapter); 3577 3578 switch (hw->mac.type) { 3579 case ixgbe_mac_82599EB: 3580 ixgbe_check_sfp_event(adapter, eicr); 3581 fallthrough; 3582 case ixgbe_mac_X540: 3583 case ixgbe_mac_X550: 3584 case ixgbe_mac_X550EM_x: 3585 case ixgbe_mac_x550em_a: 3586 case ixgbe_mac_e610: 3587 if (eicr & IXGBE_EICR_ECC) { 3588 e_info(link, "Received ECC Err, initiating reset\n"); 3589 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3590 ixgbe_service_event_schedule(adapter); 3591 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3592 } 3593 ixgbe_check_overtemp_event(adapter, eicr); 3594 break; 3595 default: 3596 break; 3597 } 3598 3599 ixgbe_check_fan_failure(adapter, eicr); 3600 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3601 ixgbe_ptp_check_pps_event(adapter); 3602 3603 /* would disable interrupts here but EIAM disabled it */ 3604 napi_schedule_irqoff(&q_vector->napi); 3605 3606 /* 3607 * re-enable link(maybe) and non-queue interrupts, no flush. 3608 * ixgbe_poll will re-enable the queue interrupts 3609 */ 3610 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3611 ixgbe_irq_enable(adapter, false, false); 3612 3613 return IRQ_HANDLED; 3614 } 3615 3616 /** 3617 * ixgbe_request_irq - initialize interrupts 3618 * @adapter: board private structure 3619 * 3620 * Attempts to configure interrupts using the best available 3621 * capabilities of the hardware and kernel. 3622 **/ 3623 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 3624 { 3625 struct net_device *netdev = adapter->netdev; 3626 int err; 3627 3628 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 3629 err = ixgbe_request_msix_irqs(adapter); 3630 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 3631 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 3632 netdev->name, adapter); 3633 else 3634 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 3635 netdev->name, adapter); 3636 3637 if (err) 3638 e_err(probe, "request_irq failed, Error %d\n", err); 3639 3640 return err; 3641 } 3642 3643 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 3644 { 3645 int vector; 3646 3647 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3648 free_irq(adapter->pdev->irq, adapter); 3649 return; 3650 } 3651 3652 if (!adapter->msix_entries) 3653 return; 3654 3655 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3656 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3657 struct msix_entry *entry = &adapter->msix_entries[vector]; 3658 3659 /* free only the irqs that were actually requested */ 3660 if (!q_vector->rx.ring && !q_vector->tx.ring) 3661 continue; 3662 3663 /* clear the affinity_mask in the IRQ descriptor */ 3664 irq_update_affinity_hint(entry->vector, NULL); 3665 3666 free_irq(entry->vector, q_vector); 3667 } 3668 3669 free_irq(adapter->msix_entries[vector].vector, adapter); 3670 } 3671 3672 /** 3673 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 3674 * @adapter: board private structure 3675 **/ 3676 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 3677 { 3678 switch (adapter->hw.mac.type) { 3679 case ixgbe_mac_82598EB: 3680 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3681 break; 3682 case ixgbe_mac_82599EB: 3683 case ixgbe_mac_X540: 3684 case ixgbe_mac_X550: 3685 case ixgbe_mac_X550EM_x: 3686 case ixgbe_mac_x550em_a: 3687 case ixgbe_mac_e610: 3688 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3689 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3690 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3691 break; 3692 default: 3693 break; 3694 } 3695 IXGBE_WRITE_FLUSH(&adapter->hw); 3696 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3697 int vector; 3698 3699 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3700 synchronize_irq(adapter->msix_entries[vector].vector); 3701 3702 synchronize_irq(adapter->msix_entries[vector++].vector); 3703 } else { 3704 synchronize_irq(adapter->pdev->irq); 3705 } 3706 } 3707 3708 /** 3709 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3710 * @adapter: board private structure 3711 * 3712 **/ 3713 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3714 { 3715 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3716 3717 ixgbe_write_eitr(q_vector); 3718 3719 ixgbe_set_ivar(adapter, 0, 0, 0); 3720 ixgbe_set_ivar(adapter, 1, 0, 0); 3721 3722 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3723 } 3724 3725 /** 3726 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3727 * @adapter: board private structure 3728 * @ring: structure containing ring specific data 3729 * 3730 * Configure the Tx descriptor ring after a reset. 3731 **/ 3732 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3733 struct ixgbe_ring *ring) 3734 { 3735 struct ixgbe_hw *hw = &adapter->hw; 3736 u64 tdba = ring->dma; 3737 int wait_loop = 10; 3738 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3739 u8 reg_idx = ring->reg_idx; 3740 3741 ring->xsk_pool = NULL; 3742 if (ring_is_xdp(ring)) 3743 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring); 3744 3745 /* disable queue to avoid issues while updating state */ 3746 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3747 IXGBE_WRITE_FLUSH(hw); 3748 3749 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3750 (tdba & DMA_BIT_MASK(32))); 3751 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3752 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3753 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3754 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3755 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3756 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3757 3758 /* 3759 * set WTHRESH to encourage burst writeback, it should not be set 3760 * higher than 1 when: 3761 * - ITR is 0 as it could cause false TX hangs 3762 * - ITR is set to > 100k int/sec and BQL is enabled 3763 * 3764 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3765 * to or less than the number of on chip descriptors, which is 3766 * currently 40. 3767 */ 3768 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3769 txdctl |= 1u << 16; /* WTHRESH = 1 */ 3770 else 3771 txdctl |= 8u << 16; /* WTHRESH = 8 */ 3772 3773 /* 3774 * Setting PTHRESH to 32 both improves performance 3775 * and avoids a TX hang with DFP enabled 3776 */ 3777 txdctl |= (1u << 8) | /* HTHRESH = 1 */ 3778 32; /* PTHRESH = 32 */ 3779 3780 /* reinitialize flowdirector state */ 3781 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3782 ring->atr_sample_rate = adapter->atr_sample_rate; 3783 ring->atr_count = 0; 3784 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3785 } else { 3786 ring->atr_sample_rate = 0; 3787 } 3788 3789 /* initialize XPS */ 3790 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3791 struct ixgbe_q_vector *q_vector = ring->q_vector; 3792 3793 if (q_vector) 3794 netif_set_xps_queue(ring->netdev, 3795 &q_vector->affinity_mask, 3796 ring->queue_index); 3797 } 3798 3799 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3800 3801 /* reinitialize tx_buffer_info */ 3802 memset(ring->tx_buffer_info, 0, 3803 sizeof(struct ixgbe_tx_buffer) * ring->count); 3804 3805 /* enable queue */ 3806 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3807 3808 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3809 if (hw->mac.type == ixgbe_mac_82598EB && 3810 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3811 return; 3812 3813 /* poll to verify queue is enabled */ 3814 do { 3815 usleep_range(1000, 2000); 3816 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3817 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3818 if (!wait_loop) 3819 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); 3820 } 3821 3822 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3823 { 3824 struct ixgbe_hw *hw = &adapter->hw; 3825 u32 rttdcs, mtqc; 3826 u8 tcs = adapter->hw_tcs; 3827 3828 if (hw->mac.type == ixgbe_mac_82598EB) 3829 return; 3830 3831 /* disable the arbiter while setting MTQC */ 3832 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3833 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3834 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3835 3836 /* set transmit pool layout */ 3837 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3838 mtqc = IXGBE_MTQC_VT_ENA; 3839 if (tcs > 4) 3840 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3841 else if (tcs > 1) 3842 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3843 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3844 IXGBE_82599_VMDQ_4Q_MASK) 3845 mtqc |= IXGBE_MTQC_32VF; 3846 else 3847 mtqc |= IXGBE_MTQC_64VF; 3848 } else { 3849 if (tcs > 4) { 3850 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3851 } else if (tcs > 1) { 3852 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3853 } else { 3854 u8 max_txq = adapter->num_tx_queues + 3855 adapter->num_xdp_queues; 3856 if (max_txq > 63) 3857 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3858 else 3859 mtqc = IXGBE_MTQC_64Q_1PB; 3860 } 3861 } 3862 3863 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3864 3865 /* Enable Security TX Buffer IFG for multiple pb */ 3866 if (tcs) { 3867 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3868 sectx |= IXGBE_SECTX_DCB; 3869 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3870 } 3871 3872 /* re-enable the arbiter */ 3873 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3874 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3875 } 3876 3877 /** 3878 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3879 * @adapter: board private structure 3880 * 3881 * Configure the Tx unit of the MAC after a reset. 3882 **/ 3883 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3884 { 3885 struct ixgbe_hw *hw = &adapter->hw; 3886 u32 dmatxctl; 3887 u32 i; 3888 3889 ixgbe_setup_mtqc(adapter); 3890 3891 if (hw->mac.type != ixgbe_mac_82598EB) { 3892 /* DMATXCTL.EN must be before Tx queues are enabled */ 3893 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3894 dmatxctl |= IXGBE_DMATXCTL_TE; 3895 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3896 } 3897 3898 /* Setup the HW Tx Head and Tail descriptor pointers */ 3899 for (i = 0; i < adapter->num_tx_queues; i++) 3900 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3901 for (i = 0; i < adapter->num_xdp_queues; i++) 3902 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]); 3903 } 3904 3905 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3906 struct ixgbe_ring *ring) 3907 { 3908 struct ixgbe_hw *hw = &adapter->hw; 3909 u8 reg_idx = ring->reg_idx; 3910 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3911 3912 srrctl |= IXGBE_SRRCTL_DROP_EN; 3913 3914 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3915 } 3916 3917 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3918 struct ixgbe_ring *ring) 3919 { 3920 struct ixgbe_hw *hw = &adapter->hw; 3921 u8 reg_idx = ring->reg_idx; 3922 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3923 3924 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3925 3926 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3927 } 3928 3929 #ifdef CONFIG_IXGBE_DCB 3930 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3931 #else 3932 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3933 #endif 3934 { 3935 int i; 3936 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3937 3938 if (adapter->ixgbe_ieee_pfc) 3939 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3940 3941 /* 3942 * We should set the drop enable bit if: 3943 * SR-IOV is enabled 3944 * or 3945 * Number of Rx queues > 1 and flow control is disabled 3946 * 3947 * This allows us to avoid head of line blocking for security 3948 * and performance reasons. 3949 */ 3950 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3951 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3952 for (i = 0; i < adapter->num_rx_queues; i++) 3953 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3954 } else { 3955 for (i = 0; i < adapter->num_rx_queues; i++) 3956 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3957 } 3958 } 3959 3960 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3961 3962 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3963 struct ixgbe_ring *rx_ring) 3964 { 3965 struct ixgbe_hw *hw = &adapter->hw; 3966 u32 srrctl; 3967 u8 reg_idx = rx_ring->reg_idx; 3968 3969 if (hw->mac.type == ixgbe_mac_82598EB) { 3970 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3971 3972 /* 3973 * if VMDq is not active we must program one srrctl register 3974 * per RSS queue since we have enabled RDRXCTL.MVMEN 3975 */ 3976 reg_idx &= mask; 3977 } 3978 3979 /* configure header buffer length, needed for RSC */ 3980 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3981 3982 /* configure the packet buffer length */ 3983 if (rx_ring->xsk_pool) { 3984 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(rx_ring->xsk_pool); 3985 3986 /* If the MAC support setting RXDCTL.RLPML, the 3987 * SRRCTL[n].BSIZEPKT is set to PAGE_SIZE and 3988 * RXDCTL.RLPML is set to the actual UMEM buffer 3989 * size. If not, then we are stuck with a 1k buffer 3990 * size resolution. In this case frames larger than 3991 * the UMEM buffer size viewed in a 1k resolution will 3992 * be dropped. 3993 */ 3994 if (hw->mac.type != ixgbe_mac_82599EB) 3995 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3996 else 3997 srrctl |= xsk_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3998 } else if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) { 3999 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 4000 } else { 4001 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 4002 } 4003 4004 /* configure descriptor type */ 4005 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 4006 4007 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 4008 } 4009 4010 /** 4011 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries 4012 * @adapter: device handle 4013 * 4014 * - 82598/82599/X540: 128 4015 * - X550(non-SRIOV mode): 512 4016 * - X550(SRIOV mode): 64 4017 */ 4018 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 4019 { 4020 if (adapter->hw.mac.type < ixgbe_mac_X550) 4021 return 128; 4022 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 4023 return 64; 4024 else 4025 return 512; 4026 } 4027 4028 /** 4029 * ixgbe_store_key - Write the RSS key to HW 4030 * @adapter: device handle 4031 * 4032 * Write the RSS key stored in adapter.rss_key to HW. 4033 */ 4034 void ixgbe_store_key(struct ixgbe_adapter *adapter) 4035 { 4036 struct ixgbe_hw *hw = &adapter->hw; 4037 int i; 4038 4039 for (i = 0; i < 10; i++) 4040 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 4041 } 4042 4043 /** 4044 * ixgbe_init_rss_key - Initialize adapter RSS key 4045 * @adapter: device handle 4046 * 4047 * Allocates and initializes the RSS key if it is not allocated. 4048 **/ 4049 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter) 4050 { 4051 u32 *rss_key; 4052 4053 if (!adapter->rss_key) { 4054 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL); 4055 if (unlikely(!rss_key)) 4056 return -ENOMEM; 4057 4058 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE); 4059 adapter->rss_key = rss_key; 4060 } 4061 4062 return 0; 4063 } 4064 4065 /** 4066 * ixgbe_store_reta - Write the RETA table to HW 4067 * @adapter: device handle 4068 * 4069 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 4070 */ 4071 void ixgbe_store_reta(struct ixgbe_adapter *adapter) 4072 { 4073 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 4074 struct ixgbe_hw *hw = &adapter->hw; 4075 u32 reta = 0; 4076 u32 indices_multi; 4077 u8 *indir_tbl = adapter->rss_indir_tbl; 4078 4079 /* Fill out the redirection table as follows: 4080 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 4081 * indices. 4082 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 4083 * - X550: 8 bit wide entries containing 6 bit RSS index 4084 */ 4085 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 4086 indices_multi = 0x11; 4087 else 4088 indices_multi = 0x1; 4089 4090 /* Write redirection table to HW */ 4091 for (i = 0; i < reta_entries; i++) { 4092 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 4093 if ((i & 3) == 3) { 4094 if (i < 128) 4095 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 4096 else 4097 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 4098 reta); 4099 reta = 0; 4100 } 4101 } 4102 } 4103 4104 /** 4105 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) 4106 * @adapter: device handle 4107 * 4108 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 4109 */ 4110 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 4111 { 4112 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 4113 struct ixgbe_hw *hw = &adapter->hw; 4114 u32 vfreta = 0; 4115 4116 /* Write redirection table to HW */ 4117 for (i = 0; i < reta_entries; i++) { 4118 u16 pool = adapter->num_rx_pools; 4119 4120 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 4121 if ((i & 3) != 3) 4122 continue; 4123 4124 while (pool--) 4125 IXGBE_WRITE_REG(hw, 4126 IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)), 4127 vfreta); 4128 vfreta = 0; 4129 } 4130 } 4131 4132 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 4133 { 4134 u32 i, j; 4135 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 4136 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 4137 4138 /* Program table for at least 4 queues w/ SR-IOV so that VFs can 4139 * make full use of any rings they may have. We will use the 4140 * PSRTYPE register to control how many rings we use within the PF. 4141 */ 4142 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4)) 4143 rss_i = 4; 4144 4145 /* Fill out hash function seeds */ 4146 ixgbe_store_key(adapter); 4147 4148 /* Fill out redirection table */ 4149 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 4150 4151 for (i = 0, j = 0; i < reta_entries; i++, j++) { 4152 if (j == rss_i) 4153 j = 0; 4154 4155 adapter->rss_indir_tbl[i] = j; 4156 } 4157 4158 ixgbe_store_reta(adapter); 4159 } 4160 4161 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 4162 { 4163 struct ixgbe_hw *hw = &adapter->hw; 4164 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 4165 int i, j; 4166 4167 /* Fill out hash function seeds */ 4168 for (i = 0; i < 10; i++) { 4169 u16 pool = adapter->num_rx_pools; 4170 4171 while (pool--) 4172 IXGBE_WRITE_REG(hw, 4173 IXGBE_PFVFRSSRK(i, VMDQ_P(pool)), 4174 *(adapter->rss_key + i)); 4175 } 4176 4177 /* Fill out the redirection table */ 4178 for (i = 0, j = 0; i < 64; i++, j++) { 4179 if (j == rss_i) 4180 j = 0; 4181 4182 adapter->rss_indir_tbl[i] = j; 4183 } 4184 4185 ixgbe_store_vfreta(adapter); 4186 } 4187 4188 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 4189 { 4190 struct ixgbe_hw *hw = &adapter->hw; 4191 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 4192 u32 rxcsum; 4193 4194 /* Disable indicating checksum in descriptor, enables RSS hash */ 4195 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 4196 rxcsum |= IXGBE_RXCSUM_PCSD; 4197 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 4198 4199 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 4200 if (adapter->ring_feature[RING_F_RSS].mask) 4201 mrqc = IXGBE_MRQC_RSSEN; 4202 } else { 4203 u8 tcs = adapter->hw_tcs; 4204 4205 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 4206 if (tcs > 4) 4207 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 4208 else if (tcs > 1) 4209 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 4210 else if (adapter->ring_feature[RING_F_VMDQ].mask == 4211 IXGBE_82599_VMDQ_4Q_MASK) 4212 mrqc = IXGBE_MRQC_VMDQRSS32EN; 4213 else 4214 mrqc = IXGBE_MRQC_VMDQRSS64EN; 4215 4216 /* Enable L3/L4 for Tx Switched packets only for X550, 4217 * older devices do not support this feature 4218 */ 4219 if (hw->mac.type >= ixgbe_mac_X550) 4220 mrqc |= IXGBE_MRQC_L3L4TXSWEN; 4221 } else { 4222 if (tcs > 4) 4223 mrqc = IXGBE_MRQC_RTRSS8TCEN; 4224 else if (tcs > 1) 4225 mrqc = IXGBE_MRQC_RTRSS4TCEN; 4226 else 4227 mrqc = IXGBE_MRQC_RSSEN; 4228 } 4229 } 4230 4231 /* Perform hash on these packet types */ 4232 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 4233 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 4234 IXGBE_MRQC_RSS_FIELD_IPV6 | 4235 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 4236 4237 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 4238 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 4239 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 4240 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 4241 4242 if ((hw->mac.type >= ixgbe_mac_X550) && 4243 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 4244 u16 pool = adapter->num_rx_pools; 4245 4246 /* Enable VF RSS mode */ 4247 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 4248 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 4249 4250 /* Setup RSS through the VF registers */ 4251 ixgbe_setup_vfreta(adapter); 4252 vfmrqc = IXGBE_MRQC_RSSEN; 4253 vfmrqc |= rss_field; 4254 4255 while (pool--) 4256 IXGBE_WRITE_REG(hw, 4257 IXGBE_PFVFMRQC(VMDQ_P(pool)), 4258 vfmrqc); 4259 } else { 4260 ixgbe_setup_reta(adapter); 4261 mrqc |= rss_field; 4262 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 4263 } 4264 } 4265 4266 /** 4267 * ixgbe_configure_rscctl - enable RSC for the indicated ring 4268 * @adapter: address of board private structure 4269 * @ring: structure containing ring specific data 4270 **/ 4271 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 4272 struct ixgbe_ring *ring) 4273 { 4274 struct ixgbe_hw *hw = &adapter->hw; 4275 u32 rscctrl; 4276 u8 reg_idx = ring->reg_idx; 4277 4278 if (!ring_is_rsc_enabled(ring)) 4279 return; 4280 4281 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 4282 rscctrl |= IXGBE_RSCCTL_RSCEN; 4283 /* 4284 * we must limit the number of descriptors so that the 4285 * total size of max desc * buf_len is not greater 4286 * than 65536 4287 */ 4288 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 4289 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 4290 } 4291 4292 #define IXGBE_MAX_RX_DESC_POLL 10 4293 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 4294 struct ixgbe_ring *ring) 4295 { 4296 struct ixgbe_hw *hw = &adapter->hw; 4297 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4298 u32 rxdctl; 4299 u8 reg_idx = ring->reg_idx; 4300 4301 if (ixgbe_removed(hw->hw_addr)) 4302 return; 4303 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 4304 if (hw->mac.type == ixgbe_mac_82598EB && 4305 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4306 return; 4307 4308 do { 4309 usleep_range(1000, 2000); 4310 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4311 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 4312 4313 if (!wait_loop) { 4314 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 4315 "the polling period\n", reg_idx); 4316 } 4317 } 4318 4319 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 4320 struct ixgbe_ring *ring) 4321 { 4322 struct ixgbe_hw *hw = &adapter->hw; 4323 union ixgbe_adv_rx_desc *rx_desc; 4324 u64 rdba = ring->dma; 4325 u32 rxdctl; 4326 u8 reg_idx = ring->reg_idx; 4327 4328 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4329 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring); 4330 if (ring->xsk_pool) { 4331 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4332 MEM_TYPE_XSK_BUFF_POOL, 4333 NULL)); 4334 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq); 4335 } else { 4336 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4337 MEM_TYPE_PAGE_SHARED, NULL)); 4338 } 4339 4340 /* disable queue to avoid use of these values while updating state */ 4341 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4342 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 4343 4344 /* write value back with RXDCTL.ENABLE bit cleared */ 4345 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4346 IXGBE_WRITE_FLUSH(hw); 4347 4348 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 4349 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 4350 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 4351 ring->count * sizeof(union ixgbe_adv_rx_desc)); 4352 /* Force flushing of IXGBE_RDLEN to prevent MDD */ 4353 IXGBE_WRITE_FLUSH(hw); 4354 4355 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 4356 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 4357 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 4358 4359 ixgbe_configure_srrctl(adapter, ring); 4360 ixgbe_configure_rscctl(adapter, ring); 4361 4362 if (hw->mac.type == ixgbe_mac_82598EB) { 4363 /* 4364 * enable cache line friendly hardware writes: 4365 * PTHRESH=32 descriptors (half the internal cache), 4366 * this also removes ugly rx_no_buffer_count increment 4367 * HTHRESH=4 descriptors (to minimize latency on fetch) 4368 * WTHRESH=8 burst writeback up to two cache lines 4369 */ 4370 rxdctl &= ~0x3FFFFF; 4371 rxdctl |= 0x080420; 4372 #if (PAGE_SIZE < 8192) 4373 /* RXDCTL.RLPML does not work on 82599 */ 4374 } else if (hw->mac.type != ixgbe_mac_82599EB) { 4375 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4376 IXGBE_RXDCTL_RLPML_EN); 4377 4378 /* Limit the maximum frame size so we don't overrun the skb. 4379 * This can happen in SRIOV mode when the MTU of the VF is 4380 * higher than the MTU of the PF. 4381 */ 4382 if (ring_uses_build_skb(ring) && 4383 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 4384 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB | 4385 IXGBE_RXDCTL_RLPML_EN; 4386 #endif 4387 } 4388 4389 ring->rx_offset = ixgbe_rx_offset(ring); 4390 4391 if (ring->xsk_pool && hw->mac.type != ixgbe_mac_82599EB) { 4392 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(ring->xsk_pool); 4393 4394 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4395 IXGBE_RXDCTL_RLPML_EN); 4396 rxdctl |= xsk_buf_len | IXGBE_RXDCTL_RLPML_EN; 4397 4398 ring->rx_buf_len = xsk_buf_len; 4399 } 4400 4401 /* initialize rx_buffer_info */ 4402 memset(ring->rx_buffer_info, 0, 4403 sizeof(struct ixgbe_rx_buffer) * ring->count); 4404 4405 /* initialize Rx descriptor 0 */ 4406 rx_desc = IXGBE_RX_DESC(ring, 0); 4407 rx_desc->wb.upper.length = 0; 4408 4409 /* enable receive descriptor ring */ 4410 rxdctl |= IXGBE_RXDCTL_ENABLE; 4411 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4412 4413 ixgbe_rx_desc_queue_enable(adapter, ring); 4414 if (ring->xsk_pool) 4415 ixgbe_alloc_rx_buffers_zc(ring, ixgbe_desc_unused(ring)); 4416 else 4417 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 4418 } 4419 4420 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 4421 { 4422 struct ixgbe_hw *hw = &adapter->hw; 4423 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 4424 u16 pool = adapter->num_rx_pools; 4425 4426 /* PSRTYPE must be initialized in non 82598 adapters */ 4427 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4428 IXGBE_PSRTYPE_UDPHDR | 4429 IXGBE_PSRTYPE_IPV4HDR | 4430 IXGBE_PSRTYPE_L2HDR | 4431 IXGBE_PSRTYPE_IPV6HDR; 4432 4433 if (hw->mac.type == ixgbe_mac_82598EB) 4434 return; 4435 4436 if (rss_i > 3) 4437 psrtype |= 2u << 29; 4438 else if (rss_i > 1) 4439 psrtype |= 1u << 29; 4440 4441 while (pool--) 4442 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4443 } 4444 4445 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 4446 { 4447 struct ixgbe_hw *hw = &adapter->hw; 4448 u16 pool = adapter->num_rx_pools; 4449 u32 reg_offset, vf_shift, vmolr; 4450 u32 gcr_ext, vmdctl; 4451 int i; 4452 4453 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 4454 return; 4455 4456 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 4457 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 4458 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 4459 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 4460 vmdctl |= IXGBE_VT_CTL_REPLEN; 4461 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 4462 4463 /* accept untagged packets until a vlan tag is 4464 * specifically set for the VMDQ queue/pool 4465 */ 4466 vmolr = IXGBE_VMOLR_AUPE; 4467 while (pool--) 4468 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(pool)), vmolr); 4469 4470 vf_shift = VMDQ_P(0) % 32; 4471 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 4472 4473 /* Enable only the PF's pool for Tx/Rx */ 4474 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); 4475 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 4476 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); 4477 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 4478 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 4479 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 4480 4481 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 4482 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 4483 4484 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 4485 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4486 4487 /* 4488 * Set up VF register offsets for selected VT Mode, 4489 * i.e. 32 or 64 VFs for SR-IOV 4490 */ 4491 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4492 case IXGBE_82599_VMDQ_8Q_MASK: 4493 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 4494 break; 4495 case IXGBE_82599_VMDQ_4Q_MASK: 4496 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 4497 break; 4498 default: 4499 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 4500 break; 4501 } 4502 4503 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4504 4505 for (i = 0; i < adapter->num_vfs; i++) { 4506 /* configure spoof checking */ 4507 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, 4508 adapter->vfinfo[i].spoofchk_enabled); 4509 4510 /* Enable/Disable RSS query feature */ 4511 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 4512 adapter->vfinfo[i].rss_query_enabled); 4513 } 4514 } 4515 4516 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 4517 { 4518 struct ixgbe_hw *hw = &adapter->hw; 4519 struct net_device *netdev = adapter->netdev; 4520 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4521 struct ixgbe_ring *rx_ring; 4522 int i; 4523 u32 mhadd, hlreg0; 4524 4525 #ifdef IXGBE_FCOE 4526 /* adjust max frame to be able to do baby jumbo for FCoE */ 4527 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 4528 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 4529 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4530 4531 #endif /* IXGBE_FCOE */ 4532 4533 /* adjust max frame to be at least the size of a standard frame */ 4534 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 4535 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 4536 4537 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 4538 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 4539 mhadd &= ~IXGBE_MHADD_MFS_MASK; 4540 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 4541 4542 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 4543 } 4544 4545 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4546 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 4547 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4548 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4549 4550 /* 4551 * Setup the HW Rx Head and Tail Descriptor Pointers and 4552 * the Base and Length of the Rx Descriptor Ring 4553 */ 4554 for (i = 0; i < adapter->num_rx_queues; i++) { 4555 rx_ring = adapter->rx_ring[i]; 4556 4557 clear_ring_rsc_enabled(rx_ring); 4558 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4559 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4560 4561 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4562 set_ring_rsc_enabled(rx_ring); 4563 4564 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state)) 4565 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4566 4567 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 4568 continue; 4569 4570 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4571 4572 #if (PAGE_SIZE < 8192) 4573 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4574 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4575 4576 if (IXGBE_2K_TOO_SMALL_WITH_PADDING || 4577 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 4578 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4579 #endif 4580 } 4581 } 4582 4583 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 4584 { 4585 struct ixgbe_hw *hw = &adapter->hw; 4586 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 4587 4588 switch (hw->mac.type) { 4589 case ixgbe_mac_82598EB: 4590 /* 4591 * For VMDq support of different descriptor types or 4592 * buffer sizes through the use of multiple SRRCTL 4593 * registers, RDRXCTL.MVMEN must be set to 1 4594 * 4595 * also, the manual doesn't mention it clearly but DCA hints 4596 * will only use queue 0's tags unless this bit is set. Side 4597 * effects of setting this bit are only that SRRCTL must be 4598 * fully programmed [0..15] 4599 */ 4600 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 4601 break; 4602 case ixgbe_mac_X550: 4603 case ixgbe_mac_X550EM_x: 4604 case ixgbe_mac_x550em_a: 4605 case ixgbe_mac_e610: 4606 if (adapter->num_vfs) 4607 rdrxctl |= IXGBE_RDRXCTL_PSP; 4608 fallthrough; 4609 case ixgbe_mac_82599EB: 4610 case ixgbe_mac_X540: 4611 /* Disable RSC for ACK packets */ 4612 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 4613 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 4614 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 4615 /* hardware requires some bits to be set by default */ 4616 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 4617 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 4618 break; 4619 default: 4620 /* We should do nothing since we don't know this hardware */ 4621 return; 4622 } 4623 4624 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 4625 } 4626 4627 /** 4628 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 4629 * @adapter: board private structure 4630 * 4631 * Configure the Rx unit of the MAC after a reset. 4632 **/ 4633 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 4634 { 4635 struct ixgbe_hw *hw = &adapter->hw; 4636 int i; 4637 u32 rxctrl, rfctl; 4638 4639 /* disable receives while setting up the descriptors */ 4640 hw->mac.ops.disable_rx(hw); 4641 4642 ixgbe_setup_psrtype(adapter); 4643 ixgbe_setup_rdrxctl(adapter); 4644 4645 /* RSC Setup */ 4646 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 4647 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 4648 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 4649 rfctl |= IXGBE_RFCTL_RSC_DIS; 4650 4651 /* disable NFS filtering */ 4652 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS); 4653 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 4654 4655 /* Program registers for the distribution of queues */ 4656 ixgbe_setup_mrqc(adapter); 4657 4658 /* set_rx_buffer_len must be called before ring initialization */ 4659 ixgbe_set_rx_buffer_len(adapter); 4660 4661 /* 4662 * Setup the HW Rx Head and Tail Descriptor Pointers and 4663 * the Base and Length of the Rx Descriptor Ring 4664 */ 4665 for (i = 0; i < adapter->num_rx_queues; i++) 4666 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 4667 4668 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4669 /* disable drop enable for 82598 parts */ 4670 if (hw->mac.type == ixgbe_mac_82598EB) 4671 rxctrl |= IXGBE_RXCTRL_DMBYPS; 4672 4673 /* enable all receives */ 4674 rxctrl |= IXGBE_RXCTRL_RXEN; 4675 hw->mac.ops.enable_rx_dma(hw, rxctrl); 4676 } 4677 4678 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 4679 __be16 proto, u16 vid) 4680 { 4681 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4682 struct ixgbe_hw *hw = &adapter->hw; 4683 4684 /* add VID to filter table */ 4685 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4686 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); 4687 4688 set_bit(vid, adapter->active_vlans); 4689 4690 return 0; 4691 } 4692 4693 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) 4694 { 4695 u32 vlvf; 4696 int idx; 4697 4698 /* short cut the special case */ 4699 if (vlan == 0) 4700 return 0; 4701 4702 /* Search for the vlan id in the VLVF entries */ 4703 for (idx = IXGBE_VLVF_ENTRIES; --idx;) { 4704 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); 4705 if ((vlvf & VLAN_VID_MASK) == vlan) 4706 break; 4707 } 4708 4709 return idx; 4710 } 4711 4712 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) 4713 { 4714 struct ixgbe_hw *hw = &adapter->hw; 4715 u32 bits, word; 4716 int idx; 4717 4718 idx = ixgbe_find_vlvf_entry(hw, vid); 4719 if (!idx) 4720 return; 4721 4722 /* See if any other pools are set for this VLAN filter 4723 * entry other than the PF. 4724 */ 4725 word = idx * 2 + (VMDQ_P(0) / 32); 4726 bits = ~BIT(VMDQ_P(0) % 32); 4727 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4728 4729 /* Disable the filter so this falls into the default pool. */ 4730 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { 4731 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4732 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); 4733 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); 4734 } 4735 } 4736 4737 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 4738 __be16 proto, u16 vid) 4739 { 4740 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4741 struct ixgbe_hw *hw = &adapter->hw; 4742 4743 /* remove VID from filter table */ 4744 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4745 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); 4746 4747 clear_bit(vid, adapter->active_vlans); 4748 4749 return 0; 4750 } 4751 4752 /** 4753 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 4754 * @adapter: driver data 4755 */ 4756 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 4757 { 4758 struct ixgbe_hw *hw = &adapter->hw; 4759 u32 vlnctrl; 4760 int i, j; 4761 4762 switch (hw->mac.type) { 4763 case ixgbe_mac_82598EB: 4764 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4765 vlnctrl &= ~IXGBE_VLNCTRL_VME; 4766 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4767 break; 4768 case ixgbe_mac_82599EB: 4769 case ixgbe_mac_X540: 4770 case ixgbe_mac_X550: 4771 case ixgbe_mac_X550EM_x: 4772 case ixgbe_mac_x550em_a: 4773 case ixgbe_mac_e610: 4774 for (i = 0; i < adapter->num_rx_queues; i++) { 4775 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4776 4777 if (!netif_is_ixgbe(ring->netdev)) 4778 continue; 4779 4780 j = ring->reg_idx; 4781 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4782 vlnctrl &= ~IXGBE_RXDCTL_VME; 4783 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4784 } 4785 break; 4786 default: 4787 break; 4788 } 4789 } 4790 4791 /** 4792 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 4793 * @adapter: driver data 4794 */ 4795 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 4796 { 4797 struct ixgbe_hw *hw = &adapter->hw; 4798 u32 vlnctrl; 4799 int i, j; 4800 4801 switch (hw->mac.type) { 4802 case ixgbe_mac_82598EB: 4803 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4804 vlnctrl |= IXGBE_VLNCTRL_VME; 4805 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4806 break; 4807 case ixgbe_mac_82599EB: 4808 case ixgbe_mac_X540: 4809 case ixgbe_mac_X550: 4810 case ixgbe_mac_X550EM_x: 4811 case ixgbe_mac_x550em_a: 4812 case ixgbe_mac_e610: 4813 for (i = 0; i < adapter->num_rx_queues; i++) { 4814 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4815 4816 if (!netif_is_ixgbe(ring->netdev)) 4817 continue; 4818 4819 j = ring->reg_idx; 4820 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4821 vlnctrl |= IXGBE_RXDCTL_VME; 4822 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4823 } 4824 break; 4825 default: 4826 break; 4827 } 4828 } 4829 4830 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) 4831 { 4832 struct ixgbe_hw *hw = &adapter->hw; 4833 u32 vlnctrl, i; 4834 4835 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4836 4837 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { 4838 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */ 4839 vlnctrl |= IXGBE_VLNCTRL_VFE; 4840 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4841 } else { 4842 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 4843 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4844 return; 4845 } 4846 4847 /* Nothing to do for 82598 */ 4848 if (hw->mac.type == ixgbe_mac_82598EB) 4849 return; 4850 4851 /* We are already in VLAN promisc, nothing to do */ 4852 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) 4853 return; 4854 4855 /* Set flag so we don't redo unnecessary work */ 4856 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; 4857 4858 /* Add PF to all active pools */ 4859 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4860 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); 4861 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); 4862 4863 vlvfb |= BIT(VMDQ_P(0) % 32); 4864 IXGBE_WRITE_REG(hw, reg_offset, vlvfb); 4865 } 4866 4867 /* Set all bits in the VLAN filter table array */ 4868 for (i = hw->mac.vft_size; i--;) 4869 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); 4870 } 4871 4872 #define VFTA_BLOCK_SIZE 8 4873 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) 4874 { 4875 struct ixgbe_hw *hw = &adapter->hw; 4876 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4877 u32 vid_start = vfta_offset * 32; 4878 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4879 u32 i, vid, word, bits; 4880 4881 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4882 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); 4883 4884 /* pull VLAN ID from VLVF */ 4885 vid = vlvf & VLAN_VID_MASK; 4886 4887 /* only concern outselves with a certain range */ 4888 if (vid < vid_start || vid >= vid_end) 4889 continue; 4890 4891 if (vlvf) { 4892 /* record VLAN ID in VFTA */ 4893 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4894 4895 /* if PF is part of this then continue */ 4896 if (test_bit(vid, adapter->active_vlans)) 4897 continue; 4898 } 4899 4900 /* remove PF from the pool */ 4901 word = i * 2 + VMDQ_P(0) / 32; 4902 bits = ~BIT(VMDQ_P(0) % 32); 4903 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4904 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); 4905 } 4906 4907 /* extract values from active_vlans and write back to VFTA */ 4908 for (i = VFTA_BLOCK_SIZE; i--;) { 4909 vid = (vfta_offset + i) * 32; 4910 word = vid / BITS_PER_LONG; 4911 bits = vid % BITS_PER_LONG; 4912 4913 vfta[i] |= adapter->active_vlans[word] >> bits; 4914 4915 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); 4916 } 4917 } 4918 4919 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) 4920 { 4921 struct ixgbe_hw *hw = &adapter->hw; 4922 u32 vlnctrl, i; 4923 4924 /* Set VLAN filtering to enabled */ 4925 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4926 vlnctrl |= IXGBE_VLNCTRL_VFE; 4927 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4928 4929 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) || 4930 hw->mac.type == ixgbe_mac_82598EB) 4931 return; 4932 4933 /* We are not in VLAN promisc, nothing to do */ 4934 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4935 return; 4936 4937 /* Set flag so we don't redo unnecessary work */ 4938 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4939 4940 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) 4941 ixgbe_scrub_vfta(adapter, i); 4942 } 4943 4944 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 4945 { 4946 u16 vid = 1; 4947 4948 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 4949 4950 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 4951 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 4952 } 4953 4954 /** 4955 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 4956 * @netdev: network interface device structure 4957 * 4958 * Writes multicast address list to the MTA hash table. 4959 * Returns: -ENOMEM on failure 4960 * 0 on no addresses written 4961 * X on writing X addresses to MTA 4962 **/ 4963 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 4964 { 4965 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4966 struct ixgbe_hw *hw = &adapter->hw; 4967 4968 if (!netif_running(netdev)) 4969 return 0; 4970 4971 if (hw->mac.ops.update_mc_addr_list) 4972 hw->mac.ops.update_mc_addr_list(hw, netdev); 4973 else 4974 return -ENOMEM; 4975 4976 #ifdef CONFIG_PCI_IOV 4977 ixgbe_restore_vf_multicasts(adapter); 4978 #endif 4979 4980 return netdev_mc_count(netdev); 4981 } 4982 4983 #ifdef CONFIG_PCI_IOV 4984 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 4985 { 4986 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4987 struct ixgbe_hw *hw = &adapter->hw; 4988 int i; 4989 4990 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4991 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4992 4993 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4994 hw->mac.ops.set_rar(hw, i, 4995 mac_table->addr, 4996 mac_table->pool, 4997 IXGBE_RAH_AV); 4998 else 4999 hw->mac.ops.clear_rar(hw, i); 5000 } 5001 } 5002 5003 #endif 5004 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 5005 { 5006 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 5007 struct ixgbe_hw *hw = &adapter->hw; 5008 int i; 5009 5010 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 5011 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) 5012 continue; 5013 5014 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 5015 5016 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 5017 hw->mac.ops.set_rar(hw, i, 5018 mac_table->addr, 5019 mac_table->pool, 5020 IXGBE_RAH_AV); 5021 else 5022 hw->mac.ops.clear_rar(hw, i); 5023 } 5024 } 5025 5026 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 5027 { 5028 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 5029 struct ixgbe_hw *hw = &adapter->hw; 5030 int i; 5031 5032 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 5033 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 5034 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 5035 } 5036 5037 ixgbe_sync_mac_table(adapter); 5038 } 5039 5040 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) 5041 { 5042 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 5043 struct ixgbe_hw *hw = &adapter->hw; 5044 int i, count = 0; 5045 5046 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 5047 /* do not count default RAR as available */ 5048 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) 5049 continue; 5050 5051 /* only count unused and addresses that belong to us */ 5052 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { 5053 if (mac_table->pool != pool) 5054 continue; 5055 } 5056 5057 count++; 5058 } 5059 5060 return count; 5061 } 5062 5063 /* this function destroys the first RAR entry */ 5064 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) 5065 { 5066 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 5067 struct ixgbe_hw *hw = &adapter->hw; 5068 5069 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); 5070 mac_table->pool = VMDQ_P(0); 5071 5072 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; 5073 5074 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, 5075 IXGBE_RAH_AV); 5076 } 5077 5078 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 5079 const u8 *addr, u16 pool) 5080 { 5081 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 5082 struct ixgbe_hw *hw = &adapter->hw; 5083 int i; 5084 5085 if (is_zero_ether_addr(addr)) 5086 return -EINVAL; 5087 5088 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 5089 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 5090 continue; 5091 5092 ether_addr_copy(mac_table->addr, addr); 5093 mac_table->pool = pool; 5094 5095 mac_table->state |= IXGBE_MAC_STATE_MODIFIED | 5096 IXGBE_MAC_STATE_IN_USE; 5097 5098 ixgbe_sync_mac_table(adapter); 5099 5100 return i; 5101 } 5102 5103 return -ENOMEM; 5104 } 5105 5106 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 5107 const u8 *addr, u16 pool) 5108 { 5109 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 5110 struct ixgbe_hw *hw = &adapter->hw; 5111 int i; 5112 5113 if (is_zero_ether_addr(addr)) 5114 return -EINVAL; 5115 5116 /* search table for addr, if found clear IN_USE flag and sync */ 5117 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 5118 /* we can only delete an entry if it is in use */ 5119 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) 5120 continue; 5121 /* we only care about entries that belong to the given pool */ 5122 if (mac_table->pool != pool) 5123 continue; 5124 /* we only care about a specific MAC address */ 5125 if (!ether_addr_equal(addr, mac_table->addr)) 5126 continue; 5127 5128 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 5129 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 5130 5131 ixgbe_sync_mac_table(adapter); 5132 5133 return 0; 5134 } 5135 5136 return -ENOMEM; 5137 } 5138 5139 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) 5140 { 5141 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5142 int ret; 5143 5144 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); 5145 5146 return min_t(int, ret, 0); 5147 } 5148 5149 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) 5150 { 5151 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5152 5153 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); 5154 5155 return 0; 5156 } 5157 5158 /** 5159 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 5160 * @netdev: network interface device structure 5161 * 5162 * The set_rx_method entry point is called whenever the unicast/multicast 5163 * address list or the network interface flags are updated. This routine is 5164 * responsible for configuring the hardware for proper unicast, multicast and 5165 * promiscuous mode. 5166 **/ 5167 void ixgbe_set_rx_mode(struct net_device *netdev) 5168 { 5169 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5170 struct ixgbe_hw *hw = &adapter->hw; 5171 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 5172 netdev_features_t features = netdev->features; 5173 int count; 5174 5175 /* Check for Promiscuous and All Multicast modes */ 5176 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 5177 5178 /* set all bits that we expect to always be set */ 5179 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 5180 fctrl |= IXGBE_FCTRL_BAM; 5181 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 5182 fctrl |= IXGBE_FCTRL_PMCF; 5183 5184 /* clear the bits we are changing the status of */ 5185 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 5186 if (netdev->flags & IFF_PROMISC) { 5187 hw->addr_ctrl.user_set_promisc = true; 5188 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 5189 vmolr |= IXGBE_VMOLR_MPE; 5190 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 5191 } else { 5192 if (netdev->flags & IFF_ALLMULTI) { 5193 fctrl |= IXGBE_FCTRL_MPE; 5194 vmolr |= IXGBE_VMOLR_MPE; 5195 } 5196 hw->addr_ctrl.user_set_promisc = false; 5197 } 5198 5199 /* 5200 * Write addresses to available RAR registers, if there is not 5201 * sufficient space to store all the addresses then enable 5202 * unicast promiscuous mode 5203 */ 5204 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { 5205 fctrl |= IXGBE_FCTRL_UPE; 5206 vmolr |= IXGBE_VMOLR_ROPE; 5207 } 5208 5209 /* Write addresses to the MTA, if the attempt fails 5210 * then we should just turn on promiscuous mode so 5211 * that we can at least receive multicast traffic 5212 */ 5213 count = ixgbe_write_mc_addr_list(netdev); 5214 if (count < 0) { 5215 fctrl |= IXGBE_FCTRL_MPE; 5216 vmolr |= IXGBE_VMOLR_MPE; 5217 } else if (count) { 5218 vmolr |= IXGBE_VMOLR_ROMPE; 5219 } 5220 5221 if (hw->mac.type != ixgbe_mac_82598EB) { 5222 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 5223 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 5224 IXGBE_VMOLR_ROPE); 5225 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 5226 } 5227 5228 /* This is useful for sniffing bad packets. */ 5229 if (features & NETIF_F_RXALL) { 5230 /* UPE and MPE will be handled by normal PROMISC logic 5231 * in e1000e_set_rx_mode */ 5232 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 5233 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 5234 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 5235 5236 fctrl &= ~(IXGBE_FCTRL_DPF); 5237 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 5238 } 5239 5240 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 5241 5242 if (features & NETIF_F_HW_VLAN_CTAG_RX) 5243 ixgbe_vlan_strip_enable(adapter); 5244 else 5245 ixgbe_vlan_strip_disable(adapter); 5246 5247 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 5248 ixgbe_vlan_promisc_disable(adapter); 5249 else 5250 ixgbe_vlan_promisc_enable(adapter); 5251 } 5252 5253 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 5254 { 5255 int q_idx; 5256 5257 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 5258 napi_enable(&adapter->q_vector[q_idx]->napi); 5259 } 5260 5261 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 5262 { 5263 int q_idx; 5264 5265 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 5266 napi_disable(&adapter->q_vector[q_idx]->napi); 5267 } 5268 5269 static int ixgbe_udp_tunnel_sync(struct net_device *dev, unsigned int table) 5270 { 5271 struct ixgbe_adapter *adapter = netdev_priv(dev); 5272 struct ixgbe_hw *hw = &adapter->hw; 5273 struct udp_tunnel_info ti; 5274 5275 udp_tunnel_nic_get_port(dev, table, 0, &ti); 5276 if (ti.type == UDP_TUNNEL_TYPE_VXLAN) 5277 adapter->vxlan_port = ti.port; 5278 else 5279 adapter->geneve_port = ti.port; 5280 5281 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, 5282 ntohs(adapter->vxlan_port) | 5283 ntohs(adapter->geneve_port) << 5284 IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT); 5285 return 0; 5286 } 5287 5288 static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550 = { 5289 .sync_table = ixgbe_udp_tunnel_sync, 5290 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY, 5291 .tables = { 5292 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 5293 }, 5294 }; 5295 5296 static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550em_a = { 5297 .sync_table = ixgbe_udp_tunnel_sync, 5298 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY, 5299 .tables = { 5300 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 5301 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, }, 5302 }, 5303 }; 5304 5305 #ifdef CONFIG_IXGBE_DCB 5306 /** 5307 * ixgbe_configure_dcb - Configure DCB hardware 5308 * @adapter: ixgbe adapter struct 5309 * 5310 * This is called by the driver on open to configure the DCB hardware. 5311 * This is also called by the gennetlink interface when reconfiguring 5312 * the DCB state. 5313 */ 5314 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 5315 { 5316 struct ixgbe_hw *hw = &adapter->hw; 5317 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 5318 5319 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 5320 if (hw->mac.type == ixgbe_mac_82598EB) 5321 netif_set_tso_max_size(adapter->netdev, 65536); 5322 return; 5323 } 5324 5325 if (hw->mac.type == ixgbe_mac_82598EB) 5326 netif_set_tso_max_size(adapter->netdev, 32768); 5327 5328 #ifdef IXGBE_FCOE 5329 if (adapter->netdev->fcoe_mtu) 5330 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 5331 #endif 5332 5333 /* reconfigure the hardware */ 5334 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 5335 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5336 DCB_TX_CONFIG); 5337 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5338 DCB_RX_CONFIG); 5339 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 5340 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 5341 ixgbe_dcb_hw_ets(&adapter->hw, 5342 adapter->ixgbe_ieee_ets, 5343 max_frame); 5344 ixgbe_dcb_hw_pfc_config(&adapter->hw, 5345 adapter->ixgbe_ieee_pfc->pfc_en, 5346 adapter->ixgbe_ieee_ets->prio_tc); 5347 } 5348 5349 /* Enable RSS Hash per TC */ 5350 if (hw->mac.type != ixgbe_mac_82598EB) { 5351 u32 msb = 0; 5352 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 5353 5354 while (rss_i) { 5355 msb++; 5356 rss_i >>= 1; 5357 } 5358 5359 /* write msb to all 8 TCs in one write */ 5360 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 5361 } 5362 } 5363 #endif 5364 5365 /* Additional bittime to account for IXGBE framing */ 5366 #define IXGBE_ETH_FRAMING 20 5367 5368 /** 5369 * ixgbe_hpbthresh - calculate high water mark for flow control 5370 * 5371 * @adapter: board private structure to calculate for 5372 * @pb: packet buffer to calculate 5373 */ 5374 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 5375 { 5376 struct ixgbe_hw *hw = &adapter->hw; 5377 struct net_device *dev = adapter->netdev; 5378 int link, tc, kb, marker; 5379 u32 dv_id, rx_pba; 5380 5381 /* Calculate max LAN frame size */ 5382 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 5383 5384 #ifdef IXGBE_FCOE 5385 /* FCoE traffic class uses FCOE jumbo frames */ 5386 if (dev->fcoe_mtu && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE && 5387 (pb == ixgbe_fcoe_get_tc(adapter))) 5388 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5389 #endif 5390 5391 /* Calculate delay value for device */ 5392 switch (hw->mac.type) { 5393 case ixgbe_mac_X540: 5394 case ixgbe_mac_X550: 5395 case ixgbe_mac_X550EM_x: 5396 case ixgbe_mac_x550em_a: 5397 case ixgbe_mac_e610: 5398 dv_id = IXGBE_DV_X540(link, tc); 5399 break; 5400 default: 5401 dv_id = IXGBE_DV(link, tc); 5402 break; 5403 } 5404 5405 /* Loopback switch introduces additional latency */ 5406 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5407 dv_id += IXGBE_B2BT(tc); 5408 5409 /* Delay value is calculated in bit times convert to KB */ 5410 kb = IXGBE_BT2KB(dv_id); 5411 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 5412 5413 marker = rx_pba - kb; 5414 5415 /* It is possible that the packet buffer is not large enough 5416 * to provide required headroom. In this case throw an error 5417 * to user and a do the best we can. 5418 */ 5419 if (marker < 0) { 5420 e_warn(drv, "Packet Buffer(%i) can not provide enough" 5421 "headroom to support flow control." 5422 "Decrease MTU or number of traffic classes\n", pb); 5423 marker = tc + 1; 5424 } 5425 5426 return marker; 5427 } 5428 5429 /** 5430 * ixgbe_lpbthresh - calculate low water mark for flow control 5431 * 5432 * @adapter: board private structure to calculate for 5433 * @pb: packet buffer to calculate 5434 */ 5435 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 5436 { 5437 struct ixgbe_hw *hw = &adapter->hw; 5438 struct net_device *dev = adapter->netdev; 5439 int tc; 5440 u32 dv_id; 5441 5442 /* Calculate max LAN frame size */ 5443 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 5444 5445 #ifdef IXGBE_FCOE 5446 /* FCoE traffic class uses FCOE jumbo frames */ 5447 if (dev->fcoe_mtu && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE && 5448 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 5449 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5450 #endif 5451 5452 /* Calculate delay value for device */ 5453 switch (hw->mac.type) { 5454 case ixgbe_mac_X540: 5455 case ixgbe_mac_X550: 5456 case ixgbe_mac_X550EM_x: 5457 case ixgbe_mac_x550em_a: 5458 case ixgbe_mac_e610: 5459 dv_id = IXGBE_LOW_DV_X540(tc); 5460 break; 5461 default: 5462 dv_id = IXGBE_LOW_DV(tc); 5463 break; 5464 } 5465 5466 /* Delay value is calculated in bit times convert to KB */ 5467 return IXGBE_BT2KB(dv_id); 5468 } 5469 5470 /* 5471 * ixgbe_pbthresh_setup - calculate and setup high low water marks 5472 */ 5473 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 5474 { 5475 struct ixgbe_hw *hw = &adapter->hw; 5476 int num_tc = adapter->hw_tcs; 5477 int i; 5478 5479 if (!num_tc) 5480 num_tc = 1; 5481 5482 for (i = 0; i < num_tc; i++) { 5483 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 5484 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 5485 5486 /* Low water marks must not be larger than high water marks */ 5487 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 5488 hw->fc.low_water[i] = 0; 5489 } 5490 5491 for (; i < MAX_TRAFFIC_CLASS; i++) 5492 hw->fc.high_water[i] = 0; 5493 } 5494 5495 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 5496 { 5497 struct ixgbe_hw *hw = &adapter->hw; 5498 int hdrm; 5499 u8 tc = adapter->hw_tcs; 5500 5501 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 5502 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 5503 hdrm = 32 << adapter->fdir_pballoc; 5504 else 5505 hdrm = 0; 5506 5507 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 5508 ixgbe_pbthresh_setup(adapter); 5509 } 5510 5511 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 5512 { 5513 struct ixgbe_hw *hw = &adapter->hw; 5514 struct hlist_node *node2; 5515 struct ixgbe_fdir_filter *filter; 5516 u8 queue; 5517 5518 spin_lock(&adapter->fdir_perfect_lock); 5519 5520 if (!hlist_empty(&adapter->fdir_filter_list)) 5521 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 5522 5523 hlist_for_each_entry_safe(filter, node2, 5524 &adapter->fdir_filter_list, fdir_node) { 5525 if (filter->action == IXGBE_FDIR_DROP_QUEUE) { 5526 queue = IXGBE_FDIR_DROP_QUEUE; 5527 } else { 5528 u32 ring = ethtool_get_flow_spec_ring(filter->action); 5529 u8 vf = ethtool_get_flow_spec_ring_vf(filter->action); 5530 5531 if (!vf && (ring >= adapter->num_rx_queues)) { 5532 e_err(drv, "FDIR restore failed without VF, ring: %u\n", 5533 ring); 5534 continue; 5535 } else if (vf && 5536 ((vf > adapter->num_vfs) || 5537 ring >= adapter->num_rx_queues_per_pool)) { 5538 e_err(drv, "FDIR restore failed with VF, vf: %hhu, ring: %u\n", 5539 vf, ring); 5540 continue; 5541 } 5542 5543 /* Map the ring onto the absolute queue index */ 5544 if (!vf) 5545 queue = adapter->rx_ring[ring]->reg_idx; 5546 else 5547 queue = ((vf - 1) * 5548 adapter->num_rx_queues_per_pool) + ring; 5549 } 5550 5551 ixgbe_fdir_write_perfect_filter_82599(hw, 5552 &filter->filter, filter->sw_idx, queue); 5553 } 5554 5555 spin_unlock(&adapter->fdir_perfect_lock); 5556 } 5557 5558 /** 5559 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 5560 * @rx_ring: ring to free buffers from 5561 **/ 5562 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 5563 { 5564 u16 i = rx_ring->next_to_clean; 5565 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 5566 5567 if (rx_ring->xsk_pool) { 5568 ixgbe_xsk_clean_rx_ring(rx_ring); 5569 goto skip_free; 5570 } 5571 5572 /* Free all the Rx ring sk_buffs */ 5573 while (i != rx_ring->next_to_alloc) { 5574 if (rx_buffer->skb) { 5575 struct sk_buff *skb = rx_buffer->skb; 5576 if (IXGBE_CB(skb)->page_released) 5577 dma_unmap_page_attrs(rx_ring->dev, 5578 IXGBE_CB(skb)->dma, 5579 ixgbe_rx_pg_size(rx_ring), 5580 DMA_FROM_DEVICE, 5581 IXGBE_RX_DMA_ATTR); 5582 dev_kfree_skb(skb); 5583 } 5584 5585 /* Invalidate cache lines that may have been written to by 5586 * device so that we avoid corrupting memory. 5587 */ 5588 dma_sync_single_range_for_cpu(rx_ring->dev, 5589 rx_buffer->dma, 5590 rx_buffer->page_offset, 5591 ixgbe_rx_bufsz(rx_ring), 5592 DMA_FROM_DEVICE); 5593 5594 /* free resources associated with mapping */ 5595 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 5596 ixgbe_rx_pg_size(rx_ring), 5597 DMA_FROM_DEVICE, 5598 IXGBE_RX_DMA_ATTR); 5599 __page_frag_cache_drain(rx_buffer->page, 5600 rx_buffer->pagecnt_bias); 5601 5602 i++; 5603 rx_buffer++; 5604 if (i == rx_ring->count) { 5605 i = 0; 5606 rx_buffer = rx_ring->rx_buffer_info; 5607 } 5608 } 5609 5610 skip_free: 5611 rx_ring->next_to_alloc = 0; 5612 rx_ring->next_to_clean = 0; 5613 rx_ring->next_to_use = 0; 5614 } 5615 5616 static int ixgbe_fwd_ring_up(struct ixgbe_adapter *adapter, 5617 struct ixgbe_fwd_adapter *accel) 5618 { 5619 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 5620 int num_tc = netdev_get_num_tc(adapter->netdev); 5621 struct net_device *vdev = accel->netdev; 5622 int i, baseq, err; 5623 5624 baseq = accel->pool * adapter->num_rx_queues_per_pool; 5625 netdev_dbg(vdev, "pool %i:%i queues %i:%i\n", 5626 accel->pool, adapter->num_rx_pools, 5627 baseq, baseq + adapter->num_rx_queues_per_pool); 5628 5629 accel->rx_base_queue = baseq; 5630 accel->tx_base_queue = baseq; 5631 5632 /* record configuration for macvlan interface in vdev */ 5633 for (i = 0; i < num_tc; i++) 5634 netdev_bind_sb_channel_queue(adapter->netdev, vdev, 5635 i, rss_i, baseq + (rss_i * i)); 5636 5637 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5638 adapter->rx_ring[baseq + i]->netdev = vdev; 5639 5640 /* Guarantee all rings are updated before we update the 5641 * MAC address filter. 5642 */ 5643 wmb(); 5644 5645 /* ixgbe_add_mac_filter will return an index if it succeeds, so we 5646 * need to only treat it as an error value if it is negative. 5647 */ 5648 err = ixgbe_add_mac_filter(adapter, vdev->dev_addr, 5649 VMDQ_P(accel->pool)); 5650 if (err >= 0) 5651 return 0; 5652 5653 /* if we cannot add the MAC rule then disable the offload */ 5654 macvlan_release_l2fw_offload(vdev); 5655 5656 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5657 adapter->rx_ring[baseq + i]->netdev = NULL; 5658 5659 netdev_err(vdev, "L2FW offload disabled due to L2 filter error\n"); 5660 5661 /* unbind the queues and drop the subordinate channel config */ 5662 netdev_unbind_sb_channel(adapter->netdev, vdev); 5663 netdev_set_sb_channel(vdev, 0); 5664 5665 clear_bit(accel->pool, adapter->fwd_bitmask); 5666 kfree(accel); 5667 5668 return err; 5669 } 5670 5671 static int ixgbe_macvlan_up(struct net_device *vdev, 5672 struct netdev_nested_priv *priv) 5673 { 5674 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data; 5675 struct ixgbe_fwd_adapter *accel; 5676 5677 if (!netif_is_macvlan(vdev)) 5678 return 0; 5679 5680 accel = macvlan_accel_priv(vdev); 5681 if (!accel) 5682 return 0; 5683 5684 ixgbe_fwd_ring_up(adapter, accel); 5685 5686 return 0; 5687 } 5688 5689 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 5690 { 5691 struct netdev_nested_priv priv = { 5692 .data = (void *)adapter, 5693 }; 5694 5695 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5696 ixgbe_macvlan_up, &priv); 5697 } 5698 5699 static void ixgbe_configure(struct ixgbe_adapter *adapter) 5700 { 5701 struct ixgbe_hw *hw = &adapter->hw; 5702 5703 ixgbe_configure_pb(adapter); 5704 #ifdef CONFIG_IXGBE_DCB 5705 ixgbe_configure_dcb(adapter); 5706 #endif 5707 /* 5708 * We must restore virtualization before VLANs or else 5709 * the VLVF registers will not be populated 5710 */ 5711 ixgbe_configure_virtualization(adapter); 5712 5713 ixgbe_set_rx_mode(adapter->netdev); 5714 ixgbe_restore_vlan(adapter); 5715 ixgbe_ipsec_restore(adapter); 5716 5717 switch (hw->mac.type) { 5718 case ixgbe_mac_82599EB: 5719 case ixgbe_mac_X540: 5720 hw->mac.ops.disable_rx_buff(hw); 5721 break; 5722 default: 5723 break; 5724 } 5725 5726 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 5727 ixgbe_init_fdir_signature_82599(&adapter->hw, 5728 adapter->fdir_pballoc); 5729 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 5730 ixgbe_init_fdir_perfect_82599(&adapter->hw, 5731 adapter->fdir_pballoc); 5732 ixgbe_fdir_filter_restore(adapter); 5733 } 5734 5735 switch (hw->mac.type) { 5736 case ixgbe_mac_82599EB: 5737 case ixgbe_mac_X540: 5738 hw->mac.ops.enable_rx_buff(hw); 5739 break; 5740 default: 5741 break; 5742 } 5743 5744 #ifdef CONFIG_IXGBE_DCA 5745 /* configure DCA */ 5746 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) 5747 ixgbe_setup_dca(adapter); 5748 #endif /* CONFIG_IXGBE_DCA */ 5749 5750 #ifdef IXGBE_FCOE 5751 /* configure FCoE L2 filters, redirection table, and Rx control */ 5752 ixgbe_configure_fcoe(adapter); 5753 5754 #endif /* IXGBE_FCOE */ 5755 ixgbe_configure_tx(adapter); 5756 ixgbe_configure_rx(adapter); 5757 ixgbe_configure_dfwd(adapter); 5758 } 5759 5760 /** 5761 * ixgbe_enable_link_status_events - enable link status events 5762 * @adapter: pointer to the adapter structure 5763 * @mask: event mask to be set 5764 * 5765 * Enables link status events by invoking ixgbe_configure_lse() 5766 * 5767 * Return: the exit code of the operation. 5768 */ 5769 static int ixgbe_enable_link_status_events(struct ixgbe_adapter *adapter, 5770 u16 mask) 5771 { 5772 int err; 5773 5774 err = ixgbe_configure_lse(&adapter->hw, true, mask); 5775 if (err) 5776 return err; 5777 5778 adapter->lse_mask = mask; 5779 return 0; 5780 } 5781 5782 /** 5783 * ixgbe_disable_link_status_events - disable link status events 5784 * @adapter: pointer to the adapter structure 5785 * 5786 * Disables link status events by invoking ixgbe_configure_lse() 5787 * 5788 * Return: the exit code of the operation. 5789 */ 5790 static int ixgbe_disable_link_status_events(struct ixgbe_adapter *adapter) 5791 { 5792 int err; 5793 5794 err = ixgbe_configure_lse(&adapter->hw, false, adapter->lse_mask); 5795 if (err) 5796 return err; 5797 5798 adapter->lse_mask = 0; 5799 return 0; 5800 } 5801 5802 /** 5803 * ixgbe_sfp_link_config - set up SFP+ link 5804 * @adapter: pointer to private adapter struct 5805 **/ 5806 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 5807 { 5808 /* 5809 * We are assuming the worst case scenario here, and that 5810 * is that an SFP was inserted/removed after the reset 5811 * but before SFP detection was enabled. As such the best 5812 * solution is to just start searching as soon as we start 5813 */ 5814 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 5815 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 5816 5817 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 5818 adapter->sfp_poll_time = 0; 5819 } 5820 5821 /** 5822 * ixgbe_non_sfp_link_config - set up non-SFP+ link 5823 * @hw: pointer to private hardware struct 5824 * 5825 * Configure non-SFP link. 5826 * 5827 * Return: 0 on success, negative on failure 5828 **/ 5829 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 5830 { 5831 struct ixgbe_adapter *adapter = container_of(hw, struct ixgbe_adapter, 5832 hw); 5833 u16 mask = ~((u16)(IXGBE_ACI_LINK_EVENT_UPDOWN | 5834 IXGBE_ACI_LINK_EVENT_MEDIA_NA | 5835 IXGBE_ACI_LINK_EVENT_MODULE_QUAL_FAIL | 5836 IXGBE_ACI_LINK_EVENT_PHY_FW_LOAD_FAIL)); 5837 bool autoneg, link_up = false; 5838 int ret = -EIO; 5839 u32 speed; 5840 5841 if (hw->mac.ops.check_link) 5842 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 5843 5844 if (ret) 5845 return ret; 5846 5847 speed = hw->phy.autoneg_advertised; 5848 if (!speed && hw->mac.ops.get_link_capabilities) { 5849 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 5850 &autoneg); 5851 /* remove NBASE-T speeds from default autonegotiation 5852 * to accommodate broken network switches in the field 5853 * which cannot cope with advertised NBASE-T speeds 5854 */ 5855 speed &= ~(IXGBE_LINK_SPEED_5GB_FULL | 5856 IXGBE_LINK_SPEED_2_5GB_FULL); 5857 } 5858 5859 if (ret) 5860 return ret; 5861 5862 if (hw->mac.ops.setup_link) { 5863 if (adapter->hw.mac.type == ixgbe_mac_e610) { 5864 ret = ixgbe_enable_link_status_events(adapter, mask); 5865 if (ret) 5866 return ret; 5867 } 5868 ret = hw->mac.ops.setup_link(hw, speed, link_up); 5869 } 5870 5871 return ret; 5872 } 5873 5874 /** 5875 * ixgbe_check_media_subtask - check for media 5876 * @adapter: pointer to adapter structure 5877 * 5878 * If media is available then initialize PHY user configuration. Configure the 5879 * PHY if the interface is up. 5880 */ 5881 static void ixgbe_check_media_subtask(struct ixgbe_adapter *adapter) 5882 { 5883 struct ixgbe_hw *hw = &adapter->hw; 5884 5885 /* No need to check for media if it's already present */ 5886 if (!(adapter->flags2 & IXGBE_FLAG2_NO_MEDIA)) 5887 return; 5888 5889 /* Refresh link info and check if media is present */ 5890 if (ixgbe_update_link_info(hw)) 5891 return; 5892 5893 ixgbe_check_link_cfg_err(adapter, hw->link.link_info.link_cfg_err); 5894 5895 if (hw->link.link_info.link_info & IXGBE_ACI_MEDIA_AVAILABLE) { 5896 /* PHY settings are reset on media insertion, reconfigure 5897 * PHY to preserve settings. 5898 */ 5899 if (!(ixgbe_non_sfp_link_config(&adapter->hw))) 5900 adapter->flags2 &= ~IXGBE_FLAG2_NO_MEDIA; 5901 5902 /* A Link Status Event will be generated; the event handler 5903 * will complete bringing the interface up 5904 */ 5905 } 5906 } 5907 5908 /** 5909 * ixgbe_clear_vf_stats_counters - Clear out VF stats after reset 5910 * @adapter: board private structure 5911 * 5912 * On a reset we need to clear out the VF stats or accounting gets 5913 * messed up because they're not clear on read. 5914 **/ 5915 static void ixgbe_clear_vf_stats_counters(struct ixgbe_adapter *adapter) 5916 { 5917 struct ixgbe_hw *hw = &adapter->hw; 5918 int i; 5919 5920 for (i = 0; i < adapter->num_vfs; i++) { 5921 adapter->vfinfo[i].last_vfstats.gprc = 5922 IXGBE_READ_REG(hw, IXGBE_PVFGPRC(i)); 5923 adapter->vfinfo[i].saved_rst_vfstats.gprc += 5924 adapter->vfinfo[i].vfstats.gprc; 5925 adapter->vfinfo[i].vfstats.gprc = 0; 5926 adapter->vfinfo[i].last_vfstats.gptc = 5927 IXGBE_READ_REG(hw, IXGBE_PVFGPTC(i)); 5928 adapter->vfinfo[i].saved_rst_vfstats.gptc += 5929 adapter->vfinfo[i].vfstats.gptc; 5930 adapter->vfinfo[i].vfstats.gptc = 0; 5931 adapter->vfinfo[i].last_vfstats.gorc = 5932 IXGBE_READ_REG(hw, IXGBE_PVFGORC_LSB(i)); 5933 adapter->vfinfo[i].saved_rst_vfstats.gorc += 5934 adapter->vfinfo[i].vfstats.gorc; 5935 adapter->vfinfo[i].vfstats.gorc = 0; 5936 adapter->vfinfo[i].last_vfstats.gotc = 5937 IXGBE_READ_REG(hw, IXGBE_PVFGOTC_LSB(i)); 5938 adapter->vfinfo[i].saved_rst_vfstats.gotc += 5939 adapter->vfinfo[i].vfstats.gotc; 5940 adapter->vfinfo[i].vfstats.gotc = 0; 5941 adapter->vfinfo[i].last_vfstats.mprc = 5942 IXGBE_READ_REG(hw, IXGBE_PVFMPRC(i)); 5943 adapter->vfinfo[i].saved_rst_vfstats.mprc += 5944 adapter->vfinfo[i].vfstats.mprc; 5945 adapter->vfinfo[i].vfstats.mprc = 0; 5946 } 5947 } 5948 5949 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 5950 { 5951 struct ixgbe_hw *hw = &adapter->hw; 5952 u32 gpie = 0; 5953 5954 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 5955 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5956 IXGBE_GPIE_OCD; 5957 gpie |= IXGBE_GPIE_EIAME; 5958 /* 5959 * use EIAM to auto-mask when MSI-X interrupt is asserted 5960 * this saves a register write for every interrupt 5961 */ 5962 switch (hw->mac.type) { 5963 case ixgbe_mac_82598EB: 5964 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5965 break; 5966 case ixgbe_mac_82599EB: 5967 case ixgbe_mac_X540: 5968 case ixgbe_mac_X550: 5969 case ixgbe_mac_X550EM_x: 5970 case ixgbe_mac_x550em_a: 5971 case ixgbe_mac_e610: 5972 default: 5973 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5974 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5975 break; 5976 } 5977 } else { 5978 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 5979 * specifically only auto mask tx and rx interrupts */ 5980 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5981 } 5982 5983 /* XXX: to interrupt immediately for EICS writes, enable this */ 5984 /* gpie |= IXGBE_GPIE_EIMEN; */ 5985 5986 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 5987 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 5988 5989 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 5990 case IXGBE_82599_VMDQ_8Q_MASK: 5991 gpie |= IXGBE_GPIE_VTMODE_16; 5992 break; 5993 case IXGBE_82599_VMDQ_4Q_MASK: 5994 gpie |= IXGBE_GPIE_VTMODE_32; 5995 break; 5996 default: 5997 gpie |= IXGBE_GPIE_VTMODE_64; 5998 break; 5999 } 6000 } 6001 6002 /* Enable Thermal over heat sensor interrupt */ 6003 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 6004 switch (adapter->hw.mac.type) { 6005 case ixgbe_mac_82599EB: 6006 gpie |= IXGBE_SDP0_GPIEN_8259X; 6007 break; 6008 default: 6009 break; 6010 } 6011 } 6012 6013 /* Enable fan failure interrupt */ 6014 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 6015 gpie |= IXGBE_SDP1_GPIEN(hw); 6016 6017 switch (hw->mac.type) { 6018 case ixgbe_mac_82599EB: 6019 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; 6020 break; 6021 case ixgbe_mac_X550EM_x: 6022 case ixgbe_mac_x550em_a: 6023 gpie |= IXGBE_SDP0_GPIEN_X540; 6024 break; 6025 default: 6026 break; 6027 } 6028 6029 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 6030 } 6031 6032 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 6033 { 6034 struct ixgbe_hw *hw = &adapter->hw; 6035 int err; 6036 u32 ctrl_ext; 6037 6038 ixgbe_get_hw_control(adapter); 6039 ixgbe_setup_gpie(adapter); 6040 6041 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 6042 ixgbe_configure_msix(adapter); 6043 else 6044 ixgbe_configure_msi_and_legacy(adapter); 6045 6046 /* enable the optics for 82599 SFP+ fiber */ 6047 if (hw->mac.ops.enable_tx_laser) 6048 hw->mac.ops.enable_tx_laser(hw); 6049 6050 if (hw->phy.ops.set_phy_power) 6051 hw->phy.ops.set_phy_power(hw, true); 6052 6053 smp_mb__before_atomic(); 6054 clear_bit(__IXGBE_DOWN, &adapter->state); 6055 ixgbe_napi_enable_all(adapter); 6056 6057 if (ixgbe_is_sfp(hw)) { 6058 ixgbe_sfp_link_config(adapter); 6059 } else { 6060 err = ixgbe_non_sfp_link_config(hw); 6061 if (err) 6062 e_err(probe, "link_config FAILED %d\n", err); 6063 } 6064 6065 /* clear any pending interrupts, may auto mask */ 6066 IXGBE_READ_REG(hw, IXGBE_EICR); 6067 ixgbe_irq_enable(adapter, true, true); 6068 6069 /* 6070 * If this adapter has a fan, check to see if we had a failure 6071 * before we enabled the interrupt. 6072 */ 6073 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 6074 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 6075 if (esdp & IXGBE_ESDP_SDP1) 6076 e_crit(drv, "Fan has stopped, replace the adapter\n"); 6077 } 6078 6079 /* bring the link up in the watchdog, this could race with our first 6080 * link up interrupt but shouldn't be a problem */ 6081 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 6082 adapter->link_check_timeout = jiffies; 6083 mod_timer(&adapter->service_timer, jiffies); 6084 6085 ixgbe_clear_vf_stats_counters(adapter); 6086 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 6087 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 6088 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 6089 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 6090 6091 /* update setting rx tx for all active vfs */ 6092 ixgbe_set_all_vfs(adapter); 6093 } 6094 6095 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 6096 { 6097 /* put off any impending NetWatchDogTimeout */ 6098 netif_trans_update(adapter->netdev); 6099 6100 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 6101 usleep_range(1000, 2000); 6102 if (adapter->hw.phy.type == ixgbe_phy_fw) 6103 ixgbe_watchdog_link_is_down(adapter); 6104 ixgbe_down(adapter); 6105 /* 6106 * If SR-IOV enabled then wait a bit before bringing the adapter 6107 * back up to give the VFs time to respond to the reset. The 6108 * two second wait is based upon the watchdog timer cycle in 6109 * the VF driver. 6110 */ 6111 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 6112 msleep(2000); 6113 ixgbe_up(adapter); 6114 clear_bit(__IXGBE_RESETTING, &adapter->state); 6115 } 6116 6117 void ixgbe_up(struct ixgbe_adapter *adapter) 6118 { 6119 /* hardware has been reset, we need to reload some things */ 6120 ixgbe_configure(adapter); 6121 6122 ixgbe_up_complete(adapter); 6123 } 6124 6125 static unsigned long ixgbe_get_completion_timeout(struct ixgbe_adapter *adapter) 6126 { 6127 u16 devctl2; 6128 6129 pcie_capability_read_word(adapter->pdev, PCI_EXP_DEVCTL2, &devctl2); 6130 6131 switch (devctl2 & IXGBE_PCIDEVCTRL2_TIMEO_MASK) { 6132 case IXGBE_PCIDEVCTRL2_17_34s: 6133 case IXGBE_PCIDEVCTRL2_4_8s: 6134 /* For now we cap the upper limit on delay to 2 seconds 6135 * as we end up going up to 34 seconds of delay in worst 6136 * case timeout value. 6137 */ 6138 case IXGBE_PCIDEVCTRL2_1_2s: 6139 return 2000000ul; /* 2.0 s */ 6140 case IXGBE_PCIDEVCTRL2_260_520ms: 6141 return 520000ul; /* 520 ms */ 6142 case IXGBE_PCIDEVCTRL2_65_130ms: 6143 return 130000ul; /* 130 ms */ 6144 case IXGBE_PCIDEVCTRL2_16_32ms: 6145 return 32000ul; /* 32 ms */ 6146 case IXGBE_PCIDEVCTRL2_1_2ms: 6147 return 2000ul; /* 2 ms */ 6148 case IXGBE_PCIDEVCTRL2_50_100us: 6149 return 100ul; /* 100 us */ 6150 case IXGBE_PCIDEVCTRL2_16_32ms_def: 6151 return 32000ul; /* 32 ms */ 6152 default: 6153 break; 6154 } 6155 6156 /* We shouldn't need to hit this path, but just in case default as 6157 * though completion timeout is not supported and support 32ms. 6158 */ 6159 return 32000ul; 6160 } 6161 6162 void ixgbe_disable_rx(struct ixgbe_adapter *adapter) 6163 { 6164 unsigned long wait_delay, delay_interval; 6165 struct ixgbe_hw *hw = &adapter->hw; 6166 int i, wait_loop; 6167 u32 rxdctl; 6168 6169 /* disable receives */ 6170 hw->mac.ops.disable_rx(hw); 6171 6172 if (ixgbe_removed(hw->hw_addr)) 6173 return; 6174 6175 /* disable all enabled Rx queues */ 6176 for (i = 0; i < adapter->num_rx_queues; i++) { 6177 struct ixgbe_ring *ring = adapter->rx_ring[i]; 6178 u8 reg_idx = ring->reg_idx; 6179 6180 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 6181 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 6182 rxdctl |= IXGBE_RXDCTL_SWFLSH; 6183 6184 /* write value back with RXDCTL.ENABLE bit cleared */ 6185 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 6186 } 6187 6188 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 6189 if (hw->mac.type == ixgbe_mac_82598EB && 6190 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 6191 return; 6192 6193 /* Determine our minimum delay interval. We will increase this value 6194 * with each subsequent test. This way if the device returns quickly 6195 * we should spend as little time as possible waiting, however as 6196 * the time increases we will wait for larger periods of time. 6197 * 6198 * The trick here is that we increase the interval using the 6199 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 6200 * of that wait is that it totals up to 100x whatever interval we 6201 * choose. Since our minimum wait is 100us we can just divide the 6202 * total timeout by 100 to get our minimum delay interval. 6203 */ 6204 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 6205 6206 wait_loop = IXGBE_MAX_RX_DESC_POLL; 6207 wait_delay = delay_interval; 6208 6209 while (wait_loop--) { 6210 usleep_range(wait_delay, wait_delay + 10); 6211 wait_delay += delay_interval * 2; 6212 rxdctl = 0; 6213 6214 /* OR together the reading of all the active RXDCTL registers, 6215 * and then test the result. We need the disable to complete 6216 * before we start freeing the memory and invalidating the 6217 * DMA mappings. 6218 */ 6219 for (i = 0; i < adapter->num_rx_queues; i++) { 6220 struct ixgbe_ring *ring = adapter->rx_ring[i]; 6221 u8 reg_idx = ring->reg_idx; 6222 6223 rxdctl |= IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 6224 } 6225 6226 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 6227 return; 6228 } 6229 6230 e_err(drv, 6231 "RXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 6232 } 6233 6234 void ixgbe_disable_tx(struct ixgbe_adapter *adapter) 6235 { 6236 unsigned long wait_delay, delay_interval; 6237 struct ixgbe_hw *hw = &adapter->hw; 6238 int i, wait_loop; 6239 u32 txdctl; 6240 6241 if (ixgbe_removed(hw->hw_addr)) 6242 return; 6243 6244 /* disable all enabled Tx queues */ 6245 for (i = 0; i < adapter->num_tx_queues; i++) { 6246 struct ixgbe_ring *ring = adapter->tx_ring[i]; 6247 u8 reg_idx = ring->reg_idx; 6248 6249 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 6250 } 6251 6252 /* disable all enabled XDP Tx queues */ 6253 for (i = 0; i < adapter->num_xdp_queues; i++) { 6254 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 6255 u8 reg_idx = ring->reg_idx; 6256 6257 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 6258 } 6259 6260 /* If the link is not up there shouldn't be much in the way of 6261 * pending transactions. Those that are left will be flushed out 6262 * when the reset logic goes through the flush sequence to clean out 6263 * the pending Tx transactions. 6264 */ 6265 if (!(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 6266 goto dma_engine_disable; 6267 6268 /* Determine our minimum delay interval. We will increase this value 6269 * with each subsequent test. This way if the device returns quickly 6270 * we should spend as little time as possible waiting, however as 6271 * the time increases we will wait for larger periods of time. 6272 * 6273 * The trick here is that we increase the interval using the 6274 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 6275 * of that wait is that it totals up to 100x whatever interval we 6276 * choose. Since our minimum wait is 100us we can just divide the 6277 * total timeout by 100 to get our minimum delay interval. 6278 */ 6279 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 6280 6281 wait_loop = IXGBE_MAX_RX_DESC_POLL; 6282 wait_delay = delay_interval; 6283 6284 while (wait_loop--) { 6285 usleep_range(wait_delay, wait_delay + 10); 6286 wait_delay += delay_interval * 2; 6287 txdctl = 0; 6288 6289 /* OR together the reading of all the active TXDCTL registers, 6290 * and then test the result. We need the disable to complete 6291 * before we start freeing the memory and invalidating the 6292 * DMA mappings. 6293 */ 6294 for (i = 0; i < adapter->num_tx_queues; i++) { 6295 struct ixgbe_ring *ring = adapter->tx_ring[i]; 6296 u8 reg_idx = ring->reg_idx; 6297 6298 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 6299 } 6300 for (i = 0; i < adapter->num_xdp_queues; i++) { 6301 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 6302 u8 reg_idx = ring->reg_idx; 6303 6304 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 6305 } 6306 6307 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 6308 goto dma_engine_disable; 6309 } 6310 6311 e_err(drv, 6312 "TXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 6313 6314 dma_engine_disable: 6315 /* Disable the Tx DMA engine on 82599 and later MAC */ 6316 switch (hw->mac.type) { 6317 case ixgbe_mac_82599EB: 6318 case ixgbe_mac_X540: 6319 case ixgbe_mac_X550: 6320 case ixgbe_mac_X550EM_x: 6321 case ixgbe_mac_x550em_a: 6322 case ixgbe_mac_e610: 6323 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 6324 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 6325 ~IXGBE_DMATXCTL_TE)); 6326 fallthrough; 6327 default: 6328 break; 6329 } 6330 } 6331 6332 void ixgbe_reset(struct ixgbe_adapter *adapter) 6333 { 6334 struct ixgbe_hw *hw = &adapter->hw; 6335 struct net_device *netdev = adapter->netdev; 6336 int err; 6337 6338 if (ixgbe_removed(hw->hw_addr)) 6339 return; 6340 /* lock SFP init bit to prevent race conditions with the watchdog */ 6341 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 6342 usleep_range(1000, 2000); 6343 6344 /* clear all SFP and link config related flags while holding SFP_INIT */ 6345 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 6346 IXGBE_FLAG2_SFP_NEEDS_RESET); 6347 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 6348 6349 err = hw->mac.ops.init_hw(hw); 6350 switch (err) { 6351 case 0: 6352 case -ENOENT: 6353 case -EOPNOTSUPP: 6354 break; 6355 case -EALREADY: 6356 e_dev_err("primary disable timed out\n"); 6357 break; 6358 case -EACCES: 6359 /* We are running on a pre-production device, log a warning */ 6360 e_dev_warn("This device is a pre-production adapter/LOM. " 6361 "Please be aware there may be issues associated with " 6362 "your hardware. If you are experiencing problems " 6363 "please contact your Intel or hardware " 6364 "representative who provided you with this " 6365 "hardware.\n"); 6366 break; 6367 default: 6368 e_dev_err("Hardware Error: %d\n", err); 6369 } 6370 6371 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 6372 6373 /* flush entries out of MAC table */ 6374 ixgbe_flush_sw_mac_table(adapter); 6375 __dev_uc_unsync(netdev, NULL); 6376 6377 /* do not flush user set addresses */ 6378 ixgbe_mac_set_default_filter(adapter); 6379 6380 /* update SAN MAC vmdq pool selection */ 6381 if (hw->mac.san_mac_rar_index) 6382 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 6383 6384 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 6385 ixgbe_ptp_reset(adapter); 6386 6387 if (hw->phy.ops.set_phy_power) { 6388 if (!netif_running(adapter->netdev) && !adapter->wol) 6389 hw->phy.ops.set_phy_power(hw, false); 6390 else 6391 hw->phy.ops.set_phy_power(hw, true); 6392 } 6393 } 6394 6395 /** 6396 * ixgbe_clean_tx_ring - Free Tx Buffers 6397 * @tx_ring: ring to be cleaned 6398 **/ 6399 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 6400 { 6401 u16 i = tx_ring->next_to_clean; 6402 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 6403 6404 if (tx_ring->xsk_pool) { 6405 ixgbe_xsk_clean_tx_ring(tx_ring); 6406 goto out; 6407 } 6408 6409 while (i != tx_ring->next_to_use) { 6410 union ixgbe_adv_tx_desc *eop_desc, *tx_desc; 6411 6412 /* Free all the Tx ring sk_buffs */ 6413 if (ring_is_xdp(tx_ring)) 6414 xdp_return_frame(tx_buffer->xdpf); 6415 else 6416 dev_kfree_skb_any(tx_buffer->skb); 6417 6418 /* unmap skb header data */ 6419 dma_unmap_single(tx_ring->dev, 6420 dma_unmap_addr(tx_buffer, dma), 6421 dma_unmap_len(tx_buffer, len), 6422 DMA_TO_DEVICE); 6423 6424 /* check for eop_desc to determine the end of the packet */ 6425 eop_desc = tx_buffer->next_to_watch; 6426 tx_desc = IXGBE_TX_DESC(tx_ring, i); 6427 6428 /* unmap remaining buffers */ 6429 while (tx_desc != eop_desc) { 6430 tx_buffer++; 6431 tx_desc++; 6432 i++; 6433 if (unlikely(i == tx_ring->count)) { 6434 i = 0; 6435 tx_buffer = tx_ring->tx_buffer_info; 6436 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 6437 } 6438 6439 /* unmap any remaining paged data */ 6440 if (dma_unmap_len(tx_buffer, len)) 6441 dma_unmap_page(tx_ring->dev, 6442 dma_unmap_addr(tx_buffer, dma), 6443 dma_unmap_len(tx_buffer, len), 6444 DMA_TO_DEVICE); 6445 } 6446 6447 /* move us one more past the eop_desc for start of next pkt */ 6448 tx_buffer++; 6449 i++; 6450 if (unlikely(i == tx_ring->count)) { 6451 i = 0; 6452 tx_buffer = tx_ring->tx_buffer_info; 6453 } 6454 } 6455 6456 /* reset BQL for queue */ 6457 if (!ring_is_xdp(tx_ring)) 6458 netdev_tx_reset_queue(txring_txq(tx_ring)); 6459 6460 out: 6461 /* reset next_to_use and next_to_clean */ 6462 tx_ring->next_to_use = 0; 6463 tx_ring->next_to_clean = 0; 6464 } 6465 6466 /** 6467 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 6468 * @adapter: board private structure 6469 **/ 6470 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 6471 { 6472 int i; 6473 6474 for (i = 0; i < adapter->num_rx_queues; i++) 6475 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 6476 } 6477 6478 /** 6479 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 6480 * @adapter: board private structure 6481 **/ 6482 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 6483 { 6484 int i; 6485 6486 for (i = 0; i < adapter->num_tx_queues; i++) 6487 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 6488 for (i = 0; i < adapter->num_xdp_queues; i++) 6489 ixgbe_clean_tx_ring(adapter->xdp_ring[i]); 6490 } 6491 6492 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 6493 { 6494 struct hlist_node *node2; 6495 struct ixgbe_fdir_filter *filter; 6496 6497 spin_lock(&adapter->fdir_perfect_lock); 6498 6499 hlist_for_each_entry_safe(filter, node2, 6500 &adapter->fdir_filter_list, fdir_node) { 6501 hlist_del(&filter->fdir_node); 6502 kfree(filter); 6503 } 6504 adapter->fdir_filter_count = 0; 6505 6506 spin_unlock(&adapter->fdir_perfect_lock); 6507 } 6508 6509 void ixgbe_down(struct ixgbe_adapter *adapter) 6510 { 6511 struct net_device *netdev = adapter->netdev; 6512 struct ixgbe_hw *hw = &adapter->hw; 6513 int i; 6514 6515 /* signal that we are down to the interrupt handler */ 6516 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 6517 return; /* do nothing if already down */ 6518 6519 /* Shut off incoming Tx traffic */ 6520 netif_tx_stop_all_queues(netdev); 6521 6522 /* call carrier off first to avoid false dev_watchdog timeouts */ 6523 netif_carrier_off(netdev); 6524 netif_tx_disable(netdev); 6525 6526 /* Disable Rx */ 6527 ixgbe_disable_rx(adapter); 6528 6529 /* synchronize_rcu() needed for pending XDP buffers to drain */ 6530 if (adapter->xdp_ring[0]) 6531 synchronize_rcu(); 6532 6533 ixgbe_irq_disable(adapter); 6534 6535 ixgbe_napi_disable_all(adapter); 6536 6537 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 6538 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 6539 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 6540 6541 timer_delete_sync(&adapter->service_timer); 6542 6543 if (adapter->num_vfs) { 6544 /* Clear EITR Select mapping */ 6545 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 6546 6547 /* Mark all the VFs as inactive */ 6548 for (i = 0 ; i < adapter->num_vfs; i++) 6549 adapter->vfinfo[i].clear_to_send = false; 6550 6551 /* update setting rx tx for all active vfs */ 6552 ixgbe_set_all_vfs(adapter); 6553 } 6554 6555 /* disable transmits in the hardware now that interrupts are off */ 6556 ixgbe_disable_tx(adapter); 6557 6558 if (!pci_channel_offline(adapter->pdev)) 6559 ixgbe_reset(adapter); 6560 6561 /* power down the optics for 82599 SFP+ fiber */ 6562 if (hw->mac.ops.disable_tx_laser) 6563 hw->mac.ops.disable_tx_laser(hw); 6564 6565 ixgbe_clean_all_tx_rings(adapter); 6566 ixgbe_clean_all_rx_rings(adapter); 6567 if (adapter->hw.mac.type == ixgbe_mac_e610) 6568 ixgbe_disable_link_status_events(adapter); 6569 } 6570 6571 /** 6572 * ixgbe_set_eee_capable - helper function to determine EEE support on X550 6573 * @adapter: board private structure 6574 */ 6575 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter) 6576 { 6577 struct ixgbe_hw *hw = &adapter->hw; 6578 6579 switch (hw->device_id) { 6580 case IXGBE_DEV_ID_X550EM_A_1G_T: 6581 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6582 if (!hw->phy.eee_speeds_supported) 6583 break; 6584 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE; 6585 if (!hw->phy.eee_speeds_advertised) 6586 break; 6587 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 6588 break; 6589 default: 6590 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE; 6591 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 6592 break; 6593 } 6594 } 6595 6596 /** 6597 * ixgbe_tx_timeout - Respond to a Tx Hang 6598 * @netdev: network interface device structure 6599 * @txqueue: queue number that timed out 6600 **/ 6601 static void ixgbe_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6602 { 6603 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6604 6605 /* Do the reset outside of interrupt context */ 6606 ixgbe_tx_timeout_reset(adapter); 6607 } 6608 6609 #ifdef CONFIG_IXGBE_DCB 6610 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) 6611 { 6612 struct ixgbe_hw *hw = &adapter->hw; 6613 struct tc_configuration *tc; 6614 int j; 6615 6616 switch (hw->mac.type) { 6617 case ixgbe_mac_82598EB: 6618 case ixgbe_mac_82599EB: 6619 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 6620 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 6621 break; 6622 case ixgbe_mac_X540: 6623 case ixgbe_mac_X550: 6624 case ixgbe_mac_e610: 6625 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 6626 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 6627 break; 6628 case ixgbe_mac_X550EM_x: 6629 case ixgbe_mac_x550em_a: 6630 default: 6631 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; 6632 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; 6633 break; 6634 } 6635 6636 /* Configure DCB traffic classes */ 6637 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 6638 tc = &adapter->dcb_cfg.tc_config[j]; 6639 tc->path[DCB_TX_CONFIG].bwg_id = 0; 6640 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 6641 tc->path[DCB_RX_CONFIG].bwg_id = 0; 6642 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 6643 tc->dcb_pfc = pfc_disabled; 6644 } 6645 6646 /* Initialize default user to priority mapping, UPx->TC0 */ 6647 tc = &adapter->dcb_cfg.tc_config[0]; 6648 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 6649 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 6650 6651 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 6652 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 6653 adapter->dcb_cfg.pfc_mode_enable = false; 6654 adapter->dcb_set_bitmap = 0x00; 6655 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 6656 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 6657 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 6658 sizeof(adapter->temp_dcb_cfg)); 6659 } 6660 #endif 6661 6662 /** 6663 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 6664 * @adapter: board private structure to initialize 6665 * @ii: pointer to ixgbe_info for device 6666 * 6667 * ixgbe_sw_init initializes the Adapter private data structure. 6668 * Fields are initialized based on PCI device information and 6669 * OS network device settings (MTU size). 6670 **/ 6671 static int ixgbe_sw_init(struct ixgbe_adapter *adapter, 6672 const struct ixgbe_info *ii) 6673 { 6674 struct ixgbe_hw *hw = &adapter->hw; 6675 struct pci_dev *pdev = adapter->pdev; 6676 unsigned int rss, fdir; 6677 u32 fwsm; 6678 int i; 6679 6680 /* PCI config space info */ 6681 6682 hw->vendor_id = pdev->vendor; 6683 hw->device_id = pdev->device; 6684 hw->revision_id = pdev->revision; 6685 hw->subsystem_vendor_id = pdev->subsystem_vendor; 6686 hw->subsystem_device_id = pdev->subsystem_device; 6687 6688 hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME; 6689 6690 /* get_invariants needs the device IDs */ 6691 ii->get_invariants(hw); 6692 6693 /* Set common capability flags and settings */ 6694 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 6695 adapter->ring_feature[RING_F_RSS].limit = rss; 6696 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 6697 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 6698 adapter->atr_sample_rate = 20; 6699 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 6700 adapter->ring_feature[RING_F_FDIR].limit = fdir; 6701 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 6702 adapter->ring_feature[RING_F_VMDQ].limit = 1; 6703 #ifdef CONFIG_IXGBE_DCA 6704 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 6705 #endif 6706 #ifdef CONFIG_IXGBE_DCB 6707 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; 6708 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 6709 #endif 6710 #ifdef IXGBE_FCOE 6711 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 6712 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6713 #ifdef CONFIG_IXGBE_DCB 6714 /* Default traffic class to use for FCoE */ 6715 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 6716 #endif /* CONFIG_IXGBE_DCB */ 6717 #endif /* IXGBE_FCOE */ 6718 6719 /* initialize static ixgbe jump table entries */ 6720 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]), 6721 GFP_KERNEL); 6722 if (!adapter->jump_tables[0]) 6723 return -ENOMEM; 6724 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; 6725 6726 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) 6727 adapter->jump_tables[i] = NULL; 6728 6729 adapter->mac_table = kcalloc(hw->mac.num_rar_entries, 6730 sizeof(struct ixgbe_mac_addr), 6731 GFP_KERNEL); 6732 if (!adapter->mac_table) 6733 return -ENOMEM; 6734 6735 if (ixgbe_init_rss_key(adapter)) 6736 return -ENOMEM; 6737 6738 adapter->af_xdp_zc_qps = bitmap_zalloc(IXGBE_MAX_XDP_QS, GFP_KERNEL); 6739 if (!adapter->af_xdp_zc_qps) 6740 return -ENOMEM; 6741 6742 /* Set MAC specific capability flags and exceptions */ 6743 switch (hw->mac.type) { 6744 case ixgbe_mac_82598EB: 6745 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 6746 6747 if (hw->device_id == IXGBE_DEV_ID_82598AT) 6748 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 6749 6750 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 6751 adapter->ring_feature[RING_F_FDIR].limit = 0; 6752 adapter->atr_sample_rate = 0; 6753 adapter->fdir_pballoc = 0; 6754 #ifdef IXGBE_FCOE 6755 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6756 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6757 #ifdef CONFIG_IXGBE_DCB 6758 adapter->fcoe.up = 0; 6759 #endif /* IXGBE_DCB */ 6760 #endif /* IXGBE_FCOE */ 6761 break; 6762 case ixgbe_mac_82599EB: 6763 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 6764 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6765 break; 6766 case ixgbe_mac_X540: 6767 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 6768 if (fwsm & IXGBE_FWSM_TS_ENABLED) 6769 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6770 break; 6771 case ixgbe_mac_x550em_a: 6772 switch (hw->device_id) { 6773 case IXGBE_DEV_ID_X550EM_A_1G_T: 6774 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6775 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6776 break; 6777 default: 6778 break; 6779 } 6780 fallthrough; 6781 case ixgbe_mac_X550EM_x: 6782 #ifdef CONFIG_IXGBE_DCB 6783 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; 6784 #endif 6785 #ifdef IXGBE_FCOE 6786 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6787 #ifdef CONFIG_IXGBE_DCB 6788 adapter->fcoe.up = 0; 6789 #endif /* IXGBE_DCB */ 6790 #endif /* IXGBE_FCOE */ 6791 fallthrough; 6792 case ixgbe_mac_X550: 6793 if (hw->mac.type == ixgbe_mac_X550) 6794 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6795 #ifdef CONFIG_IXGBE_DCA 6796 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 6797 #endif 6798 break; 6799 default: 6800 break; 6801 } 6802 6803 #ifdef IXGBE_FCOE 6804 /* FCoE support exists, always init the FCoE lock */ 6805 spin_lock_init(&adapter->fcoe.lock); 6806 6807 #endif 6808 /* n-tuple support exists, always init our spinlock */ 6809 spin_lock_init(&adapter->fdir_perfect_lock); 6810 6811 /* init spinlock to avoid concurrency of VF resources */ 6812 spin_lock_init(&adapter->vfs_lock); 6813 6814 #ifdef CONFIG_IXGBE_DCB 6815 ixgbe_init_dcb(adapter); 6816 #endif 6817 ixgbe_init_ipsec_offload(adapter); 6818 6819 /* default flow control settings */ 6820 hw->fc.requested_mode = ixgbe_fc_full; 6821 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 6822 ixgbe_pbthresh_setup(adapter); 6823 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 6824 hw->fc.send_xon = true; 6825 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 6826 6827 #ifdef CONFIG_PCI_IOV 6828 if (max_vfs > 0) 6829 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 6830 6831 /* assign number of SR-IOV VFs */ 6832 if (hw->mac.type != ixgbe_mac_82598EB) { 6833 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 6834 max_vfs = 0; 6835 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 6836 } 6837 } 6838 #endif /* CONFIG_PCI_IOV */ 6839 6840 /* enable itr by default in dynamic mode */ 6841 adapter->rx_itr_setting = 1; 6842 adapter->tx_itr_setting = 1; 6843 6844 /* set default ring sizes */ 6845 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 6846 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 6847 6848 /* set default work limits */ 6849 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 6850 6851 /* initialize eeprom parameters */ 6852 if (ixgbe_init_eeprom_params_generic(hw)) { 6853 e_dev_err("EEPROM initialization failed\n"); 6854 return -EIO; 6855 } 6856 6857 /* PF holds first pool slot */ 6858 set_bit(0, adapter->fwd_bitmask); 6859 set_bit(__IXGBE_DOWN, &adapter->state); 6860 6861 /* enable locking for XDP_TX if we have more CPUs than queues */ 6862 if (nr_cpu_ids > IXGBE_MAX_XDP_QS) 6863 static_branch_enable(&ixgbe_xdp_locking_key); 6864 6865 return 0; 6866 } 6867 6868 /** 6869 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 6870 * @tx_ring: tx descriptor ring (for a specific queue) to setup 6871 * 6872 * Return 0 on success, negative on failure 6873 **/ 6874 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 6875 { 6876 struct device *dev = tx_ring->dev; 6877 int orig_node = dev_to_node(dev); 6878 int ring_node = NUMA_NO_NODE; 6879 int size; 6880 6881 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 6882 6883 if (tx_ring->q_vector) 6884 ring_node = tx_ring->q_vector->numa_node; 6885 6886 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node); 6887 if (!tx_ring->tx_buffer_info) 6888 tx_ring->tx_buffer_info = vmalloc(size); 6889 if (!tx_ring->tx_buffer_info) 6890 goto err; 6891 6892 /* round up to nearest 4K */ 6893 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 6894 tx_ring->size = ALIGN(tx_ring->size, 4096); 6895 6896 set_dev_node(dev, ring_node); 6897 tx_ring->desc = dma_alloc_coherent(dev, 6898 tx_ring->size, 6899 &tx_ring->dma, 6900 GFP_KERNEL); 6901 set_dev_node(dev, orig_node); 6902 if (!tx_ring->desc) 6903 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 6904 &tx_ring->dma, GFP_KERNEL); 6905 if (!tx_ring->desc) 6906 goto err; 6907 6908 tx_ring->next_to_use = 0; 6909 tx_ring->next_to_clean = 0; 6910 return 0; 6911 6912 err: 6913 vfree(tx_ring->tx_buffer_info); 6914 tx_ring->tx_buffer_info = NULL; 6915 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 6916 return -ENOMEM; 6917 } 6918 6919 /** 6920 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 6921 * @adapter: board private structure 6922 * 6923 * If this function returns with an error, then it's possible one or 6924 * more of the rings is populated (while the rest are not). It is the 6925 * callers duty to clean those orphaned rings. 6926 * 6927 * Return 0 on success, negative on failure 6928 **/ 6929 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 6930 { 6931 int i, j = 0, err = 0; 6932 6933 for (i = 0; i < adapter->num_tx_queues; i++) { 6934 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 6935 if (!err) 6936 continue; 6937 6938 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 6939 goto err_setup_tx; 6940 } 6941 for (j = 0; j < adapter->num_xdp_queues; j++) { 6942 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]); 6943 if (!err) 6944 continue; 6945 6946 e_err(probe, "Allocation for Tx Queue %u failed\n", j); 6947 goto err_setup_tx; 6948 } 6949 6950 return 0; 6951 err_setup_tx: 6952 /* rewind the index freeing the rings as we go */ 6953 while (j--) 6954 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 6955 while (i--) 6956 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6957 return err; 6958 } 6959 6960 static int ixgbe_rx_napi_id(struct ixgbe_ring *rx_ring) 6961 { 6962 struct ixgbe_q_vector *q_vector = rx_ring->q_vector; 6963 6964 return q_vector ? q_vector->napi.napi_id : 0; 6965 } 6966 6967 /** 6968 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 6969 * @adapter: pointer to ixgbe_adapter 6970 * @rx_ring: rx descriptor ring (for a specific queue) to setup 6971 * 6972 * Returns 0 on success, negative on failure 6973 **/ 6974 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, 6975 struct ixgbe_ring *rx_ring) 6976 { 6977 struct device *dev = rx_ring->dev; 6978 int orig_node = dev_to_node(dev); 6979 int ring_node = NUMA_NO_NODE; 6980 int size; 6981 6982 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 6983 6984 if (rx_ring->q_vector) 6985 ring_node = rx_ring->q_vector->numa_node; 6986 6987 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node); 6988 if (!rx_ring->rx_buffer_info) 6989 rx_ring->rx_buffer_info = vmalloc(size); 6990 if (!rx_ring->rx_buffer_info) 6991 goto err; 6992 6993 /* Round up to nearest 4K */ 6994 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 6995 rx_ring->size = ALIGN(rx_ring->size, 4096); 6996 6997 set_dev_node(dev, ring_node); 6998 rx_ring->desc = dma_alloc_coherent(dev, 6999 rx_ring->size, 7000 &rx_ring->dma, 7001 GFP_KERNEL); 7002 set_dev_node(dev, orig_node); 7003 if (!rx_ring->desc) 7004 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 7005 &rx_ring->dma, GFP_KERNEL); 7006 if (!rx_ring->desc) 7007 goto err; 7008 7009 rx_ring->next_to_clean = 0; 7010 rx_ring->next_to_use = 0; 7011 7012 /* XDP RX-queue info */ 7013 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev, 7014 rx_ring->queue_index, ixgbe_rx_napi_id(rx_ring)) < 0) 7015 goto err; 7016 7017 WRITE_ONCE(rx_ring->xdp_prog, adapter->xdp_prog); 7018 7019 return 0; 7020 err: 7021 vfree(rx_ring->rx_buffer_info); 7022 rx_ring->rx_buffer_info = NULL; 7023 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 7024 return -ENOMEM; 7025 } 7026 7027 /** 7028 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 7029 * @adapter: board private structure 7030 * 7031 * If this function returns with an error, then it's possible one or 7032 * more of the rings is populated (while the rest are not). It is the 7033 * callers duty to clean those orphaned rings. 7034 * 7035 * Return 0 on success, negative on failure 7036 **/ 7037 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 7038 { 7039 int i, err = 0; 7040 7041 for (i = 0; i < adapter->num_rx_queues; i++) { 7042 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); 7043 if (!err) 7044 continue; 7045 7046 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 7047 goto err_setup_rx; 7048 } 7049 7050 #ifdef IXGBE_FCOE 7051 err = ixgbe_setup_fcoe_ddp_resources(adapter); 7052 if (!err) 7053 #endif 7054 return 0; 7055 err_setup_rx: 7056 /* rewind the index freeing the rings as we go */ 7057 while (i--) 7058 ixgbe_free_rx_resources(adapter->rx_ring[i]); 7059 return err; 7060 } 7061 7062 /** 7063 * ixgbe_free_tx_resources - Free Tx Resources per Queue 7064 * @tx_ring: Tx descriptor ring for a specific queue 7065 * 7066 * Free all transmit software resources 7067 **/ 7068 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 7069 { 7070 ixgbe_clean_tx_ring(tx_ring); 7071 7072 vfree(tx_ring->tx_buffer_info); 7073 tx_ring->tx_buffer_info = NULL; 7074 7075 /* if not set, then don't free */ 7076 if (!tx_ring->desc) 7077 return; 7078 7079 dma_free_coherent(tx_ring->dev, tx_ring->size, 7080 tx_ring->desc, tx_ring->dma); 7081 7082 tx_ring->desc = NULL; 7083 } 7084 7085 /** 7086 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 7087 * @adapter: board private structure 7088 * 7089 * Free all transmit software resources 7090 **/ 7091 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 7092 { 7093 int i; 7094 7095 for (i = 0; i < adapter->num_tx_queues; i++) 7096 if (adapter->tx_ring[i]->desc) 7097 ixgbe_free_tx_resources(adapter->tx_ring[i]); 7098 for (i = 0; i < adapter->num_xdp_queues; i++) 7099 if (adapter->xdp_ring[i]->desc) 7100 ixgbe_free_tx_resources(adapter->xdp_ring[i]); 7101 } 7102 7103 /** 7104 * ixgbe_free_rx_resources - Free Rx Resources 7105 * @rx_ring: ring to clean the resources from 7106 * 7107 * Free all receive software resources 7108 **/ 7109 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 7110 { 7111 ixgbe_clean_rx_ring(rx_ring); 7112 7113 rx_ring->xdp_prog = NULL; 7114 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 7115 vfree(rx_ring->rx_buffer_info); 7116 rx_ring->rx_buffer_info = NULL; 7117 7118 /* if not set, then don't free */ 7119 if (!rx_ring->desc) 7120 return; 7121 7122 dma_free_coherent(rx_ring->dev, rx_ring->size, 7123 rx_ring->desc, rx_ring->dma); 7124 7125 rx_ring->desc = NULL; 7126 } 7127 7128 /** 7129 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 7130 * @adapter: board private structure 7131 * 7132 * Free all receive software resources 7133 **/ 7134 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 7135 { 7136 int i; 7137 7138 #ifdef IXGBE_FCOE 7139 ixgbe_free_fcoe_ddp_resources(adapter); 7140 7141 #endif 7142 for (i = 0; i < adapter->num_rx_queues; i++) 7143 if (adapter->rx_ring[i]->desc) 7144 ixgbe_free_rx_resources(adapter->rx_ring[i]); 7145 } 7146 7147 /** 7148 * ixgbe_max_xdp_frame_size - returns the maximum allowed frame size for XDP 7149 * @adapter: device handle, pointer to adapter 7150 */ 7151 static int ixgbe_max_xdp_frame_size(struct ixgbe_adapter *adapter) 7152 { 7153 if (PAGE_SIZE >= 8192 || adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 7154 return IXGBE_RXBUFFER_2K; 7155 else 7156 return IXGBE_RXBUFFER_3K; 7157 } 7158 7159 /** 7160 * ixgbe_change_mtu - Change the Maximum Transfer Unit 7161 * @netdev: network interface device structure 7162 * @new_mtu: new value for maximum frame size 7163 * 7164 * Returns 0 on success, negative on failure 7165 **/ 7166 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 7167 { 7168 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7169 7170 if (ixgbe_enabled_xdp_adapter(adapter)) { 7171 int new_frame_size = new_mtu + IXGBE_PKT_HDR_PAD; 7172 7173 if (new_frame_size > ixgbe_max_xdp_frame_size(adapter)) { 7174 e_warn(probe, "Requested MTU size is not supported with XDP\n"); 7175 return -EINVAL; 7176 } 7177 } 7178 7179 /* 7180 * For 82599EB we cannot allow legacy VFs to enable their receive 7181 * paths when MTU greater than 1500 is configured. So display a 7182 * warning that legacy VFs will be disabled. 7183 */ 7184 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 7185 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 7186 (new_mtu > ETH_DATA_LEN)) 7187 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 7188 7189 netdev_dbg(netdev, "changing MTU from %d to %d\n", 7190 netdev->mtu, new_mtu); 7191 7192 /* must set new MTU before calling down or up */ 7193 WRITE_ONCE(netdev->mtu, new_mtu); 7194 7195 if (netif_running(netdev)) 7196 ixgbe_reinit_locked(adapter); 7197 7198 return 0; 7199 } 7200 7201 /** 7202 * ixgbe_open - Called when a network interface is made active 7203 * @netdev: network interface device structure 7204 * 7205 * Returns 0 on success, negative value on failure 7206 * 7207 * The open entry point is called when a network interface is made 7208 * active by the system (IFF_UP). At this point all resources needed 7209 * for transmit and receive operations are allocated, the interrupt 7210 * handler is registered with the OS, the watchdog timer is started, 7211 * and the stack is notified that the interface is ready. 7212 **/ 7213 int ixgbe_open(struct net_device *netdev) 7214 { 7215 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7216 struct ixgbe_hw *hw = &adapter->hw; 7217 int err, queues; 7218 7219 /* disallow open during test */ 7220 if (test_bit(__IXGBE_TESTING, &adapter->state)) 7221 return -EBUSY; 7222 7223 netif_carrier_off(netdev); 7224 7225 /* allocate transmit descriptors */ 7226 err = ixgbe_setup_all_tx_resources(adapter); 7227 if (err) 7228 goto err_setup_tx; 7229 7230 /* allocate receive descriptors */ 7231 err = ixgbe_setup_all_rx_resources(adapter); 7232 if (err) 7233 goto err_setup_rx; 7234 7235 ixgbe_configure(adapter); 7236 7237 err = ixgbe_request_irq(adapter); 7238 if (err) 7239 goto err_req_irq; 7240 7241 /* Notify the stack of the actual queue counts. */ 7242 queues = adapter->num_tx_queues; 7243 err = netif_set_real_num_tx_queues(netdev, queues); 7244 if (err) 7245 goto err_set_queues; 7246 7247 queues = adapter->num_rx_queues; 7248 err = netif_set_real_num_rx_queues(netdev, queues); 7249 if (err) 7250 goto err_set_queues; 7251 7252 ixgbe_ptp_init(adapter); 7253 7254 ixgbe_up_complete(adapter); 7255 7256 udp_tunnel_nic_reset_ntf(netdev); 7257 if (adapter->hw.mac.type == ixgbe_mac_e610) { 7258 int err = ixgbe_update_link_info(&adapter->hw); 7259 7260 if (err) 7261 e_dev_err("Failed to update link info, err %d.\n", err); 7262 7263 ixgbe_check_link_cfg_err(adapter, 7264 adapter->hw.link.link_info.link_cfg_err); 7265 7266 err = ixgbe_non_sfp_link_config(&adapter->hw); 7267 if (ixgbe_non_sfp_link_config(&adapter->hw)) 7268 e_dev_err("Link setup failed, err %d.\n", err); 7269 } 7270 7271 return 0; 7272 7273 err_set_queues: 7274 ixgbe_free_irq(adapter); 7275 err_req_irq: 7276 ixgbe_free_all_rx_resources(adapter); 7277 if (hw->phy.ops.set_phy_power && !adapter->wol) 7278 hw->phy.ops.set_phy_power(&adapter->hw, false); 7279 err_setup_rx: 7280 ixgbe_free_all_tx_resources(adapter); 7281 err_setup_tx: 7282 ixgbe_reset(adapter); 7283 7284 return err; 7285 } 7286 7287 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 7288 { 7289 ixgbe_ptp_suspend(adapter); 7290 7291 if (adapter->hw.phy.ops.enter_lplu) { 7292 adapter->hw.phy.reset_disable = true; 7293 ixgbe_down(adapter); 7294 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 7295 adapter->hw.phy.reset_disable = false; 7296 } else { 7297 ixgbe_down(adapter); 7298 } 7299 7300 ixgbe_free_irq(adapter); 7301 7302 ixgbe_free_all_tx_resources(adapter); 7303 ixgbe_free_all_rx_resources(adapter); 7304 } 7305 7306 /** 7307 * ixgbe_close - Disables a network interface 7308 * @netdev: network interface device structure 7309 * 7310 * Returns 0, this is not allowed to fail 7311 * 7312 * The close entry point is called when an interface is de-activated 7313 * by the OS. The hardware is still under the drivers control, but 7314 * needs to be disabled. A global MAC reset is issued to stop the 7315 * hardware, and all transmit and receive resources are freed. 7316 **/ 7317 int ixgbe_close(struct net_device *netdev) 7318 { 7319 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7320 7321 ixgbe_ptp_stop(adapter); 7322 7323 if (netif_device_present(netdev)) 7324 ixgbe_close_suspend(adapter); 7325 7326 ixgbe_fdir_filter_exit(adapter); 7327 7328 ixgbe_release_hw_control(adapter); 7329 7330 return 0; 7331 } 7332 7333 static int ixgbe_resume(struct device *dev_d) 7334 { 7335 struct pci_dev *pdev = to_pci_dev(dev_d); 7336 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 7337 struct net_device *netdev = adapter->netdev; 7338 u32 err; 7339 7340 adapter->hw.hw_addr = adapter->io_addr; 7341 7342 err = pci_enable_device_mem(pdev); 7343 if (err) { 7344 e_dev_err("Cannot enable PCI device from suspend\n"); 7345 return err; 7346 } 7347 smp_mb__before_atomic(); 7348 clear_bit(__IXGBE_DISABLED, &adapter->state); 7349 pci_set_master(pdev); 7350 7351 device_wakeup_disable(dev_d); 7352 7353 ixgbe_reset(adapter); 7354 7355 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 7356 7357 rtnl_lock(); 7358 err = ixgbe_init_interrupt_scheme(adapter); 7359 if (!err && netif_running(netdev)) 7360 err = ixgbe_open(netdev); 7361 7362 7363 if (!err) 7364 netif_device_attach(netdev); 7365 rtnl_unlock(); 7366 7367 return err; 7368 } 7369 7370 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 7371 { 7372 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 7373 struct net_device *netdev = adapter->netdev; 7374 struct ixgbe_hw *hw = &adapter->hw; 7375 u32 ctrl; 7376 u32 wufc = adapter->wol; 7377 7378 rtnl_lock(); 7379 netif_device_detach(netdev); 7380 7381 if (netif_running(netdev)) 7382 ixgbe_close_suspend(adapter); 7383 7384 ixgbe_clear_interrupt_scheme(adapter); 7385 rtnl_unlock(); 7386 7387 if (hw->mac.ops.stop_link_on_d3) 7388 hw->mac.ops.stop_link_on_d3(hw); 7389 7390 if (wufc) { 7391 u32 fctrl; 7392 7393 ixgbe_set_rx_mode(netdev); 7394 7395 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 7396 if (hw->mac.ops.enable_tx_laser) 7397 hw->mac.ops.enable_tx_laser(hw); 7398 7399 /* enable the reception of multicast packets */ 7400 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7401 fctrl |= IXGBE_FCTRL_MPE; 7402 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 7403 7404 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 7405 ctrl |= IXGBE_CTRL_GIO_DIS; 7406 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 7407 7408 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 7409 } else { 7410 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 7411 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 7412 } 7413 7414 switch (hw->mac.type) { 7415 case ixgbe_mac_82598EB: 7416 pci_wake_from_d3(pdev, false); 7417 break; 7418 case ixgbe_mac_82599EB: 7419 case ixgbe_mac_X540: 7420 case ixgbe_mac_X550: 7421 case ixgbe_mac_X550EM_x: 7422 case ixgbe_mac_x550em_a: 7423 case ixgbe_mac_e610: 7424 pci_wake_from_d3(pdev, !!wufc); 7425 break; 7426 default: 7427 break; 7428 } 7429 7430 *enable_wake = !!wufc; 7431 if (hw->phy.ops.set_phy_power && !*enable_wake) 7432 hw->phy.ops.set_phy_power(hw, false); 7433 7434 ixgbe_release_hw_control(adapter); 7435 7436 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 7437 pci_disable_device(pdev); 7438 7439 return 0; 7440 } 7441 7442 static int ixgbe_suspend(struct device *dev_d) 7443 { 7444 struct pci_dev *pdev = to_pci_dev(dev_d); 7445 int retval; 7446 bool wake; 7447 7448 retval = __ixgbe_shutdown(pdev, &wake); 7449 7450 device_set_wakeup_enable(dev_d, wake); 7451 7452 return retval; 7453 } 7454 7455 static void ixgbe_shutdown(struct pci_dev *pdev) 7456 { 7457 bool wake; 7458 7459 __ixgbe_shutdown(pdev, &wake); 7460 7461 if (system_state == SYSTEM_POWER_OFF) { 7462 pci_wake_from_d3(pdev, wake); 7463 pci_set_power_state(pdev, PCI_D3hot); 7464 } 7465 } 7466 7467 /** 7468 * ixgbe_update_stats - Update the board statistics counters. 7469 * @adapter: board private structure 7470 **/ 7471 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 7472 { 7473 struct net_device *netdev = adapter->netdev; 7474 struct ixgbe_hw *hw = &adapter->hw; 7475 struct ixgbe_hw_stats *hwstats = &adapter->stats; 7476 u64 total_mpc = 0; 7477 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 7478 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 7479 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 7480 u64 alloc_rx_page = 0; 7481 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 7482 7483 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7484 test_bit(__IXGBE_RESETTING, &adapter->state)) 7485 return; 7486 7487 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 7488 u64 rsc_count = 0; 7489 u64 rsc_flush = 0; 7490 for (i = 0; i < adapter->num_rx_queues; i++) { 7491 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 7492 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 7493 } 7494 adapter->rsc_total_count = rsc_count; 7495 adapter->rsc_total_flush = rsc_flush; 7496 } 7497 7498 for (i = 0; i < adapter->num_rx_queues; i++) { 7499 struct ixgbe_ring *rx_ring = READ_ONCE(adapter->rx_ring[i]); 7500 7501 if (!rx_ring) 7502 continue; 7503 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 7504 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page; 7505 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 7506 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 7507 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 7508 bytes += rx_ring->stats.bytes; 7509 packets += rx_ring->stats.packets; 7510 } 7511 adapter->non_eop_descs = non_eop_descs; 7512 adapter->alloc_rx_page = alloc_rx_page; 7513 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 7514 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 7515 adapter->hw_csum_rx_error = hw_csum_rx_error; 7516 netdev->stats.rx_bytes = bytes; 7517 netdev->stats.rx_packets = packets; 7518 7519 bytes = 0; 7520 packets = 0; 7521 /* gather some stats to the adapter struct that are per queue */ 7522 for (i = 0; i < adapter->num_tx_queues; i++) { 7523 struct ixgbe_ring *tx_ring = READ_ONCE(adapter->tx_ring[i]); 7524 7525 if (!tx_ring) 7526 continue; 7527 restart_queue += tx_ring->tx_stats.restart_queue; 7528 tx_busy += tx_ring->tx_stats.tx_busy; 7529 bytes += tx_ring->stats.bytes; 7530 packets += tx_ring->stats.packets; 7531 } 7532 for (i = 0; i < adapter->num_xdp_queues; i++) { 7533 struct ixgbe_ring *xdp_ring = READ_ONCE(adapter->xdp_ring[i]); 7534 7535 if (!xdp_ring) 7536 continue; 7537 restart_queue += xdp_ring->tx_stats.restart_queue; 7538 tx_busy += xdp_ring->tx_stats.tx_busy; 7539 bytes += xdp_ring->stats.bytes; 7540 packets += xdp_ring->stats.packets; 7541 } 7542 adapter->restart_queue = restart_queue; 7543 adapter->tx_busy = tx_busy; 7544 netdev->stats.tx_bytes = bytes; 7545 netdev->stats.tx_packets = packets; 7546 7547 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 7548 7549 /* 8 register reads */ 7550 for (i = 0; i < 8; i++) { 7551 /* for packet buffers not used, the register should read 0 */ 7552 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 7553 missed_rx += mpc; 7554 hwstats->mpc[i] += mpc; 7555 total_mpc += hwstats->mpc[i]; 7556 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 7557 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 7558 switch (hw->mac.type) { 7559 case ixgbe_mac_82598EB: 7560 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 7561 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 7562 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 7563 hwstats->pxonrxc[i] += 7564 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 7565 break; 7566 case ixgbe_mac_82599EB: 7567 case ixgbe_mac_X540: 7568 case ixgbe_mac_X550: 7569 case ixgbe_mac_X550EM_x: 7570 case ixgbe_mac_x550em_a: 7571 case ixgbe_mac_e610: 7572 hwstats->pxonrxc[i] += 7573 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 7574 break; 7575 default: 7576 break; 7577 } 7578 } 7579 7580 /*16 register reads */ 7581 for (i = 0; i < 16; i++) { 7582 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 7583 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 7584 if (hw->mac.type == ixgbe_mac_82599EB || 7585 hw->mac.type == ixgbe_mac_X540 || 7586 hw->mac.type == ixgbe_mac_X550 || 7587 hw->mac.type == ixgbe_mac_X550EM_x || 7588 hw->mac.type == ixgbe_mac_x550em_a || 7589 hw->mac.type == ixgbe_mac_e610) { 7590 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 7591 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 7592 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 7593 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 7594 } 7595 } 7596 7597 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 7598 /* work around hardware counting issue */ 7599 hwstats->gprc -= missed_rx; 7600 7601 ixgbe_update_xoff_received(adapter); 7602 7603 /* 82598 hardware only has a 32 bit counter in the high register */ 7604 switch (hw->mac.type) { 7605 case ixgbe_mac_82598EB: 7606 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 7607 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 7608 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 7609 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 7610 break; 7611 case ixgbe_mac_X540: 7612 case ixgbe_mac_X550: 7613 case ixgbe_mac_X550EM_x: 7614 case ixgbe_mac_x550em_a: 7615 case ixgbe_mac_e610: 7616 /* OS2BMC stats are X540 and later */ 7617 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 7618 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 7619 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 7620 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 7621 fallthrough; 7622 case ixgbe_mac_82599EB: 7623 for (i = 0; i < 16; i++) 7624 adapter->hw_rx_no_dma_resources += 7625 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 7626 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 7627 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 7628 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 7629 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 7630 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 7631 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 7632 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 7633 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 7634 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 7635 #ifdef IXGBE_FCOE 7636 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 7637 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 7638 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 7639 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 7640 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 7641 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 7642 /* Add up per cpu counters for total ddp aloc fail */ 7643 if (adapter->fcoe.ddp_pool) { 7644 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 7645 struct ixgbe_fcoe_ddp_pool *ddp_pool; 7646 unsigned int cpu; 7647 u64 noddp = 0, noddp_ext_buff = 0; 7648 for_each_possible_cpu(cpu) { 7649 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 7650 noddp += ddp_pool->noddp; 7651 noddp_ext_buff += ddp_pool->noddp_ext_buff; 7652 } 7653 hwstats->fcoe_noddp = noddp; 7654 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 7655 } 7656 #endif /* IXGBE_FCOE */ 7657 break; 7658 default: 7659 break; 7660 } 7661 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 7662 hwstats->bprc += bprc; 7663 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 7664 if (hw->mac.type == ixgbe_mac_82598EB) 7665 hwstats->mprc -= bprc; 7666 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 7667 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 7668 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 7669 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 7670 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 7671 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 7672 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 7673 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 7674 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 7675 hwstats->lxontxc += lxon; 7676 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 7677 hwstats->lxofftxc += lxoff; 7678 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 7679 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 7680 /* 7681 * 82598 errata - tx of flow control packets is included in tx counters 7682 */ 7683 xon_off_tot = lxon + lxoff; 7684 hwstats->gptc -= xon_off_tot; 7685 hwstats->mptc -= xon_off_tot; 7686 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 7687 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 7688 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 7689 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 7690 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 7691 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 7692 hwstats->ptc64 -= xon_off_tot; 7693 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 7694 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 7695 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 7696 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 7697 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 7698 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 7699 7700 /* Fill out the OS statistics structure */ 7701 netdev->stats.multicast = hwstats->mprc; 7702 7703 /* Rx Errors */ 7704 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 7705 netdev->stats.rx_dropped = 0; 7706 netdev->stats.rx_length_errors = hwstats->rlec; 7707 netdev->stats.rx_crc_errors = hwstats->crcerrs; 7708 netdev->stats.rx_missed_errors = total_mpc; 7709 7710 /* VF Stats Collection - skip while resetting because these 7711 * are not clear on read and otherwise you'll sometimes get 7712 * crazy values. 7713 */ 7714 if (!test_bit(__IXGBE_RESETTING, &adapter->state)) { 7715 for (i = 0; i < adapter->num_vfs; i++) { 7716 UPDATE_VF_COUNTER_32bit(IXGBE_PVFGPRC(i), 7717 adapter->vfinfo[i].last_vfstats.gprc, 7718 adapter->vfinfo[i].vfstats.gprc); 7719 UPDATE_VF_COUNTER_32bit(IXGBE_PVFGPTC(i), 7720 adapter->vfinfo[i].last_vfstats.gptc, 7721 adapter->vfinfo[i].vfstats.gptc); 7722 UPDATE_VF_COUNTER_36bit(IXGBE_PVFGORC_LSB(i), 7723 IXGBE_PVFGORC_MSB(i), 7724 adapter->vfinfo[i].last_vfstats.gorc, 7725 adapter->vfinfo[i].vfstats.gorc); 7726 UPDATE_VF_COUNTER_36bit(IXGBE_PVFGOTC_LSB(i), 7727 IXGBE_PVFGOTC_MSB(i), 7728 adapter->vfinfo[i].last_vfstats.gotc, 7729 adapter->vfinfo[i].vfstats.gotc); 7730 UPDATE_VF_COUNTER_32bit(IXGBE_PVFMPRC(i), 7731 adapter->vfinfo[i].last_vfstats.mprc, 7732 adapter->vfinfo[i].vfstats.mprc); 7733 } 7734 } 7735 } 7736 7737 /** 7738 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 7739 * @adapter: pointer to the device adapter structure 7740 **/ 7741 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 7742 { 7743 struct ixgbe_hw *hw = &adapter->hw; 7744 int i; 7745 7746 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 7747 return; 7748 7749 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 7750 7751 /* if interface is down do nothing */ 7752 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7753 return; 7754 7755 /* do nothing if we are not using signature filters */ 7756 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 7757 return; 7758 7759 adapter->fdir_overflow++; 7760 7761 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 7762 for (i = 0; i < adapter->num_tx_queues; i++) 7763 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7764 &(adapter->tx_ring[i]->state)); 7765 for (i = 0; i < adapter->num_xdp_queues; i++) 7766 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7767 &adapter->xdp_ring[i]->state); 7768 /* re-enable flow director interrupts */ 7769 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 7770 } else { 7771 e_err(probe, "failed to finish FDIR re-initialization, " 7772 "ignored adding FDIR ATR filters\n"); 7773 } 7774 } 7775 7776 /** 7777 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 7778 * @adapter: pointer to the device adapter structure 7779 * 7780 * This function serves two purposes. First it strobes the interrupt lines 7781 * in order to make certain interrupts are occurring. Secondly it sets the 7782 * bits needed to check for TX hangs. As a result we should immediately 7783 * determine if a hang has occurred. 7784 */ 7785 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 7786 { 7787 struct ixgbe_hw *hw = &adapter->hw; 7788 u64 eics = 0; 7789 int i; 7790 7791 /* If we're down, removing or resetting, just bail */ 7792 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7793 test_bit(__IXGBE_REMOVING, &adapter->state) || 7794 test_bit(__IXGBE_RESETTING, &adapter->state)) 7795 return; 7796 7797 /* Force detection of hung controller */ 7798 if (netif_carrier_ok(adapter->netdev)) { 7799 for (i = 0; i < adapter->num_tx_queues; i++) 7800 set_check_for_tx_hang(adapter->tx_ring[i]); 7801 for (i = 0; i < adapter->num_xdp_queues; i++) 7802 set_check_for_tx_hang(adapter->xdp_ring[i]); 7803 } 7804 7805 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 7806 /* 7807 * for legacy and MSI interrupts don't set any bits 7808 * that are enabled for EIAM, because this operation 7809 * would set *both* EIMS and EICS for any bit in EIAM 7810 */ 7811 IXGBE_WRITE_REG(hw, IXGBE_EICS, 7812 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 7813 } else { 7814 /* get one bit for every active tx/rx interrupt vector */ 7815 for (i = 0; i < adapter->num_q_vectors; i++) { 7816 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 7817 if (qv->rx.ring || qv->tx.ring) 7818 eics |= BIT_ULL(i); 7819 } 7820 } 7821 7822 /* Cause software interrupt to ensure rings are cleaned */ 7823 ixgbe_irq_rearm_queues(adapter, eics); 7824 } 7825 7826 /** 7827 * ixgbe_watchdog_update_link - update the link status 7828 * @adapter: pointer to the device adapter structure 7829 **/ 7830 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 7831 { 7832 struct ixgbe_hw *hw = &adapter->hw; 7833 u32 link_speed = adapter->link_speed; 7834 bool link_up = adapter->link_up; 7835 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 7836 7837 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 7838 return; 7839 7840 if (hw->mac.ops.check_link) { 7841 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 7842 } else { 7843 /* always assume link is up, if no check link function */ 7844 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 7845 link_up = true; 7846 } 7847 7848 if (adapter->ixgbe_ieee_pfc) 7849 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 7850 7851 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 7852 hw->mac.ops.fc_enable(hw); 7853 ixgbe_set_rx_drop_en(adapter); 7854 } 7855 7856 if (link_up || 7857 time_after(jiffies, (adapter->link_check_timeout + 7858 IXGBE_TRY_LINK_TIMEOUT))) { 7859 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 7860 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 7861 IXGBE_WRITE_FLUSH(hw); 7862 } 7863 7864 adapter->link_up = link_up; 7865 adapter->link_speed = link_speed; 7866 } 7867 7868 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 7869 { 7870 #ifdef CONFIG_IXGBE_DCB 7871 struct net_device *netdev = adapter->netdev; 7872 struct dcb_app app = { 7873 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 7874 .protocol = 0, 7875 }; 7876 u8 up = 0; 7877 7878 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 7879 up = dcb_ieee_getapp_mask(netdev, &app); 7880 7881 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 7882 #endif 7883 } 7884 7885 /** 7886 * ixgbe_watchdog_link_is_up - update netif_carrier status and 7887 * print link up message 7888 * @adapter: pointer to the device adapter structure 7889 **/ 7890 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 7891 { 7892 struct net_device *netdev = adapter->netdev; 7893 struct ixgbe_hw *hw = &adapter->hw; 7894 u32 link_speed = adapter->link_speed; 7895 const char *speed_str; 7896 bool flow_rx, flow_tx; 7897 7898 /* only continue if link was previously down */ 7899 if (netif_carrier_ok(netdev)) 7900 return; 7901 7902 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 7903 7904 switch (hw->mac.type) { 7905 case ixgbe_mac_82598EB: { 7906 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7907 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 7908 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 7909 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 7910 } 7911 break; 7912 case ixgbe_mac_X540: 7913 case ixgbe_mac_X550: 7914 case ixgbe_mac_X550EM_x: 7915 case ixgbe_mac_x550em_a: 7916 case ixgbe_mac_e610: 7917 case ixgbe_mac_82599EB: { 7918 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 7919 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 7920 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 7921 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 7922 } 7923 break; 7924 default: 7925 flow_tx = false; 7926 flow_rx = false; 7927 break; 7928 } 7929 7930 adapter->last_rx_ptp_check = jiffies; 7931 7932 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7933 ixgbe_ptp_start_cyclecounter(adapter); 7934 7935 switch (link_speed) { 7936 case IXGBE_LINK_SPEED_10GB_FULL: 7937 speed_str = "10 Gbps"; 7938 break; 7939 case IXGBE_LINK_SPEED_5GB_FULL: 7940 speed_str = "5 Gbps"; 7941 break; 7942 case IXGBE_LINK_SPEED_2_5GB_FULL: 7943 speed_str = "2.5 Gbps"; 7944 break; 7945 case IXGBE_LINK_SPEED_1GB_FULL: 7946 speed_str = "1 Gbps"; 7947 break; 7948 case IXGBE_LINK_SPEED_100_FULL: 7949 speed_str = "100 Mbps"; 7950 break; 7951 case IXGBE_LINK_SPEED_10_FULL: 7952 speed_str = "10 Mbps"; 7953 break; 7954 default: 7955 speed_str = "unknown speed"; 7956 break; 7957 } 7958 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, 7959 ((flow_rx && flow_tx) ? "RX/TX" : 7960 (flow_rx ? "RX" : 7961 (flow_tx ? "TX" : "None")))); 7962 7963 netif_carrier_on(netdev); 7964 ixgbe_check_vf_rate_limit(adapter); 7965 7966 /* enable transmits */ 7967 netif_tx_wake_all_queues(adapter->netdev); 7968 7969 /* update the default user priority for VFs */ 7970 ixgbe_update_default_up(adapter); 7971 7972 /* ping all the active vfs to let them know link has changed */ 7973 ixgbe_ping_all_vfs(adapter); 7974 } 7975 7976 /** 7977 * ixgbe_watchdog_link_is_down - update netif_carrier status and 7978 * print link down message 7979 * @adapter: pointer to the adapter structure 7980 **/ 7981 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 7982 { 7983 struct net_device *netdev = adapter->netdev; 7984 struct ixgbe_hw *hw = &adapter->hw; 7985 7986 adapter->link_up = false; 7987 adapter->link_speed = 0; 7988 7989 /* only continue if link was up previously */ 7990 if (!netif_carrier_ok(netdev)) 7991 return; 7992 7993 /* poll for SFP+ cable when link is down */ 7994 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 7995 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 7996 7997 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7998 ixgbe_ptp_start_cyclecounter(adapter); 7999 8000 e_info(drv, "NIC Link is Down\n"); 8001 netif_carrier_off(netdev); 8002 8003 /* ping all the active vfs to let them know link has changed */ 8004 ixgbe_ping_all_vfs(adapter); 8005 } 8006 8007 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 8008 { 8009 int i; 8010 8011 for (i = 0; i < adapter->num_tx_queues; i++) { 8012 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 8013 8014 if (tx_ring->next_to_use != tx_ring->next_to_clean) 8015 return true; 8016 } 8017 8018 for (i = 0; i < adapter->num_xdp_queues; i++) { 8019 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 8020 8021 if (ring->next_to_use != ring->next_to_clean) 8022 return true; 8023 } 8024 8025 return false; 8026 } 8027 8028 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 8029 { 8030 struct ixgbe_hw *hw = &adapter->hw; 8031 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 8032 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 8033 8034 int i, j; 8035 8036 if (!adapter->num_vfs) 8037 return false; 8038 8039 /* resetting the PF is only needed for MAC before X550 */ 8040 if (hw->mac.type >= ixgbe_mac_X550) 8041 return false; 8042 8043 for (i = 0; i < adapter->num_vfs; i++) { 8044 for (j = 0; j < q_per_pool; j++) { 8045 u32 h, t; 8046 8047 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 8048 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 8049 8050 if (h != t) 8051 return true; 8052 } 8053 } 8054 8055 return false; 8056 } 8057 8058 /** 8059 * ixgbe_watchdog_flush_tx - flush queues on link down 8060 * @adapter: pointer to the device adapter structure 8061 **/ 8062 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 8063 { 8064 if (!netif_carrier_ok(adapter->netdev)) { 8065 if (ixgbe_ring_tx_pending(adapter) || 8066 ixgbe_vf_tx_pending(adapter)) { 8067 /* We've lost link, so the controller stops DMA, 8068 * but we've got queued Tx work that's never going 8069 * to get done, so reset controller to flush Tx. 8070 * (Do the reset outside of interrupt context). 8071 */ 8072 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 8073 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 8074 } 8075 } 8076 } 8077 8078 #ifdef CONFIG_PCI_IOV 8079 static void ixgbe_bad_vf_abort(struct ixgbe_adapter *adapter, u32 vf) 8080 { 8081 struct ixgbe_hw *hw = &adapter->hw; 8082 8083 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 8084 adapter->flags2 & IXGBE_FLAG2_AUTO_DISABLE_VF) { 8085 adapter->vfinfo[vf].primary_abort_count++; 8086 if (adapter->vfinfo[vf].primary_abort_count == 8087 IXGBE_PRIMARY_ABORT_LIMIT) { 8088 ixgbe_set_vf_link_state(adapter, vf, 8089 IFLA_VF_LINK_STATE_DISABLE); 8090 adapter->vfinfo[vf].primary_abort_count = 0; 8091 8092 e_info(drv, 8093 "Malicious Driver Detection event detected on PF %d VF %d MAC: %pM mdd-disable-vf=on", 8094 hw->bus.func, vf, 8095 adapter->vfinfo[vf].vf_mac_addresses); 8096 } 8097 } 8098 } 8099 8100 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 8101 { 8102 struct ixgbe_hw *hw = &adapter->hw; 8103 struct pci_dev *pdev = adapter->pdev; 8104 unsigned int vf; 8105 u32 gpc; 8106 8107 if (!(netif_carrier_ok(adapter->netdev))) 8108 return; 8109 8110 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 8111 if (gpc) /* If incrementing then no need for the check below */ 8112 return; 8113 /* Check to see if a bad DMA write target from an errant or 8114 * malicious VF has caused a PCIe error. If so then we can 8115 * issue a VFLR to the offending VF(s) and then resume without 8116 * requesting a full slot reset. 8117 */ 8118 8119 if (!pdev) 8120 return; 8121 8122 /* check status reg for all VFs owned by this PF */ 8123 for (vf = 0; vf < adapter->num_vfs; ++vf) { 8124 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; 8125 u16 status_reg; 8126 8127 if (!vfdev) 8128 continue; 8129 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 8130 if (status_reg != IXGBE_FAILED_READ_CFG_WORD && 8131 status_reg & PCI_STATUS_REC_MASTER_ABORT) { 8132 ixgbe_bad_vf_abort(adapter, vf); 8133 pcie_flr(vfdev); 8134 } 8135 } 8136 } 8137 8138 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 8139 { 8140 u32 ssvpc; 8141 8142 /* Do not perform spoof check for 82598 or if not in IOV mode */ 8143 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 8144 adapter->num_vfs == 0) 8145 return; 8146 8147 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 8148 8149 /* 8150 * ssvpc register is cleared on read, if zero then no 8151 * spoofed packets in the last interval. 8152 */ 8153 if (!ssvpc) 8154 return; 8155 8156 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 8157 } 8158 #else 8159 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 8160 { 8161 } 8162 8163 static void 8164 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 8165 { 8166 } 8167 #endif /* CONFIG_PCI_IOV */ 8168 8169 8170 /** 8171 * ixgbe_watchdog_subtask - check and bring link up 8172 * @adapter: pointer to the device adapter structure 8173 **/ 8174 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 8175 { 8176 /* if interface is down, removing or resetting, do nothing */ 8177 if (test_bit(__IXGBE_DOWN, &adapter->state) || 8178 test_bit(__IXGBE_REMOVING, &adapter->state) || 8179 test_bit(__IXGBE_RESETTING, &adapter->state)) 8180 return; 8181 8182 ixgbe_watchdog_update_link(adapter); 8183 8184 if (adapter->link_up) 8185 ixgbe_watchdog_link_is_up(adapter); 8186 else 8187 ixgbe_watchdog_link_is_down(adapter); 8188 8189 ixgbe_check_for_bad_vf(adapter); 8190 ixgbe_spoof_check(adapter); 8191 ixgbe_update_stats(adapter); 8192 8193 ixgbe_watchdog_flush_tx(adapter); 8194 } 8195 8196 /** 8197 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 8198 * @adapter: the ixgbe adapter structure 8199 **/ 8200 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 8201 { 8202 struct ixgbe_hw *hw = &adapter->hw; 8203 int err; 8204 8205 /* not searching for SFP so there is nothing to do here */ 8206 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 8207 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 8208 return; 8209 8210 if (adapter->sfp_poll_time && 8211 time_after(adapter->sfp_poll_time, jiffies)) 8212 return; /* If not yet time to poll for SFP */ 8213 8214 /* someone else is in init, wait until next service event */ 8215 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 8216 return; 8217 8218 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; 8219 8220 err = hw->phy.ops.identify_sfp(hw); 8221 if (err == -EOPNOTSUPP) 8222 goto sfp_out; 8223 8224 if (err == -ENOENT) { 8225 /* If no cable is present, then we need to reset 8226 * the next time we find a good cable. */ 8227 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 8228 } 8229 8230 /* exit on error */ 8231 if (err) 8232 goto sfp_out; 8233 8234 /* exit if reset not needed */ 8235 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 8236 goto sfp_out; 8237 8238 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 8239 8240 /* 8241 * A module may be identified correctly, but the EEPROM may not have 8242 * support for that module. setup_sfp() will fail in that case, so 8243 * we should not allow that module to load. 8244 */ 8245 if (hw->mac.type == ixgbe_mac_82598EB) 8246 err = hw->phy.ops.reset(hw); 8247 else 8248 err = hw->mac.ops.setup_sfp(hw); 8249 8250 if (err == -EOPNOTSUPP) 8251 goto sfp_out; 8252 8253 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 8254 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 8255 8256 sfp_out: 8257 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 8258 8259 if (err == -EOPNOTSUPP && 8260 adapter->netdev->reg_state == NETREG_REGISTERED) { 8261 e_dev_err("failed to initialize because an unsupported " 8262 "SFP+ module type was detected.\n"); 8263 e_dev_err("Reload the driver after installing a " 8264 "supported module.\n"); 8265 unregister_netdev(adapter->netdev); 8266 } 8267 } 8268 8269 /** 8270 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 8271 * @adapter: the ixgbe adapter structure 8272 **/ 8273 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 8274 { 8275 struct ixgbe_hw *hw = &adapter->hw; 8276 u32 cap_speed; 8277 u32 speed; 8278 bool autoneg = false; 8279 8280 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 8281 return; 8282 8283 /* someone else is in init, wait until next service event */ 8284 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 8285 return; 8286 8287 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 8288 8289 hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg); 8290 8291 /* advertise highest capable link speed */ 8292 if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL)) 8293 speed = IXGBE_LINK_SPEED_10GB_FULL; 8294 else 8295 speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL | 8296 IXGBE_LINK_SPEED_1GB_FULL); 8297 8298 if (hw->mac.ops.setup_link) 8299 hw->mac.ops.setup_link(hw, speed, true); 8300 8301 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 8302 adapter->link_check_timeout = jiffies; 8303 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 8304 } 8305 8306 /** 8307 * ixgbe_service_timer - Timer Call-back 8308 * @t: pointer to timer_list structure 8309 **/ 8310 static void ixgbe_service_timer(struct timer_list *t) 8311 { 8312 struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer); 8313 unsigned long next_event_offset; 8314 8315 /* poll faster when waiting for link */ 8316 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 8317 next_event_offset = HZ / 10; 8318 else 8319 next_event_offset = HZ * 2; 8320 8321 /* Reset the timer */ 8322 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 8323 8324 ixgbe_service_event_schedule(adapter); 8325 } 8326 8327 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 8328 { 8329 struct ixgbe_hw *hw = &adapter->hw; 8330 bool overtemp; 8331 8332 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 8333 return; 8334 8335 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 8336 8337 if (!hw->phy.ops.handle_lasi) 8338 return; 8339 8340 hw->phy.ops.handle_lasi(&adapter->hw, &overtemp); 8341 if (overtemp) 8342 e_crit(drv, "%s\n", ixgbe_overheat_msg); 8343 } 8344 8345 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 8346 { 8347 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state)) 8348 return; 8349 8350 rtnl_lock(); 8351 /* If we're already down, removing or resetting, just bail */ 8352 if (test_bit(__IXGBE_DOWN, &adapter->state) || 8353 test_bit(__IXGBE_REMOVING, &adapter->state) || 8354 test_bit(__IXGBE_RESETTING, &adapter->state)) { 8355 rtnl_unlock(); 8356 return; 8357 } 8358 8359 ixgbe_dump(adapter); 8360 netdev_err(adapter->netdev, "Reset adapter\n"); 8361 adapter->tx_timeout_count++; 8362 8363 ixgbe_reinit_locked(adapter); 8364 rtnl_unlock(); 8365 } 8366 8367 /** 8368 * ixgbe_check_fw_error - Check firmware for errors 8369 * @adapter: the adapter private structure 8370 * 8371 * Check firmware errors in register FWSM 8372 */ 8373 static bool ixgbe_check_fw_error(struct ixgbe_adapter *adapter) 8374 { 8375 struct ixgbe_hw *hw = &adapter->hw; 8376 u32 fwsm; 8377 8378 /* read fwsm.ext_err_ind register and log errors */ 8379 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 8380 8381 if (fwsm & IXGBE_FWSM_EXT_ERR_IND_MASK || 8382 !(fwsm & IXGBE_FWSM_FW_VAL_BIT)) 8383 e_dev_warn("Warning firmware error detected FWSM: 0x%08X\n", 8384 fwsm); 8385 8386 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 8387 e_dev_err("Firmware recovery mode detected. Limiting functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware recovery mode.\n"); 8388 return true; 8389 } 8390 8391 return false; 8392 } 8393 8394 /** 8395 * ixgbe_service_task - manages and runs subtasks 8396 * @work: pointer to work_struct containing our data 8397 **/ 8398 static void ixgbe_service_task(struct work_struct *work) 8399 { 8400 struct ixgbe_adapter *adapter = container_of(work, 8401 struct ixgbe_adapter, 8402 service_task); 8403 if (ixgbe_removed(adapter->hw.hw_addr)) { 8404 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 8405 rtnl_lock(); 8406 ixgbe_down(adapter); 8407 rtnl_unlock(); 8408 } 8409 ixgbe_service_event_complete(adapter); 8410 return; 8411 } 8412 if (ixgbe_check_fw_error(adapter)) { 8413 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 8414 unregister_netdev(adapter->netdev); 8415 ixgbe_service_event_complete(adapter); 8416 return; 8417 } 8418 if (adapter->hw.mac.type == ixgbe_mac_e610) { 8419 if (adapter->flags2 & IXGBE_FLAG2_FW_ASYNC_EVENT) 8420 ixgbe_handle_fw_event(adapter); 8421 ixgbe_check_media_subtask(adapter); 8422 } 8423 ixgbe_reset_subtask(adapter); 8424 ixgbe_phy_interrupt_subtask(adapter); 8425 ixgbe_sfp_detection_subtask(adapter); 8426 ixgbe_sfp_link_config_subtask(adapter); 8427 ixgbe_check_overtemp_subtask(adapter); 8428 ixgbe_watchdog_subtask(adapter); 8429 ixgbe_fdir_reinit_subtask(adapter); 8430 ixgbe_check_hang_subtask(adapter); 8431 8432 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 8433 ixgbe_ptp_overflow_check(adapter); 8434 if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER) 8435 ixgbe_ptp_rx_hang(adapter); 8436 ixgbe_ptp_tx_hang(adapter); 8437 } 8438 8439 ixgbe_service_event_complete(adapter); 8440 } 8441 8442 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 8443 struct ixgbe_tx_buffer *first, 8444 u8 *hdr_len, 8445 struct ixgbe_ipsec_tx_data *itd) 8446 { 8447 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 8448 struct sk_buff *skb = first->skb; 8449 union { 8450 struct iphdr *v4; 8451 struct ipv6hdr *v6; 8452 unsigned char *hdr; 8453 } ip; 8454 union { 8455 struct tcphdr *tcp; 8456 struct udphdr *udp; 8457 unsigned char *hdr; 8458 } l4; 8459 u32 paylen, l4_offset; 8460 u32 fceof_saidx = 0; 8461 int err; 8462 8463 if (skb->ip_summed != CHECKSUM_PARTIAL) 8464 return 0; 8465 8466 if (!skb_is_gso(skb)) 8467 return 0; 8468 8469 err = skb_cow_head(skb, 0); 8470 if (err < 0) 8471 return err; 8472 8473 if (eth_p_mpls(first->protocol)) 8474 ip.hdr = skb_inner_network_header(skb); 8475 else 8476 ip.hdr = skb_network_header(skb); 8477 l4.hdr = skb_checksum_start(skb); 8478 8479 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 8480 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 8481 IXGBE_ADVTXD_TUCMD_L4T_UDP : IXGBE_ADVTXD_TUCMD_L4T_TCP; 8482 8483 /* initialize outer IP header fields */ 8484 if (ip.v4->version == 4) { 8485 unsigned char *csum_start = skb_checksum_start(skb); 8486 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 8487 int len = csum_start - trans_start; 8488 8489 /* IP header will have to cancel out any data that 8490 * is not a part of the outer IP header, so set to 8491 * a reverse csum if needed, else init check to 0. 8492 */ 8493 ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ? 8494 csum_fold(csum_partial(trans_start, 8495 len, 0)) : 0; 8496 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 8497 8498 ip.v4->tot_len = 0; 8499 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 8500 IXGBE_TX_FLAGS_CSUM | 8501 IXGBE_TX_FLAGS_IPV4; 8502 } else { 8503 ip.v6->payload_len = 0; 8504 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 8505 IXGBE_TX_FLAGS_CSUM; 8506 } 8507 8508 /* determine offset of inner transport header */ 8509 l4_offset = l4.hdr - skb->data; 8510 8511 /* remove payload length from inner checksum */ 8512 paylen = skb->len - l4_offset; 8513 8514 if (type_tucmd & IXGBE_ADVTXD_TUCMD_L4T_TCP) { 8515 /* compute length of segmentation header */ 8516 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 8517 csum_replace_by_diff(&l4.tcp->check, 8518 (__force __wsum)htonl(paylen)); 8519 } else { 8520 /* compute length of segmentation header */ 8521 *hdr_len = sizeof(*l4.udp) + l4_offset; 8522 csum_replace_by_diff(&l4.udp->check, 8523 (__force __wsum)htonl(paylen)); 8524 } 8525 8526 /* update gso size and bytecount with header size */ 8527 first->gso_segs = skb_shinfo(skb)->gso_segs; 8528 first->bytecount += (first->gso_segs - 1) * *hdr_len; 8529 8530 /* mss_l4len_id: use 0 as index for TSO */ 8531 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; 8532 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 8533 8534 fceof_saidx |= itd->sa_idx; 8535 type_tucmd |= itd->flags | itd->trailer_len; 8536 8537 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 8538 vlan_macip_lens = l4.hdr - ip.hdr; 8539 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; 8540 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8541 8542 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 8543 mss_l4len_idx); 8544 8545 return 1; 8546 } 8547 8548 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 8549 struct ixgbe_tx_buffer *first, 8550 struct ixgbe_ipsec_tx_data *itd) 8551 { 8552 struct sk_buff *skb = first->skb; 8553 u32 vlan_macip_lens = 0; 8554 u32 fceof_saidx = 0; 8555 u32 type_tucmd = 0; 8556 8557 if (skb->ip_summed != CHECKSUM_PARTIAL) { 8558 csum_failed: 8559 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | 8560 IXGBE_TX_FLAGS_CC))) 8561 return; 8562 goto no_csum; 8563 } 8564 8565 switch (skb->csum_offset) { 8566 case offsetof(struct tcphdr, check): 8567 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 8568 fallthrough; 8569 case offsetof(struct udphdr, check): 8570 break; 8571 case offsetof(struct sctphdr, checksum): 8572 /* validate that this is actually an SCTP request */ 8573 if (skb_csum_is_sctp(skb)) { 8574 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; 8575 break; 8576 } 8577 fallthrough; 8578 default: 8579 skb_checksum_help(skb); 8580 goto csum_failed; 8581 } 8582 8583 /* update TX checksum flag */ 8584 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 8585 vlan_macip_lens = skb_checksum_start_offset(skb) - 8586 skb_network_offset(skb); 8587 no_csum: 8588 /* vlan_macip_lens: MACLEN, VLAN tag */ 8589 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 8590 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8591 8592 fceof_saidx |= itd->sa_idx; 8593 type_tucmd |= itd->flags | itd->trailer_len; 8594 8595 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0); 8596 } 8597 8598 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 8599 ((_flag <= _result) ? \ 8600 ((u32)(_input & _flag) * (_result / _flag)) : \ 8601 ((u32)(_input & _flag) / (_flag / _result))) 8602 8603 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 8604 { 8605 /* set type for advanced descriptor with frame checksum insertion */ 8606 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8607 IXGBE_ADVTXD_DCMD_DEXT | 8608 IXGBE_ADVTXD_DCMD_IFCS; 8609 8610 /* set HW vlan bit if vlan is present */ 8611 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 8612 IXGBE_ADVTXD_DCMD_VLE); 8613 8614 /* set segmentation enable bits for TSO/FSO */ 8615 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 8616 IXGBE_ADVTXD_DCMD_TSE); 8617 8618 /* set timestamp bit if present */ 8619 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 8620 IXGBE_ADVTXD_MAC_TSTAMP); 8621 8622 /* insert frame checksum */ 8623 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 8624 8625 return cmd_type; 8626 } 8627 8628 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 8629 u32 tx_flags, unsigned int paylen) 8630 { 8631 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 8632 8633 /* enable L4 checksum for TSO and TX checksum offload */ 8634 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8635 IXGBE_TX_FLAGS_CSUM, 8636 IXGBE_ADVTXD_POPTS_TXSM); 8637 8638 /* enable IPv4 checksum for TSO */ 8639 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8640 IXGBE_TX_FLAGS_IPV4, 8641 IXGBE_ADVTXD_POPTS_IXSM); 8642 8643 /* enable IPsec */ 8644 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8645 IXGBE_TX_FLAGS_IPSEC, 8646 IXGBE_ADVTXD_POPTS_IPSEC); 8647 8648 /* 8649 * Check Context must be set if Tx switch is enabled, which it 8650 * always is for case where virtual functions are running 8651 */ 8652 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8653 IXGBE_TX_FLAGS_CC, 8654 IXGBE_ADVTXD_CC); 8655 8656 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 8657 } 8658 8659 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8660 { 8661 if (!netif_subqueue_try_stop(tx_ring->netdev, tx_ring->queue_index, 8662 ixgbe_desc_unused(tx_ring), size)) 8663 return -EBUSY; 8664 8665 ++tx_ring->tx_stats.restart_queue; 8666 return 0; 8667 } 8668 8669 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8670 { 8671 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 8672 return 0; 8673 8674 return __ixgbe_maybe_stop_tx(tx_ring, size); 8675 } 8676 8677 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring, 8678 struct ixgbe_tx_buffer *first, 8679 const u8 hdr_len) 8680 { 8681 struct sk_buff *skb = first->skb; 8682 struct ixgbe_tx_buffer *tx_buffer; 8683 union ixgbe_adv_tx_desc *tx_desc; 8684 skb_frag_t *frag; 8685 dma_addr_t dma; 8686 unsigned int data_len, size; 8687 u32 tx_flags = first->tx_flags; 8688 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 8689 u16 i = tx_ring->next_to_use; 8690 8691 tx_desc = IXGBE_TX_DESC(tx_ring, i); 8692 8693 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 8694 8695 size = skb_headlen(skb); 8696 data_len = skb->data_len; 8697 8698 #ifdef IXGBE_FCOE 8699 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 8700 if (data_len < sizeof(struct fcoe_crc_eof)) { 8701 size -= sizeof(struct fcoe_crc_eof) - data_len; 8702 data_len = 0; 8703 } else { 8704 data_len -= sizeof(struct fcoe_crc_eof); 8705 } 8706 } 8707 8708 #endif 8709 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 8710 8711 tx_buffer = first; 8712 8713 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 8714 if (dma_mapping_error(tx_ring->dev, dma)) 8715 goto dma_error; 8716 8717 /* record length, and DMA address */ 8718 dma_unmap_len_set(tx_buffer, len, size); 8719 dma_unmap_addr_set(tx_buffer, dma, dma); 8720 8721 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8722 8723 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 8724 tx_desc->read.cmd_type_len = 8725 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 8726 8727 i++; 8728 tx_desc++; 8729 if (i == tx_ring->count) { 8730 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8731 i = 0; 8732 } 8733 tx_desc->read.olinfo_status = 0; 8734 8735 dma += IXGBE_MAX_DATA_PER_TXD; 8736 size -= IXGBE_MAX_DATA_PER_TXD; 8737 8738 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8739 } 8740 8741 if (likely(!data_len)) 8742 break; 8743 8744 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 8745 8746 i++; 8747 tx_desc++; 8748 if (i == tx_ring->count) { 8749 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8750 i = 0; 8751 } 8752 tx_desc->read.olinfo_status = 0; 8753 8754 #ifdef IXGBE_FCOE 8755 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 8756 #else 8757 size = skb_frag_size(frag); 8758 #endif 8759 data_len -= size; 8760 8761 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 8762 DMA_TO_DEVICE); 8763 8764 tx_buffer = &tx_ring->tx_buffer_info[i]; 8765 } 8766 8767 /* write last descriptor with RS and EOP bits */ 8768 cmd_type |= size | IXGBE_TXD_CMD; 8769 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8770 8771 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 8772 8773 /* set the timestamp */ 8774 first->time_stamp = jiffies; 8775 8776 skb_tx_timestamp(skb); 8777 8778 /* 8779 * Force memory writes to complete before letting h/w know there 8780 * are new descriptors to fetch. (Only applicable for weak-ordered 8781 * memory model archs, such as IA-64). 8782 * 8783 * We also need this memory barrier to make certain all of the 8784 * status bits have been updated before next_to_watch is written. 8785 */ 8786 wmb(); 8787 8788 /* set next_to_watch value indicating a packet is present */ 8789 first->next_to_watch = tx_desc; 8790 8791 i++; 8792 if (i == tx_ring->count) 8793 i = 0; 8794 8795 tx_ring->next_to_use = i; 8796 8797 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 8798 8799 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 8800 writel(i, tx_ring->tail); 8801 } 8802 8803 return 0; 8804 dma_error: 8805 dev_err(tx_ring->dev, "TX DMA map failed\n"); 8806 8807 /* clear dma mappings for failed tx_buffer_info map */ 8808 for (;;) { 8809 tx_buffer = &tx_ring->tx_buffer_info[i]; 8810 if (dma_unmap_len(tx_buffer, len)) 8811 dma_unmap_page(tx_ring->dev, 8812 dma_unmap_addr(tx_buffer, dma), 8813 dma_unmap_len(tx_buffer, len), 8814 DMA_TO_DEVICE); 8815 dma_unmap_len_set(tx_buffer, len, 0); 8816 if (tx_buffer == first) 8817 break; 8818 if (i == 0) 8819 i += tx_ring->count; 8820 i--; 8821 } 8822 8823 dev_kfree_skb_any(first->skb); 8824 first->skb = NULL; 8825 8826 tx_ring->next_to_use = i; 8827 8828 return -1; 8829 } 8830 8831 static void ixgbe_atr(struct ixgbe_ring *ring, 8832 struct ixgbe_tx_buffer *first) 8833 { 8834 struct ixgbe_q_vector *q_vector = ring->q_vector; 8835 union ixgbe_atr_hash_dword input = { .dword = 0 }; 8836 union ixgbe_atr_hash_dword common = { .dword = 0 }; 8837 union { 8838 unsigned char *network; 8839 struct iphdr *ipv4; 8840 struct ipv6hdr *ipv6; 8841 } hdr; 8842 struct tcphdr *th; 8843 unsigned int hlen; 8844 struct sk_buff *skb; 8845 __be16 vlan_id; 8846 int l4_proto; 8847 8848 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 8849 if (!q_vector) 8850 return; 8851 8852 /* do nothing if sampling is disabled */ 8853 if (!ring->atr_sample_rate) 8854 return; 8855 8856 ring->atr_count++; 8857 8858 /* currently only IPv4/IPv6 with TCP is supported */ 8859 if ((first->protocol != htons(ETH_P_IP)) && 8860 (first->protocol != htons(ETH_P_IPV6))) 8861 return; 8862 8863 /* snag network header to get L4 type and address */ 8864 skb = first->skb; 8865 hdr.network = skb_network_header(skb); 8866 if (unlikely(hdr.network <= skb->data)) 8867 return; 8868 if (skb->encapsulation && 8869 first->protocol == htons(ETH_P_IP) && 8870 hdr.ipv4->protocol == IPPROTO_UDP) { 8871 struct ixgbe_adapter *adapter = q_vector->adapter; 8872 8873 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8874 vxlan_headroom(0))) 8875 return; 8876 8877 /* verify the port is recognized as VXLAN */ 8878 if (adapter->vxlan_port && 8879 udp_hdr(skb)->dest == adapter->vxlan_port) 8880 hdr.network = skb_inner_network_header(skb); 8881 8882 if (adapter->geneve_port && 8883 udp_hdr(skb)->dest == adapter->geneve_port) 8884 hdr.network = skb_inner_network_header(skb); 8885 } 8886 8887 /* Make sure we have at least [minimum IPv4 header + TCP] 8888 * or [IPv6 header] bytes 8889 */ 8890 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40)) 8891 return; 8892 8893 /* Currently only IPv4/IPv6 with TCP is supported */ 8894 switch (hdr.ipv4->version) { 8895 case IPVERSION: 8896 /* access ihl as u8 to avoid unaligned access on ia64 */ 8897 hlen = (hdr.network[0] & 0x0F) << 2; 8898 l4_proto = hdr.ipv4->protocol; 8899 break; 8900 case 6: 8901 hlen = hdr.network - skb->data; 8902 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 8903 hlen -= hdr.network - skb->data; 8904 break; 8905 default: 8906 return; 8907 } 8908 8909 if (l4_proto != IPPROTO_TCP) 8910 return; 8911 8912 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8913 hlen + sizeof(struct tcphdr))) 8914 return; 8915 8916 th = (struct tcphdr *)(hdr.network + hlen); 8917 8918 /* skip this packet since the socket is closing */ 8919 if (th->fin) 8920 return; 8921 8922 /* sample on all syn packets or once every atr sample count */ 8923 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 8924 return; 8925 8926 /* reset sample count */ 8927 ring->atr_count = 0; 8928 8929 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 8930 8931 /* 8932 * src and dst are inverted, think how the receiver sees them 8933 * 8934 * The input is broken into two sections, a non-compressed section 8935 * containing vm_pool, vlan_id, and flow_type. The rest of the data 8936 * is XORed together and stored in the compressed dword. 8937 */ 8938 input.formatted.vlan_id = vlan_id; 8939 8940 /* 8941 * since src port and flex bytes occupy the same word XOR them together 8942 * and write the value to source port portion of compressed dword 8943 */ 8944 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 8945 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 8946 else 8947 common.port.src ^= th->dest ^ first->protocol; 8948 common.port.dst ^= th->source; 8949 8950 switch (hdr.ipv4->version) { 8951 case IPVERSION: 8952 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 8953 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 8954 break; 8955 case 6: 8956 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 8957 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 8958 hdr.ipv6->saddr.s6_addr32[1] ^ 8959 hdr.ipv6->saddr.s6_addr32[2] ^ 8960 hdr.ipv6->saddr.s6_addr32[3] ^ 8961 hdr.ipv6->daddr.s6_addr32[0] ^ 8962 hdr.ipv6->daddr.s6_addr32[1] ^ 8963 hdr.ipv6->daddr.s6_addr32[2] ^ 8964 hdr.ipv6->daddr.s6_addr32[3]; 8965 break; 8966 default: 8967 break; 8968 } 8969 8970 if (hdr.network != skb_network_header(skb)) 8971 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 8972 8973 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 8974 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 8975 input, common, ring->queue_index); 8976 } 8977 8978 #ifdef IXGBE_FCOE 8979 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 8980 struct net_device *sb_dev) 8981 { 8982 struct ixgbe_adapter *adapter; 8983 struct ixgbe_ring_feature *f; 8984 int txq; 8985 8986 if (sb_dev) { 8987 u8 tc = netdev_get_prio_tc_map(dev, skb->priority); 8988 struct net_device *vdev = sb_dev; 8989 8990 txq = vdev->tc_to_txq[tc].offset; 8991 txq += reciprocal_scale(skb_get_hash(skb), 8992 vdev->tc_to_txq[tc].count); 8993 8994 return txq; 8995 } 8996 8997 /* 8998 * only execute the code below if protocol is FCoE 8999 * or FIP and we have FCoE enabled on the adapter 9000 */ 9001 switch (vlan_get_protocol(skb)) { 9002 case htons(ETH_P_FCOE): 9003 case htons(ETH_P_FIP): 9004 adapter = netdev_priv(dev); 9005 9006 if (!sb_dev && (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) 9007 break; 9008 fallthrough; 9009 default: 9010 return netdev_pick_tx(dev, skb, sb_dev); 9011 } 9012 9013 f = &adapter->ring_feature[RING_F_FCOE]; 9014 9015 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 9016 smp_processor_id(); 9017 9018 while (txq >= f->indices) 9019 txq -= f->indices; 9020 9021 return txq + f->offset; 9022 } 9023 9024 #endif 9025 int ixgbe_xmit_xdp_ring(struct ixgbe_ring *ring, 9026 struct xdp_frame *xdpf) 9027 { 9028 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 9029 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 9030 u16 i = 0, index = ring->next_to_use; 9031 struct ixgbe_tx_buffer *tx_head = &ring->tx_buffer_info[index]; 9032 struct ixgbe_tx_buffer *tx_buff = tx_head; 9033 union ixgbe_adv_tx_desc *tx_desc = IXGBE_TX_DESC(ring, index); 9034 u32 cmd_type, len = xdpf->len; 9035 void *data = xdpf->data; 9036 9037 if (unlikely(ixgbe_desc_unused(ring) < 1 + nr_frags)) 9038 return IXGBE_XDP_CONSUMED; 9039 9040 tx_head->bytecount = xdp_get_frame_len(xdpf); 9041 tx_head->gso_segs = 1; 9042 tx_head->xdpf = xdpf; 9043 9044 tx_desc->read.olinfo_status = 9045 cpu_to_le32(tx_head->bytecount << IXGBE_ADVTXD_PAYLEN_SHIFT); 9046 9047 for (;;) { 9048 dma_addr_t dma; 9049 9050 dma = dma_map_single(ring->dev, data, len, DMA_TO_DEVICE); 9051 if (dma_mapping_error(ring->dev, dma)) 9052 goto unmap; 9053 9054 dma_unmap_len_set(tx_buff, len, len); 9055 dma_unmap_addr_set(tx_buff, dma, dma); 9056 9057 cmd_type = IXGBE_ADVTXD_DTYP_DATA | IXGBE_ADVTXD_DCMD_DEXT | 9058 IXGBE_ADVTXD_DCMD_IFCS | len; 9059 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 9060 tx_desc->read.buffer_addr = cpu_to_le64(dma); 9061 tx_buff->protocol = 0; 9062 9063 if (++index == ring->count) 9064 index = 0; 9065 9066 if (i == nr_frags) 9067 break; 9068 9069 tx_buff = &ring->tx_buffer_info[index]; 9070 tx_desc = IXGBE_TX_DESC(ring, index); 9071 tx_desc->read.olinfo_status = 0; 9072 9073 data = skb_frag_address(&sinfo->frags[i]); 9074 len = skb_frag_size(&sinfo->frags[i]); 9075 i++; 9076 } 9077 /* put descriptor type bits */ 9078 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD); 9079 9080 /* Avoid any potential race with xdp_xmit and cleanup */ 9081 smp_wmb(); 9082 9083 tx_head->next_to_watch = tx_desc; 9084 ring->next_to_use = index; 9085 9086 return IXGBE_XDP_TX; 9087 9088 unmap: 9089 for (;;) { 9090 tx_buff = &ring->tx_buffer_info[index]; 9091 if (dma_unmap_len(tx_buff, len)) 9092 dma_unmap_page(ring->dev, dma_unmap_addr(tx_buff, dma), 9093 dma_unmap_len(tx_buff, len), 9094 DMA_TO_DEVICE); 9095 dma_unmap_len_set(tx_buff, len, 0); 9096 if (tx_buff == tx_head) 9097 break; 9098 9099 if (!index) 9100 index += ring->count; 9101 index--; 9102 } 9103 9104 return IXGBE_XDP_CONSUMED; 9105 } 9106 9107 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 9108 struct ixgbe_adapter *adapter, 9109 struct ixgbe_ring *tx_ring) 9110 { 9111 struct ixgbe_tx_buffer *first; 9112 int tso; 9113 u32 tx_flags = 0; 9114 unsigned short f; 9115 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 9116 struct ixgbe_ipsec_tx_data ipsec_tx = { 0 }; 9117 __be16 protocol = skb->protocol; 9118 u8 hdr_len = 0; 9119 9120 /* 9121 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 9122 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 9123 * + 2 desc gap to keep tail from touching head, 9124 * + 1 desc for context descriptor, 9125 * otherwise try next time 9126 */ 9127 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 9128 count += TXD_USE_COUNT(skb_frag_size( 9129 &skb_shinfo(skb)->frags[f])); 9130 9131 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 9132 tx_ring->tx_stats.tx_busy++; 9133 return NETDEV_TX_BUSY; 9134 } 9135 9136 /* record the location of the first descriptor for this packet */ 9137 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 9138 first->skb = skb; 9139 first->bytecount = skb->len; 9140 first->gso_segs = 1; 9141 9142 /* if we have a HW VLAN tag being added default to the HW one */ 9143 if (skb_vlan_tag_present(skb)) { 9144 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 9145 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 9146 /* else if it is a SW VLAN check the next protocol and store the tag */ 9147 } else if (protocol == htons(ETH_P_8021Q)) { 9148 struct vlan_hdr *vhdr, _vhdr; 9149 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 9150 if (!vhdr) 9151 goto out_drop; 9152 9153 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 9154 IXGBE_TX_FLAGS_VLAN_SHIFT; 9155 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 9156 } 9157 protocol = vlan_get_protocol(skb); 9158 9159 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 9160 adapter->ptp_clock) { 9161 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 9162 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 9163 &adapter->state)) { 9164 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 9165 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 9166 9167 /* schedule check for Tx timestamp */ 9168 adapter->ptp_tx_skb = skb_get(skb); 9169 adapter->ptp_tx_start = jiffies; 9170 schedule_work(&adapter->ptp_tx_work); 9171 } else { 9172 adapter->tx_hwtstamp_skipped++; 9173 } 9174 } 9175 9176 #ifdef CONFIG_PCI_IOV 9177 /* 9178 * Use the l2switch_enable flag - would be false if the DMA 9179 * Tx switch had been disabled. 9180 */ 9181 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 9182 tx_flags |= IXGBE_TX_FLAGS_CC; 9183 9184 #endif 9185 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 9186 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 9187 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 9188 (skb->priority != TC_PRIO_CONTROL))) { 9189 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 9190 tx_flags |= (skb->priority & 0x7) << 9191 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 9192 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 9193 struct vlan_ethhdr *vhdr; 9194 9195 if (skb_cow_head(skb, 0)) 9196 goto out_drop; 9197 vhdr = skb_vlan_eth_hdr(skb); 9198 vhdr->h_vlan_TCI = htons(tx_flags >> 9199 IXGBE_TX_FLAGS_VLAN_SHIFT); 9200 } else { 9201 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 9202 } 9203 } 9204 9205 /* record initial flags and protocol */ 9206 first->tx_flags = tx_flags; 9207 first->protocol = protocol; 9208 9209 #ifdef IXGBE_FCOE 9210 /* setup tx offload for FCoE */ 9211 if ((protocol == htons(ETH_P_FCOE)) && 9212 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 9213 tso = ixgbe_fso(tx_ring, first, &hdr_len); 9214 if (tso < 0) 9215 goto out_drop; 9216 9217 goto xmit_fcoe; 9218 } 9219 9220 #endif /* IXGBE_FCOE */ 9221 9222 #ifdef CONFIG_IXGBE_IPSEC 9223 if (xfrm_offload(skb) && 9224 !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx)) 9225 goto out_drop; 9226 #endif 9227 tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx); 9228 if (tso < 0) 9229 goto out_drop; 9230 else if (!tso) 9231 ixgbe_tx_csum(tx_ring, first, &ipsec_tx); 9232 9233 /* add the ATR filter if ATR is on */ 9234 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 9235 ixgbe_atr(tx_ring, first); 9236 9237 #ifdef IXGBE_FCOE 9238 xmit_fcoe: 9239 #endif /* IXGBE_FCOE */ 9240 if (ixgbe_tx_map(tx_ring, first, hdr_len)) 9241 goto cleanup_tx_timestamp; 9242 9243 return NETDEV_TX_OK; 9244 9245 out_drop: 9246 dev_kfree_skb_any(first->skb); 9247 first->skb = NULL; 9248 cleanup_tx_timestamp: 9249 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) { 9250 dev_kfree_skb_any(adapter->ptp_tx_skb); 9251 adapter->ptp_tx_skb = NULL; 9252 cancel_work_sync(&adapter->ptp_tx_work); 9253 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state); 9254 } 9255 9256 return NETDEV_TX_OK; 9257 } 9258 9259 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 9260 struct net_device *netdev, 9261 struct ixgbe_ring *ring) 9262 { 9263 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9264 struct ixgbe_ring *tx_ring; 9265 9266 /* 9267 * The minimum packet size for olinfo paylen is 17 so pad the skb 9268 * in order to meet this minimum size requirement. 9269 */ 9270 if (skb_put_padto(skb, 17)) 9271 return NETDEV_TX_OK; 9272 9273 tx_ring = ring ? ring : adapter->tx_ring[skb_get_queue_mapping(skb)]; 9274 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &tx_ring->state))) 9275 return NETDEV_TX_BUSY; 9276 9277 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 9278 } 9279 9280 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 9281 struct net_device *netdev) 9282 { 9283 return __ixgbe_xmit_frame(skb, netdev, NULL); 9284 } 9285 9286 /** 9287 * ixgbe_set_mac - Change the Ethernet Address of the NIC 9288 * @netdev: network interface device structure 9289 * @p: pointer to an address structure 9290 * 9291 * Returns 0 on success, negative on failure 9292 **/ 9293 static int ixgbe_set_mac(struct net_device *netdev, void *p) 9294 { 9295 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9296 struct ixgbe_hw *hw = &adapter->hw; 9297 struct sockaddr *addr = p; 9298 9299 if (!is_valid_ether_addr(addr->sa_data)) 9300 return -EADDRNOTAVAIL; 9301 9302 eth_hw_addr_set(netdev, addr->sa_data); 9303 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 9304 9305 ixgbe_mac_set_default_filter(adapter); 9306 9307 return 0; 9308 } 9309 9310 static int 9311 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 9312 { 9313 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9314 struct ixgbe_hw *hw = &adapter->hw; 9315 u16 value; 9316 int rc; 9317 9318 if (adapter->mii_bus) { 9319 int regnum = addr; 9320 9321 if (devad != MDIO_DEVAD_NONE) 9322 return mdiobus_c45_read(adapter->mii_bus, prtad, 9323 devad, regnum); 9324 9325 return mdiobus_read(adapter->mii_bus, prtad, regnum); 9326 } 9327 9328 if (prtad != hw->phy.mdio.prtad) 9329 return -EINVAL; 9330 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 9331 if (!rc) 9332 rc = value; 9333 return rc; 9334 } 9335 9336 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 9337 u16 addr, u16 value) 9338 { 9339 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9340 struct ixgbe_hw *hw = &adapter->hw; 9341 9342 if (adapter->mii_bus) { 9343 int regnum = addr; 9344 9345 if (devad != MDIO_DEVAD_NONE) 9346 return mdiobus_c45_write(adapter->mii_bus, prtad, devad, 9347 regnum, value); 9348 9349 return mdiobus_write(adapter->mii_bus, prtad, regnum, value); 9350 } 9351 9352 if (prtad != hw->phy.mdio.prtad) 9353 return -EINVAL; 9354 return hw->phy.ops.write_reg(hw, addr, devad, value); 9355 } 9356 9357 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 9358 { 9359 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9360 9361 switch (cmd) { 9362 case SIOCSHWTSTAMP: 9363 return ixgbe_ptp_set_ts_config(adapter, req); 9364 case SIOCGHWTSTAMP: 9365 return ixgbe_ptp_get_ts_config(adapter, req); 9366 case SIOCGMIIPHY: 9367 if (!adapter->hw.phy.ops.read_reg) 9368 return -EOPNOTSUPP; 9369 fallthrough; 9370 default: 9371 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 9372 } 9373 } 9374 9375 /** 9376 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 9377 * netdev->dev_addrs 9378 * @dev: network interface device structure 9379 * 9380 * Returns non-zero on failure 9381 **/ 9382 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 9383 { 9384 int err = 0; 9385 struct ixgbe_adapter *adapter = netdev_priv(dev); 9386 struct ixgbe_hw *hw = &adapter->hw; 9387 9388 if (is_valid_ether_addr(hw->mac.san_addr)) { 9389 rtnl_lock(); 9390 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 9391 rtnl_unlock(); 9392 9393 /* update SAN MAC vmdq pool selection */ 9394 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 9395 } 9396 return err; 9397 } 9398 9399 /** 9400 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 9401 * netdev->dev_addrs 9402 * @dev: network interface device structure 9403 * 9404 * Returns non-zero on failure 9405 **/ 9406 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 9407 { 9408 int err = 0; 9409 struct ixgbe_adapter *adapter = netdev_priv(dev); 9410 struct ixgbe_mac_info *mac = &adapter->hw.mac; 9411 9412 if (is_valid_ether_addr(mac->san_addr)) { 9413 rtnl_lock(); 9414 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 9415 rtnl_unlock(); 9416 } 9417 return err; 9418 } 9419 9420 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats, 9421 struct ixgbe_ring *ring) 9422 { 9423 u64 bytes, packets; 9424 unsigned int start; 9425 9426 if (ring) { 9427 do { 9428 start = u64_stats_fetch_begin(&ring->syncp); 9429 packets = ring->stats.packets; 9430 bytes = ring->stats.bytes; 9431 } while (u64_stats_fetch_retry(&ring->syncp, start)); 9432 stats->tx_packets += packets; 9433 stats->tx_bytes += bytes; 9434 } 9435 } 9436 9437 static void ixgbe_get_stats64(struct net_device *netdev, 9438 struct rtnl_link_stats64 *stats) 9439 { 9440 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9441 int i; 9442 9443 rcu_read_lock(); 9444 for (i = 0; i < adapter->num_rx_queues; i++) { 9445 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]); 9446 u64 bytes, packets; 9447 unsigned int start; 9448 9449 if (ring) { 9450 do { 9451 start = u64_stats_fetch_begin(&ring->syncp); 9452 packets = ring->stats.packets; 9453 bytes = ring->stats.bytes; 9454 } while (u64_stats_fetch_retry(&ring->syncp, start)); 9455 stats->rx_packets += packets; 9456 stats->rx_bytes += bytes; 9457 } 9458 } 9459 9460 for (i = 0; i < adapter->num_tx_queues; i++) { 9461 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]); 9462 9463 ixgbe_get_ring_stats64(stats, ring); 9464 } 9465 for (i = 0; i < adapter->num_xdp_queues; i++) { 9466 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]); 9467 9468 ixgbe_get_ring_stats64(stats, ring); 9469 } 9470 rcu_read_unlock(); 9471 9472 /* following stats updated by ixgbe_watchdog_task() */ 9473 stats->multicast = netdev->stats.multicast; 9474 stats->rx_errors = netdev->stats.rx_errors; 9475 stats->rx_length_errors = netdev->stats.rx_length_errors; 9476 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 9477 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 9478 } 9479 9480 static int ixgbe_ndo_get_vf_stats(struct net_device *netdev, int vf, 9481 struct ifla_vf_stats *vf_stats) 9482 { 9483 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9484 9485 if (vf < 0 || vf >= adapter->num_vfs) 9486 return -EINVAL; 9487 9488 vf_stats->rx_packets = adapter->vfinfo[vf].vfstats.gprc; 9489 vf_stats->rx_bytes = adapter->vfinfo[vf].vfstats.gorc; 9490 vf_stats->tx_packets = adapter->vfinfo[vf].vfstats.gptc; 9491 vf_stats->tx_bytes = adapter->vfinfo[vf].vfstats.gotc; 9492 vf_stats->multicast = adapter->vfinfo[vf].vfstats.mprc; 9493 9494 return 0; 9495 } 9496 9497 #ifdef CONFIG_IXGBE_DCB 9498 /** 9499 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 9500 * @adapter: pointer to ixgbe_adapter 9501 * @tc: number of traffic classes currently enabled 9502 * 9503 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 9504 * 802.1Q priority maps to a packet buffer that exists. 9505 */ 9506 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 9507 { 9508 struct ixgbe_hw *hw = &adapter->hw; 9509 u32 reg, rsave; 9510 int i; 9511 9512 /* 82598 have a static priority to TC mapping that can not 9513 * be changed so no validation is needed. 9514 */ 9515 if (hw->mac.type == ixgbe_mac_82598EB) 9516 return; 9517 9518 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 9519 rsave = reg; 9520 9521 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 9522 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 9523 9524 /* If up2tc is out of bounds default to zero */ 9525 if (up2tc > tc) 9526 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 9527 } 9528 9529 if (reg != rsave) 9530 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 9531 9532 return; 9533 } 9534 9535 /** 9536 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 9537 * @adapter: Pointer to adapter struct 9538 * 9539 * Populate the netdev user priority to tc map 9540 */ 9541 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 9542 { 9543 struct net_device *dev = adapter->netdev; 9544 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 9545 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 9546 u8 prio; 9547 9548 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 9549 u8 tc = 0; 9550 9551 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 9552 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 9553 else if (ets) 9554 tc = ets->prio_tc[prio]; 9555 9556 netdev_set_prio_tc_map(dev, prio, tc); 9557 } 9558 } 9559 9560 #endif /* CONFIG_IXGBE_DCB */ 9561 static int ixgbe_reassign_macvlan_pool(struct net_device *vdev, 9562 struct netdev_nested_priv *priv) 9563 { 9564 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data; 9565 struct ixgbe_fwd_adapter *accel; 9566 int pool; 9567 9568 /* we only care about macvlans... */ 9569 if (!netif_is_macvlan(vdev)) 9570 return 0; 9571 9572 /* that have hardware offload enabled... */ 9573 accel = macvlan_accel_priv(vdev); 9574 if (!accel) 9575 return 0; 9576 9577 /* If we can relocate to a different bit do so */ 9578 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 9579 if (pool < adapter->num_rx_pools) { 9580 set_bit(pool, adapter->fwd_bitmask); 9581 accel->pool = pool; 9582 return 0; 9583 } 9584 9585 /* if we cannot find a free pool then disable the offload */ 9586 netdev_err(vdev, "L2FW offload disabled due to lack of queue resources\n"); 9587 macvlan_release_l2fw_offload(vdev); 9588 9589 /* unbind the queues and drop the subordinate channel config */ 9590 netdev_unbind_sb_channel(adapter->netdev, vdev); 9591 netdev_set_sb_channel(vdev, 0); 9592 9593 kfree(accel); 9594 9595 return 0; 9596 } 9597 9598 static void ixgbe_defrag_macvlan_pools(struct net_device *dev) 9599 { 9600 struct ixgbe_adapter *adapter = netdev_priv(dev); 9601 struct netdev_nested_priv priv = { 9602 .data = (void *)adapter, 9603 }; 9604 9605 /* flush any stale bits out of the fwd bitmask */ 9606 bitmap_clear(adapter->fwd_bitmask, 1, 63); 9607 9608 /* walk through upper devices reassigning pools */ 9609 netdev_walk_all_upper_dev_rcu(dev, ixgbe_reassign_macvlan_pool, 9610 &priv); 9611 } 9612 9613 /** 9614 * ixgbe_setup_tc - configure net_device for multiple traffic classes 9615 * 9616 * @dev: net device to configure 9617 * @tc: number of traffic classes to enable 9618 */ 9619 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 9620 { 9621 struct ixgbe_adapter *adapter = netdev_priv(dev); 9622 struct ixgbe_hw *hw = &adapter->hw; 9623 9624 /* Hardware supports up to 8 traffic classes */ 9625 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 9626 return -EINVAL; 9627 9628 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 9629 return -EINVAL; 9630 9631 /* Hardware has to reinitialize queues and interrupts to 9632 * match packet buffer alignment. Unfortunately, the 9633 * hardware is not flexible enough to do this dynamically. 9634 */ 9635 if (netif_running(dev)) 9636 ixgbe_close(dev); 9637 else 9638 ixgbe_reset(adapter); 9639 9640 ixgbe_clear_interrupt_scheme(adapter); 9641 9642 #ifdef CONFIG_IXGBE_DCB 9643 if (tc) { 9644 if (adapter->xdp_prog) { 9645 e_warn(probe, "DCB is not supported with XDP\n"); 9646 9647 ixgbe_init_interrupt_scheme(adapter); 9648 if (netif_running(dev)) 9649 ixgbe_open(dev); 9650 return -EINVAL; 9651 } 9652 9653 netdev_set_num_tc(dev, tc); 9654 ixgbe_set_prio_tc_map(adapter); 9655 9656 adapter->hw_tcs = tc; 9657 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 9658 9659 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 9660 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 9661 adapter->hw.fc.requested_mode = ixgbe_fc_none; 9662 } 9663 } else { 9664 netdev_reset_tc(dev); 9665 9666 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 9667 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 9668 9669 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 9670 adapter->hw_tcs = tc; 9671 9672 adapter->temp_dcb_cfg.pfc_mode_enable = false; 9673 adapter->dcb_cfg.pfc_mode_enable = false; 9674 } 9675 9676 ixgbe_validate_rtr(adapter, tc); 9677 9678 #endif /* CONFIG_IXGBE_DCB */ 9679 ixgbe_init_interrupt_scheme(adapter); 9680 9681 ixgbe_defrag_macvlan_pools(dev); 9682 9683 if (netif_running(dev)) 9684 return ixgbe_open(dev); 9685 9686 return 0; 9687 } 9688 9689 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, 9690 struct tc_cls_u32_offload *cls) 9691 { 9692 u32 hdl = cls->knode.handle; 9693 u32 uhtid = TC_U32_USERHTID(cls->knode.handle); 9694 u32 loc = cls->knode.handle & 0xfffff; 9695 int err = 0, i, j; 9696 struct ixgbe_jump_table *jump = NULL; 9697 9698 if (loc > IXGBE_MAX_HW_ENTRIES) 9699 return -EINVAL; 9700 9701 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) 9702 return -EINVAL; 9703 9704 /* Clear this filter in the link data it is associated with */ 9705 if (uhtid != 0x800) { 9706 jump = adapter->jump_tables[uhtid]; 9707 if (!jump) 9708 return -EINVAL; 9709 if (!test_bit(loc - 1, jump->child_loc_map)) 9710 return -EINVAL; 9711 clear_bit(loc - 1, jump->child_loc_map); 9712 } 9713 9714 /* Check if the filter being deleted is a link */ 9715 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9716 jump = adapter->jump_tables[i]; 9717 if (jump && jump->link_hdl == hdl) { 9718 /* Delete filters in the hardware in the child hash 9719 * table associated with this link 9720 */ 9721 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) { 9722 if (!test_bit(j, jump->child_loc_map)) 9723 continue; 9724 spin_lock(&adapter->fdir_perfect_lock); 9725 err = ixgbe_update_ethtool_fdir_entry(adapter, 9726 NULL, 9727 j + 1); 9728 spin_unlock(&adapter->fdir_perfect_lock); 9729 clear_bit(j, jump->child_loc_map); 9730 } 9731 /* Remove resources for this link */ 9732 kfree(jump->input); 9733 kfree(jump->mask); 9734 kfree(jump); 9735 adapter->jump_tables[i] = NULL; 9736 return err; 9737 } 9738 } 9739 9740 spin_lock(&adapter->fdir_perfect_lock); 9741 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); 9742 spin_unlock(&adapter->fdir_perfect_lock); 9743 return err; 9744 } 9745 9746 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, 9747 struct tc_cls_u32_offload *cls) 9748 { 9749 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9750 9751 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9752 return -EINVAL; 9753 9754 /* This ixgbe devices do not support hash tables at the moment 9755 * so abort when given hash tables. 9756 */ 9757 if (cls->hnode.divisor > 0) 9758 return -EINVAL; 9759 9760 set_bit(uhtid - 1, &adapter->tables); 9761 return 0; 9762 } 9763 9764 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, 9765 struct tc_cls_u32_offload *cls) 9766 { 9767 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9768 9769 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9770 return -EINVAL; 9771 9772 clear_bit(uhtid - 1, &adapter->tables); 9773 return 0; 9774 } 9775 9776 #ifdef CONFIG_NET_CLS_ACT 9777 struct upper_walk_data { 9778 struct ixgbe_adapter *adapter; 9779 u64 action; 9780 int ifindex; 9781 u8 queue; 9782 }; 9783 9784 static int get_macvlan_queue(struct net_device *upper, 9785 struct netdev_nested_priv *priv) 9786 { 9787 if (netif_is_macvlan(upper)) { 9788 struct ixgbe_fwd_adapter *vadapter = macvlan_accel_priv(upper); 9789 struct ixgbe_adapter *adapter; 9790 struct upper_walk_data *data; 9791 int ifindex; 9792 9793 data = (struct upper_walk_data *)priv->data; 9794 ifindex = data->ifindex; 9795 adapter = data->adapter; 9796 if (vadapter && upper->ifindex == ifindex) { 9797 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; 9798 data->action = data->queue; 9799 return 1; 9800 } 9801 } 9802 9803 return 0; 9804 } 9805 9806 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, 9807 u8 *queue, u64 *action) 9808 { 9809 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 9810 unsigned int num_vfs = adapter->num_vfs, vf; 9811 struct netdev_nested_priv priv; 9812 struct upper_walk_data data; 9813 struct net_device *upper; 9814 9815 /* redirect to a SRIOV VF */ 9816 for (vf = 0; vf < num_vfs; ++vf) { 9817 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); 9818 if (upper->ifindex == ifindex) { 9819 *queue = vf * __ALIGN_MASK(1, ~vmdq->mask); 9820 *action = vf + 1; 9821 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 9822 return 0; 9823 } 9824 } 9825 9826 /* redirect to a offloaded macvlan netdev */ 9827 data.adapter = adapter; 9828 data.ifindex = ifindex; 9829 data.action = 0; 9830 data.queue = 0; 9831 priv.data = (void *)&data; 9832 if (netdev_walk_all_upper_dev_rcu(adapter->netdev, 9833 get_macvlan_queue, &priv)) { 9834 *action = data.action; 9835 *queue = data.queue; 9836 9837 return 0; 9838 } 9839 9840 return -EINVAL; 9841 } 9842 9843 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9844 struct tcf_exts *exts, u64 *action, u8 *queue) 9845 { 9846 const struct tc_action *a; 9847 int i; 9848 9849 if (!tcf_exts_has_actions(exts)) 9850 return -EINVAL; 9851 9852 tcf_exts_for_each_action(i, a, exts) { 9853 /* Drop action */ 9854 if (is_tcf_gact_shot(a)) { 9855 *action = IXGBE_FDIR_DROP_QUEUE; 9856 *queue = IXGBE_FDIR_DROP_QUEUE; 9857 return 0; 9858 } 9859 9860 /* Redirect to a VF or a offloaded macvlan */ 9861 if (is_tcf_mirred_egress_redirect(a)) { 9862 struct net_device *dev = tcf_mirred_dev(a); 9863 9864 if (!dev) 9865 return -EINVAL; 9866 return handle_redirect_action(adapter, dev->ifindex, 9867 queue, action); 9868 } 9869 9870 return -EINVAL; 9871 } 9872 9873 return -EINVAL; 9874 } 9875 #else 9876 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9877 struct tcf_exts *exts, u64 *action, u8 *queue) 9878 { 9879 return -EINVAL; 9880 } 9881 #endif /* CONFIG_NET_CLS_ACT */ 9882 9883 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, 9884 union ixgbe_atr_input *mask, 9885 struct tc_cls_u32_offload *cls, 9886 struct ixgbe_mat_field *field_ptr, 9887 struct ixgbe_nexthdr *nexthdr) 9888 { 9889 int i, j, off; 9890 __be32 val, m; 9891 bool found_entry = false, found_jump_field = false; 9892 9893 for (i = 0; i < cls->knode.sel->nkeys; i++) { 9894 off = cls->knode.sel->keys[i].off; 9895 val = cls->knode.sel->keys[i].val; 9896 m = cls->knode.sel->keys[i].mask; 9897 9898 for (j = 0; field_ptr[j].val; j++) { 9899 if (field_ptr[j].off == off) { 9900 field_ptr[j].val(input, mask, (__force u32)val, 9901 (__force u32)m); 9902 input->filter.formatted.flow_type |= 9903 field_ptr[j].type; 9904 found_entry = true; 9905 break; 9906 } 9907 } 9908 if (nexthdr) { 9909 if (nexthdr->off == cls->knode.sel->keys[i].off && 9910 nexthdr->val == 9911 (__force u32)cls->knode.sel->keys[i].val && 9912 nexthdr->mask == 9913 (__force u32)cls->knode.sel->keys[i].mask) 9914 found_jump_field = true; 9915 else 9916 continue; 9917 } 9918 } 9919 9920 if (nexthdr && !found_jump_field) 9921 return -EINVAL; 9922 9923 if (!found_entry) 9924 return 0; 9925 9926 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 9927 IXGBE_ATR_L4TYPE_MASK; 9928 9929 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 9930 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 9931 9932 return 0; 9933 } 9934 9935 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, 9936 struct tc_cls_u32_offload *cls) 9937 { 9938 __be16 protocol = cls->common.protocol; 9939 u32 loc = cls->knode.handle & 0xfffff; 9940 struct ixgbe_hw *hw = &adapter->hw; 9941 struct ixgbe_mat_field *field_ptr; 9942 struct ixgbe_fdir_filter *input = NULL; 9943 union ixgbe_atr_input *mask = NULL; 9944 struct ixgbe_jump_table *jump = NULL; 9945 int i, err = -EINVAL; 9946 u8 queue; 9947 u32 uhtid, link_uhtid; 9948 9949 uhtid = TC_U32_USERHTID(cls->knode.handle); 9950 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); 9951 9952 /* At the moment cls_u32 jumps to network layer and skips past 9953 * L2 headers. The canonical method to match L2 frames is to use 9954 * negative values. However this is error prone at best but really 9955 * just broken because there is no way to "know" what sort of hdr 9956 * is in front of the network layer. Fix cls_u32 to support L2 9957 * headers when needed. 9958 */ 9959 if (protocol != htons(ETH_P_IP)) 9960 return err; 9961 9962 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { 9963 e_err(drv, "Location out of range\n"); 9964 return err; 9965 } 9966 9967 /* cls u32 is a graph starting at root node 0x800. The driver tracks 9968 * links and also the fields used to advance the parser across each 9969 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map 9970 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h 9971 * To add support for new nodes update ixgbe_model.h parse structures 9972 * this function _should_ be generic try not to hardcode values here. 9973 */ 9974 if (uhtid == 0x800) { 9975 field_ptr = (adapter->jump_tables[0])->mat; 9976 } else { 9977 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9978 return err; 9979 if (!adapter->jump_tables[uhtid]) 9980 return err; 9981 field_ptr = (adapter->jump_tables[uhtid])->mat; 9982 } 9983 9984 if (!field_ptr) 9985 return err; 9986 9987 /* At this point we know the field_ptr is valid and need to either 9988 * build cls_u32 link or attach filter. Because adding a link to 9989 * a handle that does not exist is invalid and the same for adding 9990 * rules to handles that don't exist. 9991 */ 9992 9993 if (link_uhtid) { 9994 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; 9995 9996 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) 9997 return err; 9998 9999 if (!test_bit(link_uhtid - 1, &adapter->tables)) 10000 return err; 10001 10002 /* Multiple filters as links to the same hash table are not 10003 * supported. To add a new filter with the same next header 10004 * but different match/jump conditions, create a new hash table 10005 * and link to it. 10006 */ 10007 if (adapter->jump_tables[link_uhtid] && 10008 (adapter->jump_tables[link_uhtid])->link_hdl) { 10009 e_err(drv, "Link filter exists for link: %x\n", 10010 link_uhtid); 10011 return err; 10012 } 10013 10014 for (i = 0; nexthdr[i].jump; i++) { 10015 if (nexthdr[i].o != cls->knode.sel->offoff || 10016 nexthdr[i].s != cls->knode.sel->offshift || 10017 nexthdr[i].m != 10018 (__force u32)cls->knode.sel->offmask) 10019 return err; 10020 10021 jump = kzalloc(sizeof(*jump), GFP_KERNEL); 10022 if (!jump) 10023 return -ENOMEM; 10024 input = kzalloc(sizeof(*input), GFP_KERNEL); 10025 if (!input) { 10026 err = -ENOMEM; 10027 goto free_jump; 10028 } 10029 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 10030 if (!mask) { 10031 err = -ENOMEM; 10032 goto free_input; 10033 } 10034 jump->input = input; 10035 jump->mask = mask; 10036 jump->link_hdl = cls->knode.handle; 10037 10038 err = ixgbe_clsu32_build_input(input, mask, cls, 10039 field_ptr, &nexthdr[i]); 10040 if (!err) { 10041 jump->mat = nexthdr[i].jump; 10042 adapter->jump_tables[link_uhtid] = jump; 10043 break; 10044 } else { 10045 kfree(mask); 10046 kfree(input); 10047 kfree(jump); 10048 } 10049 } 10050 return 0; 10051 } 10052 10053 input = kzalloc(sizeof(*input), GFP_KERNEL); 10054 if (!input) 10055 return -ENOMEM; 10056 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 10057 if (!mask) { 10058 err = -ENOMEM; 10059 goto free_input; 10060 } 10061 10062 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { 10063 if ((adapter->jump_tables[uhtid])->input) 10064 memcpy(input, (adapter->jump_tables[uhtid])->input, 10065 sizeof(*input)); 10066 if ((adapter->jump_tables[uhtid])->mask) 10067 memcpy(mask, (adapter->jump_tables[uhtid])->mask, 10068 sizeof(*mask)); 10069 10070 /* Lookup in all child hash tables if this location is already 10071 * filled with a filter 10072 */ 10073 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 10074 struct ixgbe_jump_table *link = adapter->jump_tables[i]; 10075 10076 if (link && (test_bit(loc - 1, link->child_loc_map))) { 10077 e_err(drv, "Filter exists in location: %x\n", 10078 loc); 10079 err = -EINVAL; 10080 goto err_out; 10081 } 10082 } 10083 } 10084 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); 10085 if (err) 10086 goto err_out; 10087 10088 err = parse_tc_actions(adapter, cls->knode.exts, &input->action, 10089 &queue); 10090 if (err < 0) 10091 goto err_out; 10092 10093 input->sw_idx = loc; 10094 10095 spin_lock(&adapter->fdir_perfect_lock); 10096 10097 if (hlist_empty(&adapter->fdir_filter_list)) { 10098 memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); 10099 err = ixgbe_fdir_set_input_mask_82599(hw, mask); 10100 if (err) 10101 goto err_out_w_lock; 10102 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { 10103 err = -EINVAL; 10104 goto err_out_w_lock; 10105 } 10106 10107 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); 10108 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, 10109 input->sw_idx, queue); 10110 if (err) 10111 goto err_out_w_lock; 10112 10113 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 10114 spin_unlock(&adapter->fdir_perfect_lock); 10115 10116 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) 10117 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map); 10118 10119 kfree(mask); 10120 return err; 10121 err_out_w_lock: 10122 spin_unlock(&adapter->fdir_perfect_lock); 10123 err_out: 10124 kfree(mask); 10125 free_input: 10126 kfree(input); 10127 free_jump: 10128 kfree(jump); 10129 return err; 10130 } 10131 10132 static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter, 10133 struct tc_cls_u32_offload *cls_u32) 10134 { 10135 switch (cls_u32->command) { 10136 case TC_CLSU32_NEW_KNODE: 10137 case TC_CLSU32_REPLACE_KNODE: 10138 return ixgbe_configure_clsu32(adapter, cls_u32); 10139 case TC_CLSU32_DELETE_KNODE: 10140 return ixgbe_delete_clsu32(adapter, cls_u32); 10141 case TC_CLSU32_NEW_HNODE: 10142 case TC_CLSU32_REPLACE_HNODE: 10143 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32); 10144 case TC_CLSU32_DELETE_HNODE: 10145 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32); 10146 default: 10147 return -EOPNOTSUPP; 10148 } 10149 } 10150 10151 static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 10152 void *cb_priv) 10153 { 10154 struct ixgbe_adapter *adapter = cb_priv; 10155 10156 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 10157 return -EOPNOTSUPP; 10158 10159 switch (type) { 10160 case TC_SETUP_CLSU32: 10161 return ixgbe_setup_tc_cls_u32(adapter, type_data); 10162 default: 10163 return -EOPNOTSUPP; 10164 } 10165 } 10166 10167 static int ixgbe_setup_tc_mqprio(struct net_device *dev, 10168 struct tc_mqprio_qopt *mqprio) 10169 { 10170 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 10171 return ixgbe_setup_tc(dev, mqprio->num_tc); 10172 } 10173 10174 static LIST_HEAD(ixgbe_block_cb_list); 10175 10176 static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type, 10177 void *type_data) 10178 { 10179 struct ixgbe_adapter *adapter = netdev_priv(dev); 10180 10181 switch (type) { 10182 case TC_SETUP_BLOCK: 10183 return flow_block_cb_setup_simple(type_data, 10184 &ixgbe_block_cb_list, 10185 ixgbe_setup_tc_block_cb, 10186 adapter, adapter, true); 10187 case TC_SETUP_QDISC_MQPRIO: 10188 return ixgbe_setup_tc_mqprio(dev, type_data); 10189 default: 10190 return -EOPNOTSUPP; 10191 } 10192 } 10193 10194 #ifdef CONFIG_PCI_IOV 10195 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 10196 { 10197 struct net_device *netdev = adapter->netdev; 10198 10199 rtnl_lock(); 10200 ixgbe_setup_tc(netdev, adapter->hw_tcs); 10201 rtnl_unlock(); 10202 } 10203 10204 #endif 10205 void ixgbe_do_reset(struct net_device *netdev) 10206 { 10207 struct ixgbe_adapter *adapter = netdev_priv(netdev); 10208 10209 if (netif_running(netdev)) 10210 ixgbe_reinit_locked(adapter); 10211 else 10212 ixgbe_reset(adapter); 10213 } 10214 10215 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 10216 netdev_features_t features) 10217 { 10218 struct ixgbe_adapter *adapter = netdev_priv(netdev); 10219 10220 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 10221 if (!(features & NETIF_F_RXCSUM)) 10222 features &= ~NETIF_F_LRO; 10223 10224 /* Turn off LRO if not RSC capable */ 10225 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 10226 features &= ~NETIF_F_LRO; 10227 10228 if (adapter->xdp_prog && (features & NETIF_F_LRO)) { 10229 e_dev_err("LRO is not supported with XDP\n"); 10230 features &= ~NETIF_F_LRO; 10231 } 10232 10233 return features; 10234 } 10235 10236 static void ixgbe_reset_l2fw_offload(struct ixgbe_adapter *adapter) 10237 { 10238 int rss = min_t(int, ixgbe_max_rss_indices(adapter), 10239 num_online_cpus()); 10240 10241 /* go back to full RSS if we're not running SR-IOV */ 10242 if (!adapter->ring_feature[RING_F_VMDQ].offset) 10243 adapter->flags &= ~(IXGBE_FLAG_VMDQ_ENABLED | 10244 IXGBE_FLAG_SRIOV_ENABLED); 10245 10246 adapter->ring_feature[RING_F_RSS].limit = rss; 10247 adapter->ring_feature[RING_F_VMDQ].limit = 1; 10248 10249 ixgbe_setup_tc(adapter->netdev, adapter->hw_tcs); 10250 } 10251 10252 static int ixgbe_set_features(struct net_device *netdev, 10253 netdev_features_t features) 10254 { 10255 struct ixgbe_adapter *adapter = netdev_priv(netdev); 10256 netdev_features_t changed = netdev->features ^ features; 10257 bool need_reset = false; 10258 10259 /* Make sure RSC matches LRO, reset if change */ 10260 if (!(features & NETIF_F_LRO)) { 10261 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 10262 need_reset = true; 10263 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 10264 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 10265 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 10266 if (adapter->rx_itr_setting == 1 || 10267 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 10268 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 10269 need_reset = true; 10270 } else if ((changed ^ features) & NETIF_F_LRO) { 10271 e_info(probe, "rx-usecs set too low, " 10272 "disabling RSC\n"); 10273 } 10274 } 10275 10276 /* 10277 * Check if Flow Director n-tuple support or hw_tc support was 10278 * enabled or disabled. If the state changed, we need to reset. 10279 */ 10280 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { 10281 /* turn off ATR, enable perfect filters and reset */ 10282 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 10283 need_reset = true; 10284 10285 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 10286 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 10287 } else { 10288 /* turn off perfect filters, enable ATR and reset */ 10289 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 10290 need_reset = true; 10291 10292 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 10293 10294 /* We cannot enable ATR if SR-IOV is enabled */ 10295 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || 10296 /* We cannot enable ATR if we have 2 or more tcs */ 10297 (adapter->hw_tcs > 1) || 10298 /* We cannot enable ATR if RSS is disabled */ 10299 (adapter->ring_feature[RING_F_RSS].limit <= 1) || 10300 /* A sample rate of 0 indicates ATR disabled */ 10301 (!adapter->atr_sample_rate)) 10302 ; /* do nothing not supported */ 10303 else /* otherwise supported and set the flag */ 10304 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 10305 } 10306 10307 if (changed & NETIF_F_RXALL) 10308 need_reset = true; 10309 10310 netdev->features = features; 10311 10312 if ((changed & NETIF_F_HW_L2FW_DOFFLOAD) && adapter->num_rx_pools > 1) 10313 ixgbe_reset_l2fw_offload(adapter); 10314 else if (need_reset) 10315 ixgbe_do_reset(netdev); 10316 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | 10317 NETIF_F_HW_VLAN_CTAG_FILTER)) 10318 ixgbe_set_rx_mode(netdev); 10319 10320 return 1; 10321 } 10322 10323 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 10324 struct net_device *dev, 10325 const unsigned char *addr, u16 vid, 10326 u16 flags, bool *notified, 10327 struct netlink_ext_ack *extack) 10328 { 10329 /* guarantee we can provide a unique filter for the unicast address */ 10330 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 10331 struct ixgbe_adapter *adapter = netdev_priv(dev); 10332 u16 pool = VMDQ_P(0); 10333 10334 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) 10335 return -ENOMEM; 10336 } 10337 10338 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 10339 } 10340 10341 /** 10342 * ixgbe_configure_bridge_mode - set various bridge modes 10343 * @adapter: the private structure 10344 * @mode: requested bridge mode 10345 * 10346 * Configure some settings require for various bridge modes. 10347 **/ 10348 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 10349 __u16 mode) 10350 { 10351 struct ixgbe_hw *hw = &adapter->hw; 10352 unsigned int p, num_pools; 10353 u32 vmdctl; 10354 10355 switch (mode) { 10356 case BRIDGE_MODE_VEPA: 10357 /* disable Tx loopback, rely on switch hairpin mode */ 10358 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 10359 10360 /* must enable Rx switching replication to allow multicast 10361 * packet reception on all VFs, and to enable source address 10362 * pruning. 10363 */ 10364 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 10365 vmdctl |= IXGBE_VT_CTL_REPLEN; 10366 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 10367 10368 /* enable Rx source address pruning. Note, this requires 10369 * replication to be enabled or else it does nothing. 10370 */ 10371 num_pools = adapter->num_vfs + adapter->num_rx_pools; 10372 for (p = 0; p < num_pools; p++) { 10373 if (hw->mac.ops.set_source_address_pruning) 10374 hw->mac.ops.set_source_address_pruning(hw, 10375 true, 10376 p); 10377 } 10378 break; 10379 case BRIDGE_MODE_VEB: 10380 /* enable Tx loopback for internal VF/PF communication */ 10381 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 10382 IXGBE_PFDTXGSWC_VT_LBEN); 10383 10384 /* disable Rx switching replication unless we have SR-IOV 10385 * virtual functions 10386 */ 10387 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 10388 if (!adapter->num_vfs) 10389 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 10390 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 10391 10392 /* disable Rx source address pruning, since we don't expect to 10393 * be receiving external loopback of our transmitted frames. 10394 */ 10395 num_pools = adapter->num_vfs + adapter->num_rx_pools; 10396 for (p = 0; p < num_pools; p++) { 10397 if (hw->mac.ops.set_source_address_pruning) 10398 hw->mac.ops.set_source_address_pruning(hw, 10399 false, 10400 p); 10401 } 10402 break; 10403 default: 10404 return -EINVAL; 10405 } 10406 10407 adapter->bridge_mode = mode; 10408 10409 e_info(drv, "enabling bridge mode: %s\n", 10410 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 10411 10412 return 0; 10413 } 10414 10415 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 10416 struct nlmsghdr *nlh, u16 flags, 10417 struct netlink_ext_ack *extack) 10418 { 10419 struct ixgbe_adapter *adapter = netdev_priv(dev); 10420 struct nlattr *attr, *br_spec; 10421 int rem; 10422 10423 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 10424 return -EOPNOTSUPP; 10425 10426 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 10427 if (!br_spec) 10428 return -EINVAL; 10429 10430 nla_for_each_nested_type(attr, IFLA_BRIDGE_MODE, br_spec, rem) { 10431 __u16 mode = nla_get_u16(attr); 10432 int status = ixgbe_configure_bridge_mode(adapter, mode); 10433 10434 if (status) 10435 return status; 10436 10437 break; 10438 } 10439 10440 return 0; 10441 } 10442 10443 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 10444 struct net_device *dev, 10445 u32 filter_mask, int nlflags) 10446 { 10447 struct ixgbe_adapter *adapter = netdev_priv(dev); 10448 10449 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 10450 return 0; 10451 10452 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 10453 adapter->bridge_mode, 0, 0, nlflags, 10454 filter_mask, NULL); 10455 } 10456 10457 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 10458 { 10459 struct ixgbe_adapter *adapter = netdev_priv(pdev); 10460 struct ixgbe_fwd_adapter *accel; 10461 int tcs = adapter->hw_tcs ? : 1; 10462 int pool, err; 10463 10464 if (adapter->xdp_prog) { 10465 e_warn(probe, "L2FW offload is not supported with XDP\n"); 10466 return ERR_PTR(-EINVAL); 10467 } 10468 10469 /* The hardware supported by ixgbe only filters on the destination MAC 10470 * address. In order to avoid issues we only support offloading modes 10471 * where the hardware can actually provide the functionality. 10472 */ 10473 if (!macvlan_supports_dest_filter(vdev)) 10474 return ERR_PTR(-EMEDIUMTYPE); 10475 10476 /* We need to lock down the macvlan to be a single queue device so that 10477 * we can reuse the tc_to_txq field in the macvlan netdev to represent 10478 * the queue mapping to our netdev. 10479 */ 10480 if (netif_is_multiqueue(vdev)) 10481 return ERR_PTR(-ERANGE); 10482 10483 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 10484 if (pool == adapter->num_rx_pools) { 10485 u16 used_pools = adapter->num_vfs + adapter->num_rx_pools; 10486 u16 reserved_pools; 10487 10488 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 10489 adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) || 10490 adapter->num_rx_pools > IXGBE_MAX_MACVLANS) 10491 return ERR_PTR(-EBUSY); 10492 10493 /* Hardware has a limited number of available pools. Each VF, 10494 * and the PF require a pool. Check to ensure we don't 10495 * attempt to use more then the available number of pools. 10496 */ 10497 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 10498 return ERR_PTR(-EBUSY); 10499 10500 /* Enable VMDq flag so device will be set in VM mode */ 10501 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | 10502 IXGBE_FLAG_SRIOV_ENABLED; 10503 10504 /* Try to reserve as many queues per pool as possible, 10505 * we start with the configurations that support 4 queues 10506 * per pools, followed by 2, and then by just 1 per pool. 10507 */ 10508 if (used_pools < 32 && adapter->num_rx_pools < 16) 10509 reserved_pools = min_t(u16, 10510 32 - used_pools, 10511 16 - adapter->num_rx_pools); 10512 else if (adapter->num_rx_pools < 32) 10513 reserved_pools = min_t(u16, 10514 64 - used_pools, 10515 32 - adapter->num_rx_pools); 10516 else 10517 reserved_pools = 64 - used_pools; 10518 10519 10520 if (!reserved_pools) 10521 return ERR_PTR(-EBUSY); 10522 10523 adapter->ring_feature[RING_F_VMDQ].limit += reserved_pools; 10524 10525 /* Force reinit of ring allocation with VMDQ enabled */ 10526 err = ixgbe_setup_tc(pdev, adapter->hw_tcs); 10527 if (err) 10528 return ERR_PTR(err); 10529 10530 if (pool >= adapter->num_rx_pools) 10531 return ERR_PTR(-ENOMEM); 10532 } 10533 10534 accel = kzalloc(sizeof(*accel), GFP_KERNEL); 10535 if (!accel) 10536 return ERR_PTR(-ENOMEM); 10537 10538 set_bit(pool, adapter->fwd_bitmask); 10539 netdev_set_sb_channel(vdev, pool); 10540 accel->pool = pool; 10541 accel->netdev = vdev; 10542 10543 if (!netif_running(pdev)) 10544 return accel; 10545 10546 err = ixgbe_fwd_ring_up(adapter, accel); 10547 if (err) 10548 return ERR_PTR(err); 10549 10550 return accel; 10551 } 10552 10553 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 10554 { 10555 struct ixgbe_fwd_adapter *accel = priv; 10556 struct ixgbe_adapter *adapter = netdev_priv(pdev); 10557 unsigned int rxbase = accel->rx_base_queue; 10558 unsigned int i; 10559 10560 /* delete unicast filter associated with offloaded interface */ 10561 ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr, 10562 VMDQ_P(accel->pool)); 10563 10564 /* Allow remaining Rx packets to get flushed out of the 10565 * Rx FIFO before we drop the netdev for the ring. 10566 */ 10567 usleep_range(10000, 20000); 10568 10569 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 10570 struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i]; 10571 struct ixgbe_q_vector *qv = ring->q_vector; 10572 10573 /* Make sure we aren't processing any packets and clear 10574 * netdev to shut down the ring. 10575 */ 10576 if (netif_running(adapter->netdev)) 10577 napi_synchronize(&qv->napi); 10578 ring->netdev = NULL; 10579 } 10580 10581 /* unbind the queues and drop the subordinate channel config */ 10582 netdev_unbind_sb_channel(pdev, accel->netdev); 10583 netdev_set_sb_channel(accel->netdev, 0); 10584 10585 clear_bit(accel->pool, adapter->fwd_bitmask); 10586 kfree(accel); 10587 } 10588 10589 #define IXGBE_MAX_MAC_HDR_LEN 127 10590 #define IXGBE_MAX_NETWORK_HDR_LEN 511 10591 10592 static netdev_features_t 10593 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 10594 netdev_features_t features) 10595 { 10596 unsigned int network_hdr_len, mac_hdr_len; 10597 10598 /* Make certain the headers can be described by a context descriptor */ 10599 mac_hdr_len = skb_network_offset(skb); 10600 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) 10601 return features & ~(NETIF_F_HW_CSUM | 10602 NETIF_F_SCTP_CRC | 10603 NETIF_F_GSO_UDP_L4 | 10604 NETIF_F_HW_VLAN_CTAG_TX | 10605 NETIF_F_TSO | 10606 NETIF_F_TSO6); 10607 10608 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 10609 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) 10610 return features & ~(NETIF_F_HW_CSUM | 10611 NETIF_F_SCTP_CRC | 10612 NETIF_F_GSO_UDP_L4 | 10613 NETIF_F_TSO | 10614 NETIF_F_TSO6); 10615 10616 /* We can only support IPV4 TSO in tunnels if we can mangle the 10617 * inner IP ID field, so strip TSO if MANGLEID is not supported. 10618 * IPsec offoad sets skb->encapsulation but still can handle 10619 * the TSO, so it's the exception. 10620 */ 10621 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) { 10622 #ifdef CONFIG_IXGBE_IPSEC 10623 if (!secpath_exists(skb)) 10624 #endif 10625 features &= ~NETIF_F_TSO; 10626 } 10627 10628 return features; 10629 } 10630 10631 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog) 10632 { 10633 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 10634 struct ixgbe_adapter *adapter = netdev_priv(dev); 10635 struct bpf_prog *old_prog; 10636 bool need_reset; 10637 int num_queues; 10638 10639 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 10640 return -EINVAL; 10641 10642 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) 10643 return -EINVAL; 10644 10645 /* verify ixgbe ring attributes are sufficient for XDP */ 10646 for (i = 0; i < adapter->num_rx_queues; i++) { 10647 struct ixgbe_ring *ring = adapter->rx_ring[i]; 10648 10649 if (ring_is_rsc_enabled(ring)) 10650 return -EINVAL; 10651 10652 if (frame_size > ixgbe_rx_bufsz(ring)) 10653 return -EINVAL; 10654 } 10655 10656 /* if the number of cpus is much larger than the maximum of queues, 10657 * we should stop it and then return with ENOMEM like before. 10658 */ 10659 if (nr_cpu_ids > IXGBE_MAX_XDP_QS * 2) 10660 return -ENOMEM; 10661 10662 old_prog = xchg(&adapter->xdp_prog, prog); 10663 need_reset = (!!prog != !!old_prog); 10664 10665 /* If transitioning XDP modes reconfigure rings */ 10666 if (need_reset) { 10667 int err; 10668 10669 if (!prog) 10670 /* Wait until ndo_xsk_wakeup completes. */ 10671 synchronize_rcu(); 10672 err = ixgbe_setup_tc(dev, adapter->hw_tcs); 10673 10674 if (err) 10675 return -EINVAL; 10676 if (!prog) 10677 xdp_features_clear_redirect_target(dev); 10678 } else { 10679 for (i = 0; i < adapter->num_rx_queues; i++) { 10680 WRITE_ONCE(adapter->rx_ring[i]->xdp_prog, 10681 adapter->xdp_prog); 10682 } 10683 } 10684 10685 if (old_prog) 10686 bpf_prog_put(old_prog); 10687 10688 /* Kick start the NAPI context if there is an AF_XDP socket open 10689 * on that queue id. This so that receiving will start. 10690 */ 10691 if (need_reset && prog) { 10692 num_queues = min_t(int, adapter->num_rx_queues, 10693 adapter->num_xdp_queues); 10694 for (i = 0; i < num_queues; i++) 10695 if (adapter->xdp_ring[i]->xsk_pool) 10696 (void)ixgbe_xsk_wakeup(adapter->netdev, i, 10697 XDP_WAKEUP_RX); 10698 xdp_features_set_redirect_target(dev, true); 10699 } 10700 10701 return 0; 10702 } 10703 10704 static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp) 10705 { 10706 struct ixgbe_adapter *adapter = netdev_priv(dev); 10707 10708 switch (xdp->command) { 10709 case XDP_SETUP_PROG: 10710 return ixgbe_xdp_setup(dev, xdp->prog); 10711 case XDP_SETUP_XSK_POOL: 10712 return ixgbe_xsk_pool_setup(adapter, xdp->xsk.pool, 10713 xdp->xsk.queue_id); 10714 10715 default: 10716 return -EINVAL; 10717 } 10718 } 10719 10720 void ixgbe_xdp_ring_update_tail(struct ixgbe_ring *ring) 10721 { 10722 /* Force memory writes to complete before letting h/w know there 10723 * are new descriptors to fetch. 10724 */ 10725 wmb(); 10726 writel(ring->next_to_use, ring->tail); 10727 } 10728 10729 void ixgbe_xdp_ring_update_tail_locked(struct ixgbe_ring *ring) 10730 { 10731 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 10732 spin_lock(&ring->tx_lock); 10733 ixgbe_xdp_ring_update_tail(ring); 10734 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 10735 spin_unlock(&ring->tx_lock); 10736 } 10737 10738 static int ixgbe_xdp_xmit(struct net_device *dev, int n, 10739 struct xdp_frame **frames, u32 flags) 10740 { 10741 struct ixgbe_adapter *adapter = netdev_priv(dev); 10742 struct ixgbe_ring *ring; 10743 int nxmit = 0; 10744 int i; 10745 10746 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 10747 return -ENETDOWN; 10748 10749 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 10750 return -EINVAL; 10751 10752 /* During program transitions its possible adapter->xdp_prog is assigned 10753 * but ring has not been configured yet. In this case simply abort xmit. 10754 */ 10755 ring = adapter->xdp_prog ? ixgbe_determine_xdp_ring(adapter) : NULL; 10756 if (unlikely(!ring)) 10757 return -ENXIO; 10758 10759 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &ring->state))) 10760 return -ENXIO; 10761 10762 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 10763 spin_lock(&ring->tx_lock); 10764 10765 for (i = 0; i < n; i++) { 10766 struct xdp_frame *xdpf = frames[i]; 10767 int err; 10768 10769 err = ixgbe_xmit_xdp_ring(ring, xdpf); 10770 if (err != IXGBE_XDP_TX) 10771 break; 10772 nxmit++; 10773 } 10774 10775 if (unlikely(flags & XDP_XMIT_FLUSH)) 10776 ixgbe_xdp_ring_update_tail(ring); 10777 10778 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 10779 spin_unlock(&ring->tx_lock); 10780 10781 return nxmit; 10782 } 10783 10784 static const struct net_device_ops ixgbe_netdev_ops = { 10785 .ndo_open = ixgbe_open, 10786 .ndo_stop = ixgbe_close, 10787 .ndo_start_xmit = ixgbe_xmit_frame, 10788 .ndo_set_rx_mode = ixgbe_set_rx_mode, 10789 .ndo_validate_addr = eth_validate_addr, 10790 .ndo_set_mac_address = ixgbe_set_mac, 10791 .ndo_change_mtu = ixgbe_change_mtu, 10792 .ndo_tx_timeout = ixgbe_tx_timeout, 10793 .ndo_set_tx_maxrate = ixgbe_tx_maxrate, 10794 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 10795 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 10796 .ndo_eth_ioctl = ixgbe_ioctl, 10797 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 10798 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 10799 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 10800 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 10801 .ndo_set_vf_link_state = ixgbe_ndo_set_vf_link_state, 10802 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 10803 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, 10804 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 10805 .ndo_get_vf_stats = ixgbe_ndo_get_vf_stats, 10806 .ndo_get_stats64 = ixgbe_get_stats64, 10807 .ndo_setup_tc = __ixgbe_setup_tc, 10808 #ifdef IXGBE_FCOE 10809 .ndo_select_queue = ixgbe_select_queue, 10810 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 10811 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 10812 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 10813 .ndo_fcoe_enable = ixgbe_fcoe_enable, 10814 .ndo_fcoe_disable = ixgbe_fcoe_disable, 10815 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 10816 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 10817 #endif /* IXGBE_FCOE */ 10818 .ndo_set_features = ixgbe_set_features, 10819 .ndo_fix_features = ixgbe_fix_features, 10820 .ndo_fdb_add = ixgbe_ndo_fdb_add, 10821 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 10822 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 10823 .ndo_dfwd_add_station = ixgbe_fwd_add, 10824 .ndo_dfwd_del_station = ixgbe_fwd_del, 10825 .ndo_features_check = ixgbe_features_check, 10826 .ndo_bpf = ixgbe_xdp, 10827 .ndo_xdp_xmit = ixgbe_xdp_xmit, 10828 .ndo_xsk_wakeup = ixgbe_xsk_wakeup, 10829 }; 10830 10831 static void ixgbe_disable_txr_hw(struct ixgbe_adapter *adapter, 10832 struct ixgbe_ring *tx_ring) 10833 { 10834 unsigned long wait_delay, delay_interval; 10835 struct ixgbe_hw *hw = &adapter->hw; 10836 u8 reg_idx = tx_ring->reg_idx; 10837 int wait_loop; 10838 u32 txdctl; 10839 10840 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 10841 10842 /* delay mechanism from ixgbe_disable_tx */ 10843 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 10844 10845 wait_loop = IXGBE_MAX_RX_DESC_POLL; 10846 wait_delay = delay_interval; 10847 10848 while (wait_loop--) { 10849 usleep_range(wait_delay, wait_delay + 10); 10850 wait_delay += delay_interval * 2; 10851 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 10852 10853 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 10854 return; 10855 } 10856 10857 e_err(drv, "TXDCTL.ENABLE not cleared within the polling period\n"); 10858 } 10859 10860 static void ixgbe_disable_txr(struct ixgbe_adapter *adapter, 10861 struct ixgbe_ring *tx_ring) 10862 { 10863 set_bit(__IXGBE_TX_DISABLED, &tx_ring->state); 10864 ixgbe_disable_txr_hw(adapter, tx_ring); 10865 } 10866 10867 static void ixgbe_disable_rxr_hw(struct ixgbe_adapter *adapter, 10868 struct ixgbe_ring *rx_ring) 10869 { 10870 unsigned long wait_delay, delay_interval; 10871 struct ixgbe_hw *hw = &adapter->hw; 10872 u8 reg_idx = rx_ring->reg_idx; 10873 int wait_loop; 10874 u32 rxdctl; 10875 10876 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 10877 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 10878 rxdctl |= IXGBE_RXDCTL_SWFLSH; 10879 10880 /* write value back with RXDCTL.ENABLE bit cleared */ 10881 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 10882 10883 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 10884 if (hw->mac.type == ixgbe_mac_82598EB && 10885 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 10886 return; 10887 10888 /* delay mechanism from ixgbe_disable_rx */ 10889 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 10890 10891 wait_loop = IXGBE_MAX_RX_DESC_POLL; 10892 wait_delay = delay_interval; 10893 10894 while (wait_loop--) { 10895 usleep_range(wait_delay, wait_delay + 10); 10896 wait_delay += delay_interval * 2; 10897 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 10898 10899 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 10900 return; 10901 } 10902 10903 e_err(drv, "RXDCTL.ENABLE not cleared within the polling period\n"); 10904 } 10905 10906 static void ixgbe_reset_txr_stats(struct ixgbe_ring *tx_ring) 10907 { 10908 memset(&tx_ring->stats, 0, sizeof(tx_ring->stats)); 10909 memset(&tx_ring->tx_stats, 0, sizeof(tx_ring->tx_stats)); 10910 } 10911 10912 static void ixgbe_reset_rxr_stats(struct ixgbe_ring *rx_ring) 10913 { 10914 memset(&rx_ring->stats, 0, sizeof(rx_ring->stats)); 10915 memset(&rx_ring->rx_stats, 0, sizeof(rx_ring->rx_stats)); 10916 } 10917 10918 /** 10919 * ixgbe_irq_disable_single - Disable single IRQ vector 10920 * @adapter: adapter structure 10921 * @ring: ring index 10922 **/ 10923 static void ixgbe_irq_disable_single(struct ixgbe_adapter *adapter, u32 ring) 10924 { 10925 struct ixgbe_hw *hw = &adapter->hw; 10926 u64 qmask = BIT_ULL(ring); 10927 u32 mask; 10928 10929 switch (adapter->hw.mac.type) { 10930 case ixgbe_mac_82598EB: 10931 mask = qmask & IXGBE_EIMC_RTX_QUEUE; 10932 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask); 10933 break; 10934 case ixgbe_mac_82599EB: 10935 case ixgbe_mac_X540: 10936 case ixgbe_mac_X550: 10937 case ixgbe_mac_X550EM_x: 10938 case ixgbe_mac_x550em_a: 10939 mask = (qmask & 0xFFFFFFFF); 10940 if (mask) 10941 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 10942 mask = (qmask >> 32); 10943 if (mask) 10944 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 10945 break; 10946 default: 10947 break; 10948 } 10949 IXGBE_WRITE_FLUSH(&adapter->hw); 10950 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 10951 synchronize_irq(adapter->msix_entries[ring].vector); 10952 else 10953 synchronize_irq(adapter->pdev->irq); 10954 } 10955 10956 /** 10957 * ixgbe_txrx_ring_disable - Disable Rx/Tx/XDP Tx rings 10958 * @adapter: adapter structure 10959 * @ring: ring index 10960 * 10961 * This function disables a certain Rx/Tx/XDP Tx ring. The function 10962 * assumes that the netdev is running. 10963 **/ 10964 void ixgbe_txrx_ring_disable(struct ixgbe_adapter *adapter, int ring) 10965 { 10966 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 10967 10968 rx_ring = adapter->rx_ring[ring]; 10969 tx_ring = adapter->tx_ring[ring]; 10970 xdp_ring = adapter->xdp_ring[ring]; 10971 10972 ixgbe_irq_disable_single(adapter, ring); 10973 10974 /* Rx/Tx/XDP Tx share the same napi context. */ 10975 napi_disable(&rx_ring->q_vector->napi); 10976 10977 ixgbe_disable_txr(adapter, tx_ring); 10978 if (xdp_ring) 10979 ixgbe_disable_txr(adapter, xdp_ring); 10980 ixgbe_disable_rxr_hw(adapter, rx_ring); 10981 10982 if (xdp_ring) 10983 synchronize_rcu(); 10984 10985 ixgbe_clean_tx_ring(tx_ring); 10986 if (xdp_ring) 10987 ixgbe_clean_tx_ring(xdp_ring); 10988 ixgbe_clean_rx_ring(rx_ring); 10989 10990 ixgbe_reset_txr_stats(tx_ring); 10991 if (xdp_ring) 10992 ixgbe_reset_txr_stats(xdp_ring); 10993 ixgbe_reset_rxr_stats(rx_ring); 10994 } 10995 10996 /** 10997 * ixgbe_txrx_ring_enable - Enable Rx/Tx/XDP Tx rings 10998 * @adapter: adapter structure 10999 * @ring: ring index 11000 * 11001 * This function enables a certain Rx/Tx/XDP Tx ring. The function 11002 * assumes that the netdev is running. 11003 **/ 11004 void ixgbe_txrx_ring_enable(struct ixgbe_adapter *adapter, int ring) 11005 { 11006 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 11007 11008 rx_ring = adapter->rx_ring[ring]; 11009 tx_ring = adapter->tx_ring[ring]; 11010 xdp_ring = adapter->xdp_ring[ring]; 11011 11012 ixgbe_configure_tx_ring(adapter, tx_ring); 11013 if (xdp_ring) 11014 ixgbe_configure_tx_ring(adapter, xdp_ring); 11015 ixgbe_configure_rx_ring(adapter, rx_ring); 11016 11017 clear_bit(__IXGBE_TX_DISABLED, &tx_ring->state); 11018 if (xdp_ring) 11019 clear_bit(__IXGBE_TX_DISABLED, &xdp_ring->state); 11020 11021 /* Rx/Tx/XDP Tx share the same napi context. */ 11022 napi_enable(&rx_ring->q_vector->napi); 11023 ixgbe_irq_enable_queues(adapter, BIT_ULL(ring)); 11024 IXGBE_WRITE_FLUSH(&adapter->hw); 11025 } 11026 11027 /** 11028 * ixgbe_enumerate_functions - Get the number of ports this device has 11029 * @adapter: adapter structure 11030 * 11031 * This function enumerates the phsyical functions co-located on a single slot, 11032 * in order to determine how many ports a device has. This is most useful in 11033 * determining the required GT/s of PCIe bandwidth necessary for optimal 11034 * performance. 11035 **/ 11036 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 11037 { 11038 struct pci_dev *entry, *pdev = adapter->pdev; 11039 int physfns = 0; 11040 11041 /* Some cards can not use the generic count PCIe functions method, 11042 * because they are behind a parent switch, so we hardcode these with 11043 * the correct number of functions. 11044 */ 11045 if (ixgbe_pcie_from_parent(&adapter->hw)) 11046 physfns = 4; 11047 11048 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 11049 /* don't count virtual functions */ 11050 if (entry->is_virtfn) 11051 continue; 11052 11053 /* When the devices on the bus don't all match our device ID, 11054 * we can't reliably determine the correct number of 11055 * functions. This can occur if a function has been direct 11056 * attached to a virtual machine using VT-d, for example. In 11057 * this case, simply return -1 to indicate this. 11058 */ 11059 if ((entry->vendor != pdev->vendor) || 11060 (entry->device != pdev->device)) 11061 return -1; 11062 11063 physfns++; 11064 } 11065 11066 return physfns; 11067 } 11068 11069 /** 11070 * ixgbe_wol_supported - Check whether device supports WoL 11071 * @adapter: the adapter private structure 11072 * @device_id: the device ID 11073 * @subdevice_id: the subsystem device ID 11074 * 11075 * This function is used by probe and ethtool to determine 11076 * which devices have WoL support 11077 * 11078 **/ 11079 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 11080 u16 subdevice_id) 11081 { 11082 struct ixgbe_hw *hw = &adapter->hw; 11083 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 11084 11085 /* WOL not supported on 82598 */ 11086 if (hw->mac.type == ixgbe_mac_82598EB) 11087 return false; 11088 11089 /* check eeprom to see if WOL is enabled for X540 and newer */ 11090 if (hw->mac.type >= ixgbe_mac_X540) { 11091 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 11092 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 11093 (hw->bus.func == 0))) 11094 return true; 11095 } 11096 11097 /* WOL is determined based on device IDs for 82599 MACs */ 11098 switch (device_id) { 11099 case IXGBE_DEV_ID_82599_SFP: 11100 /* Only these subdevices could supports WOL */ 11101 switch (subdevice_id) { 11102 case IXGBE_SUBDEV_ID_82599_560FLR: 11103 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: 11104 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 11105 case IXGBE_SUBDEV_ID_82599_SFP_2OCP: 11106 /* only support first port */ 11107 if (hw->bus.func != 0) 11108 break; 11109 fallthrough; 11110 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 11111 case IXGBE_SUBDEV_ID_82599_SFP: 11112 case IXGBE_SUBDEV_ID_82599_RNDC: 11113 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 11114 case IXGBE_SUBDEV_ID_82599_SFP_1OCP: 11115 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: 11116 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: 11117 return true; 11118 } 11119 break; 11120 case IXGBE_DEV_ID_82599EN_SFP: 11121 /* Only these subdevices support WOL */ 11122 switch (subdevice_id) { 11123 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 11124 return true; 11125 } 11126 break; 11127 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 11128 /* All except this subdevice support WOL */ 11129 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 11130 return true; 11131 break; 11132 case IXGBE_DEV_ID_82599_KX4: 11133 return true; 11134 default: 11135 break; 11136 } 11137 11138 return false; 11139 } 11140 11141 /** 11142 * ixgbe_set_fw_version_e610 - Set FW version specifically on E610 adapters 11143 * @adapter: the adapter private structure 11144 * 11145 * This function is used by probe and ethtool to determine the FW version to 11146 * format to display. The FW version is taken from the EEPROM/NVM. 11147 * 11148 */ 11149 static void ixgbe_set_fw_version_e610(struct ixgbe_adapter *adapter) 11150 { 11151 struct ixgbe_orom_info *orom = &adapter->hw.flash.orom; 11152 struct ixgbe_nvm_info *nvm = &adapter->hw.flash.nvm; 11153 11154 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 11155 "%x.%02x 0x%x %d.%d.%d", nvm->major, nvm->minor, 11156 nvm->eetrack, orom->major, orom->build, orom->patch); 11157 } 11158 11159 /** 11160 * ixgbe_set_fw_version - Set FW version 11161 * @adapter: the adapter private structure 11162 * 11163 * This function is used by probe and ethtool to determine the FW version to 11164 * format to display. The FW version is taken from the EEPROM/NVM. 11165 */ 11166 static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter) 11167 { 11168 struct ixgbe_hw *hw = &adapter->hw; 11169 struct ixgbe_nvm_version nvm_ver; 11170 11171 if (adapter->hw.mac.type == ixgbe_mac_e610) { 11172 ixgbe_set_fw_version_e610(adapter); 11173 return; 11174 } 11175 11176 ixgbe_get_oem_prod_version(hw, &nvm_ver); 11177 if (nvm_ver.oem_valid) { 11178 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 11179 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor, 11180 nvm_ver.oem_release); 11181 return; 11182 } 11183 11184 ixgbe_get_etk_id(hw, &nvm_ver); 11185 ixgbe_get_orom_version(hw, &nvm_ver); 11186 11187 if (nvm_ver.or_valid) { 11188 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 11189 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major, 11190 nvm_ver.or_build, nvm_ver.or_patch); 11191 return; 11192 } 11193 11194 /* Set ETrack ID format */ 11195 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 11196 "0x%08x", nvm_ver.etk_id); 11197 } 11198 11199 /** 11200 * ixgbe_probe - Device Initialization Routine 11201 * @pdev: PCI device information struct 11202 * @ent: entry in ixgbe_pci_tbl 11203 * 11204 * Returns 0 on success, negative on failure 11205 * 11206 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 11207 * The OS initialization, configuring of the adapter private structure, 11208 * and a hardware reset occur. 11209 **/ 11210 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 11211 { 11212 struct net_device *netdev; 11213 struct ixgbe_adapter *adapter = NULL; 11214 struct ixgbe_hw *hw; 11215 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 11216 unsigned int indices = MAX_TX_QUEUES; 11217 u8 part_str[IXGBE_PBANUM_LENGTH]; 11218 int i, err, expected_gts; 11219 bool disable_dev = false; 11220 #ifdef IXGBE_FCOE 11221 u16 device_caps; 11222 #endif 11223 u32 eec; 11224 11225 /* Catch broken hardware that put the wrong VF device ID in 11226 * the PCIe SR-IOV capability. 11227 */ 11228 if (pdev->is_virtfn) { 11229 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 11230 pci_name(pdev), pdev->vendor, pdev->device); 11231 return -EINVAL; 11232 } 11233 11234 err = pci_enable_device_mem(pdev); 11235 if (err) 11236 return err; 11237 11238 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 11239 if (err) { 11240 dev_err(&pdev->dev, 11241 "No usable DMA configuration, aborting\n"); 11242 goto err_dma; 11243 } 11244 11245 err = pci_request_mem_regions(pdev, ixgbe_driver_name); 11246 if (err) { 11247 dev_err(&pdev->dev, 11248 "pci_request_selected_regions failed 0x%x\n", err); 11249 goto err_pci_reg; 11250 } 11251 11252 pci_set_master(pdev); 11253 pci_save_state(pdev); 11254 11255 if (ii->mac == ixgbe_mac_82598EB) { 11256 #ifdef CONFIG_IXGBE_DCB 11257 /* 8 TC w/ 4 queues per TC */ 11258 indices = 4 * MAX_TRAFFIC_CLASS; 11259 #else 11260 indices = IXGBE_MAX_RSS_INDICES; 11261 #endif 11262 } else if (ii->mac == ixgbe_mac_e610) { 11263 indices = IXGBE_MAX_RSS_INDICES_X550; 11264 } 11265 11266 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 11267 if (!netdev) { 11268 err = -ENOMEM; 11269 goto err_alloc_etherdev; 11270 } 11271 11272 SET_NETDEV_DEV(netdev, &pdev->dev); 11273 11274 adapter = netdev_priv(netdev); 11275 11276 adapter->netdev = netdev; 11277 adapter->pdev = pdev; 11278 hw = &adapter->hw; 11279 hw->back = adapter; 11280 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 11281 11282 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 11283 pci_resource_len(pdev, 0)); 11284 adapter->io_addr = hw->hw_addr; 11285 if (!hw->hw_addr) { 11286 err = -EIO; 11287 goto err_ioremap; 11288 } 11289 11290 netdev->netdev_ops = &ixgbe_netdev_ops; 11291 ixgbe_set_ethtool_ops(netdev); 11292 netdev->watchdog_timeo = 5 * HZ; 11293 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 11294 11295 /* Setup hw api */ 11296 hw->mac.ops = *ii->mac_ops; 11297 hw->mac.type = ii->mac; 11298 hw->mvals = ii->mvals; 11299 if (ii->link_ops) 11300 hw->link.ops = *ii->link_ops; 11301 11302 /* EEPROM */ 11303 hw->eeprom.ops = *ii->eeprom_ops; 11304 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 11305 if (ixgbe_removed(hw->hw_addr)) { 11306 err = -EIO; 11307 goto err_ioremap; 11308 } 11309 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 11310 if (!(eec & BIT(8))) 11311 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 11312 11313 /* PHY */ 11314 hw->phy.ops = *ii->phy_ops; 11315 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 11316 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 11317 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 11318 hw->phy.mdio.mmds = 0; 11319 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 11320 hw->phy.mdio.dev = netdev; 11321 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 11322 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 11323 11324 /* setup the private structure */ 11325 err = ixgbe_sw_init(adapter, ii); 11326 if (err) 11327 goto err_sw_init; 11328 11329 if (adapter->hw.mac.type == ixgbe_mac_e610) { 11330 err = ixgbe_get_caps(&adapter->hw); 11331 if (err) 11332 dev_err(&pdev->dev, "ixgbe_get_caps failed %d\n", err); 11333 } 11334 11335 if (adapter->hw.mac.type == ixgbe_mac_82599EB) 11336 adapter->flags2 |= IXGBE_FLAG2_AUTO_DISABLE_VF; 11337 11338 switch (adapter->hw.mac.type) { 11339 case ixgbe_mac_X550: 11340 case ixgbe_mac_X550EM_x: 11341 case ixgbe_mac_e610: 11342 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550; 11343 break; 11344 case ixgbe_mac_x550em_a: 11345 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550em_a; 11346 break; 11347 default: 11348 break; 11349 } 11350 11351 /* Make sure the SWFW semaphore is in a valid state */ 11352 if (hw->mac.ops.init_swfw_sync) 11353 hw->mac.ops.init_swfw_sync(hw); 11354 11355 /* Make it possible the adapter to be woken up via WOL */ 11356 switch (adapter->hw.mac.type) { 11357 case ixgbe_mac_82599EB: 11358 case ixgbe_mac_X540: 11359 case ixgbe_mac_X550: 11360 case ixgbe_mac_X550EM_x: 11361 case ixgbe_mac_x550em_a: 11362 case ixgbe_mac_e610: 11363 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 11364 break; 11365 default: 11366 break; 11367 } 11368 11369 /* 11370 * If there is a fan on this device and it has failed log the 11371 * failure. 11372 */ 11373 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 11374 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 11375 if (esdp & IXGBE_ESDP_SDP1) 11376 e_crit(probe, "Fan has stopped, replace the adapter\n"); 11377 } 11378 11379 if (allow_unsupported_sfp) 11380 hw->allow_unsupported_sfp = allow_unsupported_sfp; 11381 11382 /* reset_hw fills in the perm_addr as well */ 11383 hw->phy.reset_if_overtemp = true; 11384 err = hw->mac.ops.reset_hw(hw); 11385 hw->phy.reset_if_overtemp = false; 11386 ixgbe_set_eee_capable(adapter); 11387 if (err == -ENOENT) { 11388 err = 0; 11389 } else if (err == -EOPNOTSUPP) { 11390 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 11391 e_dev_err("Reload the driver after installing a supported module.\n"); 11392 goto err_sw_init; 11393 } else if (err) { 11394 e_dev_err("HW Init failed: %d\n", err); 11395 goto err_sw_init; 11396 } 11397 11398 #ifdef CONFIG_PCI_IOV 11399 /* SR-IOV not supported on the 82598 */ 11400 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 11401 goto skip_sriov; 11402 /* Mailbox */ 11403 ixgbe_init_mbx_params_pf(hw); 11404 hw->mbx.ops = ii->mbx_ops; 11405 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 11406 ixgbe_enable_sriov(adapter, max_vfs); 11407 skip_sriov: 11408 11409 #endif 11410 netdev->features = NETIF_F_SG | 11411 NETIF_F_TSO | 11412 NETIF_F_TSO6 | 11413 NETIF_F_RXHASH | 11414 NETIF_F_RXCSUM | 11415 NETIF_F_HW_CSUM; 11416 11417 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 11418 NETIF_F_GSO_GRE_CSUM | \ 11419 NETIF_F_GSO_IPXIP4 | \ 11420 NETIF_F_GSO_IPXIP6 | \ 11421 NETIF_F_GSO_UDP_TUNNEL | \ 11422 NETIF_F_GSO_UDP_TUNNEL_CSUM) 11423 11424 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; 11425 netdev->features |= NETIF_F_GSO_PARTIAL | 11426 IXGBE_GSO_PARTIAL_FEATURES; 11427 11428 if (hw->mac.type >= ixgbe_mac_82599EB) 11429 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 11430 11431 #ifdef CONFIG_IXGBE_IPSEC 11432 #define IXGBE_ESP_FEATURES (NETIF_F_HW_ESP | \ 11433 NETIF_F_HW_ESP_TX_CSUM | \ 11434 NETIF_F_GSO_ESP) 11435 11436 if (adapter->ipsec) 11437 netdev->features |= IXGBE_ESP_FEATURES; 11438 #endif 11439 /* copy netdev features into list of user selectable features */ 11440 netdev->hw_features |= netdev->features | 11441 NETIF_F_HW_VLAN_CTAG_FILTER | 11442 NETIF_F_HW_VLAN_CTAG_RX | 11443 NETIF_F_HW_VLAN_CTAG_TX | 11444 NETIF_F_RXALL | 11445 NETIF_F_HW_L2FW_DOFFLOAD; 11446 11447 if (hw->mac.type >= ixgbe_mac_82599EB) 11448 netdev->hw_features |= NETIF_F_NTUPLE | 11449 NETIF_F_HW_TC; 11450 11451 netdev->features |= NETIF_F_HIGHDMA; 11452 11453 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 11454 netdev->hw_enc_features |= netdev->vlan_features; 11455 netdev->mpls_features |= NETIF_F_SG | 11456 NETIF_F_TSO | 11457 NETIF_F_TSO6 | 11458 NETIF_F_HW_CSUM; 11459 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES; 11460 11461 /* set this bit last since it cannot be part of vlan_features */ 11462 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 11463 NETIF_F_HW_VLAN_CTAG_RX | 11464 NETIF_F_HW_VLAN_CTAG_TX; 11465 11466 netdev->priv_flags |= IFF_UNICAST_FLT; 11467 netdev->priv_flags |= IFF_SUPP_NOFCS; 11468 11469 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | 11470 NETDEV_XDP_ACT_XSK_ZEROCOPY; 11471 11472 /* MTU range: 68 - 9710 */ 11473 netdev->min_mtu = ETH_MIN_MTU; 11474 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN); 11475 11476 #ifdef CONFIG_IXGBE_DCB 11477 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 11478 netdev->dcbnl_ops = &ixgbe_dcbnl_ops; 11479 #endif 11480 11481 #ifdef IXGBE_FCOE 11482 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 11483 unsigned int fcoe_l; 11484 11485 if (hw->mac.ops.get_device_caps) { 11486 hw->mac.ops.get_device_caps(hw, &device_caps); 11487 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 11488 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 11489 } 11490 11491 11492 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 11493 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 11494 11495 netdev->features |= NETIF_F_FSO | 11496 NETIF_F_FCOE_CRC; 11497 11498 netdev->vlan_features |= NETIF_F_FSO | 11499 NETIF_F_FCOE_CRC; 11500 } 11501 #endif /* IXGBE_FCOE */ 11502 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 11503 netdev->hw_features |= NETIF_F_LRO; 11504 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 11505 netdev->features |= NETIF_F_LRO; 11506 11507 if (ixgbe_check_fw_error(adapter)) { 11508 err = -EIO; 11509 goto err_sw_init; 11510 } 11511 11512 /* make sure the EEPROM is good */ 11513 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 11514 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 11515 err = -EIO; 11516 goto err_sw_init; 11517 } 11518 11519 eth_platform_get_mac_address(&adapter->pdev->dev, 11520 adapter->hw.mac.perm_addr); 11521 11522 eth_hw_addr_set(netdev, hw->mac.perm_addr); 11523 11524 if (!is_valid_ether_addr(netdev->dev_addr)) { 11525 e_dev_err("invalid MAC address\n"); 11526 err = -EIO; 11527 goto err_sw_init; 11528 } 11529 11530 /* Set hw->mac.addr to permanent MAC address */ 11531 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); 11532 ixgbe_mac_set_default_filter(adapter); 11533 11534 if (hw->mac.type == ixgbe_mac_e610) 11535 mutex_init(&hw->aci.lock); 11536 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0); 11537 11538 if (ixgbe_removed(hw->hw_addr)) { 11539 err = -EIO; 11540 goto err_sw_init; 11541 } 11542 INIT_WORK(&adapter->service_task, ixgbe_service_task); 11543 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 11544 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 11545 11546 err = ixgbe_init_interrupt_scheme(adapter); 11547 if (err) 11548 goto err_sw_init; 11549 11550 for (i = 0; i < adapter->num_rx_queues; i++) 11551 u64_stats_init(&adapter->rx_ring[i]->syncp); 11552 for (i = 0; i < adapter->num_tx_queues; i++) 11553 u64_stats_init(&adapter->tx_ring[i]->syncp); 11554 for (i = 0; i < adapter->num_xdp_queues; i++) 11555 u64_stats_init(&adapter->xdp_ring[i]->syncp); 11556 11557 /* WOL not supported for all devices */ 11558 adapter->wol = 0; 11559 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 11560 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 11561 pdev->subsystem_device); 11562 if (hw->wol_enabled) 11563 adapter->wol = IXGBE_WUFC_MAG; 11564 11565 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 11566 11567 /* save off EEPROM version number */ 11568 ixgbe_set_fw_version(adapter); 11569 11570 /* pick up the PCI bus settings for reporting later */ 11571 if (ixgbe_pcie_from_parent(hw)) 11572 ixgbe_get_parent_bus_info(adapter); 11573 else 11574 hw->mac.ops.get_bus_info(hw); 11575 11576 /* calculate the expected PCIe bandwidth required for optimal 11577 * performance. Note that some older parts will never have enough 11578 * bandwidth due to being older generation PCIe parts. We clamp these 11579 * parts to ensure no warning is displayed if it can't be fixed. 11580 */ 11581 switch (hw->mac.type) { 11582 case ixgbe_mac_82598EB: 11583 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 11584 break; 11585 default: 11586 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 11587 break; 11588 } 11589 11590 /* don't check link if we failed to enumerate functions */ 11591 if (expected_gts > 0) 11592 ixgbe_check_minimum_link(adapter, expected_gts); 11593 11594 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 11595 if (err) 11596 strscpy(part_str, "Unknown", sizeof(part_str)); 11597 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 11598 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 11599 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 11600 part_str); 11601 else 11602 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 11603 hw->mac.type, hw->phy.type, part_str); 11604 11605 e_dev_info("%pM\n", netdev->dev_addr); 11606 11607 /* reset the hardware with the new settings */ 11608 err = hw->mac.ops.start_hw(hw); 11609 if (err == -EACCES) { 11610 /* We are running on a pre-production device, log a warning */ 11611 e_dev_warn("This device is a pre-production adapter/LOM. " 11612 "Please be aware there may be issues associated " 11613 "with your hardware. If you are experiencing " 11614 "problems please contact your Intel or hardware " 11615 "representative who provided you with this " 11616 "hardware.\n"); 11617 } 11618 strcpy(netdev->name, "eth%d"); 11619 pci_set_drvdata(pdev, adapter); 11620 err = register_netdev(netdev); 11621 if (err) 11622 goto err_register; 11623 11624 11625 /* power down the optics for 82599 SFP+ fiber */ 11626 if (hw->mac.ops.disable_tx_laser) 11627 hw->mac.ops.disable_tx_laser(hw); 11628 11629 /* carrier off reporting is important to ethtool even BEFORE open */ 11630 netif_carrier_off(netdev); 11631 11632 #ifdef CONFIG_IXGBE_DCA 11633 if (dca_add_requester(&pdev->dev) == 0) { 11634 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 11635 ixgbe_setup_dca(adapter); 11636 } 11637 #endif 11638 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 11639 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 11640 for (i = 0; i < adapter->num_vfs; i++) 11641 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 11642 } 11643 11644 /* firmware requires driver version to be 0xFFFFFFFF 11645 * since os does not support feature 11646 */ 11647 if (hw->mac.ops.set_fw_drv_ver) 11648 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF, 11649 sizeof(UTS_RELEASE) - 1, 11650 UTS_RELEASE); 11651 11652 /* add san mac addr to netdev */ 11653 ixgbe_add_sanmac_netdev(netdev); 11654 11655 e_dev_info("%s\n", ixgbe_default_device_descr); 11656 11657 #ifdef CONFIG_IXGBE_HWMON 11658 if (ixgbe_sysfs_init(adapter)) 11659 e_err(probe, "failed to allocate sysfs resources\n"); 11660 #endif /* CONFIG_IXGBE_HWMON */ 11661 11662 ixgbe_dbg_adapter_init(adapter); 11663 11664 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 11665 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 11666 hw->mac.ops.setup_link(hw, 11667 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 11668 true); 11669 11670 err = ixgbe_mii_bus_init(hw); 11671 if (err) 11672 goto err_netdev; 11673 11674 return 0; 11675 11676 err_netdev: 11677 unregister_netdev(netdev); 11678 err_register: 11679 ixgbe_release_hw_control(adapter); 11680 ixgbe_clear_interrupt_scheme(adapter); 11681 if (hw->mac.type == ixgbe_mac_e610) 11682 mutex_destroy(&adapter->hw.aci.lock); 11683 err_sw_init: 11684 ixgbe_disable_sriov(adapter); 11685 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 11686 iounmap(adapter->io_addr); 11687 kfree(adapter->jump_tables[0]); 11688 kfree(adapter->mac_table); 11689 kfree(adapter->rss_key); 11690 bitmap_free(adapter->af_xdp_zc_qps); 11691 err_ioremap: 11692 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 11693 free_netdev(netdev); 11694 err_alloc_etherdev: 11695 pci_release_mem_regions(pdev); 11696 err_pci_reg: 11697 err_dma: 11698 if (!adapter || disable_dev) 11699 pci_disable_device(pdev); 11700 return err; 11701 } 11702 11703 /** 11704 * ixgbe_remove - Device Removal Routine 11705 * @pdev: PCI device information struct 11706 * 11707 * ixgbe_remove is called by the PCI subsystem to alert the driver 11708 * that it should release a PCI device. The could be caused by a 11709 * Hot-Plug event, or because the driver is going to be removed from 11710 * memory. 11711 **/ 11712 static void ixgbe_remove(struct pci_dev *pdev) 11713 { 11714 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11715 struct net_device *netdev; 11716 bool disable_dev; 11717 int i; 11718 11719 /* if !adapter then we already cleaned up in probe */ 11720 if (!adapter) 11721 return; 11722 11723 netdev = adapter->netdev; 11724 ixgbe_dbg_adapter_exit(adapter); 11725 11726 set_bit(__IXGBE_REMOVING, &adapter->state); 11727 cancel_work_sync(&adapter->service_task); 11728 11729 if (adapter->hw.mac.type == ixgbe_mac_e610) { 11730 ixgbe_disable_link_status_events(adapter); 11731 mutex_destroy(&adapter->hw.aci.lock); 11732 } 11733 11734 if (adapter->mii_bus) 11735 mdiobus_unregister(adapter->mii_bus); 11736 11737 #ifdef CONFIG_IXGBE_DCA 11738 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 11739 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 11740 dca_remove_requester(&pdev->dev); 11741 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 11742 IXGBE_DCA_CTRL_DCA_DISABLE); 11743 } 11744 11745 #endif 11746 #ifdef CONFIG_IXGBE_HWMON 11747 ixgbe_sysfs_exit(adapter); 11748 #endif /* CONFIG_IXGBE_HWMON */ 11749 11750 /* remove the added san mac */ 11751 ixgbe_del_sanmac_netdev(netdev); 11752 11753 #ifdef CONFIG_PCI_IOV 11754 ixgbe_disable_sriov(adapter); 11755 #endif 11756 if (netdev->reg_state == NETREG_REGISTERED) 11757 unregister_netdev(netdev); 11758 11759 ixgbe_stop_ipsec_offload(adapter); 11760 ixgbe_clear_interrupt_scheme(adapter); 11761 11762 ixgbe_release_hw_control(adapter); 11763 11764 #ifdef CONFIG_DCB 11765 kfree(adapter->ixgbe_ieee_pfc); 11766 kfree(adapter->ixgbe_ieee_ets); 11767 11768 #endif 11769 iounmap(adapter->io_addr); 11770 pci_release_mem_regions(pdev); 11771 11772 e_dev_info("complete\n"); 11773 11774 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { 11775 if (adapter->jump_tables[i]) { 11776 kfree(adapter->jump_tables[i]->input); 11777 kfree(adapter->jump_tables[i]->mask); 11778 } 11779 kfree(adapter->jump_tables[i]); 11780 } 11781 11782 kfree(adapter->mac_table); 11783 kfree(adapter->rss_key); 11784 bitmap_free(adapter->af_xdp_zc_qps); 11785 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 11786 free_netdev(netdev); 11787 11788 if (disable_dev) 11789 pci_disable_device(pdev); 11790 } 11791 11792 /** 11793 * ixgbe_io_error_detected - called when PCI error is detected 11794 * @pdev: Pointer to PCI device 11795 * @state: The current pci connection state 11796 * 11797 * This function is called after a PCI bus error affecting 11798 * this device has been detected. 11799 */ 11800 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 11801 pci_channel_state_t state) 11802 { 11803 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11804 struct net_device *netdev = adapter->netdev; 11805 11806 #ifdef CONFIG_PCI_IOV 11807 struct ixgbe_hw *hw = &adapter->hw; 11808 struct pci_dev *bdev, *vfdev; 11809 u32 dw0, dw1, dw2, dw3; 11810 int vf, pos; 11811 u16 req_id, pf_func; 11812 11813 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 11814 adapter->num_vfs == 0) 11815 goto skip_bad_vf_detection; 11816 11817 bdev = pdev->bus->self; 11818 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 11819 bdev = bdev->bus->self; 11820 11821 if (!bdev) 11822 goto skip_bad_vf_detection; 11823 11824 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 11825 if (!pos) 11826 goto skip_bad_vf_detection; 11827 11828 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 11829 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 11830 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 11831 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 11832 if (ixgbe_removed(hw->hw_addr)) 11833 goto skip_bad_vf_detection; 11834 11835 req_id = dw1 >> 16; 11836 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 11837 if (!(req_id & 0x0080)) 11838 goto skip_bad_vf_detection; 11839 11840 pf_func = req_id & 0x01; 11841 if ((pf_func & 1) == (pdev->devfn & 1)) { 11842 unsigned int device_id; 11843 11844 vf = FIELD_GET(0x7F, req_id); 11845 e_dev_err("VF %d has caused a PCIe error\n", vf); 11846 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 11847 "%8.8x\tdw3: %8.8x\n", 11848 dw0, dw1, dw2, dw3); 11849 switch (adapter->hw.mac.type) { 11850 case ixgbe_mac_82599EB: 11851 device_id = IXGBE_82599_VF_DEVICE_ID; 11852 break; 11853 case ixgbe_mac_X540: 11854 device_id = IXGBE_X540_VF_DEVICE_ID; 11855 break; 11856 case ixgbe_mac_X550: 11857 device_id = IXGBE_DEV_ID_X550_VF; 11858 break; 11859 case ixgbe_mac_X550EM_x: 11860 device_id = IXGBE_DEV_ID_X550EM_X_VF; 11861 break; 11862 case ixgbe_mac_x550em_a: 11863 device_id = IXGBE_DEV_ID_X550EM_A_VF; 11864 break; 11865 case ixgbe_mac_e610: 11866 device_id = IXGBE_DEV_ID_E610_VF; 11867 break; 11868 default: 11869 device_id = 0; 11870 break; 11871 } 11872 11873 /* Find the pci device of the offending VF */ 11874 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 11875 while (vfdev) { 11876 if (vfdev->devfn == (req_id & 0xFF)) 11877 break; 11878 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 11879 device_id, vfdev); 11880 } 11881 /* 11882 * There's a slim chance the VF could have been hot plugged, 11883 * so if it is no longer present we don't need to issue the 11884 * VFLR. Just clean up the AER in that case. 11885 */ 11886 if (vfdev) { 11887 pcie_flr(vfdev); 11888 /* Free device reference count */ 11889 pci_dev_put(vfdev); 11890 } 11891 } 11892 11893 /* 11894 * Even though the error may have occurred on the other port 11895 * we still need to increment the vf error reference count for 11896 * both ports because the I/O resume function will be called 11897 * for both of them. 11898 */ 11899 adapter->vferr_refcount++; 11900 11901 return PCI_ERS_RESULT_RECOVERED; 11902 11903 skip_bad_vf_detection: 11904 #endif /* CONFIG_PCI_IOV */ 11905 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 11906 return PCI_ERS_RESULT_DISCONNECT; 11907 11908 if (!netif_device_present(netdev)) 11909 return PCI_ERS_RESULT_DISCONNECT; 11910 11911 rtnl_lock(); 11912 netif_device_detach(netdev); 11913 11914 if (netif_running(netdev)) 11915 ixgbe_close_suspend(adapter); 11916 11917 if (state == pci_channel_io_perm_failure) { 11918 rtnl_unlock(); 11919 return PCI_ERS_RESULT_DISCONNECT; 11920 } 11921 11922 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 11923 pci_disable_device(pdev); 11924 rtnl_unlock(); 11925 11926 /* Request a slot reset. */ 11927 return PCI_ERS_RESULT_NEED_RESET; 11928 } 11929 11930 /** 11931 * ixgbe_io_slot_reset - called after the pci bus has been reset. 11932 * @pdev: Pointer to PCI device 11933 * 11934 * Restart the card from scratch, as if from a cold-boot. 11935 */ 11936 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 11937 { 11938 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11939 pci_ers_result_t result; 11940 11941 if (pci_enable_device_mem(pdev)) { 11942 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 11943 result = PCI_ERS_RESULT_DISCONNECT; 11944 } else { 11945 smp_mb__before_atomic(); 11946 clear_bit(__IXGBE_DISABLED, &adapter->state); 11947 adapter->hw.hw_addr = adapter->io_addr; 11948 pci_set_master(pdev); 11949 pci_restore_state(pdev); 11950 pci_save_state(pdev); 11951 11952 pci_wake_from_d3(pdev, false); 11953 11954 ixgbe_reset(adapter); 11955 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 11956 result = PCI_ERS_RESULT_RECOVERED; 11957 } 11958 11959 return result; 11960 } 11961 11962 /** 11963 * ixgbe_io_resume - called when traffic can start flowing again. 11964 * @pdev: Pointer to PCI device 11965 * 11966 * This callback is called when the error recovery driver tells us that 11967 * its OK to resume normal operation. 11968 */ 11969 static void ixgbe_io_resume(struct pci_dev *pdev) 11970 { 11971 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11972 struct net_device *netdev = adapter->netdev; 11973 11974 #ifdef CONFIG_PCI_IOV 11975 if (adapter->vferr_refcount) { 11976 e_info(drv, "Resuming after VF err\n"); 11977 adapter->vferr_refcount--; 11978 return; 11979 } 11980 11981 #endif 11982 rtnl_lock(); 11983 if (netif_running(netdev)) 11984 ixgbe_open(netdev); 11985 11986 netif_device_attach(netdev); 11987 rtnl_unlock(); 11988 } 11989 11990 static const struct pci_error_handlers ixgbe_err_handler = { 11991 .error_detected = ixgbe_io_error_detected, 11992 .slot_reset = ixgbe_io_slot_reset, 11993 .resume = ixgbe_io_resume, 11994 }; 11995 11996 static DEFINE_SIMPLE_DEV_PM_OPS(ixgbe_pm_ops, ixgbe_suspend, ixgbe_resume); 11997 11998 static struct pci_driver ixgbe_driver = { 11999 .name = ixgbe_driver_name, 12000 .id_table = ixgbe_pci_tbl, 12001 .probe = ixgbe_probe, 12002 .remove = ixgbe_remove, 12003 .driver.pm = pm_sleep_ptr(&ixgbe_pm_ops), 12004 .shutdown = ixgbe_shutdown, 12005 .sriov_configure = ixgbe_pci_sriov_configure, 12006 .err_handler = &ixgbe_err_handler 12007 }; 12008 12009 /** 12010 * ixgbe_init_module - Driver Registration Routine 12011 * 12012 * ixgbe_init_module is the first routine called when the driver is 12013 * loaded. All it does is register with the PCI subsystem. 12014 **/ 12015 static int __init ixgbe_init_module(void) 12016 { 12017 int ret; 12018 pr_info("%s\n", ixgbe_driver_string); 12019 pr_info("%s\n", ixgbe_copyright); 12020 12021 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); 12022 if (!ixgbe_wq) { 12023 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); 12024 return -ENOMEM; 12025 } 12026 12027 ixgbe_dbg_init(); 12028 12029 ret = pci_register_driver(&ixgbe_driver); 12030 if (ret) { 12031 destroy_workqueue(ixgbe_wq); 12032 ixgbe_dbg_exit(); 12033 return ret; 12034 } 12035 12036 #ifdef CONFIG_IXGBE_DCA 12037 dca_register_notify(&dca_notifier); 12038 #endif 12039 12040 return 0; 12041 } 12042 12043 module_init(ixgbe_init_module); 12044 12045 /** 12046 * ixgbe_exit_module - Driver Exit Cleanup Routine 12047 * 12048 * ixgbe_exit_module is called just before the driver is removed 12049 * from memory. 12050 **/ 12051 static void __exit ixgbe_exit_module(void) 12052 { 12053 #ifdef CONFIG_IXGBE_DCA 12054 dca_unregister_notify(&dca_notifier); 12055 #endif 12056 pci_unregister_driver(&ixgbe_driver); 12057 12058 ixgbe_dbg_exit(); 12059 if (ixgbe_wq) { 12060 destroy_workqueue(ixgbe_wq); 12061 ixgbe_wq = NULL; 12062 } 12063 } 12064 12065 #ifdef CONFIG_IXGBE_DCA 12066 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 12067 void *p) 12068 { 12069 int ret_val; 12070 12071 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 12072 __ixgbe_notify_dca); 12073 12074 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 12075 } 12076 12077 #endif /* CONFIG_IXGBE_DCA */ 12078 12079 module_exit(ixgbe_exit_module); 12080 12081 /* ixgbe_main.c */ 12082