xref: /linux/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c (revision b2105aa2c6481fda72c1825800b753a0bf614517)
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3 
4 #include <linux/types.h>
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/netdevice.h>
8 #include <linux/vmalloc.h>
9 #include <linux/string.h>
10 #include <linux/in.h>
11 #include <linux/interrupt.h>
12 #include <linux/ip.h>
13 #include <linux/tcp.h>
14 #include <linux/sctp.h>
15 #include <linux/pkt_sched.h>
16 #include <linux/ipv6.h>
17 #include <linux/slab.h>
18 #include <net/checksum.h>
19 #include <net/ip6_checksum.h>
20 #include <linux/etherdevice.h>
21 #include <linux/ethtool.h>
22 #include <linux/if.h>
23 #include <linux/if_vlan.h>
24 #include <linux/if_macvlan.h>
25 #include <linux/if_bridge.h>
26 #include <linux/prefetch.h>
27 #include <linux/bpf.h>
28 #include <linux/bpf_trace.h>
29 #include <linux/atomic.h>
30 #include <linux/numa.h>
31 #include <generated/utsrelease.h>
32 #include <scsi/fc/fc_fcoe.h>
33 #include <net/udp_tunnel.h>
34 #include <net/pkt_cls.h>
35 #include <net/tc_act/tc_gact.h>
36 #include <net/tc_act/tc_mirred.h>
37 #include <net/vxlan.h>
38 #include <net/mpls.h>
39 #include <net/xdp_sock_drv.h>
40 #include <net/xfrm.h>
41 
42 #include "ixgbe.h"
43 #include "ixgbe_common.h"
44 #include "ixgbe_dcb_82599.h"
45 #include "ixgbe_phy.h"
46 #include "ixgbe_sriov.h"
47 #include "ixgbe_model.h"
48 #include "ixgbe_txrx_common.h"
49 
50 char ixgbe_driver_name[] = "ixgbe";
51 static const char ixgbe_driver_string[] =
52 			      "Intel(R) 10 Gigabit PCI Express Network Driver";
53 #ifdef IXGBE_FCOE
54 char ixgbe_default_device_descr[] =
55 			      "Intel(R) 10 Gigabit Network Connection";
56 #else
57 static char ixgbe_default_device_descr[] =
58 			      "Intel(R) 10 Gigabit Network Connection";
59 #endif
60 static const char ixgbe_copyright[] =
61 				"Copyright (c) 1999-2016 Intel Corporation.";
62 
63 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
64 
65 static const struct ixgbe_info *ixgbe_info_tbl[] = {
66 	[board_82598]		= &ixgbe_82598_info,
67 	[board_82599]		= &ixgbe_82599_info,
68 	[board_X540]		= &ixgbe_X540_info,
69 	[board_X550]		= &ixgbe_X550_info,
70 	[board_X550EM_x]	= &ixgbe_X550EM_x_info,
71 	[board_x550em_x_fw]	= &ixgbe_x550em_x_fw_info,
72 	[board_x550em_a]	= &ixgbe_x550em_a_info,
73 	[board_x550em_a_fw]	= &ixgbe_x550em_a_fw_info,
74 };
75 
76 /* ixgbe_pci_tbl - PCI Device ID Table
77  *
78  * Wildcard entries (PCI_ANY_ID) should come last
79  * Last entry must be all 0s
80  *
81  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
82  *   Class, Class Mask, private data (not used) }
83  */
84 static const struct pci_device_id ixgbe_pci_tbl[] = {
85 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
86 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
87 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
88 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
89 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
90 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
91 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
92 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
93 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
94 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
95 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
96 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
97 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
98 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
99 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
100 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
101 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
102 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
103 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
104 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
105 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
106 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
107 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
108 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
109 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
110 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
111 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
112 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
113 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
114 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
115 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
116 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550},
117 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
118 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x},
119 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
120 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
121 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
122 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw},
123 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a },
124 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a },
125 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a },
126 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a },
127 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a },
128 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a},
129 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a },
130 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw },
131 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw },
132 	/* required last entry */
133 	{0, }
134 };
135 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
136 
137 #ifdef CONFIG_IXGBE_DCA
138 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
139 			    void *p);
140 static struct notifier_block dca_notifier = {
141 	.notifier_call = ixgbe_notify_dca,
142 	.next          = NULL,
143 	.priority      = 0
144 };
145 #endif
146 
147 #ifdef CONFIG_PCI_IOV
148 static unsigned int max_vfs;
149 module_param(max_vfs, uint, 0);
150 MODULE_PARM_DESC(max_vfs,
151 		 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
152 #endif /* CONFIG_PCI_IOV */
153 
154 static unsigned int allow_unsupported_sfp;
155 module_param(allow_unsupported_sfp, uint, 0);
156 MODULE_PARM_DESC(allow_unsupported_sfp,
157 		 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
158 
159 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
160 static int debug = -1;
161 module_param(debug, int, 0);
162 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
163 
164 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
165 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
166 MODULE_LICENSE("GPL v2");
167 
168 static struct workqueue_struct *ixgbe_wq;
169 
170 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
171 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *);
172 
173 static const struct net_device_ops ixgbe_netdev_ops;
174 
175 static bool netif_is_ixgbe(struct net_device *dev)
176 {
177 	return dev && (dev->netdev_ops == &ixgbe_netdev_ops);
178 }
179 
180 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
181 					  u32 reg, u16 *value)
182 {
183 	struct pci_dev *parent_dev;
184 	struct pci_bus *parent_bus;
185 
186 	parent_bus = adapter->pdev->bus->parent;
187 	if (!parent_bus)
188 		return -1;
189 
190 	parent_dev = parent_bus->self;
191 	if (!parent_dev)
192 		return -1;
193 
194 	if (!pci_is_pcie(parent_dev))
195 		return -1;
196 
197 	pcie_capability_read_word(parent_dev, reg, value);
198 	if (*value == IXGBE_FAILED_READ_CFG_WORD &&
199 	    ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
200 		return -1;
201 	return 0;
202 }
203 
204 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
205 {
206 	struct ixgbe_hw *hw = &adapter->hw;
207 	u16 link_status = 0;
208 	int err;
209 
210 	hw->bus.type = ixgbe_bus_type_pci_express;
211 
212 	/* Get the negotiated link width and speed from PCI config space of the
213 	 * parent, as this device is behind a switch
214 	 */
215 	err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
216 
217 	/* assume caller will handle error case */
218 	if (err)
219 		return err;
220 
221 	hw->bus.width = ixgbe_convert_bus_width(link_status);
222 	hw->bus.speed = ixgbe_convert_bus_speed(link_status);
223 
224 	return 0;
225 }
226 
227 /**
228  * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
229  * @hw: hw specific details
230  *
231  * This function is used by probe to determine whether a device's PCI-Express
232  * bandwidth details should be gathered from the parent bus instead of from the
233  * device. Used to ensure that various locations all have the correct device ID
234  * checks.
235  */
236 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
237 {
238 	switch (hw->device_id) {
239 	case IXGBE_DEV_ID_82599_SFP_SF_QP:
240 	case IXGBE_DEV_ID_82599_QSFP_SF_QP:
241 		return true;
242 	default:
243 		return false;
244 	}
245 }
246 
247 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
248 				     int expected_gts)
249 {
250 	struct ixgbe_hw *hw = &adapter->hw;
251 	struct pci_dev *pdev;
252 
253 	/* Some devices are not connected over PCIe and thus do not negotiate
254 	 * speed. These devices do not have valid bus info, and thus any report
255 	 * we generate may not be correct.
256 	 */
257 	if (hw->bus.type == ixgbe_bus_type_internal)
258 		return;
259 
260 	/* determine whether to use the parent device */
261 	if (ixgbe_pcie_from_parent(&adapter->hw))
262 		pdev = adapter->pdev->bus->parent->self;
263 	else
264 		pdev = adapter->pdev;
265 
266 	pcie_print_link_status(pdev);
267 }
268 
269 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
270 {
271 	if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
272 	    !test_bit(__IXGBE_REMOVING, &adapter->state) &&
273 	    !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
274 		queue_work(ixgbe_wq, &adapter->service_task);
275 }
276 
277 static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
278 {
279 	struct ixgbe_adapter *adapter = hw->back;
280 
281 	if (!hw->hw_addr)
282 		return;
283 	hw->hw_addr = NULL;
284 	e_dev_err("Adapter removed\n");
285 	if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
286 		ixgbe_service_event_schedule(adapter);
287 }
288 
289 static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
290 {
291 	u8 __iomem *reg_addr;
292 	u32 value;
293 	int i;
294 
295 	reg_addr = READ_ONCE(hw->hw_addr);
296 	if (ixgbe_removed(reg_addr))
297 		return IXGBE_FAILED_READ_REG;
298 
299 	/* Register read of 0xFFFFFFF can indicate the adapter has been removed,
300 	 * so perform several status register reads to determine if the adapter
301 	 * has been removed.
302 	 */
303 	for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) {
304 		value = readl(reg_addr + IXGBE_STATUS);
305 		if (value != IXGBE_FAILED_READ_REG)
306 			break;
307 		mdelay(3);
308 	}
309 
310 	if (value == IXGBE_FAILED_READ_REG)
311 		ixgbe_remove_adapter(hw);
312 	else
313 		value = readl(reg_addr + reg);
314 	return value;
315 }
316 
317 /**
318  * ixgbe_read_reg - Read from device register
319  * @hw: hw specific details
320  * @reg: offset of register to read
321  *
322  * Returns : value read or IXGBE_FAILED_READ_REG if removed
323  *
324  * This function is used to read device registers. It checks for device
325  * removal by confirming any read that returns all ones by checking the
326  * status register value for all ones. This function avoids reading from
327  * the hardware if a removal was previously detected in which case it
328  * returns IXGBE_FAILED_READ_REG (all ones).
329  */
330 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
331 {
332 	u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr);
333 	u32 value;
334 
335 	if (ixgbe_removed(reg_addr))
336 		return IXGBE_FAILED_READ_REG;
337 	if (unlikely(hw->phy.nw_mng_if_sel &
338 		     IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) {
339 		struct ixgbe_adapter *adapter;
340 		int i;
341 
342 		for (i = 0; i < 200; ++i) {
343 			value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY);
344 			if (likely(!value))
345 				goto writes_completed;
346 			if (value == IXGBE_FAILED_READ_REG) {
347 				ixgbe_remove_adapter(hw);
348 				return IXGBE_FAILED_READ_REG;
349 			}
350 			udelay(5);
351 		}
352 
353 		adapter = hw->back;
354 		e_warn(hw, "register writes incomplete %08x\n", value);
355 	}
356 
357 writes_completed:
358 	value = readl(reg_addr + reg);
359 	if (unlikely(value == IXGBE_FAILED_READ_REG))
360 		value = ixgbe_check_remove(hw, reg);
361 	return value;
362 }
363 
364 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
365 {
366 	u16 value;
367 
368 	pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
369 	if (value == IXGBE_FAILED_READ_CFG_WORD) {
370 		ixgbe_remove_adapter(hw);
371 		return true;
372 	}
373 	return false;
374 }
375 
376 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
377 {
378 	struct ixgbe_adapter *adapter = hw->back;
379 	u16 value;
380 
381 	if (ixgbe_removed(hw->hw_addr))
382 		return IXGBE_FAILED_READ_CFG_WORD;
383 	pci_read_config_word(adapter->pdev, reg, &value);
384 	if (value == IXGBE_FAILED_READ_CFG_WORD &&
385 	    ixgbe_check_cfg_remove(hw, adapter->pdev))
386 		return IXGBE_FAILED_READ_CFG_WORD;
387 	return value;
388 }
389 
390 #ifdef CONFIG_PCI_IOV
391 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
392 {
393 	struct ixgbe_adapter *adapter = hw->back;
394 	u32 value;
395 
396 	if (ixgbe_removed(hw->hw_addr))
397 		return IXGBE_FAILED_READ_CFG_DWORD;
398 	pci_read_config_dword(adapter->pdev, reg, &value);
399 	if (value == IXGBE_FAILED_READ_CFG_DWORD &&
400 	    ixgbe_check_cfg_remove(hw, adapter->pdev))
401 		return IXGBE_FAILED_READ_CFG_DWORD;
402 	return value;
403 }
404 #endif /* CONFIG_PCI_IOV */
405 
406 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
407 {
408 	struct ixgbe_adapter *adapter = hw->back;
409 
410 	if (ixgbe_removed(hw->hw_addr))
411 		return;
412 	pci_write_config_word(adapter->pdev, reg, value);
413 }
414 
415 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
416 {
417 	BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
418 
419 	/* flush memory to make sure state is correct before next watchdog */
420 	smp_mb__before_atomic();
421 	clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
422 }
423 
424 struct ixgbe_reg_info {
425 	u32 ofs;
426 	char *name;
427 };
428 
429 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
430 
431 	/* General Registers */
432 	{IXGBE_CTRL, "CTRL"},
433 	{IXGBE_STATUS, "STATUS"},
434 	{IXGBE_CTRL_EXT, "CTRL_EXT"},
435 
436 	/* Interrupt Registers */
437 	{IXGBE_EICR, "EICR"},
438 
439 	/* RX Registers */
440 	{IXGBE_SRRCTL(0), "SRRCTL"},
441 	{IXGBE_DCA_RXCTRL(0), "DRXCTL"},
442 	{IXGBE_RDLEN(0), "RDLEN"},
443 	{IXGBE_RDH(0), "RDH"},
444 	{IXGBE_RDT(0), "RDT"},
445 	{IXGBE_RXDCTL(0), "RXDCTL"},
446 	{IXGBE_RDBAL(0), "RDBAL"},
447 	{IXGBE_RDBAH(0), "RDBAH"},
448 
449 	/* TX Registers */
450 	{IXGBE_TDBAL(0), "TDBAL"},
451 	{IXGBE_TDBAH(0), "TDBAH"},
452 	{IXGBE_TDLEN(0), "TDLEN"},
453 	{IXGBE_TDH(0), "TDH"},
454 	{IXGBE_TDT(0), "TDT"},
455 	{IXGBE_TXDCTL(0), "TXDCTL"},
456 
457 	/* List Terminator */
458 	{ .name = NULL }
459 };
460 
461 
462 /*
463  * ixgbe_regdump - register printout routine
464  */
465 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
466 {
467 	int i;
468 	char rname[16];
469 	u32 regs[64];
470 
471 	switch (reginfo->ofs) {
472 	case IXGBE_SRRCTL(0):
473 		for (i = 0; i < 64; i++)
474 			regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
475 		break;
476 	case IXGBE_DCA_RXCTRL(0):
477 		for (i = 0; i < 64; i++)
478 			regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
479 		break;
480 	case IXGBE_RDLEN(0):
481 		for (i = 0; i < 64; i++)
482 			regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
483 		break;
484 	case IXGBE_RDH(0):
485 		for (i = 0; i < 64; i++)
486 			regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
487 		break;
488 	case IXGBE_RDT(0):
489 		for (i = 0; i < 64; i++)
490 			regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
491 		break;
492 	case IXGBE_RXDCTL(0):
493 		for (i = 0; i < 64; i++)
494 			regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
495 		break;
496 	case IXGBE_RDBAL(0):
497 		for (i = 0; i < 64; i++)
498 			regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
499 		break;
500 	case IXGBE_RDBAH(0):
501 		for (i = 0; i < 64; i++)
502 			regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
503 		break;
504 	case IXGBE_TDBAL(0):
505 		for (i = 0; i < 64; i++)
506 			regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
507 		break;
508 	case IXGBE_TDBAH(0):
509 		for (i = 0; i < 64; i++)
510 			regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
511 		break;
512 	case IXGBE_TDLEN(0):
513 		for (i = 0; i < 64; i++)
514 			regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
515 		break;
516 	case IXGBE_TDH(0):
517 		for (i = 0; i < 64; i++)
518 			regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
519 		break;
520 	case IXGBE_TDT(0):
521 		for (i = 0; i < 64; i++)
522 			regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
523 		break;
524 	case IXGBE_TXDCTL(0):
525 		for (i = 0; i < 64; i++)
526 			regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
527 		break;
528 	default:
529 		pr_info("%-15s %08x\n",
530 			reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs));
531 		return;
532 	}
533 
534 	i = 0;
535 	while (i < 64) {
536 		int j;
537 		char buf[9 * 8 + 1];
538 		char *p = buf;
539 
540 		snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7);
541 		for (j = 0; j < 8; j++)
542 			p += sprintf(p, " %08x", regs[i++]);
543 		pr_err("%-15s%s\n", rname, buf);
544 	}
545 
546 }
547 
548 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n)
549 {
550 	struct ixgbe_tx_buffer *tx_buffer;
551 
552 	tx_buffer = &ring->tx_buffer_info[ring->next_to_clean];
553 	pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
554 		n, ring->next_to_use, ring->next_to_clean,
555 		(u64)dma_unmap_addr(tx_buffer, dma),
556 		dma_unmap_len(tx_buffer, len),
557 		tx_buffer->next_to_watch,
558 		(u64)tx_buffer->time_stamp);
559 }
560 
561 /*
562  * ixgbe_dump - Print registers, tx-rings and rx-rings
563  */
564 static void ixgbe_dump(struct ixgbe_adapter *adapter)
565 {
566 	struct net_device *netdev = adapter->netdev;
567 	struct ixgbe_hw *hw = &adapter->hw;
568 	struct ixgbe_reg_info *reginfo;
569 	int n = 0;
570 	struct ixgbe_ring *ring;
571 	struct ixgbe_tx_buffer *tx_buffer;
572 	union ixgbe_adv_tx_desc *tx_desc;
573 	struct my_u0 { u64 a; u64 b; } *u0;
574 	struct ixgbe_ring *rx_ring;
575 	union ixgbe_adv_rx_desc *rx_desc;
576 	struct ixgbe_rx_buffer *rx_buffer_info;
577 	int i = 0;
578 
579 	if (!netif_msg_hw(adapter))
580 		return;
581 
582 	/* Print netdevice Info */
583 	if (netdev) {
584 		dev_info(&adapter->pdev->dev, "Net device Info\n");
585 		pr_info("Device Name     state            "
586 			"trans_start\n");
587 		pr_info("%-15s %016lX %016lX\n",
588 			netdev->name,
589 			netdev->state,
590 			dev_trans_start(netdev));
591 	}
592 
593 	/* Print Registers */
594 	dev_info(&adapter->pdev->dev, "Register Dump\n");
595 	pr_info(" Register Name   Value\n");
596 	for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
597 	     reginfo->name; reginfo++) {
598 		ixgbe_regdump(hw, reginfo);
599 	}
600 
601 	/* Print TX Ring Summary */
602 	if (!netdev || !netif_running(netdev))
603 		return;
604 
605 	dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
606 	pr_info(" %s     %s              %s        %s\n",
607 		"Queue [NTU] [NTC] [bi(ntc)->dma  ]",
608 		"leng", "ntw", "timestamp");
609 	for (n = 0; n < adapter->num_tx_queues; n++) {
610 		ring = adapter->tx_ring[n];
611 		ixgbe_print_buffer(ring, n);
612 	}
613 
614 	for (n = 0; n < adapter->num_xdp_queues; n++) {
615 		ring = adapter->xdp_ring[n];
616 		ixgbe_print_buffer(ring, n);
617 	}
618 
619 	/* Print TX Rings */
620 	if (!netif_msg_tx_done(adapter))
621 		goto rx_ring_summary;
622 
623 	dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
624 
625 	/* Transmit Descriptor Formats
626 	 *
627 	 * 82598 Advanced Transmit Descriptor
628 	 *   +--------------------------------------------------------------+
629 	 * 0 |         Buffer Address [63:0]                                |
630 	 *   +--------------------------------------------------------------+
631 	 * 8 |  PAYLEN  | POPTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
632 	 *   +--------------------------------------------------------------+
633 	 *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
634 	 *
635 	 * 82598 Advanced Transmit Descriptor (Write-Back Format)
636 	 *   +--------------------------------------------------------------+
637 	 * 0 |                          RSV [63:0]                          |
638 	 *   +--------------------------------------------------------------+
639 	 * 8 |            RSV           |  STA  |          NXTSEQ           |
640 	 *   +--------------------------------------------------------------+
641 	 *   63                       36 35   32 31                         0
642 	 *
643 	 * 82599+ Advanced Transmit Descriptor
644 	 *   +--------------------------------------------------------------+
645 	 * 0 |         Buffer Address [63:0]                                |
646 	 *   +--------------------------------------------------------------+
647 	 * 8 |PAYLEN  |POPTS|CC|IDX  |STA  |DCMD  |DTYP |MAC  |RSV  |DTALEN |
648 	 *   +--------------------------------------------------------------+
649 	 *   63     46 45 40 39 38 36 35 32 31  24 23 20 19 18 17 16 15     0
650 	 *
651 	 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
652 	 *   +--------------------------------------------------------------+
653 	 * 0 |                          RSV [63:0]                          |
654 	 *   +--------------------------------------------------------------+
655 	 * 8 |            RSV           |  STA  |           RSV             |
656 	 *   +--------------------------------------------------------------+
657 	 *   63                       36 35   32 31                         0
658 	 */
659 
660 	for (n = 0; n < adapter->num_tx_queues; n++) {
661 		ring = adapter->tx_ring[n];
662 		pr_info("------------------------------------\n");
663 		pr_info("TX QUEUE INDEX = %d\n", ring->queue_index);
664 		pr_info("------------------------------------\n");
665 		pr_info("%s%s    %s              %s        %s          %s\n",
666 			"T [desc]     [address 63:0  ] ",
667 			"[PlPOIdStDDt Ln] [bi->dma       ] ",
668 			"leng", "ntw", "timestamp", "bi->skb");
669 
670 		for (i = 0; ring->desc && (i < ring->count); i++) {
671 			tx_desc = IXGBE_TX_DESC(ring, i);
672 			tx_buffer = &ring->tx_buffer_info[i];
673 			u0 = (struct my_u0 *)tx_desc;
674 			if (dma_unmap_len(tx_buffer, len) > 0) {
675 				const char *ring_desc;
676 
677 				if (i == ring->next_to_use &&
678 				    i == ring->next_to_clean)
679 					ring_desc = " NTC/U";
680 				else if (i == ring->next_to_use)
681 					ring_desc = " NTU";
682 				else if (i == ring->next_to_clean)
683 					ring_desc = " NTC";
684 				else
685 					ring_desc = "";
686 				pr_info("T [0x%03X]    %016llX %016llX %016llX %08X %p %016llX %p%s",
687 					i,
688 					le64_to_cpu((__force __le64)u0->a),
689 					le64_to_cpu((__force __le64)u0->b),
690 					(u64)dma_unmap_addr(tx_buffer, dma),
691 					dma_unmap_len(tx_buffer, len),
692 					tx_buffer->next_to_watch,
693 					(u64)tx_buffer->time_stamp,
694 					tx_buffer->skb,
695 					ring_desc);
696 
697 				if (netif_msg_pktdata(adapter) &&
698 				    tx_buffer->skb)
699 					print_hex_dump(KERN_INFO, "",
700 						DUMP_PREFIX_ADDRESS, 16, 1,
701 						tx_buffer->skb->data,
702 						dma_unmap_len(tx_buffer, len),
703 						true);
704 			}
705 		}
706 	}
707 
708 	/* Print RX Rings Summary */
709 rx_ring_summary:
710 	dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
711 	pr_info("Queue [NTU] [NTC]\n");
712 	for (n = 0; n < adapter->num_rx_queues; n++) {
713 		rx_ring = adapter->rx_ring[n];
714 		pr_info("%5d %5X %5X\n",
715 			n, rx_ring->next_to_use, rx_ring->next_to_clean);
716 	}
717 
718 	/* Print RX Rings */
719 	if (!netif_msg_rx_status(adapter))
720 		return;
721 
722 	dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
723 
724 	/* Receive Descriptor Formats
725 	 *
726 	 * 82598 Advanced Receive Descriptor (Read) Format
727 	 *    63                                           1        0
728 	 *    +-----------------------------------------------------+
729 	 *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
730 	 *    +----------------------------------------------+------+
731 	 *  8 |       Header Buffer Address [63:1]           |  DD  |
732 	 *    +-----------------------------------------------------+
733 	 *
734 	 *
735 	 * 82598 Advanced Receive Descriptor (Write-Back) Format
736 	 *
737 	 *   63       48 47    32 31  30      21 20 16 15   4 3     0
738 	 *   +------------------------------------------------------+
739 	 * 0 |       RSS Hash /  |SPH| HDR_LEN  | RSV |Packet|  RSS |
740 	 *   | Packet   | IP     |   |          |     | Type | Type |
741 	 *   | Checksum | Ident  |   |          |     |      |      |
742 	 *   +------------------------------------------------------+
743 	 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
744 	 *   +------------------------------------------------------+
745 	 *   63       48 47    32 31            20 19               0
746 	 *
747 	 * 82599+ Advanced Receive Descriptor (Read) Format
748 	 *    63                                           1        0
749 	 *    +-----------------------------------------------------+
750 	 *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
751 	 *    +----------------------------------------------+------+
752 	 *  8 |       Header Buffer Address [63:1]           |  DD  |
753 	 *    +-----------------------------------------------------+
754 	 *
755 	 *
756 	 * 82599+ Advanced Receive Descriptor (Write-Back) Format
757 	 *
758 	 *   63       48 47    32 31  30      21 20 17 16   4 3     0
759 	 *   +------------------------------------------------------+
760 	 * 0 |RSS / Frag Checksum|SPH| HDR_LEN  |RSC- |Packet|  RSS |
761 	 *   |/ RTT / PCoE_PARAM |   |          | CNT | Type | Type |
762 	 *   |/ Flow Dir Flt ID  |   |          |     |      |      |
763 	 *   +------------------------------------------------------+
764 	 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
765 	 *   +------------------------------------------------------+
766 	 *   63       48 47    32 31          20 19                 0
767 	 */
768 
769 	for (n = 0; n < adapter->num_rx_queues; n++) {
770 		rx_ring = adapter->rx_ring[n];
771 		pr_info("------------------------------------\n");
772 		pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
773 		pr_info("------------------------------------\n");
774 		pr_info("%s%s%s\n",
775 			"R  [desc]      [ PktBuf     A0] ",
776 			"[  HeadBuf   DD] [bi->dma       ] [bi->skb       ] ",
777 			"<-- Adv Rx Read format");
778 		pr_info("%s%s%s\n",
779 			"RWB[desc]      [PcsmIpSHl PtRs] ",
780 			"[vl er S cks ln] ---------------- [bi->skb       ] ",
781 			"<-- Adv Rx Write-Back format");
782 
783 		for (i = 0; i < rx_ring->count; i++) {
784 			const char *ring_desc;
785 
786 			if (i == rx_ring->next_to_use)
787 				ring_desc = " NTU";
788 			else if (i == rx_ring->next_to_clean)
789 				ring_desc = " NTC";
790 			else
791 				ring_desc = "";
792 
793 			rx_buffer_info = &rx_ring->rx_buffer_info[i];
794 			rx_desc = IXGBE_RX_DESC(rx_ring, i);
795 			u0 = (struct my_u0 *)rx_desc;
796 			if (rx_desc->wb.upper.length) {
797 				/* Descriptor Done */
798 				pr_info("RWB[0x%03X]     %016llX %016llX ---------------- %p%s\n",
799 					i,
800 					le64_to_cpu((__force __le64)u0->a),
801 					le64_to_cpu((__force __le64)u0->b),
802 					rx_buffer_info->skb,
803 					ring_desc);
804 			} else {
805 				pr_info("R  [0x%03X]     %016llX %016llX %016llX %p%s\n",
806 					i,
807 					le64_to_cpu((__force __le64)u0->a),
808 					le64_to_cpu((__force __le64)u0->b),
809 					(u64)rx_buffer_info->dma,
810 					rx_buffer_info->skb,
811 					ring_desc);
812 
813 				if (netif_msg_pktdata(adapter) &&
814 				    rx_buffer_info->dma) {
815 					print_hex_dump(KERN_INFO, "",
816 					   DUMP_PREFIX_ADDRESS, 16, 1,
817 					   page_address(rx_buffer_info->page) +
818 						    rx_buffer_info->page_offset,
819 					   ixgbe_rx_bufsz(rx_ring), true);
820 				}
821 			}
822 		}
823 	}
824 }
825 
826 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
827 {
828 	u32 ctrl_ext;
829 
830 	/* Let firmware take over control of h/w */
831 	ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
832 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
833 			ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
834 }
835 
836 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
837 {
838 	u32 ctrl_ext;
839 
840 	/* Let firmware know the driver has taken over */
841 	ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
842 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
843 			ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
844 }
845 
846 /**
847  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
848  * @adapter: pointer to adapter struct
849  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
850  * @queue: queue to map the corresponding interrupt to
851  * @msix_vector: the vector to map to the corresponding queue
852  *
853  */
854 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
855 			   u8 queue, u8 msix_vector)
856 {
857 	u32 ivar, index;
858 	struct ixgbe_hw *hw = &adapter->hw;
859 	switch (hw->mac.type) {
860 	case ixgbe_mac_82598EB:
861 		msix_vector |= IXGBE_IVAR_ALLOC_VAL;
862 		if (direction == -1)
863 			direction = 0;
864 		index = (((direction * 64) + queue) >> 2) & 0x1F;
865 		ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
866 		ivar &= ~(0xFF << (8 * (queue & 0x3)));
867 		ivar |= (msix_vector << (8 * (queue & 0x3)));
868 		IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
869 		break;
870 	case ixgbe_mac_82599EB:
871 	case ixgbe_mac_X540:
872 	case ixgbe_mac_X550:
873 	case ixgbe_mac_X550EM_x:
874 	case ixgbe_mac_x550em_a:
875 		if (direction == -1) {
876 			/* other causes */
877 			msix_vector |= IXGBE_IVAR_ALLOC_VAL;
878 			index = ((queue & 1) * 8);
879 			ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
880 			ivar &= ~(0xFF << index);
881 			ivar |= (msix_vector << index);
882 			IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
883 			break;
884 		} else {
885 			/* tx or rx causes */
886 			msix_vector |= IXGBE_IVAR_ALLOC_VAL;
887 			index = ((16 * (queue & 1)) + (8 * direction));
888 			ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
889 			ivar &= ~(0xFF << index);
890 			ivar |= (msix_vector << index);
891 			IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
892 			break;
893 		}
894 	default:
895 		break;
896 	}
897 }
898 
899 void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
900 			    u64 qmask)
901 {
902 	u32 mask;
903 
904 	switch (adapter->hw.mac.type) {
905 	case ixgbe_mac_82598EB:
906 		mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
907 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
908 		break;
909 	case ixgbe_mac_82599EB:
910 	case ixgbe_mac_X540:
911 	case ixgbe_mac_X550:
912 	case ixgbe_mac_X550EM_x:
913 	case ixgbe_mac_x550em_a:
914 		mask = (qmask & 0xFFFFFFFF);
915 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
916 		mask = (qmask >> 32);
917 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
918 		break;
919 	default:
920 		break;
921 	}
922 }
923 
924 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
925 {
926 	struct ixgbe_hw *hw = &adapter->hw;
927 	struct ixgbe_hw_stats *hwstats = &adapter->stats;
928 	int i;
929 	u32 data;
930 
931 	if ((hw->fc.current_mode != ixgbe_fc_full) &&
932 	    (hw->fc.current_mode != ixgbe_fc_rx_pause))
933 		return;
934 
935 	switch (hw->mac.type) {
936 	case ixgbe_mac_82598EB:
937 		data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
938 		break;
939 	default:
940 		data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
941 	}
942 	hwstats->lxoffrxc += data;
943 
944 	/* refill credits (no tx hang) if we received xoff */
945 	if (!data)
946 		return;
947 
948 	for (i = 0; i < adapter->num_tx_queues; i++)
949 		clear_bit(__IXGBE_HANG_CHECK_ARMED,
950 			  &adapter->tx_ring[i]->state);
951 
952 	for (i = 0; i < adapter->num_xdp_queues; i++)
953 		clear_bit(__IXGBE_HANG_CHECK_ARMED,
954 			  &adapter->xdp_ring[i]->state);
955 }
956 
957 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
958 {
959 	struct ixgbe_hw *hw = &adapter->hw;
960 	struct ixgbe_hw_stats *hwstats = &adapter->stats;
961 	u32 xoff[8] = {0};
962 	u8 tc;
963 	int i;
964 	bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
965 
966 	if (adapter->ixgbe_ieee_pfc)
967 		pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
968 
969 	if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
970 		ixgbe_update_xoff_rx_lfc(adapter);
971 		return;
972 	}
973 
974 	/* update stats for each tc, only valid with PFC enabled */
975 	for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
976 		u32 pxoffrxc;
977 
978 		switch (hw->mac.type) {
979 		case ixgbe_mac_82598EB:
980 			pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
981 			break;
982 		default:
983 			pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
984 		}
985 		hwstats->pxoffrxc[i] += pxoffrxc;
986 		/* Get the TC for given UP */
987 		tc = netdev_get_prio_tc_map(adapter->netdev, i);
988 		xoff[tc] += pxoffrxc;
989 	}
990 
991 	/* disarm tx queues that have received xoff frames */
992 	for (i = 0; i < adapter->num_tx_queues; i++) {
993 		struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
994 
995 		tc = tx_ring->dcb_tc;
996 		if (xoff[tc])
997 			clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
998 	}
999 
1000 	for (i = 0; i < adapter->num_xdp_queues; i++) {
1001 		struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i];
1002 
1003 		tc = xdp_ring->dcb_tc;
1004 		if (xoff[tc])
1005 			clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state);
1006 	}
1007 }
1008 
1009 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
1010 {
1011 	return ring->stats.packets;
1012 }
1013 
1014 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1015 {
1016 	unsigned int head, tail;
1017 
1018 	head = ring->next_to_clean;
1019 	tail = ring->next_to_use;
1020 
1021 	return ((head <= tail) ? tail : tail + ring->count) - head;
1022 }
1023 
1024 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1025 {
1026 	u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1027 	u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1028 	u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
1029 
1030 	clear_check_for_tx_hang(tx_ring);
1031 
1032 	/*
1033 	 * Check for a hung queue, but be thorough. This verifies
1034 	 * that a transmit has been completed since the previous
1035 	 * check AND there is at least one packet pending. The
1036 	 * ARMED bit is set to indicate a potential hang. The
1037 	 * bit is cleared if a pause frame is received to remove
1038 	 * false hang detection due to PFC or 802.3x frames. By
1039 	 * requiring this to fail twice we avoid races with
1040 	 * pfc clearing the ARMED bit and conditions where we
1041 	 * run the check_tx_hang logic with a transmit completion
1042 	 * pending but without time to complete it yet.
1043 	 */
1044 	if (tx_done_old == tx_done && tx_pending)
1045 		/* make sure it is true for two checks in a row */
1046 		return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1047 					&tx_ring->state);
1048 	/* update completed stats and continue */
1049 	tx_ring->tx_stats.tx_done_old = tx_done;
1050 	/* reset the countdown */
1051 	clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1052 
1053 	return false;
1054 }
1055 
1056 /**
1057  * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1058  * @adapter: driver private struct
1059  **/
1060 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1061 {
1062 
1063 	/* Do the reset outside of interrupt context */
1064 	if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1065 		set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
1066 		e_warn(drv, "initiating reset due to tx timeout\n");
1067 		ixgbe_service_event_schedule(adapter);
1068 	}
1069 }
1070 
1071 /**
1072  * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate
1073  * @netdev: network interface device structure
1074  * @queue_index: Tx queue to set
1075  * @maxrate: desired maximum transmit bitrate
1076  **/
1077 static int ixgbe_tx_maxrate(struct net_device *netdev,
1078 			    int queue_index, u32 maxrate)
1079 {
1080 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
1081 	struct ixgbe_hw *hw = &adapter->hw;
1082 	u32 bcnrc_val = ixgbe_link_mbps(adapter);
1083 
1084 	if (!maxrate)
1085 		return 0;
1086 
1087 	/* Calculate the rate factor values to set */
1088 	bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT;
1089 	bcnrc_val /= maxrate;
1090 
1091 	/* clear everything but the rate factor */
1092 	bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK |
1093 	IXGBE_RTTBCNRC_RF_DEC_MASK;
1094 
1095 	/* enable the rate scheduler */
1096 	bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA;
1097 
1098 	IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index);
1099 	IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
1100 
1101 	return 0;
1102 }
1103 
1104 /**
1105  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
1106  * @q_vector: structure containing interrupt and ring information
1107  * @tx_ring: tx ring to clean
1108  * @napi_budget: Used to determine if we are in netpoll
1109  **/
1110 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
1111 			       struct ixgbe_ring *tx_ring, int napi_budget)
1112 {
1113 	struct ixgbe_adapter *adapter = q_vector->adapter;
1114 	struct ixgbe_tx_buffer *tx_buffer;
1115 	union ixgbe_adv_tx_desc *tx_desc;
1116 	unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0;
1117 	unsigned int budget = q_vector->tx.work_limit;
1118 	unsigned int i = tx_ring->next_to_clean;
1119 
1120 	if (test_bit(__IXGBE_DOWN, &adapter->state))
1121 		return true;
1122 
1123 	tx_buffer = &tx_ring->tx_buffer_info[i];
1124 	tx_desc = IXGBE_TX_DESC(tx_ring, i);
1125 	i -= tx_ring->count;
1126 
1127 	do {
1128 		union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1129 
1130 		/* if next_to_watch is not set then there is no work pending */
1131 		if (!eop_desc)
1132 			break;
1133 
1134 		/* prevent any other reads prior to eop_desc */
1135 		smp_rmb();
1136 
1137 		/* if DD is not set pending work has not been completed */
1138 		if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1139 			break;
1140 
1141 		/* clear next_to_watch to prevent false hangs */
1142 		tx_buffer->next_to_watch = NULL;
1143 
1144 		/* update the statistics for this packet */
1145 		total_bytes += tx_buffer->bytecount;
1146 		total_packets += tx_buffer->gso_segs;
1147 		if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC)
1148 			total_ipsec++;
1149 
1150 		/* free the skb */
1151 		if (ring_is_xdp(tx_ring))
1152 			xdp_return_frame(tx_buffer->xdpf);
1153 		else
1154 			napi_consume_skb(tx_buffer->skb, napi_budget);
1155 
1156 		/* unmap skb header data */
1157 		dma_unmap_single(tx_ring->dev,
1158 				 dma_unmap_addr(tx_buffer, dma),
1159 				 dma_unmap_len(tx_buffer, len),
1160 				 DMA_TO_DEVICE);
1161 
1162 		/* clear tx_buffer data */
1163 		dma_unmap_len_set(tx_buffer, len, 0);
1164 
1165 		/* unmap remaining buffers */
1166 		while (tx_desc != eop_desc) {
1167 			tx_buffer++;
1168 			tx_desc++;
1169 			i++;
1170 			if (unlikely(!i)) {
1171 				i -= tx_ring->count;
1172 				tx_buffer = tx_ring->tx_buffer_info;
1173 				tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1174 			}
1175 
1176 			/* unmap any remaining paged data */
1177 			if (dma_unmap_len(tx_buffer, len)) {
1178 				dma_unmap_page(tx_ring->dev,
1179 					       dma_unmap_addr(tx_buffer, dma),
1180 					       dma_unmap_len(tx_buffer, len),
1181 					       DMA_TO_DEVICE);
1182 				dma_unmap_len_set(tx_buffer, len, 0);
1183 			}
1184 		}
1185 
1186 		/* move us one more past the eop_desc for start of next pkt */
1187 		tx_buffer++;
1188 		tx_desc++;
1189 		i++;
1190 		if (unlikely(!i)) {
1191 			i -= tx_ring->count;
1192 			tx_buffer = tx_ring->tx_buffer_info;
1193 			tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1194 		}
1195 
1196 		/* issue prefetch for next Tx descriptor */
1197 		prefetch(tx_desc);
1198 
1199 		/* update budget accounting */
1200 		budget--;
1201 	} while (likely(budget));
1202 
1203 	i += tx_ring->count;
1204 	tx_ring->next_to_clean = i;
1205 	u64_stats_update_begin(&tx_ring->syncp);
1206 	tx_ring->stats.bytes += total_bytes;
1207 	tx_ring->stats.packets += total_packets;
1208 	u64_stats_update_end(&tx_ring->syncp);
1209 	q_vector->tx.total_bytes += total_bytes;
1210 	q_vector->tx.total_packets += total_packets;
1211 	adapter->tx_ipsec += total_ipsec;
1212 
1213 	if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1214 		/* schedule immediate reset if we believe we hung */
1215 		struct ixgbe_hw *hw = &adapter->hw;
1216 		e_err(drv, "Detected Tx Unit Hang %s\n"
1217 			"  Tx Queue             <%d>\n"
1218 			"  TDH, TDT             <%x>, <%x>\n"
1219 			"  next_to_use          <%x>\n"
1220 			"  next_to_clean        <%x>\n"
1221 			"tx_buffer_info[next_to_clean]\n"
1222 			"  time_stamp           <%lx>\n"
1223 			"  jiffies              <%lx>\n",
1224 			ring_is_xdp(tx_ring) ? "(XDP)" : "",
1225 			tx_ring->queue_index,
1226 			IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1227 			IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1228 			tx_ring->next_to_use, i,
1229 			tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1230 
1231 		if (!ring_is_xdp(tx_ring))
1232 			netif_stop_subqueue(tx_ring->netdev,
1233 					    tx_ring->queue_index);
1234 
1235 		e_info(probe,
1236 		       "tx hang %d detected on queue %d, resetting adapter\n",
1237 			adapter->tx_timeout_count + 1, tx_ring->queue_index);
1238 
1239 		/* schedule immediate reset if we believe we hung */
1240 		ixgbe_tx_timeout_reset(adapter);
1241 
1242 		/* the adapter is about to reset, no point in enabling stuff */
1243 		return true;
1244 	}
1245 
1246 	if (ring_is_xdp(tx_ring))
1247 		return !!budget;
1248 
1249 	netdev_tx_completed_queue(txring_txq(tx_ring),
1250 				  total_packets, total_bytes);
1251 
1252 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1253 	if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1254 		     (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1255 		/* Make sure that anybody stopping the queue after this
1256 		 * sees the new next_to_clean.
1257 		 */
1258 		smp_mb();
1259 		if (__netif_subqueue_stopped(tx_ring->netdev,
1260 					     tx_ring->queue_index)
1261 		    && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1262 			netif_wake_subqueue(tx_ring->netdev,
1263 					    tx_ring->queue_index);
1264 			++tx_ring->tx_stats.restart_queue;
1265 		}
1266 	}
1267 
1268 	return !!budget;
1269 }
1270 
1271 #ifdef CONFIG_IXGBE_DCA
1272 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1273 				struct ixgbe_ring *tx_ring,
1274 				int cpu)
1275 {
1276 	struct ixgbe_hw *hw = &adapter->hw;
1277 	u32 txctrl = 0;
1278 	u16 reg_offset;
1279 
1280 	if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1281 		txctrl = dca3_get_tag(tx_ring->dev, cpu);
1282 
1283 	switch (hw->mac.type) {
1284 	case ixgbe_mac_82598EB:
1285 		reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1286 		break;
1287 	case ixgbe_mac_82599EB:
1288 	case ixgbe_mac_X540:
1289 		reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1290 		txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1291 		break;
1292 	default:
1293 		/* for unknown hardware do not write register */
1294 		return;
1295 	}
1296 
1297 	/*
1298 	 * We can enable relaxed ordering for reads, but not writes when
1299 	 * DCA is enabled.  This is due to a known issue in some chipsets
1300 	 * which will cause the DCA tag to be cleared.
1301 	 */
1302 	txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1303 		  IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1304 		  IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1305 
1306 	IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1307 }
1308 
1309 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1310 				struct ixgbe_ring *rx_ring,
1311 				int cpu)
1312 {
1313 	struct ixgbe_hw *hw = &adapter->hw;
1314 	u32 rxctrl = 0;
1315 	u8 reg_idx = rx_ring->reg_idx;
1316 
1317 	if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1318 		rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1319 
1320 	switch (hw->mac.type) {
1321 	case ixgbe_mac_82599EB:
1322 	case ixgbe_mac_X540:
1323 		rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1324 		break;
1325 	default:
1326 		break;
1327 	}
1328 
1329 	/*
1330 	 * We can enable relaxed ordering for reads, but not writes when
1331 	 * DCA is enabled.  This is due to a known issue in some chipsets
1332 	 * which will cause the DCA tag to be cleared.
1333 	 */
1334 	rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1335 		  IXGBE_DCA_RXCTRL_DATA_DCA_EN |
1336 		  IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1337 
1338 	IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1339 }
1340 
1341 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1342 {
1343 	struct ixgbe_adapter *adapter = q_vector->adapter;
1344 	struct ixgbe_ring *ring;
1345 	int cpu = get_cpu();
1346 
1347 	if (q_vector->cpu == cpu)
1348 		goto out_no_update;
1349 
1350 	ixgbe_for_each_ring(ring, q_vector->tx)
1351 		ixgbe_update_tx_dca(adapter, ring, cpu);
1352 
1353 	ixgbe_for_each_ring(ring, q_vector->rx)
1354 		ixgbe_update_rx_dca(adapter, ring, cpu);
1355 
1356 	q_vector->cpu = cpu;
1357 out_no_update:
1358 	put_cpu();
1359 }
1360 
1361 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1362 {
1363 	int i;
1364 
1365 	/* always use CB2 mode, difference is masked in the CB driver */
1366 	if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1367 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1368 				IXGBE_DCA_CTRL_DCA_MODE_CB2);
1369 	else
1370 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1371 				IXGBE_DCA_CTRL_DCA_DISABLE);
1372 
1373 	for (i = 0; i < adapter->num_q_vectors; i++) {
1374 		adapter->q_vector[i]->cpu = -1;
1375 		ixgbe_update_dca(adapter->q_vector[i]);
1376 	}
1377 }
1378 
1379 static int __ixgbe_notify_dca(struct device *dev, void *data)
1380 {
1381 	struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1382 	unsigned long event = *(unsigned long *)data;
1383 
1384 	if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1385 		return 0;
1386 
1387 	switch (event) {
1388 	case DCA_PROVIDER_ADD:
1389 		/* if we're already enabled, don't do it again */
1390 		if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1391 			break;
1392 		if (dca_add_requester(dev) == 0) {
1393 			adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1394 			IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1395 					IXGBE_DCA_CTRL_DCA_MODE_CB2);
1396 			break;
1397 		}
1398 		fallthrough; /* DCA is disabled. */
1399 	case DCA_PROVIDER_REMOVE:
1400 		if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1401 			dca_remove_requester(dev);
1402 			adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1403 			IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1404 					IXGBE_DCA_CTRL_DCA_DISABLE);
1405 		}
1406 		break;
1407 	}
1408 
1409 	return 0;
1410 }
1411 
1412 #endif /* CONFIG_IXGBE_DCA */
1413 
1414 #define IXGBE_RSS_L4_TYPES_MASK \
1415 	((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1416 	 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1417 	 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1418 	 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1419 
1420 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1421 				 union ixgbe_adv_rx_desc *rx_desc,
1422 				 struct sk_buff *skb)
1423 {
1424 	u16 rss_type;
1425 
1426 	if (!(ring->netdev->features & NETIF_F_RXHASH))
1427 		return;
1428 
1429 	rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1430 		   IXGBE_RXDADV_RSSTYPE_MASK;
1431 
1432 	if (!rss_type)
1433 		return;
1434 
1435 	skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1436 		     (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1437 		     PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
1438 }
1439 
1440 #ifdef IXGBE_FCOE
1441 /**
1442  * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1443  * @ring: structure containing ring specific data
1444  * @rx_desc: advanced rx descriptor
1445  *
1446  * Returns : true if it is FCoE pkt
1447  */
1448 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1449 				    union ixgbe_adv_rx_desc *rx_desc)
1450 {
1451 	__le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1452 
1453 	return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1454 	       ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1455 		(cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1456 			     IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1457 }
1458 
1459 #endif /* IXGBE_FCOE */
1460 /**
1461  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1462  * @ring: structure containing ring specific data
1463  * @rx_desc: current Rx descriptor being processed
1464  * @skb: skb currently being received and modified
1465  **/
1466 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1467 				     union ixgbe_adv_rx_desc *rx_desc,
1468 				     struct sk_buff *skb)
1469 {
1470 	__le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1471 	bool encap_pkt = false;
1472 
1473 	skb_checksum_none_assert(skb);
1474 
1475 	/* Rx csum disabled */
1476 	if (!(ring->netdev->features & NETIF_F_RXCSUM))
1477 		return;
1478 
1479 	/* check for VXLAN and Geneve packets */
1480 	if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) {
1481 		encap_pkt = true;
1482 		skb->encapsulation = 1;
1483 	}
1484 
1485 	/* if IP and error */
1486 	if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1487 	    ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1488 		ring->rx_stats.csum_err++;
1489 		return;
1490 	}
1491 
1492 	if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1493 		return;
1494 
1495 	if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1496 		/*
1497 		 * 82599 errata, UDP frames with a 0 checksum can be marked as
1498 		 * checksum errors.
1499 		 */
1500 		if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1501 		    test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1502 			return;
1503 
1504 		ring->rx_stats.csum_err++;
1505 		return;
1506 	}
1507 
1508 	/* It must be a TCP or UDP packet with a valid checksum */
1509 	skb->ip_summed = CHECKSUM_UNNECESSARY;
1510 	if (encap_pkt) {
1511 		if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1512 			return;
1513 
1514 		if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1515 			skb->ip_summed = CHECKSUM_NONE;
1516 			return;
1517 		}
1518 		/* If we checked the outer header let the stack know */
1519 		skb->csum_level = 1;
1520 	}
1521 }
1522 
1523 static inline unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring)
1524 {
1525 	return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0;
1526 }
1527 
1528 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1529 				    struct ixgbe_rx_buffer *bi)
1530 {
1531 	struct page *page = bi->page;
1532 	dma_addr_t dma;
1533 
1534 	/* since we are recycling buffers we should seldom need to alloc */
1535 	if (likely(page))
1536 		return true;
1537 
1538 	/* alloc new page for storage */
1539 	page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1540 	if (unlikely(!page)) {
1541 		rx_ring->rx_stats.alloc_rx_page_failed++;
1542 		return false;
1543 	}
1544 
1545 	/* map page for use */
1546 	dma = dma_map_page_attrs(rx_ring->dev, page, 0,
1547 				 ixgbe_rx_pg_size(rx_ring),
1548 				 DMA_FROM_DEVICE,
1549 				 IXGBE_RX_DMA_ATTR);
1550 
1551 	/*
1552 	 * if mapping failed free memory back to system since
1553 	 * there isn't much point in holding memory we can't use
1554 	 */
1555 	if (dma_mapping_error(rx_ring->dev, dma)) {
1556 		__free_pages(page, ixgbe_rx_pg_order(rx_ring));
1557 
1558 		rx_ring->rx_stats.alloc_rx_page_failed++;
1559 		return false;
1560 	}
1561 
1562 	bi->dma = dma;
1563 	bi->page = page;
1564 	bi->page_offset = ixgbe_rx_offset(rx_ring);
1565 	page_ref_add(page, USHRT_MAX - 1);
1566 	bi->pagecnt_bias = USHRT_MAX;
1567 	rx_ring->rx_stats.alloc_rx_page++;
1568 
1569 	return true;
1570 }
1571 
1572 /**
1573  * ixgbe_alloc_rx_buffers - Replace used receive buffers
1574  * @rx_ring: ring to place buffers on
1575  * @cleaned_count: number of buffers to replace
1576  **/
1577 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1578 {
1579 	union ixgbe_adv_rx_desc *rx_desc;
1580 	struct ixgbe_rx_buffer *bi;
1581 	u16 i = rx_ring->next_to_use;
1582 	u16 bufsz;
1583 
1584 	/* nothing to do */
1585 	if (!cleaned_count)
1586 		return;
1587 
1588 	rx_desc = IXGBE_RX_DESC(rx_ring, i);
1589 	bi = &rx_ring->rx_buffer_info[i];
1590 	i -= rx_ring->count;
1591 
1592 	bufsz = ixgbe_rx_bufsz(rx_ring);
1593 
1594 	do {
1595 		if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1596 			break;
1597 
1598 		/* sync the buffer for use by the device */
1599 		dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
1600 						 bi->page_offset, bufsz,
1601 						 DMA_FROM_DEVICE);
1602 
1603 		/*
1604 		 * Refresh the desc even if buffer_addrs didn't change
1605 		 * because each write-back erases this info.
1606 		 */
1607 		rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1608 
1609 		rx_desc++;
1610 		bi++;
1611 		i++;
1612 		if (unlikely(!i)) {
1613 			rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1614 			bi = rx_ring->rx_buffer_info;
1615 			i -= rx_ring->count;
1616 		}
1617 
1618 		/* clear the length for the next_to_use descriptor */
1619 		rx_desc->wb.upper.length = 0;
1620 
1621 		cleaned_count--;
1622 	} while (cleaned_count);
1623 
1624 	i += rx_ring->count;
1625 
1626 	if (rx_ring->next_to_use != i) {
1627 		rx_ring->next_to_use = i;
1628 
1629 		/* update next to alloc since we have filled the ring */
1630 		rx_ring->next_to_alloc = i;
1631 
1632 		/* Force memory writes to complete before letting h/w
1633 		 * know there are new descriptors to fetch.  (Only
1634 		 * applicable for weak-ordered memory model archs,
1635 		 * such as IA-64).
1636 		 */
1637 		wmb();
1638 		writel(i, rx_ring->tail);
1639 	}
1640 }
1641 
1642 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1643 				   struct sk_buff *skb)
1644 {
1645 	u16 hdr_len = skb_headlen(skb);
1646 
1647 	/* set gso_size to avoid messing up TCP MSS */
1648 	skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1649 						 IXGBE_CB(skb)->append_cnt);
1650 	skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1651 }
1652 
1653 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1654 				   struct sk_buff *skb)
1655 {
1656 	/* if append_cnt is 0 then frame is not RSC */
1657 	if (!IXGBE_CB(skb)->append_cnt)
1658 		return;
1659 
1660 	rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1661 	rx_ring->rx_stats.rsc_flush++;
1662 
1663 	ixgbe_set_rsc_gso_size(rx_ring, skb);
1664 
1665 	/* gso_size is computed using append_cnt so always clear it last */
1666 	IXGBE_CB(skb)->append_cnt = 0;
1667 }
1668 
1669 /**
1670  * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1671  * @rx_ring: rx descriptor ring packet is being transacted on
1672  * @rx_desc: pointer to the EOP Rx descriptor
1673  * @skb: pointer to current skb being populated
1674  *
1675  * This function checks the ring, descriptor, and packet information in
1676  * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1677  * other fields within the skb.
1678  **/
1679 void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1680 			      union ixgbe_adv_rx_desc *rx_desc,
1681 			      struct sk_buff *skb)
1682 {
1683 	struct net_device *dev = rx_ring->netdev;
1684 	u32 flags = rx_ring->q_vector->adapter->flags;
1685 
1686 	ixgbe_update_rsc_stats(rx_ring, skb);
1687 
1688 	ixgbe_rx_hash(rx_ring, rx_desc, skb);
1689 
1690 	ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1691 
1692 	if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED))
1693 		ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
1694 
1695 	if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1696 	    ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1697 		u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1698 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1699 	}
1700 
1701 	if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP))
1702 		ixgbe_ipsec_rx(rx_ring, rx_desc, skb);
1703 
1704 	/* record Rx queue, or update MACVLAN statistics */
1705 	if (netif_is_ixgbe(dev))
1706 		skb_record_rx_queue(skb, rx_ring->queue_index);
1707 	else
1708 		macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true,
1709 				 false);
1710 
1711 	skb->protocol = eth_type_trans(skb, dev);
1712 }
1713 
1714 void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1715 		  struct sk_buff *skb)
1716 {
1717 	napi_gro_receive(&q_vector->napi, skb);
1718 }
1719 
1720 /**
1721  * ixgbe_is_non_eop - process handling of non-EOP buffers
1722  * @rx_ring: Rx ring being processed
1723  * @rx_desc: Rx descriptor for current buffer
1724  * @skb: Current socket buffer containing buffer in progress
1725  *
1726  * This function updates next to clean.  If the buffer is an EOP buffer
1727  * this function exits returning false, otherwise it will place the
1728  * sk_buff in the next buffer to be chained and return true indicating
1729  * that this is in fact a non-EOP buffer.
1730  **/
1731 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1732 			     union ixgbe_adv_rx_desc *rx_desc,
1733 			     struct sk_buff *skb)
1734 {
1735 	u32 ntc = rx_ring->next_to_clean + 1;
1736 
1737 	/* fetch, update, and store next to clean */
1738 	ntc = (ntc < rx_ring->count) ? ntc : 0;
1739 	rx_ring->next_to_clean = ntc;
1740 
1741 	prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1742 
1743 	/* update RSC append count if present */
1744 	if (ring_is_rsc_enabled(rx_ring)) {
1745 		__le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1746 				     cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1747 
1748 		if (unlikely(rsc_enabled)) {
1749 			u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1750 
1751 			rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1752 			IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1753 
1754 			/* update ntc based on RSC value */
1755 			ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1756 			ntc &= IXGBE_RXDADV_NEXTP_MASK;
1757 			ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1758 		}
1759 	}
1760 
1761 	/* if we are the last buffer then there is nothing else to do */
1762 	if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1763 		return false;
1764 
1765 	/* place skb in next buffer to be received */
1766 	rx_ring->rx_buffer_info[ntc].skb = skb;
1767 	rx_ring->rx_stats.non_eop_descs++;
1768 
1769 	return true;
1770 }
1771 
1772 /**
1773  * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1774  * @rx_ring: rx descriptor ring packet is being transacted on
1775  * @skb: pointer to current skb being adjusted
1776  *
1777  * This function is an ixgbe specific version of __pskb_pull_tail.  The
1778  * main difference between this version and the original function is that
1779  * this function can make several assumptions about the state of things
1780  * that allow for significant optimizations versus the standard function.
1781  * As a result we can do things like drop a frag and maintain an accurate
1782  * truesize for the skb.
1783  */
1784 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1785 			    struct sk_buff *skb)
1786 {
1787 	skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
1788 	unsigned char *va;
1789 	unsigned int pull_len;
1790 
1791 	/*
1792 	 * it is valid to use page_address instead of kmap since we are
1793 	 * working with pages allocated out of the lomem pool per
1794 	 * alloc_page(GFP_ATOMIC)
1795 	 */
1796 	va = skb_frag_address(frag);
1797 
1798 	/*
1799 	 * we need the header to contain the greater of either ETH_HLEN or
1800 	 * 60 bytes if the skb->len is less than 60 for skb_pad.
1801 	 */
1802 	pull_len = eth_get_headlen(skb->dev, va, IXGBE_RX_HDR_SIZE);
1803 
1804 	/* align pull length to size of long to optimize memcpy performance */
1805 	skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1806 
1807 	/* update all of the pointers */
1808 	skb_frag_size_sub(frag, pull_len);
1809 	skb_frag_off_add(frag, pull_len);
1810 	skb->data_len -= pull_len;
1811 	skb->tail += pull_len;
1812 }
1813 
1814 /**
1815  * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1816  * @rx_ring: rx descriptor ring packet is being transacted on
1817  * @skb: pointer to current skb being updated
1818  *
1819  * This function provides a basic DMA sync up for the first fragment of an
1820  * skb.  The reason for doing this is that the first fragment cannot be
1821  * unmapped until we have reached the end of packet descriptor for a buffer
1822  * chain.
1823  */
1824 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1825 				struct sk_buff *skb)
1826 {
1827 	if (ring_uses_build_skb(rx_ring)) {
1828 		unsigned long offset = (unsigned long)(skb->data) & ~PAGE_MASK;
1829 
1830 		dma_sync_single_range_for_cpu(rx_ring->dev,
1831 					      IXGBE_CB(skb)->dma,
1832 					      offset,
1833 					      skb_headlen(skb),
1834 					      DMA_FROM_DEVICE);
1835 	} else {
1836 		skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
1837 
1838 		dma_sync_single_range_for_cpu(rx_ring->dev,
1839 					      IXGBE_CB(skb)->dma,
1840 					      skb_frag_off(frag),
1841 					      skb_frag_size(frag),
1842 					      DMA_FROM_DEVICE);
1843 	}
1844 
1845 	/* If the page was released, just unmap it. */
1846 	if (unlikely(IXGBE_CB(skb)->page_released)) {
1847 		dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma,
1848 				     ixgbe_rx_pg_size(rx_ring),
1849 				     DMA_FROM_DEVICE,
1850 				     IXGBE_RX_DMA_ATTR);
1851 	}
1852 }
1853 
1854 /**
1855  * ixgbe_cleanup_headers - Correct corrupted or empty headers
1856  * @rx_ring: rx descriptor ring packet is being transacted on
1857  * @rx_desc: pointer to the EOP Rx descriptor
1858  * @skb: pointer to current skb being fixed
1859  *
1860  * Check if the skb is valid in the XDP case it will be an error pointer.
1861  * Return true in this case to abort processing and advance to next
1862  * descriptor.
1863  *
1864  * Check for corrupted packet headers caused by senders on the local L2
1865  * embedded NIC switch not setting up their Tx Descriptors right.  These
1866  * should be very rare.
1867  *
1868  * Also address the case where we are pulling data in on pages only
1869  * and as such no data is present in the skb header.
1870  *
1871  * In addition if skb is not at least 60 bytes we need to pad it so that
1872  * it is large enough to qualify as a valid Ethernet frame.
1873  *
1874  * Returns true if an error was encountered and skb was freed.
1875  **/
1876 bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1877 			   union ixgbe_adv_rx_desc *rx_desc,
1878 			   struct sk_buff *skb)
1879 {
1880 	struct net_device *netdev = rx_ring->netdev;
1881 
1882 	/* XDP packets use error pointer so abort at this point */
1883 	if (IS_ERR(skb))
1884 		return true;
1885 
1886 	/* Verify netdev is present, and that packet does not have any
1887 	 * errors that would be unacceptable to the netdev.
1888 	 */
1889 	if (!netdev ||
1890 	    (unlikely(ixgbe_test_staterr(rx_desc,
1891 					 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1892 	     !(netdev->features & NETIF_F_RXALL)))) {
1893 		dev_kfree_skb_any(skb);
1894 		return true;
1895 	}
1896 
1897 	/* place header in linear portion of buffer */
1898 	if (!skb_headlen(skb))
1899 		ixgbe_pull_tail(rx_ring, skb);
1900 
1901 #ifdef IXGBE_FCOE
1902 	/* do not attempt to pad FCoE Frames as this will disrupt DDP */
1903 	if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1904 		return false;
1905 
1906 #endif
1907 	/* if eth_skb_pad returns an error the skb was freed */
1908 	if (eth_skb_pad(skb))
1909 		return true;
1910 
1911 	return false;
1912 }
1913 
1914 /**
1915  * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1916  * @rx_ring: rx descriptor ring to store buffers on
1917  * @old_buff: donor buffer to have page reused
1918  *
1919  * Synchronizes page for reuse by the adapter
1920  **/
1921 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1922 				struct ixgbe_rx_buffer *old_buff)
1923 {
1924 	struct ixgbe_rx_buffer *new_buff;
1925 	u16 nta = rx_ring->next_to_alloc;
1926 
1927 	new_buff = &rx_ring->rx_buffer_info[nta];
1928 
1929 	/* update, and store next to alloc */
1930 	nta++;
1931 	rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1932 
1933 	/* Transfer page from old buffer to new buffer.
1934 	 * Move each member individually to avoid possible store
1935 	 * forwarding stalls and unnecessary copy of skb.
1936 	 */
1937 	new_buff->dma		= old_buff->dma;
1938 	new_buff->page		= old_buff->page;
1939 	new_buff->page_offset	= old_buff->page_offset;
1940 	new_buff->pagecnt_bias	= old_buff->pagecnt_bias;
1941 }
1942 
1943 static inline bool ixgbe_page_is_reserved(struct page *page)
1944 {
1945 	return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
1946 }
1947 
1948 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer)
1949 {
1950 	unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1951 	struct page *page = rx_buffer->page;
1952 
1953 	/* avoid re-using remote pages */
1954 	if (unlikely(ixgbe_page_is_reserved(page)))
1955 		return false;
1956 
1957 #if (PAGE_SIZE < 8192)
1958 	/* if we are only owner of page we can reuse it */
1959 	if (unlikely((page_ref_count(page) - pagecnt_bias) > 1))
1960 		return false;
1961 #else
1962 	/* The last offset is a bit aggressive in that we assume the
1963 	 * worst case of FCoE being enabled and using a 3K buffer.
1964 	 * However this should have minimal impact as the 1K extra is
1965 	 * still less than one buffer in size.
1966 	 */
1967 #define IXGBE_LAST_OFFSET \
1968 	(SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K)
1969 	if (rx_buffer->page_offset > IXGBE_LAST_OFFSET)
1970 		return false;
1971 #endif
1972 
1973 	/* If we have drained the page fragment pool we need to update
1974 	 * the pagecnt_bias and page count so that we fully restock the
1975 	 * number of references the driver holds.
1976 	 */
1977 	if (unlikely(pagecnt_bias == 1)) {
1978 		page_ref_add(page, USHRT_MAX - 1);
1979 		rx_buffer->pagecnt_bias = USHRT_MAX;
1980 	}
1981 
1982 	return true;
1983 }
1984 
1985 /**
1986  * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1987  * @rx_ring: rx descriptor ring to transact packets on
1988  * @rx_buffer: buffer containing page to add
1989  * @skb: sk_buff to place the data into
1990  * @size: size of data in rx_buffer
1991  *
1992  * This function will add the data contained in rx_buffer->page to the skb.
1993  * This is done either through a direct copy if the data in the buffer is
1994  * less than the skb header size, otherwise it will just attach the page as
1995  * a frag to the skb.
1996  *
1997  * The function will then update the page offset if necessary and return
1998  * true if the buffer can be reused by the adapter.
1999  **/
2000 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
2001 			      struct ixgbe_rx_buffer *rx_buffer,
2002 			      struct sk_buff *skb,
2003 			      unsigned int size)
2004 {
2005 #if (PAGE_SIZE < 8192)
2006 	unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2007 #else
2008 	unsigned int truesize = ring_uses_build_skb(rx_ring) ?
2009 				SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) :
2010 				SKB_DATA_ALIGN(size);
2011 #endif
2012 	skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
2013 			rx_buffer->page_offset, size, truesize);
2014 #if (PAGE_SIZE < 8192)
2015 	rx_buffer->page_offset ^= truesize;
2016 #else
2017 	rx_buffer->page_offset += truesize;
2018 #endif
2019 }
2020 
2021 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring,
2022 						   union ixgbe_adv_rx_desc *rx_desc,
2023 						   struct sk_buff **skb,
2024 						   const unsigned int size)
2025 {
2026 	struct ixgbe_rx_buffer *rx_buffer;
2027 
2028 	rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2029 	prefetchw(rx_buffer->page);
2030 	*skb = rx_buffer->skb;
2031 
2032 	/* Delay unmapping of the first packet. It carries the header
2033 	 * information, HW may still access the header after the writeback.
2034 	 * Only unmap it when EOP is reached
2035 	 */
2036 	if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) {
2037 		if (!*skb)
2038 			goto skip_sync;
2039 	} else {
2040 		if (*skb)
2041 			ixgbe_dma_sync_frag(rx_ring, *skb);
2042 	}
2043 
2044 	/* we are reusing so sync this buffer for CPU use */
2045 	dma_sync_single_range_for_cpu(rx_ring->dev,
2046 				      rx_buffer->dma,
2047 				      rx_buffer->page_offset,
2048 				      size,
2049 				      DMA_FROM_DEVICE);
2050 skip_sync:
2051 	rx_buffer->pagecnt_bias--;
2052 
2053 	return rx_buffer;
2054 }
2055 
2056 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring,
2057 				struct ixgbe_rx_buffer *rx_buffer,
2058 				struct sk_buff *skb)
2059 {
2060 	if (ixgbe_can_reuse_rx_page(rx_buffer)) {
2061 		/* hand second half of page back to the ring */
2062 		ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2063 	} else {
2064 		if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) {
2065 			/* the page has been released from the ring */
2066 			IXGBE_CB(skb)->page_released = true;
2067 		} else {
2068 			/* we are not reusing the buffer so unmap it */
2069 			dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
2070 					     ixgbe_rx_pg_size(rx_ring),
2071 					     DMA_FROM_DEVICE,
2072 					     IXGBE_RX_DMA_ATTR);
2073 		}
2074 		__page_frag_cache_drain(rx_buffer->page,
2075 					rx_buffer->pagecnt_bias);
2076 	}
2077 
2078 	/* clear contents of rx_buffer */
2079 	rx_buffer->page = NULL;
2080 	rx_buffer->skb = NULL;
2081 }
2082 
2083 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring,
2084 					   struct ixgbe_rx_buffer *rx_buffer,
2085 					   struct xdp_buff *xdp,
2086 					   union ixgbe_adv_rx_desc *rx_desc)
2087 {
2088 	unsigned int size = xdp->data_end - xdp->data;
2089 #if (PAGE_SIZE < 8192)
2090 	unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2091 #else
2092 	unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end -
2093 					       xdp->data_hard_start);
2094 #endif
2095 	struct sk_buff *skb;
2096 
2097 	/* prefetch first cache line of first page */
2098 	net_prefetch(xdp->data);
2099 
2100 	/* Note, we get here by enabling legacy-rx via:
2101 	 *
2102 	 *    ethtool --set-priv-flags <dev> legacy-rx on
2103 	 *
2104 	 * In this mode, we currently get 0 extra XDP headroom as
2105 	 * opposed to having legacy-rx off, where we process XDP
2106 	 * packets going to stack via ixgbe_build_skb(). The latter
2107 	 * provides us currently with 192 bytes of headroom.
2108 	 *
2109 	 * For ixgbe_construct_skb() mode it means that the
2110 	 * xdp->data_meta will always point to xdp->data, since
2111 	 * the helper cannot expand the head. Should this ever
2112 	 * change in future for legacy-rx mode on, then lets also
2113 	 * add xdp->data_meta handling here.
2114 	 */
2115 
2116 	/* allocate a skb to store the frags */
2117 	skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE);
2118 	if (unlikely(!skb))
2119 		return NULL;
2120 
2121 	if (size > IXGBE_RX_HDR_SIZE) {
2122 		if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2123 			IXGBE_CB(skb)->dma = rx_buffer->dma;
2124 
2125 		skb_add_rx_frag(skb, 0, rx_buffer->page,
2126 				xdp->data - page_address(rx_buffer->page),
2127 				size, truesize);
2128 #if (PAGE_SIZE < 8192)
2129 		rx_buffer->page_offset ^= truesize;
2130 #else
2131 		rx_buffer->page_offset += truesize;
2132 #endif
2133 	} else {
2134 		memcpy(__skb_put(skb, size),
2135 		       xdp->data, ALIGN(size, sizeof(long)));
2136 		rx_buffer->pagecnt_bias++;
2137 	}
2138 
2139 	return skb;
2140 }
2141 
2142 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring,
2143 				       struct ixgbe_rx_buffer *rx_buffer,
2144 				       struct xdp_buff *xdp,
2145 				       union ixgbe_adv_rx_desc *rx_desc)
2146 {
2147 	unsigned int metasize = xdp->data - xdp->data_meta;
2148 #if (PAGE_SIZE < 8192)
2149 	unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2150 #else
2151 	unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
2152 				SKB_DATA_ALIGN(xdp->data_end -
2153 					       xdp->data_hard_start);
2154 #endif
2155 	struct sk_buff *skb;
2156 
2157 	/* Prefetch first cache line of first page. If xdp->data_meta
2158 	 * is unused, this points extactly as xdp->data, otherwise we
2159 	 * likely have a consumer accessing first few bytes of meta
2160 	 * data, and then actual data.
2161 	 */
2162 	net_prefetch(xdp->data_meta);
2163 
2164 	/* build an skb to around the page buffer */
2165 	skb = build_skb(xdp->data_hard_start, truesize);
2166 	if (unlikely(!skb))
2167 		return NULL;
2168 
2169 	/* update pointers within the skb to store the data */
2170 	skb_reserve(skb, xdp->data - xdp->data_hard_start);
2171 	__skb_put(skb, xdp->data_end - xdp->data);
2172 	if (metasize)
2173 		skb_metadata_set(skb, metasize);
2174 
2175 	/* record DMA address if this is the start of a chain of buffers */
2176 	if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2177 		IXGBE_CB(skb)->dma = rx_buffer->dma;
2178 
2179 	/* update buffer offset */
2180 #if (PAGE_SIZE < 8192)
2181 	rx_buffer->page_offset ^= truesize;
2182 #else
2183 	rx_buffer->page_offset += truesize;
2184 #endif
2185 
2186 	return skb;
2187 }
2188 
2189 static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter,
2190 				     struct ixgbe_ring *rx_ring,
2191 				     struct xdp_buff *xdp)
2192 {
2193 	int err, result = IXGBE_XDP_PASS;
2194 	struct bpf_prog *xdp_prog;
2195 	struct xdp_frame *xdpf;
2196 	u32 act;
2197 
2198 	rcu_read_lock();
2199 	xdp_prog = READ_ONCE(rx_ring->xdp_prog);
2200 
2201 	if (!xdp_prog)
2202 		goto xdp_out;
2203 
2204 	prefetchw(xdp->data_hard_start); /* xdp_frame write */
2205 
2206 	act = bpf_prog_run_xdp(xdp_prog, xdp);
2207 	switch (act) {
2208 	case XDP_PASS:
2209 		break;
2210 	case XDP_TX:
2211 		xdpf = xdp_convert_buff_to_frame(xdp);
2212 		if (unlikely(!xdpf)) {
2213 			result = IXGBE_XDP_CONSUMED;
2214 			break;
2215 		}
2216 		result = ixgbe_xmit_xdp_ring(adapter, xdpf);
2217 		break;
2218 	case XDP_REDIRECT:
2219 		err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog);
2220 		if (!err)
2221 			result = IXGBE_XDP_REDIR;
2222 		else
2223 			result = IXGBE_XDP_CONSUMED;
2224 		break;
2225 	default:
2226 		bpf_warn_invalid_xdp_action(act);
2227 		fallthrough;
2228 	case XDP_ABORTED:
2229 		trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
2230 		fallthrough; /* handle aborts by dropping packet */
2231 	case XDP_DROP:
2232 		result = IXGBE_XDP_CONSUMED;
2233 		break;
2234 	}
2235 xdp_out:
2236 	rcu_read_unlock();
2237 	return ERR_PTR(-result);
2238 }
2239 
2240 static unsigned int ixgbe_rx_frame_truesize(struct ixgbe_ring *rx_ring,
2241 					    unsigned int size)
2242 {
2243 	unsigned int truesize;
2244 
2245 #if (PAGE_SIZE < 8192)
2246 	truesize = ixgbe_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */
2247 #else
2248 	truesize = ring_uses_build_skb(rx_ring) ?
2249 		SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) +
2250 		SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
2251 		SKB_DATA_ALIGN(size);
2252 #endif
2253 	return truesize;
2254 }
2255 
2256 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring,
2257 				 struct ixgbe_rx_buffer *rx_buffer,
2258 				 unsigned int size)
2259 {
2260 	unsigned int truesize = ixgbe_rx_frame_truesize(rx_ring, size);
2261 #if (PAGE_SIZE < 8192)
2262 	rx_buffer->page_offset ^= truesize;
2263 #else
2264 	rx_buffer->page_offset += truesize;
2265 #endif
2266 }
2267 
2268 /**
2269  * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2270  * @q_vector: structure containing interrupt and ring information
2271  * @rx_ring: rx descriptor ring to transact packets on
2272  * @budget: Total limit on number of packets to process
2273  *
2274  * This function provides a "bounce buffer" approach to Rx interrupt
2275  * processing.  The advantage to this is that on systems that have
2276  * expensive overhead for IOMMU access this provides a means of avoiding
2277  * it by maintaining the mapping of the page to the syste.
2278  *
2279  * Returns amount of work completed
2280  **/
2281 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
2282 			       struct ixgbe_ring *rx_ring,
2283 			       const int budget)
2284 {
2285 	unsigned int total_rx_bytes = 0, total_rx_packets = 0;
2286 	struct ixgbe_adapter *adapter = q_vector->adapter;
2287 #ifdef IXGBE_FCOE
2288 	int ddp_bytes;
2289 	unsigned int mss = 0;
2290 #endif /* IXGBE_FCOE */
2291 	u16 cleaned_count = ixgbe_desc_unused(rx_ring);
2292 	unsigned int xdp_xmit = 0;
2293 	struct xdp_buff xdp;
2294 
2295 	xdp.rxq = &rx_ring->xdp_rxq;
2296 
2297 	/* Frame size depend on rx_ring setup when PAGE_SIZE=4K */
2298 #if (PAGE_SIZE < 8192)
2299 	xdp.frame_sz = ixgbe_rx_frame_truesize(rx_ring, 0);
2300 #endif
2301 
2302 	while (likely(total_rx_packets < budget)) {
2303 		union ixgbe_adv_rx_desc *rx_desc;
2304 		struct ixgbe_rx_buffer *rx_buffer;
2305 		struct sk_buff *skb;
2306 		unsigned int size;
2307 
2308 		/* return some buffers to hardware, one at a time is too slow */
2309 		if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2310 			ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2311 			cleaned_count = 0;
2312 		}
2313 
2314 		rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2315 		size = le16_to_cpu(rx_desc->wb.upper.length);
2316 		if (!size)
2317 			break;
2318 
2319 		/* This memory barrier is needed to keep us from reading
2320 		 * any other fields out of the rx_desc until we know the
2321 		 * descriptor has been written back
2322 		 */
2323 		dma_rmb();
2324 
2325 		rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size);
2326 
2327 		/* retrieve a buffer from the ring */
2328 		if (!skb) {
2329 			xdp.data = page_address(rx_buffer->page) +
2330 				   rx_buffer->page_offset;
2331 			xdp.data_meta = xdp.data;
2332 			xdp.data_hard_start = xdp.data -
2333 					      ixgbe_rx_offset(rx_ring);
2334 			xdp.data_end = xdp.data + size;
2335 #if (PAGE_SIZE > 4096)
2336 			/* At larger PAGE_SIZE, frame_sz depend on len size */
2337 			xdp.frame_sz = ixgbe_rx_frame_truesize(rx_ring, size);
2338 #endif
2339 			skb = ixgbe_run_xdp(adapter, rx_ring, &xdp);
2340 		}
2341 
2342 		if (IS_ERR(skb)) {
2343 			unsigned int xdp_res = -PTR_ERR(skb);
2344 
2345 			if (xdp_res & (IXGBE_XDP_TX | IXGBE_XDP_REDIR)) {
2346 				xdp_xmit |= xdp_res;
2347 				ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size);
2348 			} else {
2349 				rx_buffer->pagecnt_bias++;
2350 			}
2351 			total_rx_packets++;
2352 			total_rx_bytes += size;
2353 		} else if (skb) {
2354 			ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size);
2355 		} else if (ring_uses_build_skb(rx_ring)) {
2356 			skb = ixgbe_build_skb(rx_ring, rx_buffer,
2357 					      &xdp, rx_desc);
2358 		} else {
2359 			skb = ixgbe_construct_skb(rx_ring, rx_buffer,
2360 						  &xdp, rx_desc);
2361 		}
2362 
2363 		/* exit if we failed to retrieve a buffer */
2364 		if (!skb) {
2365 			rx_ring->rx_stats.alloc_rx_buff_failed++;
2366 			rx_buffer->pagecnt_bias++;
2367 			break;
2368 		}
2369 
2370 		ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb);
2371 		cleaned_count++;
2372 
2373 		/* place incomplete frames back on ring for completion */
2374 		if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2375 			continue;
2376 
2377 		/* verify the packet layout is correct */
2378 		if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2379 			continue;
2380 
2381 		/* probably a little skewed due to removing CRC */
2382 		total_rx_bytes += skb->len;
2383 
2384 		/* populate checksum, timestamp, VLAN, and protocol */
2385 		ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2386 
2387 #ifdef IXGBE_FCOE
2388 		/* if ddp, not passing to ULD unless for FCP_RSP or error */
2389 		if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2390 			ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2391 			/* include DDPed FCoE data */
2392 			if (ddp_bytes > 0) {
2393 				if (!mss) {
2394 					mss = rx_ring->netdev->mtu -
2395 						sizeof(struct fcoe_hdr) -
2396 						sizeof(struct fc_frame_header) -
2397 						sizeof(struct fcoe_crc_eof);
2398 					if (mss > 512)
2399 						mss &= ~511;
2400 				}
2401 				total_rx_bytes += ddp_bytes;
2402 				total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2403 								 mss);
2404 			}
2405 			if (!ddp_bytes) {
2406 				dev_kfree_skb_any(skb);
2407 				continue;
2408 			}
2409 		}
2410 
2411 #endif /* IXGBE_FCOE */
2412 		ixgbe_rx_skb(q_vector, skb);
2413 
2414 		/* update budget accounting */
2415 		total_rx_packets++;
2416 	}
2417 
2418 	if (xdp_xmit & IXGBE_XDP_REDIR)
2419 		xdp_do_flush_map();
2420 
2421 	if (xdp_xmit & IXGBE_XDP_TX) {
2422 		struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()];
2423 
2424 		/* Force memory writes to complete before letting h/w
2425 		 * know there are new descriptors to fetch.
2426 		 */
2427 		wmb();
2428 		writel(ring->next_to_use, ring->tail);
2429 	}
2430 
2431 	u64_stats_update_begin(&rx_ring->syncp);
2432 	rx_ring->stats.packets += total_rx_packets;
2433 	rx_ring->stats.bytes += total_rx_bytes;
2434 	u64_stats_update_end(&rx_ring->syncp);
2435 	q_vector->rx.total_packets += total_rx_packets;
2436 	q_vector->rx.total_bytes += total_rx_bytes;
2437 
2438 	return total_rx_packets;
2439 }
2440 
2441 /**
2442  * ixgbe_configure_msix - Configure MSI-X hardware
2443  * @adapter: board private structure
2444  *
2445  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2446  * interrupts.
2447  **/
2448 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2449 {
2450 	struct ixgbe_q_vector *q_vector;
2451 	int v_idx;
2452 	u32 mask;
2453 
2454 	/* Populate MSIX to EITR Select */
2455 	if (adapter->num_vfs > 32) {
2456 		u32 eitrsel = BIT(adapter->num_vfs - 32) - 1;
2457 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2458 	}
2459 
2460 	/*
2461 	 * Populate the IVAR table and set the ITR values to the
2462 	 * corresponding register.
2463 	 */
2464 	for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2465 		struct ixgbe_ring *ring;
2466 		q_vector = adapter->q_vector[v_idx];
2467 
2468 		ixgbe_for_each_ring(ring, q_vector->rx)
2469 			ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2470 
2471 		ixgbe_for_each_ring(ring, q_vector->tx)
2472 			ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2473 
2474 		ixgbe_write_eitr(q_vector);
2475 	}
2476 
2477 	switch (adapter->hw.mac.type) {
2478 	case ixgbe_mac_82598EB:
2479 		ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2480 			       v_idx);
2481 		break;
2482 	case ixgbe_mac_82599EB:
2483 	case ixgbe_mac_X540:
2484 	case ixgbe_mac_X550:
2485 	case ixgbe_mac_X550EM_x:
2486 	case ixgbe_mac_x550em_a:
2487 		ixgbe_set_ivar(adapter, -1, 1, v_idx);
2488 		break;
2489 	default:
2490 		break;
2491 	}
2492 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2493 
2494 	/* set up to autoclear timer, and the vectors */
2495 	mask = IXGBE_EIMS_ENABLE_MASK;
2496 	mask &= ~(IXGBE_EIMS_OTHER |
2497 		  IXGBE_EIMS_MAILBOX |
2498 		  IXGBE_EIMS_LSC);
2499 
2500 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2501 }
2502 
2503 /**
2504  * ixgbe_update_itr - update the dynamic ITR value based on statistics
2505  * @q_vector: structure containing interrupt and ring information
2506  * @ring_container: structure containing ring performance data
2507  *
2508  *      Stores a new ITR value based on packets and byte
2509  *      counts during the last interrupt.  The advantage of per interrupt
2510  *      computation is faster updates and more accurate ITR for the current
2511  *      traffic pattern.  Constants in this function were computed
2512  *      based on theoretical maximum wire speed and thresholds were set based
2513  *      on testing data as well as attempting to minimize response time
2514  *      while increasing bulk throughput.
2515  **/
2516 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2517 			     struct ixgbe_ring_container *ring_container)
2518 {
2519 	unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS |
2520 			   IXGBE_ITR_ADAPTIVE_LATENCY;
2521 	unsigned int avg_wire_size, packets, bytes;
2522 	unsigned long next_update = jiffies;
2523 
2524 	/* If we don't have any rings just leave ourselves set for maximum
2525 	 * possible latency so we take ourselves out of the equation.
2526 	 */
2527 	if (!ring_container->ring)
2528 		return;
2529 
2530 	/* If we didn't update within up to 1 - 2 jiffies we can assume
2531 	 * that either packets are coming in so slow there hasn't been
2532 	 * any work, or that there is so much work that NAPI is dealing
2533 	 * with interrupt moderation and we don't need to do anything.
2534 	 */
2535 	if (time_after(next_update, ring_container->next_update))
2536 		goto clear_counts;
2537 
2538 	packets = ring_container->total_packets;
2539 
2540 	/* We have no packets to actually measure against. This means
2541 	 * either one of the other queues on this vector is active or
2542 	 * we are a Tx queue doing TSO with too high of an interrupt rate.
2543 	 *
2544 	 * When this occurs just tick up our delay by the minimum value
2545 	 * and hope that this extra delay will prevent us from being called
2546 	 * without any work on our queue.
2547 	 */
2548 	if (!packets) {
2549 		itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC;
2550 		if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS)
2551 			itr = IXGBE_ITR_ADAPTIVE_MAX_USECS;
2552 		itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY;
2553 		goto clear_counts;
2554 	}
2555 
2556 	bytes = ring_container->total_bytes;
2557 
2558 	/* If packets are less than 4 or bytes are less than 9000 assume
2559 	 * insufficient data to use bulk rate limiting approach. We are
2560 	 * likely latency driven.
2561 	 */
2562 	if (packets < 4 && bytes < 9000) {
2563 		itr = IXGBE_ITR_ADAPTIVE_LATENCY;
2564 		goto adjust_by_size;
2565 	}
2566 
2567 	/* Between 4 and 48 we can assume that our current interrupt delay
2568 	 * is only slightly too low. As such we should increase it by a small
2569 	 * fixed amount.
2570 	 */
2571 	if (packets < 48) {
2572 		itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC;
2573 		if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS)
2574 			itr = IXGBE_ITR_ADAPTIVE_MAX_USECS;
2575 		goto clear_counts;
2576 	}
2577 
2578 	/* Between 48 and 96 is our "goldilocks" zone where we are working
2579 	 * out "just right". Just report that our current ITR is good for us.
2580 	 */
2581 	if (packets < 96) {
2582 		itr = q_vector->itr >> 2;
2583 		goto clear_counts;
2584 	}
2585 
2586 	/* If packet count is 96 or greater we are likely looking at a slight
2587 	 * overrun of the delay we want. Try halving our delay to see if that
2588 	 * will cut the number of packets in half per interrupt.
2589 	 */
2590 	if (packets < 256) {
2591 		itr = q_vector->itr >> 3;
2592 		if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS)
2593 			itr = IXGBE_ITR_ADAPTIVE_MIN_USECS;
2594 		goto clear_counts;
2595 	}
2596 
2597 	/* The paths below assume we are dealing with a bulk ITR since number
2598 	 * of packets is 256 or greater. We are just going to have to compute
2599 	 * a value and try to bring the count under control, though for smaller
2600 	 * packet sizes there isn't much we can do as NAPI polling will likely
2601 	 * be kicking in sooner rather than later.
2602 	 */
2603 	itr = IXGBE_ITR_ADAPTIVE_BULK;
2604 
2605 adjust_by_size:
2606 	/* If packet counts are 256 or greater we can assume we have a gross
2607 	 * overestimation of what the rate should be. Instead of trying to fine
2608 	 * tune it just use the formula below to try and dial in an exact value
2609 	 * give the current packet size of the frame.
2610 	 */
2611 	avg_wire_size = bytes / packets;
2612 
2613 	/* The following is a crude approximation of:
2614 	 *  wmem_default / (size + overhead) = desired_pkts_per_int
2615 	 *  rate / bits_per_byte / (size + ethernet overhead) = pkt_rate
2616 	 *  (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value
2617 	 *
2618 	 * Assuming wmem_default is 212992 and overhead is 640 bytes per
2619 	 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the
2620 	 * formula down to
2621 	 *
2622 	 *  (170 * (size + 24)) / (size + 640) = ITR
2623 	 *
2624 	 * We first do some math on the packet size and then finally bitshift
2625 	 * by 8 after rounding up. We also have to account for PCIe link speed
2626 	 * difference as ITR scales based on this.
2627 	 */
2628 	if (avg_wire_size <= 60) {
2629 		/* Start at 50k ints/sec */
2630 		avg_wire_size = 5120;
2631 	} else if (avg_wire_size <= 316) {
2632 		/* 50K ints/sec to 16K ints/sec */
2633 		avg_wire_size *= 40;
2634 		avg_wire_size += 2720;
2635 	} else if (avg_wire_size <= 1084) {
2636 		/* 16K ints/sec to 9.2K ints/sec */
2637 		avg_wire_size *= 15;
2638 		avg_wire_size += 11452;
2639 	} else if (avg_wire_size < 1968) {
2640 		/* 9.2K ints/sec to 8K ints/sec */
2641 		avg_wire_size *= 5;
2642 		avg_wire_size += 22420;
2643 	} else {
2644 		/* plateau at a limit of 8K ints/sec */
2645 		avg_wire_size = 32256;
2646 	}
2647 
2648 	/* If we are in low latency mode half our delay which doubles the rate
2649 	 * to somewhere between 100K to 16K ints/sec
2650 	 */
2651 	if (itr & IXGBE_ITR_ADAPTIVE_LATENCY)
2652 		avg_wire_size >>= 1;
2653 
2654 	/* Resultant value is 256 times larger than it needs to be. This
2655 	 * gives us room to adjust the value as needed to either increase
2656 	 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc.
2657 	 *
2658 	 * Use addition as we have already recorded the new latency flag
2659 	 * for the ITR value.
2660 	 */
2661 	switch (q_vector->adapter->link_speed) {
2662 	case IXGBE_LINK_SPEED_10GB_FULL:
2663 	case IXGBE_LINK_SPEED_100_FULL:
2664 	default:
2665 		itr += DIV_ROUND_UP(avg_wire_size,
2666 				    IXGBE_ITR_ADAPTIVE_MIN_INC * 256) *
2667 		       IXGBE_ITR_ADAPTIVE_MIN_INC;
2668 		break;
2669 	case IXGBE_LINK_SPEED_2_5GB_FULL:
2670 	case IXGBE_LINK_SPEED_1GB_FULL:
2671 	case IXGBE_LINK_SPEED_10_FULL:
2672 		if (avg_wire_size > 8064)
2673 			avg_wire_size = 8064;
2674 		itr += DIV_ROUND_UP(avg_wire_size,
2675 				    IXGBE_ITR_ADAPTIVE_MIN_INC * 64) *
2676 		       IXGBE_ITR_ADAPTIVE_MIN_INC;
2677 		break;
2678 	}
2679 
2680 clear_counts:
2681 	/* write back value */
2682 	ring_container->itr = itr;
2683 
2684 	/* next update should occur within next jiffy */
2685 	ring_container->next_update = next_update + 1;
2686 
2687 	ring_container->total_bytes = 0;
2688 	ring_container->total_packets = 0;
2689 }
2690 
2691 /**
2692  * ixgbe_write_eitr - write EITR register in hardware specific way
2693  * @q_vector: structure containing interrupt and ring information
2694  *
2695  * This function is made to be called by ethtool and by the driver
2696  * when it needs to update EITR registers at runtime.  Hardware
2697  * specific quirks/differences are taken care of here.
2698  */
2699 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2700 {
2701 	struct ixgbe_adapter *adapter = q_vector->adapter;
2702 	struct ixgbe_hw *hw = &adapter->hw;
2703 	int v_idx = q_vector->v_idx;
2704 	u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2705 
2706 	switch (adapter->hw.mac.type) {
2707 	case ixgbe_mac_82598EB:
2708 		/* must write high and low 16 bits to reset counter */
2709 		itr_reg |= (itr_reg << 16);
2710 		break;
2711 	case ixgbe_mac_82599EB:
2712 	case ixgbe_mac_X540:
2713 	case ixgbe_mac_X550:
2714 	case ixgbe_mac_X550EM_x:
2715 	case ixgbe_mac_x550em_a:
2716 		/*
2717 		 * set the WDIS bit to not clear the timer bits and cause an
2718 		 * immediate assertion of the interrupt
2719 		 */
2720 		itr_reg |= IXGBE_EITR_CNT_WDIS;
2721 		break;
2722 	default:
2723 		break;
2724 	}
2725 	IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2726 }
2727 
2728 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2729 {
2730 	u32 new_itr;
2731 
2732 	ixgbe_update_itr(q_vector, &q_vector->tx);
2733 	ixgbe_update_itr(q_vector, &q_vector->rx);
2734 
2735 	/* use the smallest value of new ITR delay calculations */
2736 	new_itr = min(q_vector->rx.itr, q_vector->tx.itr);
2737 
2738 	/* Clear latency flag if set, shift into correct position */
2739 	new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY;
2740 	new_itr <<= 2;
2741 
2742 	if (new_itr != q_vector->itr) {
2743 		/* save the algorithm value here */
2744 		q_vector->itr = new_itr;
2745 
2746 		ixgbe_write_eitr(q_vector);
2747 	}
2748 }
2749 
2750 /**
2751  * ixgbe_check_overtemp_subtask - check for over temperature
2752  * @adapter: pointer to adapter
2753  **/
2754 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2755 {
2756 	struct ixgbe_hw *hw = &adapter->hw;
2757 	u32 eicr = adapter->interrupt_event;
2758 	s32 rc;
2759 
2760 	if (test_bit(__IXGBE_DOWN, &adapter->state))
2761 		return;
2762 
2763 	if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2764 		return;
2765 
2766 	adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2767 
2768 	switch (hw->device_id) {
2769 	case IXGBE_DEV_ID_82599_T3_LOM:
2770 		/*
2771 		 * Since the warning interrupt is for both ports
2772 		 * we don't have to check if:
2773 		 *  - This interrupt wasn't for our port.
2774 		 *  - We may have missed the interrupt so always have to
2775 		 *    check if we  got a LSC
2776 		 */
2777 		if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
2778 		    !(eicr & IXGBE_EICR_LSC))
2779 			return;
2780 
2781 		if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2782 			u32 speed;
2783 			bool link_up = false;
2784 
2785 			hw->mac.ops.check_link(hw, &speed, &link_up, false);
2786 
2787 			if (link_up)
2788 				return;
2789 		}
2790 
2791 		/* Check if this is not due to overtemp */
2792 		if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2793 			return;
2794 
2795 		break;
2796 	case IXGBE_DEV_ID_X550EM_A_1G_T:
2797 	case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2798 		rc = hw->phy.ops.check_overtemp(hw);
2799 		if (rc != IXGBE_ERR_OVERTEMP)
2800 			return;
2801 		break;
2802 	default:
2803 		if (adapter->hw.mac.type >= ixgbe_mac_X540)
2804 			return;
2805 		if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
2806 			return;
2807 		break;
2808 	}
2809 	e_crit(drv, "%s\n", ixgbe_overheat_msg);
2810 
2811 	adapter->interrupt_event = 0;
2812 }
2813 
2814 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2815 {
2816 	struct ixgbe_hw *hw = &adapter->hw;
2817 
2818 	if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2819 	    (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2820 		e_crit(probe, "Fan has stopped, replace the adapter\n");
2821 		/* write to clear the interrupt */
2822 		IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2823 	}
2824 }
2825 
2826 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2827 {
2828 	struct ixgbe_hw *hw = &adapter->hw;
2829 
2830 	if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2831 		return;
2832 
2833 	switch (adapter->hw.mac.type) {
2834 	case ixgbe_mac_82599EB:
2835 		/*
2836 		 * Need to check link state so complete overtemp check
2837 		 * on service task
2838 		 */
2839 		if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2840 		     (eicr & IXGBE_EICR_LSC)) &&
2841 		    (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2842 			adapter->interrupt_event = eicr;
2843 			adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2844 			ixgbe_service_event_schedule(adapter);
2845 			return;
2846 		}
2847 		return;
2848 	case ixgbe_mac_x550em_a:
2849 		if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) {
2850 			adapter->interrupt_event = eicr;
2851 			adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2852 			ixgbe_service_event_schedule(adapter);
2853 			IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
2854 					IXGBE_EICR_GPI_SDP0_X550EM_a);
2855 			IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR,
2856 					IXGBE_EICR_GPI_SDP0_X550EM_a);
2857 		}
2858 		return;
2859 	case ixgbe_mac_X550:
2860 	case ixgbe_mac_X540:
2861 		if (!(eicr & IXGBE_EICR_TS))
2862 			return;
2863 		break;
2864 	default:
2865 		return;
2866 	}
2867 
2868 	e_crit(drv, "%s\n", ixgbe_overheat_msg);
2869 }
2870 
2871 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2872 {
2873 	switch (hw->mac.type) {
2874 	case ixgbe_mac_82598EB:
2875 		if (hw->phy.type == ixgbe_phy_nl)
2876 			return true;
2877 		return false;
2878 	case ixgbe_mac_82599EB:
2879 	case ixgbe_mac_X550EM_x:
2880 	case ixgbe_mac_x550em_a:
2881 		switch (hw->mac.ops.get_media_type(hw)) {
2882 		case ixgbe_media_type_fiber:
2883 		case ixgbe_media_type_fiber_qsfp:
2884 			return true;
2885 		default:
2886 			return false;
2887 		}
2888 	default:
2889 		return false;
2890 	}
2891 }
2892 
2893 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2894 {
2895 	struct ixgbe_hw *hw = &adapter->hw;
2896 	u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
2897 
2898 	if (!ixgbe_is_sfp(hw))
2899 		return;
2900 
2901 	/* Later MAC's use different SDP */
2902 	if (hw->mac.type >= ixgbe_mac_X540)
2903 		eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2904 
2905 	if (eicr & eicr_mask) {
2906 		/* Clear the interrupt */
2907 		IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
2908 		if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2909 			adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2910 			adapter->sfp_poll_time = 0;
2911 			ixgbe_service_event_schedule(adapter);
2912 		}
2913 	}
2914 
2915 	if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2916 	    (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2917 		/* Clear the interrupt */
2918 		IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2919 		if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2920 			adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2921 			ixgbe_service_event_schedule(adapter);
2922 		}
2923 	}
2924 }
2925 
2926 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2927 {
2928 	struct ixgbe_hw *hw = &adapter->hw;
2929 
2930 	adapter->lsc_int++;
2931 	adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2932 	adapter->link_check_timeout = jiffies;
2933 	if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2934 		IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2935 		IXGBE_WRITE_FLUSH(hw);
2936 		ixgbe_service_event_schedule(adapter);
2937 	}
2938 }
2939 
2940 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2941 					   u64 qmask)
2942 {
2943 	u32 mask;
2944 	struct ixgbe_hw *hw = &adapter->hw;
2945 
2946 	switch (hw->mac.type) {
2947 	case ixgbe_mac_82598EB:
2948 		mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2949 		IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2950 		break;
2951 	case ixgbe_mac_82599EB:
2952 	case ixgbe_mac_X540:
2953 	case ixgbe_mac_X550:
2954 	case ixgbe_mac_X550EM_x:
2955 	case ixgbe_mac_x550em_a:
2956 		mask = (qmask & 0xFFFFFFFF);
2957 		if (mask)
2958 			IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2959 		mask = (qmask >> 32);
2960 		if (mask)
2961 			IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2962 		break;
2963 	default:
2964 		break;
2965 	}
2966 	/* skip the flush */
2967 }
2968 
2969 /**
2970  * ixgbe_irq_enable - Enable default interrupt generation settings
2971  * @adapter: board private structure
2972  * @queues: enable irqs for queues
2973  * @flush: flush register write
2974  **/
2975 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2976 				    bool flush)
2977 {
2978 	struct ixgbe_hw *hw = &adapter->hw;
2979 	u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2980 
2981 	/* don't reenable LSC while waiting for link */
2982 	if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2983 		mask &= ~IXGBE_EIMS_LSC;
2984 
2985 	if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2986 		switch (adapter->hw.mac.type) {
2987 		case ixgbe_mac_82599EB:
2988 			mask |= IXGBE_EIMS_GPI_SDP0(hw);
2989 			break;
2990 		case ixgbe_mac_X540:
2991 		case ixgbe_mac_X550:
2992 		case ixgbe_mac_X550EM_x:
2993 		case ixgbe_mac_x550em_a:
2994 			mask |= IXGBE_EIMS_TS;
2995 			break;
2996 		default:
2997 			break;
2998 		}
2999 	if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3000 		mask |= IXGBE_EIMS_GPI_SDP1(hw);
3001 	switch (adapter->hw.mac.type) {
3002 	case ixgbe_mac_82599EB:
3003 		mask |= IXGBE_EIMS_GPI_SDP1(hw);
3004 		mask |= IXGBE_EIMS_GPI_SDP2(hw);
3005 		fallthrough;
3006 	case ixgbe_mac_X540:
3007 	case ixgbe_mac_X550:
3008 	case ixgbe_mac_X550EM_x:
3009 	case ixgbe_mac_x550em_a:
3010 		if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP ||
3011 		    adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP ||
3012 		    adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N)
3013 			mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
3014 		if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
3015 			mask |= IXGBE_EICR_GPI_SDP0_X540;
3016 		mask |= IXGBE_EIMS_ECC;
3017 		mask |= IXGBE_EIMS_MAILBOX;
3018 		break;
3019 	default:
3020 		break;
3021 	}
3022 
3023 	if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
3024 	    !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
3025 		mask |= IXGBE_EIMS_FLOW_DIR;
3026 
3027 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
3028 	if (queues)
3029 		ixgbe_irq_enable_queues(adapter, ~0);
3030 	if (flush)
3031 		IXGBE_WRITE_FLUSH(&adapter->hw);
3032 }
3033 
3034 static irqreturn_t ixgbe_msix_other(int irq, void *data)
3035 {
3036 	struct ixgbe_adapter *adapter = data;
3037 	struct ixgbe_hw *hw = &adapter->hw;
3038 	u32 eicr;
3039 
3040 	/*
3041 	 * Workaround for Silicon errata.  Use clear-by-write instead
3042 	 * of clear-by-read.  Reading with EICS will return the
3043 	 * interrupt causes without clearing, which later be done
3044 	 * with the write to EICR.
3045 	 */
3046 	eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
3047 
3048 	/* The lower 16bits of the EICR register are for the queue interrupts
3049 	 * which should be masked here in order to not accidentally clear them if
3050 	 * the bits are high when ixgbe_msix_other is called. There is a race
3051 	 * condition otherwise which results in possible performance loss
3052 	 * especially if the ixgbe_msix_other interrupt is triggering
3053 	 * consistently (as it would when PPS is turned on for the X540 device)
3054 	 */
3055 	eicr &= 0xFFFF0000;
3056 
3057 	IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
3058 
3059 	if (eicr & IXGBE_EICR_LSC)
3060 		ixgbe_check_lsc(adapter);
3061 
3062 	if (eicr & IXGBE_EICR_MAILBOX)
3063 		ixgbe_msg_task(adapter);
3064 
3065 	switch (hw->mac.type) {
3066 	case ixgbe_mac_82599EB:
3067 	case ixgbe_mac_X540:
3068 	case ixgbe_mac_X550:
3069 	case ixgbe_mac_X550EM_x:
3070 	case ixgbe_mac_x550em_a:
3071 		if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
3072 		    (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
3073 			adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
3074 			ixgbe_service_event_schedule(adapter);
3075 			IXGBE_WRITE_REG(hw, IXGBE_EICR,
3076 					IXGBE_EICR_GPI_SDP0_X540);
3077 		}
3078 		if (eicr & IXGBE_EICR_ECC) {
3079 			e_info(link, "Received ECC Err, initiating reset\n");
3080 			set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
3081 			ixgbe_service_event_schedule(adapter);
3082 			IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
3083 		}
3084 		/* Handle Flow Director Full threshold interrupt */
3085 		if (eicr & IXGBE_EICR_FLOW_DIR) {
3086 			int reinit_count = 0;
3087 			int i;
3088 			for (i = 0; i < adapter->num_tx_queues; i++) {
3089 				struct ixgbe_ring *ring = adapter->tx_ring[i];
3090 				if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
3091 						       &ring->state))
3092 					reinit_count++;
3093 			}
3094 			if (reinit_count) {
3095 				/* no more flow director interrupts until after init */
3096 				IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
3097 				adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
3098 				ixgbe_service_event_schedule(adapter);
3099 			}
3100 		}
3101 		ixgbe_check_sfp_event(adapter, eicr);
3102 		ixgbe_check_overtemp_event(adapter, eicr);
3103 		break;
3104 	default:
3105 		break;
3106 	}
3107 
3108 	ixgbe_check_fan_failure(adapter, eicr);
3109 
3110 	if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
3111 		ixgbe_ptp_check_pps_event(adapter);
3112 
3113 	/* re-enable the original interrupt state, no lsc, no queues */
3114 	if (!test_bit(__IXGBE_DOWN, &adapter->state))
3115 		ixgbe_irq_enable(adapter, false, false);
3116 
3117 	return IRQ_HANDLED;
3118 }
3119 
3120 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
3121 {
3122 	struct ixgbe_q_vector *q_vector = data;
3123 
3124 	/* EIAM disabled interrupts (on this vector) for us */
3125 
3126 	if (q_vector->rx.ring || q_vector->tx.ring)
3127 		napi_schedule_irqoff(&q_vector->napi);
3128 
3129 	return IRQ_HANDLED;
3130 }
3131 
3132 /**
3133  * ixgbe_poll - NAPI Rx polling callback
3134  * @napi: structure for representing this polling device
3135  * @budget: how many packets driver is allowed to clean
3136  *
3137  * This function is used for legacy and MSI, NAPI mode
3138  **/
3139 int ixgbe_poll(struct napi_struct *napi, int budget)
3140 {
3141 	struct ixgbe_q_vector *q_vector =
3142 				container_of(napi, struct ixgbe_q_vector, napi);
3143 	struct ixgbe_adapter *adapter = q_vector->adapter;
3144 	struct ixgbe_ring *ring;
3145 	int per_ring_budget, work_done = 0;
3146 	bool clean_complete = true;
3147 
3148 #ifdef CONFIG_IXGBE_DCA
3149 	if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3150 		ixgbe_update_dca(q_vector);
3151 #endif
3152 
3153 	ixgbe_for_each_ring(ring, q_vector->tx) {
3154 		bool wd = ring->xsk_pool ?
3155 			  ixgbe_clean_xdp_tx_irq(q_vector, ring, budget) :
3156 			  ixgbe_clean_tx_irq(q_vector, ring, budget);
3157 
3158 		if (!wd)
3159 			clean_complete = false;
3160 	}
3161 
3162 	/* Exit if we are called by netpoll */
3163 	if (budget <= 0)
3164 		return budget;
3165 
3166 	/* attempt to distribute budget to each queue fairly, but don't allow
3167 	 * the budget to go below 1 because we'll exit polling */
3168 	if (q_vector->rx.count > 1)
3169 		per_ring_budget = max(budget/q_vector->rx.count, 1);
3170 	else
3171 		per_ring_budget = budget;
3172 
3173 	ixgbe_for_each_ring(ring, q_vector->rx) {
3174 		int cleaned = ring->xsk_pool ?
3175 			      ixgbe_clean_rx_irq_zc(q_vector, ring,
3176 						    per_ring_budget) :
3177 			      ixgbe_clean_rx_irq(q_vector, ring,
3178 						 per_ring_budget);
3179 
3180 		work_done += cleaned;
3181 		if (cleaned >= per_ring_budget)
3182 			clean_complete = false;
3183 	}
3184 
3185 	/* If all work not completed, return budget and keep polling */
3186 	if (!clean_complete)
3187 		return budget;
3188 
3189 	/* all work done, exit the polling mode */
3190 	if (likely(napi_complete_done(napi, work_done))) {
3191 		if (adapter->rx_itr_setting & 1)
3192 			ixgbe_set_itr(q_vector);
3193 		if (!test_bit(__IXGBE_DOWN, &adapter->state))
3194 			ixgbe_irq_enable_queues(adapter,
3195 						BIT_ULL(q_vector->v_idx));
3196 	}
3197 
3198 	return min(work_done, budget - 1);
3199 }
3200 
3201 /**
3202  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
3203  * @adapter: board private structure
3204  *
3205  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
3206  * interrupts from the kernel.
3207  **/
3208 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
3209 {
3210 	struct net_device *netdev = adapter->netdev;
3211 	unsigned int ri = 0, ti = 0;
3212 	int vector, err;
3213 
3214 	for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3215 		struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3216 		struct msix_entry *entry = &adapter->msix_entries[vector];
3217 
3218 		if (q_vector->tx.ring && q_vector->rx.ring) {
3219 			snprintf(q_vector->name, sizeof(q_vector->name),
3220 				 "%s-TxRx-%u", netdev->name, ri++);
3221 			ti++;
3222 		} else if (q_vector->rx.ring) {
3223 			snprintf(q_vector->name, sizeof(q_vector->name),
3224 				 "%s-rx-%u", netdev->name, ri++);
3225 		} else if (q_vector->tx.ring) {
3226 			snprintf(q_vector->name, sizeof(q_vector->name),
3227 				 "%s-tx-%u", netdev->name, ti++);
3228 		} else {
3229 			/* skip this unused q_vector */
3230 			continue;
3231 		}
3232 		err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
3233 				  q_vector->name, q_vector);
3234 		if (err) {
3235 			e_err(probe, "request_irq failed for MSIX interrupt "
3236 			      "Error: %d\n", err);
3237 			goto free_queue_irqs;
3238 		}
3239 		/* If Flow Director is enabled, set interrupt affinity */
3240 		if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3241 			/* assign the mask for this irq */
3242 			irq_set_affinity_hint(entry->vector,
3243 					      &q_vector->affinity_mask);
3244 		}
3245 	}
3246 
3247 	err = request_irq(adapter->msix_entries[vector].vector,
3248 			  ixgbe_msix_other, 0, netdev->name, adapter);
3249 	if (err) {
3250 		e_err(probe, "request_irq for msix_other failed: %d\n", err);
3251 		goto free_queue_irqs;
3252 	}
3253 
3254 	return 0;
3255 
3256 free_queue_irqs:
3257 	while (vector) {
3258 		vector--;
3259 		irq_set_affinity_hint(adapter->msix_entries[vector].vector,
3260 				      NULL);
3261 		free_irq(adapter->msix_entries[vector].vector,
3262 			 adapter->q_vector[vector]);
3263 	}
3264 	adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3265 	pci_disable_msix(adapter->pdev);
3266 	kfree(adapter->msix_entries);
3267 	adapter->msix_entries = NULL;
3268 	return err;
3269 }
3270 
3271 /**
3272  * ixgbe_intr - legacy mode Interrupt Handler
3273  * @irq: interrupt number
3274  * @data: pointer to a network interface device structure
3275  **/
3276 static irqreturn_t ixgbe_intr(int irq, void *data)
3277 {
3278 	struct ixgbe_adapter *adapter = data;
3279 	struct ixgbe_hw *hw = &adapter->hw;
3280 	struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
3281 	u32 eicr;
3282 
3283 	/*
3284 	 * Workaround for silicon errata #26 on 82598.  Mask the interrupt
3285 	 * before the read of EICR.
3286 	 */
3287 	IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
3288 
3289 	/* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
3290 	 * therefore no explicit interrupt disable is necessary */
3291 	eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3292 	if (!eicr) {
3293 		/*
3294 		 * shared interrupt alert!
3295 		 * make sure interrupts are enabled because the read will
3296 		 * have disabled interrupts due to EIAM
3297 		 * finish the workaround of silicon errata on 82598.  Unmask
3298 		 * the interrupt that we masked before the EICR read.
3299 		 */
3300 		if (!test_bit(__IXGBE_DOWN, &adapter->state))
3301 			ixgbe_irq_enable(adapter, true, true);
3302 		return IRQ_NONE;	/* Not our interrupt */
3303 	}
3304 
3305 	if (eicr & IXGBE_EICR_LSC)
3306 		ixgbe_check_lsc(adapter);
3307 
3308 	switch (hw->mac.type) {
3309 	case ixgbe_mac_82599EB:
3310 		ixgbe_check_sfp_event(adapter, eicr);
3311 		fallthrough;
3312 	case ixgbe_mac_X540:
3313 	case ixgbe_mac_X550:
3314 	case ixgbe_mac_X550EM_x:
3315 	case ixgbe_mac_x550em_a:
3316 		if (eicr & IXGBE_EICR_ECC) {
3317 			e_info(link, "Received ECC Err, initiating reset\n");
3318 			set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
3319 			ixgbe_service_event_schedule(adapter);
3320 			IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
3321 		}
3322 		ixgbe_check_overtemp_event(adapter, eicr);
3323 		break;
3324 	default:
3325 		break;
3326 	}
3327 
3328 	ixgbe_check_fan_failure(adapter, eicr);
3329 	if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
3330 		ixgbe_ptp_check_pps_event(adapter);
3331 
3332 	/* would disable interrupts here but EIAM disabled it */
3333 	napi_schedule_irqoff(&q_vector->napi);
3334 
3335 	/*
3336 	 * re-enable link(maybe) and non-queue interrupts, no flush.
3337 	 * ixgbe_poll will re-enable the queue interrupts
3338 	 */
3339 	if (!test_bit(__IXGBE_DOWN, &adapter->state))
3340 		ixgbe_irq_enable(adapter, false, false);
3341 
3342 	return IRQ_HANDLED;
3343 }
3344 
3345 /**
3346  * ixgbe_request_irq - initialize interrupts
3347  * @adapter: board private structure
3348  *
3349  * Attempts to configure interrupts using the best available
3350  * capabilities of the hardware and kernel.
3351  **/
3352 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
3353 {
3354 	struct net_device *netdev = adapter->netdev;
3355 	int err;
3356 
3357 	if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3358 		err = ixgbe_request_msix_irqs(adapter);
3359 	else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
3360 		err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
3361 				  netdev->name, adapter);
3362 	else
3363 		err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
3364 				  netdev->name, adapter);
3365 
3366 	if (err)
3367 		e_err(probe, "request_irq failed, Error %d\n", err);
3368 
3369 	return err;
3370 }
3371 
3372 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
3373 {
3374 	int vector;
3375 
3376 	if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3377 		free_irq(adapter->pdev->irq, adapter);
3378 		return;
3379 	}
3380 
3381 	if (!adapter->msix_entries)
3382 		return;
3383 
3384 	for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3385 		struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3386 		struct msix_entry *entry = &adapter->msix_entries[vector];
3387 
3388 		/* free only the irqs that were actually requested */
3389 		if (!q_vector->rx.ring && !q_vector->tx.ring)
3390 			continue;
3391 
3392 		/* clear the affinity_mask in the IRQ descriptor */
3393 		irq_set_affinity_hint(entry->vector, NULL);
3394 
3395 		free_irq(entry->vector, q_vector);
3396 	}
3397 
3398 	free_irq(adapter->msix_entries[vector].vector, adapter);
3399 }
3400 
3401 /**
3402  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3403  * @adapter: board private structure
3404  **/
3405 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3406 {
3407 	switch (adapter->hw.mac.type) {
3408 	case ixgbe_mac_82598EB:
3409 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
3410 		break;
3411 	case ixgbe_mac_82599EB:
3412 	case ixgbe_mac_X540:
3413 	case ixgbe_mac_X550:
3414 	case ixgbe_mac_X550EM_x:
3415 	case ixgbe_mac_x550em_a:
3416 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3417 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
3418 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
3419 		break;
3420 	default:
3421 		break;
3422 	}
3423 	IXGBE_WRITE_FLUSH(&adapter->hw);
3424 	if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3425 		int vector;
3426 
3427 		for (vector = 0; vector < adapter->num_q_vectors; vector++)
3428 			synchronize_irq(adapter->msix_entries[vector].vector);
3429 
3430 		synchronize_irq(adapter->msix_entries[vector++].vector);
3431 	} else {
3432 		synchronize_irq(adapter->pdev->irq);
3433 	}
3434 }
3435 
3436 /**
3437  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3438  * @adapter: board private structure
3439  *
3440  **/
3441 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3442 {
3443 	struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
3444 
3445 	ixgbe_write_eitr(q_vector);
3446 
3447 	ixgbe_set_ivar(adapter, 0, 0, 0);
3448 	ixgbe_set_ivar(adapter, 1, 0, 0);
3449 
3450 	e_info(hw, "Legacy interrupt IVAR setup done\n");
3451 }
3452 
3453 /**
3454  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3455  * @adapter: board private structure
3456  * @ring: structure containing ring specific data
3457  *
3458  * Configure the Tx descriptor ring after a reset.
3459  **/
3460 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3461 			     struct ixgbe_ring *ring)
3462 {
3463 	struct ixgbe_hw *hw = &adapter->hw;
3464 	u64 tdba = ring->dma;
3465 	int wait_loop = 10;
3466 	u32 txdctl = IXGBE_TXDCTL_ENABLE;
3467 	u8 reg_idx = ring->reg_idx;
3468 
3469 	ring->xsk_pool = NULL;
3470 	if (ring_is_xdp(ring))
3471 		ring->xsk_pool = ixgbe_xsk_pool(adapter, ring);
3472 
3473 	/* disable queue to avoid issues while updating state */
3474 	IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
3475 	IXGBE_WRITE_FLUSH(hw);
3476 
3477 	IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
3478 			(tdba & DMA_BIT_MASK(32)));
3479 	IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3480 	IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3481 			ring->count * sizeof(union ixgbe_adv_tx_desc));
3482 	IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3483 	IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
3484 	ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
3485 
3486 	/*
3487 	 * set WTHRESH to encourage burst writeback, it should not be set
3488 	 * higher than 1 when:
3489 	 * - ITR is 0 as it could cause false TX hangs
3490 	 * - ITR is set to > 100k int/sec and BQL is enabled
3491 	 *
3492 	 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3493 	 * to or less than the number of on chip descriptors, which is
3494 	 * currently 40.
3495 	 */
3496 	if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3497 		txdctl |= 1u << 16;	/* WTHRESH = 1 */
3498 	else
3499 		txdctl |= 8u << 16;	/* WTHRESH = 8 */
3500 
3501 	/*
3502 	 * Setting PTHRESH to 32 both improves performance
3503 	 * and avoids a TX hang with DFP enabled
3504 	 */
3505 	txdctl |= (1u << 8) |	/* HTHRESH = 1 */
3506 		   32;		/* PTHRESH = 32 */
3507 
3508 	/* reinitialize flowdirector state */
3509 	if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3510 		ring->atr_sample_rate = adapter->atr_sample_rate;
3511 		ring->atr_count = 0;
3512 		set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3513 	} else {
3514 		ring->atr_sample_rate = 0;
3515 	}
3516 
3517 	/* initialize XPS */
3518 	if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3519 		struct ixgbe_q_vector *q_vector = ring->q_vector;
3520 
3521 		if (q_vector)
3522 			netif_set_xps_queue(ring->netdev,
3523 					    &q_vector->affinity_mask,
3524 					    ring->queue_index);
3525 	}
3526 
3527 	clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3528 
3529 	/* reinitialize tx_buffer_info */
3530 	memset(ring->tx_buffer_info, 0,
3531 	       sizeof(struct ixgbe_tx_buffer) * ring->count);
3532 
3533 	/* enable queue */
3534 	IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3535 
3536 	/* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3537 	if (hw->mac.type == ixgbe_mac_82598EB &&
3538 	    !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3539 		return;
3540 
3541 	/* poll to verify queue is enabled */
3542 	do {
3543 		usleep_range(1000, 2000);
3544 		txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3545 	} while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3546 	if (!wait_loop)
3547 		hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx);
3548 }
3549 
3550 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3551 {
3552 	struct ixgbe_hw *hw = &adapter->hw;
3553 	u32 rttdcs, mtqc;
3554 	u8 tcs = adapter->hw_tcs;
3555 
3556 	if (hw->mac.type == ixgbe_mac_82598EB)
3557 		return;
3558 
3559 	/* disable the arbiter while setting MTQC */
3560 	rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3561 	rttdcs |= IXGBE_RTTDCS_ARBDIS;
3562 	IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3563 
3564 	/* set transmit pool layout */
3565 	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3566 		mtqc = IXGBE_MTQC_VT_ENA;
3567 		if (tcs > 4)
3568 			mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3569 		else if (tcs > 1)
3570 			mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3571 		else if (adapter->ring_feature[RING_F_VMDQ].mask ==
3572 			 IXGBE_82599_VMDQ_4Q_MASK)
3573 			mtqc |= IXGBE_MTQC_32VF;
3574 		else
3575 			mtqc |= IXGBE_MTQC_64VF;
3576 	} else {
3577 		if (tcs > 4) {
3578 			mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3579 		} else if (tcs > 1) {
3580 			mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3581 		} else {
3582 			u8 max_txq = adapter->num_tx_queues +
3583 				adapter->num_xdp_queues;
3584 			if (max_txq > 63)
3585 				mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3586 			else
3587 				mtqc = IXGBE_MTQC_64Q_1PB;
3588 		}
3589 	}
3590 
3591 	IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3592 
3593 	/* Enable Security TX Buffer IFG for multiple pb */
3594 	if (tcs) {
3595 		u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3596 		sectx |= IXGBE_SECTX_DCB;
3597 		IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3598 	}
3599 
3600 	/* re-enable the arbiter */
3601 	rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3602 	IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3603 }
3604 
3605 /**
3606  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3607  * @adapter: board private structure
3608  *
3609  * Configure the Tx unit of the MAC after a reset.
3610  **/
3611 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3612 {
3613 	struct ixgbe_hw *hw = &adapter->hw;
3614 	u32 dmatxctl;
3615 	u32 i;
3616 
3617 	ixgbe_setup_mtqc(adapter);
3618 
3619 	if (hw->mac.type != ixgbe_mac_82598EB) {
3620 		/* DMATXCTL.EN must be before Tx queues are enabled */
3621 		dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3622 		dmatxctl |= IXGBE_DMATXCTL_TE;
3623 		IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3624 	}
3625 
3626 	/* Setup the HW Tx Head and Tail descriptor pointers */
3627 	for (i = 0; i < adapter->num_tx_queues; i++)
3628 		ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3629 	for (i = 0; i < adapter->num_xdp_queues; i++)
3630 		ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]);
3631 }
3632 
3633 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3634 				 struct ixgbe_ring *ring)
3635 {
3636 	struct ixgbe_hw *hw = &adapter->hw;
3637 	u8 reg_idx = ring->reg_idx;
3638 	u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3639 
3640 	srrctl |= IXGBE_SRRCTL_DROP_EN;
3641 
3642 	IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3643 }
3644 
3645 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3646 				  struct ixgbe_ring *ring)
3647 {
3648 	struct ixgbe_hw *hw = &adapter->hw;
3649 	u8 reg_idx = ring->reg_idx;
3650 	u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3651 
3652 	srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3653 
3654 	IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3655 }
3656 
3657 #ifdef CONFIG_IXGBE_DCB
3658 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3659 #else
3660 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3661 #endif
3662 {
3663 	int i;
3664 	bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3665 
3666 	if (adapter->ixgbe_ieee_pfc)
3667 		pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3668 
3669 	/*
3670 	 * We should set the drop enable bit if:
3671 	 *  SR-IOV is enabled
3672 	 *   or
3673 	 *  Number of Rx queues > 1 and flow control is disabled
3674 	 *
3675 	 *  This allows us to avoid head of line blocking for security
3676 	 *  and performance reasons.
3677 	 */
3678 	if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3679 	    !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3680 		for (i = 0; i < adapter->num_rx_queues; i++)
3681 			ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3682 	} else {
3683 		for (i = 0; i < adapter->num_rx_queues; i++)
3684 			ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3685 	}
3686 }
3687 
3688 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3689 
3690 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3691 				   struct ixgbe_ring *rx_ring)
3692 {
3693 	struct ixgbe_hw *hw = &adapter->hw;
3694 	u32 srrctl;
3695 	u8 reg_idx = rx_ring->reg_idx;
3696 
3697 	if (hw->mac.type == ixgbe_mac_82598EB) {
3698 		u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3699 
3700 		/*
3701 		 * if VMDq is not active we must program one srrctl register
3702 		 * per RSS queue since we have enabled RDRXCTL.MVMEN
3703 		 */
3704 		reg_idx &= mask;
3705 	}
3706 
3707 	/* configure header buffer length, needed for RSC */
3708 	srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3709 
3710 	/* configure the packet buffer length */
3711 	if (rx_ring->xsk_pool) {
3712 		u32 xsk_buf_len = xsk_pool_get_rx_frame_size(rx_ring->xsk_pool);
3713 
3714 		/* If the MAC support setting RXDCTL.RLPML, the
3715 		 * SRRCTL[n].BSIZEPKT is set to PAGE_SIZE and
3716 		 * RXDCTL.RLPML is set to the actual UMEM buffer
3717 		 * size. If not, then we are stuck with a 1k buffer
3718 		 * size resolution. In this case frames larger than
3719 		 * the UMEM buffer size viewed in a 1k resolution will
3720 		 * be dropped.
3721 		 */
3722 		if (hw->mac.type != ixgbe_mac_82599EB)
3723 			srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3724 		else
3725 			srrctl |= xsk_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3726 	} else if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) {
3727 		srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3728 	} else {
3729 		srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3730 	}
3731 
3732 	/* configure descriptor type */
3733 	srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3734 
3735 	IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3736 }
3737 
3738 /**
3739  * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries
3740  * @adapter: device handle
3741  *
3742  *  - 82598/82599/X540:     128
3743  *  - X550(non-SRIOV mode): 512
3744  *  - X550(SRIOV mode):     64
3745  */
3746 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
3747 {
3748 	if (adapter->hw.mac.type < ixgbe_mac_X550)
3749 		return 128;
3750 	else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3751 		return 64;
3752 	else
3753 		return 512;
3754 }
3755 
3756 /**
3757  * ixgbe_store_key - Write the RSS key to HW
3758  * @adapter: device handle
3759  *
3760  * Write the RSS key stored in adapter.rss_key to HW.
3761  */
3762 void ixgbe_store_key(struct ixgbe_adapter *adapter)
3763 {
3764 	struct ixgbe_hw *hw = &adapter->hw;
3765 	int i;
3766 
3767 	for (i = 0; i < 10; i++)
3768 		IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3769 }
3770 
3771 /**
3772  * ixgbe_init_rss_key - Initialize adapter RSS key
3773  * @adapter: device handle
3774  *
3775  * Allocates and initializes the RSS key if it is not allocated.
3776  **/
3777 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter)
3778 {
3779 	u32 *rss_key;
3780 
3781 	if (!adapter->rss_key) {
3782 		rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL);
3783 		if (unlikely(!rss_key))
3784 			return -ENOMEM;
3785 
3786 		netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE);
3787 		adapter->rss_key = rss_key;
3788 	}
3789 
3790 	return 0;
3791 }
3792 
3793 /**
3794  * ixgbe_store_reta - Write the RETA table to HW
3795  * @adapter: device handle
3796  *
3797  * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3798  */
3799 void ixgbe_store_reta(struct ixgbe_adapter *adapter)
3800 {
3801 	u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3802 	struct ixgbe_hw *hw = &adapter->hw;
3803 	u32 reta = 0;
3804 	u32 indices_multi;
3805 	u8 *indir_tbl = adapter->rss_indir_tbl;
3806 
3807 	/* Fill out the redirection table as follows:
3808 	 *  - 82598:      8 bit wide entries containing pair of 4 bit RSS
3809 	 *    indices.
3810 	 *  - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3811 	 *  - X550:       8 bit wide entries containing 6 bit RSS index
3812 	 */
3813 	if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3814 		indices_multi = 0x11;
3815 	else
3816 		indices_multi = 0x1;
3817 
3818 	/* Write redirection table to HW */
3819 	for (i = 0; i < reta_entries; i++) {
3820 		reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
3821 		if ((i & 3) == 3) {
3822 			if (i < 128)
3823 				IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3824 			else
3825 				IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3826 						reta);
3827 			reta = 0;
3828 		}
3829 	}
3830 }
3831 
3832 /**
3833  * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode)
3834  * @adapter: device handle
3835  *
3836  * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3837  */
3838 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
3839 {
3840 	u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3841 	struct ixgbe_hw *hw = &adapter->hw;
3842 	u32 vfreta = 0;
3843 
3844 	/* Write redirection table to HW */
3845 	for (i = 0; i < reta_entries; i++) {
3846 		u16 pool = adapter->num_rx_pools;
3847 
3848 		vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3849 		if ((i & 3) != 3)
3850 			continue;
3851 
3852 		while (pool--)
3853 			IXGBE_WRITE_REG(hw,
3854 					IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)),
3855 					vfreta);
3856 		vfreta = 0;
3857 	}
3858 }
3859 
3860 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3861 {
3862 	u32 i, j;
3863 	u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3864 	u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3865 
3866 	/* Program table for at least 4 queues w/ SR-IOV so that VFs can
3867 	 * make full use of any rings they may have.  We will use the
3868 	 * PSRTYPE register to control how many rings we use within the PF.
3869 	 */
3870 	if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4))
3871 		rss_i = 4;
3872 
3873 	/* Fill out hash function seeds */
3874 	ixgbe_store_key(adapter);
3875 
3876 	/* Fill out redirection table */
3877 	memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3878 
3879 	for (i = 0, j = 0; i < reta_entries; i++, j++) {
3880 		if (j == rss_i)
3881 			j = 0;
3882 
3883 		adapter->rss_indir_tbl[i] = j;
3884 	}
3885 
3886 	ixgbe_store_reta(adapter);
3887 }
3888 
3889 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3890 {
3891 	struct ixgbe_hw *hw = &adapter->hw;
3892 	u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3893 	int i, j;
3894 
3895 	/* Fill out hash function seeds */
3896 	for (i = 0; i < 10; i++) {
3897 		u16 pool = adapter->num_rx_pools;
3898 
3899 		while (pool--)
3900 			IXGBE_WRITE_REG(hw,
3901 					IXGBE_PFVFRSSRK(i, VMDQ_P(pool)),
3902 					*(adapter->rss_key + i));
3903 	}
3904 
3905 	/* Fill out the redirection table */
3906 	for (i = 0, j = 0; i < 64; i++, j++) {
3907 		if (j == rss_i)
3908 			j = 0;
3909 
3910 		adapter->rss_indir_tbl[i] = j;
3911 	}
3912 
3913 	ixgbe_store_vfreta(adapter);
3914 }
3915 
3916 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3917 {
3918 	struct ixgbe_hw *hw = &adapter->hw;
3919 	u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
3920 	u32 rxcsum;
3921 
3922 	/* Disable indicating checksum in descriptor, enables RSS hash */
3923 	rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3924 	rxcsum |= IXGBE_RXCSUM_PCSD;
3925 	IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3926 
3927 	if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3928 		if (adapter->ring_feature[RING_F_RSS].mask)
3929 			mrqc = IXGBE_MRQC_RSSEN;
3930 	} else {
3931 		u8 tcs = adapter->hw_tcs;
3932 
3933 		if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3934 			if (tcs > 4)
3935 				mrqc = IXGBE_MRQC_VMDQRT8TCEN;	/* 8 TCs */
3936 			else if (tcs > 1)
3937 				mrqc = IXGBE_MRQC_VMDQRT4TCEN;	/* 4 TCs */
3938 			else if (adapter->ring_feature[RING_F_VMDQ].mask ==
3939 				 IXGBE_82599_VMDQ_4Q_MASK)
3940 				mrqc = IXGBE_MRQC_VMDQRSS32EN;
3941 			else
3942 				mrqc = IXGBE_MRQC_VMDQRSS64EN;
3943 
3944 			/* Enable L3/L4 for Tx Switched packets only for X550,
3945 			 * older devices do not support this feature
3946 			 */
3947 			if (hw->mac.type >= ixgbe_mac_X550)
3948 				mrqc |= IXGBE_MRQC_L3L4TXSWEN;
3949 		} else {
3950 			if (tcs > 4)
3951 				mrqc = IXGBE_MRQC_RTRSS8TCEN;
3952 			else if (tcs > 1)
3953 				mrqc = IXGBE_MRQC_RTRSS4TCEN;
3954 			else
3955 				mrqc = IXGBE_MRQC_RSSEN;
3956 		}
3957 	}
3958 
3959 	/* Perform hash on these packet types */
3960 	rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3961 		     IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3962 		     IXGBE_MRQC_RSS_FIELD_IPV6 |
3963 		     IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3964 
3965 	if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3966 		rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3967 	if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3968 		rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3969 
3970 	if ((hw->mac.type >= ixgbe_mac_X550) &&
3971 	    (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3972 		u16 pool = adapter->num_rx_pools;
3973 
3974 		/* Enable VF RSS mode */
3975 		mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3976 		IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3977 
3978 		/* Setup RSS through the VF registers */
3979 		ixgbe_setup_vfreta(adapter);
3980 		vfmrqc = IXGBE_MRQC_RSSEN;
3981 		vfmrqc |= rss_field;
3982 
3983 		while (pool--)
3984 			IXGBE_WRITE_REG(hw,
3985 					IXGBE_PFVFMRQC(VMDQ_P(pool)),
3986 					vfmrqc);
3987 	} else {
3988 		ixgbe_setup_reta(adapter);
3989 		mrqc |= rss_field;
3990 		IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3991 	}
3992 }
3993 
3994 /**
3995  * ixgbe_configure_rscctl - enable RSC for the indicated ring
3996  * @adapter: address of board private structure
3997  * @ring: structure containing ring specific data
3998  **/
3999 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
4000 				   struct ixgbe_ring *ring)
4001 {
4002 	struct ixgbe_hw *hw = &adapter->hw;
4003 	u32 rscctrl;
4004 	u8 reg_idx = ring->reg_idx;
4005 
4006 	if (!ring_is_rsc_enabled(ring))
4007 		return;
4008 
4009 	rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
4010 	rscctrl |= IXGBE_RSCCTL_RSCEN;
4011 	/*
4012 	 * we must limit the number of descriptors so that the
4013 	 * total size of max desc * buf_len is not greater
4014 	 * than 65536
4015 	 */
4016 	rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
4017 	IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
4018 }
4019 
4020 #define IXGBE_MAX_RX_DESC_POLL 10
4021 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
4022 				       struct ixgbe_ring *ring)
4023 {
4024 	struct ixgbe_hw *hw = &adapter->hw;
4025 	int wait_loop = IXGBE_MAX_RX_DESC_POLL;
4026 	u32 rxdctl;
4027 	u8 reg_idx = ring->reg_idx;
4028 
4029 	if (ixgbe_removed(hw->hw_addr))
4030 		return;
4031 	/* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
4032 	if (hw->mac.type == ixgbe_mac_82598EB &&
4033 	    !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
4034 		return;
4035 
4036 	do {
4037 		usleep_range(1000, 2000);
4038 		rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
4039 	} while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4040 
4041 	if (!wait_loop) {
4042 		e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
4043 		      "the polling period\n", reg_idx);
4044 	}
4045 }
4046 
4047 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
4048 			     struct ixgbe_ring *ring)
4049 {
4050 	struct ixgbe_hw *hw = &adapter->hw;
4051 	union ixgbe_adv_rx_desc *rx_desc;
4052 	u64 rdba = ring->dma;
4053 	u32 rxdctl;
4054 	u8 reg_idx = ring->reg_idx;
4055 
4056 	xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq);
4057 	ring->xsk_pool = ixgbe_xsk_pool(adapter, ring);
4058 	if (ring->xsk_pool) {
4059 		WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
4060 						   MEM_TYPE_XSK_BUFF_POOL,
4061 						   NULL));
4062 		xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq);
4063 	} else {
4064 		WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
4065 						   MEM_TYPE_PAGE_SHARED, NULL));
4066 	}
4067 
4068 	/* disable queue to avoid use of these values while updating state */
4069 	rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
4070 	rxdctl &= ~IXGBE_RXDCTL_ENABLE;
4071 
4072 	/* write value back with RXDCTL.ENABLE bit cleared */
4073 	IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
4074 	IXGBE_WRITE_FLUSH(hw);
4075 
4076 	IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
4077 	IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
4078 	IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
4079 			ring->count * sizeof(union ixgbe_adv_rx_desc));
4080 	/* Force flushing of IXGBE_RDLEN to prevent MDD */
4081 	IXGBE_WRITE_FLUSH(hw);
4082 
4083 	IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
4084 	IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
4085 	ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
4086 
4087 	ixgbe_configure_srrctl(adapter, ring);
4088 	ixgbe_configure_rscctl(adapter, ring);
4089 
4090 	if (hw->mac.type == ixgbe_mac_82598EB) {
4091 		/*
4092 		 * enable cache line friendly hardware writes:
4093 		 * PTHRESH=32 descriptors (half the internal cache),
4094 		 * this also removes ugly rx_no_buffer_count increment
4095 		 * HTHRESH=4 descriptors (to minimize latency on fetch)
4096 		 * WTHRESH=8 burst writeback up to two cache lines
4097 		 */
4098 		rxdctl &= ~0x3FFFFF;
4099 		rxdctl |=  0x080420;
4100 #if (PAGE_SIZE < 8192)
4101 	/* RXDCTL.RLPML does not work on 82599 */
4102 	} else if (hw->mac.type != ixgbe_mac_82599EB) {
4103 		rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK |
4104 			    IXGBE_RXDCTL_RLPML_EN);
4105 
4106 		/* Limit the maximum frame size so we don't overrun the skb.
4107 		 * This can happen in SRIOV mode when the MTU of the VF is
4108 		 * higher than the MTU of the PF.
4109 		 */
4110 		if (ring_uses_build_skb(ring) &&
4111 		    !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state))
4112 			rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB |
4113 				  IXGBE_RXDCTL_RLPML_EN;
4114 #endif
4115 	}
4116 
4117 	if (ring->xsk_pool && hw->mac.type != ixgbe_mac_82599EB) {
4118 		u32 xsk_buf_len = xsk_pool_get_rx_frame_size(ring->xsk_pool);
4119 
4120 		rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK |
4121 			    IXGBE_RXDCTL_RLPML_EN);
4122 		rxdctl |= xsk_buf_len | IXGBE_RXDCTL_RLPML_EN;
4123 
4124 		ring->rx_buf_len = xsk_buf_len;
4125 	}
4126 
4127 	/* initialize rx_buffer_info */
4128 	memset(ring->rx_buffer_info, 0,
4129 	       sizeof(struct ixgbe_rx_buffer) * ring->count);
4130 
4131 	/* initialize Rx descriptor 0 */
4132 	rx_desc = IXGBE_RX_DESC(ring, 0);
4133 	rx_desc->wb.upper.length = 0;
4134 
4135 	/* enable receive descriptor ring */
4136 	rxdctl |= IXGBE_RXDCTL_ENABLE;
4137 	IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
4138 
4139 	ixgbe_rx_desc_queue_enable(adapter, ring);
4140 	if (ring->xsk_pool)
4141 		ixgbe_alloc_rx_buffers_zc(ring, ixgbe_desc_unused(ring));
4142 	else
4143 		ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
4144 }
4145 
4146 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
4147 {
4148 	struct ixgbe_hw *hw = &adapter->hw;
4149 	int rss_i = adapter->ring_feature[RING_F_RSS].indices;
4150 	u16 pool = adapter->num_rx_pools;
4151 
4152 	/* PSRTYPE must be initialized in non 82598 adapters */
4153 	u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4154 		      IXGBE_PSRTYPE_UDPHDR |
4155 		      IXGBE_PSRTYPE_IPV4HDR |
4156 		      IXGBE_PSRTYPE_L2HDR |
4157 		      IXGBE_PSRTYPE_IPV6HDR;
4158 
4159 	if (hw->mac.type == ixgbe_mac_82598EB)
4160 		return;
4161 
4162 	if (rss_i > 3)
4163 		psrtype |= 2u << 29;
4164 	else if (rss_i > 1)
4165 		psrtype |= 1u << 29;
4166 
4167 	while (pool--)
4168 		IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4169 }
4170 
4171 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
4172 {
4173 	struct ixgbe_hw *hw = &adapter->hw;
4174 	u16 pool = adapter->num_rx_pools;
4175 	u32 reg_offset, vf_shift, vmolr;
4176 	u32 gcr_ext, vmdctl;
4177 	int i;
4178 
4179 	if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
4180 		return;
4181 
4182 	vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4183 	vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
4184 	vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
4185 	vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
4186 	vmdctl |= IXGBE_VT_CTL_REPLEN;
4187 	IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
4188 
4189 	/* accept untagged packets until a vlan tag is
4190 	 * specifically set for the VMDQ queue/pool
4191 	 */
4192 	vmolr = IXGBE_VMOLR_AUPE;
4193 	while (pool--)
4194 		IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(pool)), vmolr);
4195 
4196 	vf_shift = VMDQ_P(0) % 32;
4197 	reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
4198 
4199 	/* Enable only the PF's pool for Tx/Rx */
4200 	IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift));
4201 	IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
4202 	IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift));
4203 	IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
4204 	if (adapter->bridge_mode == BRIDGE_MODE_VEB)
4205 		IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
4206 
4207 	/* Map PF MAC address in RAR Entry 0 to first pool following VFs */
4208 	hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
4209 
4210 	/* clear VLAN promisc flag so VFTA will be updated if necessary */
4211 	adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4212 
4213 	/*
4214 	 * Set up VF register offsets for selected VT Mode,
4215 	 * i.e. 32 or 64 VFs for SR-IOV
4216 	 */
4217 	switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4218 	case IXGBE_82599_VMDQ_8Q_MASK:
4219 		gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
4220 		break;
4221 	case IXGBE_82599_VMDQ_4Q_MASK:
4222 		gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
4223 		break;
4224 	default:
4225 		gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
4226 		break;
4227 	}
4228 
4229 	IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4230 
4231 	for (i = 0; i < adapter->num_vfs; i++) {
4232 		/* configure spoof checking */
4233 		ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i,
4234 					  adapter->vfinfo[i].spoofchk_enabled);
4235 
4236 		/* Enable/Disable RSS query feature  */
4237 		ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
4238 					  adapter->vfinfo[i].rss_query_enabled);
4239 	}
4240 }
4241 
4242 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
4243 {
4244 	struct ixgbe_hw *hw = &adapter->hw;
4245 	struct net_device *netdev = adapter->netdev;
4246 	int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4247 	struct ixgbe_ring *rx_ring;
4248 	int i;
4249 	u32 mhadd, hlreg0;
4250 
4251 #ifdef IXGBE_FCOE
4252 	/* adjust max frame to be able to do baby jumbo for FCoE */
4253 	if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
4254 	    (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
4255 		max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4256 
4257 #endif /* IXGBE_FCOE */
4258 
4259 	/* adjust max frame to be at least the size of a standard frame */
4260 	if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
4261 		max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
4262 
4263 	mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
4264 	if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
4265 		mhadd &= ~IXGBE_MHADD_MFS_MASK;
4266 		mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
4267 
4268 		IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
4269 	}
4270 
4271 	hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4272 	/* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
4273 	hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4274 	IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4275 
4276 	/*
4277 	 * Setup the HW Rx Head and Tail Descriptor Pointers and
4278 	 * the Base and Length of the Rx Descriptor Ring
4279 	 */
4280 	for (i = 0; i < adapter->num_rx_queues; i++) {
4281 		rx_ring = adapter->rx_ring[i];
4282 
4283 		clear_ring_rsc_enabled(rx_ring);
4284 		clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4285 		clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
4286 
4287 		if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
4288 			set_ring_rsc_enabled(rx_ring);
4289 
4290 		if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state))
4291 			set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4292 
4293 		if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY)
4294 			continue;
4295 
4296 		set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
4297 
4298 #if (PAGE_SIZE < 8192)
4299 		if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
4300 			set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4301 
4302 		if (IXGBE_2K_TOO_SMALL_WITH_PADDING ||
4303 		    (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
4304 			set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4305 #endif
4306 	}
4307 }
4308 
4309 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
4310 {
4311 	struct ixgbe_hw *hw = &adapter->hw;
4312 	u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4313 
4314 	switch (hw->mac.type) {
4315 	case ixgbe_mac_82598EB:
4316 		/*
4317 		 * For VMDq support of different descriptor types or
4318 		 * buffer sizes through the use of multiple SRRCTL
4319 		 * registers, RDRXCTL.MVMEN must be set to 1
4320 		 *
4321 		 * also, the manual doesn't mention it clearly but DCA hints
4322 		 * will only use queue 0's tags unless this bit is set.  Side
4323 		 * effects of setting this bit are only that SRRCTL must be
4324 		 * fully programmed [0..15]
4325 		 */
4326 		rdrxctl |= IXGBE_RDRXCTL_MVMEN;
4327 		break;
4328 	case ixgbe_mac_X550:
4329 	case ixgbe_mac_X550EM_x:
4330 	case ixgbe_mac_x550em_a:
4331 		if (adapter->num_vfs)
4332 			rdrxctl |= IXGBE_RDRXCTL_PSP;
4333 		fallthrough;
4334 	case ixgbe_mac_82599EB:
4335 	case ixgbe_mac_X540:
4336 		/* Disable RSC for ACK packets */
4337 		IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
4338 		   (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
4339 		rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4340 		/* hardware requires some bits to be set by default */
4341 		rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
4342 		rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4343 		break;
4344 	default:
4345 		/* We should do nothing since we don't know this hardware */
4346 		return;
4347 	}
4348 
4349 	IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4350 }
4351 
4352 /**
4353  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
4354  * @adapter: board private structure
4355  *
4356  * Configure the Rx unit of the MAC after a reset.
4357  **/
4358 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
4359 {
4360 	struct ixgbe_hw *hw = &adapter->hw;
4361 	int i;
4362 	u32 rxctrl, rfctl;
4363 
4364 	/* disable receives while setting up the descriptors */
4365 	hw->mac.ops.disable_rx(hw);
4366 
4367 	ixgbe_setup_psrtype(adapter);
4368 	ixgbe_setup_rdrxctl(adapter);
4369 
4370 	/* RSC Setup */
4371 	rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4372 	rfctl &= ~IXGBE_RFCTL_RSC_DIS;
4373 	if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
4374 		rfctl |= IXGBE_RFCTL_RSC_DIS;
4375 
4376 	/* disable NFS filtering */
4377 	rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS);
4378 	IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4379 
4380 	/* Program registers for the distribution of queues */
4381 	ixgbe_setup_mrqc(adapter);
4382 
4383 	/* set_rx_buffer_len must be called before ring initialization */
4384 	ixgbe_set_rx_buffer_len(adapter);
4385 
4386 	/*
4387 	 * Setup the HW Rx Head and Tail Descriptor Pointers and
4388 	 * the Base and Length of the Rx Descriptor Ring
4389 	 */
4390 	for (i = 0; i < adapter->num_rx_queues; i++)
4391 		ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
4392 
4393 	rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4394 	/* disable drop enable for 82598 parts */
4395 	if (hw->mac.type == ixgbe_mac_82598EB)
4396 		rxctrl |= IXGBE_RXCTRL_DMBYPS;
4397 
4398 	/* enable all receives */
4399 	rxctrl |= IXGBE_RXCTRL_RXEN;
4400 	hw->mac.ops.enable_rx_dma(hw, rxctrl);
4401 }
4402 
4403 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
4404 				 __be16 proto, u16 vid)
4405 {
4406 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
4407 	struct ixgbe_hw *hw = &adapter->hw;
4408 
4409 	/* add VID to filter table */
4410 	if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4411 		hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid);
4412 
4413 	set_bit(vid, adapter->active_vlans);
4414 
4415 	return 0;
4416 }
4417 
4418 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan)
4419 {
4420 	u32 vlvf;
4421 	int idx;
4422 
4423 	/* short cut the special case */
4424 	if (vlan == 0)
4425 		return 0;
4426 
4427 	/* Search for the vlan id in the VLVF entries */
4428 	for (idx = IXGBE_VLVF_ENTRIES; --idx;) {
4429 		vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx));
4430 		if ((vlvf & VLAN_VID_MASK) == vlan)
4431 			break;
4432 	}
4433 
4434 	return idx;
4435 }
4436 
4437 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid)
4438 {
4439 	struct ixgbe_hw *hw = &adapter->hw;
4440 	u32 bits, word;
4441 	int idx;
4442 
4443 	idx = ixgbe_find_vlvf_entry(hw, vid);
4444 	if (!idx)
4445 		return;
4446 
4447 	/* See if any other pools are set for this VLAN filter
4448 	 * entry other than the PF.
4449 	 */
4450 	word = idx * 2 + (VMDQ_P(0) / 32);
4451 	bits = ~BIT(VMDQ_P(0) % 32);
4452 	bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4453 
4454 	/* Disable the filter so this falls into the default pool. */
4455 	if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) {
4456 		if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4457 			IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0);
4458 		IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0);
4459 	}
4460 }
4461 
4462 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
4463 				  __be16 proto, u16 vid)
4464 {
4465 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
4466 	struct ixgbe_hw *hw = &adapter->hw;
4467 
4468 	/* remove VID from filter table */
4469 	if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4470 		hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true);
4471 
4472 	clear_bit(vid, adapter->active_vlans);
4473 
4474 	return 0;
4475 }
4476 
4477 /**
4478  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
4479  * @adapter: driver data
4480  */
4481 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
4482 {
4483 	struct ixgbe_hw *hw = &adapter->hw;
4484 	u32 vlnctrl;
4485 	int i, j;
4486 
4487 	switch (hw->mac.type) {
4488 	case ixgbe_mac_82598EB:
4489 		vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4490 		vlnctrl &= ~IXGBE_VLNCTRL_VME;
4491 		IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4492 		break;
4493 	case ixgbe_mac_82599EB:
4494 	case ixgbe_mac_X540:
4495 	case ixgbe_mac_X550:
4496 	case ixgbe_mac_X550EM_x:
4497 	case ixgbe_mac_x550em_a:
4498 		for (i = 0; i < adapter->num_rx_queues; i++) {
4499 			struct ixgbe_ring *ring = adapter->rx_ring[i];
4500 
4501 			if (!netif_is_ixgbe(ring->netdev))
4502 				continue;
4503 
4504 			j = ring->reg_idx;
4505 			vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4506 			vlnctrl &= ~IXGBE_RXDCTL_VME;
4507 			IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4508 		}
4509 		break;
4510 	default:
4511 		break;
4512 	}
4513 }
4514 
4515 /**
4516  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
4517  * @adapter: driver data
4518  */
4519 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
4520 {
4521 	struct ixgbe_hw *hw = &adapter->hw;
4522 	u32 vlnctrl;
4523 	int i, j;
4524 
4525 	switch (hw->mac.type) {
4526 	case ixgbe_mac_82598EB:
4527 		vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4528 		vlnctrl |= IXGBE_VLNCTRL_VME;
4529 		IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4530 		break;
4531 	case ixgbe_mac_82599EB:
4532 	case ixgbe_mac_X540:
4533 	case ixgbe_mac_X550:
4534 	case ixgbe_mac_X550EM_x:
4535 	case ixgbe_mac_x550em_a:
4536 		for (i = 0; i < adapter->num_rx_queues; i++) {
4537 			struct ixgbe_ring *ring = adapter->rx_ring[i];
4538 
4539 			if (!netif_is_ixgbe(ring->netdev))
4540 				continue;
4541 
4542 			j = ring->reg_idx;
4543 			vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4544 			vlnctrl |= IXGBE_RXDCTL_VME;
4545 			IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4546 		}
4547 		break;
4548 	default:
4549 		break;
4550 	}
4551 }
4552 
4553 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter)
4554 {
4555 	struct ixgbe_hw *hw = &adapter->hw;
4556 	u32 vlnctrl, i;
4557 
4558 	vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4559 
4560 	if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
4561 	/* For VMDq and SR-IOV we must leave VLAN filtering enabled */
4562 		vlnctrl |= IXGBE_VLNCTRL_VFE;
4563 		IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4564 	} else {
4565 		vlnctrl &= ~IXGBE_VLNCTRL_VFE;
4566 		IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4567 		return;
4568 	}
4569 
4570 	/* Nothing to do for 82598 */
4571 	if (hw->mac.type == ixgbe_mac_82598EB)
4572 		return;
4573 
4574 	/* We are already in VLAN promisc, nothing to do */
4575 	if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)
4576 		return;
4577 
4578 	/* Set flag so we don't redo unnecessary work */
4579 	adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC;
4580 
4581 	/* Add PF to all active pools */
4582 	for (i = IXGBE_VLVF_ENTRIES; --i;) {
4583 		u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32);
4584 		u32 vlvfb = IXGBE_READ_REG(hw, reg_offset);
4585 
4586 		vlvfb |= BIT(VMDQ_P(0) % 32);
4587 		IXGBE_WRITE_REG(hw, reg_offset, vlvfb);
4588 	}
4589 
4590 	/* Set all bits in the VLAN filter table array */
4591 	for (i = hw->mac.vft_size; i--;)
4592 		IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U);
4593 }
4594 
4595 #define VFTA_BLOCK_SIZE 8
4596 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset)
4597 {
4598 	struct ixgbe_hw *hw = &adapter->hw;
4599 	u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4600 	u32 vid_start = vfta_offset * 32;
4601 	u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4602 	u32 i, vid, word, bits;
4603 
4604 	for (i = IXGBE_VLVF_ENTRIES; --i;) {
4605 		u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i));
4606 
4607 		/* pull VLAN ID from VLVF */
4608 		vid = vlvf & VLAN_VID_MASK;
4609 
4610 		/* only concern outselves with a certain range */
4611 		if (vid < vid_start || vid >= vid_end)
4612 			continue;
4613 
4614 		if (vlvf) {
4615 			/* record VLAN ID in VFTA */
4616 			vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
4617 
4618 			/* if PF is part of this then continue */
4619 			if (test_bit(vid, adapter->active_vlans))
4620 				continue;
4621 		}
4622 
4623 		/* remove PF from the pool */
4624 		word = i * 2 + VMDQ_P(0) / 32;
4625 		bits = ~BIT(VMDQ_P(0) % 32);
4626 		bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4627 		IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits);
4628 	}
4629 
4630 	/* extract values from active_vlans and write back to VFTA */
4631 	for (i = VFTA_BLOCK_SIZE; i--;) {
4632 		vid = (vfta_offset + i) * 32;
4633 		word = vid / BITS_PER_LONG;
4634 		bits = vid % BITS_PER_LONG;
4635 
4636 		vfta[i] |= adapter->active_vlans[word] >> bits;
4637 
4638 		IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]);
4639 	}
4640 }
4641 
4642 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter)
4643 {
4644 	struct ixgbe_hw *hw = &adapter->hw;
4645 	u32 vlnctrl, i;
4646 
4647 	/* Set VLAN filtering to enabled */
4648 	vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4649 	vlnctrl |= IXGBE_VLNCTRL_VFE;
4650 	IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4651 
4652 	if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) ||
4653 	    hw->mac.type == ixgbe_mac_82598EB)
4654 		return;
4655 
4656 	/* We are not in VLAN promisc, nothing to do */
4657 	if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4658 		return;
4659 
4660 	/* Set flag so we don't redo unnecessary work */
4661 	adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4662 
4663 	for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE)
4664 		ixgbe_scrub_vfta(adapter, i);
4665 }
4666 
4667 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
4668 {
4669 	u16 vid = 1;
4670 
4671 	ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
4672 
4673 	for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
4674 		ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
4675 }
4676 
4677 /**
4678  * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4679  * @netdev: network interface device structure
4680  *
4681  * Writes multicast address list to the MTA hash table.
4682  * Returns: -ENOMEM on failure
4683  *                0 on no addresses written
4684  *                X on writing X addresses to MTA
4685  **/
4686 static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4687 {
4688 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
4689 	struct ixgbe_hw *hw = &adapter->hw;
4690 
4691 	if (!netif_running(netdev))
4692 		return 0;
4693 
4694 	if (hw->mac.ops.update_mc_addr_list)
4695 		hw->mac.ops.update_mc_addr_list(hw, netdev);
4696 	else
4697 		return -ENOMEM;
4698 
4699 #ifdef CONFIG_PCI_IOV
4700 	ixgbe_restore_vf_multicasts(adapter);
4701 #endif
4702 
4703 	return netdev_mc_count(netdev);
4704 }
4705 
4706 #ifdef CONFIG_PCI_IOV
4707 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4708 {
4709 	struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4710 	struct ixgbe_hw *hw = &adapter->hw;
4711 	int i;
4712 
4713 	for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4714 		mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4715 
4716 		if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4717 			hw->mac.ops.set_rar(hw, i,
4718 					    mac_table->addr,
4719 					    mac_table->pool,
4720 					    IXGBE_RAH_AV);
4721 		else
4722 			hw->mac.ops.clear_rar(hw, i);
4723 	}
4724 }
4725 
4726 #endif
4727 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4728 {
4729 	struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4730 	struct ixgbe_hw *hw = &adapter->hw;
4731 	int i;
4732 
4733 	for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4734 		if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED))
4735 			continue;
4736 
4737 		mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4738 
4739 		if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4740 			hw->mac.ops.set_rar(hw, i,
4741 					    mac_table->addr,
4742 					    mac_table->pool,
4743 					    IXGBE_RAH_AV);
4744 		else
4745 			hw->mac.ops.clear_rar(hw, i);
4746 	}
4747 }
4748 
4749 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4750 {
4751 	struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4752 	struct ixgbe_hw *hw = &adapter->hw;
4753 	int i;
4754 
4755 	for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4756 		mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4757 		mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4758 	}
4759 
4760 	ixgbe_sync_mac_table(adapter);
4761 }
4762 
4763 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool)
4764 {
4765 	struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4766 	struct ixgbe_hw *hw = &adapter->hw;
4767 	int i, count = 0;
4768 
4769 	for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4770 		/* do not count default RAR as available */
4771 		if (mac_table->state & IXGBE_MAC_STATE_DEFAULT)
4772 			continue;
4773 
4774 		/* only count unused and addresses that belong to us */
4775 		if (mac_table->state & IXGBE_MAC_STATE_IN_USE) {
4776 			if (mac_table->pool != pool)
4777 				continue;
4778 		}
4779 
4780 		count++;
4781 	}
4782 
4783 	return count;
4784 }
4785 
4786 /* this function destroys the first RAR entry */
4787 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter)
4788 {
4789 	struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4790 	struct ixgbe_hw *hw = &adapter->hw;
4791 
4792 	memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN);
4793 	mac_table->pool = VMDQ_P(0);
4794 
4795 	mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE;
4796 
4797 	hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool,
4798 			    IXGBE_RAH_AV);
4799 }
4800 
4801 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4802 			 const u8 *addr, u16 pool)
4803 {
4804 	struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4805 	struct ixgbe_hw *hw = &adapter->hw;
4806 	int i;
4807 
4808 	if (is_zero_ether_addr(addr))
4809 		return -EINVAL;
4810 
4811 	for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4812 		if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4813 			continue;
4814 
4815 		ether_addr_copy(mac_table->addr, addr);
4816 		mac_table->pool = pool;
4817 
4818 		mac_table->state |= IXGBE_MAC_STATE_MODIFIED |
4819 				    IXGBE_MAC_STATE_IN_USE;
4820 
4821 		ixgbe_sync_mac_table(adapter);
4822 
4823 		return i;
4824 	}
4825 
4826 	return -ENOMEM;
4827 }
4828 
4829 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
4830 			 const u8 *addr, u16 pool)
4831 {
4832 	struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4833 	struct ixgbe_hw *hw = &adapter->hw;
4834 	int i;
4835 
4836 	if (is_zero_ether_addr(addr))
4837 		return -EINVAL;
4838 
4839 	/* search table for addr, if found clear IN_USE flag and sync */
4840 	for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4841 		/* we can only delete an entry if it is in use */
4842 		if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE))
4843 			continue;
4844 		/* we only care about entries that belong to the given pool */
4845 		if (mac_table->pool != pool)
4846 			continue;
4847 		/* we only care about a specific MAC address */
4848 		if (!ether_addr_equal(addr, mac_table->addr))
4849 			continue;
4850 
4851 		mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4852 		mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4853 
4854 		ixgbe_sync_mac_table(adapter);
4855 
4856 		return 0;
4857 	}
4858 
4859 	return -ENOMEM;
4860 }
4861 
4862 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr)
4863 {
4864 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
4865 	int ret;
4866 
4867 	ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0));
4868 
4869 	return min_t(int, ret, 0);
4870 }
4871 
4872 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr)
4873 {
4874 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
4875 
4876 	ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0));
4877 
4878 	return 0;
4879 }
4880 
4881 /**
4882  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
4883  * @netdev: network interface device structure
4884  *
4885  * The set_rx_method entry point is called whenever the unicast/multicast
4886  * address list or the network interface flags are updated.  This routine is
4887  * responsible for configuring the hardware for proper unicast, multicast and
4888  * promiscuous mode.
4889  **/
4890 void ixgbe_set_rx_mode(struct net_device *netdev)
4891 {
4892 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
4893 	struct ixgbe_hw *hw = &adapter->hw;
4894 	u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
4895 	netdev_features_t features = netdev->features;
4896 	int count;
4897 
4898 	/* Check for Promiscuous and All Multicast modes */
4899 	fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4900 
4901 	/* set all bits that we expect to always be set */
4902 	fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
4903 	fctrl |= IXGBE_FCTRL_BAM;
4904 	fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4905 	fctrl |= IXGBE_FCTRL_PMCF;
4906 
4907 	/* clear the bits we are changing the status of */
4908 	fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4909 	if (netdev->flags & IFF_PROMISC) {
4910 		hw->addr_ctrl.user_set_promisc = true;
4911 		fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4912 		vmolr |= IXGBE_VMOLR_MPE;
4913 		features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4914 	} else {
4915 		if (netdev->flags & IFF_ALLMULTI) {
4916 			fctrl |= IXGBE_FCTRL_MPE;
4917 			vmolr |= IXGBE_VMOLR_MPE;
4918 		}
4919 		hw->addr_ctrl.user_set_promisc = false;
4920 	}
4921 
4922 	/*
4923 	 * Write addresses to available RAR registers, if there is not
4924 	 * sufficient space to store all the addresses then enable
4925 	 * unicast promiscuous mode
4926 	 */
4927 	if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) {
4928 		fctrl |= IXGBE_FCTRL_UPE;
4929 		vmolr |= IXGBE_VMOLR_ROPE;
4930 	}
4931 
4932 	/* Write addresses to the MTA, if the attempt fails
4933 	 * then we should just turn on promiscuous mode so
4934 	 * that we can at least receive multicast traffic
4935 	 */
4936 	count = ixgbe_write_mc_addr_list(netdev);
4937 	if (count < 0) {
4938 		fctrl |= IXGBE_FCTRL_MPE;
4939 		vmolr |= IXGBE_VMOLR_MPE;
4940 	} else if (count) {
4941 		vmolr |= IXGBE_VMOLR_ROMPE;
4942 	}
4943 
4944 	if (hw->mac.type != ixgbe_mac_82598EB) {
4945 		vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
4946 			 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4947 			   IXGBE_VMOLR_ROPE);
4948 		IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
4949 	}
4950 
4951 	/* This is useful for sniffing bad packets. */
4952 	if (features & NETIF_F_RXALL) {
4953 		/* UPE and MPE will be handled by normal PROMISC logic
4954 		 * in e1000e_set_rx_mode */
4955 		fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4956 			  IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4957 			  IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4958 
4959 		fctrl &= ~(IXGBE_FCTRL_DPF);
4960 		/* NOTE:  VLAN filtering is disabled by setting PROMISC */
4961 	}
4962 
4963 	IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4964 
4965 	if (features & NETIF_F_HW_VLAN_CTAG_RX)
4966 		ixgbe_vlan_strip_enable(adapter);
4967 	else
4968 		ixgbe_vlan_strip_disable(adapter);
4969 
4970 	if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
4971 		ixgbe_vlan_promisc_disable(adapter);
4972 	else
4973 		ixgbe_vlan_promisc_enable(adapter);
4974 }
4975 
4976 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4977 {
4978 	int q_idx;
4979 
4980 	for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
4981 		napi_enable(&adapter->q_vector[q_idx]->napi);
4982 }
4983 
4984 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4985 {
4986 	int q_idx;
4987 
4988 	for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
4989 		napi_disable(&adapter->q_vector[q_idx]->napi);
4990 }
4991 
4992 static int ixgbe_udp_tunnel_sync(struct net_device *dev, unsigned int table)
4993 {
4994 	struct ixgbe_adapter *adapter = netdev_priv(dev);
4995 	struct ixgbe_hw *hw = &adapter->hw;
4996 	struct udp_tunnel_info ti;
4997 
4998 	udp_tunnel_nic_get_port(dev, table, 0, &ti);
4999 	if (ti.type == UDP_TUNNEL_TYPE_VXLAN)
5000 		adapter->vxlan_port = ti.port;
5001 	else
5002 		adapter->geneve_port = ti.port;
5003 
5004 	IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL,
5005 			ntohs(adapter->vxlan_port) |
5006 			ntohs(adapter->geneve_port) <<
5007 				IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT);
5008 	return 0;
5009 }
5010 
5011 static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550 = {
5012 	.sync_table	= ixgbe_udp_tunnel_sync,
5013 	.flags		= UDP_TUNNEL_NIC_INFO_IPV4_ONLY,
5014 	.tables		= {
5015 		{ .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN,  },
5016 	},
5017 };
5018 
5019 static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550em_a = {
5020 	.sync_table	= ixgbe_udp_tunnel_sync,
5021 	.flags		= UDP_TUNNEL_NIC_INFO_IPV4_ONLY,
5022 	.tables		= {
5023 		{ .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN,  },
5024 		{ .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, },
5025 	},
5026 };
5027 
5028 #ifdef CONFIG_IXGBE_DCB
5029 /**
5030  * ixgbe_configure_dcb - Configure DCB hardware
5031  * @adapter: ixgbe adapter struct
5032  *
5033  * This is called by the driver on open to configure the DCB hardware.
5034  * This is also called by the gennetlink interface when reconfiguring
5035  * the DCB state.
5036  */
5037 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
5038 {
5039 	struct ixgbe_hw *hw = &adapter->hw;
5040 	int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
5041 
5042 	if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
5043 		if (hw->mac.type == ixgbe_mac_82598EB)
5044 			netif_set_gso_max_size(adapter->netdev, 65536);
5045 		return;
5046 	}
5047 
5048 	if (hw->mac.type == ixgbe_mac_82598EB)
5049 		netif_set_gso_max_size(adapter->netdev, 32768);
5050 
5051 #ifdef IXGBE_FCOE
5052 	if (adapter->netdev->features & NETIF_F_FCOE_MTU)
5053 		max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
5054 #endif
5055 
5056 	/* reconfigure the hardware */
5057 	if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
5058 		ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
5059 						DCB_TX_CONFIG);
5060 		ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
5061 						DCB_RX_CONFIG);
5062 		ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
5063 	} else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
5064 		ixgbe_dcb_hw_ets(&adapter->hw,
5065 				 adapter->ixgbe_ieee_ets,
5066 				 max_frame);
5067 		ixgbe_dcb_hw_pfc_config(&adapter->hw,
5068 					adapter->ixgbe_ieee_pfc->pfc_en,
5069 					adapter->ixgbe_ieee_ets->prio_tc);
5070 	}
5071 
5072 	/* Enable RSS Hash per TC */
5073 	if (hw->mac.type != ixgbe_mac_82598EB) {
5074 		u32 msb = 0;
5075 		u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
5076 
5077 		while (rss_i) {
5078 			msb++;
5079 			rss_i >>= 1;
5080 		}
5081 
5082 		/* write msb to all 8 TCs in one write */
5083 		IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
5084 	}
5085 }
5086 #endif
5087 
5088 /* Additional bittime to account for IXGBE framing */
5089 #define IXGBE_ETH_FRAMING 20
5090 
5091 /**
5092  * ixgbe_hpbthresh - calculate high water mark for flow control
5093  *
5094  * @adapter: board private structure to calculate for
5095  * @pb: packet buffer to calculate
5096  */
5097 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
5098 {
5099 	struct ixgbe_hw *hw = &adapter->hw;
5100 	struct net_device *dev = adapter->netdev;
5101 	int link, tc, kb, marker;
5102 	u32 dv_id, rx_pba;
5103 
5104 	/* Calculate max LAN frame size */
5105 	tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
5106 
5107 #ifdef IXGBE_FCOE
5108 	/* FCoE traffic class uses FCOE jumbo frames */
5109 	if ((dev->features & NETIF_F_FCOE_MTU) &&
5110 	    (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
5111 	    (pb == ixgbe_fcoe_get_tc(adapter)))
5112 		tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
5113 #endif
5114 
5115 	/* Calculate delay value for device */
5116 	switch (hw->mac.type) {
5117 	case ixgbe_mac_X540:
5118 	case ixgbe_mac_X550:
5119 	case ixgbe_mac_X550EM_x:
5120 	case ixgbe_mac_x550em_a:
5121 		dv_id = IXGBE_DV_X540(link, tc);
5122 		break;
5123 	default:
5124 		dv_id = IXGBE_DV(link, tc);
5125 		break;
5126 	}
5127 
5128 	/* Loopback switch introduces additional latency */
5129 	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5130 		dv_id += IXGBE_B2BT(tc);
5131 
5132 	/* Delay value is calculated in bit times convert to KB */
5133 	kb = IXGBE_BT2KB(dv_id);
5134 	rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
5135 
5136 	marker = rx_pba - kb;
5137 
5138 	/* It is possible that the packet buffer is not large enough
5139 	 * to provide required headroom. In this case throw an error
5140 	 * to user and a do the best we can.
5141 	 */
5142 	if (marker < 0) {
5143 		e_warn(drv, "Packet Buffer(%i) can not provide enough"
5144 			    "headroom to support flow control."
5145 			    "Decrease MTU or number of traffic classes\n", pb);
5146 		marker = tc + 1;
5147 	}
5148 
5149 	return marker;
5150 }
5151 
5152 /**
5153  * ixgbe_lpbthresh - calculate low water mark for for flow control
5154  *
5155  * @adapter: board private structure to calculate for
5156  * @pb: packet buffer to calculate
5157  */
5158 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
5159 {
5160 	struct ixgbe_hw *hw = &adapter->hw;
5161 	struct net_device *dev = adapter->netdev;
5162 	int tc;
5163 	u32 dv_id;
5164 
5165 	/* Calculate max LAN frame size */
5166 	tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5167 
5168 #ifdef IXGBE_FCOE
5169 	/* FCoE traffic class uses FCOE jumbo frames */
5170 	if ((dev->features & NETIF_F_FCOE_MTU) &&
5171 	    (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
5172 	    (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
5173 		tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
5174 #endif
5175 
5176 	/* Calculate delay value for device */
5177 	switch (hw->mac.type) {
5178 	case ixgbe_mac_X540:
5179 	case ixgbe_mac_X550:
5180 	case ixgbe_mac_X550EM_x:
5181 	case ixgbe_mac_x550em_a:
5182 		dv_id = IXGBE_LOW_DV_X540(tc);
5183 		break;
5184 	default:
5185 		dv_id = IXGBE_LOW_DV(tc);
5186 		break;
5187 	}
5188 
5189 	/* Delay value is calculated in bit times convert to KB */
5190 	return IXGBE_BT2KB(dv_id);
5191 }
5192 
5193 /*
5194  * ixgbe_pbthresh_setup - calculate and setup high low water marks
5195  */
5196 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
5197 {
5198 	struct ixgbe_hw *hw = &adapter->hw;
5199 	int num_tc = adapter->hw_tcs;
5200 	int i;
5201 
5202 	if (!num_tc)
5203 		num_tc = 1;
5204 
5205 	for (i = 0; i < num_tc; i++) {
5206 		hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
5207 		hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
5208 
5209 		/* Low water marks must not be larger than high water marks */
5210 		if (hw->fc.low_water[i] > hw->fc.high_water[i])
5211 			hw->fc.low_water[i] = 0;
5212 	}
5213 
5214 	for (; i < MAX_TRAFFIC_CLASS; i++)
5215 		hw->fc.high_water[i] = 0;
5216 }
5217 
5218 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
5219 {
5220 	struct ixgbe_hw *hw = &adapter->hw;
5221 	int hdrm;
5222 	u8 tc = adapter->hw_tcs;
5223 
5224 	if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5225 	    adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5226 		hdrm = 32 << adapter->fdir_pballoc;
5227 	else
5228 		hdrm = 0;
5229 
5230 	hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
5231 	ixgbe_pbthresh_setup(adapter);
5232 }
5233 
5234 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
5235 {
5236 	struct ixgbe_hw *hw = &adapter->hw;
5237 	struct hlist_node *node2;
5238 	struct ixgbe_fdir_filter *filter;
5239 	u8 queue;
5240 
5241 	spin_lock(&adapter->fdir_perfect_lock);
5242 
5243 	if (!hlist_empty(&adapter->fdir_filter_list))
5244 		ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
5245 
5246 	hlist_for_each_entry_safe(filter, node2,
5247 				  &adapter->fdir_filter_list, fdir_node) {
5248 		if (filter->action == IXGBE_FDIR_DROP_QUEUE) {
5249 			queue = IXGBE_FDIR_DROP_QUEUE;
5250 		} else {
5251 			u32 ring = ethtool_get_flow_spec_ring(filter->action);
5252 			u8 vf = ethtool_get_flow_spec_ring_vf(filter->action);
5253 
5254 			if (!vf && (ring >= adapter->num_rx_queues)) {
5255 				e_err(drv, "FDIR restore failed without VF, ring: %u\n",
5256 				      ring);
5257 				continue;
5258 			} else if (vf &&
5259 				   ((vf > adapter->num_vfs) ||
5260 				     ring >= adapter->num_rx_queues_per_pool)) {
5261 				e_err(drv, "FDIR restore failed with VF, vf: %hhu, ring: %u\n",
5262 				      vf, ring);
5263 				continue;
5264 			}
5265 
5266 			/* Map the ring onto the absolute queue index */
5267 			if (!vf)
5268 				queue = adapter->rx_ring[ring]->reg_idx;
5269 			else
5270 				queue = ((vf - 1) *
5271 					adapter->num_rx_queues_per_pool) + ring;
5272 		}
5273 
5274 		ixgbe_fdir_write_perfect_filter_82599(hw,
5275 				&filter->filter, filter->sw_idx, queue);
5276 	}
5277 
5278 	spin_unlock(&adapter->fdir_perfect_lock);
5279 }
5280 
5281 /**
5282  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
5283  * @rx_ring: ring to free buffers from
5284  **/
5285 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
5286 {
5287 	u16 i = rx_ring->next_to_clean;
5288 	struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
5289 
5290 	if (rx_ring->xsk_pool) {
5291 		ixgbe_xsk_clean_rx_ring(rx_ring);
5292 		goto skip_free;
5293 	}
5294 
5295 	/* Free all the Rx ring sk_buffs */
5296 	while (i != rx_ring->next_to_alloc) {
5297 		if (rx_buffer->skb) {
5298 			struct sk_buff *skb = rx_buffer->skb;
5299 			if (IXGBE_CB(skb)->page_released)
5300 				dma_unmap_page_attrs(rx_ring->dev,
5301 						     IXGBE_CB(skb)->dma,
5302 						     ixgbe_rx_pg_size(rx_ring),
5303 						     DMA_FROM_DEVICE,
5304 						     IXGBE_RX_DMA_ATTR);
5305 			dev_kfree_skb(skb);
5306 		}
5307 
5308 		/* Invalidate cache lines that may have been written to by
5309 		 * device so that we avoid corrupting memory.
5310 		 */
5311 		dma_sync_single_range_for_cpu(rx_ring->dev,
5312 					      rx_buffer->dma,
5313 					      rx_buffer->page_offset,
5314 					      ixgbe_rx_bufsz(rx_ring),
5315 					      DMA_FROM_DEVICE);
5316 
5317 		/* free resources associated with mapping */
5318 		dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
5319 				     ixgbe_rx_pg_size(rx_ring),
5320 				     DMA_FROM_DEVICE,
5321 				     IXGBE_RX_DMA_ATTR);
5322 		__page_frag_cache_drain(rx_buffer->page,
5323 					rx_buffer->pagecnt_bias);
5324 
5325 		i++;
5326 		rx_buffer++;
5327 		if (i == rx_ring->count) {
5328 			i = 0;
5329 			rx_buffer = rx_ring->rx_buffer_info;
5330 		}
5331 	}
5332 
5333 skip_free:
5334 	rx_ring->next_to_alloc = 0;
5335 	rx_ring->next_to_clean = 0;
5336 	rx_ring->next_to_use = 0;
5337 }
5338 
5339 static int ixgbe_fwd_ring_up(struct ixgbe_adapter *adapter,
5340 			     struct ixgbe_fwd_adapter *accel)
5341 {
5342 	u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
5343 	int num_tc = netdev_get_num_tc(adapter->netdev);
5344 	struct net_device *vdev = accel->netdev;
5345 	int i, baseq, err;
5346 
5347 	baseq = accel->pool * adapter->num_rx_queues_per_pool;
5348 	netdev_dbg(vdev, "pool %i:%i queues %i:%i\n",
5349 		   accel->pool, adapter->num_rx_pools,
5350 		   baseq, baseq + adapter->num_rx_queues_per_pool);
5351 
5352 	accel->rx_base_queue = baseq;
5353 	accel->tx_base_queue = baseq;
5354 
5355 	/* record configuration for macvlan interface in vdev */
5356 	for (i = 0; i < num_tc; i++)
5357 		netdev_bind_sb_channel_queue(adapter->netdev, vdev,
5358 					     i, rss_i, baseq + (rss_i * i));
5359 
5360 	for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
5361 		adapter->rx_ring[baseq + i]->netdev = vdev;
5362 
5363 	/* Guarantee all rings are updated before we update the
5364 	 * MAC address filter.
5365 	 */
5366 	wmb();
5367 
5368 	/* ixgbe_add_mac_filter will return an index if it succeeds, so we
5369 	 * need to only treat it as an error value if it is negative.
5370 	 */
5371 	err = ixgbe_add_mac_filter(adapter, vdev->dev_addr,
5372 				   VMDQ_P(accel->pool));
5373 	if (err >= 0)
5374 		return 0;
5375 
5376 	/* if we cannot add the MAC rule then disable the offload */
5377 	macvlan_release_l2fw_offload(vdev);
5378 
5379 	for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
5380 		adapter->rx_ring[baseq + i]->netdev = NULL;
5381 
5382 	netdev_err(vdev, "L2FW offload disabled due to L2 filter error\n");
5383 
5384 	/* unbind the queues and drop the subordinate channel config */
5385 	netdev_unbind_sb_channel(adapter->netdev, vdev);
5386 	netdev_set_sb_channel(vdev, 0);
5387 
5388 	clear_bit(accel->pool, adapter->fwd_bitmask);
5389 	kfree(accel);
5390 
5391 	return err;
5392 }
5393 
5394 static int ixgbe_macvlan_up(struct net_device *vdev,
5395 			    struct netdev_nested_priv *priv)
5396 {
5397 	struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data;
5398 	struct ixgbe_fwd_adapter *accel;
5399 
5400 	if (!netif_is_macvlan(vdev))
5401 		return 0;
5402 
5403 	accel = macvlan_accel_priv(vdev);
5404 	if (!accel)
5405 		return 0;
5406 
5407 	ixgbe_fwd_ring_up(adapter, accel);
5408 
5409 	return 0;
5410 }
5411 
5412 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
5413 {
5414 	struct netdev_nested_priv priv = {
5415 		.data = (void *)adapter,
5416 	};
5417 
5418 	netdev_walk_all_upper_dev_rcu(adapter->netdev,
5419 				      ixgbe_macvlan_up, &priv);
5420 }
5421 
5422 static void ixgbe_configure(struct ixgbe_adapter *adapter)
5423 {
5424 	struct ixgbe_hw *hw = &adapter->hw;
5425 
5426 	ixgbe_configure_pb(adapter);
5427 #ifdef CONFIG_IXGBE_DCB
5428 	ixgbe_configure_dcb(adapter);
5429 #endif
5430 	/*
5431 	 * We must restore virtualization before VLANs or else
5432 	 * the VLVF registers will not be populated
5433 	 */
5434 	ixgbe_configure_virtualization(adapter);
5435 
5436 	ixgbe_set_rx_mode(adapter->netdev);
5437 	ixgbe_restore_vlan(adapter);
5438 	ixgbe_ipsec_restore(adapter);
5439 
5440 	switch (hw->mac.type) {
5441 	case ixgbe_mac_82599EB:
5442 	case ixgbe_mac_X540:
5443 		hw->mac.ops.disable_rx_buff(hw);
5444 		break;
5445 	default:
5446 		break;
5447 	}
5448 
5449 	if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
5450 		ixgbe_init_fdir_signature_82599(&adapter->hw,
5451 						adapter->fdir_pballoc);
5452 	} else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
5453 		ixgbe_init_fdir_perfect_82599(&adapter->hw,
5454 					      adapter->fdir_pballoc);
5455 		ixgbe_fdir_filter_restore(adapter);
5456 	}
5457 
5458 	switch (hw->mac.type) {
5459 	case ixgbe_mac_82599EB:
5460 	case ixgbe_mac_X540:
5461 		hw->mac.ops.enable_rx_buff(hw);
5462 		break;
5463 	default:
5464 		break;
5465 	}
5466 
5467 #ifdef CONFIG_IXGBE_DCA
5468 	/* configure DCA */
5469 	if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
5470 		ixgbe_setup_dca(adapter);
5471 #endif /* CONFIG_IXGBE_DCA */
5472 
5473 #ifdef IXGBE_FCOE
5474 	/* configure FCoE L2 filters, redirection table, and Rx control */
5475 	ixgbe_configure_fcoe(adapter);
5476 
5477 #endif /* IXGBE_FCOE */
5478 	ixgbe_configure_tx(adapter);
5479 	ixgbe_configure_rx(adapter);
5480 	ixgbe_configure_dfwd(adapter);
5481 }
5482 
5483 /**
5484  * ixgbe_sfp_link_config - set up SFP+ link
5485  * @adapter: pointer to private adapter struct
5486  **/
5487 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
5488 {
5489 	/*
5490 	 * We are assuming the worst case scenario here, and that
5491 	 * is that an SFP was inserted/removed after the reset
5492 	 * but before SFP detection was enabled.  As such the best
5493 	 * solution is to just start searching as soon as we start
5494 	 */
5495 	if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5496 		adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5497 
5498 	adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5499 	adapter->sfp_poll_time = 0;
5500 }
5501 
5502 /**
5503  * ixgbe_non_sfp_link_config - set up non-SFP+ link
5504  * @hw: pointer to private hardware struct
5505  *
5506  * Returns 0 on success, negative on failure
5507  **/
5508 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
5509 {
5510 	u32 speed;
5511 	bool autoneg, link_up = false;
5512 	int ret = IXGBE_ERR_LINK_SETUP;
5513 
5514 	if (hw->mac.ops.check_link)
5515 		ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
5516 
5517 	if (ret)
5518 		return ret;
5519 
5520 	speed = hw->phy.autoneg_advertised;
5521 	if (!speed && hw->mac.ops.get_link_capabilities) {
5522 		ret = hw->mac.ops.get_link_capabilities(hw, &speed,
5523 							&autoneg);
5524 		speed &= ~(IXGBE_LINK_SPEED_5GB_FULL |
5525 			   IXGBE_LINK_SPEED_2_5GB_FULL);
5526 	}
5527 
5528 	if (ret)
5529 		return ret;
5530 
5531 	if (hw->mac.ops.setup_link)
5532 		ret = hw->mac.ops.setup_link(hw, speed, link_up);
5533 
5534 	return ret;
5535 }
5536 
5537 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
5538 {
5539 	struct ixgbe_hw *hw = &adapter->hw;
5540 	u32 gpie = 0;
5541 
5542 	if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5543 		gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5544 		       IXGBE_GPIE_OCD;
5545 		gpie |= IXGBE_GPIE_EIAME;
5546 		/*
5547 		 * use EIAM to auto-mask when MSI-X interrupt is asserted
5548 		 * this saves a register write for every interrupt
5549 		 */
5550 		switch (hw->mac.type) {
5551 		case ixgbe_mac_82598EB:
5552 			IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5553 			break;
5554 		case ixgbe_mac_82599EB:
5555 		case ixgbe_mac_X540:
5556 		case ixgbe_mac_X550:
5557 		case ixgbe_mac_X550EM_x:
5558 		case ixgbe_mac_x550em_a:
5559 		default:
5560 			IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5561 			IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5562 			break;
5563 		}
5564 	} else {
5565 		/* legacy interrupts, use EIAM to auto-mask when reading EICR,
5566 		 * specifically only auto mask tx and rx interrupts */
5567 		IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5568 	}
5569 
5570 	/* XXX: to interrupt immediately for EICS writes, enable this */
5571 	/* gpie |= IXGBE_GPIE_EIMEN; */
5572 
5573 	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
5574 		gpie &= ~IXGBE_GPIE_VTMODE_MASK;
5575 
5576 		switch (adapter->ring_feature[RING_F_VMDQ].mask) {
5577 		case IXGBE_82599_VMDQ_8Q_MASK:
5578 			gpie |= IXGBE_GPIE_VTMODE_16;
5579 			break;
5580 		case IXGBE_82599_VMDQ_4Q_MASK:
5581 			gpie |= IXGBE_GPIE_VTMODE_32;
5582 			break;
5583 		default:
5584 			gpie |= IXGBE_GPIE_VTMODE_64;
5585 			break;
5586 		}
5587 	}
5588 
5589 	/* Enable Thermal over heat sensor interrupt */
5590 	if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
5591 		switch (adapter->hw.mac.type) {
5592 		case ixgbe_mac_82599EB:
5593 			gpie |= IXGBE_SDP0_GPIEN_8259X;
5594 			break;
5595 		default:
5596 			break;
5597 		}
5598 	}
5599 
5600 	/* Enable fan failure interrupt */
5601 	if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
5602 		gpie |= IXGBE_SDP1_GPIEN(hw);
5603 
5604 	switch (hw->mac.type) {
5605 	case ixgbe_mac_82599EB:
5606 		gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
5607 		break;
5608 	case ixgbe_mac_X550EM_x:
5609 	case ixgbe_mac_x550em_a:
5610 		gpie |= IXGBE_SDP0_GPIEN_X540;
5611 		break;
5612 	default:
5613 		break;
5614 	}
5615 
5616 	IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5617 }
5618 
5619 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
5620 {
5621 	struct ixgbe_hw *hw = &adapter->hw;
5622 	int err;
5623 	u32 ctrl_ext;
5624 
5625 	ixgbe_get_hw_control(adapter);
5626 	ixgbe_setup_gpie(adapter);
5627 
5628 	if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5629 		ixgbe_configure_msix(adapter);
5630 	else
5631 		ixgbe_configure_msi_and_legacy(adapter);
5632 
5633 	/* enable the optics for 82599 SFP+ fiber */
5634 	if (hw->mac.ops.enable_tx_laser)
5635 		hw->mac.ops.enable_tx_laser(hw);
5636 
5637 	if (hw->phy.ops.set_phy_power)
5638 		hw->phy.ops.set_phy_power(hw, true);
5639 
5640 	smp_mb__before_atomic();
5641 	clear_bit(__IXGBE_DOWN, &adapter->state);
5642 	ixgbe_napi_enable_all(adapter);
5643 
5644 	if (ixgbe_is_sfp(hw)) {
5645 		ixgbe_sfp_link_config(adapter);
5646 	} else {
5647 		err = ixgbe_non_sfp_link_config(hw);
5648 		if (err)
5649 			e_err(probe, "link_config FAILED %d\n", err);
5650 	}
5651 
5652 	/* clear any pending interrupts, may auto mask */
5653 	IXGBE_READ_REG(hw, IXGBE_EICR);
5654 	ixgbe_irq_enable(adapter, true, true);
5655 
5656 	/*
5657 	 * If this adapter has a fan, check to see if we had a failure
5658 	 * before we enabled the interrupt.
5659 	 */
5660 	if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5661 		u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5662 		if (esdp & IXGBE_ESDP_SDP1)
5663 			e_crit(drv, "Fan has stopped, replace the adapter\n");
5664 	}
5665 
5666 	/* bring the link up in the watchdog, this could race with our first
5667 	 * link up interrupt but shouldn't be a problem */
5668 	adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5669 	adapter->link_check_timeout = jiffies;
5670 	mod_timer(&adapter->service_timer, jiffies);
5671 
5672 	/* Set PF Reset Done bit so PF/VF Mail Ops can work */
5673 	ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5674 	ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5675 	IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
5676 }
5677 
5678 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5679 {
5680 	/* put off any impending NetWatchDogTimeout */
5681 	netif_trans_update(adapter->netdev);
5682 
5683 	while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
5684 		usleep_range(1000, 2000);
5685 	if (adapter->hw.phy.type == ixgbe_phy_fw)
5686 		ixgbe_watchdog_link_is_down(adapter);
5687 	ixgbe_down(adapter);
5688 	/*
5689 	 * If SR-IOV enabled then wait a bit before bringing the adapter
5690 	 * back up to give the VFs time to respond to the reset.  The
5691 	 * two second wait is based upon the watchdog timer cycle in
5692 	 * the VF driver.
5693 	 */
5694 	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5695 		msleep(2000);
5696 	ixgbe_up(adapter);
5697 	clear_bit(__IXGBE_RESETTING, &adapter->state);
5698 }
5699 
5700 void ixgbe_up(struct ixgbe_adapter *adapter)
5701 {
5702 	/* hardware has been reset, we need to reload some things */
5703 	ixgbe_configure(adapter);
5704 
5705 	ixgbe_up_complete(adapter);
5706 }
5707 
5708 static unsigned long ixgbe_get_completion_timeout(struct ixgbe_adapter *adapter)
5709 {
5710 	u16 devctl2;
5711 
5712 	pcie_capability_read_word(adapter->pdev, PCI_EXP_DEVCTL2, &devctl2);
5713 
5714 	switch (devctl2 & IXGBE_PCIDEVCTRL2_TIMEO_MASK) {
5715 	case IXGBE_PCIDEVCTRL2_17_34s:
5716 	case IXGBE_PCIDEVCTRL2_4_8s:
5717 		/* For now we cap the upper limit on delay to 2 seconds
5718 		 * as we end up going up to 34 seconds of delay in worst
5719 		 * case timeout value.
5720 		 */
5721 	case IXGBE_PCIDEVCTRL2_1_2s:
5722 		return 2000000ul;	/* 2.0 s */
5723 	case IXGBE_PCIDEVCTRL2_260_520ms:
5724 		return 520000ul;	/* 520 ms */
5725 	case IXGBE_PCIDEVCTRL2_65_130ms:
5726 		return 130000ul;	/* 130 ms */
5727 	case IXGBE_PCIDEVCTRL2_16_32ms:
5728 		return 32000ul;		/* 32 ms */
5729 	case IXGBE_PCIDEVCTRL2_1_2ms:
5730 		return 2000ul;		/* 2 ms */
5731 	case IXGBE_PCIDEVCTRL2_50_100us:
5732 		return 100ul;		/* 100 us */
5733 	case IXGBE_PCIDEVCTRL2_16_32ms_def:
5734 		return 32000ul;		/* 32 ms */
5735 	default:
5736 		break;
5737 	}
5738 
5739 	/* We shouldn't need to hit this path, but just in case default as
5740 	 * though completion timeout is not supported and support 32ms.
5741 	 */
5742 	return 32000ul;
5743 }
5744 
5745 void ixgbe_disable_rx(struct ixgbe_adapter *adapter)
5746 {
5747 	unsigned long wait_delay, delay_interval;
5748 	struct ixgbe_hw *hw = &adapter->hw;
5749 	int i, wait_loop;
5750 	u32 rxdctl;
5751 
5752 	/* disable receives */
5753 	hw->mac.ops.disable_rx(hw);
5754 
5755 	if (ixgbe_removed(hw->hw_addr))
5756 		return;
5757 
5758 	/* disable all enabled Rx queues */
5759 	for (i = 0; i < adapter->num_rx_queues; i++) {
5760 		struct ixgbe_ring *ring = adapter->rx_ring[i];
5761 		u8 reg_idx = ring->reg_idx;
5762 
5763 		rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
5764 		rxdctl &= ~IXGBE_RXDCTL_ENABLE;
5765 		rxdctl |= IXGBE_RXDCTL_SWFLSH;
5766 
5767 		/* write value back with RXDCTL.ENABLE bit cleared */
5768 		IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
5769 	}
5770 
5771 	/* RXDCTL.EN may not change on 82598 if link is down, so skip it */
5772 	if (hw->mac.type == ixgbe_mac_82598EB &&
5773 	    !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
5774 		return;
5775 
5776 	/* Determine our minimum delay interval. We will increase this value
5777 	 * with each subsequent test. This way if the device returns quickly
5778 	 * we should spend as little time as possible waiting, however as
5779 	 * the time increases we will wait for larger periods of time.
5780 	 *
5781 	 * The trick here is that we increase the interval using the
5782 	 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result
5783 	 * of that wait is that it totals up to 100x whatever interval we
5784 	 * choose. Since our minimum wait is 100us we can just divide the
5785 	 * total timeout by 100 to get our minimum delay interval.
5786 	 */
5787 	delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
5788 
5789 	wait_loop = IXGBE_MAX_RX_DESC_POLL;
5790 	wait_delay = delay_interval;
5791 
5792 	while (wait_loop--) {
5793 		usleep_range(wait_delay, wait_delay + 10);
5794 		wait_delay += delay_interval * 2;
5795 		rxdctl = 0;
5796 
5797 		/* OR together the reading of all the active RXDCTL registers,
5798 		 * and then test the result. We need the disable to complete
5799 		 * before we start freeing the memory and invalidating the
5800 		 * DMA mappings.
5801 		 */
5802 		for (i = 0; i < adapter->num_rx_queues; i++) {
5803 			struct ixgbe_ring *ring = adapter->rx_ring[i];
5804 			u8 reg_idx = ring->reg_idx;
5805 
5806 			rxdctl |= IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
5807 		}
5808 
5809 		if (!(rxdctl & IXGBE_RXDCTL_ENABLE))
5810 			return;
5811 	}
5812 
5813 	e_err(drv,
5814 	      "RXDCTL.ENABLE for one or more queues not cleared within the polling period\n");
5815 }
5816 
5817 void ixgbe_disable_tx(struct ixgbe_adapter *adapter)
5818 {
5819 	unsigned long wait_delay, delay_interval;
5820 	struct ixgbe_hw *hw = &adapter->hw;
5821 	int i, wait_loop;
5822 	u32 txdctl;
5823 
5824 	if (ixgbe_removed(hw->hw_addr))
5825 		return;
5826 
5827 	/* disable all enabled Tx queues */
5828 	for (i = 0; i < adapter->num_tx_queues; i++) {
5829 		struct ixgbe_ring *ring = adapter->tx_ring[i];
5830 		u8 reg_idx = ring->reg_idx;
5831 
5832 		IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5833 	}
5834 
5835 	/* disable all enabled XDP Tx queues */
5836 	for (i = 0; i < adapter->num_xdp_queues; i++) {
5837 		struct ixgbe_ring *ring = adapter->xdp_ring[i];
5838 		u8 reg_idx = ring->reg_idx;
5839 
5840 		IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5841 	}
5842 
5843 	/* If the link is not up there shouldn't be much in the way of
5844 	 * pending transactions. Those that are left will be flushed out
5845 	 * when the reset logic goes through the flush sequence to clean out
5846 	 * the pending Tx transactions.
5847 	 */
5848 	if (!(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
5849 		goto dma_engine_disable;
5850 
5851 	/* Determine our minimum delay interval. We will increase this value
5852 	 * with each subsequent test. This way if the device returns quickly
5853 	 * we should spend as little time as possible waiting, however as
5854 	 * the time increases we will wait for larger periods of time.
5855 	 *
5856 	 * The trick here is that we increase the interval using the
5857 	 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result
5858 	 * of that wait is that it totals up to 100x whatever interval we
5859 	 * choose. Since our minimum wait is 100us we can just divide the
5860 	 * total timeout by 100 to get our minimum delay interval.
5861 	 */
5862 	delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
5863 
5864 	wait_loop = IXGBE_MAX_RX_DESC_POLL;
5865 	wait_delay = delay_interval;
5866 
5867 	while (wait_loop--) {
5868 		usleep_range(wait_delay, wait_delay + 10);
5869 		wait_delay += delay_interval * 2;
5870 		txdctl = 0;
5871 
5872 		/* OR together the reading of all the active TXDCTL registers,
5873 		 * and then test the result. We need the disable to complete
5874 		 * before we start freeing the memory and invalidating the
5875 		 * DMA mappings.
5876 		 */
5877 		for (i = 0; i < adapter->num_tx_queues; i++) {
5878 			struct ixgbe_ring *ring = adapter->tx_ring[i];
5879 			u8 reg_idx = ring->reg_idx;
5880 
5881 			txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
5882 		}
5883 		for (i = 0; i < adapter->num_xdp_queues; i++) {
5884 			struct ixgbe_ring *ring = adapter->xdp_ring[i];
5885 			u8 reg_idx = ring->reg_idx;
5886 
5887 			txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
5888 		}
5889 
5890 		if (!(txdctl & IXGBE_TXDCTL_ENABLE))
5891 			goto dma_engine_disable;
5892 	}
5893 
5894 	e_err(drv,
5895 	      "TXDCTL.ENABLE for one or more queues not cleared within the polling period\n");
5896 
5897 dma_engine_disable:
5898 	/* Disable the Tx DMA engine on 82599 and later MAC */
5899 	switch (hw->mac.type) {
5900 	case ixgbe_mac_82599EB:
5901 	case ixgbe_mac_X540:
5902 	case ixgbe_mac_X550:
5903 	case ixgbe_mac_X550EM_x:
5904 	case ixgbe_mac_x550em_a:
5905 		IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
5906 				(IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5907 				 ~IXGBE_DMATXCTL_TE));
5908 		fallthrough;
5909 	default:
5910 		break;
5911 	}
5912 }
5913 
5914 void ixgbe_reset(struct ixgbe_adapter *adapter)
5915 {
5916 	struct ixgbe_hw *hw = &adapter->hw;
5917 	struct net_device *netdev = adapter->netdev;
5918 	int err;
5919 
5920 	if (ixgbe_removed(hw->hw_addr))
5921 		return;
5922 	/* lock SFP init bit to prevent race conditions with the watchdog */
5923 	while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5924 		usleep_range(1000, 2000);
5925 
5926 	/* clear all SFP and link config related flags while holding SFP_INIT */
5927 	adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5928 			     IXGBE_FLAG2_SFP_NEEDS_RESET);
5929 	adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5930 
5931 	err = hw->mac.ops.init_hw(hw);
5932 	switch (err) {
5933 	case 0:
5934 	case IXGBE_ERR_SFP_NOT_PRESENT:
5935 	case IXGBE_ERR_SFP_NOT_SUPPORTED:
5936 		break;
5937 	case IXGBE_ERR_MASTER_REQUESTS_PENDING:
5938 		e_dev_err("master disable timed out\n");
5939 		break;
5940 	case IXGBE_ERR_EEPROM_VERSION:
5941 		/* We are running on a pre-production device, log a warning */
5942 		e_dev_warn("This device is a pre-production adapter/LOM. "
5943 			   "Please be aware there may be issues associated with "
5944 			   "your hardware.  If you are experiencing problems "
5945 			   "please contact your Intel or hardware "
5946 			   "representative who provided you with this "
5947 			   "hardware.\n");
5948 		break;
5949 	default:
5950 		e_dev_err("Hardware Error: %d\n", err);
5951 	}
5952 
5953 	clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5954 
5955 	/* flush entries out of MAC table */
5956 	ixgbe_flush_sw_mac_table(adapter);
5957 	__dev_uc_unsync(netdev, NULL);
5958 
5959 	/* do not flush user set addresses */
5960 	ixgbe_mac_set_default_filter(adapter);
5961 
5962 	/* update SAN MAC vmdq pool selection */
5963 	if (hw->mac.san_mac_rar_index)
5964 		hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
5965 
5966 	if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
5967 		ixgbe_ptp_reset(adapter);
5968 
5969 	if (hw->phy.ops.set_phy_power) {
5970 		if (!netif_running(adapter->netdev) && !adapter->wol)
5971 			hw->phy.ops.set_phy_power(hw, false);
5972 		else
5973 			hw->phy.ops.set_phy_power(hw, true);
5974 	}
5975 }
5976 
5977 /**
5978  * ixgbe_clean_tx_ring - Free Tx Buffers
5979  * @tx_ring: ring to be cleaned
5980  **/
5981 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
5982 {
5983 	u16 i = tx_ring->next_to_clean;
5984 	struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
5985 
5986 	if (tx_ring->xsk_pool) {
5987 		ixgbe_xsk_clean_tx_ring(tx_ring);
5988 		goto out;
5989 	}
5990 
5991 	while (i != tx_ring->next_to_use) {
5992 		union ixgbe_adv_tx_desc *eop_desc, *tx_desc;
5993 
5994 		/* Free all the Tx ring sk_buffs */
5995 		if (ring_is_xdp(tx_ring))
5996 			xdp_return_frame(tx_buffer->xdpf);
5997 		else
5998 			dev_kfree_skb_any(tx_buffer->skb);
5999 
6000 		/* unmap skb header data */
6001 		dma_unmap_single(tx_ring->dev,
6002 				 dma_unmap_addr(tx_buffer, dma),
6003 				 dma_unmap_len(tx_buffer, len),
6004 				 DMA_TO_DEVICE);
6005 
6006 		/* check for eop_desc to determine the end of the packet */
6007 		eop_desc = tx_buffer->next_to_watch;
6008 		tx_desc = IXGBE_TX_DESC(tx_ring, i);
6009 
6010 		/* unmap remaining buffers */
6011 		while (tx_desc != eop_desc) {
6012 			tx_buffer++;
6013 			tx_desc++;
6014 			i++;
6015 			if (unlikely(i == tx_ring->count)) {
6016 				i = 0;
6017 				tx_buffer = tx_ring->tx_buffer_info;
6018 				tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6019 			}
6020 
6021 			/* unmap any remaining paged data */
6022 			if (dma_unmap_len(tx_buffer, len))
6023 				dma_unmap_page(tx_ring->dev,
6024 					       dma_unmap_addr(tx_buffer, dma),
6025 					       dma_unmap_len(tx_buffer, len),
6026 					       DMA_TO_DEVICE);
6027 		}
6028 
6029 		/* move us one more past the eop_desc for start of next pkt */
6030 		tx_buffer++;
6031 		i++;
6032 		if (unlikely(i == tx_ring->count)) {
6033 			i = 0;
6034 			tx_buffer = tx_ring->tx_buffer_info;
6035 		}
6036 	}
6037 
6038 	/* reset BQL for queue */
6039 	if (!ring_is_xdp(tx_ring))
6040 		netdev_tx_reset_queue(txring_txq(tx_ring));
6041 
6042 out:
6043 	/* reset next_to_use and next_to_clean */
6044 	tx_ring->next_to_use = 0;
6045 	tx_ring->next_to_clean = 0;
6046 }
6047 
6048 /**
6049  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
6050  * @adapter: board private structure
6051  **/
6052 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
6053 {
6054 	int i;
6055 
6056 	for (i = 0; i < adapter->num_rx_queues; i++)
6057 		ixgbe_clean_rx_ring(adapter->rx_ring[i]);
6058 }
6059 
6060 /**
6061  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
6062  * @adapter: board private structure
6063  **/
6064 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
6065 {
6066 	int i;
6067 
6068 	for (i = 0; i < adapter->num_tx_queues; i++)
6069 		ixgbe_clean_tx_ring(adapter->tx_ring[i]);
6070 	for (i = 0; i < adapter->num_xdp_queues; i++)
6071 		ixgbe_clean_tx_ring(adapter->xdp_ring[i]);
6072 }
6073 
6074 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
6075 {
6076 	struct hlist_node *node2;
6077 	struct ixgbe_fdir_filter *filter;
6078 
6079 	spin_lock(&adapter->fdir_perfect_lock);
6080 
6081 	hlist_for_each_entry_safe(filter, node2,
6082 				  &adapter->fdir_filter_list, fdir_node) {
6083 		hlist_del(&filter->fdir_node);
6084 		kfree(filter);
6085 	}
6086 	adapter->fdir_filter_count = 0;
6087 
6088 	spin_unlock(&adapter->fdir_perfect_lock);
6089 }
6090 
6091 void ixgbe_down(struct ixgbe_adapter *adapter)
6092 {
6093 	struct net_device *netdev = adapter->netdev;
6094 	struct ixgbe_hw *hw = &adapter->hw;
6095 	int i;
6096 
6097 	/* signal that we are down to the interrupt handler */
6098 	if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
6099 		return; /* do nothing if already down */
6100 
6101 	/* Shut off incoming Tx traffic */
6102 	netif_tx_stop_all_queues(netdev);
6103 
6104 	/* call carrier off first to avoid false dev_watchdog timeouts */
6105 	netif_carrier_off(netdev);
6106 	netif_tx_disable(netdev);
6107 
6108 	/* Disable Rx */
6109 	ixgbe_disable_rx(adapter);
6110 
6111 	/* synchronize_rcu() needed for pending XDP buffers to drain */
6112 	if (adapter->xdp_ring[0])
6113 		synchronize_rcu();
6114 
6115 	ixgbe_irq_disable(adapter);
6116 
6117 	ixgbe_napi_disable_all(adapter);
6118 
6119 	clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
6120 	adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
6121 	adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6122 
6123 	del_timer_sync(&adapter->service_timer);
6124 
6125 	if (adapter->num_vfs) {
6126 		/* Clear EITR Select mapping */
6127 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
6128 
6129 		/* Mark all the VFs as inactive */
6130 		for (i = 0 ; i < adapter->num_vfs; i++)
6131 			adapter->vfinfo[i].clear_to_send = false;
6132 
6133 		/* ping all the active vfs to let them know we are going down */
6134 		ixgbe_ping_all_vfs(adapter);
6135 
6136 		/* Disable all VFTE/VFRE TX/RX */
6137 		ixgbe_disable_tx_rx(adapter);
6138 	}
6139 
6140 	/* disable transmits in the hardware now that interrupts are off */
6141 	ixgbe_disable_tx(adapter);
6142 
6143 	if (!pci_channel_offline(adapter->pdev))
6144 		ixgbe_reset(adapter);
6145 
6146 	/* power down the optics for 82599 SFP+ fiber */
6147 	if (hw->mac.ops.disable_tx_laser)
6148 		hw->mac.ops.disable_tx_laser(hw);
6149 
6150 	ixgbe_clean_all_tx_rings(adapter);
6151 	ixgbe_clean_all_rx_rings(adapter);
6152 }
6153 
6154 /**
6155  * ixgbe_eee_capable - helper function to determine EEE support on X550
6156  * @adapter: board private structure
6157  */
6158 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter)
6159 {
6160 	struct ixgbe_hw *hw = &adapter->hw;
6161 
6162 	switch (hw->device_id) {
6163 	case IXGBE_DEV_ID_X550EM_A_1G_T:
6164 	case IXGBE_DEV_ID_X550EM_A_1G_T_L:
6165 		if (!hw->phy.eee_speeds_supported)
6166 			break;
6167 		adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE;
6168 		if (!hw->phy.eee_speeds_advertised)
6169 			break;
6170 		adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED;
6171 		break;
6172 	default:
6173 		adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE;
6174 		adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED;
6175 		break;
6176 	}
6177 }
6178 
6179 /**
6180  * ixgbe_tx_timeout - Respond to a Tx Hang
6181  * @netdev: network interface device structure
6182  * @txqueue: queue number that timed out
6183  **/
6184 static void ixgbe_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue)
6185 {
6186 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
6187 
6188 	/* Do the reset outside of interrupt context */
6189 	ixgbe_tx_timeout_reset(adapter);
6190 }
6191 
6192 #ifdef CONFIG_IXGBE_DCB
6193 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter)
6194 {
6195 	struct ixgbe_hw *hw = &adapter->hw;
6196 	struct tc_configuration *tc;
6197 	int j;
6198 
6199 	switch (hw->mac.type) {
6200 	case ixgbe_mac_82598EB:
6201 	case ixgbe_mac_82599EB:
6202 		adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
6203 		adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
6204 		break;
6205 	case ixgbe_mac_X540:
6206 	case ixgbe_mac_X550:
6207 		adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
6208 		adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
6209 		break;
6210 	case ixgbe_mac_X550EM_x:
6211 	case ixgbe_mac_x550em_a:
6212 	default:
6213 		adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS;
6214 		adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS;
6215 		break;
6216 	}
6217 
6218 	/* Configure DCB traffic classes */
6219 	for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
6220 		tc = &adapter->dcb_cfg.tc_config[j];
6221 		tc->path[DCB_TX_CONFIG].bwg_id = 0;
6222 		tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
6223 		tc->path[DCB_RX_CONFIG].bwg_id = 0;
6224 		tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
6225 		tc->dcb_pfc = pfc_disabled;
6226 	}
6227 
6228 	/* Initialize default user to priority mapping, UPx->TC0 */
6229 	tc = &adapter->dcb_cfg.tc_config[0];
6230 	tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
6231 	tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
6232 
6233 	adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
6234 	adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
6235 	adapter->dcb_cfg.pfc_mode_enable = false;
6236 	adapter->dcb_set_bitmap = 0x00;
6237 	if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE)
6238 		adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
6239 	memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
6240 	       sizeof(adapter->temp_dcb_cfg));
6241 }
6242 #endif
6243 
6244 /**
6245  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
6246  * @adapter: board private structure to initialize
6247  * @ii: pointer to ixgbe_info for device
6248  *
6249  * ixgbe_sw_init initializes the Adapter private data structure.
6250  * Fields are initialized based on PCI device information and
6251  * OS network device settings (MTU size).
6252  **/
6253 static int ixgbe_sw_init(struct ixgbe_adapter *adapter,
6254 			 const struct ixgbe_info *ii)
6255 {
6256 	struct ixgbe_hw *hw = &adapter->hw;
6257 	struct pci_dev *pdev = adapter->pdev;
6258 	unsigned int rss, fdir;
6259 	u32 fwsm;
6260 	int i;
6261 
6262 	/* PCI config space info */
6263 
6264 	hw->vendor_id = pdev->vendor;
6265 	hw->device_id = pdev->device;
6266 	hw->revision_id = pdev->revision;
6267 	hw->subsystem_vendor_id = pdev->subsystem_vendor;
6268 	hw->subsystem_device_id = pdev->subsystem_device;
6269 
6270 	/* get_invariants needs the device IDs */
6271 	ii->get_invariants(hw);
6272 
6273 	/* Set common capability flags and settings */
6274 	rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
6275 	adapter->ring_feature[RING_F_RSS].limit = rss;
6276 	adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
6277 	adapter->max_q_vectors = MAX_Q_VECTORS_82599;
6278 	adapter->atr_sample_rate = 20;
6279 	fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
6280 	adapter->ring_feature[RING_F_FDIR].limit = fdir;
6281 	adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
6282 	adapter->ring_feature[RING_F_VMDQ].limit = 1;
6283 #ifdef CONFIG_IXGBE_DCA
6284 	adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
6285 #endif
6286 #ifdef CONFIG_IXGBE_DCB
6287 	adapter->flags |= IXGBE_FLAG_DCB_CAPABLE;
6288 	adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6289 #endif
6290 #ifdef IXGBE_FCOE
6291 	adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
6292 	adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
6293 #ifdef CONFIG_IXGBE_DCB
6294 	/* Default traffic class to use for FCoE */
6295 	adapter->fcoe.up = IXGBE_FCOE_DEFTC;
6296 #endif /* CONFIG_IXGBE_DCB */
6297 #endif /* IXGBE_FCOE */
6298 
6299 	/* initialize static ixgbe jump table entries */
6300 	adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]),
6301 					  GFP_KERNEL);
6302 	if (!adapter->jump_tables[0])
6303 		return -ENOMEM;
6304 	adapter->jump_tables[0]->mat = ixgbe_ipv4_fields;
6305 
6306 	for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++)
6307 		adapter->jump_tables[i] = NULL;
6308 
6309 	adapter->mac_table = kcalloc(hw->mac.num_rar_entries,
6310 				     sizeof(struct ixgbe_mac_addr),
6311 				     GFP_KERNEL);
6312 	if (!adapter->mac_table)
6313 		return -ENOMEM;
6314 
6315 	if (ixgbe_init_rss_key(adapter))
6316 		return -ENOMEM;
6317 
6318 	adapter->af_xdp_zc_qps = bitmap_zalloc(MAX_XDP_QUEUES, GFP_KERNEL);
6319 	if (!adapter->af_xdp_zc_qps)
6320 		return -ENOMEM;
6321 
6322 	/* Set MAC specific capability flags and exceptions */
6323 	switch (hw->mac.type) {
6324 	case ixgbe_mac_82598EB:
6325 		adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
6326 
6327 		if (hw->device_id == IXGBE_DEV_ID_82598AT)
6328 			adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
6329 
6330 		adapter->max_q_vectors = MAX_Q_VECTORS_82598;
6331 		adapter->ring_feature[RING_F_FDIR].limit = 0;
6332 		adapter->atr_sample_rate = 0;
6333 		adapter->fdir_pballoc = 0;
6334 #ifdef IXGBE_FCOE
6335 		adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6336 		adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
6337 #ifdef CONFIG_IXGBE_DCB
6338 		adapter->fcoe.up = 0;
6339 #endif /* IXGBE_DCB */
6340 #endif /* IXGBE_FCOE */
6341 		break;
6342 	case ixgbe_mac_82599EB:
6343 		if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
6344 			adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6345 		break;
6346 	case ixgbe_mac_X540:
6347 		fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
6348 		if (fwsm & IXGBE_FWSM_TS_ENABLED)
6349 			adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6350 		break;
6351 	case ixgbe_mac_x550em_a:
6352 		switch (hw->device_id) {
6353 		case IXGBE_DEV_ID_X550EM_A_1G_T:
6354 		case IXGBE_DEV_ID_X550EM_A_1G_T_L:
6355 			adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6356 			break;
6357 		default:
6358 			break;
6359 		}
6360 		fallthrough;
6361 	case ixgbe_mac_X550EM_x:
6362 #ifdef CONFIG_IXGBE_DCB
6363 		adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE;
6364 #endif
6365 #ifdef IXGBE_FCOE
6366 		adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6367 #ifdef CONFIG_IXGBE_DCB
6368 		adapter->fcoe.up = 0;
6369 #endif /* IXGBE_DCB */
6370 #endif /* IXGBE_FCOE */
6371 		fallthrough;
6372 	case ixgbe_mac_X550:
6373 		if (hw->mac.type == ixgbe_mac_X550)
6374 			adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6375 #ifdef CONFIG_IXGBE_DCA
6376 		adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
6377 #endif
6378 		break;
6379 	default:
6380 		break;
6381 	}
6382 
6383 #ifdef IXGBE_FCOE
6384 	/* FCoE support exists, always init the FCoE lock */
6385 	spin_lock_init(&adapter->fcoe.lock);
6386 
6387 #endif
6388 	/* n-tuple support exists, always init our spinlock */
6389 	spin_lock_init(&adapter->fdir_perfect_lock);
6390 
6391 #ifdef CONFIG_IXGBE_DCB
6392 	ixgbe_init_dcb(adapter);
6393 #endif
6394 	ixgbe_init_ipsec_offload(adapter);
6395 
6396 	/* default flow control settings */
6397 	hw->fc.requested_mode = ixgbe_fc_full;
6398 	hw->fc.current_mode = ixgbe_fc_full;	/* init for ethtool output */
6399 	ixgbe_pbthresh_setup(adapter);
6400 	hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
6401 	hw->fc.send_xon = true;
6402 	hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
6403 
6404 #ifdef CONFIG_PCI_IOV
6405 	if (max_vfs > 0)
6406 		e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
6407 
6408 	/* assign number of SR-IOV VFs */
6409 	if (hw->mac.type != ixgbe_mac_82598EB) {
6410 		if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
6411 			max_vfs = 0;
6412 			e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
6413 		}
6414 	}
6415 #endif /* CONFIG_PCI_IOV */
6416 
6417 	/* enable itr by default in dynamic mode */
6418 	adapter->rx_itr_setting = 1;
6419 	adapter->tx_itr_setting = 1;
6420 
6421 	/* set default ring sizes */
6422 	adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
6423 	adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
6424 
6425 	/* set default work limits */
6426 	adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
6427 
6428 	/* initialize eeprom parameters */
6429 	if (ixgbe_init_eeprom_params_generic(hw)) {
6430 		e_dev_err("EEPROM initialization failed\n");
6431 		return -EIO;
6432 	}
6433 
6434 	/* PF holds first pool slot */
6435 	set_bit(0, adapter->fwd_bitmask);
6436 	set_bit(__IXGBE_DOWN, &adapter->state);
6437 
6438 	return 0;
6439 }
6440 
6441 /**
6442  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
6443  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
6444  *
6445  * Return 0 on success, negative on failure
6446  **/
6447 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
6448 {
6449 	struct device *dev = tx_ring->dev;
6450 	int orig_node = dev_to_node(dev);
6451 	int ring_node = NUMA_NO_NODE;
6452 	int size;
6453 
6454 	size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
6455 
6456 	if (tx_ring->q_vector)
6457 		ring_node = tx_ring->q_vector->numa_node;
6458 
6459 	tx_ring->tx_buffer_info = vmalloc_node(size, ring_node);
6460 	if (!tx_ring->tx_buffer_info)
6461 		tx_ring->tx_buffer_info = vmalloc(size);
6462 	if (!tx_ring->tx_buffer_info)
6463 		goto err;
6464 
6465 	/* round up to nearest 4K */
6466 	tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
6467 	tx_ring->size = ALIGN(tx_ring->size, 4096);
6468 
6469 	set_dev_node(dev, ring_node);
6470 	tx_ring->desc = dma_alloc_coherent(dev,
6471 					   tx_ring->size,
6472 					   &tx_ring->dma,
6473 					   GFP_KERNEL);
6474 	set_dev_node(dev, orig_node);
6475 	if (!tx_ring->desc)
6476 		tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
6477 						   &tx_ring->dma, GFP_KERNEL);
6478 	if (!tx_ring->desc)
6479 		goto err;
6480 
6481 	tx_ring->next_to_use = 0;
6482 	tx_ring->next_to_clean = 0;
6483 	return 0;
6484 
6485 err:
6486 	vfree(tx_ring->tx_buffer_info);
6487 	tx_ring->tx_buffer_info = NULL;
6488 	dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
6489 	return -ENOMEM;
6490 }
6491 
6492 /**
6493  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
6494  * @adapter: board private structure
6495  *
6496  * If this function returns with an error, then it's possible one or
6497  * more of the rings is populated (while the rest are not).  It is the
6498  * callers duty to clean those orphaned rings.
6499  *
6500  * Return 0 on success, negative on failure
6501  **/
6502 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
6503 {
6504 	int i, j = 0, err = 0;
6505 
6506 	for (i = 0; i < adapter->num_tx_queues; i++) {
6507 		err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
6508 		if (!err)
6509 			continue;
6510 
6511 		e_err(probe, "Allocation for Tx Queue %u failed\n", i);
6512 		goto err_setup_tx;
6513 	}
6514 	for (j = 0; j < adapter->num_xdp_queues; j++) {
6515 		err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]);
6516 		if (!err)
6517 			continue;
6518 
6519 		e_err(probe, "Allocation for Tx Queue %u failed\n", j);
6520 		goto err_setup_tx;
6521 	}
6522 
6523 	return 0;
6524 err_setup_tx:
6525 	/* rewind the index freeing the rings as we go */
6526 	while (j--)
6527 		ixgbe_free_tx_resources(adapter->xdp_ring[j]);
6528 	while (i--)
6529 		ixgbe_free_tx_resources(adapter->tx_ring[i]);
6530 	return err;
6531 }
6532 
6533 /**
6534  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
6535  * @adapter: pointer to ixgbe_adapter
6536  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
6537  *
6538  * Returns 0 on success, negative on failure
6539  **/
6540 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
6541 			     struct ixgbe_ring *rx_ring)
6542 {
6543 	struct device *dev = rx_ring->dev;
6544 	int orig_node = dev_to_node(dev);
6545 	int ring_node = NUMA_NO_NODE;
6546 	int size;
6547 
6548 	size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
6549 
6550 	if (rx_ring->q_vector)
6551 		ring_node = rx_ring->q_vector->numa_node;
6552 
6553 	rx_ring->rx_buffer_info = vmalloc_node(size, ring_node);
6554 	if (!rx_ring->rx_buffer_info)
6555 		rx_ring->rx_buffer_info = vmalloc(size);
6556 	if (!rx_ring->rx_buffer_info)
6557 		goto err;
6558 
6559 	/* Round up to nearest 4K */
6560 	rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
6561 	rx_ring->size = ALIGN(rx_ring->size, 4096);
6562 
6563 	set_dev_node(dev, ring_node);
6564 	rx_ring->desc = dma_alloc_coherent(dev,
6565 					   rx_ring->size,
6566 					   &rx_ring->dma,
6567 					   GFP_KERNEL);
6568 	set_dev_node(dev, orig_node);
6569 	if (!rx_ring->desc)
6570 		rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
6571 						   &rx_ring->dma, GFP_KERNEL);
6572 	if (!rx_ring->desc)
6573 		goto err;
6574 
6575 	rx_ring->next_to_clean = 0;
6576 	rx_ring->next_to_use = 0;
6577 
6578 	/* XDP RX-queue info */
6579 	if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev,
6580 			     rx_ring->queue_index) < 0)
6581 		goto err;
6582 
6583 	rx_ring->xdp_prog = adapter->xdp_prog;
6584 
6585 	return 0;
6586 err:
6587 	vfree(rx_ring->rx_buffer_info);
6588 	rx_ring->rx_buffer_info = NULL;
6589 	dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
6590 	return -ENOMEM;
6591 }
6592 
6593 /**
6594  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
6595  * @adapter: board private structure
6596  *
6597  * If this function returns with an error, then it's possible one or
6598  * more of the rings is populated (while the rest are not).  It is the
6599  * callers duty to clean those orphaned rings.
6600  *
6601  * Return 0 on success, negative on failure
6602  **/
6603 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
6604 {
6605 	int i, err = 0;
6606 
6607 	for (i = 0; i < adapter->num_rx_queues; i++) {
6608 		err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
6609 		if (!err)
6610 			continue;
6611 
6612 		e_err(probe, "Allocation for Rx Queue %u failed\n", i);
6613 		goto err_setup_rx;
6614 	}
6615 
6616 #ifdef IXGBE_FCOE
6617 	err = ixgbe_setup_fcoe_ddp_resources(adapter);
6618 	if (!err)
6619 #endif
6620 		return 0;
6621 err_setup_rx:
6622 	/* rewind the index freeing the rings as we go */
6623 	while (i--)
6624 		ixgbe_free_rx_resources(adapter->rx_ring[i]);
6625 	return err;
6626 }
6627 
6628 /**
6629  * ixgbe_free_tx_resources - Free Tx Resources per Queue
6630  * @tx_ring: Tx descriptor ring for a specific queue
6631  *
6632  * Free all transmit software resources
6633  **/
6634 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
6635 {
6636 	ixgbe_clean_tx_ring(tx_ring);
6637 
6638 	vfree(tx_ring->tx_buffer_info);
6639 	tx_ring->tx_buffer_info = NULL;
6640 
6641 	/* if not set, then don't free */
6642 	if (!tx_ring->desc)
6643 		return;
6644 
6645 	dma_free_coherent(tx_ring->dev, tx_ring->size,
6646 			  tx_ring->desc, tx_ring->dma);
6647 
6648 	tx_ring->desc = NULL;
6649 }
6650 
6651 /**
6652  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
6653  * @adapter: board private structure
6654  *
6655  * Free all transmit software resources
6656  **/
6657 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
6658 {
6659 	int i;
6660 
6661 	for (i = 0; i < adapter->num_tx_queues; i++)
6662 		if (adapter->tx_ring[i]->desc)
6663 			ixgbe_free_tx_resources(adapter->tx_ring[i]);
6664 	for (i = 0; i < adapter->num_xdp_queues; i++)
6665 		if (adapter->xdp_ring[i]->desc)
6666 			ixgbe_free_tx_resources(adapter->xdp_ring[i]);
6667 }
6668 
6669 /**
6670  * ixgbe_free_rx_resources - Free Rx Resources
6671  * @rx_ring: ring to clean the resources from
6672  *
6673  * Free all receive software resources
6674  **/
6675 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
6676 {
6677 	ixgbe_clean_rx_ring(rx_ring);
6678 
6679 	rx_ring->xdp_prog = NULL;
6680 	xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
6681 	vfree(rx_ring->rx_buffer_info);
6682 	rx_ring->rx_buffer_info = NULL;
6683 
6684 	/* if not set, then don't free */
6685 	if (!rx_ring->desc)
6686 		return;
6687 
6688 	dma_free_coherent(rx_ring->dev, rx_ring->size,
6689 			  rx_ring->desc, rx_ring->dma);
6690 
6691 	rx_ring->desc = NULL;
6692 }
6693 
6694 /**
6695  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
6696  * @adapter: board private structure
6697  *
6698  * Free all receive software resources
6699  **/
6700 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
6701 {
6702 	int i;
6703 
6704 #ifdef IXGBE_FCOE
6705 	ixgbe_free_fcoe_ddp_resources(adapter);
6706 
6707 #endif
6708 	for (i = 0; i < adapter->num_rx_queues; i++)
6709 		if (adapter->rx_ring[i]->desc)
6710 			ixgbe_free_rx_resources(adapter->rx_ring[i]);
6711 }
6712 
6713 /**
6714  * ixgbe_change_mtu - Change the Maximum Transfer Unit
6715  * @netdev: network interface device structure
6716  * @new_mtu: new value for maximum frame size
6717  *
6718  * Returns 0 on success, negative on failure
6719  **/
6720 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
6721 {
6722 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
6723 
6724 	if (adapter->xdp_prog) {
6725 		int new_frame_size = new_mtu + ETH_HLEN + ETH_FCS_LEN +
6726 				     VLAN_HLEN;
6727 		int i;
6728 
6729 		for (i = 0; i < adapter->num_rx_queues; i++) {
6730 			struct ixgbe_ring *ring = adapter->rx_ring[i];
6731 
6732 			if (new_frame_size > ixgbe_rx_bufsz(ring)) {
6733 				e_warn(probe, "Requested MTU size is not supported with XDP\n");
6734 				return -EINVAL;
6735 			}
6736 		}
6737 	}
6738 
6739 	/*
6740 	 * For 82599EB we cannot allow legacy VFs to enable their receive
6741 	 * paths when MTU greater than 1500 is configured.  So display a
6742 	 * warning that legacy VFs will be disabled.
6743 	 */
6744 	if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
6745 	    (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
6746 	    (new_mtu > ETH_DATA_LEN))
6747 		e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
6748 
6749 	netdev_dbg(netdev, "changing MTU from %d to %d\n",
6750 		   netdev->mtu, new_mtu);
6751 
6752 	/* must set new MTU before calling down or up */
6753 	netdev->mtu = new_mtu;
6754 
6755 	if (netif_running(netdev))
6756 		ixgbe_reinit_locked(adapter);
6757 
6758 	return 0;
6759 }
6760 
6761 /**
6762  * ixgbe_open - Called when a network interface is made active
6763  * @netdev: network interface device structure
6764  *
6765  * Returns 0 on success, negative value on failure
6766  *
6767  * The open entry point is called when a network interface is made
6768  * active by the system (IFF_UP).  At this point all resources needed
6769  * for transmit and receive operations are allocated, the interrupt
6770  * handler is registered with the OS, the watchdog timer is started,
6771  * and the stack is notified that the interface is ready.
6772  **/
6773 int ixgbe_open(struct net_device *netdev)
6774 {
6775 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
6776 	struct ixgbe_hw *hw = &adapter->hw;
6777 	int err, queues;
6778 
6779 	/* disallow open during test */
6780 	if (test_bit(__IXGBE_TESTING, &adapter->state))
6781 		return -EBUSY;
6782 
6783 	netif_carrier_off(netdev);
6784 
6785 	/* allocate transmit descriptors */
6786 	err = ixgbe_setup_all_tx_resources(adapter);
6787 	if (err)
6788 		goto err_setup_tx;
6789 
6790 	/* allocate receive descriptors */
6791 	err = ixgbe_setup_all_rx_resources(adapter);
6792 	if (err)
6793 		goto err_setup_rx;
6794 
6795 	ixgbe_configure(adapter);
6796 
6797 	err = ixgbe_request_irq(adapter);
6798 	if (err)
6799 		goto err_req_irq;
6800 
6801 	/* Notify the stack of the actual queue counts. */
6802 	queues = adapter->num_tx_queues;
6803 	err = netif_set_real_num_tx_queues(netdev, queues);
6804 	if (err)
6805 		goto err_set_queues;
6806 
6807 	queues = adapter->num_rx_queues;
6808 	err = netif_set_real_num_rx_queues(netdev, queues);
6809 	if (err)
6810 		goto err_set_queues;
6811 
6812 	ixgbe_ptp_init(adapter);
6813 
6814 	ixgbe_up_complete(adapter);
6815 
6816 	udp_tunnel_nic_reset_ntf(netdev);
6817 
6818 	return 0;
6819 
6820 err_set_queues:
6821 	ixgbe_free_irq(adapter);
6822 err_req_irq:
6823 	ixgbe_free_all_rx_resources(adapter);
6824 	if (hw->phy.ops.set_phy_power && !adapter->wol)
6825 		hw->phy.ops.set_phy_power(&adapter->hw, false);
6826 err_setup_rx:
6827 	ixgbe_free_all_tx_resources(adapter);
6828 err_setup_tx:
6829 	ixgbe_reset(adapter);
6830 
6831 	return err;
6832 }
6833 
6834 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
6835 {
6836 	ixgbe_ptp_suspend(adapter);
6837 
6838 	if (adapter->hw.phy.ops.enter_lplu) {
6839 		adapter->hw.phy.reset_disable = true;
6840 		ixgbe_down(adapter);
6841 		adapter->hw.phy.ops.enter_lplu(&adapter->hw);
6842 		adapter->hw.phy.reset_disable = false;
6843 	} else {
6844 		ixgbe_down(adapter);
6845 	}
6846 
6847 	ixgbe_free_irq(adapter);
6848 
6849 	ixgbe_free_all_tx_resources(adapter);
6850 	ixgbe_free_all_rx_resources(adapter);
6851 }
6852 
6853 /**
6854  * ixgbe_close - Disables a network interface
6855  * @netdev: network interface device structure
6856  *
6857  * Returns 0, this is not allowed to fail
6858  *
6859  * The close entry point is called when an interface is de-activated
6860  * by the OS.  The hardware is still under the drivers control, but
6861  * needs to be disabled.  A global MAC reset is issued to stop the
6862  * hardware, and all transmit and receive resources are freed.
6863  **/
6864 int ixgbe_close(struct net_device *netdev)
6865 {
6866 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
6867 
6868 	ixgbe_ptp_stop(adapter);
6869 
6870 	if (netif_device_present(netdev))
6871 		ixgbe_close_suspend(adapter);
6872 
6873 	ixgbe_fdir_filter_exit(adapter);
6874 
6875 	ixgbe_release_hw_control(adapter);
6876 
6877 	return 0;
6878 }
6879 
6880 static int __maybe_unused ixgbe_resume(struct device *dev_d)
6881 {
6882 	struct pci_dev *pdev = to_pci_dev(dev_d);
6883 	struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6884 	struct net_device *netdev = adapter->netdev;
6885 	u32 err;
6886 
6887 	adapter->hw.hw_addr = adapter->io_addr;
6888 
6889 	smp_mb__before_atomic();
6890 	clear_bit(__IXGBE_DISABLED, &adapter->state);
6891 	pci_set_master(pdev);
6892 
6893 	device_wakeup_disable(dev_d);
6894 
6895 	ixgbe_reset(adapter);
6896 
6897 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6898 
6899 	rtnl_lock();
6900 	err = ixgbe_init_interrupt_scheme(adapter);
6901 	if (!err && netif_running(netdev))
6902 		err = ixgbe_open(netdev);
6903 
6904 
6905 	if (!err)
6906 		netif_device_attach(netdev);
6907 	rtnl_unlock();
6908 
6909 	return err;
6910 }
6911 
6912 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
6913 {
6914 	struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6915 	struct net_device *netdev = adapter->netdev;
6916 	struct ixgbe_hw *hw = &adapter->hw;
6917 	u32 ctrl;
6918 	u32 wufc = adapter->wol;
6919 
6920 	rtnl_lock();
6921 	netif_device_detach(netdev);
6922 
6923 	if (netif_running(netdev))
6924 		ixgbe_close_suspend(adapter);
6925 
6926 	ixgbe_clear_interrupt_scheme(adapter);
6927 	rtnl_unlock();
6928 
6929 	if (hw->mac.ops.stop_link_on_d3)
6930 		hw->mac.ops.stop_link_on_d3(hw);
6931 
6932 	if (wufc) {
6933 		u32 fctrl;
6934 
6935 		ixgbe_set_rx_mode(netdev);
6936 
6937 		/* enable the optics for 82599 SFP+ fiber as we can WoL */
6938 		if (hw->mac.ops.enable_tx_laser)
6939 			hw->mac.ops.enable_tx_laser(hw);
6940 
6941 		/* enable the reception of multicast packets */
6942 		fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6943 		fctrl |= IXGBE_FCTRL_MPE;
6944 		IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
6945 
6946 		ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
6947 		ctrl |= IXGBE_CTRL_GIO_DIS;
6948 		IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
6949 
6950 		IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
6951 	} else {
6952 		IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
6953 		IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
6954 	}
6955 
6956 	switch (hw->mac.type) {
6957 	case ixgbe_mac_82598EB:
6958 		pci_wake_from_d3(pdev, false);
6959 		break;
6960 	case ixgbe_mac_82599EB:
6961 	case ixgbe_mac_X540:
6962 	case ixgbe_mac_X550:
6963 	case ixgbe_mac_X550EM_x:
6964 	case ixgbe_mac_x550em_a:
6965 		pci_wake_from_d3(pdev, !!wufc);
6966 		break;
6967 	default:
6968 		break;
6969 	}
6970 
6971 	*enable_wake = !!wufc;
6972 	if (hw->phy.ops.set_phy_power && !*enable_wake)
6973 		hw->phy.ops.set_phy_power(hw, false);
6974 
6975 	ixgbe_release_hw_control(adapter);
6976 
6977 	if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
6978 		pci_disable_device(pdev);
6979 
6980 	return 0;
6981 }
6982 
6983 static int __maybe_unused ixgbe_suspend(struct device *dev_d)
6984 {
6985 	struct pci_dev *pdev = to_pci_dev(dev_d);
6986 	int retval;
6987 	bool wake;
6988 
6989 	retval = __ixgbe_shutdown(pdev, &wake);
6990 
6991 	device_set_wakeup_enable(dev_d, wake);
6992 
6993 	return retval;
6994 }
6995 
6996 static void ixgbe_shutdown(struct pci_dev *pdev)
6997 {
6998 	bool wake;
6999 
7000 	__ixgbe_shutdown(pdev, &wake);
7001 
7002 	if (system_state == SYSTEM_POWER_OFF) {
7003 		pci_wake_from_d3(pdev, wake);
7004 		pci_set_power_state(pdev, PCI_D3hot);
7005 	}
7006 }
7007 
7008 /**
7009  * ixgbe_update_stats - Update the board statistics counters.
7010  * @adapter: board private structure
7011  **/
7012 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
7013 {
7014 	struct net_device *netdev = adapter->netdev;
7015 	struct ixgbe_hw *hw = &adapter->hw;
7016 	struct ixgbe_hw_stats *hwstats = &adapter->stats;
7017 	u64 total_mpc = 0;
7018 	u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
7019 	u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
7020 	u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
7021 	u64 alloc_rx_page = 0;
7022 	u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
7023 
7024 	if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7025 	    test_bit(__IXGBE_RESETTING, &adapter->state))
7026 		return;
7027 
7028 	if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
7029 		u64 rsc_count = 0;
7030 		u64 rsc_flush = 0;
7031 		for (i = 0; i < adapter->num_rx_queues; i++) {
7032 			rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
7033 			rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
7034 		}
7035 		adapter->rsc_total_count = rsc_count;
7036 		adapter->rsc_total_flush = rsc_flush;
7037 	}
7038 
7039 	for (i = 0; i < adapter->num_rx_queues; i++) {
7040 		struct ixgbe_ring *rx_ring = READ_ONCE(adapter->rx_ring[i]);
7041 
7042 		if (!rx_ring)
7043 			continue;
7044 		non_eop_descs += rx_ring->rx_stats.non_eop_descs;
7045 		alloc_rx_page += rx_ring->rx_stats.alloc_rx_page;
7046 		alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
7047 		alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
7048 		hw_csum_rx_error += rx_ring->rx_stats.csum_err;
7049 		bytes += rx_ring->stats.bytes;
7050 		packets += rx_ring->stats.packets;
7051 	}
7052 	adapter->non_eop_descs = non_eop_descs;
7053 	adapter->alloc_rx_page = alloc_rx_page;
7054 	adapter->alloc_rx_page_failed = alloc_rx_page_failed;
7055 	adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
7056 	adapter->hw_csum_rx_error = hw_csum_rx_error;
7057 	netdev->stats.rx_bytes = bytes;
7058 	netdev->stats.rx_packets = packets;
7059 
7060 	bytes = 0;
7061 	packets = 0;
7062 	/* gather some stats to the adapter struct that are per queue */
7063 	for (i = 0; i < adapter->num_tx_queues; i++) {
7064 		struct ixgbe_ring *tx_ring = READ_ONCE(adapter->tx_ring[i]);
7065 
7066 		if (!tx_ring)
7067 			continue;
7068 		restart_queue += tx_ring->tx_stats.restart_queue;
7069 		tx_busy += tx_ring->tx_stats.tx_busy;
7070 		bytes += tx_ring->stats.bytes;
7071 		packets += tx_ring->stats.packets;
7072 	}
7073 	for (i = 0; i < adapter->num_xdp_queues; i++) {
7074 		struct ixgbe_ring *xdp_ring = READ_ONCE(adapter->xdp_ring[i]);
7075 
7076 		if (!xdp_ring)
7077 			continue;
7078 		restart_queue += xdp_ring->tx_stats.restart_queue;
7079 		tx_busy += xdp_ring->tx_stats.tx_busy;
7080 		bytes += xdp_ring->stats.bytes;
7081 		packets += xdp_ring->stats.packets;
7082 	}
7083 	adapter->restart_queue = restart_queue;
7084 	adapter->tx_busy = tx_busy;
7085 	netdev->stats.tx_bytes = bytes;
7086 	netdev->stats.tx_packets = packets;
7087 
7088 	hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
7089 
7090 	/* 8 register reads */
7091 	for (i = 0; i < 8; i++) {
7092 		/* for packet buffers not used, the register should read 0 */
7093 		mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
7094 		missed_rx += mpc;
7095 		hwstats->mpc[i] += mpc;
7096 		total_mpc += hwstats->mpc[i];
7097 		hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
7098 		hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
7099 		switch (hw->mac.type) {
7100 		case ixgbe_mac_82598EB:
7101 			hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
7102 			hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
7103 			hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7104 			hwstats->pxonrxc[i] +=
7105 				IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
7106 			break;
7107 		case ixgbe_mac_82599EB:
7108 		case ixgbe_mac_X540:
7109 		case ixgbe_mac_X550:
7110 		case ixgbe_mac_X550EM_x:
7111 		case ixgbe_mac_x550em_a:
7112 			hwstats->pxonrxc[i] +=
7113 				IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
7114 			break;
7115 		default:
7116 			break;
7117 		}
7118 	}
7119 
7120 	/*16 register reads */
7121 	for (i = 0; i < 16; i++) {
7122 		hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
7123 		hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
7124 		if ((hw->mac.type == ixgbe_mac_82599EB) ||
7125 		    (hw->mac.type == ixgbe_mac_X540) ||
7126 		    (hw->mac.type == ixgbe_mac_X550) ||
7127 		    (hw->mac.type == ixgbe_mac_X550EM_x) ||
7128 		    (hw->mac.type == ixgbe_mac_x550em_a)) {
7129 			hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
7130 			IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
7131 			hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
7132 			IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
7133 		}
7134 	}
7135 
7136 	hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
7137 	/* work around hardware counting issue */
7138 	hwstats->gprc -= missed_rx;
7139 
7140 	ixgbe_update_xoff_received(adapter);
7141 
7142 	/* 82598 hardware only has a 32 bit counter in the high register */
7143 	switch (hw->mac.type) {
7144 	case ixgbe_mac_82598EB:
7145 		hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
7146 		hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
7147 		hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
7148 		hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
7149 		break;
7150 	case ixgbe_mac_X540:
7151 	case ixgbe_mac_X550:
7152 	case ixgbe_mac_X550EM_x:
7153 	case ixgbe_mac_x550em_a:
7154 		/* OS2BMC stats are X540 and later */
7155 		hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
7156 		hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
7157 		hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
7158 		hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
7159 		fallthrough;
7160 	case ixgbe_mac_82599EB:
7161 		for (i = 0; i < 16; i++)
7162 			adapter->hw_rx_no_dma_resources +=
7163 					     IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7164 		hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
7165 		IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7166 		hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
7167 		IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7168 		hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
7169 		IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7170 		hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7171 		hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
7172 		hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
7173 #ifdef IXGBE_FCOE
7174 		hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
7175 		hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
7176 		hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
7177 		hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
7178 		hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
7179 		hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7180 		/* Add up per cpu counters for total ddp aloc fail */
7181 		if (adapter->fcoe.ddp_pool) {
7182 			struct ixgbe_fcoe *fcoe = &adapter->fcoe;
7183 			struct ixgbe_fcoe_ddp_pool *ddp_pool;
7184 			unsigned int cpu;
7185 			u64 noddp = 0, noddp_ext_buff = 0;
7186 			for_each_possible_cpu(cpu) {
7187 				ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
7188 				noddp += ddp_pool->noddp;
7189 				noddp_ext_buff += ddp_pool->noddp_ext_buff;
7190 			}
7191 			hwstats->fcoe_noddp = noddp;
7192 			hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7193 		}
7194 #endif /* IXGBE_FCOE */
7195 		break;
7196 	default:
7197 		break;
7198 	}
7199 	bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7200 	hwstats->bprc += bprc;
7201 	hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
7202 	if (hw->mac.type == ixgbe_mac_82598EB)
7203 		hwstats->mprc -= bprc;
7204 	hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
7205 	hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
7206 	hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
7207 	hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
7208 	hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
7209 	hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
7210 	hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
7211 	hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
7212 	lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7213 	hwstats->lxontxc += lxon;
7214 	lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7215 	hwstats->lxofftxc += lxoff;
7216 	hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
7217 	hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
7218 	/*
7219 	 * 82598 errata - tx of flow control packets is included in tx counters
7220 	 */
7221 	xon_off_tot = lxon + lxoff;
7222 	hwstats->gptc -= xon_off_tot;
7223 	hwstats->mptc -= xon_off_tot;
7224 	hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
7225 	hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
7226 	hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
7227 	hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
7228 	hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
7229 	hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
7230 	hwstats->ptc64 -= xon_off_tot;
7231 	hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
7232 	hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
7233 	hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
7234 	hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
7235 	hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
7236 	hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
7237 
7238 	/* Fill out the OS statistics structure */
7239 	netdev->stats.multicast = hwstats->mprc;
7240 
7241 	/* Rx Errors */
7242 	netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
7243 	netdev->stats.rx_dropped = 0;
7244 	netdev->stats.rx_length_errors = hwstats->rlec;
7245 	netdev->stats.rx_crc_errors = hwstats->crcerrs;
7246 	netdev->stats.rx_missed_errors = total_mpc;
7247 }
7248 
7249 /**
7250  * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
7251  * @adapter: pointer to the device adapter structure
7252  **/
7253 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
7254 {
7255 	struct ixgbe_hw *hw = &adapter->hw;
7256 	int i;
7257 
7258 	if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
7259 		return;
7260 
7261 	adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
7262 
7263 	/* if interface is down do nothing */
7264 	if (test_bit(__IXGBE_DOWN, &adapter->state))
7265 		return;
7266 
7267 	/* do nothing if we are not using signature filters */
7268 	if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
7269 		return;
7270 
7271 	adapter->fdir_overflow++;
7272 
7273 	if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
7274 		for (i = 0; i < adapter->num_tx_queues; i++)
7275 			set_bit(__IXGBE_TX_FDIR_INIT_DONE,
7276 				&(adapter->tx_ring[i]->state));
7277 		for (i = 0; i < adapter->num_xdp_queues; i++)
7278 			set_bit(__IXGBE_TX_FDIR_INIT_DONE,
7279 				&adapter->xdp_ring[i]->state);
7280 		/* re-enable flow director interrupts */
7281 		IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
7282 	} else {
7283 		e_err(probe, "failed to finish FDIR re-initialization, "
7284 		      "ignored adding FDIR ATR filters\n");
7285 	}
7286 }
7287 
7288 /**
7289  * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
7290  * @adapter: pointer to the device adapter structure
7291  *
7292  * This function serves two purposes.  First it strobes the interrupt lines
7293  * in order to make certain interrupts are occurring.  Secondly it sets the
7294  * bits needed to check for TX hangs.  As a result we should immediately
7295  * determine if a hang has occurred.
7296  */
7297 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
7298 {
7299 	struct ixgbe_hw *hw = &adapter->hw;
7300 	u64 eics = 0;
7301 	int i;
7302 
7303 	/* If we're down, removing or resetting, just bail */
7304 	if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7305 	    test_bit(__IXGBE_REMOVING, &adapter->state) ||
7306 	    test_bit(__IXGBE_RESETTING, &adapter->state))
7307 		return;
7308 
7309 	/* Force detection of hung controller */
7310 	if (netif_carrier_ok(adapter->netdev)) {
7311 		for (i = 0; i < adapter->num_tx_queues; i++)
7312 			set_check_for_tx_hang(adapter->tx_ring[i]);
7313 		for (i = 0; i < adapter->num_xdp_queues; i++)
7314 			set_check_for_tx_hang(adapter->xdp_ring[i]);
7315 	}
7316 
7317 	if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7318 		/*
7319 		 * for legacy and MSI interrupts don't set any bits
7320 		 * that are enabled for EIAM, because this operation
7321 		 * would set *both* EIMS and EICS for any bit in EIAM
7322 		 */
7323 		IXGBE_WRITE_REG(hw, IXGBE_EICS,
7324 			(IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
7325 	} else {
7326 		/* get one bit for every active tx/rx interrupt vector */
7327 		for (i = 0; i < adapter->num_q_vectors; i++) {
7328 			struct ixgbe_q_vector *qv = adapter->q_vector[i];
7329 			if (qv->rx.ring || qv->tx.ring)
7330 				eics |= BIT_ULL(i);
7331 		}
7332 	}
7333 
7334 	/* Cause software interrupt to ensure rings are cleaned */
7335 	ixgbe_irq_rearm_queues(adapter, eics);
7336 }
7337 
7338 /**
7339  * ixgbe_watchdog_update_link - update the link status
7340  * @adapter: pointer to the device adapter structure
7341  **/
7342 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
7343 {
7344 	struct ixgbe_hw *hw = &adapter->hw;
7345 	u32 link_speed = adapter->link_speed;
7346 	bool link_up = adapter->link_up;
7347 	bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
7348 
7349 	if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
7350 		return;
7351 
7352 	if (hw->mac.ops.check_link) {
7353 		hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
7354 	} else {
7355 		/* always assume link is up, if no check link function */
7356 		link_speed = IXGBE_LINK_SPEED_10GB_FULL;
7357 		link_up = true;
7358 	}
7359 
7360 	if (adapter->ixgbe_ieee_pfc)
7361 		pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
7362 
7363 	if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
7364 		hw->mac.ops.fc_enable(hw);
7365 		ixgbe_set_rx_drop_en(adapter);
7366 	}
7367 
7368 	if (link_up ||
7369 	    time_after(jiffies, (adapter->link_check_timeout +
7370 				 IXGBE_TRY_LINK_TIMEOUT))) {
7371 		adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
7372 		IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
7373 		IXGBE_WRITE_FLUSH(hw);
7374 	}
7375 
7376 	adapter->link_up = link_up;
7377 	adapter->link_speed = link_speed;
7378 }
7379 
7380 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
7381 {
7382 #ifdef CONFIG_IXGBE_DCB
7383 	struct net_device *netdev = adapter->netdev;
7384 	struct dcb_app app = {
7385 			      .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
7386 			      .protocol = 0,
7387 			     };
7388 	u8 up = 0;
7389 
7390 	if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
7391 		up = dcb_ieee_getapp_mask(netdev, &app);
7392 
7393 	adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
7394 #endif
7395 }
7396 
7397 /**
7398  * ixgbe_watchdog_link_is_up - update netif_carrier status and
7399  *                             print link up message
7400  * @adapter: pointer to the device adapter structure
7401  **/
7402 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
7403 {
7404 	struct net_device *netdev = adapter->netdev;
7405 	struct ixgbe_hw *hw = &adapter->hw;
7406 	u32 link_speed = adapter->link_speed;
7407 	const char *speed_str;
7408 	bool flow_rx, flow_tx;
7409 
7410 	/* only continue if link was previously down */
7411 	if (netif_carrier_ok(netdev))
7412 		return;
7413 
7414 	adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7415 
7416 	switch (hw->mac.type) {
7417 	case ixgbe_mac_82598EB: {
7418 		u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
7419 		u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
7420 		flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
7421 		flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
7422 	}
7423 		break;
7424 	case ixgbe_mac_X540:
7425 	case ixgbe_mac_X550:
7426 	case ixgbe_mac_X550EM_x:
7427 	case ixgbe_mac_x550em_a:
7428 	case ixgbe_mac_82599EB: {
7429 		u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
7430 		u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
7431 		flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
7432 		flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
7433 	}
7434 		break;
7435 	default:
7436 		flow_tx = false;
7437 		flow_rx = false;
7438 		break;
7439 	}
7440 
7441 	adapter->last_rx_ptp_check = jiffies;
7442 
7443 	if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
7444 		ixgbe_ptp_start_cyclecounter(adapter);
7445 
7446 	switch (link_speed) {
7447 	case IXGBE_LINK_SPEED_10GB_FULL:
7448 		speed_str = "10 Gbps";
7449 		break;
7450 	case IXGBE_LINK_SPEED_5GB_FULL:
7451 		speed_str = "5 Gbps";
7452 		break;
7453 	case IXGBE_LINK_SPEED_2_5GB_FULL:
7454 		speed_str = "2.5 Gbps";
7455 		break;
7456 	case IXGBE_LINK_SPEED_1GB_FULL:
7457 		speed_str = "1 Gbps";
7458 		break;
7459 	case IXGBE_LINK_SPEED_100_FULL:
7460 		speed_str = "100 Mbps";
7461 		break;
7462 	case IXGBE_LINK_SPEED_10_FULL:
7463 		speed_str = "10 Mbps";
7464 		break;
7465 	default:
7466 		speed_str = "unknown speed";
7467 		break;
7468 	}
7469 	e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
7470 	       ((flow_rx && flow_tx) ? "RX/TX" :
7471 	       (flow_rx ? "RX" :
7472 	       (flow_tx ? "TX" : "None"))));
7473 
7474 	netif_carrier_on(netdev);
7475 	ixgbe_check_vf_rate_limit(adapter);
7476 
7477 	/* enable transmits */
7478 	netif_tx_wake_all_queues(adapter->netdev);
7479 
7480 	/* update the default user priority for VFs */
7481 	ixgbe_update_default_up(adapter);
7482 
7483 	/* ping all the active vfs to let them know link has changed */
7484 	ixgbe_ping_all_vfs(adapter);
7485 }
7486 
7487 /**
7488  * ixgbe_watchdog_link_is_down - update netif_carrier status and
7489  *                               print link down message
7490  * @adapter: pointer to the adapter structure
7491  **/
7492 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
7493 {
7494 	struct net_device *netdev = adapter->netdev;
7495 	struct ixgbe_hw *hw = &adapter->hw;
7496 
7497 	adapter->link_up = false;
7498 	adapter->link_speed = 0;
7499 
7500 	/* only continue if link was up previously */
7501 	if (!netif_carrier_ok(netdev))
7502 		return;
7503 
7504 	/* poll for SFP+ cable when link is down */
7505 	if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
7506 		adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
7507 
7508 	if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
7509 		ixgbe_ptp_start_cyclecounter(adapter);
7510 
7511 	e_info(drv, "NIC Link is Down\n");
7512 	netif_carrier_off(netdev);
7513 
7514 	/* ping all the active vfs to let them know link has changed */
7515 	ixgbe_ping_all_vfs(adapter);
7516 }
7517 
7518 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
7519 {
7520 	int i;
7521 
7522 	for (i = 0; i < adapter->num_tx_queues; i++) {
7523 		struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
7524 
7525 		if (tx_ring->next_to_use != tx_ring->next_to_clean)
7526 			return true;
7527 	}
7528 
7529 	for (i = 0; i < adapter->num_xdp_queues; i++) {
7530 		struct ixgbe_ring *ring = adapter->xdp_ring[i];
7531 
7532 		if (ring->next_to_use != ring->next_to_clean)
7533 			return true;
7534 	}
7535 
7536 	return false;
7537 }
7538 
7539 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
7540 {
7541 	struct ixgbe_hw *hw = &adapter->hw;
7542 	struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
7543 	u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
7544 
7545 	int i, j;
7546 
7547 	if (!adapter->num_vfs)
7548 		return false;
7549 
7550 	/* resetting the PF is only needed for MAC before X550 */
7551 	if (hw->mac.type >= ixgbe_mac_X550)
7552 		return false;
7553 
7554 	for (i = 0; i < adapter->num_vfs; i++) {
7555 		for (j = 0; j < q_per_pool; j++) {
7556 			u32 h, t;
7557 
7558 			h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
7559 			t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
7560 
7561 			if (h != t)
7562 				return true;
7563 		}
7564 	}
7565 
7566 	return false;
7567 }
7568 
7569 /**
7570  * ixgbe_watchdog_flush_tx - flush queues on link down
7571  * @adapter: pointer to the device adapter structure
7572  **/
7573 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
7574 {
7575 	if (!netif_carrier_ok(adapter->netdev)) {
7576 		if (ixgbe_ring_tx_pending(adapter) ||
7577 		    ixgbe_vf_tx_pending(adapter)) {
7578 			/* We've lost link, so the controller stops DMA,
7579 			 * but we've got queued Tx work that's never going
7580 			 * to get done, so reset controller to flush Tx.
7581 			 * (Do the reset outside of interrupt context).
7582 			 */
7583 			e_warn(drv, "initiating reset to clear Tx work after link loss\n");
7584 			set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
7585 		}
7586 	}
7587 }
7588 
7589 #ifdef CONFIG_PCI_IOV
7590 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
7591 {
7592 	struct ixgbe_hw *hw = &adapter->hw;
7593 	struct pci_dev *pdev = adapter->pdev;
7594 	unsigned int vf;
7595 	u32 gpc;
7596 
7597 	if (!(netif_carrier_ok(adapter->netdev)))
7598 		return;
7599 
7600 	gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
7601 	if (gpc) /* If incrementing then no need for the check below */
7602 		return;
7603 	/* Check to see if a bad DMA write target from an errant or
7604 	 * malicious VF has caused a PCIe error.  If so then we can
7605 	 * issue a VFLR to the offending VF(s) and then resume without
7606 	 * requesting a full slot reset.
7607 	 */
7608 
7609 	if (!pdev)
7610 		return;
7611 
7612 	/* check status reg for all VFs owned by this PF */
7613 	for (vf = 0; vf < adapter->num_vfs; ++vf) {
7614 		struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev;
7615 		u16 status_reg;
7616 
7617 		if (!vfdev)
7618 			continue;
7619 		pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
7620 		if (status_reg != IXGBE_FAILED_READ_CFG_WORD &&
7621 		    status_reg & PCI_STATUS_REC_MASTER_ABORT)
7622 			pcie_flr(vfdev);
7623 	}
7624 }
7625 
7626 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
7627 {
7628 	u32 ssvpc;
7629 
7630 	/* Do not perform spoof check for 82598 or if not in IOV mode */
7631 	if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7632 	    adapter->num_vfs == 0)
7633 		return;
7634 
7635 	ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
7636 
7637 	/*
7638 	 * ssvpc register is cleared on read, if zero then no
7639 	 * spoofed packets in the last interval.
7640 	 */
7641 	if (!ssvpc)
7642 		return;
7643 
7644 	e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
7645 }
7646 #else
7647 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
7648 {
7649 }
7650 
7651 static void
7652 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
7653 {
7654 }
7655 #endif /* CONFIG_PCI_IOV */
7656 
7657 
7658 /**
7659  * ixgbe_watchdog_subtask - check and bring link up
7660  * @adapter: pointer to the device adapter structure
7661  **/
7662 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
7663 {
7664 	/* if interface is down, removing or resetting, do nothing */
7665 	if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7666 	    test_bit(__IXGBE_REMOVING, &adapter->state) ||
7667 	    test_bit(__IXGBE_RESETTING, &adapter->state))
7668 		return;
7669 
7670 	ixgbe_watchdog_update_link(adapter);
7671 
7672 	if (adapter->link_up)
7673 		ixgbe_watchdog_link_is_up(adapter);
7674 	else
7675 		ixgbe_watchdog_link_is_down(adapter);
7676 
7677 	ixgbe_check_for_bad_vf(adapter);
7678 	ixgbe_spoof_check(adapter);
7679 	ixgbe_update_stats(adapter);
7680 
7681 	ixgbe_watchdog_flush_tx(adapter);
7682 }
7683 
7684 /**
7685  * ixgbe_sfp_detection_subtask - poll for SFP+ cable
7686  * @adapter: the ixgbe adapter structure
7687  **/
7688 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
7689 {
7690 	struct ixgbe_hw *hw = &adapter->hw;
7691 	s32 err;
7692 
7693 	/* not searching for SFP so there is nothing to do here */
7694 	if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
7695 	    !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7696 		return;
7697 
7698 	if (adapter->sfp_poll_time &&
7699 	    time_after(adapter->sfp_poll_time, jiffies))
7700 		return; /* If not yet time to poll for SFP */
7701 
7702 	/* someone else is in init, wait until next service event */
7703 	if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7704 		return;
7705 
7706 	adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
7707 
7708 	err = hw->phy.ops.identify_sfp(hw);
7709 	if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7710 		goto sfp_out;
7711 
7712 	if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
7713 		/* If no cable is present, then we need to reset
7714 		 * the next time we find a good cable. */
7715 		adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
7716 	}
7717 
7718 	/* exit on error */
7719 	if (err)
7720 		goto sfp_out;
7721 
7722 	/* exit if reset not needed */
7723 	if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7724 		goto sfp_out;
7725 
7726 	adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
7727 
7728 	/*
7729 	 * A module may be identified correctly, but the EEPROM may not have
7730 	 * support for that module.  setup_sfp() will fail in that case, so
7731 	 * we should not allow that module to load.
7732 	 */
7733 	if (hw->mac.type == ixgbe_mac_82598EB)
7734 		err = hw->phy.ops.reset(hw);
7735 	else
7736 		err = hw->mac.ops.setup_sfp(hw);
7737 
7738 	if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7739 		goto sfp_out;
7740 
7741 	adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
7742 	e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
7743 
7744 sfp_out:
7745 	clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7746 
7747 	if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
7748 	    (adapter->netdev->reg_state == NETREG_REGISTERED)) {
7749 		e_dev_err("failed to initialize because an unsupported "
7750 			  "SFP+ module type was detected.\n");
7751 		e_dev_err("Reload the driver after installing a "
7752 			  "supported module.\n");
7753 		unregister_netdev(adapter->netdev);
7754 	}
7755 }
7756 
7757 /**
7758  * ixgbe_sfp_link_config_subtask - set up link SFP after module install
7759  * @adapter: the ixgbe adapter structure
7760  **/
7761 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
7762 {
7763 	struct ixgbe_hw *hw = &adapter->hw;
7764 	u32 cap_speed;
7765 	u32 speed;
7766 	bool autoneg = false;
7767 
7768 	if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
7769 		return;
7770 
7771 	/* someone else is in init, wait until next service event */
7772 	if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7773 		return;
7774 
7775 	adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
7776 
7777 	hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg);
7778 
7779 	/* advertise highest capable link speed */
7780 	if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL))
7781 		speed = IXGBE_LINK_SPEED_10GB_FULL;
7782 	else
7783 		speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL |
7784 				     IXGBE_LINK_SPEED_1GB_FULL);
7785 
7786 	if (hw->mac.ops.setup_link)
7787 		hw->mac.ops.setup_link(hw, speed, true);
7788 
7789 	adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
7790 	adapter->link_check_timeout = jiffies;
7791 	clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7792 }
7793 
7794 /**
7795  * ixgbe_service_timer - Timer Call-back
7796  * @t: pointer to timer_list structure
7797  **/
7798 static void ixgbe_service_timer(struct timer_list *t)
7799 {
7800 	struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer);
7801 	unsigned long next_event_offset;
7802 
7803 	/* poll faster when waiting for link */
7804 	if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
7805 		next_event_offset = HZ / 10;
7806 	else
7807 		next_event_offset = HZ * 2;
7808 
7809 	/* Reset the timer */
7810 	mod_timer(&adapter->service_timer, next_event_offset + jiffies);
7811 
7812 	ixgbe_service_event_schedule(adapter);
7813 }
7814 
7815 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
7816 {
7817 	struct ixgbe_hw *hw = &adapter->hw;
7818 	u32 status;
7819 
7820 	if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
7821 		return;
7822 
7823 	adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
7824 
7825 	if (!hw->phy.ops.handle_lasi)
7826 		return;
7827 
7828 	status = hw->phy.ops.handle_lasi(&adapter->hw);
7829 	if (status != IXGBE_ERR_OVERTEMP)
7830 		return;
7831 
7832 	e_crit(drv, "%s\n", ixgbe_overheat_msg);
7833 }
7834 
7835 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
7836 {
7837 	if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state))
7838 		return;
7839 
7840 	rtnl_lock();
7841 	/* If we're already down, removing or resetting, just bail */
7842 	if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7843 	    test_bit(__IXGBE_REMOVING, &adapter->state) ||
7844 	    test_bit(__IXGBE_RESETTING, &adapter->state)) {
7845 		rtnl_unlock();
7846 		return;
7847 	}
7848 
7849 	ixgbe_dump(adapter);
7850 	netdev_err(adapter->netdev, "Reset adapter\n");
7851 	adapter->tx_timeout_count++;
7852 
7853 	ixgbe_reinit_locked(adapter);
7854 	rtnl_unlock();
7855 }
7856 
7857 /**
7858  * ixgbe_check_fw_error - Check firmware for errors
7859  * @adapter: the adapter private structure
7860  *
7861  * Check firmware errors in register FWSM
7862  */
7863 static bool ixgbe_check_fw_error(struct ixgbe_adapter *adapter)
7864 {
7865 	struct ixgbe_hw *hw = &adapter->hw;
7866 	u32 fwsm;
7867 
7868 	/* read fwsm.ext_err_ind register and log errors */
7869 	fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
7870 
7871 	if (fwsm & IXGBE_FWSM_EXT_ERR_IND_MASK ||
7872 	    !(fwsm & IXGBE_FWSM_FW_VAL_BIT))
7873 		e_dev_warn("Warning firmware error detected FWSM: 0x%08X\n",
7874 			   fwsm);
7875 
7876 	if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
7877 		e_dev_err("Firmware recovery mode detected. Limiting functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware recovery mode.\n");
7878 		return true;
7879 	}
7880 
7881 	return false;
7882 }
7883 
7884 /**
7885  * ixgbe_service_task - manages and runs subtasks
7886  * @work: pointer to work_struct containing our data
7887  **/
7888 static void ixgbe_service_task(struct work_struct *work)
7889 {
7890 	struct ixgbe_adapter *adapter = container_of(work,
7891 						     struct ixgbe_adapter,
7892 						     service_task);
7893 	if (ixgbe_removed(adapter->hw.hw_addr)) {
7894 		if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
7895 			rtnl_lock();
7896 			ixgbe_down(adapter);
7897 			rtnl_unlock();
7898 		}
7899 		ixgbe_service_event_complete(adapter);
7900 		return;
7901 	}
7902 	if (ixgbe_check_fw_error(adapter)) {
7903 		if (!test_bit(__IXGBE_DOWN, &adapter->state))
7904 			unregister_netdev(adapter->netdev);
7905 		ixgbe_service_event_complete(adapter);
7906 		return;
7907 	}
7908 	ixgbe_reset_subtask(adapter);
7909 	ixgbe_phy_interrupt_subtask(adapter);
7910 	ixgbe_sfp_detection_subtask(adapter);
7911 	ixgbe_sfp_link_config_subtask(adapter);
7912 	ixgbe_check_overtemp_subtask(adapter);
7913 	ixgbe_watchdog_subtask(adapter);
7914 	ixgbe_fdir_reinit_subtask(adapter);
7915 	ixgbe_check_hang_subtask(adapter);
7916 
7917 	if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
7918 		ixgbe_ptp_overflow_check(adapter);
7919 		if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER)
7920 			ixgbe_ptp_rx_hang(adapter);
7921 		ixgbe_ptp_tx_hang(adapter);
7922 	}
7923 
7924 	ixgbe_service_event_complete(adapter);
7925 }
7926 
7927 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
7928 		     struct ixgbe_tx_buffer *first,
7929 		     u8 *hdr_len,
7930 		     struct ixgbe_ipsec_tx_data *itd)
7931 {
7932 	u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
7933 	struct sk_buff *skb = first->skb;
7934 	union {
7935 		struct iphdr *v4;
7936 		struct ipv6hdr *v6;
7937 		unsigned char *hdr;
7938 	} ip;
7939 	union {
7940 		struct tcphdr *tcp;
7941 		struct udphdr *udp;
7942 		unsigned char *hdr;
7943 	} l4;
7944 	u32 paylen, l4_offset;
7945 	u32 fceof_saidx = 0;
7946 	int err;
7947 
7948 	if (skb->ip_summed != CHECKSUM_PARTIAL)
7949 		return 0;
7950 
7951 	if (!skb_is_gso(skb))
7952 		return 0;
7953 
7954 	err = skb_cow_head(skb, 0);
7955 	if (err < 0)
7956 		return err;
7957 
7958 	if (eth_p_mpls(first->protocol))
7959 		ip.hdr = skb_inner_network_header(skb);
7960 	else
7961 		ip.hdr = skb_network_header(skb);
7962 	l4.hdr = skb_checksum_start(skb);
7963 
7964 	/* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
7965 	type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ?
7966 		      IXGBE_ADVTXD_TUCMD_L4T_UDP : IXGBE_ADVTXD_TUCMD_L4T_TCP;
7967 
7968 	/* initialize outer IP header fields */
7969 	if (ip.v4->version == 4) {
7970 		unsigned char *csum_start = skb_checksum_start(skb);
7971 		unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
7972 		int len = csum_start - trans_start;
7973 
7974 		/* IP header will have to cancel out any data that
7975 		 * is not a part of the outer IP header, so set to
7976 		 * a reverse csum if needed, else init check to 0.
7977 		 */
7978 		ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ?
7979 					   csum_fold(csum_partial(trans_start,
7980 								  len, 0)) : 0;
7981 		type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
7982 
7983 		ip.v4->tot_len = 0;
7984 		first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7985 				   IXGBE_TX_FLAGS_CSUM |
7986 				   IXGBE_TX_FLAGS_IPV4;
7987 	} else {
7988 		ip.v6->payload_len = 0;
7989 		first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7990 				   IXGBE_TX_FLAGS_CSUM;
7991 	}
7992 
7993 	/* determine offset of inner transport header */
7994 	l4_offset = l4.hdr - skb->data;
7995 
7996 	/* remove payload length from inner checksum */
7997 	paylen = skb->len - l4_offset;
7998 
7999 	if (type_tucmd & IXGBE_ADVTXD_TUCMD_L4T_TCP) {
8000 		/* compute length of segmentation header */
8001 		*hdr_len = (l4.tcp->doff * 4) + l4_offset;
8002 		csum_replace_by_diff(&l4.tcp->check,
8003 				     (__force __wsum)htonl(paylen));
8004 	} else {
8005 		/* compute length of segmentation header */
8006 		*hdr_len = sizeof(*l4.udp) + l4_offset;
8007 		csum_replace_by_diff(&l4.udp->check,
8008 				     (__force __wsum)htonl(paylen));
8009 	}
8010 
8011 	/* update gso size and bytecount with header size */
8012 	first->gso_segs = skb_shinfo(skb)->gso_segs;
8013 	first->bytecount += (first->gso_segs - 1) * *hdr_len;
8014 
8015 	/* mss_l4len_id: use 0 as index for TSO */
8016 	mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT;
8017 	mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
8018 
8019 	fceof_saidx |= itd->sa_idx;
8020 	type_tucmd |= itd->flags | itd->trailer_len;
8021 
8022 	/* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
8023 	vlan_macip_lens = l4.hdr - ip.hdr;
8024 	vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT;
8025 	vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
8026 
8027 	ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd,
8028 			  mss_l4len_idx);
8029 
8030 	return 1;
8031 }
8032 
8033 static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb)
8034 {
8035 	unsigned int offset = 0;
8036 
8037 	ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL);
8038 
8039 	return offset == skb_checksum_start_offset(skb);
8040 }
8041 
8042 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
8043 			  struct ixgbe_tx_buffer *first,
8044 			  struct ixgbe_ipsec_tx_data *itd)
8045 {
8046 	struct sk_buff *skb = first->skb;
8047 	u32 vlan_macip_lens = 0;
8048 	u32 fceof_saidx = 0;
8049 	u32 type_tucmd = 0;
8050 
8051 	if (skb->ip_summed != CHECKSUM_PARTIAL) {
8052 csum_failed:
8053 		if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN |
8054 					 IXGBE_TX_FLAGS_CC)))
8055 			return;
8056 		goto no_csum;
8057 	}
8058 
8059 	switch (skb->csum_offset) {
8060 	case offsetof(struct tcphdr, check):
8061 		type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
8062 		fallthrough;
8063 	case offsetof(struct udphdr, check):
8064 		break;
8065 	case offsetof(struct sctphdr, checksum):
8066 		/* validate that this is actually an SCTP request */
8067 		if (((first->protocol == htons(ETH_P_IP)) &&
8068 		     (ip_hdr(skb)->protocol == IPPROTO_SCTP)) ||
8069 		    ((first->protocol == htons(ETH_P_IPV6)) &&
8070 		     ixgbe_ipv6_csum_is_sctp(skb))) {
8071 			type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP;
8072 			break;
8073 		}
8074 		fallthrough;
8075 	default:
8076 		skb_checksum_help(skb);
8077 		goto csum_failed;
8078 	}
8079 
8080 	/* update TX checksum flag */
8081 	first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
8082 	vlan_macip_lens = skb_checksum_start_offset(skb) -
8083 			  skb_network_offset(skb);
8084 no_csum:
8085 	/* vlan_macip_lens: MACLEN, VLAN tag */
8086 	vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
8087 	vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
8088 
8089 	fceof_saidx |= itd->sa_idx;
8090 	type_tucmd |= itd->flags | itd->trailer_len;
8091 
8092 	ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0);
8093 }
8094 
8095 #define IXGBE_SET_FLAG(_input, _flag, _result) \
8096 	((_flag <= _result) ? \
8097 	 ((u32)(_input & _flag) * (_result / _flag)) : \
8098 	 ((u32)(_input & _flag) / (_flag / _result)))
8099 
8100 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
8101 {
8102 	/* set type for advanced descriptor with frame checksum insertion */
8103 	u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
8104 		       IXGBE_ADVTXD_DCMD_DEXT |
8105 		       IXGBE_ADVTXD_DCMD_IFCS;
8106 
8107 	/* set HW vlan bit if vlan is present */
8108 	cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
8109 				   IXGBE_ADVTXD_DCMD_VLE);
8110 
8111 	/* set segmentation enable bits for TSO/FSO */
8112 	cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
8113 				   IXGBE_ADVTXD_DCMD_TSE);
8114 
8115 	/* set timestamp bit if present */
8116 	cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
8117 				   IXGBE_ADVTXD_MAC_TSTAMP);
8118 
8119 	/* insert frame checksum */
8120 	cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
8121 
8122 	return cmd_type;
8123 }
8124 
8125 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
8126 				   u32 tx_flags, unsigned int paylen)
8127 {
8128 	u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
8129 
8130 	/* enable L4 checksum for TSO and TX checksum offload */
8131 	olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8132 					IXGBE_TX_FLAGS_CSUM,
8133 					IXGBE_ADVTXD_POPTS_TXSM);
8134 
8135 	/* enable IPv4 checksum for TSO */
8136 	olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8137 					IXGBE_TX_FLAGS_IPV4,
8138 					IXGBE_ADVTXD_POPTS_IXSM);
8139 
8140 	/* enable IPsec */
8141 	olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8142 					IXGBE_TX_FLAGS_IPSEC,
8143 					IXGBE_ADVTXD_POPTS_IPSEC);
8144 
8145 	/*
8146 	 * Check Context must be set if Tx switch is enabled, which it
8147 	 * always is for case where virtual functions are running
8148 	 */
8149 	olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8150 					IXGBE_TX_FLAGS_CC,
8151 					IXGBE_ADVTXD_CC);
8152 
8153 	tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
8154 }
8155 
8156 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
8157 {
8158 	netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
8159 
8160 	/* Herbert's original patch had:
8161 	 *  smp_mb__after_netif_stop_queue();
8162 	 * but since that doesn't exist yet, just open code it.
8163 	 */
8164 	smp_mb();
8165 
8166 	/* We need to check again in a case another CPU has just
8167 	 * made room available.
8168 	 */
8169 	if (likely(ixgbe_desc_unused(tx_ring) < size))
8170 		return -EBUSY;
8171 
8172 	/* A reprieve! - use start_queue because it doesn't call schedule */
8173 	netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
8174 	++tx_ring->tx_stats.restart_queue;
8175 	return 0;
8176 }
8177 
8178 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
8179 {
8180 	if (likely(ixgbe_desc_unused(tx_ring) >= size))
8181 		return 0;
8182 
8183 	return __ixgbe_maybe_stop_tx(tx_ring, size);
8184 }
8185 
8186 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring,
8187 			struct ixgbe_tx_buffer *first,
8188 			const u8 hdr_len)
8189 {
8190 	struct sk_buff *skb = first->skb;
8191 	struct ixgbe_tx_buffer *tx_buffer;
8192 	union ixgbe_adv_tx_desc *tx_desc;
8193 	skb_frag_t *frag;
8194 	dma_addr_t dma;
8195 	unsigned int data_len, size;
8196 	u32 tx_flags = first->tx_flags;
8197 	u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
8198 	u16 i = tx_ring->next_to_use;
8199 
8200 	tx_desc = IXGBE_TX_DESC(tx_ring, i);
8201 
8202 	ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
8203 
8204 	size = skb_headlen(skb);
8205 	data_len = skb->data_len;
8206 
8207 #ifdef IXGBE_FCOE
8208 	if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
8209 		if (data_len < sizeof(struct fcoe_crc_eof)) {
8210 			size -= sizeof(struct fcoe_crc_eof) - data_len;
8211 			data_len = 0;
8212 		} else {
8213 			data_len -= sizeof(struct fcoe_crc_eof);
8214 		}
8215 	}
8216 
8217 #endif
8218 	dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8219 
8220 	tx_buffer = first;
8221 
8222 	for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
8223 		if (dma_mapping_error(tx_ring->dev, dma))
8224 			goto dma_error;
8225 
8226 		/* record length, and DMA address */
8227 		dma_unmap_len_set(tx_buffer, len, size);
8228 		dma_unmap_addr_set(tx_buffer, dma, dma);
8229 
8230 		tx_desc->read.buffer_addr = cpu_to_le64(dma);
8231 
8232 		while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
8233 			tx_desc->read.cmd_type_len =
8234 				cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
8235 
8236 			i++;
8237 			tx_desc++;
8238 			if (i == tx_ring->count) {
8239 				tx_desc = IXGBE_TX_DESC(tx_ring, 0);
8240 				i = 0;
8241 			}
8242 			tx_desc->read.olinfo_status = 0;
8243 
8244 			dma += IXGBE_MAX_DATA_PER_TXD;
8245 			size -= IXGBE_MAX_DATA_PER_TXD;
8246 
8247 			tx_desc->read.buffer_addr = cpu_to_le64(dma);
8248 		}
8249 
8250 		if (likely(!data_len))
8251 			break;
8252 
8253 		tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
8254 
8255 		i++;
8256 		tx_desc++;
8257 		if (i == tx_ring->count) {
8258 			tx_desc = IXGBE_TX_DESC(tx_ring, 0);
8259 			i = 0;
8260 		}
8261 		tx_desc->read.olinfo_status = 0;
8262 
8263 #ifdef IXGBE_FCOE
8264 		size = min_t(unsigned int, data_len, skb_frag_size(frag));
8265 #else
8266 		size = skb_frag_size(frag);
8267 #endif
8268 		data_len -= size;
8269 
8270 		dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
8271 				       DMA_TO_DEVICE);
8272 
8273 		tx_buffer = &tx_ring->tx_buffer_info[i];
8274 	}
8275 
8276 	/* write last descriptor with RS and EOP bits */
8277 	cmd_type |= size | IXGBE_TXD_CMD;
8278 	tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8279 
8280 	netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
8281 
8282 	/* set the timestamp */
8283 	first->time_stamp = jiffies;
8284 
8285 	skb_tx_timestamp(skb);
8286 
8287 	/*
8288 	 * Force memory writes to complete before letting h/w know there
8289 	 * are new descriptors to fetch.  (Only applicable for weak-ordered
8290 	 * memory model archs, such as IA-64).
8291 	 *
8292 	 * We also need this memory barrier to make certain all of the
8293 	 * status bits have been updated before next_to_watch is written.
8294 	 */
8295 	wmb();
8296 
8297 	/* set next_to_watch value indicating a packet is present */
8298 	first->next_to_watch = tx_desc;
8299 
8300 	i++;
8301 	if (i == tx_ring->count)
8302 		i = 0;
8303 
8304 	tx_ring->next_to_use = i;
8305 
8306 	ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
8307 
8308 	if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
8309 		writel(i, tx_ring->tail);
8310 	}
8311 
8312 	return 0;
8313 dma_error:
8314 	dev_err(tx_ring->dev, "TX DMA map failed\n");
8315 
8316 	/* clear dma mappings for failed tx_buffer_info map */
8317 	for (;;) {
8318 		tx_buffer = &tx_ring->tx_buffer_info[i];
8319 		if (dma_unmap_len(tx_buffer, len))
8320 			dma_unmap_page(tx_ring->dev,
8321 				       dma_unmap_addr(tx_buffer, dma),
8322 				       dma_unmap_len(tx_buffer, len),
8323 				       DMA_TO_DEVICE);
8324 		dma_unmap_len_set(tx_buffer, len, 0);
8325 		if (tx_buffer == first)
8326 			break;
8327 		if (i == 0)
8328 			i += tx_ring->count;
8329 		i--;
8330 	}
8331 
8332 	dev_kfree_skb_any(first->skb);
8333 	first->skb = NULL;
8334 
8335 	tx_ring->next_to_use = i;
8336 
8337 	return -1;
8338 }
8339 
8340 static void ixgbe_atr(struct ixgbe_ring *ring,
8341 		      struct ixgbe_tx_buffer *first)
8342 {
8343 	struct ixgbe_q_vector *q_vector = ring->q_vector;
8344 	union ixgbe_atr_hash_dword input = { .dword = 0 };
8345 	union ixgbe_atr_hash_dword common = { .dword = 0 };
8346 	union {
8347 		unsigned char *network;
8348 		struct iphdr *ipv4;
8349 		struct ipv6hdr *ipv6;
8350 	} hdr;
8351 	struct tcphdr *th;
8352 	unsigned int hlen;
8353 	struct sk_buff *skb;
8354 	__be16 vlan_id;
8355 	int l4_proto;
8356 
8357 	/* if ring doesn't have a interrupt vector, cannot perform ATR */
8358 	if (!q_vector)
8359 		return;
8360 
8361 	/* do nothing if sampling is disabled */
8362 	if (!ring->atr_sample_rate)
8363 		return;
8364 
8365 	ring->atr_count++;
8366 
8367 	/* currently only IPv4/IPv6 with TCP is supported */
8368 	if ((first->protocol != htons(ETH_P_IP)) &&
8369 	    (first->protocol != htons(ETH_P_IPV6)))
8370 		return;
8371 
8372 	/* snag network header to get L4 type and address */
8373 	skb = first->skb;
8374 	hdr.network = skb_network_header(skb);
8375 	if (unlikely(hdr.network <= skb->data))
8376 		return;
8377 	if (skb->encapsulation &&
8378 	    first->protocol == htons(ETH_P_IP) &&
8379 	    hdr.ipv4->protocol == IPPROTO_UDP) {
8380 		struct ixgbe_adapter *adapter = q_vector->adapter;
8381 
8382 		if (unlikely(skb_tail_pointer(skb) < hdr.network +
8383 			     VXLAN_HEADROOM))
8384 			return;
8385 
8386 		/* verify the port is recognized as VXLAN */
8387 		if (adapter->vxlan_port &&
8388 		    udp_hdr(skb)->dest == adapter->vxlan_port)
8389 			hdr.network = skb_inner_network_header(skb);
8390 
8391 		if (adapter->geneve_port &&
8392 		    udp_hdr(skb)->dest == adapter->geneve_port)
8393 			hdr.network = skb_inner_network_header(skb);
8394 	}
8395 
8396 	/* Make sure we have at least [minimum IPv4 header + TCP]
8397 	 * or [IPv6 header] bytes
8398 	 */
8399 	if (unlikely(skb_tail_pointer(skb) < hdr.network + 40))
8400 		return;
8401 
8402 	/* Currently only IPv4/IPv6 with TCP is supported */
8403 	switch (hdr.ipv4->version) {
8404 	case IPVERSION:
8405 		/* access ihl as u8 to avoid unaligned access on ia64 */
8406 		hlen = (hdr.network[0] & 0x0F) << 2;
8407 		l4_proto = hdr.ipv4->protocol;
8408 		break;
8409 	case 6:
8410 		hlen = hdr.network - skb->data;
8411 		l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL);
8412 		hlen -= hdr.network - skb->data;
8413 		break;
8414 	default:
8415 		return;
8416 	}
8417 
8418 	if (l4_proto != IPPROTO_TCP)
8419 		return;
8420 
8421 	if (unlikely(skb_tail_pointer(skb) < hdr.network +
8422 		     hlen + sizeof(struct tcphdr)))
8423 		return;
8424 
8425 	th = (struct tcphdr *)(hdr.network + hlen);
8426 
8427 	/* skip this packet since the socket is closing */
8428 	if (th->fin)
8429 		return;
8430 
8431 	/* sample on all syn packets or once every atr sample count */
8432 	if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
8433 		return;
8434 
8435 	/* reset sample count */
8436 	ring->atr_count = 0;
8437 
8438 	vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
8439 
8440 	/*
8441 	 * src and dst are inverted, think how the receiver sees them
8442 	 *
8443 	 * The input is broken into two sections, a non-compressed section
8444 	 * containing vm_pool, vlan_id, and flow_type.  The rest of the data
8445 	 * is XORed together and stored in the compressed dword.
8446 	 */
8447 	input.formatted.vlan_id = vlan_id;
8448 
8449 	/*
8450 	 * since src port and flex bytes occupy the same word XOR them together
8451 	 * and write the value to source port portion of compressed dword
8452 	 */
8453 	if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
8454 		common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
8455 	else
8456 		common.port.src ^= th->dest ^ first->protocol;
8457 	common.port.dst ^= th->source;
8458 
8459 	switch (hdr.ipv4->version) {
8460 	case IPVERSION:
8461 		input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
8462 		common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
8463 		break;
8464 	case 6:
8465 		input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
8466 		common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
8467 			     hdr.ipv6->saddr.s6_addr32[1] ^
8468 			     hdr.ipv6->saddr.s6_addr32[2] ^
8469 			     hdr.ipv6->saddr.s6_addr32[3] ^
8470 			     hdr.ipv6->daddr.s6_addr32[0] ^
8471 			     hdr.ipv6->daddr.s6_addr32[1] ^
8472 			     hdr.ipv6->daddr.s6_addr32[2] ^
8473 			     hdr.ipv6->daddr.s6_addr32[3];
8474 		break;
8475 	default:
8476 		break;
8477 	}
8478 
8479 	if (hdr.network != skb_network_header(skb))
8480 		input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
8481 
8482 	/* This assumes the Rx queue and Tx queue are bound to the same CPU */
8483 	ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
8484 					      input, common, ring->queue_index);
8485 }
8486 
8487 #ifdef IXGBE_FCOE
8488 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
8489 			      struct net_device *sb_dev)
8490 {
8491 	struct ixgbe_adapter *adapter;
8492 	struct ixgbe_ring_feature *f;
8493 	int txq;
8494 
8495 	if (sb_dev) {
8496 		u8 tc = netdev_get_prio_tc_map(dev, skb->priority);
8497 		struct net_device *vdev = sb_dev;
8498 
8499 		txq = vdev->tc_to_txq[tc].offset;
8500 		txq += reciprocal_scale(skb_get_hash(skb),
8501 					vdev->tc_to_txq[tc].count);
8502 
8503 		return txq;
8504 	}
8505 
8506 	/*
8507 	 * only execute the code below if protocol is FCoE
8508 	 * or FIP and we have FCoE enabled on the adapter
8509 	 */
8510 	switch (vlan_get_protocol(skb)) {
8511 	case htons(ETH_P_FCOE):
8512 	case htons(ETH_P_FIP):
8513 		adapter = netdev_priv(dev);
8514 
8515 		if (!sb_dev && (adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
8516 			break;
8517 		fallthrough;
8518 	default:
8519 		return netdev_pick_tx(dev, skb, sb_dev);
8520 	}
8521 
8522 	f = &adapter->ring_feature[RING_F_FCOE];
8523 
8524 	txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
8525 					   smp_processor_id();
8526 
8527 	while (txq >= f->indices)
8528 		txq -= f->indices;
8529 
8530 	return txq + f->offset;
8531 }
8532 
8533 #endif
8534 int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter,
8535 			struct xdp_frame *xdpf)
8536 {
8537 	struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()];
8538 	struct ixgbe_tx_buffer *tx_buffer;
8539 	union ixgbe_adv_tx_desc *tx_desc;
8540 	u32 len, cmd_type;
8541 	dma_addr_t dma;
8542 	u16 i;
8543 
8544 	len = xdpf->len;
8545 
8546 	if (unlikely(!ixgbe_desc_unused(ring)))
8547 		return IXGBE_XDP_CONSUMED;
8548 
8549 	dma = dma_map_single(ring->dev, xdpf->data, len, DMA_TO_DEVICE);
8550 	if (dma_mapping_error(ring->dev, dma))
8551 		return IXGBE_XDP_CONSUMED;
8552 
8553 	/* record the location of the first descriptor for this packet */
8554 	tx_buffer = &ring->tx_buffer_info[ring->next_to_use];
8555 	tx_buffer->bytecount = len;
8556 	tx_buffer->gso_segs = 1;
8557 	tx_buffer->protocol = 0;
8558 
8559 	i = ring->next_to_use;
8560 	tx_desc = IXGBE_TX_DESC(ring, i);
8561 
8562 	dma_unmap_len_set(tx_buffer, len, len);
8563 	dma_unmap_addr_set(tx_buffer, dma, dma);
8564 	tx_buffer->xdpf = xdpf;
8565 
8566 	tx_desc->read.buffer_addr = cpu_to_le64(dma);
8567 
8568 	/* put descriptor type bits */
8569 	cmd_type = IXGBE_ADVTXD_DTYP_DATA |
8570 		   IXGBE_ADVTXD_DCMD_DEXT |
8571 		   IXGBE_ADVTXD_DCMD_IFCS;
8572 	cmd_type |= len | IXGBE_TXD_CMD;
8573 	tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8574 	tx_desc->read.olinfo_status =
8575 		cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT);
8576 
8577 	/* Avoid any potential race with xdp_xmit and cleanup */
8578 	smp_wmb();
8579 
8580 	/* set next_to_watch value indicating a packet is present */
8581 	i++;
8582 	if (i == ring->count)
8583 		i = 0;
8584 
8585 	tx_buffer->next_to_watch = tx_desc;
8586 	ring->next_to_use = i;
8587 
8588 	return IXGBE_XDP_TX;
8589 }
8590 
8591 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
8592 			  struct ixgbe_adapter *adapter,
8593 			  struct ixgbe_ring *tx_ring)
8594 {
8595 	struct ixgbe_tx_buffer *first;
8596 	int tso;
8597 	u32 tx_flags = 0;
8598 	unsigned short f;
8599 	u16 count = TXD_USE_COUNT(skb_headlen(skb));
8600 	struct ixgbe_ipsec_tx_data ipsec_tx = { 0 };
8601 	__be16 protocol = skb->protocol;
8602 	u8 hdr_len = 0;
8603 
8604 	/*
8605 	 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
8606 	 *       + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
8607 	 *       + 2 desc gap to keep tail from touching head,
8608 	 *       + 1 desc for context descriptor,
8609 	 * otherwise try next time
8610 	 */
8611 	for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
8612 		count += TXD_USE_COUNT(skb_frag_size(
8613 						&skb_shinfo(skb)->frags[f]));
8614 
8615 	if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
8616 		tx_ring->tx_stats.tx_busy++;
8617 		return NETDEV_TX_BUSY;
8618 	}
8619 
8620 	/* record the location of the first descriptor for this packet */
8621 	first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
8622 	first->skb = skb;
8623 	first->bytecount = skb->len;
8624 	first->gso_segs = 1;
8625 
8626 	/* if we have a HW VLAN tag being added default to the HW one */
8627 	if (skb_vlan_tag_present(skb)) {
8628 		tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
8629 		tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
8630 	/* else if it is a SW VLAN check the next protocol and store the tag */
8631 	} else if (protocol == htons(ETH_P_8021Q)) {
8632 		struct vlan_hdr *vhdr, _vhdr;
8633 		vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
8634 		if (!vhdr)
8635 			goto out_drop;
8636 
8637 		tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
8638 				  IXGBE_TX_FLAGS_VLAN_SHIFT;
8639 		tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
8640 	}
8641 	protocol = vlan_get_protocol(skb);
8642 
8643 	if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
8644 	    adapter->ptp_clock) {
8645 		if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON &&
8646 		    !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
8647 					   &adapter->state)) {
8648 			skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
8649 			tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
8650 
8651 			/* schedule check for Tx timestamp */
8652 			adapter->ptp_tx_skb = skb_get(skb);
8653 			adapter->ptp_tx_start = jiffies;
8654 			schedule_work(&adapter->ptp_tx_work);
8655 		} else {
8656 			adapter->tx_hwtstamp_skipped++;
8657 		}
8658 	}
8659 
8660 #ifdef CONFIG_PCI_IOV
8661 	/*
8662 	 * Use the l2switch_enable flag - would be false if the DMA
8663 	 * Tx switch had been disabled.
8664 	 */
8665 	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
8666 		tx_flags |= IXGBE_TX_FLAGS_CC;
8667 
8668 #endif
8669 	/* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
8670 	if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8671 	    ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
8672 	     (skb->priority != TC_PRIO_CONTROL))) {
8673 		tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
8674 		tx_flags |= (skb->priority & 0x7) <<
8675 					IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
8676 		if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
8677 			struct vlan_ethhdr *vhdr;
8678 
8679 			if (skb_cow_head(skb, 0))
8680 				goto out_drop;
8681 			vhdr = (struct vlan_ethhdr *)skb->data;
8682 			vhdr->h_vlan_TCI = htons(tx_flags >>
8683 						 IXGBE_TX_FLAGS_VLAN_SHIFT);
8684 		} else {
8685 			tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
8686 		}
8687 	}
8688 
8689 	/* record initial flags and protocol */
8690 	first->tx_flags = tx_flags;
8691 	first->protocol = protocol;
8692 
8693 #ifdef IXGBE_FCOE
8694 	/* setup tx offload for FCoE */
8695 	if ((protocol == htons(ETH_P_FCOE)) &&
8696 	    (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
8697 		tso = ixgbe_fso(tx_ring, first, &hdr_len);
8698 		if (tso < 0)
8699 			goto out_drop;
8700 
8701 		goto xmit_fcoe;
8702 	}
8703 
8704 #endif /* IXGBE_FCOE */
8705 
8706 #ifdef CONFIG_IXGBE_IPSEC
8707 	if (xfrm_offload(skb) &&
8708 	    !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx))
8709 		goto out_drop;
8710 #endif
8711 	tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx);
8712 	if (tso < 0)
8713 		goto out_drop;
8714 	else if (!tso)
8715 		ixgbe_tx_csum(tx_ring, first, &ipsec_tx);
8716 
8717 	/* add the ATR filter if ATR is on */
8718 	if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
8719 		ixgbe_atr(tx_ring, first);
8720 
8721 #ifdef IXGBE_FCOE
8722 xmit_fcoe:
8723 #endif /* IXGBE_FCOE */
8724 	if (ixgbe_tx_map(tx_ring, first, hdr_len))
8725 		goto cleanup_tx_timestamp;
8726 
8727 	return NETDEV_TX_OK;
8728 
8729 out_drop:
8730 	dev_kfree_skb_any(first->skb);
8731 	first->skb = NULL;
8732 cleanup_tx_timestamp:
8733 	if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) {
8734 		dev_kfree_skb_any(adapter->ptp_tx_skb);
8735 		adapter->ptp_tx_skb = NULL;
8736 		cancel_work_sync(&adapter->ptp_tx_work);
8737 		clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
8738 	}
8739 
8740 	return NETDEV_TX_OK;
8741 }
8742 
8743 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
8744 				      struct net_device *netdev,
8745 				      struct ixgbe_ring *ring)
8746 {
8747 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
8748 	struct ixgbe_ring *tx_ring;
8749 
8750 	/*
8751 	 * The minimum packet size for olinfo paylen is 17 so pad the skb
8752 	 * in order to meet this minimum size requirement.
8753 	 */
8754 	if (skb_put_padto(skb, 17))
8755 		return NETDEV_TX_OK;
8756 
8757 	tx_ring = ring ? ring : adapter->tx_ring[skb_get_queue_mapping(skb)];
8758 	if (unlikely(test_bit(__IXGBE_TX_DISABLED, &tx_ring->state)))
8759 		return NETDEV_TX_BUSY;
8760 
8761 	return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
8762 }
8763 
8764 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
8765 				    struct net_device *netdev)
8766 {
8767 	return __ixgbe_xmit_frame(skb, netdev, NULL);
8768 }
8769 
8770 /**
8771  * ixgbe_set_mac - Change the Ethernet Address of the NIC
8772  * @netdev: network interface device structure
8773  * @p: pointer to an address structure
8774  *
8775  * Returns 0 on success, negative on failure
8776  **/
8777 static int ixgbe_set_mac(struct net_device *netdev, void *p)
8778 {
8779 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
8780 	struct ixgbe_hw *hw = &adapter->hw;
8781 	struct sockaddr *addr = p;
8782 
8783 	if (!is_valid_ether_addr(addr->sa_data))
8784 		return -EADDRNOTAVAIL;
8785 
8786 	memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
8787 	memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
8788 
8789 	ixgbe_mac_set_default_filter(adapter);
8790 
8791 	return 0;
8792 }
8793 
8794 static int
8795 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
8796 {
8797 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
8798 	struct ixgbe_hw *hw = &adapter->hw;
8799 	u16 value;
8800 	int rc;
8801 
8802 	if (adapter->mii_bus) {
8803 		int regnum = addr;
8804 
8805 		if (devad != MDIO_DEVAD_NONE)
8806 			regnum |= (devad << 16) | MII_ADDR_C45;
8807 
8808 		return mdiobus_read(adapter->mii_bus, prtad, regnum);
8809 	}
8810 
8811 	if (prtad != hw->phy.mdio.prtad)
8812 		return -EINVAL;
8813 	rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
8814 	if (!rc)
8815 		rc = value;
8816 	return rc;
8817 }
8818 
8819 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
8820 			    u16 addr, u16 value)
8821 {
8822 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
8823 	struct ixgbe_hw *hw = &adapter->hw;
8824 
8825 	if (adapter->mii_bus) {
8826 		int regnum = addr;
8827 
8828 		if (devad != MDIO_DEVAD_NONE)
8829 			regnum |= (devad << 16) | MII_ADDR_C45;
8830 
8831 		return mdiobus_write(adapter->mii_bus, prtad, regnum, value);
8832 	}
8833 
8834 	if (prtad != hw->phy.mdio.prtad)
8835 		return -EINVAL;
8836 	return hw->phy.ops.write_reg(hw, addr, devad, value);
8837 }
8838 
8839 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
8840 {
8841 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
8842 
8843 	switch (cmd) {
8844 	case SIOCSHWTSTAMP:
8845 		return ixgbe_ptp_set_ts_config(adapter, req);
8846 	case SIOCGHWTSTAMP:
8847 		return ixgbe_ptp_get_ts_config(adapter, req);
8848 	case SIOCGMIIPHY:
8849 		if (!adapter->hw.phy.ops.read_reg)
8850 			return -EOPNOTSUPP;
8851 		fallthrough;
8852 	default:
8853 		return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
8854 	}
8855 }
8856 
8857 /**
8858  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
8859  * netdev->dev_addrs
8860  * @dev: network interface device structure
8861  *
8862  * Returns non-zero on failure
8863  **/
8864 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
8865 {
8866 	int err = 0;
8867 	struct ixgbe_adapter *adapter = netdev_priv(dev);
8868 	struct ixgbe_hw *hw = &adapter->hw;
8869 
8870 	if (is_valid_ether_addr(hw->mac.san_addr)) {
8871 		rtnl_lock();
8872 		err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
8873 		rtnl_unlock();
8874 
8875 		/* update SAN MAC vmdq pool selection */
8876 		hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
8877 	}
8878 	return err;
8879 }
8880 
8881 /**
8882  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
8883  * netdev->dev_addrs
8884  * @dev: network interface device structure
8885  *
8886  * Returns non-zero on failure
8887  **/
8888 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
8889 {
8890 	int err = 0;
8891 	struct ixgbe_adapter *adapter = netdev_priv(dev);
8892 	struct ixgbe_mac_info *mac = &adapter->hw.mac;
8893 
8894 	if (is_valid_ether_addr(mac->san_addr)) {
8895 		rtnl_lock();
8896 		err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
8897 		rtnl_unlock();
8898 	}
8899 	return err;
8900 }
8901 
8902 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats,
8903 				   struct ixgbe_ring *ring)
8904 {
8905 	u64 bytes, packets;
8906 	unsigned int start;
8907 
8908 	if (ring) {
8909 		do {
8910 			start = u64_stats_fetch_begin_irq(&ring->syncp);
8911 			packets = ring->stats.packets;
8912 			bytes   = ring->stats.bytes;
8913 		} while (u64_stats_fetch_retry_irq(&ring->syncp, start));
8914 		stats->tx_packets += packets;
8915 		stats->tx_bytes   += bytes;
8916 	}
8917 }
8918 
8919 static void ixgbe_get_stats64(struct net_device *netdev,
8920 			      struct rtnl_link_stats64 *stats)
8921 {
8922 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
8923 	int i;
8924 
8925 	rcu_read_lock();
8926 	for (i = 0; i < adapter->num_rx_queues; i++) {
8927 		struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]);
8928 		u64 bytes, packets;
8929 		unsigned int start;
8930 
8931 		if (ring) {
8932 			do {
8933 				start = u64_stats_fetch_begin_irq(&ring->syncp);
8934 				packets = ring->stats.packets;
8935 				bytes   = ring->stats.bytes;
8936 			} while (u64_stats_fetch_retry_irq(&ring->syncp, start));
8937 			stats->rx_packets += packets;
8938 			stats->rx_bytes   += bytes;
8939 		}
8940 	}
8941 
8942 	for (i = 0; i < adapter->num_tx_queues; i++) {
8943 		struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]);
8944 
8945 		ixgbe_get_ring_stats64(stats, ring);
8946 	}
8947 	for (i = 0; i < adapter->num_xdp_queues; i++) {
8948 		struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]);
8949 
8950 		ixgbe_get_ring_stats64(stats, ring);
8951 	}
8952 	rcu_read_unlock();
8953 
8954 	/* following stats updated by ixgbe_watchdog_task() */
8955 	stats->multicast	= netdev->stats.multicast;
8956 	stats->rx_errors	= netdev->stats.rx_errors;
8957 	stats->rx_length_errors	= netdev->stats.rx_length_errors;
8958 	stats->rx_crc_errors	= netdev->stats.rx_crc_errors;
8959 	stats->rx_missed_errors	= netdev->stats.rx_missed_errors;
8960 }
8961 
8962 #ifdef CONFIG_IXGBE_DCB
8963 /**
8964  * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
8965  * @adapter: pointer to ixgbe_adapter
8966  * @tc: number of traffic classes currently enabled
8967  *
8968  * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
8969  * 802.1Q priority maps to a packet buffer that exists.
8970  */
8971 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
8972 {
8973 	struct ixgbe_hw *hw = &adapter->hw;
8974 	u32 reg, rsave;
8975 	int i;
8976 
8977 	/* 82598 have a static priority to TC mapping that can not
8978 	 * be changed so no validation is needed.
8979 	 */
8980 	if (hw->mac.type == ixgbe_mac_82598EB)
8981 		return;
8982 
8983 	reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
8984 	rsave = reg;
8985 
8986 	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
8987 		u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
8988 
8989 		/* If up2tc is out of bounds default to zero */
8990 		if (up2tc > tc)
8991 			reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
8992 	}
8993 
8994 	if (reg != rsave)
8995 		IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
8996 
8997 	return;
8998 }
8999 
9000 /**
9001  * ixgbe_set_prio_tc_map - Configure netdev prio tc map
9002  * @adapter: Pointer to adapter struct
9003  *
9004  * Populate the netdev user priority to tc map
9005  */
9006 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
9007 {
9008 	struct net_device *dev = adapter->netdev;
9009 	struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
9010 	struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
9011 	u8 prio;
9012 
9013 	for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
9014 		u8 tc = 0;
9015 
9016 		if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
9017 			tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
9018 		else if (ets)
9019 			tc = ets->prio_tc[prio];
9020 
9021 		netdev_set_prio_tc_map(dev, prio, tc);
9022 	}
9023 }
9024 
9025 #endif /* CONFIG_IXGBE_DCB */
9026 static int ixgbe_reassign_macvlan_pool(struct net_device *vdev,
9027 				       struct netdev_nested_priv *priv)
9028 {
9029 	struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data;
9030 	struct ixgbe_fwd_adapter *accel;
9031 	int pool;
9032 
9033 	/* we only care about macvlans... */
9034 	if (!netif_is_macvlan(vdev))
9035 		return 0;
9036 
9037 	/* that have hardware offload enabled... */
9038 	accel = macvlan_accel_priv(vdev);
9039 	if (!accel)
9040 		return 0;
9041 
9042 	/* If we can relocate to a different bit do so */
9043 	pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools);
9044 	if (pool < adapter->num_rx_pools) {
9045 		set_bit(pool, adapter->fwd_bitmask);
9046 		accel->pool = pool;
9047 		return 0;
9048 	}
9049 
9050 	/* if we cannot find a free pool then disable the offload */
9051 	netdev_err(vdev, "L2FW offload disabled due to lack of queue resources\n");
9052 	macvlan_release_l2fw_offload(vdev);
9053 
9054 	/* unbind the queues and drop the subordinate channel config */
9055 	netdev_unbind_sb_channel(adapter->netdev, vdev);
9056 	netdev_set_sb_channel(vdev, 0);
9057 
9058 	kfree(accel);
9059 
9060 	return 0;
9061 }
9062 
9063 static void ixgbe_defrag_macvlan_pools(struct net_device *dev)
9064 {
9065 	struct ixgbe_adapter *adapter = netdev_priv(dev);
9066 	struct netdev_nested_priv priv = {
9067 		.data = (void *)adapter,
9068 	};
9069 
9070 	/* flush any stale bits out of the fwd bitmask */
9071 	bitmap_clear(adapter->fwd_bitmask, 1, 63);
9072 
9073 	/* walk through upper devices reassigning pools */
9074 	netdev_walk_all_upper_dev_rcu(dev, ixgbe_reassign_macvlan_pool,
9075 				      &priv);
9076 }
9077 
9078 /**
9079  * ixgbe_setup_tc - configure net_device for multiple traffic classes
9080  *
9081  * @dev: net device to configure
9082  * @tc: number of traffic classes to enable
9083  */
9084 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
9085 {
9086 	struct ixgbe_adapter *adapter = netdev_priv(dev);
9087 	struct ixgbe_hw *hw = &adapter->hw;
9088 
9089 	/* Hardware supports up to 8 traffic classes */
9090 	if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
9091 		return -EINVAL;
9092 
9093 	if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
9094 		return -EINVAL;
9095 
9096 	/* Hardware has to reinitialize queues and interrupts to
9097 	 * match packet buffer alignment. Unfortunately, the
9098 	 * hardware is not flexible enough to do this dynamically.
9099 	 */
9100 	if (netif_running(dev))
9101 		ixgbe_close(dev);
9102 	else
9103 		ixgbe_reset(adapter);
9104 
9105 	ixgbe_clear_interrupt_scheme(adapter);
9106 
9107 #ifdef CONFIG_IXGBE_DCB
9108 	if (tc) {
9109 		if (adapter->xdp_prog) {
9110 			e_warn(probe, "DCB is not supported with XDP\n");
9111 
9112 			ixgbe_init_interrupt_scheme(adapter);
9113 			if (netif_running(dev))
9114 				ixgbe_open(dev);
9115 			return -EINVAL;
9116 		}
9117 
9118 		netdev_set_num_tc(dev, tc);
9119 		ixgbe_set_prio_tc_map(adapter);
9120 
9121 		adapter->hw_tcs = tc;
9122 		adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
9123 
9124 		if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
9125 			adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
9126 			adapter->hw.fc.requested_mode = ixgbe_fc_none;
9127 		}
9128 	} else {
9129 		netdev_reset_tc(dev);
9130 
9131 		if (adapter->hw.mac.type == ixgbe_mac_82598EB)
9132 			adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
9133 
9134 		adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
9135 		adapter->hw_tcs = tc;
9136 
9137 		adapter->temp_dcb_cfg.pfc_mode_enable = false;
9138 		adapter->dcb_cfg.pfc_mode_enable = false;
9139 	}
9140 
9141 	ixgbe_validate_rtr(adapter, tc);
9142 
9143 #endif /* CONFIG_IXGBE_DCB */
9144 	ixgbe_init_interrupt_scheme(adapter);
9145 
9146 	ixgbe_defrag_macvlan_pools(dev);
9147 
9148 	if (netif_running(dev))
9149 		return ixgbe_open(dev);
9150 
9151 	return 0;
9152 }
9153 
9154 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter,
9155 			       struct tc_cls_u32_offload *cls)
9156 {
9157 	u32 hdl = cls->knode.handle;
9158 	u32 uhtid = TC_U32_USERHTID(cls->knode.handle);
9159 	u32 loc = cls->knode.handle & 0xfffff;
9160 	int err = 0, i, j;
9161 	struct ixgbe_jump_table *jump = NULL;
9162 
9163 	if (loc > IXGBE_MAX_HW_ENTRIES)
9164 		return -EINVAL;
9165 
9166 	if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE))
9167 		return -EINVAL;
9168 
9169 	/* Clear this filter in the link data it is associated with */
9170 	if (uhtid != 0x800) {
9171 		jump = adapter->jump_tables[uhtid];
9172 		if (!jump)
9173 			return -EINVAL;
9174 		if (!test_bit(loc - 1, jump->child_loc_map))
9175 			return -EINVAL;
9176 		clear_bit(loc - 1, jump->child_loc_map);
9177 	}
9178 
9179 	/* Check if the filter being deleted is a link */
9180 	for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) {
9181 		jump = adapter->jump_tables[i];
9182 		if (jump && jump->link_hdl == hdl) {
9183 			/* Delete filters in the hardware in the child hash
9184 			 * table associated with this link
9185 			 */
9186 			for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) {
9187 				if (!test_bit(j, jump->child_loc_map))
9188 					continue;
9189 				spin_lock(&adapter->fdir_perfect_lock);
9190 				err = ixgbe_update_ethtool_fdir_entry(adapter,
9191 								      NULL,
9192 								      j + 1);
9193 				spin_unlock(&adapter->fdir_perfect_lock);
9194 				clear_bit(j, jump->child_loc_map);
9195 			}
9196 			/* Remove resources for this link */
9197 			kfree(jump->input);
9198 			kfree(jump->mask);
9199 			kfree(jump);
9200 			adapter->jump_tables[i] = NULL;
9201 			return err;
9202 		}
9203 	}
9204 
9205 	spin_lock(&adapter->fdir_perfect_lock);
9206 	err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc);
9207 	spin_unlock(&adapter->fdir_perfect_lock);
9208 	return err;
9209 }
9210 
9211 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter,
9212 					    struct tc_cls_u32_offload *cls)
9213 {
9214 	u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
9215 
9216 	if (uhtid >= IXGBE_MAX_LINK_HANDLE)
9217 		return -EINVAL;
9218 
9219 	/* This ixgbe devices do not support hash tables at the moment
9220 	 * so abort when given hash tables.
9221 	 */
9222 	if (cls->hnode.divisor > 0)
9223 		return -EINVAL;
9224 
9225 	set_bit(uhtid - 1, &adapter->tables);
9226 	return 0;
9227 }
9228 
9229 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter,
9230 					    struct tc_cls_u32_offload *cls)
9231 {
9232 	u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
9233 
9234 	if (uhtid >= IXGBE_MAX_LINK_HANDLE)
9235 		return -EINVAL;
9236 
9237 	clear_bit(uhtid - 1, &adapter->tables);
9238 	return 0;
9239 }
9240 
9241 #ifdef CONFIG_NET_CLS_ACT
9242 struct upper_walk_data {
9243 	struct ixgbe_adapter *adapter;
9244 	u64 action;
9245 	int ifindex;
9246 	u8 queue;
9247 };
9248 
9249 static int get_macvlan_queue(struct net_device *upper,
9250 			     struct netdev_nested_priv *priv)
9251 {
9252 	if (netif_is_macvlan(upper)) {
9253 		struct ixgbe_fwd_adapter *vadapter = macvlan_accel_priv(upper);
9254 		struct ixgbe_adapter *adapter;
9255 		struct upper_walk_data *data;
9256 		int ifindex;
9257 
9258 		data = (struct upper_walk_data *)priv->data;
9259 		ifindex = data->ifindex;
9260 		adapter = data->adapter;
9261 		if (vadapter && upper->ifindex == ifindex) {
9262 			data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx;
9263 			data->action = data->queue;
9264 			return 1;
9265 		}
9266 	}
9267 
9268 	return 0;
9269 }
9270 
9271 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex,
9272 				  u8 *queue, u64 *action)
9273 {
9274 	struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
9275 	unsigned int num_vfs = adapter->num_vfs, vf;
9276 	struct netdev_nested_priv priv;
9277 	struct upper_walk_data data;
9278 	struct net_device *upper;
9279 
9280 	/* redirect to a SRIOV VF */
9281 	for (vf = 0; vf < num_vfs; ++vf) {
9282 		upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev);
9283 		if (upper->ifindex == ifindex) {
9284 			*queue = vf * __ALIGN_MASK(1, ~vmdq->mask);
9285 			*action = vf + 1;
9286 			*action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
9287 			return 0;
9288 		}
9289 	}
9290 
9291 	/* redirect to a offloaded macvlan netdev */
9292 	data.adapter = adapter;
9293 	data.ifindex = ifindex;
9294 	data.action = 0;
9295 	data.queue = 0;
9296 	priv.data = (void *)&data;
9297 	if (netdev_walk_all_upper_dev_rcu(adapter->netdev,
9298 					  get_macvlan_queue, &priv)) {
9299 		*action = data.action;
9300 		*queue = data.queue;
9301 
9302 		return 0;
9303 	}
9304 
9305 	return -EINVAL;
9306 }
9307 
9308 static int parse_tc_actions(struct ixgbe_adapter *adapter,
9309 			    struct tcf_exts *exts, u64 *action, u8 *queue)
9310 {
9311 	const struct tc_action *a;
9312 	int i;
9313 
9314 	if (!tcf_exts_has_actions(exts))
9315 		return -EINVAL;
9316 
9317 	tcf_exts_for_each_action(i, a, exts) {
9318 		/* Drop action */
9319 		if (is_tcf_gact_shot(a)) {
9320 			*action = IXGBE_FDIR_DROP_QUEUE;
9321 			*queue = IXGBE_FDIR_DROP_QUEUE;
9322 			return 0;
9323 		}
9324 
9325 		/* Redirect to a VF or a offloaded macvlan */
9326 		if (is_tcf_mirred_egress_redirect(a)) {
9327 			struct net_device *dev = tcf_mirred_dev(a);
9328 
9329 			if (!dev)
9330 				return -EINVAL;
9331 			return handle_redirect_action(adapter, dev->ifindex,
9332 						      queue, action);
9333 		}
9334 
9335 		return -EINVAL;
9336 	}
9337 
9338 	return -EINVAL;
9339 }
9340 #else
9341 static int parse_tc_actions(struct ixgbe_adapter *adapter,
9342 			    struct tcf_exts *exts, u64 *action, u8 *queue)
9343 {
9344 	return -EINVAL;
9345 }
9346 #endif /* CONFIG_NET_CLS_ACT */
9347 
9348 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input,
9349 				    union ixgbe_atr_input *mask,
9350 				    struct tc_cls_u32_offload *cls,
9351 				    struct ixgbe_mat_field *field_ptr,
9352 				    struct ixgbe_nexthdr *nexthdr)
9353 {
9354 	int i, j, off;
9355 	__be32 val, m;
9356 	bool found_entry = false, found_jump_field = false;
9357 
9358 	for (i = 0; i < cls->knode.sel->nkeys; i++) {
9359 		off = cls->knode.sel->keys[i].off;
9360 		val = cls->knode.sel->keys[i].val;
9361 		m = cls->knode.sel->keys[i].mask;
9362 
9363 		for (j = 0; field_ptr[j].val; j++) {
9364 			if (field_ptr[j].off == off) {
9365 				field_ptr[j].val(input, mask, (__force u32)val,
9366 						 (__force u32)m);
9367 				input->filter.formatted.flow_type |=
9368 					field_ptr[j].type;
9369 				found_entry = true;
9370 				break;
9371 			}
9372 		}
9373 		if (nexthdr) {
9374 			if (nexthdr->off == cls->knode.sel->keys[i].off &&
9375 			    nexthdr->val ==
9376 			    (__force u32)cls->knode.sel->keys[i].val &&
9377 			    nexthdr->mask ==
9378 			    (__force u32)cls->knode.sel->keys[i].mask)
9379 				found_jump_field = true;
9380 			else
9381 				continue;
9382 		}
9383 	}
9384 
9385 	if (nexthdr && !found_jump_field)
9386 		return -EINVAL;
9387 
9388 	if (!found_entry)
9389 		return 0;
9390 
9391 	mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
9392 				    IXGBE_ATR_L4TYPE_MASK;
9393 
9394 	if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
9395 		mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
9396 
9397 	return 0;
9398 }
9399 
9400 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter,
9401 				  struct tc_cls_u32_offload *cls)
9402 {
9403 	__be16 protocol = cls->common.protocol;
9404 	u32 loc = cls->knode.handle & 0xfffff;
9405 	struct ixgbe_hw *hw = &adapter->hw;
9406 	struct ixgbe_mat_field *field_ptr;
9407 	struct ixgbe_fdir_filter *input = NULL;
9408 	union ixgbe_atr_input *mask = NULL;
9409 	struct ixgbe_jump_table *jump = NULL;
9410 	int i, err = -EINVAL;
9411 	u8 queue;
9412 	u32 uhtid, link_uhtid;
9413 
9414 	uhtid = TC_U32_USERHTID(cls->knode.handle);
9415 	link_uhtid = TC_U32_USERHTID(cls->knode.link_handle);
9416 
9417 	/* At the moment cls_u32 jumps to network layer and skips past
9418 	 * L2 headers. The canonical method to match L2 frames is to use
9419 	 * negative values. However this is error prone at best but really
9420 	 * just broken because there is no way to "know" what sort of hdr
9421 	 * is in front of the network layer. Fix cls_u32 to support L2
9422 	 * headers when needed.
9423 	 */
9424 	if (protocol != htons(ETH_P_IP))
9425 		return err;
9426 
9427 	if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) {
9428 		e_err(drv, "Location out of range\n");
9429 		return err;
9430 	}
9431 
9432 	/* cls u32 is a graph starting at root node 0x800. The driver tracks
9433 	 * links and also the fields used to advance the parser across each
9434 	 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map
9435 	 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h
9436 	 * To add support for new nodes update ixgbe_model.h parse structures
9437 	 * this function _should_ be generic try not to hardcode values here.
9438 	 */
9439 	if (uhtid == 0x800) {
9440 		field_ptr = (adapter->jump_tables[0])->mat;
9441 	} else {
9442 		if (uhtid >= IXGBE_MAX_LINK_HANDLE)
9443 			return err;
9444 		if (!adapter->jump_tables[uhtid])
9445 			return err;
9446 		field_ptr = (adapter->jump_tables[uhtid])->mat;
9447 	}
9448 
9449 	if (!field_ptr)
9450 		return err;
9451 
9452 	/* At this point we know the field_ptr is valid and need to either
9453 	 * build cls_u32 link or attach filter. Because adding a link to
9454 	 * a handle that does not exist is invalid and the same for adding
9455 	 * rules to handles that don't exist.
9456 	 */
9457 
9458 	if (link_uhtid) {
9459 		struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps;
9460 
9461 		if (link_uhtid >= IXGBE_MAX_LINK_HANDLE)
9462 			return err;
9463 
9464 		if (!test_bit(link_uhtid - 1, &adapter->tables))
9465 			return err;
9466 
9467 		/* Multiple filters as links to the same hash table are not
9468 		 * supported. To add a new filter with the same next header
9469 		 * but different match/jump conditions, create a new hash table
9470 		 * and link to it.
9471 		 */
9472 		if (adapter->jump_tables[link_uhtid] &&
9473 		    (adapter->jump_tables[link_uhtid])->link_hdl) {
9474 			e_err(drv, "Link filter exists for link: %x\n",
9475 			      link_uhtid);
9476 			return err;
9477 		}
9478 
9479 		for (i = 0; nexthdr[i].jump; i++) {
9480 			if (nexthdr[i].o != cls->knode.sel->offoff ||
9481 			    nexthdr[i].s != cls->knode.sel->offshift ||
9482 			    nexthdr[i].m !=
9483 			    (__force u32)cls->knode.sel->offmask)
9484 				return err;
9485 
9486 			jump = kzalloc(sizeof(*jump), GFP_KERNEL);
9487 			if (!jump)
9488 				return -ENOMEM;
9489 			input = kzalloc(sizeof(*input), GFP_KERNEL);
9490 			if (!input) {
9491 				err = -ENOMEM;
9492 				goto free_jump;
9493 			}
9494 			mask = kzalloc(sizeof(*mask), GFP_KERNEL);
9495 			if (!mask) {
9496 				err = -ENOMEM;
9497 				goto free_input;
9498 			}
9499 			jump->input = input;
9500 			jump->mask = mask;
9501 			jump->link_hdl = cls->knode.handle;
9502 
9503 			err = ixgbe_clsu32_build_input(input, mask, cls,
9504 						       field_ptr, &nexthdr[i]);
9505 			if (!err) {
9506 				jump->mat = nexthdr[i].jump;
9507 				adapter->jump_tables[link_uhtid] = jump;
9508 				break;
9509 			} else {
9510 				kfree(mask);
9511 				kfree(input);
9512 				kfree(jump);
9513 			}
9514 		}
9515 		return 0;
9516 	}
9517 
9518 	input = kzalloc(sizeof(*input), GFP_KERNEL);
9519 	if (!input)
9520 		return -ENOMEM;
9521 	mask = kzalloc(sizeof(*mask), GFP_KERNEL);
9522 	if (!mask) {
9523 		err = -ENOMEM;
9524 		goto free_input;
9525 	}
9526 
9527 	if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) {
9528 		if ((adapter->jump_tables[uhtid])->input)
9529 			memcpy(input, (adapter->jump_tables[uhtid])->input,
9530 			       sizeof(*input));
9531 		if ((adapter->jump_tables[uhtid])->mask)
9532 			memcpy(mask, (adapter->jump_tables[uhtid])->mask,
9533 			       sizeof(*mask));
9534 
9535 		/* Lookup in all child hash tables if this location is already
9536 		 * filled with a filter
9537 		 */
9538 		for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) {
9539 			struct ixgbe_jump_table *link = adapter->jump_tables[i];
9540 
9541 			if (link && (test_bit(loc - 1, link->child_loc_map))) {
9542 				e_err(drv, "Filter exists in location: %x\n",
9543 				      loc);
9544 				err = -EINVAL;
9545 				goto err_out;
9546 			}
9547 		}
9548 	}
9549 	err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL);
9550 	if (err)
9551 		goto err_out;
9552 
9553 	err = parse_tc_actions(adapter, cls->knode.exts, &input->action,
9554 			       &queue);
9555 	if (err < 0)
9556 		goto err_out;
9557 
9558 	input->sw_idx = loc;
9559 
9560 	spin_lock(&adapter->fdir_perfect_lock);
9561 
9562 	if (hlist_empty(&adapter->fdir_filter_list)) {
9563 		memcpy(&adapter->fdir_mask, mask, sizeof(*mask));
9564 		err = ixgbe_fdir_set_input_mask_82599(hw, mask);
9565 		if (err)
9566 			goto err_out_w_lock;
9567 	} else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) {
9568 		err = -EINVAL;
9569 		goto err_out_w_lock;
9570 	}
9571 
9572 	ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask);
9573 	err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter,
9574 						    input->sw_idx, queue);
9575 	if (!err)
9576 		ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
9577 	spin_unlock(&adapter->fdir_perfect_lock);
9578 
9579 	if ((uhtid != 0x800) && (adapter->jump_tables[uhtid]))
9580 		set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map);
9581 
9582 	kfree(mask);
9583 	return err;
9584 err_out_w_lock:
9585 	spin_unlock(&adapter->fdir_perfect_lock);
9586 err_out:
9587 	kfree(mask);
9588 free_input:
9589 	kfree(input);
9590 free_jump:
9591 	kfree(jump);
9592 	return err;
9593 }
9594 
9595 static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter,
9596 				  struct tc_cls_u32_offload *cls_u32)
9597 {
9598 	switch (cls_u32->command) {
9599 	case TC_CLSU32_NEW_KNODE:
9600 	case TC_CLSU32_REPLACE_KNODE:
9601 		return ixgbe_configure_clsu32(adapter, cls_u32);
9602 	case TC_CLSU32_DELETE_KNODE:
9603 		return ixgbe_delete_clsu32(adapter, cls_u32);
9604 	case TC_CLSU32_NEW_HNODE:
9605 	case TC_CLSU32_REPLACE_HNODE:
9606 		return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32);
9607 	case TC_CLSU32_DELETE_HNODE:
9608 		return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32);
9609 	default:
9610 		return -EOPNOTSUPP;
9611 	}
9612 }
9613 
9614 static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
9615 				   void *cb_priv)
9616 {
9617 	struct ixgbe_adapter *adapter = cb_priv;
9618 
9619 	if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data))
9620 		return -EOPNOTSUPP;
9621 
9622 	switch (type) {
9623 	case TC_SETUP_CLSU32:
9624 		return ixgbe_setup_tc_cls_u32(adapter, type_data);
9625 	default:
9626 		return -EOPNOTSUPP;
9627 	}
9628 }
9629 
9630 static int ixgbe_setup_tc_mqprio(struct net_device *dev,
9631 				 struct tc_mqprio_qopt *mqprio)
9632 {
9633 	mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
9634 	return ixgbe_setup_tc(dev, mqprio->num_tc);
9635 }
9636 
9637 static LIST_HEAD(ixgbe_block_cb_list);
9638 
9639 static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type,
9640 			    void *type_data)
9641 {
9642 	struct ixgbe_adapter *adapter = netdev_priv(dev);
9643 
9644 	switch (type) {
9645 	case TC_SETUP_BLOCK:
9646 		return flow_block_cb_setup_simple(type_data,
9647 						  &ixgbe_block_cb_list,
9648 						  ixgbe_setup_tc_block_cb,
9649 						  adapter, adapter, true);
9650 	case TC_SETUP_QDISC_MQPRIO:
9651 		return ixgbe_setup_tc_mqprio(dev, type_data);
9652 	default:
9653 		return -EOPNOTSUPP;
9654 	}
9655 }
9656 
9657 #ifdef CONFIG_PCI_IOV
9658 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
9659 {
9660 	struct net_device *netdev = adapter->netdev;
9661 
9662 	rtnl_lock();
9663 	ixgbe_setup_tc(netdev, adapter->hw_tcs);
9664 	rtnl_unlock();
9665 }
9666 
9667 #endif
9668 void ixgbe_do_reset(struct net_device *netdev)
9669 {
9670 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
9671 
9672 	if (netif_running(netdev))
9673 		ixgbe_reinit_locked(adapter);
9674 	else
9675 		ixgbe_reset(adapter);
9676 }
9677 
9678 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
9679 					    netdev_features_t features)
9680 {
9681 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
9682 
9683 	/* If Rx checksum is disabled, then RSC/LRO should also be disabled */
9684 	if (!(features & NETIF_F_RXCSUM))
9685 		features &= ~NETIF_F_LRO;
9686 
9687 	/* Turn off LRO if not RSC capable */
9688 	if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
9689 		features &= ~NETIF_F_LRO;
9690 
9691 	if (adapter->xdp_prog && (features & NETIF_F_LRO)) {
9692 		e_dev_err("LRO is not supported with XDP\n");
9693 		features &= ~NETIF_F_LRO;
9694 	}
9695 
9696 	return features;
9697 }
9698 
9699 static void ixgbe_reset_l2fw_offload(struct ixgbe_adapter *adapter)
9700 {
9701 	int rss = min_t(int, ixgbe_max_rss_indices(adapter),
9702 			num_online_cpus());
9703 
9704 	/* go back to full RSS if we're not running SR-IOV */
9705 	if (!adapter->ring_feature[RING_F_VMDQ].offset)
9706 		adapter->flags &= ~(IXGBE_FLAG_VMDQ_ENABLED |
9707 				    IXGBE_FLAG_SRIOV_ENABLED);
9708 
9709 	adapter->ring_feature[RING_F_RSS].limit = rss;
9710 	adapter->ring_feature[RING_F_VMDQ].limit = 1;
9711 
9712 	ixgbe_setup_tc(adapter->netdev, adapter->hw_tcs);
9713 }
9714 
9715 static int ixgbe_set_features(struct net_device *netdev,
9716 			      netdev_features_t features)
9717 {
9718 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
9719 	netdev_features_t changed = netdev->features ^ features;
9720 	bool need_reset = false;
9721 
9722 	/* Make sure RSC matches LRO, reset if change */
9723 	if (!(features & NETIF_F_LRO)) {
9724 		if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
9725 			need_reset = true;
9726 		adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
9727 	} else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
9728 		   !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
9729 		if (adapter->rx_itr_setting == 1 ||
9730 		    adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
9731 			adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
9732 			need_reset = true;
9733 		} else if ((changed ^ features) & NETIF_F_LRO) {
9734 			e_info(probe, "rx-usecs set too low, "
9735 			       "disabling RSC\n");
9736 		}
9737 	}
9738 
9739 	/*
9740 	 * Check if Flow Director n-tuple support or hw_tc support was
9741 	 * enabled or disabled.  If the state changed, we need to reset.
9742 	 */
9743 	if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) {
9744 		/* turn off ATR, enable perfect filters and reset */
9745 		if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
9746 			need_reset = true;
9747 
9748 		adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
9749 		adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
9750 	} else {
9751 		/* turn off perfect filters, enable ATR and reset */
9752 		if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
9753 			need_reset = true;
9754 
9755 		adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
9756 
9757 		/* We cannot enable ATR if SR-IOV is enabled */
9758 		if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED ||
9759 		    /* We cannot enable ATR if we have 2 or more tcs */
9760 		    (adapter->hw_tcs > 1) ||
9761 		    /* We cannot enable ATR if RSS is disabled */
9762 		    (adapter->ring_feature[RING_F_RSS].limit <= 1) ||
9763 		    /* A sample rate of 0 indicates ATR disabled */
9764 		    (!adapter->atr_sample_rate))
9765 			; /* do nothing not supported */
9766 		else /* otherwise supported and set the flag */
9767 			adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
9768 	}
9769 
9770 	if (changed & NETIF_F_RXALL)
9771 		need_reset = true;
9772 
9773 	netdev->features = features;
9774 
9775 	if ((changed & NETIF_F_HW_L2FW_DOFFLOAD) && adapter->num_rx_pools > 1)
9776 		ixgbe_reset_l2fw_offload(adapter);
9777 	else if (need_reset)
9778 		ixgbe_do_reset(netdev);
9779 	else if (changed & (NETIF_F_HW_VLAN_CTAG_RX |
9780 			    NETIF_F_HW_VLAN_CTAG_FILTER))
9781 		ixgbe_set_rx_mode(netdev);
9782 
9783 	return 1;
9784 }
9785 
9786 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
9787 			     struct net_device *dev,
9788 			     const unsigned char *addr, u16 vid,
9789 			     u16 flags,
9790 			     struct netlink_ext_ack *extack)
9791 {
9792 	/* guarantee we can provide a unique filter for the unicast address */
9793 	if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
9794 		struct ixgbe_adapter *adapter = netdev_priv(dev);
9795 		u16 pool = VMDQ_P(0);
9796 
9797 		if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool))
9798 			return -ENOMEM;
9799 	}
9800 
9801 	return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
9802 }
9803 
9804 /**
9805  * ixgbe_configure_bridge_mode - set various bridge modes
9806  * @adapter: the private structure
9807  * @mode: requested bridge mode
9808  *
9809  * Configure some settings require for various bridge modes.
9810  **/
9811 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
9812 				       __u16 mode)
9813 {
9814 	struct ixgbe_hw *hw = &adapter->hw;
9815 	unsigned int p, num_pools;
9816 	u32 vmdctl;
9817 
9818 	switch (mode) {
9819 	case BRIDGE_MODE_VEPA:
9820 		/* disable Tx loopback, rely on switch hairpin mode */
9821 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
9822 
9823 		/* must enable Rx switching replication to allow multicast
9824 		 * packet reception on all VFs, and to enable source address
9825 		 * pruning.
9826 		 */
9827 		vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
9828 		vmdctl |= IXGBE_VT_CTL_REPLEN;
9829 		IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
9830 
9831 		/* enable Rx source address pruning. Note, this requires
9832 		 * replication to be enabled or else it does nothing.
9833 		 */
9834 		num_pools = adapter->num_vfs + adapter->num_rx_pools;
9835 		for (p = 0; p < num_pools; p++) {
9836 			if (hw->mac.ops.set_source_address_pruning)
9837 				hw->mac.ops.set_source_address_pruning(hw,
9838 								       true,
9839 								       p);
9840 		}
9841 		break;
9842 	case BRIDGE_MODE_VEB:
9843 		/* enable Tx loopback for internal VF/PF communication */
9844 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
9845 				IXGBE_PFDTXGSWC_VT_LBEN);
9846 
9847 		/* disable Rx switching replication unless we have SR-IOV
9848 		 * virtual functions
9849 		 */
9850 		vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
9851 		if (!adapter->num_vfs)
9852 			vmdctl &= ~IXGBE_VT_CTL_REPLEN;
9853 		IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
9854 
9855 		/* disable Rx source address pruning, since we don't expect to
9856 		 * be receiving external loopback of our transmitted frames.
9857 		 */
9858 		num_pools = adapter->num_vfs + adapter->num_rx_pools;
9859 		for (p = 0; p < num_pools; p++) {
9860 			if (hw->mac.ops.set_source_address_pruning)
9861 				hw->mac.ops.set_source_address_pruning(hw,
9862 								       false,
9863 								       p);
9864 		}
9865 		break;
9866 	default:
9867 		return -EINVAL;
9868 	}
9869 
9870 	adapter->bridge_mode = mode;
9871 
9872 	e_info(drv, "enabling bridge mode: %s\n",
9873 	       mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
9874 
9875 	return 0;
9876 }
9877 
9878 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
9879 				    struct nlmsghdr *nlh, u16 flags,
9880 				    struct netlink_ext_ack *extack)
9881 {
9882 	struct ixgbe_adapter *adapter = netdev_priv(dev);
9883 	struct nlattr *attr, *br_spec;
9884 	int rem;
9885 
9886 	if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
9887 		return -EOPNOTSUPP;
9888 
9889 	br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
9890 	if (!br_spec)
9891 		return -EINVAL;
9892 
9893 	nla_for_each_nested(attr, br_spec, rem) {
9894 		int status;
9895 		__u16 mode;
9896 
9897 		if (nla_type(attr) != IFLA_BRIDGE_MODE)
9898 			continue;
9899 
9900 		if (nla_len(attr) < sizeof(mode))
9901 			return -EINVAL;
9902 
9903 		mode = nla_get_u16(attr);
9904 		status = ixgbe_configure_bridge_mode(adapter, mode);
9905 		if (status)
9906 			return status;
9907 
9908 		break;
9909 	}
9910 
9911 	return 0;
9912 }
9913 
9914 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
9915 				    struct net_device *dev,
9916 				    u32 filter_mask, int nlflags)
9917 {
9918 	struct ixgbe_adapter *adapter = netdev_priv(dev);
9919 
9920 	if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
9921 		return 0;
9922 
9923 	return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
9924 				       adapter->bridge_mode, 0, 0, nlflags,
9925 				       filter_mask, NULL);
9926 }
9927 
9928 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
9929 {
9930 	struct ixgbe_adapter *adapter = netdev_priv(pdev);
9931 	struct ixgbe_fwd_adapter *accel;
9932 	int tcs = adapter->hw_tcs ? : 1;
9933 	int pool, err;
9934 
9935 	if (adapter->xdp_prog) {
9936 		e_warn(probe, "L2FW offload is not supported with XDP\n");
9937 		return ERR_PTR(-EINVAL);
9938 	}
9939 
9940 	/* The hardware supported by ixgbe only filters on the destination MAC
9941 	 * address. In order to avoid issues we only support offloading modes
9942 	 * where the hardware can actually provide the functionality.
9943 	 */
9944 	if (!macvlan_supports_dest_filter(vdev))
9945 		return ERR_PTR(-EMEDIUMTYPE);
9946 
9947 	/* We need to lock down the macvlan to be a single queue device so that
9948 	 * we can reuse the tc_to_txq field in the macvlan netdev to represent
9949 	 * the queue mapping to our netdev.
9950 	 */
9951 	if (netif_is_multiqueue(vdev))
9952 		return ERR_PTR(-ERANGE);
9953 
9954 	pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools);
9955 	if (pool == adapter->num_rx_pools) {
9956 		u16 used_pools = adapter->num_vfs + adapter->num_rx_pools;
9957 		u16 reserved_pools;
9958 
9959 		if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
9960 		     adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) ||
9961 		    adapter->num_rx_pools > IXGBE_MAX_MACVLANS)
9962 			return ERR_PTR(-EBUSY);
9963 
9964 		/* Hardware has a limited number of available pools. Each VF,
9965 		 * and the PF require a pool. Check to ensure we don't
9966 		 * attempt to use more then the available number of pools.
9967 		 */
9968 		if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
9969 			return ERR_PTR(-EBUSY);
9970 
9971 		/* Enable VMDq flag so device will be set in VM mode */
9972 		adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED |
9973 				  IXGBE_FLAG_SRIOV_ENABLED;
9974 
9975 		/* Try to reserve as many queues per pool as possible,
9976 		 * we start with the configurations that support 4 queues
9977 		 * per pools, followed by 2, and then by just 1 per pool.
9978 		 */
9979 		if (used_pools < 32 && adapter->num_rx_pools < 16)
9980 			reserved_pools = min_t(u16,
9981 					       32 - used_pools,
9982 					       16 - adapter->num_rx_pools);
9983 		else if (adapter->num_rx_pools < 32)
9984 			reserved_pools = min_t(u16,
9985 					       64 - used_pools,
9986 					       32 - adapter->num_rx_pools);
9987 		else
9988 			reserved_pools = 64 - used_pools;
9989 
9990 
9991 		if (!reserved_pools)
9992 			return ERR_PTR(-EBUSY);
9993 
9994 		adapter->ring_feature[RING_F_VMDQ].limit += reserved_pools;
9995 
9996 		/* Force reinit of ring allocation with VMDQ enabled */
9997 		err = ixgbe_setup_tc(pdev, adapter->hw_tcs);
9998 		if (err)
9999 			return ERR_PTR(err);
10000 
10001 		if (pool >= adapter->num_rx_pools)
10002 			return ERR_PTR(-ENOMEM);
10003 	}
10004 
10005 	accel = kzalloc(sizeof(*accel), GFP_KERNEL);
10006 	if (!accel)
10007 		return ERR_PTR(-ENOMEM);
10008 
10009 	set_bit(pool, adapter->fwd_bitmask);
10010 	netdev_set_sb_channel(vdev, pool);
10011 	accel->pool = pool;
10012 	accel->netdev = vdev;
10013 
10014 	if (!netif_running(pdev))
10015 		return accel;
10016 
10017 	err = ixgbe_fwd_ring_up(adapter, accel);
10018 	if (err)
10019 		return ERR_PTR(err);
10020 
10021 	return accel;
10022 }
10023 
10024 static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
10025 {
10026 	struct ixgbe_fwd_adapter *accel = priv;
10027 	struct ixgbe_adapter *adapter = netdev_priv(pdev);
10028 	unsigned int rxbase = accel->rx_base_queue;
10029 	unsigned int i;
10030 
10031 	/* delete unicast filter associated with offloaded interface */
10032 	ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr,
10033 			     VMDQ_P(accel->pool));
10034 
10035 	/* Allow remaining Rx packets to get flushed out of the
10036 	 * Rx FIFO before we drop the netdev for the ring.
10037 	 */
10038 	usleep_range(10000, 20000);
10039 
10040 	for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
10041 		struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i];
10042 		struct ixgbe_q_vector *qv = ring->q_vector;
10043 
10044 		/* Make sure we aren't processing any packets and clear
10045 		 * netdev to shut down the ring.
10046 		 */
10047 		if (netif_running(adapter->netdev))
10048 			napi_synchronize(&qv->napi);
10049 		ring->netdev = NULL;
10050 	}
10051 
10052 	/* unbind the queues and drop the subordinate channel config */
10053 	netdev_unbind_sb_channel(pdev, accel->netdev);
10054 	netdev_set_sb_channel(accel->netdev, 0);
10055 
10056 	clear_bit(accel->pool, adapter->fwd_bitmask);
10057 	kfree(accel);
10058 }
10059 
10060 #define IXGBE_MAX_MAC_HDR_LEN		127
10061 #define IXGBE_MAX_NETWORK_HDR_LEN	511
10062 
10063 static netdev_features_t
10064 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
10065 		     netdev_features_t features)
10066 {
10067 	unsigned int network_hdr_len, mac_hdr_len;
10068 
10069 	/* Make certain the headers can be described by a context descriptor */
10070 	mac_hdr_len = skb_network_header(skb) - skb->data;
10071 	if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN))
10072 		return features & ~(NETIF_F_HW_CSUM |
10073 				    NETIF_F_SCTP_CRC |
10074 				    NETIF_F_GSO_UDP_L4 |
10075 				    NETIF_F_HW_VLAN_CTAG_TX |
10076 				    NETIF_F_TSO |
10077 				    NETIF_F_TSO6);
10078 
10079 	network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
10080 	if (unlikely(network_hdr_len >  IXGBE_MAX_NETWORK_HDR_LEN))
10081 		return features & ~(NETIF_F_HW_CSUM |
10082 				    NETIF_F_SCTP_CRC |
10083 				    NETIF_F_GSO_UDP_L4 |
10084 				    NETIF_F_TSO |
10085 				    NETIF_F_TSO6);
10086 
10087 	/* We can only support IPV4 TSO in tunnels if we can mangle the
10088 	 * inner IP ID field, so strip TSO if MANGLEID is not supported.
10089 	 * IPsec offoad sets skb->encapsulation but still can handle
10090 	 * the TSO, so it's the exception.
10091 	 */
10092 	if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) {
10093 #ifdef CONFIG_IXGBE_IPSEC
10094 		if (!secpath_exists(skb))
10095 #endif
10096 			features &= ~NETIF_F_TSO;
10097 	}
10098 
10099 	return features;
10100 }
10101 
10102 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog)
10103 {
10104 	int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
10105 	struct ixgbe_adapter *adapter = netdev_priv(dev);
10106 	struct bpf_prog *old_prog;
10107 	bool need_reset;
10108 
10109 	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
10110 		return -EINVAL;
10111 
10112 	if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
10113 		return -EINVAL;
10114 
10115 	/* verify ixgbe ring attributes are sufficient for XDP */
10116 	for (i = 0; i < adapter->num_rx_queues; i++) {
10117 		struct ixgbe_ring *ring = adapter->rx_ring[i];
10118 
10119 		if (ring_is_rsc_enabled(ring))
10120 			return -EINVAL;
10121 
10122 		if (frame_size > ixgbe_rx_bufsz(ring))
10123 			return -EINVAL;
10124 	}
10125 
10126 	if (nr_cpu_ids > MAX_XDP_QUEUES)
10127 		return -ENOMEM;
10128 
10129 	old_prog = xchg(&adapter->xdp_prog, prog);
10130 	need_reset = (!!prog != !!old_prog);
10131 
10132 	/* If transitioning XDP modes reconfigure rings */
10133 	if (need_reset) {
10134 		int err;
10135 
10136 		if (!prog)
10137 			/* Wait until ndo_xsk_wakeup completes. */
10138 			synchronize_rcu();
10139 		err = ixgbe_setup_tc(dev, adapter->hw_tcs);
10140 
10141 		if (err) {
10142 			rcu_assign_pointer(adapter->xdp_prog, old_prog);
10143 			return -EINVAL;
10144 		}
10145 	} else {
10146 		for (i = 0; i < adapter->num_rx_queues; i++)
10147 			(void)xchg(&adapter->rx_ring[i]->xdp_prog,
10148 			    adapter->xdp_prog);
10149 	}
10150 
10151 	if (old_prog)
10152 		bpf_prog_put(old_prog);
10153 
10154 	/* Kick start the NAPI context if there is an AF_XDP socket open
10155 	 * on that queue id. This so that receiving will start.
10156 	 */
10157 	if (need_reset && prog)
10158 		for (i = 0; i < adapter->num_rx_queues; i++)
10159 			if (adapter->xdp_ring[i]->xsk_pool)
10160 				(void)ixgbe_xsk_wakeup(adapter->netdev, i,
10161 						       XDP_WAKEUP_RX);
10162 
10163 	return 0;
10164 }
10165 
10166 static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp)
10167 {
10168 	struct ixgbe_adapter *adapter = netdev_priv(dev);
10169 
10170 	switch (xdp->command) {
10171 	case XDP_SETUP_PROG:
10172 		return ixgbe_xdp_setup(dev, xdp->prog);
10173 	case XDP_SETUP_XSK_POOL:
10174 		return ixgbe_xsk_pool_setup(adapter, xdp->xsk.pool,
10175 					    xdp->xsk.queue_id);
10176 
10177 	default:
10178 		return -EINVAL;
10179 	}
10180 }
10181 
10182 void ixgbe_xdp_ring_update_tail(struct ixgbe_ring *ring)
10183 {
10184 	/* Force memory writes to complete before letting h/w know there
10185 	 * are new descriptors to fetch.
10186 	 */
10187 	wmb();
10188 	writel(ring->next_to_use, ring->tail);
10189 }
10190 
10191 static int ixgbe_xdp_xmit(struct net_device *dev, int n,
10192 			  struct xdp_frame **frames, u32 flags)
10193 {
10194 	struct ixgbe_adapter *adapter = netdev_priv(dev);
10195 	struct ixgbe_ring *ring;
10196 	int drops = 0;
10197 	int i;
10198 
10199 	if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state)))
10200 		return -ENETDOWN;
10201 
10202 	if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
10203 		return -EINVAL;
10204 
10205 	/* During program transitions its possible adapter->xdp_prog is assigned
10206 	 * but ring has not been configured yet. In this case simply abort xmit.
10207 	 */
10208 	ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL;
10209 	if (unlikely(!ring))
10210 		return -ENXIO;
10211 
10212 	if (unlikely(test_bit(__IXGBE_TX_DISABLED, &ring->state)))
10213 		return -ENXIO;
10214 
10215 	for (i = 0; i < n; i++) {
10216 		struct xdp_frame *xdpf = frames[i];
10217 		int err;
10218 
10219 		err = ixgbe_xmit_xdp_ring(adapter, xdpf);
10220 		if (err != IXGBE_XDP_TX) {
10221 			xdp_return_frame_rx_napi(xdpf);
10222 			drops++;
10223 		}
10224 	}
10225 
10226 	if (unlikely(flags & XDP_XMIT_FLUSH))
10227 		ixgbe_xdp_ring_update_tail(ring);
10228 
10229 	return n - drops;
10230 }
10231 
10232 static const struct net_device_ops ixgbe_netdev_ops = {
10233 	.ndo_open		= ixgbe_open,
10234 	.ndo_stop		= ixgbe_close,
10235 	.ndo_start_xmit		= ixgbe_xmit_frame,
10236 	.ndo_set_rx_mode	= ixgbe_set_rx_mode,
10237 	.ndo_validate_addr	= eth_validate_addr,
10238 	.ndo_set_mac_address	= ixgbe_set_mac,
10239 	.ndo_change_mtu		= ixgbe_change_mtu,
10240 	.ndo_tx_timeout		= ixgbe_tx_timeout,
10241 	.ndo_set_tx_maxrate	= ixgbe_tx_maxrate,
10242 	.ndo_vlan_rx_add_vid	= ixgbe_vlan_rx_add_vid,
10243 	.ndo_vlan_rx_kill_vid	= ixgbe_vlan_rx_kill_vid,
10244 	.ndo_do_ioctl		= ixgbe_ioctl,
10245 	.ndo_set_vf_mac		= ixgbe_ndo_set_vf_mac,
10246 	.ndo_set_vf_vlan	= ixgbe_ndo_set_vf_vlan,
10247 	.ndo_set_vf_rate	= ixgbe_ndo_set_vf_bw,
10248 	.ndo_set_vf_spoofchk	= ixgbe_ndo_set_vf_spoofchk,
10249 	.ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
10250 	.ndo_set_vf_trust	= ixgbe_ndo_set_vf_trust,
10251 	.ndo_get_vf_config	= ixgbe_ndo_get_vf_config,
10252 	.ndo_get_stats64	= ixgbe_get_stats64,
10253 	.ndo_setup_tc		= __ixgbe_setup_tc,
10254 #ifdef IXGBE_FCOE
10255 	.ndo_select_queue	= ixgbe_select_queue,
10256 	.ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
10257 	.ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
10258 	.ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
10259 	.ndo_fcoe_enable = ixgbe_fcoe_enable,
10260 	.ndo_fcoe_disable = ixgbe_fcoe_disable,
10261 	.ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
10262 	.ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
10263 #endif /* IXGBE_FCOE */
10264 	.ndo_set_features = ixgbe_set_features,
10265 	.ndo_fix_features = ixgbe_fix_features,
10266 	.ndo_fdb_add		= ixgbe_ndo_fdb_add,
10267 	.ndo_bridge_setlink	= ixgbe_ndo_bridge_setlink,
10268 	.ndo_bridge_getlink	= ixgbe_ndo_bridge_getlink,
10269 	.ndo_dfwd_add_station	= ixgbe_fwd_add,
10270 	.ndo_dfwd_del_station	= ixgbe_fwd_del,
10271 	.ndo_udp_tunnel_add	= udp_tunnel_nic_add_port,
10272 	.ndo_udp_tunnel_del	= udp_tunnel_nic_del_port,
10273 	.ndo_features_check	= ixgbe_features_check,
10274 	.ndo_bpf		= ixgbe_xdp,
10275 	.ndo_xdp_xmit		= ixgbe_xdp_xmit,
10276 	.ndo_xsk_wakeup         = ixgbe_xsk_wakeup,
10277 };
10278 
10279 static void ixgbe_disable_txr_hw(struct ixgbe_adapter *adapter,
10280 				 struct ixgbe_ring *tx_ring)
10281 {
10282 	unsigned long wait_delay, delay_interval;
10283 	struct ixgbe_hw *hw = &adapter->hw;
10284 	u8 reg_idx = tx_ring->reg_idx;
10285 	int wait_loop;
10286 	u32 txdctl;
10287 
10288 	IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
10289 
10290 	/* delay mechanism from ixgbe_disable_tx */
10291 	delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
10292 
10293 	wait_loop = IXGBE_MAX_RX_DESC_POLL;
10294 	wait_delay = delay_interval;
10295 
10296 	while (wait_loop--) {
10297 		usleep_range(wait_delay, wait_delay + 10);
10298 		wait_delay += delay_interval * 2;
10299 		txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
10300 
10301 		if (!(txdctl & IXGBE_TXDCTL_ENABLE))
10302 			return;
10303 	}
10304 
10305 	e_err(drv, "TXDCTL.ENABLE not cleared within the polling period\n");
10306 }
10307 
10308 static void ixgbe_disable_txr(struct ixgbe_adapter *adapter,
10309 			      struct ixgbe_ring *tx_ring)
10310 {
10311 	set_bit(__IXGBE_TX_DISABLED, &tx_ring->state);
10312 	ixgbe_disable_txr_hw(adapter, tx_ring);
10313 }
10314 
10315 static void ixgbe_disable_rxr_hw(struct ixgbe_adapter *adapter,
10316 				 struct ixgbe_ring *rx_ring)
10317 {
10318 	unsigned long wait_delay, delay_interval;
10319 	struct ixgbe_hw *hw = &adapter->hw;
10320 	u8 reg_idx = rx_ring->reg_idx;
10321 	int wait_loop;
10322 	u32 rxdctl;
10323 
10324 	rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
10325 	rxdctl &= ~IXGBE_RXDCTL_ENABLE;
10326 	rxdctl |= IXGBE_RXDCTL_SWFLSH;
10327 
10328 	/* write value back with RXDCTL.ENABLE bit cleared */
10329 	IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
10330 
10331 	/* RXDCTL.EN may not change on 82598 if link is down, so skip it */
10332 	if (hw->mac.type == ixgbe_mac_82598EB &&
10333 	    !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
10334 		return;
10335 
10336 	/* delay mechanism from ixgbe_disable_rx */
10337 	delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
10338 
10339 	wait_loop = IXGBE_MAX_RX_DESC_POLL;
10340 	wait_delay = delay_interval;
10341 
10342 	while (wait_loop--) {
10343 		usleep_range(wait_delay, wait_delay + 10);
10344 		wait_delay += delay_interval * 2;
10345 		rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
10346 
10347 		if (!(rxdctl & IXGBE_RXDCTL_ENABLE))
10348 			return;
10349 	}
10350 
10351 	e_err(drv, "RXDCTL.ENABLE not cleared within the polling period\n");
10352 }
10353 
10354 static void ixgbe_reset_txr_stats(struct ixgbe_ring *tx_ring)
10355 {
10356 	memset(&tx_ring->stats, 0, sizeof(tx_ring->stats));
10357 	memset(&tx_ring->tx_stats, 0, sizeof(tx_ring->tx_stats));
10358 }
10359 
10360 static void ixgbe_reset_rxr_stats(struct ixgbe_ring *rx_ring)
10361 {
10362 	memset(&rx_ring->stats, 0, sizeof(rx_ring->stats));
10363 	memset(&rx_ring->rx_stats, 0, sizeof(rx_ring->rx_stats));
10364 }
10365 
10366 /**
10367  * ixgbe_txrx_ring_disable - Disable Rx/Tx/XDP Tx rings
10368  * @adapter: adapter structure
10369  * @ring: ring index
10370  *
10371  * This function disables a certain Rx/Tx/XDP Tx ring. The function
10372  * assumes that the netdev is running.
10373  **/
10374 void ixgbe_txrx_ring_disable(struct ixgbe_adapter *adapter, int ring)
10375 {
10376 	struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring;
10377 
10378 	rx_ring = adapter->rx_ring[ring];
10379 	tx_ring = adapter->tx_ring[ring];
10380 	xdp_ring = adapter->xdp_ring[ring];
10381 
10382 	ixgbe_disable_txr(adapter, tx_ring);
10383 	if (xdp_ring)
10384 		ixgbe_disable_txr(adapter, xdp_ring);
10385 	ixgbe_disable_rxr_hw(adapter, rx_ring);
10386 
10387 	if (xdp_ring)
10388 		synchronize_rcu();
10389 
10390 	/* Rx/Tx/XDP Tx share the same napi context. */
10391 	napi_disable(&rx_ring->q_vector->napi);
10392 
10393 	ixgbe_clean_tx_ring(tx_ring);
10394 	if (xdp_ring)
10395 		ixgbe_clean_tx_ring(xdp_ring);
10396 	ixgbe_clean_rx_ring(rx_ring);
10397 
10398 	ixgbe_reset_txr_stats(tx_ring);
10399 	if (xdp_ring)
10400 		ixgbe_reset_txr_stats(xdp_ring);
10401 	ixgbe_reset_rxr_stats(rx_ring);
10402 }
10403 
10404 /**
10405  * ixgbe_txrx_ring_enable - Enable Rx/Tx/XDP Tx rings
10406  * @adapter: adapter structure
10407  * @ring: ring index
10408  *
10409  * This function enables a certain Rx/Tx/XDP Tx ring. The function
10410  * assumes that the netdev is running.
10411  **/
10412 void ixgbe_txrx_ring_enable(struct ixgbe_adapter *adapter, int ring)
10413 {
10414 	struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring;
10415 
10416 	rx_ring = adapter->rx_ring[ring];
10417 	tx_ring = adapter->tx_ring[ring];
10418 	xdp_ring = adapter->xdp_ring[ring];
10419 
10420 	/* Rx/Tx/XDP Tx share the same napi context. */
10421 	napi_enable(&rx_ring->q_vector->napi);
10422 
10423 	ixgbe_configure_tx_ring(adapter, tx_ring);
10424 	if (xdp_ring)
10425 		ixgbe_configure_tx_ring(adapter, xdp_ring);
10426 	ixgbe_configure_rx_ring(adapter, rx_ring);
10427 
10428 	clear_bit(__IXGBE_TX_DISABLED, &tx_ring->state);
10429 	if (xdp_ring)
10430 		clear_bit(__IXGBE_TX_DISABLED, &xdp_ring->state);
10431 }
10432 
10433 /**
10434  * ixgbe_enumerate_functions - Get the number of ports this device has
10435  * @adapter: adapter structure
10436  *
10437  * This function enumerates the phsyical functions co-located on a single slot,
10438  * in order to determine how many ports a device has. This is most useful in
10439  * determining the required GT/s of PCIe bandwidth necessary for optimal
10440  * performance.
10441  **/
10442 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
10443 {
10444 	struct pci_dev *entry, *pdev = adapter->pdev;
10445 	int physfns = 0;
10446 
10447 	/* Some cards can not use the generic count PCIe functions method,
10448 	 * because they are behind a parent switch, so we hardcode these with
10449 	 * the correct number of functions.
10450 	 */
10451 	if (ixgbe_pcie_from_parent(&adapter->hw))
10452 		physfns = 4;
10453 
10454 	list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
10455 		/* don't count virtual functions */
10456 		if (entry->is_virtfn)
10457 			continue;
10458 
10459 		/* When the devices on the bus don't all match our device ID,
10460 		 * we can't reliably determine the correct number of
10461 		 * functions. This can occur if a function has been direct
10462 		 * attached to a virtual machine using VT-d, for example. In
10463 		 * this case, simply return -1 to indicate this.
10464 		 */
10465 		if ((entry->vendor != pdev->vendor) ||
10466 		    (entry->device != pdev->device))
10467 			return -1;
10468 
10469 		physfns++;
10470 	}
10471 
10472 	return physfns;
10473 }
10474 
10475 /**
10476  * ixgbe_wol_supported - Check whether device supports WoL
10477  * @adapter: the adapter private structure
10478  * @device_id: the device ID
10479  * @subdevice_id: the subsystem device ID
10480  *
10481  * This function is used by probe and ethtool to determine
10482  * which devices have WoL support
10483  *
10484  **/
10485 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
10486 			 u16 subdevice_id)
10487 {
10488 	struct ixgbe_hw *hw = &adapter->hw;
10489 	u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
10490 
10491 	/* WOL not supported on 82598 */
10492 	if (hw->mac.type == ixgbe_mac_82598EB)
10493 		return false;
10494 
10495 	/* check eeprom to see if WOL is enabled for X540 and newer */
10496 	if (hw->mac.type >= ixgbe_mac_X540) {
10497 		if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
10498 		    ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
10499 		     (hw->bus.func == 0)))
10500 			return true;
10501 	}
10502 
10503 	/* WOL is determined based on device IDs for 82599 MACs */
10504 	switch (device_id) {
10505 	case IXGBE_DEV_ID_82599_SFP:
10506 		/* Only these subdevices could supports WOL */
10507 		switch (subdevice_id) {
10508 		case IXGBE_SUBDEV_ID_82599_560FLR:
10509 		case IXGBE_SUBDEV_ID_82599_LOM_SNAP6:
10510 		case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
10511 		case IXGBE_SUBDEV_ID_82599_SFP_2OCP:
10512 			/* only support first port */
10513 			if (hw->bus.func != 0)
10514 				break;
10515 			fallthrough;
10516 		case IXGBE_SUBDEV_ID_82599_SP_560FLR:
10517 		case IXGBE_SUBDEV_ID_82599_SFP:
10518 		case IXGBE_SUBDEV_ID_82599_RNDC:
10519 		case IXGBE_SUBDEV_ID_82599_ECNA_DP:
10520 		case IXGBE_SUBDEV_ID_82599_SFP_1OCP:
10521 		case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1:
10522 		case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2:
10523 			return true;
10524 		}
10525 		break;
10526 	case IXGBE_DEV_ID_82599EN_SFP:
10527 		/* Only these subdevices support WOL */
10528 		switch (subdevice_id) {
10529 		case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
10530 			return true;
10531 		}
10532 		break;
10533 	case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
10534 		/* All except this subdevice support WOL */
10535 		if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
10536 			return true;
10537 		break;
10538 	case IXGBE_DEV_ID_82599_KX4:
10539 		return  true;
10540 	default:
10541 		break;
10542 	}
10543 
10544 	return false;
10545 }
10546 
10547 /**
10548  * ixgbe_set_fw_version - Set FW version
10549  * @adapter: the adapter private structure
10550  *
10551  * This function is used by probe and ethtool to determine the FW version to
10552  * format to display. The FW version is taken from the EEPROM/NVM.
10553  */
10554 static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter)
10555 {
10556 	struct ixgbe_hw *hw = &adapter->hw;
10557 	struct ixgbe_nvm_version nvm_ver;
10558 
10559 	ixgbe_get_oem_prod_version(hw, &nvm_ver);
10560 	if (nvm_ver.oem_valid) {
10561 		snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10562 			 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor,
10563 			 nvm_ver.oem_release);
10564 		return;
10565 	}
10566 
10567 	ixgbe_get_etk_id(hw, &nvm_ver);
10568 	ixgbe_get_orom_version(hw, &nvm_ver);
10569 
10570 	if (nvm_ver.or_valid) {
10571 		snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10572 			 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major,
10573 			 nvm_ver.or_build, nvm_ver.or_patch);
10574 		return;
10575 	}
10576 
10577 	/* Set ETrack ID format */
10578 	snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10579 		 "0x%08x", nvm_ver.etk_id);
10580 }
10581 
10582 /**
10583  * ixgbe_probe - Device Initialization Routine
10584  * @pdev: PCI device information struct
10585  * @ent: entry in ixgbe_pci_tbl
10586  *
10587  * Returns 0 on success, negative on failure
10588  *
10589  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
10590  * The OS initialization, configuring of the adapter private structure,
10591  * and a hardware reset occur.
10592  **/
10593 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10594 {
10595 	struct net_device *netdev;
10596 	struct ixgbe_adapter *adapter = NULL;
10597 	struct ixgbe_hw *hw;
10598 	const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
10599 	int i, err, pci_using_dac, expected_gts;
10600 	unsigned int indices = MAX_TX_QUEUES;
10601 	u8 part_str[IXGBE_PBANUM_LENGTH];
10602 	bool disable_dev = false;
10603 #ifdef IXGBE_FCOE
10604 	u16 device_caps;
10605 #endif
10606 	u32 eec;
10607 
10608 	/* Catch broken hardware that put the wrong VF device ID in
10609 	 * the PCIe SR-IOV capability.
10610 	 */
10611 	if (pdev->is_virtfn) {
10612 		WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
10613 		     pci_name(pdev), pdev->vendor, pdev->device);
10614 		return -EINVAL;
10615 	}
10616 
10617 	err = pci_enable_device_mem(pdev);
10618 	if (err)
10619 		return err;
10620 
10621 	if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
10622 		pci_using_dac = 1;
10623 	} else {
10624 		err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10625 		if (err) {
10626 			dev_err(&pdev->dev,
10627 				"No usable DMA configuration, aborting\n");
10628 			goto err_dma;
10629 		}
10630 		pci_using_dac = 0;
10631 	}
10632 
10633 	err = pci_request_mem_regions(pdev, ixgbe_driver_name);
10634 	if (err) {
10635 		dev_err(&pdev->dev,
10636 			"pci_request_selected_regions failed 0x%x\n", err);
10637 		goto err_pci_reg;
10638 	}
10639 
10640 	pci_enable_pcie_error_reporting(pdev);
10641 
10642 	pci_set_master(pdev);
10643 	pci_save_state(pdev);
10644 
10645 	if (ii->mac == ixgbe_mac_82598EB) {
10646 #ifdef CONFIG_IXGBE_DCB
10647 		/* 8 TC w/ 4 queues per TC */
10648 		indices = 4 * MAX_TRAFFIC_CLASS;
10649 #else
10650 		indices = IXGBE_MAX_RSS_INDICES;
10651 #endif
10652 	}
10653 
10654 	netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
10655 	if (!netdev) {
10656 		err = -ENOMEM;
10657 		goto err_alloc_etherdev;
10658 	}
10659 
10660 	SET_NETDEV_DEV(netdev, &pdev->dev);
10661 
10662 	adapter = netdev_priv(netdev);
10663 
10664 	adapter->netdev = netdev;
10665 	adapter->pdev = pdev;
10666 	hw = &adapter->hw;
10667 	hw->back = adapter;
10668 	adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
10669 
10670 	hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
10671 			      pci_resource_len(pdev, 0));
10672 	adapter->io_addr = hw->hw_addr;
10673 	if (!hw->hw_addr) {
10674 		err = -EIO;
10675 		goto err_ioremap;
10676 	}
10677 
10678 	netdev->netdev_ops = &ixgbe_netdev_ops;
10679 	ixgbe_set_ethtool_ops(netdev);
10680 	netdev->watchdog_timeo = 5 * HZ;
10681 	strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
10682 
10683 	/* Setup hw api */
10684 	hw->mac.ops   = *ii->mac_ops;
10685 	hw->mac.type  = ii->mac;
10686 	hw->mvals     = ii->mvals;
10687 	if (ii->link_ops)
10688 		hw->link.ops  = *ii->link_ops;
10689 
10690 	/* EEPROM */
10691 	hw->eeprom.ops = *ii->eeprom_ops;
10692 	eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
10693 	if (ixgbe_removed(hw->hw_addr)) {
10694 		err = -EIO;
10695 		goto err_ioremap;
10696 	}
10697 	/* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
10698 	if (!(eec & BIT(8)))
10699 		hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
10700 
10701 	/* PHY */
10702 	hw->phy.ops = *ii->phy_ops;
10703 	hw->phy.sfp_type = ixgbe_sfp_type_unknown;
10704 	/* ixgbe_identify_phy_generic will set prtad and mmds properly */
10705 	hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
10706 	hw->phy.mdio.mmds = 0;
10707 	hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10708 	hw->phy.mdio.dev = netdev;
10709 	hw->phy.mdio.mdio_read = ixgbe_mdio_read;
10710 	hw->phy.mdio.mdio_write = ixgbe_mdio_write;
10711 
10712 	/* setup the private structure */
10713 	err = ixgbe_sw_init(adapter, ii);
10714 	if (err)
10715 		goto err_sw_init;
10716 
10717 	switch (adapter->hw.mac.type) {
10718 	case ixgbe_mac_X550:
10719 	case ixgbe_mac_X550EM_x:
10720 		netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550;
10721 		break;
10722 	case ixgbe_mac_x550em_a:
10723 		netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550em_a;
10724 		break;
10725 	default:
10726 		break;
10727 	}
10728 
10729 	/* Make sure the SWFW semaphore is in a valid state */
10730 	if (hw->mac.ops.init_swfw_sync)
10731 		hw->mac.ops.init_swfw_sync(hw);
10732 
10733 	/* Make it possible the adapter to be woken up via WOL */
10734 	switch (adapter->hw.mac.type) {
10735 	case ixgbe_mac_82599EB:
10736 	case ixgbe_mac_X540:
10737 	case ixgbe_mac_X550:
10738 	case ixgbe_mac_X550EM_x:
10739 	case ixgbe_mac_x550em_a:
10740 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
10741 		break;
10742 	default:
10743 		break;
10744 	}
10745 
10746 	/*
10747 	 * If there is a fan on this device and it has failed log the
10748 	 * failure.
10749 	 */
10750 	if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
10751 		u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
10752 		if (esdp & IXGBE_ESDP_SDP1)
10753 			e_crit(probe, "Fan has stopped, replace the adapter\n");
10754 	}
10755 
10756 	if (allow_unsupported_sfp)
10757 		hw->allow_unsupported_sfp = allow_unsupported_sfp;
10758 
10759 	/* reset_hw fills in the perm_addr as well */
10760 	hw->phy.reset_if_overtemp = true;
10761 	err = hw->mac.ops.reset_hw(hw);
10762 	hw->phy.reset_if_overtemp = false;
10763 	ixgbe_set_eee_capable(adapter);
10764 	if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
10765 		err = 0;
10766 	} else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
10767 		e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
10768 		e_dev_err("Reload the driver after installing a supported module.\n");
10769 		goto err_sw_init;
10770 	} else if (err) {
10771 		e_dev_err("HW Init failed: %d\n", err);
10772 		goto err_sw_init;
10773 	}
10774 
10775 #ifdef CONFIG_PCI_IOV
10776 	/* SR-IOV not supported on the 82598 */
10777 	if (adapter->hw.mac.type == ixgbe_mac_82598EB)
10778 		goto skip_sriov;
10779 	/* Mailbox */
10780 	ixgbe_init_mbx_params_pf(hw);
10781 	hw->mbx.ops = ii->mbx_ops;
10782 	pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
10783 	ixgbe_enable_sriov(adapter, max_vfs);
10784 skip_sriov:
10785 
10786 #endif
10787 	netdev->features = NETIF_F_SG |
10788 			   NETIF_F_TSO |
10789 			   NETIF_F_TSO6 |
10790 			   NETIF_F_RXHASH |
10791 			   NETIF_F_RXCSUM |
10792 			   NETIF_F_HW_CSUM;
10793 
10794 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
10795 				    NETIF_F_GSO_GRE_CSUM | \
10796 				    NETIF_F_GSO_IPXIP4 | \
10797 				    NETIF_F_GSO_IPXIP6 | \
10798 				    NETIF_F_GSO_UDP_TUNNEL | \
10799 				    NETIF_F_GSO_UDP_TUNNEL_CSUM)
10800 
10801 	netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES;
10802 	netdev->features |= NETIF_F_GSO_PARTIAL |
10803 			    IXGBE_GSO_PARTIAL_FEATURES;
10804 
10805 	if (hw->mac.type >= ixgbe_mac_82599EB)
10806 		netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4;
10807 
10808 #ifdef CONFIG_IXGBE_IPSEC
10809 #define IXGBE_ESP_FEATURES	(NETIF_F_HW_ESP | \
10810 				 NETIF_F_HW_ESP_TX_CSUM | \
10811 				 NETIF_F_GSO_ESP)
10812 
10813 	if (adapter->ipsec)
10814 		netdev->features |= IXGBE_ESP_FEATURES;
10815 #endif
10816 	/* copy netdev features into list of user selectable features */
10817 	netdev->hw_features |= netdev->features |
10818 			       NETIF_F_HW_VLAN_CTAG_FILTER |
10819 			       NETIF_F_HW_VLAN_CTAG_RX |
10820 			       NETIF_F_HW_VLAN_CTAG_TX |
10821 			       NETIF_F_RXALL |
10822 			       NETIF_F_HW_L2FW_DOFFLOAD;
10823 
10824 	if (hw->mac.type >= ixgbe_mac_82599EB)
10825 		netdev->hw_features |= NETIF_F_NTUPLE |
10826 				       NETIF_F_HW_TC;
10827 
10828 	if (pci_using_dac)
10829 		netdev->features |= NETIF_F_HIGHDMA;
10830 
10831 	netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
10832 	netdev->hw_enc_features |= netdev->vlan_features;
10833 	netdev->mpls_features |= NETIF_F_SG |
10834 				 NETIF_F_TSO |
10835 				 NETIF_F_TSO6 |
10836 				 NETIF_F_HW_CSUM;
10837 	netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES;
10838 
10839 	/* set this bit last since it cannot be part of vlan_features */
10840 	netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
10841 			    NETIF_F_HW_VLAN_CTAG_RX |
10842 			    NETIF_F_HW_VLAN_CTAG_TX;
10843 
10844 	netdev->priv_flags |= IFF_UNICAST_FLT;
10845 	netdev->priv_flags |= IFF_SUPP_NOFCS;
10846 
10847 	/* MTU range: 68 - 9710 */
10848 	netdev->min_mtu = ETH_MIN_MTU;
10849 	netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN);
10850 
10851 #ifdef CONFIG_IXGBE_DCB
10852 	if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE)
10853 		netdev->dcbnl_ops = &ixgbe_dcbnl_ops;
10854 #endif
10855 
10856 #ifdef IXGBE_FCOE
10857 	if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
10858 		unsigned int fcoe_l;
10859 
10860 		if (hw->mac.ops.get_device_caps) {
10861 			hw->mac.ops.get_device_caps(hw, &device_caps);
10862 			if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
10863 				adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
10864 		}
10865 
10866 
10867 		fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
10868 		adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
10869 
10870 		netdev->features |= NETIF_F_FSO |
10871 				    NETIF_F_FCOE_CRC;
10872 
10873 		netdev->vlan_features |= NETIF_F_FSO |
10874 					 NETIF_F_FCOE_CRC |
10875 					 NETIF_F_FCOE_MTU;
10876 	}
10877 #endif /* IXGBE_FCOE */
10878 	if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
10879 		netdev->hw_features |= NETIF_F_LRO;
10880 	if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
10881 		netdev->features |= NETIF_F_LRO;
10882 
10883 	if (ixgbe_check_fw_error(adapter)) {
10884 		err = -EIO;
10885 		goto err_sw_init;
10886 	}
10887 
10888 	/* make sure the EEPROM is good */
10889 	if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
10890 		e_dev_err("The EEPROM Checksum Is Not Valid\n");
10891 		err = -EIO;
10892 		goto err_sw_init;
10893 	}
10894 
10895 	eth_platform_get_mac_address(&adapter->pdev->dev,
10896 				     adapter->hw.mac.perm_addr);
10897 
10898 	memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
10899 
10900 	if (!is_valid_ether_addr(netdev->dev_addr)) {
10901 		e_dev_err("invalid MAC address\n");
10902 		err = -EIO;
10903 		goto err_sw_init;
10904 	}
10905 
10906 	/* Set hw->mac.addr to permanent MAC address */
10907 	ether_addr_copy(hw->mac.addr, hw->mac.perm_addr);
10908 	ixgbe_mac_set_default_filter(adapter);
10909 
10910 	timer_setup(&adapter->service_timer, ixgbe_service_timer, 0);
10911 
10912 	if (ixgbe_removed(hw->hw_addr)) {
10913 		err = -EIO;
10914 		goto err_sw_init;
10915 	}
10916 	INIT_WORK(&adapter->service_task, ixgbe_service_task);
10917 	set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
10918 	clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
10919 
10920 	err = ixgbe_init_interrupt_scheme(adapter);
10921 	if (err)
10922 		goto err_sw_init;
10923 
10924 	for (i = 0; i < adapter->num_rx_queues; i++)
10925 		u64_stats_init(&adapter->rx_ring[i]->syncp);
10926 	for (i = 0; i < adapter->num_tx_queues; i++)
10927 		u64_stats_init(&adapter->tx_ring[i]->syncp);
10928 	for (i = 0; i < adapter->num_xdp_queues; i++)
10929 		u64_stats_init(&adapter->xdp_ring[i]->syncp);
10930 
10931 	/* WOL not supported for all devices */
10932 	adapter->wol = 0;
10933 	hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
10934 	hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
10935 						pdev->subsystem_device);
10936 	if (hw->wol_enabled)
10937 		adapter->wol = IXGBE_WUFC_MAG;
10938 
10939 	device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
10940 
10941 	/* save off EEPROM version number */
10942 	ixgbe_set_fw_version(adapter);
10943 
10944 	/* pick up the PCI bus settings for reporting later */
10945 	if (ixgbe_pcie_from_parent(hw))
10946 		ixgbe_get_parent_bus_info(adapter);
10947 	else
10948 		 hw->mac.ops.get_bus_info(hw);
10949 
10950 	/* calculate the expected PCIe bandwidth required for optimal
10951 	 * performance. Note that some older parts will never have enough
10952 	 * bandwidth due to being older generation PCIe parts. We clamp these
10953 	 * parts to ensure no warning is displayed if it can't be fixed.
10954 	 */
10955 	switch (hw->mac.type) {
10956 	case ixgbe_mac_82598EB:
10957 		expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
10958 		break;
10959 	default:
10960 		expected_gts = ixgbe_enumerate_functions(adapter) * 10;
10961 		break;
10962 	}
10963 
10964 	/* don't check link if we failed to enumerate functions */
10965 	if (expected_gts > 0)
10966 		ixgbe_check_minimum_link(adapter, expected_gts);
10967 
10968 	err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
10969 	if (err)
10970 		strlcpy(part_str, "Unknown", sizeof(part_str));
10971 	if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
10972 		e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
10973 			   hw->mac.type, hw->phy.type, hw->phy.sfp_type,
10974 			   part_str);
10975 	else
10976 		e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
10977 			   hw->mac.type, hw->phy.type, part_str);
10978 
10979 	e_dev_info("%pM\n", netdev->dev_addr);
10980 
10981 	/* reset the hardware with the new settings */
10982 	err = hw->mac.ops.start_hw(hw);
10983 	if (err == IXGBE_ERR_EEPROM_VERSION) {
10984 		/* We are running on a pre-production device, log a warning */
10985 		e_dev_warn("This device is a pre-production adapter/LOM. "
10986 			   "Please be aware there may be issues associated "
10987 			   "with your hardware.  If you are experiencing "
10988 			   "problems please contact your Intel or hardware "
10989 			   "representative who provided you with this "
10990 			   "hardware.\n");
10991 	}
10992 	strcpy(netdev->name, "eth%d");
10993 	pci_set_drvdata(pdev, adapter);
10994 	err = register_netdev(netdev);
10995 	if (err)
10996 		goto err_register;
10997 
10998 
10999 	/* power down the optics for 82599 SFP+ fiber */
11000 	if (hw->mac.ops.disable_tx_laser)
11001 		hw->mac.ops.disable_tx_laser(hw);
11002 
11003 	/* carrier off reporting is important to ethtool even BEFORE open */
11004 	netif_carrier_off(netdev);
11005 
11006 #ifdef CONFIG_IXGBE_DCA
11007 	if (dca_add_requester(&pdev->dev) == 0) {
11008 		adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
11009 		ixgbe_setup_dca(adapter);
11010 	}
11011 #endif
11012 	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
11013 		e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
11014 		for (i = 0; i < adapter->num_vfs; i++)
11015 			ixgbe_vf_configuration(pdev, (i | 0x10000000));
11016 	}
11017 
11018 	/* firmware requires driver version to be 0xFFFFFFFF
11019 	 * since os does not support feature
11020 	 */
11021 	if (hw->mac.ops.set_fw_drv_ver)
11022 		hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF,
11023 					   sizeof(UTS_RELEASE) - 1,
11024 					   UTS_RELEASE);
11025 
11026 	/* add san mac addr to netdev */
11027 	ixgbe_add_sanmac_netdev(netdev);
11028 
11029 	e_dev_info("%s\n", ixgbe_default_device_descr);
11030 
11031 #ifdef CONFIG_IXGBE_HWMON
11032 	if (ixgbe_sysfs_init(adapter))
11033 		e_err(probe, "failed to allocate sysfs resources\n");
11034 #endif /* CONFIG_IXGBE_HWMON */
11035 
11036 	ixgbe_dbg_adapter_init(adapter);
11037 
11038 	/* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
11039 	if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
11040 		hw->mac.ops.setup_link(hw,
11041 			IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
11042 			true);
11043 
11044 	err = ixgbe_mii_bus_init(hw);
11045 	if (err)
11046 		goto err_netdev;
11047 
11048 	return 0;
11049 
11050 err_netdev:
11051 	unregister_netdev(netdev);
11052 err_register:
11053 	ixgbe_release_hw_control(adapter);
11054 	ixgbe_clear_interrupt_scheme(adapter);
11055 err_sw_init:
11056 	ixgbe_disable_sriov(adapter);
11057 	adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
11058 	iounmap(adapter->io_addr);
11059 	kfree(adapter->jump_tables[0]);
11060 	kfree(adapter->mac_table);
11061 	kfree(adapter->rss_key);
11062 	bitmap_free(adapter->af_xdp_zc_qps);
11063 err_ioremap:
11064 	disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
11065 	free_netdev(netdev);
11066 err_alloc_etherdev:
11067 	pci_release_mem_regions(pdev);
11068 err_pci_reg:
11069 err_dma:
11070 	if (!adapter || disable_dev)
11071 		pci_disable_device(pdev);
11072 	return err;
11073 }
11074 
11075 /**
11076  * ixgbe_remove - Device Removal Routine
11077  * @pdev: PCI device information struct
11078  *
11079  * ixgbe_remove is called by the PCI subsystem to alert the driver
11080  * that it should release a PCI device.  The could be caused by a
11081  * Hot-Plug event, or because the driver is going to be removed from
11082  * memory.
11083  **/
11084 static void ixgbe_remove(struct pci_dev *pdev)
11085 {
11086 	struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11087 	struct net_device *netdev;
11088 	bool disable_dev;
11089 	int i;
11090 
11091 	/* if !adapter then we already cleaned up in probe */
11092 	if (!adapter)
11093 		return;
11094 
11095 	netdev  = adapter->netdev;
11096 	ixgbe_dbg_adapter_exit(adapter);
11097 
11098 	set_bit(__IXGBE_REMOVING, &adapter->state);
11099 	cancel_work_sync(&adapter->service_task);
11100 
11101 	if (adapter->mii_bus)
11102 		mdiobus_unregister(adapter->mii_bus);
11103 
11104 #ifdef CONFIG_IXGBE_DCA
11105 	if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
11106 		adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
11107 		dca_remove_requester(&pdev->dev);
11108 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
11109 				IXGBE_DCA_CTRL_DCA_DISABLE);
11110 	}
11111 
11112 #endif
11113 #ifdef CONFIG_IXGBE_HWMON
11114 	ixgbe_sysfs_exit(adapter);
11115 #endif /* CONFIG_IXGBE_HWMON */
11116 
11117 	/* remove the added san mac */
11118 	ixgbe_del_sanmac_netdev(netdev);
11119 
11120 #ifdef CONFIG_PCI_IOV
11121 	ixgbe_disable_sriov(adapter);
11122 #endif
11123 	if (netdev->reg_state == NETREG_REGISTERED)
11124 		unregister_netdev(netdev);
11125 
11126 	ixgbe_stop_ipsec_offload(adapter);
11127 	ixgbe_clear_interrupt_scheme(adapter);
11128 
11129 	ixgbe_release_hw_control(adapter);
11130 
11131 #ifdef CONFIG_DCB
11132 	kfree(adapter->ixgbe_ieee_pfc);
11133 	kfree(adapter->ixgbe_ieee_ets);
11134 
11135 #endif
11136 	iounmap(adapter->io_addr);
11137 	pci_release_mem_regions(pdev);
11138 
11139 	e_dev_info("complete\n");
11140 
11141 	for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) {
11142 		if (adapter->jump_tables[i]) {
11143 			kfree(adapter->jump_tables[i]->input);
11144 			kfree(adapter->jump_tables[i]->mask);
11145 		}
11146 		kfree(adapter->jump_tables[i]);
11147 	}
11148 
11149 	kfree(adapter->mac_table);
11150 	kfree(adapter->rss_key);
11151 	bitmap_free(adapter->af_xdp_zc_qps);
11152 	disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
11153 	free_netdev(netdev);
11154 
11155 	pci_disable_pcie_error_reporting(pdev);
11156 
11157 	if (disable_dev)
11158 		pci_disable_device(pdev);
11159 }
11160 
11161 /**
11162  * ixgbe_io_error_detected - called when PCI error is detected
11163  * @pdev: Pointer to PCI device
11164  * @state: The current pci connection state
11165  *
11166  * This function is called after a PCI bus error affecting
11167  * this device has been detected.
11168  */
11169 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
11170 						pci_channel_state_t state)
11171 {
11172 	struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11173 	struct net_device *netdev = adapter->netdev;
11174 
11175 #ifdef CONFIG_PCI_IOV
11176 	struct ixgbe_hw *hw = &adapter->hw;
11177 	struct pci_dev *bdev, *vfdev;
11178 	u32 dw0, dw1, dw2, dw3;
11179 	int vf, pos;
11180 	u16 req_id, pf_func;
11181 
11182 	if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
11183 	    adapter->num_vfs == 0)
11184 		goto skip_bad_vf_detection;
11185 
11186 	bdev = pdev->bus->self;
11187 	while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
11188 		bdev = bdev->bus->self;
11189 
11190 	if (!bdev)
11191 		goto skip_bad_vf_detection;
11192 
11193 	pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
11194 	if (!pos)
11195 		goto skip_bad_vf_detection;
11196 
11197 	dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
11198 	dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
11199 	dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
11200 	dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
11201 	if (ixgbe_removed(hw->hw_addr))
11202 		goto skip_bad_vf_detection;
11203 
11204 	req_id = dw1 >> 16;
11205 	/* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
11206 	if (!(req_id & 0x0080))
11207 		goto skip_bad_vf_detection;
11208 
11209 	pf_func = req_id & 0x01;
11210 	if ((pf_func & 1) == (pdev->devfn & 1)) {
11211 		unsigned int device_id;
11212 
11213 		vf = (req_id & 0x7F) >> 1;
11214 		e_dev_err("VF %d has caused a PCIe error\n", vf);
11215 		e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
11216 				"%8.8x\tdw3: %8.8x\n",
11217 		dw0, dw1, dw2, dw3);
11218 		switch (adapter->hw.mac.type) {
11219 		case ixgbe_mac_82599EB:
11220 			device_id = IXGBE_82599_VF_DEVICE_ID;
11221 			break;
11222 		case ixgbe_mac_X540:
11223 			device_id = IXGBE_X540_VF_DEVICE_ID;
11224 			break;
11225 		case ixgbe_mac_X550:
11226 			device_id = IXGBE_DEV_ID_X550_VF;
11227 			break;
11228 		case ixgbe_mac_X550EM_x:
11229 			device_id = IXGBE_DEV_ID_X550EM_X_VF;
11230 			break;
11231 		case ixgbe_mac_x550em_a:
11232 			device_id = IXGBE_DEV_ID_X550EM_A_VF;
11233 			break;
11234 		default:
11235 			device_id = 0;
11236 			break;
11237 		}
11238 
11239 		/* Find the pci device of the offending VF */
11240 		vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
11241 		while (vfdev) {
11242 			if (vfdev->devfn == (req_id & 0xFF))
11243 				break;
11244 			vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
11245 					       device_id, vfdev);
11246 		}
11247 		/*
11248 		 * There's a slim chance the VF could have been hot plugged,
11249 		 * so if it is no longer present we don't need to issue the
11250 		 * VFLR.  Just clean up the AER in that case.
11251 		 */
11252 		if (vfdev) {
11253 			pcie_flr(vfdev);
11254 			/* Free device reference count */
11255 			pci_dev_put(vfdev);
11256 		}
11257 	}
11258 
11259 	/*
11260 	 * Even though the error may have occurred on the other port
11261 	 * we still need to increment the vf error reference count for
11262 	 * both ports because the I/O resume function will be called
11263 	 * for both of them.
11264 	 */
11265 	adapter->vferr_refcount++;
11266 
11267 	return PCI_ERS_RESULT_RECOVERED;
11268 
11269 skip_bad_vf_detection:
11270 #endif /* CONFIG_PCI_IOV */
11271 	if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
11272 		return PCI_ERS_RESULT_DISCONNECT;
11273 
11274 	if (!netif_device_present(netdev))
11275 		return PCI_ERS_RESULT_DISCONNECT;
11276 
11277 	rtnl_lock();
11278 	netif_device_detach(netdev);
11279 
11280 	if (netif_running(netdev))
11281 		ixgbe_close_suspend(adapter);
11282 
11283 	if (state == pci_channel_io_perm_failure) {
11284 		rtnl_unlock();
11285 		return PCI_ERS_RESULT_DISCONNECT;
11286 	}
11287 
11288 	if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
11289 		pci_disable_device(pdev);
11290 	rtnl_unlock();
11291 
11292 	/* Request a slot reset. */
11293 	return PCI_ERS_RESULT_NEED_RESET;
11294 }
11295 
11296 /**
11297  * ixgbe_io_slot_reset - called after the pci bus has been reset.
11298  * @pdev: Pointer to PCI device
11299  *
11300  * Restart the card from scratch, as if from a cold-boot.
11301  */
11302 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
11303 {
11304 	struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11305 	pci_ers_result_t result;
11306 
11307 	if (pci_enable_device_mem(pdev)) {
11308 		e_err(probe, "Cannot re-enable PCI device after reset.\n");
11309 		result = PCI_ERS_RESULT_DISCONNECT;
11310 	} else {
11311 		smp_mb__before_atomic();
11312 		clear_bit(__IXGBE_DISABLED, &adapter->state);
11313 		adapter->hw.hw_addr = adapter->io_addr;
11314 		pci_set_master(pdev);
11315 		pci_restore_state(pdev);
11316 		pci_save_state(pdev);
11317 
11318 		pci_wake_from_d3(pdev, false);
11319 
11320 		ixgbe_reset(adapter);
11321 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
11322 		result = PCI_ERS_RESULT_RECOVERED;
11323 	}
11324 
11325 	return result;
11326 }
11327 
11328 /**
11329  * ixgbe_io_resume - called when traffic can start flowing again.
11330  * @pdev: Pointer to PCI device
11331  *
11332  * This callback is called when the error recovery driver tells us that
11333  * its OK to resume normal operation.
11334  */
11335 static void ixgbe_io_resume(struct pci_dev *pdev)
11336 {
11337 	struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11338 	struct net_device *netdev = adapter->netdev;
11339 
11340 #ifdef CONFIG_PCI_IOV
11341 	if (adapter->vferr_refcount) {
11342 		e_info(drv, "Resuming after VF err\n");
11343 		adapter->vferr_refcount--;
11344 		return;
11345 	}
11346 
11347 #endif
11348 	rtnl_lock();
11349 	if (netif_running(netdev))
11350 		ixgbe_open(netdev);
11351 
11352 	netif_device_attach(netdev);
11353 	rtnl_unlock();
11354 }
11355 
11356 static const struct pci_error_handlers ixgbe_err_handler = {
11357 	.error_detected = ixgbe_io_error_detected,
11358 	.slot_reset = ixgbe_io_slot_reset,
11359 	.resume = ixgbe_io_resume,
11360 };
11361 
11362 static SIMPLE_DEV_PM_OPS(ixgbe_pm_ops, ixgbe_suspend, ixgbe_resume);
11363 
11364 static struct pci_driver ixgbe_driver = {
11365 	.name      = ixgbe_driver_name,
11366 	.id_table  = ixgbe_pci_tbl,
11367 	.probe     = ixgbe_probe,
11368 	.remove    = ixgbe_remove,
11369 	.driver.pm = &ixgbe_pm_ops,
11370 	.shutdown  = ixgbe_shutdown,
11371 	.sriov_configure = ixgbe_pci_sriov_configure,
11372 	.err_handler = &ixgbe_err_handler
11373 };
11374 
11375 /**
11376  * ixgbe_init_module - Driver Registration Routine
11377  *
11378  * ixgbe_init_module is the first routine called when the driver is
11379  * loaded. All it does is register with the PCI subsystem.
11380  **/
11381 static int __init ixgbe_init_module(void)
11382 {
11383 	int ret;
11384 	pr_info("%s\n", ixgbe_driver_string);
11385 	pr_info("%s\n", ixgbe_copyright);
11386 
11387 	ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name);
11388 	if (!ixgbe_wq) {
11389 		pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name);
11390 		return -ENOMEM;
11391 	}
11392 
11393 	ixgbe_dbg_init();
11394 
11395 	ret = pci_register_driver(&ixgbe_driver);
11396 	if (ret) {
11397 		destroy_workqueue(ixgbe_wq);
11398 		ixgbe_dbg_exit();
11399 		return ret;
11400 	}
11401 
11402 #ifdef CONFIG_IXGBE_DCA
11403 	dca_register_notify(&dca_notifier);
11404 #endif
11405 
11406 	return 0;
11407 }
11408 
11409 module_init(ixgbe_init_module);
11410 
11411 /**
11412  * ixgbe_exit_module - Driver Exit Cleanup Routine
11413  *
11414  * ixgbe_exit_module is called just before the driver is removed
11415  * from memory.
11416  **/
11417 static void __exit ixgbe_exit_module(void)
11418 {
11419 #ifdef CONFIG_IXGBE_DCA
11420 	dca_unregister_notify(&dca_notifier);
11421 #endif
11422 	pci_unregister_driver(&ixgbe_driver);
11423 
11424 	ixgbe_dbg_exit();
11425 	if (ixgbe_wq) {
11426 		destroy_workqueue(ixgbe_wq);
11427 		ixgbe_wq = NULL;
11428 	}
11429 }
11430 
11431 #ifdef CONFIG_IXGBE_DCA
11432 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
11433 			    void *p)
11434 {
11435 	int ret_val;
11436 
11437 	ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
11438 					 __ixgbe_notify_dca);
11439 
11440 	return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
11441 }
11442 
11443 #endif /* CONFIG_IXGBE_DCA */
11444 
11445 module_exit(ixgbe_exit_module);
11446 
11447 /* ixgbe_main.c */
11448