1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2016 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/types.h> 30 #include <linux/module.h> 31 #include <linux/pci.h> 32 #include <linux/netdevice.h> 33 #include <linux/vmalloc.h> 34 #include <linux/string.h> 35 #include <linux/in.h> 36 #include <linux/interrupt.h> 37 #include <linux/ip.h> 38 #include <linux/tcp.h> 39 #include <linux/sctp.h> 40 #include <linux/pkt_sched.h> 41 #include <linux/ipv6.h> 42 #include <linux/slab.h> 43 #include <net/checksum.h> 44 #include <net/ip6_checksum.h> 45 #include <linux/etherdevice.h> 46 #include <linux/ethtool.h> 47 #include <linux/if.h> 48 #include <linux/if_vlan.h> 49 #include <linux/if_macvlan.h> 50 #include <linux/if_bridge.h> 51 #include <linux/prefetch.h> 52 #include <scsi/fc/fc_fcoe.h> 53 #include <net/udp_tunnel.h> 54 #include <net/pkt_cls.h> 55 #include <net/tc_act/tc_gact.h> 56 #include <net/tc_act/tc_mirred.h> 57 58 #include "ixgbe.h" 59 #include "ixgbe_common.h" 60 #include "ixgbe_dcb_82599.h" 61 #include "ixgbe_sriov.h" 62 #include "ixgbe_model.h" 63 64 char ixgbe_driver_name[] = "ixgbe"; 65 static const char ixgbe_driver_string[] = 66 "Intel(R) 10 Gigabit PCI Express Network Driver"; 67 #ifdef IXGBE_FCOE 68 char ixgbe_default_device_descr[] = 69 "Intel(R) 10 Gigabit Network Connection"; 70 #else 71 static char ixgbe_default_device_descr[] = 72 "Intel(R) 10 Gigabit Network Connection"; 73 #endif 74 #define DRV_VERSION "4.4.0-k" 75 const char ixgbe_driver_version[] = DRV_VERSION; 76 static const char ixgbe_copyright[] = 77 "Copyright (c) 1999-2016 Intel Corporation."; 78 79 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 80 81 static const struct ixgbe_info *ixgbe_info_tbl[] = { 82 [board_82598] = &ixgbe_82598_info, 83 [board_82599] = &ixgbe_82599_info, 84 [board_X540] = &ixgbe_X540_info, 85 [board_X550] = &ixgbe_X550_info, 86 [board_X550EM_x] = &ixgbe_X550EM_x_info, 87 [board_x550em_a] = &ixgbe_x550em_a_info, 88 }; 89 90 /* ixgbe_pci_tbl - PCI Device ID Table 91 * 92 * Wildcard entries (PCI_ANY_ID) should come last 93 * Last entry must be all 0s 94 * 95 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 96 * Class, Class Mask, private data (not used) } 97 */ 98 static const struct pci_device_id ixgbe_pci_tbl[] = { 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550}, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, 135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a }, 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a }, 137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a }, 138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a }, 139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a }, 140 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a}, 141 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a }, 142 /* required last entry */ 143 {0, } 144 }; 145 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 146 147 #ifdef CONFIG_IXGBE_DCA 148 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 149 void *p); 150 static struct notifier_block dca_notifier = { 151 .notifier_call = ixgbe_notify_dca, 152 .next = NULL, 153 .priority = 0 154 }; 155 #endif 156 157 #ifdef CONFIG_PCI_IOV 158 static unsigned int max_vfs; 159 module_param(max_vfs, uint, 0); 160 MODULE_PARM_DESC(max_vfs, 161 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 162 #endif /* CONFIG_PCI_IOV */ 163 164 static unsigned int allow_unsupported_sfp; 165 module_param(allow_unsupported_sfp, uint, 0); 166 MODULE_PARM_DESC(allow_unsupported_sfp, 167 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 168 169 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 170 static int debug = -1; 171 module_param(debug, int, 0); 172 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 173 174 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 175 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 176 MODULE_LICENSE("GPL"); 177 MODULE_VERSION(DRV_VERSION); 178 179 static struct workqueue_struct *ixgbe_wq; 180 181 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 182 183 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 184 u32 reg, u16 *value) 185 { 186 struct pci_dev *parent_dev; 187 struct pci_bus *parent_bus; 188 189 parent_bus = adapter->pdev->bus->parent; 190 if (!parent_bus) 191 return -1; 192 193 parent_dev = parent_bus->self; 194 if (!parent_dev) 195 return -1; 196 197 if (!pci_is_pcie(parent_dev)) 198 return -1; 199 200 pcie_capability_read_word(parent_dev, reg, value); 201 if (*value == IXGBE_FAILED_READ_CFG_WORD && 202 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 203 return -1; 204 return 0; 205 } 206 207 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 208 { 209 struct ixgbe_hw *hw = &adapter->hw; 210 u16 link_status = 0; 211 int err; 212 213 hw->bus.type = ixgbe_bus_type_pci_express; 214 215 /* Get the negotiated link width and speed from PCI config space of the 216 * parent, as this device is behind a switch 217 */ 218 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 219 220 /* assume caller will handle error case */ 221 if (err) 222 return err; 223 224 hw->bus.width = ixgbe_convert_bus_width(link_status); 225 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 226 227 return 0; 228 } 229 230 /** 231 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent 232 * @hw: hw specific details 233 * 234 * This function is used by probe to determine whether a device's PCI-Express 235 * bandwidth details should be gathered from the parent bus instead of from the 236 * device. Used to ensure that various locations all have the correct device ID 237 * checks. 238 */ 239 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 240 { 241 switch (hw->device_id) { 242 case IXGBE_DEV_ID_82599_SFP_SF_QP: 243 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 244 return true; 245 default: 246 return false; 247 } 248 } 249 250 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 251 int expected_gts) 252 { 253 struct ixgbe_hw *hw = &adapter->hw; 254 int max_gts = 0; 255 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; 256 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; 257 struct pci_dev *pdev; 258 259 /* Some devices are not connected over PCIe and thus do not negotiate 260 * speed. These devices do not have valid bus info, and thus any report 261 * we generate may not be correct. 262 */ 263 if (hw->bus.type == ixgbe_bus_type_internal) 264 return; 265 266 /* determine whether to use the parent device */ 267 if (ixgbe_pcie_from_parent(&adapter->hw)) 268 pdev = adapter->pdev->bus->parent->self; 269 else 270 pdev = adapter->pdev; 271 272 if (pcie_get_minimum_link(pdev, &speed, &width) || 273 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { 274 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 275 return; 276 } 277 278 switch (speed) { 279 case PCIE_SPEED_2_5GT: 280 /* 8b/10b encoding reduces max throughput by 20% */ 281 max_gts = 2 * width; 282 break; 283 case PCIE_SPEED_5_0GT: 284 /* 8b/10b encoding reduces max throughput by 20% */ 285 max_gts = 4 * width; 286 break; 287 case PCIE_SPEED_8_0GT: 288 /* 128b/130b encoding reduces throughput by less than 2% */ 289 max_gts = 8 * width; 290 break; 291 default: 292 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 293 return; 294 } 295 296 e_dev_info("PCI Express bandwidth of %dGT/s available\n", 297 max_gts); 298 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n", 299 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : 300 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : 301 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : 302 "Unknown"), 303 width, 304 (speed == PCIE_SPEED_2_5GT ? "20%" : 305 speed == PCIE_SPEED_5_0GT ? "20%" : 306 speed == PCIE_SPEED_8_0GT ? "<2%" : 307 "Unknown")); 308 309 if (max_gts < expected_gts) { 310 e_dev_warn("This is not sufficient for optimal performance of this card.\n"); 311 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n", 312 expected_gts); 313 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n"); 314 } 315 } 316 317 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 318 { 319 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 320 !test_bit(__IXGBE_REMOVING, &adapter->state) && 321 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 322 queue_work(ixgbe_wq, &adapter->service_task); 323 } 324 325 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 326 { 327 struct ixgbe_adapter *adapter = hw->back; 328 329 if (!hw->hw_addr) 330 return; 331 hw->hw_addr = NULL; 332 e_dev_err("Adapter removed\n"); 333 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 334 ixgbe_service_event_schedule(adapter); 335 } 336 337 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 338 { 339 u32 value; 340 341 /* The following check not only optimizes a bit by not 342 * performing a read on the status register when the 343 * register just read was a status register read that 344 * returned IXGBE_FAILED_READ_REG. It also blocks any 345 * potential recursion. 346 */ 347 if (reg == IXGBE_STATUS) { 348 ixgbe_remove_adapter(hw); 349 return; 350 } 351 value = ixgbe_read_reg(hw, IXGBE_STATUS); 352 if (value == IXGBE_FAILED_READ_REG) 353 ixgbe_remove_adapter(hw); 354 } 355 356 /** 357 * ixgbe_read_reg - Read from device register 358 * @hw: hw specific details 359 * @reg: offset of register to read 360 * 361 * Returns : value read or IXGBE_FAILED_READ_REG if removed 362 * 363 * This function is used to read device registers. It checks for device 364 * removal by confirming any read that returns all ones by checking the 365 * status register value for all ones. This function avoids reading from 366 * the hardware if a removal was previously detected in which case it 367 * returns IXGBE_FAILED_READ_REG (all ones). 368 */ 369 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 370 { 371 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr); 372 u32 value; 373 374 if (ixgbe_removed(reg_addr)) 375 return IXGBE_FAILED_READ_REG; 376 if (unlikely(hw->phy.nw_mng_if_sel & 377 IXGBE_NW_MNG_IF_SEL_ENABLE_10_100M)) { 378 struct ixgbe_adapter *adapter; 379 int i; 380 381 for (i = 0; i < 200; ++i) { 382 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); 383 if (likely(!value)) 384 goto writes_completed; 385 if (value == IXGBE_FAILED_READ_REG) { 386 ixgbe_remove_adapter(hw); 387 return IXGBE_FAILED_READ_REG; 388 } 389 udelay(5); 390 } 391 392 adapter = hw->back; 393 e_warn(hw, "register writes incomplete %08x\n", value); 394 } 395 396 writes_completed: 397 value = readl(reg_addr + reg); 398 if (unlikely(value == IXGBE_FAILED_READ_REG)) 399 ixgbe_check_remove(hw, reg); 400 return value; 401 } 402 403 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 404 { 405 u16 value; 406 407 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 408 if (value == IXGBE_FAILED_READ_CFG_WORD) { 409 ixgbe_remove_adapter(hw); 410 return true; 411 } 412 return false; 413 } 414 415 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 416 { 417 struct ixgbe_adapter *adapter = hw->back; 418 u16 value; 419 420 if (ixgbe_removed(hw->hw_addr)) 421 return IXGBE_FAILED_READ_CFG_WORD; 422 pci_read_config_word(adapter->pdev, reg, &value); 423 if (value == IXGBE_FAILED_READ_CFG_WORD && 424 ixgbe_check_cfg_remove(hw, adapter->pdev)) 425 return IXGBE_FAILED_READ_CFG_WORD; 426 return value; 427 } 428 429 #ifdef CONFIG_PCI_IOV 430 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 431 { 432 struct ixgbe_adapter *adapter = hw->back; 433 u32 value; 434 435 if (ixgbe_removed(hw->hw_addr)) 436 return IXGBE_FAILED_READ_CFG_DWORD; 437 pci_read_config_dword(adapter->pdev, reg, &value); 438 if (value == IXGBE_FAILED_READ_CFG_DWORD && 439 ixgbe_check_cfg_remove(hw, adapter->pdev)) 440 return IXGBE_FAILED_READ_CFG_DWORD; 441 return value; 442 } 443 #endif /* CONFIG_PCI_IOV */ 444 445 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 446 { 447 struct ixgbe_adapter *adapter = hw->back; 448 449 if (ixgbe_removed(hw->hw_addr)) 450 return; 451 pci_write_config_word(adapter->pdev, reg, value); 452 } 453 454 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 455 { 456 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 457 458 /* flush memory to make sure state is correct before next watchdog */ 459 smp_mb__before_atomic(); 460 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 461 } 462 463 struct ixgbe_reg_info { 464 u32 ofs; 465 char *name; 466 }; 467 468 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 469 470 /* General Registers */ 471 {IXGBE_CTRL, "CTRL"}, 472 {IXGBE_STATUS, "STATUS"}, 473 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 474 475 /* Interrupt Registers */ 476 {IXGBE_EICR, "EICR"}, 477 478 /* RX Registers */ 479 {IXGBE_SRRCTL(0), "SRRCTL"}, 480 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 481 {IXGBE_RDLEN(0), "RDLEN"}, 482 {IXGBE_RDH(0), "RDH"}, 483 {IXGBE_RDT(0), "RDT"}, 484 {IXGBE_RXDCTL(0), "RXDCTL"}, 485 {IXGBE_RDBAL(0), "RDBAL"}, 486 {IXGBE_RDBAH(0), "RDBAH"}, 487 488 /* TX Registers */ 489 {IXGBE_TDBAL(0), "TDBAL"}, 490 {IXGBE_TDBAH(0), "TDBAH"}, 491 {IXGBE_TDLEN(0), "TDLEN"}, 492 {IXGBE_TDH(0), "TDH"}, 493 {IXGBE_TDT(0), "TDT"}, 494 {IXGBE_TXDCTL(0), "TXDCTL"}, 495 496 /* List Terminator */ 497 { .name = NULL } 498 }; 499 500 501 /* 502 * ixgbe_regdump - register printout routine 503 */ 504 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 505 { 506 int i = 0, j = 0; 507 char rname[16]; 508 u32 regs[64]; 509 510 switch (reginfo->ofs) { 511 case IXGBE_SRRCTL(0): 512 for (i = 0; i < 64; i++) 513 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 514 break; 515 case IXGBE_DCA_RXCTRL(0): 516 for (i = 0; i < 64; i++) 517 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 518 break; 519 case IXGBE_RDLEN(0): 520 for (i = 0; i < 64; i++) 521 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 522 break; 523 case IXGBE_RDH(0): 524 for (i = 0; i < 64; i++) 525 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 526 break; 527 case IXGBE_RDT(0): 528 for (i = 0; i < 64; i++) 529 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 530 break; 531 case IXGBE_RXDCTL(0): 532 for (i = 0; i < 64; i++) 533 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 534 break; 535 case IXGBE_RDBAL(0): 536 for (i = 0; i < 64; i++) 537 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 538 break; 539 case IXGBE_RDBAH(0): 540 for (i = 0; i < 64; i++) 541 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 542 break; 543 case IXGBE_TDBAL(0): 544 for (i = 0; i < 64; i++) 545 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 546 break; 547 case IXGBE_TDBAH(0): 548 for (i = 0; i < 64; i++) 549 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 550 break; 551 case IXGBE_TDLEN(0): 552 for (i = 0; i < 64; i++) 553 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 554 break; 555 case IXGBE_TDH(0): 556 for (i = 0; i < 64; i++) 557 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 558 break; 559 case IXGBE_TDT(0): 560 for (i = 0; i < 64; i++) 561 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 562 break; 563 case IXGBE_TXDCTL(0): 564 for (i = 0; i < 64; i++) 565 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 566 break; 567 default: 568 pr_info("%-15s %08x\n", reginfo->name, 569 IXGBE_READ_REG(hw, reginfo->ofs)); 570 return; 571 } 572 573 for (i = 0; i < 8; i++) { 574 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); 575 pr_err("%-15s", rname); 576 for (j = 0; j < 8; j++) 577 pr_cont(" %08x", regs[i*8+j]); 578 pr_cont("\n"); 579 } 580 581 } 582 583 /* 584 * ixgbe_dump - Print registers, tx-rings and rx-rings 585 */ 586 static void ixgbe_dump(struct ixgbe_adapter *adapter) 587 { 588 struct net_device *netdev = adapter->netdev; 589 struct ixgbe_hw *hw = &adapter->hw; 590 struct ixgbe_reg_info *reginfo; 591 int n = 0; 592 struct ixgbe_ring *tx_ring; 593 struct ixgbe_tx_buffer *tx_buffer; 594 union ixgbe_adv_tx_desc *tx_desc; 595 struct my_u0 { u64 a; u64 b; } *u0; 596 struct ixgbe_ring *rx_ring; 597 union ixgbe_adv_rx_desc *rx_desc; 598 struct ixgbe_rx_buffer *rx_buffer_info; 599 u32 staterr; 600 int i = 0; 601 602 if (!netif_msg_hw(adapter)) 603 return; 604 605 /* Print netdevice Info */ 606 if (netdev) { 607 dev_info(&adapter->pdev->dev, "Net device Info\n"); 608 pr_info("Device Name state " 609 "trans_start last_rx\n"); 610 pr_info("%-15s %016lX %016lX %016lX\n", 611 netdev->name, 612 netdev->state, 613 dev_trans_start(netdev), 614 netdev->last_rx); 615 } 616 617 /* Print Registers */ 618 dev_info(&adapter->pdev->dev, "Register Dump\n"); 619 pr_info(" Register Name Value\n"); 620 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 621 reginfo->name; reginfo++) { 622 ixgbe_regdump(hw, reginfo); 623 } 624 625 /* Print TX Ring Summary */ 626 if (!netdev || !netif_running(netdev)) 627 return; 628 629 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 630 pr_info(" %s %s %s %s\n", 631 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 632 "leng", "ntw", "timestamp"); 633 for (n = 0; n < adapter->num_tx_queues; n++) { 634 tx_ring = adapter->tx_ring[n]; 635 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 636 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 637 n, tx_ring->next_to_use, tx_ring->next_to_clean, 638 (u64)dma_unmap_addr(tx_buffer, dma), 639 dma_unmap_len(tx_buffer, len), 640 tx_buffer->next_to_watch, 641 (u64)tx_buffer->time_stamp); 642 } 643 644 /* Print TX Rings */ 645 if (!netif_msg_tx_done(adapter)) 646 goto rx_ring_summary; 647 648 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 649 650 /* Transmit Descriptor Formats 651 * 652 * 82598 Advanced Transmit Descriptor 653 * +--------------------------------------------------------------+ 654 * 0 | Buffer Address [63:0] | 655 * +--------------------------------------------------------------+ 656 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 657 * +--------------------------------------------------------------+ 658 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 659 * 660 * 82598 Advanced Transmit Descriptor (Write-Back Format) 661 * +--------------------------------------------------------------+ 662 * 0 | RSV [63:0] | 663 * +--------------------------------------------------------------+ 664 * 8 | RSV | STA | NXTSEQ | 665 * +--------------------------------------------------------------+ 666 * 63 36 35 32 31 0 667 * 668 * 82599+ Advanced Transmit Descriptor 669 * +--------------------------------------------------------------+ 670 * 0 | Buffer Address [63:0] | 671 * +--------------------------------------------------------------+ 672 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 673 * +--------------------------------------------------------------+ 674 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 675 * 676 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 677 * +--------------------------------------------------------------+ 678 * 0 | RSV [63:0] | 679 * +--------------------------------------------------------------+ 680 * 8 | RSV | STA | RSV | 681 * +--------------------------------------------------------------+ 682 * 63 36 35 32 31 0 683 */ 684 685 for (n = 0; n < adapter->num_tx_queues; n++) { 686 tx_ring = adapter->tx_ring[n]; 687 pr_info("------------------------------------\n"); 688 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 689 pr_info("------------------------------------\n"); 690 pr_info("%s%s %s %s %s %s\n", 691 "T [desc] [address 63:0 ] ", 692 "[PlPOIdStDDt Ln] [bi->dma ] ", 693 "leng", "ntw", "timestamp", "bi->skb"); 694 695 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 696 tx_desc = IXGBE_TX_DESC(tx_ring, i); 697 tx_buffer = &tx_ring->tx_buffer_info[i]; 698 u0 = (struct my_u0 *)tx_desc; 699 if (dma_unmap_len(tx_buffer, len) > 0) { 700 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p", 701 i, 702 le64_to_cpu(u0->a), 703 le64_to_cpu(u0->b), 704 (u64)dma_unmap_addr(tx_buffer, dma), 705 dma_unmap_len(tx_buffer, len), 706 tx_buffer->next_to_watch, 707 (u64)tx_buffer->time_stamp, 708 tx_buffer->skb); 709 if (i == tx_ring->next_to_use && 710 i == tx_ring->next_to_clean) 711 pr_cont(" NTC/U\n"); 712 else if (i == tx_ring->next_to_use) 713 pr_cont(" NTU\n"); 714 else if (i == tx_ring->next_to_clean) 715 pr_cont(" NTC\n"); 716 else 717 pr_cont("\n"); 718 719 if (netif_msg_pktdata(adapter) && 720 tx_buffer->skb) 721 print_hex_dump(KERN_INFO, "", 722 DUMP_PREFIX_ADDRESS, 16, 1, 723 tx_buffer->skb->data, 724 dma_unmap_len(tx_buffer, len), 725 true); 726 } 727 } 728 } 729 730 /* Print RX Rings Summary */ 731 rx_ring_summary: 732 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 733 pr_info("Queue [NTU] [NTC]\n"); 734 for (n = 0; n < adapter->num_rx_queues; n++) { 735 rx_ring = adapter->rx_ring[n]; 736 pr_info("%5d %5X %5X\n", 737 n, rx_ring->next_to_use, rx_ring->next_to_clean); 738 } 739 740 /* Print RX Rings */ 741 if (!netif_msg_rx_status(adapter)) 742 return; 743 744 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 745 746 /* Receive Descriptor Formats 747 * 748 * 82598 Advanced Receive Descriptor (Read) Format 749 * 63 1 0 750 * +-----------------------------------------------------+ 751 * 0 | Packet Buffer Address [63:1] |A0/NSE| 752 * +----------------------------------------------+------+ 753 * 8 | Header Buffer Address [63:1] | DD | 754 * +-----------------------------------------------------+ 755 * 756 * 757 * 82598 Advanced Receive Descriptor (Write-Back) Format 758 * 759 * 63 48 47 32 31 30 21 20 16 15 4 3 0 760 * +------------------------------------------------------+ 761 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 762 * | Packet | IP | | | | Type | Type | 763 * | Checksum | Ident | | | | | | 764 * +------------------------------------------------------+ 765 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 766 * +------------------------------------------------------+ 767 * 63 48 47 32 31 20 19 0 768 * 769 * 82599+ Advanced Receive Descriptor (Read) Format 770 * 63 1 0 771 * +-----------------------------------------------------+ 772 * 0 | Packet Buffer Address [63:1] |A0/NSE| 773 * +----------------------------------------------+------+ 774 * 8 | Header Buffer Address [63:1] | DD | 775 * +-----------------------------------------------------+ 776 * 777 * 778 * 82599+ Advanced Receive Descriptor (Write-Back) Format 779 * 780 * 63 48 47 32 31 30 21 20 17 16 4 3 0 781 * +------------------------------------------------------+ 782 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 783 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 784 * |/ Flow Dir Flt ID | | | | | | 785 * +------------------------------------------------------+ 786 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 787 * +------------------------------------------------------+ 788 * 63 48 47 32 31 20 19 0 789 */ 790 791 for (n = 0; n < adapter->num_rx_queues; n++) { 792 rx_ring = adapter->rx_ring[n]; 793 pr_info("------------------------------------\n"); 794 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 795 pr_info("------------------------------------\n"); 796 pr_info("%s%s%s", 797 "R [desc] [ PktBuf A0] ", 798 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 799 "<-- Adv Rx Read format\n"); 800 pr_info("%s%s%s", 801 "RWB[desc] [PcsmIpSHl PtRs] ", 802 "[vl er S cks ln] ---------------- [bi->skb ] ", 803 "<-- Adv Rx Write-Back format\n"); 804 805 for (i = 0; i < rx_ring->count; i++) { 806 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 807 rx_desc = IXGBE_RX_DESC(rx_ring, i); 808 u0 = (struct my_u0 *)rx_desc; 809 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 810 if (staterr & IXGBE_RXD_STAT_DD) { 811 /* Descriptor Done */ 812 pr_info("RWB[0x%03X] %016llX " 813 "%016llX ---------------- %p", i, 814 le64_to_cpu(u0->a), 815 le64_to_cpu(u0->b), 816 rx_buffer_info->skb); 817 } else { 818 pr_info("R [0x%03X] %016llX " 819 "%016llX %016llX %p", i, 820 le64_to_cpu(u0->a), 821 le64_to_cpu(u0->b), 822 (u64)rx_buffer_info->dma, 823 rx_buffer_info->skb); 824 825 if (netif_msg_pktdata(adapter) && 826 rx_buffer_info->dma) { 827 print_hex_dump(KERN_INFO, "", 828 DUMP_PREFIX_ADDRESS, 16, 1, 829 page_address(rx_buffer_info->page) + 830 rx_buffer_info->page_offset, 831 ixgbe_rx_bufsz(rx_ring), true); 832 } 833 } 834 835 if (i == rx_ring->next_to_use) 836 pr_cont(" NTU\n"); 837 else if (i == rx_ring->next_to_clean) 838 pr_cont(" NTC\n"); 839 else 840 pr_cont("\n"); 841 842 } 843 } 844 } 845 846 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 847 { 848 u32 ctrl_ext; 849 850 /* Let firmware take over control of h/w */ 851 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 852 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 853 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 854 } 855 856 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 857 { 858 u32 ctrl_ext; 859 860 /* Let firmware know the driver has taken over */ 861 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 862 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 863 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 864 } 865 866 /** 867 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 868 * @adapter: pointer to adapter struct 869 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 870 * @queue: queue to map the corresponding interrupt to 871 * @msix_vector: the vector to map to the corresponding queue 872 * 873 */ 874 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 875 u8 queue, u8 msix_vector) 876 { 877 u32 ivar, index; 878 struct ixgbe_hw *hw = &adapter->hw; 879 switch (hw->mac.type) { 880 case ixgbe_mac_82598EB: 881 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 882 if (direction == -1) 883 direction = 0; 884 index = (((direction * 64) + queue) >> 2) & 0x1F; 885 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 886 ivar &= ~(0xFF << (8 * (queue & 0x3))); 887 ivar |= (msix_vector << (8 * (queue & 0x3))); 888 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 889 break; 890 case ixgbe_mac_82599EB: 891 case ixgbe_mac_X540: 892 case ixgbe_mac_X550: 893 case ixgbe_mac_X550EM_x: 894 case ixgbe_mac_x550em_a: 895 if (direction == -1) { 896 /* other causes */ 897 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 898 index = ((queue & 1) * 8); 899 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 900 ivar &= ~(0xFF << index); 901 ivar |= (msix_vector << index); 902 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 903 break; 904 } else { 905 /* tx or rx causes */ 906 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 907 index = ((16 * (queue & 1)) + (8 * direction)); 908 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 909 ivar &= ~(0xFF << index); 910 ivar |= (msix_vector << index); 911 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 912 break; 913 } 914 default: 915 break; 916 } 917 } 918 919 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 920 u64 qmask) 921 { 922 u32 mask; 923 924 switch (adapter->hw.mac.type) { 925 case ixgbe_mac_82598EB: 926 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 927 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 928 break; 929 case ixgbe_mac_82599EB: 930 case ixgbe_mac_X540: 931 case ixgbe_mac_X550: 932 case ixgbe_mac_X550EM_x: 933 case ixgbe_mac_x550em_a: 934 mask = (qmask & 0xFFFFFFFF); 935 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 936 mask = (qmask >> 32); 937 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 938 break; 939 default: 940 break; 941 } 942 } 943 944 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring, 945 struct ixgbe_tx_buffer *tx_buffer) 946 { 947 if (tx_buffer->skb) { 948 dev_kfree_skb_any(tx_buffer->skb); 949 if (dma_unmap_len(tx_buffer, len)) 950 dma_unmap_single(ring->dev, 951 dma_unmap_addr(tx_buffer, dma), 952 dma_unmap_len(tx_buffer, len), 953 DMA_TO_DEVICE); 954 } else if (dma_unmap_len(tx_buffer, len)) { 955 dma_unmap_page(ring->dev, 956 dma_unmap_addr(tx_buffer, dma), 957 dma_unmap_len(tx_buffer, len), 958 DMA_TO_DEVICE); 959 } 960 tx_buffer->next_to_watch = NULL; 961 tx_buffer->skb = NULL; 962 dma_unmap_len_set(tx_buffer, len, 0); 963 /* tx_buffer must be completely set up in the transmit path */ 964 } 965 966 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 967 { 968 struct ixgbe_hw *hw = &adapter->hw; 969 struct ixgbe_hw_stats *hwstats = &adapter->stats; 970 int i; 971 u32 data; 972 973 if ((hw->fc.current_mode != ixgbe_fc_full) && 974 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 975 return; 976 977 switch (hw->mac.type) { 978 case ixgbe_mac_82598EB: 979 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 980 break; 981 default: 982 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 983 } 984 hwstats->lxoffrxc += data; 985 986 /* refill credits (no tx hang) if we received xoff */ 987 if (!data) 988 return; 989 990 for (i = 0; i < adapter->num_tx_queues; i++) 991 clear_bit(__IXGBE_HANG_CHECK_ARMED, 992 &adapter->tx_ring[i]->state); 993 } 994 995 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 996 { 997 struct ixgbe_hw *hw = &adapter->hw; 998 struct ixgbe_hw_stats *hwstats = &adapter->stats; 999 u32 xoff[8] = {0}; 1000 u8 tc; 1001 int i; 1002 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 1003 1004 if (adapter->ixgbe_ieee_pfc) 1005 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 1006 1007 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 1008 ixgbe_update_xoff_rx_lfc(adapter); 1009 return; 1010 } 1011 1012 /* update stats for each tc, only valid with PFC enabled */ 1013 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 1014 u32 pxoffrxc; 1015 1016 switch (hw->mac.type) { 1017 case ixgbe_mac_82598EB: 1018 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 1019 break; 1020 default: 1021 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 1022 } 1023 hwstats->pxoffrxc[i] += pxoffrxc; 1024 /* Get the TC for given UP */ 1025 tc = netdev_get_prio_tc_map(adapter->netdev, i); 1026 xoff[tc] += pxoffrxc; 1027 } 1028 1029 /* disarm tx queues that have received xoff frames */ 1030 for (i = 0; i < adapter->num_tx_queues; i++) { 1031 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 1032 1033 tc = tx_ring->dcb_tc; 1034 if (xoff[tc]) 1035 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1036 } 1037 } 1038 1039 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1040 { 1041 return ring->stats.packets; 1042 } 1043 1044 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1045 { 1046 struct ixgbe_adapter *adapter; 1047 struct ixgbe_hw *hw; 1048 u32 head, tail; 1049 1050 if (ring->l2_accel_priv) 1051 adapter = ring->l2_accel_priv->real_adapter; 1052 else 1053 adapter = netdev_priv(ring->netdev); 1054 1055 hw = &adapter->hw; 1056 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); 1057 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); 1058 1059 if (head != tail) 1060 return (head < tail) ? 1061 tail - head : (tail + ring->count - head); 1062 1063 return 0; 1064 } 1065 1066 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1067 { 1068 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1069 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1070 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1071 1072 clear_check_for_tx_hang(tx_ring); 1073 1074 /* 1075 * Check for a hung queue, but be thorough. This verifies 1076 * that a transmit has been completed since the previous 1077 * check AND there is at least one packet pending. The 1078 * ARMED bit is set to indicate a potential hang. The 1079 * bit is cleared if a pause frame is received to remove 1080 * false hang detection due to PFC or 802.3x frames. By 1081 * requiring this to fail twice we avoid races with 1082 * pfc clearing the ARMED bit and conditions where we 1083 * run the check_tx_hang logic with a transmit completion 1084 * pending but without time to complete it yet. 1085 */ 1086 if (tx_done_old == tx_done && tx_pending) 1087 /* make sure it is true for two checks in a row */ 1088 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1089 &tx_ring->state); 1090 /* update completed stats and continue */ 1091 tx_ring->tx_stats.tx_done_old = tx_done; 1092 /* reset the countdown */ 1093 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1094 1095 return false; 1096 } 1097 1098 /** 1099 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1100 * @adapter: driver private struct 1101 **/ 1102 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1103 { 1104 1105 /* Do the reset outside of interrupt context */ 1106 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1107 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 1108 e_warn(drv, "initiating reset due to tx timeout\n"); 1109 ixgbe_service_event_schedule(adapter); 1110 } 1111 } 1112 1113 /** 1114 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate 1115 **/ 1116 static int ixgbe_tx_maxrate(struct net_device *netdev, 1117 int queue_index, u32 maxrate) 1118 { 1119 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1120 struct ixgbe_hw *hw = &adapter->hw; 1121 u32 bcnrc_val = ixgbe_link_mbps(adapter); 1122 1123 if (!maxrate) 1124 return 0; 1125 1126 /* Calculate the rate factor values to set */ 1127 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; 1128 bcnrc_val /= maxrate; 1129 1130 /* clear everything but the rate factor */ 1131 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | 1132 IXGBE_RTTBCNRC_RF_DEC_MASK; 1133 1134 /* enable the rate scheduler */ 1135 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; 1136 1137 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); 1138 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 1139 1140 return 0; 1141 } 1142 1143 /** 1144 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1145 * @q_vector: structure containing interrupt and ring information 1146 * @tx_ring: tx ring to clean 1147 * @napi_budget: Used to determine if we are in netpoll 1148 **/ 1149 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1150 struct ixgbe_ring *tx_ring, int napi_budget) 1151 { 1152 struct ixgbe_adapter *adapter = q_vector->adapter; 1153 struct ixgbe_tx_buffer *tx_buffer; 1154 union ixgbe_adv_tx_desc *tx_desc; 1155 unsigned int total_bytes = 0, total_packets = 0; 1156 unsigned int budget = q_vector->tx.work_limit; 1157 unsigned int i = tx_ring->next_to_clean; 1158 1159 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1160 return true; 1161 1162 tx_buffer = &tx_ring->tx_buffer_info[i]; 1163 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1164 i -= tx_ring->count; 1165 1166 do { 1167 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1168 1169 /* if next_to_watch is not set then there is no work pending */ 1170 if (!eop_desc) 1171 break; 1172 1173 /* prevent any other reads prior to eop_desc */ 1174 read_barrier_depends(); 1175 1176 /* if DD is not set pending work has not been completed */ 1177 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1178 break; 1179 1180 /* clear next_to_watch to prevent false hangs */ 1181 tx_buffer->next_to_watch = NULL; 1182 1183 /* update the statistics for this packet */ 1184 total_bytes += tx_buffer->bytecount; 1185 total_packets += tx_buffer->gso_segs; 1186 1187 /* free the skb */ 1188 napi_consume_skb(tx_buffer->skb, napi_budget); 1189 1190 /* unmap skb header data */ 1191 dma_unmap_single(tx_ring->dev, 1192 dma_unmap_addr(tx_buffer, dma), 1193 dma_unmap_len(tx_buffer, len), 1194 DMA_TO_DEVICE); 1195 1196 /* clear tx_buffer data */ 1197 tx_buffer->skb = NULL; 1198 dma_unmap_len_set(tx_buffer, len, 0); 1199 1200 /* unmap remaining buffers */ 1201 while (tx_desc != eop_desc) { 1202 tx_buffer++; 1203 tx_desc++; 1204 i++; 1205 if (unlikely(!i)) { 1206 i -= tx_ring->count; 1207 tx_buffer = tx_ring->tx_buffer_info; 1208 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1209 } 1210 1211 /* unmap any remaining paged data */ 1212 if (dma_unmap_len(tx_buffer, len)) { 1213 dma_unmap_page(tx_ring->dev, 1214 dma_unmap_addr(tx_buffer, dma), 1215 dma_unmap_len(tx_buffer, len), 1216 DMA_TO_DEVICE); 1217 dma_unmap_len_set(tx_buffer, len, 0); 1218 } 1219 } 1220 1221 /* move us one more past the eop_desc for start of next pkt */ 1222 tx_buffer++; 1223 tx_desc++; 1224 i++; 1225 if (unlikely(!i)) { 1226 i -= tx_ring->count; 1227 tx_buffer = tx_ring->tx_buffer_info; 1228 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1229 } 1230 1231 /* issue prefetch for next Tx descriptor */ 1232 prefetch(tx_desc); 1233 1234 /* update budget accounting */ 1235 budget--; 1236 } while (likely(budget)); 1237 1238 i += tx_ring->count; 1239 tx_ring->next_to_clean = i; 1240 u64_stats_update_begin(&tx_ring->syncp); 1241 tx_ring->stats.bytes += total_bytes; 1242 tx_ring->stats.packets += total_packets; 1243 u64_stats_update_end(&tx_ring->syncp); 1244 q_vector->tx.total_bytes += total_bytes; 1245 q_vector->tx.total_packets += total_packets; 1246 1247 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1248 /* schedule immediate reset if we believe we hung */ 1249 struct ixgbe_hw *hw = &adapter->hw; 1250 e_err(drv, "Detected Tx Unit Hang\n" 1251 " Tx Queue <%d>\n" 1252 " TDH, TDT <%x>, <%x>\n" 1253 " next_to_use <%x>\n" 1254 " next_to_clean <%x>\n" 1255 "tx_buffer_info[next_to_clean]\n" 1256 " time_stamp <%lx>\n" 1257 " jiffies <%lx>\n", 1258 tx_ring->queue_index, 1259 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1260 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1261 tx_ring->next_to_use, i, 1262 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1263 1264 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 1265 1266 e_info(probe, 1267 "tx hang %d detected on queue %d, resetting adapter\n", 1268 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1269 1270 /* schedule immediate reset if we believe we hung */ 1271 ixgbe_tx_timeout_reset(adapter); 1272 1273 /* the adapter is about to reset, no point in enabling stuff */ 1274 return true; 1275 } 1276 1277 netdev_tx_completed_queue(txring_txq(tx_ring), 1278 total_packets, total_bytes); 1279 1280 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1281 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1282 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1283 /* Make sure that anybody stopping the queue after this 1284 * sees the new next_to_clean. 1285 */ 1286 smp_mb(); 1287 if (__netif_subqueue_stopped(tx_ring->netdev, 1288 tx_ring->queue_index) 1289 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 1290 netif_wake_subqueue(tx_ring->netdev, 1291 tx_ring->queue_index); 1292 ++tx_ring->tx_stats.restart_queue; 1293 } 1294 } 1295 1296 return !!budget; 1297 } 1298 1299 #ifdef CONFIG_IXGBE_DCA 1300 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1301 struct ixgbe_ring *tx_ring, 1302 int cpu) 1303 { 1304 struct ixgbe_hw *hw = &adapter->hw; 1305 u32 txctrl = 0; 1306 u16 reg_offset; 1307 1308 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1309 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1310 1311 switch (hw->mac.type) { 1312 case ixgbe_mac_82598EB: 1313 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1314 break; 1315 case ixgbe_mac_82599EB: 1316 case ixgbe_mac_X540: 1317 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1318 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1319 break; 1320 default: 1321 /* for unknown hardware do not write register */ 1322 return; 1323 } 1324 1325 /* 1326 * We can enable relaxed ordering for reads, but not writes when 1327 * DCA is enabled. This is due to a known issue in some chipsets 1328 * which will cause the DCA tag to be cleared. 1329 */ 1330 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1331 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1332 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1333 1334 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1335 } 1336 1337 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1338 struct ixgbe_ring *rx_ring, 1339 int cpu) 1340 { 1341 struct ixgbe_hw *hw = &adapter->hw; 1342 u32 rxctrl = 0; 1343 u8 reg_idx = rx_ring->reg_idx; 1344 1345 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1346 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1347 1348 switch (hw->mac.type) { 1349 case ixgbe_mac_82599EB: 1350 case ixgbe_mac_X540: 1351 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1352 break; 1353 default: 1354 break; 1355 } 1356 1357 /* 1358 * We can enable relaxed ordering for reads, but not writes when 1359 * DCA is enabled. This is due to a known issue in some chipsets 1360 * which will cause the DCA tag to be cleared. 1361 */ 1362 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1363 IXGBE_DCA_RXCTRL_DATA_DCA_EN | 1364 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1365 1366 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1367 } 1368 1369 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1370 { 1371 struct ixgbe_adapter *adapter = q_vector->adapter; 1372 struct ixgbe_ring *ring; 1373 int cpu = get_cpu(); 1374 1375 if (q_vector->cpu == cpu) 1376 goto out_no_update; 1377 1378 ixgbe_for_each_ring(ring, q_vector->tx) 1379 ixgbe_update_tx_dca(adapter, ring, cpu); 1380 1381 ixgbe_for_each_ring(ring, q_vector->rx) 1382 ixgbe_update_rx_dca(adapter, ring, cpu); 1383 1384 q_vector->cpu = cpu; 1385 out_no_update: 1386 put_cpu(); 1387 } 1388 1389 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1390 { 1391 int i; 1392 1393 /* always use CB2 mode, difference is masked in the CB driver */ 1394 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1395 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1396 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1397 else 1398 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1399 IXGBE_DCA_CTRL_DCA_DISABLE); 1400 1401 for (i = 0; i < adapter->num_q_vectors; i++) { 1402 adapter->q_vector[i]->cpu = -1; 1403 ixgbe_update_dca(adapter->q_vector[i]); 1404 } 1405 } 1406 1407 static int __ixgbe_notify_dca(struct device *dev, void *data) 1408 { 1409 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1410 unsigned long event = *(unsigned long *)data; 1411 1412 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1413 return 0; 1414 1415 switch (event) { 1416 case DCA_PROVIDER_ADD: 1417 /* if we're already enabled, don't do it again */ 1418 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1419 break; 1420 if (dca_add_requester(dev) == 0) { 1421 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1422 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1423 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1424 break; 1425 } 1426 /* Fall Through since DCA is disabled. */ 1427 case DCA_PROVIDER_REMOVE: 1428 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1429 dca_remove_requester(dev); 1430 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1431 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1432 IXGBE_DCA_CTRL_DCA_DISABLE); 1433 } 1434 break; 1435 } 1436 1437 return 0; 1438 } 1439 1440 #endif /* CONFIG_IXGBE_DCA */ 1441 1442 #define IXGBE_RSS_L4_TYPES_MASK \ 1443 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1444 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1445 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1446 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1447 1448 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1449 union ixgbe_adv_rx_desc *rx_desc, 1450 struct sk_buff *skb) 1451 { 1452 u16 rss_type; 1453 1454 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1455 return; 1456 1457 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1458 IXGBE_RXDADV_RSSTYPE_MASK; 1459 1460 if (!rss_type) 1461 return; 1462 1463 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1464 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1465 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1466 } 1467 1468 #ifdef IXGBE_FCOE 1469 /** 1470 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1471 * @ring: structure containing ring specific data 1472 * @rx_desc: advanced rx descriptor 1473 * 1474 * Returns : true if it is FCoE pkt 1475 */ 1476 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1477 union ixgbe_adv_rx_desc *rx_desc) 1478 { 1479 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1480 1481 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1482 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1483 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1484 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1485 } 1486 1487 #endif /* IXGBE_FCOE */ 1488 /** 1489 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1490 * @ring: structure containing ring specific data 1491 * @rx_desc: current Rx descriptor being processed 1492 * @skb: skb currently being received and modified 1493 **/ 1494 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1495 union ixgbe_adv_rx_desc *rx_desc, 1496 struct sk_buff *skb) 1497 { 1498 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1499 bool encap_pkt = false; 1500 1501 skb_checksum_none_assert(skb); 1502 1503 /* Rx csum disabled */ 1504 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1505 return; 1506 1507 /* check for VXLAN and Geneve packets */ 1508 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) { 1509 encap_pkt = true; 1510 skb->encapsulation = 1; 1511 } 1512 1513 /* if IP and error */ 1514 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1515 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1516 ring->rx_stats.csum_err++; 1517 return; 1518 } 1519 1520 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1521 return; 1522 1523 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1524 /* 1525 * 82599 errata, UDP frames with a 0 checksum can be marked as 1526 * checksum errors. 1527 */ 1528 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1529 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1530 return; 1531 1532 ring->rx_stats.csum_err++; 1533 return; 1534 } 1535 1536 /* It must be a TCP or UDP packet with a valid checksum */ 1537 skb->ip_summed = CHECKSUM_UNNECESSARY; 1538 if (encap_pkt) { 1539 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1540 return; 1541 1542 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1543 skb->ip_summed = CHECKSUM_NONE; 1544 return; 1545 } 1546 /* If we checked the outer header let the stack know */ 1547 skb->csum_level = 1; 1548 } 1549 } 1550 1551 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1552 struct ixgbe_rx_buffer *bi) 1553 { 1554 struct page *page = bi->page; 1555 dma_addr_t dma; 1556 1557 /* since we are recycling buffers we should seldom need to alloc */ 1558 if (likely(page)) 1559 return true; 1560 1561 /* alloc new page for storage */ 1562 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1563 if (unlikely(!page)) { 1564 rx_ring->rx_stats.alloc_rx_page_failed++; 1565 return false; 1566 } 1567 1568 /* map page for use */ 1569 dma = dma_map_page(rx_ring->dev, page, 0, 1570 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); 1571 1572 /* 1573 * if mapping failed free memory back to system since 1574 * there isn't much point in holding memory we can't use 1575 */ 1576 if (dma_mapping_error(rx_ring->dev, dma)) { 1577 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1578 1579 rx_ring->rx_stats.alloc_rx_page_failed++; 1580 return false; 1581 } 1582 1583 bi->dma = dma; 1584 bi->page = page; 1585 bi->page_offset = 0; 1586 1587 return true; 1588 } 1589 1590 /** 1591 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1592 * @rx_ring: ring to place buffers on 1593 * @cleaned_count: number of buffers to replace 1594 **/ 1595 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1596 { 1597 union ixgbe_adv_rx_desc *rx_desc; 1598 struct ixgbe_rx_buffer *bi; 1599 u16 i = rx_ring->next_to_use; 1600 1601 /* nothing to do */ 1602 if (!cleaned_count) 1603 return; 1604 1605 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1606 bi = &rx_ring->rx_buffer_info[i]; 1607 i -= rx_ring->count; 1608 1609 do { 1610 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1611 break; 1612 1613 /* 1614 * Refresh the desc even if buffer_addrs didn't change 1615 * because each write-back erases this info. 1616 */ 1617 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1618 1619 rx_desc++; 1620 bi++; 1621 i++; 1622 if (unlikely(!i)) { 1623 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1624 bi = rx_ring->rx_buffer_info; 1625 i -= rx_ring->count; 1626 } 1627 1628 /* clear the status bits for the next_to_use descriptor */ 1629 rx_desc->wb.upper.status_error = 0; 1630 1631 cleaned_count--; 1632 } while (cleaned_count); 1633 1634 i += rx_ring->count; 1635 1636 if (rx_ring->next_to_use != i) { 1637 rx_ring->next_to_use = i; 1638 1639 /* update next to alloc since we have filled the ring */ 1640 rx_ring->next_to_alloc = i; 1641 1642 /* Force memory writes to complete before letting h/w 1643 * know there are new descriptors to fetch. (Only 1644 * applicable for weak-ordered memory model archs, 1645 * such as IA-64). 1646 */ 1647 wmb(); 1648 writel(i, rx_ring->tail); 1649 } 1650 } 1651 1652 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1653 struct sk_buff *skb) 1654 { 1655 u16 hdr_len = skb_headlen(skb); 1656 1657 /* set gso_size to avoid messing up TCP MSS */ 1658 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1659 IXGBE_CB(skb)->append_cnt); 1660 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1661 } 1662 1663 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1664 struct sk_buff *skb) 1665 { 1666 /* if append_cnt is 0 then frame is not RSC */ 1667 if (!IXGBE_CB(skb)->append_cnt) 1668 return; 1669 1670 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1671 rx_ring->rx_stats.rsc_flush++; 1672 1673 ixgbe_set_rsc_gso_size(rx_ring, skb); 1674 1675 /* gso_size is computed using append_cnt so always clear it last */ 1676 IXGBE_CB(skb)->append_cnt = 0; 1677 } 1678 1679 /** 1680 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1681 * @rx_ring: rx descriptor ring packet is being transacted on 1682 * @rx_desc: pointer to the EOP Rx descriptor 1683 * @skb: pointer to current skb being populated 1684 * 1685 * This function checks the ring, descriptor, and packet information in 1686 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1687 * other fields within the skb. 1688 **/ 1689 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1690 union ixgbe_adv_rx_desc *rx_desc, 1691 struct sk_buff *skb) 1692 { 1693 struct net_device *dev = rx_ring->netdev; 1694 u32 flags = rx_ring->q_vector->adapter->flags; 1695 1696 ixgbe_update_rsc_stats(rx_ring, skb); 1697 1698 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1699 1700 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1701 1702 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) 1703 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 1704 1705 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1706 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1707 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1708 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1709 } 1710 1711 skb_record_rx_queue(skb, rx_ring->queue_index); 1712 1713 skb->protocol = eth_type_trans(skb, dev); 1714 } 1715 1716 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1717 struct sk_buff *skb) 1718 { 1719 skb_mark_napi_id(skb, &q_vector->napi); 1720 if (ixgbe_qv_busy_polling(q_vector)) 1721 netif_receive_skb(skb); 1722 else 1723 napi_gro_receive(&q_vector->napi, skb); 1724 } 1725 1726 /** 1727 * ixgbe_is_non_eop - process handling of non-EOP buffers 1728 * @rx_ring: Rx ring being processed 1729 * @rx_desc: Rx descriptor for current buffer 1730 * @skb: Current socket buffer containing buffer in progress 1731 * 1732 * This function updates next to clean. If the buffer is an EOP buffer 1733 * this function exits returning false, otherwise it will place the 1734 * sk_buff in the next buffer to be chained and return true indicating 1735 * that this is in fact a non-EOP buffer. 1736 **/ 1737 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1738 union ixgbe_adv_rx_desc *rx_desc, 1739 struct sk_buff *skb) 1740 { 1741 u32 ntc = rx_ring->next_to_clean + 1; 1742 1743 /* fetch, update, and store next to clean */ 1744 ntc = (ntc < rx_ring->count) ? ntc : 0; 1745 rx_ring->next_to_clean = ntc; 1746 1747 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1748 1749 /* update RSC append count if present */ 1750 if (ring_is_rsc_enabled(rx_ring)) { 1751 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1752 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1753 1754 if (unlikely(rsc_enabled)) { 1755 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1756 1757 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1758 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1759 1760 /* update ntc based on RSC value */ 1761 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1762 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1763 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1764 } 1765 } 1766 1767 /* if we are the last buffer then there is nothing else to do */ 1768 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1769 return false; 1770 1771 /* place skb in next buffer to be received */ 1772 rx_ring->rx_buffer_info[ntc].skb = skb; 1773 rx_ring->rx_stats.non_eop_descs++; 1774 1775 return true; 1776 } 1777 1778 /** 1779 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1780 * @rx_ring: rx descriptor ring packet is being transacted on 1781 * @skb: pointer to current skb being adjusted 1782 * 1783 * This function is an ixgbe specific version of __pskb_pull_tail. The 1784 * main difference between this version and the original function is that 1785 * this function can make several assumptions about the state of things 1786 * that allow for significant optimizations versus the standard function. 1787 * As a result we can do things like drop a frag and maintain an accurate 1788 * truesize for the skb. 1789 */ 1790 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1791 struct sk_buff *skb) 1792 { 1793 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1794 unsigned char *va; 1795 unsigned int pull_len; 1796 1797 /* 1798 * it is valid to use page_address instead of kmap since we are 1799 * working with pages allocated out of the lomem pool per 1800 * alloc_page(GFP_ATOMIC) 1801 */ 1802 va = skb_frag_address(frag); 1803 1804 /* 1805 * we need the header to contain the greater of either ETH_HLEN or 1806 * 60 bytes if the skb->len is less than 60 for skb_pad. 1807 */ 1808 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE); 1809 1810 /* align pull length to size of long to optimize memcpy performance */ 1811 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1812 1813 /* update all of the pointers */ 1814 skb_frag_size_sub(frag, pull_len); 1815 frag->page_offset += pull_len; 1816 skb->data_len -= pull_len; 1817 skb->tail += pull_len; 1818 } 1819 1820 /** 1821 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1822 * @rx_ring: rx descriptor ring packet is being transacted on 1823 * @skb: pointer to current skb being updated 1824 * 1825 * This function provides a basic DMA sync up for the first fragment of an 1826 * skb. The reason for doing this is that the first fragment cannot be 1827 * unmapped until we have reached the end of packet descriptor for a buffer 1828 * chain. 1829 */ 1830 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1831 struct sk_buff *skb) 1832 { 1833 /* if the page was released unmap it, else just sync our portion */ 1834 if (unlikely(IXGBE_CB(skb)->page_released)) { 1835 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma, 1836 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); 1837 IXGBE_CB(skb)->page_released = false; 1838 } else { 1839 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1840 1841 dma_sync_single_range_for_cpu(rx_ring->dev, 1842 IXGBE_CB(skb)->dma, 1843 frag->page_offset, 1844 ixgbe_rx_bufsz(rx_ring), 1845 DMA_FROM_DEVICE); 1846 } 1847 IXGBE_CB(skb)->dma = 0; 1848 } 1849 1850 /** 1851 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1852 * @rx_ring: rx descriptor ring packet is being transacted on 1853 * @rx_desc: pointer to the EOP Rx descriptor 1854 * @skb: pointer to current skb being fixed 1855 * 1856 * Check for corrupted packet headers caused by senders on the local L2 1857 * embedded NIC switch not setting up their Tx Descriptors right. These 1858 * should be very rare. 1859 * 1860 * Also address the case where we are pulling data in on pages only 1861 * and as such no data is present in the skb header. 1862 * 1863 * In addition if skb is not at least 60 bytes we need to pad it so that 1864 * it is large enough to qualify as a valid Ethernet frame. 1865 * 1866 * Returns true if an error was encountered and skb was freed. 1867 **/ 1868 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1869 union ixgbe_adv_rx_desc *rx_desc, 1870 struct sk_buff *skb) 1871 { 1872 struct net_device *netdev = rx_ring->netdev; 1873 1874 /* verify that the packet does not have any known errors */ 1875 if (unlikely(ixgbe_test_staterr(rx_desc, 1876 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1877 !(netdev->features & NETIF_F_RXALL))) { 1878 dev_kfree_skb_any(skb); 1879 return true; 1880 } 1881 1882 /* place header in linear portion of buffer */ 1883 if (skb_is_nonlinear(skb)) 1884 ixgbe_pull_tail(rx_ring, skb); 1885 1886 #ifdef IXGBE_FCOE 1887 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1888 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1889 return false; 1890 1891 #endif 1892 /* if eth_skb_pad returns an error the skb was freed */ 1893 if (eth_skb_pad(skb)) 1894 return true; 1895 1896 return false; 1897 } 1898 1899 /** 1900 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1901 * @rx_ring: rx descriptor ring to store buffers on 1902 * @old_buff: donor buffer to have page reused 1903 * 1904 * Synchronizes page for reuse by the adapter 1905 **/ 1906 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1907 struct ixgbe_rx_buffer *old_buff) 1908 { 1909 struct ixgbe_rx_buffer *new_buff; 1910 u16 nta = rx_ring->next_to_alloc; 1911 1912 new_buff = &rx_ring->rx_buffer_info[nta]; 1913 1914 /* update, and store next to alloc */ 1915 nta++; 1916 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1917 1918 /* transfer page from old buffer to new buffer */ 1919 *new_buff = *old_buff; 1920 1921 /* sync the buffer for use by the device */ 1922 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma, 1923 new_buff->page_offset, 1924 ixgbe_rx_bufsz(rx_ring), 1925 DMA_FROM_DEVICE); 1926 } 1927 1928 static inline bool ixgbe_page_is_reserved(struct page *page) 1929 { 1930 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 1931 } 1932 1933 /** 1934 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 1935 * @rx_ring: rx descriptor ring to transact packets on 1936 * @rx_buffer: buffer containing page to add 1937 * @rx_desc: descriptor containing length of buffer written by hardware 1938 * @skb: sk_buff to place the data into 1939 * 1940 * This function will add the data contained in rx_buffer->page to the skb. 1941 * This is done either through a direct copy if the data in the buffer is 1942 * less than the skb header size, otherwise it will just attach the page as 1943 * a frag to the skb. 1944 * 1945 * The function will then update the page offset if necessary and return 1946 * true if the buffer can be reused by the adapter. 1947 **/ 1948 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 1949 struct ixgbe_rx_buffer *rx_buffer, 1950 union ixgbe_adv_rx_desc *rx_desc, 1951 struct sk_buff *skb) 1952 { 1953 struct page *page = rx_buffer->page; 1954 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 1955 #if (PAGE_SIZE < 8192) 1956 unsigned int truesize = ixgbe_rx_bufsz(rx_ring); 1957 #else 1958 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 1959 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) - 1960 ixgbe_rx_bufsz(rx_ring); 1961 #endif 1962 1963 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) { 1964 unsigned char *va = page_address(page) + rx_buffer->page_offset; 1965 1966 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 1967 1968 /* page is not reserved, we can reuse buffer as-is */ 1969 if (likely(!ixgbe_page_is_reserved(page))) 1970 return true; 1971 1972 /* this page cannot be reused so discard it */ 1973 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1974 return false; 1975 } 1976 1977 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 1978 rx_buffer->page_offset, size, truesize); 1979 1980 /* avoid re-using remote pages */ 1981 if (unlikely(ixgbe_page_is_reserved(page))) 1982 return false; 1983 1984 #if (PAGE_SIZE < 8192) 1985 /* if we are only owner of page we can reuse it */ 1986 if (unlikely(page_count(page) != 1)) 1987 return false; 1988 1989 /* flip page offset to other buffer */ 1990 rx_buffer->page_offset ^= truesize; 1991 #else 1992 /* move offset up to the next cache line */ 1993 rx_buffer->page_offset += truesize; 1994 1995 if (rx_buffer->page_offset > last_offset) 1996 return false; 1997 #endif 1998 1999 /* Even if we own the page, we are not allowed to use atomic_set() 2000 * This would break get_page_unless_zero() users. 2001 */ 2002 page_ref_inc(page); 2003 2004 return true; 2005 } 2006 2007 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring, 2008 union ixgbe_adv_rx_desc *rx_desc) 2009 { 2010 struct ixgbe_rx_buffer *rx_buffer; 2011 struct sk_buff *skb; 2012 struct page *page; 2013 2014 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 2015 page = rx_buffer->page; 2016 prefetchw(page); 2017 2018 skb = rx_buffer->skb; 2019 2020 if (likely(!skb)) { 2021 void *page_addr = page_address(page) + 2022 rx_buffer->page_offset; 2023 2024 /* prefetch first cache line of first page */ 2025 prefetch(page_addr); 2026 #if L1_CACHE_BYTES < 128 2027 prefetch(page_addr + L1_CACHE_BYTES); 2028 #endif 2029 2030 /* allocate a skb to store the frags */ 2031 skb = napi_alloc_skb(&rx_ring->q_vector->napi, 2032 IXGBE_RX_HDR_SIZE); 2033 if (unlikely(!skb)) { 2034 rx_ring->rx_stats.alloc_rx_buff_failed++; 2035 return NULL; 2036 } 2037 2038 /* 2039 * we will be copying header into skb->data in 2040 * pskb_may_pull so it is in our interest to prefetch 2041 * it now to avoid a possible cache miss 2042 */ 2043 prefetchw(skb->data); 2044 2045 /* 2046 * Delay unmapping of the first packet. It carries the 2047 * header information, HW may still access the header 2048 * after the writeback. Only unmap it when EOP is 2049 * reached 2050 */ 2051 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 2052 goto dma_sync; 2053 2054 IXGBE_CB(skb)->dma = rx_buffer->dma; 2055 } else { 2056 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2057 ixgbe_dma_sync_frag(rx_ring, skb); 2058 2059 dma_sync: 2060 /* we are reusing so sync this buffer for CPU use */ 2061 dma_sync_single_range_for_cpu(rx_ring->dev, 2062 rx_buffer->dma, 2063 rx_buffer->page_offset, 2064 ixgbe_rx_bufsz(rx_ring), 2065 DMA_FROM_DEVICE); 2066 2067 rx_buffer->skb = NULL; 2068 } 2069 2070 /* pull page into skb */ 2071 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 2072 /* hand second half of page back to the ring */ 2073 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2074 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) { 2075 /* the page has been released from the ring */ 2076 IXGBE_CB(skb)->page_released = true; 2077 } else { 2078 /* we are not reusing the buffer so unmap it */ 2079 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 2080 ixgbe_rx_pg_size(rx_ring), 2081 DMA_FROM_DEVICE); 2082 } 2083 2084 /* clear contents of buffer_info */ 2085 rx_buffer->page = NULL; 2086 2087 return skb; 2088 } 2089 2090 /** 2091 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2092 * @q_vector: structure containing interrupt and ring information 2093 * @rx_ring: rx descriptor ring to transact packets on 2094 * @budget: Total limit on number of packets to process 2095 * 2096 * This function provides a "bounce buffer" approach to Rx interrupt 2097 * processing. The advantage to this is that on systems that have 2098 * expensive overhead for IOMMU access this provides a means of avoiding 2099 * it by maintaining the mapping of the page to the syste. 2100 * 2101 * Returns amount of work completed 2102 **/ 2103 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2104 struct ixgbe_ring *rx_ring, 2105 const int budget) 2106 { 2107 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 2108 #ifdef IXGBE_FCOE 2109 struct ixgbe_adapter *adapter = q_vector->adapter; 2110 int ddp_bytes; 2111 unsigned int mss = 0; 2112 #endif /* IXGBE_FCOE */ 2113 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2114 2115 while (likely(total_rx_packets < budget)) { 2116 union ixgbe_adv_rx_desc *rx_desc; 2117 struct sk_buff *skb; 2118 2119 /* return some buffers to hardware, one at a time is too slow */ 2120 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2121 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2122 cleaned_count = 0; 2123 } 2124 2125 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2126 2127 if (!rx_desc->wb.upper.status_error) 2128 break; 2129 2130 /* This memory barrier is needed to keep us from reading 2131 * any other fields out of the rx_desc until we know the 2132 * descriptor has been written back 2133 */ 2134 dma_rmb(); 2135 2136 /* retrieve a buffer from the ring */ 2137 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc); 2138 2139 /* exit if we failed to retrieve a buffer */ 2140 if (!skb) 2141 break; 2142 2143 cleaned_count++; 2144 2145 /* place incomplete frames back on ring for completion */ 2146 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2147 continue; 2148 2149 /* verify the packet layout is correct */ 2150 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2151 continue; 2152 2153 /* probably a little skewed due to removing CRC */ 2154 total_rx_bytes += skb->len; 2155 2156 /* populate checksum, timestamp, VLAN, and protocol */ 2157 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2158 2159 #ifdef IXGBE_FCOE 2160 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2161 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2162 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2163 /* include DDPed FCoE data */ 2164 if (ddp_bytes > 0) { 2165 if (!mss) { 2166 mss = rx_ring->netdev->mtu - 2167 sizeof(struct fcoe_hdr) - 2168 sizeof(struct fc_frame_header) - 2169 sizeof(struct fcoe_crc_eof); 2170 if (mss > 512) 2171 mss &= ~511; 2172 } 2173 total_rx_bytes += ddp_bytes; 2174 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2175 mss); 2176 } 2177 if (!ddp_bytes) { 2178 dev_kfree_skb_any(skb); 2179 continue; 2180 } 2181 } 2182 2183 #endif /* IXGBE_FCOE */ 2184 ixgbe_rx_skb(q_vector, skb); 2185 2186 /* update budget accounting */ 2187 total_rx_packets++; 2188 } 2189 2190 u64_stats_update_begin(&rx_ring->syncp); 2191 rx_ring->stats.packets += total_rx_packets; 2192 rx_ring->stats.bytes += total_rx_bytes; 2193 u64_stats_update_end(&rx_ring->syncp); 2194 q_vector->rx.total_packets += total_rx_packets; 2195 q_vector->rx.total_bytes += total_rx_bytes; 2196 2197 return total_rx_packets; 2198 } 2199 2200 #ifdef CONFIG_NET_RX_BUSY_POLL 2201 /* must be called with local_bh_disable()d */ 2202 static int ixgbe_low_latency_recv(struct napi_struct *napi) 2203 { 2204 struct ixgbe_q_vector *q_vector = 2205 container_of(napi, struct ixgbe_q_vector, napi); 2206 struct ixgbe_adapter *adapter = q_vector->adapter; 2207 struct ixgbe_ring *ring; 2208 int found = 0; 2209 2210 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2211 return LL_FLUSH_FAILED; 2212 2213 if (!ixgbe_qv_lock_poll(q_vector)) 2214 return LL_FLUSH_BUSY; 2215 2216 ixgbe_for_each_ring(ring, q_vector->rx) { 2217 found = ixgbe_clean_rx_irq(q_vector, ring, 4); 2218 #ifdef BP_EXTENDED_STATS 2219 if (found) 2220 ring->stats.cleaned += found; 2221 else 2222 ring->stats.misses++; 2223 #endif 2224 if (found) 2225 break; 2226 } 2227 2228 ixgbe_qv_unlock_poll(q_vector); 2229 2230 return found; 2231 } 2232 #endif /* CONFIG_NET_RX_BUSY_POLL */ 2233 2234 /** 2235 * ixgbe_configure_msix - Configure MSI-X hardware 2236 * @adapter: board private structure 2237 * 2238 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2239 * interrupts. 2240 **/ 2241 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2242 { 2243 struct ixgbe_q_vector *q_vector; 2244 int v_idx; 2245 u32 mask; 2246 2247 /* Populate MSIX to EITR Select */ 2248 if (adapter->num_vfs > 32) { 2249 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; 2250 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2251 } 2252 2253 /* 2254 * Populate the IVAR table and set the ITR values to the 2255 * corresponding register. 2256 */ 2257 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2258 struct ixgbe_ring *ring; 2259 q_vector = adapter->q_vector[v_idx]; 2260 2261 ixgbe_for_each_ring(ring, q_vector->rx) 2262 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2263 2264 ixgbe_for_each_ring(ring, q_vector->tx) 2265 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2266 2267 ixgbe_write_eitr(q_vector); 2268 } 2269 2270 switch (adapter->hw.mac.type) { 2271 case ixgbe_mac_82598EB: 2272 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2273 v_idx); 2274 break; 2275 case ixgbe_mac_82599EB: 2276 case ixgbe_mac_X540: 2277 case ixgbe_mac_X550: 2278 case ixgbe_mac_X550EM_x: 2279 case ixgbe_mac_x550em_a: 2280 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2281 break; 2282 default: 2283 break; 2284 } 2285 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2286 2287 /* set up to autoclear timer, and the vectors */ 2288 mask = IXGBE_EIMS_ENABLE_MASK; 2289 mask &= ~(IXGBE_EIMS_OTHER | 2290 IXGBE_EIMS_MAILBOX | 2291 IXGBE_EIMS_LSC); 2292 2293 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2294 } 2295 2296 enum latency_range { 2297 lowest_latency = 0, 2298 low_latency = 1, 2299 bulk_latency = 2, 2300 latency_invalid = 255 2301 }; 2302 2303 /** 2304 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2305 * @q_vector: structure containing interrupt and ring information 2306 * @ring_container: structure containing ring performance data 2307 * 2308 * Stores a new ITR value based on packets and byte 2309 * counts during the last interrupt. The advantage of per interrupt 2310 * computation is faster updates and more accurate ITR for the current 2311 * traffic pattern. Constants in this function were computed 2312 * based on theoretical maximum wire speed and thresholds were set based 2313 * on testing data as well as attempting to minimize response time 2314 * while increasing bulk throughput. 2315 * this functionality is controlled by the InterruptThrottleRate module 2316 * parameter (see ixgbe_param.c) 2317 **/ 2318 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2319 struct ixgbe_ring_container *ring_container) 2320 { 2321 int bytes = ring_container->total_bytes; 2322 int packets = ring_container->total_packets; 2323 u32 timepassed_us; 2324 u64 bytes_perint; 2325 u8 itr_setting = ring_container->itr; 2326 2327 if (packets == 0) 2328 return; 2329 2330 /* simple throttlerate management 2331 * 0-10MB/s lowest (100000 ints/s) 2332 * 10-20MB/s low (20000 ints/s) 2333 * 20-1249MB/s bulk (12000 ints/s) 2334 */ 2335 /* what was last interrupt timeslice? */ 2336 timepassed_us = q_vector->itr >> 2; 2337 if (timepassed_us == 0) 2338 return; 2339 2340 bytes_perint = bytes / timepassed_us; /* bytes/usec */ 2341 2342 switch (itr_setting) { 2343 case lowest_latency: 2344 if (bytes_perint > 10) 2345 itr_setting = low_latency; 2346 break; 2347 case low_latency: 2348 if (bytes_perint > 20) 2349 itr_setting = bulk_latency; 2350 else if (bytes_perint <= 10) 2351 itr_setting = lowest_latency; 2352 break; 2353 case bulk_latency: 2354 if (bytes_perint <= 20) 2355 itr_setting = low_latency; 2356 break; 2357 } 2358 2359 /* clear work counters since we have the values we need */ 2360 ring_container->total_bytes = 0; 2361 ring_container->total_packets = 0; 2362 2363 /* write updated itr to ring container */ 2364 ring_container->itr = itr_setting; 2365 } 2366 2367 /** 2368 * ixgbe_write_eitr - write EITR register in hardware specific way 2369 * @q_vector: structure containing interrupt and ring information 2370 * 2371 * This function is made to be called by ethtool and by the driver 2372 * when it needs to update EITR registers at runtime. Hardware 2373 * specific quirks/differences are taken care of here. 2374 */ 2375 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2376 { 2377 struct ixgbe_adapter *adapter = q_vector->adapter; 2378 struct ixgbe_hw *hw = &adapter->hw; 2379 int v_idx = q_vector->v_idx; 2380 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2381 2382 switch (adapter->hw.mac.type) { 2383 case ixgbe_mac_82598EB: 2384 /* must write high and low 16 bits to reset counter */ 2385 itr_reg |= (itr_reg << 16); 2386 break; 2387 case ixgbe_mac_82599EB: 2388 case ixgbe_mac_X540: 2389 case ixgbe_mac_X550: 2390 case ixgbe_mac_X550EM_x: 2391 case ixgbe_mac_x550em_a: 2392 /* 2393 * set the WDIS bit to not clear the timer bits and cause an 2394 * immediate assertion of the interrupt 2395 */ 2396 itr_reg |= IXGBE_EITR_CNT_WDIS; 2397 break; 2398 default: 2399 break; 2400 } 2401 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2402 } 2403 2404 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2405 { 2406 u32 new_itr = q_vector->itr; 2407 u8 current_itr; 2408 2409 ixgbe_update_itr(q_vector, &q_vector->tx); 2410 ixgbe_update_itr(q_vector, &q_vector->rx); 2411 2412 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 2413 2414 switch (current_itr) { 2415 /* counts and packets in update_itr are dependent on these numbers */ 2416 case lowest_latency: 2417 new_itr = IXGBE_100K_ITR; 2418 break; 2419 case low_latency: 2420 new_itr = IXGBE_20K_ITR; 2421 break; 2422 case bulk_latency: 2423 new_itr = IXGBE_12K_ITR; 2424 break; 2425 default: 2426 break; 2427 } 2428 2429 if (new_itr != q_vector->itr) { 2430 /* do an exponential smoothing */ 2431 new_itr = (10 * new_itr * q_vector->itr) / 2432 ((9 * new_itr) + q_vector->itr); 2433 2434 /* save the algorithm value here */ 2435 q_vector->itr = new_itr; 2436 2437 ixgbe_write_eitr(q_vector); 2438 } 2439 } 2440 2441 /** 2442 * ixgbe_check_overtemp_subtask - check for over temperature 2443 * @adapter: pointer to adapter 2444 **/ 2445 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2446 { 2447 struct ixgbe_hw *hw = &adapter->hw; 2448 u32 eicr = adapter->interrupt_event; 2449 2450 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2451 return; 2452 2453 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && 2454 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2455 return; 2456 2457 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2458 2459 switch (hw->device_id) { 2460 case IXGBE_DEV_ID_82599_T3_LOM: 2461 /* 2462 * Since the warning interrupt is for both ports 2463 * we don't have to check if: 2464 * - This interrupt wasn't for our port. 2465 * - We may have missed the interrupt so always have to 2466 * check if we got a LSC 2467 */ 2468 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2469 !(eicr & IXGBE_EICR_LSC)) 2470 return; 2471 2472 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2473 u32 speed; 2474 bool link_up = false; 2475 2476 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2477 2478 if (link_up) 2479 return; 2480 } 2481 2482 /* Check if this is not due to overtemp */ 2483 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) 2484 return; 2485 2486 break; 2487 default: 2488 if (adapter->hw.mac.type >= ixgbe_mac_X540) 2489 return; 2490 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 2491 return; 2492 break; 2493 } 2494 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2495 2496 adapter->interrupt_event = 0; 2497 } 2498 2499 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2500 { 2501 struct ixgbe_hw *hw = &adapter->hw; 2502 2503 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2504 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2505 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2506 /* write to clear the interrupt */ 2507 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2508 } 2509 } 2510 2511 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2512 { 2513 struct ixgbe_hw *hw = &adapter->hw; 2514 2515 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2516 return; 2517 2518 switch (adapter->hw.mac.type) { 2519 case ixgbe_mac_82599EB: 2520 /* 2521 * Need to check link state so complete overtemp check 2522 * on service task 2523 */ 2524 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 2525 (eicr & IXGBE_EICR_LSC)) && 2526 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2527 adapter->interrupt_event = eicr; 2528 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2529 ixgbe_service_event_schedule(adapter); 2530 return; 2531 } 2532 return; 2533 case ixgbe_mac_X540: 2534 if (!(eicr & IXGBE_EICR_TS)) 2535 return; 2536 break; 2537 default: 2538 return; 2539 } 2540 2541 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2542 } 2543 2544 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 2545 { 2546 switch (hw->mac.type) { 2547 case ixgbe_mac_82598EB: 2548 if (hw->phy.type == ixgbe_phy_nl) 2549 return true; 2550 return false; 2551 case ixgbe_mac_82599EB: 2552 case ixgbe_mac_X550EM_x: 2553 case ixgbe_mac_x550em_a: 2554 switch (hw->mac.ops.get_media_type(hw)) { 2555 case ixgbe_media_type_fiber: 2556 case ixgbe_media_type_fiber_qsfp: 2557 return true; 2558 default: 2559 return false; 2560 } 2561 default: 2562 return false; 2563 } 2564 } 2565 2566 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2567 { 2568 struct ixgbe_hw *hw = &adapter->hw; 2569 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); 2570 2571 if (!ixgbe_is_sfp(hw)) 2572 return; 2573 2574 /* Later MAC's use different SDP */ 2575 if (hw->mac.type >= ixgbe_mac_X540) 2576 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2577 2578 if (eicr & eicr_mask) { 2579 /* Clear the interrupt */ 2580 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2581 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2582 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2583 adapter->sfp_poll_time = 0; 2584 ixgbe_service_event_schedule(adapter); 2585 } 2586 } 2587 2588 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 2589 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2590 /* Clear the interrupt */ 2591 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2592 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2593 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2594 ixgbe_service_event_schedule(adapter); 2595 } 2596 } 2597 } 2598 2599 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2600 { 2601 struct ixgbe_hw *hw = &adapter->hw; 2602 2603 adapter->lsc_int++; 2604 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2605 adapter->link_check_timeout = jiffies; 2606 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2607 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2608 IXGBE_WRITE_FLUSH(hw); 2609 ixgbe_service_event_schedule(adapter); 2610 } 2611 } 2612 2613 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2614 u64 qmask) 2615 { 2616 u32 mask; 2617 struct ixgbe_hw *hw = &adapter->hw; 2618 2619 switch (hw->mac.type) { 2620 case ixgbe_mac_82598EB: 2621 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2622 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2623 break; 2624 case ixgbe_mac_82599EB: 2625 case ixgbe_mac_X540: 2626 case ixgbe_mac_X550: 2627 case ixgbe_mac_X550EM_x: 2628 case ixgbe_mac_x550em_a: 2629 mask = (qmask & 0xFFFFFFFF); 2630 if (mask) 2631 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2632 mask = (qmask >> 32); 2633 if (mask) 2634 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2635 break; 2636 default: 2637 break; 2638 } 2639 /* skip the flush */ 2640 } 2641 2642 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, 2643 u64 qmask) 2644 { 2645 u32 mask; 2646 struct ixgbe_hw *hw = &adapter->hw; 2647 2648 switch (hw->mac.type) { 2649 case ixgbe_mac_82598EB: 2650 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2651 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 2652 break; 2653 case ixgbe_mac_82599EB: 2654 case ixgbe_mac_X540: 2655 case ixgbe_mac_X550: 2656 case ixgbe_mac_X550EM_x: 2657 case ixgbe_mac_x550em_a: 2658 mask = (qmask & 0xFFFFFFFF); 2659 if (mask) 2660 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 2661 mask = (qmask >> 32); 2662 if (mask) 2663 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 2664 break; 2665 default: 2666 break; 2667 } 2668 /* skip the flush */ 2669 } 2670 2671 /** 2672 * ixgbe_irq_enable - Enable default interrupt generation settings 2673 * @adapter: board private structure 2674 **/ 2675 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 2676 bool flush) 2677 { 2678 struct ixgbe_hw *hw = &adapter->hw; 2679 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 2680 2681 /* don't reenable LSC while waiting for link */ 2682 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 2683 mask &= ~IXGBE_EIMS_LSC; 2684 2685 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 2686 switch (adapter->hw.mac.type) { 2687 case ixgbe_mac_82599EB: 2688 mask |= IXGBE_EIMS_GPI_SDP0(hw); 2689 break; 2690 case ixgbe_mac_X540: 2691 case ixgbe_mac_X550: 2692 case ixgbe_mac_X550EM_x: 2693 case ixgbe_mac_x550em_a: 2694 mask |= IXGBE_EIMS_TS; 2695 break; 2696 default: 2697 break; 2698 } 2699 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 2700 mask |= IXGBE_EIMS_GPI_SDP1(hw); 2701 switch (adapter->hw.mac.type) { 2702 case ixgbe_mac_82599EB: 2703 mask |= IXGBE_EIMS_GPI_SDP1(hw); 2704 mask |= IXGBE_EIMS_GPI_SDP2(hw); 2705 /* fall through */ 2706 case ixgbe_mac_X540: 2707 case ixgbe_mac_X550: 2708 case ixgbe_mac_X550EM_x: 2709 case ixgbe_mac_x550em_a: 2710 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || 2711 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || 2712 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) 2713 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); 2714 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 2715 mask |= IXGBE_EICR_GPI_SDP0_X540; 2716 mask |= IXGBE_EIMS_ECC; 2717 mask |= IXGBE_EIMS_MAILBOX; 2718 break; 2719 default: 2720 break; 2721 } 2722 2723 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 2724 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 2725 mask |= IXGBE_EIMS_FLOW_DIR; 2726 2727 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 2728 if (queues) 2729 ixgbe_irq_enable_queues(adapter, ~0); 2730 if (flush) 2731 IXGBE_WRITE_FLUSH(&adapter->hw); 2732 } 2733 2734 static irqreturn_t ixgbe_msix_other(int irq, void *data) 2735 { 2736 struct ixgbe_adapter *adapter = data; 2737 struct ixgbe_hw *hw = &adapter->hw; 2738 u32 eicr; 2739 2740 /* 2741 * Workaround for Silicon errata. Use clear-by-write instead 2742 * of clear-by-read. Reading with EICS will return the 2743 * interrupt causes without clearing, which later be done 2744 * with the write to EICR. 2745 */ 2746 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 2747 2748 /* The lower 16bits of the EICR register are for the queue interrupts 2749 * which should be masked here in order to not accidentally clear them if 2750 * the bits are high when ixgbe_msix_other is called. There is a race 2751 * condition otherwise which results in possible performance loss 2752 * especially if the ixgbe_msix_other interrupt is triggering 2753 * consistently (as it would when PPS is turned on for the X540 device) 2754 */ 2755 eicr &= 0xFFFF0000; 2756 2757 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 2758 2759 if (eicr & IXGBE_EICR_LSC) 2760 ixgbe_check_lsc(adapter); 2761 2762 if (eicr & IXGBE_EICR_MAILBOX) 2763 ixgbe_msg_task(adapter); 2764 2765 switch (hw->mac.type) { 2766 case ixgbe_mac_82599EB: 2767 case ixgbe_mac_X540: 2768 case ixgbe_mac_X550: 2769 case ixgbe_mac_X550EM_x: 2770 case ixgbe_mac_x550em_a: 2771 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 2772 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 2773 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 2774 ixgbe_service_event_schedule(adapter); 2775 IXGBE_WRITE_REG(hw, IXGBE_EICR, 2776 IXGBE_EICR_GPI_SDP0_X540); 2777 } 2778 if (eicr & IXGBE_EICR_ECC) { 2779 e_info(link, "Received ECC Err, initiating reset\n"); 2780 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 2781 ixgbe_service_event_schedule(adapter); 2782 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 2783 } 2784 /* Handle Flow Director Full threshold interrupt */ 2785 if (eicr & IXGBE_EICR_FLOW_DIR) { 2786 int reinit_count = 0; 2787 int i; 2788 for (i = 0; i < adapter->num_tx_queues; i++) { 2789 struct ixgbe_ring *ring = adapter->tx_ring[i]; 2790 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 2791 &ring->state)) 2792 reinit_count++; 2793 } 2794 if (reinit_count) { 2795 /* no more flow director interrupts until after init */ 2796 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 2797 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 2798 ixgbe_service_event_schedule(adapter); 2799 } 2800 } 2801 ixgbe_check_sfp_event(adapter, eicr); 2802 ixgbe_check_overtemp_event(adapter, eicr); 2803 break; 2804 default: 2805 break; 2806 } 2807 2808 ixgbe_check_fan_failure(adapter, eicr); 2809 2810 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 2811 ixgbe_ptp_check_pps_event(adapter); 2812 2813 /* re-enable the original interrupt state, no lsc, no queues */ 2814 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2815 ixgbe_irq_enable(adapter, false, false); 2816 2817 return IRQ_HANDLED; 2818 } 2819 2820 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 2821 { 2822 struct ixgbe_q_vector *q_vector = data; 2823 2824 /* EIAM disabled interrupts (on this vector) for us */ 2825 2826 if (q_vector->rx.ring || q_vector->tx.ring) 2827 napi_schedule_irqoff(&q_vector->napi); 2828 2829 return IRQ_HANDLED; 2830 } 2831 2832 /** 2833 * ixgbe_poll - NAPI Rx polling callback 2834 * @napi: structure for representing this polling device 2835 * @budget: how many packets driver is allowed to clean 2836 * 2837 * This function is used for legacy and MSI, NAPI mode 2838 **/ 2839 int ixgbe_poll(struct napi_struct *napi, int budget) 2840 { 2841 struct ixgbe_q_vector *q_vector = 2842 container_of(napi, struct ixgbe_q_vector, napi); 2843 struct ixgbe_adapter *adapter = q_vector->adapter; 2844 struct ixgbe_ring *ring; 2845 int per_ring_budget, work_done = 0; 2846 bool clean_complete = true; 2847 2848 #ifdef CONFIG_IXGBE_DCA 2849 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 2850 ixgbe_update_dca(q_vector); 2851 #endif 2852 2853 ixgbe_for_each_ring(ring, q_vector->tx) { 2854 if (!ixgbe_clean_tx_irq(q_vector, ring, budget)) 2855 clean_complete = false; 2856 } 2857 2858 /* Exit if we are called by netpoll or busy polling is active */ 2859 if ((budget <= 0) || !ixgbe_qv_lock_napi(q_vector)) 2860 return budget; 2861 2862 /* attempt to distribute budget to each queue fairly, but don't allow 2863 * the budget to go below 1 because we'll exit polling */ 2864 if (q_vector->rx.count > 1) 2865 per_ring_budget = max(budget/q_vector->rx.count, 1); 2866 else 2867 per_ring_budget = budget; 2868 2869 ixgbe_for_each_ring(ring, q_vector->rx) { 2870 int cleaned = ixgbe_clean_rx_irq(q_vector, ring, 2871 per_ring_budget); 2872 2873 work_done += cleaned; 2874 if (cleaned >= per_ring_budget) 2875 clean_complete = false; 2876 } 2877 2878 ixgbe_qv_unlock_napi(q_vector); 2879 /* If all work not completed, return budget and keep polling */ 2880 if (!clean_complete) 2881 return budget; 2882 2883 /* all work done, exit the polling mode */ 2884 napi_complete_done(napi, work_done); 2885 if (adapter->rx_itr_setting & 1) 2886 ixgbe_set_itr(q_vector); 2887 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2888 ixgbe_irq_enable_queues(adapter, BIT_ULL(q_vector->v_idx)); 2889 2890 return min(work_done, budget - 1); 2891 } 2892 2893 /** 2894 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 2895 * @adapter: board private structure 2896 * 2897 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 2898 * interrupts from the kernel. 2899 **/ 2900 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 2901 { 2902 struct net_device *netdev = adapter->netdev; 2903 int vector, err; 2904 int ri = 0, ti = 0; 2905 2906 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 2907 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 2908 struct msix_entry *entry = &adapter->msix_entries[vector]; 2909 2910 if (q_vector->tx.ring && q_vector->rx.ring) { 2911 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2912 "%s-%s-%d", netdev->name, "TxRx", ri++); 2913 ti++; 2914 } else if (q_vector->rx.ring) { 2915 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2916 "%s-%s-%d", netdev->name, "rx", ri++); 2917 } else if (q_vector->tx.ring) { 2918 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2919 "%s-%s-%d", netdev->name, "tx", ti++); 2920 } else { 2921 /* skip this unused q_vector */ 2922 continue; 2923 } 2924 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 2925 q_vector->name, q_vector); 2926 if (err) { 2927 e_err(probe, "request_irq failed for MSIX interrupt " 2928 "Error: %d\n", err); 2929 goto free_queue_irqs; 2930 } 2931 /* If Flow Director is enabled, set interrupt affinity */ 2932 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 2933 /* assign the mask for this irq */ 2934 irq_set_affinity_hint(entry->vector, 2935 &q_vector->affinity_mask); 2936 } 2937 } 2938 2939 err = request_irq(adapter->msix_entries[vector].vector, 2940 ixgbe_msix_other, 0, netdev->name, adapter); 2941 if (err) { 2942 e_err(probe, "request_irq for msix_other failed: %d\n", err); 2943 goto free_queue_irqs; 2944 } 2945 2946 return 0; 2947 2948 free_queue_irqs: 2949 while (vector) { 2950 vector--; 2951 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 2952 NULL); 2953 free_irq(adapter->msix_entries[vector].vector, 2954 adapter->q_vector[vector]); 2955 } 2956 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 2957 pci_disable_msix(adapter->pdev); 2958 kfree(adapter->msix_entries); 2959 adapter->msix_entries = NULL; 2960 return err; 2961 } 2962 2963 /** 2964 * ixgbe_intr - legacy mode Interrupt Handler 2965 * @irq: interrupt number 2966 * @data: pointer to a network interface device structure 2967 **/ 2968 static irqreturn_t ixgbe_intr(int irq, void *data) 2969 { 2970 struct ixgbe_adapter *adapter = data; 2971 struct ixgbe_hw *hw = &adapter->hw; 2972 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 2973 u32 eicr; 2974 2975 /* 2976 * Workaround for silicon errata #26 on 82598. Mask the interrupt 2977 * before the read of EICR. 2978 */ 2979 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 2980 2981 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 2982 * therefore no explicit interrupt disable is necessary */ 2983 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 2984 if (!eicr) { 2985 /* 2986 * shared interrupt alert! 2987 * make sure interrupts are enabled because the read will 2988 * have disabled interrupts due to EIAM 2989 * finish the workaround of silicon errata on 82598. Unmask 2990 * the interrupt that we masked before the EICR read. 2991 */ 2992 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2993 ixgbe_irq_enable(adapter, true, true); 2994 return IRQ_NONE; /* Not our interrupt */ 2995 } 2996 2997 if (eicr & IXGBE_EICR_LSC) 2998 ixgbe_check_lsc(adapter); 2999 3000 switch (hw->mac.type) { 3001 case ixgbe_mac_82599EB: 3002 ixgbe_check_sfp_event(adapter, eicr); 3003 /* Fall through */ 3004 case ixgbe_mac_X540: 3005 case ixgbe_mac_X550: 3006 case ixgbe_mac_X550EM_x: 3007 case ixgbe_mac_x550em_a: 3008 if (eicr & IXGBE_EICR_ECC) { 3009 e_info(link, "Received ECC Err, initiating reset\n"); 3010 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3011 ixgbe_service_event_schedule(adapter); 3012 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3013 } 3014 ixgbe_check_overtemp_event(adapter, eicr); 3015 break; 3016 default: 3017 break; 3018 } 3019 3020 ixgbe_check_fan_failure(adapter, eicr); 3021 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3022 ixgbe_ptp_check_pps_event(adapter); 3023 3024 /* would disable interrupts here but EIAM disabled it */ 3025 napi_schedule_irqoff(&q_vector->napi); 3026 3027 /* 3028 * re-enable link(maybe) and non-queue interrupts, no flush. 3029 * ixgbe_poll will re-enable the queue interrupts 3030 */ 3031 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3032 ixgbe_irq_enable(adapter, false, false); 3033 3034 return IRQ_HANDLED; 3035 } 3036 3037 /** 3038 * ixgbe_request_irq - initialize interrupts 3039 * @adapter: board private structure 3040 * 3041 * Attempts to configure interrupts using the best available 3042 * capabilities of the hardware and kernel. 3043 **/ 3044 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 3045 { 3046 struct net_device *netdev = adapter->netdev; 3047 int err; 3048 3049 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 3050 err = ixgbe_request_msix_irqs(adapter); 3051 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 3052 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 3053 netdev->name, adapter); 3054 else 3055 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 3056 netdev->name, adapter); 3057 3058 if (err) 3059 e_err(probe, "request_irq failed, Error %d\n", err); 3060 3061 return err; 3062 } 3063 3064 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 3065 { 3066 int vector; 3067 3068 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3069 free_irq(adapter->pdev->irq, adapter); 3070 return; 3071 } 3072 3073 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3074 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3075 struct msix_entry *entry = &adapter->msix_entries[vector]; 3076 3077 /* free only the irqs that were actually requested */ 3078 if (!q_vector->rx.ring && !q_vector->tx.ring) 3079 continue; 3080 3081 /* clear the affinity_mask in the IRQ descriptor */ 3082 irq_set_affinity_hint(entry->vector, NULL); 3083 3084 free_irq(entry->vector, q_vector); 3085 } 3086 3087 free_irq(adapter->msix_entries[vector].vector, adapter); 3088 } 3089 3090 /** 3091 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 3092 * @adapter: board private structure 3093 **/ 3094 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 3095 { 3096 switch (adapter->hw.mac.type) { 3097 case ixgbe_mac_82598EB: 3098 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3099 break; 3100 case ixgbe_mac_82599EB: 3101 case ixgbe_mac_X540: 3102 case ixgbe_mac_X550: 3103 case ixgbe_mac_X550EM_x: 3104 case ixgbe_mac_x550em_a: 3105 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3106 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3107 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3108 break; 3109 default: 3110 break; 3111 } 3112 IXGBE_WRITE_FLUSH(&adapter->hw); 3113 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3114 int vector; 3115 3116 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3117 synchronize_irq(adapter->msix_entries[vector].vector); 3118 3119 synchronize_irq(adapter->msix_entries[vector++].vector); 3120 } else { 3121 synchronize_irq(adapter->pdev->irq); 3122 } 3123 } 3124 3125 /** 3126 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3127 * 3128 **/ 3129 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3130 { 3131 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3132 3133 ixgbe_write_eitr(q_vector); 3134 3135 ixgbe_set_ivar(adapter, 0, 0, 0); 3136 ixgbe_set_ivar(adapter, 1, 0, 0); 3137 3138 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3139 } 3140 3141 /** 3142 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3143 * @adapter: board private structure 3144 * @ring: structure containing ring specific data 3145 * 3146 * Configure the Tx descriptor ring after a reset. 3147 **/ 3148 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3149 struct ixgbe_ring *ring) 3150 { 3151 struct ixgbe_hw *hw = &adapter->hw; 3152 u64 tdba = ring->dma; 3153 int wait_loop = 10; 3154 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3155 u8 reg_idx = ring->reg_idx; 3156 3157 /* disable queue to avoid issues while updating state */ 3158 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3159 IXGBE_WRITE_FLUSH(hw); 3160 3161 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3162 (tdba & DMA_BIT_MASK(32))); 3163 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3164 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3165 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3166 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3167 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3168 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3169 3170 /* 3171 * set WTHRESH to encourage burst writeback, it should not be set 3172 * higher than 1 when: 3173 * - ITR is 0 as it could cause false TX hangs 3174 * - ITR is set to > 100k int/sec and BQL is enabled 3175 * 3176 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3177 * to or less than the number of on chip descriptors, which is 3178 * currently 40. 3179 */ 3180 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3181 txdctl |= 1u << 16; /* WTHRESH = 1 */ 3182 else 3183 txdctl |= 8u << 16; /* WTHRESH = 8 */ 3184 3185 /* 3186 * Setting PTHRESH to 32 both improves performance 3187 * and avoids a TX hang with DFP enabled 3188 */ 3189 txdctl |= (1u << 8) | /* HTHRESH = 1 */ 3190 32; /* PTHRESH = 32 */ 3191 3192 /* reinitialize flowdirector state */ 3193 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3194 ring->atr_sample_rate = adapter->atr_sample_rate; 3195 ring->atr_count = 0; 3196 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3197 } else { 3198 ring->atr_sample_rate = 0; 3199 } 3200 3201 /* initialize XPS */ 3202 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3203 struct ixgbe_q_vector *q_vector = ring->q_vector; 3204 3205 if (q_vector) 3206 netif_set_xps_queue(ring->netdev, 3207 &q_vector->affinity_mask, 3208 ring->queue_index); 3209 } 3210 3211 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3212 3213 /* enable queue */ 3214 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3215 3216 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3217 if (hw->mac.type == ixgbe_mac_82598EB && 3218 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3219 return; 3220 3221 /* poll to verify queue is enabled */ 3222 do { 3223 usleep_range(1000, 2000); 3224 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3225 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3226 if (!wait_loop) 3227 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); 3228 } 3229 3230 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3231 { 3232 struct ixgbe_hw *hw = &adapter->hw; 3233 u32 rttdcs, mtqc; 3234 u8 tcs = netdev_get_num_tc(adapter->netdev); 3235 3236 if (hw->mac.type == ixgbe_mac_82598EB) 3237 return; 3238 3239 /* disable the arbiter while setting MTQC */ 3240 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3241 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3242 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3243 3244 /* set transmit pool layout */ 3245 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3246 mtqc = IXGBE_MTQC_VT_ENA; 3247 if (tcs > 4) 3248 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3249 else if (tcs > 1) 3250 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3251 else if (adapter->ring_feature[RING_F_RSS].indices == 4) 3252 mtqc |= IXGBE_MTQC_32VF; 3253 else 3254 mtqc |= IXGBE_MTQC_64VF; 3255 } else { 3256 if (tcs > 4) 3257 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3258 else if (tcs > 1) 3259 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3260 else 3261 mtqc = IXGBE_MTQC_64Q_1PB; 3262 } 3263 3264 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3265 3266 /* Enable Security TX Buffer IFG for multiple pb */ 3267 if (tcs) { 3268 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3269 sectx |= IXGBE_SECTX_DCB; 3270 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3271 } 3272 3273 /* re-enable the arbiter */ 3274 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3275 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3276 } 3277 3278 /** 3279 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3280 * @adapter: board private structure 3281 * 3282 * Configure the Tx unit of the MAC after a reset. 3283 **/ 3284 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3285 { 3286 struct ixgbe_hw *hw = &adapter->hw; 3287 u32 dmatxctl; 3288 u32 i; 3289 3290 ixgbe_setup_mtqc(adapter); 3291 3292 if (hw->mac.type != ixgbe_mac_82598EB) { 3293 /* DMATXCTL.EN must be before Tx queues are enabled */ 3294 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3295 dmatxctl |= IXGBE_DMATXCTL_TE; 3296 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3297 } 3298 3299 /* Setup the HW Tx Head and Tail descriptor pointers */ 3300 for (i = 0; i < adapter->num_tx_queues; i++) 3301 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3302 } 3303 3304 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3305 struct ixgbe_ring *ring) 3306 { 3307 struct ixgbe_hw *hw = &adapter->hw; 3308 u8 reg_idx = ring->reg_idx; 3309 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3310 3311 srrctl |= IXGBE_SRRCTL_DROP_EN; 3312 3313 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3314 } 3315 3316 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3317 struct ixgbe_ring *ring) 3318 { 3319 struct ixgbe_hw *hw = &adapter->hw; 3320 u8 reg_idx = ring->reg_idx; 3321 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3322 3323 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3324 3325 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3326 } 3327 3328 #ifdef CONFIG_IXGBE_DCB 3329 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3330 #else 3331 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3332 #endif 3333 { 3334 int i; 3335 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3336 3337 if (adapter->ixgbe_ieee_pfc) 3338 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3339 3340 /* 3341 * We should set the drop enable bit if: 3342 * SR-IOV is enabled 3343 * or 3344 * Number of Rx queues > 1 and flow control is disabled 3345 * 3346 * This allows us to avoid head of line blocking for security 3347 * and performance reasons. 3348 */ 3349 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3350 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3351 for (i = 0; i < adapter->num_rx_queues; i++) 3352 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3353 } else { 3354 for (i = 0; i < adapter->num_rx_queues; i++) 3355 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3356 } 3357 } 3358 3359 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3360 3361 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3362 struct ixgbe_ring *rx_ring) 3363 { 3364 struct ixgbe_hw *hw = &adapter->hw; 3365 u32 srrctl; 3366 u8 reg_idx = rx_ring->reg_idx; 3367 3368 if (hw->mac.type == ixgbe_mac_82598EB) { 3369 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3370 3371 /* 3372 * if VMDq is not active we must program one srrctl register 3373 * per RSS queue since we have enabled RDRXCTL.MVMEN 3374 */ 3375 reg_idx &= mask; 3376 } 3377 3378 /* configure header buffer length, needed for RSC */ 3379 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3380 3381 /* configure the packet buffer length */ 3382 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3383 3384 /* configure descriptor type */ 3385 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3386 3387 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3388 } 3389 3390 /** 3391 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries 3392 * @adapter: device handle 3393 * 3394 * - 82598/82599/X540: 128 3395 * - X550(non-SRIOV mode): 512 3396 * - X550(SRIOV mode): 64 3397 */ 3398 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 3399 { 3400 if (adapter->hw.mac.type < ixgbe_mac_X550) 3401 return 128; 3402 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3403 return 64; 3404 else 3405 return 512; 3406 } 3407 3408 /** 3409 * ixgbe_store_reta - Write the RETA table to HW 3410 * @adapter: device handle 3411 * 3412 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3413 */ 3414 void ixgbe_store_reta(struct ixgbe_adapter *adapter) 3415 { 3416 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3417 struct ixgbe_hw *hw = &adapter->hw; 3418 u32 reta = 0; 3419 u32 indices_multi; 3420 u8 *indir_tbl = adapter->rss_indir_tbl; 3421 3422 /* Fill out the redirection table as follows: 3423 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 3424 * indices. 3425 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 3426 * - X550: 8 bit wide entries containing 6 bit RSS index 3427 */ 3428 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3429 indices_multi = 0x11; 3430 else 3431 indices_multi = 0x1; 3432 3433 /* Write redirection table to HW */ 3434 for (i = 0; i < reta_entries; i++) { 3435 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 3436 if ((i & 3) == 3) { 3437 if (i < 128) 3438 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3439 else 3440 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3441 reta); 3442 reta = 0; 3443 } 3444 } 3445 } 3446 3447 /** 3448 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) 3449 * @adapter: device handle 3450 * 3451 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3452 */ 3453 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 3454 { 3455 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3456 struct ixgbe_hw *hw = &adapter->hw; 3457 u32 vfreta = 0; 3458 unsigned int pf_pool = adapter->num_vfs; 3459 3460 /* Write redirection table to HW */ 3461 for (i = 0; i < reta_entries; i++) { 3462 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 3463 if ((i & 3) == 3) { 3464 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool), 3465 vfreta); 3466 vfreta = 0; 3467 } 3468 } 3469 } 3470 3471 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 3472 { 3473 struct ixgbe_hw *hw = &adapter->hw; 3474 u32 i, j; 3475 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3476 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3477 3478 /* Program table for at least 2 queues w/ SR-IOV so that VFs can 3479 * make full use of any rings they may have. We will use the 3480 * PSRTYPE register to control how many rings we use within the PF. 3481 */ 3482 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2)) 3483 rss_i = 2; 3484 3485 /* Fill out hash function seeds */ 3486 for (i = 0; i < 10; i++) 3487 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 3488 3489 /* Fill out redirection table */ 3490 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 3491 3492 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3493 if (j == rss_i) 3494 j = 0; 3495 3496 adapter->rss_indir_tbl[i] = j; 3497 } 3498 3499 ixgbe_store_reta(adapter); 3500 } 3501 3502 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 3503 { 3504 struct ixgbe_hw *hw = &adapter->hw; 3505 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3506 unsigned int pf_pool = adapter->num_vfs; 3507 int i, j; 3508 3509 /* Fill out hash function seeds */ 3510 for (i = 0; i < 10; i++) 3511 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool), 3512 adapter->rss_key[i]); 3513 3514 /* Fill out the redirection table */ 3515 for (i = 0, j = 0; i < 64; i++, j++) { 3516 if (j == rss_i) 3517 j = 0; 3518 3519 adapter->rss_indir_tbl[i] = j; 3520 } 3521 3522 ixgbe_store_vfreta(adapter); 3523 } 3524 3525 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3526 { 3527 struct ixgbe_hw *hw = &adapter->hw; 3528 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3529 u32 rxcsum; 3530 3531 /* Disable indicating checksum in descriptor, enables RSS hash */ 3532 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3533 rxcsum |= IXGBE_RXCSUM_PCSD; 3534 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3535 3536 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3537 if (adapter->ring_feature[RING_F_RSS].mask) 3538 mrqc = IXGBE_MRQC_RSSEN; 3539 } else { 3540 u8 tcs = netdev_get_num_tc(adapter->netdev); 3541 3542 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3543 if (tcs > 4) 3544 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3545 else if (tcs > 1) 3546 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3547 else if (adapter->ring_feature[RING_F_RSS].indices == 4) 3548 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3549 else 3550 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3551 } else { 3552 if (tcs > 4) 3553 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3554 else if (tcs > 1) 3555 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3556 else 3557 mrqc = IXGBE_MRQC_RSSEN; 3558 } 3559 } 3560 3561 /* Perform hash on these packet types */ 3562 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3563 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3564 IXGBE_MRQC_RSS_FIELD_IPV6 | 3565 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3566 3567 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3568 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3569 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3570 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3571 3572 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key)); 3573 if ((hw->mac.type >= ixgbe_mac_X550) && 3574 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 3575 unsigned int pf_pool = adapter->num_vfs; 3576 3577 /* Enable VF RSS mode */ 3578 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 3579 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3580 3581 /* Setup RSS through the VF registers */ 3582 ixgbe_setup_vfreta(adapter); 3583 vfmrqc = IXGBE_MRQC_RSSEN; 3584 vfmrqc |= rss_field; 3585 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc); 3586 } else { 3587 ixgbe_setup_reta(adapter); 3588 mrqc |= rss_field; 3589 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3590 } 3591 } 3592 3593 /** 3594 * ixgbe_configure_rscctl - enable RSC for the indicated ring 3595 * @adapter: address of board private structure 3596 * @index: index of ring to set 3597 **/ 3598 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 3599 struct ixgbe_ring *ring) 3600 { 3601 struct ixgbe_hw *hw = &adapter->hw; 3602 u32 rscctrl; 3603 u8 reg_idx = ring->reg_idx; 3604 3605 if (!ring_is_rsc_enabled(ring)) 3606 return; 3607 3608 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 3609 rscctrl |= IXGBE_RSCCTL_RSCEN; 3610 /* 3611 * we must limit the number of descriptors so that the 3612 * total size of max desc * buf_len is not greater 3613 * than 65536 3614 */ 3615 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 3616 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 3617 } 3618 3619 #define IXGBE_MAX_RX_DESC_POLL 10 3620 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 3621 struct ixgbe_ring *ring) 3622 { 3623 struct ixgbe_hw *hw = &adapter->hw; 3624 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 3625 u32 rxdctl; 3626 u8 reg_idx = ring->reg_idx; 3627 3628 if (ixgbe_removed(hw->hw_addr)) 3629 return; 3630 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3631 if (hw->mac.type == ixgbe_mac_82598EB && 3632 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3633 return; 3634 3635 do { 3636 usleep_range(1000, 2000); 3637 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3638 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 3639 3640 if (!wait_loop) { 3641 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 3642 "the polling period\n", reg_idx); 3643 } 3644 } 3645 3646 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, 3647 struct ixgbe_ring *ring) 3648 { 3649 struct ixgbe_hw *hw = &adapter->hw; 3650 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 3651 u32 rxdctl; 3652 u8 reg_idx = ring->reg_idx; 3653 3654 if (ixgbe_removed(hw->hw_addr)) 3655 return; 3656 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3657 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 3658 3659 /* write value back with RXDCTL.ENABLE bit cleared */ 3660 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 3661 3662 if (hw->mac.type == ixgbe_mac_82598EB && 3663 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3664 return; 3665 3666 /* the hardware may take up to 100us to really disable the rx queue */ 3667 do { 3668 udelay(10); 3669 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3670 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); 3671 3672 if (!wait_loop) { 3673 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " 3674 "the polling period\n", reg_idx); 3675 } 3676 } 3677 3678 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 3679 struct ixgbe_ring *ring) 3680 { 3681 struct ixgbe_hw *hw = &adapter->hw; 3682 u64 rdba = ring->dma; 3683 u32 rxdctl; 3684 u8 reg_idx = ring->reg_idx; 3685 3686 /* disable queue to avoid issues while updating state */ 3687 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3688 ixgbe_disable_rx_queue(adapter, ring); 3689 3690 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 3691 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 3692 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 3693 ring->count * sizeof(union ixgbe_adv_rx_desc)); 3694 /* Force flushing of IXGBE_RDLEN to prevent MDD */ 3695 IXGBE_WRITE_FLUSH(hw); 3696 3697 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 3698 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 3699 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 3700 3701 ixgbe_configure_srrctl(adapter, ring); 3702 ixgbe_configure_rscctl(adapter, ring); 3703 3704 if (hw->mac.type == ixgbe_mac_82598EB) { 3705 /* 3706 * enable cache line friendly hardware writes: 3707 * PTHRESH=32 descriptors (half the internal cache), 3708 * this also removes ugly rx_no_buffer_count increment 3709 * HTHRESH=4 descriptors (to minimize latency on fetch) 3710 * WTHRESH=8 burst writeback up to two cache lines 3711 */ 3712 rxdctl &= ~0x3FFFFF; 3713 rxdctl |= 0x080420; 3714 } 3715 3716 /* enable receive descriptor ring */ 3717 rxdctl |= IXGBE_RXDCTL_ENABLE; 3718 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 3719 3720 ixgbe_rx_desc_queue_enable(adapter, ring); 3721 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 3722 } 3723 3724 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 3725 { 3726 struct ixgbe_hw *hw = &adapter->hw; 3727 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 3728 u16 pool; 3729 3730 /* PSRTYPE must be initialized in non 82598 adapters */ 3731 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 3732 IXGBE_PSRTYPE_UDPHDR | 3733 IXGBE_PSRTYPE_IPV4HDR | 3734 IXGBE_PSRTYPE_L2HDR | 3735 IXGBE_PSRTYPE_IPV6HDR; 3736 3737 if (hw->mac.type == ixgbe_mac_82598EB) 3738 return; 3739 3740 if (rss_i > 3) 3741 psrtype |= 2u << 29; 3742 else if (rss_i > 1) 3743 psrtype |= 1u << 29; 3744 3745 for_each_set_bit(pool, &adapter->fwd_bitmask, 32) 3746 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 3747 } 3748 3749 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 3750 { 3751 struct ixgbe_hw *hw = &adapter->hw; 3752 u32 reg_offset, vf_shift; 3753 u32 gcr_ext, vmdctl; 3754 int i; 3755 3756 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 3757 return; 3758 3759 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 3760 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 3761 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 3762 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 3763 vmdctl |= IXGBE_VT_CTL_REPLEN; 3764 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 3765 3766 vf_shift = VMDQ_P(0) % 32; 3767 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 3768 3769 /* Enable only the PF's pool for Tx/Rx */ 3770 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); 3771 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 3772 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); 3773 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 3774 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 3775 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 3776 3777 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 3778 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 3779 3780 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 3781 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 3782 3783 /* 3784 * Set up VF register offsets for selected VT Mode, 3785 * i.e. 32 or 64 VFs for SR-IOV 3786 */ 3787 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 3788 case IXGBE_82599_VMDQ_8Q_MASK: 3789 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 3790 break; 3791 case IXGBE_82599_VMDQ_4Q_MASK: 3792 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 3793 break; 3794 default: 3795 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 3796 break; 3797 } 3798 3799 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 3800 3801 for (i = 0; i < adapter->num_vfs; i++) { 3802 /* configure spoof checking */ 3803 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, 3804 adapter->vfinfo[i].spoofchk_enabled); 3805 3806 /* Enable/Disable RSS query feature */ 3807 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 3808 adapter->vfinfo[i].rss_query_enabled); 3809 } 3810 } 3811 3812 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 3813 { 3814 struct ixgbe_hw *hw = &adapter->hw; 3815 struct net_device *netdev = adapter->netdev; 3816 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 3817 struct ixgbe_ring *rx_ring; 3818 int i; 3819 u32 mhadd, hlreg0; 3820 3821 #ifdef IXGBE_FCOE 3822 /* adjust max frame to be able to do baby jumbo for FCoE */ 3823 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 3824 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 3825 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 3826 3827 #endif /* IXGBE_FCOE */ 3828 3829 /* adjust max frame to be at least the size of a standard frame */ 3830 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 3831 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 3832 3833 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 3834 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 3835 mhadd &= ~IXGBE_MHADD_MFS_MASK; 3836 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 3837 3838 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 3839 } 3840 3841 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3842 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 3843 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 3844 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3845 3846 /* 3847 * Setup the HW Rx Head and Tail Descriptor Pointers and 3848 * the Base and Length of the Rx Descriptor Ring 3849 */ 3850 for (i = 0; i < adapter->num_rx_queues; i++) { 3851 rx_ring = adapter->rx_ring[i]; 3852 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 3853 set_ring_rsc_enabled(rx_ring); 3854 else 3855 clear_ring_rsc_enabled(rx_ring); 3856 } 3857 } 3858 3859 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 3860 { 3861 struct ixgbe_hw *hw = &adapter->hw; 3862 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 3863 3864 switch (hw->mac.type) { 3865 case ixgbe_mac_82598EB: 3866 /* 3867 * For VMDq support of different descriptor types or 3868 * buffer sizes through the use of multiple SRRCTL 3869 * registers, RDRXCTL.MVMEN must be set to 1 3870 * 3871 * also, the manual doesn't mention it clearly but DCA hints 3872 * will only use queue 0's tags unless this bit is set. Side 3873 * effects of setting this bit are only that SRRCTL must be 3874 * fully programmed [0..15] 3875 */ 3876 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 3877 break; 3878 case ixgbe_mac_X550: 3879 case ixgbe_mac_X550EM_x: 3880 case ixgbe_mac_x550em_a: 3881 if (adapter->num_vfs) 3882 rdrxctl |= IXGBE_RDRXCTL_PSP; 3883 /* fall through for older HW */ 3884 case ixgbe_mac_82599EB: 3885 case ixgbe_mac_X540: 3886 /* Disable RSC for ACK packets */ 3887 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 3888 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 3889 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 3890 /* hardware requires some bits to be set by default */ 3891 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 3892 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 3893 break; 3894 default: 3895 /* We should do nothing since we don't know this hardware */ 3896 return; 3897 } 3898 3899 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 3900 } 3901 3902 /** 3903 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 3904 * @adapter: board private structure 3905 * 3906 * Configure the Rx unit of the MAC after a reset. 3907 **/ 3908 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 3909 { 3910 struct ixgbe_hw *hw = &adapter->hw; 3911 int i; 3912 u32 rxctrl, rfctl; 3913 3914 /* disable receives while setting up the descriptors */ 3915 hw->mac.ops.disable_rx(hw); 3916 3917 ixgbe_setup_psrtype(adapter); 3918 ixgbe_setup_rdrxctl(adapter); 3919 3920 /* RSC Setup */ 3921 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 3922 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 3923 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 3924 rfctl |= IXGBE_RFCTL_RSC_DIS; 3925 3926 /* disable NFS filtering */ 3927 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS); 3928 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 3929 3930 /* Program registers for the distribution of queues */ 3931 ixgbe_setup_mrqc(adapter); 3932 3933 /* set_rx_buffer_len must be called before ring initialization */ 3934 ixgbe_set_rx_buffer_len(adapter); 3935 3936 /* 3937 * Setup the HW Rx Head and Tail Descriptor Pointers and 3938 * the Base and Length of the Rx Descriptor Ring 3939 */ 3940 for (i = 0; i < adapter->num_rx_queues; i++) 3941 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 3942 3943 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 3944 /* disable drop enable for 82598 parts */ 3945 if (hw->mac.type == ixgbe_mac_82598EB) 3946 rxctrl |= IXGBE_RXCTRL_DMBYPS; 3947 3948 /* enable all receives */ 3949 rxctrl |= IXGBE_RXCTRL_RXEN; 3950 hw->mac.ops.enable_rx_dma(hw, rxctrl); 3951 } 3952 3953 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 3954 __be16 proto, u16 vid) 3955 { 3956 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3957 struct ixgbe_hw *hw = &adapter->hw; 3958 3959 /* add VID to filter table */ 3960 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 3961 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); 3962 3963 set_bit(vid, adapter->active_vlans); 3964 3965 return 0; 3966 } 3967 3968 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) 3969 { 3970 u32 vlvf; 3971 int idx; 3972 3973 /* short cut the special case */ 3974 if (vlan == 0) 3975 return 0; 3976 3977 /* Search for the vlan id in the VLVF entries */ 3978 for (idx = IXGBE_VLVF_ENTRIES; --idx;) { 3979 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); 3980 if ((vlvf & VLAN_VID_MASK) == vlan) 3981 break; 3982 } 3983 3984 return idx; 3985 } 3986 3987 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) 3988 { 3989 struct ixgbe_hw *hw = &adapter->hw; 3990 u32 bits, word; 3991 int idx; 3992 3993 idx = ixgbe_find_vlvf_entry(hw, vid); 3994 if (!idx) 3995 return; 3996 3997 /* See if any other pools are set for this VLAN filter 3998 * entry other than the PF. 3999 */ 4000 word = idx * 2 + (VMDQ_P(0) / 32); 4001 bits = ~BIT(VMDQ_P(0) % 32); 4002 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4003 4004 /* Disable the filter so this falls into the default pool. */ 4005 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { 4006 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4007 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); 4008 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); 4009 } 4010 } 4011 4012 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 4013 __be16 proto, u16 vid) 4014 { 4015 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4016 struct ixgbe_hw *hw = &adapter->hw; 4017 4018 /* remove VID from filter table */ 4019 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4020 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); 4021 4022 clear_bit(vid, adapter->active_vlans); 4023 4024 return 0; 4025 } 4026 4027 /** 4028 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 4029 * @adapter: driver data 4030 */ 4031 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 4032 { 4033 struct ixgbe_hw *hw = &adapter->hw; 4034 u32 vlnctrl; 4035 int i, j; 4036 4037 switch (hw->mac.type) { 4038 case ixgbe_mac_82598EB: 4039 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4040 vlnctrl &= ~IXGBE_VLNCTRL_VME; 4041 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4042 break; 4043 case ixgbe_mac_82599EB: 4044 case ixgbe_mac_X540: 4045 case ixgbe_mac_X550: 4046 case ixgbe_mac_X550EM_x: 4047 case ixgbe_mac_x550em_a: 4048 for (i = 0; i < adapter->num_rx_queues; i++) { 4049 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4050 4051 if (ring->l2_accel_priv) 4052 continue; 4053 j = ring->reg_idx; 4054 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4055 vlnctrl &= ~IXGBE_RXDCTL_VME; 4056 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4057 } 4058 break; 4059 default: 4060 break; 4061 } 4062 } 4063 4064 /** 4065 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 4066 * @adapter: driver data 4067 */ 4068 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 4069 { 4070 struct ixgbe_hw *hw = &adapter->hw; 4071 u32 vlnctrl; 4072 int i, j; 4073 4074 switch (hw->mac.type) { 4075 case ixgbe_mac_82598EB: 4076 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4077 vlnctrl |= IXGBE_VLNCTRL_VME; 4078 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4079 break; 4080 case ixgbe_mac_82599EB: 4081 case ixgbe_mac_X540: 4082 case ixgbe_mac_X550: 4083 case ixgbe_mac_X550EM_x: 4084 case ixgbe_mac_x550em_a: 4085 for (i = 0; i < adapter->num_rx_queues; i++) { 4086 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4087 4088 if (ring->l2_accel_priv) 4089 continue; 4090 j = ring->reg_idx; 4091 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4092 vlnctrl |= IXGBE_RXDCTL_VME; 4093 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4094 } 4095 break; 4096 default: 4097 break; 4098 } 4099 } 4100 4101 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) 4102 { 4103 struct ixgbe_hw *hw = &adapter->hw; 4104 u32 vlnctrl, i; 4105 4106 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4107 4108 switch (hw->mac.type) { 4109 case ixgbe_mac_82599EB: 4110 case ixgbe_mac_X540: 4111 case ixgbe_mac_X550: 4112 case ixgbe_mac_X550EM_x: 4113 case ixgbe_mac_x550em_a: 4114 default: 4115 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) 4116 break; 4117 /* fall through */ 4118 case ixgbe_mac_82598EB: 4119 /* legacy case, we can just disable VLAN filtering */ 4120 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 4121 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4122 return; 4123 } 4124 4125 /* We are already in VLAN promisc, nothing to do */ 4126 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) 4127 return; 4128 4129 /* Set flag so we don't redo unnecessary work */ 4130 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; 4131 4132 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */ 4133 vlnctrl |= IXGBE_VLNCTRL_VFE; 4134 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4135 4136 /* Add PF to all active pools */ 4137 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4138 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); 4139 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); 4140 4141 vlvfb |= BIT(VMDQ_P(0) % 32); 4142 IXGBE_WRITE_REG(hw, reg_offset, vlvfb); 4143 } 4144 4145 /* Set all bits in the VLAN filter table array */ 4146 for (i = hw->mac.vft_size; i--;) 4147 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); 4148 } 4149 4150 #define VFTA_BLOCK_SIZE 8 4151 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) 4152 { 4153 struct ixgbe_hw *hw = &adapter->hw; 4154 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4155 u32 vid_start = vfta_offset * 32; 4156 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4157 u32 i, vid, word, bits; 4158 4159 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4160 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); 4161 4162 /* pull VLAN ID from VLVF */ 4163 vid = vlvf & VLAN_VID_MASK; 4164 4165 /* only concern outselves with a certain range */ 4166 if (vid < vid_start || vid >= vid_end) 4167 continue; 4168 4169 if (vlvf) { 4170 /* record VLAN ID in VFTA */ 4171 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4172 4173 /* if PF is part of this then continue */ 4174 if (test_bit(vid, adapter->active_vlans)) 4175 continue; 4176 } 4177 4178 /* remove PF from the pool */ 4179 word = i * 2 + VMDQ_P(0) / 32; 4180 bits = ~BIT(VMDQ_P(0) % 32); 4181 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4182 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); 4183 } 4184 4185 /* extract values from active_vlans and write back to VFTA */ 4186 for (i = VFTA_BLOCK_SIZE; i--;) { 4187 vid = (vfta_offset + i) * 32; 4188 word = vid / BITS_PER_LONG; 4189 bits = vid % BITS_PER_LONG; 4190 4191 vfta[i] |= adapter->active_vlans[word] >> bits; 4192 4193 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); 4194 } 4195 } 4196 4197 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) 4198 { 4199 struct ixgbe_hw *hw = &adapter->hw; 4200 u32 vlnctrl, i; 4201 4202 /* Set VLAN filtering to enabled */ 4203 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4204 vlnctrl |= IXGBE_VLNCTRL_VFE; 4205 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4206 4207 switch (hw->mac.type) { 4208 case ixgbe_mac_82599EB: 4209 case ixgbe_mac_X540: 4210 case ixgbe_mac_X550: 4211 case ixgbe_mac_X550EM_x: 4212 case ixgbe_mac_x550em_a: 4213 default: 4214 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) 4215 break; 4216 /* fall through */ 4217 case ixgbe_mac_82598EB: 4218 return; 4219 } 4220 4221 /* We are not in VLAN promisc, nothing to do */ 4222 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4223 return; 4224 4225 /* Set flag so we don't redo unnecessary work */ 4226 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4227 4228 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) 4229 ixgbe_scrub_vfta(adapter, i); 4230 } 4231 4232 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 4233 { 4234 u16 vid = 1; 4235 4236 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 4237 4238 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 4239 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 4240 } 4241 4242 /** 4243 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 4244 * @netdev: network interface device structure 4245 * 4246 * Writes multicast address list to the MTA hash table. 4247 * Returns: -ENOMEM on failure 4248 * 0 on no addresses written 4249 * X on writing X addresses to MTA 4250 **/ 4251 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 4252 { 4253 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4254 struct ixgbe_hw *hw = &adapter->hw; 4255 4256 if (!netif_running(netdev)) 4257 return 0; 4258 4259 if (hw->mac.ops.update_mc_addr_list) 4260 hw->mac.ops.update_mc_addr_list(hw, netdev); 4261 else 4262 return -ENOMEM; 4263 4264 #ifdef CONFIG_PCI_IOV 4265 ixgbe_restore_vf_multicasts(adapter); 4266 #endif 4267 4268 return netdev_mc_count(netdev); 4269 } 4270 4271 #ifdef CONFIG_PCI_IOV 4272 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 4273 { 4274 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4275 struct ixgbe_hw *hw = &adapter->hw; 4276 int i; 4277 4278 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4279 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4280 4281 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4282 hw->mac.ops.set_rar(hw, i, 4283 mac_table->addr, 4284 mac_table->pool, 4285 IXGBE_RAH_AV); 4286 else 4287 hw->mac.ops.clear_rar(hw, i); 4288 } 4289 } 4290 4291 #endif 4292 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 4293 { 4294 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4295 struct ixgbe_hw *hw = &adapter->hw; 4296 int i; 4297 4298 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4299 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) 4300 continue; 4301 4302 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4303 4304 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4305 hw->mac.ops.set_rar(hw, i, 4306 mac_table->addr, 4307 mac_table->pool, 4308 IXGBE_RAH_AV); 4309 else 4310 hw->mac.ops.clear_rar(hw, i); 4311 } 4312 } 4313 4314 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 4315 { 4316 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4317 struct ixgbe_hw *hw = &adapter->hw; 4318 int i; 4319 4320 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4321 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4322 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4323 } 4324 4325 ixgbe_sync_mac_table(adapter); 4326 } 4327 4328 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) 4329 { 4330 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4331 struct ixgbe_hw *hw = &adapter->hw; 4332 int i, count = 0; 4333 4334 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4335 /* do not count default RAR as available */ 4336 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) 4337 continue; 4338 4339 /* only count unused and addresses that belong to us */ 4340 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { 4341 if (mac_table->pool != pool) 4342 continue; 4343 } 4344 4345 count++; 4346 } 4347 4348 return count; 4349 } 4350 4351 /* this function destroys the first RAR entry */ 4352 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) 4353 { 4354 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4355 struct ixgbe_hw *hw = &adapter->hw; 4356 4357 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); 4358 mac_table->pool = VMDQ_P(0); 4359 4360 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; 4361 4362 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, 4363 IXGBE_RAH_AV); 4364 } 4365 4366 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 4367 const u8 *addr, u16 pool) 4368 { 4369 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4370 struct ixgbe_hw *hw = &adapter->hw; 4371 int i; 4372 4373 if (is_zero_ether_addr(addr)) 4374 return -EINVAL; 4375 4376 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4377 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4378 continue; 4379 4380 ether_addr_copy(mac_table->addr, addr); 4381 mac_table->pool = pool; 4382 4383 mac_table->state |= IXGBE_MAC_STATE_MODIFIED | 4384 IXGBE_MAC_STATE_IN_USE; 4385 4386 ixgbe_sync_mac_table(adapter); 4387 4388 return i; 4389 } 4390 4391 return -ENOMEM; 4392 } 4393 4394 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 4395 const u8 *addr, u16 pool) 4396 { 4397 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4398 struct ixgbe_hw *hw = &adapter->hw; 4399 int i; 4400 4401 if (is_zero_ether_addr(addr)) 4402 return -EINVAL; 4403 4404 /* search table for addr, if found clear IN_USE flag and sync */ 4405 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4406 /* we can only delete an entry if it is in use */ 4407 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) 4408 continue; 4409 /* we only care about entries that belong to the given pool */ 4410 if (mac_table->pool != pool) 4411 continue; 4412 /* we only care about a specific MAC address */ 4413 if (!ether_addr_equal(addr, mac_table->addr)) 4414 continue; 4415 4416 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4417 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4418 4419 ixgbe_sync_mac_table(adapter); 4420 4421 return 0; 4422 } 4423 4424 return -ENOMEM; 4425 } 4426 /** 4427 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table 4428 * @netdev: network interface device structure 4429 * 4430 * Writes unicast address list to the RAR table. 4431 * Returns: -ENOMEM on failure/insufficient address space 4432 * 0 on no addresses written 4433 * X on writing X addresses to the RAR table 4434 **/ 4435 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn) 4436 { 4437 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4438 int count = 0; 4439 4440 /* return ENOMEM indicating insufficient memory for addresses */ 4441 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter, vfn)) 4442 return -ENOMEM; 4443 4444 if (!netdev_uc_empty(netdev)) { 4445 struct netdev_hw_addr *ha; 4446 netdev_for_each_uc_addr(ha, netdev) { 4447 ixgbe_del_mac_filter(adapter, ha->addr, vfn); 4448 ixgbe_add_mac_filter(adapter, ha->addr, vfn); 4449 count++; 4450 } 4451 } 4452 return count; 4453 } 4454 4455 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) 4456 { 4457 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4458 int ret; 4459 4460 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); 4461 4462 return min_t(int, ret, 0); 4463 } 4464 4465 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) 4466 { 4467 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4468 4469 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); 4470 4471 return 0; 4472 } 4473 4474 /** 4475 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4476 * @netdev: network interface device structure 4477 * 4478 * The set_rx_method entry point is called whenever the unicast/multicast 4479 * address list or the network interface flags are updated. This routine is 4480 * responsible for configuring the hardware for proper unicast, multicast and 4481 * promiscuous mode. 4482 **/ 4483 void ixgbe_set_rx_mode(struct net_device *netdev) 4484 { 4485 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4486 struct ixgbe_hw *hw = &adapter->hw; 4487 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4488 netdev_features_t features = netdev->features; 4489 int count; 4490 4491 /* Check for Promiscuous and All Multicast modes */ 4492 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4493 4494 /* set all bits that we expect to always be set */ 4495 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4496 fctrl |= IXGBE_FCTRL_BAM; 4497 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4498 fctrl |= IXGBE_FCTRL_PMCF; 4499 4500 /* clear the bits we are changing the status of */ 4501 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4502 if (netdev->flags & IFF_PROMISC) { 4503 hw->addr_ctrl.user_set_promisc = true; 4504 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4505 vmolr |= IXGBE_VMOLR_MPE; 4506 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4507 } else { 4508 if (netdev->flags & IFF_ALLMULTI) { 4509 fctrl |= IXGBE_FCTRL_MPE; 4510 vmolr |= IXGBE_VMOLR_MPE; 4511 } 4512 hw->addr_ctrl.user_set_promisc = false; 4513 } 4514 4515 /* 4516 * Write addresses to available RAR registers, if there is not 4517 * sufficient space to store all the addresses then enable 4518 * unicast promiscuous mode 4519 */ 4520 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { 4521 fctrl |= IXGBE_FCTRL_UPE; 4522 vmolr |= IXGBE_VMOLR_ROPE; 4523 } 4524 4525 /* Write addresses to the MTA, if the attempt fails 4526 * then we should just turn on promiscuous mode so 4527 * that we can at least receive multicast traffic 4528 */ 4529 count = ixgbe_write_mc_addr_list(netdev); 4530 if (count < 0) { 4531 fctrl |= IXGBE_FCTRL_MPE; 4532 vmolr |= IXGBE_VMOLR_MPE; 4533 } else if (count) { 4534 vmolr |= IXGBE_VMOLR_ROMPE; 4535 } 4536 4537 if (hw->mac.type != ixgbe_mac_82598EB) { 4538 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4539 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4540 IXGBE_VMOLR_ROPE); 4541 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4542 } 4543 4544 /* This is useful for sniffing bad packets. */ 4545 if (features & NETIF_F_RXALL) { 4546 /* UPE and MPE will be handled by normal PROMISC logic 4547 * in e1000e_set_rx_mode */ 4548 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 4549 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 4550 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 4551 4552 fctrl &= ~(IXGBE_FCTRL_DPF); 4553 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 4554 } 4555 4556 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4557 4558 if (features & NETIF_F_HW_VLAN_CTAG_RX) 4559 ixgbe_vlan_strip_enable(adapter); 4560 else 4561 ixgbe_vlan_strip_disable(adapter); 4562 4563 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 4564 ixgbe_vlan_promisc_disable(adapter); 4565 else 4566 ixgbe_vlan_promisc_enable(adapter); 4567 } 4568 4569 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 4570 { 4571 int q_idx; 4572 4573 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) { 4574 ixgbe_qv_init_lock(adapter->q_vector[q_idx]); 4575 napi_enable(&adapter->q_vector[q_idx]->napi); 4576 } 4577 } 4578 4579 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 4580 { 4581 int q_idx; 4582 4583 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) { 4584 napi_disable(&adapter->q_vector[q_idx]->napi); 4585 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) { 4586 pr_info("QV %d locked\n", q_idx); 4587 usleep_range(1000, 20000); 4588 } 4589 } 4590 } 4591 4592 static void ixgbe_clear_udp_tunnel_port(struct ixgbe_adapter *adapter, u32 mask) 4593 { 4594 struct ixgbe_hw *hw = &adapter->hw; 4595 u32 vxlanctrl; 4596 4597 if (!(adapter->flags & (IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE | 4598 IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))) 4599 return; 4600 4601 vxlanctrl = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) && ~mask; 4602 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, vxlanctrl); 4603 4604 if (mask & IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK) 4605 adapter->vxlan_port = 0; 4606 4607 if (mask & IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK) 4608 adapter->geneve_port = 0; 4609 } 4610 4611 #ifdef CONFIG_IXGBE_DCB 4612 /** 4613 * ixgbe_configure_dcb - Configure DCB hardware 4614 * @adapter: ixgbe adapter struct 4615 * 4616 * This is called by the driver on open to configure the DCB hardware. 4617 * This is also called by the gennetlink interface when reconfiguring 4618 * the DCB state. 4619 */ 4620 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 4621 { 4622 struct ixgbe_hw *hw = &adapter->hw; 4623 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4624 4625 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 4626 if (hw->mac.type == ixgbe_mac_82598EB) 4627 netif_set_gso_max_size(adapter->netdev, 65536); 4628 return; 4629 } 4630 4631 if (hw->mac.type == ixgbe_mac_82598EB) 4632 netif_set_gso_max_size(adapter->netdev, 32768); 4633 4634 #ifdef IXGBE_FCOE 4635 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 4636 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 4637 #endif 4638 4639 /* reconfigure the hardware */ 4640 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 4641 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 4642 DCB_TX_CONFIG); 4643 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 4644 DCB_RX_CONFIG); 4645 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 4646 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 4647 ixgbe_dcb_hw_ets(&adapter->hw, 4648 adapter->ixgbe_ieee_ets, 4649 max_frame); 4650 ixgbe_dcb_hw_pfc_config(&adapter->hw, 4651 adapter->ixgbe_ieee_pfc->pfc_en, 4652 adapter->ixgbe_ieee_ets->prio_tc); 4653 } 4654 4655 /* Enable RSS Hash per TC */ 4656 if (hw->mac.type != ixgbe_mac_82598EB) { 4657 u32 msb = 0; 4658 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 4659 4660 while (rss_i) { 4661 msb++; 4662 rss_i >>= 1; 4663 } 4664 4665 /* write msb to all 8 TCs in one write */ 4666 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 4667 } 4668 } 4669 #endif 4670 4671 /* Additional bittime to account for IXGBE framing */ 4672 #define IXGBE_ETH_FRAMING 20 4673 4674 /** 4675 * ixgbe_hpbthresh - calculate high water mark for flow control 4676 * 4677 * @adapter: board private structure to calculate for 4678 * @pb: packet buffer to calculate 4679 */ 4680 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 4681 { 4682 struct ixgbe_hw *hw = &adapter->hw; 4683 struct net_device *dev = adapter->netdev; 4684 int link, tc, kb, marker; 4685 u32 dv_id, rx_pba; 4686 4687 /* Calculate max LAN frame size */ 4688 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 4689 4690 #ifdef IXGBE_FCOE 4691 /* FCoE traffic class uses FCOE jumbo frames */ 4692 if ((dev->features & NETIF_F_FCOE_MTU) && 4693 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 4694 (pb == ixgbe_fcoe_get_tc(adapter))) 4695 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4696 #endif 4697 4698 /* Calculate delay value for device */ 4699 switch (hw->mac.type) { 4700 case ixgbe_mac_X540: 4701 case ixgbe_mac_X550: 4702 case ixgbe_mac_X550EM_x: 4703 case ixgbe_mac_x550em_a: 4704 dv_id = IXGBE_DV_X540(link, tc); 4705 break; 4706 default: 4707 dv_id = IXGBE_DV(link, tc); 4708 break; 4709 } 4710 4711 /* Loopback switch introduces additional latency */ 4712 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 4713 dv_id += IXGBE_B2BT(tc); 4714 4715 /* Delay value is calculated in bit times convert to KB */ 4716 kb = IXGBE_BT2KB(dv_id); 4717 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 4718 4719 marker = rx_pba - kb; 4720 4721 /* It is possible that the packet buffer is not large enough 4722 * to provide required headroom. In this case throw an error 4723 * to user and a do the best we can. 4724 */ 4725 if (marker < 0) { 4726 e_warn(drv, "Packet Buffer(%i) can not provide enough" 4727 "headroom to support flow control." 4728 "Decrease MTU or number of traffic classes\n", pb); 4729 marker = tc + 1; 4730 } 4731 4732 return marker; 4733 } 4734 4735 /** 4736 * ixgbe_lpbthresh - calculate low water mark for for flow control 4737 * 4738 * @adapter: board private structure to calculate for 4739 * @pb: packet buffer to calculate 4740 */ 4741 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 4742 { 4743 struct ixgbe_hw *hw = &adapter->hw; 4744 struct net_device *dev = adapter->netdev; 4745 int tc; 4746 u32 dv_id; 4747 4748 /* Calculate max LAN frame size */ 4749 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 4750 4751 #ifdef IXGBE_FCOE 4752 /* FCoE traffic class uses FCOE jumbo frames */ 4753 if ((dev->features & NETIF_F_FCOE_MTU) && 4754 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 4755 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 4756 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4757 #endif 4758 4759 /* Calculate delay value for device */ 4760 switch (hw->mac.type) { 4761 case ixgbe_mac_X540: 4762 case ixgbe_mac_X550: 4763 case ixgbe_mac_X550EM_x: 4764 case ixgbe_mac_x550em_a: 4765 dv_id = IXGBE_LOW_DV_X540(tc); 4766 break; 4767 default: 4768 dv_id = IXGBE_LOW_DV(tc); 4769 break; 4770 } 4771 4772 /* Delay value is calculated in bit times convert to KB */ 4773 return IXGBE_BT2KB(dv_id); 4774 } 4775 4776 /* 4777 * ixgbe_pbthresh_setup - calculate and setup high low water marks 4778 */ 4779 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 4780 { 4781 struct ixgbe_hw *hw = &adapter->hw; 4782 int num_tc = netdev_get_num_tc(adapter->netdev); 4783 int i; 4784 4785 if (!num_tc) 4786 num_tc = 1; 4787 4788 for (i = 0; i < num_tc; i++) { 4789 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 4790 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 4791 4792 /* Low water marks must not be larger than high water marks */ 4793 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 4794 hw->fc.low_water[i] = 0; 4795 } 4796 4797 for (; i < MAX_TRAFFIC_CLASS; i++) 4798 hw->fc.high_water[i] = 0; 4799 } 4800 4801 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 4802 { 4803 struct ixgbe_hw *hw = &adapter->hw; 4804 int hdrm; 4805 u8 tc = netdev_get_num_tc(adapter->netdev); 4806 4807 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 4808 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 4809 hdrm = 32 << adapter->fdir_pballoc; 4810 else 4811 hdrm = 0; 4812 4813 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 4814 ixgbe_pbthresh_setup(adapter); 4815 } 4816 4817 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 4818 { 4819 struct ixgbe_hw *hw = &adapter->hw; 4820 struct hlist_node *node2; 4821 struct ixgbe_fdir_filter *filter; 4822 4823 spin_lock(&adapter->fdir_perfect_lock); 4824 4825 if (!hlist_empty(&adapter->fdir_filter_list)) 4826 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 4827 4828 hlist_for_each_entry_safe(filter, node2, 4829 &adapter->fdir_filter_list, fdir_node) { 4830 ixgbe_fdir_write_perfect_filter_82599(hw, 4831 &filter->filter, 4832 filter->sw_idx, 4833 (filter->action == IXGBE_FDIR_DROP_QUEUE) ? 4834 IXGBE_FDIR_DROP_QUEUE : 4835 adapter->rx_ring[filter->action]->reg_idx); 4836 } 4837 4838 spin_unlock(&adapter->fdir_perfect_lock); 4839 } 4840 4841 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool, 4842 struct ixgbe_adapter *adapter) 4843 { 4844 struct ixgbe_hw *hw = &adapter->hw; 4845 u32 vmolr; 4846 4847 /* No unicast promiscuous support for VMDQ devices. */ 4848 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool)); 4849 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE); 4850 4851 /* clear the affected bit */ 4852 vmolr &= ~IXGBE_VMOLR_MPE; 4853 4854 if (dev->flags & IFF_ALLMULTI) { 4855 vmolr |= IXGBE_VMOLR_MPE; 4856 } else { 4857 vmolr |= IXGBE_VMOLR_ROMPE; 4858 hw->mac.ops.update_mc_addr_list(hw, dev); 4859 } 4860 ixgbe_write_uc_addr_list(adapter->netdev, pool); 4861 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr); 4862 } 4863 4864 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter) 4865 { 4866 struct ixgbe_adapter *adapter = vadapter->real_adapter; 4867 int rss_i = adapter->num_rx_queues_per_pool; 4868 struct ixgbe_hw *hw = &adapter->hw; 4869 u16 pool = vadapter->pool; 4870 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4871 IXGBE_PSRTYPE_UDPHDR | 4872 IXGBE_PSRTYPE_IPV4HDR | 4873 IXGBE_PSRTYPE_L2HDR | 4874 IXGBE_PSRTYPE_IPV6HDR; 4875 4876 if (hw->mac.type == ixgbe_mac_82598EB) 4877 return; 4878 4879 if (rss_i > 3) 4880 psrtype |= 2u << 29; 4881 else if (rss_i > 1) 4882 psrtype |= 1u << 29; 4883 4884 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4885 } 4886 4887 /** 4888 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 4889 * @rx_ring: ring to free buffers from 4890 **/ 4891 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 4892 { 4893 struct device *dev = rx_ring->dev; 4894 unsigned long size; 4895 u16 i; 4896 4897 /* ring already cleared, nothing to do */ 4898 if (!rx_ring->rx_buffer_info) 4899 return; 4900 4901 /* Free all the Rx ring sk_buffs */ 4902 for (i = 0; i < rx_ring->count; i++) { 4903 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 4904 4905 if (rx_buffer->skb) { 4906 struct sk_buff *skb = rx_buffer->skb; 4907 if (IXGBE_CB(skb)->page_released) 4908 dma_unmap_page(dev, 4909 IXGBE_CB(skb)->dma, 4910 ixgbe_rx_bufsz(rx_ring), 4911 DMA_FROM_DEVICE); 4912 dev_kfree_skb(skb); 4913 rx_buffer->skb = NULL; 4914 } 4915 4916 if (!rx_buffer->page) 4917 continue; 4918 4919 dma_unmap_page(dev, rx_buffer->dma, 4920 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); 4921 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring)); 4922 4923 rx_buffer->page = NULL; 4924 } 4925 4926 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 4927 memset(rx_ring->rx_buffer_info, 0, size); 4928 4929 /* Zero out the descriptor ring */ 4930 memset(rx_ring->desc, 0, rx_ring->size); 4931 4932 rx_ring->next_to_alloc = 0; 4933 rx_ring->next_to_clean = 0; 4934 rx_ring->next_to_use = 0; 4935 } 4936 4937 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter, 4938 struct ixgbe_ring *rx_ring) 4939 { 4940 struct ixgbe_adapter *adapter = vadapter->real_adapter; 4941 int index = rx_ring->queue_index + vadapter->rx_base_queue; 4942 4943 /* shutdown specific queue receive and wait for dma to settle */ 4944 ixgbe_disable_rx_queue(adapter, rx_ring); 4945 usleep_range(10000, 20000); 4946 ixgbe_irq_disable_queues(adapter, BIT_ULL(index)); 4947 ixgbe_clean_rx_ring(rx_ring); 4948 rx_ring->l2_accel_priv = NULL; 4949 } 4950 4951 static int ixgbe_fwd_ring_down(struct net_device *vdev, 4952 struct ixgbe_fwd_adapter *accel) 4953 { 4954 struct ixgbe_adapter *adapter = accel->real_adapter; 4955 unsigned int rxbase = accel->rx_base_queue; 4956 unsigned int txbase = accel->tx_base_queue; 4957 int i; 4958 4959 netif_tx_stop_all_queues(vdev); 4960 4961 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4962 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); 4963 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev; 4964 } 4965 4966 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4967 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL; 4968 adapter->tx_ring[txbase + i]->netdev = adapter->netdev; 4969 } 4970 4971 4972 return 0; 4973 } 4974 4975 static int ixgbe_fwd_ring_up(struct net_device *vdev, 4976 struct ixgbe_fwd_adapter *accel) 4977 { 4978 struct ixgbe_adapter *adapter = accel->real_adapter; 4979 unsigned int rxbase, txbase, queues; 4980 int i, baseq, err = 0; 4981 4982 if (!test_bit(accel->pool, &adapter->fwd_bitmask)) 4983 return 0; 4984 4985 baseq = accel->pool * adapter->num_rx_queues_per_pool; 4986 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", 4987 accel->pool, adapter->num_rx_pools, 4988 baseq, baseq + adapter->num_rx_queues_per_pool, 4989 adapter->fwd_bitmask); 4990 4991 accel->netdev = vdev; 4992 accel->rx_base_queue = rxbase = baseq; 4993 accel->tx_base_queue = txbase = baseq; 4994 4995 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 4996 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); 4997 4998 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4999 adapter->rx_ring[rxbase + i]->netdev = vdev; 5000 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel; 5001 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]); 5002 } 5003 5004 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 5005 adapter->tx_ring[txbase + i]->netdev = vdev; 5006 adapter->tx_ring[txbase + i]->l2_accel_priv = accel; 5007 } 5008 5009 queues = min_t(unsigned int, 5010 adapter->num_rx_queues_per_pool, vdev->num_tx_queues); 5011 err = netif_set_real_num_tx_queues(vdev, queues); 5012 if (err) 5013 goto fwd_queue_err; 5014 5015 err = netif_set_real_num_rx_queues(vdev, queues); 5016 if (err) 5017 goto fwd_queue_err; 5018 5019 if (is_valid_ether_addr(vdev->dev_addr)) 5020 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool); 5021 5022 ixgbe_fwd_psrtype(accel); 5023 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter); 5024 return err; 5025 fwd_queue_err: 5026 ixgbe_fwd_ring_down(vdev, accel); 5027 return err; 5028 } 5029 5030 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 5031 { 5032 struct net_device *upper; 5033 struct list_head *iter; 5034 int err; 5035 5036 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { 5037 if (netif_is_macvlan(upper)) { 5038 struct macvlan_dev *dfwd = netdev_priv(upper); 5039 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; 5040 5041 if (dfwd->fwd_priv) { 5042 err = ixgbe_fwd_ring_up(upper, vadapter); 5043 if (err) 5044 continue; 5045 } 5046 } 5047 } 5048 } 5049 5050 static void ixgbe_configure(struct ixgbe_adapter *adapter) 5051 { 5052 struct ixgbe_hw *hw = &adapter->hw; 5053 5054 ixgbe_configure_pb(adapter); 5055 #ifdef CONFIG_IXGBE_DCB 5056 ixgbe_configure_dcb(adapter); 5057 #endif 5058 /* 5059 * We must restore virtualization before VLANs or else 5060 * the VLVF registers will not be populated 5061 */ 5062 ixgbe_configure_virtualization(adapter); 5063 5064 ixgbe_set_rx_mode(adapter->netdev); 5065 ixgbe_restore_vlan(adapter); 5066 5067 switch (hw->mac.type) { 5068 case ixgbe_mac_82599EB: 5069 case ixgbe_mac_X540: 5070 hw->mac.ops.disable_rx_buff(hw); 5071 break; 5072 default: 5073 break; 5074 } 5075 5076 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 5077 ixgbe_init_fdir_signature_82599(&adapter->hw, 5078 adapter->fdir_pballoc); 5079 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 5080 ixgbe_init_fdir_perfect_82599(&adapter->hw, 5081 adapter->fdir_pballoc); 5082 ixgbe_fdir_filter_restore(adapter); 5083 } 5084 5085 switch (hw->mac.type) { 5086 case ixgbe_mac_82599EB: 5087 case ixgbe_mac_X540: 5088 hw->mac.ops.enable_rx_buff(hw); 5089 break; 5090 default: 5091 break; 5092 } 5093 5094 #ifdef CONFIG_IXGBE_DCA 5095 /* configure DCA */ 5096 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) 5097 ixgbe_setup_dca(adapter); 5098 #endif /* CONFIG_IXGBE_DCA */ 5099 5100 #ifdef IXGBE_FCOE 5101 /* configure FCoE L2 filters, redirection table, and Rx control */ 5102 ixgbe_configure_fcoe(adapter); 5103 5104 #endif /* IXGBE_FCOE */ 5105 ixgbe_configure_tx(adapter); 5106 ixgbe_configure_rx(adapter); 5107 ixgbe_configure_dfwd(adapter); 5108 } 5109 5110 /** 5111 * ixgbe_sfp_link_config - set up SFP+ link 5112 * @adapter: pointer to private adapter struct 5113 **/ 5114 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 5115 { 5116 /* 5117 * We are assuming the worst case scenario here, and that 5118 * is that an SFP was inserted/removed after the reset 5119 * but before SFP detection was enabled. As such the best 5120 * solution is to just start searching as soon as we start 5121 */ 5122 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 5123 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 5124 5125 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 5126 adapter->sfp_poll_time = 0; 5127 } 5128 5129 /** 5130 * ixgbe_non_sfp_link_config - set up non-SFP+ link 5131 * @hw: pointer to private hardware struct 5132 * 5133 * Returns 0 on success, negative on failure 5134 **/ 5135 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 5136 { 5137 u32 speed; 5138 bool autoneg, link_up = false; 5139 int ret = IXGBE_ERR_LINK_SETUP; 5140 5141 if (hw->mac.ops.check_link) 5142 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 5143 5144 if (ret) 5145 return ret; 5146 5147 speed = hw->phy.autoneg_advertised; 5148 if ((!speed) && (hw->mac.ops.get_link_capabilities)) 5149 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 5150 &autoneg); 5151 if (ret) 5152 return ret; 5153 5154 if (hw->mac.ops.setup_link) 5155 ret = hw->mac.ops.setup_link(hw, speed, link_up); 5156 5157 return ret; 5158 } 5159 5160 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 5161 { 5162 struct ixgbe_hw *hw = &adapter->hw; 5163 u32 gpie = 0; 5164 5165 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 5166 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5167 IXGBE_GPIE_OCD; 5168 gpie |= IXGBE_GPIE_EIAME; 5169 /* 5170 * use EIAM to auto-mask when MSI-X interrupt is asserted 5171 * this saves a register write for every interrupt 5172 */ 5173 switch (hw->mac.type) { 5174 case ixgbe_mac_82598EB: 5175 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5176 break; 5177 case ixgbe_mac_82599EB: 5178 case ixgbe_mac_X540: 5179 case ixgbe_mac_X550: 5180 case ixgbe_mac_X550EM_x: 5181 case ixgbe_mac_x550em_a: 5182 default: 5183 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5184 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5185 break; 5186 } 5187 } else { 5188 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 5189 * specifically only auto mask tx and rx interrupts */ 5190 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5191 } 5192 5193 /* XXX: to interrupt immediately for EICS writes, enable this */ 5194 /* gpie |= IXGBE_GPIE_EIMEN; */ 5195 5196 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 5197 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 5198 5199 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 5200 case IXGBE_82599_VMDQ_8Q_MASK: 5201 gpie |= IXGBE_GPIE_VTMODE_16; 5202 break; 5203 case IXGBE_82599_VMDQ_4Q_MASK: 5204 gpie |= IXGBE_GPIE_VTMODE_32; 5205 break; 5206 default: 5207 gpie |= IXGBE_GPIE_VTMODE_64; 5208 break; 5209 } 5210 } 5211 5212 /* Enable Thermal over heat sensor interrupt */ 5213 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 5214 switch (adapter->hw.mac.type) { 5215 case ixgbe_mac_82599EB: 5216 gpie |= IXGBE_SDP0_GPIEN_8259X; 5217 break; 5218 default: 5219 break; 5220 } 5221 } 5222 5223 /* Enable fan failure interrupt */ 5224 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 5225 gpie |= IXGBE_SDP1_GPIEN(hw); 5226 5227 switch (hw->mac.type) { 5228 case ixgbe_mac_82599EB: 5229 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; 5230 break; 5231 case ixgbe_mac_X550EM_x: 5232 case ixgbe_mac_x550em_a: 5233 gpie |= IXGBE_SDP0_GPIEN_X540; 5234 break; 5235 default: 5236 break; 5237 } 5238 5239 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5240 } 5241 5242 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 5243 { 5244 struct ixgbe_hw *hw = &adapter->hw; 5245 int err; 5246 u32 ctrl_ext; 5247 5248 ixgbe_get_hw_control(adapter); 5249 ixgbe_setup_gpie(adapter); 5250 5251 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 5252 ixgbe_configure_msix(adapter); 5253 else 5254 ixgbe_configure_msi_and_legacy(adapter); 5255 5256 /* enable the optics for 82599 SFP+ fiber */ 5257 if (hw->mac.ops.enable_tx_laser) 5258 hw->mac.ops.enable_tx_laser(hw); 5259 5260 if (hw->phy.ops.set_phy_power) 5261 hw->phy.ops.set_phy_power(hw, true); 5262 5263 smp_mb__before_atomic(); 5264 clear_bit(__IXGBE_DOWN, &adapter->state); 5265 ixgbe_napi_enable_all(adapter); 5266 5267 if (ixgbe_is_sfp(hw)) { 5268 ixgbe_sfp_link_config(adapter); 5269 } else { 5270 err = ixgbe_non_sfp_link_config(hw); 5271 if (err) 5272 e_err(probe, "link_config FAILED %d\n", err); 5273 } 5274 5275 /* clear any pending interrupts, may auto mask */ 5276 IXGBE_READ_REG(hw, IXGBE_EICR); 5277 ixgbe_irq_enable(adapter, true, true); 5278 5279 /* 5280 * If this adapter has a fan, check to see if we had a failure 5281 * before we enabled the interrupt. 5282 */ 5283 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 5284 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5285 if (esdp & IXGBE_ESDP_SDP1) 5286 e_crit(drv, "Fan has stopped, replace the adapter\n"); 5287 } 5288 5289 /* bring the link up in the watchdog, this could race with our first 5290 * link up interrupt but shouldn't be a problem */ 5291 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 5292 adapter->link_check_timeout = jiffies; 5293 mod_timer(&adapter->service_timer, jiffies); 5294 5295 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 5296 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 5297 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 5298 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 5299 } 5300 5301 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 5302 { 5303 WARN_ON(in_interrupt()); 5304 /* put off any impending NetWatchDogTimeout */ 5305 netif_trans_update(adapter->netdev); 5306 5307 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 5308 usleep_range(1000, 2000); 5309 ixgbe_down(adapter); 5310 /* 5311 * If SR-IOV enabled then wait a bit before bringing the adapter 5312 * back up to give the VFs time to respond to the reset. The 5313 * two second wait is based upon the watchdog timer cycle in 5314 * the VF driver. 5315 */ 5316 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5317 msleep(2000); 5318 ixgbe_up(adapter); 5319 clear_bit(__IXGBE_RESETTING, &adapter->state); 5320 } 5321 5322 void ixgbe_up(struct ixgbe_adapter *adapter) 5323 { 5324 /* hardware has been reset, we need to reload some things */ 5325 ixgbe_configure(adapter); 5326 5327 ixgbe_up_complete(adapter); 5328 } 5329 5330 void ixgbe_reset(struct ixgbe_adapter *adapter) 5331 { 5332 struct ixgbe_hw *hw = &adapter->hw; 5333 struct net_device *netdev = adapter->netdev; 5334 int err; 5335 5336 if (ixgbe_removed(hw->hw_addr)) 5337 return; 5338 /* lock SFP init bit to prevent race conditions with the watchdog */ 5339 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 5340 usleep_range(1000, 2000); 5341 5342 /* clear all SFP and link config related flags while holding SFP_INIT */ 5343 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 5344 IXGBE_FLAG2_SFP_NEEDS_RESET); 5345 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 5346 5347 err = hw->mac.ops.init_hw(hw); 5348 switch (err) { 5349 case 0: 5350 case IXGBE_ERR_SFP_NOT_PRESENT: 5351 case IXGBE_ERR_SFP_NOT_SUPPORTED: 5352 break; 5353 case IXGBE_ERR_MASTER_REQUESTS_PENDING: 5354 e_dev_err("master disable timed out\n"); 5355 break; 5356 case IXGBE_ERR_EEPROM_VERSION: 5357 /* We are running on a pre-production device, log a warning */ 5358 e_dev_warn("This device is a pre-production adapter/LOM. " 5359 "Please be aware there may be issues associated with " 5360 "your hardware. If you are experiencing problems " 5361 "please contact your Intel or hardware " 5362 "representative who provided you with this " 5363 "hardware.\n"); 5364 break; 5365 default: 5366 e_dev_err("Hardware Error: %d\n", err); 5367 } 5368 5369 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 5370 5371 /* flush entries out of MAC table */ 5372 ixgbe_flush_sw_mac_table(adapter); 5373 __dev_uc_unsync(netdev, NULL); 5374 5375 /* do not flush user set addresses */ 5376 ixgbe_mac_set_default_filter(adapter); 5377 5378 /* update SAN MAC vmdq pool selection */ 5379 if (hw->mac.san_mac_rar_index) 5380 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 5381 5382 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 5383 ixgbe_ptp_reset(adapter); 5384 5385 if (hw->phy.ops.set_phy_power) { 5386 if (!netif_running(adapter->netdev) && !adapter->wol) 5387 hw->phy.ops.set_phy_power(hw, false); 5388 else 5389 hw->phy.ops.set_phy_power(hw, true); 5390 } 5391 } 5392 5393 /** 5394 * ixgbe_clean_tx_ring - Free Tx Buffers 5395 * @tx_ring: ring to be cleaned 5396 **/ 5397 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 5398 { 5399 struct ixgbe_tx_buffer *tx_buffer_info; 5400 unsigned long size; 5401 u16 i; 5402 5403 /* ring already cleared, nothing to do */ 5404 if (!tx_ring->tx_buffer_info) 5405 return; 5406 5407 /* Free all the Tx ring sk_buffs */ 5408 for (i = 0; i < tx_ring->count; i++) { 5409 tx_buffer_info = &tx_ring->tx_buffer_info[i]; 5410 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); 5411 } 5412 5413 netdev_tx_reset_queue(txring_txq(tx_ring)); 5414 5415 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 5416 memset(tx_ring->tx_buffer_info, 0, size); 5417 5418 /* Zero out the descriptor ring */ 5419 memset(tx_ring->desc, 0, tx_ring->size); 5420 5421 tx_ring->next_to_use = 0; 5422 tx_ring->next_to_clean = 0; 5423 } 5424 5425 /** 5426 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 5427 * @adapter: board private structure 5428 **/ 5429 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 5430 { 5431 int i; 5432 5433 for (i = 0; i < adapter->num_rx_queues; i++) 5434 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 5435 } 5436 5437 /** 5438 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 5439 * @adapter: board private structure 5440 **/ 5441 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 5442 { 5443 int i; 5444 5445 for (i = 0; i < adapter->num_tx_queues; i++) 5446 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 5447 } 5448 5449 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 5450 { 5451 struct hlist_node *node2; 5452 struct ixgbe_fdir_filter *filter; 5453 5454 spin_lock(&adapter->fdir_perfect_lock); 5455 5456 hlist_for_each_entry_safe(filter, node2, 5457 &adapter->fdir_filter_list, fdir_node) { 5458 hlist_del(&filter->fdir_node); 5459 kfree(filter); 5460 } 5461 adapter->fdir_filter_count = 0; 5462 5463 spin_unlock(&adapter->fdir_perfect_lock); 5464 } 5465 5466 void ixgbe_down(struct ixgbe_adapter *adapter) 5467 { 5468 struct net_device *netdev = adapter->netdev; 5469 struct ixgbe_hw *hw = &adapter->hw; 5470 struct net_device *upper; 5471 struct list_head *iter; 5472 int i; 5473 5474 /* signal that we are down to the interrupt handler */ 5475 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 5476 return; /* do nothing if already down */ 5477 5478 /* disable receives */ 5479 hw->mac.ops.disable_rx(hw); 5480 5481 /* disable all enabled rx queues */ 5482 for (i = 0; i < adapter->num_rx_queues; i++) 5483 /* this call also flushes the previous write */ 5484 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); 5485 5486 usleep_range(10000, 20000); 5487 5488 netif_tx_stop_all_queues(netdev); 5489 5490 /* call carrier off first to avoid false dev_watchdog timeouts */ 5491 netif_carrier_off(netdev); 5492 netif_tx_disable(netdev); 5493 5494 /* disable any upper devices */ 5495 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { 5496 if (netif_is_macvlan(upper)) { 5497 struct macvlan_dev *vlan = netdev_priv(upper); 5498 5499 if (vlan->fwd_priv) { 5500 netif_tx_stop_all_queues(upper); 5501 netif_carrier_off(upper); 5502 netif_tx_disable(upper); 5503 } 5504 } 5505 } 5506 5507 ixgbe_irq_disable(adapter); 5508 5509 ixgbe_napi_disable_all(adapter); 5510 5511 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 5512 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 5513 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 5514 5515 del_timer_sync(&adapter->service_timer); 5516 5517 if (adapter->num_vfs) { 5518 /* Clear EITR Select mapping */ 5519 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 5520 5521 /* Mark all the VFs as inactive */ 5522 for (i = 0 ; i < adapter->num_vfs; i++) 5523 adapter->vfinfo[i].clear_to_send = false; 5524 5525 /* ping all the active vfs to let them know we are going down */ 5526 ixgbe_ping_all_vfs(adapter); 5527 5528 /* Disable all VFTE/VFRE TX/RX */ 5529 ixgbe_disable_tx_rx(adapter); 5530 } 5531 5532 /* disable transmits in the hardware now that interrupts are off */ 5533 for (i = 0; i < adapter->num_tx_queues; i++) { 5534 u8 reg_idx = adapter->tx_ring[i]->reg_idx; 5535 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5536 } 5537 5538 /* Disable the Tx DMA engine on 82599 and later MAC */ 5539 switch (hw->mac.type) { 5540 case ixgbe_mac_82599EB: 5541 case ixgbe_mac_X540: 5542 case ixgbe_mac_X550: 5543 case ixgbe_mac_X550EM_x: 5544 case ixgbe_mac_x550em_a: 5545 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5546 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5547 ~IXGBE_DMATXCTL_TE)); 5548 break; 5549 default: 5550 break; 5551 } 5552 5553 if (!pci_channel_offline(adapter->pdev)) 5554 ixgbe_reset(adapter); 5555 5556 /* power down the optics for 82599 SFP+ fiber */ 5557 if (hw->mac.ops.disable_tx_laser) 5558 hw->mac.ops.disable_tx_laser(hw); 5559 5560 ixgbe_clean_all_tx_rings(adapter); 5561 ixgbe_clean_all_rx_rings(adapter); 5562 } 5563 5564 /** 5565 * ixgbe_tx_timeout - Respond to a Tx Hang 5566 * @netdev: network interface device structure 5567 **/ 5568 static void ixgbe_tx_timeout(struct net_device *netdev) 5569 { 5570 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5571 5572 /* Do the reset outside of interrupt context */ 5573 ixgbe_tx_timeout_reset(adapter); 5574 } 5575 5576 #ifdef CONFIG_IXGBE_DCB 5577 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) 5578 { 5579 struct ixgbe_hw *hw = &adapter->hw; 5580 struct tc_configuration *tc; 5581 int j; 5582 5583 switch (hw->mac.type) { 5584 case ixgbe_mac_82598EB: 5585 case ixgbe_mac_82599EB: 5586 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 5587 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 5588 break; 5589 case ixgbe_mac_X540: 5590 case ixgbe_mac_X550: 5591 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 5592 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 5593 break; 5594 case ixgbe_mac_X550EM_x: 5595 case ixgbe_mac_x550em_a: 5596 default: 5597 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; 5598 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; 5599 break; 5600 } 5601 5602 /* Configure DCB traffic classes */ 5603 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 5604 tc = &adapter->dcb_cfg.tc_config[j]; 5605 tc->path[DCB_TX_CONFIG].bwg_id = 0; 5606 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 5607 tc->path[DCB_RX_CONFIG].bwg_id = 0; 5608 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 5609 tc->dcb_pfc = pfc_disabled; 5610 } 5611 5612 /* Initialize default user to priority mapping, UPx->TC0 */ 5613 tc = &adapter->dcb_cfg.tc_config[0]; 5614 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 5615 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 5616 5617 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 5618 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 5619 adapter->dcb_cfg.pfc_mode_enable = false; 5620 adapter->dcb_set_bitmap = 0x00; 5621 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 5622 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 5623 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 5624 sizeof(adapter->temp_dcb_cfg)); 5625 } 5626 #endif 5627 5628 /** 5629 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 5630 * @adapter: board private structure to initialize 5631 * 5632 * ixgbe_sw_init initializes the Adapter private data structure. 5633 * Fields are initialized based on PCI device information and 5634 * OS network device settings (MTU size). 5635 **/ 5636 static int ixgbe_sw_init(struct ixgbe_adapter *adapter) 5637 { 5638 struct ixgbe_hw *hw = &adapter->hw; 5639 struct pci_dev *pdev = adapter->pdev; 5640 unsigned int rss, fdir; 5641 u32 fwsm; 5642 int i; 5643 5644 /* PCI config space info */ 5645 5646 hw->vendor_id = pdev->vendor; 5647 hw->device_id = pdev->device; 5648 hw->revision_id = pdev->revision; 5649 hw->subsystem_vendor_id = pdev->subsystem_vendor; 5650 hw->subsystem_device_id = pdev->subsystem_device; 5651 5652 /* Set common capability flags and settings */ 5653 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 5654 adapter->ring_feature[RING_F_RSS].limit = rss; 5655 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 5656 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 5657 adapter->atr_sample_rate = 20; 5658 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 5659 adapter->ring_feature[RING_F_FDIR].limit = fdir; 5660 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 5661 #ifdef CONFIG_IXGBE_DCA 5662 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 5663 #endif 5664 #ifdef CONFIG_IXGBE_DCB 5665 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; 5666 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 5667 #endif 5668 #ifdef IXGBE_FCOE 5669 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 5670 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 5671 #ifdef CONFIG_IXGBE_DCB 5672 /* Default traffic class to use for FCoE */ 5673 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 5674 #endif /* CONFIG_IXGBE_DCB */ 5675 #endif /* IXGBE_FCOE */ 5676 5677 /* initialize static ixgbe jump table entries */ 5678 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]), 5679 GFP_KERNEL); 5680 if (!adapter->jump_tables[0]) 5681 return -ENOMEM; 5682 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; 5683 5684 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) 5685 adapter->jump_tables[i] = NULL; 5686 5687 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) * 5688 hw->mac.num_rar_entries, 5689 GFP_ATOMIC); 5690 if (!adapter->mac_table) 5691 return -ENOMEM; 5692 5693 /* Set MAC specific capability flags and exceptions */ 5694 switch (hw->mac.type) { 5695 case ixgbe_mac_82598EB: 5696 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 5697 5698 if (hw->device_id == IXGBE_DEV_ID_82598AT) 5699 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 5700 5701 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 5702 adapter->ring_feature[RING_F_FDIR].limit = 0; 5703 adapter->atr_sample_rate = 0; 5704 adapter->fdir_pballoc = 0; 5705 #ifdef IXGBE_FCOE 5706 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 5707 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 5708 #ifdef CONFIG_IXGBE_DCB 5709 adapter->fcoe.up = 0; 5710 #endif /* IXGBE_DCB */ 5711 #endif /* IXGBE_FCOE */ 5712 break; 5713 case ixgbe_mac_82599EB: 5714 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 5715 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 5716 break; 5717 case ixgbe_mac_X540: 5718 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 5719 if (fwsm & IXGBE_FWSM_TS_ENABLED) 5720 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 5721 break; 5722 case ixgbe_mac_x550em_a: 5723 adapter->flags |= IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE; 5724 /* fall through */ 5725 case ixgbe_mac_X550EM_x: 5726 #ifdef CONFIG_IXGBE_DCB 5727 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; 5728 #endif 5729 #ifdef IXGBE_FCOE 5730 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 5731 #ifdef CONFIG_IXGBE_DCB 5732 adapter->fcoe.up = 0; 5733 #endif /* IXGBE_DCB */ 5734 #endif /* IXGBE_FCOE */ 5735 /* Fall Through */ 5736 case ixgbe_mac_X550: 5737 #ifdef CONFIG_IXGBE_DCA 5738 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 5739 #endif 5740 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE; 5741 break; 5742 default: 5743 break; 5744 } 5745 5746 #ifdef IXGBE_FCOE 5747 /* FCoE support exists, always init the FCoE lock */ 5748 spin_lock_init(&adapter->fcoe.lock); 5749 5750 #endif 5751 /* n-tuple support exists, always init our spinlock */ 5752 spin_lock_init(&adapter->fdir_perfect_lock); 5753 5754 #ifdef CONFIG_IXGBE_DCB 5755 ixgbe_init_dcb(adapter); 5756 #endif 5757 5758 /* default flow control settings */ 5759 hw->fc.requested_mode = ixgbe_fc_full; 5760 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 5761 ixgbe_pbthresh_setup(adapter); 5762 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 5763 hw->fc.send_xon = true; 5764 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 5765 5766 #ifdef CONFIG_PCI_IOV 5767 if (max_vfs > 0) 5768 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 5769 5770 /* assign number of SR-IOV VFs */ 5771 if (hw->mac.type != ixgbe_mac_82598EB) { 5772 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 5773 adapter->num_vfs = 0; 5774 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 5775 } else { 5776 adapter->num_vfs = max_vfs; 5777 } 5778 } 5779 #endif /* CONFIG_PCI_IOV */ 5780 5781 /* enable itr by default in dynamic mode */ 5782 adapter->rx_itr_setting = 1; 5783 adapter->tx_itr_setting = 1; 5784 5785 /* set default ring sizes */ 5786 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 5787 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 5788 5789 /* set default work limits */ 5790 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 5791 5792 /* initialize eeprom parameters */ 5793 if (ixgbe_init_eeprom_params_generic(hw)) { 5794 e_dev_err("EEPROM initialization failed\n"); 5795 return -EIO; 5796 } 5797 5798 /* PF holds first pool slot */ 5799 set_bit(0, &adapter->fwd_bitmask); 5800 set_bit(__IXGBE_DOWN, &adapter->state); 5801 5802 return 0; 5803 } 5804 5805 /** 5806 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 5807 * @tx_ring: tx descriptor ring (for a specific queue) to setup 5808 * 5809 * Return 0 on success, negative on failure 5810 **/ 5811 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 5812 { 5813 struct device *dev = tx_ring->dev; 5814 int orig_node = dev_to_node(dev); 5815 int ring_node = -1; 5816 int size; 5817 5818 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 5819 5820 if (tx_ring->q_vector) 5821 ring_node = tx_ring->q_vector->numa_node; 5822 5823 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node); 5824 if (!tx_ring->tx_buffer_info) 5825 tx_ring->tx_buffer_info = vzalloc(size); 5826 if (!tx_ring->tx_buffer_info) 5827 goto err; 5828 5829 u64_stats_init(&tx_ring->syncp); 5830 5831 /* round up to nearest 4K */ 5832 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 5833 tx_ring->size = ALIGN(tx_ring->size, 4096); 5834 5835 set_dev_node(dev, ring_node); 5836 tx_ring->desc = dma_alloc_coherent(dev, 5837 tx_ring->size, 5838 &tx_ring->dma, 5839 GFP_KERNEL); 5840 set_dev_node(dev, orig_node); 5841 if (!tx_ring->desc) 5842 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 5843 &tx_ring->dma, GFP_KERNEL); 5844 if (!tx_ring->desc) 5845 goto err; 5846 5847 tx_ring->next_to_use = 0; 5848 tx_ring->next_to_clean = 0; 5849 return 0; 5850 5851 err: 5852 vfree(tx_ring->tx_buffer_info); 5853 tx_ring->tx_buffer_info = NULL; 5854 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 5855 return -ENOMEM; 5856 } 5857 5858 /** 5859 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 5860 * @adapter: board private structure 5861 * 5862 * If this function returns with an error, then it's possible one or 5863 * more of the rings is populated (while the rest are not). It is the 5864 * callers duty to clean those orphaned rings. 5865 * 5866 * Return 0 on success, negative on failure 5867 **/ 5868 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 5869 { 5870 int i, err = 0; 5871 5872 for (i = 0; i < adapter->num_tx_queues; i++) { 5873 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 5874 if (!err) 5875 continue; 5876 5877 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 5878 goto err_setup_tx; 5879 } 5880 5881 return 0; 5882 err_setup_tx: 5883 /* rewind the index freeing the rings as we go */ 5884 while (i--) 5885 ixgbe_free_tx_resources(adapter->tx_ring[i]); 5886 return err; 5887 } 5888 5889 /** 5890 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 5891 * @rx_ring: rx descriptor ring (for a specific queue) to setup 5892 * 5893 * Returns 0 on success, negative on failure 5894 **/ 5895 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring) 5896 { 5897 struct device *dev = rx_ring->dev; 5898 int orig_node = dev_to_node(dev); 5899 int ring_node = -1; 5900 int size; 5901 5902 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 5903 5904 if (rx_ring->q_vector) 5905 ring_node = rx_ring->q_vector->numa_node; 5906 5907 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node); 5908 if (!rx_ring->rx_buffer_info) 5909 rx_ring->rx_buffer_info = vzalloc(size); 5910 if (!rx_ring->rx_buffer_info) 5911 goto err; 5912 5913 u64_stats_init(&rx_ring->syncp); 5914 5915 /* Round up to nearest 4K */ 5916 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 5917 rx_ring->size = ALIGN(rx_ring->size, 4096); 5918 5919 set_dev_node(dev, ring_node); 5920 rx_ring->desc = dma_alloc_coherent(dev, 5921 rx_ring->size, 5922 &rx_ring->dma, 5923 GFP_KERNEL); 5924 set_dev_node(dev, orig_node); 5925 if (!rx_ring->desc) 5926 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 5927 &rx_ring->dma, GFP_KERNEL); 5928 if (!rx_ring->desc) 5929 goto err; 5930 5931 rx_ring->next_to_clean = 0; 5932 rx_ring->next_to_use = 0; 5933 5934 return 0; 5935 err: 5936 vfree(rx_ring->rx_buffer_info); 5937 rx_ring->rx_buffer_info = NULL; 5938 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 5939 return -ENOMEM; 5940 } 5941 5942 /** 5943 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 5944 * @adapter: board private structure 5945 * 5946 * If this function returns with an error, then it's possible one or 5947 * more of the rings is populated (while the rest are not). It is the 5948 * callers duty to clean those orphaned rings. 5949 * 5950 * Return 0 on success, negative on failure 5951 **/ 5952 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 5953 { 5954 int i, err = 0; 5955 5956 for (i = 0; i < adapter->num_rx_queues; i++) { 5957 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]); 5958 if (!err) 5959 continue; 5960 5961 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 5962 goto err_setup_rx; 5963 } 5964 5965 #ifdef IXGBE_FCOE 5966 err = ixgbe_setup_fcoe_ddp_resources(adapter); 5967 if (!err) 5968 #endif 5969 return 0; 5970 err_setup_rx: 5971 /* rewind the index freeing the rings as we go */ 5972 while (i--) 5973 ixgbe_free_rx_resources(adapter->rx_ring[i]); 5974 return err; 5975 } 5976 5977 /** 5978 * ixgbe_free_tx_resources - Free Tx Resources per Queue 5979 * @tx_ring: Tx descriptor ring for a specific queue 5980 * 5981 * Free all transmit software resources 5982 **/ 5983 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 5984 { 5985 ixgbe_clean_tx_ring(tx_ring); 5986 5987 vfree(tx_ring->tx_buffer_info); 5988 tx_ring->tx_buffer_info = NULL; 5989 5990 /* if not set, then don't free */ 5991 if (!tx_ring->desc) 5992 return; 5993 5994 dma_free_coherent(tx_ring->dev, tx_ring->size, 5995 tx_ring->desc, tx_ring->dma); 5996 5997 tx_ring->desc = NULL; 5998 } 5999 6000 /** 6001 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 6002 * @adapter: board private structure 6003 * 6004 * Free all transmit software resources 6005 **/ 6006 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 6007 { 6008 int i; 6009 6010 for (i = 0; i < adapter->num_tx_queues; i++) 6011 if (adapter->tx_ring[i]->desc) 6012 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6013 } 6014 6015 /** 6016 * ixgbe_free_rx_resources - Free Rx Resources 6017 * @rx_ring: ring to clean the resources from 6018 * 6019 * Free all receive software resources 6020 **/ 6021 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 6022 { 6023 ixgbe_clean_rx_ring(rx_ring); 6024 6025 vfree(rx_ring->rx_buffer_info); 6026 rx_ring->rx_buffer_info = NULL; 6027 6028 /* if not set, then don't free */ 6029 if (!rx_ring->desc) 6030 return; 6031 6032 dma_free_coherent(rx_ring->dev, rx_ring->size, 6033 rx_ring->desc, rx_ring->dma); 6034 6035 rx_ring->desc = NULL; 6036 } 6037 6038 /** 6039 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 6040 * @adapter: board private structure 6041 * 6042 * Free all receive software resources 6043 **/ 6044 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 6045 { 6046 int i; 6047 6048 #ifdef IXGBE_FCOE 6049 ixgbe_free_fcoe_ddp_resources(adapter); 6050 6051 #endif 6052 for (i = 0; i < adapter->num_rx_queues; i++) 6053 if (adapter->rx_ring[i]->desc) 6054 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6055 } 6056 6057 /** 6058 * ixgbe_change_mtu - Change the Maximum Transfer Unit 6059 * @netdev: network interface device structure 6060 * @new_mtu: new value for maximum frame size 6061 * 6062 * Returns 0 on success, negative on failure 6063 **/ 6064 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 6065 { 6066 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6067 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; 6068 6069 /* MTU < 68 is an error and causes problems on some kernels */ 6070 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) 6071 return -EINVAL; 6072 6073 /* 6074 * For 82599EB we cannot allow legacy VFs to enable their receive 6075 * paths when MTU greater than 1500 is configured. So display a 6076 * warning that legacy VFs will be disabled. 6077 */ 6078 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 6079 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 6080 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 6081 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 6082 6083 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); 6084 6085 /* must set new MTU before calling down or up */ 6086 netdev->mtu = new_mtu; 6087 6088 if (netif_running(netdev)) 6089 ixgbe_reinit_locked(adapter); 6090 6091 return 0; 6092 } 6093 6094 /** 6095 * ixgbe_open - Called when a network interface is made active 6096 * @netdev: network interface device structure 6097 * 6098 * Returns 0 on success, negative value on failure 6099 * 6100 * The open entry point is called when a network interface is made 6101 * active by the system (IFF_UP). At this point all resources needed 6102 * for transmit and receive operations are allocated, the interrupt 6103 * handler is registered with the OS, the watchdog timer is started, 6104 * and the stack is notified that the interface is ready. 6105 **/ 6106 int ixgbe_open(struct net_device *netdev) 6107 { 6108 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6109 struct ixgbe_hw *hw = &adapter->hw; 6110 int err, queues; 6111 6112 /* disallow open during test */ 6113 if (test_bit(__IXGBE_TESTING, &adapter->state)) 6114 return -EBUSY; 6115 6116 netif_carrier_off(netdev); 6117 6118 /* allocate transmit descriptors */ 6119 err = ixgbe_setup_all_tx_resources(adapter); 6120 if (err) 6121 goto err_setup_tx; 6122 6123 /* allocate receive descriptors */ 6124 err = ixgbe_setup_all_rx_resources(adapter); 6125 if (err) 6126 goto err_setup_rx; 6127 6128 ixgbe_configure(adapter); 6129 6130 err = ixgbe_request_irq(adapter); 6131 if (err) 6132 goto err_req_irq; 6133 6134 /* Notify the stack of the actual queue counts. */ 6135 if (adapter->num_rx_pools > 1) 6136 queues = adapter->num_rx_queues_per_pool; 6137 else 6138 queues = adapter->num_tx_queues; 6139 6140 err = netif_set_real_num_tx_queues(netdev, queues); 6141 if (err) 6142 goto err_set_queues; 6143 6144 if (adapter->num_rx_pools > 1 && 6145 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES) 6146 queues = IXGBE_MAX_L2A_QUEUES; 6147 else 6148 queues = adapter->num_rx_queues; 6149 err = netif_set_real_num_rx_queues(netdev, queues); 6150 if (err) 6151 goto err_set_queues; 6152 6153 ixgbe_ptp_init(adapter); 6154 6155 ixgbe_up_complete(adapter); 6156 6157 ixgbe_clear_udp_tunnel_port(adapter, IXGBE_VXLANCTRL_ALL_UDPPORT_MASK); 6158 udp_tunnel_get_rx_info(netdev); 6159 6160 return 0; 6161 6162 err_set_queues: 6163 ixgbe_free_irq(adapter); 6164 err_req_irq: 6165 ixgbe_free_all_rx_resources(adapter); 6166 if (hw->phy.ops.set_phy_power && !adapter->wol) 6167 hw->phy.ops.set_phy_power(&adapter->hw, false); 6168 err_setup_rx: 6169 ixgbe_free_all_tx_resources(adapter); 6170 err_setup_tx: 6171 ixgbe_reset(adapter); 6172 6173 return err; 6174 } 6175 6176 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 6177 { 6178 ixgbe_ptp_suspend(adapter); 6179 6180 if (adapter->hw.phy.ops.enter_lplu) { 6181 adapter->hw.phy.reset_disable = true; 6182 ixgbe_down(adapter); 6183 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 6184 adapter->hw.phy.reset_disable = false; 6185 } else { 6186 ixgbe_down(adapter); 6187 } 6188 6189 ixgbe_free_irq(adapter); 6190 6191 ixgbe_free_all_tx_resources(adapter); 6192 ixgbe_free_all_rx_resources(adapter); 6193 } 6194 6195 /** 6196 * ixgbe_close - Disables a network interface 6197 * @netdev: network interface device structure 6198 * 6199 * Returns 0, this is not allowed to fail 6200 * 6201 * The close entry point is called when an interface is de-activated 6202 * by the OS. The hardware is still under the drivers control, but 6203 * needs to be disabled. A global MAC reset is issued to stop the 6204 * hardware, and all transmit and receive resources are freed. 6205 **/ 6206 int ixgbe_close(struct net_device *netdev) 6207 { 6208 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6209 6210 ixgbe_ptp_stop(adapter); 6211 6212 ixgbe_close_suspend(adapter); 6213 6214 ixgbe_fdir_filter_exit(adapter); 6215 6216 ixgbe_release_hw_control(adapter); 6217 6218 return 0; 6219 } 6220 6221 #ifdef CONFIG_PM 6222 static int ixgbe_resume(struct pci_dev *pdev) 6223 { 6224 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6225 struct net_device *netdev = adapter->netdev; 6226 u32 err; 6227 6228 adapter->hw.hw_addr = adapter->io_addr; 6229 pci_set_power_state(pdev, PCI_D0); 6230 pci_restore_state(pdev); 6231 /* 6232 * pci_restore_state clears dev->state_saved so call 6233 * pci_save_state to restore it. 6234 */ 6235 pci_save_state(pdev); 6236 6237 err = pci_enable_device_mem(pdev); 6238 if (err) { 6239 e_dev_err("Cannot enable PCI device from suspend\n"); 6240 return err; 6241 } 6242 smp_mb__before_atomic(); 6243 clear_bit(__IXGBE_DISABLED, &adapter->state); 6244 pci_set_master(pdev); 6245 6246 pci_wake_from_d3(pdev, false); 6247 6248 ixgbe_reset(adapter); 6249 6250 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 6251 6252 rtnl_lock(); 6253 err = ixgbe_init_interrupt_scheme(adapter); 6254 if (!err && netif_running(netdev)) 6255 err = ixgbe_open(netdev); 6256 6257 rtnl_unlock(); 6258 6259 if (err) 6260 return err; 6261 6262 netif_device_attach(netdev); 6263 6264 return 0; 6265 } 6266 #endif /* CONFIG_PM */ 6267 6268 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 6269 { 6270 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6271 struct net_device *netdev = adapter->netdev; 6272 struct ixgbe_hw *hw = &adapter->hw; 6273 u32 ctrl, fctrl; 6274 u32 wufc = adapter->wol; 6275 #ifdef CONFIG_PM 6276 int retval = 0; 6277 #endif 6278 6279 netif_device_detach(netdev); 6280 6281 rtnl_lock(); 6282 if (netif_running(netdev)) 6283 ixgbe_close_suspend(adapter); 6284 rtnl_unlock(); 6285 6286 ixgbe_clear_interrupt_scheme(adapter); 6287 6288 #ifdef CONFIG_PM 6289 retval = pci_save_state(pdev); 6290 if (retval) 6291 return retval; 6292 6293 #endif 6294 if (hw->mac.ops.stop_link_on_d3) 6295 hw->mac.ops.stop_link_on_d3(hw); 6296 6297 if (wufc) { 6298 ixgbe_set_rx_mode(netdev); 6299 6300 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 6301 if (hw->mac.ops.enable_tx_laser) 6302 hw->mac.ops.enable_tx_laser(hw); 6303 6304 /* turn on all-multi mode if wake on multicast is enabled */ 6305 if (wufc & IXGBE_WUFC_MC) { 6306 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6307 fctrl |= IXGBE_FCTRL_MPE; 6308 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 6309 } 6310 6311 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 6312 ctrl |= IXGBE_CTRL_GIO_DIS; 6313 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 6314 6315 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 6316 } else { 6317 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 6318 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 6319 } 6320 6321 switch (hw->mac.type) { 6322 case ixgbe_mac_82598EB: 6323 pci_wake_from_d3(pdev, false); 6324 break; 6325 case ixgbe_mac_82599EB: 6326 case ixgbe_mac_X540: 6327 case ixgbe_mac_X550: 6328 case ixgbe_mac_X550EM_x: 6329 case ixgbe_mac_x550em_a: 6330 pci_wake_from_d3(pdev, !!wufc); 6331 break; 6332 default: 6333 break; 6334 } 6335 6336 *enable_wake = !!wufc; 6337 if (hw->phy.ops.set_phy_power && !*enable_wake) 6338 hw->phy.ops.set_phy_power(hw, false); 6339 6340 ixgbe_release_hw_control(adapter); 6341 6342 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 6343 pci_disable_device(pdev); 6344 6345 return 0; 6346 } 6347 6348 #ifdef CONFIG_PM 6349 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) 6350 { 6351 int retval; 6352 bool wake; 6353 6354 retval = __ixgbe_shutdown(pdev, &wake); 6355 if (retval) 6356 return retval; 6357 6358 if (wake) { 6359 pci_prepare_to_sleep(pdev); 6360 } else { 6361 pci_wake_from_d3(pdev, false); 6362 pci_set_power_state(pdev, PCI_D3hot); 6363 } 6364 6365 return 0; 6366 } 6367 #endif /* CONFIG_PM */ 6368 6369 static void ixgbe_shutdown(struct pci_dev *pdev) 6370 { 6371 bool wake; 6372 6373 __ixgbe_shutdown(pdev, &wake); 6374 6375 if (system_state == SYSTEM_POWER_OFF) { 6376 pci_wake_from_d3(pdev, wake); 6377 pci_set_power_state(pdev, PCI_D3hot); 6378 } 6379 } 6380 6381 /** 6382 * ixgbe_update_stats - Update the board statistics counters. 6383 * @adapter: board private structure 6384 **/ 6385 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 6386 { 6387 struct net_device *netdev = adapter->netdev; 6388 struct ixgbe_hw *hw = &adapter->hw; 6389 struct ixgbe_hw_stats *hwstats = &adapter->stats; 6390 u64 total_mpc = 0; 6391 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 6392 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 6393 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 6394 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 6395 6396 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6397 test_bit(__IXGBE_RESETTING, &adapter->state)) 6398 return; 6399 6400 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 6401 u64 rsc_count = 0; 6402 u64 rsc_flush = 0; 6403 for (i = 0; i < adapter->num_rx_queues; i++) { 6404 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 6405 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 6406 } 6407 adapter->rsc_total_count = rsc_count; 6408 adapter->rsc_total_flush = rsc_flush; 6409 } 6410 6411 for (i = 0; i < adapter->num_rx_queues; i++) { 6412 struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; 6413 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 6414 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 6415 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 6416 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 6417 bytes += rx_ring->stats.bytes; 6418 packets += rx_ring->stats.packets; 6419 } 6420 adapter->non_eop_descs = non_eop_descs; 6421 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 6422 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 6423 adapter->hw_csum_rx_error = hw_csum_rx_error; 6424 netdev->stats.rx_bytes = bytes; 6425 netdev->stats.rx_packets = packets; 6426 6427 bytes = 0; 6428 packets = 0; 6429 /* gather some stats to the adapter struct that are per queue */ 6430 for (i = 0; i < adapter->num_tx_queues; i++) { 6431 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 6432 restart_queue += tx_ring->tx_stats.restart_queue; 6433 tx_busy += tx_ring->tx_stats.tx_busy; 6434 bytes += tx_ring->stats.bytes; 6435 packets += tx_ring->stats.packets; 6436 } 6437 adapter->restart_queue = restart_queue; 6438 adapter->tx_busy = tx_busy; 6439 netdev->stats.tx_bytes = bytes; 6440 netdev->stats.tx_packets = packets; 6441 6442 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 6443 6444 /* 8 register reads */ 6445 for (i = 0; i < 8; i++) { 6446 /* for packet buffers not used, the register should read 0 */ 6447 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 6448 missed_rx += mpc; 6449 hwstats->mpc[i] += mpc; 6450 total_mpc += hwstats->mpc[i]; 6451 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 6452 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 6453 switch (hw->mac.type) { 6454 case ixgbe_mac_82598EB: 6455 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 6456 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 6457 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 6458 hwstats->pxonrxc[i] += 6459 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 6460 break; 6461 case ixgbe_mac_82599EB: 6462 case ixgbe_mac_X540: 6463 case ixgbe_mac_X550: 6464 case ixgbe_mac_X550EM_x: 6465 case ixgbe_mac_x550em_a: 6466 hwstats->pxonrxc[i] += 6467 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 6468 break; 6469 default: 6470 break; 6471 } 6472 } 6473 6474 /*16 register reads */ 6475 for (i = 0; i < 16; i++) { 6476 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 6477 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 6478 if ((hw->mac.type == ixgbe_mac_82599EB) || 6479 (hw->mac.type == ixgbe_mac_X540) || 6480 (hw->mac.type == ixgbe_mac_X550) || 6481 (hw->mac.type == ixgbe_mac_X550EM_x) || 6482 (hw->mac.type == ixgbe_mac_x550em_a)) { 6483 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 6484 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 6485 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 6486 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 6487 } 6488 } 6489 6490 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 6491 /* work around hardware counting issue */ 6492 hwstats->gprc -= missed_rx; 6493 6494 ixgbe_update_xoff_received(adapter); 6495 6496 /* 82598 hardware only has a 32 bit counter in the high register */ 6497 switch (hw->mac.type) { 6498 case ixgbe_mac_82598EB: 6499 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 6500 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 6501 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 6502 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 6503 break; 6504 case ixgbe_mac_X540: 6505 case ixgbe_mac_X550: 6506 case ixgbe_mac_X550EM_x: 6507 case ixgbe_mac_x550em_a: 6508 /* OS2BMC stats are X540 and later */ 6509 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 6510 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 6511 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 6512 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 6513 case ixgbe_mac_82599EB: 6514 for (i = 0; i < 16; i++) 6515 adapter->hw_rx_no_dma_resources += 6516 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 6517 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 6518 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 6519 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 6520 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 6521 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 6522 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 6523 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 6524 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 6525 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 6526 #ifdef IXGBE_FCOE 6527 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 6528 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 6529 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 6530 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 6531 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 6532 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 6533 /* Add up per cpu counters for total ddp aloc fail */ 6534 if (adapter->fcoe.ddp_pool) { 6535 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 6536 struct ixgbe_fcoe_ddp_pool *ddp_pool; 6537 unsigned int cpu; 6538 u64 noddp = 0, noddp_ext_buff = 0; 6539 for_each_possible_cpu(cpu) { 6540 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 6541 noddp += ddp_pool->noddp; 6542 noddp_ext_buff += ddp_pool->noddp_ext_buff; 6543 } 6544 hwstats->fcoe_noddp = noddp; 6545 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 6546 } 6547 #endif /* IXGBE_FCOE */ 6548 break; 6549 default: 6550 break; 6551 } 6552 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 6553 hwstats->bprc += bprc; 6554 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 6555 if (hw->mac.type == ixgbe_mac_82598EB) 6556 hwstats->mprc -= bprc; 6557 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 6558 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 6559 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 6560 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 6561 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 6562 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 6563 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 6564 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 6565 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 6566 hwstats->lxontxc += lxon; 6567 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 6568 hwstats->lxofftxc += lxoff; 6569 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 6570 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 6571 /* 6572 * 82598 errata - tx of flow control packets is included in tx counters 6573 */ 6574 xon_off_tot = lxon + lxoff; 6575 hwstats->gptc -= xon_off_tot; 6576 hwstats->mptc -= xon_off_tot; 6577 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 6578 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 6579 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 6580 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 6581 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 6582 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 6583 hwstats->ptc64 -= xon_off_tot; 6584 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 6585 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 6586 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 6587 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 6588 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 6589 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 6590 6591 /* Fill out the OS statistics structure */ 6592 netdev->stats.multicast = hwstats->mprc; 6593 6594 /* Rx Errors */ 6595 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 6596 netdev->stats.rx_dropped = 0; 6597 netdev->stats.rx_length_errors = hwstats->rlec; 6598 netdev->stats.rx_crc_errors = hwstats->crcerrs; 6599 netdev->stats.rx_missed_errors = total_mpc; 6600 } 6601 6602 /** 6603 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 6604 * @adapter: pointer to the device adapter structure 6605 **/ 6606 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 6607 { 6608 struct ixgbe_hw *hw = &adapter->hw; 6609 int i; 6610 6611 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 6612 return; 6613 6614 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 6615 6616 /* if interface is down do nothing */ 6617 if (test_bit(__IXGBE_DOWN, &adapter->state)) 6618 return; 6619 6620 /* do nothing if we are not using signature filters */ 6621 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 6622 return; 6623 6624 adapter->fdir_overflow++; 6625 6626 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 6627 for (i = 0; i < adapter->num_tx_queues; i++) 6628 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 6629 &(adapter->tx_ring[i]->state)); 6630 /* re-enable flow director interrupts */ 6631 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 6632 } else { 6633 e_err(probe, "failed to finish FDIR re-initialization, " 6634 "ignored adding FDIR ATR filters\n"); 6635 } 6636 } 6637 6638 /** 6639 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 6640 * @adapter: pointer to the device adapter structure 6641 * 6642 * This function serves two purposes. First it strobes the interrupt lines 6643 * in order to make certain interrupts are occurring. Secondly it sets the 6644 * bits needed to check for TX hangs. As a result we should immediately 6645 * determine if a hang has occurred. 6646 */ 6647 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 6648 { 6649 struct ixgbe_hw *hw = &adapter->hw; 6650 u64 eics = 0; 6651 int i; 6652 6653 /* If we're down, removing or resetting, just bail */ 6654 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6655 test_bit(__IXGBE_REMOVING, &adapter->state) || 6656 test_bit(__IXGBE_RESETTING, &adapter->state)) 6657 return; 6658 6659 /* Force detection of hung controller */ 6660 if (netif_carrier_ok(adapter->netdev)) { 6661 for (i = 0; i < adapter->num_tx_queues; i++) 6662 set_check_for_tx_hang(adapter->tx_ring[i]); 6663 } 6664 6665 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 6666 /* 6667 * for legacy and MSI interrupts don't set any bits 6668 * that are enabled for EIAM, because this operation 6669 * would set *both* EIMS and EICS for any bit in EIAM 6670 */ 6671 IXGBE_WRITE_REG(hw, IXGBE_EICS, 6672 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 6673 } else { 6674 /* get one bit for every active tx/rx interrupt vector */ 6675 for (i = 0; i < adapter->num_q_vectors; i++) { 6676 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 6677 if (qv->rx.ring || qv->tx.ring) 6678 eics |= BIT_ULL(i); 6679 } 6680 } 6681 6682 /* Cause software interrupt to ensure rings are cleaned */ 6683 ixgbe_irq_rearm_queues(adapter, eics); 6684 } 6685 6686 /** 6687 * ixgbe_watchdog_update_link - update the link status 6688 * @adapter: pointer to the device adapter structure 6689 * @link_speed: pointer to a u32 to store the link_speed 6690 **/ 6691 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 6692 { 6693 struct ixgbe_hw *hw = &adapter->hw; 6694 u32 link_speed = adapter->link_speed; 6695 bool link_up = adapter->link_up; 6696 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 6697 6698 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 6699 return; 6700 6701 if (hw->mac.ops.check_link) { 6702 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 6703 } else { 6704 /* always assume link is up, if no check link function */ 6705 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 6706 link_up = true; 6707 } 6708 6709 if (adapter->ixgbe_ieee_pfc) 6710 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 6711 6712 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 6713 hw->mac.ops.fc_enable(hw); 6714 ixgbe_set_rx_drop_en(adapter); 6715 } 6716 6717 if (link_up || 6718 time_after(jiffies, (adapter->link_check_timeout + 6719 IXGBE_TRY_LINK_TIMEOUT))) { 6720 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 6721 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 6722 IXGBE_WRITE_FLUSH(hw); 6723 } 6724 6725 adapter->link_up = link_up; 6726 adapter->link_speed = link_speed; 6727 } 6728 6729 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 6730 { 6731 #ifdef CONFIG_IXGBE_DCB 6732 struct net_device *netdev = adapter->netdev; 6733 struct dcb_app app = { 6734 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 6735 .protocol = 0, 6736 }; 6737 u8 up = 0; 6738 6739 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 6740 up = dcb_ieee_getapp_mask(netdev, &app); 6741 6742 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 6743 #endif 6744 } 6745 6746 /** 6747 * ixgbe_watchdog_link_is_up - update netif_carrier status and 6748 * print link up message 6749 * @adapter: pointer to the device adapter structure 6750 **/ 6751 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 6752 { 6753 struct net_device *netdev = adapter->netdev; 6754 struct ixgbe_hw *hw = &adapter->hw; 6755 struct net_device *upper; 6756 struct list_head *iter; 6757 u32 link_speed = adapter->link_speed; 6758 const char *speed_str; 6759 bool flow_rx, flow_tx; 6760 6761 /* only continue if link was previously down */ 6762 if (netif_carrier_ok(netdev)) 6763 return; 6764 6765 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 6766 6767 switch (hw->mac.type) { 6768 case ixgbe_mac_82598EB: { 6769 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6770 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 6771 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 6772 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 6773 } 6774 break; 6775 case ixgbe_mac_X540: 6776 case ixgbe_mac_X550: 6777 case ixgbe_mac_X550EM_x: 6778 case ixgbe_mac_x550em_a: 6779 case ixgbe_mac_82599EB: { 6780 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 6781 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 6782 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 6783 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 6784 } 6785 break; 6786 default: 6787 flow_tx = false; 6788 flow_rx = false; 6789 break; 6790 } 6791 6792 adapter->last_rx_ptp_check = jiffies; 6793 6794 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 6795 ixgbe_ptp_start_cyclecounter(adapter); 6796 6797 switch (link_speed) { 6798 case IXGBE_LINK_SPEED_10GB_FULL: 6799 speed_str = "10 Gbps"; 6800 break; 6801 case IXGBE_LINK_SPEED_2_5GB_FULL: 6802 speed_str = "2.5 Gbps"; 6803 break; 6804 case IXGBE_LINK_SPEED_1GB_FULL: 6805 speed_str = "1 Gbps"; 6806 break; 6807 case IXGBE_LINK_SPEED_100_FULL: 6808 speed_str = "100 Mbps"; 6809 break; 6810 default: 6811 speed_str = "unknown speed"; 6812 break; 6813 } 6814 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, 6815 ((flow_rx && flow_tx) ? "RX/TX" : 6816 (flow_rx ? "RX" : 6817 (flow_tx ? "TX" : "None")))); 6818 6819 netif_carrier_on(netdev); 6820 ixgbe_check_vf_rate_limit(adapter); 6821 6822 /* enable transmits */ 6823 netif_tx_wake_all_queues(adapter->netdev); 6824 6825 /* enable any upper devices */ 6826 rtnl_lock(); 6827 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { 6828 if (netif_is_macvlan(upper)) { 6829 struct macvlan_dev *vlan = netdev_priv(upper); 6830 6831 if (vlan->fwd_priv) 6832 netif_tx_wake_all_queues(upper); 6833 } 6834 } 6835 rtnl_unlock(); 6836 6837 /* update the default user priority for VFs */ 6838 ixgbe_update_default_up(adapter); 6839 6840 /* ping all the active vfs to let them know link has changed */ 6841 ixgbe_ping_all_vfs(adapter); 6842 } 6843 6844 /** 6845 * ixgbe_watchdog_link_is_down - update netif_carrier status and 6846 * print link down message 6847 * @adapter: pointer to the adapter structure 6848 **/ 6849 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 6850 { 6851 struct net_device *netdev = adapter->netdev; 6852 struct ixgbe_hw *hw = &adapter->hw; 6853 6854 adapter->link_up = false; 6855 adapter->link_speed = 0; 6856 6857 /* only continue if link was up previously */ 6858 if (!netif_carrier_ok(netdev)) 6859 return; 6860 6861 /* poll for SFP+ cable when link is down */ 6862 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 6863 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 6864 6865 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 6866 ixgbe_ptp_start_cyclecounter(adapter); 6867 6868 e_info(drv, "NIC Link is Down\n"); 6869 netif_carrier_off(netdev); 6870 6871 /* ping all the active vfs to let them know link has changed */ 6872 ixgbe_ping_all_vfs(adapter); 6873 } 6874 6875 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 6876 { 6877 int i; 6878 6879 for (i = 0; i < adapter->num_tx_queues; i++) { 6880 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 6881 6882 if (tx_ring->next_to_use != tx_ring->next_to_clean) 6883 return true; 6884 } 6885 6886 return false; 6887 } 6888 6889 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 6890 { 6891 struct ixgbe_hw *hw = &adapter->hw; 6892 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 6893 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 6894 6895 int i, j; 6896 6897 if (!adapter->num_vfs) 6898 return false; 6899 6900 /* resetting the PF is only needed for MAC before X550 */ 6901 if (hw->mac.type >= ixgbe_mac_X550) 6902 return false; 6903 6904 for (i = 0; i < adapter->num_vfs; i++) { 6905 for (j = 0; j < q_per_pool; j++) { 6906 u32 h, t; 6907 6908 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 6909 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 6910 6911 if (h != t) 6912 return true; 6913 } 6914 } 6915 6916 return false; 6917 } 6918 6919 /** 6920 * ixgbe_watchdog_flush_tx - flush queues on link down 6921 * @adapter: pointer to the device adapter structure 6922 **/ 6923 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 6924 { 6925 if (!netif_carrier_ok(adapter->netdev)) { 6926 if (ixgbe_ring_tx_pending(adapter) || 6927 ixgbe_vf_tx_pending(adapter)) { 6928 /* We've lost link, so the controller stops DMA, 6929 * but we've got queued Tx work that's never going 6930 * to get done, so reset controller to flush Tx. 6931 * (Do the reset outside of interrupt context). 6932 */ 6933 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 6934 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 6935 } 6936 } 6937 } 6938 6939 #ifdef CONFIG_PCI_IOV 6940 static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter, 6941 struct pci_dev *vfdev) 6942 { 6943 if (!pci_wait_for_pending_transaction(vfdev)) 6944 e_dev_warn("Issuing VFLR with pending transactions\n"); 6945 6946 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev)); 6947 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 6948 6949 msleep(100); 6950 } 6951 6952 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 6953 { 6954 struct ixgbe_hw *hw = &adapter->hw; 6955 struct pci_dev *pdev = adapter->pdev; 6956 unsigned int vf; 6957 u32 gpc; 6958 6959 if (!(netif_carrier_ok(adapter->netdev))) 6960 return; 6961 6962 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 6963 if (gpc) /* If incrementing then no need for the check below */ 6964 return; 6965 /* Check to see if a bad DMA write target from an errant or 6966 * malicious VF has caused a PCIe error. If so then we can 6967 * issue a VFLR to the offending VF(s) and then resume without 6968 * requesting a full slot reset. 6969 */ 6970 6971 if (!pdev) 6972 return; 6973 6974 /* check status reg for all VFs owned by this PF */ 6975 for (vf = 0; vf < adapter->num_vfs; ++vf) { 6976 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; 6977 u16 status_reg; 6978 6979 if (!vfdev) 6980 continue; 6981 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 6982 if (status_reg != IXGBE_FAILED_READ_CFG_WORD && 6983 status_reg & PCI_STATUS_REC_MASTER_ABORT) 6984 ixgbe_issue_vf_flr(adapter, vfdev); 6985 } 6986 } 6987 6988 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 6989 { 6990 u32 ssvpc; 6991 6992 /* Do not perform spoof check for 82598 or if not in IOV mode */ 6993 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 6994 adapter->num_vfs == 0) 6995 return; 6996 6997 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 6998 6999 /* 7000 * ssvpc register is cleared on read, if zero then no 7001 * spoofed packets in the last interval. 7002 */ 7003 if (!ssvpc) 7004 return; 7005 7006 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 7007 } 7008 #else 7009 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 7010 { 7011 } 7012 7013 static void 7014 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 7015 { 7016 } 7017 #endif /* CONFIG_PCI_IOV */ 7018 7019 7020 /** 7021 * ixgbe_watchdog_subtask - check and bring link up 7022 * @adapter: pointer to the device adapter structure 7023 **/ 7024 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 7025 { 7026 /* if interface is down, removing or resetting, do nothing */ 7027 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7028 test_bit(__IXGBE_REMOVING, &adapter->state) || 7029 test_bit(__IXGBE_RESETTING, &adapter->state)) 7030 return; 7031 7032 ixgbe_watchdog_update_link(adapter); 7033 7034 if (adapter->link_up) 7035 ixgbe_watchdog_link_is_up(adapter); 7036 else 7037 ixgbe_watchdog_link_is_down(adapter); 7038 7039 ixgbe_check_for_bad_vf(adapter); 7040 ixgbe_spoof_check(adapter); 7041 ixgbe_update_stats(adapter); 7042 7043 ixgbe_watchdog_flush_tx(adapter); 7044 } 7045 7046 /** 7047 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 7048 * @adapter: the ixgbe adapter structure 7049 **/ 7050 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 7051 { 7052 struct ixgbe_hw *hw = &adapter->hw; 7053 s32 err; 7054 7055 /* not searching for SFP so there is nothing to do here */ 7056 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 7057 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7058 return; 7059 7060 if (adapter->sfp_poll_time && 7061 time_after(adapter->sfp_poll_time, jiffies)) 7062 return; /* If not yet time to poll for SFP */ 7063 7064 /* someone else is in init, wait until next service event */ 7065 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7066 return; 7067 7068 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; 7069 7070 err = hw->phy.ops.identify_sfp(hw); 7071 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7072 goto sfp_out; 7073 7074 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 7075 /* If no cable is present, then we need to reset 7076 * the next time we find a good cable. */ 7077 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 7078 } 7079 7080 /* exit on error */ 7081 if (err) 7082 goto sfp_out; 7083 7084 /* exit if reset not needed */ 7085 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7086 goto sfp_out; 7087 7088 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 7089 7090 /* 7091 * A module may be identified correctly, but the EEPROM may not have 7092 * support for that module. setup_sfp() will fail in that case, so 7093 * we should not allow that module to load. 7094 */ 7095 if (hw->mac.type == ixgbe_mac_82598EB) 7096 err = hw->phy.ops.reset(hw); 7097 else 7098 err = hw->mac.ops.setup_sfp(hw); 7099 7100 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7101 goto sfp_out; 7102 7103 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 7104 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 7105 7106 sfp_out: 7107 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7108 7109 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && 7110 (adapter->netdev->reg_state == NETREG_REGISTERED)) { 7111 e_dev_err("failed to initialize because an unsupported " 7112 "SFP+ module type was detected.\n"); 7113 e_dev_err("Reload the driver after installing a " 7114 "supported module.\n"); 7115 unregister_netdev(adapter->netdev); 7116 } 7117 } 7118 7119 /** 7120 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 7121 * @adapter: the ixgbe adapter structure 7122 **/ 7123 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 7124 { 7125 struct ixgbe_hw *hw = &adapter->hw; 7126 u32 speed; 7127 bool autoneg = false; 7128 7129 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 7130 return; 7131 7132 /* someone else is in init, wait until next service event */ 7133 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7134 return; 7135 7136 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 7137 7138 speed = hw->phy.autoneg_advertised; 7139 if ((!speed) && (hw->mac.ops.get_link_capabilities)) { 7140 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg); 7141 7142 /* setup the highest link when no autoneg */ 7143 if (!autoneg) { 7144 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 7145 speed = IXGBE_LINK_SPEED_10GB_FULL; 7146 } 7147 } 7148 7149 if (hw->mac.ops.setup_link) 7150 hw->mac.ops.setup_link(hw, speed, true); 7151 7152 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 7153 adapter->link_check_timeout = jiffies; 7154 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7155 } 7156 7157 /** 7158 * ixgbe_service_timer - Timer Call-back 7159 * @data: pointer to adapter cast into an unsigned long 7160 **/ 7161 static void ixgbe_service_timer(unsigned long data) 7162 { 7163 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; 7164 unsigned long next_event_offset; 7165 7166 /* poll faster when waiting for link */ 7167 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 7168 next_event_offset = HZ / 10; 7169 else 7170 next_event_offset = HZ * 2; 7171 7172 /* Reset the timer */ 7173 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 7174 7175 ixgbe_service_event_schedule(adapter); 7176 } 7177 7178 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 7179 { 7180 struct ixgbe_hw *hw = &adapter->hw; 7181 u32 status; 7182 7183 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 7184 return; 7185 7186 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 7187 7188 if (!hw->phy.ops.handle_lasi) 7189 return; 7190 7191 status = hw->phy.ops.handle_lasi(&adapter->hw); 7192 if (status != IXGBE_ERR_OVERTEMP) 7193 return; 7194 7195 e_crit(drv, "%s\n", ixgbe_overheat_msg); 7196 } 7197 7198 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 7199 { 7200 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state)) 7201 return; 7202 7203 /* If we're already down, removing or resetting, just bail */ 7204 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7205 test_bit(__IXGBE_REMOVING, &adapter->state) || 7206 test_bit(__IXGBE_RESETTING, &adapter->state)) 7207 return; 7208 7209 ixgbe_dump(adapter); 7210 netdev_err(adapter->netdev, "Reset adapter\n"); 7211 adapter->tx_timeout_count++; 7212 7213 rtnl_lock(); 7214 ixgbe_reinit_locked(adapter); 7215 rtnl_unlock(); 7216 } 7217 7218 /** 7219 * ixgbe_service_task - manages and runs subtasks 7220 * @work: pointer to work_struct containing our data 7221 **/ 7222 static void ixgbe_service_task(struct work_struct *work) 7223 { 7224 struct ixgbe_adapter *adapter = container_of(work, 7225 struct ixgbe_adapter, 7226 service_task); 7227 if (ixgbe_removed(adapter->hw.hw_addr)) { 7228 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 7229 rtnl_lock(); 7230 ixgbe_down(adapter); 7231 rtnl_unlock(); 7232 } 7233 ixgbe_service_event_complete(adapter); 7234 return; 7235 } 7236 if (adapter->flags2 & IXGBE_FLAG2_UDP_TUN_REREG_NEEDED) { 7237 rtnl_lock(); 7238 adapter->flags2 &= ~IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 7239 udp_tunnel_get_rx_info(adapter->netdev); 7240 rtnl_unlock(); 7241 } 7242 ixgbe_reset_subtask(adapter); 7243 ixgbe_phy_interrupt_subtask(adapter); 7244 ixgbe_sfp_detection_subtask(adapter); 7245 ixgbe_sfp_link_config_subtask(adapter); 7246 ixgbe_check_overtemp_subtask(adapter); 7247 ixgbe_watchdog_subtask(adapter); 7248 ixgbe_fdir_reinit_subtask(adapter); 7249 ixgbe_check_hang_subtask(adapter); 7250 7251 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 7252 ixgbe_ptp_overflow_check(adapter); 7253 ixgbe_ptp_rx_hang(adapter); 7254 } 7255 7256 ixgbe_service_event_complete(adapter); 7257 } 7258 7259 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 7260 struct ixgbe_tx_buffer *first, 7261 u8 *hdr_len) 7262 { 7263 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 7264 struct sk_buff *skb = first->skb; 7265 union { 7266 struct iphdr *v4; 7267 struct ipv6hdr *v6; 7268 unsigned char *hdr; 7269 } ip; 7270 union { 7271 struct tcphdr *tcp; 7272 unsigned char *hdr; 7273 } l4; 7274 u32 paylen, l4_offset; 7275 int err; 7276 7277 if (skb->ip_summed != CHECKSUM_PARTIAL) 7278 return 0; 7279 7280 if (!skb_is_gso(skb)) 7281 return 0; 7282 7283 err = skb_cow_head(skb, 0); 7284 if (err < 0) 7285 return err; 7286 7287 ip.hdr = skb_network_header(skb); 7288 l4.hdr = skb_checksum_start(skb); 7289 7290 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 7291 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 7292 7293 /* initialize outer IP header fields */ 7294 if (ip.v4->version == 4) { 7295 /* IP header will have to cancel out any data that 7296 * is not a part of the outer IP header 7297 */ 7298 ip.v4->check = csum_fold(csum_add(lco_csum(skb), 7299 csum_unfold(l4.tcp->check))); 7300 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 7301 7302 ip.v4->tot_len = 0; 7303 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7304 IXGBE_TX_FLAGS_CSUM | 7305 IXGBE_TX_FLAGS_IPV4; 7306 } else { 7307 ip.v6->payload_len = 0; 7308 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7309 IXGBE_TX_FLAGS_CSUM; 7310 } 7311 7312 /* determine offset of inner transport header */ 7313 l4_offset = l4.hdr - skb->data; 7314 7315 /* compute length of segmentation header */ 7316 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 7317 7318 /* remove payload length from inner checksum */ 7319 paylen = skb->len - l4_offset; 7320 csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); 7321 7322 /* update gso size and bytecount with header size */ 7323 first->gso_segs = skb_shinfo(skb)->gso_segs; 7324 first->bytecount += (first->gso_segs - 1) * *hdr_len; 7325 7326 /* mss_l4len_id: use 0 as index for TSO */ 7327 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; 7328 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 7329 7330 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 7331 vlan_macip_lens = l4.hdr - ip.hdr; 7332 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; 7333 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 7334 7335 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 7336 mss_l4len_idx); 7337 7338 return 1; 7339 } 7340 7341 static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb) 7342 { 7343 unsigned int offset = 0; 7344 7345 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 7346 7347 return offset == skb_checksum_start_offset(skb); 7348 } 7349 7350 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 7351 struct ixgbe_tx_buffer *first) 7352 { 7353 struct sk_buff *skb = first->skb; 7354 u32 vlan_macip_lens = 0; 7355 u32 type_tucmd = 0; 7356 7357 if (skb->ip_summed != CHECKSUM_PARTIAL) { 7358 csum_failed: 7359 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | 7360 IXGBE_TX_FLAGS_CC))) 7361 return; 7362 goto no_csum; 7363 } 7364 7365 switch (skb->csum_offset) { 7366 case offsetof(struct tcphdr, check): 7367 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 7368 /* fall through */ 7369 case offsetof(struct udphdr, check): 7370 break; 7371 case offsetof(struct sctphdr, checksum): 7372 /* validate that this is actually an SCTP request */ 7373 if (((first->protocol == htons(ETH_P_IP)) && 7374 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 7375 ((first->protocol == htons(ETH_P_IPV6)) && 7376 ixgbe_ipv6_csum_is_sctp(skb))) { 7377 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; 7378 break; 7379 } 7380 /* fall through */ 7381 default: 7382 skb_checksum_help(skb); 7383 goto csum_failed; 7384 } 7385 7386 /* update TX checksum flag */ 7387 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 7388 vlan_macip_lens = skb_checksum_start_offset(skb) - 7389 skb_network_offset(skb); 7390 no_csum: 7391 /* vlan_macip_lens: MACLEN, VLAN tag */ 7392 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 7393 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 7394 7395 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 0); 7396 } 7397 7398 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 7399 ((_flag <= _result) ? \ 7400 ((u32)(_input & _flag) * (_result / _flag)) : \ 7401 ((u32)(_input & _flag) / (_flag / _result))) 7402 7403 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 7404 { 7405 /* set type for advanced descriptor with frame checksum insertion */ 7406 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 7407 IXGBE_ADVTXD_DCMD_DEXT | 7408 IXGBE_ADVTXD_DCMD_IFCS; 7409 7410 /* set HW vlan bit if vlan is present */ 7411 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 7412 IXGBE_ADVTXD_DCMD_VLE); 7413 7414 /* set segmentation enable bits for TSO/FSO */ 7415 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 7416 IXGBE_ADVTXD_DCMD_TSE); 7417 7418 /* set timestamp bit if present */ 7419 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 7420 IXGBE_ADVTXD_MAC_TSTAMP); 7421 7422 /* insert frame checksum */ 7423 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 7424 7425 return cmd_type; 7426 } 7427 7428 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 7429 u32 tx_flags, unsigned int paylen) 7430 { 7431 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 7432 7433 /* enable L4 checksum for TSO and TX checksum offload */ 7434 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7435 IXGBE_TX_FLAGS_CSUM, 7436 IXGBE_ADVTXD_POPTS_TXSM); 7437 7438 /* enble IPv4 checksum for TSO */ 7439 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7440 IXGBE_TX_FLAGS_IPV4, 7441 IXGBE_ADVTXD_POPTS_IXSM); 7442 7443 /* 7444 * Check Context must be set if Tx switch is enabled, which it 7445 * always is for case where virtual functions are running 7446 */ 7447 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7448 IXGBE_TX_FLAGS_CC, 7449 IXGBE_ADVTXD_CC); 7450 7451 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 7452 } 7453 7454 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 7455 { 7456 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 7457 7458 /* Herbert's original patch had: 7459 * smp_mb__after_netif_stop_queue(); 7460 * but since that doesn't exist yet, just open code it. 7461 */ 7462 smp_mb(); 7463 7464 /* We need to check again in a case another CPU has just 7465 * made room available. 7466 */ 7467 if (likely(ixgbe_desc_unused(tx_ring) < size)) 7468 return -EBUSY; 7469 7470 /* A reprieve! - use start_queue because it doesn't call schedule */ 7471 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 7472 ++tx_ring->tx_stats.restart_queue; 7473 return 0; 7474 } 7475 7476 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 7477 { 7478 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 7479 return 0; 7480 7481 return __ixgbe_maybe_stop_tx(tx_ring, size); 7482 } 7483 7484 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ 7485 IXGBE_TXD_CMD_RS) 7486 7487 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring, 7488 struct ixgbe_tx_buffer *first, 7489 const u8 hdr_len) 7490 { 7491 struct sk_buff *skb = first->skb; 7492 struct ixgbe_tx_buffer *tx_buffer; 7493 union ixgbe_adv_tx_desc *tx_desc; 7494 struct skb_frag_struct *frag; 7495 dma_addr_t dma; 7496 unsigned int data_len, size; 7497 u32 tx_flags = first->tx_flags; 7498 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 7499 u16 i = tx_ring->next_to_use; 7500 7501 tx_desc = IXGBE_TX_DESC(tx_ring, i); 7502 7503 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 7504 7505 size = skb_headlen(skb); 7506 data_len = skb->data_len; 7507 7508 #ifdef IXGBE_FCOE 7509 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 7510 if (data_len < sizeof(struct fcoe_crc_eof)) { 7511 size -= sizeof(struct fcoe_crc_eof) - data_len; 7512 data_len = 0; 7513 } else { 7514 data_len -= sizeof(struct fcoe_crc_eof); 7515 } 7516 } 7517 7518 #endif 7519 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 7520 7521 tx_buffer = first; 7522 7523 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 7524 if (dma_mapping_error(tx_ring->dev, dma)) 7525 goto dma_error; 7526 7527 /* record length, and DMA address */ 7528 dma_unmap_len_set(tx_buffer, len, size); 7529 dma_unmap_addr_set(tx_buffer, dma, dma); 7530 7531 tx_desc->read.buffer_addr = cpu_to_le64(dma); 7532 7533 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 7534 tx_desc->read.cmd_type_len = 7535 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 7536 7537 i++; 7538 tx_desc++; 7539 if (i == tx_ring->count) { 7540 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 7541 i = 0; 7542 } 7543 tx_desc->read.olinfo_status = 0; 7544 7545 dma += IXGBE_MAX_DATA_PER_TXD; 7546 size -= IXGBE_MAX_DATA_PER_TXD; 7547 7548 tx_desc->read.buffer_addr = cpu_to_le64(dma); 7549 } 7550 7551 if (likely(!data_len)) 7552 break; 7553 7554 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 7555 7556 i++; 7557 tx_desc++; 7558 if (i == tx_ring->count) { 7559 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 7560 i = 0; 7561 } 7562 tx_desc->read.olinfo_status = 0; 7563 7564 #ifdef IXGBE_FCOE 7565 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 7566 #else 7567 size = skb_frag_size(frag); 7568 #endif 7569 data_len -= size; 7570 7571 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 7572 DMA_TO_DEVICE); 7573 7574 tx_buffer = &tx_ring->tx_buffer_info[i]; 7575 } 7576 7577 /* write last descriptor with RS and EOP bits */ 7578 cmd_type |= size | IXGBE_TXD_CMD; 7579 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 7580 7581 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 7582 7583 /* set the timestamp */ 7584 first->time_stamp = jiffies; 7585 7586 /* 7587 * Force memory writes to complete before letting h/w know there 7588 * are new descriptors to fetch. (Only applicable for weak-ordered 7589 * memory model archs, such as IA-64). 7590 * 7591 * We also need this memory barrier to make certain all of the 7592 * status bits have been updated before next_to_watch is written. 7593 */ 7594 wmb(); 7595 7596 /* set next_to_watch value indicating a packet is present */ 7597 first->next_to_watch = tx_desc; 7598 7599 i++; 7600 if (i == tx_ring->count) 7601 i = 0; 7602 7603 tx_ring->next_to_use = i; 7604 7605 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 7606 7607 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 7608 writel(i, tx_ring->tail); 7609 7610 /* we need this if more than one processor can write to our tail 7611 * at a time, it synchronizes IO on IA64/Altix systems 7612 */ 7613 mmiowb(); 7614 } 7615 7616 return; 7617 dma_error: 7618 dev_err(tx_ring->dev, "TX DMA map failed\n"); 7619 7620 /* clear dma mappings for failed tx_buffer_info map */ 7621 for (;;) { 7622 tx_buffer = &tx_ring->tx_buffer_info[i]; 7623 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer); 7624 if (tx_buffer == first) 7625 break; 7626 if (i == 0) 7627 i = tx_ring->count; 7628 i--; 7629 } 7630 7631 tx_ring->next_to_use = i; 7632 } 7633 7634 static void ixgbe_atr(struct ixgbe_ring *ring, 7635 struct ixgbe_tx_buffer *first) 7636 { 7637 struct ixgbe_q_vector *q_vector = ring->q_vector; 7638 union ixgbe_atr_hash_dword input = { .dword = 0 }; 7639 union ixgbe_atr_hash_dword common = { .dword = 0 }; 7640 union { 7641 unsigned char *network; 7642 struct iphdr *ipv4; 7643 struct ipv6hdr *ipv6; 7644 } hdr; 7645 struct tcphdr *th; 7646 unsigned int hlen; 7647 struct sk_buff *skb; 7648 __be16 vlan_id; 7649 int l4_proto; 7650 7651 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 7652 if (!q_vector) 7653 return; 7654 7655 /* do nothing if sampling is disabled */ 7656 if (!ring->atr_sample_rate) 7657 return; 7658 7659 ring->atr_count++; 7660 7661 /* currently only IPv4/IPv6 with TCP is supported */ 7662 if ((first->protocol != htons(ETH_P_IP)) && 7663 (first->protocol != htons(ETH_P_IPV6))) 7664 return; 7665 7666 /* snag network header to get L4 type and address */ 7667 skb = first->skb; 7668 hdr.network = skb_network_header(skb); 7669 if (skb->encapsulation && 7670 first->protocol == htons(ETH_P_IP) && 7671 hdr.ipv4->protocol != IPPROTO_UDP) { 7672 struct ixgbe_adapter *adapter = q_vector->adapter; 7673 7674 /* verify the port is recognized as VXLAN */ 7675 if (adapter->vxlan_port && 7676 udp_hdr(skb)->dest == adapter->vxlan_port) 7677 hdr.network = skb_inner_network_header(skb); 7678 7679 if (adapter->geneve_port && 7680 udp_hdr(skb)->dest == adapter->geneve_port) 7681 hdr.network = skb_inner_network_header(skb); 7682 } 7683 7684 /* Currently only IPv4/IPv6 with TCP is supported */ 7685 switch (hdr.ipv4->version) { 7686 case IPVERSION: 7687 /* access ihl as u8 to avoid unaligned access on ia64 */ 7688 hlen = (hdr.network[0] & 0x0F) << 2; 7689 l4_proto = hdr.ipv4->protocol; 7690 break; 7691 case 6: 7692 hlen = hdr.network - skb->data; 7693 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 7694 hlen -= hdr.network - skb->data; 7695 break; 7696 default: 7697 return; 7698 } 7699 7700 if (l4_proto != IPPROTO_TCP) 7701 return; 7702 7703 th = (struct tcphdr *)(hdr.network + hlen); 7704 7705 /* skip this packet since the socket is closing */ 7706 if (th->fin) 7707 return; 7708 7709 /* sample on all syn packets or once every atr sample count */ 7710 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 7711 return; 7712 7713 /* reset sample count */ 7714 ring->atr_count = 0; 7715 7716 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 7717 7718 /* 7719 * src and dst are inverted, think how the receiver sees them 7720 * 7721 * The input is broken into two sections, a non-compressed section 7722 * containing vm_pool, vlan_id, and flow_type. The rest of the data 7723 * is XORed together and stored in the compressed dword. 7724 */ 7725 input.formatted.vlan_id = vlan_id; 7726 7727 /* 7728 * since src port and flex bytes occupy the same word XOR them together 7729 * and write the value to source port portion of compressed dword 7730 */ 7731 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 7732 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 7733 else 7734 common.port.src ^= th->dest ^ first->protocol; 7735 common.port.dst ^= th->source; 7736 7737 switch (hdr.ipv4->version) { 7738 case IPVERSION: 7739 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 7740 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 7741 break; 7742 case 6: 7743 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 7744 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 7745 hdr.ipv6->saddr.s6_addr32[1] ^ 7746 hdr.ipv6->saddr.s6_addr32[2] ^ 7747 hdr.ipv6->saddr.s6_addr32[3] ^ 7748 hdr.ipv6->daddr.s6_addr32[0] ^ 7749 hdr.ipv6->daddr.s6_addr32[1] ^ 7750 hdr.ipv6->daddr.s6_addr32[2] ^ 7751 hdr.ipv6->daddr.s6_addr32[3]; 7752 break; 7753 default: 7754 break; 7755 } 7756 7757 if (hdr.network != skb_network_header(skb)) 7758 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 7759 7760 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 7761 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 7762 input, common, ring->queue_index); 7763 } 7764 7765 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 7766 void *accel_priv, select_queue_fallback_t fallback) 7767 { 7768 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv; 7769 #ifdef IXGBE_FCOE 7770 struct ixgbe_adapter *adapter; 7771 struct ixgbe_ring_feature *f; 7772 int txq; 7773 #endif 7774 7775 if (fwd_adapter) 7776 return skb->queue_mapping + fwd_adapter->tx_base_queue; 7777 7778 #ifdef IXGBE_FCOE 7779 7780 /* 7781 * only execute the code below if protocol is FCoE 7782 * or FIP and we have FCoE enabled on the adapter 7783 */ 7784 switch (vlan_get_protocol(skb)) { 7785 case htons(ETH_P_FCOE): 7786 case htons(ETH_P_FIP): 7787 adapter = netdev_priv(dev); 7788 7789 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) 7790 break; 7791 default: 7792 return fallback(dev, skb); 7793 } 7794 7795 f = &adapter->ring_feature[RING_F_FCOE]; 7796 7797 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 7798 smp_processor_id(); 7799 7800 while (txq >= f->indices) 7801 txq -= f->indices; 7802 7803 return txq + f->offset; 7804 #else 7805 return fallback(dev, skb); 7806 #endif 7807 } 7808 7809 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 7810 struct ixgbe_adapter *adapter, 7811 struct ixgbe_ring *tx_ring) 7812 { 7813 struct ixgbe_tx_buffer *first; 7814 int tso; 7815 u32 tx_flags = 0; 7816 unsigned short f; 7817 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 7818 __be16 protocol = skb->protocol; 7819 u8 hdr_len = 0; 7820 7821 /* 7822 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 7823 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 7824 * + 2 desc gap to keep tail from touching head, 7825 * + 1 desc for context descriptor, 7826 * otherwise try next time 7827 */ 7828 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 7829 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 7830 7831 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 7832 tx_ring->tx_stats.tx_busy++; 7833 return NETDEV_TX_BUSY; 7834 } 7835 7836 /* record the location of the first descriptor for this packet */ 7837 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 7838 first->skb = skb; 7839 first->bytecount = skb->len; 7840 first->gso_segs = 1; 7841 7842 /* if we have a HW VLAN tag being added default to the HW one */ 7843 if (skb_vlan_tag_present(skb)) { 7844 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 7845 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 7846 /* else if it is a SW VLAN check the next protocol and store the tag */ 7847 } else if (protocol == htons(ETH_P_8021Q)) { 7848 struct vlan_hdr *vhdr, _vhdr; 7849 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 7850 if (!vhdr) 7851 goto out_drop; 7852 7853 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 7854 IXGBE_TX_FLAGS_VLAN_SHIFT; 7855 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 7856 } 7857 protocol = vlan_get_protocol(skb); 7858 7859 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 7860 adapter->ptp_clock && 7861 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 7862 &adapter->state)) { 7863 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 7864 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 7865 7866 /* schedule check for Tx timestamp */ 7867 adapter->ptp_tx_skb = skb_get(skb); 7868 adapter->ptp_tx_start = jiffies; 7869 schedule_work(&adapter->ptp_tx_work); 7870 } 7871 7872 skb_tx_timestamp(skb); 7873 7874 #ifdef CONFIG_PCI_IOV 7875 /* 7876 * Use the l2switch_enable flag - would be false if the DMA 7877 * Tx switch had been disabled. 7878 */ 7879 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 7880 tx_flags |= IXGBE_TX_FLAGS_CC; 7881 7882 #endif 7883 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 7884 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 7885 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 7886 (skb->priority != TC_PRIO_CONTROL))) { 7887 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 7888 tx_flags |= (skb->priority & 0x7) << 7889 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 7890 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 7891 struct vlan_ethhdr *vhdr; 7892 7893 if (skb_cow_head(skb, 0)) 7894 goto out_drop; 7895 vhdr = (struct vlan_ethhdr *)skb->data; 7896 vhdr->h_vlan_TCI = htons(tx_flags >> 7897 IXGBE_TX_FLAGS_VLAN_SHIFT); 7898 } else { 7899 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 7900 } 7901 } 7902 7903 /* record initial flags and protocol */ 7904 first->tx_flags = tx_flags; 7905 first->protocol = protocol; 7906 7907 #ifdef IXGBE_FCOE 7908 /* setup tx offload for FCoE */ 7909 if ((protocol == htons(ETH_P_FCOE)) && 7910 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 7911 tso = ixgbe_fso(tx_ring, first, &hdr_len); 7912 if (tso < 0) 7913 goto out_drop; 7914 7915 goto xmit_fcoe; 7916 } 7917 7918 #endif /* IXGBE_FCOE */ 7919 tso = ixgbe_tso(tx_ring, first, &hdr_len); 7920 if (tso < 0) 7921 goto out_drop; 7922 else if (!tso) 7923 ixgbe_tx_csum(tx_ring, first); 7924 7925 /* add the ATR filter if ATR is on */ 7926 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 7927 ixgbe_atr(tx_ring, first); 7928 7929 #ifdef IXGBE_FCOE 7930 xmit_fcoe: 7931 #endif /* IXGBE_FCOE */ 7932 ixgbe_tx_map(tx_ring, first, hdr_len); 7933 7934 return NETDEV_TX_OK; 7935 7936 out_drop: 7937 dev_kfree_skb_any(first->skb); 7938 first->skb = NULL; 7939 7940 return NETDEV_TX_OK; 7941 } 7942 7943 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 7944 struct net_device *netdev, 7945 struct ixgbe_ring *ring) 7946 { 7947 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7948 struct ixgbe_ring *tx_ring; 7949 7950 /* 7951 * The minimum packet size for olinfo paylen is 17 so pad the skb 7952 * in order to meet this minimum size requirement. 7953 */ 7954 if (skb_put_padto(skb, 17)) 7955 return NETDEV_TX_OK; 7956 7957 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping]; 7958 7959 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 7960 } 7961 7962 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 7963 struct net_device *netdev) 7964 { 7965 return __ixgbe_xmit_frame(skb, netdev, NULL); 7966 } 7967 7968 /** 7969 * ixgbe_set_mac - Change the Ethernet Address of the NIC 7970 * @netdev: network interface device structure 7971 * @p: pointer to an address structure 7972 * 7973 * Returns 0 on success, negative on failure 7974 **/ 7975 static int ixgbe_set_mac(struct net_device *netdev, void *p) 7976 { 7977 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7978 struct ixgbe_hw *hw = &adapter->hw; 7979 struct sockaddr *addr = p; 7980 7981 if (!is_valid_ether_addr(addr->sa_data)) 7982 return -EADDRNOTAVAIL; 7983 7984 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 7985 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 7986 7987 ixgbe_mac_set_default_filter(adapter); 7988 7989 return 0; 7990 } 7991 7992 static int 7993 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 7994 { 7995 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7996 struct ixgbe_hw *hw = &adapter->hw; 7997 u16 value; 7998 int rc; 7999 8000 if (prtad != hw->phy.mdio.prtad) 8001 return -EINVAL; 8002 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 8003 if (!rc) 8004 rc = value; 8005 return rc; 8006 } 8007 8008 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 8009 u16 addr, u16 value) 8010 { 8011 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8012 struct ixgbe_hw *hw = &adapter->hw; 8013 8014 if (prtad != hw->phy.mdio.prtad) 8015 return -EINVAL; 8016 return hw->phy.ops.write_reg(hw, addr, devad, value); 8017 } 8018 8019 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 8020 { 8021 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8022 8023 switch (cmd) { 8024 case SIOCSHWTSTAMP: 8025 return ixgbe_ptp_set_ts_config(adapter, req); 8026 case SIOCGHWTSTAMP: 8027 return ixgbe_ptp_get_ts_config(adapter, req); 8028 default: 8029 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 8030 } 8031 } 8032 8033 /** 8034 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 8035 * netdev->dev_addrs 8036 * @netdev: network interface device structure 8037 * 8038 * Returns non-zero on failure 8039 **/ 8040 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 8041 { 8042 int err = 0; 8043 struct ixgbe_adapter *adapter = netdev_priv(dev); 8044 struct ixgbe_hw *hw = &adapter->hw; 8045 8046 if (is_valid_ether_addr(hw->mac.san_addr)) { 8047 rtnl_lock(); 8048 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 8049 rtnl_unlock(); 8050 8051 /* update SAN MAC vmdq pool selection */ 8052 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 8053 } 8054 return err; 8055 } 8056 8057 /** 8058 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 8059 * netdev->dev_addrs 8060 * @netdev: network interface device structure 8061 * 8062 * Returns non-zero on failure 8063 **/ 8064 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 8065 { 8066 int err = 0; 8067 struct ixgbe_adapter *adapter = netdev_priv(dev); 8068 struct ixgbe_mac_info *mac = &adapter->hw.mac; 8069 8070 if (is_valid_ether_addr(mac->san_addr)) { 8071 rtnl_lock(); 8072 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 8073 rtnl_unlock(); 8074 } 8075 return err; 8076 } 8077 8078 #ifdef CONFIG_NET_POLL_CONTROLLER 8079 /* 8080 * Polling 'interrupt' - used by things like netconsole to send skbs 8081 * without having to re-enable interrupts. It's not called while 8082 * the interrupt routine is executing. 8083 */ 8084 static void ixgbe_netpoll(struct net_device *netdev) 8085 { 8086 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8087 int i; 8088 8089 /* if interface is down do nothing */ 8090 if (test_bit(__IXGBE_DOWN, &adapter->state)) 8091 return; 8092 8093 /* loop through and schedule all active queues */ 8094 for (i = 0; i < adapter->num_q_vectors; i++) 8095 ixgbe_msix_clean_rings(0, adapter->q_vector[i]); 8096 } 8097 8098 #endif 8099 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev, 8100 struct rtnl_link_stats64 *stats) 8101 { 8102 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8103 int i; 8104 8105 rcu_read_lock(); 8106 for (i = 0; i < adapter->num_rx_queues; i++) { 8107 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); 8108 u64 bytes, packets; 8109 unsigned int start; 8110 8111 if (ring) { 8112 do { 8113 start = u64_stats_fetch_begin_irq(&ring->syncp); 8114 packets = ring->stats.packets; 8115 bytes = ring->stats.bytes; 8116 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8117 stats->rx_packets += packets; 8118 stats->rx_bytes += bytes; 8119 } 8120 } 8121 8122 for (i = 0; i < adapter->num_tx_queues; i++) { 8123 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); 8124 u64 bytes, packets; 8125 unsigned int start; 8126 8127 if (ring) { 8128 do { 8129 start = u64_stats_fetch_begin_irq(&ring->syncp); 8130 packets = ring->stats.packets; 8131 bytes = ring->stats.bytes; 8132 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8133 stats->tx_packets += packets; 8134 stats->tx_bytes += bytes; 8135 } 8136 } 8137 rcu_read_unlock(); 8138 /* following stats updated by ixgbe_watchdog_task() */ 8139 stats->multicast = netdev->stats.multicast; 8140 stats->rx_errors = netdev->stats.rx_errors; 8141 stats->rx_length_errors = netdev->stats.rx_length_errors; 8142 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 8143 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 8144 return stats; 8145 } 8146 8147 #ifdef CONFIG_IXGBE_DCB 8148 /** 8149 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 8150 * @adapter: pointer to ixgbe_adapter 8151 * @tc: number of traffic classes currently enabled 8152 * 8153 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 8154 * 802.1Q priority maps to a packet buffer that exists. 8155 */ 8156 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 8157 { 8158 struct ixgbe_hw *hw = &adapter->hw; 8159 u32 reg, rsave; 8160 int i; 8161 8162 /* 82598 have a static priority to TC mapping that can not 8163 * be changed so no validation is needed. 8164 */ 8165 if (hw->mac.type == ixgbe_mac_82598EB) 8166 return; 8167 8168 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 8169 rsave = reg; 8170 8171 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 8172 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 8173 8174 /* If up2tc is out of bounds default to zero */ 8175 if (up2tc > tc) 8176 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 8177 } 8178 8179 if (reg != rsave) 8180 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 8181 8182 return; 8183 } 8184 8185 /** 8186 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 8187 * @adapter: Pointer to adapter struct 8188 * 8189 * Populate the netdev user priority to tc map 8190 */ 8191 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 8192 { 8193 struct net_device *dev = adapter->netdev; 8194 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 8195 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 8196 u8 prio; 8197 8198 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 8199 u8 tc = 0; 8200 8201 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 8202 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 8203 else if (ets) 8204 tc = ets->prio_tc[prio]; 8205 8206 netdev_set_prio_tc_map(dev, prio, tc); 8207 } 8208 } 8209 8210 #endif /* CONFIG_IXGBE_DCB */ 8211 /** 8212 * ixgbe_setup_tc - configure net_device for multiple traffic classes 8213 * 8214 * @netdev: net device to configure 8215 * @tc: number of traffic classes to enable 8216 */ 8217 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 8218 { 8219 struct ixgbe_adapter *adapter = netdev_priv(dev); 8220 struct ixgbe_hw *hw = &adapter->hw; 8221 bool pools; 8222 8223 /* Hardware supports up to 8 traffic classes */ 8224 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 8225 return -EINVAL; 8226 8227 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 8228 return -EINVAL; 8229 8230 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1); 8231 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS) 8232 return -EBUSY; 8233 8234 /* Hardware has to reinitialize queues and interrupts to 8235 * match packet buffer alignment. Unfortunately, the 8236 * hardware is not flexible enough to do this dynamically. 8237 */ 8238 if (netif_running(dev)) 8239 ixgbe_close(dev); 8240 else 8241 ixgbe_reset(adapter); 8242 8243 ixgbe_clear_interrupt_scheme(adapter); 8244 8245 #ifdef CONFIG_IXGBE_DCB 8246 if (tc) { 8247 netdev_set_num_tc(dev, tc); 8248 ixgbe_set_prio_tc_map(adapter); 8249 8250 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 8251 8252 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 8253 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 8254 adapter->hw.fc.requested_mode = ixgbe_fc_none; 8255 } 8256 } else { 8257 netdev_reset_tc(dev); 8258 8259 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 8260 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 8261 8262 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 8263 8264 adapter->temp_dcb_cfg.pfc_mode_enable = false; 8265 adapter->dcb_cfg.pfc_mode_enable = false; 8266 } 8267 8268 ixgbe_validate_rtr(adapter, tc); 8269 8270 #endif /* CONFIG_IXGBE_DCB */ 8271 ixgbe_init_interrupt_scheme(adapter); 8272 8273 if (netif_running(dev)) 8274 return ixgbe_open(dev); 8275 8276 return 0; 8277 } 8278 8279 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, 8280 struct tc_cls_u32_offload *cls) 8281 { 8282 u32 hdl = cls->knode.handle; 8283 u32 uhtid = TC_U32_USERHTID(cls->knode.handle); 8284 u32 loc = cls->knode.handle & 0xfffff; 8285 int err = 0, i, j; 8286 struct ixgbe_jump_table *jump = NULL; 8287 8288 if (loc > IXGBE_MAX_HW_ENTRIES) 8289 return -EINVAL; 8290 8291 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) 8292 return -EINVAL; 8293 8294 /* Clear this filter in the link data it is associated with */ 8295 if (uhtid != 0x800) { 8296 jump = adapter->jump_tables[uhtid]; 8297 if (!jump) 8298 return -EINVAL; 8299 if (!test_bit(loc - 1, jump->child_loc_map)) 8300 return -EINVAL; 8301 clear_bit(loc - 1, jump->child_loc_map); 8302 } 8303 8304 /* Check if the filter being deleted is a link */ 8305 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 8306 jump = adapter->jump_tables[i]; 8307 if (jump && jump->link_hdl == hdl) { 8308 /* Delete filters in the hardware in the child hash 8309 * table associated with this link 8310 */ 8311 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) { 8312 if (!test_bit(j, jump->child_loc_map)) 8313 continue; 8314 spin_lock(&adapter->fdir_perfect_lock); 8315 err = ixgbe_update_ethtool_fdir_entry(adapter, 8316 NULL, 8317 j + 1); 8318 spin_unlock(&adapter->fdir_perfect_lock); 8319 clear_bit(j, jump->child_loc_map); 8320 } 8321 /* Remove resources for this link */ 8322 kfree(jump->input); 8323 kfree(jump->mask); 8324 kfree(jump); 8325 adapter->jump_tables[i] = NULL; 8326 return err; 8327 } 8328 } 8329 8330 spin_lock(&adapter->fdir_perfect_lock); 8331 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); 8332 spin_unlock(&adapter->fdir_perfect_lock); 8333 return err; 8334 } 8335 8336 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, 8337 __be16 protocol, 8338 struct tc_cls_u32_offload *cls) 8339 { 8340 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 8341 8342 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 8343 return -EINVAL; 8344 8345 /* This ixgbe devices do not support hash tables at the moment 8346 * so abort when given hash tables. 8347 */ 8348 if (cls->hnode.divisor > 0) 8349 return -EINVAL; 8350 8351 set_bit(uhtid - 1, &adapter->tables); 8352 return 0; 8353 } 8354 8355 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, 8356 struct tc_cls_u32_offload *cls) 8357 { 8358 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 8359 8360 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 8361 return -EINVAL; 8362 8363 clear_bit(uhtid - 1, &adapter->tables); 8364 return 0; 8365 } 8366 8367 #ifdef CONFIG_NET_CLS_ACT 8368 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, 8369 u8 *queue, u64 *action) 8370 { 8371 unsigned int num_vfs = adapter->num_vfs, vf; 8372 struct net_device *upper; 8373 struct list_head *iter; 8374 8375 /* redirect to a SRIOV VF */ 8376 for (vf = 0; vf < num_vfs; ++vf) { 8377 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); 8378 if (upper->ifindex == ifindex) { 8379 if (adapter->num_rx_pools > 1) 8380 *queue = vf * 2; 8381 else 8382 *queue = vf * adapter->num_rx_queues_per_pool; 8383 8384 *action = vf + 1; 8385 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 8386 return 0; 8387 } 8388 } 8389 8390 /* redirect to a offloaded macvlan netdev */ 8391 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { 8392 if (netif_is_macvlan(upper)) { 8393 struct macvlan_dev *dfwd = netdev_priv(upper); 8394 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; 8395 8396 if (vadapter && vadapter->netdev->ifindex == ifindex) { 8397 *queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; 8398 *action = *queue; 8399 return 0; 8400 } 8401 } 8402 } 8403 8404 return -EINVAL; 8405 } 8406 8407 static int parse_tc_actions(struct ixgbe_adapter *adapter, 8408 struct tcf_exts *exts, u64 *action, u8 *queue) 8409 { 8410 const struct tc_action *a; 8411 LIST_HEAD(actions); 8412 int err; 8413 8414 if (tc_no_actions(exts)) 8415 return -EINVAL; 8416 8417 tcf_exts_to_list(exts, &actions); 8418 list_for_each_entry(a, &actions, list) { 8419 8420 /* Drop action */ 8421 if (is_tcf_gact_shot(a)) { 8422 *action = IXGBE_FDIR_DROP_QUEUE; 8423 *queue = IXGBE_FDIR_DROP_QUEUE; 8424 return 0; 8425 } 8426 8427 /* Redirect to a VF or a offloaded macvlan */ 8428 if (is_tcf_mirred_redirect(a)) { 8429 int ifindex = tcf_mirred_ifindex(a); 8430 8431 err = handle_redirect_action(adapter, ifindex, queue, 8432 action); 8433 if (err == 0) 8434 return err; 8435 } 8436 } 8437 8438 return -EINVAL; 8439 } 8440 #else 8441 static int parse_tc_actions(struct ixgbe_adapter *adapter, 8442 struct tcf_exts *exts, u64 *action, u8 *queue) 8443 { 8444 return -EINVAL; 8445 } 8446 #endif /* CONFIG_NET_CLS_ACT */ 8447 8448 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, 8449 union ixgbe_atr_input *mask, 8450 struct tc_cls_u32_offload *cls, 8451 struct ixgbe_mat_field *field_ptr, 8452 struct ixgbe_nexthdr *nexthdr) 8453 { 8454 int i, j, off; 8455 __be32 val, m; 8456 bool found_entry = false, found_jump_field = false; 8457 8458 for (i = 0; i < cls->knode.sel->nkeys; i++) { 8459 off = cls->knode.sel->keys[i].off; 8460 val = cls->knode.sel->keys[i].val; 8461 m = cls->knode.sel->keys[i].mask; 8462 8463 for (j = 0; field_ptr[j].val; j++) { 8464 if (field_ptr[j].off == off) { 8465 field_ptr[j].val(input, mask, val, m); 8466 input->filter.formatted.flow_type |= 8467 field_ptr[j].type; 8468 found_entry = true; 8469 break; 8470 } 8471 } 8472 if (nexthdr) { 8473 if (nexthdr->off == cls->knode.sel->keys[i].off && 8474 nexthdr->val == cls->knode.sel->keys[i].val && 8475 nexthdr->mask == cls->knode.sel->keys[i].mask) 8476 found_jump_field = true; 8477 else 8478 continue; 8479 } 8480 } 8481 8482 if (nexthdr && !found_jump_field) 8483 return -EINVAL; 8484 8485 if (!found_entry) 8486 return 0; 8487 8488 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 8489 IXGBE_ATR_L4TYPE_MASK; 8490 8491 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 8492 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 8493 8494 return 0; 8495 } 8496 8497 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, 8498 __be16 protocol, 8499 struct tc_cls_u32_offload *cls) 8500 { 8501 u32 loc = cls->knode.handle & 0xfffff; 8502 struct ixgbe_hw *hw = &adapter->hw; 8503 struct ixgbe_mat_field *field_ptr; 8504 struct ixgbe_fdir_filter *input = NULL; 8505 union ixgbe_atr_input *mask = NULL; 8506 struct ixgbe_jump_table *jump = NULL; 8507 int i, err = -EINVAL; 8508 u8 queue; 8509 u32 uhtid, link_uhtid; 8510 8511 uhtid = TC_U32_USERHTID(cls->knode.handle); 8512 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); 8513 8514 /* At the moment cls_u32 jumps to network layer and skips past 8515 * L2 headers. The canonical method to match L2 frames is to use 8516 * negative values. However this is error prone at best but really 8517 * just broken because there is no way to "know" what sort of hdr 8518 * is in front of the network layer. Fix cls_u32 to support L2 8519 * headers when needed. 8520 */ 8521 if (protocol != htons(ETH_P_IP)) 8522 return err; 8523 8524 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { 8525 e_err(drv, "Location out of range\n"); 8526 return err; 8527 } 8528 8529 /* cls u32 is a graph starting at root node 0x800. The driver tracks 8530 * links and also the fields used to advance the parser across each 8531 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map 8532 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h 8533 * To add support for new nodes update ixgbe_model.h parse structures 8534 * this function _should_ be generic try not to hardcode values here. 8535 */ 8536 if (uhtid == 0x800) { 8537 field_ptr = (adapter->jump_tables[0])->mat; 8538 } else { 8539 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 8540 return err; 8541 if (!adapter->jump_tables[uhtid]) 8542 return err; 8543 field_ptr = (adapter->jump_tables[uhtid])->mat; 8544 } 8545 8546 if (!field_ptr) 8547 return err; 8548 8549 /* At this point we know the field_ptr is valid and need to either 8550 * build cls_u32 link or attach filter. Because adding a link to 8551 * a handle that does not exist is invalid and the same for adding 8552 * rules to handles that don't exist. 8553 */ 8554 8555 if (link_uhtid) { 8556 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; 8557 8558 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) 8559 return err; 8560 8561 if (!test_bit(link_uhtid - 1, &adapter->tables)) 8562 return err; 8563 8564 /* Multiple filters as links to the same hash table are not 8565 * supported. To add a new filter with the same next header 8566 * but different match/jump conditions, create a new hash table 8567 * and link to it. 8568 */ 8569 if (adapter->jump_tables[link_uhtid] && 8570 (adapter->jump_tables[link_uhtid])->link_hdl) { 8571 e_err(drv, "Link filter exists for link: %x\n", 8572 link_uhtid); 8573 return err; 8574 } 8575 8576 for (i = 0; nexthdr[i].jump; i++) { 8577 if (nexthdr[i].o != cls->knode.sel->offoff || 8578 nexthdr[i].s != cls->knode.sel->offshift || 8579 nexthdr[i].m != cls->knode.sel->offmask) 8580 return err; 8581 8582 jump = kzalloc(sizeof(*jump), GFP_KERNEL); 8583 if (!jump) 8584 return -ENOMEM; 8585 input = kzalloc(sizeof(*input), GFP_KERNEL); 8586 if (!input) { 8587 err = -ENOMEM; 8588 goto free_jump; 8589 } 8590 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 8591 if (!mask) { 8592 err = -ENOMEM; 8593 goto free_input; 8594 } 8595 jump->input = input; 8596 jump->mask = mask; 8597 jump->link_hdl = cls->knode.handle; 8598 8599 err = ixgbe_clsu32_build_input(input, mask, cls, 8600 field_ptr, &nexthdr[i]); 8601 if (!err) { 8602 jump->mat = nexthdr[i].jump; 8603 adapter->jump_tables[link_uhtid] = jump; 8604 break; 8605 } 8606 } 8607 return 0; 8608 } 8609 8610 input = kzalloc(sizeof(*input), GFP_KERNEL); 8611 if (!input) 8612 return -ENOMEM; 8613 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 8614 if (!mask) { 8615 err = -ENOMEM; 8616 goto free_input; 8617 } 8618 8619 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { 8620 if ((adapter->jump_tables[uhtid])->input) 8621 memcpy(input, (adapter->jump_tables[uhtid])->input, 8622 sizeof(*input)); 8623 if ((adapter->jump_tables[uhtid])->mask) 8624 memcpy(mask, (adapter->jump_tables[uhtid])->mask, 8625 sizeof(*mask)); 8626 8627 /* Lookup in all child hash tables if this location is already 8628 * filled with a filter 8629 */ 8630 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 8631 struct ixgbe_jump_table *link = adapter->jump_tables[i]; 8632 8633 if (link && (test_bit(loc - 1, link->child_loc_map))) { 8634 e_err(drv, "Filter exists in location: %x\n", 8635 loc); 8636 err = -EINVAL; 8637 goto err_out; 8638 } 8639 } 8640 } 8641 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); 8642 if (err) 8643 goto err_out; 8644 8645 err = parse_tc_actions(adapter, cls->knode.exts, &input->action, 8646 &queue); 8647 if (err < 0) 8648 goto err_out; 8649 8650 input->sw_idx = loc; 8651 8652 spin_lock(&adapter->fdir_perfect_lock); 8653 8654 if (hlist_empty(&adapter->fdir_filter_list)) { 8655 memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); 8656 err = ixgbe_fdir_set_input_mask_82599(hw, mask); 8657 if (err) 8658 goto err_out_w_lock; 8659 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { 8660 err = -EINVAL; 8661 goto err_out_w_lock; 8662 } 8663 8664 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); 8665 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, 8666 input->sw_idx, queue); 8667 if (!err) 8668 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 8669 spin_unlock(&adapter->fdir_perfect_lock); 8670 8671 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) 8672 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map); 8673 8674 kfree(mask); 8675 return err; 8676 err_out_w_lock: 8677 spin_unlock(&adapter->fdir_perfect_lock); 8678 err_out: 8679 kfree(mask); 8680 free_input: 8681 kfree(input); 8682 free_jump: 8683 kfree(jump); 8684 return err; 8685 } 8686 8687 static int __ixgbe_setup_tc(struct net_device *dev, u32 handle, __be16 proto, 8688 struct tc_to_netdev *tc) 8689 { 8690 struct ixgbe_adapter *adapter = netdev_priv(dev); 8691 8692 if (TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS) && 8693 tc->type == TC_SETUP_CLSU32) { 8694 switch (tc->cls_u32->command) { 8695 case TC_CLSU32_NEW_KNODE: 8696 case TC_CLSU32_REPLACE_KNODE: 8697 return ixgbe_configure_clsu32(adapter, 8698 proto, tc->cls_u32); 8699 case TC_CLSU32_DELETE_KNODE: 8700 return ixgbe_delete_clsu32(adapter, tc->cls_u32); 8701 case TC_CLSU32_NEW_HNODE: 8702 case TC_CLSU32_REPLACE_HNODE: 8703 return ixgbe_configure_clsu32_add_hnode(adapter, proto, 8704 tc->cls_u32); 8705 case TC_CLSU32_DELETE_HNODE: 8706 return ixgbe_configure_clsu32_del_hnode(adapter, 8707 tc->cls_u32); 8708 default: 8709 return -EINVAL; 8710 } 8711 } 8712 8713 if (tc->type != TC_SETUP_MQPRIO) 8714 return -EINVAL; 8715 8716 return ixgbe_setup_tc(dev, tc->tc); 8717 } 8718 8719 #ifdef CONFIG_PCI_IOV 8720 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 8721 { 8722 struct net_device *netdev = adapter->netdev; 8723 8724 rtnl_lock(); 8725 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev)); 8726 rtnl_unlock(); 8727 } 8728 8729 #endif 8730 void ixgbe_do_reset(struct net_device *netdev) 8731 { 8732 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8733 8734 if (netif_running(netdev)) 8735 ixgbe_reinit_locked(adapter); 8736 else 8737 ixgbe_reset(adapter); 8738 } 8739 8740 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 8741 netdev_features_t features) 8742 { 8743 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8744 8745 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 8746 if (!(features & NETIF_F_RXCSUM)) 8747 features &= ~NETIF_F_LRO; 8748 8749 /* Turn off LRO if not RSC capable */ 8750 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 8751 features &= ~NETIF_F_LRO; 8752 8753 return features; 8754 } 8755 8756 static int ixgbe_set_features(struct net_device *netdev, 8757 netdev_features_t features) 8758 { 8759 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8760 netdev_features_t changed = netdev->features ^ features; 8761 bool need_reset = false; 8762 8763 /* Make sure RSC matches LRO, reset if change */ 8764 if (!(features & NETIF_F_LRO)) { 8765 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 8766 need_reset = true; 8767 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 8768 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 8769 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 8770 if (adapter->rx_itr_setting == 1 || 8771 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 8772 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 8773 need_reset = true; 8774 } else if ((changed ^ features) & NETIF_F_LRO) { 8775 e_info(probe, "rx-usecs set too low, " 8776 "disabling RSC\n"); 8777 } 8778 } 8779 8780 /* 8781 * Check if Flow Director n-tuple support or hw_tc support was 8782 * enabled or disabled. If the state changed, we need to reset. 8783 */ 8784 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { 8785 /* turn off ATR, enable perfect filters and reset */ 8786 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 8787 need_reset = true; 8788 8789 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 8790 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 8791 } else { 8792 /* turn off perfect filters, enable ATR and reset */ 8793 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 8794 need_reset = true; 8795 8796 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 8797 8798 /* We cannot enable ATR if SR-IOV is enabled */ 8799 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || 8800 /* We cannot enable ATR if we have 2 or more tcs */ 8801 (netdev_get_num_tc(netdev) > 1) || 8802 /* We cannot enable ATR if RSS is disabled */ 8803 (adapter->ring_feature[RING_F_RSS].limit <= 1) || 8804 /* A sample rate of 0 indicates ATR disabled */ 8805 (!adapter->atr_sample_rate)) 8806 ; /* do nothing not supported */ 8807 else /* otherwise supported and set the flag */ 8808 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 8809 } 8810 8811 if (changed & NETIF_F_RXALL) 8812 need_reset = true; 8813 8814 netdev->features = features; 8815 8816 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) { 8817 if (features & NETIF_F_RXCSUM) { 8818 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 8819 } else { 8820 u32 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 8821 8822 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 8823 } 8824 } 8825 8826 if ((adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) { 8827 if (features & NETIF_F_RXCSUM) { 8828 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 8829 } else { 8830 u32 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 8831 8832 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 8833 } 8834 } 8835 8836 if (need_reset) 8837 ixgbe_do_reset(netdev); 8838 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | 8839 NETIF_F_HW_VLAN_CTAG_FILTER)) 8840 ixgbe_set_rx_mode(netdev); 8841 8842 return 0; 8843 } 8844 8845 /** 8846 * ixgbe_add_udp_tunnel_port - Get notifications about adding UDP tunnel ports 8847 * @dev: The port's netdev 8848 * @ti: Tunnel endpoint information 8849 **/ 8850 static void ixgbe_add_udp_tunnel_port(struct net_device *dev, 8851 struct udp_tunnel_info *ti) 8852 { 8853 struct ixgbe_adapter *adapter = netdev_priv(dev); 8854 struct ixgbe_hw *hw = &adapter->hw; 8855 __be16 port = ti->port; 8856 u32 port_shift = 0; 8857 u32 reg; 8858 8859 if (ti->sa_family != AF_INET) 8860 return; 8861 8862 switch (ti->type) { 8863 case UDP_TUNNEL_TYPE_VXLAN: 8864 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 8865 return; 8866 8867 if (adapter->vxlan_port == port) 8868 return; 8869 8870 if (adapter->vxlan_port) { 8871 netdev_info(dev, 8872 "VXLAN port %d set, not adding port %d\n", 8873 ntohs(adapter->vxlan_port), 8874 ntohs(port)); 8875 return; 8876 } 8877 8878 adapter->vxlan_port = port; 8879 break; 8880 case UDP_TUNNEL_TYPE_GENEVE: 8881 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 8882 return; 8883 8884 if (adapter->geneve_port == port) 8885 return; 8886 8887 if (adapter->geneve_port) { 8888 netdev_info(dev, 8889 "GENEVE port %d set, not adding port %d\n", 8890 ntohs(adapter->geneve_port), 8891 ntohs(port)); 8892 return; 8893 } 8894 8895 port_shift = IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT; 8896 adapter->geneve_port = port; 8897 break; 8898 default: 8899 return; 8900 } 8901 8902 reg = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) | ntohs(port) << port_shift; 8903 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, reg); 8904 } 8905 8906 /** 8907 * ixgbe_del_udp_tunnel_port - Get notifications about removing UDP tunnel ports 8908 * @dev: The port's netdev 8909 * @ti: Tunnel endpoint information 8910 **/ 8911 static void ixgbe_del_udp_tunnel_port(struct net_device *dev, 8912 struct udp_tunnel_info *ti) 8913 { 8914 struct ixgbe_adapter *adapter = netdev_priv(dev); 8915 u32 port_mask; 8916 8917 if (ti->type != UDP_TUNNEL_TYPE_VXLAN && 8918 ti->type != UDP_TUNNEL_TYPE_GENEVE) 8919 return; 8920 8921 if (ti->sa_family != AF_INET) 8922 return; 8923 8924 switch (ti->type) { 8925 case UDP_TUNNEL_TYPE_VXLAN: 8926 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 8927 return; 8928 8929 if (adapter->vxlan_port != ti->port) { 8930 netdev_info(dev, "VXLAN port %d not found\n", 8931 ntohs(ti->port)); 8932 return; 8933 } 8934 8935 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 8936 break; 8937 case UDP_TUNNEL_TYPE_GENEVE: 8938 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 8939 return; 8940 8941 if (adapter->geneve_port != ti->port) { 8942 netdev_info(dev, "GENEVE port %d not found\n", 8943 ntohs(ti->port)); 8944 return; 8945 } 8946 8947 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 8948 break; 8949 default: 8950 return; 8951 } 8952 8953 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 8954 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 8955 } 8956 8957 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 8958 struct net_device *dev, 8959 const unsigned char *addr, u16 vid, 8960 u16 flags) 8961 { 8962 /* guarantee we can provide a unique filter for the unicast address */ 8963 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 8964 struct ixgbe_adapter *adapter = netdev_priv(dev); 8965 u16 pool = VMDQ_P(0); 8966 8967 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) 8968 return -ENOMEM; 8969 } 8970 8971 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 8972 } 8973 8974 /** 8975 * ixgbe_configure_bridge_mode - set various bridge modes 8976 * @adapter - the private structure 8977 * @mode - requested bridge mode 8978 * 8979 * Configure some settings require for various bridge modes. 8980 **/ 8981 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 8982 __u16 mode) 8983 { 8984 struct ixgbe_hw *hw = &adapter->hw; 8985 unsigned int p, num_pools; 8986 u32 vmdctl; 8987 8988 switch (mode) { 8989 case BRIDGE_MODE_VEPA: 8990 /* disable Tx loopback, rely on switch hairpin mode */ 8991 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 8992 8993 /* must enable Rx switching replication to allow multicast 8994 * packet reception on all VFs, and to enable source address 8995 * pruning. 8996 */ 8997 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 8998 vmdctl |= IXGBE_VT_CTL_REPLEN; 8999 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9000 9001 /* enable Rx source address pruning. Note, this requires 9002 * replication to be enabled or else it does nothing. 9003 */ 9004 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9005 for (p = 0; p < num_pools; p++) { 9006 if (hw->mac.ops.set_source_address_pruning) 9007 hw->mac.ops.set_source_address_pruning(hw, 9008 true, 9009 p); 9010 } 9011 break; 9012 case BRIDGE_MODE_VEB: 9013 /* enable Tx loopback for internal VF/PF communication */ 9014 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 9015 IXGBE_PFDTXGSWC_VT_LBEN); 9016 9017 /* disable Rx switching replication unless we have SR-IOV 9018 * virtual functions 9019 */ 9020 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9021 if (!adapter->num_vfs) 9022 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 9023 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9024 9025 /* disable Rx source address pruning, since we don't expect to 9026 * be receiving external loopback of our transmitted frames. 9027 */ 9028 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9029 for (p = 0; p < num_pools; p++) { 9030 if (hw->mac.ops.set_source_address_pruning) 9031 hw->mac.ops.set_source_address_pruning(hw, 9032 false, 9033 p); 9034 } 9035 break; 9036 default: 9037 return -EINVAL; 9038 } 9039 9040 adapter->bridge_mode = mode; 9041 9042 e_info(drv, "enabling bridge mode: %s\n", 9043 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 9044 9045 return 0; 9046 } 9047 9048 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 9049 struct nlmsghdr *nlh, u16 flags) 9050 { 9051 struct ixgbe_adapter *adapter = netdev_priv(dev); 9052 struct nlattr *attr, *br_spec; 9053 int rem; 9054 9055 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9056 return -EOPNOTSUPP; 9057 9058 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 9059 if (!br_spec) 9060 return -EINVAL; 9061 9062 nla_for_each_nested(attr, br_spec, rem) { 9063 int status; 9064 __u16 mode; 9065 9066 if (nla_type(attr) != IFLA_BRIDGE_MODE) 9067 continue; 9068 9069 if (nla_len(attr) < sizeof(mode)) 9070 return -EINVAL; 9071 9072 mode = nla_get_u16(attr); 9073 status = ixgbe_configure_bridge_mode(adapter, mode); 9074 if (status) 9075 return status; 9076 9077 break; 9078 } 9079 9080 return 0; 9081 } 9082 9083 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 9084 struct net_device *dev, 9085 u32 filter_mask, int nlflags) 9086 { 9087 struct ixgbe_adapter *adapter = netdev_priv(dev); 9088 9089 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9090 return 0; 9091 9092 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 9093 adapter->bridge_mode, 0, 0, nlflags, 9094 filter_mask, NULL); 9095 } 9096 9097 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 9098 { 9099 struct ixgbe_fwd_adapter *fwd_adapter = NULL; 9100 struct ixgbe_adapter *adapter = netdev_priv(pdev); 9101 int used_pools = adapter->num_vfs + adapter->num_rx_pools; 9102 unsigned int limit; 9103 int pool, err; 9104 9105 /* Hardware has a limited number of available pools. Each VF, and the 9106 * PF require a pool. Check to ensure we don't attempt to use more 9107 * then the available number of pools. 9108 */ 9109 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 9110 return ERR_PTR(-EINVAL); 9111 9112 #ifdef CONFIG_RPS 9113 if (vdev->num_rx_queues != vdev->num_tx_queues) { 9114 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n", 9115 vdev->name); 9116 return ERR_PTR(-EINVAL); 9117 } 9118 #endif 9119 /* Check for hardware restriction on number of rx/tx queues */ 9120 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES || 9121 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) { 9122 netdev_info(pdev, 9123 "%s: Supports RX/TX Queue counts 1,2, and 4\n", 9124 pdev->name); 9125 return ERR_PTR(-EINVAL); 9126 } 9127 9128 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 9129 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) || 9130 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS)) 9131 return ERR_PTR(-EBUSY); 9132 9133 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL); 9134 if (!fwd_adapter) 9135 return ERR_PTR(-ENOMEM); 9136 9137 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32); 9138 adapter->num_rx_pools++; 9139 set_bit(pool, &adapter->fwd_bitmask); 9140 limit = find_last_bit(&adapter->fwd_bitmask, 32); 9141 9142 /* Enable VMDq flag so device will be set in VM mode */ 9143 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED; 9144 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 9145 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues; 9146 9147 /* Force reinit of ring allocation with VMDQ enabled */ 9148 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); 9149 if (err) 9150 goto fwd_add_err; 9151 fwd_adapter->pool = pool; 9152 fwd_adapter->real_adapter = adapter; 9153 err = ixgbe_fwd_ring_up(vdev, fwd_adapter); 9154 if (err) 9155 goto fwd_add_err; 9156 netif_tx_start_all_queues(vdev); 9157 return fwd_adapter; 9158 fwd_add_err: 9159 /* unwind counter and free adapter struct */ 9160 netdev_info(pdev, 9161 "%s: dfwd hardware acceleration failed\n", vdev->name); 9162 clear_bit(pool, &adapter->fwd_bitmask); 9163 adapter->num_rx_pools--; 9164 kfree(fwd_adapter); 9165 return ERR_PTR(err); 9166 } 9167 9168 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 9169 { 9170 struct ixgbe_fwd_adapter *fwd_adapter = priv; 9171 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter; 9172 unsigned int limit; 9173 9174 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask); 9175 adapter->num_rx_pools--; 9176 9177 limit = find_last_bit(&adapter->fwd_bitmask, 32); 9178 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 9179 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter); 9180 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); 9181 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", 9182 fwd_adapter->pool, adapter->num_rx_pools, 9183 fwd_adapter->rx_base_queue, 9184 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool, 9185 adapter->fwd_bitmask); 9186 kfree(fwd_adapter); 9187 } 9188 9189 #define IXGBE_MAX_MAC_HDR_LEN 127 9190 #define IXGBE_MAX_NETWORK_HDR_LEN 511 9191 9192 static netdev_features_t 9193 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 9194 netdev_features_t features) 9195 { 9196 unsigned int network_hdr_len, mac_hdr_len; 9197 9198 /* Make certain the headers can be described by a context descriptor */ 9199 mac_hdr_len = skb_network_header(skb) - skb->data; 9200 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) 9201 return features & ~(NETIF_F_HW_CSUM | 9202 NETIF_F_SCTP_CRC | 9203 NETIF_F_HW_VLAN_CTAG_TX | 9204 NETIF_F_TSO | 9205 NETIF_F_TSO6); 9206 9207 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 9208 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) 9209 return features & ~(NETIF_F_HW_CSUM | 9210 NETIF_F_SCTP_CRC | 9211 NETIF_F_TSO | 9212 NETIF_F_TSO6); 9213 9214 /* We can only support IPV4 TSO in tunnels if we can mangle the 9215 * inner IP ID field, so strip TSO if MANGLEID is not supported. 9216 */ 9217 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 9218 features &= ~NETIF_F_TSO; 9219 9220 return features; 9221 } 9222 9223 static const struct net_device_ops ixgbe_netdev_ops = { 9224 .ndo_open = ixgbe_open, 9225 .ndo_stop = ixgbe_close, 9226 .ndo_start_xmit = ixgbe_xmit_frame, 9227 .ndo_select_queue = ixgbe_select_queue, 9228 .ndo_set_rx_mode = ixgbe_set_rx_mode, 9229 .ndo_validate_addr = eth_validate_addr, 9230 .ndo_set_mac_address = ixgbe_set_mac, 9231 .ndo_change_mtu = ixgbe_change_mtu, 9232 .ndo_tx_timeout = ixgbe_tx_timeout, 9233 .ndo_set_tx_maxrate = ixgbe_tx_maxrate, 9234 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 9235 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 9236 .ndo_do_ioctl = ixgbe_ioctl, 9237 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 9238 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 9239 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 9240 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 9241 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 9242 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, 9243 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 9244 .ndo_get_stats64 = ixgbe_get_stats64, 9245 .ndo_setup_tc = __ixgbe_setup_tc, 9246 #ifdef CONFIG_NET_POLL_CONTROLLER 9247 .ndo_poll_controller = ixgbe_netpoll, 9248 #endif 9249 #ifdef CONFIG_NET_RX_BUSY_POLL 9250 .ndo_busy_poll = ixgbe_low_latency_recv, 9251 #endif 9252 #ifdef IXGBE_FCOE 9253 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 9254 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 9255 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 9256 .ndo_fcoe_enable = ixgbe_fcoe_enable, 9257 .ndo_fcoe_disable = ixgbe_fcoe_disable, 9258 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 9259 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 9260 #endif /* IXGBE_FCOE */ 9261 .ndo_set_features = ixgbe_set_features, 9262 .ndo_fix_features = ixgbe_fix_features, 9263 .ndo_fdb_add = ixgbe_ndo_fdb_add, 9264 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 9265 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 9266 .ndo_dfwd_add_station = ixgbe_fwd_add, 9267 .ndo_dfwd_del_station = ixgbe_fwd_del, 9268 .ndo_udp_tunnel_add = ixgbe_add_udp_tunnel_port, 9269 .ndo_udp_tunnel_del = ixgbe_del_udp_tunnel_port, 9270 .ndo_features_check = ixgbe_features_check, 9271 }; 9272 9273 /** 9274 * ixgbe_enumerate_functions - Get the number of ports this device has 9275 * @adapter: adapter structure 9276 * 9277 * This function enumerates the phsyical functions co-located on a single slot, 9278 * in order to determine how many ports a device has. This is most useful in 9279 * determining the required GT/s of PCIe bandwidth necessary for optimal 9280 * performance. 9281 **/ 9282 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 9283 { 9284 struct pci_dev *entry, *pdev = adapter->pdev; 9285 int physfns = 0; 9286 9287 /* Some cards can not use the generic count PCIe functions method, 9288 * because they are behind a parent switch, so we hardcode these with 9289 * the correct number of functions. 9290 */ 9291 if (ixgbe_pcie_from_parent(&adapter->hw)) 9292 physfns = 4; 9293 9294 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 9295 /* don't count virtual functions */ 9296 if (entry->is_virtfn) 9297 continue; 9298 9299 /* When the devices on the bus don't all match our device ID, 9300 * we can't reliably determine the correct number of 9301 * functions. This can occur if a function has been direct 9302 * attached to a virtual machine using VT-d, for example. In 9303 * this case, simply return -1 to indicate this. 9304 */ 9305 if ((entry->vendor != pdev->vendor) || 9306 (entry->device != pdev->device)) 9307 return -1; 9308 9309 physfns++; 9310 } 9311 9312 return physfns; 9313 } 9314 9315 /** 9316 * ixgbe_wol_supported - Check whether device supports WoL 9317 * @adapter: the adapter private structure 9318 * @device_id: the device ID 9319 * @subdev_id: the subsystem device ID 9320 * 9321 * This function is used by probe and ethtool to determine 9322 * which devices have WoL support 9323 * 9324 **/ 9325 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 9326 u16 subdevice_id) 9327 { 9328 struct ixgbe_hw *hw = &adapter->hw; 9329 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 9330 9331 /* WOL not supported on 82598 */ 9332 if (hw->mac.type == ixgbe_mac_82598EB) 9333 return false; 9334 9335 /* check eeprom to see if WOL is enabled for X540 and newer */ 9336 if (hw->mac.type >= ixgbe_mac_X540) { 9337 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 9338 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 9339 (hw->bus.func == 0))) 9340 return true; 9341 } 9342 9343 /* WOL is determined based on device IDs for 82599 MACs */ 9344 switch (device_id) { 9345 case IXGBE_DEV_ID_82599_SFP: 9346 /* Only these subdevices could supports WOL */ 9347 switch (subdevice_id) { 9348 case IXGBE_SUBDEV_ID_82599_560FLR: 9349 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: 9350 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 9351 case IXGBE_SUBDEV_ID_82599_SFP_2OCP: 9352 /* only support first port */ 9353 if (hw->bus.func != 0) 9354 break; 9355 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 9356 case IXGBE_SUBDEV_ID_82599_SFP: 9357 case IXGBE_SUBDEV_ID_82599_RNDC: 9358 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 9359 case IXGBE_SUBDEV_ID_82599_SFP_1OCP: 9360 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: 9361 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: 9362 return true; 9363 } 9364 break; 9365 case IXGBE_DEV_ID_82599EN_SFP: 9366 /* Only these subdevices support WOL */ 9367 switch (subdevice_id) { 9368 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 9369 return true; 9370 } 9371 break; 9372 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 9373 /* All except this subdevice support WOL */ 9374 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 9375 return true; 9376 break; 9377 case IXGBE_DEV_ID_82599_KX4: 9378 return true; 9379 default: 9380 break; 9381 } 9382 9383 return false; 9384 } 9385 9386 /** 9387 * ixgbe_probe - Device Initialization Routine 9388 * @pdev: PCI device information struct 9389 * @ent: entry in ixgbe_pci_tbl 9390 * 9391 * Returns 0 on success, negative on failure 9392 * 9393 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 9394 * The OS initialization, configuring of the adapter private structure, 9395 * and a hardware reset occur. 9396 **/ 9397 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 9398 { 9399 struct net_device *netdev; 9400 struct ixgbe_adapter *adapter = NULL; 9401 struct ixgbe_hw *hw; 9402 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 9403 int i, err, pci_using_dac, expected_gts; 9404 unsigned int indices = MAX_TX_QUEUES; 9405 u8 part_str[IXGBE_PBANUM_LENGTH]; 9406 bool disable_dev = false; 9407 #ifdef IXGBE_FCOE 9408 u16 device_caps; 9409 #endif 9410 u32 eec; 9411 9412 /* Catch broken hardware that put the wrong VF device ID in 9413 * the PCIe SR-IOV capability. 9414 */ 9415 if (pdev->is_virtfn) { 9416 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 9417 pci_name(pdev), pdev->vendor, pdev->device); 9418 return -EINVAL; 9419 } 9420 9421 err = pci_enable_device_mem(pdev); 9422 if (err) 9423 return err; 9424 9425 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 9426 pci_using_dac = 1; 9427 } else { 9428 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 9429 if (err) { 9430 dev_err(&pdev->dev, 9431 "No usable DMA configuration, aborting\n"); 9432 goto err_dma; 9433 } 9434 pci_using_dac = 0; 9435 } 9436 9437 err = pci_request_mem_regions(pdev, ixgbe_driver_name); 9438 if (err) { 9439 dev_err(&pdev->dev, 9440 "pci_request_selected_regions failed 0x%x\n", err); 9441 goto err_pci_reg; 9442 } 9443 9444 pci_enable_pcie_error_reporting(pdev); 9445 9446 pci_set_master(pdev); 9447 pci_save_state(pdev); 9448 9449 if (ii->mac == ixgbe_mac_82598EB) { 9450 #ifdef CONFIG_IXGBE_DCB 9451 /* 8 TC w/ 4 queues per TC */ 9452 indices = 4 * MAX_TRAFFIC_CLASS; 9453 #else 9454 indices = IXGBE_MAX_RSS_INDICES; 9455 #endif 9456 } 9457 9458 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 9459 if (!netdev) { 9460 err = -ENOMEM; 9461 goto err_alloc_etherdev; 9462 } 9463 9464 SET_NETDEV_DEV(netdev, &pdev->dev); 9465 9466 adapter = netdev_priv(netdev); 9467 9468 adapter->netdev = netdev; 9469 adapter->pdev = pdev; 9470 hw = &adapter->hw; 9471 hw->back = adapter; 9472 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 9473 9474 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 9475 pci_resource_len(pdev, 0)); 9476 adapter->io_addr = hw->hw_addr; 9477 if (!hw->hw_addr) { 9478 err = -EIO; 9479 goto err_ioremap; 9480 } 9481 9482 netdev->netdev_ops = &ixgbe_netdev_ops; 9483 ixgbe_set_ethtool_ops(netdev); 9484 netdev->watchdog_timeo = 5 * HZ; 9485 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 9486 9487 /* Setup hw api */ 9488 hw->mac.ops = *ii->mac_ops; 9489 hw->mac.type = ii->mac; 9490 hw->mvals = ii->mvals; 9491 9492 /* EEPROM */ 9493 hw->eeprom.ops = *ii->eeprom_ops; 9494 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 9495 if (ixgbe_removed(hw->hw_addr)) { 9496 err = -EIO; 9497 goto err_ioremap; 9498 } 9499 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 9500 if (!(eec & BIT(8))) 9501 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 9502 9503 /* PHY */ 9504 hw->phy.ops = *ii->phy_ops; 9505 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 9506 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 9507 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 9508 hw->phy.mdio.mmds = 0; 9509 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 9510 hw->phy.mdio.dev = netdev; 9511 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 9512 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 9513 9514 ii->get_invariants(hw); 9515 9516 /* setup the private structure */ 9517 err = ixgbe_sw_init(adapter); 9518 if (err) 9519 goto err_sw_init; 9520 9521 /* Make sure the SWFW semaphore is in a valid state */ 9522 if (hw->mac.ops.init_swfw_sync) 9523 hw->mac.ops.init_swfw_sync(hw); 9524 9525 /* Make it possible the adapter to be woken up via WOL */ 9526 switch (adapter->hw.mac.type) { 9527 case ixgbe_mac_82599EB: 9528 case ixgbe_mac_X540: 9529 case ixgbe_mac_X550: 9530 case ixgbe_mac_X550EM_x: 9531 case ixgbe_mac_x550em_a: 9532 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 9533 break; 9534 default: 9535 break; 9536 } 9537 9538 /* 9539 * If there is a fan on this device and it has failed log the 9540 * failure. 9541 */ 9542 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 9543 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 9544 if (esdp & IXGBE_ESDP_SDP1) 9545 e_crit(probe, "Fan has stopped, replace the adapter\n"); 9546 } 9547 9548 if (allow_unsupported_sfp) 9549 hw->allow_unsupported_sfp = allow_unsupported_sfp; 9550 9551 /* reset_hw fills in the perm_addr as well */ 9552 hw->phy.reset_if_overtemp = true; 9553 err = hw->mac.ops.reset_hw(hw); 9554 hw->phy.reset_if_overtemp = false; 9555 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 9556 err = 0; 9557 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 9558 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 9559 e_dev_err("Reload the driver after installing a supported module.\n"); 9560 goto err_sw_init; 9561 } else if (err) { 9562 e_dev_err("HW Init failed: %d\n", err); 9563 goto err_sw_init; 9564 } 9565 9566 #ifdef CONFIG_PCI_IOV 9567 /* SR-IOV not supported on the 82598 */ 9568 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 9569 goto skip_sriov; 9570 /* Mailbox */ 9571 ixgbe_init_mbx_params_pf(hw); 9572 hw->mbx.ops = ii->mbx_ops; 9573 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 9574 ixgbe_enable_sriov(adapter); 9575 skip_sriov: 9576 9577 #endif 9578 netdev->features = NETIF_F_SG | 9579 NETIF_F_TSO | 9580 NETIF_F_TSO6 | 9581 NETIF_F_RXHASH | 9582 NETIF_F_RXCSUM | 9583 NETIF_F_HW_CSUM; 9584 9585 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 9586 NETIF_F_GSO_GRE_CSUM | \ 9587 NETIF_F_GSO_IPXIP4 | \ 9588 NETIF_F_GSO_IPXIP6 | \ 9589 NETIF_F_GSO_UDP_TUNNEL | \ 9590 NETIF_F_GSO_UDP_TUNNEL_CSUM) 9591 9592 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; 9593 netdev->features |= NETIF_F_GSO_PARTIAL | 9594 IXGBE_GSO_PARTIAL_FEATURES; 9595 9596 if (hw->mac.type >= ixgbe_mac_82599EB) 9597 netdev->features |= NETIF_F_SCTP_CRC; 9598 9599 /* copy netdev features into list of user selectable features */ 9600 netdev->hw_features |= netdev->features | 9601 NETIF_F_HW_VLAN_CTAG_FILTER | 9602 NETIF_F_HW_VLAN_CTAG_RX | 9603 NETIF_F_HW_VLAN_CTAG_TX | 9604 NETIF_F_RXALL | 9605 NETIF_F_HW_L2FW_DOFFLOAD; 9606 9607 if (hw->mac.type >= ixgbe_mac_82599EB) 9608 netdev->hw_features |= NETIF_F_NTUPLE | 9609 NETIF_F_HW_TC; 9610 9611 if (pci_using_dac) 9612 netdev->features |= NETIF_F_HIGHDMA; 9613 9614 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 9615 netdev->hw_enc_features |= netdev->vlan_features; 9616 netdev->mpls_features |= NETIF_F_HW_CSUM; 9617 9618 /* set this bit last since it cannot be part of vlan_features */ 9619 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 9620 NETIF_F_HW_VLAN_CTAG_RX | 9621 NETIF_F_HW_VLAN_CTAG_TX; 9622 9623 netdev->priv_flags |= IFF_UNICAST_FLT; 9624 netdev->priv_flags |= IFF_SUPP_NOFCS; 9625 9626 #ifdef CONFIG_IXGBE_DCB 9627 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 9628 netdev->dcbnl_ops = &dcbnl_ops; 9629 #endif 9630 9631 #ifdef IXGBE_FCOE 9632 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 9633 unsigned int fcoe_l; 9634 9635 if (hw->mac.ops.get_device_caps) { 9636 hw->mac.ops.get_device_caps(hw, &device_caps); 9637 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 9638 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 9639 } 9640 9641 9642 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 9643 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 9644 9645 netdev->features |= NETIF_F_FSO | 9646 NETIF_F_FCOE_CRC; 9647 9648 netdev->vlan_features |= NETIF_F_FSO | 9649 NETIF_F_FCOE_CRC | 9650 NETIF_F_FCOE_MTU; 9651 } 9652 #endif /* IXGBE_FCOE */ 9653 9654 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 9655 netdev->hw_features |= NETIF_F_LRO; 9656 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 9657 netdev->features |= NETIF_F_LRO; 9658 9659 /* make sure the EEPROM is good */ 9660 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 9661 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 9662 err = -EIO; 9663 goto err_sw_init; 9664 } 9665 9666 eth_platform_get_mac_address(&adapter->pdev->dev, 9667 adapter->hw.mac.perm_addr); 9668 9669 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 9670 9671 if (!is_valid_ether_addr(netdev->dev_addr)) { 9672 e_dev_err("invalid MAC address\n"); 9673 err = -EIO; 9674 goto err_sw_init; 9675 } 9676 9677 /* Set hw->mac.addr to permanent MAC address */ 9678 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); 9679 ixgbe_mac_set_default_filter(adapter); 9680 9681 setup_timer(&adapter->service_timer, &ixgbe_service_timer, 9682 (unsigned long) adapter); 9683 9684 if (ixgbe_removed(hw->hw_addr)) { 9685 err = -EIO; 9686 goto err_sw_init; 9687 } 9688 INIT_WORK(&adapter->service_task, ixgbe_service_task); 9689 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 9690 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 9691 9692 err = ixgbe_init_interrupt_scheme(adapter); 9693 if (err) 9694 goto err_sw_init; 9695 9696 /* WOL not supported for all devices */ 9697 adapter->wol = 0; 9698 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 9699 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 9700 pdev->subsystem_device); 9701 if (hw->wol_enabled) 9702 adapter->wol = IXGBE_WUFC_MAG; 9703 9704 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 9705 9706 /* save off EEPROM version number */ 9707 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh); 9708 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl); 9709 9710 /* pick up the PCI bus settings for reporting later */ 9711 if (ixgbe_pcie_from_parent(hw)) 9712 ixgbe_get_parent_bus_info(adapter); 9713 else 9714 hw->mac.ops.get_bus_info(hw); 9715 9716 /* calculate the expected PCIe bandwidth required for optimal 9717 * performance. Note that some older parts will never have enough 9718 * bandwidth due to being older generation PCIe parts. We clamp these 9719 * parts to ensure no warning is displayed if it can't be fixed. 9720 */ 9721 switch (hw->mac.type) { 9722 case ixgbe_mac_82598EB: 9723 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 9724 break; 9725 default: 9726 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 9727 break; 9728 } 9729 9730 /* don't check link if we failed to enumerate functions */ 9731 if (expected_gts > 0) 9732 ixgbe_check_minimum_link(adapter, expected_gts); 9733 9734 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 9735 if (err) 9736 strlcpy(part_str, "Unknown", sizeof(part_str)); 9737 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 9738 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 9739 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 9740 part_str); 9741 else 9742 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 9743 hw->mac.type, hw->phy.type, part_str); 9744 9745 e_dev_info("%pM\n", netdev->dev_addr); 9746 9747 /* reset the hardware with the new settings */ 9748 err = hw->mac.ops.start_hw(hw); 9749 if (err == IXGBE_ERR_EEPROM_VERSION) { 9750 /* We are running on a pre-production device, log a warning */ 9751 e_dev_warn("This device is a pre-production adapter/LOM. " 9752 "Please be aware there may be issues associated " 9753 "with your hardware. If you are experiencing " 9754 "problems please contact your Intel or hardware " 9755 "representative who provided you with this " 9756 "hardware.\n"); 9757 } 9758 strcpy(netdev->name, "eth%d"); 9759 err = register_netdev(netdev); 9760 if (err) 9761 goto err_register; 9762 9763 pci_set_drvdata(pdev, adapter); 9764 9765 /* power down the optics for 82599 SFP+ fiber */ 9766 if (hw->mac.ops.disable_tx_laser) 9767 hw->mac.ops.disable_tx_laser(hw); 9768 9769 /* carrier off reporting is important to ethtool even BEFORE open */ 9770 netif_carrier_off(netdev); 9771 9772 #ifdef CONFIG_IXGBE_DCA 9773 if (dca_add_requester(&pdev->dev) == 0) { 9774 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 9775 ixgbe_setup_dca(adapter); 9776 } 9777 #endif 9778 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 9779 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 9780 for (i = 0; i < adapter->num_vfs; i++) 9781 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 9782 } 9783 9784 /* firmware requires driver version to be 0xFFFFFFFF 9785 * since os does not support feature 9786 */ 9787 if (hw->mac.ops.set_fw_drv_ver) 9788 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 9789 0xFF); 9790 9791 /* add san mac addr to netdev */ 9792 ixgbe_add_sanmac_netdev(netdev); 9793 9794 e_dev_info("%s\n", ixgbe_default_device_descr); 9795 9796 #ifdef CONFIG_IXGBE_HWMON 9797 if (ixgbe_sysfs_init(adapter)) 9798 e_err(probe, "failed to allocate sysfs resources\n"); 9799 #endif /* CONFIG_IXGBE_HWMON */ 9800 9801 ixgbe_dbg_adapter_init(adapter); 9802 9803 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 9804 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 9805 hw->mac.ops.setup_link(hw, 9806 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 9807 true); 9808 9809 return 0; 9810 9811 err_register: 9812 ixgbe_release_hw_control(adapter); 9813 ixgbe_clear_interrupt_scheme(adapter); 9814 err_sw_init: 9815 ixgbe_disable_sriov(adapter); 9816 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 9817 iounmap(adapter->io_addr); 9818 kfree(adapter->jump_tables[0]); 9819 kfree(adapter->mac_table); 9820 err_ioremap: 9821 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 9822 free_netdev(netdev); 9823 err_alloc_etherdev: 9824 pci_release_mem_regions(pdev); 9825 err_pci_reg: 9826 err_dma: 9827 if (!adapter || disable_dev) 9828 pci_disable_device(pdev); 9829 return err; 9830 } 9831 9832 /** 9833 * ixgbe_remove - Device Removal Routine 9834 * @pdev: PCI device information struct 9835 * 9836 * ixgbe_remove is called by the PCI subsystem to alert the driver 9837 * that it should release a PCI device. The could be caused by a 9838 * Hot-Plug event, or because the driver is going to be removed from 9839 * memory. 9840 **/ 9841 static void ixgbe_remove(struct pci_dev *pdev) 9842 { 9843 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 9844 struct net_device *netdev; 9845 bool disable_dev; 9846 int i; 9847 9848 /* if !adapter then we already cleaned up in probe */ 9849 if (!adapter) 9850 return; 9851 9852 netdev = adapter->netdev; 9853 ixgbe_dbg_adapter_exit(adapter); 9854 9855 set_bit(__IXGBE_REMOVING, &adapter->state); 9856 cancel_work_sync(&adapter->service_task); 9857 9858 9859 #ifdef CONFIG_IXGBE_DCA 9860 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 9861 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 9862 dca_remove_requester(&pdev->dev); 9863 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 9864 IXGBE_DCA_CTRL_DCA_DISABLE); 9865 } 9866 9867 #endif 9868 #ifdef CONFIG_IXGBE_HWMON 9869 ixgbe_sysfs_exit(adapter); 9870 #endif /* CONFIG_IXGBE_HWMON */ 9871 9872 /* remove the added san mac */ 9873 ixgbe_del_sanmac_netdev(netdev); 9874 9875 #ifdef CONFIG_PCI_IOV 9876 ixgbe_disable_sriov(adapter); 9877 #endif 9878 if (netdev->reg_state == NETREG_REGISTERED) 9879 unregister_netdev(netdev); 9880 9881 ixgbe_clear_interrupt_scheme(adapter); 9882 9883 ixgbe_release_hw_control(adapter); 9884 9885 #ifdef CONFIG_DCB 9886 kfree(adapter->ixgbe_ieee_pfc); 9887 kfree(adapter->ixgbe_ieee_ets); 9888 9889 #endif 9890 iounmap(adapter->io_addr); 9891 pci_release_mem_regions(pdev); 9892 9893 e_dev_info("complete\n"); 9894 9895 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { 9896 if (adapter->jump_tables[i]) { 9897 kfree(adapter->jump_tables[i]->input); 9898 kfree(adapter->jump_tables[i]->mask); 9899 } 9900 kfree(adapter->jump_tables[i]); 9901 } 9902 9903 kfree(adapter->mac_table); 9904 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 9905 free_netdev(netdev); 9906 9907 pci_disable_pcie_error_reporting(pdev); 9908 9909 if (disable_dev) 9910 pci_disable_device(pdev); 9911 } 9912 9913 /** 9914 * ixgbe_io_error_detected - called when PCI error is detected 9915 * @pdev: Pointer to PCI device 9916 * @state: The current pci connection state 9917 * 9918 * This function is called after a PCI bus error affecting 9919 * this device has been detected. 9920 */ 9921 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 9922 pci_channel_state_t state) 9923 { 9924 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 9925 struct net_device *netdev = adapter->netdev; 9926 9927 #ifdef CONFIG_PCI_IOV 9928 struct ixgbe_hw *hw = &adapter->hw; 9929 struct pci_dev *bdev, *vfdev; 9930 u32 dw0, dw1, dw2, dw3; 9931 int vf, pos; 9932 u16 req_id, pf_func; 9933 9934 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 9935 adapter->num_vfs == 0) 9936 goto skip_bad_vf_detection; 9937 9938 bdev = pdev->bus->self; 9939 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 9940 bdev = bdev->bus->self; 9941 9942 if (!bdev) 9943 goto skip_bad_vf_detection; 9944 9945 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 9946 if (!pos) 9947 goto skip_bad_vf_detection; 9948 9949 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 9950 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 9951 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 9952 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 9953 if (ixgbe_removed(hw->hw_addr)) 9954 goto skip_bad_vf_detection; 9955 9956 req_id = dw1 >> 16; 9957 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 9958 if (!(req_id & 0x0080)) 9959 goto skip_bad_vf_detection; 9960 9961 pf_func = req_id & 0x01; 9962 if ((pf_func & 1) == (pdev->devfn & 1)) { 9963 unsigned int device_id; 9964 9965 vf = (req_id & 0x7F) >> 1; 9966 e_dev_err("VF %d has caused a PCIe error\n", vf); 9967 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 9968 "%8.8x\tdw3: %8.8x\n", 9969 dw0, dw1, dw2, dw3); 9970 switch (adapter->hw.mac.type) { 9971 case ixgbe_mac_82599EB: 9972 device_id = IXGBE_82599_VF_DEVICE_ID; 9973 break; 9974 case ixgbe_mac_X540: 9975 device_id = IXGBE_X540_VF_DEVICE_ID; 9976 break; 9977 case ixgbe_mac_X550: 9978 device_id = IXGBE_DEV_ID_X550_VF; 9979 break; 9980 case ixgbe_mac_X550EM_x: 9981 device_id = IXGBE_DEV_ID_X550EM_X_VF; 9982 break; 9983 case ixgbe_mac_x550em_a: 9984 device_id = IXGBE_DEV_ID_X550EM_A_VF; 9985 break; 9986 default: 9987 device_id = 0; 9988 break; 9989 } 9990 9991 /* Find the pci device of the offending VF */ 9992 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 9993 while (vfdev) { 9994 if (vfdev->devfn == (req_id & 0xFF)) 9995 break; 9996 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 9997 device_id, vfdev); 9998 } 9999 /* 10000 * There's a slim chance the VF could have been hot plugged, 10001 * so if it is no longer present we don't need to issue the 10002 * VFLR. Just clean up the AER in that case. 10003 */ 10004 if (vfdev) { 10005 ixgbe_issue_vf_flr(adapter, vfdev); 10006 /* Free device reference count */ 10007 pci_dev_put(vfdev); 10008 } 10009 10010 pci_cleanup_aer_uncorrect_error_status(pdev); 10011 } 10012 10013 /* 10014 * Even though the error may have occurred on the other port 10015 * we still need to increment the vf error reference count for 10016 * both ports because the I/O resume function will be called 10017 * for both of them. 10018 */ 10019 adapter->vferr_refcount++; 10020 10021 return PCI_ERS_RESULT_RECOVERED; 10022 10023 skip_bad_vf_detection: 10024 #endif /* CONFIG_PCI_IOV */ 10025 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 10026 return PCI_ERS_RESULT_DISCONNECT; 10027 10028 rtnl_lock(); 10029 netif_device_detach(netdev); 10030 10031 if (state == pci_channel_io_perm_failure) { 10032 rtnl_unlock(); 10033 return PCI_ERS_RESULT_DISCONNECT; 10034 } 10035 10036 if (netif_running(netdev)) 10037 ixgbe_down(adapter); 10038 10039 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 10040 pci_disable_device(pdev); 10041 rtnl_unlock(); 10042 10043 /* Request a slot reset. */ 10044 return PCI_ERS_RESULT_NEED_RESET; 10045 } 10046 10047 /** 10048 * ixgbe_io_slot_reset - called after the pci bus has been reset. 10049 * @pdev: Pointer to PCI device 10050 * 10051 * Restart the card from scratch, as if from a cold-boot. 10052 */ 10053 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 10054 { 10055 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10056 pci_ers_result_t result; 10057 int err; 10058 10059 if (pci_enable_device_mem(pdev)) { 10060 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 10061 result = PCI_ERS_RESULT_DISCONNECT; 10062 } else { 10063 smp_mb__before_atomic(); 10064 clear_bit(__IXGBE_DISABLED, &adapter->state); 10065 adapter->hw.hw_addr = adapter->io_addr; 10066 pci_set_master(pdev); 10067 pci_restore_state(pdev); 10068 pci_save_state(pdev); 10069 10070 pci_wake_from_d3(pdev, false); 10071 10072 ixgbe_reset(adapter); 10073 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10074 result = PCI_ERS_RESULT_RECOVERED; 10075 } 10076 10077 err = pci_cleanup_aer_uncorrect_error_status(pdev); 10078 if (err) { 10079 e_dev_err("pci_cleanup_aer_uncorrect_error_status " 10080 "failed 0x%0x\n", err); 10081 /* non-fatal, continue */ 10082 } 10083 10084 return result; 10085 } 10086 10087 /** 10088 * ixgbe_io_resume - called when traffic can start flowing again. 10089 * @pdev: Pointer to PCI device 10090 * 10091 * This callback is called when the error recovery driver tells us that 10092 * its OK to resume normal operation. 10093 */ 10094 static void ixgbe_io_resume(struct pci_dev *pdev) 10095 { 10096 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10097 struct net_device *netdev = adapter->netdev; 10098 10099 #ifdef CONFIG_PCI_IOV 10100 if (adapter->vferr_refcount) { 10101 e_info(drv, "Resuming after VF err\n"); 10102 adapter->vferr_refcount--; 10103 return; 10104 } 10105 10106 #endif 10107 if (netif_running(netdev)) 10108 ixgbe_up(adapter); 10109 10110 netif_device_attach(netdev); 10111 } 10112 10113 static const struct pci_error_handlers ixgbe_err_handler = { 10114 .error_detected = ixgbe_io_error_detected, 10115 .slot_reset = ixgbe_io_slot_reset, 10116 .resume = ixgbe_io_resume, 10117 }; 10118 10119 static struct pci_driver ixgbe_driver = { 10120 .name = ixgbe_driver_name, 10121 .id_table = ixgbe_pci_tbl, 10122 .probe = ixgbe_probe, 10123 .remove = ixgbe_remove, 10124 #ifdef CONFIG_PM 10125 .suspend = ixgbe_suspend, 10126 .resume = ixgbe_resume, 10127 #endif 10128 .shutdown = ixgbe_shutdown, 10129 .sriov_configure = ixgbe_pci_sriov_configure, 10130 .err_handler = &ixgbe_err_handler 10131 }; 10132 10133 /** 10134 * ixgbe_init_module - Driver Registration Routine 10135 * 10136 * ixgbe_init_module is the first routine called when the driver is 10137 * loaded. All it does is register with the PCI subsystem. 10138 **/ 10139 static int __init ixgbe_init_module(void) 10140 { 10141 int ret; 10142 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); 10143 pr_info("%s\n", ixgbe_copyright); 10144 10145 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); 10146 if (!ixgbe_wq) { 10147 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); 10148 return -ENOMEM; 10149 } 10150 10151 ixgbe_dbg_init(); 10152 10153 ret = pci_register_driver(&ixgbe_driver); 10154 if (ret) { 10155 destroy_workqueue(ixgbe_wq); 10156 ixgbe_dbg_exit(); 10157 return ret; 10158 } 10159 10160 #ifdef CONFIG_IXGBE_DCA 10161 dca_register_notify(&dca_notifier); 10162 #endif 10163 10164 return 0; 10165 } 10166 10167 module_init(ixgbe_init_module); 10168 10169 /** 10170 * ixgbe_exit_module - Driver Exit Cleanup Routine 10171 * 10172 * ixgbe_exit_module is called just before the driver is removed 10173 * from memory. 10174 **/ 10175 static void __exit ixgbe_exit_module(void) 10176 { 10177 #ifdef CONFIG_IXGBE_DCA 10178 dca_unregister_notify(&dca_notifier); 10179 #endif 10180 pci_unregister_driver(&ixgbe_driver); 10181 10182 ixgbe_dbg_exit(); 10183 if (ixgbe_wq) { 10184 destroy_workqueue(ixgbe_wq); 10185 ixgbe_wq = NULL; 10186 } 10187 } 10188 10189 #ifdef CONFIG_IXGBE_DCA 10190 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 10191 void *p) 10192 { 10193 int ret_val; 10194 10195 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 10196 __ixgbe_notify_dca); 10197 10198 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 10199 } 10200 10201 #endif /* CONFIG_IXGBE_DCA */ 10202 10203 module_exit(ixgbe_exit_module); 10204 10205 /* ixgbe_main.c */ 10206