1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/types.h> 30 #include <linux/module.h> 31 #include <linux/pci.h> 32 #include <linux/netdevice.h> 33 #include <linux/vmalloc.h> 34 #include <linux/string.h> 35 #include <linux/in.h> 36 #include <linux/interrupt.h> 37 #include <linux/ip.h> 38 #include <linux/tcp.h> 39 #include <linux/sctp.h> 40 #include <linux/pkt_sched.h> 41 #include <linux/ipv6.h> 42 #include <linux/slab.h> 43 #include <net/checksum.h> 44 #include <net/ip6_checksum.h> 45 #include <linux/etherdevice.h> 46 #include <linux/ethtool.h> 47 #include <linux/if.h> 48 #include <linux/if_vlan.h> 49 #include <linux/if_macvlan.h> 50 #include <linux/if_bridge.h> 51 #include <linux/prefetch.h> 52 #include <scsi/fc/fc_fcoe.h> 53 54 #ifdef CONFIG_OF 55 #include <linux/of_net.h> 56 #endif 57 58 #ifdef CONFIG_SPARC 59 #include <asm/idprom.h> 60 #include <asm/prom.h> 61 #endif 62 63 #include "ixgbe.h" 64 #include "ixgbe_common.h" 65 #include "ixgbe_dcb_82599.h" 66 #include "ixgbe_sriov.h" 67 68 char ixgbe_driver_name[] = "ixgbe"; 69 static const char ixgbe_driver_string[] = 70 "Intel(R) 10 Gigabit PCI Express Network Driver"; 71 #ifdef IXGBE_FCOE 72 char ixgbe_default_device_descr[] = 73 "Intel(R) 10 Gigabit Network Connection"; 74 #else 75 static char ixgbe_default_device_descr[] = 76 "Intel(R) 10 Gigabit Network Connection"; 77 #endif 78 #define DRV_VERSION "4.0.1-k" 79 const char ixgbe_driver_version[] = DRV_VERSION; 80 static const char ixgbe_copyright[] = 81 "Copyright (c) 1999-2014 Intel Corporation."; 82 83 static const struct ixgbe_info *ixgbe_info_tbl[] = { 84 [board_82598] = &ixgbe_82598_info, 85 [board_82599] = &ixgbe_82599_info, 86 [board_X540] = &ixgbe_X540_info, 87 [board_X550] = &ixgbe_X550_info, 88 [board_X550EM_x] = &ixgbe_X550EM_x_info, 89 }; 90 91 /* ixgbe_pci_tbl - PCI Device ID Table 92 * 93 * Wildcard entries (PCI_ANY_ID) should come last 94 * Last entry must be all 0s 95 * 96 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 97 * Class, Class Mask, private data (not used) } 98 */ 99 static const struct pci_device_id ixgbe_pci_tbl[] = { 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 133 /* required last entry */ 134 {0, } 135 }; 136 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 137 138 #ifdef CONFIG_IXGBE_DCA 139 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 140 void *p); 141 static struct notifier_block dca_notifier = { 142 .notifier_call = ixgbe_notify_dca, 143 .next = NULL, 144 .priority = 0 145 }; 146 #endif 147 148 #ifdef CONFIG_PCI_IOV 149 static unsigned int max_vfs; 150 module_param(max_vfs, uint, 0); 151 MODULE_PARM_DESC(max_vfs, 152 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 153 #endif /* CONFIG_PCI_IOV */ 154 155 static unsigned int allow_unsupported_sfp; 156 module_param(allow_unsupported_sfp, uint, 0); 157 MODULE_PARM_DESC(allow_unsupported_sfp, 158 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 159 160 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 161 static int debug = -1; 162 module_param(debug, int, 0); 163 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 164 165 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 166 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 167 MODULE_LICENSE("GPL"); 168 MODULE_VERSION(DRV_VERSION); 169 170 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 171 172 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 173 u32 reg, u16 *value) 174 { 175 struct pci_dev *parent_dev; 176 struct pci_bus *parent_bus; 177 178 parent_bus = adapter->pdev->bus->parent; 179 if (!parent_bus) 180 return -1; 181 182 parent_dev = parent_bus->self; 183 if (!parent_dev) 184 return -1; 185 186 if (!pci_is_pcie(parent_dev)) 187 return -1; 188 189 pcie_capability_read_word(parent_dev, reg, value); 190 if (*value == IXGBE_FAILED_READ_CFG_WORD && 191 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 192 return -1; 193 return 0; 194 } 195 196 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 197 { 198 struct ixgbe_hw *hw = &adapter->hw; 199 u16 link_status = 0; 200 int err; 201 202 hw->bus.type = ixgbe_bus_type_pci_express; 203 204 /* Get the negotiated link width and speed from PCI config space of the 205 * parent, as this device is behind a switch 206 */ 207 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 208 209 /* assume caller will handle error case */ 210 if (err) 211 return err; 212 213 hw->bus.width = ixgbe_convert_bus_width(link_status); 214 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 215 216 return 0; 217 } 218 219 /** 220 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent 221 * @hw: hw specific details 222 * 223 * This function is used by probe to determine whether a device's PCI-Express 224 * bandwidth details should be gathered from the parent bus instead of from the 225 * device. Used to ensure that various locations all have the correct device ID 226 * checks. 227 */ 228 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 229 { 230 switch (hw->device_id) { 231 case IXGBE_DEV_ID_82599_SFP_SF_QP: 232 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 233 return true; 234 default: 235 return false; 236 } 237 } 238 239 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 240 int expected_gts) 241 { 242 int max_gts = 0; 243 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; 244 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; 245 struct pci_dev *pdev; 246 247 /* determine whether to use the the parent device 248 */ 249 if (ixgbe_pcie_from_parent(&adapter->hw)) 250 pdev = adapter->pdev->bus->parent->self; 251 else 252 pdev = adapter->pdev; 253 254 if (pcie_get_minimum_link(pdev, &speed, &width) || 255 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { 256 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 257 return; 258 } 259 260 switch (speed) { 261 case PCIE_SPEED_2_5GT: 262 /* 8b/10b encoding reduces max throughput by 20% */ 263 max_gts = 2 * width; 264 break; 265 case PCIE_SPEED_5_0GT: 266 /* 8b/10b encoding reduces max throughput by 20% */ 267 max_gts = 4 * width; 268 break; 269 case PCIE_SPEED_8_0GT: 270 /* 128b/130b encoding reduces throughput by less than 2% */ 271 max_gts = 8 * width; 272 break; 273 default: 274 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 275 return; 276 } 277 278 e_dev_info("PCI Express bandwidth of %dGT/s available\n", 279 max_gts); 280 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n", 281 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : 282 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : 283 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : 284 "Unknown"), 285 width, 286 (speed == PCIE_SPEED_2_5GT ? "20%" : 287 speed == PCIE_SPEED_5_0GT ? "20%" : 288 speed == PCIE_SPEED_8_0GT ? "<2%" : 289 "Unknown")); 290 291 if (max_gts < expected_gts) { 292 e_dev_warn("This is not sufficient for optimal performance of this card.\n"); 293 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n", 294 expected_gts); 295 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n"); 296 } 297 } 298 299 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 300 { 301 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 302 !test_bit(__IXGBE_REMOVING, &adapter->state) && 303 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 304 schedule_work(&adapter->service_task); 305 } 306 307 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 308 { 309 struct ixgbe_adapter *adapter = hw->back; 310 311 if (!hw->hw_addr) 312 return; 313 hw->hw_addr = NULL; 314 e_dev_err("Adapter removed\n"); 315 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 316 ixgbe_service_event_schedule(adapter); 317 } 318 319 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 320 { 321 u32 value; 322 323 /* The following check not only optimizes a bit by not 324 * performing a read on the status register when the 325 * register just read was a status register read that 326 * returned IXGBE_FAILED_READ_REG. It also blocks any 327 * potential recursion. 328 */ 329 if (reg == IXGBE_STATUS) { 330 ixgbe_remove_adapter(hw); 331 return; 332 } 333 value = ixgbe_read_reg(hw, IXGBE_STATUS); 334 if (value == IXGBE_FAILED_READ_REG) 335 ixgbe_remove_adapter(hw); 336 } 337 338 /** 339 * ixgbe_read_reg - Read from device register 340 * @hw: hw specific details 341 * @reg: offset of register to read 342 * 343 * Returns : value read or IXGBE_FAILED_READ_REG if removed 344 * 345 * This function is used to read device registers. It checks for device 346 * removal by confirming any read that returns all ones by checking the 347 * status register value for all ones. This function avoids reading from 348 * the hardware if a removal was previously detected in which case it 349 * returns IXGBE_FAILED_READ_REG (all ones). 350 */ 351 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 352 { 353 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr); 354 u32 value; 355 356 if (ixgbe_removed(reg_addr)) 357 return IXGBE_FAILED_READ_REG; 358 value = readl(reg_addr + reg); 359 if (unlikely(value == IXGBE_FAILED_READ_REG)) 360 ixgbe_check_remove(hw, reg); 361 return value; 362 } 363 364 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 365 { 366 u16 value; 367 368 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 369 if (value == IXGBE_FAILED_READ_CFG_WORD) { 370 ixgbe_remove_adapter(hw); 371 return true; 372 } 373 return false; 374 } 375 376 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 377 { 378 struct ixgbe_adapter *adapter = hw->back; 379 u16 value; 380 381 if (ixgbe_removed(hw->hw_addr)) 382 return IXGBE_FAILED_READ_CFG_WORD; 383 pci_read_config_word(adapter->pdev, reg, &value); 384 if (value == IXGBE_FAILED_READ_CFG_WORD && 385 ixgbe_check_cfg_remove(hw, adapter->pdev)) 386 return IXGBE_FAILED_READ_CFG_WORD; 387 return value; 388 } 389 390 #ifdef CONFIG_PCI_IOV 391 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 392 { 393 struct ixgbe_adapter *adapter = hw->back; 394 u32 value; 395 396 if (ixgbe_removed(hw->hw_addr)) 397 return IXGBE_FAILED_READ_CFG_DWORD; 398 pci_read_config_dword(adapter->pdev, reg, &value); 399 if (value == IXGBE_FAILED_READ_CFG_DWORD && 400 ixgbe_check_cfg_remove(hw, adapter->pdev)) 401 return IXGBE_FAILED_READ_CFG_DWORD; 402 return value; 403 } 404 #endif /* CONFIG_PCI_IOV */ 405 406 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 407 { 408 struct ixgbe_adapter *adapter = hw->back; 409 410 if (ixgbe_removed(hw->hw_addr)) 411 return; 412 pci_write_config_word(adapter->pdev, reg, value); 413 } 414 415 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 416 { 417 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 418 419 /* flush memory to make sure state is correct before next watchdog */ 420 smp_mb__before_atomic(); 421 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 422 } 423 424 struct ixgbe_reg_info { 425 u32 ofs; 426 char *name; 427 }; 428 429 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 430 431 /* General Registers */ 432 {IXGBE_CTRL, "CTRL"}, 433 {IXGBE_STATUS, "STATUS"}, 434 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 435 436 /* Interrupt Registers */ 437 {IXGBE_EICR, "EICR"}, 438 439 /* RX Registers */ 440 {IXGBE_SRRCTL(0), "SRRCTL"}, 441 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 442 {IXGBE_RDLEN(0), "RDLEN"}, 443 {IXGBE_RDH(0), "RDH"}, 444 {IXGBE_RDT(0), "RDT"}, 445 {IXGBE_RXDCTL(0), "RXDCTL"}, 446 {IXGBE_RDBAL(0), "RDBAL"}, 447 {IXGBE_RDBAH(0), "RDBAH"}, 448 449 /* TX Registers */ 450 {IXGBE_TDBAL(0), "TDBAL"}, 451 {IXGBE_TDBAH(0), "TDBAH"}, 452 {IXGBE_TDLEN(0), "TDLEN"}, 453 {IXGBE_TDH(0), "TDH"}, 454 {IXGBE_TDT(0), "TDT"}, 455 {IXGBE_TXDCTL(0), "TXDCTL"}, 456 457 /* List Terminator */ 458 { .name = NULL } 459 }; 460 461 462 /* 463 * ixgbe_regdump - register printout routine 464 */ 465 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 466 { 467 int i = 0, j = 0; 468 char rname[16]; 469 u32 regs[64]; 470 471 switch (reginfo->ofs) { 472 case IXGBE_SRRCTL(0): 473 for (i = 0; i < 64; i++) 474 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 475 break; 476 case IXGBE_DCA_RXCTRL(0): 477 for (i = 0; i < 64; i++) 478 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 479 break; 480 case IXGBE_RDLEN(0): 481 for (i = 0; i < 64; i++) 482 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 483 break; 484 case IXGBE_RDH(0): 485 for (i = 0; i < 64; i++) 486 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 487 break; 488 case IXGBE_RDT(0): 489 for (i = 0; i < 64; i++) 490 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 491 break; 492 case IXGBE_RXDCTL(0): 493 for (i = 0; i < 64; i++) 494 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 495 break; 496 case IXGBE_RDBAL(0): 497 for (i = 0; i < 64; i++) 498 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 499 break; 500 case IXGBE_RDBAH(0): 501 for (i = 0; i < 64; i++) 502 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 503 break; 504 case IXGBE_TDBAL(0): 505 for (i = 0; i < 64; i++) 506 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 507 break; 508 case IXGBE_TDBAH(0): 509 for (i = 0; i < 64; i++) 510 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 511 break; 512 case IXGBE_TDLEN(0): 513 for (i = 0; i < 64; i++) 514 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 515 break; 516 case IXGBE_TDH(0): 517 for (i = 0; i < 64; i++) 518 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 519 break; 520 case IXGBE_TDT(0): 521 for (i = 0; i < 64; i++) 522 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 523 break; 524 case IXGBE_TXDCTL(0): 525 for (i = 0; i < 64; i++) 526 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 527 break; 528 default: 529 pr_info("%-15s %08x\n", reginfo->name, 530 IXGBE_READ_REG(hw, reginfo->ofs)); 531 return; 532 } 533 534 for (i = 0; i < 8; i++) { 535 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); 536 pr_err("%-15s", rname); 537 for (j = 0; j < 8; j++) 538 pr_cont(" %08x", regs[i*8+j]); 539 pr_cont("\n"); 540 } 541 542 } 543 544 /* 545 * ixgbe_dump - Print registers, tx-rings and rx-rings 546 */ 547 static void ixgbe_dump(struct ixgbe_adapter *adapter) 548 { 549 struct net_device *netdev = adapter->netdev; 550 struct ixgbe_hw *hw = &adapter->hw; 551 struct ixgbe_reg_info *reginfo; 552 int n = 0; 553 struct ixgbe_ring *tx_ring; 554 struct ixgbe_tx_buffer *tx_buffer; 555 union ixgbe_adv_tx_desc *tx_desc; 556 struct my_u0 { u64 a; u64 b; } *u0; 557 struct ixgbe_ring *rx_ring; 558 union ixgbe_adv_rx_desc *rx_desc; 559 struct ixgbe_rx_buffer *rx_buffer_info; 560 u32 staterr; 561 int i = 0; 562 563 if (!netif_msg_hw(adapter)) 564 return; 565 566 /* Print netdevice Info */ 567 if (netdev) { 568 dev_info(&adapter->pdev->dev, "Net device Info\n"); 569 pr_info("Device Name state " 570 "trans_start last_rx\n"); 571 pr_info("%-15s %016lX %016lX %016lX\n", 572 netdev->name, 573 netdev->state, 574 netdev->trans_start, 575 netdev->last_rx); 576 } 577 578 /* Print Registers */ 579 dev_info(&adapter->pdev->dev, "Register Dump\n"); 580 pr_info(" Register Name Value\n"); 581 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 582 reginfo->name; reginfo++) { 583 ixgbe_regdump(hw, reginfo); 584 } 585 586 /* Print TX Ring Summary */ 587 if (!netdev || !netif_running(netdev)) 588 return; 589 590 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 591 pr_info(" %s %s %s %s\n", 592 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 593 "leng", "ntw", "timestamp"); 594 for (n = 0; n < adapter->num_tx_queues; n++) { 595 tx_ring = adapter->tx_ring[n]; 596 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 597 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 598 n, tx_ring->next_to_use, tx_ring->next_to_clean, 599 (u64)dma_unmap_addr(tx_buffer, dma), 600 dma_unmap_len(tx_buffer, len), 601 tx_buffer->next_to_watch, 602 (u64)tx_buffer->time_stamp); 603 } 604 605 /* Print TX Rings */ 606 if (!netif_msg_tx_done(adapter)) 607 goto rx_ring_summary; 608 609 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 610 611 /* Transmit Descriptor Formats 612 * 613 * 82598 Advanced Transmit Descriptor 614 * +--------------------------------------------------------------+ 615 * 0 | Buffer Address [63:0] | 616 * +--------------------------------------------------------------+ 617 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 618 * +--------------------------------------------------------------+ 619 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 620 * 621 * 82598 Advanced Transmit Descriptor (Write-Back Format) 622 * +--------------------------------------------------------------+ 623 * 0 | RSV [63:0] | 624 * +--------------------------------------------------------------+ 625 * 8 | RSV | STA | NXTSEQ | 626 * +--------------------------------------------------------------+ 627 * 63 36 35 32 31 0 628 * 629 * 82599+ Advanced Transmit Descriptor 630 * +--------------------------------------------------------------+ 631 * 0 | Buffer Address [63:0] | 632 * +--------------------------------------------------------------+ 633 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 634 * +--------------------------------------------------------------+ 635 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 636 * 637 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 638 * +--------------------------------------------------------------+ 639 * 0 | RSV [63:0] | 640 * +--------------------------------------------------------------+ 641 * 8 | RSV | STA | RSV | 642 * +--------------------------------------------------------------+ 643 * 63 36 35 32 31 0 644 */ 645 646 for (n = 0; n < adapter->num_tx_queues; n++) { 647 tx_ring = adapter->tx_ring[n]; 648 pr_info("------------------------------------\n"); 649 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 650 pr_info("------------------------------------\n"); 651 pr_info("%s%s %s %s %s %s\n", 652 "T [desc] [address 63:0 ] ", 653 "[PlPOIdStDDt Ln] [bi->dma ] ", 654 "leng", "ntw", "timestamp", "bi->skb"); 655 656 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 657 tx_desc = IXGBE_TX_DESC(tx_ring, i); 658 tx_buffer = &tx_ring->tx_buffer_info[i]; 659 u0 = (struct my_u0 *)tx_desc; 660 if (dma_unmap_len(tx_buffer, len) > 0) { 661 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p", 662 i, 663 le64_to_cpu(u0->a), 664 le64_to_cpu(u0->b), 665 (u64)dma_unmap_addr(tx_buffer, dma), 666 dma_unmap_len(tx_buffer, len), 667 tx_buffer->next_to_watch, 668 (u64)tx_buffer->time_stamp, 669 tx_buffer->skb); 670 if (i == tx_ring->next_to_use && 671 i == tx_ring->next_to_clean) 672 pr_cont(" NTC/U\n"); 673 else if (i == tx_ring->next_to_use) 674 pr_cont(" NTU\n"); 675 else if (i == tx_ring->next_to_clean) 676 pr_cont(" NTC\n"); 677 else 678 pr_cont("\n"); 679 680 if (netif_msg_pktdata(adapter) && 681 tx_buffer->skb) 682 print_hex_dump(KERN_INFO, "", 683 DUMP_PREFIX_ADDRESS, 16, 1, 684 tx_buffer->skb->data, 685 dma_unmap_len(tx_buffer, len), 686 true); 687 } 688 } 689 } 690 691 /* Print RX Rings Summary */ 692 rx_ring_summary: 693 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 694 pr_info("Queue [NTU] [NTC]\n"); 695 for (n = 0; n < adapter->num_rx_queues; n++) { 696 rx_ring = adapter->rx_ring[n]; 697 pr_info("%5d %5X %5X\n", 698 n, rx_ring->next_to_use, rx_ring->next_to_clean); 699 } 700 701 /* Print RX Rings */ 702 if (!netif_msg_rx_status(adapter)) 703 return; 704 705 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 706 707 /* Receive Descriptor Formats 708 * 709 * 82598 Advanced Receive Descriptor (Read) Format 710 * 63 1 0 711 * +-----------------------------------------------------+ 712 * 0 | Packet Buffer Address [63:1] |A0/NSE| 713 * +----------------------------------------------+------+ 714 * 8 | Header Buffer Address [63:1] | DD | 715 * +-----------------------------------------------------+ 716 * 717 * 718 * 82598 Advanced Receive Descriptor (Write-Back) Format 719 * 720 * 63 48 47 32 31 30 21 20 16 15 4 3 0 721 * +------------------------------------------------------+ 722 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 723 * | Packet | IP | | | | Type | Type | 724 * | Checksum | Ident | | | | | | 725 * +------------------------------------------------------+ 726 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 727 * +------------------------------------------------------+ 728 * 63 48 47 32 31 20 19 0 729 * 730 * 82599+ Advanced Receive Descriptor (Read) Format 731 * 63 1 0 732 * +-----------------------------------------------------+ 733 * 0 | Packet Buffer Address [63:1] |A0/NSE| 734 * +----------------------------------------------+------+ 735 * 8 | Header Buffer Address [63:1] | DD | 736 * +-----------------------------------------------------+ 737 * 738 * 739 * 82599+ Advanced Receive Descriptor (Write-Back) Format 740 * 741 * 63 48 47 32 31 30 21 20 17 16 4 3 0 742 * +------------------------------------------------------+ 743 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 744 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 745 * |/ Flow Dir Flt ID | | | | | | 746 * +------------------------------------------------------+ 747 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 748 * +------------------------------------------------------+ 749 * 63 48 47 32 31 20 19 0 750 */ 751 752 for (n = 0; n < adapter->num_rx_queues; n++) { 753 rx_ring = adapter->rx_ring[n]; 754 pr_info("------------------------------------\n"); 755 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 756 pr_info("------------------------------------\n"); 757 pr_info("%s%s%s", 758 "R [desc] [ PktBuf A0] ", 759 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 760 "<-- Adv Rx Read format\n"); 761 pr_info("%s%s%s", 762 "RWB[desc] [PcsmIpSHl PtRs] ", 763 "[vl er S cks ln] ---------------- [bi->skb ] ", 764 "<-- Adv Rx Write-Back format\n"); 765 766 for (i = 0; i < rx_ring->count; i++) { 767 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 768 rx_desc = IXGBE_RX_DESC(rx_ring, i); 769 u0 = (struct my_u0 *)rx_desc; 770 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 771 if (staterr & IXGBE_RXD_STAT_DD) { 772 /* Descriptor Done */ 773 pr_info("RWB[0x%03X] %016llX " 774 "%016llX ---------------- %p", i, 775 le64_to_cpu(u0->a), 776 le64_to_cpu(u0->b), 777 rx_buffer_info->skb); 778 } else { 779 pr_info("R [0x%03X] %016llX " 780 "%016llX %016llX %p", i, 781 le64_to_cpu(u0->a), 782 le64_to_cpu(u0->b), 783 (u64)rx_buffer_info->dma, 784 rx_buffer_info->skb); 785 786 if (netif_msg_pktdata(adapter) && 787 rx_buffer_info->dma) { 788 print_hex_dump(KERN_INFO, "", 789 DUMP_PREFIX_ADDRESS, 16, 1, 790 page_address(rx_buffer_info->page) + 791 rx_buffer_info->page_offset, 792 ixgbe_rx_bufsz(rx_ring), true); 793 } 794 } 795 796 if (i == rx_ring->next_to_use) 797 pr_cont(" NTU\n"); 798 else if (i == rx_ring->next_to_clean) 799 pr_cont(" NTC\n"); 800 else 801 pr_cont("\n"); 802 803 } 804 } 805 } 806 807 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 808 { 809 u32 ctrl_ext; 810 811 /* Let firmware take over control of h/w */ 812 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 813 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 814 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 815 } 816 817 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 818 { 819 u32 ctrl_ext; 820 821 /* Let firmware know the driver has taken over */ 822 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 823 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 824 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 825 } 826 827 /** 828 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 829 * @adapter: pointer to adapter struct 830 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 831 * @queue: queue to map the corresponding interrupt to 832 * @msix_vector: the vector to map to the corresponding queue 833 * 834 */ 835 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 836 u8 queue, u8 msix_vector) 837 { 838 u32 ivar, index; 839 struct ixgbe_hw *hw = &adapter->hw; 840 switch (hw->mac.type) { 841 case ixgbe_mac_82598EB: 842 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 843 if (direction == -1) 844 direction = 0; 845 index = (((direction * 64) + queue) >> 2) & 0x1F; 846 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 847 ivar &= ~(0xFF << (8 * (queue & 0x3))); 848 ivar |= (msix_vector << (8 * (queue & 0x3))); 849 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 850 break; 851 case ixgbe_mac_82599EB: 852 case ixgbe_mac_X540: 853 case ixgbe_mac_X550: 854 case ixgbe_mac_X550EM_x: 855 if (direction == -1) { 856 /* other causes */ 857 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 858 index = ((queue & 1) * 8); 859 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 860 ivar &= ~(0xFF << index); 861 ivar |= (msix_vector << index); 862 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 863 break; 864 } else { 865 /* tx or rx causes */ 866 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 867 index = ((16 * (queue & 1)) + (8 * direction)); 868 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 869 ivar &= ~(0xFF << index); 870 ivar |= (msix_vector << index); 871 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 872 break; 873 } 874 default: 875 break; 876 } 877 } 878 879 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 880 u64 qmask) 881 { 882 u32 mask; 883 884 switch (adapter->hw.mac.type) { 885 case ixgbe_mac_82598EB: 886 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 887 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 888 break; 889 case ixgbe_mac_82599EB: 890 case ixgbe_mac_X540: 891 case ixgbe_mac_X550: 892 case ixgbe_mac_X550EM_x: 893 mask = (qmask & 0xFFFFFFFF); 894 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 895 mask = (qmask >> 32); 896 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 897 break; 898 default: 899 break; 900 } 901 } 902 903 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring, 904 struct ixgbe_tx_buffer *tx_buffer) 905 { 906 if (tx_buffer->skb) { 907 dev_kfree_skb_any(tx_buffer->skb); 908 if (dma_unmap_len(tx_buffer, len)) 909 dma_unmap_single(ring->dev, 910 dma_unmap_addr(tx_buffer, dma), 911 dma_unmap_len(tx_buffer, len), 912 DMA_TO_DEVICE); 913 } else if (dma_unmap_len(tx_buffer, len)) { 914 dma_unmap_page(ring->dev, 915 dma_unmap_addr(tx_buffer, dma), 916 dma_unmap_len(tx_buffer, len), 917 DMA_TO_DEVICE); 918 } 919 tx_buffer->next_to_watch = NULL; 920 tx_buffer->skb = NULL; 921 dma_unmap_len_set(tx_buffer, len, 0); 922 /* tx_buffer must be completely set up in the transmit path */ 923 } 924 925 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 926 { 927 struct ixgbe_hw *hw = &adapter->hw; 928 struct ixgbe_hw_stats *hwstats = &adapter->stats; 929 int i; 930 u32 data; 931 932 if ((hw->fc.current_mode != ixgbe_fc_full) && 933 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 934 return; 935 936 switch (hw->mac.type) { 937 case ixgbe_mac_82598EB: 938 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 939 break; 940 default: 941 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 942 } 943 hwstats->lxoffrxc += data; 944 945 /* refill credits (no tx hang) if we received xoff */ 946 if (!data) 947 return; 948 949 for (i = 0; i < adapter->num_tx_queues; i++) 950 clear_bit(__IXGBE_HANG_CHECK_ARMED, 951 &adapter->tx_ring[i]->state); 952 } 953 954 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 955 { 956 struct ixgbe_hw *hw = &adapter->hw; 957 struct ixgbe_hw_stats *hwstats = &adapter->stats; 958 u32 xoff[8] = {0}; 959 u8 tc; 960 int i; 961 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 962 963 if (adapter->ixgbe_ieee_pfc) 964 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 965 966 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 967 ixgbe_update_xoff_rx_lfc(adapter); 968 return; 969 } 970 971 /* update stats for each tc, only valid with PFC enabled */ 972 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 973 u32 pxoffrxc; 974 975 switch (hw->mac.type) { 976 case ixgbe_mac_82598EB: 977 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 978 break; 979 default: 980 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 981 } 982 hwstats->pxoffrxc[i] += pxoffrxc; 983 /* Get the TC for given UP */ 984 tc = netdev_get_prio_tc_map(adapter->netdev, i); 985 xoff[tc] += pxoffrxc; 986 } 987 988 /* disarm tx queues that have received xoff frames */ 989 for (i = 0; i < adapter->num_tx_queues; i++) { 990 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 991 992 tc = tx_ring->dcb_tc; 993 if (xoff[tc]) 994 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 995 } 996 } 997 998 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 999 { 1000 return ring->stats.packets; 1001 } 1002 1003 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1004 { 1005 struct ixgbe_adapter *adapter; 1006 struct ixgbe_hw *hw; 1007 u32 head, tail; 1008 1009 if (ring->l2_accel_priv) 1010 adapter = ring->l2_accel_priv->real_adapter; 1011 else 1012 adapter = netdev_priv(ring->netdev); 1013 1014 hw = &adapter->hw; 1015 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); 1016 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); 1017 1018 if (head != tail) 1019 return (head < tail) ? 1020 tail - head : (tail + ring->count - head); 1021 1022 return 0; 1023 } 1024 1025 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1026 { 1027 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1028 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1029 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1030 1031 clear_check_for_tx_hang(tx_ring); 1032 1033 /* 1034 * Check for a hung queue, but be thorough. This verifies 1035 * that a transmit has been completed since the previous 1036 * check AND there is at least one packet pending. The 1037 * ARMED bit is set to indicate a potential hang. The 1038 * bit is cleared if a pause frame is received to remove 1039 * false hang detection due to PFC or 802.3x frames. By 1040 * requiring this to fail twice we avoid races with 1041 * pfc clearing the ARMED bit and conditions where we 1042 * run the check_tx_hang logic with a transmit completion 1043 * pending but without time to complete it yet. 1044 */ 1045 if (tx_done_old == tx_done && tx_pending) 1046 /* make sure it is true for two checks in a row */ 1047 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1048 &tx_ring->state); 1049 /* update completed stats and continue */ 1050 tx_ring->tx_stats.tx_done_old = tx_done; 1051 /* reset the countdown */ 1052 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1053 1054 return false; 1055 } 1056 1057 /** 1058 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1059 * @adapter: driver private struct 1060 **/ 1061 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1062 { 1063 1064 /* Do the reset outside of interrupt context */ 1065 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1066 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 1067 e_warn(drv, "initiating reset due to tx timeout\n"); 1068 ixgbe_service_event_schedule(adapter); 1069 } 1070 } 1071 1072 /** 1073 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1074 * @q_vector: structure containing interrupt and ring information 1075 * @tx_ring: tx ring to clean 1076 **/ 1077 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1078 struct ixgbe_ring *tx_ring) 1079 { 1080 struct ixgbe_adapter *adapter = q_vector->adapter; 1081 struct ixgbe_tx_buffer *tx_buffer; 1082 union ixgbe_adv_tx_desc *tx_desc; 1083 unsigned int total_bytes = 0, total_packets = 0; 1084 unsigned int budget = q_vector->tx.work_limit; 1085 unsigned int i = tx_ring->next_to_clean; 1086 1087 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1088 return true; 1089 1090 tx_buffer = &tx_ring->tx_buffer_info[i]; 1091 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1092 i -= tx_ring->count; 1093 1094 do { 1095 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1096 1097 /* if next_to_watch is not set then there is no work pending */ 1098 if (!eop_desc) 1099 break; 1100 1101 /* prevent any other reads prior to eop_desc */ 1102 read_barrier_depends(); 1103 1104 /* if DD is not set pending work has not been completed */ 1105 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1106 break; 1107 1108 /* clear next_to_watch to prevent false hangs */ 1109 tx_buffer->next_to_watch = NULL; 1110 1111 /* update the statistics for this packet */ 1112 total_bytes += tx_buffer->bytecount; 1113 total_packets += tx_buffer->gso_segs; 1114 1115 /* free the skb */ 1116 dev_consume_skb_any(tx_buffer->skb); 1117 1118 /* unmap skb header data */ 1119 dma_unmap_single(tx_ring->dev, 1120 dma_unmap_addr(tx_buffer, dma), 1121 dma_unmap_len(tx_buffer, len), 1122 DMA_TO_DEVICE); 1123 1124 /* clear tx_buffer data */ 1125 tx_buffer->skb = NULL; 1126 dma_unmap_len_set(tx_buffer, len, 0); 1127 1128 /* unmap remaining buffers */ 1129 while (tx_desc != eop_desc) { 1130 tx_buffer++; 1131 tx_desc++; 1132 i++; 1133 if (unlikely(!i)) { 1134 i -= tx_ring->count; 1135 tx_buffer = tx_ring->tx_buffer_info; 1136 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1137 } 1138 1139 /* unmap any remaining paged data */ 1140 if (dma_unmap_len(tx_buffer, len)) { 1141 dma_unmap_page(tx_ring->dev, 1142 dma_unmap_addr(tx_buffer, dma), 1143 dma_unmap_len(tx_buffer, len), 1144 DMA_TO_DEVICE); 1145 dma_unmap_len_set(tx_buffer, len, 0); 1146 } 1147 } 1148 1149 /* move us one more past the eop_desc for start of next pkt */ 1150 tx_buffer++; 1151 tx_desc++; 1152 i++; 1153 if (unlikely(!i)) { 1154 i -= tx_ring->count; 1155 tx_buffer = tx_ring->tx_buffer_info; 1156 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1157 } 1158 1159 /* issue prefetch for next Tx descriptor */ 1160 prefetch(tx_desc); 1161 1162 /* update budget accounting */ 1163 budget--; 1164 } while (likely(budget)); 1165 1166 i += tx_ring->count; 1167 tx_ring->next_to_clean = i; 1168 u64_stats_update_begin(&tx_ring->syncp); 1169 tx_ring->stats.bytes += total_bytes; 1170 tx_ring->stats.packets += total_packets; 1171 u64_stats_update_end(&tx_ring->syncp); 1172 q_vector->tx.total_bytes += total_bytes; 1173 q_vector->tx.total_packets += total_packets; 1174 1175 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1176 /* schedule immediate reset if we believe we hung */ 1177 struct ixgbe_hw *hw = &adapter->hw; 1178 e_err(drv, "Detected Tx Unit Hang\n" 1179 " Tx Queue <%d>\n" 1180 " TDH, TDT <%x>, <%x>\n" 1181 " next_to_use <%x>\n" 1182 " next_to_clean <%x>\n" 1183 "tx_buffer_info[next_to_clean]\n" 1184 " time_stamp <%lx>\n" 1185 " jiffies <%lx>\n", 1186 tx_ring->queue_index, 1187 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1188 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1189 tx_ring->next_to_use, i, 1190 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1191 1192 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 1193 1194 e_info(probe, 1195 "tx hang %d detected on queue %d, resetting adapter\n", 1196 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1197 1198 /* schedule immediate reset if we believe we hung */ 1199 ixgbe_tx_timeout_reset(adapter); 1200 1201 /* the adapter is about to reset, no point in enabling stuff */ 1202 return true; 1203 } 1204 1205 netdev_tx_completed_queue(txring_txq(tx_ring), 1206 total_packets, total_bytes); 1207 1208 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1209 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1210 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1211 /* Make sure that anybody stopping the queue after this 1212 * sees the new next_to_clean. 1213 */ 1214 smp_mb(); 1215 if (__netif_subqueue_stopped(tx_ring->netdev, 1216 tx_ring->queue_index) 1217 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 1218 netif_wake_subqueue(tx_ring->netdev, 1219 tx_ring->queue_index); 1220 ++tx_ring->tx_stats.restart_queue; 1221 } 1222 } 1223 1224 return !!budget; 1225 } 1226 1227 #ifdef CONFIG_IXGBE_DCA 1228 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1229 struct ixgbe_ring *tx_ring, 1230 int cpu) 1231 { 1232 struct ixgbe_hw *hw = &adapter->hw; 1233 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1234 u16 reg_offset; 1235 1236 switch (hw->mac.type) { 1237 case ixgbe_mac_82598EB: 1238 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1239 break; 1240 case ixgbe_mac_82599EB: 1241 case ixgbe_mac_X540: 1242 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1243 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1244 break; 1245 default: 1246 /* for unknown hardware do not write register */ 1247 return; 1248 } 1249 1250 /* 1251 * We can enable relaxed ordering for reads, but not writes when 1252 * DCA is enabled. This is due to a known issue in some chipsets 1253 * which will cause the DCA tag to be cleared. 1254 */ 1255 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1256 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1257 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1258 1259 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1260 } 1261 1262 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1263 struct ixgbe_ring *rx_ring, 1264 int cpu) 1265 { 1266 struct ixgbe_hw *hw = &adapter->hw; 1267 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1268 u8 reg_idx = rx_ring->reg_idx; 1269 1270 1271 switch (hw->mac.type) { 1272 case ixgbe_mac_82599EB: 1273 case ixgbe_mac_X540: 1274 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1275 break; 1276 default: 1277 break; 1278 } 1279 1280 /* 1281 * We can enable relaxed ordering for reads, but not writes when 1282 * DCA is enabled. This is due to a known issue in some chipsets 1283 * which will cause the DCA tag to be cleared. 1284 */ 1285 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1286 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1287 1288 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1289 } 1290 1291 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1292 { 1293 struct ixgbe_adapter *adapter = q_vector->adapter; 1294 struct ixgbe_ring *ring; 1295 int cpu = get_cpu(); 1296 1297 if (q_vector->cpu == cpu) 1298 goto out_no_update; 1299 1300 ixgbe_for_each_ring(ring, q_vector->tx) 1301 ixgbe_update_tx_dca(adapter, ring, cpu); 1302 1303 ixgbe_for_each_ring(ring, q_vector->rx) 1304 ixgbe_update_rx_dca(adapter, ring, cpu); 1305 1306 q_vector->cpu = cpu; 1307 out_no_update: 1308 put_cpu(); 1309 } 1310 1311 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1312 { 1313 int i; 1314 1315 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) 1316 return; 1317 1318 /* always use CB2 mode, difference is masked in the CB driver */ 1319 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); 1320 1321 for (i = 0; i < adapter->num_q_vectors; i++) { 1322 adapter->q_vector[i]->cpu = -1; 1323 ixgbe_update_dca(adapter->q_vector[i]); 1324 } 1325 } 1326 1327 static int __ixgbe_notify_dca(struct device *dev, void *data) 1328 { 1329 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1330 unsigned long event = *(unsigned long *)data; 1331 1332 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1333 return 0; 1334 1335 switch (event) { 1336 case DCA_PROVIDER_ADD: 1337 /* if we're already enabled, don't do it again */ 1338 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1339 break; 1340 if (dca_add_requester(dev) == 0) { 1341 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1342 ixgbe_setup_dca(adapter); 1343 break; 1344 } 1345 /* Fall Through since DCA is disabled. */ 1346 case DCA_PROVIDER_REMOVE: 1347 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1348 dca_remove_requester(dev); 1349 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1350 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); 1351 } 1352 break; 1353 } 1354 1355 return 0; 1356 } 1357 1358 #endif /* CONFIG_IXGBE_DCA */ 1359 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1360 union ixgbe_adv_rx_desc *rx_desc, 1361 struct sk_buff *skb) 1362 { 1363 if (ring->netdev->features & NETIF_F_RXHASH) 1364 skb_set_hash(skb, 1365 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1366 PKT_HASH_TYPE_L3); 1367 } 1368 1369 #ifdef IXGBE_FCOE 1370 /** 1371 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1372 * @ring: structure containing ring specific data 1373 * @rx_desc: advanced rx descriptor 1374 * 1375 * Returns : true if it is FCoE pkt 1376 */ 1377 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1378 union ixgbe_adv_rx_desc *rx_desc) 1379 { 1380 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1381 1382 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1383 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1384 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1385 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1386 } 1387 1388 #endif /* IXGBE_FCOE */ 1389 /** 1390 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1391 * @ring: structure containing ring specific data 1392 * @rx_desc: current Rx descriptor being processed 1393 * @skb: skb currently being received and modified 1394 **/ 1395 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1396 union ixgbe_adv_rx_desc *rx_desc, 1397 struct sk_buff *skb) 1398 { 1399 skb_checksum_none_assert(skb); 1400 1401 /* Rx csum disabled */ 1402 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1403 return; 1404 1405 /* if IP and error */ 1406 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1407 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1408 ring->rx_stats.csum_err++; 1409 return; 1410 } 1411 1412 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1413 return; 1414 1415 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1416 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1417 1418 /* 1419 * 82599 errata, UDP frames with a 0 checksum can be marked as 1420 * checksum errors. 1421 */ 1422 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1423 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1424 return; 1425 1426 ring->rx_stats.csum_err++; 1427 return; 1428 } 1429 1430 /* It must be a TCP or UDP packet with a valid checksum */ 1431 skb->ip_summed = CHECKSUM_UNNECESSARY; 1432 } 1433 1434 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1435 struct ixgbe_rx_buffer *bi) 1436 { 1437 struct page *page = bi->page; 1438 dma_addr_t dma; 1439 1440 /* since we are recycling buffers we should seldom need to alloc */ 1441 if (likely(page)) 1442 return true; 1443 1444 /* alloc new page for storage */ 1445 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1446 if (unlikely(!page)) { 1447 rx_ring->rx_stats.alloc_rx_page_failed++; 1448 return false; 1449 } 1450 1451 /* map page for use */ 1452 dma = dma_map_page(rx_ring->dev, page, 0, 1453 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); 1454 1455 /* 1456 * if mapping failed free memory back to system since 1457 * there isn't much point in holding memory we can't use 1458 */ 1459 if (dma_mapping_error(rx_ring->dev, dma)) { 1460 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1461 1462 rx_ring->rx_stats.alloc_rx_page_failed++; 1463 return false; 1464 } 1465 1466 bi->dma = dma; 1467 bi->page = page; 1468 bi->page_offset = 0; 1469 1470 return true; 1471 } 1472 1473 /** 1474 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1475 * @rx_ring: ring to place buffers on 1476 * @cleaned_count: number of buffers to replace 1477 **/ 1478 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1479 { 1480 union ixgbe_adv_rx_desc *rx_desc; 1481 struct ixgbe_rx_buffer *bi; 1482 u16 i = rx_ring->next_to_use; 1483 1484 /* nothing to do */ 1485 if (!cleaned_count) 1486 return; 1487 1488 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1489 bi = &rx_ring->rx_buffer_info[i]; 1490 i -= rx_ring->count; 1491 1492 do { 1493 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1494 break; 1495 1496 /* 1497 * Refresh the desc even if buffer_addrs didn't change 1498 * because each write-back erases this info. 1499 */ 1500 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1501 1502 rx_desc++; 1503 bi++; 1504 i++; 1505 if (unlikely(!i)) { 1506 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1507 bi = rx_ring->rx_buffer_info; 1508 i -= rx_ring->count; 1509 } 1510 1511 /* clear the status bits for the next_to_use descriptor */ 1512 rx_desc->wb.upper.status_error = 0; 1513 1514 cleaned_count--; 1515 } while (cleaned_count); 1516 1517 i += rx_ring->count; 1518 1519 if (rx_ring->next_to_use != i) { 1520 rx_ring->next_to_use = i; 1521 1522 /* update next to alloc since we have filled the ring */ 1523 rx_ring->next_to_alloc = i; 1524 1525 /* Force memory writes to complete before letting h/w 1526 * know there are new descriptors to fetch. (Only 1527 * applicable for weak-ordered memory model archs, 1528 * such as IA-64). 1529 */ 1530 wmb(); 1531 writel(i, rx_ring->tail); 1532 } 1533 } 1534 1535 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1536 struct sk_buff *skb) 1537 { 1538 u16 hdr_len = skb_headlen(skb); 1539 1540 /* set gso_size to avoid messing up TCP MSS */ 1541 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1542 IXGBE_CB(skb)->append_cnt); 1543 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1544 } 1545 1546 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1547 struct sk_buff *skb) 1548 { 1549 /* if append_cnt is 0 then frame is not RSC */ 1550 if (!IXGBE_CB(skb)->append_cnt) 1551 return; 1552 1553 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1554 rx_ring->rx_stats.rsc_flush++; 1555 1556 ixgbe_set_rsc_gso_size(rx_ring, skb); 1557 1558 /* gso_size is computed using append_cnt so always clear it last */ 1559 IXGBE_CB(skb)->append_cnt = 0; 1560 } 1561 1562 /** 1563 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1564 * @rx_ring: rx descriptor ring packet is being transacted on 1565 * @rx_desc: pointer to the EOP Rx descriptor 1566 * @skb: pointer to current skb being populated 1567 * 1568 * This function checks the ring, descriptor, and packet information in 1569 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1570 * other fields within the skb. 1571 **/ 1572 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1573 union ixgbe_adv_rx_desc *rx_desc, 1574 struct sk_buff *skb) 1575 { 1576 struct net_device *dev = rx_ring->netdev; 1577 1578 ixgbe_update_rsc_stats(rx_ring, skb); 1579 1580 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1581 1582 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1583 1584 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))) 1585 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb); 1586 1587 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1588 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1589 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1590 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1591 } 1592 1593 skb_record_rx_queue(skb, rx_ring->queue_index); 1594 1595 skb->protocol = eth_type_trans(skb, dev); 1596 } 1597 1598 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1599 struct sk_buff *skb) 1600 { 1601 struct ixgbe_adapter *adapter = q_vector->adapter; 1602 1603 if (ixgbe_qv_busy_polling(q_vector)) 1604 netif_receive_skb(skb); 1605 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) 1606 napi_gro_receive(&q_vector->napi, skb); 1607 else 1608 netif_rx(skb); 1609 } 1610 1611 /** 1612 * ixgbe_is_non_eop - process handling of non-EOP buffers 1613 * @rx_ring: Rx ring being processed 1614 * @rx_desc: Rx descriptor for current buffer 1615 * @skb: Current socket buffer containing buffer in progress 1616 * 1617 * This function updates next to clean. If the buffer is an EOP buffer 1618 * this function exits returning false, otherwise it will place the 1619 * sk_buff in the next buffer to be chained and return true indicating 1620 * that this is in fact a non-EOP buffer. 1621 **/ 1622 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1623 union ixgbe_adv_rx_desc *rx_desc, 1624 struct sk_buff *skb) 1625 { 1626 u32 ntc = rx_ring->next_to_clean + 1; 1627 1628 /* fetch, update, and store next to clean */ 1629 ntc = (ntc < rx_ring->count) ? ntc : 0; 1630 rx_ring->next_to_clean = ntc; 1631 1632 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1633 1634 /* update RSC append count if present */ 1635 if (ring_is_rsc_enabled(rx_ring)) { 1636 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1637 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1638 1639 if (unlikely(rsc_enabled)) { 1640 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1641 1642 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1643 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1644 1645 /* update ntc based on RSC value */ 1646 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1647 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1648 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1649 } 1650 } 1651 1652 /* if we are the last buffer then there is nothing else to do */ 1653 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1654 return false; 1655 1656 /* place skb in next buffer to be received */ 1657 rx_ring->rx_buffer_info[ntc].skb = skb; 1658 rx_ring->rx_stats.non_eop_descs++; 1659 1660 return true; 1661 } 1662 1663 /** 1664 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1665 * @rx_ring: rx descriptor ring packet is being transacted on 1666 * @skb: pointer to current skb being adjusted 1667 * 1668 * This function is an ixgbe specific version of __pskb_pull_tail. The 1669 * main difference between this version and the original function is that 1670 * this function can make several assumptions about the state of things 1671 * that allow for significant optimizations versus the standard function. 1672 * As a result we can do things like drop a frag and maintain an accurate 1673 * truesize for the skb. 1674 */ 1675 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1676 struct sk_buff *skb) 1677 { 1678 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1679 unsigned char *va; 1680 unsigned int pull_len; 1681 1682 /* 1683 * it is valid to use page_address instead of kmap since we are 1684 * working with pages allocated out of the lomem pool per 1685 * alloc_page(GFP_ATOMIC) 1686 */ 1687 va = skb_frag_address(frag); 1688 1689 /* 1690 * we need the header to contain the greater of either ETH_HLEN or 1691 * 60 bytes if the skb->len is less than 60 for skb_pad. 1692 */ 1693 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE); 1694 1695 /* align pull length to size of long to optimize memcpy performance */ 1696 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1697 1698 /* update all of the pointers */ 1699 skb_frag_size_sub(frag, pull_len); 1700 frag->page_offset += pull_len; 1701 skb->data_len -= pull_len; 1702 skb->tail += pull_len; 1703 } 1704 1705 /** 1706 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1707 * @rx_ring: rx descriptor ring packet is being transacted on 1708 * @skb: pointer to current skb being updated 1709 * 1710 * This function provides a basic DMA sync up for the first fragment of an 1711 * skb. The reason for doing this is that the first fragment cannot be 1712 * unmapped until we have reached the end of packet descriptor for a buffer 1713 * chain. 1714 */ 1715 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1716 struct sk_buff *skb) 1717 { 1718 /* if the page was released unmap it, else just sync our portion */ 1719 if (unlikely(IXGBE_CB(skb)->page_released)) { 1720 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma, 1721 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); 1722 IXGBE_CB(skb)->page_released = false; 1723 } else { 1724 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1725 1726 dma_sync_single_range_for_cpu(rx_ring->dev, 1727 IXGBE_CB(skb)->dma, 1728 frag->page_offset, 1729 ixgbe_rx_bufsz(rx_ring), 1730 DMA_FROM_DEVICE); 1731 } 1732 IXGBE_CB(skb)->dma = 0; 1733 } 1734 1735 /** 1736 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1737 * @rx_ring: rx descriptor ring packet is being transacted on 1738 * @rx_desc: pointer to the EOP Rx descriptor 1739 * @skb: pointer to current skb being fixed 1740 * 1741 * Check for corrupted packet headers caused by senders on the local L2 1742 * embedded NIC switch not setting up their Tx Descriptors right. These 1743 * should be very rare. 1744 * 1745 * Also address the case where we are pulling data in on pages only 1746 * and as such no data is present in the skb header. 1747 * 1748 * In addition if skb is not at least 60 bytes we need to pad it so that 1749 * it is large enough to qualify as a valid Ethernet frame. 1750 * 1751 * Returns true if an error was encountered and skb was freed. 1752 **/ 1753 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1754 union ixgbe_adv_rx_desc *rx_desc, 1755 struct sk_buff *skb) 1756 { 1757 struct net_device *netdev = rx_ring->netdev; 1758 1759 /* verify that the packet does not have any known errors */ 1760 if (unlikely(ixgbe_test_staterr(rx_desc, 1761 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1762 !(netdev->features & NETIF_F_RXALL))) { 1763 dev_kfree_skb_any(skb); 1764 return true; 1765 } 1766 1767 /* place header in linear portion of buffer */ 1768 if (skb_is_nonlinear(skb)) 1769 ixgbe_pull_tail(rx_ring, skb); 1770 1771 #ifdef IXGBE_FCOE 1772 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1773 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1774 return false; 1775 1776 #endif 1777 /* if eth_skb_pad returns an error the skb was freed */ 1778 if (eth_skb_pad(skb)) 1779 return true; 1780 1781 return false; 1782 } 1783 1784 /** 1785 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1786 * @rx_ring: rx descriptor ring to store buffers on 1787 * @old_buff: donor buffer to have page reused 1788 * 1789 * Synchronizes page for reuse by the adapter 1790 **/ 1791 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1792 struct ixgbe_rx_buffer *old_buff) 1793 { 1794 struct ixgbe_rx_buffer *new_buff; 1795 u16 nta = rx_ring->next_to_alloc; 1796 1797 new_buff = &rx_ring->rx_buffer_info[nta]; 1798 1799 /* update, and store next to alloc */ 1800 nta++; 1801 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1802 1803 /* transfer page from old buffer to new buffer */ 1804 *new_buff = *old_buff; 1805 1806 /* sync the buffer for use by the device */ 1807 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma, 1808 new_buff->page_offset, 1809 ixgbe_rx_bufsz(rx_ring), 1810 DMA_FROM_DEVICE); 1811 } 1812 1813 static inline bool ixgbe_page_is_reserved(struct page *page) 1814 { 1815 return (page_to_nid(page) != numa_mem_id()) || page->pfmemalloc; 1816 } 1817 1818 /** 1819 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 1820 * @rx_ring: rx descriptor ring to transact packets on 1821 * @rx_buffer: buffer containing page to add 1822 * @rx_desc: descriptor containing length of buffer written by hardware 1823 * @skb: sk_buff to place the data into 1824 * 1825 * This function will add the data contained in rx_buffer->page to the skb. 1826 * This is done either through a direct copy if the data in the buffer is 1827 * less than the skb header size, otherwise it will just attach the page as 1828 * a frag to the skb. 1829 * 1830 * The function will then update the page offset if necessary and return 1831 * true if the buffer can be reused by the adapter. 1832 **/ 1833 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 1834 struct ixgbe_rx_buffer *rx_buffer, 1835 union ixgbe_adv_rx_desc *rx_desc, 1836 struct sk_buff *skb) 1837 { 1838 struct page *page = rx_buffer->page; 1839 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 1840 #if (PAGE_SIZE < 8192) 1841 unsigned int truesize = ixgbe_rx_bufsz(rx_ring); 1842 #else 1843 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 1844 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) - 1845 ixgbe_rx_bufsz(rx_ring); 1846 #endif 1847 1848 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) { 1849 unsigned char *va = page_address(page) + rx_buffer->page_offset; 1850 1851 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 1852 1853 /* page is not reserved, we can reuse buffer as-is */ 1854 if (likely(!ixgbe_page_is_reserved(page))) 1855 return true; 1856 1857 /* this page cannot be reused so discard it */ 1858 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1859 return false; 1860 } 1861 1862 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 1863 rx_buffer->page_offset, size, truesize); 1864 1865 /* avoid re-using remote pages */ 1866 if (unlikely(ixgbe_page_is_reserved(page))) 1867 return false; 1868 1869 #if (PAGE_SIZE < 8192) 1870 /* if we are only owner of page we can reuse it */ 1871 if (unlikely(page_count(page) != 1)) 1872 return false; 1873 1874 /* flip page offset to other buffer */ 1875 rx_buffer->page_offset ^= truesize; 1876 #else 1877 /* move offset up to the next cache line */ 1878 rx_buffer->page_offset += truesize; 1879 1880 if (rx_buffer->page_offset > last_offset) 1881 return false; 1882 #endif 1883 1884 /* Even if we own the page, we are not allowed to use atomic_set() 1885 * This would break get_page_unless_zero() users. 1886 */ 1887 atomic_inc(&page->_count); 1888 1889 return true; 1890 } 1891 1892 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring, 1893 union ixgbe_adv_rx_desc *rx_desc) 1894 { 1895 struct ixgbe_rx_buffer *rx_buffer; 1896 struct sk_buff *skb; 1897 struct page *page; 1898 1899 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 1900 page = rx_buffer->page; 1901 prefetchw(page); 1902 1903 skb = rx_buffer->skb; 1904 1905 if (likely(!skb)) { 1906 void *page_addr = page_address(page) + 1907 rx_buffer->page_offset; 1908 1909 /* prefetch first cache line of first page */ 1910 prefetch(page_addr); 1911 #if L1_CACHE_BYTES < 128 1912 prefetch(page_addr + L1_CACHE_BYTES); 1913 #endif 1914 1915 /* allocate a skb to store the frags */ 1916 skb = napi_alloc_skb(&rx_ring->q_vector->napi, 1917 IXGBE_RX_HDR_SIZE); 1918 if (unlikely(!skb)) { 1919 rx_ring->rx_stats.alloc_rx_buff_failed++; 1920 return NULL; 1921 } 1922 1923 /* 1924 * we will be copying header into skb->data in 1925 * pskb_may_pull so it is in our interest to prefetch 1926 * it now to avoid a possible cache miss 1927 */ 1928 prefetchw(skb->data); 1929 1930 /* 1931 * Delay unmapping of the first packet. It carries the 1932 * header information, HW may still access the header 1933 * after the writeback. Only unmap it when EOP is 1934 * reached 1935 */ 1936 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1937 goto dma_sync; 1938 1939 IXGBE_CB(skb)->dma = rx_buffer->dma; 1940 } else { 1941 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 1942 ixgbe_dma_sync_frag(rx_ring, skb); 1943 1944 dma_sync: 1945 /* we are reusing so sync this buffer for CPU use */ 1946 dma_sync_single_range_for_cpu(rx_ring->dev, 1947 rx_buffer->dma, 1948 rx_buffer->page_offset, 1949 ixgbe_rx_bufsz(rx_ring), 1950 DMA_FROM_DEVICE); 1951 1952 rx_buffer->skb = NULL; 1953 } 1954 1955 /* pull page into skb */ 1956 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 1957 /* hand second half of page back to the ring */ 1958 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 1959 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) { 1960 /* the page has been released from the ring */ 1961 IXGBE_CB(skb)->page_released = true; 1962 } else { 1963 /* we are not reusing the buffer so unmap it */ 1964 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 1965 ixgbe_rx_pg_size(rx_ring), 1966 DMA_FROM_DEVICE); 1967 } 1968 1969 /* clear contents of buffer_info */ 1970 rx_buffer->page = NULL; 1971 1972 return skb; 1973 } 1974 1975 /** 1976 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 1977 * @q_vector: structure containing interrupt and ring information 1978 * @rx_ring: rx descriptor ring to transact packets on 1979 * @budget: Total limit on number of packets to process 1980 * 1981 * This function provides a "bounce buffer" approach to Rx interrupt 1982 * processing. The advantage to this is that on systems that have 1983 * expensive overhead for IOMMU access this provides a means of avoiding 1984 * it by maintaining the mapping of the page to the syste. 1985 * 1986 * Returns amount of work completed 1987 **/ 1988 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 1989 struct ixgbe_ring *rx_ring, 1990 const int budget) 1991 { 1992 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1993 #ifdef IXGBE_FCOE 1994 struct ixgbe_adapter *adapter = q_vector->adapter; 1995 int ddp_bytes; 1996 unsigned int mss = 0; 1997 #endif /* IXGBE_FCOE */ 1998 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 1999 2000 while (likely(total_rx_packets < budget)) { 2001 union ixgbe_adv_rx_desc *rx_desc; 2002 struct sk_buff *skb; 2003 2004 /* return some buffers to hardware, one at a time is too slow */ 2005 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2006 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2007 cleaned_count = 0; 2008 } 2009 2010 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2011 2012 if (!rx_desc->wb.upper.status_error) 2013 break; 2014 2015 /* This memory barrier is needed to keep us from reading 2016 * any other fields out of the rx_desc until we know the 2017 * descriptor has been written back 2018 */ 2019 dma_rmb(); 2020 2021 /* retrieve a buffer from the ring */ 2022 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc); 2023 2024 /* exit if we failed to retrieve a buffer */ 2025 if (!skb) 2026 break; 2027 2028 cleaned_count++; 2029 2030 /* place incomplete frames back on ring for completion */ 2031 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2032 continue; 2033 2034 /* verify the packet layout is correct */ 2035 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2036 continue; 2037 2038 /* probably a little skewed due to removing CRC */ 2039 total_rx_bytes += skb->len; 2040 2041 /* populate checksum, timestamp, VLAN, and protocol */ 2042 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2043 2044 #ifdef IXGBE_FCOE 2045 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2046 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2047 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2048 /* include DDPed FCoE data */ 2049 if (ddp_bytes > 0) { 2050 if (!mss) { 2051 mss = rx_ring->netdev->mtu - 2052 sizeof(struct fcoe_hdr) - 2053 sizeof(struct fc_frame_header) - 2054 sizeof(struct fcoe_crc_eof); 2055 if (mss > 512) 2056 mss &= ~511; 2057 } 2058 total_rx_bytes += ddp_bytes; 2059 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2060 mss); 2061 } 2062 if (!ddp_bytes) { 2063 dev_kfree_skb_any(skb); 2064 continue; 2065 } 2066 } 2067 2068 #endif /* IXGBE_FCOE */ 2069 skb_mark_napi_id(skb, &q_vector->napi); 2070 ixgbe_rx_skb(q_vector, skb); 2071 2072 /* update budget accounting */ 2073 total_rx_packets++; 2074 } 2075 2076 u64_stats_update_begin(&rx_ring->syncp); 2077 rx_ring->stats.packets += total_rx_packets; 2078 rx_ring->stats.bytes += total_rx_bytes; 2079 u64_stats_update_end(&rx_ring->syncp); 2080 q_vector->rx.total_packets += total_rx_packets; 2081 q_vector->rx.total_bytes += total_rx_bytes; 2082 2083 return total_rx_packets; 2084 } 2085 2086 #ifdef CONFIG_NET_RX_BUSY_POLL 2087 /* must be called with local_bh_disable()d */ 2088 static int ixgbe_low_latency_recv(struct napi_struct *napi) 2089 { 2090 struct ixgbe_q_vector *q_vector = 2091 container_of(napi, struct ixgbe_q_vector, napi); 2092 struct ixgbe_adapter *adapter = q_vector->adapter; 2093 struct ixgbe_ring *ring; 2094 int found = 0; 2095 2096 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2097 return LL_FLUSH_FAILED; 2098 2099 if (!ixgbe_qv_lock_poll(q_vector)) 2100 return LL_FLUSH_BUSY; 2101 2102 ixgbe_for_each_ring(ring, q_vector->rx) { 2103 found = ixgbe_clean_rx_irq(q_vector, ring, 4); 2104 #ifdef BP_EXTENDED_STATS 2105 if (found) 2106 ring->stats.cleaned += found; 2107 else 2108 ring->stats.misses++; 2109 #endif 2110 if (found) 2111 break; 2112 } 2113 2114 ixgbe_qv_unlock_poll(q_vector); 2115 2116 return found; 2117 } 2118 #endif /* CONFIG_NET_RX_BUSY_POLL */ 2119 2120 /** 2121 * ixgbe_configure_msix - Configure MSI-X hardware 2122 * @adapter: board private structure 2123 * 2124 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2125 * interrupts. 2126 **/ 2127 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2128 { 2129 struct ixgbe_q_vector *q_vector; 2130 int v_idx; 2131 u32 mask; 2132 2133 /* Populate MSIX to EITR Select */ 2134 if (adapter->num_vfs > 32) { 2135 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; 2136 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2137 } 2138 2139 /* 2140 * Populate the IVAR table and set the ITR values to the 2141 * corresponding register. 2142 */ 2143 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2144 struct ixgbe_ring *ring; 2145 q_vector = adapter->q_vector[v_idx]; 2146 2147 ixgbe_for_each_ring(ring, q_vector->rx) 2148 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2149 2150 ixgbe_for_each_ring(ring, q_vector->tx) 2151 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2152 2153 ixgbe_write_eitr(q_vector); 2154 } 2155 2156 switch (adapter->hw.mac.type) { 2157 case ixgbe_mac_82598EB: 2158 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2159 v_idx); 2160 break; 2161 case ixgbe_mac_82599EB: 2162 case ixgbe_mac_X540: 2163 case ixgbe_mac_X550: 2164 case ixgbe_mac_X550EM_x: 2165 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2166 break; 2167 default: 2168 break; 2169 } 2170 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2171 2172 /* set up to autoclear timer, and the vectors */ 2173 mask = IXGBE_EIMS_ENABLE_MASK; 2174 mask &= ~(IXGBE_EIMS_OTHER | 2175 IXGBE_EIMS_MAILBOX | 2176 IXGBE_EIMS_LSC); 2177 2178 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2179 } 2180 2181 enum latency_range { 2182 lowest_latency = 0, 2183 low_latency = 1, 2184 bulk_latency = 2, 2185 latency_invalid = 255 2186 }; 2187 2188 /** 2189 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2190 * @q_vector: structure containing interrupt and ring information 2191 * @ring_container: structure containing ring performance data 2192 * 2193 * Stores a new ITR value based on packets and byte 2194 * counts during the last interrupt. The advantage of per interrupt 2195 * computation is faster updates and more accurate ITR for the current 2196 * traffic pattern. Constants in this function were computed 2197 * based on theoretical maximum wire speed and thresholds were set based 2198 * on testing data as well as attempting to minimize response time 2199 * while increasing bulk throughput. 2200 * this functionality is controlled by the InterruptThrottleRate module 2201 * parameter (see ixgbe_param.c) 2202 **/ 2203 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2204 struct ixgbe_ring_container *ring_container) 2205 { 2206 int bytes = ring_container->total_bytes; 2207 int packets = ring_container->total_packets; 2208 u32 timepassed_us; 2209 u64 bytes_perint; 2210 u8 itr_setting = ring_container->itr; 2211 2212 if (packets == 0) 2213 return; 2214 2215 /* simple throttlerate management 2216 * 0-10MB/s lowest (100000 ints/s) 2217 * 10-20MB/s low (20000 ints/s) 2218 * 20-1249MB/s bulk (8000 ints/s) 2219 */ 2220 /* what was last interrupt timeslice? */ 2221 timepassed_us = q_vector->itr >> 2; 2222 if (timepassed_us == 0) 2223 return; 2224 2225 bytes_perint = bytes / timepassed_us; /* bytes/usec */ 2226 2227 switch (itr_setting) { 2228 case lowest_latency: 2229 if (bytes_perint > 10) 2230 itr_setting = low_latency; 2231 break; 2232 case low_latency: 2233 if (bytes_perint > 20) 2234 itr_setting = bulk_latency; 2235 else if (bytes_perint <= 10) 2236 itr_setting = lowest_latency; 2237 break; 2238 case bulk_latency: 2239 if (bytes_perint <= 20) 2240 itr_setting = low_latency; 2241 break; 2242 } 2243 2244 /* clear work counters since we have the values we need */ 2245 ring_container->total_bytes = 0; 2246 ring_container->total_packets = 0; 2247 2248 /* write updated itr to ring container */ 2249 ring_container->itr = itr_setting; 2250 } 2251 2252 /** 2253 * ixgbe_write_eitr - write EITR register in hardware specific way 2254 * @q_vector: structure containing interrupt and ring information 2255 * 2256 * This function is made to be called by ethtool and by the driver 2257 * when it needs to update EITR registers at runtime. Hardware 2258 * specific quirks/differences are taken care of here. 2259 */ 2260 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2261 { 2262 struct ixgbe_adapter *adapter = q_vector->adapter; 2263 struct ixgbe_hw *hw = &adapter->hw; 2264 int v_idx = q_vector->v_idx; 2265 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2266 2267 switch (adapter->hw.mac.type) { 2268 case ixgbe_mac_82598EB: 2269 /* must write high and low 16 bits to reset counter */ 2270 itr_reg |= (itr_reg << 16); 2271 break; 2272 case ixgbe_mac_82599EB: 2273 case ixgbe_mac_X540: 2274 case ixgbe_mac_X550: 2275 case ixgbe_mac_X550EM_x: 2276 /* 2277 * set the WDIS bit to not clear the timer bits and cause an 2278 * immediate assertion of the interrupt 2279 */ 2280 itr_reg |= IXGBE_EITR_CNT_WDIS; 2281 break; 2282 default: 2283 break; 2284 } 2285 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2286 } 2287 2288 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2289 { 2290 u32 new_itr = q_vector->itr; 2291 u8 current_itr; 2292 2293 ixgbe_update_itr(q_vector, &q_vector->tx); 2294 ixgbe_update_itr(q_vector, &q_vector->rx); 2295 2296 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 2297 2298 switch (current_itr) { 2299 /* counts and packets in update_itr are dependent on these numbers */ 2300 case lowest_latency: 2301 new_itr = IXGBE_100K_ITR; 2302 break; 2303 case low_latency: 2304 new_itr = IXGBE_20K_ITR; 2305 break; 2306 case bulk_latency: 2307 new_itr = IXGBE_8K_ITR; 2308 break; 2309 default: 2310 break; 2311 } 2312 2313 if (new_itr != q_vector->itr) { 2314 /* do an exponential smoothing */ 2315 new_itr = (10 * new_itr * q_vector->itr) / 2316 ((9 * new_itr) + q_vector->itr); 2317 2318 /* save the algorithm value here */ 2319 q_vector->itr = new_itr; 2320 2321 ixgbe_write_eitr(q_vector); 2322 } 2323 } 2324 2325 /** 2326 * ixgbe_check_overtemp_subtask - check for over temperature 2327 * @adapter: pointer to adapter 2328 **/ 2329 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2330 { 2331 struct ixgbe_hw *hw = &adapter->hw; 2332 u32 eicr = adapter->interrupt_event; 2333 2334 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2335 return; 2336 2337 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && 2338 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2339 return; 2340 2341 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2342 2343 switch (hw->device_id) { 2344 case IXGBE_DEV_ID_82599_T3_LOM: 2345 /* 2346 * Since the warning interrupt is for both ports 2347 * we don't have to check if: 2348 * - This interrupt wasn't for our port. 2349 * - We may have missed the interrupt so always have to 2350 * check if we got a LSC 2351 */ 2352 if (!(eicr & IXGBE_EICR_GPI_SDP0) && 2353 !(eicr & IXGBE_EICR_LSC)) 2354 return; 2355 2356 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2357 u32 speed; 2358 bool link_up = false; 2359 2360 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2361 2362 if (link_up) 2363 return; 2364 } 2365 2366 /* Check if this is not due to overtemp */ 2367 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) 2368 return; 2369 2370 break; 2371 default: 2372 if (!(eicr & IXGBE_EICR_GPI_SDP0)) 2373 return; 2374 break; 2375 } 2376 e_crit(drv, 2377 "Network adapter has been stopped because it has over heated. " 2378 "Restart the computer. If the problem persists, " 2379 "power off the system and replace the adapter\n"); 2380 2381 adapter->interrupt_event = 0; 2382 } 2383 2384 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2385 { 2386 struct ixgbe_hw *hw = &adapter->hw; 2387 2388 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2389 (eicr & IXGBE_EICR_GPI_SDP1)) { 2390 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2391 /* write to clear the interrupt */ 2392 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); 2393 } 2394 } 2395 2396 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2397 { 2398 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2399 return; 2400 2401 switch (adapter->hw.mac.type) { 2402 case ixgbe_mac_82599EB: 2403 /* 2404 * Need to check link state so complete overtemp check 2405 * on service task 2406 */ 2407 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) && 2408 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2409 adapter->interrupt_event = eicr; 2410 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2411 ixgbe_service_event_schedule(adapter); 2412 return; 2413 } 2414 return; 2415 case ixgbe_mac_X540: 2416 if (!(eicr & IXGBE_EICR_TS)) 2417 return; 2418 break; 2419 default: 2420 return; 2421 } 2422 2423 e_crit(drv, 2424 "Network adapter has been stopped because it has over heated. " 2425 "Restart the computer. If the problem persists, " 2426 "power off the system and replace the adapter\n"); 2427 } 2428 2429 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2430 { 2431 struct ixgbe_hw *hw = &adapter->hw; 2432 2433 if (eicr & IXGBE_EICR_GPI_SDP2) { 2434 /* Clear the interrupt */ 2435 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); 2436 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2437 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2438 ixgbe_service_event_schedule(adapter); 2439 } 2440 } 2441 2442 if (eicr & IXGBE_EICR_GPI_SDP1) { 2443 /* Clear the interrupt */ 2444 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); 2445 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2446 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2447 ixgbe_service_event_schedule(adapter); 2448 } 2449 } 2450 } 2451 2452 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2453 { 2454 struct ixgbe_hw *hw = &adapter->hw; 2455 2456 adapter->lsc_int++; 2457 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2458 adapter->link_check_timeout = jiffies; 2459 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2460 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2461 IXGBE_WRITE_FLUSH(hw); 2462 ixgbe_service_event_schedule(adapter); 2463 } 2464 } 2465 2466 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2467 u64 qmask) 2468 { 2469 u32 mask; 2470 struct ixgbe_hw *hw = &adapter->hw; 2471 2472 switch (hw->mac.type) { 2473 case ixgbe_mac_82598EB: 2474 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2475 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2476 break; 2477 case ixgbe_mac_82599EB: 2478 case ixgbe_mac_X540: 2479 case ixgbe_mac_X550: 2480 case ixgbe_mac_X550EM_x: 2481 mask = (qmask & 0xFFFFFFFF); 2482 if (mask) 2483 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2484 mask = (qmask >> 32); 2485 if (mask) 2486 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2487 break; 2488 default: 2489 break; 2490 } 2491 /* skip the flush */ 2492 } 2493 2494 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, 2495 u64 qmask) 2496 { 2497 u32 mask; 2498 struct ixgbe_hw *hw = &adapter->hw; 2499 2500 switch (hw->mac.type) { 2501 case ixgbe_mac_82598EB: 2502 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2503 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 2504 break; 2505 case ixgbe_mac_82599EB: 2506 case ixgbe_mac_X540: 2507 case ixgbe_mac_X550: 2508 case ixgbe_mac_X550EM_x: 2509 mask = (qmask & 0xFFFFFFFF); 2510 if (mask) 2511 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 2512 mask = (qmask >> 32); 2513 if (mask) 2514 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 2515 break; 2516 default: 2517 break; 2518 } 2519 /* skip the flush */ 2520 } 2521 2522 /** 2523 * ixgbe_irq_enable - Enable default interrupt generation settings 2524 * @adapter: board private structure 2525 **/ 2526 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 2527 bool flush) 2528 { 2529 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 2530 2531 /* don't reenable LSC while waiting for link */ 2532 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 2533 mask &= ~IXGBE_EIMS_LSC; 2534 2535 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 2536 switch (adapter->hw.mac.type) { 2537 case ixgbe_mac_82599EB: 2538 mask |= IXGBE_EIMS_GPI_SDP0; 2539 break; 2540 case ixgbe_mac_X540: 2541 case ixgbe_mac_X550: 2542 case ixgbe_mac_X550EM_x: 2543 mask |= IXGBE_EIMS_TS; 2544 break; 2545 default: 2546 break; 2547 } 2548 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 2549 mask |= IXGBE_EIMS_GPI_SDP1; 2550 switch (adapter->hw.mac.type) { 2551 case ixgbe_mac_82599EB: 2552 mask |= IXGBE_EIMS_GPI_SDP1; 2553 mask |= IXGBE_EIMS_GPI_SDP2; 2554 /* fall through */ 2555 case ixgbe_mac_X540: 2556 case ixgbe_mac_X550: 2557 case ixgbe_mac_X550EM_x: 2558 mask |= IXGBE_EIMS_ECC; 2559 mask |= IXGBE_EIMS_MAILBOX; 2560 break; 2561 default: 2562 break; 2563 } 2564 2565 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 2566 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 2567 mask |= IXGBE_EIMS_FLOW_DIR; 2568 2569 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 2570 if (queues) 2571 ixgbe_irq_enable_queues(adapter, ~0); 2572 if (flush) 2573 IXGBE_WRITE_FLUSH(&adapter->hw); 2574 } 2575 2576 static irqreturn_t ixgbe_msix_other(int irq, void *data) 2577 { 2578 struct ixgbe_adapter *adapter = data; 2579 struct ixgbe_hw *hw = &adapter->hw; 2580 u32 eicr; 2581 2582 /* 2583 * Workaround for Silicon errata. Use clear-by-write instead 2584 * of clear-by-read. Reading with EICS will return the 2585 * interrupt causes without clearing, which later be done 2586 * with the write to EICR. 2587 */ 2588 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 2589 2590 /* The lower 16bits of the EICR register are for the queue interrupts 2591 * which should be masked here in order to not accidently clear them if 2592 * the bits are high when ixgbe_msix_other is called. There is a race 2593 * condition otherwise which results in possible performance loss 2594 * especially if the ixgbe_msix_other interrupt is triggering 2595 * consistently (as it would when PPS is turned on for the X540 device) 2596 */ 2597 eicr &= 0xFFFF0000; 2598 2599 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 2600 2601 if (eicr & IXGBE_EICR_LSC) 2602 ixgbe_check_lsc(adapter); 2603 2604 if (eicr & IXGBE_EICR_MAILBOX) 2605 ixgbe_msg_task(adapter); 2606 2607 switch (hw->mac.type) { 2608 case ixgbe_mac_82599EB: 2609 case ixgbe_mac_X540: 2610 case ixgbe_mac_X550: 2611 case ixgbe_mac_X550EM_x: 2612 if (eicr & IXGBE_EICR_ECC) { 2613 e_info(link, "Received ECC Err, initiating reset\n"); 2614 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 2615 ixgbe_service_event_schedule(adapter); 2616 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 2617 } 2618 /* Handle Flow Director Full threshold interrupt */ 2619 if (eicr & IXGBE_EICR_FLOW_DIR) { 2620 int reinit_count = 0; 2621 int i; 2622 for (i = 0; i < adapter->num_tx_queues; i++) { 2623 struct ixgbe_ring *ring = adapter->tx_ring[i]; 2624 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 2625 &ring->state)) 2626 reinit_count++; 2627 } 2628 if (reinit_count) { 2629 /* no more flow director interrupts until after init */ 2630 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 2631 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 2632 ixgbe_service_event_schedule(adapter); 2633 } 2634 } 2635 ixgbe_check_sfp_event(adapter, eicr); 2636 ixgbe_check_overtemp_event(adapter, eicr); 2637 break; 2638 default: 2639 break; 2640 } 2641 2642 ixgbe_check_fan_failure(adapter, eicr); 2643 2644 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 2645 ixgbe_ptp_check_pps_event(adapter, eicr); 2646 2647 /* re-enable the original interrupt state, no lsc, no queues */ 2648 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2649 ixgbe_irq_enable(adapter, false, false); 2650 2651 return IRQ_HANDLED; 2652 } 2653 2654 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 2655 { 2656 struct ixgbe_q_vector *q_vector = data; 2657 2658 /* EIAM disabled interrupts (on this vector) for us */ 2659 2660 if (q_vector->rx.ring || q_vector->tx.ring) 2661 napi_schedule(&q_vector->napi); 2662 2663 return IRQ_HANDLED; 2664 } 2665 2666 /** 2667 * ixgbe_poll - NAPI Rx polling callback 2668 * @napi: structure for representing this polling device 2669 * @budget: how many packets driver is allowed to clean 2670 * 2671 * This function is used for legacy and MSI, NAPI mode 2672 **/ 2673 int ixgbe_poll(struct napi_struct *napi, int budget) 2674 { 2675 struct ixgbe_q_vector *q_vector = 2676 container_of(napi, struct ixgbe_q_vector, napi); 2677 struct ixgbe_adapter *adapter = q_vector->adapter; 2678 struct ixgbe_ring *ring; 2679 int per_ring_budget; 2680 bool clean_complete = true; 2681 2682 #ifdef CONFIG_IXGBE_DCA 2683 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 2684 ixgbe_update_dca(q_vector); 2685 #endif 2686 2687 ixgbe_for_each_ring(ring, q_vector->tx) 2688 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring); 2689 2690 if (!ixgbe_qv_lock_napi(q_vector)) 2691 return budget; 2692 2693 /* attempt to distribute budget to each queue fairly, but don't allow 2694 * the budget to go below 1 because we'll exit polling */ 2695 if (q_vector->rx.count > 1) 2696 per_ring_budget = max(budget/q_vector->rx.count, 1); 2697 else 2698 per_ring_budget = budget; 2699 2700 ixgbe_for_each_ring(ring, q_vector->rx) 2701 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring, 2702 per_ring_budget) < per_ring_budget); 2703 2704 ixgbe_qv_unlock_napi(q_vector); 2705 /* If all work not completed, return budget and keep polling */ 2706 if (!clean_complete) 2707 return budget; 2708 2709 /* all work done, exit the polling mode */ 2710 napi_complete(napi); 2711 if (adapter->rx_itr_setting & 1) 2712 ixgbe_set_itr(q_vector); 2713 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2714 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); 2715 2716 return 0; 2717 } 2718 2719 /** 2720 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 2721 * @adapter: board private structure 2722 * 2723 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 2724 * interrupts from the kernel. 2725 **/ 2726 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 2727 { 2728 struct net_device *netdev = adapter->netdev; 2729 int vector, err; 2730 int ri = 0, ti = 0; 2731 2732 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 2733 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 2734 struct msix_entry *entry = &adapter->msix_entries[vector]; 2735 2736 if (q_vector->tx.ring && q_vector->rx.ring) { 2737 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2738 "%s-%s-%d", netdev->name, "TxRx", ri++); 2739 ti++; 2740 } else if (q_vector->rx.ring) { 2741 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2742 "%s-%s-%d", netdev->name, "rx", ri++); 2743 } else if (q_vector->tx.ring) { 2744 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2745 "%s-%s-%d", netdev->name, "tx", ti++); 2746 } else { 2747 /* skip this unused q_vector */ 2748 continue; 2749 } 2750 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 2751 q_vector->name, q_vector); 2752 if (err) { 2753 e_err(probe, "request_irq failed for MSIX interrupt " 2754 "Error: %d\n", err); 2755 goto free_queue_irqs; 2756 } 2757 /* If Flow Director is enabled, set interrupt affinity */ 2758 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 2759 /* assign the mask for this irq */ 2760 irq_set_affinity_hint(entry->vector, 2761 &q_vector->affinity_mask); 2762 } 2763 } 2764 2765 err = request_irq(adapter->msix_entries[vector].vector, 2766 ixgbe_msix_other, 0, netdev->name, adapter); 2767 if (err) { 2768 e_err(probe, "request_irq for msix_other failed: %d\n", err); 2769 goto free_queue_irqs; 2770 } 2771 2772 return 0; 2773 2774 free_queue_irqs: 2775 while (vector) { 2776 vector--; 2777 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 2778 NULL); 2779 free_irq(adapter->msix_entries[vector].vector, 2780 adapter->q_vector[vector]); 2781 } 2782 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 2783 pci_disable_msix(adapter->pdev); 2784 kfree(adapter->msix_entries); 2785 adapter->msix_entries = NULL; 2786 return err; 2787 } 2788 2789 /** 2790 * ixgbe_intr - legacy mode Interrupt Handler 2791 * @irq: interrupt number 2792 * @data: pointer to a network interface device structure 2793 **/ 2794 static irqreturn_t ixgbe_intr(int irq, void *data) 2795 { 2796 struct ixgbe_adapter *adapter = data; 2797 struct ixgbe_hw *hw = &adapter->hw; 2798 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 2799 u32 eicr; 2800 2801 /* 2802 * Workaround for silicon errata #26 on 82598. Mask the interrupt 2803 * before the read of EICR. 2804 */ 2805 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 2806 2807 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 2808 * therefore no explicit interrupt disable is necessary */ 2809 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 2810 if (!eicr) { 2811 /* 2812 * shared interrupt alert! 2813 * make sure interrupts are enabled because the read will 2814 * have disabled interrupts due to EIAM 2815 * finish the workaround of silicon errata on 82598. Unmask 2816 * the interrupt that we masked before the EICR read. 2817 */ 2818 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2819 ixgbe_irq_enable(adapter, true, true); 2820 return IRQ_NONE; /* Not our interrupt */ 2821 } 2822 2823 if (eicr & IXGBE_EICR_LSC) 2824 ixgbe_check_lsc(adapter); 2825 2826 switch (hw->mac.type) { 2827 case ixgbe_mac_82599EB: 2828 ixgbe_check_sfp_event(adapter, eicr); 2829 /* Fall through */ 2830 case ixgbe_mac_X540: 2831 case ixgbe_mac_X550: 2832 case ixgbe_mac_X550EM_x: 2833 if (eicr & IXGBE_EICR_ECC) { 2834 e_info(link, "Received ECC Err, initiating reset\n"); 2835 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 2836 ixgbe_service_event_schedule(adapter); 2837 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 2838 } 2839 ixgbe_check_overtemp_event(adapter, eicr); 2840 break; 2841 default: 2842 break; 2843 } 2844 2845 ixgbe_check_fan_failure(adapter, eicr); 2846 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 2847 ixgbe_ptp_check_pps_event(adapter, eicr); 2848 2849 /* would disable interrupts here but EIAM disabled it */ 2850 napi_schedule(&q_vector->napi); 2851 2852 /* 2853 * re-enable link(maybe) and non-queue interrupts, no flush. 2854 * ixgbe_poll will re-enable the queue interrupts 2855 */ 2856 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2857 ixgbe_irq_enable(adapter, false, false); 2858 2859 return IRQ_HANDLED; 2860 } 2861 2862 /** 2863 * ixgbe_request_irq - initialize interrupts 2864 * @adapter: board private structure 2865 * 2866 * Attempts to configure interrupts using the best available 2867 * capabilities of the hardware and kernel. 2868 **/ 2869 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 2870 { 2871 struct net_device *netdev = adapter->netdev; 2872 int err; 2873 2874 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 2875 err = ixgbe_request_msix_irqs(adapter); 2876 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 2877 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 2878 netdev->name, adapter); 2879 else 2880 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 2881 netdev->name, adapter); 2882 2883 if (err) 2884 e_err(probe, "request_irq failed, Error %d\n", err); 2885 2886 return err; 2887 } 2888 2889 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 2890 { 2891 int vector; 2892 2893 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 2894 free_irq(adapter->pdev->irq, adapter); 2895 return; 2896 } 2897 2898 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 2899 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 2900 struct msix_entry *entry = &adapter->msix_entries[vector]; 2901 2902 /* free only the irqs that were actually requested */ 2903 if (!q_vector->rx.ring && !q_vector->tx.ring) 2904 continue; 2905 2906 /* clear the affinity_mask in the IRQ descriptor */ 2907 irq_set_affinity_hint(entry->vector, NULL); 2908 2909 free_irq(entry->vector, q_vector); 2910 } 2911 2912 free_irq(adapter->msix_entries[vector++].vector, adapter); 2913 } 2914 2915 /** 2916 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 2917 * @adapter: board private structure 2918 **/ 2919 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 2920 { 2921 switch (adapter->hw.mac.type) { 2922 case ixgbe_mac_82598EB: 2923 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 2924 break; 2925 case ixgbe_mac_82599EB: 2926 case ixgbe_mac_X540: 2927 case ixgbe_mac_X550: 2928 case ixgbe_mac_X550EM_x: 2929 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 2930 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 2931 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 2932 break; 2933 default: 2934 break; 2935 } 2936 IXGBE_WRITE_FLUSH(&adapter->hw); 2937 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 2938 int vector; 2939 2940 for (vector = 0; vector < adapter->num_q_vectors; vector++) 2941 synchronize_irq(adapter->msix_entries[vector].vector); 2942 2943 synchronize_irq(adapter->msix_entries[vector++].vector); 2944 } else { 2945 synchronize_irq(adapter->pdev->irq); 2946 } 2947 } 2948 2949 /** 2950 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 2951 * 2952 **/ 2953 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 2954 { 2955 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 2956 2957 ixgbe_write_eitr(q_vector); 2958 2959 ixgbe_set_ivar(adapter, 0, 0, 0); 2960 ixgbe_set_ivar(adapter, 1, 0, 0); 2961 2962 e_info(hw, "Legacy interrupt IVAR setup done\n"); 2963 } 2964 2965 /** 2966 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 2967 * @adapter: board private structure 2968 * @ring: structure containing ring specific data 2969 * 2970 * Configure the Tx descriptor ring after a reset. 2971 **/ 2972 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 2973 struct ixgbe_ring *ring) 2974 { 2975 struct ixgbe_hw *hw = &adapter->hw; 2976 u64 tdba = ring->dma; 2977 int wait_loop = 10; 2978 u32 txdctl = IXGBE_TXDCTL_ENABLE; 2979 u8 reg_idx = ring->reg_idx; 2980 2981 /* disable queue to avoid issues while updating state */ 2982 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 2983 IXGBE_WRITE_FLUSH(hw); 2984 2985 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 2986 (tdba & DMA_BIT_MASK(32))); 2987 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 2988 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 2989 ring->count * sizeof(union ixgbe_adv_tx_desc)); 2990 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 2991 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 2992 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 2993 2994 /* 2995 * set WTHRESH to encourage burst writeback, it should not be set 2996 * higher than 1 when: 2997 * - ITR is 0 as it could cause false TX hangs 2998 * - ITR is set to > 100k int/sec and BQL is enabled 2999 * 3000 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3001 * to or less than the number of on chip descriptors, which is 3002 * currently 40. 3003 */ 3004 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3005 txdctl |= (1 << 16); /* WTHRESH = 1 */ 3006 else 3007 txdctl |= (8 << 16); /* WTHRESH = 8 */ 3008 3009 /* 3010 * Setting PTHRESH to 32 both improves performance 3011 * and avoids a TX hang with DFP enabled 3012 */ 3013 txdctl |= (1 << 8) | /* HTHRESH = 1 */ 3014 32; /* PTHRESH = 32 */ 3015 3016 /* reinitialize flowdirector state */ 3017 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3018 ring->atr_sample_rate = adapter->atr_sample_rate; 3019 ring->atr_count = 0; 3020 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3021 } else { 3022 ring->atr_sample_rate = 0; 3023 } 3024 3025 /* initialize XPS */ 3026 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3027 struct ixgbe_q_vector *q_vector = ring->q_vector; 3028 3029 if (q_vector) 3030 netif_set_xps_queue(ring->netdev, 3031 &q_vector->affinity_mask, 3032 ring->queue_index); 3033 } 3034 3035 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3036 3037 /* enable queue */ 3038 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3039 3040 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3041 if (hw->mac.type == ixgbe_mac_82598EB && 3042 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3043 return; 3044 3045 /* poll to verify queue is enabled */ 3046 do { 3047 usleep_range(1000, 2000); 3048 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3049 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3050 if (!wait_loop) 3051 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx); 3052 } 3053 3054 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3055 { 3056 struct ixgbe_hw *hw = &adapter->hw; 3057 u32 rttdcs, mtqc; 3058 u8 tcs = netdev_get_num_tc(adapter->netdev); 3059 3060 if (hw->mac.type == ixgbe_mac_82598EB) 3061 return; 3062 3063 /* disable the arbiter while setting MTQC */ 3064 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3065 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3066 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3067 3068 /* set transmit pool layout */ 3069 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3070 mtqc = IXGBE_MTQC_VT_ENA; 3071 if (tcs > 4) 3072 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3073 else if (tcs > 1) 3074 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3075 else if (adapter->ring_feature[RING_F_RSS].indices == 4) 3076 mtqc |= IXGBE_MTQC_32VF; 3077 else 3078 mtqc |= IXGBE_MTQC_64VF; 3079 } else { 3080 if (tcs > 4) 3081 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3082 else if (tcs > 1) 3083 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3084 else 3085 mtqc = IXGBE_MTQC_64Q_1PB; 3086 } 3087 3088 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3089 3090 /* Enable Security TX Buffer IFG for multiple pb */ 3091 if (tcs) { 3092 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3093 sectx |= IXGBE_SECTX_DCB; 3094 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3095 } 3096 3097 /* re-enable the arbiter */ 3098 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3099 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3100 } 3101 3102 /** 3103 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3104 * @adapter: board private structure 3105 * 3106 * Configure the Tx unit of the MAC after a reset. 3107 **/ 3108 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3109 { 3110 struct ixgbe_hw *hw = &adapter->hw; 3111 u32 dmatxctl; 3112 u32 i; 3113 3114 ixgbe_setup_mtqc(adapter); 3115 3116 if (hw->mac.type != ixgbe_mac_82598EB) { 3117 /* DMATXCTL.EN must be before Tx queues are enabled */ 3118 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3119 dmatxctl |= IXGBE_DMATXCTL_TE; 3120 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3121 } 3122 3123 /* Setup the HW Tx Head and Tail descriptor pointers */ 3124 for (i = 0; i < adapter->num_tx_queues; i++) 3125 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3126 } 3127 3128 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3129 struct ixgbe_ring *ring) 3130 { 3131 struct ixgbe_hw *hw = &adapter->hw; 3132 u8 reg_idx = ring->reg_idx; 3133 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3134 3135 srrctl |= IXGBE_SRRCTL_DROP_EN; 3136 3137 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3138 } 3139 3140 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3141 struct ixgbe_ring *ring) 3142 { 3143 struct ixgbe_hw *hw = &adapter->hw; 3144 u8 reg_idx = ring->reg_idx; 3145 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3146 3147 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3148 3149 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3150 } 3151 3152 #ifdef CONFIG_IXGBE_DCB 3153 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3154 #else 3155 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3156 #endif 3157 { 3158 int i; 3159 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3160 3161 if (adapter->ixgbe_ieee_pfc) 3162 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3163 3164 /* 3165 * We should set the drop enable bit if: 3166 * SR-IOV is enabled 3167 * or 3168 * Number of Rx queues > 1 and flow control is disabled 3169 * 3170 * This allows us to avoid head of line blocking for security 3171 * and performance reasons. 3172 */ 3173 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3174 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3175 for (i = 0; i < adapter->num_rx_queues; i++) 3176 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3177 } else { 3178 for (i = 0; i < adapter->num_rx_queues; i++) 3179 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3180 } 3181 } 3182 3183 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3184 3185 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3186 struct ixgbe_ring *rx_ring) 3187 { 3188 struct ixgbe_hw *hw = &adapter->hw; 3189 u32 srrctl; 3190 u8 reg_idx = rx_ring->reg_idx; 3191 3192 if (hw->mac.type == ixgbe_mac_82598EB) { 3193 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3194 3195 /* 3196 * if VMDq is not active we must program one srrctl register 3197 * per RSS queue since we have enabled RDRXCTL.MVMEN 3198 */ 3199 reg_idx &= mask; 3200 } 3201 3202 /* configure header buffer length, needed for RSC */ 3203 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3204 3205 /* configure the packet buffer length */ 3206 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3207 3208 /* configure descriptor type */ 3209 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3210 3211 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3212 } 3213 3214 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter, const u32 *seed) 3215 { 3216 struct ixgbe_hw *hw = &adapter->hw; 3217 u32 reta = 0; 3218 int i, j; 3219 int reta_entries = 128; 3220 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3221 int indices_multi; 3222 3223 /* 3224 * Program table for at least 2 queues w/ SR-IOV so that VFs can 3225 * make full use of any rings they may have. We will use the 3226 * PSRTYPE register to control how many rings we use within the PF. 3227 */ 3228 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2)) 3229 rss_i = 2; 3230 3231 /* Fill out hash function seeds */ 3232 for (i = 0; i < 10; i++) 3233 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); 3234 3235 /* Fill out the redirection table as follows: 3236 * 82598: 128 (8 bit wide) entries containing pair of 4 bit RSS indices 3237 * 82599/X540: 128 (8 bit wide) entries containing 4 bit RSS index 3238 * X550: 512 (8 bit wide) entries containing 6 bit RSS index 3239 */ 3240 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3241 indices_multi = 0x11; 3242 else 3243 indices_multi = 0x1; 3244 3245 switch (adapter->hw.mac.type) { 3246 case ixgbe_mac_X550: 3247 case ixgbe_mac_X550EM_x: 3248 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 3249 reta_entries = 512; 3250 default: 3251 break; 3252 } 3253 3254 /* Fill out redirection table */ 3255 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3256 if (j == rss_i) 3257 j = 0; 3258 reta = (reta << 8) | (j * indices_multi); 3259 if ((i & 3) == 3) { 3260 if (i < 128) 3261 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3262 else 3263 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3264 reta); 3265 } 3266 } 3267 } 3268 3269 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter, const u32 *seed) 3270 { 3271 struct ixgbe_hw *hw = &adapter->hw; 3272 u32 vfreta = 0; 3273 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3274 unsigned int pf_pool = adapter->num_vfs; 3275 int i, j; 3276 3277 /* Fill out hash function seeds */ 3278 for (i = 0; i < 10; i++) 3279 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool), seed[i]); 3280 3281 /* Fill out the redirection table */ 3282 for (i = 0, j = 0; i < 64; i++, j++) { 3283 if (j == rss_i) 3284 j = 0; 3285 vfreta = (vfreta << 8) | j; 3286 if ((i & 3) == 3) 3287 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool), 3288 vfreta); 3289 } 3290 } 3291 3292 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3293 { 3294 struct ixgbe_hw *hw = &adapter->hw; 3295 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3296 u32 rss_key[10]; 3297 u32 rxcsum; 3298 3299 /* Disable indicating checksum in descriptor, enables RSS hash */ 3300 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3301 rxcsum |= IXGBE_RXCSUM_PCSD; 3302 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3303 3304 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3305 if (adapter->ring_feature[RING_F_RSS].mask) 3306 mrqc = IXGBE_MRQC_RSSEN; 3307 } else { 3308 u8 tcs = netdev_get_num_tc(adapter->netdev); 3309 3310 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3311 if (tcs > 4) 3312 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3313 else if (tcs > 1) 3314 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3315 else if (adapter->ring_feature[RING_F_RSS].indices == 4) 3316 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3317 else 3318 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3319 } else { 3320 if (tcs > 4) 3321 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3322 else if (tcs > 1) 3323 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3324 else 3325 mrqc = IXGBE_MRQC_RSSEN; 3326 } 3327 } 3328 3329 /* Perform hash on these packet types */ 3330 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3331 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3332 IXGBE_MRQC_RSS_FIELD_IPV6 | 3333 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3334 3335 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3336 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3337 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3338 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3339 3340 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3341 if ((hw->mac.type >= ixgbe_mac_X550) && 3342 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 3343 unsigned int pf_pool = adapter->num_vfs; 3344 3345 /* Enable VF RSS mode */ 3346 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 3347 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3348 3349 /* Setup RSS through the VF registers */ 3350 ixgbe_setup_vfreta(adapter, rss_key); 3351 vfmrqc = IXGBE_MRQC_RSSEN; 3352 vfmrqc |= rss_field; 3353 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc); 3354 } else { 3355 ixgbe_setup_reta(adapter, rss_key); 3356 mrqc |= rss_field; 3357 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3358 } 3359 } 3360 3361 /** 3362 * ixgbe_configure_rscctl - enable RSC for the indicated ring 3363 * @adapter: address of board private structure 3364 * @index: index of ring to set 3365 **/ 3366 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 3367 struct ixgbe_ring *ring) 3368 { 3369 struct ixgbe_hw *hw = &adapter->hw; 3370 u32 rscctrl; 3371 u8 reg_idx = ring->reg_idx; 3372 3373 if (!ring_is_rsc_enabled(ring)) 3374 return; 3375 3376 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 3377 rscctrl |= IXGBE_RSCCTL_RSCEN; 3378 /* 3379 * we must limit the number of descriptors so that the 3380 * total size of max desc * buf_len is not greater 3381 * than 65536 3382 */ 3383 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 3384 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 3385 } 3386 3387 #define IXGBE_MAX_RX_DESC_POLL 10 3388 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 3389 struct ixgbe_ring *ring) 3390 { 3391 struct ixgbe_hw *hw = &adapter->hw; 3392 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 3393 u32 rxdctl; 3394 u8 reg_idx = ring->reg_idx; 3395 3396 if (ixgbe_removed(hw->hw_addr)) 3397 return; 3398 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3399 if (hw->mac.type == ixgbe_mac_82598EB && 3400 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3401 return; 3402 3403 do { 3404 usleep_range(1000, 2000); 3405 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3406 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 3407 3408 if (!wait_loop) { 3409 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 3410 "the polling period\n", reg_idx); 3411 } 3412 } 3413 3414 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, 3415 struct ixgbe_ring *ring) 3416 { 3417 struct ixgbe_hw *hw = &adapter->hw; 3418 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 3419 u32 rxdctl; 3420 u8 reg_idx = ring->reg_idx; 3421 3422 if (ixgbe_removed(hw->hw_addr)) 3423 return; 3424 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3425 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 3426 3427 /* write value back with RXDCTL.ENABLE bit cleared */ 3428 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 3429 3430 if (hw->mac.type == ixgbe_mac_82598EB && 3431 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3432 return; 3433 3434 /* the hardware may take up to 100us to really disable the rx queue */ 3435 do { 3436 udelay(10); 3437 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3438 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); 3439 3440 if (!wait_loop) { 3441 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " 3442 "the polling period\n", reg_idx); 3443 } 3444 } 3445 3446 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 3447 struct ixgbe_ring *ring) 3448 { 3449 struct ixgbe_hw *hw = &adapter->hw; 3450 u64 rdba = ring->dma; 3451 u32 rxdctl; 3452 u8 reg_idx = ring->reg_idx; 3453 3454 /* disable queue to avoid issues while updating state */ 3455 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3456 ixgbe_disable_rx_queue(adapter, ring); 3457 3458 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 3459 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 3460 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 3461 ring->count * sizeof(union ixgbe_adv_rx_desc)); 3462 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 3463 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 3464 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 3465 3466 ixgbe_configure_srrctl(adapter, ring); 3467 ixgbe_configure_rscctl(adapter, ring); 3468 3469 if (hw->mac.type == ixgbe_mac_82598EB) { 3470 /* 3471 * enable cache line friendly hardware writes: 3472 * PTHRESH=32 descriptors (half the internal cache), 3473 * this also removes ugly rx_no_buffer_count increment 3474 * HTHRESH=4 descriptors (to minimize latency on fetch) 3475 * WTHRESH=8 burst writeback up to two cache lines 3476 */ 3477 rxdctl &= ~0x3FFFFF; 3478 rxdctl |= 0x080420; 3479 } 3480 3481 /* enable receive descriptor ring */ 3482 rxdctl |= IXGBE_RXDCTL_ENABLE; 3483 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 3484 3485 ixgbe_rx_desc_queue_enable(adapter, ring); 3486 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 3487 } 3488 3489 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 3490 { 3491 struct ixgbe_hw *hw = &adapter->hw; 3492 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 3493 u16 pool; 3494 3495 /* PSRTYPE must be initialized in non 82598 adapters */ 3496 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 3497 IXGBE_PSRTYPE_UDPHDR | 3498 IXGBE_PSRTYPE_IPV4HDR | 3499 IXGBE_PSRTYPE_L2HDR | 3500 IXGBE_PSRTYPE_IPV6HDR; 3501 3502 if (hw->mac.type == ixgbe_mac_82598EB) 3503 return; 3504 3505 if (rss_i > 3) 3506 psrtype |= 2 << 29; 3507 else if (rss_i > 1) 3508 psrtype |= 1 << 29; 3509 3510 for_each_set_bit(pool, &adapter->fwd_bitmask, 32) 3511 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 3512 } 3513 3514 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 3515 { 3516 struct ixgbe_hw *hw = &adapter->hw; 3517 u32 reg_offset, vf_shift; 3518 u32 gcr_ext, vmdctl; 3519 int i; 3520 3521 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 3522 return; 3523 3524 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 3525 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 3526 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 3527 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 3528 vmdctl |= IXGBE_VT_CTL_REPLEN; 3529 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 3530 3531 vf_shift = VMDQ_P(0) % 32; 3532 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 3533 3534 /* Enable only the PF's pool for Tx/Rx */ 3535 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift); 3536 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 3537 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift); 3538 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 3539 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB) 3540 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 3541 3542 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 3543 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 3544 3545 /* 3546 * Set up VF register offsets for selected VT Mode, 3547 * i.e. 32 or 64 VFs for SR-IOV 3548 */ 3549 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 3550 case IXGBE_82599_VMDQ_8Q_MASK: 3551 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 3552 break; 3553 case IXGBE_82599_VMDQ_4Q_MASK: 3554 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 3555 break; 3556 default: 3557 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 3558 break; 3559 } 3560 3561 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 3562 3563 3564 /* Enable MAC Anti-Spoofing */ 3565 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0), 3566 adapter->num_vfs); 3567 /* For VFs that have spoof checking turned off */ 3568 for (i = 0; i < adapter->num_vfs; i++) { 3569 if (!adapter->vfinfo[i].spoofchk_enabled) 3570 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false); 3571 } 3572 } 3573 3574 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 3575 { 3576 struct ixgbe_hw *hw = &adapter->hw; 3577 struct net_device *netdev = adapter->netdev; 3578 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 3579 struct ixgbe_ring *rx_ring; 3580 int i; 3581 u32 mhadd, hlreg0; 3582 3583 #ifdef IXGBE_FCOE 3584 /* adjust max frame to be able to do baby jumbo for FCoE */ 3585 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 3586 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 3587 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 3588 3589 #endif /* IXGBE_FCOE */ 3590 3591 /* adjust max frame to be at least the size of a standard frame */ 3592 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 3593 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 3594 3595 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 3596 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 3597 mhadd &= ~IXGBE_MHADD_MFS_MASK; 3598 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 3599 3600 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 3601 } 3602 3603 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3604 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 3605 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 3606 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3607 3608 /* 3609 * Setup the HW Rx Head and Tail Descriptor Pointers and 3610 * the Base and Length of the Rx Descriptor Ring 3611 */ 3612 for (i = 0; i < adapter->num_rx_queues; i++) { 3613 rx_ring = adapter->rx_ring[i]; 3614 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 3615 set_ring_rsc_enabled(rx_ring); 3616 else 3617 clear_ring_rsc_enabled(rx_ring); 3618 } 3619 } 3620 3621 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 3622 { 3623 struct ixgbe_hw *hw = &adapter->hw; 3624 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 3625 3626 switch (hw->mac.type) { 3627 case ixgbe_mac_X550: 3628 case ixgbe_mac_X550EM_x: 3629 case ixgbe_mac_82598EB: 3630 /* 3631 * For VMDq support of different descriptor types or 3632 * buffer sizes through the use of multiple SRRCTL 3633 * registers, RDRXCTL.MVMEN must be set to 1 3634 * 3635 * also, the manual doesn't mention it clearly but DCA hints 3636 * will only use queue 0's tags unless this bit is set. Side 3637 * effects of setting this bit are only that SRRCTL must be 3638 * fully programmed [0..15] 3639 */ 3640 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 3641 break; 3642 case ixgbe_mac_82599EB: 3643 case ixgbe_mac_X540: 3644 /* Disable RSC for ACK packets */ 3645 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 3646 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 3647 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 3648 /* hardware requires some bits to be set by default */ 3649 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 3650 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 3651 break; 3652 default: 3653 /* We should do nothing since we don't know this hardware */ 3654 return; 3655 } 3656 3657 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 3658 } 3659 3660 /** 3661 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 3662 * @adapter: board private structure 3663 * 3664 * Configure the Rx unit of the MAC after a reset. 3665 **/ 3666 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 3667 { 3668 struct ixgbe_hw *hw = &adapter->hw; 3669 int i; 3670 u32 rxctrl, rfctl; 3671 3672 /* disable receives while setting up the descriptors */ 3673 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 3674 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); 3675 3676 ixgbe_setup_psrtype(adapter); 3677 ixgbe_setup_rdrxctl(adapter); 3678 3679 /* RSC Setup */ 3680 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 3681 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 3682 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 3683 rfctl |= IXGBE_RFCTL_RSC_DIS; 3684 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 3685 3686 /* Program registers for the distribution of queues */ 3687 ixgbe_setup_mrqc(adapter); 3688 3689 /* set_rx_buffer_len must be called before ring initialization */ 3690 ixgbe_set_rx_buffer_len(adapter); 3691 3692 /* 3693 * Setup the HW Rx Head and Tail Descriptor Pointers and 3694 * the Base and Length of the Rx Descriptor Ring 3695 */ 3696 for (i = 0; i < adapter->num_rx_queues; i++) 3697 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 3698 3699 /* disable drop enable for 82598 parts */ 3700 if (hw->mac.type == ixgbe_mac_82598EB) 3701 rxctrl |= IXGBE_RXCTRL_DMBYPS; 3702 3703 /* enable all receives */ 3704 rxctrl |= IXGBE_RXCTRL_RXEN; 3705 hw->mac.ops.enable_rx_dma(hw, rxctrl); 3706 } 3707 3708 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 3709 __be16 proto, u16 vid) 3710 { 3711 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3712 struct ixgbe_hw *hw = &adapter->hw; 3713 3714 /* add VID to filter table */ 3715 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true); 3716 set_bit(vid, adapter->active_vlans); 3717 3718 return 0; 3719 } 3720 3721 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 3722 __be16 proto, u16 vid) 3723 { 3724 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3725 struct ixgbe_hw *hw = &adapter->hw; 3726 3727 /* remove VID from filter table */ 3728 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false); 3729 clear_bit(vid, adapter->active_vlans); 3730 3731 return 0; 3732 } 3733 3734 /** 3735 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 3736 * @adapter: driver data 3737 */ 3738 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 3739 { 3740 struct ixgbe_hw *hw = &adapter->hw; 3741 u32 vlnctrl; 3742 int i, j; 3743 3744 switch (hw->mac.type) { 3745 case ixgbe_mac_82598EB: 3746 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 3747 vlnctrl &= ~IXGBE_VLNCTRL_VME; 3748 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 3749 break; 3750 case ixgbe_mac_82599EB: 3751 case ixgbe_mac_X540: 3752 case ixgbe_mac_X550: 3753 case ixgbe_mac_X550EM_x: 3754 for (i = 0; i < adapter->num_rx_queues; i++) { 3755 struct ixgbe_ring *ring = adapter->rx_ring[i]; 3756 3757 if (ring->l2_accel_priv) 3758 continue; 3759 j = ring->reg_idx; 3760 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 3761 vlnctrl &= ~IXGBE_RXDCTL_VME; 3762 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 3763 } 3764 break; 3765 default: 3766 break; 3767 } 3768 } 3769 3770 /** 3771 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 3772 * @adapter: driver data 3773 */ 3774 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 3775 { 3776 struct ixgbe_hw *hw = &adapter->hw; 3777 u32 vlnctrl; 3778 int i, j; 3779 3780 switch (hw->mac.type) { 3781 case ixgbe_mac_82598EB: 3782 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 3783 vlnctrl |= IXGBE_VLNCTRL_VME; 3784 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 3785 break; 3786 case ixgbe_mac_82599EB: 3787 case ixgbe_mac_X540: 3788 case ixgbe_mac_X550: 3789 case ixgbe_mac_X550EM_x: 3790 for (i = 0; i < adapter->num_rx_queues; i++) { 3791 struct ixgbe_ring *ring = adapter->rx_ring[i]; 3792 3793 if (ring->l2_accel_priv) 3794 continue; 3795 j = ring->reg_idx; 3796 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 3797 vlnctrl |= IXGBE_RXDCTL_VME; 3798 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 3799 } 3800 break; 3801 default: 3802 break; 3803 } 3804 } 3805 3806 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 3807 { 3808 u16 vid; 3809 3810 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 3811 3812 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 3813 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 3814 } 3815 3816 /** 3817 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 3818 * @netdev: network interface device structure 3819 * 3820 * Writes multicast address list to the MTA hash table. 3821 * Returns: -ENOMEM on failure 3822 * 0 on no addresses written 3823 * X on writing X addresses to MTA 3824 **/ 3825 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 3826 { 3827 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3828 struct ixgbe_hw *hw = &adapter->hw; 3829 3830 if (!netif_running(netdev)) 3831 return 0; 3832 3833 if (hw->mac.ops.update_mc_addr_list) 3834 hw->mac.ops.update_mc_addr_list(hw, netdev); 3835 else 3836 return -ENOMEM; 3837 3838 #ifdef CONFIG_PCI_IOV 3839 ixgbe_restore_vf_multicasts(adapter); 3840 #endif 3841 3842 return netdev_mc_count(netdev); 3843 } 3844 3845 #ifdef CONFIG_PCI_IOV 3846 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 3847 { 3848 struct ixgbe_hw *hw = &adapter->hw; 3849 int i; 3850 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3851 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE) 3852 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr, 3853 adapter->mac_table[i].queue, 3854 IXGBE_RAH_AV); 3855 else 3856 hw->mac.ops.clear_rar(hw, i); 3857 3858 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED); 3859 } 3860 } 3861 #endif 3862 3863 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 3864 { 3865 struct ixgbe_hw *hw = &adapter->hw; 3866 int i; 3867 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3868 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) { 3869 if (adapter->mac_table[i].state & 3870 IXGBE_MAC_STATE_IN_USE) 3871 hw->mac.ops.set_rar(hw, i, 3872 adapter->mac_table[i].addr, 3873 adapter->mac_table[i].queue, 3874 IXGBE_RAH_AV); 3875 else 3876 hw->mac.ops.clear_rar(hw, i); 3877 3878 adapter->mac_table[i].state &= 3879 ~(IXGBE_MAC_STATE_MODIFIED); 3880 } 3881 } 3882 } 3883 3884 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 3885 { 3886 int i; 3887 struct ixgbe_hw *hw = &adapter->hw; 3888 3889 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3890 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED; 3891 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE; 3892 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 3893 adapter->mac_table[i].queue = 0; 3894 } 3895 ixgbe_sync_mac_table(adapter); 3896 } 3897 3898 static int ixgbe_available_rars(struct ixgbe_adapter *adapter) 3899 { 3900 struct ixgbe_hw *hw = &adapter->hw; 3901 int i, count = 0; 3902 3903 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3904 if (adapter->mac_table[i].state == 0) 3905 count++; 3906 } 3907 return count; 3908 } 3909 3910 /* this function destroys the first RAR entry */ 3911 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter, 3912 u8 *addr) 3913 { 3914 struct ixgbe_hw *hw = &adapter->hw; 3915 3916 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN); 3917 adapter->mac_table[0].queue = VMDQ_P(0); 3918 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT | 3919 IXGBE_MAC_STATE_IN_USE); 3920 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr, 3921 adapter->mac_table[0].queue, 3922 IXGBE_RAH_AV); 3923 } 3924 3925 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue) 3926 { 3927 struct ixgbe_hw *hw = &adapter->hw; 3928 int i; 3929 3930 if (is_zero_ether_addr(addr)) 3931 return -EINVAL; 3932 3933 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3934 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE) 3935 continue; 3936 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED | 3937 IXGBE_MAC_STATE_IN_USE); 3938 ether_addr_copy(adapter->mac_table[i].addr, addr); 3939 adapter->mac_table[i].queue = queue; 3940 ixgbe_sync_mac_table(adapter); 3941 return i; 3942 } 3943 return -ENOMEM; 3944 } 3945 3946 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue) 3947 { 3948 /* search table for addr, if found, set to 0 and sync */ 3949 int i; 3950 struct ixgbe_hw *hw = &adapter->hw; 3951 3952 if (is_zero_ether_addr(addr)) 3953 return -EINVAL; 3954 3955 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3956 if (ether_addr_equal(addr, adapter->mac_table[i].addr) && 3957 adapter->mac_table[i].queue == queue) { 3958 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED; 3959 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE; 3960 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 3961 adapter->mac_table[i].queue = 0; 3962 ixgbe_sync_mac_table(adapter); 3963 return 0; 3964 } 3965 } 3966 return -ENOMEM; 3967 } 3968 /** 3969 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table 3970 * @netdev: network interface device structure 3971 * 3972 * Writes unicast address list to the RAR table. 3973 * Returns: -ENOMEM on failure/insufficient address space 3974 * 0 on no addresses written 3975 * X on writing X addresses to the RAR table 3976 **/ 3977 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn) 3978 { 3979 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3980 int count = 0; 3981 3982 /* return ENOMEM indicating insufficient memory for addresses */ 3983 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter)) 3984 return -ENOMEM; 3985 3986 if (!netdev_uc_empty(netdev)) { 3987 struct netdev_hw_addr *ha; 3988 netdev_for_each_uc_addr(ha, netdev) { 3989 ixgbe_del_mac_filter(adapter, ha->addr, vfn); 3990 ixgbe_add_mac_filter(adapter, ha->addr, vfn); 3991 count++; 3992 } 3993 } 3994 return count; 3995 } 3996 3997 /** 3998 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 3999 * @netdev: network interface device structure 4000 * 4001 * The set_rx_method entry point is called whenever the unicast/multicast 4002 * address list or the network interface flags are updated. This routine is 4003 * responsible for configuring the hardware for proper unicast, multicast and 4004 * promiscuous mode. 4005 **/ 4006 void ixgbe_set_rx_mode(struct net_device *netdev) 4007 { 4008 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4009 struct ixgbe_hw *hw = &adapter->hw; 4010 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4011 u32 vlnctrl; 4012 int count; 4013 4014 /* Check for Promiscuous and All Multicast modes */ 4015 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4016 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4017 4018 /* set all bits that we expect to always be set */ 4019 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4020 fctrl |= IXGBE_FCTRL_BAM; 4021 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4022 fctrl |= IXGBE_FCTRL_PMCF; 4023 4024 /* clear the bits we are changing the status of */ 4025 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4026 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); 4027 if (netdev->flags & IFF_PROMISC) { 4028 hw->addr_ctrl.user_set_promisc = true; 4029 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4030 vmolr |= IXGBE_VMOLR_MPE; 4031 /* Only disable hardware filter vlans in promiscuous mode 4032 * if SR-IOV and VMDQ are disabled - otherwise ensure 4033 * that hardware VLAN filters remain enabled. 4034 */ 4035 if (adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED | 4036 IXGBE_FLAG_SRIOV_ENABLED)) 4037 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); 4038 } else { 4039 if (netdev->flags & IFF_ALLMULTI) { 4040 fctrl |= IXGBE_FCTRL_MPE; 4041 vmolr |= IXGBE_VMOLR_MPE; 4042 } 4043 vlnctrl |= IXGBE_VLNCTRL_VFE; 4044 hw->addr_ctrl.user_set_promisc = false; 4045 } 4046 4047 /* 4048 * Write addresses to available RAR registers, if there is not 4049 * sufficient space to store all the addresses then enable 4050 * unicast promiscuous mode 4051 */ 4052 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0)); 4053 if (count < 0) { 4054 fctrl |= IXGBE_FCTRL_UPE; 4055 vmolr |= IXGBE_VMOLR_ROPE; 4056 } 4057 4058 /* Write addresses to the MTA, if the attempt fails 4059 * then we should just turn on promiscuous mode so 4060 * that we can at least receive multicast traffic 4061 */ 4062 count = ixgbe_write_mc_addr_list(netdev); 4063 if (count < 0) { 4064 fctrl |= IXGBE_FCTRL_MPE; 4065 vmolr |= IXGBE_VMOLR_MPE; 4066 } else if (count) { 4067 vmolr |= IXGBE_VMOLR_ROMPE; 4068 } 4069 4070 if (hw->mac.type != ixgbe_mac_82598EB) { 4071 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4072 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4073 IXGBE_VMOLR_ROPE); 4074 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4075 } 4076 4077 /* This is useful for sniffing bad packets. */ 4078 if (adapter->netdev->features & NETIF_F_RXALL) { 4079 /* UPE and MPE will be handled by normal PROMISC logic 4080 * in e1000e_set_rx_mode */ 4081 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 4082 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 4083 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 4084 4085 fctrl &= ~(IXGBE_FCTRL_DPF); 4086 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 4087 } 4088 4089 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4090 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4091 4092 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 4093 ixgbe_vlan_strip_enable(adapter); 4094 else 4095 ixgbe_vlan_strip_disable(adapter); 4096 } 4097 4098 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 4099 { 4100 int q_idx; 4101 4102 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) { 4103 ixgbe_qv_init_lock(adapter->q_vector[q_idx]); 4104 napi_enable(&adapter->q_vector[q_idx]->napi); 4105 } 4106 } 4107 4108 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 4109 { 4110 int q_idx; 4111 4112 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) { 4113 napi_disable(&adapter->q_vector[q_idx]->napi); 4114 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) { 4115 pr_info("QV %d locked\n", q_idx); 4116 usleep_range(1000, 20000); 4117 } 4118 } 4119 } 4120 4121 #ifdef CONFIG_IXGBE_DCB 4122 /** 4123 * ixgbe_configure_dcb - Configure DCB hardware 4124 * @adapter: ixgbe adapter struct 4125 * 4126 * This is called by the driver on open to configure the DCB hardware. 4127 * This is also called by the gennetlink interface when reconfiguring 4128 * the DCB state. 4129 */ 4130 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 4131 { 4132 struct ixgbe_hw *hw = &adapter->hw; 4133 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4134 4135 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 4136 if (hw->mac.type == ixgbe_mac_82598EB) 4137 netif_set_gso_max_size(adapter->netdev, 65536); 4138 return; 4139 } 4140 4141 if (hw->mac.type == ixgbe_mac_82598EB) 4142 netif_set_gso_max_size(adapter->netdev, 32768); 4143 4144 #ifdef IXGBE_FCOE 4145 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 4146 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 4147 #endif 4148 4149 /* reconfigure the hardware */ 4150 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 4151 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 4152 DCB_TX_CONFIG); 4153 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 4154 DCB_RX_CONFIG); 4155 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 4156 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 4157 ixgbe_dcb_hw_ets(&adapter->hw, 4158 adapter->ixgbe_ieee_ets, 4159 max_frame); 4160 ixgbe_dcb_hw_pfc_config(&adapter->hw, 4161 adapter->ixgbe_ieee_pfc->pfc_en, 4162 adapter->ixgbe_ieee_ets->prio_tc); 4163 } 4164 4165 /* Enable RSS Hash per TC */ 4166 if (hw->mac.type != ixgbe_mac_82598EB) { 4167 u32 msb = 0; 4168 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 4169 4170 while (rss_i) { 4171 msb++; 4172 rss_i >>= 1; 4173 } 4174 4175 /* write msb to all 8 TCs in one write */ 4176 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 4177 } 4178 } 4179 #endif 4180 4181 /* Additional bittime to account for IXGBE framing */ 4182 #define IXGBE_ETH_FRAMING 20 4183 4184 /** 4185 * ixgbe_hpbthresh - calculate high water mark for flow control 4186 * 4187 * @adapter: board private structure to calculate for 4188 * @pb: packet buffer to calculate 4189 */ 4190 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 4191 { 4192 struct ixgbe_hw *hw = &adapter->hw; 4193 struct net_device *dev = adapter->netdev; 4194 int link, tc, kb, marker; 4195 u32 dv_id, rx_pba; 4196 4197 /* Calculate max LAN frame size */ 4198 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 4199 4200 #ifdef IXGBE_FCOE 4201 /* FCoE traffic class uses FCOE jumbo frames */ 4202 if ((dev->features & NETIF_F_FCOE_MTU) && 4203 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 4204 (pb == ixgbe_fcoe_get_tc(adapter))) 4205 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4206 #endif 4207 4208 /* Calculate delay value for device */ 4209 switch (hw->mac.type) { 4210 case ixgbe_mac_X540: 4211 case ixgbe_mac_X550: 4212 case ixgbe_mac_X550EM_x: 4213 dv_id = IXGBE_DV_X540(link, tc); 4214 break; 4215 default: 4216 dv_id = IXGBE_DV(link, tc); 4217 break; 4218 } 4219 4220 /* Loopback switch introduces additional latency */ 4221 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 4222 dv_id += IXGBE_B2BT(tc); 4223 4224 /* Delay value is calculated in bit times convert to KB */ 4225 kb = IXGBE_BT2KB(dv_id); 4226 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 4227 4228 marker = rx_pba - kb; 4229 4230 /* It is possible that the packet buffer is not large enough 4231 * to provide required headroom. In this case throw an error 4232 * to user and a do the best we can. 4233 */ 4234 if (marker < 0) { 4235 e_warn(drv, "Packet Buffer(%i) can not provide enough" 4236 "headroom to support flow control." 4237 "Decrease MTU or number of traffic classes\n", pb); 4238 marker = tc + 1; 4239 } 4240 4241 return marker; 4242 } 4243 4244 /** 4245 * ixgbe_lpbthresh - calculate low water mark for for flow control 4246 * 4247 * @adapter: board private structure to calculate for 4248 * @pb: packet buffer to calculate 4249 */ 4250 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 4251 { 4252 struct ixgbe_hw *hw = &adapter->hw; 4253 struct net_device *dev = adapter->netdev; 4254 int tc; 4255 u32 dv_id; 4256 4257 /* Calculate max LAN frame size */ 4258 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 4259 4260 #ifdef IXGBE_FCOE 4261 /* FCoE traffic class uses FCOE jumbo frames */ 4262 if ((dev->features & NETIF_F_FCOE_MTU) && 4263 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 4264 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 4265 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4266 #endif 4267 4268 /* Calculate delay value for device */ 4269 switch (hw->mac.type) { 4270 case ixgbe_mac_X540: 4271 case ixgbe_mac_X550: 4272 case ixgbe_mac_X550EM_x: 4273 dv_id = IXGBE_LOW_DV_X540(tc); 4274 break; 4275 default: 4276 dv_id = IXGBE_LOW_DV(tc); 4277 break; 4278 } 4279 4280 /* Delay value is calculated in bit times convert to KB */ 4281 return IXGBE_BT2KB(dv_id); 4282 } 4283 4284 /* 4285 * ixgbe_pbthresh_setup - calculate and setup high low water marks 4286 */ 4287 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 4288 { 4289 struct ixgbe_hw *hw = &adapter->hw; 4290 int num_tc = netdev_get_num_tc(adapter->netdev); 4291 int i; 4292 4293 if (!num_tc) 4294 num_tc = 1; 4295 4296 for (i = 0; i < num_tc; i++) { 4297 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 4298 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 4299 4300 /* Low water marks must not be larger than high water marks */ 4301 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 4302 hw->fc.low_water[i] = 0; 4303 } 4304 4305 for (; i < MAX_TRAFFIC_CLASS; i++) 4306 hw->fc.high_water[i] = 0; 4307 } 4308 4309 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 4310 { 4311 struct ixgbe_hw *hw = &adapter->hw; 4312 int hdrm; 4313 u8 tc = netdev_get_num_tc(adapter->netdev); 4314 4315 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 4316 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 4317 hdrm = 32 << adapter->fdir_pballoc; 4318 else 4319 hdrm = 0; 4320 4321 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 4322 ixgbe_pbthresh_setup(adapter); 4323 } 4324 4325 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 4326 { 4327 struct ixgbe_hw *hw = &adapter->hw; 4328 struct hlist_node *node2; 4329 struct ixgbe_fdir_filter *filter; 4330 4331 spin_lock(&adapter->fdir_perfect_lock); 4332 4333 if (!hlist_empty(&adapter->fdir_filter_list)) 4334 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 4335 4336 hlist_for_each_entry_safe(filter, node2, 4337 &adapter->fdir_filter_list, fdir_node) { 4338 ixgbe_fdir_write_perfect_filter_82599(hw, 4339 &filter->filter, 4340 filter->sw_idx, 4341 (filter->action == IXGBE_FDIR_DROP_QUEUE) ? 4342 IXGBE_FDIR_DROP_QUEUE : 4343 adapter->rx_ring[filter->action]->reg_idx); 4344 } 4345 4346 spin_unlock(&adapter->fdir_perfect_lock); 4347 } 4348 4349 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool, 4350 struct ixgbe_adapter *adapter) 4351 { 4352 struct ixgbe_hw *hw = &adapter->hw; 4353 u32 vmolr; 4354 4355 /* No unicast promiscuous support for VMDQ devices. */ 4356 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool)); 4357 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE); 4358 4359 /* clear the affected bit */ 4360 vmolr &= ~IXGBE_VMOLR_MPE; 4361 4362 if (dev->flags & IFF_ALLMULTI) { 4363 vmolr |= IXGBE_VMOLR_MPE; 4364 } else { 4365 vmolr |= IXGBE_VMOLR_ROMPE; 4366 hw->mac.ops.update_mc_addr_list(hw, dev); 4367 } 4368 ixgbe_write_uc_addr_list(adapter->netdev, pool); 4369 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr); 4370 } 4371 4372 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter) 4373 { 4374 struct ixgbe_adapter *adapter = vadapter->real_adapter; 4375 int rss_i = adapter->num_rx_queues_per_pool; 4376 struct ixgbe_hw *hw = &adapter->hw; 4377 u16 pool = vadapter->pool; 4378 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4379 IXGBE_PSRTYPE_UDPHDR | 4380 IXGBE_PSRTYPE_IPV4HDR | 4381 IXGBE_PSRTYPE_L2HDR | 4382 IXGBE_PSRTYPE_IPV6HDR; 4383 4384 if (hw->mac.type == ixgbe_mac_82598EB) 4385 return; 4386 4387 if (rss_i > 3) 4388 psrtype |= 2 << 29; 4389 else if (rss_i > 1) 4390 psrtype |= 1 << 29; 4391 4392 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4393 } 4394 4395 /** 4396 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 4397 * @rx_ring: ring to free buffers from 4398 **/ 4399 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 4400 { 4401 struct device *dev = rx_ring->dev; 4402 unsigned long size; 4403 u16 i; 4404 4405 /* ring already cleared, nothing to do */ 4406 if (!rx_ring->rx_buffer_info) 4407 return; 4408 4409 /* Free all the Rx ring sk_buffs */ 4410 for (i = 0; i < rx_ring->count; i++) { 4411 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 4412 4413 if (rx_buffer->skb) { 4414 struct sk_buff *skb = rx_buffer->skb; 4415 if (IXGBE_CB(skb)->page_released) 4416 dma_unmap_page(dev, 4417 IXGBE_CB(skb)->dma, 4418 ixgbe_rx_bufsz(rx_ring), 4419 DMA_FROM_DEVICE); 4420 dev_kfree_skb(skb); 4421 rx_buffer->skb = NULL; 4422 } 4423 4424 if (!rx_buffer->page) 4425 continue; 4426 4427 dma_unmap_page(dev, rx_buffer->dma, 4428 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); 4429 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring)); 4430 4431 rx_buffer->page = NULL; 4432 } 4433 4434 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 4435 memset(rx_ring->rx_buffer_info, 0, size); 4436 4437 /* Zero out the descriptor ring */ 4438 memset(rx_ring->desc, 0, rx_ring->size); 4439 4440 rx_ring->next_to_alloc = 0; 4441 rx_ring->next_to_clean = 0; 4442 rx_ring->next_to_use = 0; 4443 } 4444 4445 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter, 4446 struct ixgbe_ring *rx_ring) 4447 { 4448 struct ixgbe_adapter *adapter = vadapter->real_adapter; 4449 int index = rx_ring->queue_index + vadapter->rx_base_queue; 4450 4451 /* shutdown specific queue receive and wait for dma to settle */ 4452 ixgbe_disable_rx_queue(adapter, rx_ring); 4453 usleep_range(10000, 20000); 4454 ixgbe_irq_disable_queues(adapter, ((u64)1 << index)); 4455 ixgbe_clean_rx_ring(rx_ring); 4456 rx_ring->l2_accel_priv = NULL; 4457 } 4458 4459 static int ixgbe_fwd_ring_down(struct net_device *vdev, 4460 struct ixgbe_fwd_adapter *accel) 4461 { 4462 struct ixgbe_adapter *adapter = accel->real_adapter; 4463 unsigned int rxbase = accel->rx_base_queue; 4464 unsigned int txbase = accel->tx_base_queue; 4465 int i; 4466 4467 netif_tx_stop_all_queues(vdev); 4468 4469 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4470 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); 4471 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev; 4472 } 4473 4474 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4475 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL; 4476 adapter->tx_ring[txbase + i]->netdev = adapter->netdev; 4477 } 4478 4479 4480 return 0; 4481 } 4482 4483 static int ixgbe_fwd_ring_up(struct net_device *vdev, 4484 struct ixgbe_fwd_adapter *accel) 4485 { 4486 struct ixgbe_adapter *adapter = accel->real_adapter; 4487 unsigned int rxbase, txbase, queues; 4488 int i, baseq, err = 0; 4489 4490 if (!test_bit(accel->pool, &adapter->fwd_bitmask)) 4491 return 0; 4492 4493 baseq = accel->pool * adapter->num_rx_queues_per_pool; 4494 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", 4495 accel->pool, adapter->num_rx_pools, 4496 baseq, baseq + adapter->num_rx_queues_per_pool, 4497 adapter->fwd_bitmask); 4498 4499 accel->netdev = vdev; 4500 accel->rx_base_queue = rxbase = baseq; 4501 accel->tx_base_queue = txbase = baseq; 4502 4503 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 4504 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); 4505 4506 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4507 adapter->rx_ring[rxbase + i]->netdev = vdev; 4508 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel; 4509 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]); 4510 } 4511 4512 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4513 adapter->tx_ring[txbase + i]->netdev = vdev; 4514 adapter->tx_ring[txbase + i]->l2_accel_priv = accel; 4515 } 4516 4517 queues = min_t(unsigned int, 4518 adapter->num_rx_queues_per_pool, vdev->num_tx_queues); 4519 err = netif_set_real_num_tx_queues(vdev, queues); 4520 if (err) 4521 goto fwd_queue_err; 4522 4523 err = netif_set_real_num_rx_queues(vdev, queues); 4524 if (err) 4525 goto fwd_queue_err; 4526 4527 if (is_valid_ether_addr(vdev->dev_addr)) 4528 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool); 4529 4530 ixgbe_fwd_psrtype(accel); 4531 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter); 4532 return err; 4533 fwd_queue_err: 4534 ixgbe_fwd_ring_down(vdev, accel); 4535 return err; 4536 } 4537 4538 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 4539 { 4540 struct net_device *upper; 4541 struct list_head *iter; 4542 int err; 4543 4544 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { 4545 if (netif_is_macvlan(upper)) { 4546 struct macvlan_dev *dfwd = netdev_priv(upper); 4547 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; 4548 4549 if (dfwd->fwd_priv) { 4550 err = ixgbe_fwd_ring_up(upper, vadapter); 4551 if (err) 4552 continue; 4553 } 4554 } 4555 } 4556 } 4557 4558 static void ixgbe_configure(struct ixgbe_adapter *adapter) 4559 { 4560 struct ixgbe_hw *hw = &adapter->hw; 4561 4562 ixgbe_configure_pb(adapter); 4563 #ifdef CONFIG_IXGBE_DCB 4564 ixgbe_configure_dcb(adapter); 4565 #endif 4566 /* 4567 * We must restore virtualization before VLANs or else 4568 * the VLVF registers will not be populated 4569 */ 4570 ixgbe_configure_virtualization(adapter); 4571 4572 ixgbe_set_rx_mode(adapter->netdev); 4573 ixgbe_restore_vlan(adapter); 4574 4575 switch (hw->mac.type) { 4576 case ixgbe_mac_82599EB: 4577 case ixgbe_mac_X540: 4578 hw->mac.ops.disable_rx_buff(hw); 4579 break; 4580 default: 4581 break; 4582 } 4583 4584 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 4585 ixgbe_init_fdir_signature_82599(&adapter->hw, 4586 adapter->fdir_pballoc); 4587 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 4588 ixgbe_init_fdir_perfect_82599(&adapter->hw, 4589 adapter->fdir_pballoc); 4590 ixgbe_fdir_filter_restore(adapter); 4591 } 4592 4593 switch (hw->mac.type) { 4594 case ixgbe_mac_82599EB: 4595 case ixgbe_mac_X540: 4596 hw->mac.ops.enable_rx_buff(hw); 4597 break; 4598 default: 4599 break; 4600 } 4601 4602 #ifdef IXGBE_FCOE 4603 /* configure FCoE L2 filters, redirection table, and Rx control */ 4604 ixgbe_configure_fcoe(adapter); 4605 4606 #endif /* IXGBE_FCOE */ 4607 ixgbe_configure_tx(adapter); 4608 ixgbe_configure_rx(adapter); 4609 ixgbe_configure_dfwd(adapter); 4610 } 4611 4612 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 4613 { 4614 switch (hw->phy.type) { 4615 case ixgbe_phy_sfp_avago: 4616 case ixgbe_phy_sfp_ftl: 4617 case ixgbe_phy_sfp_intel: 4618 case ixgbe_phy_sfp_unknown: 4619 case ixgbe_phy_sfp_passive_tyco: 4620 case ixgbe_phy_sfp_passive_unknown: 4621 case ixgbe_phy_sfp_active_unknown: 4622 case ixgbe_phy_sfp_ftl_active: 4623 case ixgbe_phy_qsfp_passive_unknown: 4624 case ixgbe_phy_qsfp_active_unknown: 4625 case ixgbe_phy_qsfp_intel: 4626 case ixgbe_phy_qsfp_unknown: 4627 /* ixgbe_phy_none is set when no SFP module is present */ 4628 case ixgbe_phy_none: 4629 return true; 4630 case ixgbe_phy_nl: 4631 if (hw->mac.type == ixgbe_mac_82598EB) 4632 return true; 4633 default: 4634 return false; 4635 } 4636 } 4637 4638 /** 4639 * ixgbe_sfp_link_config - set up SFP+ link 4640 * @adapter: pointer to private adapter struct 4641 **/ 4642 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 4643 { 4644 /* 4645 * We are assuming the worst case scenario here, and that 4646 * is that an SFP was inserted/removed after the reset 4647 * but before SFP detection was enabled. As such the best 4648 * solution is to just start searching as soon as we start 4649 */ 4650 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 4651 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 4652 4653 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 4654 } 4655 4656 /** 4657 * ixgbe_non_sfp_link_config - set up non-SFP+ link 4658 * @hw: pointer to private hardware struct 4659 * 4660 * Returns 0 on success, negative on failure 4661 **/ 4662 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 4663 { 4664 u32 speed; 4665 bool autoneg, link_up = false; 4666 u32 ret = IXGBE_ERR_LINK_SETUP; 4667 4668 if (hw->mac.ops.check_link) 4669 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 4670 4671 if (ret) 4672 return ret; 4673 4674 speed = hw->phy.autoneg_advertised; 4675 if ((!speed) && (hw->mac.ops.get_link_capabilities)) 4676 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 4677 &autoneg); 4678 if (ret) 4679 return ret; 4680 4681 if (hw->mac.ops.setup_link) 4682 ret = hw->mac.ops.setup_link(hw, speed, link_up); 4683 4684 return ret; 4685 } 4686 4687 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 4688 { 4689 struct ixgbe_hw *hw = &adapter->hw; 4690 u32 gpie = 0; 4691 4692 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 4693 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 4694 IXGBE_GPIE_OCD; 4695 gpie |= IXGBE_GPIE_EIAME; 4696 /* 4697 * use EIAM to auto-mask when MSI-X interrupt is asserted 4698 * this saves a register write for every interrupt 4699 */ 4700 switch (hw->mac.type) { 4701 case ixgbe_mac_82598EB: 4702 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 4703 break; 4704 case ixgbe_mac_82599EB: 4705 case ixgbe_mac_X540: 4706 case ixgbe_mac_X550: 4707 case ixgbe_mac_X550EM_x: 4708 default: 4709 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 4710 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 4711 break; 4712 } 4713 } else { 4714 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 4715 * specifically only auto mask tx and rx interrupts */ 4716 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 4717 } 4718 4719 /* XXX: to interrupt immediately for EICS writes, enable this */ 4720 /* gpie |= IXGBE_GPIE_EIMEN; */ 4721 4722 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 4723 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 4724 4725 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4726 case IXGBE_82599_VMDQ_8Q_MASK: 4727 gpie |= IXGBE_GPIE_VTMODE_16; 4728 break; 4729 case IXGBE_82599_VMDQ_4Q_MASK: 4730 gpie |= IXGBE_GPIE_VTMODE_32; 4731 break; 4732 default: 4733 gpie |= IXGBE_GPIE_VTMODE_64; 4734 break; 4735 } 4736 } 4737 4738 /* Enable Thermal over heat sensor interrupt */ 4739 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 4740 switch (adapter->hw.mac.type) { 4741 case ixgbe_mac_82599EB: 4742 gpie |= IXGBE_SDP0_GPIEN; 4743 break; 4744 case ixgbe_mac_X540: 4745 gpie |= IXGBE_EIMS_TS; 4746 break; 4747 default: 4748 break; 4749 } 4750 } 4751 4752 /* Enable fan failure interrupt */ 4753 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 4754 gpie |= IXGBE_SDP1_GPIEN; 4755 4756 if (hw->mac.type == ixgbe_mac_82599EB) { 4757 gpie |= IXGBE_SDP1_GPIEN; 4758 gpie |= IXGBE_SDP2_GPIEN; 4759 } 4760 4761 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 4762 } 4763 4764 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 4765 { 4766 struct ixgbe_hw *hw = &adapter->hw; 4767 int err; 4768 u32 ctrl_ext; 4769 4770 ixgbe_get_hw_control(adapter); 4771 ixgbe_setup_gpie(adapter); 4772 4773 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 4774 ixgbe_configure_msix(adapter); 4775 else 4776 ixgbe_configure_msi_and_legacy(adapter); 4777 4778 /* enable the optics for 82599 SFP+ fiber */ 4779 if (hw->mac.ops.enable_tx_laser) 4780 hw->mac.ops.enable_tx_laser(hw); 4781 4782 smp_mb__before_atomic(); 4783 clear_bit(__IXGBE_DOWN, &adapter->state); 4784 ixgbe_napi_enable_all(adapter); 4785 4786 if (ixgbe_is_sfp(hw)) { 4787 ixgbe_sfp_link_config(adapter); 4788 } else { 4789 err = ixgbe_non_sfp_link_config(hw); 4790 if (err) 4791 e_err(probe, "link_config FAILED %d\n", err); 4792 } 4793 4794 /* clear any pending interrupts, may auto mask */ 4795 IXGBE_READ_REG(hw, IXGBE_EICR); 4796 ixgbe_irq_enable(adapter, true, true); 4797 4798 /* 4799 * If this adapter has a fan, check to see if we had a failure 4800 * before we enabled the interrupt. 4801 */ 4802 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 4803 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 4804 if (esdp & IXGBE_ESDP_SDP1) 4805 e_crit(drv, "Fan has stopped, replace the adapter\n"); 4806 } 4807 4808 /* bring the link up in the watchdog, this could race with our first 4809 * link up interrupt but shouldn't be a problem */ 4810 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 4811 adapter->link_check_timeout = jiffies; 4812 mod_timer(&adapter->service_timer, jiffies); 4813 4814 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 4815 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 4816 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 4817 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 4818 } 4819 4820 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 4821 { 4822 WARN_ON(in_interrupt()); 4823 /* put off any impending NetWatchDogTimeout */ 4824 adapter->netdev->trans_start = jiffies; 4825 4826 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 4827 usleep_range(1000, 2000); 4828 ixgbe_down(adapter); 4829 /* 4830 * If SR-IOV enabled then wait a bit before bringing the adapter 4831 * back up to give the VFs time to respond to the reset. The 4832 * two second wait is based upon the watchdog timer cycle in 4833 * the VF driver. 4834 */ 4835 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 4836 msleep(2000); 4837 ixgbe_up(adapter); 4838 clear_bit(__IXGBE_RESETTING, &adapter->state); 4839 } 4840 4841 void ixgbe_up(struct ixgbe_adapter *adapter) 4842 { 4843 /* hardware has been reset, we need to reload some things */ 4844 ixgbe_configure(adapter); 4845 4846 ixgbe_up_complete(adapter); 4847 } 4848 4849 void ixgbe_reset(struct ixgbe_adapter *adapter) 4850 { 4851 struct ixgbe_hw *hw = &adapter->hw; 4852 struct net_device *netdev = adapter->netdev; 4853 int err; 4854 u8 old_addr[ETH_ALEN]; 4855 4856 if (ixgbe_removed(hw->hw_addr)) 4857 return; 4858 /* lock SFP init bit to prevent race conditions with the watchdog */ 4859 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 4860 usleep_range(1000, 2000); 4861 4862 /* clear all SFP and link config related flags while holding SFP_INIT */ 4863 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 4864 IXGBE_FLAG2_SFP_NEEDS_RESET); 4865 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 4866 4867 err = hw->mac.ops.init_hw(hw); 4868 switch (err) { 4869 case 0: 4870 case IXGBE_ERR_SFP_NOT_PRESENT: 4871 case IXGBE_ERR_SFP_NOT_SUPPORTED: 4872 break; 4873 case IXGBE_ERR_MASTER_REQUESTS_PENDING: 4874 e_dev_err("master disable timed out\n"); 4875 break; 4876 case IXGBE_ERR_EEPROM_VERSION: 4877 /* We are running on a pre-production device, log a warning */ 4878 e_dev_warn("This device is a pre-production adapter/LOM. " 4879 "Please be aware there may be issues associated with " 4880 "your hardware. If you are experiencing problems " 4881 "please contact your Intel or hardware " 4882 "representative who provided you with this " 4883 "hardware.\n"); 4884 break; 4885 default: 4886 e_dev_err("Hardware Error: %d\n", err); 4887 } 4888 4889 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 4890 /* do not flush user set addresses */ 4891 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len); 4892 ixgbe_flush_sw_mac_table(adapter); 4893 ixgbe_mac_set_default_filter(adapter, old_addr); 4894 4895 /* update SAN MAC vmdq pool selection */ 4896 if (hw->mac.san_mac_rar_index) 4897 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 4898 4899 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 4900 ixgbe_ptp_reset(adapter); 4901 } 4902 4903 /** 4904 * ixgbe_clean_tx_ring - Free Tx Buffers 4905 * @tx_ring: ring to be cleaned 4906 **/ 4907 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 4908 { 4909 struct ixgbe_tx_buffer *tx_buffer_info; 4910 unsigned long size; 4911 u16 i; 4912 4913 /* ring already cleared, nothing to do */ 4914 if (!tx_ring->tx_buffer_info) 4915 return; 4916 4917 /* Free all the Tx ring sk_buffs */ 4918 for (i = 0; i < tx_ring->count; i++) { 4919 tx_buffer_info = &tx_ring->tx_buffer_info[i]; 4920 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); 4921 } 4922 4923 netdev_tx_reset_queue(txring_txq(tx_ring)); 4924 4925 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 4926 memset(tx_ring->tx_buffer_info, 0, size); 4927 4928 /* Zero out the descriptor ring */ 4929 memset(tx_ring->desc, 0, tx_ring->size); 4930 4931 tx_ring->next_to_use = 0; 4932 tx_ring->next_to_clean = 0; 4933 } 4934 4935 /** 4936 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 4937 * @adapter: board private structure 4938 **/ 4939 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 4940 { 4941 int i; 4942 4943 for (i = 0; i < adapter->num_rx_queues; i++) 4944 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 4945 } 4946 4947 /** 4948 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 4949 * @adapter: board private structure 4950 **/ 4951 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 4952 { 4953 int i; 4954 4955 for (i = 0; i < adapter->num_tx_queues; i++) 4956 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 4957 } 4958 4959 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 4960 { 4961 struct hlist_node *node2; 4962 struct ixgbe_fdir_filter *filter; 4963 4964 spin_lock(&adapter->fdir_perfect_lock); 4965 4966 hlist_for_each_entry_safe(filter, node2, 4967 &adapter->fdir_filter_list, fdir_node) { 4968 hlist_del(&filter->fdir_node); 4969 kfree(filter); 4970 } 4971 adapter->fdir_filter_count = 0; 4972 4973 spin_unlock(&adapter->fdir_perfect_lock); 4974 } 4975 4976 void ixgbe_down(struct ixgbe_adapter *adapter) 4977 { 4978 struct net_device *netdev = adapter->netdev; 4979 struct ixgbe_hw *hw = &adapter->hw; 4980 struct net_device *upper; 4981 struct list_head *iter; 4982 u32 rxctrl; 4983 int i; 4984 4985 /* signal that we are down to the interrupt handler */ 4986 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 4987 return; /* do nothing if already down */ 4988 4989 /* disable receives */ 4990 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4991 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); 4992 4993 /* disable all enabled rx queues */ 4994 for (i = 0; i < adapter->num_rx_queues; i++) 4995 /* this call also flushes the previous write */ 4996 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); 4997 4998 usleep_range(10000, 20000); 4999 5000 netif_tx_stop_all_queues(netdev); 5001 5002 /* call carrier off first to avoid false dev_watchdog timeouts */ 5003 netif_carrier_off(netdev); 5004 netif_tx_disable(netdev); 5005 5006 /* disable any upper devices */ 5007 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { 5008 if (netif_is_macvlan(upper)) { 5009 struct macvlan_dev *vlan = netdev_priv(upper); 5010 5011 if (vlan->fwd_priv) { 5012 netif_tx_stop_all_queues(upper); 5013 netif_carrier_off(upper); 5014 netif_tx_disable(upper); 5015 } 5016 } 5017 } 5018 5019 ixgbe_irq_disable(adapter); 5020 5021 ixgbe_napi_disable_all(adapter); 5022 5023 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT | 5024 IXGBE_FLAG2_RESET_REQUESTED); 5025 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 5026 5027 del_timer_sync(&adapter->service_timer); 5028 5029 if (adapter->num_vfs) { 5030 /* Clear EITR Select mapping */ 5031 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 5032 5033 /* Mark all the VFs as inactive */ 5034 for (i = 0 ; i < adapter->num_vfs; i++) 5035 adapter->vfinfo[i].clear_to_send = false; 5036 5037 /* ping all the active vfs to let them know we are going down */ 5038 ixgbe_ping_all_vfs(adapter); 5039 5040 /* Disable all VFTE/VFRE TX/RX */ 5041 ixgbe_disable_tx_rx(adapter); 5042 } 5043 5044 /* disable transmits in the hardware now that interrupts are off */ 5045 for (i = 0; i < adapter->num_tx_queues; i++) { 5046 u8 reg_idx = adapter->tx_ring[i]->reg_idx; 5047 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5048 } 5049 5050 /* Disable the Tx DMA engine on 82599 and later MAC */ 5051 switch (hw->mac.type) { 5052 case ixgbe_mac_82599EB: 5053 case ixgbe_mac_X540: 5054 case ixgbe_mac_X550: 5055 case ixgbe_mac_X550EM_x: 5056 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5057 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5058 ~IXGBE_DMATXCTL_TE)); 5059 break; 5060 default: 5061 break; 5062 } 5063 5064 if (!pci_channel_offline(adapter->pdev)) 5065 ixgbe_reset(adapter); 5066 5067 /* power down the optics for 82599 SFP+ fiber */ 5068 if (hw->mac.ops.disable_tx_laser) 5069 hw->mac.ops.disable_tx_laser(hw); 5070 5071 ixgbe_clean_all_tx_rings(adapter); 5072 ixgbe_clean_all_rx_rings(adapter); 5073 5074 #ifdef CONFIG_IXGBE_DCA 5075 /* since we reset the hardware DCA settings were cleared */ 5076 ixgbe_setup_dca(adapter); 5077 #endif 5078 } 5079 5080 /** 5081 * ixgbe_tx_timeout - Respond to a Tx Hang 5082 * @netdev: network interface device structure 5083 **/ 5084 static void ixgbe_tx_timeout(struct net_device *netdev) 5085 { 5086 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5087 5088 /* Do the reset outside of interrupt context */ 5089 ixgbe_tx_timeout_reset(adapter); 5090 } 5091 5092 /** 5093 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 5094 * @adapter: board private structure to initialize 5095 * 5096 * ixgbe_sw_init initializes the Adapter private data structure. 5097 * Fields are initialized based on PCI device information and 5098 * OS network device settings (MTU size). 5099 **/ 5100 static int ixgbe_sw_init(struct ixgbe_adapter *adapter) 5101 { 5102 struct ixgbe_hw *hw = &adapter->hw; 5103 struct pci_dev *pdev = adapter->pdev; 5104 unsigned int rss, fdir; 5105 u32 fwsm; 5106 #ifdef CONFIG_IXGBE_DCB 5107 int j; 5108 struct tc_configuration *tc; 5109 #endif 5110 5111 /* PCI config space info */ 5112 5113 hw->vendor_id = pdev->vendor; 5114 hw->device_id = pdev->device; 5115 hw->revision_id = pdev->revision; 5116 hw->subsystem_vendor_id = pdev->subsystem_vendor; 5117 hw->subsystem_device_id = pdev->subsystem_device; 5118 5119 /* Set common capability flags and settings */ 5120 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 5121 adapter->ring_feature[RING_F_RSS].limit = rss; 5122 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 5123 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 5124 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 5125 adapter->atr_sample_rate = 20; 5126 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 5127 adapter->ring_feature[RING_F_FDIR].limit = fdir; 5128 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 5129 #ifdef CONFIG_IXGBE_DCA 5130 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 5131 #endif 5132 #ifdef IXGBE_FCOE 5133 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 5134 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 5135 #ifdef CONFIG_IXGBE_DCB 5136 /* Default traffic class to use for FCoE */ 5137 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 5138 #endif /* CONFIG_IXGBE_DCB */ 5139 #endif /* IXGBE_FCOE */ 5140 5141 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) * 5142 hw->mac.num_rar_entries, 5143 GFP_ATOMIC); 5144 5145 /* Set MAC specific capability flags and exceptions */ 5146 switch (hw->mac.type) { 5147 case ixgbe_mac_82598EB: 5148 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 5149 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 5150 5151 if (hw->device_id == IXGBE_DEV_ID_82598AT) 5152 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 5153 5154 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 5155 adapter->ring_feature[RING_F_FDIR].limit = 0; 5156 adapter->atr_sample_rate = 0; 5157 adapter->fdir_pballoc = 0; 5158 #ifdef IXGBE_FCOE 5159 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 5160 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 5161 #ifdef CONFIG_IXGBE_DCB 5162 adapter->fcoe.up = 0; 5163 #endif /* IXGBE_DCB */ 5164 #endif /* IXGBE_FCOE */ 5165 break; 5166 case ixgbe_mac_82599EB: 5167 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 5168 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 5169 break; 5170 case ixgbe_mac_X540: 5171 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM); 5172 if (fwsm & IXGBE_FWSM_TS_ENABLED) 5173 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 5174 break; 5175 case ixgbe_mac_X550EM_x: 5176 case ixgbe_mac_X550: 5177 #ifdef CONFIG_IXGBE_DCA 5178 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 5179 #endif 5180 break; 5181 default: 5182 break; 5183 } 5184 5185 #ifdef IXGBE_FCOE 5186 /* FCoE support exists, always init the FCoE lock */ 5187 spin_lock_init(&adapter->fcoe.lock); 5188 5189 #endif 5190 /* n-tuple support exists, always init our spinlock */ 5191 spin_lock_init(&adapter->fdir_perfect_lock); 5192 5193 #ifdef CONFIG_IXGBE_DCB 5194 switch (hw->mac.type) { 5195 case ixgbe_mac_X540: 5196 case ixgbe_mac_X550: 5197 case ixgbe_mac_X550EM_x: 5198 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 5199 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 5200 break; 5201 default: 5202 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 5203 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 5204 break; 5205 } 5206 5207 /* Configure DCB traffic classes */ 5208 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 5209 tc = &adapter->dcb_cfg.tc_config[j]; 5210 tc->path[DCB_TX_CONFIG].bwg_id = 0; 5211 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 5212 tc->path[DCB_RX_CONFIG].bwg_id = 0; 5213 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 5214 tc->dcb_pfc = pfc_disabled; 5215 } 5216 5217 /* Initialize default user to priority mapping, UPx->TC0 */ 5218 tc = &adapter->dcb_cfg.tc_config[0]; 5219 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 5220 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 5221 5222 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 5223 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 5224 adapter->dcb_cfg.pfc_mode_enable = false; 5225 adapter->dcb_set_bitmap = 0x00; 5226 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 5227 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 5228 sizeof(adapter->temp_dcb_cfg)); 5229 5230 #endif 5231 5232 /* default flow control settings */ 5233 hw->fc.requested_mode = ixgbe_fc_full; 5234 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 5235 ixgbe_pbthresh_setup(adapter); 5236 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 5237 hw->fc.send_xon = true; 5238 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 5239 5240 #ifdef CONFIG_PCI_IOV 5241 if (max_vfs > 0) 5242 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 5243 5244 /* assign number of SR-IOV VFs */ 5245 if (hw->mac.type != ixgbe_mac_82598EB) { 5246 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 5247 adapter->num_vfs = 0; 5248 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 5249 } else { 5250 adapter->num_vfs = max_vfs; 5251 } 5252 } 5253 #endif /* CONFIG_PCI_IOV */ 5254 5255 /* enable itr by default in dynamic mode */ 5256 adapter->rx_itr_setting = 1; 5257 adapter->tx_itr_setting = 1; 5258 5259 /* set default ring sizes */ 5260 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 5261 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 5262 5263 /* set default work limits */ 5264 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 5265 5266 /* initialize eeprom parameters */ 5267 if (ixgbe_init_eeprom_params_generic(hw)) { 5268 e_dev_err("EEPROM initialization failed\n"); 5269 return -EIO; 5270 } 5271 5272 /* PF holds first pool slot */ 5273 set_bit(0, &adapter->fwd_bitmask); 5274 set_bit(__IXGBE_DOWN, &adapter->state); 5275 5276 return 0; 5277 } 5278 5279 /** 5280 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 5281 * @tx_ring: tx descriptor ring (for a specific queue) to setup 5282 * 5283 * Return 0 on success, negative on failure 5284 **/ 5285 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 5286 { 5287 struct device *dev = tx_ring->dev; 5288 int orig_node = dev_to_node(dev); 5289 int ring_node = -1; 5290 int size; 5291 5292 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 5293 5294 if (tx_ring->q_vector) 5295 ring_node = tx_ring->q_vector->numa_node; 5296 5297 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node); 5298 if (!tx_ring->tx_buffer_info) 5299 tx_ring->tx_buffer_info = vzalloc(size); 5300 if (!tx_ring->tx_buffer_info) 5301 goto err; 5302 5303 u64_stats_init(&tx_ring->syncp); 5304 5305 /* round up to nearest 4K */ 5306 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 5307 tx_ring->size = ALIGN(tx_ring->size, 4096); 5308 5309 set_dev_node(dev, ring_node); 5310 tx_ring->desc = dma_alloc_coherent(dev, 5311 tx_ring->size, 5312 &tx_ring->dma, 5313 GFP_KERNEL); 5314 set_dev_node(dev, orig_node); 5315 if (!tx_ring->desc) 5316 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 5317 &tx_ring->dma, GFP_KERNEL); 5318 if (!tx_ring->desc) 5319 goto err; 5320 5321 tx_ring->next_to_use = 0; 5322 tx_ring->next_to_clean = 0; 5323 return 0; 5324 5325 err: 5326 vfree(tx_ring->tx_buffer_info); 5327 tx_ring->tx_buffer_info = NULL; 5328 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 5329 return -ENOMEM; 5330 } 5331 5332 /** 5333 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 5334 * @adapter: board private structure 5335 * 5336 * If this function returns with an error, then it's possible one or 5337 * more of the rings is populated (while the rest are not). It is the 5338 * callers duty to clean those orphaned rings. 5339 * 5340 * Return 0 on success, negative on failure 5341 **/ 5342 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 5343 { 5344 int i, err = 0; 5345 5346 for (i = 0; i < adapter->num_tx_queues; i++) { 5347 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 5348 if (!err) 5349 continue; 5350 5351 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 5352 goto err_setup_tx; 5353 } 5354 5355 return 0; 5356 err_setup_tx: 5357 /* rewind the index freeing the rings as we go */ 5358 while (i--) 5359 ixgbe_free_tx_resources(adapter->tx_ring[i]); 5360 return err; 5361 } 5362 5363 /** 5364 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 5365 * @rx_ring: rx descriptor ring (for a specific queue) to setup 5366 * 5367 * Returns 0 on success, negative on failure 5368 **/ 5369 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring) 5370 { 5371 struct device *dev = rx_ring->dev; 5372 int orig_node = dev_to_node(dev); 5373 int ring_node = -1; 5374 int size; 5375 5376 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 5377 5378 if (rx_ring->q_vector) 5379 ring_node = rx_ring->q_vector->numa_node; 5380 5381 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node); 5382 if (!rx_ring->rx_buffer_info) 5383 rx_ring->rx_buffer_info = vzalloc(size); 5384 if (!rx_ring->rx_buffer_info) 5385 goto err; 5386 5387 u64_stats_init(&rx_ring->syncp); 5388 5389 /* Round up to nearest 4K */ 5390 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 5391 rx_ring->size = ALIGN(rx_ring->size, 4096); 5392 5393 set_dev_node(dev, ring_node); 5394 rx_ring->desc = dma_alloc_coherent(dev, 5395 rx_ring->size, 5396 &rx_ring->dma, 5397 GFP_KERNEL); 5398 set_dev_node(dev, orig_node); 5399 if (!rx_ring->desc) 5400 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 5401 &rx_ring->dma, GFP_KERNEL); 5402 if (!rx_ring->desc) 5403 goto err; 5404 5405 rx_ring->next_to_clean = 0; 5406 rx_ring->next_to_use = 0; 5407 5408 return 0; 5409 err: 5410 vfree(rx_ring->rx_buffer_info); 5411 rx_ring->rx_buffer_info = NULL; 5412 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 5413 return -ENOMEM; 5414 } 5415 5416 /** 5417 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 5418 * @adapter: board private structure 5419 * 5420 * If this function returns with an error, then it's possible one or 5421 * more of the rings is populated (while the rest are not). It is the 5422 * callers duty to clean those orphaned rings. 5423 * 5424 * Return 0 on success, negative on failure 5425 **/ 5426 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 5427 { 5428 int i, err = 0; 5429 5430 for (i = 0; i < adapter->num_rx_queues; i++) { 5431 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]); 5432 if (!err) 5433 continue; 5434 5435 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 5436 goto err_setup_rx; 5437 } 5438 5439 #ifdef IXGBE_FCOE 5440 err = ixgbe_setup_fcoe_ddp_resources(adapter); 5441 if (!err) 5442 #endif 5443 return 0; 5444 err_setup_rx: 5445 /* rewind the index freeing the rings as we go */ 5446 while (i--) 5447 ixgbe_free_rx_resources(adapter->rx_ring[i]); 5448 return err; 5449 } 5450 5451 /** 5452 * ixgbe_free_tx_resources - Free Tx Resources per Queue 5453 * @tx_ring: Tx descriptor ring for a specific queue 5454 * 5455 * Free all transmit software resources 5456 **/ 5457 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 5458 { 5459 ixgbe_clean_tx_ring(tx_ring); 5460 5461 vfree(tx_ring->tx_buffer_info); 5462 tx_ring->tx_buffer_info = NULL; 5463 5464 /* if not set, then don't free */ 5465 if (!tx_ring->desc) 5466 return; 5467 5468 dma_free_coherent(tx_ring->dev, tx_ring->size, 5469 tx_ring->desc, tx_ring->dma); 5470 5471 tx_ring->desc = NULL; 5472 } 5473 5474 /** 5475 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 5476 * @adapter: board private structure 5477 * 5478 * Free all transmit software resources 5479 **/ 5480 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 5481 { 5482 int i; 5483 5484 for (i = 0; i < adapter->num_tx_queues; i++) 5485 if (adapter->tx_ring[i]->desc) 5486 ixgbe_free_tx_resources(adapter->tx_ring[i]); 5487 } 5488 5489 /** 5490 * ixgbe_free_rx_resources - Free Rx Resources 5491 * @rx_ring: ring to clean the resources from 5492 * 5493 * Free all receive software resources 5494 **/ 5495 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 5496 { 5497 ixgbe_clean_rx_ring(rx_ring); 5498 5499 vfree(rx_ring->rx_buffer_info); 5500 rx_ring->rx_buffer_info = NULL; 5501 5502 /* if not set, then don't free */ 5503 if (!rx_ring->desc) 5504 return; 5505 5506 dma_free_coherent(rx_ring->dev, rx_ring->size, 5507 rx_ring->desc, rx_ring->dma); 5508 5509 rx_ring->desc = NULL; 5510 } 5511 5512 /** 5513 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 5514 * @adapter: board private structure 5515 * 5516 * Free all receive software resources 5517 **/ 5518 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 5519 { 5520 int i; 5521 5522 #ifdef IXGBE_FCOE 5523 ixgbe_free_fcoe_ddp_resources(adapter); 5524 5525 #endif 5526 for (i = 0; i < adapter->num_rx_queues; i++) 5527 if (adapter->rx_ring[i]->desc) 5528 ixgbe_free_rx_resources(adapter->rx_ring[i]); 5529 } 5530 5531 /** 5532 * ixgbe_change_mtu - Change the Maximum Transfer Unit 5533 * @netdev: network interface device structure 5534 * @new_mtu: new value for maximum frame size 5535 * 5536 * Returns 0 on success, negative on failure 5537 **/ 5538 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 5539 { 5540 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5541 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; 5542 5543 /* MTU < 68 is an error and causes problems on some kernels */ 5544 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) 5545 return -EINVAL; 5546 5547 /* 5548 * For 82599EB we cannot allow legacy VFs to enable their receive 5549 * paths when MTU greater than 1500 is configured. So display a 5550 * warning that legacy VFs will be disabled. 5551 */ 5552 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 5553 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 5554 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 5555 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 5556 5557 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); 5558 5559 /* must set new MTU before calling down or up */ 5560 netdev->mtu = new_mtu; 5561 5562 if (netif_running(netdev)) 5563 ixgbe_reinit_locked(adapter); 5564 5565 return 0; 5566 } 5567 5568 /** 5569 * ixgbe_open - Called when a network interface is made active 5570 * @netdev: network interface device structure 5571 * 5572 * Returns 0 on success, negative value on failure 5573 * 5574 * The open entry point is called when a network interface is made 5575 * active by the system (IFF_UP). At this point all resources needed 5576 * for transmit and receive operations are allocated, the interrupt 5577 * handler is registered with the OS, the watchdog timer is started, 5578 * and the stack is notified that the interface is ready. 5579 **/ 5580 static int ixgbe_open(struct net_device *netdev) 5581 { 5582 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5583 int err, queues; 5584 5585 /* disallow open during test */ 5586 if (test_bit(__IXGBE_TESTING, &adapter->state)) 5587 return -EBUSY; 5588 5589 netif_carrier_off(netdev); 5590 5591 /* allocate transmit descriptors */ 5592 err = ixgbe_setup_all_tx_resources(adapter); 5593 if (err) 5594 goto err_setup_tx; 5595 5596 /* allocate receive descriptors */ 5597 err = ixgbe_setup_all_rx_resources(adapter); 5598 if (err) 5599 goto err_setup_rx; 5600 5601 ixgbe_configure(adapter); 5602 5603 err = ixgbe_request_irq(adapter); 5604 if (err) 5605 goto err_req_irq; 5606 5607 /* Notify the stack of the actual queue counts. */ 5608 if (adapter->num_rx_pools > 1) 5609 queues = adapter->num_rx_queues_per_pool; 5610 else 5611 queues = adapter->num_tx_queues; 5612 5613 err = netif_set_real_num_tx_queues(netdev, queues); 5614 if (err) 5615 goto err_set_queues; 5616 5617 if (adapter->num_rx_pools > 1 && 5618 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES) 5619 queues = IXGBE_MAX_L2A_QUEUES; 5620 else 5621 queues = adapter->num_rx_queues; 5622 err = netif_set_real_num_rx_queues(netdev, queues); 5623 if (err) 5624 goto err_set_queues; 5625 5626 ixgbe_ptp_init(adapter); 5627 5628 ixgbe_up_complete(adapter); 5629 5630 return 0; 5631 5632 err_set_queues: 5633 ixgbe_free_irq(adapter); 5634 err_req_irq: 5635 ixgbe_free_all_rx_resources(adapter); 5636 err_setup_rx: 5637 ixgbe_free_all_tx_resources(adapter); 5638 err_setup_tx: 5639 ixgbe_reset(adapter); 5640 5641 return err; 5642 } 5643 5644 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 5645 { 5646 ixgbe_ptp_suspend(adapter); 5647 5648 ixgbe_down(adapter); 5649 ixgbe_free_irq(adapter); 5650 5651 ixgbe_free_all_tx_resources(adapter); 5652 ixgbe_free_all_rx_resources(adapter); 5653 } 5654 5655 /** 5656 * ixgbe_close - Disables a network interface 5657 * @netdev: network interface device structure 5658 * 5659 * Returns 0, this is not allowed to fail 5660 * 5661 * The close entry point is called when an interface is de-activated 5662 * by the OS. The hardware is still under the drivers control, but 5663 * needs to be disabled. A global MAC reset is issued to stop the 5664 * hardware, and all transmit and receive resources are freed. 5665 **/ 5666 static int ixgbe_close(struct net_device *netdev) 5667 { 5668 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5669 5670 ixgbe_ptp_stop(adapter); 5671 5672 ixgbe_close_suspend(adapter); 5673 5674 ixgbe_fdir_filter_exit(adapter); 5675 5676 ixgbe_release_hw_control(adapter); 5677 5678 return 0; 5679 } 5680 5681 #ifdef CONFIG_PM 5682 static int ixgbe_resume(struct pci_dev *pdev) 5683 { 5684 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 5685 struct net_device *netdev = adapter->netdev; 5686 u32 err; 5687 5688 adapter->hw.hw_addr = adapter->io_addr; 5689 pci_set_power_state(pdev, PCI_D0); 5690 pci_restore_state(pdev); 5691 /* 5692 * pci_restore_state clears dev->state_saved so call 5693 * pci_save_state to restore it. 5694 */ 5695 pci_save_state(pdev); 5696 5697 err = pci_enable_device_mem(pdev); 5698 if (err) { 5699 e_dev_err("Cannot enable PCI device from suspend\n"); 5700 return err; 5701 } 5702 smp_mb__before_atomic(); 5703 clear_bit(__IXGBE_DISABLED, &adapter->state); 5704 pci_set_master(pdev); 5705 5706 pci_wake_from_d3(pdev, false); 5707 5708 ixgbe_reset(adapter); 5709 5710 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 5711 5712 rtnl_lock(); 5713 err = ixgbe_init_interrupt_scheme(adapter); 5714 if (!err && netif_running(netdev)) 5715 err = ixgbe_open(netdev); 5716 5717 rtnl_unlock(); 5718 5719 if (err) 5720 return err; 5721 5722 netif_device_attach(netdev); 5723 5724 return 0; 5725 } 5726 #endif /* CONFIG_PM */ 5727 5728 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 5729 { 5730 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 5731 struct net_device *netdev = adapter->netdev; 5732 struct ixgbe_hw *hw = &adapter->hw; 5733 u32 ctrl, fctrl; 5734 u32 wufc = adapter->wol; 5735 #ifdef CONFIG_PM 5736 int retval = 0; 5737 #endif 5738 5739 netif_device_detach(netdev); 5740 5741 rtnl_lock(); 5742 if (netif_running(netdev)) 5743 ixgbe_close_suspend(adapter); 5744 rtnl_unlock(); 5745 5746 ixgbe_clear_interrupt_scheme(adapter); 5747 5748 #ifdef CONFIG_PM 5749 retval = pci_save_state(pdev); 5750 if (retval) 5751 return retval; 5752 5753 #endif 5754 if (hw->mac.ops.stop_link_on_d3) 5755 hw->mac.ops.stop_link_on_d3(hw); 5756 5757 if (wufc) { 5758 ixgbe_set_rx_mode(netdev); 5759 5760 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 5761 if (hw->mac.ops.enable_tx_laser) 5762 hw->mac.ops.enable_tx_laser(hw); 5763 5764 /* turn on all-multi mode if wake on multicast is enabled */ 5765 if (wufc & IXGBE_WUFC_MC) { 5766 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 5767 fctrl |= IXGBE_FCTRL_MPE; 5768 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 5769 } 5770 5771 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 5772 ctrl |= IXGBE_CTRL_GIO_DIS; 5773 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 5774 5775 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 5776 } else { 5777 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 5778 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 5779 } 5780 5781 switch (hw->mac.type) { 5782 case ixgbe_mac_82598EB: 5783 pci_wake_from_d3(pdev, false); 5784 break; 5785 case ixgbe_mac_82599EB: 5786 case ixgbe_mac_X540: 5787 case ixgbe_mac_X550: 5788 case ixgbe_mac_X550EM_x: 5789 pci_wake_from_d3(pdev, !!wufc); 5790 break; 5791 default: 5792 break; 5793 } 5794 5795 *enable_wake = !!wufc; 5796 5797 ixgbe_release_hw_control(adapter); 5798 5799 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 5800 pci_disable_device(pdev); 5801 5802 return 0; 5803 } 5804 5805 #ifdef CONFIG_PM 5806 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) 5807 { 5808 int retval; 5809 bool wake; 5810 5811 retval = __ixgbe_shutdown(pdev, &wake); 5812 if (retval) 5813 return retval; 5814 5815 if (wake) { 5816 pci_prepare_to_sleep(pdev); 5817 } else { 5818 pci_wake_from_d3(pdev, false); 5819 pci_set_power_state(pdev, PCI_D3hot); 5820 } 5821 5822 return 0; 5823 } 5824 #endif /* CONFIG_PM */ 5825 5826 static void ixgbe_shutdown(struct pci_dev *pdev) 5827 { 5828 bool wake; 5829 5830 __ixgbe_shutdown(pdev, &wake); 5831 5832 if (system_state == SYSTEM_POWER_OFF) { 5833 pci_wake_from_d3(pdev, wake); 5834 pci_set_power_state(pdev, PCI_D3hot); 5835 } 5836 } 5837 5838 /** 5839 * ixgbe_update_stats - Update the board statistics counters. 5840 * @adapter: board private structure 5841 **/ 5842 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 5843 { 5844 struct net_device *netdev = adapter->netdev; 5845 struct ixgbe_hw *hw = &adapter->hw; 5846 struct ixgbe_hw_stats *hwstats = &adapter->stats; 5847 u64 total_mpc = 0; 5848 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 5849 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 5850 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 5851 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 5852 5853 if (test_bit(__IXGBE_DOWN, &adapter->state) || 5854 test_bit(__IXGBE_RESETTING, &adapter->state)) 5855 return; 5856 5857 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 5858 u64 rsc_count = 0; 5859 u64 rsc_flush = 0; 5860 for (i = 0; i < adapter->num_rx_queues; i++) { 5861 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 5862 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 5863 } 5864 adapter->rsc_total_count = rsc_count; 5865 adapter->rsc_total_flush = rsc_flush; 5866 } 5867 5868 for (i = 0; i < adapter->num_rx_queues; i++) { 5869 struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; 5870 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 5871 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 5872 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 5873 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 5874 bytes += rx_ring->stats.bytes; 5875 packets += rx_ring->stats.packets; 5876 } 5877 adapter->non_eop_descs = non_eop_descs; 5878 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 5879 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 5880 adapter->hw_csum_rx_error = hw_csum_rx_error; 5881 netdev->stats.rx_bytes = bytes; 5882 netdev->stats.rx_packets = packets; 5883 5884 bytes = 0; 5885 packets = 0; 5886 /* gather some stats to the adapter struct that are per queue */ 5887 for (i = 0; i < adapter->num_tx_queues; i++) { 5888 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 5889 restart_queue += tx_ring->tx_stats.restart_queue; 5890 tx_busy += tx_ring->tx_stats.tx_busy; 5891 bytes += tx_ring->stats.bytes; 5892 packets += tx_ring->stats.packets; 5893 } 5894 adapter->restart_queue = restart_queue; 5895 adapter->tx_busy = tx_busy; 5896 netdev->stats.tx_bytes = bytes; 5897 netdev->stats.tx_packets = packets; 5898 5899 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 5900 5901 /* 8 register reads */ 5902 for (i = 0; i < 8; i++) { 5903 /* for packet buffers not used, the register should read 0 */ 5904 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 5905 missed_rx += mpc; 5906 hwstats->mpc[i] += mpc; 5907 total_mpc += hwstats->mpc[i]; 5908 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 5909 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 5910 switch (hw->mac.type) { 5911 case ixgbe_mac_82598EB: 5912 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 5913 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 5914 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 5915 hwstats->pxonrxc[i] += 5916 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 5917 break; 5918 case ixgbe_mac_82599EB: 5919 case ixgbe_mac_X540: 5920 case ixgbe_mac_X550: 5921 case ixgbe_mac_X550EM_x: 5922 hwstats->pxonrxc[i] += 5923 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 5924 break; 5925 default: 5926 break; 5927 } 5928 } 5929 5930 /*16 register reads */ 5931 for (i = 0; i < 16; i++) { 5932 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 5933 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 5934 if ((hw->mac.type == ixgbe_mac_82599EB) || 5935 (hw->mac.type == ixgbe_mac_X540) || 5936 (hw->mac.type == ixgbe_mac_X550) || 5937 (hw->mac.type == ixgbe_mac_X550EM_x)) { 5938 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 5939 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 5940 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 5941 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 5942 } 5943 } 5944 5945 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 5946 /* work around hardware counting issue */ 5947 hwstats->gprc -= missed_rx; 5948 5949 ixgbe_update_xoff_received(adapter); 5950 5951 /* 82598 hardware only has a 32 bit counter in the high register */ 5952 switch (hw->mac.type) { 5953 case ixgbe_mac_82598EB: 5954 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 5955 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 5956 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 5957 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 5958 break; 5959 case ixgbe_mac_X540: 5960 case ixgbe_mac_X550: 5961 case ixgbe_mac_X550EM_x: 5962 /* OS2BMC stats are X540 and later */ 5963 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 5964 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 5965 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 5966 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 5967 case ixgbe_mac_82599EB: 5968 for (i = 0; i < 16; i++) 5969 adapter->hw_rx_no_dma_resources += 5970 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 5971 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 5972 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 5973 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 5974 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 5975 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 5976 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 5977 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 5978 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 5979 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 5980 #ifdef IXGBE_FCOE 5981 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 5982 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 5983 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 5984 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 5985 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 5986 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 5987 /* Add up per cpu counters for total ddp aloc fail */ 5988 if (adapter->fcoe.ddp_pool) { 5989 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 5990 struct ixgbe_fcoe_ddp_pool *ddp_pool; 5991 unsigned int cpu; 5992 u64 noddp = 0, noddp_ext_buff = 0; 5993 for_each_possible_cpu(cpu) { 5994 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 5995 noddp += ddp_pool->noddp; 5996 noddp_ext_buff += ddp_pool->noddp_ext_buff; 5997 } 5998 hwstats->fcoe_noddp = noddp; 5999 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 6000 } 6001 #endif /* IXGBE_FCOE */ 6002 break; 6003 default: 6004 break; 6005 } 6006 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 6007 hwstats->bprc += bprc; 6008 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 6009 if (hw->mac.type == ixgbe_mac_82598EB) 6010 hwstats->mprc -= bprc; 6011 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 6012 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 6013 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 6014 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 6015 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 6016 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 6017 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 6018 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 6019 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 6020 hwstats->lxontxc += lxon; 6021 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 6022 hwstats->lxofftxc += lxoff; 6023 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 6024 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 6025 /* 6026 * 82598 errata - tx of flow control packets is included in tx counters 6027 */ 6028 xon_off_tot = lxon + lxoff; 6029 hwstats->gptc -= xon_off_tot; 6030 hwstats->mptc -= xon_off_tot; 6031 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 6032 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 6033 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 6034 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 6035 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 6036 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 6037 hwstats->ptc64 -= xon_off_tot; 6038 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 6039 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 6040 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 6041 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 6042 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 6043 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 6044 6045 /* Fill out the OS statistics structure */ 6046 netdev->stats.multicast = hwstats->mprc; 6047 6048 /* Rx Errors */ 6049 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 6050 netdev->stats.rx_dropped = 0; 6051 netdev->stats.rx_length_errors = hwstats->rlec; 6052 netdev->stats.rx_crc_errors = hwstats->crcerrs; 6053 netdev->stats.rx_missed_errors = total_mpc; 6054 } 6055 6056 /** 6057 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 6058 * @adapter: pointer to the device adapter structure 6059 **/ 6060 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 6061 { 6062 struct ixgbe_hw *hw = &adapter->hw; 6063 int i; 6064 6065 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 6066 return; 6067 6068 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 6069 6070 /* if interface is down do nothing */ 6071 if (test_bit(__IXGBE_DOWN, &adapter->state)) 6072 return; 6073 6074 /* do nothing if we are not using signature filters */ 6075 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 6076 return; 6077 6078 adapter->fdir_overflow++; 6079 6080 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 6081 for (i = 0; i < adapter->num_tx_queues; i++) 6082 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 6083 &(adapter->tx_ring[i]->state)); 6084 /* re-enable flow director interrupts */ 6085 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 6086 } else { 6087 e_err(probe, "failed to finish FDIR re-initialization, " 6088 "ignored adding FDIR ATR filters\n"); 6089 } 6090 } 6091 6092 /** 6093 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 6094 * @adapter: pointer to the device adapter structure 6095 * 6096 * This function serves two purposes. First it strobes the interrupt lines 6097 * in order to make certain interrupts are occurring. Secondly it sets the 6098 * bits needed to check for TX hangs. As a result we should immediately 6099 * determine if a hang has occurred. 6100 */ 6101 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 6102 { 6103 struct ixgbe_hw *hw = &adapter->hw; 6104 u64 eics = 0; 6105 int i; 6106 6107 /* If we're down, removing or resetting, just bail */ 6108 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6109 test_bit(__IXGBE_REMOVING, &adapter->state) || 6110 test_bit(__IXGBE_RESETTING, &adapter->state)) 6111 return; 6112 6113 /* Force detection of hung controller */ 6114 if (netif_carrier_ok(adapter->netdev)) { 6115 for (i = 0; i < adapter->num_tx_queues; i++) 6116 set_check_for_tx_hang(adapter->tx_ring[i]); 6117 } 6118 6119 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 6120 /* 6121 * for legacy and MSI interrupts don't set any bits 6122 * that are enabled for EIAM, because this operation 6123 * would set *both* EIMS and EICS for any bit in EIAM 6124 */ 6125 IXGBE_WRITE_REG(hw, IXGBE_EICS, 6126 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 6127 } else { 6128 /* get one bit for every active tx/rx interrupt vector */ 6129 for (i = 0; i < adapter->num_q_vectors; i++) { 6130 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 6131 if (qv->rx.ring || qv->tx.ring) 6132 eics |= ((u64)1 << i); 6133 } 6134 } 6135 6136 /* Cause software interrupt to ensure rings are cleaned */ 6137 ixgbe_irq_rearm_queues(adapter, eics); 6138 6139 } 6140 6141 /** 6142 * ixgbe_watchdog_update_link - update the link status 6143 * @adapter: pointer to the device adapter structure 6144 * @link_speed: pointer to a u32 to store the link_speed 6145 **/ 6146 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 6147 { 6148 struct ixgbe_hw *hw = &adapter->hw; 6149 u32 link_speed = adapter->link_speed; 6150 bool link_up = adapter->link_up; 6151 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 6152 6153 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 6154 return; 6155 6156 if (hw->mac.ops.check_link) { 6157 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 6158 } else { 6159 /* always assume link is up, if no check link function */ 6160 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 6161 link_up = true; 6162 } 6163 6164 if (adapter->ixgbe_ieee_pfc) 6165 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 6166 6167 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 6168 hw->mac.ops.fc_enable(hw); 6169 ixgbe_set_rx_drop_en(adapter); 6170 } 6171 6172 if (link_up || 6173 time_after(jiffies, (adapter->link_check_timeout + 6174 IXGBE_TRY_LINK_TIMEOUT))) { 6175 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 6176 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 6177 IXGBE_WRITE_FLUSH(hw); 6178 } 6179 6180 adapter->link_up = link_up; 6181 adapter->link_speed = link_speed; 6182 } 6183 6184 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 6185 { 6186 #ifdef CONFIG_IXGBE_DCB 6187 struct net_device *netdev = adapter->netdev; 6188 struct dcb_app app = { 6189 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 6190 .protocol = 0, 6191 }; 6192 u8 up = 0; 6193 6194 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 6195 up = dcb_ieee_getapp_mask(netdev, &app); 6196 6197 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 6198 #endif 6199 } 6200 6201 /** 6202 * ixgbe_watchdog_link_is_up - update netif_carrier status and 6203 * print link up message 6204 * @adapter: pointer to the device adapter structure 6205 **/ 6206 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 6207 { 6208 struct net_device *netdev = adapter->netdev; 6209 struct ixgbe_hw *hw = &adapter->hw; 6210 struct net_device *upper; 6211 struct list_head *iter; 6212 u32 link_speed = adapter->link_speed; 6213 bool flow_rx, flow_tx; 6214 6215 /* only continue if link was previously down */ 6216 if (netif_carrier_ok(netdev)) 6217 return; 6218 6219 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 6220 6221 switch (hw->mac.type) { 6222 case ixgbe_mac_82598EB: { 6223 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6224 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 6225 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 6226 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 6227 } 6228 break; 6229 case ixgbe_mac_X540: 6230 case ixgbe_mac_X550: 6231 case ixgbe_mac_X550EM_x: 6232 case ixgbe_mac_82599EB: { 6233 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 6234 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 6235 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 6236 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 6237 } 6238 break; 6239 default: 6240 flow_tx = false; 6241 flow_rx = false; 6242 break; 6243 } 6244 6245 adapter->last_rx_ptp_check = jiffies; 6246 6247 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 6248 ixgbe_ptp_start_cyclecounter(adapter); 6249 6250 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", 6251 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? 6252 "10 Gbps" : 6253 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? 6254 "1 Gbps" : 6255 (link_speed == IXGBE_LINK_SPEED_100_FULL ? 6256 "100 Mbps" : 6257 "unknown speed"))), 6258 ((flow_rx && flow_tx) ? "RX/TX" : 6259 (flow_rx ? "RX" : 6260 (flow_tx ? "TX" : "None")))); 6261 6262 netif_carrier_on(netdev); 6263 ixgbe_check_vf_rate_limit(adapter); 6264 6265 /* enable transmits */ 6266 netif_tx_wake_all_queues(adapter->netdev); 6267 6268 /* enable any upper devices */ 6269 rtnl_lock(); 6270 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { 6271 if (netif_is_macvlan(upper)) { 6272 struct macvlan_dev *vlan = netdev_priv(upper); 6273 6274 if (vlan->fwd_priv) 6275 netif_tx_wake_all_queues(upper); 6276 } 6277 } 6278 rtnl_unlock(); 6279 6280 /* update the default user priority for VFs */ 6281 ixgbe_update_default_up(adapter); 6282 6283 /* ping all the active vfs to let them know link has changed */ 6284 ixgbe_ping_all_vfs(adapter); 6285 } 6286 6287 /** 6288 * ixgbe_watchdog_link_is_down - update netif_carrier status and 6289 * print link down message 6290 * @adapter: pointer to the adapter structure 6291 **/ 6292 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 6293 { 6294 struct net_device *netdev = adapter->netdev; 6295 struct ixgbe_hw *hw = &adapter->hw; 6296 6297 adapter->link_up = false; 6298 adapter->link_speed = 0; 6299 6300 /* only continue if link was up previously */ 6301 if (!netif_carrier_ok(netdev)) 6302 return; 6303 6304 /* poll for SFP+ cable when link is down */ 6305 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 6306 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 6307 6308 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 6309 ixgbe_ptp_start_cyclecounter(adapter); 6310 6311 e_info(drv, "NIC Link is Down\n"); 6312 netif_carrier_off(netdev); 6313 6314 /* ping all the active vfs to let them know link has changed */ 6315 ixgbe_ping_all_vfs(adapter); 6316 } 6317 6318 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 6319 { 6320 int i; 6321 6322 for (i = 0; i < adapter->num_tx_queues; i++) { 6323 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 6324 6325 if (tx_ring->next_to_use != tx_ring->next_to_clean) 6326 return true; 6327 } 6328 6329 return false; 6330 } 6331 6332 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 6333 { 6334 struct ixgbe_hw *hw = &adapter->hw; 6335 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 6336 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 6337 6338 int i, j; 6339 6340 if (!adapter->num_vfs) 6341 return false; 6342 6343 /* resetting the PF is only needed for MAC before X550 */ 6344 if (hw->mac.type >= ixgbe_mac_X550) 6345 return false; 6346 6347 for (i = 0; i < adapter->num_vfs; i++) { 6348 for (j = 0; j < q_per_pool; j++) { 6349 u32 h, t; 6350 6351 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 6352 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 6353 6354 if (h != t) 6355 return true; 6356 } 6357 } 6358 6359 return false; 6360 } 6361 6362 /** 6363 * ixgbe_watchdog_flush_tx - flush queues on link down 6364 * @adapter: pointer to the device adapter structure 6365 **/ 6366 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 6367 { 6368 if (!netif_carrier_ok(adapter->netdev)) { 6369 if (ixgbe_ring_tx_pending(adapter) || 6370 ixgbe_vf_tx_pending(adapter)) { 6371 /* We've lost link, so the controller stops DMA, 6372 * but we've got queued Tx work that's never going 6373 * to get done, so reset controller to flush Tx. 6374 * (Do the reset outside of interrupt context). 6375 */ 6376 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 6377 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 6378 } 6379 } 6380 } 6381 6382 #ifdef CONFIG_PCI_IOV 6383 static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter, 6384 struct pci_dev *vfdev) 6385 { 6386 if (!pci_wait_for_pending_transaction(vfdev)) 6387 e_dev_warn("Issuing VFLR with pending transactions\n"); 6388 6389 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev)); 6390 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 6391 6392 msleep(100); 6393 } 6394 6395 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 6396 { 6397 struct ixgbe_hw *hw = &adapter->hw; 6398 struct pci_dev *pdev = adapter->pdev; 6399 struct pci_dev *vfdev; 6400 u32 gpc; 6401 int pos; 6402 unsigned short vf_id; 6403 6404 if (!(netif_carrier_ok(adapter->netdev))) 6405 return; 6406 6407 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 6408 if (gpc) /* If incrementing then no need for the check below */ 6409 return; 6410 /* Check to see if a bad DMA write target from an errant or 6411 * malicious VF has caused a PCIe error. If so then we can 6412 * issue a VFLR to the offending VF(s) and then resume without 6413 * requesting a full slot reset. 6414 */ 6415 6416 if (!pdev) 6417 return; 6418 6419 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); 6420 if (!pos) 6421 return; 6422 6423 /* get the device ID for the VF */ 6424 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &vf_id); 6425 6426 /* check status reg for all VFs owned by this PF */ 6427 vfdev = pci_get_device(pdev->vendor, vf_id, NULL); 6428 while (vfdev) { 6429 if (vfdev->is_virtfn && (vfdev->physfn == pdev)) { 6430 u16 status_reg; 6431 6432 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 6433 if (status_reg & PCI_STATUS_REC_MASTER_ABORT) 6434 /* issue VFLR */ 6435 ixgbe_issue_vf_flr(adapter, vfdev); 6436 } 6437 6438 vfdev = pci_get_device(pdev->vendor, vf_id, vfdev); 6439 } 6440 } 6441 6442 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 6443 { 6444 u32 ssvpc; 6445 6446 /* Do not perform spoof check for 82598 or if not in IOV mode */ 6447 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 6448 adapter->num_vfs == 0) 6449 return; 6450 6451 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 6452 6453 /* 6454 * ssvpc register is cleared on read, if zero then no 6455 * spoofed packets in the last interval. 6456 */ 6457 if (!ssvpc) 6458 return; 6459 6460 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 6461 } 6462 #else 6463 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 6464 { 6465 } 6466 6467 static void 6468 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 6469 { 6470 } 6471 #endif /* CONFIG_PCI_IOV */ 6472 6473 6474 /** 6475 * ixgbe_watchdog_subtask - check and bring link up 6476 * @adapter: pointer to the device adapter structure 6477 **/ 6478 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 6479 { 6480 /* if interface is down, removing or resetting, do nothing */ 6481 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6482 test_bit(__IXGBE_REMOVING, &adapter->state) || 6483 test_bit(__IXGBE_RESETTING, &adapter->state)) 6484 return; 6485 6486 ixgbe_watchdog_update_link(adapter); 6487 6488 if (adapter->link_up) 6489 ixgbe_watchdog_link_is_up(adapter); 6490 else 6491 ixgbe_watchdog_link_is_down(adapter); 6492 6493 ixgbe_check_for_bad_vf(adapter); 6494 ixgbe_spoof_check(adapter); 6495 ixgbe_update_stats(adapter); 6496 6497 ixgbe_watchdog_flush_tx(adapter); 6498 } 6499 6500 /** 6501 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 6502 * @adapter: the ixgbe adapter structure 6503 **/ 6504 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 6505 { 6506 struct ixgbe_hw *hw = &adapter->hw; 6507 s32 err; 6508 6509 /* not searching for SFP so there is nothing to do here */ 6510 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 6511 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 6512 return; 6513 6514 /* someone else is in init, wait until next service event */ 6515 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 6516 return; 6517 6518 err = hw->phy.ops.identify_sfp(hw); 6519 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 6520 goto sfp_out; 6521 6522 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 6523 /* If no cable is present, then we need to reset 6524 * the next time we find a good cable. */ 6525 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 6526 } 6527 6528 /* exit on error */ 6529 if (err) 6530 goto sfp_out; 6531 6532 /* exit if reset not needed */ 6533 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 6534 goto sfp_out; 6535 6536 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 6537 6538 /* 6539 * A module may be identified correctly, but the EEPROM may not have 6540 * support for that module. setup_sfp() will fail in that case, so 6541 * we should not allow that module to load. 6542 */ 6543 if (hw->mac.type == ixgbe_mac_82598EB) 6544 err = hw->phy.ops.reset(hw); 6545 else 6546 err = hw->mac.ops.setup_sfp(hw); 6547 6548 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 6549 goto sfp_out; 6550 6551 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 6552 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 6553 6554 sfp_out: 6555 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 6556 6557 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && 6558 (adapter->netdev->reg_state == NETREG_REGISTERED)) { 6559 e_dev_err("failed to initialize because an unsupported " 6560 "SFP+ module type was detected.\n"); 6561 e_dev_err("Reload the driver after installing a " 6562 "supported module.\n"); 6563 unregister_netdev(adapter->netdev); 6564 } 6565 } 6566 6567 /** 6568 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 6569 * @adapter: the ixgbe adapter structure 6570 **/ 6571 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 6572 { 6573 struct ixgbe_hw *hw = &adapter->hw; 6574 u32 speed; 6575 bool autoneg = false; 6576 6577 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 6578 return; 6579 6580 /* someone else is in init, wait until next service event */ 6581 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 6582 return; 6583 6584 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 6585 6586 speed = hw->phy.autoneg_advertised; 6587 if ((!speed) && (hw->mac.ops.get_link_capabilities)) { 6588 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg); 6589 6590 /* setup the highest link when no autoneg */ 6591 if (!autoneg) { 6592 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 6593 speed = IXGBE_LINK_SPEED_10GB_FULL; 6594 } 6595 } 6596 6597 if (hw->mac.ops.setup_link) 6598 hw->mac.ops.setup_link(hw, speed, true); 6599 6600 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 6601 adapter->link_check_timeout = jiffies; 6602 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 6603 } 6604 6605 /** 6606 * ixgbe_service_timer - Timer Call-back 6607 * @data: pointer to adapter cast into an unsigned long 6608 **/ 6609 static void ixgbe_service_timer(unsigned long data) 6610 { 6611 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; 6612 unsigned long next_event_offset; 6613 6614 /* poll faster when waiting for link */ 6615 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 6616 next_event_offset = HZ / 10; 6617 else 6618 next_event_offset = HZ * 2; 6619 6620 /* Reset the timer */ 6621 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 6622 6623 ixgbe_service_event_schedule(adapter); 6624 } 6625 6626 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 6627 { 6628 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED)) 6629 return; 6630 6631 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED; 6632 6633 /* If we're already down, removing or resetting, just bail */ 6634 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6635 test_bit(__IXGBE_REMOVING, &adapter->state) || 6636 test_bit(__IXGBE_RESETTING, &adapter->state)) 6637 return; 6638 6639 ixgbe_dump(adapter); 6640 netdev_err(adapter->netdev, "Reset adapter\n"); 6641 adapter->tx_timeout_count++; 6642 6643 rtnl_lock(); 6644 ixgbe_reinit_locked(adapter); 6645 rtnl_unlock(); 6646 } 6647 6648 /** 6649 * ixgbe_service_task - manages and runs subtasks 6650 * @work: pointer to work_struct containing our data 6651 **/ 6652 static void ixgbe_service_task(struct work_struct *work) 6653 { 6654 struct ixgbe_adapter *adapter = container_of(work, 6655 struct ixgbe_adapter, 6656 service_task); 6657 if (ixgbe_removed(adapter->hw.hw_addr)) { 6658 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 6659 rtnl_lock(); 6660 ixgbe_down(adapter); 6661 rtnl_unlock(); 6662 } 6663 ixgbe_service_event_complete(adapter); 6664 return; 6665 } 6666 ixgbe_reset_subtask(adapter); 6667 ixgbe_sfp_detection_subtask(adapter); 6668 ixgbe_sfp_link_config_subtask(adapter); 6669 ixgbe_check_overtemp_subtask(adapter); 6670 ixgbe_watchdog_subtask(adapter); 6671 ixgbe_fdir_reinit_subtask(adapter); 6672 ixgbe_check_hang_subtask(adapter); 6673 6674 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 6675 ixgbe_ptp_overflow_check(adapter); 6676 ixgbe_ptp_rx_hang(adapter); 6677 } 6678 6679 ixgbe_service_event_complete(adapter); 6680 } 6681 6682 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 6683 struct ixgbe_tx_buffer *first, 6684 u8 *hdr_len) 6685 { 6686 struct sk_buff *skb = first->skb; 6687 u32 vlan_macip_lens, type_tucmd; 6688 u32 mss_l4len_idx, l4len; 6689 int err; 6690 6691 if (skb->ip_summed != CHECKSUM_PARTIAL) 6692 return 0; 6693 6694 if (!skb_is_gso(skb)) 6695 return 0; 6696 6697 err = skb_cow_head(skb, 0); 6698 if (err < 0) 6699 return err; 6700 6701 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 6702 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 6703 6704 if (first->protocol == htons(ETH_P_IP)) { 6705 struct iphdr *iph = ip_hdr(skb); 6706 iph->tot_len = 0; 6707 iph->check = 0; 6708 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 6709 iph->daddr, 0, 6710 IPPROTO_TCP, 6711 0); 6712 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 6713 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 6714 IXGBE_TX_FLAGS_CSUM | 6715 IXGBE_TX_FLAGS_IPV4; 6716 } else if (skb_is_gso_v6(skb)) { 6717 ipv6_hdr(skb)->payload_len = 0; 6718 tcp_hdr(skb)->check = 6719 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 6720 &ipv6_hdr(skb)->daddr, 6721 0, IPPROTO_TCP, 0); 6722 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 6723 IXGBE_TX_FLAGS_CSUM; 6724 } 6725 6726 /* compute header lengths */ 6727 l4len = tcp_hdrlen(skb); 6728 *hdr_len = skb_transport_offset(skb) + l4len; 6729 6730 /* update gso size and bytecount with header size */ 6731 first->gso_segs = skb_shinfo(skb)->gso_segs; 6732 first->bytecount += (first->gso_segs - 1) * *hdr_len; 6733 6734 /* mss_l4len_id: use 0 as index for TSO */ 6735 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT; 6736 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 6737 6738 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 6739 vlan_macip_lens = skb_network_header_len(skb); 6740 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 6741 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 6742 6743 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 6744 mss_l4len_idx); 6745 6746 return 1; 6747 } 6748 6749 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 6750 struct ixgbe_tx_buffer *first) 6751 { 6752 struct sk_buff *skb = first->skb; 6753 u32 vlan_macip_lens = 0; 6754 u32 mss_l4len_idx = 0; 6755 u32 type_tucmd = 0; 6756 6757 if (skb->ip_summed != CHECKSUM_PARTIAL) { 6758 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) && 6759 !(first->tx_flags & IXGBE_TX_FLAGS_CC)) 6760 return; 6761 } else { 6762 u8 l4_hdr = 0; 6763 switch (first->protocol) { 6764 case htons(ETH_P_IP): 6765 vlan_macip_lens |= skb_network_header_len(skb); 6766 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 6767 l4_hdr = ip_hdr(skb)->protocol; 6768 break; 6769 case htons(ETH_P_IPV6): 6770 vlan_macip_lens |= skb_network_header_len(skb); 6771 l4_hdr = ipv6_hdr(skb)->nexthdr; 6772 break; 6773 default: 6774 if (unlikely(net_ratelimit())) { 6775 dev_warn(tx_ring->dev, 6776 "partial checksum but proto=%x!\n", 6777 first->protocol); 6778 } 6779 break; 6780 } 6781 6782 switch (l4_hdr) { 6783 case IPPROTO_TCP: 6784 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP; 6785 mss_l4len_idx = tcp_hdrlen(skb) << 6786 IXGBE_ADVTXD_L4LEN_SHIFT; 6787 break; 6788 case IPPROTO_SCTP: 6789 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; 6790 mss_l4len_idx = sizeof(struct sctphdr) << 6791 IXGBE_ADVTXD_L4LEN_SHIFT; 6792 break; 6793 case IPPROTO_UDP: 6794 mss_l4len_idx = sizeof(struct udphdr) << 6795 IXGBE_ADVTXD_L4LEN_SHIFT; 6796 break; 6797 default: 6798 if (unlikely(net_ratelimit())) { 6799 dev_warn(tx_ring->dev, 6800 "partial checksum but l4 proto=%x!\n", 6801 l4_hdr); 6802 } 6803 break; 6804 } 6805 6806 /* update TX checksum flag */ 6807 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 6808 } 6809 6810 /* vlan_macip_lens: MACLEN, VLAN tag */ 6811 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 6812 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 6813 6814 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, 6815 type_tucmd, mss_l4len_idx); 6816 } 6817 6818 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 6819 ((_flag <= _result) ? \ 6820 ((u32)(_input & _flag) * (_result / _flag)) : \ 6821 ((u32)(_input & _flag) / (_flag / _result))) 6822 6823 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6824 { 6825 /* set type for advanced descriptor with frame checksum insertion */ 6826 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 6827 IXGBE_ADVTXD_DCMD_DEXT | 6828 IXGBE_ADVTXD_DCMD_IFCS; 6829 6830 /* set HW vlan bit if vlan is present */ 6831 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 6832 IXGBE_ADVTXD_DCMD_VLE); 6833 6834 /* set segmentation enable bits for TSO/FSO */ 6835 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 6836 IXGBE_ADVTXD_DCMD_TSE); 6837 6838 /* set timestamp bit if present */ 6839 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 6840 IXGBE_ADVTXD_MAC_TSTAMP); 6841 6842 /* insert frame checksum */ 6843 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 6844 6845 return cmd_type; 6846 } 6847 6848 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 6849 u32 tx_flags, unsigned int paylen) 6850 { 6851 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 6852 6853 /* enable L4 checksum for TSO and TX checksum offload */ 6854 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 6855 IXGBE_TX_FLAGS_CSUM, 6856 IXGBE_ADVTXD_POPTS_TXSM); 6857 6858 /* enble IPv4 checksum for TSO */ 6859 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 6860 IXGBE_TX_FLAGS_IPV4, 6861 IXGBE_ADVTXD_POPTS_IXSM); 6862 6863 /* 6864 * Check Context must be set if Tx switch is enabled, which it 6865 * always is for case where virtual functions are running 6866 */ 6867 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 6868 IXGBE_TX_FLAGS_CC, 6869 IXGBE_ADVTXD_CC); 6870 6871 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6872 } 6873 6874 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 6875 { 6876 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 6877 6878 /* Herbert's original patch had: 6879 * smp_mb__after_netif_stop_queue(); 6880 * but since that doesn't exist yet, just open code it. 6881 */ 6882 smp_mb(); 6883 6884 /* We need to check again in a case another CPU has just 6885 * made room available. 6886 */ 6887 if (likely(ixgbe_desc_unused(tx_ring) < size)) 6888 return -EBUSY; 6889 6890 /* A reprieve! - use start_queue because it doesn't call schedule */ 6891 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 6892 ++tx_ring->tx_stats.restart_queue; 6893 return 0; 6894 } 6895 6896 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 6897 { 6898 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 6899 return 0; 6900 6901 return __ixgbe_maybe_stop_tx(tx_ring, size); 6902 } 6903 6904 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ 6905 IXGBE_TXD_CMD_RS) 6906 6907 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring, 6908 struct ixgbe_tx_buffer *first, 6909 const u8 hdr_len) 6910 { 6911 struct sk_buff *skb = first->skb; 6912 struct ixgbe_tx_buffer *tx_buffer; 6913 union ixgbe_adv_tx_desc *tx_desc; 6914 struct skb_frag_struct *frag; 6915 dma_addr_t dma; 6916 unsigned int data_len, size; 6917 u32 tx_flags = first->tx_flags; 6918 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 6919 u16 i = tx_ring->next_to_use; 6920 6921 tx_desc = IXGBE_TX_DESC(tx_ring, i); 6922 6923 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 6924 6925 size = skb_headlen(skb); 6926 data_len = skb->data_len; 6927 6928 #ifdef IXGBE_FCOE 6929 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 6930 if (data_len < sizeof(struct fcoe_crc_eof)) { 6931 size -= sizeof(struct fcoe_crc_eof) - data_len; 6932 data_len = 0; 6933 } else { 6934 data_len -= sizeof(struct fcoe_crc_eof); 6935 } 6936 } 6937 6938 #endif 6939 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6940 6941 tx_buffer = first; 6942 6943 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6944 if (dma_mapping_error(tx_ring->dev, dma)) 6945 goto dma_error; 6946 6947 /* record length, and DMA address */ 6948 dma_unmap_len_set(tx_buffer, len, size); 6949 dma_unmap_addr_set(tx_buffer, dma, dma); 6950 6951 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6952 6953 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 6954 tx_desc->read.cmd_type_len = 6955 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 6956 6957 i++; 6958 tx_desc++; 6959 if (i == tx_ring->count) { 6960 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 6961 i = 0; 6962 } 6963 tx_desc->read.olinfo_status = 0; 6964 6965 dma += IXGBE_MAX_DATA_PER_TXD; 6966 size -= IXGBE_MAX_DATA_PER_TXD; 6967 6968 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6969 } 6970 6971 if (likely(!data_len)) 6972 break; 6973 6974 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6975 6976 i++; 6977 tx_desc++; 6978 if (i == tx_ring->count) { 6979 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 6980 i = 0; 6981 } 6982 tx_desc->read.olinfo_status = 0; 6983 6984 #ifdef IXGBE_FCOE 6985 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 6986 #else 6987 size = skb_frag_size(frag); 6988 #endif 6989 data_len -= size; 6990 6991 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 6992 DMA_TO_DEVICE); 6993 6994 tx_buffer = &tx_ring->tx_buffer_info[i]; 6995 } 6996 6997 /* write last descriptor with RS and EOP bits */ 6998 cmd_type |= size | IXGBE_TXD_CMD; 6999 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 7000 7001 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 7002 7003 /* set the timestamp */ 7004 first->time_stamp = jiffies; 7005 7006 /* 7007 * Force memory writes to complete before letting h/w know there 7008 * are new descriptors to fetch. (Only applicable for weak-ordered 7009 * memory model archs, such as IA-64). 7010 * 7011 * We also need this memory barrier to make certain all of the 7012 * status bits have been updated before next_to_watch is written. 7013 */ 7014 wmb(); 7015 7016 /* set next_to_watch value indicating a packet is present */ 7017 first->next_to_watch = tx_desc; 7018 7019 i++; 7020 if (i == tx_ring->count) 7021 i = 0; 7022 7023 tx_ring->next_to_use = i; 7024 7025 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 7026 7027 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 7028 writel(i, tx_ring->tail); 7029 7030 /* we need this if more than one processor can write to our tail 7031 * at a time, it synchronizes IO on IA64/Altix systems 7032 */ 7033 mmiowb(); 7034 } 7035 7036 return; 7037 dma_error: 7038 dev_err(tx_ring->dev, "TX DMA map failed\n"); 7039 7040 /* clear dma mappings for failed tx_buffer_info map */ 7041 for (;;) { 7042 tx_buffer = &tx_ring->tx_buffer_info[i]; 7043 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer); 7044 if (tx_buffer == first) 7045 break; 7046 if (i == 0) 7047 i = tx_ring->count; 7048 i--; 7049 } 7050 7051 tx_ring->next_to_use = i; 7052 } 7053 7054 static void ixgbe_atr(struct ixgbe_ring *ring, 7055 struct ixgbe_tx_buffer *first) 7056 { 7057 struct ixgbe_q_vector *q_vector = ring->q_vector; 7058 union ixgbe_atr_hash_dword input = { .dword = 0 }; 7059 union ixgbe_atr_hash_dword common = { .dword = 0 }; 7060 union { 7061 unsigned char *network; 7062 struct iphdr *ipv4; 7063 struct ipv6hdr *ipv6; 7064 } hdr; 7065 struct tcphdr *th; 7066 __be16 vlan_id; 7067 7068 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 7069 if (!q_vector) 7070 return; 7071 7072 /* do nothing if sampling is disabled */ 7073 if (!ring->atr_sample_rate) 7074 return; 7075 7076 ring->atr_count++; 7077 7078 /* snag network header to get L4 type and address */ 7079 hdr.network = skb_network_header(first->skb); 7080 7081 /* Currently only IPv4/IPv6 with TCP is supported */ 7082 if ((first->protocol != htons(ETH_P_IPV6) || 7083 hdr.ipv6->nexthdr != IPPROTO_TCP) && 7084 (first->protocol != htons(ETH_P_IP) || 7085 hdr.ipv4->protocol != IPPROTO_TCP)) 7086 return; 7087 7088 th = tcp_hdr(first->skb); 7089 7090 /* skip this packet since it is invalid or the socket is closing */ 7091 if (!th || th->fin) 7092 return; 7093 7094 /* sample on all syn packets or once every atr sample count */ 7095 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 7096 return; 7097 7098 /* reset sample count */ 7099 ring->atr_count = 0; 7100 7101 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 7102 7103 /* 7104 * src and dst are inverted, think how the receiver sees them 7105 * 7106 * The input is broken into two sections, a non-compressed section 7107 * containing vm_pool, vlan_id, and flow_type. The rest of the data 7108 * is XORed together and stored in the compressed dword. 7109 */ 7110 input.formatted.vlan_id = vlan_id; 7111 7112 /* 7113 * since src port and flex bytes occupy the same word XOR them together 7114 * and write the value to source port portion of compressed dword 7115 */ 7116 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 7117 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 7118 else 7119 common.port.src ^= th->dest ^ first->protocol; 7120 common.port.dst ^= th->source; 7121 7122 if (first->protocol == htons(ETH_P_IP)) { 7123 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 7124 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 7125 } else { 7126 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 7127 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 7128 hdr.ipv6->saddr.s6_addr32[1] ^ 7129 hdr.ipv6->saddr.s6_addr32[2] ^ 7130 hdr.ipv6->saddr.s6_addr32[3] ^ 7131 hdr.ipv6->daddr.s6_addr32[0] ^ 7132 hdr.ipv6->daddr.s6_addr32[1] ^ 7133 hdr.ipv6->daddr.s6_addr32[2] ^ 7134 hdr.ipv6->daddr.s6_addr32[3]; 7135 } 7136 7137 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 7138 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 7139 input, common, ring->queue_index); 7140 } 7141 7142 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 7143 void *accel_priv, select_queue_fallback_t fallback) 7144 { 7145 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv; 7146 #ifdef IXGBE_FCOE 7147 struct ixgbe_adapter *adapter; 7148 struct ixgbe_ring_feature *f; 7149 int txq; 7150 #endif 7151 7152 if (fwd_adapter) 7153 return skb->queue_mapping + fwd_adapter->tx_base_queue; 7154 7155 #ifdef IXGBE_FCOE 7156 7157 /* 7158 * only execute the code below if protocol is FCoE 7159 * or FIP and we have FCoE enabled on the adapter 7160 */ 7161 switch (vlan_get_protocol(skb)) { 7162 case htons(ETH_P_FCOE): 7163 case htons(ETH_P_FIP): 7164 adapter = netdev_priv(dev); 7165 7166 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) 7167 break; 7168 default: 7169 return fallback(dev, skb); 7170 } 7171 7172 f = &adapter->ring_feature[RING_F_FCOE]; 7173 7174 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 7175 smp_processor_id(); 7176 7177 while (txq >= f->indices) 7178 txq -= f->indices; 7179 7180 return txq + f->offset; 7181 #else 7182 return fallback(dev, skb); 7183 #endif 7184 } 7185 7186 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 7187 struct ixgbe_adapter *adapter, 7188 struct ixgbe_ring *tx_ring) 7189 { 7190 struct ixgbe_tx_buffer *first; 7191 int tso; 7192 u32 tx_flags = 0; 7193 unsigned short f; 7194 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 7195 __be16 protocol = skb->protocol; 7196 u8 hdr_len = 0; 7197 7198 /* 7199 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 7200 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 7201 * + 2 desc gap to keep tail from touching head, 7202 * + 1 desc for context descriptor, 7203 * otherwise try next time 7204 */ 7205 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 7206 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 7207 7208 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 7209 tx_ring->tx_stats.tx_busy++; 7210 return NETDEV_TX_BUSY; 7211 } 7212 7213 /* record the location of the first descriptor for this packet */ 7214 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 7215 first->skb = skb; 7216 first->bytecount = skb->len; 7217 first->gso_segs = 1; 7218 7219 /* if we have a HW VLAN tag being added default to the HW one */ 7220 if (vlan_tx_tag_present(skb)) { 7221 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 7222 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 7223 /* else if it is a SW VLAN check the next protocol and store the tag */ 7224 } else if (protocol == htons(ETH_P_8021Q)) { 7225 struct vlan_hdr *vhdr, _vhdr; 7226 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 7227 if (!vhdr) 7228 goto out_drop; 7229 7230 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 7231 IXGBE_TX_FLAGS_VLAN_SHIFT; 7232 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 7233 } 7234 protocol = vlan_get_protocol(skb); 7235 7236 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 7237 adapter->ptp_clock && 7238 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 7239 &adapter->state)) { 7240 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 7241 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 7242 7243 /* schedule check for Tx timestamp */ 7244 adapter->ptp_tx_skb = skb_get(skb); 7245 adapter->ptp_tx_start = jiffies; 7246 schedule_work(&adapter->ptp_tx_work); 7247 } 7248 7249 skb_tx_timestamp(skb); 7250 7251 #ifdef CONFIG_PCI_IOV 7252 /* 7253 * Use the l2switch_enable flag - would be false if the DMA 7254 * Tx switch had been disabled. 7255 */ 7256 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 7257 tx_flags |= IXGBE_TX_FLAGS_CC; 7258 7259 #endif 7260 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 7261 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 7262 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 7263 (skb->priority != TC_PRIO_CONTROL))) { 7264 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 7265 tx_flags |= (skb->priority & 0x7) << 7266 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 7267 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 7268 struct vlan_ethhdr *vhdr; 7269 7270 if (skb_cow_head(skb, 0)) 7271 goto out_drop; 7272 vhdr = (struct vlan_ethhdr *)skb->data; 7273 vhdr->h_vlan_TCI = htons(tx_flags >> 7274 IXGBE_TX_FLAGS_VLAN_SHIFT); 7275 } else { 7276 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 7277 } 7278 } 7279 7280 /* record initial flags and protocol */ 7281 first->tx_flags = tx_flags; 7282 first->protocol = protocol; 7283 7284 #ifdef IXGBE_FCOE 7285 /* setup tx offload for FCoE */ 7286 if ((protocol == htons(ETH_P_FCOE)) && 7287 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 7288 tso = ixgbe_fso(tx_ring, first, &hdr_len); 7289 if (tso < 0) 7290 goto out_drop; 7291 7292 goto xmit_fcoe; 7293 } 7294 7295 #endif /* IXGBE_FCOE */ 7296 tso = ixgbe_tso(tx_ring, first, &hdr_len); 7297 if (tso < 0) 7298 goto out_drop; 7299 else if (!tso) 7300 ixgbe_tx_csum(tx_ring, first); 7301 7302 /* add the ATR filter if ATR is on */ 7303 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 7304 ixgbe_atr(tx_ring, first); 7305 7306 #ifdef IXGBE_FCOE 7307 xmit_fcoe: 7308 #endif /* IXGBE_FCOE */ 7309 ixgbe_tx_map(tx_ring, first, hdr_len); 7310 7311 return NETDEV_TX_OK; 7312 7313 out_drop: 7314 dev_kfree_skb_any(first->skb); 7315 first->skb = NULL; 7316 7317 return NETDEV_TX_OK; 7318 } 7319 7320 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 7321 struct net_device *netdev, 7322 struct ixgbe_ring *ring) 7323 { 7324 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7325 struct ixgbe_ring *tx_ring; 7326 7327 /* 7328 * The minimum packet size for olinfo paylen is 17 so pad the skb 7329 * in order to meet this minimum size requirement. 7330 */ 7331 if (skb_put_padto(skb, 17)) 7332 return NETDEV_TX_OK; 7333 7334 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping]; 7335 7336 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 7337 } 7338 7339 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 7340 struct net_device *netdev) 7341 { 7342 return __ixgbe_xmit_frame(skb, netdev, NULL); 7343 } 7344 7345 /** 7346 * ixgbe_set_mac - Change the Ethernet Address of the NIC 7347 * @netdev: network interface device structure 7348 * @p: pointer to an address structure 7349 * 7350 * Returns 0 on success, negative on failure 7351 **/ 7352 static int ixgbe_set_mac(struct net_device *netdev, void *p) 7353 { 7354 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7355 struct ixgbe_hw *hw = &adapter->hw; 7356 struct sockaddr *addr = p; 7357 int ret; 7358 7359 if (!is_valid_ether_addr(addr->sa_data)) 7360 return -EADDRNOTAVAIL; 7361 7362 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0)); 7363 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 7364 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 7365 7366 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0)); 7367 return ret > 0 ? 0 : ret; 7368 } 7369 7370 static int 7371 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 7372 { 7373 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7374 struct ixgbe_hw *hw = &adapter->hw; 7375 u16 value; 7376 int rc; 7377 7378 if (prtad != hw->phy.mdio.prtad) 7379 return -EINVAL; 7380 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 7381 if (!rc) 7382 rc = value; 7383 return rc; 7384 } 7385 7386 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 7387 u16 addr, u16 value) 7388 { 7389 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7390 struct ixgbe_hw *hw = &adapter->hw; 7391 7392 if (prtad != hw->phy.mdio.prtad) 7393 return -EINVAL; 7394 return hw->phy.ops.write_reg(hw, addr, devad, value); 7395 } 7396 7397 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 7398 { 7399 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7400 7401 switch (cmd) { 7402 case SIOCSHWTSTAMP: 7403 return ixgbe_ptp_set_ts_config(adapter, req); 7404 case SIOCGHWTSTAMP: 7405 return ixgbe_ptp_get_ts_config(adapter, req); 7406 default: 7407 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 7408 } 7409 } 7410 7411 /** 7412 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 7413 * netdev->dev_addrs 7414 * @netdev: network interface device structure 7415 * 7416 * Returns non-zero on failure 7417 **/ 7418 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 7419 { 7420 int err = 0; 7421 struct ixgbe_adapter *adapter = netdev_priv(dev); 7422 struct ixgbe_hw *hw = &adapter->hw; 7423 7424 if (is_valid_ether_addr(hw->mac.san_addr)) { 7425 rtnl_lock(); 7426 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 7427 rtnl_unlock(); 7428 7429 /* update SAN MAC vmdq pool selection */ 7430 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 7431 } 7432 return err; 7433 } 7434 7435 /** 7436 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 7437 * netdev->dev_addrs 7438 * @netdev: network interface device structure 7439 * 7440 * Returns non-zero on failure 7441 **/ 7442 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 7443 { 7444 int err = 0; 7445 struct ixgbe_adapter *adapter = netdev_priv(dev); 7446 struct ixgbe_mac_info *mac = &adapter->hw.mac; 7447 7448 if (is_valid_ether_addr(mac->san_addr)) { 7449 rtnl_lock(); 7450 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 7451 rtnl_unlock(); 7452 } 7453 return err; 7454 } 7455 7456 #ifdef CONFIG_NET_POLL_CONTROLLER 7457 /* 7458 * Polling 'interrupt' - used by things like netconsole to send skbs 7459 * without having to re-enable interrupts. It's not called while 7460 * the interrupt routine is executing. 7461 */ 7462 static void ixgbe_netpoll(struct net_device *netdev) 7463 { 7464 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7465 int i; 7466 7467 /* if interface is down do nothing */ 7468 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7469 return; 7470 7471 adapter->flags |= IXGBE_FLAG_IN_NETPOLL; 7472 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 7473 for (i = 0; i < adapter->num_q_vectors; i++) 7474 ixgbe_msix_clean_rings(0, adapter->q_vector[i]); 7475 } else { 7476 ixgbe_intr(adapter->pdev->irq, netdev); 7477 } 7478 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; 7479 } 7480 7481 #endif 7482 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev, 7483 struct rtnl_link_stats64 *stats) 7484 { 7485 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7486 int i; 7487 7488 rcu_read_lock(); 7489 for (i = 0; i < adapter->num_rx_queues; i++) { 7490 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); 7491 u64 bytes, packets; 7492 unsigned int start; 7493 7494 if (ring) { 7495 do { 7496 start = u64_stats_fetch_begin_irq(&ring->syncp); 7497 packets = ring->stats.packets; 7498 bytes = ring->stats.bytes; 7499 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 7500 stats->rx_packets += packets; 7501 stats->rx_bytes += bytes; 7502 } 7503 } 7504 7505 for (i = 0; i < adapter->num_tx_queues; i++) { 7506 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); 7507 u64 bytes, packets; 7508 unsigned int start; 7509 7510 if (ring) { 7511 do { 7512 start = u64_stats_fetch_begin_irq(&ring->syncp); 7513 packets = ring->stats.packets; 7514 bytes = ring->stats.bytes; 7515 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 7516 stats->tx_packets += packets; 7517 stats->tx_bytes += bytes; 7518 } 7519 } 7520 rcu_read_unlock(); 7521 /* following stats updated by ixgbe_watchdog_task() */ 7522 stats->multicast = netdev->stats.multicast; 7523 stats->rx_errors = netdev->stats.rx_errors; 7524 stats->rx_length_errors = netdev->stats.rx_length_errors; 7525 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 7526 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 7527 return stats; 7528 } 7529 7530 #ifdef CONFIG_IXGBE_DCB 7531 /** 7532 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 7533 * @adapter: pointer to ixgbe_adapter 7534 * @tc: number of traffic classes currently enabled 7535 * 7536 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 7537 * 802.1Q priority maps to a packet buffer that exists. 7538 */ 7539 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 7540 { 7541 struct ixgbe_hw *hw = &adapter->hw; 7542 u32 reg, rsave; 7543 int i; 7544 7545 /* 82598 have a static priority to TC mapping that can not 7546 * be changed so no validation is needed. 7547 */ 7548 if (hw->mac.type == ixgbe_mac_82598EB) 7549 return; 7550 7551 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 7552 rsave = reg; 7553 7554 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 7555 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 7556 7557 /* If up2tc is out of bounds default to zero */ 7558 if (up2tc > tc) 7559 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 7560 } 7561 7562 if (reg != rsave) 7563 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 7564 7565 return; 7566 } 7567 7568 /** 7569 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 7570 * @adapter: Pointer to adapter struct 7571 * 7572 * Populate the netdev user priority to tc map 7573 */ 7574 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 7575 { 7576 struct net_device *dev = adapter->netdev; 7577 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 7578 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 7579 u8 prio; 7580 7581 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 7582 u8 tc = 0; 7583 7584 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 7585 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 7586 else if (ets) 7587 tc = ets->prio_tc[prio]; 7588 7589 netdev_set_prio_tc_map(dev, prio, tc); 7590 } 7591 } 7592 7593 #endif /* CONFIG_IXGBE_DCB */ 7594 /** 7595 * ixgbe_setup_tc - configure net_device for multiple traffic classes 7596 * 7597 * @netdev: net device to configure 7598 * @tc: number of traffic classes to enable 7599 */ 7600 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 7601 { 7602 struct ixgbe_adapter *adapter = netdev_priv(dev); 7603 struct ixgbe_hw *hw = &adapter->hw; 7604 bool pools; 7605 7606 /* Hardware supports up to 8 traffic classes */ 7607 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs || 7608 (hw->mac.type == ixgbe_mac_82598EB && 7609 tc < MAX_TRAFFIC_CLASS)) 7610 return -EINVAL; 7611 7612 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1); 7613 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS) 7614 return -EBUSY; 7615 7616 /* Hardware has to reinitialize queues and interrupts to 7617 * match packet buffer alignment. Unfortunately, the 7618 * hardware is not flexible enough to do this dynamically. 7619 */ 7620 if (netif_running(dev)) 7621 ixgbe_close(dev); 7622 ixgbe_clear_interrupt_scheme(adapter); 7623 7624 #ifdef CONFIG_IXGBE_DCB 7625 if (tc) { 7626 netdev_set_num_tc(dev, tc); 7627 ixgbe_set_prio_tc_map(adapter); 7628 7629 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 7630 7631 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 7632 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 7633 adapter->hw.fc.requested_mode = ixgbe_fc_none; 7634 } 7635 } else { 7636 netdev_reset_tc(dev); 7637 7638 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 7639 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 7640 7641 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 7642 7643 adapter->temp_dcb_cfg.pfc_mode_enable = false; 7644 adapter->dcb_cfg.pfc_mode_enable = false; 7645 } 7646 7647 ixgbe_validate_rtr(adapter, tc); 7648 7649 #endif /* CONFIG_IXGBE_DCB */ 7650 ixgbe_init_interrupt_scheme(adapter); 7651 7652 if (netif_running(dev)) 7653 return ixgbe_open(dev); 7654 7655 return 0; 7656 } 7657 7658 #ifdef CONFIG_PCI_IOV 7659 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 7660 { 7661 struct net_device *netdev = adapter->netdev; 7662 7663 rtnl_lock(); 7664 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev)); 7665 rtnl_unlock(); 7666 } 7667 7668 #endif 7669 void ixgbe_do_reset(struct net_device *netdev) 7670 { 7671 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7672 7673 if (netif_running(netdev)) 7674 ixgbe_reinit_locked(adapter); 7675 else 7676 ixgbe_reset(adapter); 7677 } 7678 7679 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 7680 netdev_features_t features) 7681 { 7682 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7683 7684 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 7685 if (!(features & NETIF_F_RXCSUM)) 7686 features &= ~NETIF_F_LRO; 7687 7688 /* Turn off LRO if not RSC capable */ 7689 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 7690 features &= ~NETIF_F_LRO; 7691 7692 return features; 7693 } 7694 7695 static int ixgbe_set_features(struct net_device *netdev, 7696 netdev_features_t features) 7697 { 7698 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7699 netdev_features_t changed = netdev->features ^ features; 7700 bool need_reset = false; 7701 7702 /* Make sure RSC matches LRO, reset if change */ 7703 if (!(features & NETIF_F_LRO)) { 7704 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 7705 need_reset = true; 7706 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 7707 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 7708 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 7709 if (adapter->rx_itr_setting == 1 || 7710 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 7711 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 7712 need_reset = true; 7713 } else if ((changed ^ features) & NETIF_F_LRO) { 7714 e_info(probe, "rx-usecs set too low, " 7715 "disabling RSC\n"); 7716 } 7717 } 7718 7719 /* 7720 * Check if Flow Director n-tuple support was enabled or disabled. If 7721 * the state changed, we need to reset. 7722 */ 7723 switch (features & NETIF_F_NTUPLE) { 7724 case NETIF_F_NTUPLE: 7725 /* turn off ATR, enable perfect filters and reset */ 7726 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 7727 need_reset = true; 7728 7729 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 7730 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 7731 break; 7732 default: 7733 /* turn off perfect filters, enable ATR and reset */ 7734 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 7735 need_reset = true; 7736 7737 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 7738 7739 /* We cannot enable ATR if SR-IOV is enabled */ 7740 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 7741 break; 7742 7743 /* We cannot enable ATR if we have 2 or more traffic classes */ 7744 if (netdev_get_num_tc(netdev) > 1) 7745 break; 7746 7747 /* We cannot enable ATR if RSS is disabled */ 7748 if (adapter->ring_feature[RING_F_RSS].limit <= 1) 7749 break; 7750 7751 /* A sample rate of 0 indicates ATR disabled */ 7752 if (!adapter->atr_sample_rate) 7753 break; 7754 7755 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 7756 break; 7757 } 7758 7759 if (features & NETIF_F_HW_VLAN_CTAG_RX) 7760 ixgbe_vlan_strip_enable(adapter); 7761 else 7762 ixgbe_vlan_strip_disable(adapter); 7763 7764 if (changed & NETIF_F_RXALL) 7765 need_reset = true; 7766 7767 netdev->features = features; 7768 if (need_reset) 7769 ixgbe_do_reset(netdev); 7770 7771 return 0; 7772 } 7773 7774 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 7775 struct net_device *dev, 7776 const unsigned char *addr, u16 vid, 7777 u16 flags) 7778 { 7779 /* guarantee we can provide a unique filter for the unicast address */ 7780 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 7781 if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev)) 7782 return -ENOMEM; 7783 } 7784 7785 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 7786 } 7787 7788 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 7789 struct nlmsghdr *nlh) 7790 { 7791 struct ixgbe_adapter *adapter = netdev_priv(dev); 7792 struct nlattr *attr, *br_spec; 7793 int rem; 7794 7795 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 7796 return -EOPNOTSUPP; 7797 7798 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 7799 if (!br_spec) 7800 return -EINVAL; 7801 7802 nla_for_each_nested(attr, br_spec, rem) { 7803 __u16 mode; 7804 u32 reg = 0; 7805 7806 if (nla_type(attr) != IFLA_BRIDGE_MODE) 7807 continue; 7808 7809 if (nla_len(attr) < sizeof(mode)) 7810 return -EINVAL; 7811 7812 mode = nla_get_u16(attr); 7813 if (mode == BRIDGE_MODE_VEPA) { 7814 reg = 0; 7815 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB; 7816 } else if (mode == BRIDGE_MODE_VEB) { 7817 reg = IXGBE_PFDTXGSWC_VT_LBEN; 7818 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB; 7819 } else 7820 return -EINVAL; 7821 7822 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg); 7823 7824 e_info(drv, "enabling bridge mode: %s\n", 7825 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 7826 } 7827 7828 return 0; 7829 } 7830 7831 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 7832 struct net_device *dev, 7833 u32 filter_mask) 7834 { 7835 struct ixgbe_adapter *adapter = netdev_priv(dev); 7836 u16 mode; 7837 7838 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 7839 return 0; 7840 7841 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB) 7842 mode = BRIDGE_MODE_VEB; 7843 else 7844 mode = BRIDGE_MODE_VEPA; 7845 7846 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode, 0, 0); 7847 } 7848 7849 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 7850 { 7851 struct ixgbe_fwd_adapter *fwd_adapter = NULL; 7852 struct ixgbe_adapter *adapter = netdev_priv(pdev); 7853 int used_pools = adapter->num_vfs + adapter->num_rx_pools; 7854 unsigned int limit; 7855 int pool, err; 7856 7857 /* Hardware has a limited number of available pools. Each VF, and the 7858 * PF require a pool. Check to ensure we don't attempt to use more 7859 * then the available number of pools. 7860 */ 7861 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 7862 return ERR_PTR(-EINVAL); 7863 7864 #ifdef CONFIG_RPS 7865 if (vdev->num_rx_queues != vdev->num_tx_queues) { 7866 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n", 7867 vdev->name); 7868 return ERR_PTR(-EINVAL); 7869 } 7870 #endif 7871 /* Check for hardware restriction on number of rx/tx queues */ 7872 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES || 7873 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) { 7874 netdev_info(pdev, 7875 "%s: Supports RX/TX Queue counts 1,2, and 4\n", 7876 pdev->name); 7877 return ERR_PTR(-EINVAL); 7878 } 7879 7880 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 7881 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) || 7882 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS)) 7883 return ERR_PTR(-EBUSY); 7884 7885 fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL); 7886 if (!fwd_adapter) 7887 return ERR_PTR(-ENOMEM); 7888 7889 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32); 7890 adapter->num_rx_pools++; 7891 set_bit(pool, &adapter->fwd_bitmask); 7892 limit = find_last_bit(&adapter->fwd_bitmask, 32); 7893 7894 /* Enable VMDq flag so device will be set in VM mode */ 7895 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED; 7896 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 7897 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues; 7898 7899 /* Force reinit of ring allocation with VMDQ enabled */ 7900 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); 7901 if (err) 7902 goto fwd_add_err; 7903 fwd_adapter->pool = pool; 7904 fwd_adapter->real_adapter = adapter; 7905 err = ixgbe_fwd_ring_up(vdev, fwd_adapter); 7906 if (err) 7907 goto fwd_add_err; 7908 netif_tx_start_all_queues(vdev); 7909 return fwd_adapter; 7910 fwd_add_err: 7911 /* unwind counter and free adapter struct */ 7912 netdev_info(pdev, 7913 "%s: dfwd hardware acceleration failed\n", vdev->name); 7914 clear_bit(pool, &adapter->fwd_bitmask); 7915 adapter->num_rx_pools--; 7916 kfree(fwd_adapter); 7917 return ERR_PTR(err); 7918 } 7919 7920 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 7921 { 7922 struct ixgbe_fwd_adapter *fwd_adapter = priv; 7923 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter; 7924 unsigned int limit; 7925 7926 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask); 7927 adapter->num_rx_pools--; 7928 7929 limit = find_last_bit(&adapter->fwd_bitmask, 32); 7930 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 7931 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter); 7932 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); 7933 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", 7934 fwd_adapter->pool, adapter->num_rx_pools, 7935 fwd_adapter->rx_base_queue, 7936 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool, 7937 adapter->fwd_bitmask); 7938 kfree(fwd_adapter); 7939 } 7940 7941 static const struct net_device_ops ixgbe_netdev_ops = { 7942 .ndo_open = ixgbe_open, 7943 .ndo_stop = ixgbe_close, 7944 .ndo_start_xmit = ixgbe_xmit_frame, 7945 .ndo_select_queue = ixgbe_select_queue, 7946 .ndo_set_rx_mode = ixgbe_set_rx_mode, 7947 .ndo_validate_addr = eth_validate_addr, 7948 .ndo_set_mac_address = ixgbe_set_mac, 7949 .ndo_change_mtu = ixgbe_change_mtu, 7950 .ndo_tx_timeout = ixgbe_tx_timeout, 7951 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 7952 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 7953 .ndo_do_ioctl = ixgbe_ioctl, 7954 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 7955 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 7956 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 7957 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 7958 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 7959 .ndo_get_stats64 = ixgbe_get_stats64, 7960 #ifdef CONFIG_IXGBE_DCB 7961 .ndo_setup_tc = ixgbe_setup_tc, 7962 #endif 7963 #ifdef CONFIG_NET_POLL_CONTROLLER 7964 .ndo_poll_controller = ixgbe_netpoll, 7965 #endif 7966 #ifdef CONFIG_NET_RX_BUSY_POLL 7967 .ndo_busy_poll = ixgbe_low_latency_recv, 7968 #endif 7969 #ifdef IXGBE_FCOE 7970 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 7971 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 7972 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 7973 .ndo_fcoe_enable = ixgbe_fcoe_enable, 7974 .ndo_fcoe_disable = ixgbe_fcoe_disable, 7975 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 7976 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 7977 #endif /* IXGBE_FCOE */ 7978 .ndo_set_features = ixgbe_set_features, 7979 .ndo_fix_features = ixgbe_fix_features, 7980 .ndo_fdb_add = ixgbe_ndo_fdb_add, 7981 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 7982 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 7983 .ndo_dfwd_add_station = ixgbe_fwd_add, 7984 .ndo_dfwd_del_station = ixgbe_fwd_del, 7985 }; 7986 7987 /** 7988 * ixgbe_enumerate_functions - Get the number of ports this device has 7989 * @adapter: adapter structure 7990 * 7991 * This function enumerates the phsyical functions co-located on a single slot, 7992 * in order to determine how many ports a device has. This is most useful in 7993 * determining the required GT/s of PCIe bandwidth necessary for optimal 7994 * performance. 7995 **/ 7996 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 7997 { 7998 struct pci_dev *entry, *pdev = adapter->pdev; 7999 int physfns = 0; 8000 8001 /* Some cards can not use the generic count PCIe functions method, 8002 * because they are behind a parent switch, so we hardcode these with 8003 * the correct number of functions. 8004 */ 8005 if (ixgbe_pcie_from_parent(&adapter->hw)) 8006 physfns = 4; 8007 8008 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 8009 /* don't count virtual functions */ 8010 if (entry->is_virtfn) 8011 continue; 8012 8013 /* When the devices on the bus don't all match our device ID, 8014 * we can't reliably determine the correct number of 8015 * functions. This can occur if a function has been direct 8016 * attached to a virtual machine using VT-d, for example. In 8017 * this case, simply return -1 to indicate this. 8018 */ 8019 if ((entry->vendor != pdev->vendor) || 8020 (entry->device != pdev->device)) 8021 return -1; 8022 8023 physfns++; 8024 } 8025 8026 return physfns; 8027 } 8028 8029 /** 8030 * ixgbe_wol_supported - Check whether device supports WoL 8031 * @hw: hw specific details 8032 * @device_id: the device ID 8033 * @subdev_id: the subsystem device ID 8034 * 8035 * This function is used by probe and ethtool to determine 8036 * which devices have WoL support 8037 * 8038 **/ 8039 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 8040 u16 subdevice_id) 8041 { 8042 struct ixgbe_hw *hw = &adapter->hw; 8043 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 8044 int is_wol_supported = 0; 8045 8046 switch (device_id) { 8047 case IXGBE_DEV_ID_82599_SFP: 8048 /* Only these subdevices could supports WOL */ 8049 switch (subdevice_id) { 8050 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 8051 case IXGBE_SUBDEV_ID_82599_560FLR: 8052 /* only support first port */ 8053 if (hw->bus.func != 0) 8054 break; 8055 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 8056 case IXGBE_SUBDEV_ID_82599_SFP: 8057 case IXGBE_SUBDEV_ID_82599_RNDC: 8058 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 8059 case IXGBE_SUBDEV_ID_82599_LOM_SFP: 8060 is_wol_supported = 1; 8061 break; 8062 } 8063 break; 8064 case IXGBE_DEV_ID_82599EN_SFP: 8065 /* Only this subdevice supports WOL */ 8066 switch (subdevice_id) { 8067 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 8068 is_wol_supported = 1; 8069 break; 8070 } 8071 break; 8072 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 8073 /* All except this subdevice support WOL */ 8074 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 8075 is_wol_supported = 1; 8076 break; 8077 case IXGBE_DEV_ID_82599_KX4: 8078 is_wol_supported = 1; 8079 break; 8080 case IXGBE_DEV_ID_X540T: 8081 case IXGBE_DEV_ID_X540T1: 8082 /* check eeprom to see if enabled wol */ 8083 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 8084 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 8085 (hw->bus.func == 0))) { 8086 is_wol_supported = 1; 8087 } 8088 break; 8089 } 8090 8091 return is_wol_supported; 8092 } 8093 8094 /** 8095 * ixgbe_get_platform_mac_addr - Look up MAC address in Open Firmware / IDPROM 8096 * @adapter: Pointer to adapter struct 8097 */ 8098 static void ixgbe_get_platform_mac_addr(struct ixgbe_adapter *adapter) 8099 { 8100 #ifdef CONFIG_OF 8101 struct device_node *dp = pci_device_to_OF_node(adapter->pdev); 8102 struct ixgbe_hw *hw = &adapter->hw; 8103 const unsigned char *addr; 8104 8105 addr = of_get_mac_address(dp); 8106 if (addr) { 8107 ether_addr_copy(hw->mac.perm_addr, addr); 8108 return; 8109 } 8110 #endif /* CONFIG_OF */ 8111 8112 #ifdef CONFIG_SPARC 8113 ether_addr_copy(hw->mac.perm_addr, idprom->id_ethaddr); 8114 #endif /* CONFIG_SPARC */ 8115 } 8116 8117 /** 8118 * ixgbe_probe - Device Initialization Routine 8119 * @pdev: PCI device information struct 8120 * @ent: entry in ixgbe_pci_tbl 8121 * 8122 * Returns 0 on success, negative on failure 8123 * 8124 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 8125 * The OS initialization, configuring of the adapter private structure, 8126 * and a hardware reset occur. 8127 **/ 8128 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 8129 { 8130 struct net_device *netdev; 8131 struct ixgbe_adapter *adapter = NULL; 8132 struct ixgbe_hw *hw; 8133 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 8134 int i, err, pci_using_dac, expected_gts; 8135 unsigned int indices = MAX_TX_QUEUES; 8136 u8 part_str[IXGBE_PBANUM_LENGTH]; 8137 bool disable_dev = false; 8138 #ifdef IXGBE_FCOE 8139 u16 device_caps; 8140 #endif 8141 u32 eec; 8142 8143 /* Catch broken hardware that put the wrong VF device ID in 8144 * the PCIe SR-IOV capability. 8145 */ 8146 if (pdev->is_virtfn) { 8147 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 8148 pci_name(pdev), pdev->vendor, pdev->device); 8149 return -EINVAL; 8150 } 8151 8152 err = pci_enable_device_mem(pdev); 8153 if (err) 8154 return err; 8155 8156 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 8157 pci_using_dac = 1; 8158 } else { 8159 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 8160 if (err) { 8161 dev_err(&pdev->dev, 8162 "No usable DMA configuration, aborting\n"); 8163 goto err_dma; 8164 } 8165 pci_using_dac = 0; 8166 } 8167 8168 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 8169 IORESOURCE_MEM), ixgbe_driver_name); 8170 if (err) { 8171 dev_err(&pdev->dev, 8172 "pci_request_selected_regions failed 0x%x\n", err); 8173 goto err_pci_reg; 8174 } 8175 8176 pci_enable_pcie_error_reporting(pdev); 8177 8178 pci_set_master(pdev); 8179 pci_save_state(pdev); 8180 8181 if (ii->mac == ixgbe_mac_82598EB) { 8182 #ifdef CONFIG_IXGBE_DCB 8183 /* 8 TC w/ 4 queues per TC */ 8184 indices = 4 * MAX_TRAFFIC_CLASS; 8185 #else 8186 indices = IXGBE_MAX_RSS_INDICES; 8187 #endif 8188 } 8189 8190 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 8191 if (!netdev) { 8192 err = -ENOMEM; 8193 goto err_alloc_etherdev; 8194 } 8195 8196 SET_NETDEV_DEV(netdev, &pdev->dev); 8197 8198 adapter = netdev_priv(netdev); 8199 8200 adapter->netdev = netdev; 8201 adapter->pdev = pdev; 8202 hw = &adapter->hw; 8203 hw->back = adapter; 8204 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 8205 8206 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 8207 pci_resource_len(pdev, 0)); 8208 adapter->io_addr = hw->hw_addr; 8209 if (!hw->hw_addr) { 8210 err = -EIO; 8211 goto err_ioremap; 8212 } 8213 8214 netdev->netdev_ops = &ixgbe_netdev_ops; 8215 ixgbe_set_ethtool_ops(netdev); 8216 netdev->watchdog_timeo = 5 * HZ; 8217 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 8218 8219 /* Setup hw api */ 8220 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); 8221 hw->mac.type = ii->mac; 8222 8223 /* EEPROM */ 8224 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); 8225 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 8226 if (ixgbe_removed(hw->hw_addr)) { 8227 err = -EIO; 8228 goto err_ioremap; 8229 } 8230 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 8231 if (!(eec & (1 << 8))) 8232 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 8233 8234 /* PHY */ 8235 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); 8236 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 8237 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 8238 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 8239 hw->phy.mdio.mmds = 0; 8240 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 8241 hw->phy.mdio.dev = netdev; 8242 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 8243 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 8244 8245 ii->get_invariants(hw); 8246 8247 /* setup the private structure */ 8248 err = ixgbe_sw_init(adapter); 8249 if (err) 8250 goto err_sw_init; 8251 8252 /* Make it possible the adapter to be woken up via WOL */ 8253 switch (adapter->hw.mac.type) { 8254 case ixgbe_mac_82599EB: 8255 case ixgbe_mac_X540: 8256 case ixgbe_mac_X550: 8257 case ixgbe_mac_X550EM_x: 8258 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 8259 break; 8260 default: 8261 break; 8262 } 8263 8264 /* 8265 * If there is a fan on this device and it has failed log the 8266 * failure. 8267 */ 8268 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 8269 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 8270 if (esdp & IXGBE_ESDP_SDP1) 8271 e_crit(probe, "Fan has stopped, replace the adapter\n"); 8272 } 8273 8274 if (allow_unsupported_sfp) 8275 hw->allow_unsupported_sfp = allow_unsupported_sfp; 8276 8277 /* reset_hw fills in the perm_addr as well */ 8278 hw->phy.reset_if_overtemp = true; 8279 err = hw->mac.ops.reset_hw(hw); 8280 hw->phy.reset_if_overtemp = false; 8281 if (err == IXGBE_ERR_SFP_NOT_PRESENT && 8282 hw->mac.type == ixgbe_mac_82598EB) { 8283 err = 0; 8284 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 8285 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 8286 e_dev_err("Reload the driver after installing a supported module.\n"); 8287 goto err_sw_init; 8288 } else if (err) { 8289 e_dev_err("HW Init failed: %d\n", err); 8290 goto err_sw_init; 8291 } 8292 8293 #ifdef CONFIG_PCI_IOV 8294 /* SR-IOV not supported on the 82598 */ 8295 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 8296 goto skip_sriov; 8297 /* Mailbox */ 8298 ixgbe_init_mbx_params_pf(hw); 8299 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops)); 8300 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 8301 ixgbe_enable_sriov(adapter); 8302 skip_sriov: 8303 8304 #endif 8305 netdev->features = NETIF_F_SG | 8306 NETIF_F_IP_CSUM | 8307 NETIF_F_IPV6_CSUM | 8308 NETIF_F_HW_VLAN_CTAG_TX | 8309 NETIF_F_HW_VLAN_CTAG_RX | 8310 NETIF_F_HW_VLAN_CTAG_FILTER | 8311 NETIF_F_TSO | 8312 NETIF_F_TSO6 | 8313 NETIF_F_RXHASH | 8314 NETIF_F_RXCSUM; 8315 8316 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD; 8317 8318 switch (adapter->hw.mac.type) { 8319 case ixgbe_mac_82599EB: 8320 case ixgbe_mac_X540: 8321 case ixgbe_mac_X550: 8322 case ixgbe_mac_X550EM_x: 8323 netdev->features |= NETIF_F_SCTP_CSUM; 8324 netdev->hw_features |= NETIF_F_SCTP_CSUM | 8325 NETIF_F_NTUPLE; 8326 break; 8327 default: 8328 break; 8329 } 8330 8331 netdev->hw_features |= NETIF_F_RXALL; 8332 8333 netdev->vlan_features |= NETIF_F_TSO; 8334 netdev->vlan_features |= NETIF_F_TSO6; 8335 netdev->vlan_features |= NETIF_F_IP_CSUM; 8336 netdev->vlan_features |= NETIF_F_IPV6_CSUM; 8337 netdev->vlan_features |= NETIF_F_SG; 8338 8339 netdev->priv_flags |= IFF_UNICAST_FLT; 8340 netdev->priv_flags |= IFF_SUPP_NOFCS; 8341 8342 #ifdef CONFIG_IXGBE_DCB 8343 netdev->dcbnl_ops = &dcbnl_ops; 8344 #endif 8345 8346 #ifdef IXGBE_FCOE 8347 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 8348 unsigned int fcoe_l; 8349 8350 if (hw->mac.ops.get_device_caps) { 8351 hw->mac.ops.get_device_caps(hw, &device_caps); 8352 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 8353 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 8354 } 8355 8356 8357 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 8358 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 8359 8360 netdev->features |= NETIF_F_FSO | 8361 NETIF_F_FCOE_CRC; 8362 8363 netdev->vlan_features |= NETIF_F_FSO | 8364 NETIF_F_FCOE_CRC | 8365 NETIF_F_FCOE_MTU; 8366 } 8367 #endif /* IXGBE_FCOE */ 8368 if (pci_using_dac) { 8369 netdev->features |= NETIF_F_HIGHDMA; 8370 netdev->vlan_features |= NETIF_F_HIGHDMA; 8371 } 8372 8373 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 8374 netdev->hw_features |= NETIF_F_LRO; 8375 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 8376 netdev->features |= NETIF_F_LRO; 8377 8378 /* make sure the EEPROM is good */ 8379 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 8380 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 8381 err = -EIO; 8382 goto err_sw_init; 8383 } 8384 8385 ixgbe_get_platform_mac_addr(adapter); 8386 8387 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 8388 8389 if (!is_valid_ether_addr(netdev->dev_addr)) { 8390 e_dev_err("invalid MAC address\n"); 8391 err = -EIO; 8392 goto err_sw_init; 8393 } 8394 8395 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr); 8396 8397 setup_timer(&adapter->service_timer, &ixgbe_service_timer, 8398 (unsigned long) adapter); 8399 8400 if (ixgbe_removed(hw->hw_addr)) { 8401 err = -EIO; 8402 goto err_sw_init; 8403 } 8404 INIT_WORK(&adapter->service_task, ixgbe_service_task); 8405 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 8406 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 8407 8408 err = ixgbe_init_interrupt_scheme(adapter); 8409 if (err) 8410 goto err_sw_init; 8411 8412 /* WOL not supported for all devices */ 8413 adapter->wol = 0; 8414 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 8415 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 8416 pdev->subsystem_device); 8417 if (hw->wol_enabled) 8418 adapter->wol = IXGBE_WUFC_MAG; 8419 8420 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 8421 8422 /* save off EEPROM version number */ 8423 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh); 8424 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl); 8425 8426 /* pick up the PCI bus settings for reporting later */ 8427 hw->mac.ops.get_bus_info(hw); 8428 if (ixgbe_pcie_from_parent(hw)) 8429 ixgbe_get_parent_bus_info(adapter); 8430 8431 /* calculate the expected PCIe bandwidth required for optimal 8432 * performance. Note that some older parts will never have enough 8433 * bandwidth due to being older generation PCIe parts. We clamp these 8434 * parts to ensure no warning is displayed if it can't be fixed. 8435 */ 8436 switch (hw->mac.type) { 8437 case ixgbe_mac_82598EB: 8438 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 8439 break; 8440 default: 8441 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 8442 break; 8443 } 8444 8445 /* don't check link if we failed to enumerate functions */ 8446 if (expected_gts > 0) 8447 ixgbe_check_minimum_link(adapter, expected_gts); 8448 8449 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 8450 if (err) 8451 strlcpy(part_str, "Unknown", sizeof(part_str)); 8452 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 8453 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 8454 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 8455 part_str); 8456 else 8457 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 8458 hw->mac.type, hw->phy.type, part_str); 8459 8460 e_dev_info("%pM\n", netdev->dev_addr); 8461 8462 /* reset the hardware with the new settings */ 8463 err = hw->mac.ops.start_hw(hw); 8464 if (err == IXGBE_ERR_EEPROM_VERSION) { 8465 /* We are running on a pre-production device, log a warning */ 8466 e_dev_warn("This device is a pre-production adapter/LOM. " 8467 "Please be aware there may be issues associated " 8468 "with your hardware. If you are experiencing " 8469 "problems please contact your Intel or hardware " 8470 "representative who provided you with this " 8471 "hardware.\n"); 8472 } 8473 strcpy(netdev->name, "eth%d"); 8474 err = register_netdev(netdev); 8475 if (err) 8476 goto err_register; 8477 8478 pci_set_drvdata(pdev, adapter); 8479 8480 /* power down the optics for 82599 SFP+ fiber */ 8481 if (hw->mac.ops.disable_tx_laser) 8482 hw->mac.ops.disable_tx_laser(hw); 8483 8484 /* carrier off reporting is important to ethtool even BEFORE open */ 8485 netif_carrier_off(netdev); 8486 8487 #ifdef CONFIG_IXGBE_DCA 8488 if (dca_add_requester(&pdev->dev) == 0) { 8489 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 8490 ixgbe_setup_dca(adapter); 8491 } 8492 #endif 8493 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 8494 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 8495 for (i = 0; i < adapter->num_vfs; i++) 8496 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 8497 } 8498 8499 /* firmware requires driver version to be 0xFFFFFFFF 8500 * since os does not support feature 8501 */ 8502 if (hw->mac.ops.set_fw_drv_ver) 8503 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 8504 0xFF); 8505 8506 /* add san mac addr to netdev */ 8507 ixgbe_add_sanmac_netdev(netdev); 8508 8509 e_dev_info("%s\n", ixgbe_default_device_descr); 8510 8511 #ifdef CONFIG_IXGBE_HWMON 8512 if (ixgbe_sysfs_init(adapter)) 8513 e_err(probe, "failed to allocate sysfs resources\n"); 8514 #endif /* CONFIG_IXGBE_HWMON */ 8515 8516 ixgbe_dbg_adapter_init(adapter); 8517 8518 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 8519 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 8520 hw->mac.ops.setup_link(hw, 8521 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 8522 true); 8523 8524 return 0; 8525 8526 err_register: 8527 ixgbe_release_hw_control(adapter); 8528 ixgbe_clear_interrupt_scheme(adapter); 8529 err_sw_init: 8530 ixgbe_disable_sriov(adapter); 8531 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 8532 iounmap(adapter->io_addr); 8533 kfree(adapter->mac_table); 8534 err_ioremap: 8535 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 8536 free_netdev(netdev); 8537 err_alloc_etherdev: 8538 pci_release_selected_regions(pdev, 8539 pci_select_bars(pdev, IORESOURCE_MEM)); 8540 err_pci_reg: 8541 err_dma: 8542 if (!adapter || disable_dev) 8543 pci_disable_device(pdev); 8544 return err; 8545 } 8546 8547 /** 8548 * ixgbe_remove - Device Removal Routine 8549 * @pdev: PCI device information struct 8550 * 8551 * ixgbe_remove is called by the PCI subsystem to alert the driver 8552 * that it should release a PCI device. The could be caused by a 8553 * Hot-Plug event, or because the driver is going to be removed from 8554 * memory. 8555 **/ 8556 static void ixgbe_remove(struct pci_dev *pdev) 8557 { 8558 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 8559 struct net_device *netdev; 8560 bool disable_dev; 8561 8562 /* if !adapter then we already cleaned up in probe */ 8563 if (!adapter) 8564 return; 8565 8566 netdev = adapter->netdev; 8567 ixgbe_dbg_adapter_exit(adapter); 8568 8569 set_bit(__IXGBE_REMOVING, &adapter->state); 8570 cancel_work_sync(&adapter->service_task); 8571 8572 8573 #ifdef CONFIG_IXGBE_DCA 8574 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 8575 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 8576 dca_remove_requester(&pdev->dev); 8577 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); 8578 } 8579 8580 #endif 8581 #ifdef CONFIG_IXGBE_HWMON 8582 ixgbe_sysfs_exit(adapter); 8583 #endif /* CONFIG_IXGBE_HWMON */ 8584 8585 /* remove the added san mac */ 8586 ixgbe_del_sanmac_netdev(netdev); 8587 8588 if (netdev->reg_state == NETREG_REGISTERED) 8589 unregister_netdev(netdev); 8590 8591 #ifdef CONFIG_PCI_IOV 8592 /* 8593 * Only disable SR-IOV on unload if the user specified the now 8594 * deprecated max_vfs module parameter. 8595 */ 8596 if (max_vfs) 8597 ixgbe_disable_sriov(adapter); 8598 #endif 8599 ixgbe_clear_interrupt_scheme(adapter); 8600 8601 ixgbe_release_hw_control(adapter); 8602 8603 #ifdef CONFIG_DCB 8604 kfree(adapter->ixgbe_ieee_pfc); 8605 kfree(adapter->ixgbe_ieee_ets); 8606 8607 #endif 8608 iounmap(adapter->io_addr); 8609 pci_release_selected_regions(pdev, pci_select_bars(pdev, 8610 IORESOURCE_MEM)); 8611 8612 e_dev_info("complete\n"); 8613 8614 kfree(adapter->mac_table); 8615 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 8616 free_netdev(netdev); 8617 8618 pci_disable_pcie_error_reporting(pdev); 8619 8620 if (disable_dev) 8621 pci_disable_device(pdev); 8622 } 8623 8624 /** 8625 * ixgbe_io_error_detected - called when PCI error is detected 8626 * @pdev: Pointer to PCI device 8627 * @state: The current pci connection state 8628 * 8629 * This function is called after a PCI bus error affecting 8630 * this device has been detected. 8631 */ 8632 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 8633 pci_channel_state_t state) 8634 { 8635 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 8636 struct net_device *netdev = adapter->netdev; 8637 8638 #ifdef CONFIG_PCI_IOV 8639 struct ixgbe_hw *hw = &adapter->hw; 8640 struct pci_dev *bdev, *vfdev; 8641 u32 dw0, dw1, dw2, dw3; 8642 int vf, pos; 8643 u16 req_id, pf_func; 8644 8645 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 8646 adapter->num_vfs == 0) 8647 goto skip_bad_vf_detection; 8648 8649 bdev = pdev->bus->self; 8650 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 8651 bdev = bdev->bus->self; 8652 8653 if (!bdev) 8654 goto skip_bad_vf_detection; 8655 8656 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 8657 if (!pos) 8658 goto skip_bad_vf_detection; 8659 8660 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 8661 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 8662 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 8663 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 8664 if (ixgbe_removed(hw->hw_addr)) 8665 goto skip_bad_vf_detection; 8666 8667 req_id = dw1 >> 16; 8668 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 8669 if (!(req_id & 0x0080)) 8670 goto skip_bad_vf_detection; 8671 8672 pf_func = req_id & 0x01; 8673 if ((pf_func & 1) == (pdev->devfn & 1)) { 8674 unsigned int device_id; 8675 8676 vf = (req_id & 0x7F) >> 1; 8677 e_dev_err("VF %d has caused a PCIe error\n", vf); 8678 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 8679 "%8.8x\tdw3: %8.8x\n", 8680 dw0, dw1, dw2, dw3); 8681 switch (adapter->hw.mac.type) { 8682 case ixgbe_mac_82599EB: 8683 device_id = IXGBE_82599_VF_DEVICE_ID; 8684 break; 8685 case ixgbe_mac_X540: 8686 device_id = IXGBE_X540_VF_DEVICE_ID; 8687 break; 8688 case ixgbe_mac_X550: 8689 device_id = IXGBE_DEV_ID_X550_VF; 8690 break; 8691 case ixgbe_mac_X550EM_x: 8692 device_id = IXGBE_DEV_ID_X550EM_X_VF; 8693 break; 8694 default: 8695 device_id = 0; 8696 break; 8697 } 8698 8699 /* Find the pci device of the offending VF */ 8700 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 8701 while (vfdev) { 8702 if (vfdev->devfn == (req_id & 0xFF)) 8703 break; 8704 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 8705 device_id, vfdev); 8706 } 8707 /* 8708 * There's a slim chance the VF could have been hot plugged, 8709 * so if it is no longer present we don't need to issue the 8710 * VFLR. Just clean up the AER in that case. 8711 */ 8712 if (vfdev) { 8713 ixgbe_issue_vf_flr(adapter, vfdev); 8714 /* Free device reference count */ 8715 pci_dev_put(vfdev); 8716 } 8717 8718 pci_cleanup_aer_uncorrect_error_status(pdev); 8719 } 8720 8721 /* 8722 * Even though the error may have occurred on the other port 8723 * we still need to increment the vf error reference count for 8724 * both ports because the I/O resume function will be called 8725 * for both of them. 8726 */ 8727 adapter->vferr_refcount++; 8728 8729 return PCI_ERS_RESULT_RECOVERED; 8730 8731 skip_bad_vf_detection: 8732 #endif /* CONFIG_PCI_IOV */ 8733 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 8734 return PCI_ERS_RESULT_DISCONNECT; 8735 8736 rtnl_lock(); 8737 netif_device_detach(netdev); 8738 8739 if (state == pci_channel_io_perm_failure) { 8740 rtnl_unlock(); 8741 return PCI_ERS_RESULT_DISCONNECT; 8742 } 8743 8744 if (netif_running(netdev)) 8745 ixgbe_down(adapter); 8746 8747 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 8748 pci_disable_device(pdev); 8749 rtnl_unlock(); 8750 8751 /* Request a slot reset. */ 8752 return PCI_ERS_RESULT_NEED_RESET; 8753 } 8754 8755 /** 8756 * ixgbe_io_slot_reset - called after the pci bus has been reset. 8757 * @pdev: Pointer to PCI device 8758 * 8759 * Restart the card from scratch, as if from a cold-boot. 8760 */ 8761 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 8762 { 8763 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 8764 pci_ers_result_t result; 8765 int err; 8766 8767 if (pci_enable_device_mem(pdev)) { 8768 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 8769 result = PCI_ERS_RESULT_DISCONNECT; 8770 } else { 8771 smp_mb__before_atomic(); 8772 clear_bit(__IXGBE_DISABLED, &adapter->state); 8773 adapter->hw.hw_addr = adapter->io_addr; 8774 pci_set_master(pdev); 8775 pci_restore_state(pdev); 8776 pci_save_state(pdev); 8777 8778 pci_wake_from_d3(pdev, false); 8779 8780 ixgbe_reset(adapter); 8781 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 8782 result = PCI_ERS_RESULT_RECOVERED; 8783 } 8784 8785 err = pci_cleanup_aer_uncorrect_error_status(pdev); 8786 if (err) { 8787 e_dev_err("pci_cleanup_aer_uncorrect_error_status " 8788 "failed 0x%0x\n", err); 8789 /* non-fatal, continue */ 8790 } 8791 8792 return result; 8793 } 8794 8795 /** 8796 * ixgbe_io_resume - called when traffic can start flowing again. 8797 * @pdev: Pointer to PCI device 8798 * 8799 * This callback is called when the error recovery driver tells us that 8800 * its OK to resume normal operation. 8801 */ 8802 static void ixgbe_io_resume(struct pci_dev *pdev) 8803 { 8804 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 8805 struct net_device *netdev = adapter->netdev; 8806 8807 #ifdef CONFIG_PCI_IOV 8808 if (adapter->vferr_refcount) { 8809 e_info(drv, "Resuming after VF err\n"); 8810 adapter->vferr_refcount--; 8811 return; 8812 } 8813 8814 #endif 8815 if (netif_running(netdev)) 8816 ixgbe_up(adapter); 8817 8818 netif_device_attach(netdev); 8819 } 8820 8821 static const struct pci_error_handlers ixgbe_err_handler = { 8822 .error_detected = ixgbe_io_error_detected, 8823 .slot_reset = ixgbe_io_slot_reset, 8824 .resume = ixgbe_io_resume, 8825 }; 8826 8827 static struct pci_driver ixgbe_driver = { 8828 .name = ixgbe_driver_name, 8829 .id_table = ixgbe_pci_tbl, 8830 .probe = ixgbe_probe, 8831 .remove = ixgbe_remove, 8832 #ifdef CONFIG_PM 8833 .suspend = ixgbe_suspend, 8834 .resume = ixgbe_resume, 8835 #endif 8836 .shutdown = ixgbe_shutdown, 8837 .sriov_configure = ixgbe_pci_sriov_configure, 8838 .err_handler = &ixgbe_err_handler 8839 }; 8840 8841 /** 8842 * ixgbe_init_module - Driver Registration Routine 8843 * 8844 * ixgbe_init_module is the first routine called when the driver is 8845 * loaded. All it does is register with the PCI subsystem. 8846 **/ 8847 static int __init ixgbe_init_module(void) 8848 { 8849 int ret; 8850 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); 8851 pr_info("%s\n", ixgbe_copyright); 8852 8853 ixgbe_dbg_init(); 8854 8855 ret = pci_register_driver(&ixgbe_driver); 8856 if (ret) { 8857 ixgbe_dbg_exit(); 8858 return ret; 8859 } 8860 8861 #ifdef CONFIG_IXGBE_DCA 8862 dca_register_notify(&dca_notifier); 8863 #endif 8864 8865 return 0; 8866 } 8867 8868 module_init(ixgbe_init_module); 8869 8870 /** 8871 * ixgbe_exit_module - Driver Exit Cleanup Routine 8872 * 8873 * ixgbe_exit_module is called just before the driver is removed 8874 * from memory. 8875 **/ 8876 static void __exit ixgbe_exit_module(void) 8877 { 8878 #ifdef CONFIG_IXGBE_DCA 8879 dca_unregister_notify(&dca_notifier); 8880 #endif 8881 pci_unregister_driver(&ixgbe_driver); 8882 8883 ixgbe_dbg_exit(); 8884 8885 rcu_barrier(); /* Wait for completion of call_rcu()'s */ 8886 } 8887 8888 #ifdef CONFIG_IXGBE_DCA 8889 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 8890 void *p) 8891 { 8892 int ret_val; 8893 8894 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 8895 __ixgbe_notify_dca); 8896 8897 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 8898 } 8899 8900 #endif /* CONFIG_IXGBE_DCA */ 8901 8902 module_exit(ixgbe_exit_module); 8903 8904 /* ixgbe_main.c */ 8905