1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/types.h> 30 #include <linux/module.h> 31 #include <linux/pci.h> 32 #include <linux/netdevice.h> 33 #include <linux/vmalloc.h> 34 #include <linux/string.h> 35 #include <linux/in.h> 36 #include <linux/interrupt.h> 37 #include <linux/ip.h> 38 #include <linux/tcp.h> 39 #include <linux/sctp.h> 40 #include <linux/pkt_sched.h> 41 #include <linux/ipv6.h> 42 #include <linux/slab.h> 43 #include <net/checksum.h> 44 #include <net/ip6_checksum.h> 45 #include <linux/etherdevice.h> 46 #include <linux/ethtool.h> 47 #include <linux/if.h> 48 #include <linux/if_vlan.h> 49 #include <linux/if_macvlan.h> 50 #include <linux/if_bridge.h> 51 #include <linux/prefetch.h> 52 #include <scsi/fc/fc_fcoe.h> 53 #include <net/vxlan.h> 54 55 #ifdef CONFIG_OF 56 #include <linux/of_net.h> 57 #endif 58 59 #ifdef CONFIG_SPARC 60 #include <asm/idprom.h> 61 #include <asm/prom.h> 62 #endif 63 64 #include "ixgbe.h" 65 #include "ixgbe_common.h" 66 #include "ixgbe_dcb_82599.h" 67 #include "ixgbe_sriov.h" 68 69 char ixgbe_driver_name[] = "ixgbe"; 70 static const char ixgbe_driver_string[] = 71 "Intel(R) 10 Gigabit PCI Express Network Driver"; 72 #ifdef IXGBE_FCOE 73 char ixgbe_default_device_descr[] = 74 "Intel(R) 10 Gigabit Network Connection"; 75 #else 76 static char ixgbe_default_device_descr[] = 77 "Intel(R) 10 Gigabit Network Connection"; 78 #endif 79 #define DRV_VERSION "4.0.1-k" 80 const char ixgbe_driver_version[] = DRV_VERSION; 81 static const char ixgbe_copyright[] = 82 "Copyright (c) 1999-2014 Intel Corporation."; 83 84 static const struct ixgbe_info *ixgbe_info_tbl[] = { 85 [board_82598] = &ixgbe_82598_info, 86 [board_82599] = &ixgbe_82599_info, 87 [board_X540] = &ixgbe_X540_info, 88 [board_X550] = &ixgbe_X550_info, 89 [board_X550EM_x] = &ixgbe_X550EM_x_info, 90 }; 91 92 /* ixgbe_pci_tbl - PCI Device ID Table 93 * 94 * Wildcard entries (PCI_ANY_ID) should come last 95 * Last entry must be all 0s 96 * 97 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 98 * Class, Class Mask, private data (not used) } 99 */ 100 static const struct pci_device_id ixgbe_pci_tbl[] = { 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 134 /* required last entry */ 135 {0, } 136 }; 137 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 138 139 #ifdef CONFIG_IXGBE_DCA 140 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 141 void *p); 142 static struct notifier_block dca_notifier = { 143 .notifier_call = ixgbe_notify_dca, 144 .next = NULL, 145 .priority = 0 146 }; 147 #endif 148 149 #ifdef CONFIG_PCI_IOV 150 static unsigned int max_vfs; 151 module_param(max_vfs, uint, 0); 152 MODULE_PARM_DESC(max_vfs, 153 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 154 #endif /* CONFIG_PCI_IOV */ 155 156 static unsigned int allow_unsupported_sfp; 157 module_param(allow_unsupported_sfp, uint, 0); 158 MODULE_PARM_DESC(allow_unsupported_sfp, 159 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 160 161 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 162 static int debug = -1; 163 module_param(debug, int, 0); 164 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 165 166 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 167 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 168 MODULE_LICENSE("GPL"); 169 MODULE_VERSION(DRV_VERSION); 170 171 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 172 173 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 174 u32 reg, u16 *value) 175 { 176 struct pci_dev *parent_dev; 177 struct pci_bus *parent_bus; 178 179 parent_bus = adapter->pdev->bus->parent; 180 if (!parent_bus) 181 return -1; 182 183 parent_dev = parent_bus->self; 184 if (!parent_dev) 185 return -1; 186 187 if (!pci_is_pcie(parent_dev)) 188 return -1; 189 190 pcie_capability_read_word(parent_dev, reg, value); 191 if (*value == IXGBE_FAILED_READ_CFG_WORD && 192 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 193 return -1; 194 return 0; 195 } 196 197 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 198 { 199 struct ixgbe_hw *hw = &adapter->hw; 200 u16 link_status = 0; 201 int err; 202 203 hw->bus.type = ixgbe_bus_type_pci_express; 204 205 /* Get the negotiated link width and speed from PCI config space of the 206 * parent, as this device is behind a switch 207 */ 208 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 209 210 /* assume caller will handle error case */ 211 if (err) 212 return err; 213 214 hw->bus.width = ixgbe_convert_bus_width(link_status); 215 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 216 217 return 0; 218 } 219 220 /** 221 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent 222 * @hw: hw specific details 223 * 224 * This function is used by probe to determine whether a device's PCI-Express 225 * bandwidth details should be gathered from the parent bus instead of from the 226 * device. Used to ensure that various locations all have the correct device ID 227 * checks. 228 */ 229 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 230 { 231 switch (hw->device_id) { 232 case IXGBE_DEV_ID_82599_SFP_SF_QP: 233 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 234 return true; 235 default: 236 return false; 237 } 238 } 239 240 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 241 int expected_gts) 242 { 243 int max_gts = 0; 244 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; 245 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; 246 struct pci_dev *pdev; 247 248 /* determine whether to use the the parent device 249 */ 250 if (ixgbe_pcie_from_parent(&adapter->hw)) 251 pdev = adapter->pdev->bus->parent->self; 252 else 253 pdev = adapter->pdev; 254 255 if (pcie_get_minimum_link(pdev, &speed, &width) || 256 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { 257 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 258 return; 259 } 260 261 switch (speed) { 262 case PCIE_SPEED_2_5GT: 263 /* 8b/10b encoding reduces max throughput by 20% */ 264 max_gts = 2 * width; 265 break; 266 case PCIE_SPEED_5_0GT: 267 /* 8b/10b encoding reduces max throughput by 20% */ 268 max_gts = 4 * width; 269 break; 270 case PCIE_SPEED_8_0GT: 271 /* 128b/130b encoding reduces throughput by less than 2% */ 272 max_gts = 8 * width; 273 break; 274 default: 275 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 276 return; 277 } 278 279 e_dev_info("PCI Express bandwidth of %dGT/s available\n", 280 max_gts); 281 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n", 282 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : 283 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : 284 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : 285 "Unknown"), 286 width, 287 (speed == PCIE_SPEED_2_5GT ? "20%" : 288 speed == PCIE_SPEED_5_0GT ? "20%" : 289 speed == PCIE_SPEED_8_0GT ? "<2%" : 290 "Unknown")); 291 292 if (max_gts < expected_gts) { 293 e_dev_warn("This is not sufficient for optimal performance of this card.\n"); 294 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n", 295 expected_gts); 296 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n"); 297 } 298 } 299 300 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 301 { 302 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 303 !test_bit(__IXGBE_REMOVING, &adapter->state) && 304 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 305 schedule_work(&adapter->service_task); 306 } 307 308 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 309 { 310 struct ixgbe_adapter *adapter = hw->back; 311 312 if (!hw->hw_addr) 313 return; 314 hw->hw_addr = NULL; 315 e_dev_err("Adapter removed\n"); 316 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 317 ixgbe_service_event_schedule(adapter); 318 } 319 320 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 321 { 322 u32 value; 323 324 /* The following check not only optimizes a bit by not 325 * performing a read on the status register when the 326 * register just read was a status register read that 327 * returned IXGBE_FAILED_READ_REG. It also blocks any 328 * potential recursion. 329 */ 330 if (reg == IXGBE_STATUS) { 331 ixgbe_remove_adapter(hw); 332 return; 333 } 334 value = ixgbe_read_reg(hw, IXGBE_STATUS); 335 if (value == IXGBE_FAILED_READ_REG) 336 ixgbe_remove_adapter(hw); 337 } 338 339 /** 340 * ixgbe_read_reg - Read from device register 341 * @hw: hw specific details 342 * @reg: offset of register to read 343 * 344 * Returns : value read or IXGBE_FAILED_READ_REG if removed 345 * 346 * This function is used to read device registers. It checks for device 347 * removal by confirming any read that returns all ones by checking the 348 * status register value for all ones. This function avoids reading from 349 * the hardware if a removal was previously detected in which case it 350 * returns IXGBE_FAILED_READ_REG (all ones). 351 */ 352 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 353 { 354 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr); 355 u32 value; 356 357 if (ixgbe_removed(reg_addr)) 358 return IXGBE_FAILED_READ_REG; 359 value = readl(reg_addr + reg); 360 if (unlikely(value == IXGBE_FAILED_READ_REG)) 361 ixgbe_check_remove(hw, reg); 362 return value; 363 } 364 365 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 366 { 367 u16 value; 368 369 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 370 if (value == IXGBE_FAILED_READ_CFG_WORD) { 371 ixgbe_remove_adapter(hw); 372 return true; 373 } 374 return false; 375 } 376 377 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 378 { 379 struct ixgbe_adapter *adapter = hw->back; 380 u16 value; 381 382 if (ixgbe_removed(hw->hw_addr)) 383 return IXGBE_FAILED_READ_CFG_WORD; 384 pci_read_config_word(adapter->pdev, reg, &value); 385 if (value == IXGBE_FAILED_READ_CFG_WORD && 386 ixgbe_check_cfg_remove(hw, adapter->pdev)) 387 return IXGBE_FAILED_READ_CFG_WORD; 388 return value; 389 } 390 391 #ifdef CONFIG_PCI_IOV 392 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 393 { 394 struct ixgbe_adapter *adapter = hw->back; 395 u32 value; 396 397 if (ixgbe_removed(hw->hw_addr)) 398 return IXGBE_FAILED_READ_CFG_DWORD; 399 pci_read_config_dword(adapter->pdev, reg, &value); 400 if (value == IXGBE_FAILED_READ_CFG_DWORD && 401 ixgbe_check_cfg_remove(hw, adapter->pdev)) 402 return IXGBE_FAILED_READ_CFG_DWORD; 403 return value; 404 } 405 #endif /* CONFIG_PCI_IOV */ 406 407 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 408 { 409 struct ixgbe_adapter *adapter = hw->back; 410 411 if (ixgbe_removed(hw->hw_addr)) 412 return; 413 pci_write_config_word(adapter->pdev, reg, value); 414 } 415 416 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 417 { 418 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 419 420 /* flush memory to make sure state is correct before next watchdog */ 421 smp_mb__before_atomic(); 422 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 423 } 424 425 struct ixgbe_reg_info { 426 u32 ofs; 427 char *name; 428 }; 429 430 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 431 432 /* General Registers */ 433 {IXGBE_CTRL, "CTRL"}, 434 {IXGBE_STATUS, "STATUS"}, 435 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 436 437 /* Interrupt Registers */ 438 {IXGBE_EICR, "EICR"}, 439 440 /* RX Registers */ 441 {IXGBE_SRRCTL(0), "SRRCTL"}, 442 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 443 {IXGBE_RDLEN(0), "RDLEN"}, 444 {IXGBE_RDH(0), "RDH"}, 445 {IXGBE_RDT(0), "RDT"}, 446 {IXGBE_RXDCTL(0), "RXDCTL"}, 447 {IXGBE_RDBAL(0), "RDBAL"}, 448 {IXGBE_RDBAH(0), "RDBAH"}, 449 450 /* TX Registers */ 451 {IXGBE_TDBAL(0), "TDBAL"}, 452 {IXGBE_TDBAH(0), "TDBAH"}, 453 {IXGBE_TDLEN(0), "TDLEN"}, 454 {IXGBE_TDH(0), "TDH"}, 455 {IXGBE_TDT(0), "TDT"}, 456 {IXGBE_TXDCTL(0), "TXDCTL"}, 457 458 /* List Terminator */ 459 { .name = NULL } 460 }; 461 462 463 /* 464 * ixgbe_regdump - register printout routine 465 */ 466 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 467 { 468 int i = 0, j = 0; 469 char rname[16]; 470 u32 regs[64]; 471 472 switch (reginfo->ofs) { 473 case IXGBE_SRRCTL(0): 474 for (i = 0; i < 64; i++) 475 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 476 break; 477 case IXGBE_DCA_RXCTRL(0): 478 for (i = 0; i < 64; i++) 479 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 480 break; 481 case IXGBE_RDLEN(0): 482 for (i = 0; i < 64; i++) 483 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 484 break; 485 case IXGBE_RDH(0): 486 for (i = 0; i < 64; i++) 487 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 488 break; 489 case IXGBE_RDT(0): 490 for (i = 0; i < 64; i++) 491 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 492 break; 493 case IXGBE_RXDCTL(0): 494 for (i = 0; i < 64; i++) 495 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 496 break; 497 case IXGBE_RDBAL(0): 498 for (i = 0; i < 64; i++) 499 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 500 break; 501 case IXGBE_RDBAH(0): 502 for (i = 0; i < 64; i++) 503 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 504 break; 505 case IXGBE_TDBAL(0): 506 for (i = 0; i < 64; i++) 507 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 508 break; 509 case IXGBE_TDBAH(0): 510 for (i = 0; i < 64; i++) 511 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 512 break; 513 case IXGBE_TDLEN(0): 514 for (i = 0; i < 64; i++) 515 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 516 break; 517 case IXGBE_TDH(0): 518 for (i = 0; i < 64; i++) 519 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 520 break; 521 case IXGBE_TDT(0): 522 for (i = 0; i < 64; i++) 523 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 524 break; 525 case IXGBE_TXDCTL(0): 526 for (i = 0; i < 64; i++) 527 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 528 break; 529 default: 530 pr_info("%-15s %08x\n", reginfo->name, 531 IXGBE_READ_REG(hw, reginfo->ofs)); 532 return; 533 } 534 535 for (i = 0; i < 8; i++) { 536 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); 537 pr_err("%-15s", rname); 538 for (j = 0; j < 8; j++) 539 pr_cont(" %08x", regs[i*8+j]); 540 pr_cont("\n"); 541 } 542 543 } 544 545 /* 546 * ixgbe_dump - Print registers, tx-rings and rx-rings 547 */ 548 static void ixgbe_dump(struct ixgbe_adapter *adapter) 549 { 550 struct net_device *netdev = adapter->netdev; 551 struct ixgbe_hw *hw = &adapter->hw; 552 struct ixgbe_reg_info *reginfo; 553 int n = 0; 554 struct ixgbe_ring *tx_ring; 555 struct ixgbe_tx_buffer *tx_buffer; 556 union ixgbe_adv_tx_desc *tx_desc; 557 struct my_u0 { u64 a; u64 b; } *u0; 558 struct ixgbe_ring *rx_ring; 559 union ixgbe_adv_rx_desc *rx_desc; 560 struct ixgbe_rx_buffer *rx_buffer_info; 561 u32 staterr; 562 int i = 0; 563 564 if (!netif_msg_hw(adapter)) 565 return; 566 567 /* Print netdevice Info */ 568 if (netdev) { 569 dev_info(&adapter->pdev->dev, "Net device Info\n"); 570 pr_info("Device Name state " 571 "trans_start last_rx\n"); 572 pr_info("%-15s %016lX %016lX %016lX\n", 573 netdev->name, 574 netdev->state, 575 netdev->trans_start, 576 netdev->last_rx); 577 } 578 579 /* Print Registers */ 580 dev_info(&adapter->pdev->dev, "Register Dump\n"); 581 pr_info(" Register Name Value\n"); 582 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 583 reginfo->name; reginfo++) { 584 ixgbe_regdump(hw, reginfo); 585 } 586 587 /* Print TX Ring Summary */ 588 if (!netdev || !netif_running(netdev)) 589 return; 590 591 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 592 pr_info(" %s %s %s %s\n", 593 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 594 "leng", "ntw", "timestamp"); 595 for (n = 0; n < adapter->num_tx_queues; n++) { 596 tx_ring = adapter->tx_ring[n]; 597 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 598 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 599 n, tx_ring->next_to_use, tx_ring->next_to_clean, 600 (u64)dma_unmap_addr(tx_buffer, dma), 601 dma_unmap_len(tx_buffer, len), 602 tx_buffer->next_to_watch, 603 (u64)tx_buffer->time_stamp); 604 } 605 606 /* Print TX Rings */ 607 if (!netif_msg_tx_done(adapter)) 608 goto rx_ring_summary; 609 610 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 611 612 /* Transmit Descriptor Formats 613 * 614 * 82598 Advanced Transmit Descriptor 615 * +--------------------------------------------------------------+ 616 * 0 | Buffer Address [63:0] | 617 * +--------------------------------------------------------------+ 618 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 619 * +--------------------------------------------------------------+ 620 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 621 * 622 * 82598 Advanced Transmit Descriptor (Write-Back Format) 623 * +--------------------------------------------------------------+ 624 * 0 | RSV [63:0] | 625 * +--------------------------------------------------------------+ 626 * 8 | RSV | STA | NXTSEQ | 627 * +--------------------------------------------------------------+ 628 * 63 36 35 32 31 0 629 * 630 * 82599+ Advanced Transmit Descriptor 631 * +--------------------------------------------------------------+ 632 * 0 | Buffer Address [63:0] | 633 * +--------------------------------------------------------------+ 634 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 635 * +--------------------------------------------------------------+ 636 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 637 * 638 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 639 * +--------------------------------------------------------------+ 640 * 0 | RSV [63:0] | 641 * +--------------------------------------------------------------+ 642 * 8 | RSV | STA | RSV | 643 * +--------------------------------------------------------------+ 644 * 63 36 35 32 31 0 645 */ 646 647 for (n = 0; n < adapter->num_tx_queues; n++) { 648 tx_ring = adapter->tx_ring[n]; 649 pr_info("------------------------------------\n"); 650 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 651 pr_info("------------------------------------\n"); 652 pr_info("%s%s %s %s %s %s\n", 653 "T [desc] [address 63:0 ] ", 654 "[PlPOIdStDDt Ln] [bi->dma ] ", 655 "leng", "ntw", "timestamp", "bi->skb"); 656 657 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 658 tx_desc = IXGBE_TX_DESC(tx_ring, i); 659 tx_buffer = &tx_ring->tx_buffer_info[i]; 660 u0 = (struct my_u0 *)tx_desc; 661 if (dma_unmap_len(tx_buffer, len) > 0) { 662 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p", 663 i, 664 le64_to_cpu(u0->a), 665 le64_to_cpu(u0->b), 666 (u64)dma_unmap_addr(tx_buffer, dma), 667 dma_unmap_len(tx_buffer, len), 668 tx_buffer->next_to_watch, 669 (u64)tx_buffer->time_stamp, 670 tx_buffer->skb); 671 if (i == tx_ring->next_to_use && 672 i == tx_ring->next_to_clean) 673 pr_cont(" NTC/U\n"); 674 else if (i == tx_ring->next_to_use) 675 pr_cont(" NTU\n"); 676 else if (i == tx_ring->next_to_clean) 677 pr_cont(" NTC\n"); 678 else 679 pr_cont("\n"); 680 681 if (netif_msg_pktdata(adapter) && 682 tx_buffer->skb) 683 print_hex_dump(KERN_INFO, "", 684 DUMP_PREFIX_ADDRESS, 16, 1, 685 tx_buffer->skb->data, 686 dma_unmap_len(tx_buffer, len), 687 true); 688 } 689 } 690 } 691 692 /* Print RX Rings Summary */ 693 rx_ring_summary: 694 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 695 pr_info("Queue [NTU] [NTC]\n"); 696 for (n = 0; n < adapter->num_rx_queues; n++) { 697 rx_ring = adapter->rx_ring[n]; 698 pr_info("%5d %5X %5X\n", 699 n, rx_ring->next_to_use, rx_ring->next_to_clean); 700 } 701 702 /* Print RX Rings */ 703 if (!netif_msg_rx_status(adapter)) 704 return; 705 706 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 707 708 /* Receive Descriptor Formats 709 * 710 * 82598 Advanced Receive Descriptor (Read) Format 711 * 63 1 0 712 * +-----------------------------------------------------+ 713 * 0 | Packet Buffer Address [63:1] |A0/NSE| 714 * +----------------------------------------------+------+ 715 * 8 | Header Buffer Address [63:1] | DD | 716 * +-----------------------------------------------------+ 717 * 718 * 719 * 82598 Advanced Receive Descriptor (Write-Back) Format 720 * 721 * 63 48 47 32 31 30 21 20 16 15 4 3 0 722 * +------------------------------------------------------+ 723 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 724 * | Packet | IP | | | | Type | Type | 725 * | Checksum | Ident | | | | | | 726 * +------------------------------------------------------+ 727 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 728 * +------------------------------------------------------+ 729 * 63 48 47 32 31 20 19 0 730 * 731 * 82599+ Advanced Receive Descriptor (Read) Format 732 * 63 1 0 733 * +-----------------------------------------------------+ 734 * 0 | Packet Buffer Address [63:1] |A0/NSE| 735 * +----------------------------------------------+------+ 736 * 8 | Header Buffer Address [63:1] | DD | 737 * +-----------------------------------------------------+ 738 * 739 * 740 * 82599+ Advanced Receive Descriptor (Write-Back) Format 741 * 742 * 63 48 47 32 31 30 21 20 17 16 4 3 0 743 * +------------------------------------------------------+ 744 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 745 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 746 * |/ Flow Dir Flt ID | | | | | | 747 * +------------------------------------------------------+ 748 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 749 * +------------------------------------------------------+ 750 * 63 48 47 32 31 20 19 0 751 */ 752 753 for (n = 0; n < adapter->num_rx_queues; n++) { 754 rx_ring = adapter->rx_ring[n]; 755 pr_info("------------------------------------\n"); 756 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 757 pr_info("------------------------------------\n"); 758 pr_info("%s%s%s", 759 "R [desc] [ PktBuf A0] ", 760 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 761 "<-- Adv Rx Read format\n"); 762 pr_info("%s%s%s", 763 "RWB[desc] [PcsmIpSHl PtRs] ", 764 "[vl er S cks ln] ---------------- [bi->skb ] ", 765 "<-- Adv Rx Write-Back format\n"); 766 767 for (i = 0; i < rx_ring->count; i++) { 768 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 769 rx_desc = IXGBE_RX_DESC(rx_ring, i); 770 u0 = (struct my_u0 *)rx_desc; 771 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 772 if (staterr & IXGBE_RXD_STAT_DD) { 773 /* Descriptor Done */ 774 pr_info("RWB[0x%03X] %016llX " 775 "%016llX ---------------- %p", i, 776 le64_to_cpu(u0->a), 777 le64_to_cpu(u0->b), 778 rx_buffer_info->skb); 779 } else { 780 pr_info("R [0x%03X] %016llX " 781 "%016llX %016llX %p", i, 782 le64_to_cpu(u0->a), 783 le64_to_cpu(u0->b), 784 (u64)rx_buffer_info->dma, 785 rx_buffer_info->skb); 786 787 if (netif_msg_pktdata(adapter) && 788 rx_buffer_info->dma) { 789 print_hex_dump(KERN_INFO, "", 790 DUMP_PREFIX_ADDRESS, 16, 1, 791 page_address(rx_buffer_info->page) + 792 rx_buffer_info->page_offset, 793 ixgbe_rx_bufsz(rx_ring), true); 794 } 795 } 796 797 if (i == rx_ring->next_to_use) 798 pr_cont(" NTU\n"); 799 else if (i == rx_ring->next_to_clean) 800 pr_cont(" NTC\n"); 801 else 802 pr_cont("\n"); 803 804 } 805 } 806 } 807 808 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 809 { 810 u32 ctrl_ext; 811 812 /* Let firmware take over control of h/w */ 813 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 814 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 815 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 816 } 817 818 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 819 { 820 u32 ctrl_ext; 821 822 /* Let firmware know the driver has taken over */ 823 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 824 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 825 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 826 } 827 828 /** 829 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 830 * @adapter: pointer to adapter struct 831 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 832 * @queue: queue to map the corresponding interrupt to 833 * @msix_vector: the vector to map to the corresponding queue 834 * 835 */ 836 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 837 u8 queue, u8 msix_vector) 838 { 839 u32 ivar, index; 840 struct ixgbe_hw *hw = &adapter->hw; 841 switch (hw->mac.type) { 842 case ixgbe_mac_82598EB: 843 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 844 if (direction == -1) 845 direction = 0; 846 index = (((direction * 64) + queue) >> 2) & 0x1F; 847 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 848 ivar &= ~(0xFF << (8 * (queue & 0x3))); 849 ivar |= (msix_vector << (8 * (queue & 0x3))); 850 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 851 break; 852 case ixgbe_mac_82599EB: 853 case ixgbe_mac_X540: 854 case ixgbe_mac_X550: 855 case ixgbe_mac_X550EM_x: 856 if (direction == -1) { 857 /* other causes */ 858 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 859 index = ((queue & 1) * 8); 860 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 861 ivar &= ~(0xFF << index); 862 ivar |= (msix_vector << index); 863 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 864 break; 865 } else { 866 /* tx or rx causes */ 867 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 868 index = ((16 * (queue & 1)) + (8 * direction)); 869 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 870 ivar &= ~(0xFF << index); 871 ivar |= (msix_vector << index); 872 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 873 break; 874 } 875 default: 876 break; 877 } 878 } 879 880 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 881 u64 qmask) 882 { 883 u32 mask; 884 885 switch (adapter->hw.mac.type) { 886 case ixgbe_mac_82598EB: 887 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 888 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 889 break; 890 case ixgbe_mac_82599EB: 891 case ixgbe_mac_X540: 892 case ixgbe_mac_X550: 893 case ixgbe_mac_X550EM_x: 894 mask = (qmask & 0xFFFFFFFF); 895 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 896 mask = (qmask >> 32); 897 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 898 break; 899 default: 900 break; 901 } 902 } 903 904 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring, 905 struct ixgbe_tx_buffer *tx_buffer) 906 { 907 if (tx_buffer->skb) { 908 dev_kfree_skb_any(tx_buffer->skb); 909 if (dma_unmap_len(tx_buffer, len)) 910 dma_unmap_single(ring->dev, 911 dma_unmap_addr(tx_buffer, dma), 912 dma_unmap_len(tx_buffer, len), 913 DMA_TO_DEVICE); 914 } else if (dma_unmap_len(tx_buffer, len)) { 915 dma_unmap_page(ring->dev, 916 dma_unmap_addr(tx_buffer, dma), 917 dma_unmap_len(tx_buffer, len), 918 DMA_TO_DEVICE); 919 } 920 tx_buffer->next_to_watch = NULL; 921 tx_buffer->skb = NULL; 922 dma_unmap_len_set(tx_buffer, len, 0); 923 /* tx_buffer must be completely set up in the transmit path */ 924 } 925 926 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 927 { 928 struct ixgbe_hw *hw = &adapter->hw; 929 struct ixgbe_hw_stats *hwstats = &adapter->stats; 930 int i; 931 u32 data; 932 933 if ((hw->fc.current_mode != ixgbe_fc_full) && 934 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 935 return; 936 937 switch (hw->mac.type) { 938 case ixgbe_mac_82598EB: 939 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 940 break; 941 default: 942 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 943 } 944 hwstats->lxoffrxc += data; 945 946 /* refill credits (no tx hang) if we received xoff */ 947 if (!data) 948 return; 949 950 for (i = 0; i < adapter->num_tx_queues; i++) 951 clear_bit(__IXGBE_HANG_CHECK_ARMED, 952 &adapter->tx_ring[i]->state); 953 } 954 955 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 956 { 957 struct ixgbe_hw *hw = &adapter->hw; 958 struct ixgbe_hw_stats *hwstats = &adapter->stats; 959 u32 xoff[8] = {0}; 960 u8 tc; 961 int i; 962 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 963 964 if (adapter->ixgbe_ieee_pfc) 965 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 966 967 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 968 ixgbe_update_xoff_rx_lfc(adapter); 969 return; 970 } 971 972 /* update stats for each tc, only valid with PFC enabled */ 973 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 974 u32 pxoffrxc; 975 976 switch (hw->mac.type) { 977 case ixgbe_mac_82598EB: 978 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 979 break; 980 default: 981 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 982 } 983 hwstats->pxoffrxc[i] += pxoffrxc; 984 /* Get the TC for given UP */ 985 tc = netdev_get_prio_tc_map(adapter->netdev, i); 986 xoff[tc] += pxoffrxc; 987 } 988 989 /* disarm tx queues that have received xoff frames */ 990 for (i = 0; i < adapter->num_tx_queues; i++) { 991 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 992 993 tc = tx_ring->dcb_tc; 994 if (xoff[tc]) 995 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 996 } 997 } 998 999 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1000 { 1001 return ring->stats.packets; 1002 } 1003 1004 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1005 { 1006 struct ixgbe_adapter *adapter; 1007 struct ixgbe_hw *hw; 1008 u32 head, tail; 1009 1010 if (ring->l2_accel_priv) 1011 adapter = ring->l2_accel_priv->real_adapter; 1012 else 1013 adapter = netdev_priv(ring->netdev); 1014 1015 hw = &adapter->hw; 1016 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); 1017 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); 1018 1019 if (head != tail) 1020 return (head < tail) ? 1021 tail - head : (tail + ring->count - head); 1022 1023 return 0; 1024 } 1025 1026 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1027 { 1028 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1029 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1030 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1031 1032 clear_check_for_tx_hang(tx_ring); 1033 1034 /* 1035 * Check for a hung queue, but be thorough. This verifies 1036 * that a transmit has been completed since the previous 1037 * check AND there is at least one packet pending. The 1038 * ARMED bit is set to indicate a potential hang. The 1039 * bit is cleared if a pause frame is received to remove 1040 * false hang detection due to PFC or 802.3x frames. By 1041 * requiring this to fail twice we avoid races with 1042 * pfc clearing the ARMED bit and conditions where we 1043 * run the check_tx_hang logic with a transmit completion 1044 * pending but without time to complete it yet. 1045 */ 1046 if (tx_done_old == tx_done && tx_pending) 1047 /* make sure it is true for two checks in a row */ 1048 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1049 &tx_ring->state); 1050 /* update completed stats and continue */ 1051 tx_ring->tx_stats.tx_done_old = tx_done; 1052 /* reset the countdown */ 1053 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1054 1055 return false; 1056 } 1057 1058 /** 1059 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1060 * @adapter: driver private struct 1061 **/ 1062 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1063 { 1064 1065 /* Do the reset outside of interrupt context */ 1066 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1067 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 1068 e_warn(drv, "initiating reset due to tx timeout\n"); 1069 ixgbe_service_event_schedule(adapter); 1070 } 1071 } 1072 1073 /** 1074 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1075 * @q_vector: structure containing interrupt and ring information 1076 * @tx_ring: tx ring to clean 1077 **/ 1078 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1079 struct ixgbe_ring *tx_ring) 1080 { 1081 struct ixgbe_adapter *adapter = q_vector->adapter; 1082 struct ixgbe_tx_buffer *tx_buffer; 1083 union ixgbe_adv_tx_desc *tx_desc; 1084 unsigned int total_bytes = 0, total_packets = 0; 1085 unsigned int budget = q_vector->tx.work_limit; 1086 unsigned int i = tx_ring->next_to_clean; 1087 1088 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1089 return true; 1090 1091 tx_buffer = &tx_ring->tx_buffer_info[i]; 1092 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1093 i -= tx_ring->count; 1094 1095 do { 1096 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1097 1098 /* if next_to_watch is not set then there is no work pending */ 1099 if (!eop_desc) 1100 break; 1101 1102 /* prevent any other reads prior to eop_desc */ 1103 read_barrier_depends(); 1104 1105 /* if DD is not set pending work has not been completed */ 1106 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1107 break; 1108 1109 /* clear next_to_watch to prevent false hangs */ 1110 tx_buffer->next_to_watch = NULL; 1111 1112 /* update the statistics for this packet */ 1113 total_bytes += tx_buffer->bytecount; 1114 total_packets += tx_buffer->gso_segs; 1115 1116 /* free the skb */ 1117 dev_consume_skb_any(tx_buffer->skb); 1118 1119 /* unmap skb header data */ 1120 dma_unmap_single(tx_ring->dev, 1121 dma_unmap_addr(tx_buffer, dma), 1122 dma_unmap_len(tx_buffer, len), 1123 DMA_TO_DEVICE); 1124 1125 /* clear tx_buffer data */ 1126 tx_buffer->skb = NULL; 1127 dma_unmap_len_set(tx_buffer, len, 0); 1128 1129 /* unmap remaining buffers */ 1130 while (tx_desc != eop_desc) { 1131 tx_buffer++; 1132 tx_desc++; 1133 i++; 1134 if (unlikely(!i)) { 1135 i -= tx_ring->count; 1136 tx_buffer = tx_ring->tx_buffer_info; 1137 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1138 } 1139 1140 /* unmap any remaining paged data */ 1141 if (dma_unmap_len(tx_buffer, len)) { 1142 dma_unmap_page(tx_ring->dev, 1143 dma_unmap_addr(tx_buffer, dma), 1144 dma_unmap_len(tx_buffer, len), 1145 DMA_TO_DEVICE); 1146 dma_unmap_len_set(tx_buffer, len, 0); 1147 } 1148 } 1149 1150 /* move us one more past the eop_desc for start of next pkt */ 1151 tx_buffer++; 1152 tx_desc++; 1153 i++; 1154 if (unlikely(!i)) { 1155 i -= tx_ring->count; 1156 tx_buffer = tx_ring->tx_buffer_info; 1157 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1158 } 1159 1160 /* issue prefetch for next Tx descriptor */ 1161 prefetch(tx_desc); 1162 1163 /* update budget accounting */ 1164 budget--; 1165 } while (likely(budget)); 1166 1167 i += tx_ring->count; 1168 tx_ring->next_to_clean = i; 1169 u64_stats_update_begin(&tx_ring->syncp); 1170 tx_ring->stats.bytes += total_bytes; 1171 tx_ring->stats.packets += total_packets; 1172 u64_stats_update_end(&tx_ring->syncp); 1173 q_vector->tx.total_bytes += total_bytes; 1174 q_vector->tx.total_packets += total_packets; 1175 1176 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1177 /* schedule immediate reset if we believe we hung */ 1178 struct ixgbe_hw *hw = &adapter->hw; 1179 e_err(drv, "Detected Tx Unit Hang\n" 1180 " Tx Queue <%d>\n" 1181 " TDH, TDT <%x>, <%x>\n" 1182 " next_to_use <%x>\n" 1183 " next_to_clean <%x>\n" 1184 "tx_buffer_info[next_to_clean]\n" 1185 " time_stamp <%lx>\n" 1186 " jiffies <%lx>\n", 1187 tx_ring->queue_index, 1188 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1189 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1190 tx_ring->next_to_use, i, 1191 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1192 1193 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 1194 1195 e_info(probe, 1196 "tx hang %d detected on queue %d, resetting adapter\n", 1197 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1198 1199 /* schedule immediate reset if we believe we hung */ 1200 ixgbe_tx_timeout_reset(adapter); 1201 1202 /* the adapter is about to reset, no point in enabling stuff */ 1203 return true; 1204 } 1205 1206 netdev_tx_completed_queue(txring_txq(tx_ring), 1207 total_packets, total_bytes); 1208 1209 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1210 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1211 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1212 /* Make sure that anybody stopping the queue after this 1213 * sees the new next_to_clean. 1214 */ 1215 smp_mb(); 1216 if (__netif_subqueue_stopped(tx_ring->netdev, 1217 tx_ring->queue_index) 1218 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 1219 netif_wake_subqueue(tx_ring->netdev, 1220 tx_ring->queue_index); 1221 ++tx_ring->tx_stats.restart_queue; 1222 } 1223 } 1224 1225 return !!budget; 1226 } 1227 1228 #ifdef CONFIG_IXGBE_DCA 1229 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1230 struct ixgbe_ring *tx_ring, 1231 int cpu) 1232 { 1233 struct ixgbe_hw *hw = &adapter->hw; 1234 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1235 u16 reg_offset; 1236 1237 switch (hw->mac.type) { 1238 case ixgbe_mac_82598EB: 1239 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1240 break; 1241 case ixgbe_mac_82599EB: 1242 case ixgbe_mac_X540: 1243 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1244 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1245 break; 1246 default: 1247 /* for unknown hardware do not write register */ 1248 return; 1249 } 1250 1251 /* 1252 * We can enable relaxed ordering for reads, but not writes when 1253 * DCA is enabled. This is due to a known issue in some chipsets 1254 * which will cause the DCA tag to be cleared. 1255 */ 1256 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1257 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1258 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1259 1260 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1261 } 1262 1263 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1264 struct ixgbe_ring *rx_ring, 1265 int cpu) 1266 { 1267 struct ixgbe_hw *hw = &adapter->hw; 1268 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1269 u8 reg_idx = rx_ring->reg_idx; 1270 1271 1272 switch (hw->mac.type) { 1273 case ixgbe_mac_82599EB: 1274 case ixgbe_mac_X540: 1275 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1276 break; 1277 default: 1278 break; 1279 } 1280 1281 /* 1282 * We can enable relaxed ordering for reads, but not writes when 1283 * DCA is enabled. This is due to a known issue in some chipsets 1284 * which will cause the DCA tag to be cleared. 1285 */ 1286 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1287 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1288 1289 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1290 } 1291 1292 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1293 { 1294 struct ixgbe_adapter *adapter = q_vector->adapter; 1295 struct ixgbe_ring *ring; 1296 int cpu = get_cpu(); 1297 1298 if (q_vector->cpu == cpu) 1299 goto out_no_update; 1300 1301 ixgbe_for_each_ring(ring, q_vector->tx) 1302 ixgbe_update_tx_dca(adapter, ring, cpu); 1303 1304 ixgbe_for_each_ring(ring, q_vector->rx) 1305 ixgbe_update_rx_dca(adapter, ring, cpu); 1306 1307 q_vector->cpu = cpu; 1308 out_no_update: 1309 put_cpu(); 1310 } 1311 1312 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1313 { 1314 int i; 1315 1316 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) 1317 return; 1318 1319 /* always use CB2 mode, difference is masked in the CB driver */ 1320 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); 1321 1322 for (i = 0; i < adapter->num_q_vectors; i++) { 1323 adapter->q_vector[i]->cpu = -1; 1324 ixgbe_update_dca(adapter->q_vector[i]); 1325 } 1326 } 1327 1328 static int __ixgbe_notify_dca(struct device *dev, void *data) 1329 { 1330 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1331 unsigned long event = *(unsigned long *)data; 1332 1333 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1334 return 0; 1335 1336 switch (event) { 1337 case DCA_PROVIDER_ADD: 1338 /* if we're already enabled, don't do it again */ 1339 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1340 break; 1341 if (dca_add_requester(dev) == 0) { 1342 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1343 ixgbe_setup_dca(adapter); 1344 break; 1345 } 1346 /* Fall Through since DCA is disabled. */ 1347 case DCA_PROVIDER_REMOVE: 1348 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1349 dca_remove_requester(dev); 1350 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1351 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); 1352 } 1353 break; 1354 } 1355 1356 return 0; 1357 } 1358 1359 #endif /* CONFIG_IXGBE_DCA */ 1360 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1361 union ixgbe_adv_rx_desc *rx_desc, 1362 struct sk_buff *skb) 1363 { 1364 if (ring->netdev->features & NETIF_F_RXHASH) 1365 skb_set_hash(skb, 1366 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1367 PKT_HASH_TYPE_L3); 1368 } 1369 1370 #ifdef IXGBE_FCOE 1371 /** 1372 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1373 * @ring: structure containing ring specific data 1374 * @rx_desc: advanced rx descriptor 1375 * 1376 * Returns : true if it is FCoE pkt 1377 */ 1378 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1379 union ixgbe_adv_rx_desc *rx_desc) 1380 { 1381 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1382 1383 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1384 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1385 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1386 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1387 } 1388 1389 #endif /* IXGBE_FCOE */ 1390 /** 1391 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1392 * @ring: structure containing ring specific data 1393 * @rx_desc: current Rx descriptor being processed 1394 * @skb: skb currently being received and modified 1395 **/ 1396 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1397 union ixgbe_adv_rx_desc *rx_desc, 1398 struct sk_buff *skb) 1399 { 1400 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1401 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info; 1402 bool encap_pkt = false; 1403 1404 skb_checksum_none_assert(skb); 1405 1406 /* Rx csum disabled */ 1407 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1408 return; 1409 1410 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) && 1411 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) { 1412 encap_pkt = true; 1413 skb->encapsulation = 1; 1414 skb->ip_summed = CHECKSUM_NONE; 1415 } 1416 1417 /* if IP and error */ 1418 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1419 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1420 ring->rx_stats.csum_err++; 1421 return; 1422 } 1423 1424 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1425 return; 1426 1427 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1428 /* 1429 * 82599 errata, UDP frames with a 0 checksum can be marked as 1430 * checksum errors. 1431 */ 1432 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1433 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1434 return; 1435 1436 ring->rx_stats.csum_err++; 1437 return; 1438 } 1439 1440 /* It must be a TCP or UDP packet with a valid checksum */ 1441 skb->ip_summed = CHECKSUM_UNNECESSARY; 1442 if (encap_pkt) { 1443 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1444 return; 1445 1446 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1447 ring->rx_stats.csum_err++; 1448 return; 1449 } 1450 /* If we checked the outer header let the stack know */ 1451 skb->csum_level = 1; 1452 } 1453 } 1454 1455 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1456 struct ixgbe_rx_buffer *bi) 1457 { 1458 struct page *page = bi->page; 1459 dma_addr_t dma; 1460 1461 /* since we are recycling buffers we should seldom need to alloc */ 1462 if (likely(page)) 1463 return true; 1464 1465 /* alloc new page for storage */ 1466 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1467 if (unlikely(!page)) { 1468 rx_ring->rx_stats.alloc_rx_page_failed++; 1469 return false; 1470 } 1471 1472 /* map page for use */ 1473 dma = dma_map_page(rx_ring->dev, page, 0, 1474 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); 1475 1476 /* 1477 * if mapping failed free memory back to system since 1478 * there isn't much point in holding memory we can't use 1479 */ 1480 if (dma_mapping_error(rx_ring->dev, dma)) { 1481 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1482 1483 rx_ring->rx_stats.alloc_rx_page_failed++; 1484 return false; 1485 } 1486 1487 bi->dma = dma; 1488 bi->page = page; 1489 bi->page_offset = 0; 1490 1491 return true; 1492 } 1493 1494 /** 1495 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1496 * @rx_ring: ring to place buffers on 1497 * @cleaned_count: number of buffers to replace 1498 **/ 1499 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1500 { 1501 union ixgbe_adv_rx_desc *rx_desc; 1502 struct ixgbe_rx_buffer *bi; 1503 u16 i = rx_ring->next_to_use; 1504 1505 /* nothing to do */ 1506 if (!cleaned_count) 1507 return; 1508 1509 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1510 bi = &rx_ring->rx_buffer_info[i]; 1511 i -= rx_ring->count; 1512 1513 do { 1514 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1515 break; 1516 1517 /* 1518 * Refresh the desc even if buffer_addrs didn't change 1519 * because each write-back erases this info. 1520 */ 1521 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1522 1523 rx_desc++; 1524 bi++; 1525 i++; 1526 if (unlikely(!i)) { 1527 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1528 bi = rx_ring->rx_buffer_info; 1529 i -= rx_ring->count; 1530 } 1531 1532 /* clear the status bits for the next_to_use descriptor */ 1533 rx_desc->wb.upper.status_error = 0; 1534 1535 cleaned_count--; 1536 } while (cleaned_count); 1537 1538 i += rx_ring->count; 1539 1540 if (rx_ring->next_to_use != i) { 1541 rx_ring->next_to_use = i; 1542 1543 /* update next to alloc since we have filled the ring */ 1544 rx_ring->next_to_alloc = i; 1545 1546 /* Force memory writes to complete before letting h/w 1547 * know there are new descriptors to fetch. (Only 1548 * applicable for weak-ordered memory model archs, 1549 * such as IA-64). 1550 */ 1551 wmb(); 1552 writel(i, rx_ring->tail); 1553 } 1554 } 1555 1556 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1557 struct sk_buff *skb) 1558 { 1559 u16 hdr_len = skb_headlen(skb); 1560 1561 /* set gso_size to avoid messing up TCP MSS */ 1562 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1563 IXGBE_CB(skb)->append_cnt); 1564 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1565 } 1566 1567 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1568 struct sk_buff *skb) 1569 { 1570 /* if append_cnt is 0 then frame is not RSC */ 1571 if (!IXGBE_CB(skb)->append_cnt) 1572 return; 1573 1574 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1575 rx_ring->rx_stats.rsc_flush++; 1576 1577 ixgbe_set_rsc_gso_size(rx_ring, skb); 1578 1579 /* gso_size is computed using append_cnt so always clear it last */ 1580 IXGBE_CB(skb)->append_cnt = 0; 1581 } 1582 1583 /** 1584 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1585 * @rx_ring: rx descriptor ring packet is being transacted on 1586 * @rx_desc: pointer to the EOP Rx descriptor 1587 * @skb: pointer to current skb being populated 1588 * 1589 * This function checks the ring, descriptor, and packet information in 1590 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1591 * other fields within the skb. 1592 **/ 1593 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1594 union ixgbe_adv_rx_desc *rx_desc, 1595 struct sk_buff *skb) 1596 { 1597 struct net_device *dev = rx_ring->netdev; 1598 1599 ixgbe_update_rsc_stats(rx_ring, skb); 1600 1601 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1602 1603 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1604 1605 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))) 1606 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb); 1607 1608 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1609 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1610 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1611 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1612 } 1613 1614 skb_record_rx_queue(skb, rx_ring->queue_index); 1615 1616 skb->protocol = eth_type_trans(skb, dev); 1617 } 1618 1619 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1620 struct sk_buff *skb) 1621 { 1622 struct ixgbe_adapter *adapter = q_vector->adapter; 1623 1624 if (ixgbe_qv_busy_polling(q_vector)) 1625 netif_receive_skb(skb); 1626 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) 1627 napi_gro_receive(&q_vector->napi, skb); 1628 else 1629 netif_rx(skb); 1630 } 1631 1632 /** 1633 * ixgbe_is_non_eop - process handling of non-EOP buffers 1634 * @rx_ring: Rx ring being processed 1635 * @rx_desc: Rx descriptor for current buffer 1636 * @skb: Current socket buffer containing buffer in progress 1637 * 1638 * This function updates next to clean. If the buffer is an EOP buffer 1639 * this function exits returning false, otherwise it will place the 1640 * sk_buff in the next buffer to be chained and return true indicating 1641 * that this is in fact a non-EOP buffer. 1642 **/ 1643 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1644 union ixgbe_adv_rx_desc *rx_desc, 1645 struct sk_buff *skb) 1646 { 1647 u32 ntc = rx_ring->next_to_clean + 1; 1648 1649 /* fetch, update, and store next to clean */ 1650 ntc = (ntc < rx_ring->count) ? ntc : 0; 1651 rx_ring->next_to_clean = ntc; 1652 1653 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1654 1655 /* update RSC append count if present */ 1656 if (ring_is_rsc_enabled(rx_ring)) { 1657 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1658 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1659 1660 if (unlikely(rsc_enabled)) { 1661 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1662 1663 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1664 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1665 1666 /* update ntc based on RSC value */ 1667 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1668 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1669 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1670 } 1671 } 1672 1673 /* if we are the last buffer then there is nothing else to do */ 1674 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1675 return false; 1676 1677 /* place skb in next buffer to be received */ 1678 rx_ring->rx_buffer_info[ntc].skb = skb; 1679 rx_ring->rx_stats.non_eop_descs++; 1680 1681 return true; 1682 } 1683 1684 /** 1685 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1686 * @rx_ring: rx descriptor ring packet is being transacted on 1687 * @skb: pointer to current skb being adjusted 1688 * 1689 * This function is an ixgbe specific version of __pskb_pull_tail. The 1690 * main difference between this version and the original function is that 1691 * this function can make several assumptions about the state of things 1692 * that allow for significant optimizations versus the standard function. 1693 * As a result we can do things like drop a frag and maintain an accurate 1694 * truesize for the skb. 1695 */ 1696 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1697 struct sk_buff *skb) 1698 { 1699 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1700 unsigned char *va; 1701 unsigned int pull_len; 1702 1703 /* 1704 * it is valid to use page_address instead of kmap since we are 1705 * working with pages allocated out of the lomem pool per 1706 * alloc_page(GFP_ATOMIC) 1707 */ 1708 va = skb_frag_address(frag); 1709 1710 /* 1711 * we need the header to contain the greater of either ETH_HLEN or 1712 * 60 bytes if the skb->len is less than 60 for skb_pad. 1713 */ 1714 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE); 1715 1716 /* align pull length to size of long to optimize memcpy performance */ 1717 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1718 1719 /* update all of the pointers */ 1720 skb_frag_size_sub(frag, pull_len); 1721 frag->page_offset += pull_len; 1722 skb->data_len -= pull_len; 1723 skb->tail += pull_len; 1724 } 1725 1726 /** 1727 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1728 * @rx_ring: rx descriptor ring packet is being transacted on 1729 * @skb: pointer to current skb being updated 1730 * 1731 * This function provides a basic DMA sync up for the first fragment of an 1732 * skb. The reason for doing this is that the first fragment cannot be 1733 * unmapped until we have reached the end of packet descriptor for a buffer 1734 * chain. 1735 */ 1736 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1737 struct sk_buff *skb) 1738 { 1739 /* if the page was released unmap it, else just sync our portion */ 1740 if (unlikely(IXGBE_CB(skb)->page_released)) { 1741 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma, 1742 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); 1743 IXGBE_CB(skb)->page_released = false; 1744 } else { 1745 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1746 1747 dma_sync_single_range_for_cpu(rx_ring->dev, 1748 IXGBE_CB(skb)->dma, 1749 frag->page_offset, 1750 ixgbe_rx_bufsz(rx_ring), 1751 DMA_FROM_DEVICE); 1752 } 1753 IXGBE_CB(skb)->dma = 0; 1754 } 1755 1756 /** 1757 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1758 * @rx_ring: rx descriptor ring packet is being transacted on 1759 * @rx_desc: pointer to the EOP Rx descriptor 1760 * @skb: pointer to current skb being fixed 1761 * 1762 * Check for corrupted packet headers caused by senders on the local L2 1763 * embedded NIC switch not setting up their Tx Descriptors right. These 1764 * should be very rare. 1765 * 1766 * Also address the case where we are pulling data in on pages only 1767 * and as such no data is present in the skb header. 1768 * 1769 * In addition if skb is not at least 60 bytes we need to pad it so that 1770 * it is large enough to qualify as a valid Ethernet frame. 1771 * 1772 * Returns true if an error was encountered and skb was freed. 1773 **/ 1774 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1775 union ixgbe_adv_rx_desc *rx_desc, 1776 struct sk_buff *skb) 1777 { 1778 struct net_device *netdev = rx_ring->netdev; 1779 1780 /* verify that the packet does not have any known errors */ 1781 if (unlikely(ixgbe_test_staterr(rx_desc, 1782 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1783 !(netdev->features & NETIF_F_RXALL))) { 1784 dev_kfree_skb_any(skb); 1785 return true; 1786 } 1787 1788 /* place header in linear portion of buffer */ 1789 if (skb_is_nonlinear(skb)) 1790 ixgbe_pull_tail(rx_ring, skb); 1791 1792 #ifdef IXGBE_FCOE 1793 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1794 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1795 return false; 1796 1797 #endif 1798 /* if eth_skb_pad returns an error the skb was freed */ 1799 if (eth_skb_pad(skb)) 1800 return true; 1801 1802 return false; 1803 } 1804 1805 /** 1806 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1807 * @rx_ring: rx descriptor ring to store buffers on 1808 * @old_buff: donor buffer to have page reused 1809 * 1810 * Synchronizes page for reuse by the adapter 1811 **/ 1812 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1813 struct ixgbe_rx_buffer *old_buff) 1814 { 1815 struct ixgbe_rx_buffer *new_buff; 1816 u16 nta = rx_ring->next_to_alloc; 1817 1818 new_buff = &rx_ring->rx_buffer_info[nta]; 1819 1820 /* update, and store next to alloc */ 1821 nta++; 1822 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1823 1824 /* transfer page from old buffer to new buffer */ 1825 *new_buff = *old_buff; 1826 1827 /* sync the buffer for use by the device */ 1828 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma, 1829 new_buff->page_offset, 1830 ixgbe_rx_bufsz(rx_ring), 1831 DMA_FROM_DEVICE); 1832 } 1833 1834 static inline bool ixgbe_page_is_reserved(struct page *page) 1835 { 1836 return (page_to_nid(page) != numa_mem_id()) || page->pfmemalloc; 1837 } 1838 1839 /** 1840 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 1841 * @rx_ring: rx descriptor ring to transact packets on 1842 * @rx_buffer: buffer containing page to add 1843 * @rx_desc: descriptor containing length of buffer written by hardware 1844 * @skb: sk_buff to place the data into 1845 * 1846 * This function will add the data contained in rx_buffer->page to the skb. 1847 * This is done either through a direct copy if the data in the buffer is 1848 * less than the skb header size, otherwise it will just attach the page as 1849 * a frag to the skb. 1850 * 1851 * The function will then update the page offset if necessary and return 1852 * true if the buffer can be reused by the adapter. 1853 **/ 1854 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 1855 struct ixgbe_rx_buffer *rx_buffer, 1856 union ixgbe_adv_rx_desc *rx_desc, 1857 struct sk_buff *skb) 1858 { 1859 struct page *page = rx_buffer->page; 1860 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 1861 #if (PAGE_SIZE < 8192) 1862 unsigned int truesize = ixgbe_rx_bufsz(rx_ring); 1863 #else 1864 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 1865 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) - 1866 ixgbe_rx_bufsz(rx_ring); 1867 #endif 1868 1869 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) { 1870 unsigned char *va = page_address(page) + rx_buffer->page_offset; 1871 1872 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 1873 1874 /* page is not reserved, we can reuse buffer as-is */ 1875 if (likely(!ixgbe_page_is_reserved(page))) 1876 return true; 1877 1878 /* this page cannot be reused so discard it */ 1879 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1880 return false; 1881 } 1882 1883 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 1884 rx_buffer->page_offset, size, truesize); 1885 1886 /* avoid re-using remote pages */ 1887 if (unlikely(ixgbe_page_is_reserved(page))) 1888 return false; 1889 1890 #if (PAGE_SIZE < 8192) 1891 /* if we are only owner of page we can reuse it */ 1892 if (unlikely(page_count(page) != 1)) 1893 return false; 1894 1895 /* flip page offset to other buffer */ 1896 rx_buffer->page_offset ^= truesize; 1897 #else 1898 /* move offset up to the next cache line */ 1899 rx_buffer->page_offset += truesize; 1900 1901 if (rx_buffer->page_offset > last_offset) 1902 return false; 1903 #endif 1904 1905 /* Even if we own the page, we are not allowed to use atomic_set() 1906 * This would break get_page_unless_zero() users. 1907 */ 1908 atomic_inc(&page->_count); 1909 1910 return true; 1911 } 1912 1913 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring, 1914 union ixgbe_adv_rx_desc *rx_desc) 1915 { 1916 struct ixgbe_rx_buffer *rx_buffer; 1917 struct sk_buff *skb; 1918 struct page *page; 1919 1920 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 1921 page = rx_buffer->page; 1922 prefetchw(page); 1923 1924 skb = rx_buffer->skb; 1925 1926 if (likely(!skb)) { 1927 void *page_addr = page_address(page) + 1928 rx_buffer->page_offset; 1929 1930 /* prefetch first cache line of first page */ 1931 prefetch(page_addr); 1932 #if L1_CACHE_BYTES < 128 1933 prefetch(page_addr + L1_CACHE_BYTES); 1934 #endif 1935 1936 /* allocate a skb to store the frags */ 1937 skb = napi_alloc_skb(&rx_ring->q_vector->napi, 1938 IXGBE_RX_HDR_SIZE); 1939 if (unlikely(!skb)) { 1940 rx_ring->rx_stats.alloc_rx_buff_failed++; 1941 return NULL; 1942 } 1943 1944 /* 1945 * we will be copying header into skb->data in 1946 * pskb_may_pull so it is in our interest to prefetch 1947 * it now to avoid a possible cache miss 1948 */ 1949 prefetchw(skb->data); 1950 1951 /* 1952 * Delay unmapping of the first packet. It carries the 1953 * header information, HW may still access the header 1954 * after the writeback. Only unmap it when EOP is 1955 * reached 1956 */ 1957 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1958 goto dma_sync; 1959 1960 IXGBE_CB(skb)->dma = rx_buffer->dma; 1961 } else { 1962 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 1963 ixgbe_dma_sync_frag(rx_ring, skb); 1964 1965 dma_sync: 1966 /* we are reusing so sync this buffer for CPU use */ 1967 dma_sync_single_range_for_cpu(rx_ring->dev, 1968 rx_buffer->dma, 1969 rx_buffer->page_offset, 1970 ixgbe_rx_bufsz(rx_ring), 1971 DMA_FROM_DEVICE); 1972 1973 rx_buffer->skb = NULL; 1974 } 1975 1976 /* pull page into skb */ 1977 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 1978 /* hand second half of page back to the ring */ 1979 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 1980 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) { 1981 /* the page has been released from the ring */ 1982 IXGBE_CB(skb)->page_released = true; 1983 } else { 1984 /* we are not reusing the buffer so unmap it */ 1985 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 1986 ixgbe_rx_pg_size(rx_ring), 1987 DMA_FROM_DEVICE); 1988 } 1989 1990 /* clear contents of buffer_info */ 1991 rx_buffer->page = NULL; 1992 1993 return skb; 1994 } 1995 1996 /** 1997 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 1998 * @q_vector: structure containing interrupt and ring information 1999 * @rx_ring: rx descriptor ring to transact packets on 2000 * @budget: Total limit on number of packets to process 2001 * 2002 * This function provides a "bounce buffer" approach to Rx interrupt 2003 * processing. The advantage to this is that on systems that have 2004 * expensive overhead for IOMMU access this provides a means of avoiding 2005 * it by maintaining the mapping of the page to the syste. 2006 * 2007 * Returns amount of work completed 2008 **/ 2009 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2010 struct ixgbe_ring *rx_ring, 2011 const int budget) 2012 { 2013 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 2014 #ifdef IXGBE_FCOE 2015 struct ixgbe_adapter *adapter = q_vector->adapter; 2016 int ddp_bytes; 2017 unsigned int mss = 0; 2018 #endif /* IXGBE_FCOE */ 2019 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2020 2021 while (likely(total_rx_packets < budget)) { 2022 union ixgbe_adv_rx_desc *rx_desc; 2023 struct sk_buff *skb; 2024 2025 /* return some buffers to hardware, one at a time is too slow */ 2026 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2027 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2028 cleaned_count = 0; 2029 } 2030 2031 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2032 2033 if (!rx_desc->wb.upper.status_error) 2034 break; 2035 2036 /* This memory barrier is needed to keep us from reading 2037 * any other fields out of the rx_desc until we know the 2038 * descriptor has been written back 2039 */ 2040 dma_rmb(); 2041 2042 /* retrieve a buffer from the ring */ 2043 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc); 2044 2045 /* exit if we failed to retrieve a buffer */ 2046 if (!skb) 2047 break; 2048 2049 cleaned_count++; 2050 2051 /* place incomplete frames back on ring for completion */ 2052 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2053 continue; 2054 2055 /* verify the packet layout is correct */ 2056 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2057 continue; 2058 2059 /* probably a little skewed due to removing CRC */ 2060 total_rx_bytes += skb->len; 2061 2062 /* populate checksum, timestamp, VLAN, and protocol */ 2063 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2064 2065 #ifdef IXGBE_FCOE 2066 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2067 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2068 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2069 /* include DDPed FCoE data */ 2070 if (ddp_bytes > 0) { 2071 if (!mss) { 2072 mss = rx_ring->netdev->mtu - 2073 sizeof(struct fcoe_hdr) - 2074 sizeof(struct fc_frame_header) - 2075 sizeof(struct fcoe_crc_eof); 2076 if (mss > 512) 2077 mss &= ~511; 2078 } 2079 total_rx_bytes += ddp_bytes; 2080 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2081 mss); 2082 } 2083 if (!ddp_bytes) { 2084 dev_kfree_skb_any(skb); 2085 continue; 2086 } 2087 } 2088 2089 #endif /* IXGBE_FCOE */ 2090 skb_mark_napi_id(skb, &q_vector->napi); 2091 ixgbe_rx_skb(q_vector, skb); 2092 2093 /* update budget accounting */ 2094 total_rx_packets++; 2095 } 2096 2097 u64_stats_update_begin(&rx_ring->syncp); 2098 rx_ring->stats.packets += total_rx_packets; 2099 rx_ring->stats.bytes += total_rx_bytes; 2100 u64_stats_update_end(&rx_ring->syncp); 2101 q_vector->rx.total_packets += total_rx_packets; 2102 q_vector->rx.total_bytes += total_rx_bytes; 2103 2104 return total_rx_packets; 2105 } 2106 2107 #ifdef CONFIG_NET_RX_BUSY_POLL 2108 /* must be called with local_bh_disable()d */ 2109 static int ixgbe_low_latency_recv(struct napi_struct *napi) 2110 { 2111 struct ixgbe_q_vector *q_vector = 2112 container_of(napi, struct ixgbe_q_vector, napi); 2113 struct ixgbe_adapter *adapter = q_vector->adapter; 2114 struct ixgbe_ring *ring; 2115 int found = 0; 2116 2117 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2118 return LL_FLUSH_FAILED; 2119 2120 if (!ixgbe_qv_lock_poll(q_vector)) 2121 return LL_FLUSH_BUSY; 2122 2123 ixgbe_for_each_ring(ring, q_vector->rx) { 2124 found = ixgbe_clean_rx_irq(q_vector, ring, 4); 2125 #ifdef BP_EXTENDED_STATS 2126 if (found) 2127 ring->stats.cleaned += found; 2128 else 2129 ring->stats.misses++; 2130 #endif 2131 if (found) 2132 break; 2133 } 2134 2135 ixgbe_qv_unlock_poll(q_vector); 2136 2137 return found; 2138 } 2139 #endif /* CONFIG_NET_RX_BUSY_POLL */ 2140 2141 /** 2142 * ixgbe_configure_msix - Configure MSI-X hardware 2143 * @adapter: board private structure 2144 * 2145 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2146 * interrupts. 2147 **/ 2148 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2149 { 2150 struct ixgbe_q_vector *q_vector; 2151 int v_idx; 2152 u32 mask; 2153 2154 /* Populate MSIX to EITR Select */ 2155 if (adapter->num_vfs > 32) { 2156 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; 2157 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2158 } 2159 2160 /* 2161 * Populate the IVAR table and set the ITR values to the 2162 * corresponding register. 2163 */ 2164 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2165 struct ixgbe_ring *ring; 2166 q_vector = adapter->q_vector[v_idx]; 2167 2168 ixgbe_for_each_ring(ring, q_vector->rx) 2169 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2170 2171 ixgbe_for_each_ring(ring, q_vector->tx) 2172 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2173 2174 ixgbe_write_eitr(q_vector); 2175 } 2176 2177 switch (adapter->hw.mac.type) { 2178 case ixgbe_mac_82598EB: 2179 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2180 v_idx); 2181 break; 2182 case ixgbe_mac_82599EB: 2183 case ixgbe_mac_X540: 2184 case ixgbe_mac_X550: 2185 case ixgbe_mac_X550EM_x: 2186 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2187 break; 2188 default: 2189 break; 2190 } 2191 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2192 2193 /* set up to autoclear timer, and the vectors */ 2194 mask = IXGBE_EIMS_ENABLE_MASK; 2195 mask &= ~(IXGBE_EIMS_OTHER | 2196 IXGBE_EIMS_MAILBOX | 2197 IXGBE_EIMS_LSC); 2198 2199 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2200 } 2201 2202 enum latency_range { 2203 lowest_latency = 0, 2204 low_latency = 1, 2205 bulk_latency = 2, 2206 latency_invalid = 255 2207 }; 2208 2209 /** 2210 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2211 * @q_vector: structure containing interrupt and ring information 2212 * @ring_container: structure containing ring performance data 2213 * 2214 * Stores a new ITR value based on packets and byte 2215 * counts during the last interrupt. The advantage of per interrupt 2216 * computation is faster updates and more accurate ITR for the current 2217 * traffic pattern. Constants in this function were computed 2218 * based on theoretical maximum wire speed and thresholds were set based 2219 * on testing data as well as attempting to minimize response time 2220 * while increasing bulk throughput. 2221 * this functionality is controlled by the InterruptThrottleRate module 2222 * parameter (see ixgbe_param.c) 2223 **/ 2224 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2225 struct ixgbe_ring_container *ring_container) 2226 { 2227 int bytes = ring_container->total_bytes; 2228 int packets = ring_container->total_packets; 2229 u32 timepassed_us; 2230 u64 bytes_perint; 2231 u8 itr_setting = ring_container->itr; 2232 2233 if (packets == 0) 2234 return; 2235 2236 /* simple throttlerate management 2237 * 0-10MB/s lowest (100000 ints/s) 2238 * 10-20MB/s low (20000 ints/s) 2239 * 20-1249MB/s bulk (8000 ints/s) 2240 */ 2241 /* what was last interrupt timeslice? */ 2242 timepassed_us = q_vector->itr >> 2; 2243 if (timepassed_us == 0) 2244 return; 2245 2246 bytes_perint = bytes / timepassed_us; /* bytes/usec */ 2247 2248 switch (itr_setting) { 2249 case lowest_latency: 2250 if (bytes_perint > 10) 2251 itr_setting = low_latency; 2252 break; 2253 case low_latency: 2254 if (bytes_perint > 20) 2255 itr_setting = bulk_latency; 2256 else if (bytes_perint <= 10) 2257 itr_setting = lowest_latency; 2258 break; 2259 case bulk_latency: 2260 if (bytes_perint <= 20) 2261 itr_setting = low_latency; 2262 break; 2263 } 2264 2265 /* clear work counters since we have the values we need */ 2266 ring_container->total_bytes = 0; 2267 ring_container->total_packets = 0; 2268 2269 /* write updated itr to ring container */ 2270 ring_container->itr = itr_setting; 2271 } 2272 2273 /** 2274 * ixgbe_write_eitr - write EITR register in hardware specific way 2275 * @q_vector: structure containing interrupt and ring information 2276 * 2277 * This function is made to be called by ethtool and by the driver 2278 * when it needs to update EITR registers at runtime. Hardware 2279 * specific quirks/differences are taken care of here. 2280 */ 2281 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2282 { 2283 struct ixgbe_adapter *adapter = q_vector->adapter; 2284 struct ixgbe_hw *hw = &adapter->hw; 2285 int v_idx = q_vector->v_idx; 2286 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2287 2288 switch (adapter->hw.mac.type) { 2289 case ixgbe_mac_82598EB: 2290 /* must write high and low 16 bits to reset counter */ 2291 itr_reg |= (itr_reg << 16); 2292 break; 2293 case ixgbe_mac_82599EB: 2294 case ixgbe_mac_X540: 2295 case ixgbe_mac_X550: 2296 case ixgbe_mac_X550EM_x: 2297 /* 2298 * set the WDIS bit to not clear the timer bits and cause an 2299 * immediate assertion of the interrupt 2300 */ 2301 itr_reg |= IXGBE_EITR_CNT_WDIS; 2302 break; 2303 default: 2304 break; 2305 } 2306 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2307 } 2308 2309 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2310 { 2311 u32 new_itr = q_vector->itr; 2312 u8 current_itr; 2313 2314 ixgbe_update_itr(q_vector, &q_vector->tx); 2315 ixgbe_update_itr(q_vector, &q_vector->rx); 2316 2317 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 2318 2319 switch (current_itr) { 2320 /* counts and packets in update_itr are dependent on these numbers */ 2321 case lowest_latency: 2322 new_itr = IXGBE_100K_ITR; 2323 break; 2324 case low_latency: 2325 new_itr = IXGBE_20K_ITR; 2326 break; 2327 case bulk_latency: 2328 new_itr = IXGBE_8K_ITR; 2329 break; 2330 default: 2331 break; 2332 } 2333 2334 if (new_itr != q_vector->itr) { 2335 /* do an exponential smoothing */ 2336 new_itr = (10 * new_itr * q_vector->itr) / 2337 ((9 * new_itr) + q_vector->itr); 2338 2339 /* save the algorithm value here */ 2340 q_vector->itr = new_itr; 2341 2342 ixgbe_write_eitr(q_vector); 2343 } 2344 } 2345 2346 /** 2347 * ixgbe_check_overtemp_subtask - check for over temperature 2348 * @adapter: pointer to adapter 2349 **/ 2350 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2351 { 2352 struct ixgbe_hw *hw = &adapter->hw; 2353 u32 eicr = adapter->interrupt_event; 2354 2355 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2356 return; 2357 2358 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && 2359 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2360 return; 2361 2362 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2363 2364 switch (hw->device_id) { 2365 case IXGBE_DEV_ID_82599_T3_LOM: 2366 /* 2367 * Since the warning interrupt is for both ports 2368 * we don't have to check if: 2369 * - This interrupt wasn't for our port. 2370 * - We may have missed the interrupt so always have to 2371 * check if we got a LSC 2372 */ 2373 if (!(eicr & IXGBE_EICR_GPI_SDP0) && 2374 !(eicr & IXGBE_EICR_LSC)) 2375 return; 2376 2377 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2378 u32 speed; 2379 bool link_up = false; 2380 2381 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2382 2383 if (link_up) 2384 return; 2385 } 2386 2387 /* Check if this is not due to overtemp */ 2388 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) 2389 return; 2390 2391 break; 2392 default: 2393 if (!(eicr & IXGBE_EICR_GPI_SDP0)) 2394 return; 2395 break; 2396 } 2397 e_crit(drv, 2398 "Network adapter has been stopped because it has over heated. " 2399 "Restart the computer. If the problem persists, " 2400 "power off the system and replace the adapter\n"); 2401 2402 adapter->interrupt_event = 0; 2403 } 2404 2405 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2406 { 2407 struct ixgbe_hw *hw = &adapter->hw; 2408 2409 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2410 (eicr & IXGBE_EICR_GPI_SDP1)) { 2411 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2412 /* write to clear the interrupt */ 2413 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); 2414 } 2415 } 2416 2417 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2418 { 2419 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2420 return; 2421 2422 switch (adapter->hw.mac.type) { 2423 case ixgbe_mac_82599EB: 2424 /* 2425 * Need to check link state so complete overtemp check 2426 * on service task 2427 */ 2428 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) && 2429 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2430 adapter->interrupt_event = eicr; 2431 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2432 ixgbe_service_event_schedule(adapter); 2433 return; 2434 } 2435 return; 2436 case ixgbe_mac_X540: 2437 if (!(eicr & IXGBE_EICR_TS)) 2438 return; 2439 break; 2440 default: 2441 return; 2442 } 2443 2444 e_crit(drv, 2445 "Network adapter has been stopped because it has over heated. " 2446 "Restart the computer. If the problem persists, " 2447 "power off the system and replace the adapter\n"); 2448 } 2449 2450 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2451 { 2452 struct ixgbe_hw *hw = &adapter->hw; 2453 2454 if (eicr & IXGBE_EICR_GPI_SDP2) { 2455 /* Clear the interrupt */ 2456 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); 2457 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2458 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2459 ixgbe_service_event_schedule(adapter); 2460 } 2461 } 2462 2463 if (eicr & IXGBE_EICR_GPI_SDP1) { 2464 /* Clear the interrupt */ 2465 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); 2466 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2467 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2468 ixgbe_service_event_schedule(adapter); 2469 } 2470 } 2471 } 2472 2473 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2474 { 2475 struct ixgbe_hw *hw = &adapter->hw; 2476 2477 adapter->lsc_int++; 2478 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2479 adapter->link_check_timeout = jiffies; 2480 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2481 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2482 IXGBE_WRITE_FLUSH(hw); 2483 ixgbe_service_event_schedule(adapter); 2484 } 2485 } 2486 2487 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2488 u64 qmask) 2489 { 2490 u32 mask; 2491 struct ixgbe_hw *hw = &adapter->hw; 2492 2493 switch (hw->mac.type) { 2494 case ixgbe_mac_82598EB: 2495 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2496 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2497 break; 2498 case ixgbe_mac_82599EB: 2499 case ixgbe_mac_X540: 2500 case ixgbe_mac_X550: 2501 case ixgbe_mac_X550EM_x: 2502 mask = (qmask & 0xFFFFFFFF); 2503 if (mask) 2504 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2505 mask = (qmask >> 32); 2506 if (mask) 2507 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2508 break; 2509 default: 2510 break; 2511 } 2512 /* skip the flush */ 2513 } 2514 2515 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, 2516 u64 qmask) 2517 { 2518 u32 mask; 2519 struct ixgbe_hw *hw = &adapter->hw; 2520 2521 switch (hw->mac.type) { 2522 case ixgbe_mac_82598EB: 2523 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2524 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 2525 break; 2526 case ixgbe_mac_82599EB: 2527 case ixgbe_mac_X540: 2528 case ixgbe_mac_X550: 2529 case ixgbe_mac_X550EM_x: 2530 mask = (qmask & 0xFFFFFFFF); 2531 if (mask) 2532 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 2533 mask = (qmask >> 32); 2534 if (mask) 2535 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 2536 break; 2537 default: 2538 break; 2539 } 2540 /* skip the flush */ 2541 } 2542 2543 /** 2544 * ixgbe_irq_enable - Enable default interrupt generation settings 2545 * @adapter: board private structure 2546 **/ 2547 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 2548 bool flush) 2549 { 2550 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 2551 2552 /* don't reenable LSC while waiting for link */ 2553 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 2554 mask &= ~IXGBE_EIMS_LSC; 2555 2556 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 2557 switch (adapter->hw.mac.type) { 2558 case ixgbe_mac_82599EB: 2559 mask |= IXGBE_EIMS_GPI_SDP0; 2560 break; 2561 case ixgbe_mac_X540: 2562 case ixgbe_mac_X550: 2563 case ixgbe_mac_X550EM_x: 2564 mask |= IXGBE_EIMS_TS; 2565 break; 2566 default: 2567 break; 2568 } 2569 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 2570 mask |= IXGBE_EIMS_GPI_SDP1; 2571 switch (adapter->hw.mac.type) { 2572 case ixgbe_mac_82599EB: 2573 mask |= IXGBE_EIMS_GPI_SDP1; 2574 mask |= IXGBE_EIMS_GPI_SDP2; 2575 /* fall through */ 2576 case ixgbe_mac_X540: 2577 case ixgbe_mac_X550: 2578 case ixgbe_mac_X550EM_x: 2579 mask |= IXGBE_EIMS_ECC; 2580 mask |= IXGBE_EIMS_MAILBOX; 2581 break; 2582 default: 2583 break; 2584 } 2585 2586 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 2587 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 2588 mask |= IXGBE_EIMS_FLOW_DIR; 2589 2590 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 2591 if (queues) 2592 ixgbe_irq_enable_queues(adapter, ~0); 2593 if (flush) 2594 IXGBE_WRITE_FLUSH(&adapter->hw); 2595 } 2596 2597 static irqreturn_t ixgbe_msix_other(int irq, void *data) 2598 { 2599 struct ixgbe_adapter *adapter = data; 2600 struct ixgbe_hw *hw = &adapter->hw; 2601 u32 eicr; 2602 2603 /* 2604 * Workaround for Silicon errata. Use clear-by-write instead 2605 * of clear-by-read. Reading with EICS will return the 2606 * interrupt causes without clearing, which later be done 2607 * with the write to EICR. 2608 */ 2609 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 2610 2611 /* The lower 16bits of the EICR register are for the queue interrupts 2612 * which should be masked here in order to not accidently clear them if 2613 * the bits are high when ixgbe_msix_other is called. There is a race 2614 * condition otherwise which results in possible performance loss 2615 * especially if the ixgbe_msix_other interrupt is triggering 2616 * consistently (as it would when PPS is turned on for the X540 device) 2617 */ 2618 eicr &= 0xFFFF0000; 2619 2620 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 2621 2622 if (eicr & IXGBE_EICR_LSC) 2623 ixgbe_check_lsc(adapter); 2624 2625 if (eicr & IXGBE_EICR_MAILBOX) 2626 ixgbe_msg_task(adapter); 2627 2628 switch (hw->mac.type) { 2629 case ixgbe_mac_82599EB: 2630 case ixgbe_mac_X540: 2631 case ixgbe_mac_X550: 2632 case ixgbe_mac_X550EM_x: 2633 if (eicr & IXGBE_EICR_ECC) { 2634 e_info(link, "Received ECC Err, initiating reset\n"); 2635 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 2636 ixgbe_service_event_schedule(adapter); 2637 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 2638 } 2639 /* Handle Flow Director Full threshold interrupt */ 2640 if (eicr & IXGBE_EICR_FLOW_DIR) { 2641 int reinit_count = 0; 2642 int i; 2643 for (i = 0; i < adapter->num_tx_queues; i++) { 2644 struct ixgbe_ring *ring = adapter->tx_ring[i]; 2645 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 2646 &ring->state)) 2647 reinit_count++; 2648 } 2649 if (reinit_count) { 2650 /* no more flow director interrupts until after init */ 2651 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 2652 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 2653 ixgbe_service_event_schedule(adapter); 2654 } 2655 } 2656 ixgbe_check_sfp_event(adapter, eicr); 2657 ixgbe_check_overtemp_event(adapter, eicr); 2658 break; 2659 default: 2660 break; 2661 } 2662 2663 ixgbe_check_fan_failure(adapter, eicr); 2664 2665 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 2666 ixgbe_ptp_check_pps_event(adapter, eicr); 2667 2668 /* re-enable the original interrupt state, no lsc, no queues */ 2669 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2670 ixgbe_irq_enable(adapter, false, false); 2671 2672 return IRQ_HANDLED; 2673 } 2674 2675 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 2676 { 2677 struct ixgbe_q_vector *q_vector = data; 2678 2679 /* EIAM disabled interrupts (on this vector) for us */ 2680 2681 if (q_vector->rx.ring || q_vector->tx.ring) 2682 napi_schedule(&q_vector->napi); 2683 2684 return IRQ_HANDLED; 2685 } 2686 2687 /** 2688 * ixgbe_poll - NAPI Rx polling callback 2689 * @napi: structure for representing this polling device 2690 * @budget: how many packets driver is allowed to clean 2691 * 2692 * This function is used for legacy and MSI, NAPI mode 2693 **/ 2694 int ixgbe_poll(struct napi_struct *napi, int budget) 2695 { 2696 struct ixgbe_q_vector *q_vector = 2697 container_of(napi, struct ixgbe_q_vector, napi); 2698 struct ixgbe_adapter *adapter = q_vector->adapter; 2699 struct ixgbe_ring *ring; 2700 int per_ring_budget; 2701 bool clean_complete = true; 2702 2703 #ifdef CONFIG_IXGBE_DCA 2704 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 2705 ixgbe_update_dca(q_vector); 2706 #endif 2707 2708 ixgbe_for_each_ring(ring, q_vector->tx) 2709 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring); 2710 2711 if (!ixgbe_qv_lock_napi(q_vector)) 2712 return budget; 2713 2714 /* attempt to distribute budget to each queue fairly, but don't allow 2715 * the budget to go below 1 because we'll exit polling */ 2716 if (q_vector->rx.count > 1) 2717 per_ring_budget = max(budget/q_vector->rx.count, 1); 2718 else 2719 per_ring_budget = budget; 2720 2721 ixgbe_for_each_ring(ring, q_vector->rx) 2722 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring, 2723 per_ring_budget) < per_ring_budget); 2724 2725 ixgbe_qv_unlock_napi(q_vector); 2726 /* If all work not completed, return budget and keep polling */ 2727 if (!clean_complete) 2728 return budget; 2729 2730 /* all work done, exit the polling mode */ 2731 napi_complete(napi); 2732 if (adapter->rx_itr_setting & 1) 2733 ixgbe_set_itr(q_vector); 2734 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2735 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); 2736 2737 return 0; 2738 } 2739 2740 /** 2741 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 2742 * @adapter: board private structure 2743 * 2744 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 2745 * interrupts from the kernel. 2746 **/ 2747 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 2748 { 2749 struct net_device *netdev = adapter->netdev; 2750 int vector, err; 2751 int ri = 0, ti = 0; 2752 2753 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 2754 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 2755 struct msix_entry *entry = &adapter->msix_entries[vector]; 2756 2757 if (q_vector->tx.ring && q_vector->rx.ring) { 2758 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2759 "%s-%s-%d", netdev->name, "TxRx", ri++); 2760 ti++; 2761 } else if (q_vector->rx.ring) { 2762 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2763 "%s-%s-%d", netdev->name, "rx", ri++); 2764 } else if (q_vector->tx.ring) { 2765 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2766 "%s-%s-%d", netdev->name, "tx", ti++); 2767 } else { 2768 /* skip this unused q_vector */ 2769 continue; 2770 } 2771 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 2772 q_vector->name, q_vector); 2773 if (err) { 2774 e_err(probe, "request_irq failed for MSIX interrupt " 2775 "Error: %d\n", err); 2776 goto free_queue_irqs; 2777 } 2778 /* If Flow Director is enabled, set interrupt affinity */ 2779 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 2780 /* assign the mask for this irq */ 2781 irq_set_affinity_hint(entry->vector, 2782 &q_vector->affinity_mask); 2783 } 2784 } 2785 2786 err = request_irq(adapter->msix_entries[vector].vector, 2787 ixgbe_msix_other, 0, netdev->name, adapter); 2788 if (err) { 2789 e_err(probe, "request_irq for msix_other failed: %d\n", err); 2790 goto free_queue_irqs; 2791 } 2792 2793 return 0; 2794 2795 free_queue_irqs: 2796 while (vector) { 2797 vector--; 2798 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 2799 NULL); 2800 free_irq(adapter->msix_entries[vector].vector, 2801 adapter->q_vector[vector]); 2802 } 2803 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 2804 pci_disable_msix(adapter->pdev); 2805 kfree(adapter->msix_entries); 2806 adapter->msix_entries = NULL; 2807 return err; 2808 } 2809 2810 /** 2811 * ixgbe_intr - legacy mode Interrupt Handler 2812 * @irq: interrupt number 2813 * @data: pointer to a network interface device structure 2814 **/ 2815 static irqreturn_t ixgbe_intr(int irq, void *data) 2816 { 2817 struct ixgbe_adapter *adapter = data; 2818 struct ixgbe_hw *hw = &adapter->hw; 2819 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 2820 u32 eicr; 2821 2822 /* 2823 * Workaround for silicon errata #26 on 82598. Mask the interrupt 2824 * before the read of EICR. 2825 */ 2826 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 2827 2828 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 2829 * therefore no explicit interrupt disable is necessary */ 2830 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 2831 if (!eicr) { 2832 /* 2833 * shared interrupt alert! 2834 * make sure interrupts are enabled because the read will 2835 * have disabled interrupts due to EIAM 2836 * finish the workaround of silicon errata on 82598. Unmask 2837 * the interrupt that we masked before the EICR read. 2838 */ 2839 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2840 ixgbe_irq_enable(adapter, true, true); 2841 return IRQ_NONE; /* Not our interrupt */ 2842 } 2843 2844 if (eicr & IXGBE_EICR_LSC) 2845 ixgbe_check_lsc(adapter); 2846 2847 switch (hw->mac.type) { 2848 case ixgbe_mac_82599EB: 2849 ixgbe_check_sfp_event(adapter, eicr); 2850 /* Fall through */ 2851 case ixgbe_mac_X540: 2852 case ixgbe_mac_X550: 2853 case ixgbe_mac_X550EM_x: 2854 if (eicr & IXGBE_EICR_ECC) { 2855 e_info(link, "Received ECC Err, initiating reset\n"); 2856 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 2857 ixgbe_service_event_schedule(adapter); 2858 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 2859 } 2860 ixgbe_check_overtemp_event(adapter, eicr); 2861 break; 2862 default: 2863 break; 2864 } 2865 2866 ixgbe_check_fan_failure(adapter, eicr); 2867 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 2868 ixgbe_ptp_check_pps_event(adapter, eicr); 2869 2870 /* would disable interrupts here but EIAM disabled it */ 2871 napi_schedule(&q_vector->napi); 2872 2873 /* 2874 * re-enable link(maybe) and non-queue interrupts, no flush. 2875 * ixgbe_poll will re-enable the queue interrupts 2876 */ 2877 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2878 ixgbe_irq_enable(adapter, false, false); 2879 2880 return IRQ_HANDLED; 2881 } 2882 2883 /** 2884 * ixgbe_request_irq - initialize interrupts 2885 * @adapter: board private structure 2886 * 2887 * Attempts to configure interrupts using the best available 2888 * capabilities of the hardware and kernel. 2889 **/ 2890 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 2891 { 2892 struct net_device *netdev = adapter->netdev; 2893 int err; 2894 2895 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 2896 err = ixgbe_request_msix_irqs(adapter); 2897 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 2898 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 2899 netdev->name, adapter); 2900 else 2901 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 2902 netdev->name, adapter); 2903 2904 if (err) 2905 e_err(probe, "request_irq failed, Error %d\n", err); 2906 2907 return err; 2908 } 2909 2910 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 2911 { 2912 int vector; 2913 2914 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 2915 free_irq(adapter->pdev->irq, adapter); 2916 return; 2917 } 2918 2919 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 2920 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 2921 struct msix_entry *entry = &adapter->msix_entries[vector]; 2922 2923 /* free only the irqs that were actually requested */ 2924 if (!q_vector->rx.ring && !q_vector->tx.ring) 2925 continue; 2926 2927 /* clear the affinity_mask in the IRQ descriptor */ 2928 irq_set_affinity_hint(entry->vector, NULL); 2929 2930 free_irq(entry->vector, q_vector); 2931 } 2932 2933 free_irq(adapter->msix_entries[vector++].vector, adapter); 2934 } 2935 2936 /** 2937 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 2938 * @adapter: board private structure 2939 **/ 2940 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 2941 { 2942 switch (adapter->hw.mac.type) { 2943 case ixgbe_mac_82598EB: 2944 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 2945 break; 2946 case ixgbe_mac_82599EB: 2947 case ixgbe_mac_X540: 2948 case ixgbe_mac_X550: 2949 case ixgbe_mac_X550EM_x: 2950 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 2951 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 2952 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 2953 break; 2954 default: 2955 break; 2956 } 2957 IXGBE_WRITE_FLUSH(&adapter->hw); 2958 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 2959 int vector; 2960 2961 for (vector = 0; vector < adapter->num_q_vectors; vector++) 2962 synchronize_irq(adapter->msix_entries[vector].vector); 2963 2964 synchronize_irq(adapter->msix_entries[vector++].vector); 2965 } else { 2966 synchronize_irq(adapter->pdev->irq); 2967 } 2968 } 2969 2970 /** 2971 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 2972 * 2973 **/ 2974 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 2975 { 2976 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 2977 2978 ixgbe_write_eitr(q_vector); 2979 2980 ixgbe_set_ivar(adapter, 0, 0, 0); 2981 ixgbe_set_ivar(adapter, 1, 0, 0); 2982 2983 e_info(hw, "Legacy interrupt IVAR setup done\n"); 2984 } 2985 2986 /** 2987 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 2988 * @adapter: board private structure 2989 * @ring: structure containing ring specific data 2990 * 2991 * Configure the Tx descriptor ring after a reset. 2992 **/ 2993 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 2994 struct ixgbe_ring *ring) 2995 { 2996 struct ixgbe_hw *hw = &adapter->hw; 2997 u64 tdba = ring->dma; 2998 int wait_loop = 10; 2999 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3000 u8 reg_idx = ring->reg_idx; 3001 3002 /* disable queue to avoid issues while updating state */ 3003 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3004 IXGBE_WRITE_FLUSH(hw); 3005 3006 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3007 (tdba & DMA_BIT_MASK(32))); 3008 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3009 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3010 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3011 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3012 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3013 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3014 3015 /* 3016 * set WTHRESH to encourage burst writeback, it should not be set 3017 * higher than 1 when: 3018 * - ITR is 0 as it could cause false TX hangs 3019 * - ITR is set to > 100k int/sec and BQL is enabled 3020 * 3021 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3022 * to or less than the number of on chip descriptors, which is 3023 * currently 40. 3024 */ 3025 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3026 txdctl |= (1 << 16); /* WTHRESH = 1 */ 3027 else 3028 txdctl |= (8 << 16); /* WTHRESH = 8 */ 3029 3030 /* 3031 * Setting PTHRESH to 32 both improves performance 3032 * and avoids a TX hang with DFP enabled 3033 */ 3034 txdctl |= (1 << 8) | /* HTHRESH = 1 */ 3035 32; /* PTHRESH = 32 */ 3036 3037 /* reinitialize flowdirector state */ 3038 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3039 ring->atr_sample_rate = adapter->atr_sample_rate; 3040 ring->atr_count = 0; 3041 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3042 } else { 3043 ring->atr_sample_rate = 0; 3044 } 3045 3046 /* initialize XPS */ 3047 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3048 struct ixgbe_q_vector *q_vector = ring->q_vector; 3049 3050 if (q_vector) 3051 netif_set_xps_queue(ring->netdev, 3052 &q_vector->affinity_mask, 3053 ring->queue_index); 3054 } 3055 3056 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3057 3058 /* enable queue */ 3059 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3060 3061 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3062 if (hw->mac.type == ixgbe_mac_82598EB && 3063 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3064 return; 3065 3066 /* poll to verify queue is enabled */ 3067 do { 3068 usleep_range(1000, 2000); 3069 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3070 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3071 if (!wait_loop) 3072 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx); 3073 } 3074 3075 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3076 { 3077 struct ixgbe_hw *hw = &adapter->hw; 3078 u32 rttdcs, mtqc; 3079 u8 tcs = netdev_get_num_tc(adapter->netdev); 3080 3081 if (hw->mac.type == ixgbe_mac_82598EB) 3082 return; 3083 3084 /* disable the arbiter while setting MTQC */ 3085 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3086 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3087 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3088 3089 /* set transmit pool layout */ 3090 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3091 mtqc = IXGBE_MTQC_VT_ENA; 3092 if (tcs > 4) 3093 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3094 else if (tcs > 1) 3095 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3096 else if (adapter->ring_feature[RING_F_RSS].indices == 4) 3097 mtqc |= IXGBE_MTQC_32VF; 3098 else 3099 mtqc |= IXGBE_MTQC_64VF; 3100 } else { 3101 if (tcs > 4) 3102 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3103 else if (tcs > 1) 3104 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3105 else 3106 mtqc = IXGBE_MTQC_64Q_1PB; 3107 } 3108 3109 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3110 3111 /* Enable Security TX Buffer IFG for multiple pb */ 3112 if (tcs) { 3113 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3114 sectx |= IXGBE_SECTX_DCB; 3115 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3116 } 3117 3118 /* re-enable the arbiter */ 3119 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3120 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3121 } 3122 3123 /** 3124 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3125 * @adapter: board private structure 3126 * 3127 * Configure the Tx unit of the MAC after a reset. 3128 **/ 3129 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3130 { 3131 struct ixgbe_hw *hw = &adapter->hw; 3132 u32 dmatxctl; 3133 u32 i; 3134 3135 ixgbe_setup_mtqc(adapter); 3136 3137 if (hw->mac.type != ixgbe_mac_82598EB) { 3138 /* DMATXCTL.EN must be before Tx queues are enabled */ 3139 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3140 dmatxctl |= IXGBE_DMATXCTL_TE; 3141 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3142 } 3143 3144 /* Setup the HW Tx Head and Tail descriptor pointers */ 3145 for (i = 0; i < adapter->num_tx_queues; i++) 3146 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3147 } 3148 3149 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3150 struct ixgbe_ring *ring) 3151 { 3152 struct ixgbe_hw *hw = &adapter->hw; 3153 u8 reg_idx = ring->reg_idx; 3154 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3155 3156 srrctl |= IXGBE_SRRCTL_DROP_EN; 3157 3158 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3159 } 3160 3161 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3162 struct ixgbe_ring *ring) 3163 { 3164 struct ixgbe_hw *hw = &adapter->hw; 3165 u8 reg_idx = ring->reg_idx; 3166 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3167 3168 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3169 3170 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3171 } 3172 3173 #ifdef CONFIG_IXGBE_DCB 3174 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3175 #else 3176 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3177 #endif 3178 { 3179 int i; 3180 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3181 3182 if (adapter->ixgbe_ieee_pfc) 3183 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3184 3185 /* 3186 * We should set the drop enable bit if: 3187 * SR-IOV is enabled 3188 * or 3189 * Number of Rx queues > 1 and flow control is disabled 3190 * 3191 * This allows us to avoid head of line blocking for security 3192 * and performance reasons. 3193 */ 3194 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3195 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3196 for (i = 0; i < adapter->num_rx_queues; i++) 3197 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3198 } else { 3199 for (i = 0; i < adapter->num_rx_queues; i++) 3200 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3201 } 3202 } 3203 3204 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3205 3206 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3207 struct ixgbe_ring *rx_ring) 3208 { 3209 struct ixgbe_hw *hw = &adapter->hw; 3210 u32 srrctl; 3211 u8 reg_idx = rx_ring->reg_idx; 3212 3213 if (hw->mac.type == ixgbe_mac_82598EB) { 3214 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3215 3216 /* 3217 * if VMDq is not active we must program one srrctl register 3218 * per RSS queue since we have enabled RDRXCTL.MVMEN 3219 */ 3220 reg_idx &= mask; 3221 } 3222 3223 /* configure header buffer length, needed for RSC */ 3224 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3225 3226 /* configure the packet buffer length */ 3227 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3228 3229 /* configure descriptor type */ 3230 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3231 3232 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3233 } 3234 3235 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter, const u32 *seed) 3236 { 3237 struct ixgbe_hw *hw = &adapter->hw; 3238 u32 reta = 0; 3239 int i, j; 3240 int reta_entries = 128; 3241 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3242 int indices_multi; 3243 3244 /* 3245 * Program table for at least 2 queues w/ SR-IOV so that VFs can 3246 * make full use of any rings they may have. We will use the 3247 * PSRTYPE register to control how many rings we use within the PF. 3248 */ 3249 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2)) 3250 rss_i = 2; 3251 3252 /* Fill out hash function seeds */ 3253 for (i = 0; i < 10; i++) 3254 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); 3255 3256 /* Fill out the redirection table as follows: 3257 * 82598: 128 (8 bit wide) entries containing pair of 4 bit RSS indices 3258 * 82599/X540: 128 (8 bit wide) entries containing 4 bit RSS index 3259 * X550: 512 (8 bit wide) entries containing 6 bit RSS index 3260 */ 3261 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3262 indices_multi = 0x11; 3263 else 3264 indices_multi = 0x1; 3265 3266 switch (adapter->hw.mac.type) { 3267 case ixgbe_mac_X550: 3268 case ixgbe_mac_X550EM_x: 3269 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 3270 reta_entries = 512; 3271 default: 3272 break; 3273 } 3274 3275 /* Fill out redirection table */ 3276 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3277 if (j == rss_i) 3278 j = 0; 3279 reta = (reta << 8) | (j * indices_multi); 3280 if ((i & 3) == 3) { 3281 if (i < 128) 3282 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3283 else 3284 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3285 reta); 3286 } 3287 } 3288 } 3289 3290 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter, const u32 *seed) 3291 { 3292 struct ixgbe_hw *hw = &adapter->hw; 3293 u32 vfreta = 0; 3294 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3295 unsigned int pf_pool = adapter->num_vfs; 3296 int i, j; 3297 3298 /* Fill out hash function seeds */ 3299 for (i = 0; i < 10; i++) 3300 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool), seed[i]); 3301 3302 /* Fill out the redirection table */ 3303 for (i = 0, j = 0; i < 64; i++, j++) { 3304 if (j == rss_i) 3305 j = 0; 3306 vfreta = (vfreta << 8) | j; 3307 if ((i & 3) == 3) 3308 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool), 3309 vfreta); 3310 } 3311 } 3312 3313 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3314 { 3315 struct ixgbe_hw *hw = &adapter->hw; 3316 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3317 u32 rss_key[10]; 3318 u32 rxcsum; 3319 3320 /* Disable indicating checksum in descriptor, enables RSS hash */ 3321 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3322 rxcsum |= IXGBE_RXCSUM_PCSD; 3323 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3324 3325 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3326 if (adapter->ring_feature[RING_F_RSS].mask) 3327 mrqc = IXGBE_MRQC_RSSEN; 3328 } else { 3329 u8 tcs = netdev_get_num_tc(adapter->netdev); 3330 3331 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3332 if (tcs > 4) 3333 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3334 else if (tcs > 1) 3335 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3336 else if (adapter->ring_feature[RING_F_RSS].indices == 4) 3337 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3338 else 3339 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3340 } else { 3341 if (tcs > 4) 3342 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3343 else if (tcs > 1) 3344 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3345 else 3346 mrqc = IXGBE_MRQC_RSSEN; 3347 } 3348 } 3349 3350 /* Perform hash on these packet types */ 3351 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3352 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3353 IXGBE_MRQC_RSS_FIELD_IPV6 | 3354 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3355 3356 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3357 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3358 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3359 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3360 3361 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3362 if ((hw->mac.type >= ixgbe_mac_X550) && 3363 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 3364 unsigned int pf_pool = adapter->num_vfs; 3365 3366 /* Enable VF RSS mode */ 3367 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 3368 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3369 3370 /* Setup RSS through the VF registers */ 3371 ixgbe_setup_vfreta(adapter, rss_key); 3372 vfmrqc = IXGBE_MRQC_RSSEN; 3373 vfmrqc |= rss_field; 3374 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc); 3375 } else { 3376 ixgbe_setup_reta(adapter, rss_key); 3377 mrqc |= rss_field; 3378 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3379 } 3380 } 3381 3382 /** 3383 * ixgbe_configure_rscctl - enable RSC for the indicated ring 3384 * @adapter: address of board private structure 3385 * @index: index of ring to set 3386 **/ 3387 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 3388 struct ixgbe_ring *ring) 3389 { 3390 struct ixgbe_hw *hw = &adapter->hw; 3391 u32 rscctrl; 3392 u8 reg_idx = ring->reg_idx; 3393 3394 if (!ring_is_rsc_enabled(ring)) 3395 return; 3396 3397 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 3398 rscctrl |= IXGBE_RSCCTL_RSCEN; 3399 /* 3400 * we must limit the number of descriptors so that the 3401 * total size of max desc * buf_len is not greater 3402 * than 65536 3403 */ 3404 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 3405 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 3406 } 3407 3408 #define IXGBE_MAX_RX_DESC_POLL 10 3409 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 3410 struct ixgbe_ring *ring) 3411 { 3412 struct ixgbe_hw *hw = &adapter->hw; 3413 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 3414 u32 rxdctl; 3415 u8 reg_idx = ring->reg_idx; 3416 3417 if (ixgbe_removed(hw->hw_addr)) 3418 return; 3419 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3420 if (hw->mac.type == ixgbe_mac_82598EB && 3421 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3422 return; 3423 3424 do { 3425 usleep_range(1000, 2000); 3426 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3427 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 3428 3429 if (!wait_loop) { 3430 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 3431 "the polling period\n", reg_idx); 3432 } 3433 } 3434 3435 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, 3436 struct ixgbe_ring *ring) 3437 { 3438 struct ixgbe_hw *hw = &adapter->hw; 3439 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 3440 u32 rxdctl; 3441 u8 reg_idx = ring->reg_idx; 3442 3443 if (ixgbe_removed(hw->hw_addr)) 3444 return; 3445 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3446 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 3447 3448 /* write value back with RXDCTL.ENABLE bit cleared */ 3449 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 3450 3451 if (hw->mac.type == ixgbe_mac_82598EB && 3452 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3453 return; 3454 3455 /* the hardware may take up to 100us to really disable the rx queue */ 3456 do { 3457 udelay(10); 3458 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3459 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); 3460 3461 if (!wait_loop) { 3462 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " 3463 "the polling period\n", reg_idx); 3464 } 3465 } 3466 3467 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 3468 struct ixgbe_ring *ring) 3469 { 3470 struct ixgbe_hw *hw = &adapter->hw; 3471 u64 rdba = ring->dma; 3472 u32 rxdctl; 3473 u8 reg_idx = ring->reg_idx; 3474 3475 /* disable queue to avoid issues while updating state */ 3476 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3477 ixgbe_disable_rx_queue(adapter, ring); 3478 3479 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 3480 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 3481 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 3482 ring->count * sizeof(union ixgbe_adv_rx_desc)); 3483 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 3484 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 3485 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 3486 3487 ixgbe_configure_srrctl(adapter, ring); 3488 ixgbe_configure_rscctl(adapter, ring); 3489 3490 if (hw->mac.type == ixgbe_mac_82598EB) { 3491 /* 3492 * enable cache line friendly hardware writes: 3493 * PTHRESH=32 descriptors (half the internal cache), 3494 * this also removes ugly rx_no_buffer_count increment 3495 * HTHRESH=4 descriptors (to minimize latency on fetch) 3496 * WTHRESH=8 burst writeback up to two cache lines 3497 */ 3498 rxdctl &= ~0x3FFFFF; 3499 rxdctl |= 0x080420; 3500 } 3501 3502 /* enable receive descriptor ring */ 3503 rxdctl |= IXGBE_RXDCTL_ENABLE; 3504 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 3505 3506 ixgbe_rx_desc_queue_enable(adapter, ring); 3507 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 3508 } 3509 3510 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 3511 { 3512 struct ixgbe_hw *hw = &adapter->hw; 3513 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 3514 u16 pool; 3515 3516 /* PSRTYPE must be initialized in non 82598 adapters */ 3517 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 3518 IXGBE_PSRTYPE_UDPHDR | 3519 IXGBE_PSRTYPE_IPV4HDR | 3520 IXGBE_PSRTYPE_L2HDR | 3521 IXGBE_PSRTYPE_IPV6HDR; 3522 3523 if (hw->mac.type == ixgbe_mac_82598EB) 3524 return; 3525 3526 if (rss_i > 3) 3527 psrtype |= 2 << 29; 3528 else if (rss_i > 1) 3529 psrtype |= 1 << 29; 3530 3531 for_each_set_bit(pool, &adapter->fwd_bitmask, 32) 3532 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 3533 } 3534 3535 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 3536 { 3537 struct ixgbe_hw *hw = &adapter->hw; 3538 u32 reg_offset, vf_shift; 3539 u32 gcr_ext, vmdctl; 3540 int i; 3541 3542 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 3543 return; 3544 3545 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 3546 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 3547 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 3548 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 3549 vmdctl |= IXGBE_VT_CTL_REPLEN; 3550 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 3551 3552 vf_shift = VMDQ_P(0) % 32; 3553 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 3554 3555 /* Enable only the PF's pool for Tx/Rx */ 3556 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift); 3557 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 3558 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift); 3559 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 3560 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB) 3561 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 3562 3563 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 3564 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 3565 3566 /* 3567 * Set up VF register offsets for selected VT Mode, 3568 * i.e. 32 or 64 VFs for SR-IOV 3569 */ 3570 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 3571 case IXGBE_82599_VMDQ_8Q_MASK: 3572 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 3573 break; 3574 case IXGBE_82599_VMDQ_4Q_MASK: 3575 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 3576 break; 3577 default: 3578 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 3579 break; 3580 } 3581 3582 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 3583 3584 3585 /* Enable MAC Anti-Spoofing */ 3586 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0), 3587 adapter->num_vfs); 3588 3589 /* Ensure LLDP is set for Ethertype Antispoofing if we will be 3590 * calling set_ethertype_anti_spoofing for each VF in loop below 3591 */ 3592 if (hw->mac.ops.set_ethertype_anti_spoofing) 3593 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP), 3594 (IXGBE_ETQF_FILTER_EN | /* enable filter */ 3595 IXGBE_ETQF_TX_ANTISPOOF | /* tx antispoof */ 3596 IXGBE_ETH_P_LLDP)); /* LLDP eth type */ 3597 3598 /* For VFs that have spoof checking turned off */ 3599 for (i = 0; i < adapter->num_vfs; i++) { 3600 if (!adapter->vfinfo[i].spoofchk_enabled) 3601 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false); 3602 3603 /* enable ethertype anti spoofing if hw supports it */ 3604 if (hw->mac.ops.set_ethertype_anti_spoofing) 3605 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i); 3606 } 3607 } 3608 3609 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 3610 { 3611 struct ixgbe_hw *hw = &adapter->hw; 3612 struct net_device *netdev = adapter->netdev; 3613 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 3614 struct ixgbe_ring *rx_ring; 3615 int i; 3616 u32 mhadd, hlreg0; 3617 3618 #ifdef IXGBE_FCOE 3619 /* adjust max frame to be able to do baby jumbo for FCoE */ 3620 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 3621 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 3622 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 3623 3624 #endif /* IXGBE_FCOE */ 3625 3626 /* adjust max frame to be at least the size of a standard frame */ 3627 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 3628 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 3629 3630 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 3631 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 3632 mhadd &= ~IXGBE_MHADD_MFS_MASK; 3633 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 3634 3635 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 3636 } 3637 3638 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3639 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 3640 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 3641 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3642 3643 /* 3644 * Setup the HW Rx Head and Tail Descriptor Pointers and 3645 * the Base and Length of the Rx Descriptor Ring 3646 */ 3647 for (i = 0; i < adapter->num_rx_queues; i++) { 3648 rx_ring = adapter->rx_ring[i]; 3649 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 3650 set_ring_rsc_enabled(rx_ring); 3651 else 3652 clear_ring_rsc_enabled(rx_ring); 3653 } 3654 } 3655 3656 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 3657 { 3658 struct ixgbe_hw *hw = &adapter->hw; 3659 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 3660 3661 switch (hw->mac.type) { 3662 case ixgbe_mac_X550: 3663 case ixgbe_mac_X550EM_x: 3664 case ixgbe_mac_82598EB: 3665 /* 3666 * For VMDq support of different descriptor types or 3667 * buffer sizes through the use of multiple SRRCTL 3668 * registers, RDRXCTL.MVMEN must be set to 1 3669 * 3670 * also, the manual doesn't mention it clearly but DCA hints 3671 * will only use queue 0's tags unless this bit is set. Side 3672 * effects of setting this bit are only that SRRCTL must be 3673 * fully programmed [0..15] 3674 */ 3675 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 3676 break; 3677 case ixgbe_mac_82599EB: 3678 case ixgbe_mac_X540: 3679 /* Disable RSC for ACK packets */ 3680 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 3681 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 3682 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 3683 /* hardware requires some bits to be set by default */ 3684 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 3685 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 3686 break; 3687 default: 3688 /* We should do nothing since we don't know this hardware */ 3689 return; 3690 } 3691 3692 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 3693 } 3694 3695 /** 3696 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 3697 * @adapter: board private structure 3698 * 3699 * Configure the Rx unit of the MAC after a reset. 3700 **/ 3701 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 3702 { 3703 struct ixgbe_hw *hw = &adapter->hw; 3704 int i; 3705 u32 rxctrl, rfctl; 3706 3707 /* disable receives while setting up the descriptors */ 3708 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 3709 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); 3710 3711 ixgbe_setup_psrtype(adapter); 3712 ixgbe_setup_rdrxctl(adapter); 3713 3714 /* RSC Setup */ 3715 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 3716 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 3717 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 3718 rfctl |= IXGBE_RFCTL_RSC_DIS; 3719 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 3720 3721 /* Program registers for the distribution of queues */ 3722 ixgbe_setup_mrqc(adapter); 3723 3724 /* set_rx_buffer_len must be called before ring initialization */ 3725 ixgbe_set_rx_buffer_len(adapter); 3726 3727 /* 3728 * Setup the HW Rx Head and Tail Descriptor Pointers and 3729 * the Base and Length of the Rx Descriptor Ring 3730 */ 3731 for (i = 0; i < adapter->num_rx_queues; i++) 3732 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 3733 3734 /* disable drop enable for 82598 parts */ 3735 if (hw->mac.type == ixgbe_mac_82598EB) 3736 rxctrl |= IXGBE_RXCTRL_DMBYPS; 3737 3738 /* enable all receives */ 3739 rxctrl |= IXGBE_RXCTRL_RXEN; 3740 hw->mac.ops.enable_rx_dma(hw, rxctrl); 3741 } 3742 3743 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 3744 __be16 proto, u16 vid) 3745 { 3746 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3747 struct ixgbe_hw *hw = &adapter->hw; 3748 3749 /* add VID to filter table */ 3750 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true); 3751 set_bit(vid, adapter->active_vlans); 3752 3753 return 0; 3754 } 3755 3756 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 3757 __be16 proto, u16 vid) 3758 { 3759 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3760 struct ixgbe_hw *hw = &adapter->hw; 3761 3762 /* remove VID from filter table */ 3763 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false); 3764 clear_bit(vid, adapter->active_vlans); 3765 3766 return 0; 3767 } 3768 3769 /** 3770 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 3771 * @adapter: driver data 3772 */ 3773 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 3774 { 3775 struct ixgbe_hw *hw = &adapter->hw; 3776 u32 vlnctrl; 3777 int i, j; 3778 3779 switch (hw->mac.type) { 3780 case ixgbe_mac_82598EB: 3781 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 3782 vlnctrl &= ~IXGBE_VLNCTRL_VME; 3783 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 3784 break; 3785 case ixgbe_mac_82599EB: 3786 case ixgbe_mac_X540: 3787 case ixgbe_mac_X550: 3788 case ixgbe_mac_X550EM_x: 3789 for (i = 0; i < adapter->num_rx_queues; i++) { 3790 struct ixgbe_ring *ring = adapter->rx_ring[i]; 3791 3792 if (ring->l2_accel_priv) 3793 continue; 3794 j = ring->reg_idx; 3795 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 3796 vlnctrl &= ~IXGBE_RXDCTL_VME; 3797 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 3798 } 3799 break; 3800 default: 3801 break; 3802 } 3803 } 3804 3805 /** 3806 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 3807 * @adapter: driver data 3808 */ 3809 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 3810 { 3811 struct ixgbe_hw *hw = &adapter->hw; 3812 u32 vlnctrl; 3813 int i, j; 3814 3815 switch (hw->mac.type) { 3816 case ixgbe_mac_82598EB: 3817 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 3818 vlnctrl |= IXGBE_VLNCTRL_VME; 3819 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 3820 break; 3821 case ixgbe_mac_82599EB: 3822 case ixgbe_mac_X540: 3823 case ixgbe_mac_X550: 3824 case ixgbe_mac_X550EM_x: 3825 for (i = 0; i < adapter->num_rx_queues; i++) { 3826 struct ixgbe_ring *ring = adapter->rx_ring[i]; 3827 3828 if (ring->l2_accel_priv) 3829 continue; 3830 j = ring->reg_idx; 3831 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 3832 vlnctrl |= IXGBE_RXDCTL_VME; 3833 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 3834 } 3835 break; 3836 default: 3837 break; 3838 } 3839 } 3840 3841 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 3842 { 3843 u16 vid; 3844 3845 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 3846 3847 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 3848 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 3849 } 3850 3851 /** 3852 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 3853 * @netdev: network interface device structure 3854 * 3855 * Writes multicast address list to the MTA hash table. 3856 * Returns: -ENOMEM on failure 3857 * 0 on no addresses written 3858 * X on writing X addresses to MTA 3859 **/ 3860 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 3861 { 3862 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3863 struct ixgbe_hw *hw = &adapter->hw; 3864 3865 if (!netif_running(netdev)) 3866 return 0; 3867 3868 if (hw->mac.ops.update_mc_addr_list) 3869 hw->mac.ops.update_mc_addr_list(hw, netdev); 3870 else 3871 return -ENOMEM; 3872 3873 #ifdef CONFIG_PCI_IOV 3874 ixgbe_restore_vf_multicasts(adapter); 3875 #endif 3876 3877 return netdev_mc_count(netdev); 3878 } 3879 3880 #ifdef CONFIG_PCI_IOV 3881 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 3882 { 3883 struct ixgbe_hw *hw = &adapter->hw; 3884 int i; 3885 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3886 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE) 3887 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr, 3888 adapter->mac_table[i].queue, 3889 IXGBE_RAH_AV); 3890 else 3891 hw->mac.ops.clear_rar(hw, i); 3892 3893 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED); 3894 } 3895 } 3896 #endif 3897 3898 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 3899 { 3900 struct ixgbe_hw *hw = &adapter->hw; 3901 int i; 3902 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3903 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) { 3904 if (adapter->mac_table[i].state & 3905 IXGBE_MAC_STATE_IN_USE) 3906 hw->mac.ops.set_rar(hw, i, 3907 adapter->mac_table[i].addr, 3908 adapter->mac_table[i].queue, 3909 IXGBE_RAH_AV); 3910 else 3911 hw->mac.ops.clear_rar(hw, i); 3912 3913 adapter->mac_table[i].state &= 3914 ~(IXGBE_MAC_STATE_MODIFIED); 3915 } 3916 } 3917 } 3918 3919 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 3920 { 3921 int i; 3922 struct ixgbe_hw *hw = &adapter->hw; 3923 3924 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3925 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED; 3926 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE; 3927 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 3928 adapter->mac_table[i].queue = 0; 3929 } 3930 ixgbe_sync_mac_table(adapter); 3931 } 3932 3933 static int ixgbe_available_rars(struct ixgbe_adapter *adapter) 3934 { 3935 struct ixgbe_hw *hw = &adapter->hw; 3936 int i, count = 0; 3937 3938 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3939 if (adapter->mac_table[i].state == 0) 3940 count++; 3941 } 3942 return count; 3943 } 3944 3945 /* this function destroys the first RAR entry */ 3946 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter, 3947 u8 *addr) 3948 { 3949 struct ixgbe_hw *hw = &adapter->hw; 3950 3951 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN); 3952 adapter->mac_table[0].queue = VMDQ_P(0); 3953 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT | 3954 IXGBE_MAC_STATE_IN_USE); 3955 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr, 3956 adapter->mac_table[0].queue, 3957 IXGBE_RAH_AV); 3958 } 3959 3960 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue) 3961 { 3962 struct ixgbe_hw *hw = &adapter->hw; 3963 int i; 3964 3965 if (is_zero_ether_addr(addr)) 3966 return -EINVAL; 3967 3968 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3969 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE) 3970 continue; 3971 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED | 3972 IXGBE_MAC_STATE_IN_USE); 3973 ether_addr_copy(adapter->mac_table[i].addr, addr); 3974 adapter->mac_table[i].queue = queue; 3975 ixgbe_sync_mac_table(adapter); 3976 return i; 3977 } 3978 return -ENOMEM; 3979 } 3980 3981 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue) 3982 { 3983 /* search table for addr, if found, set to 0 and sync */ 3984 int i; 3985 struct ixgbe_hw *hw = &adapter->hw; 3986 3987 if (is_zero_ether_addr(addr)) 3988 return -EINVAL; 3989 3990 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3991 if (ether_addr_equal(addr, adapter->mac_table[i].addr) && 3992 adapter->mac_table[i].queue == queue) { 3993 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED; 3994 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE; 3995 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 3996 adapter->mac_table[i].queue = 0; 3997 ixgbe_sync_mac_table(adapter); 3998 return 0; 3999 } 4000 } 4001 return -ENOMEM; 4002 } 4003 /** 4004 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table 4005 * @netdev: network interface device structure 4006 * 4007 * Writes unicast address list to the RAR table. 4008 * Returns: -ENOMEM on failure/insufficient address space 4009 * 0 on no addresses written 4010 * X on writing X addresses to the RAR table 4011 **/ 4012 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn) 4013 { 4014 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4015 int count = 0; 4016 4017 /* return ENOMEM indicating insufficient memory for addresses */ 4018 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter)) 4019 return -ENOMEM; 4020 4021 if (!netdev_uc_empty(netdev)) { 4022 struct netdev_hw_addr *ha; 4023 netdev_for_each_uc_addr(ha, netdev) { 4024 ixgbe_del_mac_filter(adapter, ha->addr, vfn); 4025 ixgbe_add_mac_filter(adapter, ha->addr, vfn); 4026 count++; 4027 } 4028 } 4029 return count; 4030 } 4031 4032 /** 4033 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4034 * @netdev: network interface device structure 4035 * 4036 * The set_rx_method entry point is called whenever the unicast/multicast 4037 * address list or the network interface flags are updated. This routine is 4038 * responsible for configuring the hardware for proper unicast, multicast and 4039 * promiscuous mode. 4040 **/ 4041 void ixgbe_set_rx_mode(struct net_device *netdev) 4042 { 4043 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4044 struct ixgbe_hw *hw = &adapter->hw; 4045 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4046 u32 vlnctrl; 4047 int count; 4048 4049 /* Check for Promiscuous and All Multicast modes */ 4050 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4051 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4052 4053 /* set all bits that we expect to always be set */ 4054 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4055 fctrl |= IXGBE_FCTRL_BAM; 4056 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4057 fctrl |= IXGBE_FCTRL_PMCF; 4058 4059 /* clear the bits we are changing the status of */ 4060 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4061 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); 4062 if (netdev->flags & IFF_PROMISC) { 4063 hw->addr_ctrl.user_set_promisc = true; 4064 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4065 vmolr |= IXGBE_VMOLR_MPE; 4066 /* Only disable hardware filter vlans in promiscuous mode 4067 * if SR-IOV and VMDQ are disabled - otherwise ensure 4068 * that hardware VLAN filters remain enabled. 4069 */ 4070 if (adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED | 4071 IXGBE_FLAG_SRIOV_ENABLED)) 4072 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); 4073 } else { 4074 if (netdev->flags & IFF_ALLMULTI) { 4075 fctrl |= IXGBE_FCTRL_MPE; 4076 vmolr |= IXGBE_VMOLR_MPE; 4077 } 4078 vlnctrl |= IXGBE_VLNCTRL_VFE; 4079 hw->addr_ctrl.user_set_promisc = false; 4080 } 4081 4082 /* 4083 * Write addresses to available RAR registers, if there is not 4084 * sufficient space to store all the addresses then enable 4085 * unicast promiscuous mode 4086 */ 4087 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0)); 4088 if (count < 0) { 4089 fctrl |= IXGBE_FCTRL_UPE; 4090 vmolr |= IXGBE_VMOLR_ROPE; 4091 } 4092 4093 /* Write addresses to the MTA, if the attempt fails 4094 * then we should just turn on promiscuous mode so 4095 * that we can at least receive multicast traffic 4096 */ 4097 count = ixgbe_write_mc_addr_list(netdev); 4098 if (count < 0) { 4099 fctrl |= IXGBE_FCTRL_MPE; 4100 vmolr |= IXGBE_VMOLR_MPE; 4101 } else if (count) { 4102 vmolr |= IXGBE_VMOLR_ROMPE; 4103 } 4104 4105 if (hw->mac.type != ixgbe_mac_82598EB) { 4106 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4107 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4108 IXGBE_VMOLR_ROPE); 4109 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4110 } 4111 4112 /* This is useful for sniffing bad packets. */ 4113 if (adapter->netdev->features & NETIF_F_RXALL) { 4114 /* UPE and MPE will be handled by normal PROMISC logic 4115 * in e1000e_set_rx_mode */ 4116 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 4117 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 4118 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 4119 4120 fctrl &= ~(IXGBE_FCTRL_DPF); 4121 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 4122 } 4123 4124 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4125 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4126 4127 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 4128 ixgbe_vlan_strip_enable(adapter); 4129 else 4130 ixgbe_vlan_strip_disable(adapter); 4131 } 4132 4133 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 4134 { 4135 int q_idx; 4136 4137 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) { 4138 ixgbe_qv_init_lock(adapter->q_vector[q_idx]); 4139 napi_enable(&adapter->q_vector[q_idx]->napi); 4140 } 4141 } 4142 4143 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 4144 { 4145 int q_idx; 4146 4147 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) { 4148 napi_disable(&adapter->q_vector[q_idx]->napi); 4149 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) { 4150 pr_info("QV %d locked\n", q_idx); 4151 usleep_range(1000, 20000); 4152 } 4153 } 4154 } 4155 4156 #ifdef CONFIG_IXGBE_DCB 4157 /** 4158 * ixgbe_configure_dcb - Configure DCB hardware 4159 * @adapter: ixgbe adapter struct 4160 * 4161 * This is called by the driver on open to configure the DCB hardware. 4162 * This is also called by the gennetlink interface when reconfiguring 4163 * the DCB state. 4164 */ 4165 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 4166 { 4167 struct ixgbe_hw *hw = &adapter->hw; 4168 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4169 4170 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 4171 if (hw->mac.type == ixgbe_mac_82598EB) 4172 netif_set_gso_max_size(adapter->netdev, 65536); 4173 return; 4174 } 4175 4176 if (hw->mac.type == ixgbe_mac_82598EB) 4177 netif_set_gso_max_size(adapter->netdev, 32768); 4178 4179 #ifdef IXGBE_FCOE 4180 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 4181 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 4182 #endif 4183 4184 /* reconfigure the hardware */ 4185 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 4186 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 4187 DCB_TX_CONFIG); 4188 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 4189 DCB_RX_CONFIG); 4190 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 4191 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 4192 ixgbe_dcb_hw_ets(&adapter->hw, 4193 adapter->ixgbe_ieee_ets, 4194 max_frame); 4195 ixgbe_dcb_hw_pfc_config(&adapter->hw, 4196 adapter->ixgbe_ieee_pfc->pfc_en, 4197 adapter->ixgbe_ieee_ets->prio_tc); 4198 } 4199 4200 /* Enable RSS Hash per TC */ 4201 if (hw->mac.type != ixgbe_mac_82598EB) { 4202 u32 msb = 0; 4203 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 4204 4205 while (rss_i) { 4206 msb++; 4207 rss_i >>= 1; 4208 } 4209 4210 /* write msb to all 8 TCs in one write */ 4211 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 4212 } 4213 } 4214 #endif 4215 4216 /* Additional bittime to account for IXGBE framing */ 4217 #define IXGBE_ETH_FRAMING 20 4218 4219 /** 4220 * ixgbe_hpbthresh - calculate high water mark for flow control 4221 * 4222 * @adapter: board private structure to calculate for 4223 * @pb: packet buffer to calculate 4224 */ 4225 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 4226 { 4227 struct ixgbe_hw *hw = &adapter->hw; 4228 struct net_device *dev = adapter->netdev; 4229 int link, tc, kb, marker; 4230 u32 dv_id, rx_pba; 4231 4232 /* Calculate max LAN frame size */ 4233 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 4234 4235 #ifdef IXGBE_FCOE 4236 /* FCoE traffic class uses FCOE jumbo frames */ 4237 if ((dev->features & NETIF_F_FCOE_MTU) && 4238 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 4239 (pb == ixgbe_fcoe_get_tc(adapter))) 4240 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4241 #endif 4242 4243 /* Calculate delay value for device */ 4244 switch (hw->mac.type) { 4245 case ixgbe_mac_X540: 4246 case ixgbe_mac_X550: 4247 case ixgbe_mac_X550EM_x: 4248 dv_id = IXGBE_DV_X540(link, tc); 4249 break; 4250 default: 4251 dv_id = IXGBE_DV(link, tc); 4252 break; 4253 } 4254 4255 /* Loopback switch introduces additional latency */ 4256 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 4257 dv_id += IXGBE_B2BT(tc); 4258 4259 /* Delay value is calculated in bit times convert to KB */ 4260 kb = IXGBE_BT2KB(dv_id); 4261 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 4262 4263 marker = rx_pba - kb; 4264 4265 /* It is possible that the packet buffer is not large enough 4266 * to provide required headroom. In this case throw an error 4267 * to user and a do the best we can. 4268 */ 4269 if (marker < 0) { 4270 e_warn(drv, "Packet Buffer(%i) can not provide enough" 4271 "headroom to support flow control." 4272 "Decrease MTU or number of traffic classes\n", pb); 4273 marker = tc + 1; 4274 } 4275 4276 return marker; 4277 } 4278 4279 /** 4280 * ixgbe_lpbthresh - calculate low water mark for for flow control 4281 * 4282 * @adapter: board private structure to calculate for 4283 * @pb: packet buffer to calculate 4284 */ 4285 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 4286 { 4287 struct ixgbe_hw *hw = &adapter->hw; 4288 struct net_device *dev = adapter->netdev; 4289 int tc; 4290 u32 dv_id; 4291 4292 /* Calculate max LAN frame size */ 4293 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 4294 4295 #ifdef IXGBE_FCOE 4296 /* FCoE traffic class uses FCOE jumbo frames */ 4297 if ((dev->features & NETIF_F_FCOE_MTU) && 4298 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 4299 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 4300 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4301 #endif 4302 4303 /* Calculate delay value for device */ 4304 switch (hw->mac.type) { 4305 case ixgbe_mac_X540: 4306 case ixgbe_mac_X550: 4307 case ixgbe_mac_X550EM_x: 4308 dv_id = IXGBE_LOW_DV_X540(tc); 4309 break; 4310 default: 4311 dv_id = IXGBE_LOW_DV(tc); 4312 break; 4313 } 4314 4315 /* Delay value is calculated in bit times convert to KB */ 4316 return IXGBE_BT2KB(dv_id); 4317 } 4318 4319 /* 4320 * ixgbe_pbthresh_setup - calculate and setup high low water marks 4321 */ 4322 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 4323 { 4324 struct ixgbe_hw *hw = &adapter->hw; 4325 int num_tc = netdev_get_num_tc(adapter->netdev); 4326 int i; 4327 4328 if (!num_tc) 4329 num_tc = 1; 4330 4331 for (i = 0; i < num_tc; i++) { 4332 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 4333 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 4334 4335 /* Low water marks must not be larger than high water marks */ 4336 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 4337 hw->fc.low_water[i] = 0; 4338 } 4339 4340 for (; i < MAX_TRAFFIC_CLASS; i++) 4341 hw->fc.high_water[i] = 0; 4342 } 4343 4344 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 4345 { 4346 struct ixgbe_hw *hw = &adapter->hw; 4347 int hdrm; 4348 u8 tc = netdev_get_num_tc(adapter->netdev); 4349 4350 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 4351 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 4352 hdrm = 32 << adapter->fdir_pballoc; 4353 else 4354 hdrm = 0; 4355 4356 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 4357 ixgbe_pbthresh_setup(adapter); 4358 } 4359 4360 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 4361 { 4362 struct ixgbe_hw *hw = &adapter->hw; 4363 struct hlist_node *node2; 4364 struct ixgbe_fdir_filter *filter; 4365 4366 spin_lock(&adapter->fdir_perfect_lock); 4367 4368 if (!hlist_empty(&adapter->fdir_filter_list)) 4369 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 4370 4371 hlist_for_each_entry_safe(filter, node2, 4372 &adapter->fdir_filter_list, fdir_node) { 4373 ixgbe_fdir_write_perfect_filter_82599(hw, 4374 &filter->filter, 4375 filter->sw_idx, 4376 (filter->action == IXGBE_FDIR_DROP_QUEUE) ? 4377 IXGBE_FDIR_DROP_QUEUE : 4378 adapter->rx_ring[filter->action]->reg_idx); 4379 } 4380 4381 spin_unlock(&adapter->fdir_perfect_lock); 4382 } 4383 4384 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool, 4385 struct ixgbe_adapter *adapter) 4386 { 4387 struct ixgbe_hw *hw = &adapter->hw; 4388 u32 vmolr; 4389 4390 /* No unicast promiscuous support for VMDQ devices. */ 4391 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool)); 4392 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE); 4393 4394 /* clear the affected bit */ 4395 vmolr &= ~IXGBE_VMOLR_MPE; 4396 4397 if (dev->flags & IFF_ALLMULTI) { 4398 vmolr |= IXGBE_VMOLR_MPE; 4399 } else { 4400 vmolr |= IXGBE_VMOLR_ROMPE; 4401 hw->mac.ops.update_mc_addr_list(hw, dev); 4402 } 4403 ixgbe_write_uc_addr_list(adapter->netdev, pool); 4404 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr); 4405 } 4406 4407 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter) 4408 { 4409 struct ixgbe_adapter *adapter = vadapter->real_adapter; 4410 int rss_i = adapter->num_rx_queues_per_pool; 4411 struct ixgbe_hw *hw = &adapter->hw; 4412 u16 pool = vadapter->pool; 4413 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4414 IXGBE_PSRTYPE_UDPHDR | 4415 IXGBE_PSRTYPE_IPV4HDR | 4416 IXGBE_PSRTYPE_L2HDR | 4417 IXGBE_PSRTYPE_IPV6HDR; 4418 4419 if (hw->mac.type == ixgbe_mac_82598EB) 4420 return; 4421 4422 if (rss_i > 3) 4423 psrtype |= 2 << 29; 4424 else if (rss_i > 1) 4425 psrtype |= 1 << 29; 4426 4427 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4428 } 4429 4430 /** 4431 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 4432 * @rx_ring: ring to free buffers from 4433 **/ 4434 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 4435 { 4436 struct device *dev = rx_ring->dev; 4437 unsigned long size; 4438 u16 i; 4439 4440 /* ring already cleared, nothing to do */ 4441 if (!rx_ring->rx_buffer_info) 4442 return; 4443 4444 /* Free all the Rx ring sk_buffs */ 4445 for (i = 0; i < rx_ring->count; i++) { 4446 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 4447 4448 if (rx_buffer->skb) { 4449 struct sk_buff *skb = rx_buffer->skb; 4450 if (IXGBE_CB(skb)->page_released) 4451 dma_unmap_page(dev, 4452 IXGBE_CB(skb)->dma, 4453 ixgbe_rx_bufsz(rx_ring), 4454 DMA_FROM_DEVICE); 4455 dev_kfree_skb(skb); 4456 rx_buffer->skb = NULL; 4457 } 4458 4459 if (!rx_buffer->page) 4460 continue; 4461 4462 dma_unmap_page(dev, rx_buffer->dma, 4463 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); 4464 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring)); 4465 4466 rx_buffer->page = NULL; 4467 } 4468 4469 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 4470 memset(rx_ring->rx_buffer_info, 0, size); 4471 4472 /* Zero out the descriptor ring */ 4473 memset(rx_ring->desc, 0, rx_ring->size); 4474 4475 rx_ring->next_to_alloc = 0; 4476 rx_ring->next_to_clean = 0; 4477 rx_ring->next_to_use = 0; 4478 } 4479 4480 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter, 4481 struct ixgbe_ring *rx_ring) 4482 { 4483 struct ixgbe_adapter *adapter = vadapter->real_adapter; 4484 int index = rx_ring->queue_index + vadapter->rx_base_queue; 4485 4486 /* shutdown specific queue receive and wait for dma to settle */ 4487 ixgbe_disable_rx_queue(adapter, rx_ring); 4488 usleep_range(10000, 20000); 4489 ixgbe_irq_disable_queues(adapter, ((u64)1 << index)); 4490 ixgbe_clean_rx_ring(rx_ring); 4491 rx_ring->l2_accel_priv = NULL; 4492 } 4493 4494 static int ixgbe_fwd_ring_down(struct net_device *vdev, 4495 struct ixgbe_fwd_adapter *accel) 4496 { 4497 struct ixgbe_adapter *adapter = accel->real_adapter; 4498 unsigned int rxbase = accel->rx_base_queue; 4499 unsigned int txbase = accel->tx_base_queue; 4500 int i; 4501 4502 netif_tx_stop_all_queues(vdev); 4503 4504 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4505 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); 4506 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev; 4507 } 4508 4509 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4510 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL; 4511 adapter->tx_ring[txbase + i]->netdev = adapter->netdev; 4512 } 4513 4514 4515 return 0; 4516 } 4517 4518 static int ixgbe_fwd_ring_up(struct net_device *vdev, 4519 struct ixgbe_fwd_adapter *accel) 4520 { 4521 struct ixgbe_adapter *adapter = accel->real_adapter; 4522 unsigned int rxbase, txbase, queues; 4523 int i, baseq, err = 0; 4524 4525 if (!test_bit(accel->pool, &adapter->fwd_bitmask)) 4526 return 0; 4527 4528 baseq = accel->pool * adapter->num_rx_queues_per_pool; 4529 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", 4530 accel->pool, adapter->num_rx_pools, 4531 baseq, baseq + adapter->num_rx_queues_per_pool, 4532 adapter->fwd_bitmask); 4533 4534 accel->netdev = vdev; 4535 accel->rx_base_queue = rxbase = baseq; 4536 accel->tx_base_queue = txbase = baseq; 4537 4538 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 4539 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); 4540 4541 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4542 adapter->rx_ring[rxbase + i]->netdev = vdev; 4543 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel; 4544 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]); 4545 } 4546 4547 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4548 adapter->tx_ring[txbase + i]->netdev = vdev; 4549 adapter->tx_ring[txbase + i]->l2_accel_priv = accel; 4550 } 4551 4552 queues = min_t(unsigned int, 4553 adapter->num_rx_queues_per_pool, vdev->num_tx_queues); 4554 err = netif_set_real_num_tx_queues(vdev, queues); 4555 if (err) 4556 goto fwd_queue_err; 4557 4558 err = netif_set_real_num_rx_queues(vdev, queues); 4559 if (err) 4560 goto fwd_queue_err; 4561 4562 if (is_valid_ether_addr(vdev->dev_addr)) 4563 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool); 4564 4565 ixgbe_fwd_psrtype(accel); 4566 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter); 4567 return err; 4568 fwd_queue_err: 4569 ixgbe_fwd_ring_down(vdev, accel); 4570 return err; 4571 } 4572 4573 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 4574 { 4575 struct net_device *upper; 4576 struct list_head *iter; 4577 int err; 4578 4579 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { 4580 if (netif_is_macvlan(upper)) { 4581 struct macvlan_dev *dfwd = netdev_priv(upper); 4582 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; 4583 4584 if (dfwd->fwd_priv) { 4585 err = ixgbe_fwd_ring_up(upper, vadapter); 4586 if (err) 4587 continue; 4588 } 4589 } 4590 } 4591 } 4592 4593 static void ixgbe_configure(struct ixgbe_adapter *adapter) 4594 { 4595 struct ixgbe_hw *hw = &adapter->hw; 4596 4597 ixgbe_configure_pb(adapter); 4598 #ifdef CONFIG_IXGBE_DCB 4599 ixgbe_configure_dcb(adapter); 4600 #endif 4601 /* 4602 * We must restore virtualization before VLANs or else 4603 * the VLVF registers will not be populated 4604 */ 4605 ixgbe_configure_virtualization(adapter); 4606 4607 ixgbe_set_rx_mode(adapter->netdev); 4608 ixgbe_restore_vlan(adapter); 4609 4610 switch (hw->mac.type) { 4611 case ixgbe_mac_82599EB: 4612 case ixgbe_mac_X540: 4613 hw->mac.ops.disable_rx_buff(hw); 4614 break; 4615 default: 4616 break; 4617 } 4618 4619 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 4620 ixgbe_init_fdir_signature_82599(&adapter->hw, 4621 adapter->fdir_pballoc); 4622 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 4623 ixgbe_init_fdir_perfect_82599(&adapter->hw, 4624 adapter->fdir_pballoc); 4625 ixgbe_fdir_filter_restore(adapter); 4626 } 4627 4628 switch (hw->mac.type) { 4629 case ixgbe_mac_82599EB: 4630 case ixgbe_mac_X540: 4631 hw->mac.ops.enable_rx_buff(hw); 4632 break; 4633 default: 4634 break; 4635 } 4636 4637 #ifdef IXGBE_FCOE 4638 /* configure FCoE L2 filters, redirection table, and Rx control */ 4639 ixgbe_configure_fcoe(adapter); 4640 4641 #endif /* IXGBE_FCOE */ 4642 ixgbe_configure_tx(adapter); 4643 ixgbe_configure_rx(adapter); 4644 ixgbe_configure_dfwd(adapter); 4645 } 4646 4647 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 4648 { 4649 switch (hw->phy.type) { 4650 case ixgbe_phy_sfp_avago: 4651 case ixgbe_phy_sfp_ftl: 4652 case ixgbe_phy_sfp_intel: 4653 case ixgbe_phy_sfp_unknown: 4654 case ixgbe_phy_sfp_passive_tyco: 4655 case ixgbe_phy_sfp_passive_unknown: 4656 case ixgbe_phy_sfp_active_unknown: 4657 case ixgbe_phy_sfp_ftl_active: 4658 case ixgbe_phy_qsfp_passive_unknown: 4659 case ixgbe_phy_qsfp_active_unknown: 4660 case ixgbe_phy_qsfp_intel: 4661 case ixgbe_phy_qsfp_unknown: 4662 /* ixgbe_phy_none is set when no SFP module is present */ 4663 case ixgbe_phy_none: 4664 return true; 4665 case ixgbe_phy_nl: 4666 if (hw->mac.type == ixgbe_mac_82598EB) 4667 return true; 4668 default: 4669 return false; 4670 } 4671 } 4672 4673 /** 4674 * ixgbe_sfp_link_config - set up SFP+ link 4675 * @adapter: pointer to private adapter struct 4676 **/ 4677 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 4678 { 4679 /* 4680 * We are assuming the worst case scenario here, and that 4681 * is that an SFP was inserted/removed after the reset 4682 * but before SFP detection was enabled. As such the best 4683 * solution is to just start searching as soon as we start 4684 */ 4685 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 4686 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 4687 4688 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 4689 } 4690 4691 /** 4692 * ixgbe_non_sfp_link_config - set up non-SFP+ link 4693 * @hw: pointer to private hardware struct 4694 * 4695 * Returns 0 on success, negative on failure 4696 **/ 4697 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 4698 { 4699 u32 speed; 4700 bool autoneg, link_up = false; 4701 u32 ret = IXGBE_ERR_LINK_SETUP; 4702 4703 if (hw->mac.ops.check_link) 4704 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 4705 4706 if (ret) 4707 return ret; 4708 4709 speed = hw->phy.autoneg_advertised; 4710 if ((!speed) && (hw->mac.ops.get_link_capabilities)) 4711 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 4712 &autoneg); 4713 if (ret) 4714 return ret; 4715 4716 if (hw->mac.ops.setup_link) 4717 ret = hw->mac.ops.setup_link(hw, speed, link_up); 4718 4719 return ret; 4720 } 4721 4722 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 4723 { 4724 struct ixgbe_hw *hw = &adapter->hw; 4725 u32 gpie = 0; 4726 4727 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 4728 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 4729 IXGBE_GPIE_OCD; 4730 gpie |= IXGBE_GPIE_EIAME; 4731 /* 4732 * use EIAM to auto-mask when MSI-X interrupt is asserted 4733 * this saves a register write for every interrupt 4734 */ 4735 switch (hw->mac.type) { 4736 case ixgbe_mac_82598EB: 4737 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 4738 break; 4739 case ixgbe_mac_82599EB: 4740 case ixgbe_mac_X540: 4741 case ixgbe_mac_X550: 4742 case ixgbe_mac_X550EM_x: 4743 default: 4744 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 4745 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 4746 break; 4747 } 4748 } else { 4749 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 4750 * specifically only auto mask tx and rx interrupts */ 4751 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 4752 } 4753 4754 /* XXX: to interrupt immediately for EICS writes, enable this */ 4755 /* gpie |= IXGBE_GPIE_EIMEN; */ 4756 4757 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 4758 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 4759 4760 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4761 case IXGBE_82599_VMDQ_8Q_MASK: 4762 gpie |= IXGBE_GPIE_VTMODE_16; 4763 break; 4764 case IXGBE_82599_VMDQ_4Q_MASK: 4765 gpie |= IXGBE_GPIE_VTMODE_32; 4766 break; 4767 default: 4768 gpie |= IXGBE_GPIE_VTMODE_64; 4769 break; 4770 } 4771 } 4772 4773 /* Enable Thermal over heat sensor interrupt */ 4774 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 4775 switch (adapter->hw.mac.type) { 4776 case ixgbe_mac_82599EB: 4777 gpie |= IXGBE_SDP0_GPIEN; 4778 break; 4779 case ixgbe_mac_X540: 4780 gpie |= IXGBE_EIMS_TS; 4781 break; 4782 default: 4783 break; 4784 } 4785 } 4786 4787 /* Enable fan failure interrupt */ 4788 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 4789 gpie |= IXGBE_SDP1_GPIEN; 4790 4791 if (hw->mac.type == ixgbe_mac_82599EB) { 4792 gpie |= IXGBE_SDP1_GPIEN; 4793 gpie |= IXGBE_SDP2_GPIEN; 4794 } 4795 4796 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 4797 } 4798 4799 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 4800 { 4801 struct ixgbe_hw *hw = &adapter->hw; 4802 int err; 4803 u32 ctrl_ext; 4804 4805 ixgbe_get_hw_control(adapter); 4806 ixgbe_setup_gpie(adapter); 4807 4808 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 4809 ixgbe_configure_msix(adapter); 4810 else 4811 ixgbe_configure_msi_and_legacy(adapter); 4812 4813 /* enable the optics for 82599 SFP+ fiber */ 4814 if (hw->mac.ops.enable_tx_laser) 4815 hw->mac.ops.enable_tx_laser(hw); 4816 4817 smp_mb__before_atomic(); 4818 clear_bit(__IXGBE_DOWN, &adapter->state); 4819 ixgbe_napi_enable_all(adapter); 4820 4821 if (ixgbe_is_sfp(hw)) { 4822 ixgbe_sfp_link_config(adapter); 4823 } else { 4824 err = ixgbe_non_sfp_link_config(hw); 4825 if (err) 4826 e_err(probe, "link_config FAILED %d\n", err); 4827 } 4828 4829 /* clear any pending interrupts, may auto mask */ 4830 IXGBE_READ_REG(hw, IXGBE_EICR); 4831 ixgbe_irq_enable(adapter, true, true); 4832 4833 /* 4834 * If this adapter has a fan, check to see if we had a failure 4835 * before we enabled the interrupt. 4836 */ 4837 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 4838 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 4839 if (esdp & IXGBE_ESDP_SDP1) 4840 e_crit(drv, "Fan has stopped, replace the adapter\n"); 4841 } 4842 4843 /* bring the link up in the watchdog, this could race with our first 4844 * link up interrupt but shouldn't be a problem */ 4845 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 4846 adapter->link_check_timeout = jiffies; 4847 mod_timer(&adapter->service_timer, jiffies); 4848 4849 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 4850 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 4851 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 4852 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 4853 } 4854 4855 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 4856 { 4857 WARN_ON(in_interrupt()); 4858 /* put off any impending NetWatchDogTimeout */ 4859 adapter->netdev->trans_start = jiffies; 4860 4861 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 4862 usleep_range(1000, 2000); 4863 ixgbe_down(adapter); 4864 /* 4865 * If SR-IOV enabled then wait a bit before bringing the adapter 4866 * back up to give the VFs time to respond to the reset. The 4867 * two second wait is based upon the watchdog timer cycle in 4868 * the VF driver. 4869 */ 4870 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 4871 msleep(2000); 4872 ixgbe_up(adapter); 4873 clear_bit(__IXGBE_RESETTING, &adapter->state); 4874 } 4875 4876 void ixgbe_up(struct ixgbe_adapter *adapter) 4877 { 4878 /* hardware has been reset, we need to reload some things */ 4879 ixgbe_configure(adapter); 4880 4881 ixgbe_up_complete(adapter); 4882 } 4883 4884 void ixgbe_reset(struct ixgbe_adapter *adapter) 4885 { 4886 struct ixgbe_hw *hw = &adapter->hw; 4887 struct net_device *netdev = adapter->netdev; 4888 int err; 4889 u8 old_addr[ETH_ALEN]; 4890 4891 if (ixgbe_removed(hw->hw_addr)) 4892 return; 4893 /* lock SFP init bit to prevent race conditions with the watchdog */ 4894 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 4895 usleep_range(1000, 2000); 4896 4897 /* clear all SFP and link config related flags while holding SFP_INIT */ 4898 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 4899 IXGBE_FLAG2_SFP_NEEDS_RESET); 4900 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 4901 4902 err = hw->mac.ops.init_hw(hw); 4903 switch (err) { 4904 case 0: 4905 case IXGBE_ERR_SFP_NOT_PRESENT: 4906 case IXGBE_ERR_SFP_NOT_SUPPORTED: 4907 break; 4908 case IXGBE_ERR_MASTER_REQUESTS_PENDING: 4909 e_dev_err("master disable timed out\n"); 4910 break; 4911 case IXGBE_ERR_EEPROM_VERSION: 4912 /* We are running on a pre-production device, log a warning */ 4913 e_dev_warn("This device is a pre-production adapter/LOM. " 4914 "Please be aware there may be issues associated with " 4915 "your hardware. If you are experiencing problems " 4916 "please contact your Intel or hardware " 4917 "representative who provided you with this " 4918 "hardware.\n"); 4919 break; 4920 default: 4921 e_dev_err("Hardware Error: %d\n", err); 4922 } 4923 4924 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 4925 /* do not flush user set addresses */ 4926 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len); 4927 ixgbe_flush_sw_mac_table(adapter); 4928 ixgbe_mac_set_default_filter(adapter, old_addr); 4929 4930 /* update SAN MAC vmdq pool selection */ 4931 if (hw->mac.san_mac_rar_index) 4932 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 4933 4934 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 4935 ixgbe_ptp_reset(adapter); 4936 } 4937 4938 /** 4939 * ixgbe_clean_tx_ring - Free Tx Buffers 4940 * @tx_ring: ring to be cleaned 4941 **/ 4942 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 4943 { 4944 struct ixgbe_tx_buffer *tx_buffer_info; 4945 unsigned long size; 4946 u16 i; 4947 4948 /* ring already cleared, nothing to do */ 4949 if (!tx_ring->tx_buffer_info) 4950 return; 4951 4952 /* Free all the Tx ring sk_buffs */ 4953 for (i = 0; i < tx_ring->count; i++) { 4954 tx_buffer_info = &tx_ring->tx_buffer_info[i]; 4955 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); 4956 } 4957 4958 netdev_tx_reset_queue(txring_txq(tx_ring)); 4959 4960 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 4961 memset(tx_ring->tx_buffer_info, 0, size); 4962 4963 /* Zero out the descriptor ring */ 4964 memset(tx_ring->desc, 0, tx_ring->size); 4965 4966 tx_ring->next_to_use = 0; 4967 tx_ring->next_to_clean = 0; 4968 } 4969 4970 /** 4971 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 4972 * @adapter: board private structure 4973 **/ 4974 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 4975 { 4976 int i; 4977 4978 for (i = 0; i < adapter->num_rx_queues; i++) 4979 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 4980 } 4981 4982 /** 4983 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 4984 * @adapter: board private structure 4985 **/ 4986 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 4987 { 4988 int i; 4989 4990 for (i = 0; i < adapter->num_tx_queues; i++) 4991 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 4992 } 4993 4994 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 4995 { 4996 struct hlist_node *node2; 4997 struct ixgbe_fdir_filter *filter; 4998 4999 spin_lock(&adapter->fdir_perfect_lock); 5000 5001 hlist_for_each_entry_safe(filter, node2, 5002 &adapter->fdir_filter_list, fdir_node) { 5003 hlist_del(&filter->fdir_node); 5004 kfree(filter); 5005 } 5006 adapter->fdir_filter_count = 0; 5007 5008 spin_unlock(&adapter->fdir_perfect_lock); 5009 } 5010 5011 void ixgbe_down(struct ixgbe_adapter *adapter) 5012 { 5013 struct net_device *netdev = adapter->netdev; 5014 struct ixgbe_hw *hw = &adapter->hw; 5015 struct net_device *upper; 5016 struct list_head *iter; 5017 u32 rxctrl; 5018 int i; 5019 5020 /* signal that we are down to the interrupt handler */ 5021 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 5022 return; /* do nothing if already down */ 5023 5024 /* disable receives */ 5025 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 5026 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); 5027 5028 /* disable all enabled rx queues */ 5029 for (i = 0; i < adapter->num_rx_queues; i++) 5030 /* this call also flushes the previous write */ 5031 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); 5032 5033 usleep_range(10000, 20000); 5034 5035 netif_tx_stop_all_queues(netdev); 5036 5037 /* call carrier off first to avoid false dev_watchdog timeouts */ 5038 netif_carrier_off(netdev); 5039 netif_tx_disable(netdev); 5040 5041 /* disable any upper devices */ 5042 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { 5043 if (netif_is_macvlan(upper)) { 5044 struct macvlan_dev *vlan = netdev_priv(upper); 5045 5046 if (vlan->fwd_priv) { 5047 netif_tx_stop_all_queues(upper); 5048 netif_carrier_off(upper); 5049 netif_tx_disable(upper); 5050 } 5051 } 5052 } 5053 5054 ixgbe_irq_disable(adapter); 5055 5056 ixgbe_napi_disable_all(adapter); 5057 5058 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT | 5059 IXGBE_FLAG2_RESET_REQUESTED); 5060 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 5061 5062 del_timer_sync(&adapter->service_timer); 5063 5064 if (adapter->num_vfs) { 5065 /* Clear EITR Select mapping */ 5066 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 5067 5068 /* Mark all the VFs as inactive */ 5069 for (i = 0 ; i < adapter->num_vfs; i++) 5070 adapter->vfinfo[i].clear_to_send = false; 5071 5072 /* ping all the active vfs to let them know we are going down */ 5073 ixgbe_ping_all_vfs(adapter); 5074 5075 /* Disable all VFTE/VFRE TX/RX */ 5076 ixgbe_disable_tx_rx(adapter); 5077 } 5078 5079 /* disable transmits in the hardware now that interrupts are off */ 5080 for (i = 0; i < adapter->num_tx_queues; i++) { 5081 u8 reg_idx = adapter->tx_ring[i]->reg_idx; 5082 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5083 } 5084 5085 /* Disable the Tx DMA engine on 82599 and later MAC */ 5086 switch (hw->mac.type) { 5087 case ixgbe_mac_82599EB: 5088 case ixgbe_mac_X540: 5089 case ixgbe_mac_X550: 5090 case ixgbe_mac_X550EM_x: 5091 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5092 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5093 ~IXGBE_DMATXCTL_TE)); 5094 break; 5095 default: 5096 break; 5097 } 5098 5099 if (!pci_channel_offline(adapter->pdev)) 5100 ixgbe_reset(adapter); 5101 5102 /* power down the optics for 82599 SFP+ fiber */ 5103 if (hw->mac.ops.disable_tx_laser) 5104 hw->mac.ops.disable_tx_laser(hw); 5105 5106 ixgbe_clean_all_tx_rings(adapter); 5107 ixgbe_clean_all_rx_rings(adapter); 5108 5109 #ifdef CONFIG_IXGBE_DCA 5110 /* since we reset the hardware DCA settings were cleared */ 5111 ixgbe_setup_dca(adapter); 5112 #endif 5113 } 5114 5115 /** 5116 * ixgbe_tx_timeout - Respond to a Tx Hang 5117 * @netdev: network interface device structure 5118 **/ 5119 static void ixgbe_tx_timeout(struct net_device *netdev) 5120 { 5121 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5122 5123 /* Do the reset outside of interrupt context */ 5124 ixgbe_tx_timeout_reset(adapter); 5125 } 5126 5127 /** 5128 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 5129 * @adapter: board private structure to initialize 5130 * 5131 * ixgbe_sw_init initializes the Adapter private data structure. 5132 * Fields are initialized based on PCI device information and 5133 * OS network device settings (MTU size). 5134 **/ 5135 static int ixgbe_sw_init(struct ixgbe_adapter *adapter) 5136 { 5137 struct ixgbe_hw *hw = &adapter->hw; 5138 struct pci_dev *pdev = adapter->pdev; 5139 unsigned int rss, fdir; 5140 u32 fwsm; 5141 #ifdef CONFIG_IXGBE_DCB 5142 int j; 5143 struct tc_configuration *tc; 5144 #endif 5145 5146 /* PCI config space info */ 5147 5148 hw->vendor_id = pdev->vendor; 5149 hw->device_id = pdev->device; 5150 hw->revision_id = pdev->revision; 5151 hw->subsystem_vendor_id = pdev->subsystem_vendor; 5152 hw->subsystem_device_id = pdev->subsystem_device; 5153 5154 /* Set common capability flags and settings */ 5155 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 5156 adapter->ring_feature[RING_F_RSS].limit = rss; 5157 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 5158 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 5159 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 5160 adapter->atr_sample_rate = 20; 5161 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 5162 adapter->ring_feature[RING_F_FDIR].limit = fdir; 5163 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 5164 #ifdef CONFIG_IXGBE_DCA 5165 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 5166 #endif 5167 #ifdef IXGBE_FCOE 5168 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 5169 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 5170 #ifdef CONFIG_IXGBE_DCB 5171 /* Default traffic class to use for FCoE */ 5172 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 5173 #endif /* CONFIG_IXGBE_DCB */ 5174 #endif /* IXGBE_FCOE */ 5175 5176 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) * 5177 hw->mac.num_rar_entries, 5178 GFP_ATOMIC); 5179 5180 /* Set MAC specific capability flags and exceptions */ 5181 switch (hw->mac.type) { 5182 case ixgbe_mac_82598EB: 5183 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 5184 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 5185 5186 if (hw->device_id == IXGBE_DEV_ID_82598AT) 5187 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 5188 5189 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 5190 adapter->ring_feature[RING_F_FDIR].limit = 0; 5191 adapter->atr_sample_rate = 0; 5192 adapter->fdir_pballoc = 0; 5193 #ifdef IXGBE_FCOE 5194 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 5195 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 5196 #ifdef CONFIG_IXGBE_DCB 5197 adapter->fcoe.up = 0; 5198 #endif /* IXGBE_DCB */ 5199 #endif /* IXGBE_FCOE */ 5200 break; 5201 case ixgbe_mac_82599EB: 5202 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 5203 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 5204 break; 5205 case ixgbe_mac_X540: 5206 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM); 5207 if (fwsm & IXGBE_FWSM_TS_ENABLED) 5208 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 5209 break; 5210 case ixgbe_mac_X550EM_x: 5211 case ixgbe_mac_X550: 5212 #ifdef CONFIG_IXGBE_DCA 5213 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 5214 #endif 5215 break; 5216 default: 5217 break; 5218 } 5219 5220 #ifdef IXGBE_FCOE 5221 /* FCoE support exists, always init the FCoE lock */ 5222 spin_lock_init(&adapter->fcoe.lock); 5223 5224 #endif 5225 /* n-tuple support exists, always init our spinlock */ 5226 spin_lock_init(&adapter->fdir_perfect_lock); 5227 5228 #ifdef CONFIG_IXGBE_DCB 5229 switch (hw->mac.type) { 5230 case ixgbe_mac_X540: 5231 case ixgbe_mac_X550: 5232 case ixgbe_mac_X550EM_x: 5233 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 5234 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 5235 break; 5236 default: 5237 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 5238 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 5239 break; 5240 } 5241 5242 /* Configure DCB traffic classes */ 5243 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 5244 tc = &adapter->dcb_cfg.tc_config[j]; 5245 tc->path[DCB_TX_CONFIG].bwg_id = 0; 5246 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 5247 tc->path[DCB_RX_CONFIG].bwg_id = 0; 5248 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 5249 tc->dcb_pfc = pfc_disabled; 5250 } 5251 5252 /* Initialize default user to priority mapping, UPx->TC0 */ 5253 tc = &adapter->dcb_cfg.tc_config[0]; 5254 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 5255 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 5256 5257 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 5258 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 5259 adapter->dcb_cfg.pfc_mode_enable = false; 5260 adapter->dcb_set_bitmap = 0x00; 5261 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 5262 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 5263 sizeof(adapter->temp_dcb_cfg)); 5264 5265 #endif 5266 5267 /* default flow control settings */ 5268 hw->fc.requested_mode = ixgbe_fc_full; 5269 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 5270 ixgbe_pbthresh_setup(adapter); 5271 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 5272 hw->fc.send_xon = true; 5273 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 5274 5275 #ifdef CONFIG_PCI_IOV 5276 if (max_vfs > 0) 5277 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 5278 5279 /* assign number of SR-IOV VFs */ 5280 if (hw->mac.type != ixgbe_mac_82598EB) { 5281 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 5282 adapter->num_vfs = 0; 5283 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 5284 } else { 5285 adapter->num_vfs = max_vfs; 5286 } 5287 } 5288 #endif /* CONFIG_PCI_IOV */ 5289 5290 /* enable itr by default in dynamic mode */ 5291 adapter->rx_itr_setting = 1; 5292 adapter->tx_itr_setting = 1; 5293 5294 /* set default ring sizes */ 5295 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 5296 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 5297 5298 /* set default work limits */ 5299 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 5300 5301 /* initialize eeprom parameters */ 5302 if (ixgbe_init_eeprom_params_generic(hw)) { 5303 e_dev_err("EEPROM initialization failed\n"); 5304 return -EIO; 5305 } 5306 5307 /* PF holds first pool slot */ 5308 set_bit(0, &adapter->fwd_bitmask); 5309 set_bit(__IXGBE_DOWN, &adapter->state); 5310 5311 return 0; 5312 } 5313 5314 /** 5315 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 5316 * @tx_ring: tx descriptor ring (for a specific queue) to setup 5317 * 5318 * Return 0 on success, negative on failure 5319 **/ 5320 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 5321 { 5322 struct device *dev = tx_ring->dev; 5323 int orig_node = dev_to_node(dev); 5324 int ring_node = -1; 5325 int size; 5326 5327 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 5328 5329 if (tx_ring->q_vector) 5330 ring_node = tx_ring->q_vector->numa_node; 5331 5332 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node); 5333 if (!tx_ring->tx_buffer_info) 5334 tx_ring->tx_buffer_info = vzalloc(size); 5335 if (!tx_ring->tx_buffer_info) 5336 goto err; 5337 5338 u64_stats_init(&tx_ring->syncp); 5339 5340 /* round up to nearest 4K */ 5341 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 5342 tx_ring->size = ALIGN(tx_ring->size, 4096); 5343 5344 set_dev_node(dev, ring_node); 5345 tx_ring->desc = dma_alloc_coherent(dev, 5346 tx_ring->size, 5347 &tx_ring->dma, 5348 GFP_KERNEL); 5349 set_dev_node(dev, orig_node); 5350 if (!tx_ring->desc) 5351 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 5352 &tx_ring->dma, GFP_KERNEL); 5353 if (!tx_ring->desc) 5354 goto err; 5355 5356 tx_ring->next_to_use = 0; 5357 tx_ring->next_to_clean = 0; 5358 return 0; 5359 5360 err: 5361 vfree(tx_ring->tx_buffer_info); 5362 tx_ring->tx_buffer_info = NULL; 5363 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 5364 return -ENOMEM; 5365 } 5366 5367 /** 5368 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 5369 * @adapter: board private structure 5370 * 5371 * If this function returns with an error, then it's possible one or 5372 * more of the rings is populated (while the rest are not). It is the 5373 * callers duty to clean those orphaned rings. 5374 * 5375 * Return 0 on success, negative on failure 5376 **/ 5377 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 5378 { 5379 int i, err = 0; 5380 5381 for (i = 0; i < adapter->num_tx_queues; i++) { 5382 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 5383 if (!err) 5384 continue; 5385 5386 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 5387 goto err_setup_tx; 5388 } 5389 5390 return 0; 5391 err_setup_tx: 5392 /* rewind the index freeing the rings as we go */ 5393 while (i--) 5394 ixgbe_free_tx_resources(adapter->tx_ring[i]); 5395 return err; 5396 } 5397 5398 /** 5399 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 5400 * @rx_ring: rx descriptor ring (for a specific queue) to setup 5401 * 5402 * Returns 0 on success, negative on failure 5403 **/ 5404 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring) 5405 { 5406 struct device *dev = rx_ring->dev; 5407 int orig_node = dev_to_node(dev); 5408 int ring_node = -1; 5409 int size; 5410 5411 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 5412 5413 if (rx_ring->q_vector) 5414 ring_node = rx_ring->q_vector->numa_node; 5415 5416 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node); 5417 if (!rx_ring->rx_buffer_info) 5418 rx_ring->rx_buffer_info = vzalloc(size); 5419 if (!rx_ring->rx_buffer_info) 5420 goto err; 5421 5422 u64_stats_init(&rx_ring->syncp); 5423 5424 /* Round up to nearest 4K */ 5425 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 5426 rx_ring->size = ALIGN(rx_ring->size, 4096); 5427 5428 set_dev_node(dev, ring_node); 5429 rx_ring->desc = dma_alloc_coherent(dev, 5430 rx_ring->size, 5431 &rx_ring->dma, 5432 GFP_KERNEL); 5433 set_dev_node(dev, orig_node); 5434 if (!rx_ring->desc) 5435 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 5436 &rx_ring->dma, GFP_KERNEL); 5437 if (!rx_ring->desc) 5438 goto err; 5439 5440 rx_ring->next_to_clean = 0; 5441 rx_ring->next_to_use = 0; 5442 5443 return 0; 5444 err: 5445 vfree(rx_ring->rx_buffer_info); 5446 rx_ring->rx_buffer_info = NULL; 5447 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 5448 return -ENOMEM; 5449 } 5450 5451 /** 5452 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 5453 * @adapter: board private structure 5454 * 5455 * If this function returns with an error, then it's possible one or 5456 * more of the rings is populated (while the rest are not). It is the 5457 * callers duty to clean those orphaned rings. 5458 * 5459 * Return 0 on success, negative on failure 5460 **/ 5461 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 5462 { 5463 int i, err = 0; 5464 5465 for (i = 0; i < adapter->num_rx_queues; i++) { 5466 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]); 5467 if (!err) 5468 continue; 5469 5470 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 5471 goto err_setup_rx; 5472 } 5473 5474 #ifdef IXGBE_FCOE 5475 err = ixgbe_setup_fcoe_ddp_resources(adapter); 5476 if (!err) 5477 #endif 5478 return 0; 5479 err_setup_rx: 5480 /* rewind the index freeing the rings as we go */ 5481 while (i--) 5482 ixgbe_free_rx_resources(adapter->rx_ring[i]); 5483 return err; 5484 } 5485 5486 /** 5487 * ixgbe_free_tx_resources - Free Tx Resources per Queue 5488 * @tx_ring: Tx descriptor ring for a specific queue 5489 * 5490 * Free all transmit software resources 5491 **/ 5492 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 5493 { 5494 ixgbe_clean_tx_ring(tx_ring); 5495 5496 vfree(tx_ring->tx_buffer_info); 5497 tx_ring->tx_buffer_info = NULL; 5498 5499 /* if not set, then don't free */ 5500 if (!tx_ring->desc) 5501 return; 5502 5503 dma_free_coherent(tx_ring->dev, tx_ring->size, 5504 tx_ring->desc, tx_ring->dma); 5505 5506 tx_ring->desc = NULL; 5507 } 5508 5509 /** 5510 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 5511 * @adapter: board private structure 5512 * 5513 * Free all transmit software resources 5514 **/ 5515 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 5516 { 5517 int i; 5518 5519 for (i = 0; i < adapter->num_tx_queues; i++) 5520 if (adapter->tx_ring[i]->desc) 5521 ixgbe_free_tx_resources(adapter->tx_ring[i]); 5522 } 5523 5524 /** 5525 * ixgbe_free_rx_resources - Free Rx Resources 5526 * @rx_ring: ring to clean the resources from 5527 * 5528 * Free all receive software resources 5529 **/ 5530 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 5531 { 5532 ixgbe_clean_rx_ring(rx_ring); 5533 5534 vfree(rx_ring->rx_buffer_info); 5535 rx_ring->rx_buffer_info = NULL; 5536 5537 /* if not set, then don't free */ 5538 if (!rx_ring->desc) 5539 return; 5540 5541 dma_free_coherent(rx_ring->dev, rx_ring->size, 5542 rx_ring->desc, rx_ring->dma); 5543 5544 rx_ring->desc = NULL; 5545 } 5546 5547 /** 5548 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 5549 * @adapter: board private structure 5550 * 5551 * Free all receive software resources 5552 **/ 5553 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 5554 { 5555 int i; 5556 5557 #ifdef IXGBE_FCOE 5558 ixgbe_free_fcoe_ddp_resources(adapter); 5559 5560 #endif 5561 for (i = 0; i < adapter->num_rx_queues; i++) 5562 if (adapter->rx_ring[i]->desc) 5563 ixgbe_free_rx_resources(adapter->rx_ring[i]); 5564 } 5565 5566 /** 5567 * ixgbe_change_mtu - Change the Maximum Transfer Unit 5568 * @netdev: network interface device structure 5569 * @new_mtu: new value for maximum frame size 5570 * 5571 * Returns 0 on success, negative on failure 5572 **/ 5573 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 5574 { 5575 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5576 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; 5577 5578 /* MTU < 68 is an error and causes problems on some kernels */ 5579 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) 5580 return -EINVAL; 5581 5582 /* 5583 * For 82599EB we cannot allow legacy VFs to enable their receive 5584 * paths when MTU greater than 1500 is configured. So display a 5585 * warning that legacy VFs will be disabled. 5586 */ 5587 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 5588 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 5589 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 5590 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 5591 5592 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); 5593 5594 /* must set new MTU before calling down or up */ 5595 netdev->mtu = new_mtu; 5596 5597 if (netif_running(netdev)) 5598 ixgbe_reinit_locked(adapter); 5599 5600 return 0; 5601 } 5602 5603 /** 5604 * ixgbe_open - Called when a network interface is made active 5605 * @netdev: network interface device structure 5606 * 5607 * Returns 0 on success, negative value on failure 5608 * 5609 * The open entry point is called when a network interface is made 5610 * active by the system (IFF_UP). At this point all resources needed 5611 * for transmit and receive operations are allocated, the interrupt 5612 * handler is registered with the OS, the watchdog timer is started, 5613 * and the stack is notified that the interface is ready. 5614 **/ 5615 static int ixgbe_open(struct net_device *netdev) 5616 { 5617 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5618 int err, queues; 5619 5620 /* disallow open during test */ 5621 if (test_bit(__IXGBE_TESTING, &adapter->state)) 5622 return -EBUSY; 5623 5624 netif_carrier_off(netdev); 5625 5626 /* allocate transmit descriptors */ 5627 err = ixgbe_setup_all_tx_resources(adapter); 5628 if (err) 5629 goto err_setup_tx; 5630 5631 /* allocate receive descriptors */ 5632 err = ixgbe_setup_all_rx_resources(adapter); 5633 if (err) 5634 goto err_setup_rx; 5635 5636 ixgbe_configure(adapter); 5637 5638 err = ixgbe_request_irq(adapter); 5639 if (err) 5640 goto err_req_irq; 5641 5642 /* Notify the stack of the actual queue counts. */ 5643 if (adapter->num_rx_pools > 1) 5644 queues = adapter->num_rx_queues_per_pool; 5645 else 5646 queues = adapter->num_tx_queues; 5647 5648 err = netif_set_real_num_tx_queues(netdev, queues); 5649 if (err) 5650 goto err_set_queues; 5651 5652 if (adapter->num_rx_pools > 1 && 5653 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES) 5654 queues = IXGBE_MAX_L2A_QUEUES; 5655 else 5656 queues = adapter->num_rx_queues; 5657 err = netif_set_real_num_rx_queues(netdev, queues); 5658 if (err) 5659 goto err_set_queues; 5660 5661 ixgbe_ptp_init(adapter); 5662 5663 ixgbe_up_complete(adapter); 5664 5665 #if IS_ENABLED(CONFIG_IXGBE_VXLAN) 5666 vxlan_get_rx_port(netdev); 5667 5668 #endif 5669 return 0; 5670 5671 err_set_queues: 5672 ixgbe_free_irq(adapter); 5673 err_req_irq: 5674 ixgbe_free_all_rx_resources(adapter); 5675 err_setup_rx: 5676 ixgbe_free_all_tx_resources(adapter); 5677 err_setup_tx: 5678 ixgbe_reset(adapter); 5679 5680 return err; 5681 } 5682 5683 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 5684 { 5685 ixgbe_ptp_suspend(adapter); 5686 5687 ixgbe_down(adapter); 5688 ixgbe_free_irq(adapter); 5689 5690 ixgbe_free_all_tx_resources(adapter); 5691 ixgbe_free_all_rx_resources(adapter); 5692 } 5693 5694 /** 5695 * ixgbe_close - Disables a network interface 5696 * @netdev: network interface device structure 5697 * 5698 * Returns 0, this is not allowed to fail 5699 * 5700 * The close entry point is called when an interface is de-activated 5701 * by the OS. The hardware is still under the drivers control, but 5702 * needs to be disabled. A global MAC reset is issued to stop the 5703 * hardware, and all transmit and receive resources are freed. 5704 **/ 5705 static int ixgbe_close(struct net_device *netdev) 5706 { 5707 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5708 5709 ixgbe_ptp_stop(adapter); 5710 5711 ixgbe_close_suspend(adapter); 5712 5713 ixgbe_fdir_filter_exit(adapter); 5714 5715 ixgbe_release_hw_control(adapter); 5716 5717 return 0; 5718 } 5719 5720 #ifdef CONFIG_PM 5721 static int ixgbe_resume(struct pci_dev *pdev) 5722 { 5723 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 5724 struct net_device *netdev = adapter->netdev; 5725 u32 err; 5726 5727 adapter->hw.hw_addr = adapter->io_addr; 5728 pci_set_power_state(pdev, PCI_D0); 5729 pci_restore_state(pdev); 5730 /* 5731 * pci_restore_state clears dev->state_saved so call 5732 * pci_save_state to restore it. 5733 */ 5734 pci_save_state(pdev); 5735 5736 err = pci_enable_device_mem(pdev); 5737 if (err) { 5738 e_dev_err("Cannot enable PCI device from suspend\n"); 5739 return err; 5740 } 5741 smp_mb__before_atomic(); 5742 clear_bit(__IXGBE_DISABLED, &adapter->state); 5743 pci_set_master(pdev); 5744 5745 pci_wake_from_d3(pdev, false); 5746 5747 ixgbe_reset(adapter); 5748 5749 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 5750 5751 rtnl_lock(); 5752 err = ixgbe_init_interrupt_scheme(adapter); 5753 if (!err && netif_running(netdev)) 5754 err = ixgbe_open(netdev); 5755 5756 rtnl_unlock(); 5757 5758 if (err) 5759 return err; 5760 5761 netif_device_attach(netdev); 5762 5763 return 0; 5764 } 5765 #endif /* CONFIG_PM */ 5766 5767 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 5768 { 5769 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 5770 struct net_device *netdev = adapter->netdev; 5771 struct ixgbe_hw *hw = &adapter->hw; 5772 u32 ctrl, fctrl; 5773 u32 wufc = adapter->wol; 5774 #ifdef CONFIG_PM 5775 int retval = 0; 5776 #endif 5777 5778 netif_device_detach(netdev); 5779 5780 rtnl_lock(); 5781 if (netif_running(netdev)) 5782 ixgbe_close_suspend(adapter); 5783 rtnl_unlock(); 5784 5785 ixgbe_clear_interrupt_scheme(adapter); 5786 5787 #ifdef CONFIG_PM 5788 retval = pci_save_state(pdev); 5789 if (retval) 5790 return retval; 5791 5792 #endif 5793 if (hw->mac.ops.stop_link_on_d3) 5794 hw->mac.ops.stop_link_on_d3(hw); 5795 5796 if (wufc) { 5797 ixgbe_set_rx_mode(netdev); 5798 5799 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 5800 if (hw->mac.ops.enable_tx_laser) 5801 hw->mac.ops.enable_tx_laser(hw); 5802 5803 /* turn on all-multi mode if wake on multicast is enabled */ 5804 if (wufc & IXGBE_WUFC_MC) { 5805 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 5806 fctrl |= IXGBE_FCTRL_MPE; 5807 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 5808 } 5809 5810 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 5811 ctrl |= IXGBE_CTRL_GIO_DIS; 5812 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 5813 5814 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 5815 } else { 5816 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 5817 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 5818 } 5819 5820 switch (hw->mac.type) { 5821 case ixgbe_mac_82598EB: 5822 pci_wake_from_d3(pdev, false); 5823 break; 5824 case ixgbe_mac_82599EB: 5825 case ixgbe_mac_X540: 5826 case ixgbe_mac_X550: 5827 case ixgbe_mac_X550EM_x: 5828 pci_wake_from_d3(pdev, !!wufc); 5829 break; 5830 default: 5831 break; 5832 } 5833 5834 *enable_wake = !!wufc; 5835 5836 ixgbe_release_hw_control(adapter); 5837 5838 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 5839 pci_disable_device(pdev); 5840 5841 return 0; 5842 } 5843 5844 #ifdef CONFIG_PM 5845 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) 5846 { 5847 int retval; 5848 bool wake; 5849 5850 retval = __ixgbe_shutdown(pdev, &wake); 5851 if (retval) 5852 return retval; 5853 5854 if (wake) { 5855 pci_prepare_to_sleep(pdev); 5856 } else { 5857 pci_wake_from_d3(pdev, false); 5858 pci_set_power_state(pdev, PCI_D3hot); 5859 } 5860 5861 return 0; 5862 } 5863 #endif /* CONFIG_PM */ 5864 5865 static void ixgbe_shutdown(struct pci_dev *pdev) 5866 { 5867 bool wake; 5868 5869 __ixgbe_shutdown(pdev, &wake); 5870 5871 if (system_state == SYSTEM_POWER_OFF) { 5872 pci_wake_from_d3(pdev, wake); 5873 pci_set_power_state(pdev, PCI_D3hot); 5874 } 5875 } 5876 5877 /** 5878 * ixgbe_update_stats - Update the board statistics counters. 5879 * @adapter: board private structure 5880 **/ 5881 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 5882 { 5883 struct net_device *netdev = adapter->netdev; 5884 struct ixgbe_hw *hw = &adapter->hw; 5885 struct ixgbe_hw_stats *hwstats = &adapter->stats; 5886 u64 total_mpc = 0; 5887 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 5888 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 5889 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 5890 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 5891 5892 if (test_bit(__IXGBE_DOWN, &adapter->state) || 5893 test_bit(__IXGBE_RESETTING, &adapter->state)) 5894 return; 5895 5896 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 5897 u64 rsc_count = 0; 5898 u64 rsc_flush = 0; 5899 for (i = 0; i < adapter->num_rx_queues; i++) { 5900 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 5901 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 5902 } 5903 adapter->rsc_total_count = rsc_count; 5904 adapter->rsc_total_flush = rsc_flush; 5905 } 5906 5907 for (i = 0; i < adapter->num_rx_queues; i++) { 5908 struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; 5909 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 5910 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 5911 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 5912 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 5913 bytes += rx_ring->stats.bytes; 5914 packets += rx_ring->stats.packets; 5915 } 5916 adapter->non_eop_descs = non_eop_descs; 5917 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 5918 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 5919 adapter->hw_csum_rx_error = hw_csum_rx_error; 5920 netdev->stats.rx_bytes = bytes; 5921 netdev->stats.rx_packets = packets; 5922 5923 bytes = 0; 5924 packets = 0; 5925 /* gather some stats to the adapter struct that are per queue */ 5926 for (i = 0; i < adapter->num_tx_queues; i++) { 5927 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 5928 restart_queue += tx_ring->tx_stats.restart_queue; 5929 tx_busy += tx_ring->tx_stats.tx_busy; 5930 bytes += tx_ring->stats.bytes; 5931 packets += tx_ring->stats.packets; 5932 } 5933 adapter->restart_queue = restart_queue; 5934 adapter->tx_busy = tx_busy; 5935 netdev->stats.tx_bytes = bytes; 5936 netdev->stats.tx_packets = packets; 5937 5938 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 5939 5940 /* 8 register reads */ 5941 for (i = 0; i < 8; i++) { 5942 /* for packet buffers not used, the register should read 0 */ 5943 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 5944 missed_rx += mpc; 5945 hwstats->mpc[i] += mpc; 5946 total_mpc += hwstats->mpc[i]; 5947 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 5948 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 5949 switch (hw->mac.type) { 5950 case ixgbe_mac_82598EB: 5951 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 5952 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 5953 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 5954 hwstats->pxonrxc[i] += 5955 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 5956 break; 5957 case ixgbe_mac_82599EB: 5958 case ixgbe_mac_X540: 5959 case ixgbe_mac_X550: 5960 case ixgbe_mac_X550EM_x: 5961 hwstats->pxonrxc[i] += 5962 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 5963 break; 5964 default: 5965 break; 5966 } 5967 } 5968 5969 /*16 register reads */ 5970 for (i = 0; i < 16; i++) { 5971 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 5972 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 5973 if ((hw->mac.type == ixgbe_mac_82599EB) || 5974 (hw->mac.type == ixgbe_mac_X540) || 5975 (hw->mac.type == ixgbe_mac_X550) || 5976 (hw->mac.type == ixgbe_mac_X550EM_x)) { 5977 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 5978 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 5979 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 5980 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 5981 } 5982 } 5983 5984 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 5985 /* work around hardware counting issue */ 5986 hwstats->gprc -= missed_rx; 5987 5988 ixgbe_update_xoff_received(adapter); 5989 5990 /* 82598 hardware only has a 32 bit counter in the high register */ 5991 switch (hw->mac.type) { 5992 case ixgbe_mac_82598EB: 5993 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 5994 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 5995 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 5996 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 5997 break; 5998 case ixgbe_mac_X540: 5999 case ixgbe_mac_X550: 6000 case ixgbe_mac_X550EM_x: 6001 /* OS2BMC stats are X540 and later */ 6002 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 6003 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 6004 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 6005 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 6006 case ixgbe_mac_82599EB: 6007 for (i = 0; i < 16; i++) 6008 adapter->hw_rx_no_dma_resources += 6009 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 6010 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 6011 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 6012 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 6013 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 6014 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 6015 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 6016 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 6017 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 6018 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 6019 #ifdef IXGBE_FCOE 6020 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 6021 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 6022 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 6023 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 6024 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 6025 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 6026 /* Add up per cpu counters for total ddp aloc fail */ 6027 if (adapter->fcoe.ddp_pool) { 6028 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 6029 struct ixgbe_fcoe_ddp_pool *ddp_pool; 6030 unsigned int cpu; 6031 u64 noddp = 0, noddp_ext_buff = 0; 6032 for_each_possible_cpu(cpu) { 6033 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 6034 noddp += ddp_pool->noddp; 6035 noddp_ext_buff += ddp_pool->noddp_ext_buff; 6036 } 6037 hwstats->fcoe_noddp = noddp; 6038 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 6039 } 6040 #endif /* IXGBE_FCOE */ 6041 break; 6042 default: 6043 break; 6044 } 6045 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 6046 hwstats->bprc += bprc; 6047 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 6048 if (hw->mac.type == ixgbe_mac_82598EB) 6049 hwstats->mprc -= bprc; 6050 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 6051 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 6052 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 6053 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 6054 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 6055 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 6056 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 6057 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 6058 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 6059 hwstats->lxontxc += lxon; 6060 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 6061 hwstats->lxofftxc += lxoff; 6062 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 6063 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 6064 /* 6065 * 82598 errata - tx of flow control packets is included in tx counters 6066 */ 6067 xon_off_tot = lxon + lxoff; 6068 hwstats->gptc -= xon_off_tot; 6069 hwstats->mptc -= xon_off_tot; 6070 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 6071 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 6072 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 6073 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 6074 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 6075 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 6076 hwstats->ptc64 -= xon_off_tot; 6077 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 6078 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 6079 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 6080 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 6081 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 6082 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 6083 6084 /* Fill out the OS statistics structure */ 6085 netdev->stats.multicast = hwstats->mprc; 6086 6087 /* Rx Errors */ 6088 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 6089 netdev->stats.rx_dropped = 0; 6090 netdev->stats.rx_length_errors = hwstats->rlec; 6091 netdev->stats.rx_crc_errors = hwstats->crcerrs; 6092 netdev->stats.rx_missed_errors = total_mpc; 6093 } 6094 6095 /** 6096 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 6097 * @adapter: pointer to the device adapter structure 6098 **/ 6099 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 6100 { 6101 struct ixgbe_hw *hw = &adapter->hw; 6102 int i; 6103 6104 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 6105 return; 6106 6107 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 6108 6109 /* if interface is down do nothing */ 6110 if (test_bit(__IXGBE_DOWN, &adapter->state)) 6111 return; 6112 6113 /* do nothing if we are not using signature filters */ 6114 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 6115 return; 6116 6117 adapter->fdir_overflow++; 6118 6119 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 6120 for (i = 0; i < adapter->num_tx_queues; i++) 6121 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 6122 &(adapter->tx_ring[i]->state)); 6123 /* re-enable flow director interrupts */ 6124 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 6125 } else { 6126 e_err(probe, "failed to finish FDIR re-initialization, " 6127 "ignored adding FDIR ATR filters\n"); 6128 } 6129 } 6130 6131 /** 6132 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 6133 * @adapter: pointer to the device adapter structure 6134 * 6135 * This function serves two purposes. First it strobes the interrupt lines 6136 * in order to make certain interrupts are occurring. Secondly it sets the 6137 * bits needed to check for TX hangs. As a result we should immediately 6138 * determine if a hang has occurred. 6139 */ 6140 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 6141 { 6142 struct ixgbe_hw *hw = &adapter->hw; 6143 u64 eics = 0; 6144 int i; 6145 6146 /* If we're down, removing or resetting, just bail */ 6147 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6148 test_bit(__IXGBE_REMOVING, &adapter->state) || 6149 test_bit(__IXGBE_RESETTING, &adapter->state)) 6150 return; 6151 6152 /* Force detection of hung controller */ 6153 if (netif_carrier_ok(adapter->netdev)) { 6154 for (i = 0; i < adapter->num_tx_queues; i++) 6155 set_check_for_tx_hang(adapter->tx_ring[i]); 6156 } 6157 6158 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 6159 /* 6160 * for legacy and MSI interrupts don't set any bits 6161 * that are enabled for EIAM, because this operation 6162 * would set *both* EIMS and EICS for any bit in EIAM 6163 */ 6164 IXGBE_WRITE_REG(hw, IXGBE_EICS, 6165 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 6166 } else { 6167 /* get one bit for every active tx/rx interrupt vector */ 6168 for (i = 0; i < adapter->num_q_vectors; i++) { 6169 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 6170 if (qv->rx.ring || qv->tx.ring) 6171 eics |= ((u64)1 << i); 6172 } 6173 } 6174 6175 /* Cause software interrupt to ensure rings are cleaned */ 6176 ixgbe_irq_rearm_queues(adapter, eics); 6177 6178 } 6179 6180 /** 6181 * ixgbe_watchdog_update_link - update the link status 6182 * @adapter: pointer to the device adapter structure 6183 * @link_speed: pointer to a u32 to store the link_speed 6184 **/ 6185 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 6186 { 6187 struct ixgbe_hw *hw = &adapter->hw; 6188 u32 link_speed = adapter->link_speed; 6189 bool link_up = adapter->link_up; 6190 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 6191 6192 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 6193 return; 6194 6195 if (hw->mac.ops.check_link) { 6196 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 6197 } else { 6198 /* always assume link is up, if no check link function */ 6199 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 6200 link_up = true; 6201 } 6202 6203 if (adapter->ixgbe_ieee_pfc) 6204 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 6205 6206 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 6207 hw->mac.ops.fc_enable(hw); 6208 ixgbe_set_rx_drop_en(adapter); 6209 } 6210 6211 if (link_up || 6212 time_after(jiffies, (adapter->link_check_timeout + 6213 IXGBE_TRY_LINK_TIMEOUT))) { 6214 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 6215 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 6216 IXGBE_WRITE_FLUSH(hw); 6217 } 6218 6219 adapter->link_up = link_up; 6220 adapter->link_speed = link_speed; 6221 } 6222 6223 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 6224 { 6225 #ifdef CONFIG_IXGBE_DCB 6226 struct net_device *netdev = adapter->netdev; 6227 struct dcb_app app = { 6228 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 6229 .protocol = 0, 6230 }; 6231 u8 up = 0; 6232 6233 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 6234 up = dcb_ieee_getapp_mask(netdev, &app); 6235 6236 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 6237 #endif 6238 } 6239 6240 /** 6241 * ixgbe_watchdog_link_is_up - update netif_carrier status and 6242 * print link up message 6243 * @adapter: pointer to the device adapter structure 6244 **/ 6245 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 6246 { 6247 struct net_device *netdev = adapter->netdev; 6248 struct ixgbe_hw *hw = &adapter->hw; 6249 struct net_device *upper; 6250 struct list_head *iter; 6251 u32 link_speed = adapter->link_speed; 6252 bool flow_rx, flow_tx; 6253 6254 /* only continue if link was previously down */ 6255 if (netif_carrier_ok(netdev)) 6256 return; 6257 6258 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 6259 6260 switch (hw->mac.type) { 6261 case ixgbe_mac_82598EB: { 6262 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6263 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 6264 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 6265 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 6266 } 6267 break; 6268 case ixgbe_mac_X540: 6269 case ixgbe_mac_X550: 6270 case ixgbe_mac_X550EM_x: 6271 case ixgbe_mac_82599EB: { 6272 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 6273 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 6274 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 6275 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 6276 } 6277 break; 6278 default: 6279 flow_tx = false; 6280 flow_rx = false; 6281 break; 6282 } 6283 6284 adapter->last_rx_ptp_check = jiffies; 6285 6286 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 6287 ixgbe_ptp_start_cyclecounter(adapter); 6288 6289 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", 6290 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? 6291 "10 Gbps" : 6292 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? 6293 "1 Gbps" : 6294 (link_speed == IXGBE_LINK_SPEED_100_FULL ? 6295 "100 Mbps" : 6296 "unknown speed"))), 6297 ((flow_rx && flow_tx) ? "RX/TX" : 6298 (flow_rx ? "RX" : 6299 (flow_tx ? "TX" : "None")))); 6300 6301 netif_carrier_on(netdev); 6302 ixgbe_check_vf_rate_limit(adapter); 6303 6304 /* enable transmits */ 6305 netif_tx_wake_all_queues(adapter->netdev); 6306 6307 /* enable any upper devices */ 6308 rtnl_lock(); 6309 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { 6310 if (netif_is_macvlan(upper)) { 6311 struct macvlan_dev *vlan = netdev_priv(upper); 6312 6313 if (vlan->fwd_priv) 6314 netif_tx_wake_all_queues(upper); 6315 } 6316 } 6317 rtnl_unlock(); 6318 6319 /* update the default user priority for VFs */ 6320 ixgbe_update_default_up(adapter); 6321 6322 /* ping all the active vfs to let them know link has changed */ 6323 ixgbe_ping_all_vfs(adapter); 6324 } 6325 6326 /** 6327 * ixgbe_watchdog_link_is_down - update netif_carrier status and 6328 * print link down message 6329 * @adapter: pointer to the adapter structure 6330 **/ 6331 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 6332 { 6333 struct net_device *netdev = adapter->netdev; 6334 struct ixgbe_hw *hw = &adapter->hw; 6335 6336 adapter->link_up = false; 6337 adapter->link_speed = 0; 6338 6339 /* only continue if link was up previously */ 6340 if (!netif_carrier_ok(netdev)) 6341 return; 6342 6343 /* poll for SFP+ cable when link is down */ 6344 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 6345 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 6346 6347 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 6348 ixgbe_ptp_start_cyclecounter(adapter); 6349 6350 e_info(drv, "NIC Link is Down\n"); 6351 netif_carrier_off(netdev); 6352 6353 /* ping all the active vfs to let them know link has changed */ 6354 ixgbe_ping_all_vfs(adapter); 6355 } 6356 6357 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 6358 { 6359 int i; 6360 6361 for (i = 0; i < adapter->num_tx_queues; i++) { 6362 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 6363 6364 if (tx_ring->next_to_use != tx_ring->next_to_clean) 6365 return true; 6366 } 6367 6368 return false; 6369 } 6370 6371 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 6372 { 6373 struct ixgbe_hw *hw = &adapter->hw; 6374 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 6375 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 6376 6377 int i, j; 6378 6379 if (!adapter->num_vfs) 6380 return false; 6381 6382 /* resetting the PF is only needed for MAC before X550 */ 6383 if (hw->mac.type >= ixgbe_mac_X550) 6384 return false; 6385 6386 for (i = 0; i < adapter->num_vfs; i++) { 6387 for (j = 0; j < q_per_pool; j++) { 6388 u32 h, t; 6389 6390 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 6391 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 6392 6393 if (h != t) 6394 return true; 6395 } 6396 } 6397 6398 return false; 6399 } 6400 6401 /** 6402 * ixgbe_watchdog_flush_tx - flush queues on link down 6403 * @adapter: pointer to the device adapter structure 6404 **/ 6405 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 6406 { 6407 if (!netif_carrier_ok(adapter->netdev)) { 6408 if (ixgbe_ring_tx_pending(adapter) || 6409 ixgbe_vf_tx_pending(adapter)) { 6410 /* We've lost link, so the controller stops DMA, 6411 * but we've got queued Tx work that's never going 6412 * to get done, so reset controller to flush Tx. 6413 * (Do the reset outside of interrupt context). 6414 */ 6415 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 6416 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 6417 } 6418 } 6419 } 6420 6421 #ifdef CONFIG_PCI_IOV 6422 static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter, 6423 struct pci_dev *vfdev) 6424 { 6425 if (!pci_wait_for_pending_transaction(vfdev)) 6426 e_dev_warn("Issuing VFLR with pending transactions\n"); 6427 6428 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev)); 6429 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 6430 6431 msleep(100); 6432 } 6433 6434 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 6435 { 6436 struct ixgbe_hw *hw = &adapter->hw; 6437 struct pci_dev *pdev = adapter->pdev; 6438 struct pci_dev *vfdev; 6439 u32 gpc; 6440 int pos; 6441 unsigned short vf_id; 6442 6443 if (!(netif_carrier_ok(adapter->netdev))) 6444 return; 6445 6446 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 6447 if (gpc) /* If incrementing then no need for the check below */ 6448 return; 6449 /* Check to see if a bad DMA write target from an errant or 6450 * malicious VF has caused a PCIe error. If so then we can 6451 * issue a VFLR to the offending VF(s) and then resume without 6452 * requesting a full slot reset. 6453 */ 6454 6455 if (!pdev) 6456 return; 6457 6458 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); 6459 if (!pos) 6460 return; 6461 6462 /* get the device ID for the VF */ 6463 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &vf_id); 6464 6465 /* check status reg for all VFs owned by this PF */ 6466 vfdev = pci_get_device(pdev->vendor, vf_id, NULL); 6467 while (vfdev) { 6468 if (vfdev->is_virtfn && (vfdev->physfn == pdev)) { 6469 u16 status_reg; 6470 6471 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 6472 if (status_reg & PCI_STATUS_REC_MASTER_ABORT) 6473 /* issue VFLR */ 6474 ixgbe_issue_vf_flr(adapter, vfdev); 6475 } 6476 6477 vfdev = pci_get_device(pdev->vendor, vf_id, vfdev); 6478 } 6479 } 6480 6481 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 6482 { 6483 u32 ssvpc; 6484 6485 /* Do not perform spoof check for 82598 or if not in IOV mode */ 6486 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 6487 adapter->num_vfs == 0) 6488 return; 6489 6490 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 6491 6492 /* 6493 * ssvpc register is cleared on read, if zero then no 6494 * spoofed packets in the last interval. 6495 */ 6496 if (!ssvpc) 6497 return; 6498 6499 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 6500 } 6501 #else 6502 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 6503 { 6504 } 6505 6506 static void 6507 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 6508 { 6509 } 6510 #endif /* CONFIG_PCI_IOV */ 6511 6512 6513 /** 6514 * ixgbe_watchdog_subtask - check and bring link up 6515 * @adapter: pointer to the device adapter structure 6516 **/ 6517 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 6518 { 6519 /* if interface is down, removing or resetting, do nothing */ 6520 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6521 test_bit(__IXGBE_REMOVING, &adapter->state) || 6522 test_bit(__IXGBE_RESETTING, &adapter->state)) 6523 return; 6524 6525 ixgbe_watchdog_update_link(adapter); 6526 6527 if (adapter->link_up) 6528 ixgbe_watchdog_link_is_up(adapter); 6529 else 6530 ixgbe_watchdog_link_is_down(adapter); 6531 6532 ixgbe_check_for_bad_vf(adapter); 6533 ixgbe_spoof_check(adapter); 6534 ixgbe_update_stats(adapter); 6535 6536 ixgbe_watchdog_flush_tx(adapter); 6537 } 6538 6539 /** 6540 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 6541 * @adapter: the ixgbe adapter structure 6542 **/ 6543 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 6544 { 6545 struct ixgbe_hw *hw = &adapter->hw; 6546 s32 err; 6547 6548 /* not searching for SFP so there is nothing to do here */ 6549 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 6550 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 6551 return; 6552 6553 /* someone else is in init, wait until next service event */ 6554 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 6555 return; 6556 6557 err = hw->phy.ops.identify_sfp(hw); 6558 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 6559 goto sfp_out; 6560 6561 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 6562 /* If no cable is present, then we need to reset 6563 * the next time we find a good cable. */ 6564 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 6565 } 6566 6567 /* exit on error */ 6568 if (err) 6569 goto sfp_out; 6570 6571 /* exit if reset not needed */ 6572 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 6573 goto sfp_out; 6574 6575 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 6576 6577 /* 6578 * A module may be identified correctly, but the EEPROM may not have 6579 * support for that module. setup_sfp() will fail in that case, so 6580 * we should not allow that module to load. 6581 */ 6582 if (hw->mac.type == ixgbe_mac_82598EB) 6583 err = hw->phy.ops.reset(hw); 6584 else 6585 err = hw->mac.ops.setup_sfp(hw); 6586 6587 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 6588 goto sfp_out; 6589 6590 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 6591 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 6592 6593 sfp_out: 6594 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 6595 6596 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && 6597 (adapter->netdev->reg_state == NETREG_REGISTERED)) { 6598 e_dev_err("failed to initialize because an unsupported " 6599 "SFP+ module type was detected.\n"); 6600 e_dev_err("Reload the driver after installing a " 6601 "supported module.\n"); 6602 unregister_netdev(adapter->netdev); 6603 } 6604 } 6605 6606 /** 6607 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 6608 * @adapter: the ixgbe adapter structure 6609 **/ 6610 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 6611 { 6612 struct ixgbe_hw *hw = &adapter->hw; 6613 u32 speed; 6614 bool autoneg = false; 6615 6616 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 6617 return; 6618 6619 /* someone else is in init, wait until next service event */ 6620 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 6621 return; 6622 6623 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 6624 6625 speed = hw->phy.autoneg_advertised; 6626 if ((!speed) && (hw->mac.ops.get_link_capabilities)) { 6627 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg); 6628 6629 /* setup the highest link when no autoneg */ 6630 if (!autoneg) { 6631 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 6632 speed = IXGBE_LINK_SPEED_10GB_FULL; 6633 } 6634 } 6635 6636 if (hw->mac.ops.setup_link) 6637 hw->mac.ops.setup_link(hw, speed, true); 6638 6639 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 6640 adapter->link_check_timeout = jiffies; 6641 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 6642 } 6643 6644 /** 6645 * ixgbe_service_timer - Timer Call-back 6646 * @data: pointer to adapter cast into an unsigned long 6647 **/ 6648 static void ixgbe_service_timer(unsigned long data) 6649 { 6650 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; 6651 unsigned long next_event_offset; 6652 6653 /* poll faster when waiting for link */ 6654 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 6655 next_event_offset = HZ / 10; 6656 else 6657 next_event_offset = HZ * 2; 6658 6659 /* Reset the timer */ 6660 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 6661 6662 ixgbe_service_event_schedule(adapter); 6663 } 6664 6665 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 6666 { 6667 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED)) 6668 return; 6669 6670 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED; 6671 6672 /* If we're already down, removing or resetting, just bail */ 6673 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6674 test_bit(__IXGBE_REMOVING, &adapter->state) || 6675 test_bit(__IXGBE_RESETTING, &adapter->state)) 6676 return; 6677 6678 ixgbe_dump(adapter); 6679 netdev_err(adapter->netdev, "Reset adapter\n"); 6680 adapter->tx_timeout_count++; 6681 6682 rtnl_lock(); 6683 ixgbe_reinit_locked(adapter); 6684 rtnl_unlock(); 6685 } 6686 6687 /** 6688 * ixgbe_service_task - manages and runs subtasks 6689 * @work: pointer to work_struct containing our data 6690 **/ 6691 static void ixgbe_service_task(struct work_struct *work) 6692 { 6693 struct ixgbe_adapter *adapter = container_of(work, 6694 struct ixgbe_adapter, 6695 service_task); 6696 if (ixgbe_removed(adapter->hw.hw_addr)) { 6697 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 6698 rtnl_lock(); 6699 ixgbe_down(adapter); 6700 rtnl_unlock(); 6701 } 6702 ixgbe_service_event_complete(adapter); 6703 return; 6704 } 6705 ixgbe_reset_subtask(adapter); 6706 ixgbe_sfp_detection_subtask(adapter); 6707 ixgbe_sfp_link_config_subtask(adapter); 6708 ixgbe_check_overtemp_subtask(adapter); 6709 ixgbe_watchdog_subtask(adapter); 6710 ixgbe_fdir_reinit_subtask(adapter); 6711 ixgbe_check_hang_subtask(adapter); 6712 6713 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 6714 ixgbe_ptp_overflow_check(adapter); 6715 ixgbe_ptp_rx_hang(adapter); 6716 } 6717 6718 ixgbe_service_event_complete(adapter); 6719 } 6720 6721 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 6722 struct ixgbe_tx_buffer *first, 6723 u8 *hdr_len) 6724 { 6725 struct sk_buff *skb = first->skb; 6726 u32 vlan_macip_lens, type_tucmd; 6727 u32 mss_l4len_idx, l4len; 6728 int err; 6729 6730 if (skb->ip_summed != CHECKSUM_PARTIAL) 6731 return 0; 6732 6733 if (!skb_is_gso(skb)) 6734 return 0; 6735 6736 err = skb_cow_head(skb, 0); 6737 if (err < 0) 6738 return err; 6739 6740 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 6741 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 6742 6743 if (first->protocol == htons(ETH_P_IP)) { 6744 struct iphdr *iph = ip_hdr(skb); 6745 iph->tot_len = 0; 6746 iph->check = 0; 6747 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 6748 iph->daddr, 0, 6749 IPPROTO_TCP, 6750 0); 6751 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 6752 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 6753 IXGBE_TX_FLAGS_CSUM | 6754 IXGBE_TX_FLAGS_IPV4; 6755 } else if (skb_is_gso_v6(skb)) { 6756 ipv6_hdr(skb)->payload_len = 0; 6757 tcp_hdr(skb)->check = 6758 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 6759 &ipv6_hdr(skb)->daddr, 6760 0, IPPROTO_TCP, 0); 6761 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 6762 IXGBE_TX_FLAGS_CSUM; 6763 } 6764 6765 /* compute header lengths */ 6766 l4len = tcp_hdrlen(skb); 6767 *hdr_len = skb_transport_offset(skb) + l4len; 6768 6769 /* update gso size and bytecount with header size */ 6770 first->gso_segs = skb_shinfo(skb)->gso_segs; 6771 first->bytecount += (first->gso_segs - 1) * *hdr_len; 6772 6773 /* mss_l4len_id: use 0 as index for TSO */ 6774 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT; 6775 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 6776 6777 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 6778 vlan_macip_lens = skb_network_header_len(skb); 6779 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 6780 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 6781 6782 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 6783 mss_l4len_idx); 6784 6785 return 1; 6786 } 6787 6788 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 6789 struct ixgbe_tx_buffer *first) 6790 { 6791 struct sk_buff *skb = first->skb; 6792 u32 vlan_macip_lens = 0; 6793 u32 mss_l4len_idx = 0; 6794 u32 type_tucmd = 0; 6795 6796 if (skb->ip_summed != CHECKSUM_PARTIAL) { 6797 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) && 6798 !(first->tx_flags & IXGBE_TX_FLAGS_CC)) 6799 return; 6800 } else { 6801 u8 l4_hdr = 0; 6802 switch (first->protocol) { 6803 case htons(ETH_P_IP): 6804 vlan_macip_lens |= skb_network_header_len(skb); 6805 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 6806 l4_hdr = ip_hdr(skb)->protocol; 6807 break; 6808 case htons(ETH_P_IPV6): 6809 vlan_macip_lens |= skb_network_header_len(skb); 6810 l4_hdr = ipv6_hdr(skb)->nexthdr; 6811 break; 6812 default: 6813 if (unlikely(net_ratelimit())) { 6814 dev_warn(tx_ring->dev, 6815 "partial checksum but proto=%x!\n", 6816 first->protocol); 6817 } 6818 break; 6819 } 6820 6821 switch (l4_hdr) { 6822 case IPPROTO_TCP: 6823 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP; 6824 mss_l4len_idx = tcp_hdrlen(skb) << 6825 IXGBE_ADVTXD_L4LEN_SHIFT; 6826 break; 6827 case IPPROTO_SCTP: 6828 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; 6829 mss_l4len_idx = sizeof(struct sctphdr) << 6830 IXGBE_ADVTXD_L4LEN_SHIFT; 6831 break; 6832 case IPPROTO_UDP: 6833 mss_l4len_idx = sizeof(struct udphdr) << 6834 IXGBE_ADVTXD_L4LEN_SHIFT; 6835 break; 6836 default: 6837 if (unlikely(net_ratelimit())) { 6838 dev_warn(tx_ring->dev, 6839 "partial checksum but l4 proto=%x!\n", 6840 l4_hdr); 6841 } 6842 break; 6843 } 6844 6845 /* update TX checksum flag */ 6846 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 6847 } 6848 6849 /* vlan_macip_lens: MACLEN, VLAN tag */ 6850 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 6851 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 6852 6853 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, 6854 type_tucmd, mss_l4len_idx); 6855 } 6856 6857 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 6858 ((_flag <= _result) ? \ 6859 ((u32)(_input & _flag) * (_result / _flag)) : \ 6860 ((u32)(_input & _flag) / (_flag / _result))) 6861 6862 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6863 { 6864 /* set type for advanced descriptor with frame checksum insertion */ 6865 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 6866 IXGBE_ADVTXD_DCMD_DEXT | 6867 IXGBE_ADVTXD_DCMD_IFCS; 6868 6869 /* set HW vlan bit if vlan is present */ 6870 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 6871 IXGBE_ADVTXD_DCMD_VLE); 6872 6873 /* set segmentation enable bits for TSO/FSO */ 6874 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 6875 IXGBE_ADVTXD_DCMD_TSE); 6876 6877 /* set timestamp bit if present */ 6878 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 6879 IXGBE_ADVTXD_MAC_TSTAMP); 6880 6881 /* insert frame checksum */ 6882 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 6883 6884 return cmd_type; 6885 } 6886 6887 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 6888 u32 tx_flags, unsigned int paylen) 6889 { 6890 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 6891 6892 /* enable L4 checksum for TSO and TX checksum offload */ 6893 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 6894 IXGBE_TX_FLAGS_CSUM, 6895 IXGBE_ADVTXD_POPTS_TXSM); 6896 6897 /* enble IPv4 checksum for TSO */ 6898 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 6899 IXGBE_TX_FLAGS_IPV4, 6900 IXGBE_ADVTXD_POPTS_IXSM); 6901 6902 /* 6903 * Check Context must be set if Tx switch is enabled, which it 6904 * always is for case where virtual functions are running 6905 */ 6906 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 6907 IXGBE_TX_FLAGS_CC, 6908 IXGBE_ADVTXD_CC); 6909 6910 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6911 } 6912 6913 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 6914 { 6915 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 6916 6917 /* Herbert's original patch had: 6918 * smp_mb__after_netif_stop_queue(); 6919 * but since that doesn't exist yet, just open code it. 6920 */ 6921 smp_mb(); 6922 6923 /* We need to check again in a case another CPU has just 6924 * made room available. 6925 */ 6926 if (likely(ixgbe_desc_unused(tx_ring) < size)) 6927 return -EBUSY; 6928 6929 /* A reprieve! - use start_queue because it doesn't call schedule */ 6930 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 6931 ++tx_ring->tx_stats.restart_queue; 6932 return 0; 6933 } 6934 6935 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 6936 { 6937 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 6938 return 0; 6939 6940 return __ixgbe_maybe_stop_tx(tx_ring, size); 6941 } 6942 6943 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ 6944 IXGBE_TXD_CMD_RS) 6945 6946 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring, 6947 struct ixgbe_tx_buffer *first, 6948 const u8 hdr_len) 6949 { 6950 struct sk_buff *skb = first->skb; 6951 struct ixgbe_tx_buffer *tx_buffer; 6952 union ixgbe_adv_tx_desc *tx_desc; 6953 struct skb_frag_struct *frag; 6954 dma_addr_t dma; 6955 unsigned int data_len, size; 6956 u32 tx_flags = first->tx_flags; 6957 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 6958 u16 i = tx_ring->next_to_use; 6959 6960 tx_desc = IXGBE_TX_DESC(tx_ring, i); 6961 6962 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 6963 6964 size = skb_headlen(skb); 6965 data_len = skb->data_len; 6966 6967 #ifdef IXGBE_FCOE 6968 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 6969 if (data_len < sizeof(struct fcoe_crc_eof)) { 6970 size -= sizeof(struct fcoe_crc_eof) - data_len; 6971 data_len = 0; 6972 } else { 6973 data_len -= sizeof(struct fcoe_crc_eof); 6974 } 6975 } 6976 6977 #endif 6978 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6979 6980 tx_buffer = first; 6981 6982 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6983 if (dma_mapping_error(tx_ring->dev, dma)) 6984 goto dma_error; 6985 6986 /* record length, and DMA address */ 6987 dma_unmap_len_set(tx_buffer, len, size); 6988 dma_unmap_addr_set(tx_buffer, dma, dma); 6989 6990 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6991 6992 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 6993 tx_desc->read.cmd_type_len = 6994 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 6995 6996 i++; 6997 tx_desc++; 6998 if (i == tx_ring->count) { 6999 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 7000 i = 0; 7001 } 7002 tx_desc->read.olinfo_status = 0; 7003 7004 dma += IXGBE_MAX_DATA_PER_TXD; 7005 size -= IXGBE_MAX_DATA_PER_TXD; 7006 7007 tx_desc->read.buffer_addr = cpu_to_le64(dma); 7008 } 7009 7010 if (likely(!data_len)) 7011 break; 7012 7013 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 7014 7015 i++; 7016 tx_desc++; 7017 if (i == tx_ring->count) { 7018 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 7019 i = 0; 7020 } 7021 tx_desc->read.olinfo_status = 0; 7022 7023 #ifdef IXGBE_FCOE 7024 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 7025 #else 7026 size = skb_frag_size(frag); 7027 #endif 7028 data_len -= size; 7029 7030 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 7031 DMA_TO_DEVICE); 7032 7033 tx_buffer = &tx_ring->tx_buffer_info[i]; 7034 } 7035 7036 /* write last descriptor with RS and EOP bits */ 7037 cmd_type |= size | IXGBE_TXD_CMD; 7038 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 7039 7040 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 7041 7042 /* set the timestamp */ 7043 first->time_stamp = jiffies; 7044 7045 /* 7046 * Force memory writes to complete before letting h/w know there 7047 * are new descriptors to fetch. (Only applicable for weak-ordered 7048 * memory model archs, such as IA-64). 7049 * 7050 * We also need this memory barrier to make certain all of the 7051 * status bits have been updated before next_to_watch is written. 7052 */ 7053 wmb(); 7054 7055 /* set next_to_watch value indicating a packet is present */ 7056 first->next_to_watch = tx_desc; 7057 7058 i++; 7059 if (i == tx_ring->count) 7060 i = 0; 7061 7062 tx_ring->next_to_use = i; 7063 7064 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 7065 7066 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 7067 writel(i, tx_ring->tail); 7068 7069 /* we need this if more than one processor can write to our tail 7070 * at a time, it synchronizes IO on IA64/Altix systems 7071 */ 7072 mmiowb(); 7073 } 7074 7075 return; 7076 dma_error: 7077 dev_err(tx_ring->dev, "TX DMA map failed\n"); 7078 7079 /* clear dma mappings for failed tx_buffer_info map */ 7080 for (;;) { 7081 tx_buffer = &tx_ring->tx_buffer_info[i]; 7082 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer); 7083 if (tx_buffer == first) 7084 break; 7085 if (i == 0) 7086 i = tx_ring->count; 7087 i--; 7088 } 7089 7090 tx_ring->next_to_use = i; 7091 } 7092 7093 static void ixgbe_atr(struct ixgbe_ring *ring, 7094 struct ixgbe_tx_buffer *first) 7095 { 7096 struct ixgbe_q_vector *q_vector = ring->q_vector; 7097 union ixgbe_atr_hash_dword input = { .dword = 0 }; 7098 union ixgbe_atr_hash_dword common = { .dword = 0 }; 7099 union { 7100 unsigned char *network; 7101 struct iphdr *ipv4; 7102 struct ipv6hdr *ipv6; 7103 } hdr; 7104 struct tcphdr *th; 7105 __be16 vlan_id; 7106 7107 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 7108 if (!q_vector) 7109 return; 7110 7111 /* do nothing if sampling is disabled */ 7112 if (!ring->atr_sample_rate) 7113 return; 7114 7115 ring->atr_count++; 7116 7117 /* snag network header to get L4 type and address */ 7118 hdr.network = skb_network_header(first->skb); 7119 7120 /* Currently only IPv4/IPv6 with TCP is supported */ 7121 if ((first->protocol != htons(ETH_P_IPV6) || 7122 hdr.ipv6->nexthdr != IPPROTO_TCP) && 7123 (first->protocol != htons(ETH_P_IP) || 7124 hdr.ipv4->protocol != IPPROTO_TCP)) 7125 return; 7126 7127 th = tcp_hdr(first->skb); 7128 7129 /* skip this packet since it is invalid or the socket is closing */ 7130 if (!th || th->fin) 7131 return; 7132 7133 /* sample on all syn packets or once every atr sample count */ 7134 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 7135 return; 7136 7137 /* reset sample count */ 7138 ring->atr_count = 0; 7139 7140 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 7141 7142 /* 7143 * src and dst are inverted, think how the receiver sees them 7144 * 7145 * The input is broken into two sections, a non-compressed section 7146 * containing vm_pool, vlan_id, and flow_type. The rest of the data 7147 * is XORed together and stored in the compressed dword. 7148 */ 7149 input.formatted.vlan_id = vlan_id; 7150 7151 /* 7152 * since src port and flex bytes occupy the same word XOR them together 7153 * and write the value to source port portion of compressed dword 7154 */ 7155 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 7156 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 7157 else 7158 common.port.src ^= th->dest ^ first->protocol; 7159 common.port.dst ^= th->source; 7160 7161 if (first->protocol == htons(ETH_P_IP)) { 7162 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 7163 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 7164 } else { 7165 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 7166 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 7167 hdr.ipv6->saddr.s6_addr32[1] ^ 7168 hdr.ipv6->saddr.s6_addr32[2] ^ 7169 hdr.ipv6->saddr.s6_addr32[3] ^ 7170 hdr.ipv6->daddr.s6_addr32[0] ^ 7171 hdr.ipv6->daddr.s6_addr32[1] ^ 7172 hdr.ipv6->daddr.s6_addr32[2] ^ 7173 hdr.ipv6->daddr.s6_addr32[3]; 7174 } 7175 7176 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 7177 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 7178 input, common, ring->queue_index); 7179 } 7180 7181 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 7182 void *accel_priv, select_queue_fallback_t fallback) 7183 { 7184 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv; 7185 #ifdef IXGBE_FCOE 7186 struct ixgbe_adapter *adapter; 7187 struct ixgbe_ring_feature *f; 7188 int txq; 7189 #endif 7190 7191 if (fwd_adapter) 7192 return skb->queue_mapping + fwd_adapter->tx_base_queue; 7193 7194 #ifdef IXGBE_FCOE 7195 7196 /* 7197 * only execute the code below if protocol is FCoE 7198 * or FIP and we have FCoE enabled on the adapter 7199 */ 7200 switch (vlan_get_protocol(skb)) { 7201 case htons(ETH_P_FCOE): 7202 case htons(ETH_P_FIP): 7203 adapter = netdev_priv(dev); 7204 7205 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) 7206 break; 7207 default: 7208 return fallback(dev, skb); 7209 } 7210 7211 f = &adapter->ring_feature[RING_F_FCOE]; 7212 7213 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 7214 smp_processor_id(); 7215 7216 while (txq >= f->indices) 7217 txq -= f->indices; 7218 7219 return txq + f->offset; 7220 #else 7221 return fallback(dev, skb); 7222 #endif 7223 } 7224 7225 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 7226 struct ixgbe_adapter *adapter, 7227 struct ixgbe_ring *tx_ring) 7228 { 7229 struct ixgbe_tx_buffer *first; 7230 int tso; 7231 u32 tx_flags = 0; 7232 unsigned short f; 7233 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 7234 __be16 protocol = skb->protocol; 7235 u8 hdr_len = 0; 7236 7237 /* 7238 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 7239 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 7240 * + 2 desc gap to keep tail from touching head, 7241 * + 1 desc for context descriptor, 7242 * otherwise try next time 7243 */ 7244 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 7245 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 7246 7247 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 7248 tx_ring->tx_stats.tx_busy++; 7249 return NETDEV_TX_BUSY; 7250 } 7251 7252 /* record the location of the first descriptor for this packet */ 7253 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 7254 first->skb = skb; 7255 first->bytecount = skb->len; 7256 first->gso_segs = 1; 7257 7258 /* if we have a HW VLAN tag being added default to the HW one */ 7259 if (skb_vlan_tag_present(skb)) { 7260 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 7261 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 7262 /* else if it is a SW VLAN check the next protocol and store the tag */ 7263 } else if (protocol == htons(ETH_P_8021Q)) { 7264 struct vlan_hdr *vhdr, _vhdr; 7265 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 7266 if (!vhdr) 7267 goto out_drop; 7268 7269 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 7270 IXGBE_TX_FLAGS_VLAN_SHIFT; 7271 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 7272 } 7273 protocol = vlan_get_protocol(skb); 7274 7275 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 7276 adapter->ptp_clock && 7277 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 7278 &adapter->state)) { 7279 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 7280 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 7281 7282 /* schedule check for Tx timestamp */ 7283 adapter->ptp_tx_skb = skb_get(skb); 7284 adapter->ptp_tx_start = jiffies; 7285 schedule_work(&adapter->ptp_tx_work); 7286 } 7287 7288 skb_tx_timestamp(skb); 7289 7290 #ifdef CONFIG_PCI_IOV 7291 /* 7292 * Use the l2switch_enable flag - would be false if the DMA 7293 * Tx switch had been disabled. 7294 */ 7295 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 7296 tx_flags |= IXGBE_TX_FLAGS_CC; 7297 7298 #endif 7299 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 7300 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 7301 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 7302 (skb->priority != TC_PRIO_CONTROL))) { 7303 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 7304 tx_flags |= (skb->priority & 0x7) << 7305 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 7306 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 7307 struct vlan_ethhdr *vhdr; 7308 7309 if (skb_cow_head(skb, 0)) 7310 goto out_drop; 7311 vhdr = (struct vlan_ethhdr *)skb->data; 7312 vhdr->h_vlan_TCI = htons(tx_flags >> 7313 IXGBE_TX_FLAGS_VLAN_SHIFT); 7314 } else { 7315 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 7316 } 7317 } 7318 7319 /* record initial flags and protocol */ 7320 first->tx_flags = tx_flags; 7321 first->protocol = protocol; 7322 7323 #ifdef IXGBE_FCOE 7324 /* setup tx offload for FCoE */ 7325 if ((protocol == htons(ETH_P_FCOE)) && 7326 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 7327 tso = ixgbe_fso(tx_ring, first, &hdr_len); 7328 if (tso < 0) 7329 goto out_drop; 7330 7331 goto xmit_fcoe; 7332 } 7333 7334 #endif /* IXGBE_FCOE */ 7335 tso = ixgbe_tso(tx_ring, first, &hdr_len); 7336 if (tso < 0) 7337 goto out_drop; 7338 else if (!tso) 7339 ixgbe_tx_csum(tx_ring, first); 7340 7341 /* add the ATR filter if ATR is on */ 7342 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 7343 ixgbe_atr(tx_ring, first); 7344 7345 #ifdef IXGBE_FCOE 7346 xmit_fcoe: 7347 #endif /* IXGBE_FCOE */ 7348 ixgbe_tx_map(tx_ring, first, hdr_len); 7349 7350 return NETDEV_TX_OK; 7351 7352 out_drop: 7353 dev_kfree_skb_any(first->skb); 7354 first->skb = NULL; 7355 7356 return NETDEV_TX_OK; 7357 } 7358 7359 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 7360 struct net_device *netdev, 7361 struct ixgbe_ring *ring) 7362 { 7363 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7364 struct ixgbe_ring *tx_ring; 7365 7366 /* 7367 * The minimum packet size for olinfo paylen is 17 so pad the skb 7368 * in order to meet this minimum size requirement. 7369 */ 7370 if (skb_put_padto(skb, 17)) 7371 return NETDEV_TX_OK; 7372 7373 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping]; 7374 7375 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 7376 } 7377 7378 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 7379 struct net_device *netdev) 7380 { 7381 return __ixgbe_xmit_frame(skb, netdev, NULL); 7382 } 7383 7384 /** 7385 * ixgbe_set_mac - Change the Ethernet Address of the NIC 7386 * @netdev: network interface device structure 7387 * @p: pointer to an address structure 7388 * 7389 * Returns 0 on success, negative on failure 7390 **/ 7391 static int ixgbe_set_mac(struct net_device *netdev, void *p) 7392 { 7393 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7394 struct ixgbe_hw *hw = &adapter->hw; 7395 struct sockaddr *addr = p; 7396 int ret; 7397 7398 if (!is_valid_ether_addr(addr->sa_data)) 7399 return -EADDRNOTAVAIL; 7400 7401 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0)); 7402 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 7403 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 7404 7405 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0)); 7406 return ret > 0 ? 0 : ret; 7407 } 7408 7409 static int 7410 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 7411 { 7412 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7413 struct ixgbe_hw *hw = &adapter->hw; 7414 u16 value; 7415 int rc; 7416 7417 if (prtad != hw->phy.mdio.prtad) 7418 return -EINVAL; 7419 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 7420 if (!rc) 7421 rc = value; 7422 return rc; 7423 } 7424 7425 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 7426 u16 addr, u16 value) 7427 { 7428 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7429 struct ixgbe_hw *hw = &adapter->hw; 7430 7431 if (prtad != hw->phy.mdio.prtad) 7432 return -EINVAL; 7433 return hw->phy.ops.write_reg(hw, addr, devad, value); 7434 } 7435 7436 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 7437 { 7438 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7439 7440 switch (cmd) { 7441 case SIOCSHWTSTAMP: 7442 return ixgbe_ptp_set_ts_config(adapter, req); 7443 case SIOCGHWTSTAMP: 7444 return ixgbe_ptp_get_ts_config(adapter, req); 7445 default: 7446 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 7447 } 7448 } 7449 7450 /** 7451 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 7452 * netdev->dev_addrs 7453 * @netdev: network interface device structure 7454 * 7455 * Returns non-zero on failure 7456 **/ 7457 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 7458 { 7459 int err = 0; 7460 struct ixgbe_adapter *adapter = netdev_priv(dev); 7461 struct ixgbe_hw *hw = &adapter->hw; 7462 7463 if (is_valid_ether_addr(hw->mac.san_addr)) { 7464 rtnl_lock(); 7465 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 7466 rtnl_unlock(); 7467 7468 /* update SAN MAC vmdq pool selection */ 7469 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 7470 } 7471 return err; 7472 } 7473 7474 /** 7475 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 7476 * netdev->dev_addrs 7477 * @netdev: network interface device structure 7478 * 7479 * Returns non-zero on failure 7480 **/ 7481 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 7482 { 7483 int err = 0; 7484 struct ixgbe_adapter *adapter = netdev_priv(dev); 7485 struct ixgbe_mac_info *mac = &adapter->hw.mac; 7486 7487 if (is_valid_ether_addr(mac->san_addr)) { 7488 rtnl_lock(); 7489 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 7490 rtnl_unlock(); 7491 } 7492 return err; 7493 } 7494 7495 #ifdef CONFIG_NET_POLL_CONTROLLER 7496 /* 7497 * Polling 'interrupt' - used by things like netconsole to send skbs 7498 * without having to re-enable interrupts. It's not called while 7499 * the interrupt routine is executing. 7500 */ 7501 static void ixgbe_netpoll(struct net_device *netdev) 7502 { 7503 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7504 int i; 7505 7506 /* if interface is down do nothing */ 7507 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7508 return; 7509 7510 adapter->flags |= IXGBE_FLAG_IN_NETPOLL; 7511 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 7512 for (i = 0; i < adapter->num_q_vectors; i++) 7513 ixgbe_msix_clean_rings(0, adapter->q_vector[i]); 7514 } else { 7515 ixgbe_intr(adapter->pdev->irq, netdev); 7516 } 7517 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; 7518 } 7519 7520 #endif 7521 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev, 7522 struct rtnl_link_stats64 *stats) 7523 { 7524 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7525 int i; 7526 7527 rcu_read_lock(); 7528 for (i = 0; i < adapter->num_rx_queues; i++) { 7529 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); 7530 u64 bytes, packets; 7531 unsigned int start; 7532 7533 if (ring) { 7534 do { 7535 start = u64_stats_fetch_begin_irq(&ring->syncp); 7536 packets = ring->stats.packets; 7537 bytes = ring->stats.bytes; 7538 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 7539 stats->rx_packets += packets; 7540 stats->rx_bytes += bytes; 7541 } 7542 } 7543 7544 for (i = 0; i < adapter->num_tx_queues; i++) { 7545 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); 7546 u64 bytes, packets; 7547 unsigned int start; 7548 7549 if (ring) { 7550 do { 7551 start = u64_stats_fetch_begin_irq(&ring->syncp); 7552 packets = ring->stats.packets; 7553 bytes = ring->stats.bytes; 7554 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 7555 stats->tx_packets += packets; 7556 stats->tx_bytes += bytes; 7557 } 7558 } 7559 rcu_read_unlock(); 7560 /* following stats updated by ixgbe_watchdog_task() */ 7561 stats->multicast = netdev->stats.multicast; 7562 stats->rx_errors = netdev->stats.rx_errors; 7563 stats->rx_length_errors = netdev->stats.rx_length_errors; 7564 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 7565 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 7566 return stats; 7567 } 7568 7569 #ifdef CONFIG_IXGBE_DCB 7570 /** 7571 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 7572 * @adapter: pointer to ixgbe_adapter 7573 * @tc: number of traffic classes currently enabled 7574 * 7575 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 7576 * 802.1Q priority maps to a packet buffer that exists. 7577 */ 7578 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 7579 { 7580 struct ixgbe_hw *hw = &adapter->hw; 7581 u32 reg, rsave; 7582 int i; 7583 7584 /* 82598 have a static priority to TC mapping that can not 7585 * be changed so no validation is needed. 7586 */ 7587 if (hw->mac.type == ixgbe_mac_82598EB) 7588 return; 7589 7590 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 7591 rsave = reg; 7592 7593 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 7594 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 7595 7596 /* If up2tc is out of bounds default to zero */ 7597 if (up2tc > tc) 7598 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 7599 } 7600 7601 if (reg != rsave) 7602 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 7603 7604 return; 7605 } 7606 7607 /** 7608 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 7609 * @adapter: Pointer to adapter struct 7610 * 7611 * Populate the netdev user priority to tc map 7612 */ 7613 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 7614 { 7615 struct net_device *dev = adapter->netdev; 7616 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 7617 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 7618 u8 prio; 7619 7620 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 7621 u8 tc = 0; 7622 7623 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 7624 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 7625 else if (ets) 7626 tc = ets->prio_tc[prio]; 7627 7628 netdev_set_prio_tc_map(dev, prio, tc); 7629 } 7630 } 7631 7632 #endif /* CONFIG_IXGBE_DCB */ 7633 /** 7634 * ixgbe_setup_tc - configure net_device for multiple traffic classes 7635 * 7636 * @netdev: net device to configure 7637 * @tc: number of traffic classes to enable 7638 */ 7639 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 7640 { 7641 struct ixgbe_adapter *adapter = netdev_priv(dev); 7642 struct ixgbe_hw *hw = &adapter->hw; 7643 bool pools; 7644 7645 /* Hardware supports up to 8 traffic classes */ 7646 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs || 7647 (hw->mac.type == ixgbe_mac_82598EB && 7648 tc < MAX_TRAFFIC_CLASS)) 7649 return -EINVAL; 7650 7651 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1); 7652 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS) 7653 return -EBUSY; 7654 7655 /* Hardware has to reinitialize queues and interrupts to 7656 * match packet buffer alignment. Unfortunately, the 7657 * hardware is not flexible enough to do this dynamically. 7658 */ 7659 if (netif_running(dev)) 7660 ixgbe_close(dev); 7661 ixgbe_clear_interrupt_scheme(adapter); 7662 7663 #ifdef CONFIG_IXGBE_DCB 7664 if (tc) { 7665 netdev_set_num_tc(dev, tc); 7666 ixgbe_set_prio_tc_map(adapter); 7667 7668 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 7669 7670 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 7671 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 7672 adapter->hw.fc.requested_mode = ixgbe_fc_none; 7673 } 7674 } else { 7675 netdev_reset_tc(dev); 7676 7677 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 7678 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 7679 7680 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 7681 7682 adapter->temp_dcb_cfg.pfc_mode_enable = false; 7683 adapter->dcb_cfg.pfc_mode_enable = false; 7684 } 7685 7686 ixgbe_validate_rtr(adapter, tc); 7687 7688 #endif /* CONFIG_IXGBE_DCB */ 7689 ixgbe_init_interrupt_scheme(adapter); 7690 7691 if (netif_running(dev)) 7692 return ixgbe_open(dev); 7693 7694 return 0; 7695 } 7696 7697 #ifdef CONFIG_PCI_IOV 7698 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 7699 { 7700 struct net_device *netdev = adapter->netdev; 7701 7702 rtnl_lock(); 7703 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev)); 7704 rtnl_unlock(); 7705 } 7706 7707 #endif 7708 void ixgbe_do_reset(struct net_device *netdev) 7709 { 7710 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7711 7712 if (netif_running(netdev)) 7713 ixgbe_reinit_locked(adapter); 7714 else 7715 ixgbe_reset(adapter); 7716 } 7717 7718 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 7719 netdev_features_t features) 7720 { 7721 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7722 7723 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 7724 if (!(features & NETIF_F_RXCSUM)) 7725 features &= ~NETIF_F_LRO; 7726 7727 /* Turn off LRO if not RSC capable */ 7728 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 7729 features &= ~NETIF_F_LRO; 7730 7731 return features; 7732 } 7733 7734 static int ixgbe_set_features(struct net_device *netdev, 7735 netdev_features_t features) 7736 { 7737 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7738 netdev_features_t changed = netdev->features ^ features; 7739 bool need_reset = false; 7740 7741 /* Make sure RSC matches LRO, reset if change */ 7742 if (!(features & NETIF_F_LRO)) { 7743 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 7744 need_reset = true; 7745 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 7746 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 7747 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 7748 if (adapter->rx_itr_setting == 1 || 7749 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 7750 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 7751 need_reset = true; 7752 } else if ((changed ^ features) & NETIF_F_LRO) { 7753 e_info(probe, "rx-usecs set too low, " 7754 "disabling RSC\n"); 7755 } 7756 } 7757 7758 /* 7759 * Check if Flow Director n-tuple support was enabled or disabled. If 7760 * the state changed, we need to reset. 7761 */ 7762 switch (features & NETIF_F_NTUPLE) { 7763 case NETIF_F_NTUPLE: 7764 /* turn off ATR, enable perfect filters and reset */ 7765 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 7766 need_reset = true; 7767 7768 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 7769 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 7770 break; 7771 default: 7772 /* turn off perfect filters, enable ATR and reset */ 7773 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 7774 need_reset = true; 7775 7776 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 7777 7778 /* We cannot enable ATR if SR-IOV is enabled */ 7779 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 7780 break; 7781 7782 /* We cannot enable ATR if we have 2 or more traffic classes */ 7783 if (netdev_get_num_tc(netdev) > 1) 7784 break; 7785 7786 /* We cannot enable ATR if RSS is disabled */ 7787 if (adapter->ring_feature[RING_F_RSS].limit <= 1) 7788 break; 7789 7790 /* A sample rate of 0 indicates ATR disabled */ 7791 if (!adapter->atr_sample_rate) 7792 break; 7793 7794 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 7795 break; 7796 } 7797 7798 if (features & NETIF_F_HW_VLAN_CTAG_RX) 7799 ixgbe_vlan_strip_enable(adapter); 7800 else 7801 ixgbe_vlan_strip_disable(adapter); 7802 7803 if (changed & NETIF_F_RXALL) 7804 need_reset = true; 7805 7806 netdev->features = features; 7807 if (need_reset) 7808 ixgbe_do_reset(netdev); 7809 7810 return 0; 7811 } 7812 7813 /** 7814 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up 7815 * @dev: The port's netdev 7816 * @sa_family: Socket Family that VXLAN is notifiying us about 7817 * @port: New UDP port number that VXLAN started listening to 7818 **/ 7819 static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family, 7820 __be16 port) 7821 { 7822 struct ixgbe_adapter *adapter = netdev_priv(dev); 7823 struct ixgbe_hw *hw = &adapter->hw; 7824 u16 new_port = ntohs(port); 7825 7826 if (sa_family == AF_INET6) 7827 return; 7828 7829 if (adapter->vxlan_port == new_port) { 7830 netdev_info(dev, "Port %d already offloaded\n", new_port); 7831 return; 7832 } 7833 7834 if (adapter->vxlan_port) { 7835 netdev_info(dev, 7836 "Hit Max num of UDP ports, not adding port %d\n", 7837 new_port); 7838 return; 7839 } 7840 7841 adapter->vxlan_port = new_port; 7842 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, new_port); 7843 } 7844 7845 /** 7846 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away 7847 * @dev: The port's netdev 7848 * @sa_family: Socket Family that VXLAN is notifying us about 7849 * @port: UDP port number that VXLAN stopped listening to 7850 **/ 7851 static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family, 7852 __be16 port) 7853 { 7854 struct ixgbe_adapter *adapter = netdev_priv(dev); 7855 struct ixgbe_hw *hw = &adapter->hw; 7856 u16 new_port = ntohs(port); 7857 7858 if (sa_family == AF_INET6) 7859 return; 7860 7861 if (adapter->vxlan_port != new_port) { 7862 netdev_info(dev, "Port %d was not found, not deleting\n", 7863 new_port); 7864 return; 7865 } 7866 7867 adapter->vxlan_port = 0; 7868 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, 0); 7869 } 7870 7871 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 7872 struct net_device *dev, 7873 const unsigned char *addr, u16 vid, 7874 u16 flags) 7875 { 7876 /* guarantee we can provide a unique filter for the unicast address */ 7877 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 7878 if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev)) 7879 return -ENOMEM; 7880 } 7881 7882 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 7883 } 7884 7885 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 7886 struct nlmsghdr *nlh, u16 flags) 7887 { 7888 struct ixgbe_adapter *adapter = netdev_priv(dev); 7889 struct nlattr *attr, *br_spec; 7890 int rem; 7891 7892 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 7893 return -EOPNOTSUPP; 7894 7895 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 7896 if (!br_spec) 7897 return -EINVAL; 7898 7899 nla_for_each_nested(attr, br_spec, rem) { 7900 __u16 mode; 7901 u32 reg = 0; 7902 7903 if (nla_type(attr) != IFLA_BRIDGE_MODE) 7904 continue; 7905 7906 if (nla_len(attr) < sizeof(mode)) 7907 return -EINVAL; 7908 7909 mode = nla_get_u16(attr); 7910 if (mode == BRIDGE_MODE_VEPA) { 7911 reg = 0; 7912 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB; 7913 } else if (mode == BRIDGE_MODE_VEB) { 7914 reg = IXGBE_PFDTXGSWC_VT_LBEN; 7915 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB; 7916 } else 7917 return -EINVAL; 7918 7919 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg); 7920 7921 e_info(drv, "enabling bridge mode: %s\n", 7922 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 7923 } 7924 7925 return 0; 7926 } 7927 7928 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 7929 struct net_device *dev, 7930 u32 filter_mask) 7931 { 7932 struct ixgbe_adapter *adapter = netdev_priv(dev); 7933 u16 mode; 7934 7935 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 7936 return 0; 7937 7938 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB) 7939 mode = BRIDGE_MODE_VEB; 7940 else 7941 mode = BRIDGE_MODE_VEPA; 7942 7943 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode, 0, 0); 7944 } 7945 7946 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 7947 { 7948 struct ixgbe_fwd_adapter *fwd_adapter = NULL; 7949 struct ixgbe_adapter *adapter = netdev_priv(pdev); 7950 int used_pools = adapter->num_vfs + adapter->num_rx_pools; 7951 unsigned int limit; 7952 int pool, err; 7953 7954 /* Hardware has a limited number of available pools. Each VF, and the 7955 * PF require a pool. Check to ensure we don't attempt to use more 7956 * then the available number of pools. 7957 */ 7958 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 7959 return ERR_PTR(-EINVAL); 7960 7961 #ifdef CONFIG_RPS 7962 if (vdev->num_rx_queues != vdev->num_tx_queues) { 7963 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n", 7964 vdev->name); 7965 return ERR_PTR(-EINVAL); 7966 } 7967 #endif 7968 /* Check for hardware restriction on number of rx/tx queues */ 7969 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES || 7970 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) { 7971 netdev_info(pdev, 7972 "%s: Supports RX/TX Queue counts 1,2, and 4\n", 7973 pdev->name); 7974 return ERR_PTR(-EINVAL); 7975 } 7976 7977 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 7978 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) || 7979 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS)) 7980 return ERR_PTR(-EBUSY); 7981 7982 fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL); 7983 if (!fwd_adapter) 7984 return ERR_PTR(-ENOMEM); 7985 7986 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32); 7987 adapter->num_rx_pools++; 7988 set_bit(pool, &adapter->fwd_bitmask); 7989 limit = find_last_bit(&adapter->fwd_bitmask, 32); 7990 7991 /* Enable VMDq flag so device will be set in VM mode */ 7992 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED; 7993 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 7994 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues; 7995 7996 /* Force reinit of ring allocation with VMDQ enabled */ 7997 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); 7998 if (err) 7999 goto fwd_add_err; 8000 fwd_adapter->pool = pool; 8001 fwd_adapter->real_adapter = adapter; 8002 err = ixgbe_fwd_ring_up(vdev, fwd_adapter); 8003 if (err) 8004 goto fwd_add_err; 8005 netif_tx_start_all_queues(vdev); 8006 return fwd_adapter; 8007 fwd_add_err: 8008 /* unwind counter and free adapter struct */ 8009 netdev_info(pdev, 8010 "%s: dfwd hardware acceleration failed\n", vdev->name); 8011 clear_bit(pool, &adapter->fwd_bitmask); 8012 adapter->num_rx_pools--; 8013 kfree(fwd_adapter); 8014 return ERR_PTR(err); 8015 } 8016 8017 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 8018 { 8019 struct ixgbe_fwd_adapter *fwd_adapter = priv; 8020 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter; 8021 unsigned int limit; 8022 8023 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask); 8024 adapter->num_rx_pools--; 8025 8026 limit = find_last_bit(&adapter->fwd_bitmask, 32); 8027 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 8028 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter); 8029 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); 8030 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", 8031 fwd_adapter->pool, adapter->num_rx_pools, 8032 fwd_adapter->rx_base_queue, 8033 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool, 8034 adapter->fwd_bitmask); 8035 kfree(fwd_adapter); 8036 } 8037 8038 static const struct net_device_ops ixgbe_netdev_ops = { 8039 .ndo_open = ixgbe_open, 8040 .ndo_stop = ixgbe_close, 8041 .ndo_start_xmit = ixgbe_xmit_frame, 8042 .ndo_select_queue = ixgbe_select_queue, 8043 .ndo_set_rx_mode = ixgbe_set_rx_mode, 8044 .ndo_validate_addr = eth_validate_addr, 8045 .ndo_set_mac_address = ixgbe_set_mac, 8046 .ndo_change_mtu = ixgbe_change_mtu, 8047 .ndo_tx_timeout = ixgbe_tx_timeout, 8048 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 8049 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 8050 .ndo_do_ioctl = ixgbe_ioctl, 8051 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 8052 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 8053 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 8054 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 8055 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 8056 .ndo_get_stats64 = ixgbe_get_stats64, 8057 #ifdef CONFIG_IXGBE_DCB 8058 .ndo_setup_tc = ixgbe_setup_tc, 8059 #endif 8060 #ifdef CONFIG_NET_POLL_CONTROLLER 8061 .ndo_poll_controller = ixgbe_netpoll, 8062 #endif 8063 #ifdef CONFIG_NET_RX_BUSY_POLL 8064 .ndo_busy_poll = ixgbe_low_latency_recv, 8065 #endif 8066 #ifdef IXGBE_FCOE 8067 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 8068 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 8069 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 8070 .ndo_fcoe_enable = ixgbe_fcoe_enable, 8071 .ndo_fcoe_disable = ixgbe_fcoe_disable, 8072 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 8073 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 8074 #endif /* IXGBE_FCOE */ 8075 .ndo_set_features = ixgbe_set_features, 8076 .ndo_fix_features = ixgbe_fix_features, 8077 .ndo_fdb_add = ixgbe_ndo_fdb_add, 8078 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 8079 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 8080 .ndo_dfwd_add_station = ixgbe_fwd_add, 8081 .ndo_dfwd_del_station = ixgbe_fwd_del, 8082 .ndo_add_vxlan_port = ixgbe_add_vxlan_port, 8083 .ndo_del_vxlan_port = ixgbe_del_vxlan_port, 8084 }; 8085 8086 /** 8087 * ixgbe_enumerate_functions - Get the number of ports this device has 8088 * @adapter: adapter structure 8089 * 8090 * This function enumerates the phsyical functions co-located on a single slot, 8091 * in order to determine how many ports a device has. This is most useful in 8092 * determining the required GT/s of PCIe bandwidth necessary for optimal 8093 * performance. 8094 **/ 8095 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 8096 { 8097 struct pci_dev *entry, *pdev = adapter->pdev; 8098 int physfns = 0; 8099 8100 /* Some cards can not use the generic count PCIe functions method, 8101 * because they are behind a parent switch, so we hardcode these with 8102 * the correct number of functions. 8103 */ 8104 if (ixgbe_pcie_from_parent(&adapter->hw)) 8105 physfns = 4; 8106 8107 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 8108 /* don't count virtual functions */ 8109 if (entry->is_virtfn) 8110 continue; 8111 8112 /* When the devices on the bus don't all match our device ID, 8113 * we can't reliably determine the correct number of 8114 * functions. This can occur if a function has been direct 8115 * attached to a virtual machine using VT-d, for example. In 8116 * this case, simply return -1 to indicate this. 8117 */ 8118 if ((entry->vendor != pdev->vendor) || 8119 (entry->device != pdev->device)) 8120 return -1; 8121 8122 physfns++; 8123 } 8124 8125 return physfns; 8126 } 8127 8128 /** 8129 * ixgbe_wol_supported - Check whether device supports WoL 8130 * @hw: hw specific details 8131 * @device_id: the device ID 8132 * @subdev_id: the subsystem device ID 8133 * 8134 * This function is used by probe and ethtool to determine 8135 * which devices have WoL support 8136 * 8137 **/ 8138 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 8139 u16 subdevice_id) 8140 { 8141 struct ixgbe_hw *hw = &adapter->hw; 8142 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 8143 int is_wol_supported = 0; 8144 8145 switch (device_id) { 8146 case IXGBE_DEV_ID_82599_SFP: 8147 /* Only these subdevices could supports WOL */ 8148 switch (subdevice_id) { 8149 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 8150 case IXGBE_SUBDEV_ID_82599_560FLR: 8151 /* only support first port */ 8152 if (hw->bus.func != 0) 8153 break; 8154 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 8155 case IXGBE_SUBDEV_ID_82599_SFP: 8156 case IXGBE_SUBDEV_ID_82599_RNDC: 8157 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 8158 case IXGBE_SUBDEV_ID_82599_LOM_SFP: 8159 is_wol_supported = 1; 8160 break; 8161 } 8162 break; 8163 case IXGBE_DEV_ID_82599EN_SFP: 8164 /* Only this subdevice supports WOL */ 8165 switch (subdevice_id) { 8166 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 8167 is_wol_supported = 1; 8168 break; 8169 } 8170 break; 8171 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 8172 /* All except this subdevice support WOL */ 8173 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 8174 is_wol_supported = 1; 8175 break; 8176 case IXGBE_DEV_ID_82599_KX4: 8177 is_wol_supported = 1; 8178 break; 8179 case IXGBE_DEV_ID_X540T: 8180 case IXGBE_DEV_ID_X540T1: 8181 /* check eeprom to see if enabled wol */ 8182 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 8183 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 8184 (hw->bus.func == 0))) { 8185 is_wol_supported = 1; 8186 } 8187 break; 8188 } 8189 8190 return is_wol_supported; 8191 } 8192 8193 /** 8194 * ixgbe_get_platform_mac_addr - Look up MAC address in Open Firmware / IDPROM 8195 * @adapter: Pointer to adapter struct 8196 */ 8197 static void ixgbe_get_platform_mac_addr(struct ixgbe_adapter *adapter) 8198 { 8199 #ifdef CONFIG_OF 8200 struct device_node *dp = pci_device_to_OF_node(adapter->pdev); 8201 struct ixgbe_hw *hw = &adapter->hw; 8202 const unsigned char *addr; 8203 8204 addr = of_get_mac_address(dp); 8205 if (addr) { 8206 ether_addr_copy(hw->mac.perm_addr, addr); 8207 return; 8208 } 8209 #endif /* CONFIG_OF */ 8210 8211 #ifdef CONFIG_SPARC 8212 ether_addr_copy(hw->mac.perm_addr, idprom->id_ethaddr); 8213 #endif /* CONFIG_SPARC */ 8214 } 8215 8216 /** 8217 * ixgbe_probe - Device Initialization Routine 8218 * @pdev: PCI device information struct 8219 * @ent: entry in ixgbe_pci_tbl 8220 * 8221 * Returns 0 on success, negative on failure 8222 * 8223 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 8224 * The OS initialization, configuring of the adapter private structure, 8225 * and a hardware reset occur. 8226 **/ 8227 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 8228 { 8229 struct net_device *netdev; 8230 struct ixgbe_adapter *adapter = NULL; 8231 struct ixgbe_hw *hw; 8232 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 8233 int i, err, pci_using_dac, expected_gts; 8234 unsigned int indices = MAX_TX_QUEUES; 8235 u8 part_str[IXGBE_PBANUM_LENGTH]; 8236 bool disable_dev = false; 8237 #ifdef IXGBE_FCOE 8238 u16 device_caps; 8239 #endif 8240 u32 eec; 8241 8242 /* Catch broken hardware that put the wrong VF device ID in 8243 * the PCIe SR-IOV capability. 8244 */ 8245 if (pdev->is_virtfn) { 8246 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 8247 pci_name(pdev), pdev->vendor, pdev->device); 8248 return -EINVAL; 8249 } 8250 8251 err = pci_enable_device_mem(pdev); 8252 if (err) 8253 return err; 8254 8255 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 8256 pci_using_dac = 1; 8257 } else { 8258 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 8259 if (err) { 8260 dev_err(&pdev->dev, 8261 "No usable DMA configuration, aborting\n"); 8262 goto err_dma; 8263 } 8264 pci_using_dac = 0; 8265 } 8266 8267 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 8268 IORESOURCE_MEM), ixgbe_driver_name); 8269 if (err) { 8270 dev_err(&pdev->dev, 8271 "pci_request_selected_regions failed 0x%x\n", err); 8272 goto err_pci_reg; 8273 } 8274 8275 pci_enable_pcie_error_reporting(pdev); 8276 8277 pci_set_master(pdev); 8278 pci_save_state(pdev); 8279 8280 if (ii->mac == ixgbe_mac_82598EB) { 8281 #ifdef CONFIG_IXGBE_DCB 8282 /* 8 TC w/ 4 queues per TC */ 8283 indices = 4 * MAX_TRAFFIC_CLASS; 8284 #else 8285 indices = IXGBE_MAX_RSS_INDICES; 8286 #endif 8287 } 8288 8289 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 8290 if (!netdev) { 8291 err = -ENOMEM; 8292 goto err_alloc_etherdev; 8293 } 8294 8295 SET_NETDEV_DEV(netdev, &pdev->dev); 8296 8297 adapter = netdev_priv(netdev); 8298 8299 adapter->netdev = netdev; 8300 adapter->pdev = pdev; 8301 hw = &adapter->hw; 8302 hw->back = adapter; 8303 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 8304 8305 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 8306 pci_resource_len(pdev, 0)); 8307 adapter->io_addr = hw->hw_addr; 8308 if (!hw->hw_addr) { 8309 err = -EIO; 8310 goto err_ioremap; 8311 } 8312 8313 netdev->netdev_ops = &ixgbe_netdev_ops; 8314 ixgbe_set_ethtool_ops(netdev); 8315 netdev->watchdog_timeo = 5 * HZ; 8316 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 8317 8318 /* Setup hw api */ 8319 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); 8320 hw->mac.type = ii->mac; 8321 8322 /* EEPROM */ 8323 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); 8324 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 8325 if (ixgbe_removed(hw->hw_addr)) { 8326 err = -EIO; 8327 goto err_ioremap; 8328 } 8329 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 8330 if (!(eec & (1 << 8))) 8331 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 8332 8333 /* PHY */ 8334 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); 8335 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 8336 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 8337 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 8338 hw->phy.mdio.mmds = 0; 8339 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 8340 hw->phy.mdio.dev = netdev; 8341 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 8342 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 8343 8344 ii->get_invariants(hw); 8345 8346 /* setup the private structure */ 8347 err = ixgbe_sw_init(adapter); 8348 if (err) 8349 goto err_sw_init; 8350 8351 /* Make it possible the adapter to be woken up via WOL */ 8352 switch (adapter->hw.mac.type) { 8353 case ixgbe_mac_82599EB: 8354 case ixgbe_mac_X540: 8355 case ixgbe_mac_X550: 8356 case ixgbe_mac_X550EM_x: 8357 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 8358 break; 8359 default: 8360 break; 8361 } 8362 8363 /* 8364 * If there is a fan on this device and it has failed log the 8365 * failure. 8366 */ 8367 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 8368 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 8369 if (esdp & IXGBE_ESDP_SDP1) 8370 e_crit(probe, "Fan has stopped, replace the adapter\n"); 8371 } 8372 8373 if (allow_unsupported_sfp) 8374 hw->allow_unsupported_sfp = allow_unsupported_sfp; 8375 8376 /* reset_hw fills in the perm_addr as well */ 8377 hw->phy.reset_if_overtemp = true; 8378 err = hw->mac.ops.reset_hw(hw); 8379 hw->phy.reset_if_overtemp = false; 8380 if (err == IXGBE_ERR_SFP_NOT_PRESENT && 8381 hw->mac.type == ixgbe_mac_82598EB) { 8382 err = 0; 8383 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 8384 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 8385 e_dev_err("Reload the driver after installing a supported module.\n"); 8386 goto err_sw_init; 8387 } else if (err) { 8388 e_dev_err("HW Init failed: %d\n", err); 8389 goto err_sw_init; 8390 } 8391 8392 #ifdef CONFIG_PCI_IOV 8393 /* SR-IOV not supported on the 82598 */ 8394 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 8395 goto skip_sriov; 8396 /* Mailbox */ 8397 ixgbe_init_mbx_params_pf(hw); 8398 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops)); 8399 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 8400 ixgbe_enable_sriov(adapter); 8401 skip_sriov: 8402 8403 #endif 8404 netdev->features = NETIF_F_SG | 8405 NETIF_F_IP_CSUM | 8406 NETIF_F_IPV6_CSUM | 8407 NETIF_F_HW_VLAN_CTAG_TX | 8408 NETIF_F_HW_VLAN_CTAG_RX | 8409 NETIF_F_HW_VLAN_CTAG_FILTER | 8410 NETIF_F_TSO | 8411 NETIF_F_TSO6 | 8412 NETIF_F_RXHASH | 8413 NETIF_F_RXCSUM; 8414 8415 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD; 8416 8417 switch (adapter->hw.mac.type) { 8418 case ixgbe_mac_82599EB: 8419 case ixgbe_mac_X540: 8420 case ixgbe_mac_X550: 8421 case ixgbe_mac_X550EM_x: 8422 netdev->features |= NETIF_F_SCTP_CSUM; 8423 netdev->hw_features |= NETIF_F_SCTP_CSUM | 8424 NETIF_F_NTUPLE; 8425 break; 8426 default: 8427 break; 8428 } 8429 8430 netdev->hw_features |= NETIF_F_RXALL; 8431 8432 netdev->vlan_features |= NETIF_F_TSO; 8433 netdev->vlan_features |= NETIF_F_TSO6; 8434 netdev->vlan_features |= NETIF_F_IP_CSUM; 8435 netdev->vlan_features |= NETIF_F_IPV6_CSUM; 8436 netdev->vlan_features |= NETIF_F_SG; 8437 8438 netdev->priv_flags |= IFF_UNICAST_FLT; 8439 netdev->priv_flags |= IFF_SUPP_NOFCS; 8440 8441 switch (adapter->hw.mac.type) { 8442 case ixgbe_mac_X550: 8443 case ixgbe_mac_X550EM_x: 8444 netdev->hw_enc_features |= NETIF_F_RXCSUM; 8445 break; 8446 default: 8447 break; 8448 } 8449 8450 #ifdef CONFIG_IXGBE_DCB 8451 netdev->dcbnl_ops = &dcbnl_ops; 8452 #endif 8453 8454 #ifdef IXGBE_FCOE 8455 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 8456 unsigned int fcoe_l; 8457 8458 if (hw->mac.ops.get_device_caps) { 8459 hw->mac.ops.get_device_caps(hw, &device_caps); 8460 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 8461 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 8462 } 8463 8464 8465 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 8466 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 8467 8468 netdev->features |= NETIF_F_FSO | 8469 NETIF_F_FCOE_CRC; 8470 8471 netdev->vlan_features |= NETIF_F_FSO | 8472 NETIF_F_FCOE_CRC | 8473 NETIF_F_FCOE_MTU; 8474 } 8475 #endif /* IXGBE_FCOE */ 8476 if (pci_using_dac) { 8477 netdev->features |= NETIF_F_HIGHDMA; 8478 netdev->vlan_features |= NETIF_F_HIGHDMA; 8479 } 8480 8481 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 8482 netdev->hw_features |= NETIF_F_LRO; 8483 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 8484 netdev->features |= NETIF_F_LRO; 8485 8486 /* make sure the EEPROM is good */ 8487 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 8488 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 8489 err = -EIO; 8490 goto err_sw_init; 8491 } 8492 8493 ixgbe_get_platform_mac_addr(adapter); 8494 8495 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 8496 8497 if (!is_valid_ether_addr(netdev->dev_addr)) { 8498 e_dev_err("invalid MAC address\n"); 8499 err = -EIO; 8500 goto err_sw_init; 8501 } 8502 8503 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr); 8504 8505 setup_timer(&adapter->service_timer, &ixgbe_service_timer, 8506 (unsigned long) adapter); 8507 8508 if (ixgbe_removed(hw->hw_addr)) { 8509 err = -EIO; 8510 goto err_sw_init; 8511 } 8512 INIT_WORK(&adapter->service_task, ixgbe_service_task); 8513 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 8514 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 8515 8516 err = ixgbe_init_interrupt_scheme(adapter); 8517 if (err) 8518 goto err_sw_init; 8519 8520 /* WOL not supported for all devices */ 8521 adapter->wol = 0; 8522 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 8523 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 8524 pdev->subsystem_device); 8525 if (hw->wol_enabled) 8526 adapter->wol = IXGBE_WUFC_MAG; 8527 8528 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 8529 8530 /* save off EEPROM version number */ 8531 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh); 8532 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl); 8533 8534 /* pick up the PCI bus settings for reporting later */ 8535 hw->mac.ops.get_bus_info(hw); 8536 if (ixgbe_pcie_from_parent(hw)) 8537 ixgbe_get_parent_bus_info(adapter); 8538 8539 /* calculate the expected PCIe bandwidth required for optimal 8540 * performance. Note that some older parts will never have enough 8541 * bandwidth due to being older generation PCIe parts. We clamp these 8542 * parts to ensure no warning is displayed if it can't be fixed. 8543 */ 8544 switch (hw->mac.type) { 8545 case ixgbe_mac_82598EB: 8546 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 8547 break; 8548 default: 8549 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 8550 break; 8551 } 8552 8553 /* don't check link if we failed to enumerate functions */ 8554 if (expected_gts > 0) 8555 ixgbe_check_minimum_link(adapter, expected_gts); 8556 8557 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 8558 if (err) 8559 strlcpy(part_str, "Unknown", sizeof(part_str)); 8560 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 8561 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 8562 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 8563 part_str); 8564 else 8565 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 8566 hw->mac.type, hw->phy.type, part_str); 8567 8568 e_dev_info("%pM\n", netdev->dev_addr); 8569 8570 /* reset the hardware with the new settings */ 8571 err = hw->mac.ops.start_hw(hw); 8572 if (err == IXGBE_ERR_EEPROM_VERSION) { 8573 /* We are running on a pre-production device, log a warning */ 8574 e_dev_warn("This device is a pre-production adapter/LOM. " 8575 "Please be aware there may be issues associated " 8576 "with your hardware. If you are experiencing " 8577 "problems please contact your Intel or hardware " 8578 "representative who provided you with this " 8579 "hardware.\n"); 8580 } 8581 strcpy(netdev->name, "eth%d"); 8582 err = register_netdev(netdev); 8583 if (err) 8584 goto err_register; 8585 8586 pci_set_drvdata(pdev, adapter); 8587 8588 /* power down the optics for 82599 SFP+ fiber */ 8589 if (hw->mac.ops.disable_tx_laser) 8590 hw->mac.ops.disable_tx_laser(hw); 8591 8592 /* carrier off reporting is important to ethtool even BEFORE open */ 8593 netif_carrier_off(netdev); 8594 8595 #ifdef CONFIG_IXGBE_DCA 8596 if (dca_add_requester(&pdev->dev) == 0) { 8597 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 8598 ixgbe_setup_dca(adapter); 8599 } 8600 #endif 8601 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 8602 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 8603 for (i = 0; i < adapter->num_vfs; i++) 8604 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 8605 } 8606 8607 /* firmware requires driver version to be 0xFFFFFFFF 8608 * since os does not support feature 8609 */ 8610 if (hw->mac.ops.set_fw_drv_ver) 8611 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 8612 0xFF); 8613 8614 /* add san mac addr to netdev */ 8615 ixgbe_add_sanmac_netdev(netdev); 8616 8617 e_dev_info("%s\n", ixgbe_default_device_descr); 8618 8619 #ifdef CONFIG_IXGBE_HWMON 8620 if (ixgbe_sysfs_init(adapter)) 8621 e_err(probe, "failed to allocate sysfs resources\n"); 8622 #endif /* CONFIG_IXGBE_HWMON */ 8623 8624 ixgbe_dbg_adapter_init(adapter); 8625 8626 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 8627 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 8628 hw->mac.ops.setup_link(hw, 8629 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 8630 true); 8631 8632 return 0; 8633 8634 err_register: 8635 ixgbe_release_hw_control(adapter); 8636 ixgbe_clear_interrupt_scheme(adapter); 8637 err_sw_init: 8638 ixgbe_disable_sriov(adapter); 8639 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 8640 iounmap(adapter->io_addr); 8641 kfree(adapter->mac_table); 8642 err_ioremap: 8643 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 8644 free_netdev(netdev); 8645 err_alloc_etherdev: 8646 pci_release_selected_regions(pdev, 8647 pci_select_bars(pdev, IORESOURCE_MEM)); 8648 err_pci_reg: 8649 err_dma: 8650 if (!adapter || disable_dev) 8651 pci_disable_device(pdev); 8652 return err; 8653 } 8654 8655 /** 8656 * ixgbe_remove - Device Removal Routine 8657 * @pdev: PCI device information struct 8658 * 8659 * ixgbe_remove is called by the PCI subsystem to alert the driver 8660 * that it should release a PCI device. The could be caused by a 8661 * Hot-Plug event, or because the driver is going to be removed from 8662 * memory. 8663 **/ 8664 static void ixgbe_remove(struct pci_dev *pdev) 8665 { 8666 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 8667 struct net_device *netdev; 8668 bool disable_dev; 8669 8670 /* if !adapter then we already cleaned up in probe */ 8671 if (!adapter) 8672 return; 8673 8674 netdev = adapter->netdev; 8675 ixgbe_dbg_adapter_exit(adapter); 8676 8677 set_bit(__IXGBE_REMOVING, &adapter->state); 8678 cancel_work_sync(&adapter->service_task); 8679 8680 8681 #ifdef CONFIG_IXGBE_DCA 8682 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 8683 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 8684 dca_remove_requester(&pdev->dev); 8685 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); 8686 } 8687 8688 #endif 8689 #ifdef CONFIG_IXGBE_HWMON 8690 ixgbe_sysfs_exit(adapter); 8691 #endif /* CONFIG_IXGBE_HWMON */ 8692 8693 /* remove the added san mac */ 8694 ixgbe_del_sanmac_netdev(netdev); 8695 8696 if (netdev->reg_state == NETREG_REGISTERED) 8697 unregister_netdev(netdev); 8698 8699 #ifdef CONFIG_PCI_IOV 8700 /* 8701 * Only disable SR-IOV on unload if the user specified the now 8702 * deprecated max_vfs module parameter. 8703 */ 8704 if (max_vfs) 8705 ixgbe_disable_sriov(adapter); 8706 #endif 8707 ixgbe_clear_interrupt_scheme(adapter); 8708 8709 ixgbe_release_hw_control(adapter); 8710 8711 #ifdef CONFIG_DCB 8712 kfree(adapter->ixgbe_ieee_pfc); 8713 kfree(adapter->ixgbe_ieee_ets); 8714 8715 #endif 8716 iounmap(adapter->io_addr); 8717 pci_release_selected_regions(pdev, pci_select_bars(pdev, 8718 IORESOURCE_MEM)); 8719 8720 e_dev_info("complete\n"); 8721 8722 kfree(adapter->mac_table); 8723 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 8724 free_netdev(netdev); 8725 8726 pci_disable_pcie_error_reporting(pdev); 8727 8728 if (disable_dev) 8729 pci_disable_device(pdev); 8730 } 8731 8732 /** 8733 * ixgbe_io_error_detected - called when PCI error is detected 8734 * @pdev: Pointer to PCI device 8735 * @state: The current pci connection state 8736 * 8737 * This function is called after a PCI bus error affecting 8738 * this device has been detected. 8739 */ 8740 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 8741 pci_channel_state_t state) 8742 { 8743 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 8744 struct net_device *netdev = adapter->netdev; 8745 8746 #ifdef CONFIG_PCI_IOV 8747 struct ixgbe_hw *hw = &adapter->hw; 8748 struct pci_dev *bdev, *vfdev; 8749 u32 dw0, dw1, dw2, dw3; 8750 int vf, pos; 8751 u16 req_id, pf_func; 8752 8753 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 8754 adapter->num_vfs == 0) 8755 goto skip_bad_vf_detection; 8756 8757 bdev = pdev->bus->self; 8758 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 8759 bdev = bdev->bus->self; 8760 8761 if (!bdev) 8762 goto skip_bad_vf_detection; 8763 8764 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 8765 if (!pos) 8766 goto skip_bad_vf_detection; 8767 8768 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 8769 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 8770 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 8771 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 8772 if (ixgbe_removed(hw->hw_addr)) 8773 goto skip_bad_vf_detection; 8774 8775 req_id = dw1 >> 16; 8776 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 8777 if (!(req_id & 0x0080)) 8778 goto skip_bad_vf_detection; 8779 8780 pf_func = req_id & 0x01; 8781 if ((pf_func & 1) == (pdev->devfn & 1)) { 8782 unsigned int device_id; 8783 8784 vf = (req_id & 0x7F) >> 1; 8785 e_dev_err("VF %d has caused a PCIe error\n", vf); 8786 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 8787 "%8.8x\tdw3: %8.8x\n", 8788 dw0, dw1, dw2, dw3); 8789 switch (adapter->hw.mac.type) { 8790 case ixgbe_mac_82599EB: 8791 device_id = IXGBE_82599_VF_DEVICE_ID; 8792 break; 8793 case ixgbe_mac_X540: 8794 device_id = IXGBE_X540_VF_DEVICE_ID; 8795 break; 8796 case ixgbe_mac_X550: 8797 device_id = IXGBE_DEV_ID_X550_VF; 8798 break; 8799 case ixgbe_mac_X550EM_x: 8800 device_id = IXGBE_DEV_ID_X550EM_X_VF; 8801 break; 8802 default: 8803 device_id = 0; 8804 break; 8805 } 8806 8807 /* Find the pci device of the offending VF */ 8808 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 8809 while (vfdev) { 8810 if (vfdev->devfn == (req_id & 0xFF)) 8811 break; 8812 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 8813 device_id, vfdev); 8814 } 8815 /* 8816 * There's a slim chance the VF could have been hot plugged, 8817 * so if it is no longer present we don't need to issue the 8818 * VFLR. Just clean up the AER in that case. 8819 */ 8820 if (vfdev) { 8821 ixgbe_issue_vf_flr(adapter, vfdev); 8822 /* Free device reference count */ 8823 pci_dev_put(vfdev); 8824 } 8825 8826 pci_cleanup_aer_uncorrect_error_status(pdev); 8827 } 8828 8829 /* 8830 * Even though the error may have occurred on the other port 8831 * we still need to increment the vf error reference count for 8832 * both ports because the I/O resume function will be called 8833 * for both of them. 8834 */ 8835 adapter->vferr_refcount++; 8836 8837 return PCI_ERS_RESULT_RECOVERED; 8838 8839 skip_bad_vf_detection: 8840 #endif /* CONFIG_PCI_IOV */ 8841 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 8842 return PCI_ERS_RESULT_DISCONNECT; 8843 8844 rtnl_lock(); 8845 netif_device_detach(netdev); 8846 8847 if (state == pci_channel_io_perm_failure) { 8848 rtnl_unlock(); 8849 return PCI_ERS_RESULT_DISCONNECT; 8850 } 8851 8852 if (netif_running(netdev)) 8853 ixgbe_down(adapter); 8854 8855 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 8856 pci_disable_device(pdev); 8857 rtnl_unlock(); 8858 8859 /* Request a slot reset. */ 8860 return PCI_ERS_RESULT_NEED_RESET; 8861 } 8862 8863 /** 8864 * ixgbe_io_slot_reset - called after the pci bus has been reset. 8865 * @pdev: Pointer to PCI device 8866 * 8867 * Restart the card from scratch, as if from a cold-boot. 8868 */ 8869 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 8870 { 8871 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 8872 pci_ers_result_t result; 8873 int err; 8874 8875 if (pci_enable_device_mem(pdev)) { 8876 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 8877 result = PCI_ERS_RESULT_DISCONNECT; 8878 } else { 8879 smp_mb__before_atomic(); 8880 clear_bit(__IXGBE_DISABLED, &adapter->state); 8881 adapter->hw.hw_addr = adapter->io_addr; 8882 pci_set_master(pdev); 8883 pci_restore_state(pdev); 8884 pci_save_state(pdev); 8885 8886 pci_wake_from_d3(pdev, false); 8887 8888 ixgbe_reset(adapter); 8889 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 8890 result = PCI_ERS_RESULT_RECOVERED; 8891 } 8892 8893 err = pci_cleanup_aer_uncorrect_error_status(pdev); 8894 if (err) { 8895 e_dev_err("pci_cleanup_aer_uncorrect_error_status " 8896 "failed 0x%0x\n", err); 8897 /* non-fatal, continue */ 8898 } 8899 8900 return result; 8901 } 8902 8903 /** 8904 * ixgbe_io_resume - called when traffic can start flowing again. 8905 * @pdev: Pointer to PCI device 8906 * 8907 * This callback is called when the error recovery driver tells us that 8908 * its OK to resume normal operation. 8909 */ 8910 static void ixgbe_io_resume(struct pci_dev *pdev) 8911 { 8912 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 8913 struct net_device *netdev = adapter->netdev; 8914 8915 #ifdef CONFIG_PCI_IOV 8916 if (adapter->vferr_refcount) { 8917 e_info(drv, "Resuming after VF err\n"); 8918 adapter->vferr_refcount--; 8919 return; 8920 } 8921 8922 #endif 8923 if (netif_running(netdev)) 8924 ixgbe_up(adapter); 8925 8926 netif_device_attach(netdev); 8927 } 8928 8929 static const struct pci_error_handlers ixgbe_err_handler = { 8930 .error_detected = ixgbe_io_error_detected, 8931 .slot_reset = ixgbe_io_slot_reset, 8932 .resume = ixgbe_io_resume, 8933 }; 8934 8935 static struct pci_driver ixgbe_driver = { 8936 .name = ixgbe_driver_name, 8937 .id_table = ixgbe_pci_tbl, 8938 .probe = ixgbe_probe, 8939 .remove = ixgbe_remove, 8940 #ifdef CONFIG_PM 8941 .suspend = ixgbe_suspend, 8942 .resume = ixgbe_resume, 8943 #endif 8944 .shutdown = ixgbe_shutdown, 8945 .sriov_configure = ixgbe_pci_sriov_configure, 8946 .err_handler = &ixgbe_err_handler 8947 }; 8948 8949 /** 8950 * ixgbe_init_module - Driver Registration Routine 8951 * 8952 * ixgbe_init_module is the first routine called when the driver is 8953 * loaded. All it does is register with the PCI subsystem. 8954 **/ 8955 static int __init ixgbe_init_module(void) 8956 { 8957 int ret; 8958 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); 8959 pr_info("%s\n", ixgbe_copyright); 8960 8961 ixgbe_dbg_init(); 8962 8963 ret = pci_register_driver(&ixgbe_driver); 8964 if (ret) { 8965 ixgbe_dbg_exit(); 8966 return ret; 8967 } 8968 8969 #ifdef CONFIG_IXGBE_DCA 8970 dca_register_notify(&dca_notifier); 8971 #endif 8972 8973 return 0; 8974 } 8975 8976 module_init(ixgbe_init_module); 8977 8978 /** 8979 * ixgbe_exit_module - Driver Exit Cleanup Routine 8980 * 8981 * ixgbe_exit_module is called just before the driver is removed 8982 * from memory. 8983 **/ 8984 static void __exit ixgbe_exit_module(void) 8985 { 8986 #ifdef CONFIG_IXGBE_DCA 8987 dca_unregister_notify(&dca_notifier); 8988 #endif 8989 pci_unregister_driver(&ixgbe_driver); 8990 8991 ixgbe_dbg_exit(); 8992 8993 rcu_barrier(); /* Wait for completion of call_rcu()'s */ 8994 } 8995 8996 #ifdef CONFIG_IXGBE_DCA 8997 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 8998 void *p) 8999 { 9000 int ret_val; 9001 9002 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 9003 __ixgbe_notify_dca); 9004 9005 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 9006 } 9007 9008 #endif /* CONFIG_IXGBE_DCA */ 9009 9010 module_exit(ixgbe_exit_module); 9011 9012 /* ixgbe_main.c */ 9013