1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #include <linux/types.h> 29 #include <linux/module.h> 30 #include <linux/pci.h> 31 #include <linux/netdevice.h> 32 #include <linux/vmalloc.h> 33 #include <linux/string.h> 34 #include <linux/in.h> 35 #include <linux/interrupt.h> 36 #include <linux/ip.h> 37 #include <linux/tcp.h> 38 #include <linux/sctp.h> 39 #include <linux/pkt_sched.h> 40 #include <linux/ipv6.h> 41 #include <linux/slab.h> 42 #include <net/checksum.h> 43 #include <net/ip6_checksum.h> 44 #include <linux/ethtool.h> 45 #include <linux/if.h> 46 #include <linux/if_vlan.h> 47 #include <linux/if_bridge.h> 48 #include <linux/prefetch.h> 49 #include <scsi/fc/fc_fcoe.h> 50 51 #include "ixgbe.h" 52 #include "ixgbe_common.h" 53 #include "ixgbe_dcb_82599.h" 54 #include "ixgbe_sriov.h" 55 56 char ixgbe_driver_name[] = "ixgbe"; 57 static const char ixgbe_driver_string[] = 58 "Intel(R) 10 Gigabit PCI Express Network Driver"; 59 #ifdef IXGBE_FCOE 60 char ixgbe_default_device_descr[] = 61 "Intel(R) 10 Gigabit Network Connection"; 62 #else 63 static char ixgbe_default_device_descr[] = 64 "Intel(R) 10 Gigabit Network Connection"; 65 #endif 66 #define DRV_VERSION "3.11.33-k" 67 const char ixgbe_driver_version[] = DRV_VERSION; 68 static const char ixgbe_copyright[] = 69 "Copyright (c) 1999-2012 Intel Corporation."; 70 71 static const struct ixgbe_info *ixgbe_info_tbl[] = { 72 [board_82598] = &ixgbe_82598_info, 73 [board_82599] = &ixgbe_82599_info, 74 [board_X540] = &ixgbe_X540_info, 75 }; 76 77 /* ixgbe_pci_tbl - PCI Device ID Table 78 * 79 * Wildcard entries (PCI_ANY_ID) should come last 80 * Last entry must be all 0s 81 * 82 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 83 * Class, Class Mask, private data (not used) } 84 */ 85 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = { 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 115 /* required last entry */ 116 {0, } 117 }; 118 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 119 120 #ifdef CONFIG_IXGBE_DCA 121 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 122 void *p); 123 static struct notifier_block dca_notifier = { 124 .notifier_call = ixgbe_notify_dca, 125 .next = NULL, 126 .priority = 0 127 }; 128 #endif 129 130 #ifdef CONFIG_PCI_IOV 131 static unsigned int max_vfs; 132 module_param(max_vfs, uint, 0); 133 MODULE_PARM_DESC(max_vfs, 134 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63"); 135 #endif /* CONFIG_PCI_IOV */ 136 137 static unsigned int allow_unsupported_sfp; 138 module_param(allow_unsupported_sfp, uint, 0); 139 MODULE_PARM_DESC(allow_unsupported_sfp, 140 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 141 142 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 143 static int debug = -1; 144 module_param(debug, int, 0); 145 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 146 147 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 148 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 149 MODULE_LICENSE("GPL"); 150 MODULE_VERSION(DRV_VERSION); 151 152 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 153 { 154 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 155 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 156 schedule_work(&adapter->service_task); 157 } 158 159 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 160 { 161 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 162 163 /* flush memory to make sure state is correct before next watchdog */ 164 smp_mb__before_clear_bit(); 165 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 166 } 167 168 struct ixgbe_reg_info { 169 u32 ofs; 170 char *name; 171 }; 172 173 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 174 175 /* General Registers */ 176 {IXGBE_CTRL, "CTRL"}, 177 {IXGBE_STATUS, "STATUS"}, 178 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 179 180 /* Interrupt Registers */ 181 {IXGBE_EICR, "EICR"}, 182 183 /* RX Registers */ 184 {IXGBE_SRRCTL(0), "SRRCTL"}, 185 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 186 {IXGBE_RDLEN(0), "RDLEN"}, 187 {IXGBE_RDH(0), "RDH"}, 188 {IXGBE_RDT(0), "RDT"}, 189 {IXGBE_RXDCTL(0), "RXDCTL"}, 190 {IXGBE_RDBAL(0), "RDBAL"}, 191 {IXGBE_RDBAH(0), "RDBAH"}, 192 193 /* TX Registers */ 194 {IXGBE_TDBAL(0), "TDBAL"}, 195 {IXGBE_TDBAH(0), "TDBAH"}, 196 {IXGBE_TDLEN(0), "TDLEN"}, 197 {IXGBE_TDH(0), "TDH"}, 198 {IXGBE_TDT(0), "TDT"}, 199 {IXGBE_TXDCTL(0), "TXDCTL"}, 200 201 /* List Terminator */ 202 {} 203 }; 204 205 206 /* 207 * ixgbe_regdump - register printout routine 208 */ 209 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 210 { 211 int i = 0, j = 0; 212 char rname[16]; 213 u32 regs[64]; 214 215 switch (reginfo->ofs) { 216 case IXGBE_SRRCTL(0): 217 for (i = 0; i < 64; i++) 218 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 219 break; 220 case IXGBE_DCA_RXCTRL(0): 221 for (i = 0; i < 64; i++) 222 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 223 break; 224 case IXGBE_RDLEN(0): 225 for (i = 0; i < 64; i++) 226 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 227 break; 228 case IXGBE_RDH(0): 229 for (i = 0; i < 64; i++) 230 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 231 break; 232 case IXGBE_RDT(0): 233 for (i = 0; i < 64; i++) 234 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 235 break; 236 case IXGBE_RXDCTL(0): 237 for (i = 0; i < 64; i++) 238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 239 break; 240 case IXGBE_RDBAL(0): 241 for (i = 0; i < 64; i++) 242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 243 break; 244 case IXGBE_RDBAH(0): 245 for (i = 0; i < 64; i++) 246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 247 break; 248 case IXGBE_TDBAL(0): 249 for (i = 0; i < 64; i++) 250 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 251 break; 252 case IXGBE_TDBAH(0): 253 for (i = 0; i < 64; i++) 254 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 255 break; 256 case IXGBE_TDLEN(0): 257 for (i = 0; i < 64; i++) 258 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 259 break; 260 case IXGBE_TDH(0): 261 for (i = 0; i < 64; i++) 262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 263 break; 264 case IXGBE_TDT(0): 265 for (i = 0; i < 64; i++) 266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 267 break; 268 case IXGBE_TXDCTL(0): 269 for (i = 0; i < 64; i++) 270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 271 break; 272 default: 273 pr_info("%-15s %08x\n", reginfo->name, 274 IXGBE_READ_REG(hw, reginfo->ofs)); 275 return; 276 } 277 278 for (i = 0; i < 8; i++) { 279 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); 280 pr_err("%-15s", rname); 281 for (j = 0; j < 8; j++) 282 pr_cont(" %08x", regs[i*8+j]); 283 pr_cont("\n"); 284 } 285 286 } 287 288 /* 289 * ixgbe_dump - Print registers, tx-rings and rx-rings 290 */ 291 static void ixgbe_dump(struct ixgbe_adapter *adapter) 292 { 293 struct net_device *netdev = adapter->netdev; 294 struct ixgbe_hw *hw = &adapter->hw; 295 struct ixgbe_reg_info *reginfo; 296 int n = 0; 297 struct ixgbe_ring *tx_ring; 298 struct ixgbe_tx_buffer *tx_buffer; 299 union ixgbe_adv_tx_desc *tx_desc; 300 struct my_u0 { u64 a; u64 b; } *u0; 301 struct ixgbe_ring *rx_ring; 302 union ixgbe_adv_rx_desc *rx_desc; 303 struct ixgbe_rx_buffer *rx_buffer_info; 304 u32 staterr; 305 int i = 0; 306 307 if (!netif_msg_hw(adapter)) 308 return; 309 310 /* Print netdevice Info */ 311 if (netdev) { 312 dev_info(&adapter->pdev->dev, "Net device Info\n"); 313 pr_info("Device Name state " 314 "trans_start last_rx\n"); 315 pr_info("%-15s %016lX %016lX %016lX\n", 316 netdev->name, 317 netdev->state, 318 netdev->trans_start, 319 netdev->last_rx); 320 } 321 322 /* Print Registers */ 323 dev_info(&adapter->pdev->dev, "Register Dump\n"); 324 pr_info(" Register Name Value\n"); 325 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 326 reginfo->name; reginfo++) { 327 ixgbe_regdump(hw, reginfo); 328 } 329 330 /* Print TX Ring Summary */ 331 if (!netdev || !netif_running(netdev)) 332 goto exit; 333 334 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 335 pr_info(" %s %s %s %s\n", 336 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 337 "leng", "ntw", "timestamp"); 338 for (n = 0; n < adapter->num_tx_queues; n++) { 339 tx_ring = adapter->tx_ring[n]; 340 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 341 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 342 n, tx_ring->next_to_use, tx_ring->next_to_clean, 343 (u64)dma_unmap_addr(tx_buffer, dma), 344 dma_unmap_len(tx_buffer, len), 345 tx_buffer->next_to_watch, 346 (u64)tx_buffer->time_stamp); 347 } 348 349 /* Print TX Rings */ 350 if (!netif_msg_tx_done(adapter)) 351 goto rx_ring_summary; 352 353 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 354 355 /* Transmit Descriptor Formats 356 * 357 * 82598 Advanced Transmit Descriptor 358 * +--------------------------------------------------------------+ 359 * 0 | Buffer Address [63:0] | 360 * +--------------------------------------------------------------+ 361 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 362 * +--------------------------------------------------------------+ 363 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 364 * 365 * 82598 Advanced Transmit Descriptor (Write-Back Format) 366 * +--------------------------------------------------------------+ 367 * 0 | RSV [63:0] | 368 * +--------------------------------------------------------------+ 369 * 8 | RSV | STA | NXTSEQ | 370 * +--------------------------------------------------------------+ 371 * 63 36 35 32 31 0 372 * 373 * 82599+ Advanced Transmit Descriptor 374 * +--------------------------------------------------------------+ 375 * 0 | Buffer Address [63:0] | 376 * +--------------------------------------------------------------+ 377 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 378 * +--------------------------------------------------------------+ 379 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 380 * 381 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 382 * +--------------------------------------------------------------+ 383 * 0 | RSV [63:0] | 384 * +--------------------------------------------------------------+ 385 * 8 | RSV | STA | RSV | 386 * +--------------------------------------------------------------+ 387 * 63 36 35 32 31 0 388 */ 389 390 for (n = 0; n < adapter->num_tx_queues; n++) { 391 tx_ring = adapter->tx_ring[n]; 392 pr_info("------------------------------------\n"); 393 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 394 pr_info("------------------------------------\n"); 395 pr_info("%s%s %s %s %s %s\n", 396 "T [desc] [address 63:0 ] ", 397 "[PlPOIdStDDt Ln] [bi->dma ] ", 398 "leng", "ntw", "timestamp", "bi->skb"); 399 400 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 401 tx_desc = IXGBE_TX_DESC(tx_ring, i); 402 tx_buffer = &tx_ring->tx_buffer_info[i]; 403 u0 = (struct my_u0 *)tx_desc; 404 if (dma_unmap_len(tx_buffer, len) > 0) { 405 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p", 406 i, 407 le64_to_cpu(u0->a), 408 le64_to_cpu(u0->b), 409 (u64)dma_unmap_addr(tx_buffer, dma), 410 dma_unmap_len(tx_buffer, len), 411 tx_buffer->next_to_watch, 412 (u64)tx_buffer->time_stamp, 413 tx_buffer->skb); 414 if (i == tx_ring->next_to_use && 415 i == tx_ring->next_to_clean) 416 pr_cont(" NTC/U\n"); 417 else if (i == tx_ring->next_to_use) 418 pr_cont(" NTU\n"); 419 else if (i == tx_ring->next_to_clean) 420 pr_cont(" NTC\n"); 421 else 422 pr_cont("\n"); 423 424 if (netif_msg_pktdata(adapter) && 425 tx_buffer->skb) 426 print_hex_dump(KERN_INFO, "", 427 DUMP_PREFIX_ADDRESS, 16, 1, 428 tx_buffer->skb->data, 429 dma_unmap_len(tx_buffer, len), 430 true); 431 } 432 } 433 } 434 435 /* Print RX Rings Summary */ 436 rx_ring_summary: 437 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 438 pr_info("Queue [NTU] [NTC]\n"); 439 for (n = 0; n < adapter->num_rx_queues; n++) { 440 rx_ring = adapter->rx_ring[n]; 441 pr_info("%5d %5X %5X\n", 442 n, rx_ring->next_to_use, rx_ring->next_to_clean); 443 } 444 445 /* Print RX Rings */ 446 if (!netif_msg_rx_status(adapter)) 447 goto exit; 448 449 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 450 451 /* Receive Descriptor Formats 452 * 453 * 82598 Advanced Receive Descriptor (Read) Format 454 * 63 1 0 455 * +-----------------------------------------------------+ 456 * 0 | Packet Buffer Address [63:1] |A0/NSE| 457 * +----------------------------------------------+------+ 458 * 8 | Header Buffer Address [63:1] | DD | 459 * +-----------------------------------------------------+ 460 * 461 * 462 * 82598 Advanced Receive Descriptor (Write-Back) Format 463 * 464 * 63 48 47 32 31 30 21 20 16 15 4 3 0 465 * +------------------------------------------------------+ 466 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 467 * | Packet | IP | | | | Type | Type | 468 * | Checksum | Ident | | | | | | 469 * +------------------------------------------------------+ 470 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 471 * +------------------------------------------------------+ 472 * 63 48 47 32 31 20 19 0 473 * 474 * 82599+ Advanced Receive Descriptor (Read) Format 475 * 63 1 0 476 * +-----------------------------------------------------+ 477 * 0 | Packet Buffer Address [63:1] |A0/NSE| 478 * +----------------------------------------------+------+ 479 * 8 | Header Buffer Address [63:1] | DD | 480 * +-----------------------------------------------------+ 481 * 482 * 483 * 82599+ Advanced Receive Descriptor (Write-Back) Format 484 * 485 * 63 48 47 32 31 30 21 20 17 16 4 3 0 486 * +------------------------------------------------------+ 487 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 488 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 489 * |/ Flow Dir Flt ID | | | | | | 490 * +------------------------------------------------------+ 491 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 492 * +------------------------------------------------------+ 493 * 63 48 47 32 31 20 19 0 494 */ 495 496 for (n = 0; n < adapter->num_rx_queues; n++) { 497 rx_ring = adapter->rx_ring[n]; 498 pr_info("------------------------------------\n"); 499 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 500 pr_info("------------------------------------\n"); 501 pr_info("%s%s%s", 502 "R [desc] [ PktBuf A0] ", 503 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 504 "<-- Adv Rx Read format\n"); 505 pr_info("%s%s%s", 506 "RWB[desc] [PcsmIpSHl PtRs] ", 507 "[vl er S cks ln] ---------------- [bi->skb ] ", 508 "<-- Adv Rx Write-Back format\n"); 509 510 for (i = 0; i < rx_ring->count; i++) { 511 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 512 rx_desc = IXGBE_RX_DESC(rx_ring, i); 513 u0 = (struct my_u0 *)rx_desc; 514 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 515 if (staterr & IXGBE_RXD_STAT_DD) { 516 /* Descriptor Done */ 517 pr_info("RWB[0x%03X] %016llX " 518 "%016llX ---------------- %p", i, 519 le64_to_cpu(u0->a), 520 le64_to_cpu(u0->b), 521 rx_buffer_info->skb); 522 } else { 523 pr_info("R [0x%03X] %016llX " 524 "%016llX %016llX %p", i, 525 le64_to_cpu(u0->a), 526 le64_to_cpu(u0->b), 527 (u64)rx_buffer_info->dma, 528 rx_buffer_info->skb); 529 530 if (netif_msg_pktdata(adapter) && 531 rx_buffer_info->dma) { 532 print_hex_dump(KERN_INFO, "", 533 DUMP_PREFIX_ADDRESS, 16, 1, 534 page_address(rx_buffer_info->page) + 535 rx_buffer_info->page_offset, 536 ixgbe_rx_bufsz(rx_ring), true); 537 } 538 } 539 540 if (i == rx_ring->next_to_use) 541 pr_cont(" NTU\n"); 542 else if (i == rx_ring->next_to_clean) 543 pr_cont(" NTC\n"); 544 else 545 pr_cont("\n"); 546 547 } 548 } 549 550 exit: 551 return; 552 } 553 554 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 555 { 556 u32 ctrl_ext; 557 558 /* Let firmware take over control of h/w */ 559 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 560 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 561 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 562 } 563 564 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 565 { 566 u32 ctrl_ext; 567 568 /* Let firmware know the driver has taken over */ 569 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 571 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 572 } 573 574 /** 575 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 576 * @adapter: pointer to adapter struct 577 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 578 * @queue: queue to map the corresponding interrupt to 579 * @msix_vector: the vector to map to the corresponding queue 580 * 581 */ 582 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 583 u8 queue, u8 msix_vector) 584 { 585 u32 ivar, index; 586 struct ixgbe_hw *hw = &adapter->hw; 587 switch (hw->mac.type) { 588 case ixgbe_mac_82598EB: 589 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 590 if (direction == -1) 591 direction = 0; 592 index = (((direction * 64) + queue) >> 2) & 0x1F; 593 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 594 ivar &= ~(0xFF << (8 * (queue & 0x3))); 595 ivar |= (msix_vector << (8 * (queue & 0x3))); 596 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 597 break; 598 case ixgbe_mac_82599EB: 599 case ixgbe_mac_X540: 600 if (direction == -1) { 601 /* other causes */ 602 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 603 index = ((queue & 1) * 8); 604 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 605 ivar &= ~(0xFF << index); 606 ivar |= (msix_vector << index); 607 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 608 break; 609 } else { 610 /* tx or rx causes */ 611 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 612 index = ((16 * (queue & 1)) + (8 * direction)); 613 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 614 ivar &= ~(0xFF << index); 615 ivar |= (msix_vector << index); 616 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 617 break; 618 } 619 default: 620 break; 621 } 622 } 623 624 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 625 u64 qmask) 626 { 627 u32 mask; 628 629 switch (adapter->hw.mac.type) { 630 case ixgbe_mac_82598EB: 631 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 632 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 633 break; 634 case ixgbe_mac_82599EB: 635 case ixgbe_mac_X540: 636 mask = (qmask & 0xFFFFFFFF); 637 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 638 mask = (qmask >> 32); 639 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 640 break; 641 default: 642 break; 643 } 644 } 645 646 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring, 647 struct ixgbe_tx_buffer *tx_buffer) 648 { 649 if (tx_buffer->skb) { 650 dev_kfree_skb_any(tx_buffer->skb); 651 if (dma_unmap_len(tx_buffer, len)) 652 dma_unmap_single(ring->dev, 653 dma_unmap_addr(tx_buffer, dma), 654 dma_unmap_len(tx_buffer, len), 655 DMA_TO_DEVICE); 656 } else if (dma_unmap_len(tx_buffer, len)) { 657 dma_unmap_page(ring->dev, 658 dma_unmap_addr(tx_buffer, dma), 659 dma_unmap_len(tx_buffer, len), 660 DMA_TO_DEVICE); 661 } 662 tx_buffer->next_to_watch = NULL; 663 tx_buffer->skb = NULL; 664 dma_unmap_len_set(tx_buffer, len, 0); 665 /* tx_buffer must be completely set up in the transmit path */ 666 } 667 668 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 669 { 670 struct ixgbe_hw *hw = &adapter->hw; 671 struct ixgbe_hw_stats *hwstats = &adapter->stats; 672 int i; 673 u32 data; 674 675 if ((hw->fc.current_mode != ixgbe_fc_full) && 676 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 677 return; 678 679 switch (hw->mac.type) { 680 case ixgbe_mac_82598EB: 681 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 682 break; 683 default: 684 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 685 } 686 hwstats->lxoffrxc += data; 687 688 /* refill credits (no tx hang) if we received xoff */ 689 if (!data) 690 return; 691 692 for (i = 0; i < adapter->num_tx_queues; i++) 693 clear_bit(__IXGBE_HANG_CHECK_ARMED, 694 &adapter->tx_ring[i]->state); 695 } 696 697 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 698 { 699 struct ixgbe_hw *hw = &adapter->hw; 700 struct ixgbe_hw_stats *hwstats = &adapter->stats; 701 u32 xoff[8] = {0}; 702 u8 tc; 703 int i; 704 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 705 706 if (adapter->ixgbe_ieee_pfc) 707 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 708 709 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 710 ixgbe_update_xoff_rx_lfc(adapter); 711 return; 712 } 713 714 /* update stats for each tc, only valid with PFC enabled */ 715 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 716 u32 pxoffrxc; 717 718 switch (hw->mac.type) { 719 case ixgbe_mac_82598EB: 720 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 721 break; 722 default: 723 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 724 } 725 hwstats->pxoffrxc[i] += pxoffrxc; 726 /* Get the TC for given UP */ 727 tc = netdev_get_prio_tc_map(adapter->netdev, i); 728 xoff[tc] += pxoffrxc; 729 } 730 731 /* disarm tx queues that have received xoff frames */ 732 for (i = 0; i < adapter->num_tx_queues; i++) { 733 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 734 735 tc = tx_ring->dcb_tc; 736 if (xoff[tc]) 737 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 738 } 739 } 740 741 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 742 { 743 return ring->stats.packets; 744 } 745 746 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 747 { 748 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev); 749 struct ixgbe_hw *hw = &adapter->hw; 750 751 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); 752 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); 753 754 if (head != tail) 755 return (head < tail) ? 756 tail - head : (tail + ring->count - head); 757 758 return 0; 759 } 760 761 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 762 { 763 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 764 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 765 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 766 bool ret = false; 767 768 clear_check_for_tx_hang(tx_ring); 769 770 /* 771 * Check for a hung queue, but be thorough. This verifies 772 * that a transmit has been completed since the previous 773 * check AND there is at least one packet pending. The 774 * ARMED bit is set to indicate a potential hang. The 775 * bit is cleared if a pause frame is received to remove 776 * false hang detection due to PFC or 802.3x frames. By 777 * requiring this to fail twice we avoid races with 778 * pfc clearing the ARMED bit and conditions where we 779 * run the check_tx_hang logic with a transmit completion 780 * pending but without time to complete it yet. 781 */ 782 if ((tx_done_old == tx_done) && tx_pending) { 783 /* make sure it is true for two checks in a row */ 784 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 785 &tx_ring->state); 786 } else { 787 /* update completed stats and continue */ 788 tx_ring->tx_stats.tx_done_old = tx_done; 789 /* reset the countdown */ 790 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 791 } 792 793 return ret; 794 } 795 796 /** 797 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 798 * @adapter: driver private struct 799 **/ 800 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 801 { 802 803 /* Do the reset outside of interrupt context */ 804 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 805 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 806 ixgbe_service_event_schedule(adapter); 807 } 808 } 809 810 /** 811 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 812 * @q_vector: structure containing interrupt and ring information 813 * @tx_ring: tx ring to clean 814 **/ 815 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 816 struct ixgbe_ring *tx_ring) 817 { 818 struct ixgbe_adapter *adapter = q_vector->adapter; 819 struct ixgbe_tx_buffer *tx_buffer; 820 union ixgbe_adv_tx_desc *tx_desc; 821 unsigned int total_bytes = 0, total_packets = 0; 822 unsigned int budget = q_vector->tx.work_limit; 823 unsigned int i = tx_ring->next_to_clean; 824 825 if (test_bit(__IXGBE_DOWN, &adapter->state)) 826 return true; 827 828 tx_buffer = &tx_ring->tx_buffer_info[i]; 829 tx_desc = IXGBE_TX_DESC(tx_ring, i); 830 i -= tx_ring->count; 831 832 do { 833 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 834 835 /* if next_to_watch is not set then there is no work pending */ 836 if (!eop_desc) 837 break; 838 839 /* prevent any other reads prior to eop_desc */ 840 rmb(); 841 842 /* if DD is not set pending work has not been completed */ 843 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 844 break; 845 846 /* clear next_to_watch to prevent false hangs */ 847 tx_buffer->next_to_watch = NULL; 848 849 /* update the statistics for this packet */ 850 total_bytes += tx_buffer->bytecount; 851 total_packets += tx_buffer->gso_segs; 852 853 if (unlikely(tx_buffer->tx_flags & IXGBE_TX_FLAGS_TSTAMP)) 854 ixgbe_ptp_tx_hwtstamp(q_vector, tx_buffer->skb); 855 856 /* free the skb */ 857 dev_kfree_skb_any(tx_buffer->skb); 858 859 /* unmap skb header data */ 860 dma_unmap_single(tx_ring->dev, 861 dma_unmap_addr(tx_buffer, dma), 862 dma_unmap_len(tx_buffer, len), 863 DMA_TO_DEVICE); 864 865 /* clear tx_buffer data */ 866 tx_buffer->skb = NULL; 867 dma_unmap_len_set(tx_buffer, len, 0); 868 869 /* unmap remaining buffers */ 870 while (tx_desc != eop_desc) { 871 tx_buffer++; 872 tx_desc++; 873 i++; 874 if (unlikely(!i)) { 875 i -= tx_ring->count; 876 tx_buffer = tx_ring->tx_buffer_info; 877 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 878 } 879 880 /* unmap any remaining paged data */ 881 if (dma_unmap_len(tx_buffer, len)) { 882 dma_unmap_page(tx_ring->dev, 883 dma_unmap_addr(tx_buffer, dma), 884 dma_unmap_len(tx_buffer, len), 885 DMA_TO_DEVICE); 886 dma_unmap_len_set(tx_buffer, len, 0); 887 } 888 } 889 890 /* move us one more past the eop_desc for start of next pkt */ 891 tx_buffer++; 892 tx_desc++; 893 i++; 894 if (unlikely(!i)) { 895 i -= tx_ring->count; 896 tx_buffer = tx_ring->tx_buffer_info; 897 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 898 } 899 900 /* issue prefetch for next Tx descriptor */ 901 prefetch(tx_desc); 902 903 /* update budget accounting */ 904 budget--; 905 } while (likely(budget)); 906 907 i += tx_ring->count; 908 tx_ring->next_to_clean = i; 909 u64_stats_update_begin(&tx_ring->syncp); 910 tx_ring->stats.bytes += total_bytes; 911 tx_ring->stats.packets += total_packets; 912 u64_stats_update_end(&tx_ring->syncp); 913 q_vector->tx.total_bytes += total_bytes; 914 q_vector->tx.total_packets += total_packets; 915 916 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 917 /* schedule immediate reset if we believe we hung */ 918 struct ixgbe_hw *hw = &adapter->hw; 919 e_err(drv, "Detected Tx Unit Hang\n" 920 " Tx Queue <%d>\n" 921 " TDH, TDT <%x>, <%x>\n" 922 " next_to_use <%x>\n" 923 " next_to_clean <%x>\n" 924 "tx_buffer_info[next_to_clean]\n" 925 " time_stamp <%lx>\n" 926 " jiffies <%lx>\n", 927 tx_ring->queue_index, 928 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 929 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 930 tx_ring->next_to_use, i, 931 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 932 933 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 934 935 e_info(probe, 936 "tx hang %d detected on queue %d, resetting adapter\n", 937 adapter->tx_timeout_count + 1, tx_ring->queue_index); 938 939 /* schedule immediate reset if we believe we hung */ 940 ixgbe_tx_timeout_reset(adapter); 941 942 /* the adapter is about to reset, no point in enabling stuff */ 943 return true; 944 } 945 946 netdev_tx_completed_queue(txring_txq(tx_ring), 947 total_packets, total_bytes); 948 949 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 950 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 951 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 952 /* Make sure that anybody stopping the queue after this 953 * sees the new next_to_clean. 954 */ 955 smp_mb(); 956 if (__netif_subqueue_stopped(tx_ring->netdev, 957 tx_ring->queue_index) 958 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 959 netif_wake_subqueue(tx_ring->netdev, 960 tx_ring->queue_index); 961 ++tx_ring->tx_stats.restart_queue; 962 } 963 } 964 965 return !!budget; 966 } 967 968 #ifdef CONFIG_IXGBE_DCA 969 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 970 struct ixgbe_ring *tx_ring, 971 int cpu) 972 { 973 struct ixgbe_hw *hw = &adapter->hw; 974 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 975 u16 reg_offset; 976 977 switch (hw->mac.type) { 978 case ixgbe_mac_82598EB: 979 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 980 break; 981 case ixgbe_mac_82599EB: 982 case ixgbe_mac_X540: 983 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 984 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 985 break; 986 default: 987 /* for unknown hardware do not write register */ 988 return; 989 } 990 991 /* 992 * We can enable relaxed ordering for reads, but not writes when 993 * DCA is enabled. This is due to a known issue in some chipsets 994 * which will cause the DCA tag to be cleared. 995 */ 996 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 997 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 998 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 999 1000 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1001 } 1002 1003 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1004 struct ixgbe_ring *rx_ring, 1005 int cpu) 1006 { 1007 struct ixgbe_hw *hw = &adapter->hw; 1008 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1009 u8 reg_idx = rx_ring->reg_idx; 1010 1011 1012 switch (hw->mac.type) { 1013 case ixgbe_mac_82599EB: 1014 case ixgbe_mac_X540: 1015 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1016 break; 1017 default: 1018 break; 1019 } 1020 1021 /* 1022 * We can enable relaxed ordering for reads, but not writes when 1023 * DCA is enabled. This is due to a known issue in some chipsets 1024 * which will cause the DCA tag to be cleared. 1025 */ 1026 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1027 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1028 1029 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1030 } 1031 1032 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1033 { 1034 struct ixgbe_adapter *adapter = q_vector->adapter; 1035 struct ixgbe_ring *ring; 1036 int cpu = get_cpu(); 1037 1038 if (q_vector->cpu == cpu) 1039 goto out_no_update; 1040 1041 ixgbe_for_each_ring(ring, q_vector->tx) 1042 ixgbe_update_tx_dca(adapter, ring, cpu); 1043 1044 ixgbe_for_each_ring(ring, q_vector->rx) 1045 ixgbe_update_rx_dca(adapter, ring, cpu); 1046 1047 q_vector->cpu = cpu; 1048 out_no_update: 1049 put_cpu(); 1050 } 1051 1052 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1053 { 1054 int i; 1055 1056 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) 1057 return; 1058 1059 /* always use CB2 mode, difference is masked in the CB driver */ 1060 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); 1061 1062 for (i = 0; i < adapter->num_q_vectors; i++) { 1063 adapter->q_vector[i]->cpu = -1; 1064 ixgbe_update_dca(adapter->q_vector[i]); 1065 } 1066 } 1067 1068 static int __ixgbe_notify_dca(struct device *dev, void *data) 1069 { 1070 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1071 unsigned long event = *(unsigned long *)data; 1072 1073 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1074 return 0; 1075 1076 switch (event) { 1077 case DCA_PROVIDER_ADD: 1078 /* if we're already enabled, don't do it again */ 1079 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1080 break; 1081 if (dca_add_requester(dev) == 0) { 1082 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1083 ixgbe_setup_dca(adapter); 1084 break; 1085 } 1086 /* Fall Through since DCA is disabled. */ 1087 case DCA_PROVIDER_REMOVE: 1088 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1089 dca_remove_requester(dev); 1090 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1091 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); 1092 } 1093 break; 1094 } 1095 1096 return 0; 1097 } 1098 1099 #endif /* CONFIG_IXGBE_DCA */ 1100 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1101 union ixgbe_adv_rx_desc *rx_desc, 1102 struct sk_buff *skb) 1103 { 1104 if (ring->netdev->features & NETIF_F_RXHASH) 1105 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); 1106 } 1107 1108 #ifdef IXGBE_FCOE 1109 /** 1110 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1111 * @ring: structure containing ring specific data 1112 * @rx_desc: advanced rx descriptor 1113 * 1114 * Returns : true if it is FCoE pkt 1115 */ 1116 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1117 union ixgbe_adv_rx_desc *rx_desc) 1118 { 1119 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1120 1121 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1122 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1123 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1124 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1125 } 1126 1127 #endif /* IXGBE_FCOE */ 1128 /** 1129 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1130 * @ring: structure containing ring specific data 1131 * @rx_desc: current Rx descriptor being processed 1132 * @skb: skb currently being received and modified 1133 **/ 1134 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1135 union ixgbe_adv_rx_desc *rx_desc, 1136 struct sk_buff *skb) 1137 { 1138 skb_checksum_none_assert(skb); 1139 1140 /* Rx csum disabled */ 1141 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1142 return; 1143 1144 /* if IP and error */ 1145 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1146 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1147 ring->rx_stats.csum_err++; 1148 return; 1149 } 1150 1151 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1152 return; 1153 1154 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1155 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1156 1157 /* 1158 * 82599 errata, UDP frames with a 0 checksum can be marked as 1159 * checksum errors. 1160 */ 1161 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1162 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1163 return; 1164 1165 ring->rx_stats.csum_err++; 1166 return; 1167 } 1168 1169 /* It must be a TCP or UDP packet with a valid checksum */ 1170 skb->ip_summed = CHECKSUM_UNNECESSARY; 1171 } 1172 1173 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val) 1174 { 1175 rx_ring->next_to_use = val; 1176 1177 /* update next to alloc since we have filled the ring */ 1178 rx_ring->next_to_alloc = val; 1179 /* 1180 * Force memory writes to complete before letting h/w 1181 * know there are new descriptors to fetch. (Only 1182 * applicable for weak-ordered memory model archs, 1183 * such as IA-64). 1184 */ 1185 wmb(); 1186 writel(val, rx_ring->tail); 1187 } 1188 1189 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1190 struct ixgbe_rx_buffer *bi) 1191 { 1192 struct page *page = bi->page; 1193 dma_addr_t dma = bi->dma; 1194 1195 /* since we are recycling buffers we should seldom need to alloc */ 1196 if (likely(dma)) 1197 return true; 1198 1199 /* alloc new page for storage */ 1200 if (likely(!page)) { 1201 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP, 1202 bi->skb, ixgbe_rx_pg_order(rx_ring)); 1203 if (unlikely(!page)) { 1204 rx_ring->rx_stats.alloc_rx_page_failed++; 1205 return false; 1206 } 1207 bi->page = page; 1208 } 1209 1210 /* map page for use */ 1211 dma = dma_map_page(rx_ring->dev, page, 0, 1212 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); 1213 1214 /* 1215 * if mapping failed free memory back to system since 1216 * there isn't much point in holding memory we can't use 1217 */ 1218 if (dma_mapping_error(rx_ring->dev, dma)) { 1219 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1220 bi->page = NULL; 1221 1222 rx_ring->rx_stats.alloc_rx_page_failed++; 1223 return false; 1224 } 1225 1226 bi->dma = dma; 1227 bi->page_offset = 0; 1228 1229 return true; 1230 } 1231 1232 /** 1233 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1234 * @rx_ring: ring to place buffers on 1235 * @cleaned_count: number of buffers to replace 1236 **/ 1237 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1238 { 1239 union ixgbe_adv_rx_desc *rx_desc; 1240 struct ixgbe_rx_buffer *bi; 1241 u16 i = rx_ring->next_to_use; 1242 1243 /* nothing to do */ 1244 if (!cleaned_count) 1245 return; 1246 1247 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1248 bi = &rx_ring->rx_buffer_info[i]; 1249 i -= rx_ring->count; 1250 1251 do { 1252 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1253 break; 1254 1255 /* 1256 * Refresh the desc even if buffer_addrs didn't change 1257 * because each write-back erases this info. 1258 */ 1259 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1260 1261 rx_desc++; 1262 bi++; 1263 i++; 1264 if (unlikely(!i)) { 1265 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1266 bi = rx_ring->rx_buffer_info; 1267 i -= rx_ring->count; 1268 } 1269 1270 /* clear the hdr_addr for the next_to_use descriptor */ 1271 rx_desc->read.hdr_addr = 0; 1272 1273 cleaned_count--; 1274 } while (cleaned_count); 1275 1276 i += rx_ring->count; 1277 1278 if (rx_ring->next_to_use != i) 1279 ixgbe_release_rx_desc(rx_ring, i); 1280 } 1281 1282 /** 1283 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE 1284 * @data: pointer to the start of the headers 1285 * @max_len: total length of section to find headers in 1286 * 1287 * This function is meant to determine the length of headers that will 1288 * be recognized by hardware for LRO, GRO, and RSC offloads. The main 1289 * motivation of doing this is to only perform one pull for IPv4 TCP 1290 * packets so that we can do basic things like calculating the gso_size 1291 * based on the average data per packet. 1292 **/ 1293 static unsigned int ixgbe_get_headlen(unsigned char *data, 1294 unsigned int max_len) 1295 { 1296 union { 1297 unsigned char *network; 1298 /* l2 headers */ 1299 struct ethhdr *eth; 1300 struct vlan_hdr *vlan; 1301 /* l3 headers */ 1302 struct iphdr *ipv4; 1303 struct ipv6hdr *ipv6; 1304 } hdr; 1305 __be16 protocol; 1306 u8 nexthdr = 0; /* default to not TCP */ 1307 u8 hlen; 1308 1309 /* this should never happen, but better safe than sorry */ 1310 if (max_len < ETH_HLEN) 1311 return max_len; 1312 1313 /* initialize network frame pointer */ 1314 hdr.network = data; 1315 1316 /* set first protocol and move network header forward */ 1317 protocol = hdr.eth->h_proto; 1318 hdr.network += ETH_HLEN; 1319 1320 /* handle any vlan tag if present */ 1321 if (protocol == __constant_htons(ETH_P_8021Q)) { 1322 if ((hdr.network - data) > (max_len - VLAN_HLEN)) 1323 return max_len; 1324 1325 protocol = hdr.vlan->h_vlan_encapsulated_proto; 1326 hdr.network += VLAN_HLEN; 1327 } 1328 1329 /* handle L3 protocols */ 1330 if (protocol == __constant_htons(ETH_P_IP)) { 1331 if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) 1332 return max_len; 1333 1334 /* access ihl as a u8 to avoid unaligned access on ia64 */ 1335 hlen = (hdr.network[0] & 0x0F) << 2; 1336 1337 /* verify hlen meets minimum size requirements */ 1338 if (hlen < sizeof(struct iphdr)) 1339 return hdr.network - data; 1340 1341 /* record next protocol if header is present */ 1342 if (!hdr.ipv4->frag_off) 1343 nexthdr = hdr.ipv4->protocol; 1344 } else if (protocol == __constant_htons(ETH_P_IPV6)) { 1345 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr))) 1346 return max_len; 1347 1348 /* record next protocol */ 1349 nexthdr = hdr.ipv6->nexthdr; 1350 hlen = sizeof(struct ipv6hdr); 1351 #ifdef IXGBE_FCOE 1352 } else if (protocol == __constant_htons(ETH_P_FCOE)) { 1353 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN)) 1354 return max_len; 1355 hlen = FCOE_HEADER_LEN; 1356 #endif 1357 } else { 1358 return hdr.network - data; 1359 } 1360 1361 /* relocate pointer to start of L4 header */ 1362 hdr.network += hlen; 1363 1364 /* finally sort out TCP/UDP */ 1365 if (nexthdr == IPPROTO_TCP) { 1366 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) 1367 return max_len; 1368 1369 /* access doff as a u8 to avoid unaligned access on ia64 */ 1370 hlen = (hdr.network[12] & 0xF0) >> 2; 1371 1372 /* verify hlen meets minimum size requirements */ 1373 if (hlen < sizeof(struct tcphdr)) 1374 return hdr.network - data; 1375 1376 hdr.network += hlen; 1377 } else if (nexthdr == IPPROTO_UDP) { 1378 if ((hdr.network - data) > (max_len - sizeof(struct udphdr))) 1379 return max_len; 1380 1381 hdr.network += sizeof(struct udphdr); 1382 } 1383 1384 /* 1385 * If everything has gone correctly hdr.network should be the 1386 * data section of the packet and will be the end of the header. 1387 * If not then it probably represents the end of the last recognized 1388 * header. 1389 */ 1390 if ((hdr.network - data) < max_len) 1391 return hdr.network - data; 1392 else 1393 return max_len; 1394 } 1395 1396 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1397 struct sk_buff *skb) 1398 { 1399 u16 hdr_len = skb_headlen(skb); 1400 1401 /* set gso_size to avoid messing up TCP MSS */ 1402 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1403 IXGBE_CB(skb)->append_cnt); 1404 } 1405 1406 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1407 struct sk_buff *skb) 1408 { 1409 /* if append_cnt is 0 then frame is not RSC */ 1410 if (!IXGBE_CB(skb)->append_cnt) 1411 return; 1412 1413 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1414 rx_ring->rx_stats.rsc_flush++; 1415 1416 ixgbe_set_rsc_gso_size(rx_ring, skb); 1417 1418 /* gso_size is computed using append_cnt so always clear it last */ 1419 IXGBE_CB(skb)->append_cnt = 0; 1420 } 1421 1422 /** 1423 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1424 * @rx_ring: rx descriptor ring packet is being transacted on 1425 * @rx_desc: pointer to the EOP Rx descriptor 1426 * @skb: pointer to current skb being populated 1427 * 1428 * This function checks the ring, descriptor, and packet information in 1429 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1430 * other fields within the skb. 1431 **/ 1432 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1433 union ixgbe_adv_rx_desc *rx_desc, 1434 struct sk_buff *skb) 1435 { 1436 struct net_device *dev = rx_ring->netdev; 1437 1438 ixgbe_update_rsc_stats(rx_ring, skb); 1439 1440 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1441 1442 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1443 1444 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb); 1445 1446 if ((dev->features & NETIF_F_HW_VLAN_RX) && 1447 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1448 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1449 __vlan_hwaccel_put_tag(skb, vid); 1450 } 1451 1452 skb_record_rx_queue(skb, rx_ring->queue_index); 1453 1454 skb->protocol = eth_type_trans(skb, dev); 1455 } 1456 1457 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1458 struct sk_buff *skb) 1459 { 1460 struct ixgbe_adapter *adapter = q_vector->adapter; 1461 1462 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) 1463 napi_gro_receive(&q_vector->napi, skb); 1464 else 1465 netif_rx(skb); 1466 } 1467 1468 /** 1469 * ixgbe_is_non_eop - process handling of non-EOP buffers 1470 * @rx_ring: Rx ring being processed 1471 * @rx_desc: Rx descriptor for current buffer 1472 * @skb: Current socket buffer containing buffer in progress 1473 * 1474 * This function updates next to clean. If the buffer is an EOP buffer 1475 * this function exits returning false, otherwise it will place the 1476 * sk_buff in the next buffer to be chained and return true indicating 1477 * that this is in fact a non-EOP buffer. 1478 **/ 1479 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1480 union ixgbe_adv_rx_desc *rx_desc, 1481 struct sk_buff *skb) 1482 { 1483 u32 ntc = rx_ring->next_to_clean + 1; 1484 1485 /* fetch, update, and store next to clean */ 1486 ntc = (ntc < rx_ring->count) ? ntc : 0; 1487 rx_ring->next_to_clean = ntc; 1488 1489 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1490 1491 /* update RSC append count if present */ 1492 if (ring_is_rsc_enabled(rx_ring)) { 1493 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1494 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1495 1496 if (unlikely(rsc_enabled)) { 1497 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1498 1499 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1500 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1501 1502 /* update ntc based on RSC value */ 1503 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1504 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1505 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1506 } 1507 } 1508 1509 /* if we are the last buffer then there is nothing else to do */ 1510 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1511 return false; 1512 1513 /* place skb in next buffer to be received */ 1514 rx_ring->rx_buffer_info[ntc].skb = skb; 1515 rx_ring->rx_stats.non_eop_descs++; 1516 1517 return true; 1518 } 1519 1520 /** 1521 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1522 * @rx_ring: rx descriptor ring packet is being transacted on 1523 * @skb: pointer to current skb being adjusted 1524 * 1525 * This function is an ixgbe specific version of __pskb_pull_tail. The 1526 * main difference between this version and the original function is that 1527 * this function can make several assumptions about the state of things 1528 * that allow for significant optimizations versus the standard function. 1529 * As a result we can do things like drop a frag and maintain an accurate 1530 * truesize for the skb. 1531 */ 1532 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1533 struct sk_buff *skb) 1534 { 1535 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1536 unsigned char *va; 1537 unsigned int pull_len; 1538 1539 /* 1540 * it is valid to use page_address instead of kmap since we are 1541 * working with pages allocated out of the lomem pool per 1542 * alloc_page(GFP_ATOMIC) 1543 */ 1544 va = skb_frag_address(frag); 1545 1546 /* 1547 * we need the header to contain the greater of either ETH_HLEN or 1548 * 60 bytes if the skb->len is less than 60 for skb_pad. 1549 */ 1550 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE); 1551 1552 /* align pull length to size of long to optimize memcpy performance */ 1553 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1554 1555 /* update all of the pointers */ 1556 skb_frag_size_sub(frag, pull_len); 1557 frag->page_offset += pull_len; 1558 skb->data_len -= pull_len; 1559 skb->tail += pull_len; 1560 } 1561 1562 /** 1563 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1564 * @rx_ring: rx descriptor ring packet is being transacted on 1565 * @skb: pointer to current skb being updated 1566 * 1567 * This function provides a basic DMA sync up for the first fragment of an 1568 * skb. The reason for doing this is that the first fragment cannot be 1569 * unmapped until we have reached the end of packet descriptor for a buffer 1570 * chain. 1571 */ 1572 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1573 struct sk_buff *skb) 1574 { 1575 /* if the page was released unmap it, else just sync our portion */ 1576 if (unlikely(IXGBE_CB(skb)->page_released)) { 1577 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma, 1578 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); 1579 IXGBE_CB(skb)->page_released = false; 1580 } else { 1581 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1582 1583 dma_sync_single_range_for_cpu(rx_ring->dev, 1584 IXGBE_CB(skb)->dma, 1585 frag->page_offset, 1586 ixgbe_rx_bufsz(rx_ring), 1587 DMA_FROM_DEVICE); 1588 } 1589 IXGBE_CB(skb)->dma = 0; 1590 } 1591 1592 /** 1593 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1594 * @rx_ring: rx descriptor ring packet is being transacted on 1595 * @rx_desc: pointer to the EOP Rx descriptor 1596 * @skb: pointer to current skb being fixed 1597 * 1598 * Check for corrupted packet headers caused by senders on the local L2 1599 * embedded NIC switch not setting up their Tx Descriptors right. These 1600 * should be very rare. 1601 * 1602 * Also address the case where we are pulling data in on pages only 1603 * and as such no data is present in the skb header. 1604 * 1605 * In addition if skb is not at least 60 bytes we need to pad it so that 1606 * it is large enough to qualify as a valid Ethernet frame. 1607 * 1608 * Returns true if an error was encountered and skb was freed. 1609 **/ 1610 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1611 union ixgbe_adv_rx_desc *rx_desc, 1612 struct sk_buff *skb) 1613 { 1614 struct net_device *netdev = rx_ring->netdev; 1615 1616 /* verify that the packet does not have any known errors */ 1617 if (unlikely(ixgbe_test_staterr(rx_desc, 1618 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1619 !(netdev->features & NETIF_F_RXALL))) { 1620 dev_kfree_skb_any(skb); 1621 return true; 1622 } 1623 1624 /* place header in linear portion of buffer */ 1625 if (skb_is_nonlinear(skb)) 1626 ixgbe_pull_tail(rx_ring, skb); 1627 1628 #ifdef IXGBE_FCOE 1629 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1630 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1631 return false; 1632 1633 #endif 1634 /* if skb_pad returns an error the skb was freed */ 1635 if (unlikely(skb->len < 60)) { 1636 int pad_len = 60 - skb->len; 1637 1638 if (skb_pad(skb, pad_len)) 1639 return true; 1640 __skb_put(skb, pad_len); 1641 } 1642 1643 return false; 1644 } 1645 1646 /** 1647 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1648 * @rx_ring: rx descriptor ring to store buffers on 1649 * @old_buff: donor buffer to have page reused 1650 * 1651 * Synchronizes page for reuse by the adapter 1652 **/ 1653 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1654 struct ixgbe_rx_buffer *old_buff) 1655 { 1656 struct ixgbe_rx_buffer *new_buff; 1657 u16 nta = rx_ring->next_to_alloc; 1658 1659 new_buff = &rx_ring->rx_buffer_info[nta]; 1660 1661 /* update, and store next to alloc */ 1662 nta++; 1663 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1664 1665 /* transfer page from old buffer to new buffer */ 1666 new_buff->page = old_buff->page; 1667 new_buff->dma = old_buff->dma; 1668 new_buff->page_offset = old_buff->page_offset; 1669 1670 /* sync the buffer for use by the device */ 1671 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma, 1672 new_buff->page_offset, 1673 ixgbe_rx_bufsz(rx_ring), 1674 DMA_FROM_DEVICE); 1675 } 1676 1677 /** 1678 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 1679 * @rx_ring: rx descriptor ring to transact packets on 1680 * @rx_buffer: buffer containing page to add 1681 * @rx_desc: descriptor containing length of buffer written by hardware 1682 * @skb: sk_buff to place the data into 1683 * 1684 * This function will add the data contained in rx_buffer->page to the skb. 1685 * This is done either through a direct copy if the data in the buffer is 1686 * less than the skb header size, otherwise it will just attach the page as 1687 * a frag to the skb. 1688 * 1689 * The function will then update the page offset if necessary and return 1690 * true if the buffer can be reused by the adapter. 1691 **/ 1692 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 1693 struct ixgbe_rx_buffer *rx_buffer, 1694 union ixgbe_adv_rx_desc *rx_desc, 1695 struct sk_buff *skb) 1696 { 1697 struct page *page = rx_buffer->page; 1698 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 1699 #if (PAGE_SIZE < 8192) 1700 unsigned int truesize = ixgbe_rx_bufsz(rx_ring); 1701 #else 1702 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 1703 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) - 1704 ixgbe_rx_bufsz(rx_ring); 1705 #endif 1706 1707 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) { 1708 unsigned char *va = page_address(page) + rx_buffer->page_offset; 1709 1710 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 1711 1712 /* we can reuse buffer as-is, just make sure it is local */ 1713 if (likely(page_to_nid(page) == numa_node_id())) 1714 return true; 1715 1716 /* this page cannot be reused so discard it */ 1717 put_page(page); 1718 return false; 1719 } 1720 1721 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 1722 rx_buffer->page_offset, size, truesize); 1723 1724 /* avoid re-using remote pages */ 1725 if (unlikely(page_to_nid(page) != numa_node_id())) 1726 return false; 1727 1728 #if (PAGE_SIZE < 8192) 1729 /* if we are only owner of page we can reuse it */ 1730 if (unlikely(page_count(page) != 1)) 1731 return false; 1732 1733 /* flip page offset to other buffer */ 1734 rx_buffer->page_offset ^= truesize; 1735 1736 /* 1737 * since we are the only owner of the page and we need to 1738 * increment it, just set the value to 2 in order to avoid 1739 * an unecessary locked operation 1740 */ 1741 atomic_set(&page->_count, 2); 1742 #else 1743 /* move offset up to the next cache line */ 1744 rx_buffer->page_offset += truesize; 1745 1746 if (rx_buffer->page_offset > last_offset) 1747 return false; 1748 1749 /* bump ref count on page before it is given to the stack */ 1750 get_page(page); 1751 #endif 1752 1753 return true; 1754 } 1755 1756 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring, 1757 union ixgbe_adv_rx_desc *rx_desc) 1758 { 1759 struct ixgbe_rx_buffer *rx_buffer; 1760 struct sk_buff *skb; 1761 struct page *page; 1762 1763 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 1764 page = rx_buffer->page; 1765 prefetchw(page); 1766 1767 skb = rx_buffer->skb; 1768 1769 if (likely(!skb)) { 1770 void *page_addr = page_address(page) + 1771 rx_buffer->page_offset; 1772 1773 /* prefetch first cache line of first page */ 1774 prefetch(page_addr); 1775 #if L1_CACHE_BYTES < 128 1776 prefetch(page_addr + L1_CACHE_BYTES); 1777 #endif 1778 1779 /* allocate a skb to store the frags */ 1780 skb = netdev_alloc_skb_ip_align(rx_ring->netdev, 1781 IXGBE_RX_HDR_SIZE); 1782 if (unlikely(!skb)) { 1783 rx_ring->rx_stats.alloc_rx_buff_failed++; 1784 return NULL; 1785 } 1786 1787 /* 1788 * we will be copying header into skb->data in 1789 * pskb_may_pull so it is in our interest to prefetch 1790 * it now to avoid a possible cache miss 1791 */ 1792 prefetchw(skb->data); 1793 1794 /* 1795 * Delay unmapping of the first packet. It carries the 1796 * header information, HW may still access the header 1797 * after the writeback. Only unmap it when EOP is 1798 * reached 1799 */ 1800 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1801 goto dma_sync; 1802 1803 IXGBE_CB(skb)->dma = rx_buffer->dma; 1804 } else { 1805 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 1806 ixgbe_dma_sync_frag(rx_ring, skb); 1807 1808 dma_sync: 1809 /* we are reusing so sync this buffer for CPU use */ 1810 dma_sync_single_range_for_cpu(rx_ring->dev, 1811 rx_buffer->dma, 1812 rx_buffer->page_offset, 1813 ixgbe_rx_bufsz(rx_ring), 1814 DMA_FROM_DEVICE); 1815 } 1816 1817 /* pull page into skb */ 1818 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 1819 /* hand second half of page back to the ring */ 1820 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 1821 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) { 1822 /* the page has been released from the ring */ 1823 IXGBE_CB(skb)->page_released = true; 1824 } else { 1825 /* we are not reusing the buffer so unmap it */ 1826 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 1827 ixgbe_rx_pg_size(rx_ring), 1828 DMA_FROM_DEVICE); 1829 } 1830 1831 /* clear contents of buffer_info */ 1832 rx_buffer->skb = NULL; 1833 rx_buffer->dma = 0; 1834 rx_buffer->page = NULL; 1835 1836 return skb; 1837 } 1838 1839 /** 1840 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 1841 * @q_vector: structure containing interrupt and ring information 1842 * @rx_ring: rx descriptor ring to transact packets on 1843 * @budget: Total limit on number of packets to process 1844 * 1845 * This function provides a "bounce buffer" approach to Rx interrupt 1846 * processing. The advantage to this is that on systems that have 1847 * expensive overhead for IOMMU access this provides a means of avoiding 1848 * it by maintaining the mapping of the page to the syste. 1849 * 1850 * Returns true if all work is completed without reaching budget 1851 **/ 1852 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 1853 struct ixgbe_ring *rx_ring, 1854 const int budget) 1855 { 1856 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1857 #ifdef IXGBE_FCOE 1858 struct ixgbe_adapter *adapter = q_vector->adapter; 1859 int ddp_bytes; 1860 unsigned int mss = 0; 1861 #endif /* IXGBE_FCOE */ 1862 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 1863 1864 do { 1865 union ixgbe_adv_rx_desc *rx_desc; 1866 struct sk_buff *skb; 1867 1868 /* return some buffers to hardware, one at a time is too slow */ 1869 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 1870 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 1871 cleaned_count = 0; 1872 } 1873 1874 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 1875 1876 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) 1877 break; 1878 1879 /* 1880 * This memory barrier is needed to keep us from reading 1881 * any other fields out of the rx_desc until we know the 1882 * RXD_STAT_DD bit is set 1883 */ 1884 rmb(); 1885 1886 /* retrieve a buffer from the ring */ 1887 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc); 1888 1889 /* exit if we failed to retrieve a buffer */ 1890 if (!skb) 1891 break; 1892 1893 cleaned_count++; 1894 1895 /* place incomplete frames back on ring for completion */ 1896 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 1897 continue; 1898 1899 /* verify the packet layout is correct */ 1900 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 1901 continue; 1902 1903 /* probably a little skewed due to removing CRC */ 1904 total_rx_bytes += skb->len; 1905 1906 /* populate checksum, timestamp, VLAN, and protocol */ 1907 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 1908 1909 #ifdef IXGBE_FCOE 1910 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 1911 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 1912 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 1913 /* include DDPed FCoE data */ 1914 if (ddp_bytes > 0) { 1915 if (!mss) { 1916 mss = rx_ring->netdev->mtu - 1917 sizeof(struct fcoe_hdr) - 1918 sizeof(struct fc_frame_header) - 1919 sizeof(struct fcoe_crc_eof); 1920 if (mss > 512) 1921 mss &= ~511; 1922 } 1923 total_rx_bytes += ddp_bytes; 1924 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 1925 mss); 1926 } 1927 if (!ddp_bytes) { 1928 dev_kfree_skb_any(skb); 1929 continue; 1930 } 1931 } 1932 1933 #endif /* IXGBE_FCOE */ 1934 ixgbe_rx_skb(q_vector, skb); 1935 1936 /* update budget accounting */ 1937 total_rx_packets++; 1938 } while (likely(total_rx_packets < budget)); 1939 1940 u64_stats_update_begin(&rx_ring->syncp); 1941 rx_ring->stats.packets += total_rx_packets; 1942 rx_ring->stats.bytes += total_rx_bytes; 1943 u64_stats_update_end(&rx_ring->syncp); 1944 q_vector->rx.total_packets += total_rx_packets; 1945 q_vector->rx.total_bytes += total_rx_bytes; 1946 1947 if (cleaned_count) 1948 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 1949 1950 return (total_rx_packets < budget); 1951 } 1952 1953 /** 1954 * ixgbe_configure_msix - Configure MSI-X hardware 1955 * @adapter: board private structure 1956 * 1957 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 1958 * interrupts. 1959 **/ 1960 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 1961 { 1962 struct ixgbe_q_vector *q_vector; 1963 int v_idx; 1964 u32 mask; 1965 1966 /* Populate MSIX to EITR Select */ 1967 if (adapter->num_vfs > 32) { 1968 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; 1969 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 1970 } 1971 1972 /* 1973 * Populate the IVAR table and set the ITR values to the 1974 * corresponding register. 1975 */ 1976 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 1977 struct ixgbe_ring *ring; 1978 q_vector = adapter->q_vector[v_idx]; 1979 1980 ixgbe_for_each_ring(ring, q_vector->rx) 1981 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 1982 1983 ixgbe_for_each_ring(ring, q_vector->tx) 1984 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 1985 1986 ixgbe_write_eitr(q_vector); 1987 } 1988 1989 switch (adapter->hw.mac.type) { 1990 case ixgbe_mac_82598EB: 1991 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 1992 v_idx); 1993 break; 1994 case ixgbe_mac_82599EB: 1995 case ixgbe_mac_X540: 1996 ixgbe_set_ivar(adapter, -1, 1, v_idx); 1997 break; 1998 default: 1999 break; 2000 } 2001 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2002 2003 /* set up to autoclear timer, and the vectors */ 2004 mask = IXGBE_EIMS_ENABLE_MASK; 2005 mask &= ~(IXGBE_EIMS_OTHER | 2006 IXGBE_EIMS_MAILBOX | 2007 IXGBE_EIMS_LSC); 2008 2009 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2010 } 2011 2012 enum latency_range { 2013 lowest_latency = 0, 2014 low_latency = 1, 2015 bulk_latency = 2, 2016 latency_invalid = 255 2017 }; 2018 2019 /** 2020 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2021 * @q_vector: structure containing interrupt and ring information 2022 * @ring_container: structure containing ring performance data 2023 * 2024 * Stores a new ITR value based on packets and byte 2025 * counts during the last interrupt. The advantage of per interrupt 2026 * computation is faster updates and more accurate ITR for the current 2027 * traffic pattern. Constants in this function were computed 2028 * based on theoretical maximum wire speed and thresholds were set based 2029 * on testing data as well as attempting to minimize response time 2030 * while increasing bulk throughput. 2031 * this functionality is controlled by the InterruptThrottleRate module 2032 * parameter (see ixgbe_param.c) 2033 **/ 2034 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2035 struct ixgbe_ring_container *ring_container) 2036 { 2037 int bytes = ring_container->total_bytes; 2038 int packets = ring_container->total_packets; 2039 u32 timepassed_us; 2040 u64 bytes_perint; 2041 u8 itr_setting = ring_container->itr; 2042 2043 if (packets == 0) 2044 return; 2045 2046 /* simple throttlerate management 2047 * 0-10MB/s lowest (100000 ints/s) 2048 * 10-20MB/s low (20000 ints/s) 2049 * 20-1249MB/s bulk (8000 ints/s) 2050 */ 2051 /* what was last interrupt timeslice? */ 2052 timepassed_us = q_vector->itr >> 2; 2053 bytes_perint = bytes / timepassed_us; /* bytes/usec */ 2054 2055 switch (itr_setting) { 2056 case lowest_latency: 2057 if (bytes_perint > 10) 2058 itr_setting = low_latency; 2059 break; 2060 case low_latency: 2061 if (bytes_perint > 20) 2062 itr_setting = bulk_latency; 2063 else if (bytes_perint <= 10) 2064 itr_setting = lowest_latency; 2065 break; 2066 case bulk_latency: 2067 if (bytes_perint <= 20) 2068 itr_setting = low_latency; 2069 break; 2070 } 2071 2072 /* clear work counters since we have the values we need */ 2073 ring_container->total_bytes = 0; 2074 ring_container->total_packets = 0; 2075 2076 /* write updated itr to ring container */ 2077 ring_container->itr = itr_setting; 2078 } 2079 2080 /** 2081 * ixgbe_write_eitr - write EITR register in hardware specific way 2082 * @q_vector: structure containing interrupt and ring information 2083 * 2084 * This function is made to be called by ethtool and by the driver 2085 * when it needs to update EITR registers at runtime. Hardware 2086 * specific quirks/differences are taken care of here. 2087 */ 2088 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2089 { 2090 struct ixgbe_adapter *adapter = q_vector->adapter; 2091 struct ixgbe_hw *hw = &adapter->hw; 2092 int v_idx = q_vector->v_idx; 2093 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2094 2095 switch (adapter->hw.mac.type) { 2096 case ixgbe_mac_82598EB: 2097 /* must write high and low 16 bits to reset counter */ 2098 itr_reg |= (itr_reg << 16); 2099 break; 2100 case ixgbe_mac_82599EB: 2101 case ixgbe_mac_X540: 2102 /* 2103 * set the WDIS bit to not clear the timer bits and cause an 2104 * immediate assertion of the interrupt 2105 */ 2106 itr_reg |= IXGBE_EITR_CNT_WDIS; 2107 break; 2108 default: 2109 break; 2110 } 2111 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2112 } 2113 2114 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2115 { 2116 u32 new_itr = q_vector->itr; 2117 u8 current_itr; 2118 2119 ixgbe_update_itr(q_vector, &q_vector->tx); 2120 ixgbe_update_itr(q_vector, &q_vector->rx); 2121 2122 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 2123 2124 switch (current_itr) { 2125 /* counts and packets in update_itr are dependent on these numbers */ 2126 case lowest_latency: 2127 new_itr = IXGBE_100K_ITR; 2128 break; 2129 case low_latency: 2130 new_itr = IXGBE_20K_ITR; 2131 break; 2132 case bulk_latency: 2133 new_itr = IXGBE_8K_ITR; 2134 break; 2135 default: 2136 break; 2137 } 2138 2139 if (new_itr != q_vector->itr) { 2140 /* do an exponential smoothing */ 2141 new_itr = (10 * new_itr * q_vector->itr) / 2142 ((9 * new_itr) + q_vector->itr); 2143 2144 /* save the algorithm value here */ 2145 q_vector->itr = new_itr; 2146 2147 ixgbe_write_eitr(q_vector); 2148 } 2149 } 2150 2151 /** 2152 * ixgbe_check_overtemp_subtask - check for over temperature 2153 * @adapter: pointer to adapter 2154 **/ 2155 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2156 { 2157 struct ixgbe_hw *hw = &adapter->hw; 2158 u32 eicr = adapter->interrupt_event; 2159 2160 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2161 return; 2162 2163 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && 2164 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2165 return; 2166 2167 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2168 2169 switch (hw->device_id) { 2170 case IXGBE_DEV_ID_82599_T3_LOM: 2171 /* 2172 * Since the warning interrupt is for both ports 2173 * we don't have to check if: 2174 * - This interrupt wasn't for our port. 2175 * - We may have missed the interrupt so always have to 2176 * check if we got a LSC 2177 */ 2178 if (!(eicr & IXGBE_EICR_GPI_SDP0) && 2179 !(eicr & IXGBE_EICR_LSC)) 2180 return; 2181 2182 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2183 u32 autoneg; 2184 bool link_up = false; 2185 2186 hw->mac.ops.check_link(hw, &autoneg, &link_up, false); 2187 2188 if (link_up) 2189 return; 2190 } 2191 2192 /* Check if this is not due to overtemp */ 2193 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) 2194 return; 2195 2196 break; 2197 default: 2198 if (!(eicr & IXGBE_EICR_GPI_SDP0)) 2199 return; 2200 break; 2201 } 2202 e_crit(drv, 2203 "Network adapter has been stopped because it has over heated. " 2204 "Restart the computer. If the problem persists, " 2205 "power off the system and replace the adapter\n"); 2206 2207 adapter->interrupt_event = 0; 2208 } 2209 2210 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2211 { 2212 struct ixgbe_hw *hw = &adapter->hw; 2213 2214 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2215 (eicr & IXGBE_EICR_GPI_SDP1)) { 2216 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2217 /* write to clear the interrupt */ 2218 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); 2219 } 2220 } 2221 2222 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2223 { 2224 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2225 return; 2226 2227 switch (adapter->hw.mac.type) { 2228 case ixgbe_mac_82599EB: 2229 /* 2230 * Need to check link state so complete overtemp check 2231 * on service task 2232 */ 2233 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) && 2234 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2235 adapter->interrupt_event = eicr; 2236 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2237 ixgbe_service_event_schedule(adapter); 2238 return; 2239 } 2240 return; 2241 case ixgbe_mac_X540: 2242 if (!(eicr & IXGBE_EICR_TS)) 2243 return; 2244 break; 2245 default: 2246 return; 2247 } 2248 2249 e_crit(drv, 2250 "Network adapter has been stopped because it has over heated. " 2251 "Restart the computer. If the problem persists, " 2252 "power off the system and replace the adapter\n"); 2253 } 2254 2255 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2256 { 2257 struct ixgbe_hw *hw = &adapter->hw; 2258 2259 if (eicr & IXGBE_EICR_GPI_SDP2) { 2260 /* Clear the interrupt */ 2261 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); 2262 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2263 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2264 ixgbe_service_event_schedule(adapter); 2265 } 2266 } 2267 2268 if (eicr & IXGBE_EICR_GPI_SDP1) { 2269 /* Clear the interrupt */ 2270 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); 2271 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2272 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2273 ixgbe_service_event_schedule(adapter); 2274 } 2275 } 2276 } 2277 2278 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2279 { 2280 struct ixgbe_hw *hw = &adapter->hw; 2281 2282 adapter->lsc_int++; 2283 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2284 adapter->link_check_timeout = jiffies; 2285 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2286 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2287 IXGBE_WRITE_FLUSH(hw); 2288 ixgbe_service_event_schedule(adapter); 2289 } 2290 } 2291 2292 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2293 u64 qmask) 2294 { 2295 u32 mask; 2296 struct ixgbe_hw *hw = &adapter->hw; 2297 2298 switch (hw->mac.type) { 2299 case ixgbe_mac_82598EB: 2300 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2301 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2302 break; 2303 case ixgbe_mac_82599EB: 2304 case ixgbe_mac_X540: 2305 mask = (qmask & 0xFFFFFFFF); 2306 if (mask) 2307 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2308 mask = (qmask >> 32); 2309 if (mask) 2310 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2311 break; 2312 default: 2313 break; 2314 } 2315 /* skip the flush */ 2316 } 2317 2318 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, 2319 u64 qmask) 2320 { 2321 u32 mask; 2322 struct ixgbe_hw *hw = &adapter->hw; 2323 2324 switch (hw->mac.type) { 2325 case ixgbe_mac_82598EB: 2326 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2327 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 2328 break; 2329 case ixgbe_mac_82599EB: 2330 case ixgbe_mac_X540: 2331 mask = (qmask & 0xFFFFFFFF); 2332 if (mask) 2333 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 2334 mask = (qmask >> 32); 2335 if (mask) 2336 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 2337 break; 2338 default: 2339 break; 2340 } 2341 /* skip the flush */ 2342 } 2343 2344 /** 2345 * ixgbe_irq_enable - Enable default interrupt generation settings 2346 * @adapter: board private structure 2347 **/ 2348 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 2349 bool flush) 2350 { 2351 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 2352 2353 /* don't reenable LSC while waiting for link */ 2354 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 2355 mask &= ~IXGBE_EIMS_LSC; 2356 2357 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 2358 switch (adapter->hw.mac.type) { 2359 case ixgbe_mac_82599EB: 2360 mask |= IXGBE_EIMS_GPI_SDP0; 2361 break; 2362 case ixgbe_mac_X540: 2363 mask |= IXGBE_EIMS_TS; 2364 break; 2365 default: 2366 break; 2367 } 2368 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 2369 mask |= IXGBE_EIMS_GPI_SDP1; 2370 switch (adapter->hw.mac.type) { 2371 case ixgbe_mac_82599EB: 2372 mask |= IXGBE_EIMS_GPI_SDP1; 2373 mask |= IXGBE_EIMS_GPI_SDP2; 2374 case ixgbe_mac_X540: 2375 mask |= IXGBE_EIMS_ECC; 2376 mask |= IXGBE_EIMS_MAILBOX; 2377 break; 2378 default: 2379 break; 2380 } 2381 2382 if (adapter->hw.mac.type == ixgbe_mac_X540) 2383 mask |= IXGBE_EIMS_TIMESYNC; 2384 2385 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 2386 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 2387 mask |= IXGBE_EIMS_FLOW_DIR; 2388 2389 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 2390 if (queues) 2391 ixgbe_irq_enable_queues(adapter, ~0); 2392 if (flush) 2393 IXGBE_WRITE_FLUSH(&adapter->hw); 2394 } 2395 2396 static irqreturn_t ixgbe_msix_other(int irq, void *data) 2397 { 2398 struct ixgbe_adapter *adapter = data; 2399 struct ixgbe_hw *hw = &adapter->hw; 2400 u32 eicr; 2401 2402 /* 2403 * Workaround for Silicon errata. Use clear-by-write instead 2404 * of clear-by-read. Reading with EICS will return the 2405 * interrupt causes without clearing, which later be done 2406 * with the write to EICR. 2407 */ 2408 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 2409 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 2410 2411 if (eicr & IXGBE_EICR_LSC) 2412 ixgbe_check_lsc(adapter); 2413 2414 if (eicr & IXGBE_EICR_MAILBOX) 2415 ixgbe_msg_task(adapter); 2416 2417 switch (hw->mac.type) { 2418 case ixgbe_mac_82599EB: 2419 case ixgbe_mac_X540: 2420 if (eicr & IXGBE_EICR_ECC) 2421 e_info(link, "Received unrecoverable ECC Err, please " 2422 "reboot\n"); 2423 /* Handle Flow Director Full threshold interrupt */ 2424 if (eicr & IXGBE_EICR_FLOW_DIR) { 2425 int reinit_count = 0; 2426 int i; 2427 for (i = 0; i < adapter->num_tx_queues; i++) { 2428 struct ixgbe_ring *ring = adapter->tx_ring[i]; 2429 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 2430 &ring->state)) 2431 reinit_count++; 2432 } 2433 if (reinit_count) { 2434 /* no more flow director interrupts until after init */ 2435 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 2436 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 2437 ixgbe_service_event_schedule(adapter); 2438 } 2439 } 2440 ixgbe_check_sfp_event(adapter, eicr); 2441 ixgbe_check_overtemp_event(adapter, eicr); 2442 break; 2443 default: 2444 break; 2445 } 2446 2447 ixgbe_check_fan_failure(adapter, eicr); 2448 2449 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 2450 ixgbe_ptp_check_pps_event(adapter, eicr); 2451 2452 /* re-enable the original interrupt state, no lsc, no queues */ 2453 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2454 ixgbe_irq_enable(adapter, false, false); 2455 2456 return IRQ_HANDLED; 2457 } 2458 2459 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 2460 { 2461 struct ixgbe_q_vector *q_vector = data; 2462 2463 /* EIAM disabled interrupts (on this vector) for us */ 2464 2465 if (q_vector->rx.ring || q_vector->tx.ring) 2466 napi_schedule(&q_vector->napi); 2467 2468 return IRQ_HANDLED; 2469 } 2470 2471 /** 2472 * ixgbe_poll - NAPI Rx polling callback 2473 * @napi: structure for representing this polling device 2474 * @budget: how many packets driver is allowed to clean 2475 * 2476 * This function is used for legacy and MSI, NAPI mode 2477 **/ 2478 int ixgbe_poll(struct napi_struct *napi, int budget) 2479 { 2480 struct ixgbe_q_vector *q_vector = 2481 container_of(napi, struct ixgbe_q_vector, napi); 2482 struct ixgbe_adapter *adapter = q_vector->adapter; 2483 struct ixgbe_ring *ring; 2484 int per_ring_budget; 2485 bool clean_complete = true; 2486 2487 #ifdef CONFIG_IXGBE_DCA 2488 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 2489 ixgbe_update_dca(q_vector); 2490 #endif 2491 2492 ixgbe_for_each_ring(ring, q_vector->tx) 2493 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring); 2494 2495 /* attempt to distribute budget to each queue fairly, but don't allow 2496 * the budget to go below 1 because we'll exit polling */ 2497 if (q_vector->rx.count > 1) 2498 per_ring_budget = max(budget/q_vector->rx.count, 1); 2499 else 2500 per_ring_budget = budget; 2501 2502 ixgbe_for_each_ring(ring, q_vector->rx) 2503 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring, 2504 per_ring_budget); 2505 2506 /* If all work not completed, return budget and keep polling */ 2507 if (!clean_complete) 2508 return budget; 2509 2510 /* all work done, exit the polling mode */ 2511 napi_complete(napi); 2512 if (adapter->rx_itr_setting & 1) 2513 ixgbe_set_itr(q_vector); 2514 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2515 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); 2516 2517 return 0; 2518 } 2519 2520 /** 2521 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 2522 * @adapter: board private structure 2523 * 2524 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 2525 * interrupts from the kernel. 2526 **/ 2527 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 2528 { 2529 struct net_device *netdev = adapter->netdev; 2530 int vector, err; 2531 int ri = 0, ti = 0; 2532 2533 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 2534 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 2535 struct msix_entry *entry = &adapter->msix_entries[vector]; 2536 2537 if (q_vector->tx.ring && q_vector->rx.ring) { 2538 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2539 "%s-%s-%d", netdev->name, "TxRx", ri++); 2540 ti++; 2541 } else if (q_vector->rx.ring) { 2542 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2543 "%s-%s-%d", netdev->name, "rx", ri++); 2544 } else if (q_vector->tx.ring) { 2545 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2546 "%s-%s-%d", netdev->name, "tx", ti++); 2547 } else { 2548 /* skip this unused q_vector */ 2549 continue; 2550 } 2551 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 2552 q_vector->name, q_vector); 2553 if (err) { 2554 e_err(probe, "request_irq failed for MSIX interrupt " 2555 "Error: %d\n", err); 2556 goto free_queue_irqs; 2557 } 2558 /* If Flow Director is enabled, set interrupt affinity */ 2559 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 2560 /* assign the mask for this irq */ 2561 irq_set_affinity_hint(entry->vector, 2562 &q_vector->affinity_mask); 2563 } 2564 } 2565 2566 err = request_irq(adapter->msix_entries[vector].vector, 2567 ixgbe_msix_other, 0, netdev->name, adapter); 2568 if (err) { 2569 e_err(probe, "request_irq for msix_other failed: %d\n", err); 2570 goto free_queue_irqs; 2571 } 2572 2573 return 0; 2574 2575 free_queue_irqs: 2576 while (vector) { 2577 vector--; 2578 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 2579 NULL); 2580 free_irq(adapter->msix_entries[vector].vector, 2581 adapter->q_vector[vector]); 2582 } 2583 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 2584 pci_disable_msix(adapter->pdev); 2585 kfree(adapter->msix_entries); 2586 adapter->msix_entries = NULL; 2587 return err; 2588 } 2589 2590 /** 2591 * ixgbe_intr - legacy mode Interrupt Handler 2592 * @irq: interrupt number 2593 * @data: pointer to a network interface device structure 2594 **/ 2595 static irqreturn_t ixgbe_intr(int irq, void *data) 2596 { 2597 struct ixgbe_adapter *adapter = data; 2598 struct ixgbe_hw *hw = &adapter->hw; 2599 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 2600 u32 eicr; 2601 2602 /* 2603 * Workaround for silicon errata #26 on 82598. Mask the interrupt 2604 * before the read of EICR. 2605 */ 2606 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 2607 2608 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 2609 * therefore no explicit interrupt disable is necessary */ 2610 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 2611 if (!eicr) { 2612 /* 2613 * shared interrupt alert! 2614 * make sure interrupts are enabled because the read will 2615 * have disabled interrupts due to EIAM 2616 * finish the workaround of silicon errata on 82598. Unmask 2617 * the interrupt that we masked before the EICR read. 2618 */ 2619 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2620 ixgbe_irq_enable(adapter, true, true); 2621 return IRQ_NONE; /* Not our interrupt */ 2622 } 2623 2624 if (eicr & IXGBE_EICR_LSC) 2625 ixgbe_check_lsc(adapter); 2626 2627 switch (hw->mac.type) { 2628 case ixgbe_mac_82599EB: 2629 ixgbe_check_sfp_event(adapter, eicr); 2630 /* Fall through */ 2631 case ixgbe_mac_X540: 2632 if (eicr & IXGBE_EICR_ECC) 2633 e_info(link, "Received unrecoverable ECC err, please " 2634 "reboot\n"); 2635 ixgbe_check_overtemp_event(adapter, eicr); 2636 break; 2637 default: 2638 break; 2639 } 2640 2641 ixgbe_check_fan_failure(adapter, eicr); 2642 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 2643 ixgbe_ptp_check_pps_event(adapter, eicr); 2644 2645 /* would disable interrupts here but EIAM disabled it */ 2646 napi_schedule(&q_vector->napi); 2647 2648 /* 2649 * re-enable link(maybe) and non-queue interrupts, no flush. 2650 * ixgbe_poll will re-enable the queue interrupts 2651 */ 2652 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2653 ixgbe_irq_enable(adapter, false, false); 2654 2655 return IRQ_HANDLED; 2656 } 2657 2658 /** 2659 * ixgbe_request_irq - initialize interrupts 2660 * @adapter: board private structure 2661 * 2662 * Attempts to configure interrupts using the best available 2663 * capabilities of the hardware and kernel. 2664 **/ 2665 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 2666 { 2667 struct net_device *netdev = adapter->netdev; 2668 int err; 2669 2670 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 2671 err = ixgbe_request_msix_irqs(adapter); 2672 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 2673 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 2674 netdev->name, adapter); 2675 else 2676 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 2677 netdev->name, adapter); 2678 2679 if (err) 2680 e_err(probe, "request_irq failed, Error %d\n", err); 2681 2682 return err; 2683 } 2684 2685 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 2686 { 2687 int vector; 2688 2689 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 2690 free_irq(adapter->pdev->irq, adapter); 2691 return; 2692 } 2693 2694 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 2695 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 2696 struct msix_entry *entry = &adapter->msix_entries[vector]; 2697 2698 /* free only the irqs that were actually requested */ 2699 if (!q_vector->rx.ring && !q_vector->tx.ring) 2700 continue; 2701 2702 /* clear the affinity_mask in the IRQ descriptor */ 2703 irq_set_affinity_hint(entry->vector, NULL); 2704 2705 free_irq(entry->vector, q_vector); 2706 } 2707 2708 free_irq(adapter->msix_entries[vector++].vector, adapter); 2709 } 2710 2711 /** 2712 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 2713 * @adapter: board private structure 2714 **/ 2715 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 2716 { 2717 switch (adapter->hw.mac.type) { 2718 case ixgbe_mac_82598EB: 2719 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 2720 break; 2721 case ixgbe_mac_82599EB: 2722 case ixgbe_mac_X540: 2723 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 2724 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 2725 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 2726 break; 2727 default: 2728 break; 2729 } 2730 IXGBE_WRITE_FLUSH(&adapter->hw); 2731 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 2732 int vector; 2733 2734 for (vector = 0; vector < adapter->num_q_vectors; vector++) 2735 synchronize_irq(adapter->msix_entries[vector].vector); 2736 2737 synchronize_irq(adapter->msix_entries[vector++].vector); 2738 } else { 2739 synchronize_irq(adapter->pdev->irq); 2740 } 2741 } 2742 2743 /** 2744 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 2745 * 2746 **/ 2747 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 2748 { 2749 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 2750 2751 ixgbe_write_eitr(q_vector); 2752 2753 ixgbe_set_ivar(adapter, 0, 0, 0); 2754 ixgbe_set_ivar(adapter, 1, 0, 0); 2755 2756 e_info(hw, "Legacy interrupt IVAR setup done\n"); 2757 } 2758 2759 /** 2760 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 2761 * @adapter: board private structure 2762 * @ring: structure containing ring specific data 2763 * 2764 * Configure the Tx descriptor ring after a reset. 2765 **/ 2766 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 2767 struct ixgbe_ring *ring) 2768 { 2769 struct ixgbe_hw *hw = &adapter->hw; 2770 u64 tdba = ring->dma; 2771 int wait_loop = 10; 2772 u32 txdctl = IXGBE_TXDCTL_ENABLE; 2773 u8 reg_idx = ring->reg_idx; 2774 2775 /* disable queue to avoid issues while updating state */ 2776 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 2777 IXGBE_WRITE_FLUSH(hw); 2778 2779 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 2780 (tdba & DMA_BIT_MASK(32))); 2781 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 2782 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 2783 ring->count * sizeof(union ixgbe_adv_tx_desc)); 2784 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 2785 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 2786 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx); 2787 2788 /* 2789 * set WTHRESH to encourage burst writeback, it should not be set 2790 * higher than 1 when ITR is 0 as it could cause false TX hangs 2791 * 2792 * In order to avoid issues WTHRESH + PTHRESH should always be equal 2793 * to or less than the number of on chip descriptors, which is 2794 * currently 40. 2795 */ 2796 if (!ring->q_vector || (ring->q_vector->itr < 8)) 2797 txdctl |= (1 << 16); /* WTHRESH = 1 */ 2798 else 2799 txdctl |= (8 << 16); /* WTHRESH = 8 */ 2800 2801 /* 2802 * Setting PTHRESH to 32 both improves performance 2803 * and avoids a TX hang with DFP enabled 2804 */ 2805 txdctl |= (1 << 8) | /* HTHRESH = 1 */ 2806 32; /* PTHRESH = 32 */ 2807 2808 /* reinitialize flowdirector state */ 2809 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 2810 ring->atr_sample_rate = adapter->atr_sample_rate; 2811 ring->atr_count = 0; 2812 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 2813 } else { 2814 ring->atr_sample_rate = 0; 2815 } 2816 2817 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 2818 2819 /* enable queue */ 2820 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 2821 2822 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 2823 if (hw->mac.type == ixgbe_mac_82598EB && 2824 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 2825 return; 2826 2827 /* poll to verify queue is enabled */ 2828 do { 2829 usleep_range(1000, 2000); 2830 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 2831 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 2832 if (!wait_loop) 2833 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx); 2834 } 2835 2836 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 2837 { 2838 struct ixgbe_hw *hw = &adapter->hw; 2839 u32 rttdcs, mtqc; 2840 u8 tcs = netdev_get_num_tc(adapter->netdev); 2841 2842 if (hw->mac.type == ixgbe_mac_82598EB) 2843 return; 2844 2845 /* disable the arbiter while setting MTQC */ 2846 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 2847 rttdcs |= IXGBE_RTTDCS_ARBDIS; 2848 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 2849 2850 /* set transmit pool layout */ 2851 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 2852 mtqc = IXGBE_MTQC_VT_ENA; 2853 if (tcs > 4) 2854 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 2855 else if (tcs > 1) 2856 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 2857 else if (adapter->ring_feature[RING_F_RSS].indices == 4) 2858 mtqc |= IXGBE_MTQC_32VF; 2859 else 2860 mtqc |= IXGBE_MTQC_64VF; 2861 } else { 2862 if (tcs > 4) 2863 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 2864 else if (tcs > 1) 2865 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 2866 else 2867 mtqc = IXGBE_MTQC_64Q_1PB; 2868 } 2869 2870 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 2871 2872 /* Enable Security TX Buffer IFG for multiple pb */ 2873 if (tcs) { 2874 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 2875 sectx |= IXGBE_SECTX_DCB; 2876 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 2877 } 2878 2879 /* re-enable the arbiter */ 2880 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 2881 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 2882 } 2883 2884 /** 2885 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 2886 * @adapter: board private structure 2887 * 2888 * Configure the Tx unit of the MAC after a reset. 2889 **/ 2890 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 2891 { 2892 struct ixgbe_hw *hw = &adapter->hw; 2893 u32 dmatxctl; 2894 u32 i; 2895 2896 ixgbe_setup_mtqc(adapter); 2897 2898 if (hw->mac.type != ixgbe_mac_82598EB) { 2899 /* DMATXCTL.EN must be before Tx queues are enabled */ 2900 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2901 dmatxctl |= IXGBE_DMATXCTL_TE; 2902 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 2903 } 2904 2905 /* Setup the HW Tx Head and Tail descriptor pointers */ 2906 for (i = 0; i < adapter->num_tx_queues; i++) 2907 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 2908 } 2909 2910 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 2911 struct ixgbe_ring *ring) 2912 { 2913 struct ixgbe_hw *hw = &adapter->hw; 2914 u8 reg_idx = ring->reg_idx; 2915 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 2916 2917 srrctl |= IXGBE_SRRCTL_DROP_EN; 2918 2919 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 2920 } 2921 2922 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 2923 struct ixgbe_ring *ring) 2924 { 2925 struct ixgbe_hw *hw = &adapter->hw; 2926 u8 reg_idx = ring->reg_idx; 2927 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 2928 2929 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 2930 2931 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 2932 } 2933 2934 #ifdef CONFIG_IXGBE_DCB 2935 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 2936 #else 2937 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 2938 #endif 2939 { 2940 int i; 2941 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 2942 2943 if (adapter->ixgbe_ieee_pfc) 2944 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 2945 2946 /* 2947 * We should set the drop enable bit if: 2948 * SR-IOV is enabled 2949 * or 2950 * Number of Rx queues > 1 and flow control is disabled 2951 * 2952 * This allows us to avoid head of line blocking for security 2953 * and performance reasons. 2954 */ 2955 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 2956 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 2957 for (i = 0; i < adapter->num_rx_queues; i++) 2958 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 2959 } else { 2960 for (i = 0; i < adapter->num_rx_queues; i++) 2961 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 2962 } 2963 } 2964 2965 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 2966 2967 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 2968 struct ixgbe_ring *rx_ring) 2969 { 2970 struct ixgbe_hw *hw = &adapter->hw; 2971 u32 srrctl; 2972 u8 reg_idx = rx_ring->reg_idx; 2973 2974 if (hw->mac.type == ixgbe_mac_82598EB) { 2975 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 2976 2977 /* 2978 * if VMDq is not active we must program one srrctl register 2979 * per RSS queue since we have enabled RDRXCTL.MVMEN 2980 */ 2981 reg_idx &= mask; 2982 } 2983 2984 /* configure header buffer length, needed for RSC */ 2985 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 2986 2987 /* configure the packet buffer length */ 2988 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 2989 2990 /* configure descriptor type */ 2991 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 2992 2993 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 2994 } 2995 2996 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 2997 { 2998 struct ixgbe_hw *hw = &adapter->hw; 2999 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, 3000 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, 3001 0x6A3E67EA, 0x14364D17, 0x3BED200D}; 3002 u32 mrqc = 0, reta = 0; 3003 u32 rxcsum; 3004 int i, j; 3005 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3006 3007 /* 3008 * Program table for at least 2 queues w/ SR-IOV so that VFs can 3009 * make full use of any rings they may have. We will use the 3010 * PSRTYPE register to control how many rings we use within the PF. 3011 */ 3012 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2)) 3013 rss_i = 2; 3014 3015 /* Fill out hash function seeds */ 3016 for (i = 0; i < 10; i++) 3017 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); 3018 3019 /* Fill out redirection table */ 3020 for (i = 0, j = 0; i < 128; i++, j++) { 3021 if (j == rss_i) 3022 j = 0; 3023 /* reta = 4-byte sliding window of 3024 * 0x00..(indices-1)(indices-1)00..etc. */ 3025 reta = (reta << 8) | (j * 0x11); 3026 if ((i & 3) == 3) 3027 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3028 } 3029 3030 /* Disable indicating checksum in descriptor, enables RSS hash */ 3031 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3032 rxcsum |= IXGBE_RXCSUM_PCSD; 3033 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3034 3035 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3036 if (adapter->ring_feature[RING_F_RSS].mask) 3037 mrqc = IXGBE_MRQC_RSSEN; 3038 } else { 3039 u8 tcs = netdev_get_num_tc(adapter->netdev); 3040 3041 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3042 if (tcs > 4) 3043 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3044 else if (tcs > 1) 3045 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3046 else if (adapter->ring_feature[RING_F_RSS].indices == 4) 3047 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3048 else 3049 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3050 } else { 3051 if (tcs > 4) 3052 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3053 else if (tcs > 1) 3054 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3055 else 3056 mrqc = IXGBE_MRQC_RSSEN; 3057 } 3058 } 3059 3060 /* Perform hash on these packet types */ 3061 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3062 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3063 IXGBE_MRQC_RSS_FIELD_IPV6 | 3064 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3065 3066 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3067 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3068 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3069 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3070 3071 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3072 } 3073 3074 /** 3075 * ixgbe_configure_rscctl - enable RSC for the indicated ring 3076 * @adapter: address of board private structure 3077 * @index: index of ring to set 3078 **/ 3079 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 3080 struct ixgbe_ring *ring) 3081 { 3082 struct ixgbe_hw *hw = &adapter->hw; 3083 u32 rscctrl; 3084 u8 reg_idx = ring->reg_idx; 3085 3086 if (!ring_is_rsc_enabled(ring)) 3087 return; 3088 3089 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 3090 rscctrl |= IXGBE_RSCCTL_RSCEN; 3091 /* 3092 * we must limit the number of descriptors so that the 3093 * total size of max desc * buf_len is not greater 3094 * than 65536 3095 */ 3096 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 3097 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 3098 } 3099 3100 #define IXGBE_MAX_RX_DESC_POLL 10 3101 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 3102 struct ixgbe_ring *ring) 3103 { 3104 struct ixgbe_hw *hw = &adapter->hw; 3105 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 3106 u32 rxdctl; 3107 u8 reg_idx = ring->reg_idx; 3108 3109 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3110 if (hw->mac.type == ixgbe_mac_82598EB && 3111 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3112 return; 3113 3114 do { 3115 usleep_range(1000, 2000); 3116 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3117 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 3118 3119 if (!wait_loop) { 3120 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 3121 "the polling period\n", reg_idx); 3122 } 3123 } 3124 3125 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, 3126 struct ixgbe_ring *ring) 3127 { 3128 struct ixgbe_hw *hw = &adapter->hw; 3129 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 3130 u32 rxdctl; 3131 u8 reg_idx = ring->reg_idx; 3132 3133 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3134 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 3135 3136 /* write value back with RXDCTL.ENABLE bit cleared */ 3137 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 3138 3139 if (hw->mac.type == ixgbe_mac_82598EB && 3140 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3141 return; 3142 3143 /* the hardware may take up to 100us to really disable the rx queue */ 3144 do { 3145 udelay(10); 3146 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3147 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); 3148 3149 if (!wait_loop) { 3150 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " 3151 "the polling period\n", reg_idx); 3152 } 3153 } 3154 3155 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 3156 struct ixgbe_ring *ring) 3157 { 3158 struct ixgbe_hw *hw = &adapter->hw; 3159 u64 rdba = ring->dma; 3160 u32 rxdctl; 3161 u8 reg_idx = ring->reg_idx; 3162 3163 /* disable queue to avoid issues while updating state */ 3164 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3165 ixgbe_disable_rx_queue(adapter, ring); 3166 3167 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 3168 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 3169 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 3170 ring->count * sizeof(union ixgbe_adv_rx_desc)); 3171 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 3172 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 3173 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx); 3174 3175 ixgbe_configure_srrctl(adapter, ring); 3176 ixgbe_configure_rscctl(adapter, ring); 3177 3178 if (hw->mac.type == ixgbe_mac_82598EB) { 3179 /* 3180 * enable cache line friendly hardware writes: 3181 * PTHRESH=32 descriptors (half the internal cache), 3182 * this also removes ugly rx_no_buffer_count increment 3183 * HTHRESH=4 descriptors (to minimize latency on fetch) 3184 * WTHRESH=8 burst writeback up to two cache lines 3185 */ 3186 rxdctl &= ~0x3FFFFF; 3187 rxdctl |= 0x080420; 3188 } 3189 3190 /* enable receive descriptor ring */ 3191 rxdctl |= IXGBE_RXDCTL_ENABLE; 3192 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 3193 3194 ixgbe_rx_desc_queue_enable(adapter, ring); 3195 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 3196 } 3197 3198 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 3199 { 3200 struct ixgbe_hw *hw = &adapter->hw; 3201 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 3202 int p; 3203 3204 /* PSRTYPE must be initialized in non 82598 adapters */ 3205 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 3206 IXGBE_PSRTYPE_UDPHDR | 3207 IXGBE_PSRTYPE_IPV4HDR | 3208 IXGBE_PSRTYPE_L2HDR | 3209 IXGBE_PSRTYPE_IPV6HDR; 3210 3211 if (hw->mac.type == ixgbe_mac_82598EB) 3212 return; 3213 3214 if (rss_i > 3) 3215 psrtype |= 2 << 29; 3216 else if (rss_i > 1) 3217 psrtype |= 1 << 29; 3218 3219 for (p = 0; p < adapter->num_rx_pools; p++) 3220 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)), 3221 psrtype); 3222 } 3223 3224 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 3225 { 3226 struct ixgbe_hw *hw = &adapter->hw; 3227 u32 reg_offset, vf_shift; 3228 u32 gcr_ext, vmdctl; 3229 int i; 3230 3231 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 3232 return; 3233 3234 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 3235 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 3236 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 3237 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 3238 vmdctl |= IXGBE_VT_CTL_REPLEN; 3239 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 3240 3241 vf_shift = VMDQ_P(0) % 32; 3242 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 3243 3244 /* Enable only the PF's pool for Tx/Rx */ 3245 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift); 3246 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 3247 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift); 3248 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 3249 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB) 3250 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 3251 3252 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 3253 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 3254 3255 /* 3256 * Set up VF register offsets for selected VT Mode, 3257 * i.e. 32 or 64 VFs for SR-IOV 3258 */ 3259 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 3260 case IXGBE_82599_VMDQ_8Q_MASK: 3261 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 3262 break; 3263 case IXGBE_82599_VMDQ_4Q_MASK: 3264 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 3265 break; 3266 default: 3267 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 3268 break; 3269 } 3270 3271 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 3272 3273 3274 /* Enable MAC Anti-Spoofing */ 3275 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0), 3276 adapter->num_vfs); 3277 /* For VFs that have spoof checking turned off */ 3278 for (i = 0; i < adapter->num_vfs; i++) { 3279 if (!adapter->vfinfo[i].spoofchk_enabled) 3280 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false); 3281 } 3282 } 3283 3284 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 3285 { 3286 struct ixgbe_hw *hw = &adapter->hw; 3287 struct net_device *netdev = adapter->netdev; 3288 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 3289 struct ixgbe_ring *rx_ring; 3290 int i; 3291 u32 mhadd, hlreg0; 3292 3293 #ifdef IXGBE_FCOE 3294 /* adjust max frame to be able to do baby jumbo for FCoE */ 3295 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 3296 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 3297 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 3298 3299 #endif /* IXGBE_FCOE */ 3300 3301 /* adjust max frame to be at least the size of a standard frame */ 3302 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 3303 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 3304 3305 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 3306 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 3307 mhadd &= ~IXGBE_MHADD_MFS_MASK; 3308 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 3309 3310 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 3311 } 3312 3313 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3314 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 3315 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 3316 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3317 3318 /* 3319 * Setup the HW Rx Head and Tail Descriptor Pointers and 3320 * the Base and Length of the Rx Descriptor Ring 3321 */ 3322 for (i = 0; i < adapter->num_rx_queues; i++) { 3323 rx_ring = adapter->rx_ring[i]; 3324 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 3325 set_ring_rsc_enabled(rx_ring); 3326 else 3327 clear_ring_rsc_enabled(rx_ring); 3328 } 3329 } 3330 3331 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 3332 { 3333 struct ixgbe_hw *hw = &adapter->hw; 3334 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 3335 3336 switch (hw->mac.type) { 3337 case ixgbe_mac_82598EB: 3338 /* 3339 * For VMDq support of different descriptor types or 3340 * buffer sizes through the use of multiple SRRCTL 3341 * registers, RDRXCTL.MVMEN must be set to 1 3342 * 3343 * also, the manual doesn't mention it clearly but DCA hints 3344 * will only use queue 0's tags unless this bit is set. Side 3345 * effects of setting this bit are only that SRRCTL must be 3346 * fully programmed [0..15] 3347 */ 3348 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 3349 break; 3350 case ixgbe_mac_82599EB: 3351 case ixgbe_mac_X540: 3352 /* Disable RSC for ACK packets */ 3353 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 3354 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 3355 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 3356 /* hardware requires some bits to be set by default */ 3357 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 3358 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 3359 break; 3360 default: 3361 /* We should do nothing since we don't know this hardware */ 3362 return; 3363 } 3364 3365 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 3366 } 3367 3368 /** 3369 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 3370 * @adapter: board private structure 3371 * 3372 * Configure the Rx unit of the MAC after a reset. 3373 **/ 3374 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 3375 { 3376 struct ixgbe_hw *hw = &adapter->hw; 3377 int i; 3378 u32 rxctrl; 3379 3380 /* disable receives while setting up the descriptors */ 3381 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 3382 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); 3383 3384 ixgbe_setup_psrtype(adapter); 3385 ixgbe_setup_rdrxctl(adapter); 3386 3387 /* Program registers for the distribution of queues */ 3388 ixgbe_setup_mrqc(adapter); 3389 3390 /* set_rx_buffer_len must be called before ring initialization */ 3391 ixgbe_set_rx_buffer_len(adapter); 3392 3393 /* 3394 * Setup the HW Rx Head and Tail Descriptor Pointers and 3395 * the Base and Length of the Rx Descriptor Ring 3396 */ 3397 for (i = 0; i < adapter->num_rx_queues; i++) 3398 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 3399 3400 /* disable drop enable for 82598 parts */ 3401 if (hw->mac.type == ixgbe_mac_82598EB) 3402 rxctrl |= IXGBE_RXCTRL_DMBYPS; 3403 3404 /* enable all receives */ 3405 rxctrl |= IXGBE_RXCTRL_RXEN; 3406 hw->mac.ops.enable_rx_dma(hw, rxctrl); 3407 } 3408 3409 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) 3410 { 3411 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3412 struct ixgbe_hw *hw = &adapter->hw; 3413 3414 /* add VID to filter table */ 3415 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true); 3416 set_bit(vid, adapter->active_vlans); 3417 3418 return 0; 3419 } 3420 3421 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) 3422 { 3423 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3424 struct ixgbe_hw *hw = &adapter->hw; 3425 3426 /* remove VID from filter table */ 3427 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false); 3428 clear_bit(vid, adapter->active_vlans); 3429 3430 return 0; 3431 } 3432 3433 /** 3434 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering 3435 * @adapter: driver data 3436 */ 3437 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter) 3438 { 3439 struct ixgbe_hw *hw = &adapter->hw; 3440 u32 vlnctrl; 3441 3442 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 3443 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); 3444 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 3445 } 3446 3447 /** 3448 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering 3449 * @adapter: driver data 3450 */ 3451 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter) 3452 { 3453 struct ixgbe_hw *hw = &adapter->hw; 3454 u32 vlnctrl; 3455 3456 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 3457 vlnctrl |= IXGBE_VLNCTRL_VFE; 3458 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; 3459 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 3460 } 3461 3462 /** 3463 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 3464 * @adapter: driver data 3465 */ 3466 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 3467 { 3468 struct ixgbe_hw *hw = &adapter->hw; 3469 u32 vlnctrl; 3470 int i, j; 3471 3472 switch (hw->mac.type) { 3473 case ixgbe_mac_82598EB: 3474 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 3475 vlnctrl &= ~IXGBE_VLNCTRL_VME; 3476 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 3477 break; 3478 case ixgbe_mac_82599EB: 3479 case ixgbe_mac_X540: 3480 for (i = 0; i < adapter->num_rx_queues; i++) { 3481 j = adapter->rx_ring[i]->reg_idx; 3482 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 3483 vlnctrl &= ~IXGBE_RXDCTL_VME; 3484 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 3485 } 3486 break; 3487 default: 3488 break; 3489 } 3490 } 3491 3492 /** 3493 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 3494 * @adapter: driver data 3495 */ 3496 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 3497 { 3498 struct ixgbe_hw *hw = &adapter->hw; 3499 u32 vlnctrl; 3500 int i, j; 3501 3502 switch (hw->mac.type) { 3503 case ixgbe_mac_82598EB: 3504 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 3505 vlnctrl |= IXGBE_VLNCTRL_VME; 3506 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 3507 break; 3508 case ixgbe_mac_82599EB: 3509 case ixgbe_mac_X540: 3510 for (i = 0; i < adapter->num_rx_queues; i++) { 3511 j = adapter->rx_ring[i]->reg_idx; 3512 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 3513 vlnctrl |= IXGBE_RXDCTL_VME; 3514 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 3515 } 3516 break; 3517 default: 3518 break; 3519 } 3520 } 3521 3522 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 3523 { 3524 u16 vid; 3525 3526 ixgbe_vlan_rx_add_vid(adapter->netdev, 0); 3527 3528 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 3529 ixgbe_vlan_rx_add_vid(adapter->netdev, vid); 3530 } 3531 3532 /** 3533 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table 3534 * @netdev: network interface device structure 3535 * 3536 * Writes unicast address list to the RAR table. 3537 * Returns: -ENOMEM on failure/insufficient address space 3538 * 0 on no addresses written 3539 * X on writing X addresses to the RAR table 3540 **/ 3541 static int ixgbe_write_uc_addr_list(struct net_device *netdev) 3542 { 3543 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3544 struct ixgbe_hw *hw = &adapter->hw; 3545 unsigned int rar_entries = hw->mac.num_rar_entries - 1; 3546 int count = 0; 3547 3548 /* In SR-IOV mode significantly less RAR entries are available */ 3549 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3550 rar_entries = IXGBE_MAX_PF_MACVLANS - 1; 3551 3552 /* return ENOMEM indicating insufficient memory for addresses */ 3553 if (netdev_uc_count(netdev) > rar_entries) 3554 return -ENOMEM; 3555 3556 if (!netdev_uc_empty(netdev)) { 3557 struct netdev_hw_addr *ha; 3558 /* return error if we do not support writing to RAR table */ 3559 if (!hw->mac.ops.set_rar) 3560 return -ENOMEM; 3561 3562 netdev_for_each_uc_addr(ha, netdev) { 3563 if (!rar_entries) 3564 break; 3565 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr, 3566 VMDQ_P(0), IXGBE_RAH_AV); 3567 count++; 3568 } 3569 } 3570 /* write the addresses in reverse order to avoid write combining */ 3571 for (; rar_entries > 0 ; rar_entries--) 3572 hw->mac.ops.clear_rar(hw, rar_entries); 3573 3574 return count; 3575 } 3576 3577 /** 3578 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 3579 * @netdev: network interface device structure 3580 * 3581 * The set_rx_method entry point is called whenever the unicast/multicast 3582 * address list or the network interface flags are updated. This routine is 3583 * responsible for configuring the hardware for proper unicast, multicast and 3584 * promiscuous mode. 3585 **/ 3586 void ixgbe_set_rx_mode(struct net_device *netdev) 3587 { 3588 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3589 struct ixgbe_hw *hw = &adapter->hw; 3590 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 3591 int count; 3592 3593 /* Check for Promiscuous and All Multicast modes */ 3594 3595 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 3596 3597 /* set all bits that we expect to always be set */ 3598 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 3599 fctrl |= IXGBE_FCTRL_BAM; 3600 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 3601 fctrl |= IXGBE_FCTRL_PMCF; 3602 3603 /* clear the bits we are changing the status of */ 3604 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 3605 3606 if (netdev->flags & IFF_PROMISC) { 3607 hw->addr_ctrl.user_set_promisc = true; 3608 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 3609 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE); 3610 /* don't hardware filter vlans in promisc mode */ 3611 ixgbe_vlan_filter_disable(adapter); 3612 } else { 3613 if (netdev->flags & IFF_ALLMULTI) { 3614 fctrl |= IXGBE_FCTRL_MPE; 3615 vmolr |= IXGBE_VMOLR_MPE; 3616 } else { 3617 /* 3618 * Write addresses to the MTA, if the attempt fails 3619 * then we should just turn on promiscuous mode so 3620 * that we can at least receive multicast traffic 3621 */ 3622 hw->mac.ops.update_mc_addr_list(hw, netdev); 3623 vmolr |= IXGBE_VMOLR_ROMPE; 3624 } 3625 ixgbe_vlan_filter_enable(adapter); 3626 hw->addr_ctrl.user_set_promisc = false; 3627 } 3628 3629 /* 3630 * Write addresses to available RAR registers, if there is not 3631 * sufficient space to store all the addresses then enable 3632 * unicast promiscuous mode 3633 */ 3634 count = ixgbe_write_uc_addr_list(netdev); 3635 if (count < 0) { 3636 fctrl |= IXGBE_FCTRL_UPE; 3637 vmolr |= IXGBE_VMOLR_ROPE; 3638 } 3639 3640 if (adapter->num_vfs) 3641 ixgbe_restore_vf_multicasts(adapter); 3642 3643 if (hw->mac.type != ixgbe_mac_82598EB) { 3644 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 3645 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 3646 IXGBE_VMOLR_ROPE); 3647 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 3648 } 3649 3650 /* This is useful for sniffing bad packets. */ 3651 if (adapter->netdev->features & NETIF_F_RXALL) { 3652 /* UPE and MPE will be handled by normal PROMISC logic 3653 * in e1000e_set_rx_mode */ 3654 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 3655 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 3656 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 3657 3658 fctrl &= ~(IXGBE_FCTRL_DPF); 3659 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 3660 } 3661 3662 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 3663 3664 if (netdev->features & NETIF_F_HW_VLAN_RX) 3665 ixgbe_vlan_strip_enable(adapter); 3666 else 3667 ixgbe_vlan_strip_disable(adapter); 3668 } 3669 3670 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 3671 { 3672 int q_idx; 3673 3674 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 3675 napi_enable(&adapter->q_vector[q_idx]->napi); 3676 } 3677 3678 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 3679 { 3680 int q_idx; 3681 3682 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 3683 napi_disable(&adapter->q_vector[q_idx]->napi); 3684 } 3685 3686 #ifdef CONFIG_IXGBE_DCB 3687 /** 3688 * ixgbe_configure_dcb - Configure DCB hardware 3689 * @adapter: ixgbe adapter struct 3690 * 3691 * This is called by the driver on open to configure the DCB hardware. 3692 * This is also called by the gennetlink interface when reconfiguring 3693 * the DCB state. 3694 */ 3695 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 3696 { 3697 struct ixgbe_hw *hw = &adapter->hw; 3698 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 3699 3700 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 3701 if (hw->mac.type == ixgbe_mac_82598EB) 3702 netif_set_gso_max_size(adapter->netdev, 65536); 3703 return; 3704 } 3705 3706 if (hw->mac.type == ixgbe_mac_82598EB) 3707 netif_set_gso_max_size(adapter->netdev, 32768); 3708 3709 #ifdef IXGBE_FCOE 3710 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 3711 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 3712 #endif 3713 3714 /* reconfigure the hardware */ 3715 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 3716 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 3717 DCB_TX_CONFIG); 3718 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 3719 DCB_RX_CONFIG); 3720 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 3721 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 3722 ixgbe_dcb_hw_ets(&adapter->hw, 3723 adapter->ixgbe_ieee_ets, 3724 max_frame); 3725 ixgbe_dcb_hw_pfc_config(&adapter->hw, 3726 adapter->ixgbe_ieee_pfc->pfc_en, 3727 adapter->ixgbe_ieee_ets->prio_tc); 3728 } 3729 3730 /* Enable RSS Hash per TC */ 3731 if (hw->mac.type != ixgbe_mac_82598EB) { 3732 u32 msb = 0; 3733 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 3734 3735 while (rss_i) { 3736 msb++; 3737 rss_i >>= 1; 3738 } 3739 3740 /* write msb to all 8 TCs in one write */ 3741 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 3742 } 3743 } 3744 #endif 3745 3746 /* Additional bittime to account for IXGBE framing */ 3747 #define IXGBE_ETH_FRAMING 20 3748 3749 /** 3750 * ixgbe_hpbthresh - calculate high water mark for flow control 3751 * 3752 * @adapter: board private structure to calculate for 3753 * @pb: packet buffer to calculate 3754 */ 3755 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 3756 { 3757 struct ixgbe_hw *hw = &adapter->hw; 3758 struct net_device *dev = adapter->netdev; 3759 int link, tc, kb, marker; 3760 u32 dv_id, rx_pba; 3761 3762 /* Calculate max LAN frame size */ 3763 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 3764 3765 #ifdef IXGBE_FCOE 3766 /* FCoE traffic class uses FCOE jumbo frames */ 3767 if ((dev->features & NETIF_F_FCOE_MTU) && 3768 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 3769 (pb == ixgbe_fcoe_get_tc(adapter))) 3770 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 3771 3772 #endif 3773 /* Calculate delay value for device */ 3774 switch (hw->mac.type) { 3775 case ixgbe_mac_X540: 3776 dv_id = IXGBE_DV_X540(link, tc); 3777 break; 3778 default: 3779 dv_id = IXGBE_DV(link, tc); 3780 break; 3781 } 3782 3783 /* Loopback switch introduces additional latency */ 3784 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3785 dv_id += IXGBE_B2BT(tc); 3786 3787 /* Delay value is calculated in bit times convert to KB */ 3788 kb = IXGBE_BT2KB(dv_id); 3789 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 3790 3791 marker = rx_pba - kb; 3792 3793 /* It is possible that the packet buffer is not large enough 3794 * to provide required headroom. In this case throw an error 3795 * to user and a do the best we can. 3796 */ 3797 if (marker < 0) { 3798 e_warn(drv, "Packet Buffer(%i) can not provide enough" 3799 "headroom to support flow control." 3800 "Decrease MTU or number of traffic classes\n", pb); 3801 marker = tc + 1; 3802 } 3803 3804 return marker; 3805 } 3806 3807 /** 3808 * ixgbe_lpbthresh - calculate low water mark for for flow control 3809 * 3810 * @adapter: board private structure to calculate for 3811 * @pb: packet buffer to calculate 3812 */ 3813 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter) 3814 { 3815 struct ixgbe_hw *hw = &adapter->hw; 3816 struct net_device *dev = adapter->netdev; 3817 int tc; 3818 u32 dv_id; 3819 3820 /* Calculate max LAN frame size */ 3821 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 3822 3823 /* Calculate delay value for device */ 3824 switch (hw->mac.type) { 3825 case ixgbe_mac_X540: 3826 dv_id = IXGBE_LOW_DV_X540(tc); 3827 break; 3828 default: 3829 dv_id = IXGBE_LOW_DV(tc); 3830 break; 3831 } 3832 3833 /* Delay value is calculated in bit times convert to KB */ 3834 return IXGBE_BT2KB(dv_id); 3835 } 3836 3837 /* 3838 * ixgbe_pbthresh_setup - calculate and setup high low water marks 3839 */ 3840 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 3841 { 3842 struct ixgbe_hw *hw = &adapter->hw; 3843 int num_tc = netdev_get_num_tc(adapter->netdev); 3844 int i; 3845 3846 if (!num_tc) 3847 num_tc = 1; 3848 3849 hw->fc.low_water = ixgbe_lpbthresh(adapter); 3850 3851 for (i = 0; i < num_tc; i++) { 3852 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 3853 3854 /* Low water marks must not be larger than high water marks */ 3855 if (hw->fc.low_water > hw->fc.high_water[i]) 3856 hw->fc.low_water = 0; 3857 } 3858 } 3859 3860 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 3861 { 3862 struct ixgbe_hw *hw = &adapter->hw; 3863 int hdrm; 3864 u8 tc = netdev_get_num_tc(adapter->netdev); 3865 3866 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 3867 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 3868 hdrm = 32 << adapter->fdir_pballoc; 3869 else 3870 hdrm = 0; 3871 3872 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 3873 ixgbe_pbthresh_setup(adapter); 3874 } 3875 3876 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 3877 { 3878 struct ixgbe_hw *hw = &adapter->hw; 3879 struct hlist_node *node, *node2; 3880 struct ixgbe_fdir_filter *filter; 3881 3882 spin_lock(&adapter->fdir_perfect_lock); 3883 3884 if (!hlist_empty(&adapter->fdir_filter_list)) 3885 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 3886 3887 hlist_for_each_entry_safe(filter, node, node2, 3888 &adapter->fdir_filter_list, fdir_node) { 3889 ixgbe_fdir_write_perfect_filter_82599(hw, 3890 &filter->filter, 3891 filter->sw_idx, 3892 (filter->action == IXGBE_FDIR_DROP_QUEUE) ? 3893 IXGBE_FDIR_DROP_QUEUE : 3894 adapter->rx_ring[filter->action]->reg_idx); 3895 } 3896 3897 spin_unlock(&adapter->fdir_perfect_lock); 3898 } 3899 3900 static void ixgbe_configure(struct ixgbe_adapter *adapter) 3901 { 3902 struct ixgbe_hw *hw = &adapter->hw; 3903 3904 ixgbe_configure_pb(adapter); 3905 #ifdef CONFIG_IXGBE_DCB 3906 ixgbe_configure_dcb(adapter); 3907 #endif 3908 /* 3909 * We must restore virtualization before VLANs or else 3910 * the VLVF registers will not be populated 3911 */ 3912 ixgbe_configure_virtualization(adapter); 3913 3914 ixgbe_set_rx_mode(adapter->netdev); 3915 ixgbe_restore_vlan(adapter); 3916 3917 switch (hw->mac.type) { 3918 case ixgbe_mac_82599EB: 3919 case ixgbe_mac_X540: 3920 hw->mac.ops.disable_rx_buff(hw); 3921 break; 3922 default: 3923 break; 3924 } 3925 3926 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3927 ixgbe_init_fdir_signature_82599(&adapter->hw, 3928 adapter->fdir_pballoc); 3929 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 3930 ixgbe_init_fdir_perfect_82599(&adapter->hw, 3931 adapter->fdir_pballoc); 3932 ixgbe_fdir_filter_restore(adapter); 3933 } 3934 3935 switch (hw->mac.type) { 3936 case ixgbe_mac_82599EB: 3937 case ixgbe_mac_X540: 3938 hw->mac.ops.enable_rx_buff(hw); 3939 break; 3940 default: 3941 break; 3942 } 3943 3944 #ifdef IXGBE_FCOE 3945 /* configure FCoE L2 filters, redirection table, and Rx control */ 3946 ixgbe_configure_fcoe(adapter); 3947 3948 #endif /* IXGBE_FCOE */ 3949 ixgbe_configure_tx(adapter); 3950 ixgbe_configure_rx(adapter); 3951 } 3952 3953 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 3954 { 3955 switch (hw->phy.type) { 3956 case ixgbe_phy_sfp_avago: 3957 case ixgbe_phy_sfp_ftl: 3958 case ixgbe_phy_sfp_intel: 3959 case ixgbe_phy_sfp_unknown: 3960 case ixgbe_phy_sfp_passive_tyco: 3961 case ixgbe_phy_sfp_passive_unknown: 3962 case ixgbe_phy_sfp_active_unknown: 3963 case ixgbe_phy_sfp_ftl_active: 3964 return true; 3965 case ixgbe_phy_nl: 3966 if (hw->mac.type == ixgbe_mac_82598EB) 3967 return true; 3968 default: 3969 return false; 3970 } 3971 } 3972 3973 /** 3974 * ixgbe_sfp_link_config - set up SFP+ link 3975 * @adapter: pointer to private adapter struct 3976 **/ 3977 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 3978 { 3979 /* 3980 * We are assuming the worst case scenario here, and that 3981 * is that an SFP was inserted/removed after the reset 3982 * but before SFP detection was enabled. As such the best 3983 * solution is to just start searching as soon as we start 3984 */ 3985 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3986 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 3987 3988 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 3989 } 3990 3991 /** 3992 * ixgbe_non_sfp_link_config - set up non-SFP+ link 3993 * @hw: pointer to private hardware struct 3994 * 3995 * Returns 0 on success, negative on failure 3996 **/ 3997 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 3998 { 3999 u32 autoneg; 4000 bool negotiation, link_up = false; 4001 u32 ret = IXGBE_ERR_LINK_SETUP; 4002 4003 if (hw->mac.ops.check_link) 4004 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); 4005 4006 if (ret) 4007 goto link_cfg_out; 4008 4009 autoneg = hw->phy.autoneg_advertised; 4010 if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) 4011 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, 4012 &negotiation); 4013 if (ret) 4014 goto link_cfg_out; 4015 4016 if (hw->mac.ops.setup_link) 4017 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up); 4018 link_cfg_out: 4019 return ret; 4020 } 4021 4022 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 4023 { 4024 struct ixgbe_hw *hw = &adapter->hw; 4025 u32 gpie = 0; 4026 4027 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 4028 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 4029 IXGBE_GPIE_OCD; 4030 gpie |= IXGBE_GPIE_EIAME; 4031 /* 4032 * use EIAM to auto-mask when MSI-X interrupt is asserted 4033 * this saves a register write for every interrupt 4034 */ 4035 switch (hw->mac.type) { 4036 case ixgbe_mac_82598EB: 4037 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 4038 break; 4039 case ixgbe_mac_82599EB: 4040 case ixgbe_mac_X540: 4041 default: 4042 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 4043 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 4044 break; 4045 } 4046 } else { 4047 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 4048 * specifically only auto mask tx and rx interrupts */ 4049 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 4050 } 4051 4052 /* XXX: to interrupt immediately for EICS writes, enable this */ 4053 /* gpie |= IXGBE_GPIE_EIMEN; */ 4054 4055 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 4056 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 4057 4058 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4059 case IXGBE_82599_VMDQ_8Q_MASK: 4060 gpie |= IXGBE_GPIE_VTMODE_16; 4061 break; 4062 case IXGBE_82599_VMDQ_4Q_MASK: 4063 gpie |= IXGBE_GPIE_VTMODE_32; 4064 break; 4065 default: 4066 gpie |= IXGBE_GPIE_VTMODE_64; 4067 break; 4068 } 4069 } 4070 4071 /* Enable Thermal over heat sensor interrupt */ 4072 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 4073 switch (adapter->hw.mac.type) { 4074 case ixgbe_mac_82599EB: 4075 gpie |= IXGBE_SDP0_GPIEN; 4076 break; 4077 case ixgbe_mac_X540: 4078 gpie |= IXGBE_EIMS_TS; 4079 break; 4080 default: 4081 break; 4082 } 4083 } 4084 4085 /* Enable fan failure interrupt */ 4086 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 4087 gpie |= IXGBE_SDP1_GPIEN; 4088 4089 if (hw->mac.type == ixgbe_mac_82599EB) { 4090 gpie |= IXGBE_SDP1_GPIEN; 4091 gpie |= IXGBE_SDP2_GPIEN; 4092 } 4093 4094 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 4095 } 4096 4097 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 4098 { 4099 struct ixgbe_hw *hw = &adapter->hw; 4100 int err; 4101 u32 ctrl_ext; 4102 4103 ixgbe_get_hw_control(adapter); 4104 ixgbe_setup_gpie(adapter); 4105 4106 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 4107 ixgbe_configure_msix(adapter); 4108 else 4109 ixgbe_configure_msi_and_legacy(adapter); 4110 4111 /* enable the optics for 82599 SFP+ fiber */ 4112 if (hw->mac.ops.enable_tx_laser) 4113 hw->mac.ops.enable_tx_laser(hw); 4114 4115 clear_bit(__IXGBE_DOWN, &adapter->state); 4116 ixgbe_napi_enable_all(adapter); 4117 4118 if (ixgbe_is_sfp(hw)) { 4119 ixgbe_sfp_link_config(adapter); 4120 } else { 4121 err = ixgbe_non_sfp_link_config(hw); 4122 if (err) 4123 e_err(probe, "link_config FAILED %d\n", err); 4124 } 4125 4126 /* clear any pending interrupts, may auto mask */ 4127 IXGBE_READ_REG(hw, IXGBE_EICR); 4128 ixgbe_irq_enable(adapter, true, true); 4129 4130 /* 4131 * If this adapter has a fan, check to see if we had a failure 4132 * before we enabled the interrupt. 4133 */ 4134 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 4135 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 4136 if (esdp & IXGBE_ESDP_SDP1) 4137 e_crit(drv, "Fan has stopped, replace the adapter\n"); 4138 } 4139 4140 /* enable transmits */ 4141 netif_tx_start_all_queues(adapter->netdev); 4142 4143 /* bring the link up in the watchdog, this could race with our first 4144 * link up interrupt but shouldn't be a problem */ 4145 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 4146 adapter->link_check_timeout = jiffies; 4147 mod_timer(&adapter->service_timer, jiffies); 4148 4149 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 4150 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 4151 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 4152 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 4153 } 4154 4155 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 4156 { 4157 WARN_ON(in_interrupt()); 4158 /* put off any impending NetWatchDogTimeout */ 4159 adapter->netdev->trans_start = jiffies; 4160 4161 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 4162 usleep_range(1000, 2000); 4163 ixgbe_down(adapter); 4164 /* 4165 * If SR-IOV enabled then wait a bit before bringing the adapter 4166 * back up to give the VFs time to respond to the reset. The 4167 * two second wait is based upon the watchdog timer cycle in 4168 * the VF driver. 4169 */ 4170 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 4171 msleep(2000); 4172 ixgbe_up(adapter); 4173 clear_bit(__IXGBE_RESETTING, &adapter->state); 4174 } 4175 4176 void ixgbe_up(struct ixgbe_adapter *adapter) 4177 { 4178 /* hardware has been reset, we need to reload some things */ 4179 ixgbe_configure(adapter); 4180 4181 ixgbe_up_complete(adapter); 4182 } 4183 4184 void ixgbe_reset(struct ixgbe_adapter *adapter) 4185 { 4186 struct ixgbe_hw *hw = &adapter->hw; 4187 int err; 4188 4189 /* lock SFP init bit to prevent race conditions with the watchdog */ 4190 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 4191 usleep_range(1000, 2000); 4192 4193 /* clear all SFP and link config related flags while holding SFP_INIT */ 4194 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 4195 IXGBE_FLAG2_SFP_NEEDS_RESET); 4196 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 4197 4198 err = hw->mac.ops.init_hw(hw); 4199 switch (err) { 4200 case 0: 4201 case IXGBE_ERR_SFP_NOT_PRESENT: 4202 case IXGBE_ERR_SFP_NOT_SUPPORTED: 4203 break; 4204 case IXGBE_ERR_MASTER_REQUESTS_PENDING: 4205 e_dev_err("master disable timed out\n"); 4206 break; 4207 case IXGBE_ERR_EEPROM_VERSION: 4208 /* We are running on a pre-production device, log a warning */ 4209 e_dev_warn("This device is a pre-production adapter/LOM. " 4210 "Please be aware there may be issues associated with " 4211 "your hardware. If you are experiencing problems " 4212 "please contact your Intel or hardware " 4213 "representative who provided you with this " 4214 "hardware.\n"); 4215 break; 4216 default: 4217 e_dev_err("Hardware Error: %d\n", err); 4218 } 4219 4220 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 4221 4222 /* reprogram the RAR[0] in case user changed it. */ 4223 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV); 4224 4225 /* update SAN MAC vmdq pool selection */ 4226 if (hw->mac.san_mac_rar_index) 4227 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 4228 4229 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED) 4230 ixgbe_ptp_reset(adapter); 4231 } 4232 4233 /** 4234 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 4235 * @rx_ring: ring to free buffers from 4236 **/ 4237 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 4238 { 4239 struct device *dev = rx_ring->dev; 4240 unsigned long size; 4241 u16 i; 4242 4243 /* ring already cleared, nothing to do */ 4244 if (!rx_ring->rx_buffer_info) 4245 return; 4246 4247 /* Free all the Rx ring sk_buffs */ 4248 for (i = 0; i < rx_ring->count; i++) { 4249 struct ixgbe_rx_buffer *rx_buffer; 4250 4251 rx_buffer = &rx_ring->rx_buffer_info[i]; 4252 if (rx_buffer->skb) { 4253 struct sk_buff *skb = rx_buffer->skb; 4254 if (IXGBE_CB(skb)->page_released) { 4255 dma_unmap_page(dev, 4256 IXGBE_CB(skb)->dma, 4257 ixgbe_rx_bufsz(rx_ring), 4258 DMA_FROM_DEVICE); 4259 IXGBE_CB(skb)->page_released = false; 4260 } 4261 dev_kfree_skb(skb); 4262 } 4263 rx_buffer->skb = NULL; 4264 if (rx_buffer->dma) 4265 dma_unmap_page(dev, rx_buffer->dma, 4266 ixgbe_rx_pg_size(rx_ring), 4267 DMA_FROM_DEVICE); 4268 rx_buffer->dma = 0; 4269 if (rx_buffer->page) 4270 __free_pages(rx_buffer->page, 4271 ixgbe_rx_pg_order(rx_ring)); 4272 rx_buffer->page = NULL; 4273 } 4274 4275 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 4276 memset(rx_ring->rx_buffer_info, 0, size); 4277 4278 /* Zero out the descriptor ring */ 4279 memset(rx_ring->desc, 0, rx_ring->size); 4280 4281 rx_ring->next_to_alloc = 0; 4282 rx_ring->next_to_clean = 0; 4283 rx_ring->next_to_use = 0; 4284 } 4285 4286 /** 4287 * ixgbe_clean_tx_ring - Free Tx Buffers 4288 * @tx_ring: ring to be cleaned 4289 **/ 4290 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 4291 { 4292 struct ixgbe_tx_buffer *tx_buffer_info; 4293 unsigned long size; 4294 u16 i; 4295 4296 /* ring already cleared, nothing to do */ 4297 if (!tx_ring->tx_buffer_info) 4298 return; 4299 4300 /* Free all the Tx ring sk_buffs */ 4301 for (i = 0; i < tx_ring->count; i++) { 4302 tx_buffer_info = &tx_ring->tx_buffer_info[i]; 4303 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); 4304 } 4305 4306 netdev_tx_reset_queue(txring_txq(tx_ring)); 4307 4308 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 4309 memset(tx_ring->tx_buffer_info, 0, size); 4310 4311 /* Zero out the descriptor ring */ 4312 memset(tx_ring->desc, 0, tx_ring->size); 4313 4314 tx_ring->next_to_use = 0; 4315 tx_ring->next_to_clean = 0; 4316 } 4317 4318 /** 4319 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 4320 * @adapter: board private structure 4321 **/ 4322 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 4323 { 4324 int i; 4325 4326 for (i = 0; i < adapter->num_rx_queues; i++) 4327 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 4328 } 4329 4330 /** 4331 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 4332 * @adapter: board private structure 4333 **/ 4334 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 4335 { 4336 int i; 4337 4338 for (i = 0; i < adapter->num_tx_queues; i++) 4339 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 4340 } 4341 4342 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 4343 { 4344 struct hlist_node *node, *node2; 4345 struct ixgbe_fdir_filter *filter; 4346 4347 spin_lock(&adapter->fdir_perfect_lock); 4348 4349 hlist_for_each_entry_safe(filter, node, node2, 4350 &adapter->fdir_filter_list, fdir_node) { 4351 hlist_del(&filter->fdir_node); 4352 kfree(filter); 4353 } 4354 adapter->fdir_filter_count = 0; 4355 4356 spin_unlock(&adapter->fdir_perfect_lock); 4357 } 4358 4359 void ixgbe_down(struct ixgbe_adapter *adapter) 4360 { 4361 struct net_device *netdev = adapter->netdev; 4362 struct ixgbe_hw *hw = &adapter->hw; 4363 u32 rxctrl; 4364 int i; 4365 4366 /* signal that we are down to the interrupt handler */ 4367 set_bit(__IXGBE_DOWN, &adapter->state); 4368 4369 /* disable receives */ 4370 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4371 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); 4372 4373 /* disable all enabled rx queues */ 4374 for (i = 0; i < adapter->num_rx_queues; i++) 4375 /* this call also flushes the previous write */ 4376 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); 4377 4378 usleep_range(10000, 20000); 4379 4380 netif_tx_stop_all_queues(netdev); 4381 4382 /* call carrier off first to avoid false dev_watchdog timeouts */ 4383 netif_carrier_off(netdev); 4384 netif_tx_disable(netdev); 4385 4386 ixgbe_irq_disable(adapter); 4387 4388 ixgbe_napi_disable_all(adapter); 4389 4390 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT | 4391 IXGBE_FLAG2_RESET_REQUESTED); 4392 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 4393 4394 del_timer_sync(&adapter->service_timer); 4395 4396 if (adapter->num_vfs) { 4397 /* Clear EITR Select mapping */ 4398 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 4399 4400 /* Mark all the VFs as inactive */ 4401 for (i = 0 ; i < adapter->num_vfs; i++) 4402 adapter->vfinfo[i].clear_to_send = false; 4403 4404 /* ping all the active vfs to let them know we are going down */ 4405 ixgbe_ping_all_vfs(adapter); 4406 4407 /* Disable all VFTE/VFRE TX/RX */ 4408 ixgbe_disable_tx_rx(adapter); 4409 } 4410 4411 /* disable transmits in the hardware now that interrupts are off */ 4412 for (i = 0; i < adapter->num_tx_queues; i++) { 4413 u8 reg_idx = adapter->tx_ring[i]->reg_idx; 4414 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 4415 } 4416 4417 /* Disable the Tx DMA engine on 82599 and X540 */ 4418 switch (hw->mac.type) { 4419 case ixgbe_mac_82599EB: 4420 case ixgbe_mac_X540: 4421 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 4422 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 4423 ~IXGBE_DMATXCTL_TE)); 4424 break; 4425 default: 4426 break; 4427 } 4428 4429 if (!pci_channel_offline(adapter->pdev)) 4430 ixgbe_reset(adapter); 4431 4432 /* power down the optics for 82599 SFP+ fiber */ 4433 if (hw->mac.ops.disable_tx_laser) 4434 hw->mac.ops.disable_tx_laser(hw); 4435 4436 ixgbe_clean_all_tx_rings(adapter); 4437 ixgbe_clean_all_rx_rings(adapter); 4438 4439 #ifdef CONFIG_IXGBE_DCA 4440 /* since we reset the hardware DCA settings were cleared */ 4441 ixgbe_setup_dca(adapter); 4442 #endif 4443 } 4444 4445 /** 4446 * ixgbe_tx_timeout - Respond to a Tx Hang 4447 * @netdev: network interface device structure 4448 **/ 4449 static void ixgbe_tx_timeout(struct net_device *netdev) 4450 { 4451 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4452 4453 /* Do the reset outside of interrupt context */ 4454 ixgbe_tx_timeout_reset(adapter); 4455 } 4456 4457 /** 4458 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 4459 * @adapter: board private structure to initialize 4460 * 4461 * ixgbe_sw_init initializes the Adapter private data structure. 4462 * Fields are initialized based on PCI device information and 4463 * OS network device settings (MTU size). 4464 **/ 4465 static int ixgbe_sw_init(struct ixgbe_adapter *adapter) 4466 { 4467 struct ixgbe_hw *hw = &adapter->hw; 4468 struct pci_dev *pdev = adapter->pdev; 4469 unsigned int rss; 4470 u32 fwsm; 4471 #ifdef CONFIG_IXGBE_DCB 4472 int j; 4473 struct tc_configuration *tc; 4474 #endif 4475 4476 /* PCI config space info */ 4477 4478 hw->vendor_id = pdev->vendor; 4479 hw->device_id = pdev->device; 4480 hw->revision_id = pdev->revision; 4481 hw->subsystem_vendor_id = pdev->subsystem_vendor; 4482 hw->subsystem_device_id = pdev->subsystem_device; 4483 4484 /* Set capability flags */ 4485 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus()); 4486 adapter->ring_feature[RING_F_RSS].limit = rss; 4487 switch (hw->mac.type) { 4488 case ixgbe_mac_82598EB: 4489 if (hw->device_id == IXGBE_DEV_ID_82598AT) 4490 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 4491 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 4492 break; 4493 case ixgbe_mac_X540: 4494 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM); 4495 if (fwsm & IXGBE_FWSM_TS_ENABLED) 4496 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 4497 case ixgbe_mac_82599EB: 4498 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 4499 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 4500 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 4501 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 4502 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 4503 /* Flow Director hash filters enabled */ 4504 adapter->atr_sample_rate = 20; 4505 adapter->ring_feature[RING_F_FDIR].limit = 4506 IXGBE_MAX_FDIR_INDICES; 4507 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 4508 #ifdef IXGBE_FCOE 4509 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 4510 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 4511 #ifdef CONFIG_IXGBE_DCB 4512 /* Default traffic class to use for FCoE */ 4513 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 4514 #endif 4515 #endif /* IXGBE_FCOE */ 4516 break; 4517 default: 4518 break; 4519 } 4520 4521 #ifdef IXGBE_FCOE 4522 /* FCoE support exists, always init the FCoE lock */ 4523 spin_lock_init(&adapter->fcoe.lock); 4524 4525 #endif 4526 /* n-tuple support exists, always init our spinlock */ 4527 spin_lock_init(&adapter->fdir_perfect_lock); 4528 4529 #ifdef CONFIG_IXGBE_DCB 4530 switch (hw->mac.type) { 4531 case ixgbe_mac_X540: 4532 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 4533 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 4534 break; 4535 default: 4536 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 4537 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 4538 break; 4539 } 4540 4541 /* Configure DCB traffic classes */ 4542 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 4543 tc = &adapter->dcb_cfg.tc_config[j]; 4544 tc->path[DCB_TX_CONFIG].bwg_id = 0; 4545 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 4546 tc->path[DCB_RX_CONFIG].bwg_id = 0; 4547 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 4548 tc->dcb_pfc = pfc_disabled; 4549 } 4550 4551 /* Initialize default user to priority mapping, UPx->TC0 */ 4552 tc = &adapter->dcb_cfg.tc_config[0]; 4553 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 4554 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 4555 4556 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 4557 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 4558 adapter->dcb_cfg.pfc_mode_enable = false; 4559 adapter->dcb_set_bitmap = 0x00; 4560 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 4561 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 4562 sizeof(adapter->temp_dcb_cfg)); 4563 4564 #endif 4565 4566 /* default flow control settings */ 4567 hw->fc.requested_mode = ixgbe_fc_full; 4568 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 4569 ixgbe_pbthresh_setup(adapter); 4570 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 4571 hw->fc.send_xon = true; 4572 hw->fc.disable_fc_autoneg = 4573 (ixgbe_device_supports_autoneg_fc(hw) == 0) ? false : true; 4574 4575 #ifdef CONFIG_PCI_IOV 4576 /* assign number of SR-IOV VFs */ 4577 if (hw->mac.type != ixgbe_mac_82598EB) 4578 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs; 4579 4580 #endif 4581 /* enable itr by default in dynamic mode */ 4582 adapter->rx_itr_setting = 1; 4583 adapter->tx_itr_setting = 1; 4584 4585 /* set default ring sizes */ 4586 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 4587 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 4588 4589 /* set default work limits */ 4590 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 4591 4592 /* initialize eeprom parameters */ 4593 if (ixgbe_init_eeprom_params_generic(hw)) { 4594 e_dev_err("EEPROM initialization failed\n"); 4595 return -EIO; 4596 } 4597 4598 set_bit(__IXGBE_DOWN, &adapter->state); 4599 4600 return 0; 4601 } 4602 4603 /** 4604 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 4605 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4606 * 4607 * Return 0 on success, negative on failure 4608 **/ 4609 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 4610 { 4611 struct device *dev = tx_ring->dev; 4612 int orig_node = dev_to_node(dev); 4613 int numa_node = -1; 4614 int size; 4615 4616 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 4617 4618 if (tx_ring->q_vector) 4619 numa_node = tx_ring->q_vector->numa_node; 4620 4621 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node); 4622 if (!tx_ring->tx_buffer_info) 4623 tx_ring->tx_buffer_info = vzalloc(size); 4624 if (!tx_ring->tx_buffer_info) 4625 goto err; 4626 4627 /* round up to nearest 4K */ 4628 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 4629 tx_ring->size = ALIGN(tx_ring->size, 4096); 4630 4631 set_dev_node(dev, numa_node); 4632 tx_ring->desc = dma_alloc_coherent(dev, 4633 tx_ring->size, 4634 &tx_ring->dma, 4635 GFP_KERNEL); 4636 set_dev_node(dev, orig_node); 4637 if (!tx_ring->desc) 4638 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4639 &tx_ring->dma, GFP_KERNEL); 4640 if (!tx_ring->desc) 4641 goto err; 4642 4643 tx_ring->next_to_use = 0; 4644 tx_ring->next_to_clean = 0; 4645 return 0; 4646 4647 err: 4648 vfree(tx_ring->tx_buffer_info); 4649 tx_ring->tx_buffer_info = NULL; 4650 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4651 return -ENOMEM; 4652 } 4653 4654 /** 4655 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 4656 * @adapter: board private structure 4657 * 4658 * If this function returns with an error, then it's possible one or 4659 * more of the rings is populated (while the rest are not). It is the 4660 * callers duty to clean those orphaned rings. 4661 * 4662 * Return 0 on success, negative on failure 4663 **/ 4664 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 4665 { 4666 int i, err = 0; 4667 4668 for (i = 0; i < adapter->num_tx_queues; i++) { 4669 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 4670 if (!err) 4671 continue; 4672 4673 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 4674 goto err_setup_tx; 4675 } 4676 4677 return 0; 4678 err_setup_tx: 4679 /* rewind the index freeing the rings as we go */ 4680 while (i--) 4681 ixgbe_free_tx_resources(adapter->tx_ring[i]); 4682 return err; 4683 } 4684 4685 /** 4686 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 4687 * @rx_ring: rx descriptor ring (for a specific queue) to setup 4688 * 4689 * Returns 0 on success, negative on failure 4690 **/ 4691 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring) 4692 { 4693 struct device *dev = rx_ring->dev; 4694 int orig_node = dev_to_node(dev); 4695 int numa_node = -1; 4696 int size; 4697 4698 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 4699 4700 if (rx_ring->q_vector) 4701 numa_node = rx_ring->q_vector->numa_node; 4702 4703 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node); 4704 if (!rx_ring->rx_buffer_info) 4705 rx_ring->rx_buffer_info = vzalloc(size); 4706 if (!rx_ring->rx_buffer_info) 4707 goto err; 4708 4709 /* Round up to nearest 4K */ 4710 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 4711 rx_ring->size = ALIGN(rx_ring->size, 4096); 4712 4713 set_dev_node(dev, numa_node); 4714 rx_ring->desc = dma_alloc_coherent(dev, 4715 rx_ring->size, 4716 &rx_ring->dma, 4717 GFP_KERNEL); 4718 set_dev_node(dev, orig_node); 4719 if (!rx_ring->desc) 4720 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4721 &rx_ring->dma, GFP_KERNEL); 4722 if (!rx_ring->desc) 4723 goto err; 4724 4725 rx_ring->next_to_clean = 0; 4726 rx_ring->next_to_use = 0; 4727 4728 return 0; 4729 err: 4730 vfree(rx_ring->rx_buffer_info); 4731 rx_ring->rx_buffer_info = NULL; 4732 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4733 return -ENOMEM; 4734 } 4735 4736 /** 4737 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 4738 * @adapter: board private structure 4739 * 4740 * If this function returns with an error, then it's possible one or 4741 * more of the rings is populated (while the rest are not). It is the 4742 * callers duty to clean those orphaned rings. 4743 * 4744 * Return 0 on success, negative on failure 4745 **/ 4746 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 4747 { 4748 int i, err = 0; 4749 4750 for (i = 0; i < adapter->num_rx_queues; i++) { 4751 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]); 4752 if (!err) 4753 continue; 4754 4755 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 4756 goto err_setup_rx; 4757 } 4758 4759 #ifdef IXGBE_FCOE 4760 err = ixgbe_setup_fcoe_ddp_resources(adapter); 4761 if (!err) 4762 #endif 4763 return 0; 4764 err_setup_rx: 4765 /* rewind the index freeing the rings as we go */ 4766 while (i--) 4767 ixgbe_free_rx_resources(adapter->rx_ring[i]); 4768 return err; 4769 } 4770 4771 /** 4772 * ixgbe_free_tx_resources - Free Tx Resources per Queue 4773 * @tx_ring: Tx descriptor ring for a specific queue 4774 * 4775 * Free all transmit software resources 4776 **/ 4777 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 4778 { 4779 ixgbe_clean_tx_ring(tx_ring); 4780 4781 vfree(tx_ring->tx_buffer_info); 4782 tx_ring->tx_buffer_info = NULL; 4783 4784 /* if not set, then don't free */ 4785 if (!tx_ring->desc) 4786 return; 4787 4788 dma_free_coherent(tx_ring->dev, tx_ring->size, 4789 tx_ring->desc, tx_ring->dma); 4790 4791 tx_ring->desc = NULL; 4792 } 4793 4794 /** 4795 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 4796 * @adapter: board private structure 4797 * 4798 * Free all transmit software resources 4799 **/ 4800 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 4801 { 4802 int i; 4803 4804 for (i = 0; i < adapter->num_tx_queues; i++) 4805 if (adapter->tx_ring[i]->desc) 4806 ixgbe_free_tx_resources(adapter->tx_ring[i]); 4807 } 4808 4809 /** 4810 * ixgbe_free_rx_resources - Free Rx Resources 4811 * @rx_ring: ring to clean the resources from 4812 * 4813 * Free all receive software resources 4814 **/ 4815 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 4816 { 4817 ixgbe_clean_rx_ring(rx_ring); 4818 4819 vfree(rx_ring->rx_buffer_info); 4820 rx_ring->rx_buffer_info = NULL; 4821 4822 /* if not set, then don't free */ 4823 if (!rx_ring->desc) 4824 return; 4825 4826 dma_free_coherent(rx_ring->dev, rx_ring->size, 4827 rx_ring->desc, rx_ring->dma); 4828 4829 rx_ring->desc = NULL; 4830 } 4831 4832 /** 4833 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 4834 * @adapter: board private structure 4835 * 4836 * Free all receive software resources 4837 **/ 4838 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 4839 { 4840 int i; 4841 4842 #ifdef IXGBE_FCOE 4843 ixgbe_free_fcoe_ddp_resources(adapter); 4844 4845 #endif 4846 for (i = 0; i < adapter->num_rx_queues; i++) 4847 if (adapter->rx_ring[i]->desc) 4848 ixgbe_free_rx_resources(adapter->rx_ring[i]); 4849 } 4850 4851 /** 4852 * ixgbe_change_mtu - Change the Maximum Transfer Unit 4853 * @netdev: network interface device structure 4854 * @new_mtu: new value for maximum frame size 4855 * 4856 * Returns 0 on success, negative on failure 4857 **/ 4858 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 4859 { 4860 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4861 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; 4862 4863 /* MTU < 68 is an error and causes problems on some kernels */ 4864 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) 4865 return -EINVAL; 4866 4867 /* 4868 * For 82599EB we cannot allow legacy VFs to enable their receive 4869 * paths when MTU greater than 1500 is configured. So display a 4870 * warning that legacy VFs will be disabled. 4871 */ 4872 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 4873 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 4874 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE)) 4875 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 4876 4877 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); 4878 4879 /* must set new MTU before calling down or up */ 4880 netdev->mtu = new_mtu; 4881 4882 if (netif_running(netdev)) 4883 ixgbe_reinit_locked(adapter); 4884 4885 return 0; 4886 } 4887 4888 /** 4889 * ixgbe_open - Called when a network interface is made active 4890 * @netdev: network interface device structure 4891 * 4892 * Returns 0 on success, negative value on failure 4893 * 4894 * The open entry point is called when a network interface is made 4895 * active by the system (IFF_UP). At this point all resources needed 4896 * for transmit and receive operations are allocated, the interrupt 4897 * handler is registered with the OS, the watchdog timer is started, 4898 * and the stack is notified that the interface is ready. 4899 **/ 4900 static int ixgbe_open(struct net_device *netdev) 4901 { 4902 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4903 int err; 4904 4905 /* disallow open during test */ 4906 if (test_bit(__IXGBE_TESTING, &adapter->state)) 4907 return -EBUSY; 4908 4909 netif_carrier_off(netdev); 4910 4911 /* allocate transmit descriptors */ 4912 err = ixgbe_setup_all_tx_resources(adapter); 4913 if (err) 4914 goto err_setup_tx; 4915 4916 /* allocate receive descriptors */ 4917 err = ixgbe_setup_all_rx_resources(adapter); 4918 if (err) 4919 goto err_setup_rx; 4920 4921 ixgbe_configure(adapter); 4922 4923 err = ixgbe_request_irq(adapter); 4924 if (err) 4925 goto err_req_irq; 4926 4927 /* Notify the stack of the actual queue counts. */ 4928 err = netif_set_real_num_tx_queues(netdev, 4929 adapter->num_rx_pools > 1 ? 1 : 4930 adapter->num_tx_queues); 4931 if (err) 4932 goto err_set_queues; 4933 4934 4935 err = netif_set_real_num_rx_queues(netdev, 4936 adapter->num_rx_pools > 1 ? 1 : 4937 adapter->num_rx_queues); 4938 if (err) 4939 goto err_set_queues; 4940 4941 ixgbe_ptp_init(adapter); 4942 4943 ixgbe_up_complete(adapter); 4944 4945 return 0; 4946 4947 err_set_queues: 4948 ixgbe_free_irq(adapter); 4949 err_req_irq: 4950 ixgbe_free_all_rx_resources(adapter); 4951 err_setup_rx: 4952 ixgbe_free_all_tx_resources(adapter); 4953 err_setup_tx: 4954 ixgbe_reset(adapter); 4955 4956 return err; 4957 } 4958 4959 /** 4960 * ixgbe_close - Disables a network interface 4961 * @netdev: network interface device structure 4962 * 4963 * Returns 0, this is not allowed to fail 4964 * 4965 * The close entry point is called when an interface is de-activated 4966 * by the OS. The hardware is still under the drivers control, but 4967 * needs to be disabled. A global MAC reset is issued to stop the 4968 * hardware, and all transmit and receive resources are freed. 4969 **/ 4970 static int ixgbe_close(struct net_device *netdev) 4971 { 4972 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4973 4974 ixgbe_ptp_stop(adapter); 4975 4976 ixgbe_down(adapter); 4977 ixgbe_free_irq(adapter); 4978 4979 ixgbe_fdir_filter_exit(adapter); 4980 4981 ixgbe_free_all_tx_resources(adapter); 4982 ixgbe_free_all_rx_resources(adapter); 4983 4984 ixgbe_release_hw_control(adapter); 4985 4986 return 0; 4987 } 4988 4989 #ifdef CONFIG_PM 4990 static int ixgbe_resume(struct pci_dev *pdev) 4991 { 4992 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 4993 struct net_device *netdev = adapter->netdev; 4994 u32 err; 4995 4996 pci_set_power_state(pdev, PCI_D0); 4997 pci_restore_state(pdev); 4998 /* 4999 * pci_restore_state clears dev->state_saved so call 5000 * pci_save_state to restore it. 5001 */ 5002 pci_save_state(pdev); 5003 5004 err = pci_enable_device_mem(pdev); 5005 if (err) { 5006 e_dev_err("Cannot enable PCI device from suspend\n"); 5007 return err; 5008 } 5009 pci_set_master(pdev); 5010 5011 pci_wake_from_d3(pdev, false); 5012 5013 ixgbe_reset(adapter); 5014 5015 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 5016 5017 rtnl_lock(); 5018 err = ixgbe_init_interrupt_scheme(adapter); 5019 if (!err && netif_running(netdev)) 5020 err = ixgbe_open(netdev); 5021 5022 rtnl_unlock(); 5023 5024 if (err) 5025 return err; 5026 5027 netif_device_attach(netdev); 5028 5029 return 0; 5030 } 5031 #endif /* CONFIG_PM */ 5032 5033 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 5034 { 5035 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 5036 struct net_device *netdev = adapter->netdev; 5037 struct ixgbe_hw *hw = &adapter->hw; 5038 u32 ctrl, fctrl; 5039 u32 wufc = adapter->wol; 5040 #ifdef CONFIG_PM 5041 int retval = 0; 5042 #endif 5043 5044 netif_device_detach(netdev); 5045 5046 if (netif_running(netdev)) { 5047 rtnl_lock(); 5048 ixgbe_down(adapter); 5049 ixgbe_free_irq(adapter); 5050 ixgbe_free_all_tx_resources(adapter); 5051 ixgbe_free_all_rx_resources(adapter); 5052 rtnl_unlock(); 5053 } 5054 5055 ixgbe_clear_interrupt_scheme(adapter); 5056 5057 #ifdef CONFIG_PM 5058 retval = pci_save_state(pdev); 5059 if (retval) 5060 return retval; 5061 5062 #endif 5063 if (wufc) { 5064 ixgbe_set_rx_mode(netdev); 5065 5066 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 5067 if (hw->mac.ops.enable_tx_laser) 5068 hw->mac.ops.enable_tx_laser(hw); 5069 5070 /* turn on all-multi mode if wake on multicast is enabled */ 5071 if (wufc & IXGBE_WUFC_MC) { 5072 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 5073 fctrl |= IXGBE_FCTRL_MPE; 5074 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 5075 } 5076 5077 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 5078 ctrl |= IXGBE_CTRL_GIO_DIS; 5079 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 5080 5081 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 5082 } else { 5083 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 5084 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 5085 } 5086 5087 switch (hw->mac.type) { 5088 case ixgbe_mac_82598EB: 5089 pci_wake_from_d3(pdev, false); 5090 break; 5091 case ixgbe_mac_82599EB: 5092 case ixgbe_mac_X540: 5093 pci_wake_from_d3(pdev, !!wufc); 5094 break; 5095 default: 5096 break; 5097 } 5098 5099 *enable_wake = !!wufc; 5100 5101 ixgbe_release_hw_control(adapter); 5102 5103 pci_disable_device(pdev); 5104 5105 return 0; 5106 } 5107 5108 #ifdef CONFIG_PM 5109 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) 5110 { 5111 int retval; 5112 bool wake; 5113 5114 retval = __ixgbe_shutdown(pdev, &wake); 5115 if (retval) 5116 return retval; 5117 5118 if (wake) { 5119 pci_prepare_to_sleep(pdev); 5120 } else { 5121 pci_wake_from_d3(pdev, false); 5122 pci_set_power_state(pdev, PCI_D3hot); 5123 } 5124 5125 return 0; 5126 } 5127 #endif /* CONFIG_PM */ 5128 5129 static void ixgbe_shutdown(struct pci_dev *pdev) 5130 { 5131 bool wake; 5132 5133 __ixgbe_shutdown(pdev, &wake); 5134 5135 if (system_state == SYSTEM_POWER_OFF) { 5136 pci_wake_from_d3(pdev, wake); 5137 pci_set_power_state(pdev, PCI_D3hot); 5138 } 5139 } 5140 5141 /** 5142 * ixgbe_update_stats - Update the board statistics counters. 5143 * @adapter: board private structure 5144 **/ 5145 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 5146 { 5147 struct net_device *netdev = adapter->netdev; 5148 struct ixgbe_hw *hw = &adapter->hw; 5149 struct ixgbe_hw_stats *hwstats = &adapter->stats; 5150 u64 total_mpc = 0; 5151 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 5152 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 5153 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 5154 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 5155 5156 if (test_bit(__IXGBE_DOWN, &adapter->state) || 5157 test_bit(__IXGBE_RESETTING, &adapter->state)) 5158 return; 5159 5160 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 5161 u64 rsc_count = 0; 5162 u64 rsc_flush = 0; 5163 for (i = 0; i < adapter->num_rx_queues; i++) { 5164 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 5165 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 5166 } 5167 adapter->rsc_total_count = rsc_count; 5168 adapter->rsc_total_flush = rsc_flush; 5169 } 5170 5171 for (i = 0; i < adapter->num_rx_queues; i++) { 5172 struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; 5173 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 5174 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 5175 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 5176 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 5177 bytes += rx_ring->stats.bytes; 5178 packets += rx_ring->stats.packets; 5179 } 5180 adapter->non_eop_descs = non_eop_descs; 5181 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 5182 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 5183 adapter->hw_csum_rx_error = hw_csum_rx_error; 5184 netdev->stats.rx_bytes = bytes; 5185 netdev->stats.rx_packets = packets; 5186 5187 bytes = 0; 5188 packets = 0; 5189 /* gather some stats to the adapter struct that are per queue */ 5190 for (i = 0; i < adapter->num_tx_queues; i++) { 5191 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 5192 restart_queue += tx_ring->tx_stats.restart_queue; 5193 tx_busy += tx_ring->tx_stats.tx_busy; 5194 bytes += tx_ring->stats.bytes; 5195 packets += tx_ring->stats.packets; 5196 } 5197 adapter->restart_queue = restart_queue; 5198 adapter->tx_busy = tx_busy; 5199 netdev->stats.tx_bytes = bytes; 5200 netdev->stats.tx_packets = packets; 5201 5202 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 5203 5204 /* 8 register reads */ 5205 for (i = 0; i < 8; i++) { 5206 /* for packet buffers not used, the register should read 0 */ 5207 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 5208 missed_rx += mpc; 5209 hwstats->mpc[i] += mpc; 5210 total_mpc += hwstats->mpc[i]; 5211 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 5212 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 5213 switch (hw->mac.type) { 5214 case ixgbe_mac_82598EB: 5215 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 5216 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 5217 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 5218 hwstats->pxonrxc[i] += 5219 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 5220 break; 5221 case ixgbe_mac_82599EB: 5222 case ixgbe_mac_X540: 5223 hwstats->pxonrxc[i] += 5224 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 5225 break; 5226 default: 5227 break; 5228 } 5229 } 5230 5231 /*16 register reads */ 5232 for (i = 0; i < 16; i++) { 5233 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 5234 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 5235 if ((hw->mac.type == ixgbe_mac_82599EB) || 5236 (hw->mac.type == ixgbe_mac_X540)) { 5237 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 5238 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 5239 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 5240 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 5241 } 5242 } 5243 5244 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 5245 /* work around hardware counting issue */ 5246 hwstats->gprc -= missed_rx; 5247 5248 ixgbe_update_xoff_received(adapter); 5249 5250 /* 82598 hardware only has a 32 bit counter in the high register */ 5251 switch (hw->mac.type) { 5252 case ixgbe_mac_82598EB: 5253 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 5254 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 5255 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 5256 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 5257 break; 5258 case ixgbe_mac_X540: 5259 /* OS2BMC stats are X540 only*/ 5260 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 5261 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 5262 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 5263 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 5264 case ixgbe_mac_82599EB: 5265 for (i = 0; i < 16; i++) 5266 adapter->hw_rx_no_dma_resources += 5267 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 5268 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 5269 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 5270 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 5271 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 5272 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 5273 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 5274 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 5275 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 5276 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 5277 #ifdef IXGBE_FCOE 5278 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 5279 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 5280 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 5281 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 5282 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 5283 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 5284 /* Add up per cpu counters for total ddp aloc fail */ 5285 if (adapter->fcoe.ddp_pool) { 5286 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 5287 struct ixgbe_fcoe_ddp_pool *ddp_pool; 5288 unsigned int cpu; 5289 u64 noddp = 0, noddp_ext_buff = 0; 5290 for_each_possible_cpu(cpu) { 5291 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 5292 noddp += ddp_pool->noddp; 5293 noddp_ext_buff += ddp_pool->noddp_ext_buff; 5294 } 5295 hwstats->fcoe_noddp = noddp; 5296 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 5297 } 5298 #endif /* IXGBE_FCOE */ 5299 break; 5300 default: 5301 break; 5302 } 5303 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 5304 hwstats->bprc += bprc; 5305 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 5306 if (hw->mac.type == ixgbe_mac_82598EB) 5307 hwstats->mprc -= bprc; 5308 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 5309 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 5310 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 5311 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 5312 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 5313 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 5314 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 5315 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 5316 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 5317 hwstats->lxontxc += lxon; 5318 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 5319 hwstats->lxofftxc += lxoff; 5320 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 5321 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 5322 /* 5323 * 82598 errata - tx of flow control packets is included in tx counters 5324 */ 5325 xon_off_tot = lxon + lxoff; 5326 hwstats->gptc -= xon_off_tot; 5327 hwstats->mptc -= xon_off_tot; 5328 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 5329 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 5330 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 5331 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 5332 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 5333 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 5334 hwstats->ptc64 -= xon_off_tot; 5335 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 5336 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 5337 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 5338 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 5339 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 5340 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 5341 5342 /* Fill out the OS statistics structure */ 5343 netdev->stats.multicast = hwstats->mprc; 5344 5345 /* Rx Errors */ 5346 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 5347 netdev->stats.rx_dropped = 0; 5348 netdev->stats.rx_length_errors = hwstats->rlec; 5349 netdev->stats.rx_crc_errors = hwstats->crcerrs; 5350 netdev->stats.rx_missed_errors = total_mpc; 5351 } 5352 5353 /** 5354 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 5355 * @adapter: pointer to the device adapter structure 5356 **/ 5357 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 5358 { 5359 struct ixgbe_hw *hw = &adapter->hw; 5360 int i; 5361 5362 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 5363 return; 5364 5365 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 5366 5367 /* if interface is down do nothing */ 5368 if (test_bit(__IXGBE_DOWN, &adapter->state)) 5369 return; 5370 5371 /* do nothing if we are not using signature filters */ 5372 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 5373 return; 5374 5375 adapter->fdir_overflow++; 5376 5377 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 5378 for (i = 0; i < adapter->num_tx_queues; i++) 5379 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 5380 &(adapter->tx_ring[i]->state)); 5381 /* re-enable flow director interrupts */ 5382 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 5383 } else { 5384 e_err(probe, "failed to finish FDIR re-initialization, " 5385 "ignored adding FDIR ATR filters\n"); 5386 } 5387 } 5388 5389 /** 5390 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 5391 * @adapter: pointer to the device adapter structure 5392 * 5393 * This function serves two purposes. First it strobes the interrupt lines 5394 * in order to make certain interrupts are occurring. Secondly it sets the 5395 * bits needed to check for TX hangs. As a result we should immediately 5396 * determine if a hang has occurred. 5397 */ 5398 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 5399 { 5400 struct ixgbe_hw *hw = &adapter->hw; 5401 u64 eics = 0; 5402 int i; 5403 5404 /* If we're down or resetting, just bail */ 5405 if (test_bit(__IXGBE_DOWN, &adapter->state) || 5406 test_bit(__IXGBE_RESETTING, &adapter->state)) 5407 return; 5408 5409 /* Force detection of hung controller */ 5410 if (netif_carrier_ok(adapter->netdev)) { 5411 for (i = 0; i < adapter->num_tx_queues; i++) 5412 set_check_for_tx_hang(adapter->tx_ring[i]); 5413 } 5414 5415 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 5416 /* 5417 * for legacy and MSI interrupts don't set any bits 5418 * that are enabled for EIAM, because this operation 5419 * would set *both* EIMS and EICS for any bit in EIAM 5420 */ 5421 IXGBE_WRITE_REG(hw, IXGBE_EICS, 5422 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 5423 } else { 5424 /* get one bit for every active tx/rx interrupt vector */ 5425 for (i = 0; i < adapter->num_q_vectors; i++) { 5426 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 5427 if (qv->rx.ring || qv->tx.ring) 5428 eics |= ((u64)1 << i); 5429 } 5430 } 5431 5432 /* Cause software interrupt to ensure rings are cleaned */ 5433 ixgbe_irq_rearm_queues(adapter, eics); 5434 5435 } 5436 5437 /** 5438 * ixgbe_watchdog_update_link - update the link status 5439 * @adapter: pointer to the device adapter structure 5440 * @link_speed: pointer to a u32 to store the link_speed 5441 **/ 5442 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 5443 { 5444 struct ixgbe_hw *hw = &adapter->hw; 5445 u32 link_speed = adapter->link_speed; 5446 bool link_up = adapter->link_up; 5447 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 5448 5449 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 5450 return; 5451 5452 if (hw->mac.ops.check_link) { 5453 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 5454 } else { 5455 /* always assume link is up, if no check link function */ 5456 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 5457 link_up = true; 5458 } 5459 5460 if (adapter->ixgbe_ieee_pfc) 5461 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 5462 5463 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 5464 hw->mac.ops.fc_enable(hw); 5465 ixgbe_set_rx_drop_en(adapter); 5466 } 5467 5468 if (link_up || 5469 time_after(jiffies, (adapter->link_check_timeout + 5470 IXGBE_TRY_LINK_TIMEOUT))) { 5471 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 5472 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 5473 IXGBE_WRITE_FLUSH(hw); 5474 } 5475 5476 adapter->link_up = link_up; 5477 adapter->link_speed = link_speed; 5478 } 5479 5480 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 5481 { 5482 #ifdef CONFIG_IXGBE_DCB 5483 struct net_device *netdev = adapter->netdev; 5484 struct dcb_app app = { 5485 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 5486 .protocol = 0, 5487 }; 5488 u8 up = 0; 5489 5490 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 5491 up = dcb_ieee_getapp_mask(netdev, &app); 5492 5493 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 5494 #endif 5495 } 5496 5497 /** 5498 * ixgbe_watchdog_link_is_up - update netif_carrier status and 5499 * print link up message 5500 * @adapter: pointer to the device adapter structure 5501 **/ 5502 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 5503 { 5504 struct net_device *netdev = adapter->netdev; 5505 struct ixgbe_hw *hw = &adapter->hw; 5506 u32 link_speed = adapter->link_speed; 5507 bool flow_rx, flow_tx; 5508 5509 /* only continue if link was previously down */ 5510 if (netif_carrier_ok(netdev)) 5511 return; 5512 5513 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 5514 5515 switch (hw->mac.type) { 5516 case ixgbe_mac_82598EB: { 5517 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 5518 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 5519 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 5520 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 5521 } 5522 break; 5523 case ixgbe_mac_X540: 5524 case ixgbe_mac_82599EB: { 5525 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 5526 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 5527 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 5528 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 5529 } 5530 break; 5531 default: 5532 flow_tx = false; 5533 flow_rx = false; 5534 break; 5535 } 5536 5537 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED) 5538 ixgbe_ptp_start_cyclecounter(adapter); 5539 5540 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", 5541 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? 5542 "10 Gbps" : 5543 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? 5544 "1 Gbps" : 5545 (link_speed == IXGBE_LINK_SPEED_100_FULL ? 5546 "100 Mbps" : 5547 "unknown speed"))), 5548 ((flow_rx && flow_tx) ? "RX/TX" : 5549 (flow_rx ? "RX" : 5550 (flow_tx ? "TX" : "None")))); 5551 5552 netif_carrier_on(netdev); 5553 ixgbe_check_vf_rate_limit(adapter); 5554 5555 /* update the default user priority for VFs */ 5556 ixgbe_update_default_up(adapter); 5557 5558 /* ping all the active vfs to let them know link has changed */ 5559 ixgbe_ping_all_vfs(adapter); 5560 } 5561 5562 /** 5563 * ixgbe_watchdog_link_is_down - update netif_carrier status and 5564 * print link down message 5565 * @adapter: pointer to the adapter structure 5566 **/ 5567 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 5568 { 5569 struct net_device *netdev = adapter->netdev; 5570 struct ixgbe_hw *hw = &adapter->hw; 5571 5572 adapter->link_up = false; 5573 adapter->link_speed = 0; 5574 5575 /* only continue if link was up previously */ 5576 if (!netif_carrier_ok(netdev)) 5577 return; 5578 5579 /* poll for SFP+ cable when link is down */ 5580 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 5581 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 5582 5583 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED) 5584 ixgbe_ptp_start_cyclecounter(adapter); 5585 5586 e_info(drv, "NIC Link is Down\n"); 5587 netif_carrier_off(netdev); 5588 5589 /* ping all the active vfs to let them know link has changed */ 5590 ixgbe_ping_all_vfs(adapter); 5591 } 5592 5593 /** 5594 * ixgbe_watchdog_flush_tx - flush queues on link down 5595 * @adapter: pointer to the device adapter structure 5596 **/ 5597 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 5598 { 5599 int i; 5600 int some_tx_pending = 0; 5601 5602 if (!netif_carrier_ok(adapter->netdev)) { 5603 for (i = 0; i < adapter->num_tx_queues; i++) { 5604 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 5605 if (tx_ring->next_to_use != tx_ring->next_to_clean) { 5606 some_tx_pending = 1; 5607 break; 5608 } 5609 } 5610 5611 if (some_tx_pending) { 5612 /* We've lost link, so the controller stops DMA, 5613 * but we've got queued Tx work that's never going 5614 * to get done, so reset controller to flush Tx. 5615 * (Do the reset outside of interrupt context). 5616 */ 5617 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 5618 } 5619 } 5620 } 5621 5622 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 5623 { 5624 u32 ssvpc; 5625 5626 /* Do not perform spoof check for 82598 or if not in IOV mode */ 5627 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 5628 adapter->num_vfs == 0) 5629 return; 5630 5631 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 5632 5633 /* 5634 * ssvpc register is cleared on read, if zero then no 5635 * spoofed packets in the last interval. 5636 */ 5637 if (!ssvpc) 5638 return; 5639 5640 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 5641 } 5642 5643 /** 5644 * ixgbe_watchdog_subtask - check and bring link up 5645 * @adapter: pointer to the device adapter structure 5646 **/ 5647 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 5648 { 5649 /* if interface is down do nothing */ 5650 if (test_bit(__IXGBE_DOWN, &adapter->state) || 5651 test_bit(__IXGBE_RESETTING, &adapter->state)) 5652 return; 5653 5654 ixgbe_watchdog_update_link(adapter); 5655 5656 if (adapter->link_up) 5657 ixgbe_watchdog_link_is_up(adapter); 5658 else 5659 ixgbe_watchdog_link_is_down(adapter); 5660 5661 ixgbe_spoof_check(adapter); 5662 ixgbe_update_stats(adapter); 5663 5664 ixgbe_watchdog_flush_tx(adapter); 5665 } 5666 5667 /** 5668 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 5669 * @adapter: the ixgbe adapter structure 5670 **/ 5671 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 5672 { 5673 struct ixgbe_hw *hw = &adapter->hw; 5674 s32 err; 5675 5676 /* not searching for SFP so there is nothing to do here */ 5677 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 5678 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 5679 return; 5680 5681 /* someone else is in init, wait until next service event */ 5682 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 5683 return; 5684 5685 err = hw->phy.ops.identify_sfp(hw); 5686 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 5687 goto sfp_out; 5688 5689 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 5690 /* If no cable is present, then we need to reset 5691 * the next time we find a good cable. */ 5692 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 5693 } 5694 5695 /* exit on error */ 5696 if (err) 5697 goto sfp_out; 5698 5699 /* exit if reset not needed */ 5700 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 5701 goto sfp_out; 5702 5703 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 5704 5705 /* 5706 * A module may be identified correctly, but the EEPROM may not have 5707 * support for that module. setup_sfp() will fail in that case, so 5708 * we should not allow that module to load. 5709 */ 5710 if (hw->mac.type == ixgbe_mac_82598EB) 5711 err = hw->phy.ops.reset(hw); 5712 else 5713 err = hw->mac.ops.setup_sfp(hw); 5714 5715 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 5716 goto sfp_out; 5717 5718 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 5719 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 5720 5721 sfp_out: 5722 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 5723 5724 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && 5725 (adapter->netdev->reg_state == NETREG_REGISTERED)) { 5726 e_dev_err("failed to initialize because an unsupported " 5727 "SFP+ module type was detected.\n"); 5728 e_dev_err("Reload the driver after installing a " 5729 "supported module.\n"); 5730 unregister_netdev(adapter->netdev); 5731 } 5732 } 5733 5734 /** 5735 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 5736 * @adapter: the ixgbe adapter structure 5737 **/ 5738 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 5739 { 5740 struct ixgbe_hw *hw = &adapter->hw; 5741 u32 autoneg; 5742 bool negotiation; 5743 5744 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 5745 return; 5746 5747 /* someone else is in init, wait until next service event */ 5748 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 5749 return; 5750 5751 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 5752 5753 autoneg = hw->phy.autoneg_advertised; 5754 if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) 5755 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation); 5756 if (hw->mac.ops.setup_link) 5757 hw->mac.ops.setup_link(hw, autoneg, negotiation, true); 5758 5759 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 5760 adapter->link_check_timeout = jiffies; 5761 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 5762 } 5763 5764 #ifdef CONFIG_PCI_IOV 5765 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 5766 { 5767 int vf; 5768 struct ixgbe_hw *hw = &adapter->hw; 5769 struct net_device *netdev = adapter->netdev; 5770 u32 gpc; 5771 u32 ciaa, ciad; 5772 5773 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 5774 if (gpc) /* If incrementing then no need for the check below */ 5775 return; 5776 /* 5777 * Check to see if a bad DMA write target from an errant or 5778 * malicious VF has caused a PCIe error. If so then we can 5779 * issue a VFLR to the offending VF(s) and then resume without 5780 * requesting a full slot reset. 5781 */ 5782 5783 for (vf = 0; vf < adapter->num_vfs; vf++) { 5784 ciaa = (vf << 16) | 0x80000000; 5785 /* 32 bit read so align, we really want status at offset 6 */ 5786 ciaa |= PCI_COMMAND; 5787 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); 5788 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599); 5789 ciaa &= 0x7FFFFFFF; 5790 /* disable debug mode asap after reading data */ 5791 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); 5792 /* Get the upper 16 bits which will be the PCI status reg */ 5793 ciad >>= 16; 5794 if (ciad & PCI_STATUS_REC_MASTER_ABORT) { 5795 netdev_err(netdev, "VF %d Hung DMA\n", vf); 5796 /* Issue VFLR */ 5797 ciaa = (vf << 16) | 0x80000000; 5798 ciaa |= 0xA8; 5799 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); 5800 ciad = 0x00008000; /* VFLR */ 5801 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad); 5802 ciaa &= 0x7FFFFFFF; 5803 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); 5804 } 5805 } 5806 } 5807 5808 #endif 5809 /** 5810 * ixgbe_service_timer - Timer Call-back 5811 * @data: pointer to adapter cast into an unsigned long 5812 **/ 5813 static void ixgbe_service_timer(unsigned long data) 5814 { 5815 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; 5816 unsigned long next_event_offset; 5817 bool ready = true; 5818 5819 /* poll faster when waiting for link */ 5820 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 5821 next_event_offset = HZ / 10; 5822 else 5823 next_event_offset = HZ * 2; 5824 5825 #ifdef CONFIG_PCI_IOV 5826 /* 5827 * don't bother with SR-IOV VF DMA hang check if there are 5828 * no VFs or the link is down 5829 */ 5830 if (!adapter->num_vfs || 5831 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 5832 goto normal_timer_service; 5833 5834 /* If we have VFs allocated then we must check for DMA hangs */ 5835 ixgbe_check_for_bad_vf(adapter); 5836 next_event_offset = HZ / 50; 5837 adapter->timer_event_accumulator++; 5838 5839 if (adapter->timer_event_accumulator >= 100) 5840 adapter->timer_event_accumulator = 0; 5841 else 5842 ready = false; 5843 5844 normal_timer_service: 5845 #endif 5846 /* Reset the timer */ 5847 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 5848 5849 if (ready) 5850 ixgbe_service_event_schedule(adapter); 5851 } 5852 5853 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 5854 { 5855 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED)) 5856 return; 5857 5858 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED; 5859 5860 /* If we're already down or resetting, just bail */ 5861 if (test_bit(__IXGBE_DOWN, &adapter->state) || 5862 test_bit(__IXGBE_RESETTING, &adapter->state)) 5863 return; 5864 5865 ixgbe_dump(adapter); 5866 netdev_err(adapter->netdev, "Reset adapter\n"); 5867 adapter->tx_timeout_count++; 5868 5869 ixgbe_reinit_locked(adapter); 5870 } 5871 5872 /** 5873 * ixgbe_service_task - manages and runs subtasks 5874 * @work: pointer to work_struct containing our data 5875 **/ 5876 static void ixgbe_service_task(struct work_struct *work) 5877 { 5878 struct ixgbe_adapter *adapter = container_of(work, 5879 struct ixgbe_adapter, 5880 service_task); 5881 5882 ixgbe_reset_subtask(adapter); 5883 ixgbe_sfp_detection_subtask(adapter); 5884 ixgbe_sfp_link_config_subtask(adapter); 5885 ixgbe_check_overtemp_subtask(adapter); 5886 ixgbe_watchdog_subtask(adapter); 5887 ixgbe_fdir_reinit_subtask(adapter); 5888 ixgbe_check_hang_subtask(adapter); 5889 ixgbe_ptp_overflow_check(adapter); 5890 5891 ixgbe_service_event_complete(adapter); 5892 } 5893 5894 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 5895 struct ixgbe_tx_buffer *first, 5896 u8 *hdr_len) 5897 { 5898 struct sk_buff *skb = first->skb; 5899 u32 vlan_macip_lens, type_tucmd; 5900 u32 mss_l4len_idx, l4len; 5901 5902 if (!skb_is_gso(skb)) 5903 return 0; 5904 5905 if (skb_header_cloned(skb)) { 5906 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); 5907 if (err) 5908 return err; 5909 } 5910 5911 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 5912 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 5913 5914 if (first->protocol == __constant_htons(ETH_P_IP)) { 5915 struct iphdr *iph = ip_hdr(skb); 5916 iph->tot_len = 0; 5917 iph->check = 0; 5918 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 5919 iph->daddr, 0, 5920 IPPROTO_TCP, 5921 0); 5922 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 5923 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 5924 IXGBE_TX_FLAGS_CSUM | 5925 IXGBE_TX_FLAGS_IPV4; 5926 } else if (skb_is_gso_v6(skb)) { 5927 ipv6_hdr(skb)->payload_len = 0; 5928 tcp_hdr(skb)->check = 5929 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 5930 &ipv6_hdr(skb)->daddr, 5931 0, IPPROTO_TCP, 0); 5932 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 5933 IXGBE_TX_FLAGS_CSUM; 5934 } 5935 5936 /* compute header lengths */ 5937 l4len = tcp_hdrlen(skb); 5938 *hdr_len = skb_transport_offset(skb) + l4len; 5939 5940 /* update gso size and bytecount with header size */ 5941 first->gso_segs = skb_shinfo(skb)->gso_segs; 5942 first->bytecount += (first->gso_segs - 1) * *hdr_len; 5943 5944 /* mss_l4len_id: use 1 as index for TSO */ 5945 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT; 5946 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 5947 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT; 5948 5949 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 5950 vlan_macip_lens = skb_network_header_len(skb); 5951 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 5952 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 5953 5954 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 5955 mss_l4len_idx); 5956 5957 return 1; 5958 } 5959 5960 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 5961 struct ixgbe_tx_buffer *first) 5962 { 5963 struct sk_buff *skb = first->skb; 5964 u32 vlan_macip_lens = 0; 5965 u32 mss_l4len_idx = 0; 5966 u32 type_tucmd = 0; 5967 5968 if (skb->ip_summed != CHECKSUM_PARTIAL) { 5969 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN)) { 5970 if (unlikely(skb->no_fcs)) 5971 first->tx_flags |= IXGBE_TX_FLAGS_NO_IFCS; 5972 if (!(first->tx_flags & IXGBE_TX_FLAGS_TXSW)) 5973 return; 5974 } 5975 } else { 5976 u8 l4_hdr = 0; 5977 switch (first->protocol) { 5978 case __constant_htons(ETH_P_IP): 5979 vlan_macip_lens |= skb_network_header_len(skb); 5980 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 5981 l4_hdr = ip_hdr(skb)->protocol; 5982 break; 5983 case __constant_htons(ETH_P_IPV6): 5984 vlan_macip_lens |= skb_network_header_len(skb); 5985 l4_hdr = ipv6_hdr(skb)->nexthdr; 5986 break; 5987 default: 5988 if (unlikely(net_ratelimit())) { 5989 dev_warn(tx_ring->dev, 5990 "partial checksum but proto=%x!\n", 5991 first->protocol); 5992 } 5993 break; 5994 } 5995 5996 switch (l4_hdr) { 5997 case IPPROTO_TCP: 5998 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP; 5999 mss_l4len_idx = tcp_hdrlen(skb) << 6000 IXGBE_ADVTXD_L4LEN_SHIFT; 6001 break; 6002 case IPPROTO_SCTP: 6003 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; 6004 mss_l4len_idx = sizeof(struct sctphdr) << 6005 IXGBE_ADVTXD_L4LEN_SHIFT; 6006 break; 6007 case IPPROTO_UDP: 6008 mss_l4len_idx = sizeof(struct udphdr) << 6009 IXGBE_ADVTXD_L4LEN_SHIFT; 6010 break; 6011 default: 6012 if (unlikely(net_ratelimit())) { 6013 dev_warn(tx_ring->dev, 6014 "partial checksum but l4 proto=%x!\n", 6015 l4_hdr); 6016 } 6017 break; 6018 } 6019 6020 /* update TX checksum flag */ 6021 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 6022 } 6023 6024 /* vlan_macip_lens: MACLEN, VLAN tag */ 6025 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 6026 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 6027 6028 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, 6029 type_tucmd, mss_l4len_idx); 6030 } 6031 6032 static __le32 ixgbe_tx_cmd_type(u32 tx_flags) 6033 { 6034 /* set type for advanced descriptor with frame checksum insertion */ 6035 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA | 6036 IXGBE_ADVTXD_DCMD_DEXT); 6037 6038 /* set HW vlan bit if vlan is present */ 6039 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN) 6040 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE); 6041 6042 if (tx_flags & IXGBE_TX_FLAGS_TSTAMP) 6043 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP); 6044 6045 /* set segmentation enable bits for TSO/FSO */ 6046 #ifdef IXGBE_FCOE 6047 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO)) 6048 #else 6049 if (tx_flags & IXGBE_TX_FLAGS_TSO) 6050 #endif 6051 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE); 6052 6053 /* insert frame checksum */ 6054 if (!(tx_flags & IXGBE_TX_FLAGS_NO_IFCS)) 6055 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS); 6056 6057 return cmd_type; 6058 } 6059 6060 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 6061 u32 tx_flags, unsigned int paylen) 6062 { 6063 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT); 6064 6065 /* enable L4 checksum for TSO and TX checksum offload */ 6066 if (tx_flags & IXGBE_TX_FLAGS_CSUM) 6067 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM); 6068 6069 /* enble IPv4 checksum for TSO */ 6070 if (tx_flags & IXGBE_TX_FLAGS_IPV4) 6071 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM); 6072 6073 /* use index 1 context for TSO/FSO/FCOE */ 6074 #ifdef IXGBE_FCOE 6075 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE)) 6076 #else 6077 if (tx_flags & IXGBE_TX_FLAGS_TSO) 6078 #endif 6079 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT); 6080 6081 /* 6082 * Check Context must be set if Tx switch is enabled, which it 6083 * always is for case where virtual functions are running 6084 */ 6085 #ifdef IXGBE_FCOE 6086 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE)) 6087 #else 6088 if (tx_flags & IXGBE_TX_FLAGS_TXSW) 6089 #endif 6090 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC); 6091 6092 tx_desc->read.olinfo_status = olinfo_status; 6093 } 6094 6095 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ 6096 IXGBE_TXD_CMD_RS) 6097 6098 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring, 6099 struct ixgbe_tx_buffer *first, 6100 const u8 hdr_len) 6101 { 6102 dma_addr_t dma; 6103 struct sk_buff *skb = first->skb; 6104 struct ixgbe_tx_buffer *tx_buffer; 6105 union ixgbe_adv_tx_desc *tx_desc; 6106 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 6107 unsigned int data_len = skb->data_len; 6108 unsigned int size = skb_headlen(skb); 6109 unsigned int paylen = skb->len - hdr_len; 6110 u32 tx_flags = first->tx_flags; 6111 __le32 cmd_type; 6112 u16 i = tx_ring->next_to_use; 6113 6114 tx_desc = IXGBE_TX_DESC(tx_ring, i); 6115 6116 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen); 6117 cmd_type = ixgbe_tx_cmd_type(tx_flags); 6118 6119 #ifdef IXGBE_FCOE 6120 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 6121 if (data_len < sizeof(struct fcoe_crc_eof)) { 6122 size -= sizeof(struct fcoe_crc_eof) - data_len; 6123 data_len = 0; 6124 } else { 6125 data_len -= sizeof(struct fcoe_crc_eof); 6126 } 6127 } 6128 6129 #endif 6130 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6131 if (dma_mapping_error(tx_ring->dev, dma)) 6132 goto dma_error; 6133 6134 /* record length, and DMA address */ 6135 dma_unmap_len_set(first, len, size); 6136 dma_unmap_addr_set(first, dma, dma); 6137 6138 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6139 6140 for (;;) { 6141 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 6142 tx_desc->read.cmd_type_len = 6143 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD); 6144 6145 i++; 6146 tx_desc++; 6147 if (i == tx_ring->count) { 6148 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 6149 i = 0; 6150 } 6151 6152 dma += IXGBE_MAX_DATA_PER_TXD; 6153 size -= IXGBE_MAX_DATA_PER_TXD; 6154 6155 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6156 tx_desc->read.olinfo_status = 0; 6157 } 6158 6159 if (likely(!data_len)) 6160 break; 6161 6162 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size); 6163 6164 i++; 6165 tx_desc++; 6166 if (i == tx_ring->count) { 6167 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 6168 i = 0; 6169 } 6170 6171 #ifdef IXGBE_FCOE 6172 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 6173 #else 6174 size = skb_frag_size(frag); 6175 #endif 6176 data_len -= size; 6177 6178 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 6179 DMA_TO_DEVICE); 6180 if (dma_mapping_error(tx_ring->dev, dma)) 6181 goto dma_error; 6182 6183 tx_buffer = &tx_ring->tx_buffer_info[i]; 6184 dma_unmap_len_set(tx_buffer, len, size); 6185 dma_unmap_addr_set(tx_buffer, dma, dma); 6186 6187 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6188 tx_desc->read.olinfo_status = 0; 6189 6190 frag++; 6191 } 6192 6193 /* write last descriptor with RS and EOP bits */ 6194 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD); 6195 tx_desc->read.cmd_type_len = cmd_type; 6196 6197 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6198 6199 /* set the timestamp */ 6200 first->time_stamp = jiffies; 6201 6202 /* 6203 * Force memory writes to complete before letting h/w know there 6204 * are new descriptors to fetch. (Only applicable for weak-ordered 6205 * memory model archs, such as IA-64). 6206 * 6207 * We also need this memory barrier to make certain all of the 6208 * status bits have been updated before next_to_watch is written. 6209 */ 6210 wmb(); 6211 6212 /* set next_to_watch value indicating a packet is present */ 6213 first->next_to_watch = tx_desc; 6214 6215 i++; 6216 if (i == tx_ring->count) 6217 i = 0; 6218 6219 tx_ring->next_to_use = i; 6220 6221 /* notify HW of packet */ 6222 writel(i, tx_ring->tail); 6223 6224 return; 6225 dma_error: 6226 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6227 6228 /* clear dma mappings for failed tx_buffer_info map */ 6229 for (;;) { 6230 tx_buffer = &tx_ring->tx_buffer_info[i]; 6231 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer); 6232 if (tx_buffer == first) 6233 break; 6234 if (i == 0) 6235 i = tx_ring->count; 6236 i--; 6237 } 6238 6239 tx_ring->next_to_use = i; 6240 } 6241 6242 static void ixgbe_atr(struct ixgbe_ring *ring, 6243 struct ixgbe_tx_buffer *first) 6244 { 6245 struct ixgbe_q_vector *q_vector = ring->q_vector; 6246 union ixgbe_atr_hash_dword input = { .dword = 0 }; 6247 union ixgbe_atr_hash_dword common = { .dword = 0 }; 6248 union { 6249 unsigned char *network; 6250 struct iphdr *ipv4; 6251 struct ipv6hdr *ipv6; 6252 } hdr; 6253 struct tcphdr *th; 6254 __be16 vlan_id; 6255 6256 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 6257 if (!q_vector) 6258 return; 6259 6260 /* do nothing if sampling is disabled */ 6261 if (!ring->atr_sample_rate) 6262 return; 6263 6264 ring->atr_count++; 6265 6266 /* snag network header to get L4 type and address */ 6267 hdr.network = skb_network_header(first->skb); 6268 6269 /* Currently only IPv4/IPv6 with TCP is supported */ 6270 if ((first->protocol != __constant_htons(ETH_P_IPV6) || 6271 hdr.ipv6->nexthdr != IPPROTO_TCP) && 6272 (first->protocol != __constant_htons(ETH_P_IP) || 6273 hdr.ipv4->protocol != IPPROTO_TCP)) 6274 return; 6275 6276 th = tcp_hdr(first->skb); 6277 6278 /* skip this packet since it is invalid or the socket is closing */ 6279 if (!th || th->fin) 6280 return; 6281 6282 /* sample on all syn packets or once every atr sample count */ 6283 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 6284 return; 6285 6286 /* reset sample count */ 6287 ring->atr_count = 0; 6288 6289 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 6290 6291 /* 6292 * src and dst are inverted, think how the receiver sees them 6293 * 6294 * The input is broken into two sections, a non-compressed section 6295 * containing vm_pool, vlan_id, and flow_type. The rest of the data 6296 * is XORed together and stored in the compressed dword. 6297 */ 6298 input.formatted.vlan_id = vlan_id; 6299 6300 /* 6301 * since src port and flex bytes occupy the same word XOR them together 6302 * and write the value to source port portion of compressed dword 6303 */ 6304 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 6305 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q); 6306 else 6307 common.port.src ^= th->dest ^ first->protocol; 6308 common.port.dst ^= th->source; 6309 6310 if (first->protocol == __constant_htons(ETH_P_IP)) { 6311 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 6312 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 6313 } else { 6314 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 6315 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 6316 hdr.ipv6->saddr.s6_addr32[1] ^ 6317 hdr.ipv6->saddr.s6_addr32[2] ^ 6318 hdr.ipv6->saddr.s6_addr32[3] ^ 6319 hdr.ipv6->daddr.s6_addr32[0] ^ 6320 hdr.ipv6->daddr.s6_addr32[1] ^ 6321 hdr.ipv6->daddr.s6_addr32[2] ^ 6322 hdr.ipv6->daddr.s6_addr32[3]; 6323 } 6324 6325 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 6326 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 6327 input, common, ring->queue_index); 6328 } 6329 6330 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 6331 { 6332 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 6333 /* Herbert's original patch had: 6334 * smp_mb__after_netif_stop_queue(); 6335 * but since that doesn't exist yet, just open code it. */ 6336 smp_mb(); 6337 6338 /* We need to check again in a case another CPU has just 6339 * made room available. */ 6340 if (likely(ixgbe_desc_unused(tx_ring) < size)) 6341 return -EBUSY; 6342 6343 /* A reprieve! - use start_queue because it doesn't call schedule */ 6344 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 6345 ++tx_ring->tx_stats.restart_queue; 6346 return 0; 6347 } 6348 6349 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 6350 { 6351 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 6352 return 0; 6353 return __ixgbe_maybe_stop_tx(tx_ring, size); 6354 } 6355 6356 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) 6357 { 6358 struct ixgbe_adapter *adapter = netdev_priv(dev); 6359 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 6360 smp_processor_id(); 6361 #ifdef IXGBE_FCOE 6362 __be16 protocol = vlan_get_protocol(skb); 6363 6364 if (((protocol == htons(ETH_P_FCOE)) || 6365 (protocol == htons(ETH_P_FIP))) && 6366 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) { 6367 struct ixgbe_ring_feature *f; 6368 6369 f = &adapter->ring_feature[RING_F_FCOE]; 6370 6371 while (txq >= f->indices) 6372 txq -= f->indices; 6373 txq += adapter->ring_feature[RING_F_FCOE].offset; 6374 6375 return txq; 6376 } 6377 #endif 6378 6379 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 6380 while (unlikely(txq >= dev->real_num_tx_queues)) 6381 txq -= dev->real_num_tx_queues; 6382 return txq; 6383 } 6384 6385 return skb_tx_hash(dev, skb); 6386 } 6387 6388 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 6389 struct ixgbe_adapter *adapter, 6390 struct ixgbe_ring *tx_ring) 6391 { 6392 struct ixgbe_tx_buffer *first; 6393 int tso; 6394 u32 tx_flags = 0; 6395 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD 6396 unsigned short f; 6397 #endif 6398 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6399 __be16 protocol = skb->protocol; 6400 u8 hdr_len = 0; 6401 6402 /* 6403 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 6404 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 6405 * + 2 desc gap to keep tail from touching head, 6406 * + 1 desc for context descriptor, 6407 * otherwise try next time 6408 */ 6409 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD 6410 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6411 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 6412 #else 6413 count += skb_shinfo(skb)->nr_frags; 6414 #endif 6415 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 6416 tx_ring->tx_stats.tx_busy++; 6417 return NETDEV_TX_BUSY; 6418 } 6419 6420 /* record the location of the first descriptor for this packet */ 6421 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6422 first->skb = skb; 6423 first->bytecount = skb->len; 6424 first->gso_segs = 1; 6425 6426 /* if we have a HW VLAN tag being added default to the HW one */ 6427 if (vlan_tx_tag_present(skb)) { 6428 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 6429 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 6430 /* else if it is a SW VLAN check the next protocol and store the tag */ 6431 } else if (protocol == __constant_htons(ETH_P_8021Q)) { 6432 struct vlan_hdr *vhdr, _vhdr; 6433 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 6434 if (!vhdr) 6435 goto out_drop; 6436 6437 protocol = vhdr->h_vlan_encapsulated_proto; 6438 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 6439 IXGBE_TX_FLAGS_VLAN_SHIFT; 6440 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 6441 } 6442 6443 skb_tx_timestamp(skb); 6444 6445 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6446 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6447 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 6448 } 6449 6450 #ifdef CONFIG_PCI_IOV 6451 /* 6452 * Use the l2switch_enable flag - would be false if the DMA 6453 * Tx switch had been disabled. 6454 */ 6455 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 6456 tx_flags |= IXGBE_TX_FLAGS_TXSW; 6457 6458 #endif 6459 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 6460 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 6461 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 6462 (skb->priority != TC_PRIO_CONTROL))) { 6463 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 6464 tx_flags |= (skb->priority & 0x7) << 6465 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 6466 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 6467 struct vlan_ethhdr *vhdr; 6468 if (skb_header_cloned(skb) && 6469 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) 6470 goto out_drop; 6471 vhdr = (struct vlan_ethhdr *)skb->data; 6472 vhdr->h_vlan_TCI = htons(tx_flags >> 6473 IXGBE_TX_FLAGS_VLAN_SHIFT); 6474 } else { 6475 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 6476 } 6477 } 6478 6479 /* record initial flags and protocol */ 6480 first->tx_flags = tx_flags; 6481 first->protocol = protocol; 6482 6483 #ifdef IXGBE_FCOE 6484 /* setup tx offload for FCoE */ 6485 if ((protocol == __constant_htons(ETH_P_FCOE)) && 6486 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 6487 tso = ixgbe_fso(tx_ring, first, &hdr_len); 6488 if (tso < 0) 6489 goto out_drop; 6490 6491 goto xmit_fcoe; 6492 } 6493 6494 #endif /* IXGBE_FCOE */ 6495 tso = ixgbe_tso(tx_ring, first, &hdr_len); 6496 if (tso < 0) 6497 goto out_drop; 6498 else if (!tso) 6499 ixgbe_tx_csum(tx_ring, first); 6500 6501 /* add the ATR filter if ATR is on */ 6502 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 6503 ixgbe_atr(tx_ring, first); 6504 6505 #ifdef IXGBE_FCOE 6506 xmit_fcoe: 6507 #endif /* IXGBE_FCOE */ 6508 ixgbe_tx_map(tx_ring, first, hdr_len); 6509 6510 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 6511 6512 return NETDEV_TX_OK; 6513 6514 out_drop: 6515 dev_kfree_skb_any(first->skb); 6516 first->skb = NULL; 6517 6518 return NETDEV_TX_OK; 6519 } 6520 6521 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 6522 struct net_device *netdev) 6523 { 6524 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6525 struct ixgbe_ring *tx_ring; 6526 6527 /* 6528 * The minimum packet size for olinfo paylen is 17 so pad the skb 6529 * in order to meet this minimum size requirement. 6530 */ 6531 if (unlikely(skb->len < 17)) { 6532 if (skb_pad(skb, 17 - skb->len)) 6533 return NETDEV_TX_OK; 6534 skb->len = 17; 6535 skb_set_tail_pointer(skb, 17); 6536 } 6537 6538 tx_ring = adapter->tx_ring[skb->queue_mapping]; 6539 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 6540 } 6541 6542 /** 6543 * ixgbe_set_mac - Change the Ethernet Address of the NIC 6544 * @netdev: network interface device structure 6545 * @p: pointer to an address structure 6546 * 6547 * Returns 0 on success, negative on failure 6548 **/ 6549 static int ixgbe_set_mac(struct net_device *netdev, void *p) 6550 { 6551 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6552 struct ixgbe_hw *hw = &adapter->hw; 6553 struct sockaddr *addr = p; 6554 6555 if (!is_valid_ether_addr(addr->sa_data)) 6556 return -EADDRNOTAVAIL; 6557 6558 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 6559 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 6560 6561 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV); 6562 6563 return 0; 6564 } 6565 6566 static int 6567 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 6568 { 6569 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6570 struct ixgbe_hw *hw = &adapter->hw; 6571 u16 value; 6572 int rc; 6573 6574 if (prtad != hw->phy.mdio.prtad) 6575 return -EINVAL; 6576 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 6577 if (!rc) 6578 rc = value; 6579 return rc; 6580 } 6581 6582 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 6583 u16 addr, u16 value) 6584 { 6585 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6586 struct ixgbe_hw *hw = &adapter->hw; 6587 6588 if (prtad != hw->phy.mdio.prtad) 6589 return -EINVAL; 6590 return hw->phy.ops.write_reg(hw, addr, devad, value); 6591 } 6592 6593 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 6594 { 6595 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6596 6597 switch (cmd) { 6598 case SIOCSHWTSTAMP: 6599 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd); 6600 default: 6601 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 6602 } 6603 } 6604 6605 /** 6606 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 6607 * netdev->dev_addrs 6608 * @netdev: network interface device structure 6609 * 6610 * Returns non-zero on failure 6611 **/ 6612 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 6613 { 6614 int err = 0; 6615 struct ixgbe_adapter *adapter = netdev_priv(dev); 6616 struct ixgbe_hw *hw = &adapter->hw; 6617 6618 if (is_valid_ether_addr(hw->mac.san_addr)) { 6619 rtnl_lock(); 6620 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 6621 rtnl_unlock(); 6622 6623 /* update SAN MAC vmdq pool selection */ 6624 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 6625 } 6626 return err; 6627 } 6628 6629 /** 6630 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 6631 * netdev->dev_addrs 6632 * @netdev: network interface device structure 6633 * 6634 * Returns non-zero on failure 6635 **/ 6636 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 6637 { 6638 int err = 0; 6639 struct ixgbe_adapter *adapter = netdev_priv(dev); 6640 struct ixgbe_mac_info *mac = &adapter->hw.mac; 6641 6642 if (is_valid_ether_addr(mac->san_addr)) { 6643 rtnl_lock(); 6644 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 6645 rtnl_unlock(); 6646 } 6647 return err; 6648 } 6649 6650 #ifdef CONFIG_NET_POLL_CONTROLLER 6651 /* 6652 * Polling 'interrupt' - used by things like netconsole to send skbs 6653 * without having to re-enable interrupts. It's not called while 6654 * the interrupt routine is executing. 6655 */ 6656 static void ixgbe_netpoll(struct net_device *netdev) 6657 { 6658 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6659 int i; 6660 6661 /* if interface is down do nothing */ 6662 if (test_bit(__IXGBE_DOWN, &adapter->state)) 6663 return; 6664 6665 adapter->flags |= IXGBE_FLAG_IN_NETPOLL; 6666 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 6667 for (i = 0; i < adapter->num_q_vectors; i++) 6668 ixgbe_msix_clean_rings(0, adapter->q_vector[i]); 6669 } else { 6670 ixgbe_intr(adapter->pdev->irq, netdev); 6671 } 6672 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; 6673 } 6674 6675 #endif 6676 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev, 6677 struct rtnl_link_stats64 *stats) 6678 { 6679 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6680 int i; 6681 6682 rcu_read_lock(); 6683 for (i = 0; i < adapter->num_rx_queues; i++) { 6684 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); 6685 u64 bytes, packets; 6686 unsigned int start; 6687 6688 if (ring) { 6689 do { 6690 start = u64_stats_fetch_begin_bh(&ring->syncp); 6691 packets = ring->stats.packets; 6692 bytes = ring->stats.bytes; 6693 } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); 6694 stats->rx_packets += packets; 6695 stats->rx_bytes += bytes; 6696 } 6697 } 6698 6699 for (i = 0; i < adapter->num_tx_queues; i++) { 6700 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); 6701 u64 bytes, packets; 6702 unsigned int start; 6703 6704 if (ring) { 6705 do { 6706 start = u64_stats_fetch_begin_bh(&ring->syncp); 6707 packets = ring->stats.packets; 6708 bytes = ring->stats.bytes; 6709 } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); 6710 stats->tx_packets += packets; 6711 stats->tx_bytes += bytes; 6712 } 6713 } 6714 rcu_read_unlock(); 6715 /* following stats updated by ixgbe_watchdog_task() */ 6716 stats->multicast = netdev->stats.multicast; 6717 stats->rx_errors = netdev->stats.rx_errors; 6718 stats->rx_length_errors = netdev->stats.rx_length_errors; 6719 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 6720 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 6721 return stats; 6722 } 6723 6724 #ifdef CONFIG_IXGBE_DCB 6725 /** 6726 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 6727 * @adapter: pointer to ixgbe_adapter 6728 * @tc: number of traffic classes currently enabled 6729 * 6730 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 6731 * 802.1Q priority maps to a packet buffer that exists. 6732 */ 6733 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 6734 { 6735 struct ixgbe_hw *hw = &adapter->hw; 6736 u32 reg, rsave; 6737 int i; 6738 6739 /* 82598 have a static priority to TC mapping that can not 6740 * be changed so no validation is needed. 6741 */ 6742 if (hw->mac.type == ixgbe_mac_82598EB) 6743 return; 6744 6745 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 6746 rsave = reg; 6747 6748 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 6749 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 6750 6751 /* If up2tc is out of bounds default to zero */ 6752 if (up2tc > tc) 6753 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 6754 } 6755 6756 if (reg != rsave) 6757 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 6758 6759 return; 6760 } 6761 6762 /** 6763 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 6764 * @adapter: Pointer to adapter struct 6765 * 6766 * Populate the netdev user priority to tc map 6767 */ 6768 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 6769 { 6770 struct net_device *dev = adapter->netdev; 6771 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 6772 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 6773 u8 prio; 6774 6775 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 6776 u8 tc = 0; 6777 6778 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 6779 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 6780 else if (ets) 6781 tc = ets->prio_tc[prio]; 6782 6783 netdev_set_prio_tc_map(dev, prio, tc); 6784 } 6785 } 6786 6787 /** 6788 * ixgbe_setup_tc - configure net_device for multiple traffic classes 6789 * 6790 * @netdev: net device to configure 6791 * @tc: number of traffic classes to enable 6792 */ 6793 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 6794 { 6795 struct ixgbe_adapter *adapter = netdev_priv(dev); 6796 struct ixgbe_hw *hw = &adapter->hw; 6797 6798 /* Hardware supports up to 8 traffic classes */ 6799 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs || 6800 (hw->mac.type == ixgbe_mac_82598EB && 6801 tc < MAX_TRAFFIC_CLASS)) 6802 return -EINVAL; 6803 6804 /* Hardware has to reinitialize queues and interrupts to 6805 * match packet buffer alignment. Unfortunately, the 6806 * hardware is not flexible enough to do this dynamically. 6807 */ 6808 if (netif_running(dev)) 6809 ixgbe_close(dev); 6810 ixgbe_clear_interrupt_scheme(adapter); 6811 6812 if (tc) { 6813 netdev_set_num_tc(dev, tc); 6814 ixgbe_set_prio_tc_map(adapter); 6815 6816 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 6817 6818 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 6819 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 6820 adapter->hw.fc.requested_mode = ixgbe_fc_none; 6821 } 6822 } else { 6823 netdev_reset_tc(dev); 6824 6825 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 6826 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 6827 6828 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 6829 6830 adapter->temp_dcb_cfg.pfc_mode_enable = false; 6831 adapter->dcb_cfg.pfc_mode_enable = false; 6832 } 6833 6834 ixgbe_init_interrupt_scheme(adapter); 6835 ixgbe_validate_rtr(adapter, tc); 6836 if (netif_running(dev)) 6837 ixgbe_open(dev); 6838 6839 return 0; 6840 } 6841 6842 #endif /* CONFIG_IXGBE_DCB */ 6843 void ixgbe_do_reset(struct net_device *netdev) 6844 { 6845 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6846 6847 if (netif_running(netdev)) 6848 ixgbe_reinit_locked(adapter); 6849 else 6850 ixgbe_reset(adapter); 6851 } 6852 6853 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 6854 netdev_features_t features) 6855 { 6856 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6857 6858 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 6859 if (!(features & NETIF_F_RXCSUM)) 6860 features &= ~NETIF_F_LRO; 6861 6862 /* Turn off LRO if not RSC capable */ 6863 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 6864 features &= ~NETIF_F_LRO; 6865 6866 return features; 6867 } 6868 6869 static int ixgbe_set_features(struct net_device *netdev, 6870 netdev_features_t features) 6871 { 6872 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6873 netdev_features_t changed = netdev->features ^ features; 6874 bool need_reset = false; 6875 6876 /* Make sure RSC matches LRO, reset if change */ 6877 if (!(features & NETIF_F_LRO)) { 6878 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 6879 need_reset = true; 6880 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 6881 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 6882 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 6883 if (adapter->rx_itr_setting == 1 || 6884 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 6885 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 6886 need_reset = true; 6887 } else if ((changed ^ features) & NETIF_F_LRO) { 6888 e_info(probe, "rx-usecs set too low, " 6889 "disabling RSC\n"); 6890 } 6891 } 6892 6893 /* 6894 * Check if Flow Director n-tuple support was enabled or disabled. If 6895 * the state changed, we need to reset. 6896 */ 6897 switch (features & NETIF_F_NTUPLE) { 6898 case NETIF_F_NTUPLE: 6899 /* turn off ATR, enable perfect filters and reset */ 6900 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 6901 need_reset = true; 6902 6903 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 6904 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 6905 break; 6906 default: 6907 /* turn off perfect filters, enable ATR and reset */ 6908 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 6909 need_reset = true; 6910 6911 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 6912 6913 /* We cannot enable ATR if SR-IOV is enabled */ 6914 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 6915 break; 6916 6917 /* We cannot enable ATR if we have 2 or more traffic classes */ 6918 if (netdev_get_num_tc(netdev) > 1) 6919 break; 6920 6921 /* We cannot enable ATR if RSS is disabled */ 6922 if (adapter->ring_feature[RING_F_RSS].limit <= 1) 6923 break; 6924 6925 /* A sample rate of 0 indicates ATR disabled */ 6926 if (!adapter->atr_sample_rate) 6927 break; 6928 6929 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 6930 break; 6931 } 6932 6933 if (features & NETIF_F_HW_VLAN_RX) 6934 ixgbe_vlan_strip_enable(adapter); 6935 else 6936 ixgbe_vlan_strip_disable(adapter); 6937 6938 if (changed & NETIF_F_RXALL) 6939 need_reset = true; 6940 6941 netdev->features = features; 6942 if (need_reset) 6943 ixgbe_do_reset(netdev); 6944 6945 return 0; 6946 } 6947 6948 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 6949 struct net_device *dev, 6950 const unsigned char *addr, 6951 u16 flags) 6952 { 6953 struct ixgbe_adapter *adapter = netdev_priv(dev); 6954 int err; 6955 6956 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 6957 return -EOPNOTSUPP; 6958 6959 /* Hardware does not support aging addresses so if a 6960 * ndm_state is given only allow permanent addresses 6961 */ 6962 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) { 6963 pr_info("%s: FDB only supports static addresses\n", 6964 ixgbe_driver_name); 6965 return -EINVAL; 6966 } 6967 6968 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 6969 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS; 6970 6971 if (netdev_uc_count(dev) < rar_uc_entries) 6972 err = dev_uc_add_excl(dev, addr); 6973 else 6974 err = -ENOMEM; 6975 } else if (is_multicast_ether_addr(addr)) { 6976 err = dev_mc_add_excl(dev, addr); 6977 } else { 6978 err = -EINVAL; 6979 } 6980 6981 /* Only return duplicate errors if NLM_F_EXCL is set */ 6982 if (err == -EEXIST && !(flags & NLM_F_EXCL)) 6983 err = 0; 6984 6985 return err; 6986 } 6987 6988 static int ixgbe_ndo_fdb_del(struct ndmsg *ndm, 6989 struct net_device *dev, 6990 const unsigned char *addr) 6991 { 6992 struct ixgbe_adapter *adapter = netdev_priv(dev); 6993 int err = -EOPNOTSUPP; 6994 6995 if (ndm->ndm_state & NUD_PERMANENT) { 6996 pr_info("%s: FDB only supports static addresses\n", 6997 ixgbe_driver_name); 6998 return -EINVAL; 6999 } 7000 7001 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 7002 if (is_unicast_ether_addr(addr)) 7003 err = dev_uc_del(dev, addr); 7004 else if (is_multicast_ether_addr(addr)) 7005 err = dev_mc_del(dev, addr); 7006 else 7007 err = -EINVAL; 7008 } 7009 7010 return err; 7011 } 7012 7013 static int ixgbe_ndo_fdb_dump(struct sk_buff *skb, 7014 struct netlink_callback *cb, 7015 struct net_device *dev, 7016 int idx) 7017 { 7018 struct ixgbe_adapter *adapter = netdev_priv(dev); 7019 7020 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 7021 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx); 7022 7023 return idx; 7024 } 7025 7026 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 7027 struct nlmsghdr *nlh) 7028 { 7029 struct ixgbe_adapter *adapter = netdev_priv(dev); 7030 struct nlattr *attr, *br_spec; 7031 int rem; 7032 7033 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 7034 return -EOPNOTSUPP; 7035 7036 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 7037 7038 nla_for_each_nested(attr, br_spec, rem) { 7039 __u16 mode; 7040 u32 reg = 0; 7041 7042 if (nla_type(attr) != IFLA_BRIDGE_MODE) 7043 continue; 7044 7045 mode = nla_get_u16(attr); 7046 if (mode == BRIDGE_MODE_VEPA) { 7047 reg = 0; 7048 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB; 7049 } else if (mode == BRIDGE_MODE_VEB) { 7050 reg = IXGBE_PFDTXGSWC_VT_LBEN; 7051 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB; 7052 } else 7053 return -EINVAL; 7054 7055 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg); 7056 7057 e_info(drv, "enabling bridge mode: %s\n", 7058 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 7059 } 7060 7061 return 0; 7062 } 7063 7064 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 7065 struct net_device *dev) 7066 { 7067 struct ixgbe_adapter *adapter = netdev_priv(dev); 7068 u16 mode; 7069 7070 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 7071 return 0; 7072 7073 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB) 7074 mode = BRIDGE_MODE_VEB; 7075 else 7076 mode = BRIDGE_MODE_VEPA; 7077 7078 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode); 7079 } 7080 7081 static const struct net_device_ops ixgbe_netdev_ops = { 7082 .ndo_open = ixgbe_open, 7083 .ndo_stop = ixgbe_close, 7084 .ndo_start_xmit = ixgbe_xmit_frame, 7085 .ndo_select_queue = ixgbe_select_queue, 7086 .ndo_set_rx_mode = ixgbe_set_rx_mode, 7087 .ndo_validate_addr = eth_validate_addr, 7088 .ndo_set_mac_address = ixgbe_set_mac, 7089 .ndo_change_mtu = ixgbe_change_mtu, 7090 .ndo_tx_timeout = ixgbe_tx_timeout, 7091 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 7092 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 7093 .ndo_do_ioctl = ixgbe_ioctl, 7094 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 7095 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 7096 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw, 7097 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 7098 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 7099 .ndo_get_stats64 = ixgbe_get_stats64, 7100 #ifdef CONFIG_IXGBE_DCB 7101 .ndo_setup_tc = ixgbe_setup_tc, 7102 #endif 7103 #ifdef CONFIG_NET_POLL_CONTROLLER 7104 .ndo_poll_controller = ixgbe_netpoll, 7105 #endif 7106 #ifdef IXGBE_FCOE 7107 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 7108 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 7109 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 7110 .ndo_fcoe_enable = ixgbe_fcoe_enable, 7111 .ndo_fcoe_disable = ixgbe_fcoe_disable, 7112 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 7113 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 7114 #endif /* IXGBE_FCOE */ 7115 .ndo_set_features = ixgbe_set_features, 7116 .ndo_fix_features = ixgbe_fix_features, 7117 .ndo_fdb_add = ixgbe_ndo_fdb_add, 7118 .ndo_fdb_del = ixgbe_ndo_fdb_del, 7119 .ndo_fdb_dump = ixgbe_ndo_fdb_dump, 7120 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 7121 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 7122 }; 7123 7124 /** 7125 * ixgbe_wol_supported - Check whether device supports WoL 7126 * @hw: hw specific details 7127 * @device_id: the device ID 7128 * @subdev_id: the subsystem device ID 7129 * 7130 * This function is used by probe and ethtool to determine 7131 * which devices have WoL support 7132 * 7133 **/ 7134 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 7135 u16 subdevice_id) 7136 { 7137 struct ixgbe_hw *hw = &adapter->hw; 7138 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 7139 int is_wol_supported = 0; 7140 7141 switch (device_id) { 7142 case IXGBE_DEV_ID_82599_SFP: 7143 /* Only these subdevices could supports WOL */ 7144 switch (subdevice_id) { 7145 case IXGBE_SUBDEV_ID_82599_560FLR: 7146 /* only support first port */ 7147 if (hw->bus.func != 0) 7148 break; 7149 case IXGBE_SUBDEV_ID_82599_SFP: 7150 case IXGBE_SUBDEV_ID_82599_RNDC: 7151 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 7152 is_wol_supported = 1; 7153 break; 7154 } 7155 break; 7156 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 7157 /* All except this subdevice support WOL */ 7158 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 7159 is_wol_supported = 1; 7160 break; 7161 case IXGBE_DEV_ID_82599_KX4: 7162 is_wol_supported = 1; 7163 break; 7164 case IXGBE_DEV_ID_X540T: 7165 case IXGBE_DEV_ID_X540T1: 7166 /* check eeprom to see if enabled wol */ 7167 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 7168 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 7169 (hw->bus.func == 0))) { 7170 is_wol_supported = 1; 7171 } 7172 break; 7173 } 7174 7175 return is_wol_supported; 7176 } 7177 7178 /** 7179 * ixgbe_probe - Device Initialization Routine 7180 * @pdev: PCI device information struct 7181 * @ent: entry in ixgbe_pci_tbl 7182 * 7183 * Returns 0 on success, negative on failure 7184 * 7185 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 7186 * The OS initialization, configuring of the adapter private structure, 7187 * and a hardware reset occur. 7188 **/ 7189 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 7190 { 7191 struct net_device *netdev; 7192 struct ixgbe_adapter *adapter = NULL; 7193 struct ixgbe_hw *hw; 7194 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 7195 static int cards_found; 7196 int i, err, pci_using_dac; 7197 u8 part_str[IXGBE_PBANUM_LENGTH]; 7198 unsigned int indices = num_possible_cpus(); 7199 unsigned int dcb_max = 0; 7200 #ifdef IXGBE_FCOE 7201 u16 device_caps; 7202 #endif 7203 u32 eec; 7204 7205 /* Catch broken hardware that put the wrong VF device ID in 7206 * the PCIe SR-IOV capability. 7207 */ 7208 if (pdev->is_virtfn) { 7209 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 7210 pci_name(pdev), pdev->vendor, pdev->device); 7211 return -EINVAL; 7212 } 7213 7214 err = pci_enable_device_mem(pdev); 7215 if (err) 7216 return err; 7217 7218 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) && 7219 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { 7220 pci_using_dac = 1; 7221 } else { 7222 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 7223 if (err) { 7224 err = dma_set_coherent_mask(&pdev->dev, 7225 DMA_BIT_MASK(32)); 7226 if (err) { 7227 dev_err(&pdev->dev, 7228 "No usable DMA configuration, aborting\n"); 7229 goto err_dma; 7230 } 7231 } 7232 pci_using_dac = 0; 7233 } 7234 7235 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 7236 IORESOURCE_MEM), ixgbe_driver_name); 7237 if (err) { 7238 dev_err(&pdev->dev, 7239 "pci_request_selected_regions failed 0x%x\n", err); 7240 goto err_pci_reg; 7241 } 7242 7243 pci_enable_pcie_error_reporting(pdev); 7244 7245 pci_set_master(pdev); 7246 pci_save_state(pdev); 7247 7248 #ifdef CONFIG_IXGBE_DCB 7249 if (ii->mac == ixgbe_mac_82598EB) 7250 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS, 7251 IXGBE_MAX_RSS_INDICES); 7252 else 7253 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS, 7254 IXGBE_MAX_FDIR_INDICES); 7255 #endif 7256 7257 if (ii->mac == ixgbe_mac_82598EB) 7258 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES); 7259 else 7260 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES); 7261 7262 #ifdef IXGBE_FCOE 7263 indices += min_t(unsigned int, num_possible_cpus(), 7264 IXGBE_MAX_FCOE_INDICES); 7265 #endif 7266 indices = max_t(unsigned int, dcb_max, indices); 7267 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 7268 if (!netdev) { 7269 err = -ENOMEM; 7270 goto err_alloc_etherdev; 7271 } 7272 7273 SET_NETDEV_DEV(netdev, &pdev->dev); 7274 7275 adapter = netdev_priv(netdev); 7276 pci_set_drvdata(pdev, adapter); 7277 7278 adapter->netdev = netdev; 7279 adapter->pdev = pdev; 7280 hw = &adapter->hw; 7281 hw->back = adapter; 7282 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 7283 7284 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 7285 pci_resource_len(pdev, 0)); 7286 if (!hw->hw_addr) { 7287 err = -EIO; 7288 goto err_ioremap; 7289 } 7290 7291 netdev->netdev_ops = &ixgbe_netdev_ops; 7292 ixgbe_set_ethtool_ops(netdev); 7293 netdev->watchdog_timeo = 5 * HZ; 7294 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 7295 7296 adapter->bd_number = cards_found; 7297 7298 /* Setup hw api */ 7299 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); 7300 hw->mac.type = ii->mac; 7301 7302 /* EEPROM */ 7303 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); 7304 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 7305 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 7306 if (!(eec & (1 << 8))) 7307 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 7308 7309 /* PHY */ 7310 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); 7311 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 7312 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 7313 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 7314 hw->phy.mdio.mmds = 0; 7315 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 7316 hw->phy.mdio.dev = netdev; 7317 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 7318 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 7319 7320 ii->get_invariants(hw); 7321 7322 /* setup the private structure */ 7323 err = ixgbe_sw_init(adapter); 7324 if (err) 7325 goto err_sw_init; 7326 7327 /* Make it possible the adapter to be woken up via WOL */ 7328 switch (adapter->hw.mac.type) { 7329 case ixgbe_mac_82599EB: 7330 case ixgbe_mac_X540: 7331 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 7332 break; 7333 default: 7334 break; 7335 } 7336 7337 /* 7338 * If there is a fan on this device and it has failed log the 7339 * failure. 7340 */ 7341 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 7342 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 7343 if (esdp & IXGBE_ESDP_SDP1) 7344 e_crit(probe, "Fan has stopped, replace the adapter\n"); 7345 } 7346 7347 if (allow_unsupported_sfp) 7348 hw->allow_unsupported_sfp = allow_unsupported_sfp; 7349 7350 /* reset_hw fills in the perm_addr as well */ 7351 hw->phy.reset_if_overtemp = true; 7352 err = hw->mac.ops.reset_hw(hw); 7353 hw->phy.reset_if_overtemp = false; 7354 if (err == IXGBE_ERR_SFP_NOT_PRESENT && 7355 hw->mac.type == ixgbe_mac_82598EB) { 7356 err = 0; 7357 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 7358 e_dev_err("failed to load because an unsupported SFP+ " 7359 "module type was detected.\n"); 7360 e_dev_err("Reload the driver after installing a supported " 7361 "module.\n"); 7362 goto err_sw_init; 7363 } else if (err) { 7364 e_dev_err("HW Init failed: %d\n", err); 7365 goto err_sw_init; 7366 } 7367 7368 #ifdef CONFIG_PCI_IOV 7369 ixgbe_enable_sriov(adapter, ii); 7370 7371 #endif 7372 netdev->features = NETIF_F_SG | 7373 NETIF_F_IP_CSUM | 7374 NETIF_F_IPV6_CSUM | 7375 NETIF_F_HW_VLAN_TX | 7376 NETIF_F_HW_VLAN_RX | 7377 NETIF_F_HW_VLAN_FILTER | 7378 NETIF_F_TSO | 7379 NETIF_F_TSO6 | 7380 NETIF_F_RXHASH | 7381 NETIF_F_RXCSUM; 7382 7383 netdev->hw_features = netdev->features; 7384 7385 switch (adapter->hw.mac.type) { 7386 case ixgbe_mac_82599EB: 7387 case ixgbe_mac_X540: 7388 netdev->features |= NETIF_F_SCTP_CSUM; 7389 netdev->hw_features |= NETIF_F_SCTP_CSUM | 7390 NETIF_F_NTUPLE; 7391 break; 7392 default: 7393 break; 7394 } 7395 7396 netdev->hw_features |= NETIF_F_RXALL; 7397 7398 netdev->vlan_features |= NETIF_F_TSO; 7399 netdev->vlan_features |= NETIF_F_TSO6; 7400 netdev->vlan_features |= NETIF_F_IP_CSUM; 7401 netdev->vlan_features |= NETIF_F_IPV6_CSUM; 7402 netdev->vlan_features |= NETIF_F_SG; 7403 7404 netdev->priv_flags |= IFF_UNICAST_FLT; 7405 netdev->priv_flags |= IFF_SUPP_NOFCS; 7406 7407 #ifdef CONFIG_IXGBE_DCB 7408 netdev->dcbnl_ops = &dcbnl_ops; 7409 #endif 7410 7411 #ifdef IXGBE_FCOE 7412 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 7413 if (hw->mac.ops.get_device_caps) { 7414 hw->mac.ops.get_device_caps(hw, &device_caps); 7415 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 7416 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 7417 } 7418 7419 adapter->ring_feature[RING_F_FCOE].limit = IXGBE_FCRETA_SIZE; 7420 7421 netdev->features |= NETIF_F_FSO | 7422 NETIF_F_FCOE_CRC; 7423 7424 netdev->vlan_features |= NETIF_F_FSO | 7425 NETIF_F_FCOE_CRC | 7426 NETIF_F_FCOE_MTU; 7427 } 7428 #endif /* IXGBE_FCOE */ 7429 if (pci_using_dac) { 7430 netdev->features |= NETIF_F_HIGHDMA; 7431 netdev->vlan_features |= NETIF_F_HIGHDMA; 7432 } 7433 7434 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 7435 netdev->hw_features |= NETIF_F_LRO; 7436 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 7437 netdev->features |= NETIF_F_LRO; 7438 7439 /* make sure the EEPROM is good */ 7440 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 7441 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 7442 err = -EIO; 7443 goto err_sw_init; 7444 } 7445 7446 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 7447 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); 7448 7449 if (!is_valid_ether_addr(netdev->perm_addr)) { 7450 e_dev_err("invalid MAC address\n"); 7451 err = -EIO; 7452 goto err_sw_init; 7453 } 7454 7455 setup_timer(&adapter->service_timer, &ixgbe_service_timer, 7456 (unsigned long) adapter); 7457 7458 INIT_WORK(&adapter->service_task, ixgbe_service_task); 7459 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 7460 7461 err = ixgbe_init_interrupt_scheme(adapter); 7462 if (err) 7463 goto err_sw_init; 7464 7465 /* WOL not supported for all devices */ 7466 adapter->wol = 0; 7467 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 7468 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device)) 7469 adapter->wol = IXGBE_WUFC_MAG; 7470 7471 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 7472 7473 /* save off EEPROM version number */ 7474 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh); 7475 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl); 7476 7477 /* pick up the PCI bus settings for reporting later */ 7478 hw->mac.ops.get_bus_info(hw); 7479 7480 /* print bus type/speed/width info */ 7481 e_dev_info("(PCI Express:%s:%s) %pM\n", 7482 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" : 7483 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" : 7484 "Unknown"), 7485 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" : 7486 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" : 7487 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" : 7488 "Unknown"), 7489 netdev->dev_addr); 7490 7491 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH); 7492 if (err) 7493 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH); 7494 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 7495 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 7496 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 7497 part_str); 7498 else 7499 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 7500 hw->mac.type, hw->phy.type, part_str); 7501 7502 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { 7503 e_dev_warn("PCI-Express bandwidth available for this card is " 7504 "not sufficient for optimal performance.\n"); 7505 e_dev_warn("For optimal performance a x8 PCI-Express slot " 7506 "is required.\n"); 7507 } 7508 7509 /* reset the hardware with the new settings */ 7510 err = hw->mac.ops.start_hw(hw); 7511 if (err == IXGBE_ERR_EEPROM_VERSION) { 7512 /* We are running on a pre-production device, log a warning */ 7513 e_dev_warn("This device is a pre-production adapter/LOM. " 7514 "Please be aware there may be issues associated " 7515 "with your hardware. If you are experiencing " 7516 "problems please contact your Intel or hardware " 7517 "representative who provided you with this " 7518 "hardware.\n"); 7519 } 7520 strcpy(netdev->name, "eth%d"); 7521 err = register_netdev(netdev); 7522 if (err) 7523 goto err_register; 7524 7525 /* power down the optics for 82599 SFP+ fiber */ 7526 if (hw->mac.ops.disable_tx_laser) 7527 hw->mac.ops.disable_tx_laser(hw); 7528 7529 /* carrier off reporting is important to ethtool even BEFORE open */ 7530 netif_carrier_off(netdev); 7531 7532 #ifdef CONFIG_IXGBE_DCA 7533 if (dca_add_requester(&pdev->dev) == 0) { 7534 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 7535 ixgbe_setup_dca(adapter); 7536 } 7537 #endif 7538 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 7539 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 7540 for (i = 0; i < adapter->num_vfs; i++) 7541 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 7542 } 7543 7544 /* firmware requires driver version to be 0xFFFFFFFF 7545 * since os does not support feature 7546 */ 7547 if (hw->mac.ops.set_fw_drv_ver) 7548 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 7549 0xFF); 7550 7551 /* add san mac addr to netdev */ 7552 ixgbe_add_sanmac_netdev(netdev); 7553 7554 e_dev_info("%s\n", ixgbe_default_device_descr); 7555 cards_found++; 7556 7557 #ifdef CONFIG_IXGBE_HWMON 7558 if (ixgbe_sysfs_init(adapter)) 7559 e_err(probe, "failed to allocate sysfs resources\n"); 7560 #endif /* CONFIG_IXGBE_HWMON */ 7561 7562 #ifdef CONFIG_DEBUG_FS 7563 ixgbe_dbg_adapter_init(adapter); 7564 #endif /* CONFIG_DEBUG_FS */ 7565 7566 return 0; 7567 7568 err_register: 7569 ixgbe_release_hw_control(adapter); 7570 ixgbe_clear_interrupt_scheme(adapter); 7571 err_sw_init: 7572 ixgbe_disable_sriov(adapter); 7573 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 7574 iounmap(hw->hw_addr); 7575 err_ioremap: 7576 free_netdev(netdev); 7577 err_alloc_etherdev: 7578 pci_release_selected_regions(pdev, 7579 pci_select_bars(pdev, IORESOURCE_MEM)); 7580 err_pci_reg: 7581 err_dma: 7582 pci_disable_device(pdev); 7583 return err; 7584 } 7585 7586 /** 7587 * ixgbe_remove - Device Removal Routine 7588 * @pdev: PCI device information struct 7589 * 7590 * ixgbe_remove is called by the PCI subsystem to alert the driver 7591 * that it should release a PCI device. The could be caused by a 7592 * Hot-Plug event, or because the driver is going to be removed from 7593 * memory. 7594 **/ 7595 static void ixgbe_remove(struct pci_dev *pdev) 7596 { 7597 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 7598 struct net_device *netdev = adapter->netdev; 7599 7600 #ifdef CONFIG_DEBUG_FS 7601 ixgbe_dbg_adapter_exit(adapter); 7602 #endif /*CONFIG_DEBUG_FS */ 7603 7604 set_bit(__IXGBE_DOWN, &adapter->state); 7605 cancel_work_sync(&adapter->service_task); 7606 7607 7608 #ifdef CONFIG_IXGBE_DCA 7609 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 7610 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 7611 dca_remove_requester(&pdev->dev); 7612 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); 7613 } 7614 7615 #endif 7616 #ifdef CONFIG_IXGBE_HWMON 7617 ixgbe_sysfs_exit(adapter); 7618 #endif /* CONFIG_IXGBE_HWMON */ 7619 7620 /* remove the added san mac */ 7621 ixgbe_del_sanmac_netdev(netdev); 7622 7623 if (netdev->reg_state == NETREG_REGISTERED) 7624 unregister_netdev(netdev); 7625 7626 ixgbe_disable_sriov(adapter); 7627 7628 ixgbe_clear_interrupt_scheme(adapter); 7629 7630 ixgbe_release_hw_control(adapter); 7631 7632 #ifdef CONFIG_DCB 7633 kfree(adapter->ixgbe_ieee_pfc); 7634 kfree(adapter->ixgbe_ieee_ets); 7635 7636 #endif 7637 iounmap(adapter->hw.hw_addr); 7638 pci_release_selected_regions(pdev, pci_select_bars(pdev, 7639 IORESOURCE_MEM)); 7640 7641 e_dev_info("complete\n"); 7642 7643 free_netdev(netdev); 7644 7645 pci_disable_pcie_error_reporting(pdev); 7646 7647 pci_disable_device(pdev); 7648 } 7649 7650 /** 7651 * ixgbe_io_error_detected - called when PCI error is detected 7652 * @pdev: Pointer to PCI device 7653 * @state: The current pci connection state 7654 * 7655 * This function is called after a PCI bus error affecting 7656 * this device has been detected. 7657 */ 7658 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 7659 pci_channel_state_t state) 7660 { 7661 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 7662 struct net_device *netdev = adapter->netdev; 7663 7664 #ifdef CONFIG_PCI_IOV 7665 struct pci_dev *bdev, *vfdev; 7666 u32 dw0, dw1, dw2, dw3; 7667 int vf, pos; 7668 u16 req_id, pf_func; 7669 7670 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 7671 adapter->num_vfs == 0) 7672 goto skip_bad_vf_detection; 7673 7674 bdev = pdev->bus->self; 7675 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 7676 bdev = bdev->bus->self; 7677 7678 if (!bdev) 7679 goto skip_bad_vf_detection; 7680 7681 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 7682 if (!pos) 7683 goto skip_bad_vf_detection; 7684 7685 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0); 7686 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1); 7687 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2); 7688 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3); 7689 7690 req_id = dw1 >> 16; 7691 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 7692 if (!(req_id & 0x0080)) 7693 goto skip_bad_vf_detection; 7694 7695 pf_func = req_id & 0x01; 7696 if ((pf_func & 1) == (pdev->devfn & 1)) { 7697 unsigned int device_id; 7698 7699 vf = (req_id & 0x7F) >> 1; 7700 e_dev_err("VF %d has caused a PCIe error\n", vf); 7701 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 7702 "%8.8x\tdw3: %8.8x\n", 7703 dw0, dw1, dw2, dw3); 7704 switch (adapter->hw.mac.type) { 7705 case ixgbe_mac_82599EB: 7706 device_id = IXGBE_82599_VF_DEVICE_ID; 7707 break; 7708 case ixgbe_mac_X540: 7709 device_id = IXGBE_X540_VF_DEVICE_ID; 7710 break; 7711 default: 7712 device_id = 0; 7713 break; 7714 } 7715 7716 /* Find the pci device of the offending VF */ 7717 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 7718 while (vfdev) { 7719 if (vfdev->devfn == (req_id & 0xFF)) 7720 break; 7721 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 7722 device_id, vfdev); 7723 } 7724 /* 7725 * There's a slim chance the VF could have been hot plugged, 7726 * so if it is no longer present we don't need to issue the 7727 * VFLR. Just clean up the AER in that case. 7728 */ 7729 if (vfdev) { 7730 e_dev_err("Issuing VFLR to VF %d\n", vf); 7731 pci_write_config_dword(vfdev, 0xA8, 0x00008000); 7732 } 7733 7734 pci_cleanup_aer_uncorrect_error_status(pdev); 7735 } 7736 7737 /* 7738 * Even though the error may have occurred on the other port 7739 * we still need to increment the vf error reference count for 7740 * both ports because the I/O resume function will be called 7741 * for both of them. 7742 */ 7743 adapter->vferr_refcount++; 7744 7745 return PCI_ERS_RESULT_RECOVERED; 7746 7747 skip_bad_vf_detection: 7748 #endif /* CONFIG_PCI_IOV */ 7749 netif_device_detach(netdev); 7750 7751 if (state == pci_channel_io_perm_failure) 7752 return PCI_ERS_RESULT_DISCONNECT; 7753 7754 if (netif_running(netdev)) 7755 ixgbe_down(adapter); 7756 pci_disable_device(pdev); 7757 7758 /* Request a slot reset. */ 7759 return PCI_ERS_RESULT_NEED_RESET; 7760 } 7761 7762 /** 7763 * ixgbe_io_slot_reset - called after the pci bus has been reset. 7764 * @pdev: Pointer to PCI device 7765 * 7766 * Restart the card from scratch, as if from a cold-boot. 7767 */ 7768 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 7769 { 7770 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 7771 pci_ers_result_t result; 7772 int err; 7773 7774 if (pci_enable_device_mem(pdev)) { 7775 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 7776 result = PCI_ERS_RESULT_DISCONNECT; 7777 } else { 7778 pci_set_master(pdev); 7779 pci_restore_state(pdev); 7780 pci_save_state(pdev); 7781 7782 pci_wake_from_d3(pdev, false); 7783 7784 ixgbe_reset(adapter); 7785 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 7786 result = PCI_ERS_RESULT_RECOVERED; 7787 } 7788 7789 err = pci_cleanup_aer_uncorrect_error_status(pdev); 7790 if (err) { 7791 e_dev_err("pci_cleanup_aer_uncorrect_error_status " 7792 "failed 0x%0x\n", err); 7793 /* non-fatal, continue */ 7794 } 7795 7796 return result; 7797 } 7798 7799 /** 7800 * ixgbe_io_resume - called when traffic can start flowing again. 7801 * @pdev: Pointer to PCI device 7802 * 7803 * This callback is called when the error recovery driver tells us that 7804 * its OK to resume normal operation. 7805 */ 7806 static void ixgbe_io_resume(struct pci_dev *pdev) 7807 { 7808 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 7809 struct net_device *netdev = adapter->netdev; 7810 7811 #ifdef CONFIG_PCI_IOV 7812 if (adapter->vferr_refcount) { 7813 e_info(drv, "Resuming after VF err\n"); 7814 adapter->vferr_refcount--; 7815 return; 7816 } 7817 7818 #endif 7819 if (netif_running(netdev)) 7820 ixgbe_up(adapter); 7821 7822 netif_device_attach(netdev); 7823 } 7824 7825 static const struct pci_error_handlers ixgbe_err_handler = { 7826 .error_detected = ixgbe_io_error_detected, 7827 .slot_reset = ixgbe_io_slot_reset, 7828 .resume = ixgbe_io_resume, 7829 }; 7830 7831 static struct pci_driver ixgbe_driver = { 7832 .name = ixgbe_driver_name, 7833 .id_table = ixgbe_pci_tbl, 7834 .probe = ixgbe_probe, 7835 .remove = ixgbe_remove, 7836 #ifdef CONFIG_PM 7837 .suspend = ixgbe_suspend, 7838 .resume = ixgbe_resume, 7839 #endif 7840 .shutdown = ixgbe_shutdown, 7841 .err_handler = &ixgbe_err_handler 7842 }; 7843 7844 /** 7845 * ixgbe_init_module - Driver Registration Routine 7846 * 7847 * ixgbe_init_module is the first routine called when the driver is 7848 * loaded. All it does is register with the PCI subsystem. 7849 **/ 7850 static int __init ixgbe_init_module(void) 7851 { 7852 int ret; 7853 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); 7854 pr_info("%s\n", ixgbe_copyright); 7855 7856 #ifdef CONFIG_DEBUG_FS 7857 ixgbe_dbg_init(); 7858 #endif /* CONFIG_DEBUG_FS */ 7859 7860 #ifdef CONFIG_IXGBE_DCA 7861 dca_register_notify(&dca_notifier); 7862 #endif 7863 7864 ret = pci_register_driver(&ixgbe_driver); 7865 return ret; 7866 } 7867 7868 module_init(ixgbe_init_module); 7869 7870 /** 7871 * ixgbe_exit_module - Driver Exit Cleanup Routine 7872 * 7873 * ixgbe_exit_module is called just before the driver is removed 7874 * from memory. 7875 **/ 7876 static void __exit ixgbe_exit_module(void) 7877 { 7878 #ifdef CONFIG_IXGBE_DCA 7879 dca_unregister_notify(&dca_notifier); 7880 #endif 7881 pci_unregister_driver(&ixgbe_driver); 7882 7883 #ifdef CONFIG_DEBUG_FS 7884 ixgbe_dbg_exit(); 7885 #endif /* CONFIG_DEBUG_FS */ 7886 7887 rcu_barrier(); /* Wait for completion of call_rcu()'s */ 7888 } 7889 7890 #ifdef CONFIG_IXGBE_DCA 7891 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 7892 void *p) 7893 { 7894 int ret_val; 7895 7896 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 7897 __ixgbe_notify_dca); 7898 7899 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 7900 } 7901 7902 #endif /* CONFIG_IXGBE_DCA */ 7903 7904 module_exit(ixgbe_exit_module); 7905 7906 /* ixgbe_main.c */ 7907