1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2024 Intel Corporation. */ 3 4 #include <linux/types.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/netdevice.h> 8 #include <linux/vmalloc.h> 9 #include <linux/string.h> 10 #include <linux/in.h> 11 #include <linux/interrupt.h> 12 #include <linux/ip.h> 13 #include <linux/tcp.h> 14 #include <linux/sctp.h> 15 #include <linux/pkt_sched.h> 16 #include <linux/ipv6.h> 17 #include <linux/slab.h> 18 #include <net/checksum.h> 19 #include <net/ip6_checksum.h> 20 #include <linux/etherdevice.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/if_macvlan.h> 25 #include <linux/if_bridge.h> 26 #include <linux/prefetch.h> 27 #include <linux/bpf.h> 28 #include <linux/bpf_trace.h> 29 #include <linux/atomic.h> 30 #include <linux/numa.h> 31 #include <generated/utsrelease.h> 32 #include <scsi/fc/fc_fcoe.h> 33 #include <net/udp_tunnel.h> 34 #include <net/pkt_cls.h> 35 #include <net/tc_act/tc_gact.h> 36 #include <net/tc_act/tc_mirred.h> 37 #include <net/vxlan.h> 38 #include <net/mpls.h> 39 #include <net/netdev_queues.h> 40 #include <net/xdp_sock_drv.h> 41 #include <net/xfrm.h> 42 43 #include "ixgbe.h" 44 #include "ixgbe_common.h" 45 #include "ixgbe_e610.h" 46 #include "ixgbe_dcb_82599.h" 47 #include "ixgbe_mbx.h" 48 #include "ixgbe_phy.h" 49 #include "ixgbe_sriov.h" 50 #include "ixgbe_model.h" 51 #include "ixgbe_txrx_common.h" 52 53 char ixgbe_driver_name[] = "ixgbe"; 54 static const char ixgbe_driver_string[] = 55 "Intel(R) 10 Gigabit PCI Express Network Driver"; 56 #ifdef IXGBE_FCOE 57 char ixgbe_default_device_descr[] = 58 "Intel(R) 10 Gigabit Network Connection"; 59 #else 60 static char ixgbe_default_device_descr[] = 61 "Intel(R) 10 Gigabit Network Connection"; 62 #endif 63 static const char ixgbe_copyright[] = 64 "Copyright (c) 1999-2016 Intel Corporation."; 65 66 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 67 68 static const struct ixgbe_info *ixgbe_info_tbl[] = { 69 [board_82598] = &ixgbe_82598_info, 70 [board_82599] = &ixgbe_82599_info, 71 [board_X540] = &ixgbe_X540_info, 72 [board_X550] = &ixgbe_X550_info, 73 [board_X550EM_x] = &ixgbe_X550EM_x_info, 74 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info, 75 [board_x550em_a] = &ixgbe_x550em_a_info, 76 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info, 77 [board_e610] = &ixgbe_e610_info, 78 }; 79 80 /* ixgbe_pci_tbl - PCI Device ID Table 81 * 82 * Wildcard entries (PCI_ANY_ID) should come last 83 * Last entry must be all 0s 84 * 85 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 86 * Class, Class Mask, private data (not used) } 87 */ 88 static const struct pci_device_id ixgbe_pci_tbl[] = { 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550}, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x}, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw}, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a }, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a }, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a }, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a }, 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a}, 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a }, 134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw }, 135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw }, 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_E610_BACKPLANE), board_e610}, 137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_E610_SFP), board_e610}, 138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_E610_10G_T), board_e610}, 139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_E610_2_5G_T), board_e610}, 140 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_E610_SGMII), board_e610}, 141 /* required last entry */ 142 {0, } 143 }; 144 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 145 146 #ifdef CONFIG_IXGBE_DCA 147 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 148 void *p); 149 static struct notifier_block dca_notifier = { 150 .notifier_call = ixgbe_notify_dca, 151 .next = NULL, 152 .priority = 0 153 }; 154 #endif 155 156 #ifdef CONFIG_PCI_IOV 157 static unsigned int max_vfs; 158 module_param(max_vfs, uint, 0); 159 MODULE_PARM_DESC(max_vfs, 160 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 161 #endif /* CONFIG_PCI_IOV */ 162 163 static bool allow_unsupported_sfp; 164 module_param(allow_unsupported_sfp, bool, 0444); 165 MODULE_PARM_DESC(allow_unsupported_sfp, 166 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 167 168 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 169 static int debug = -1; 170 module_param(debug, int, 0); 171 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 172 173 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 174 MODULE_LICENSE("GPL v2"); 175 176 DEFINE_STATIC_KEY_FALSE(ixgbe_xdp_locking_key); 177 EXPORT_SYMBOL(ixgbe_xdp_locking_key); 178 179 static struct workqueue_struct *ixgbe_wq; 180 181 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 182 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *); 183 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *); 184 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *); 185 186 static const struct net_device_ops ixgbe_netdev_ops; 187 188 static bool netif_is_ixgbe(struct net_device *dev) 189 { 190 return dev && (dev->netdev_ops == &ixgbe_netdev_ops); 191 } 192 193 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 194 u32 reg, u16 *value) 195 { 196 struct pci_dev *parent_dev; 197 struct pci_bus *parent_bus; 198 199 parent_bus = adapter->pdev->bus->parent; 200 if (!parent_bus) 201 return -1; 202 203 parent_dev = parent_bus->self; 204 if (!parent_dev) 205 return -1; 206 207 if (!pci_is_pcie(parent_dev)) 208 return -1; 209 210 pcie_capability_read_word(parent_dev, reg, value); 211 if (*value == IXGBE_FAILED_READ_CFG_WORD && 212 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 213 return -1; 214 return 0; 215 } 216 217 static int ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 218 { 219 struct ixgbe_hw *hw = &adapter->hw; 220 u16 link_status = 0; 221 int err; 222 223 hw->bus.type = ixgbe_bus_type_pci_express; 224 225 /* Get the negotiated link width and speed from PCI config space of the 226 * parent, as this device is behind a switch 227 */ 228 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 229 230 /* assume caller will handle error case */ 231 if (err) 232 return err; 233 234 hw->bus.width = ixgbe_convert_bus_width(link_status); 235 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 236 237 return 0; 238 } 239 240 /** 241 * ixgbe_pcie_from_parent - Determine whether PCIe info should come from parent 242 * @hw: hw specific details 243 * 244 * This function is used by probe to determine whether a device's PCI-Express 245 * bandwidth details should be gathered from the parent bus instead of from the 246 * device. Used to ensure that various locations all have the correct device ID 247 * checks. 248 * 249 * Return: true if information should be collected from the parent bus, false 250 * otherwise 251 */ 252 static bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 253 { 254 switch (hw->device_id) { 255 case IXGBE_DEV_ID_82599_SFP_SF_QP: 256 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 257 return true; 258 default: 259 return false; 260 } 261 } 262 263 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 264 int expected_gts) 265 { 266 struct ixgbe_hw *hw = &adapter->hw; 267 struct pci_dev *pdev; 268 269 /* Some devices are not connected over PCIe and thus do not negotiate 270 * speed. These devices do not have valid bus info, and thus any report 271 * we generate may not be correct. 272 */ 273 if (hw->bus.type == ixgbe_bus_type_internal) 274 return; 275 276 /* determine whether to use the parent device */ 277 if (ixgbe_pcie_from_parent(&adapter->hw)) 278 pdev = adapter->pdev->bus->parent->self; 279 else 280 pdev = adapter->pdev; 281 282 pcie_print_link_status(pdev); 283 } 284 285 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 286 { 287 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 288 !test_bit(__IXGBE_REMOVING, &adapter->state) && 289 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 290 queue_work(ixgbe_wq, &adapter->service_task); 291 } 292 293 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 294 { 295 struct ixgbe_adapter *adapter = hw->back; 296 297 if (!hw->hw_addr) 298 return; 299 hw->hw_addr = NULL; 300 e_dev_err("Adapter removed\n"); 301 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 302 ixgbe_service_event_schedule(adapter); 303 } 304 305 static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 306 { 307 u8 __iomem *reg_addr; 308 u32 value; 309 int i; 310 311 reg_addr = READ_ONCE(hw->hw_addr); 312 if (ixgbe_removed(reg_addr)) 313 return IXGBE_FAILED_READ_REG; 314 315 /* Register read of 0xFFFFFFF can indicate the adapter has been removed, 316 * so perform several status register reads to determine if the adapter 317 * has been removed. 318 */ 319 for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) { 320 value = readl(reg_addr + IXGBE_STATUS); 321 if (value != IXGBE_FAILED_READ_REG) 322 break; 323 mdelay(3); 324 } 325 326 if (value == IXGBE_FAILED_READ_REG) 327 ixgbe_remove_adapter(hw); 328 else 329 value = readl(reg_addr + reg); 330 return value; 331 } 332 333 /** 334 * ixgbe_read_reg - Read from device register 335 * @hw: hw specific details 336 * @reg: offset of register to read 337 * 338 * Returns : value read or IXGBE_FAILED_READ_REG if removed 339 * 340 * This function is used to read device registers. It checks for device 341 * removal by confirming any read that returns all ones by checking the 342 * status register value for all ones. This function avoids reading from 343 * the hardware if a removal was previously detected in which case it 344 * returns IXGBE_FAILED_READ_REG (all ones). 345 */ 346 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 347 { 348 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr); 349 u32 value; 350 351 if (ixgbe_removed(reg_addr)) 352 return IXGBE_FAILED_READ_REG; 353 if (unlikely(hw->phy.nw_mng_if_sel & 354 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) { 355 struct ixgbe_adapter *adapter; 356 int i; 357 358 for (i = 0; i < 200; ++i) { 359 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); 360 if (likely(!value)) 361 goto writes_completed; 362 if (value == IXGBE_FAILED_READ_REG) { 363 ixgbe_remove_adapter(hw); 364 return IXGBE_FAILED_READ_REG; 365 } 366 udelay(5); 367 } 368 369 adapter = hw->back; 370 e_warn(hw, "register writes incomplete %08x\n", value); 371 } 372 373 writes_completed: 374 value = readl(reg_addr + reg); 375 if (unlikely(value == IXGBE_FAILED_READ_REG)) 376 value = ixgbe_check_remove(hw, reg); 377 return value; 378 } 379 380 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 381 { 382 u16 value; 383 384 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 385 if (value == IXGBE_FAILED_READ_CFG_WORD) { 386 ixgbe_remove_adapter(hw); 387 return true; 388 } 389 return false; 390 } 391 392 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 393 { 394 struct ixgbe_adapter *adapter = hw->back; 395 u16 value; 396 397 if (ixgbe_removed(hw->hw_addr)) 398 return IXGBE_FAILED_READ_CFG_WORD; 399 pci_read_config_word(adapter->pdev, reg, &value); 400 if (value == IXGBE_FAILED_READ_CFG_WORD && 401 ixgbe_check_cfg_remove(hw, adapter->pdev)) 402 return IXGBE_FAILED_READ_CFG_WORD; 403 return value; 404 } 405 406 #ifdef CONFIG_PCI_IOV 407 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 408 { 409 struct ixgbe_adapter *adapter = hw->back; 410 u32 value; 411 412 if (ixgbe_removed(hw->hw_addr)) 413 return IXGBE_FAILED_READ_CFG_DWORD; 414 pci_read_config_dword(adapter->pdev, reg, &value); 415 if (value == IXGBE_FAILED_READ_CFG_DWORD && 416 ixgbe_check_cfg_remove(hw, adapter->pdev)) 417 return IXGBE_FAILED_READ_CFG_DWORD; 418 return value; 419 } 420 #endif /* CONFIG_PCI_IOV */ 421 422 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 423 { 424 struct ixgbe_adapter *adapter = hw->back; 425 426 if (ixgbe_removed(hw->hw_addr)) 427 return; 428 pci_write_config_word(adapter->pdev, reg, value); 429 } 430 431 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 432 { 433 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 434 435 /* flush memory to make sure state is correct before next watchdog */ 436 smp_mb__before_atomic(); 437 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 438 } 439 440 struct ixgbe_reg_info { 441 u32 ofs; 442 char *name; 443 }; 444 445 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 446 447 /* General Registers */ 448 {IXGBE_CTRL, "CTRL"}, 449 {IXGBE_STATUS, "STATUS"}, 450 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 451 452 /* Interrupt Registers */ 453 {IXGBE_EICR, "EICR"}, 454 455 /* RX Registers */ 456 {IXGBE_SRRCTL(0), "SRRCTL"}, 457 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 458 {IXGBE_RDLEN(0), "RDLEN"}, 459 {IXGBE_RDH(0), "RDH"}, 460 {IXGBE_RDT(0), "RDT"}, 461 {IXGBE_RXDCTL(0), "RXDCTL"}, 462 {IXGBE_RDBAL(0), "RDBAL"}, 463 {IXGBE_RDBAH(0), "RDBAH"}, 464 465 /* TX Registers */ 466 {IXGBE_TDBAL(0), "TDBAL"}, 467 {IXGBE_TDBAH(0), "TDBAH"}, 468 {IXGBE_TDLEN(0), "TDLEN"}, 469 {IXGBE_TDH(0), "TDH"}, 470 {IXGBE_TDT(0), "TDT"}, 471 {IXGBE_TXDCTL(0), "TXDCTL"}, 472 473 /* List Terminator */ 474 { .name = NULL } 475 }; 476 477 478 /* 479 * ixgbe_regdump - register printout routine 480 */ 481 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 482 { 483 int i; 484 char rname[16]; 485 u32 regs[64]; 486 487 switch (reginfo->ofs) { 488 case IXGBE_SRRCTL(0): 489 for (i = 0; i < 64; i++) 490 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 491 break; 492 case IXGBE_DCA_RXCTRL(0): 493 for (i = 0; i < 64; i++) 494 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 495 break; 496 case IXGBE_RDLEN(0): 497 for (i = 0; i < 64; i++) 498 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 499 break; 500 case IXGBE_RDH(0): 501 for (i = 0; i < 64; i++) 502 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 503 break; 504 case IXGBE_RDT(0): 505 for (i = 0; i < 64; i++) 506 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 507 break; 508 case IXGBE_RXDCTL(0): 509 for (i = 0; i < 64; i++) 510 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 511 break; 512 case IXGBE_RDBAL(0): 513 for (i = 0; i < 64; i++) 514 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 515 break; 516 case IXGBE_RDBAH(0): 517 for (i = 0; i < 64; i++) 518 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 519 break; 520 case IXGBE_TDBAL(0): 521 for (i = 0; i < 64; i++) 522 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 523 break; 524 case IXGBE_TDBAH(0): 525 for (i = 0; i < 64; i++) 526 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 527 break; 528 case IXGBE_TDLEN(0): 529 for (i = 0; i < 64; i++) 530 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 531 break; 532 case IXGBE_TDH(0): 533 for (i = 0; i < 64; i++) 534 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 535 break; 536 case IXGBE_TDT(0): 537 for (i = 0; i < 64; i++) 538 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 539 break; 540 case IXGBE_TXDCTL(0): 541 for (i = 0; i < 64; i++) 542 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 543 break; 544 default: 545 pr_info("%-15s %08x\n", 546 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs)); 547 return; 548 } 549 550 i = 0; 551 while (i < 64) { 552 int j; 553 char buf[9 * 8 + 1]; 554 char *p = buf; 555 556 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7); 557 for (j = 0; j < 8; j++) 558 p += sprintf(p, " %08x", regs[i++]); 559 pr_err("%-15s%s\n", rname, buf); 560 } 561 562 } 563 564 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n) 565 { 566 struct ixgbe_tx_buffer *tx_buffer; 567 568 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean]; 569 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 570 n, ring->next_to_use, ring->next_to_clean, 571 (u64)dma_unmap_addr(tx_buffer, dma), 572 dma_unmap_len(tx_buffer, len), 573 tx_buffer->next_to_watch, 574 (u64)tx_buffer->time_stamp); 575 } 576 577 /* 578 * ixgbe_dump - Print registers, tx-rings and rx-rings 579 */ 580 static void ixgbe_dump(struct ixgbe_adapter *adapter) 581 { 582 struct net_device *netdev = adapter->netdev; 583 struct ixgbe_hw *hw = &adapter->hw; 584 struct ixgbe_reg_info *reginfo; 585 int n = 0; 586 struct ixgbe_ring *ring; 587 struct ixgbe_tx_buffer *tx_buffer; 588 union ixgbe_adv_tx_desc *tx_desc; 589 struct my_u0 { u64 a; u64 b; } *u0; 590 struct ixgbe_ring *rx_ring; 591 union ixgbe_adv_rx_desc *rx_desc; 592 struct ixgbe_rx_buffer *rx_buffer_info; 593 int i = 0; 594 595 if (!netif_msg_hw(adapter)) 596 return; 597 598 /* Print netdevice Info */ 599 if (netdev) { 600 dev_info(&adapter->pdev->dev, "Net device Info\n"); 601 pr_info("Device Name state " 602 "trans_start\n"); 603 pr_info("%-15s %016lX %016lX\n", 604 netdev->name, 605 netdev->state, 606 dev_trans_start(netdev)); 607 } 608 609 /* Print Registers */ 610 dev_info(&adapter->pdev->dev, "Register Dump\n"); 611 pr_info(" Register Name Value\n"); 612 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 613 reginfo->name; reginfo++) { 614 ixgbe_regdump(hw, reginfo); 615 } 616 617 /* Print TX Ring Summary */ 618 if (!netdev || !netif_running(netdev)) 619 return; 620 621 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 622 pr_info(" %s %s %s %s\n", 623 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 624 "leng", "ntw", "timestamp"); 625 for (n = 0; n < adapter->num_tx_queues; n++) { 626 ring = adapter->tx_ring[n]; 627 ixgbe_print_buffer(ring, n); 628 } 629 630 for (n = 0; n < adapter->num_xdp_queues; n++) { 631 ring = adapter->xdp_ring[n]; 632 ixgbe_print_buffer(ring, n); 633 } 634 635 /* Print TX Rings */ 636 if (!netif_msg_tx_done(adapter)) 637 goto rx_ring_summary; 638 639 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 640 641 /* Transmit Descriptor Formats 642 * 643 * 82598 Advanced Transmit Descriptor 644 * +--------------------------------------------------------------+ 645 * 0 | Buffer Address [63:0] | 646 * +--------------------------------------------------------------+ 647 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 648 * +--------------------------------------------------------------+ 649 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 650 * 651 * 82598 Advanced Transmit Descriptor (Write-Back Format) 652 * +--------------------------------------------------------------+ 653 * 0 | RSV [63:0] | 654 * +--------------------------------------------------------------+ 655 * 8 | RSV | STA | NXTSEQ | 656 * +--------------------------------------------------------------+ 657 * 63 36 35 32 31 0 658 * 659 * 82599+ Advanced Transmit Descriptor 660 * +--------------------------------------------------------------+ 661 * 0 | Buffer Address [63:0] | 662 * +--------------------------------------------------------------+ 663 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 664 * +--------------------------------------------------------------+ 665 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 666 * 667 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 668 * +--------------------------------------------------------------+ 669 * 0 | RSV [63:0] | 670 * +--------------------------------------------------------------+ 671 * 8 | RSV | STA | RSV | 672 * +--------------------------------------------------------------+ 673 * 63 36 35 32 31 0 674 */ 675 676 for (n = 0; n < adapter->num_tx_queues; n++) { 677 ring = adapter->tx_ring[n]; 678 pr_info("------------------------------------\n"); 679 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index); 680 pr_info("------------------------------------\n"); 681 pr_info("%s%s %s %s %s %s\n", 682 "T [desc] [address 63:0 ] ", 683 "[PlPOIdStDDt Ln] [bi->dma ] ", 684 "leng", "ntw", "timestamp", "bi->skb"); 685 686 for (i = 0; ring->desc && (i < ring->count); i++) { 687 tx_desc = IXGBE_TX_DESC(ring, i); 688 tx_buffer = &ring->tx_buffer_info[i]; 689 u0 = (struct my_u0 *)tx_desc; 690 if (dma_unmap_len(tx_buffer, len) > 0) { 691 const char *ring_desc; 692 693 if (i == ring->next_to_use && 694 i == ring->next_to_clean) 695 ring_desc = " NTC/U"; 696 else if (i == ring->next_to_use) 697 ring_desc = " NTU"; 698 else if (i == ring->next_to_clean) 699 ring_desc = " NTC"; 700 else 701 ring_desc = ""; 702 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s", 703 i, 704 le64_to_cpu((__force __le64)u0->a), 705 le64_to_cpu((__force __le64)u0->b), 706 (u64)dma_unmap_addr(tx_buffer, dma), 707 dma_unmap_len(tx_buffer, len), 708 tx_buffer->next_to_watch, 709 (u64)tx_buffer->time_stamp, 710 tx_buffer->skb, 711 ring_desc); 712 713 if (netif_msg_pktdata(adapter) && 714 tx_buffer->skb) 715 print_hex_dump(KERN_INFO, "", 716 DUMP_PREFIX_ADDRESS, 16, 1, 717 tx_buffer->skb->data, 718 dma_unmap_len(tx_buffer, len), 719 true); 720 } 721 } 722 } 723 724 /* Print RX Rings Summary */ 725 rx_ring_summary: 726 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 727 pr_info("Queue [NTU] [NTC]\n"); 728 for (n = 0; n < adapter->num_rx_queues; n++) { 729 rx_ring = adapter->rx_ring[n]; 730 pr_info("%5d %5X %5X\n", 731 n, rx_ring->next_to_use, rx_ring->next_to_clean); 732 } 733 734 /* Print RX Rings */ 735 if (!netif_msg_rx_status(adapter)) 736 return; 737 738 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 739 740 /* Receive Descriptor Formats 741 * 742 * 82598 Advanced Receive Descriptor (Read) Format 743 * 63 1 0 744 * +-----------------------------------------------------+ 745 * 0 | Packet Buffer Address [63:1] |A0/NSE| 746 * +----------------------------------------------+------+ 747 * 8 | Header Buffer Address [63:1] | DD | 748 * +-----------------------------------------------------+ 749 * 750 * 751 * 82598 Advanced Receive Descriptor (Write-Back) Format 752 * 753 * 63 48 47 32 31 30 21 20 16 15 4 3 0 754 * +------------------------------------------------------+ 755 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 756 * | Packet | IP | | | | Type | Type | 757 * | Checksum | Ident | | | | | | 758 * +------------------------------------------------------+ 759 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 760 * +------------------------------------------------------+ 761 * 63 48 47 32 31 20 19 0 762 * 763 * 82599+ Advanced Receive Descriptor (Read) Format 764 * 63 1 0 765 * +-----------------------------------------------------+ 766 * 0 | Packet Buffer Address [63:1] |A0/NSE| 767 * +----------------------------------------------+------+ 768 * 8 | Header Buffer Address [63:1] | DD | 769 * +-----------------------------------------------------+ 770 * 771 * 772 * 82599+ Advanced Receive Descriptor (Write-Back) Format 773 * 774 * 63 48 47 32 31 30 21 20 17 16 4 3 0 775 * +------------------------------------------------------+ 776 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 777 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 778 * |/ Flow Dir Flt ID | | | | | | 779 * +------------------------------------------------------+ 780 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 781 * +------------------------------------------------------+ 782 * 63 48 47 32 31 20 19 0 783 */ 784 785 for (n = 0; n < adapter->num_rx_queues; n++) { 786 rx_ring = adapter->rx_ring[n]; 787 pr_info("------------------------------------\n"); 788 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 789 pr_info("------------------------------------\n"); 790 pr_info("%s%s%s\n", 791 "R [desc] [ PktBuf A0] ", 792 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 793 "<-- Adv Rx Read format"); 794 pr_info("%s%s%s\n", 795 "RWB[desc] [PcsmIpSHl PtRs] ", 796 "[vl er S cks ln] ---------------- [bi->skb ] ", 797 "<-- Adv Rx Write-Back format"); 798 799 for (i = 0; i < rx_ring->count; i++) { 800 const char *ring_desc; 801 802 if (i == rx_ring->next_to_use) 803 ring_desc = " NTU"; 804 else if (i == rx_ring->next_to_clean) 805 ring_desc = " NTC"; 806 else 807 ring_desc = ""; 808 809 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 810 rx_desc = IXGBE_RX_DESC(rx_ring, i); 811 u0 = (struct my_u0 *)rx_desc; 812 if (rx_desc->wb.upper.length) { 813 /* Descriptor Done */ 814 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n", 815 i, 816 le64_to_cpu((__force __le64)u0->a), 817 le64_to_cpu((__force __le64)u0->b), 818 rx_buffer_info->skb, 819 ring_desc); 820 } else { 821 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n", 822 i, 823 le64_to_cpu((__force __le64)u0->a), 824 le64_to_cpu((__force __le64)u0->b), 825 (u64)rx_buffer_info->dma, 826 rx_buffer_info->skb, 827 ring_desc); 828 829 if (netif_msg_pktdata(adapter) && 830 rx_buffer_info->dma) { 831 print_hex_dump(KERN_INFO, "", 832 DUMP_PREFIX_ADDRESS, 16, 1, 833 page_address(rx_buffer_info->page) + 834 rx_buffer_info->page_offset, 835 ixgbe_rx_bufsz(rx_ring), true); 836 } 837 } 838 } 839 } 840 } 841 842 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 843 { 844 u32 ctrl_ext; 845 846 /* Let firmware take over control of h/w */ 847 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 848 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 849 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 850 } 851 852 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 853 { 854 u32 ctrl_ext; 855 856 /* Let firmware know the driver has taken over */ 857 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 858 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 859 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 860 } 861 862 /** 863 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 864 * @adapter: pointer to adapter struct 865 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 866 * @queue: queue to map the corresponding interrupt to 867 * @msix_vector: the vector to map to the corresponding queue 868 * 869 */ 870 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 871 u8 queue, u8 msix_vector) 872 { 873 u32 ivar, index; 874 struct ixgbe_hw *hw = &adapter->hw; 875 switch (hw->mac.type) { 876 case ixgbe_mac_82598EB: 877 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 878 if (direction == -1) 879 direction = 0; 880 index = (((direction * 64) + queue) >> 2) & 0x1F; 881 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 882 ivar &= ~(0xFF << (8 * (queue & 0x3))); 883 ivar |= (msix_vector << (8 * (queue & 0x3))); 884 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 885 break; 886 case ixgbe_mac_82599EB: 887 case ixgbe_mac_X540: 888 case ixgbe_mac_X550: 889 case ixgbe_mac_X550EM_x: 890 case ixgbe_mac_x550em_a: 891 case ixgbe_mac_e610: 892 if (direction == -1) { 893 /* other causes */ 894 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 895 index = ((queue & 1) * 8); 896 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 897 ivar &= ~(0xFF << index); 898 ivar |= (msix_vector << index); 899 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 900 break; 901 } else { 902 /* tx or rx causes */ 903 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 904 index = ((16 * (queue & 1)) + (8 * direction)); 905 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 906 ivar &= ~(0xFF << index); 907 ivar |= (msix_vector << index); 908 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 909 break; 910 } 911 default: 912 break; 913 } 914 } 915 916 void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 917 u64 qmask) 918 { 919 u32 mask; 920 921 switch (adapter->hw.mac.type) { 922 case ixgbe_mac_82598EB: 923 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 924 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 925 break; 926 case ixgbe_mac_82599EB: 927 case ixgbe_mac_X540: 928 case ixgbe_mac_X550: 929 case ixgbe_mac_X550EM_x: 930 case ixgbe_mac_x550em_a: 931 case ixgbe_mac_e610: 932 mask = (qmask & 0xFFFFFFFF); 933 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 934 mask = (qmask >> 32); 935 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 936 break; 937 default: 938 break; 939 } 940 } 941 942 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 943 { 944 struct ixgbe_hw *hw = &adapter->hw; 945 struct ixgbe_hw_stats *hwstats = &adapter->stats; 946 int i; 947 u32 data; 948 949 if ((hw->fc.current_mode != ixgbe_fc_full) && 950 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 951 return; 952 953 switch (hw->mac.type) { 954 case ixgbe_mac_82598EB: 955 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 956 break; 957 default: 958 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 959 } 960 hwstats->lxoffrxc += data; 961 962 /* refill credits (no tx hang) if we received xoff */ 963 if (!data) 964 return; 965 966 for (i = 0; i < adapter->num_tx_queues; i++) 967 clear_bit(__IXGBE_HANG_CHECK_ARMED, 968 &adapter->tx_ring[i]->state); 969 970 for (i = 0; i < adapter->num_xdp_queues; i++) 971 clear_bit(__IXGBE_HANG_CHECK_ARMED, 972 &adapter->xdp_ring[i]->state); 973 } 974 975 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 976 { 977 struct ixgbe_hw *hw = &adapter->hw; 978 struct ixgbe_hw_stats *hwstats = &adapter->stats; 979 u32 xoff[8] = {0}; 980 u8 tc; 981 int i; 982 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 983 984 if (adapter->ixgbe_ieee_pfc) 985 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 986 987 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 988 ixgbe_update_xoff_rx_lfc(adapter); 989 return; 990 } 991 992 /* update stats for each tc, only valid with PFC enabled */ 993 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 994 u32 pxoffrxc; 995 996 switch (hw->mac.type) { 997 case ixgbe_mac_82598EB: 998 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 999 break; 1000 default: 1001 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 1002 } 1003 hwstats->pxoffrxc[i] += pxoffrxc; 1004 /* Get the TC for given UP */ 1005 tc = netdev_get_prio_tc_map(adapter->netdev, i); 1006 xoff[tc] += pxoffrxc; 1007 } 1008 1009 /* disarm tx queues that have received xoff frames */ 1010 for (i = 0; i < adapter->num_tx_queues; i++) { 1011 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 1012 1013 tc = tx_ring->dcb_tc; 1014 if (xoff[tc]) 1015 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1016 } 1017 1018 for (i = 0; i < adapter->num_xdp_queues; i++) { 1019 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 1020 1021 tc = xdp_ring->dcb_tc; 1022 if (xoff[tc]) 1023 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state); 1024 } 1025 } 1026 1027 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1028 { 1029 return ring->stats.packets; 1030 } 1031 1032 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1033 { 1034 unsigned int head, tail; 1035 1036 head = ring->next_to_clean; 1037 tail = ring->next_to_use; 1038 1039 return ((head <= tail) ? tail : tail + ring->count) - head; 1040 } 1041 1042 static bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1043 { 1044 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1045 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1046 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1047 1048 clear_check_for_tx_hang(tx_ring); 1049 1050 /* 1051 * Check for a hung queue, but be thorough. This verifies 1052 * that a transmit has been completed since the previous 1053 * check AND there is at least one packet pending. The 1054 * ARMED bit is set to indicate a potential hang. The 1055 * bit is cleared if a pause frame is received to remove 1056 * false hang detection due to PFC or 802.3x frames. By 1057 * requiring this to fail twice we avoid races with 1058 * pfc clearing the ARMED bit and conditions where we 1059 * run the check_tx_hang logic with a transmit completion 1060 * pending but without time to complete it yet. 1061 */ 1062 if (tx_done_old == tx_done && tx_pending) 1063 /* make sure it is true for two checks in a row */ 1064 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1065 &tx_ring->state); 1066 /* update completed stats and continue */ 1067 tx_ring->tx_stats.tx_done_old = tx_done; 1068 /* reset the countdown */ 1069 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1070 1071 return false; 1072 } 1073 1074 /** 1075 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1076 * @adapter: driver private struct 1077 **/ 1078 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1079 { 1080 1081 /* Do the reset outside of interrupt context */ 1082 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1083 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 1084 e_warn(drv, "initiating reset due to tx timeout\n"); 1085 ixgbe_service_event_schedule(adapter); 1086 } 1087 } 1088 1089 /** 1090 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate 1091 * @netdev: network interface device structure 1092 * @queue_index: Tx queue to set 1093 * @maxrate: desired maximum transmit bitrate 1094 **/ 1095 static int ixgbe_tx_maxrate(struct net_device *netdev, 1096 int queue_index, u32 maxrate) 1097 { 1098 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1099 struct ixgbe_hw *hw = &adapter->hw; 1100 u32 bcnrc_val = ixgbe_link_mbps(adapter); 1101 1102 if (!maxrate) 1103 return 0; 1104 1105 /* Calculate the rate factor values to set */ 1106 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; 1107 bcnrc_val /= maxrate; 1108 1109 /* clear everything but the rate factor */ 1110 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | 1111 IXGBE_RTTBCNRC_RF_DEC_MASK; 1112 1113 /* enable the rate scheduler */ 1114 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; 1115 1116 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); 1117 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 1118 1119 return 0; 1120 } 1121 1122 /** 1123 * ixgbe_update_tx_ring_stats - Update Tx ring specific counters 1124 * @tx_ring: ring to update 1125 * @q_vector: queue vector ring belongs to 1126 * @pkts: number of processed packets 1127 * @bytes: number of processed bytes 1128 */ 1129 void ixgbe_update_tx_ring_stats(struct ixgbe_ring *tx_ring, 1130 struct ixgbe_q_vector *q_vector, u64 pkts, 1131 u64 bytes) 1132 { 1133 u64_stats_update_begin(&tx_ring->syncp); 1134 tx_ring->stats.bytes += bytes; 1135 tx_ring->stats.packets += pkts; 1136 u64_stats_update_end(&tx_ring->syncp); 1137 q_vector->tx.total_bytes += bytes; 1138 q_vector->tx.total_packets += pkts; 1139 } 1140 1141 /** 1142 * ixgbe_update_rx_ring_stats - Update Rx ring specific counters 1143 * @rx_ring: ring to update 1144 * @q_vector: queue vector ring belongs to 1145 * @pkts: number of processed packets 1146 * @bytes: number of processed bytes 1147 */ 1148 void ixgbe_update_rx_ring_stats(struct ixgbe_ring *rx_ring, 1149 struct ixgbe_q_vector *q_vector, u64 pkts, 1150 u64 bytes) 1151 { 1152 u64_stats_update_begin(&rx_ring->syncp); 1153 rx_ring->stats.bytes += bytes; 1154 rx_ring->stats.packets += pkts; 1155 u64_stats_update_end(&rx_ring->syncp); 1156 q_vector->rx.total_bytes += bytes; 1157 q_vector->rx.total_packets += pkts; 1158 } 1159 1160 /** 1161 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1162 * @q_vector: structure containing interrupt and ring information 1163 * @tx_ring: tx ring to clean 1164 * @napi_budget: Used to determine if we are in netpoll 1165 **/ 1166 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1167 struct ixgbe_ring *tx_ring, int napi_budget) 1168 { 1169 struct ixgbe_adapter *adapter = q_vector->adapter; 1170 struct ixgbe_tx_buffer *tx_buffer; 1171 union ixgbe_adv_tx_desc *tx_desc; 1172 unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0; 1173 unsigned int budget = q_vector->tx.work_limit; 1174 unsigned int i = tx_ring->next_to_clean; 1175 struct netdev_queue *txq; 1176 1177 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1178 return true; 1179 1180 tx_buffer = &tx_ring->tx_buffer_info[i]; 1181 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1182 i -= tx_ring->count; 1183 1184 do { 1185 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1186 1187 /* if next_to_watch is not set then there is no work pending */ 1188 if (!eop_desc) 1189 break; 1190 1191 /* prevent any other reads prior to eop_desc */ 1192 smp_rmb(); 1193 1194 /* if DD is not set pending work has not been completed */ 1195 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1196 break; 1197 1198 /* clear next_to_watch to prevent false hangs */ 1199 tx_buffer->next_to_watch = NULL; 1200 1201 /* update the statistics for this packet */ 1202 total_bytes += tx_buffer->bytecount; 1203 total_packets += tx_buffer->gso_segs; 1204 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC) 1205 total_ipsec++; 1206 1207 /* free the skb */ 1208 if (ring_is_xdp(tx_ring)) 1209 xdp_return_frame(tx_buffer->xdpf); 1210 else 1211 napi_consume_skb(tx_buffer->skb, napi_budget); 1212 1213 /* unmap skb header data */ 1214 dma_unmap_single(tx_ring->dev, 1215 dma_unmap_addr(tx_buffer, dma), 1216 dma_unmap_len(tx_buffer, len), 1217 DMA_TO_DEVICE); 1218 1219 /* clear tx_buffer data */ 1220 dma_unmap_len_set(tx_buffer, len, 0); 1221 1222 /* unmap remaining buffers */ 1223 while (tx_desc != eop_desc) { 1224 tx_buffer++; 1225 tx_desc++; 1226 i++; 1227 if (unlikely(!i)) { 1228 i -= tx_ring->count; 1229 tx_buffer = tx_ring->tx_buffer_info; 1230 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1231 } 1232 1233 /* unmap any remaining paged data */ 1234 if (dma_unmap_len(tx_buffer, len)) { 1235 dma_unmap_page(tx_ring->dev, 1236 dma_unmap_addr(tx_buffer, dma), 1237 dma_unmap_len(tx_buffer, len), 1238 DMA_TO_DEVICE); 1239 dma_unmap_len_set(tx_buffer, len, 0); 1240 } 1241 } 1242 1243 /* move us one more past the eop_desc for start of next pkt */ 1244 tx_buffer++; 1245 tx_desc++; 1246 i++; 1247 if (unlikely(!i)) { 1248 i -= tx_ring->count; 1249 tx_buffer = tx_ring->tx_buffer_info; 1250 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1251 } 1252 1253 /* issue prefetch for next Tx descriptor */ 1254 prefetch(tx_desc); 1255 1256 /* update budget accounting */ 1257 budget--; 1258 } while (likely(budget)); 1259 1260 i += tx_ring->count; 1261 tx_ring->next_to_clean = i; 1262 ixgbe_update_tx_ring_stats(tx_ring, q_vector, total_packets, 1263 total_bytes); 1264 adapter->tx_ipsec += total_ipsec; 1265 1266 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1267 /* schedule immediate reset if we believe we hung */ 1268 struct ixgbe_hw *hw = &adapter->hw; 1269 e_err(drv, "Detected Tx Unit Hang %s\n" 1270 " Tx Queue <%d>\n" 1271 " TDH, TDT <%x>, <%x>\n" 1272 " next_to_use <%x>\n" 1273 " next_to_clean <%x>\n" 1274 "tx_buffer_info[next_to_clean]\n" 1275 " time_stamp <%lx>\n" 1276 " jiffies <%lx>\n", 1277 ring_is_xdp(tx_ring) ? "(XDP)" : "", 1278 tx_ring->queue_index, 1279 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1280 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1281 tx_ring->next_to_use, i, 1282 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1283 1284 if (!ring_is_xdp(tx_ring)) 1285 netif_stop_subqueue(tx_ring->netdev, 1286 tx_ring->queue_index); 1287 1288 e_info(probe, 1289 "tx hang %d detected on queue %d, resetting adapter\n", 1290 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1291 1292 /* schedule immediate reset if we believe we hung */ 1293 ixgbe_tx_timeout_reset(adapter); 1294 1295 /* the adapter is about to reset, no point in enabling stuff */ 1296 return true; 1297 } 1298 1299 if (ring_is_xdp(tx_ring)) 1300 return !!budget; 1301 1302 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1303 txq = netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 1304 if (!__netif_txq_completed_wake(txq, total_packets, total_bytes, 1305 ixgbe_desc_unused(tx_ring), 1306 TX_WAKE_THRESHOLD, 1307 !netif_carrier_ok(tx_ring->netdev) || 1308 test_bit(__IXGBE_DOWN, &adapter->state))) 1309 ++tx_ring->tx_stats.restart_queue; 1310 1311 return !!budget; 1312 } 1313 1314 #ifdef CONFIG_IXGBE_DCA 1315 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1316 struct ixgbe_ring *tx_ring, 1317 int cpu) 1318 { 1319 struct ixgbe_hw *hw = &adapter->hw; 1320 u32 txctrl = 0; 1321 u16 reg_offset; 1322 1323 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1324 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1325 1326 switch (hw->mac.type) { 1327 case ixgbe_mac_82598EB: 1328 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1329 break; 1330 case ixgbe_mac_82599EB: 1331 case ixgbe_mac_X540: 1332 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1333 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1334 break; 1335 default: 1336 /* for unknown hardware do not write register */ 1337 return; 1338 } 1339 1340 /* 1341 * We can enable relaxed ordering for reads, but not writes when 1342 * DCA is enabled. This is due to a known issue in some chipsets 1343 * which will cause the DCA tag to be cleared. 1344 */ 1345 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1346 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1347 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1348 1349 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1350 } 1351 1352 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1353 struct ixgbe_ring *rx_ring, 1354 int cpu) 1355 { 1356 struct ixgbe_hw *hw = &adapter->hw; 1357 u32 rxctrl = 0; 1358 u8 reg_idx = rx_ring->reg_idx; 1359 1360 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1361 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1362 1363 switch (hw->mac.type) { 1364 case ixgbe_mac_82599EB: 1365 case ixgbe_mac_X540: 1366 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1367 break; 1368 default: 1369 break; 1370 } 1371 1372 /* 1373 * We can enable relaxed ordering for reads, but not writes when 1374 * DCA is enabled. This is due to a known issue in some chipsets 1375 * which will cause the DCA tag to be cleared. 1376 */ 1377 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1378 IXGBE_DCA_RXCTRL_DATA_DCA_EN | 1379 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1380 1381 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1382 } 1383 1384 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1385 { 1386 struct ixgbe_adapter *adapter = q_vector->adapter; 1387 struct ixgbe_ring *ring; 1388 int cpu = get_cpu(); 1389 1390 if (q_vector->cpu == cpu) 1391 goto out_no_update; 1392 1393 ixgbe_for_each_ring(ring, q_vector->tx) 1394 ixgbe_update_tx_dca(adapter, ring, cpu); 1395 1396 ixgbe_for_each_ring(ring, q_vector->rx) 1397 ixgbe_update_rx_dca(adapter, ring, cpu); 1398 1399 q_vector->cpu = cpu; 1400 out_no_update: 1401 put_cpu(); 1402 } 1403 1404 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1405 { 1406 int i; 1407 1408 /* always use CB2 mode, difference is masked in the CB driver */ 1409 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1410 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1411 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1412 else 1413 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1414 IXGBE_DCA_CTRL_DCA_DISABLE); 1415 1416 for (i = 0; i < adapter->num_q_vectors; i++) { 1417 adapter->q_vector[i]->cpu = -1; 1418 ixgbe_update_dca(adapter->q_vector[i]); 1419 } 1420 } 1421 1422 static int __ixgbe_notify_dca(struct device *dev, void *data) 1423 { 1424 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1425 unsigned long event = *(unsigned long *)data; 1426 1427 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1428 return 0; 1429 1430 switch (event) { 1431 case DCA_PROVIDER_ADD: 1432 /* if we're already enabled, don't do it again */ 1433 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1434 break; 1435 if (dca_add_requester(dev) == 0) { 1436 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1437 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1438 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1439 break; 1440 } 1441 fallthrough; /* DCA is disabled. */ 1442 case DCA_PROVIDER_REMOVE: 1443 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1444 dca_remove_requester(dev); 1445 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1446 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1447 IXGBE_DCA_CTRL_DCA_DISABLE); 1448 } 1449 break; 1450 } 1451 1452 return 0; 1453 } 1454 1455 #endif /* CONFIG_IXGBE_DCA */ 1456 1457 #define IXGBE_RSS_L4_TYPES_MASK \ 1458 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1459 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1460 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1461 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1462 1463 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1464 union ixgbe_adv_rx_desc *rx_desc, 1465 struct sk_buff *skb) 1466 { 1467 u16 rss_type; 1468 1469 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1470 return; 1471 1472 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1473 IXGBE_RXDADV_RSSTYPE_MASK; 1474 1475 if (!rss_type) 1476 return; 1477 1478 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1479 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1480 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1481 } 1482 1483 #ifdef IXGBE_FCOE 1484 /** 1485 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1486 * @ring: structure containing ring specific data 1487 * @rx_desc: advanced rx descriptor 1488 * 1489 * Returns : true if it is FCoE pkt 1490 */ 1491 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1492 union ixgbe_adv_rx_desc *rx_desc) 1493 { 1494 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1495 1496 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1497 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1498 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1499 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1500 } 1501 1502 #endif /* IXGBE_FCOE */ 1503 /** 1504 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1505 * @ring: structure containing ring specific data 1506 * @rx_desc: current Rx descriptor being processed 1507 * @skb: skb currently being received and modified 1508 **/ 1509 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1510 union ixgbe_adv_rx_desc *rx_desc, 1511 struct sk_buff *skb) 1512 { 1513 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1514 bool encap_pkt = false; 1515 1516 skb_checksum_none_assert(skb); 1517 1518 /* Rx csum disabled */ 1519 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1520 return; 1521 1522 /* check for VXLAN and Geneve packets */ 1523 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) { 1524 encap_pkt = true; 1525 skb->encapsulation = 1; 1526 } 1527 1528 /* if IP and error */ 1529 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1530 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1531 ring->rx_stats.csum_err++; 1532 return; 1533 } 1534 1535 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1536 return; 1537 1538 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1539 /* 1540 * 82599 errata, UDP frames with a 0 checksum can be marked as 1541 * checksum errors. 1542 */ 1543 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1544 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1545 return; 1546 1547 ring->rx_stats.csum_err++; 1548 return; 1549 } 1550 1551 /* It must be a TCP or UDP packet with a valid checksum */ 1552 skb->ip_summed = CHECKSUM_UNNECESSARY; 1553 if (encap_pkt) { 1554 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1555 return; 1556 1557 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1558 skb->ip_summed = CHECKSUM_NONE; 1559 return; 1560 } 1561 /* If we checked the outer header let the stack know */ 1562 skb->csum_level = 1; 1563 } 1564 } 1565 1566 static unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring) 1567 { 1568 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0; 1569 } 1570 1571 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1572 struct ixgbe_rx_buffer *bi) 1573 { 1574 struct page *page = bi->page; 1575 dma_addr_t dma; 1576 1577 /* since we are recycling buffers we should seldom need to alloc */ 1578 if (likely(page)) 1579 return true; 1580 1581 /* alloc new page for storage */ 1582 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1583 if (unlikely(!page)) { 1584 rx_ring->rx_stats.alloc_rx_page_failed++; 1585 return false; 1586 } 1587 1588 /* map page for use */ 1589 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1590 ixgbe_rx_pg_size(rx_ring), 1591 DMA_FROM_DEVICE, 1592 IXGBE_RX_DMA_ATTR); 1593 1594 /* 1595 * if mapping failed free memory back to system since 1596 * there isn't much point in holding memory we can't use 1597 */ 1598 if (dma_mapping_error(rx_ring->dev, dma)) { 1599 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1600 1601 rx_ring->rx_stats.alloc_rx_page_failed++; 1602 return false; 1603 } 1604 1605 bi->dma = dma; 1606 bi->page = page; 1607 bi->page_offset = rx_ring->rx_offset; 1608 page_ref_add(page, USHRT_MAX - 1); 1609 bi->pagecnt_bias = USHRT_MAX; 1610 rx_ring->rx_stats.alloc_rx_page++; 1611 1612 return true; 1613 } 1614 1615 /** 1616 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1617 * @rx_ring: ring to place buffers on 1618 * @cleaned_count: number of buffers to replace 1619 **/ 1620 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1621 { 1622 union ixgbe_adv_rx_desc *rx_desc; 1623 struct ixgbe_rx_buffer *bi; 1624 u16 i = rx_ring->next_to_use; 1625 u16 bufsz; 1626 1627 /* nothing to do */ 1628 if (!cleaned_count) 1629 return; 1630 1631 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1632 bi = &rx_ring->rx_buffer_info[i]; 1633 i -= rx_ring->count; 1634 1635 bufsz = ixgbe_rx_bufsz(rx_ring); 1636 1637 do { 1638 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1639 break; 1640 1641 /* sync the buffer for use by the device */ 1642 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1643 bi->page_offset, bufsz, 1644 DMA_FROM_DEVICE); 1645 1646 /* 1647 * Refresh the desc even if buffer_addrs didn't change 1648 * because each write-back erases this info. 1649 */ 1650 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1651 1652 rx_desc++; 1653 bi++; 1654 i++; 1655 if (unlikely(!i)) { 1656 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1657 bi = rx_ring->rx_buffer_info; 1658 i -= rx_ring->count; 1659 } 1660 1661 /* clear the length for the next_to_use descriptor */ 1662 rx_desc->wb.upper.length = 0; 1663 1664 cleaned_count--; 1665 } while (cleaned_count); 1666 1667 i += rx_ring->count; 1668 1669 if (rx_ring->next_to_use != i) { 1670 rx_ring->next_to_use = i; 1671 1672 /* update next to alloc since we have filled the ring */ 1673 rx_ring->next_to_alloc = i; 1674 1675 /* Force memory writes to complete before letting h/w 1676 * know there are new descriptors to fetch. (Only 1677 * applicable for weak-ordered memory model archs, 1678 * such as IA-64). 1679 */ 1680 wmb(); 1681 writel(i, rx_ring->tail); 1682 } 1683 } 1684 1685 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1686 struct sk_buff *skb) 1687 { 1688 u16 hdr_len = skb_headlen(skb); 1689 1690 /* set gso_size to avoid messing up TCP MSS */ 1691 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1692 IXGBE_CB(skb)->append_cnt); 1693 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1694 } 1695 1696 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1697 struct sk_buff *skb) 1698 { 1699 /* if append_cnt is 0 then frame is not RSC */ 1700 if (!IXGBE_CB(skb)->append_cnt) 1701 return; 1702 1703 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1704 rx_ring->rx_stats.rsc_flush++; 1705 1706 ixgbe_set_rsc_gso_size(rx_ring, skb); 1707 1708 /* gso_size is computed using append_cnt so always clear it last */ 1709 IXGBE_CB(skb)->append_cnt = 0; 1710 } 1711 1712 /** 1713 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1714 * @rx_ring: rx descriptor ring packet is being transacted on 1715 * @rx_desc: pointer to the EOP Rx descriptor 1716 * @skb: pointer to current skb being populated 1717 * 1718 * This function checks the ring, descriptor, and packet information in 1719 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1720 * other fields within the skb. 1721 **/ 1722 void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1723 union ixgbe_adv_rx_desc *rx_desc, 1724 struct sk_buff *skb) 1725 { 1726 struct net_device *dev = rx_ring->netdev; 1727 u32 flags = rx_ring->q_vector->adapter->flags; 1728 1729 ixgbe_update_rsc_stats(rx_ring, skb); 1730 1731 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1732 1733 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1734 1735 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) 1736 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 1737 1738 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1739 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1740 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1741 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1742 } 1743 1744 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP)) 1745 ixgbe_ipsec_rx(rx_ring, rx_desc, skb); 1746 1747 /* record Rx queue, or update MACVLAN statistics */ 1748 if (netif_is_ixgbe(dev)) 1749 skb_record_rx_queue(skb, rx_ring->queue_index); 1750 else 1751 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true, 1752 false); 1753 1754 skb->protocol = eth_type_trans(skb, dev); 1755 } 1756 1757 void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1758 struct sk_buff *skb) 1759 { 1760 napi_gro_receive(&q_vector->napi, skb); 1761 } 1762 1763 /** 1764 * ixgbe_is_non_eop - process handling of non-EOP buffers 1765 * @rx_ring: Rx ring being processed 1766 * @rx_desc: Rx descriptor for current buffer 1767 * @skb: Current socket buffer containing buffer in progress 1768 * 1769 * This function updates next to clean. If the buffer is an EOP buffer 1770 * this function exits returning false, otherwise it will place the 1771 * sk_buff in the next buffer to be chained and return true indicating 1772 * that this is in fact a non-EOP buffer. 1773 **/ 1774 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1775 union ixgbe_adv_rx_desc *rx_desc, 1776 struct sk_buff *skb) 1777 { 1778 u32 ntc = rx_ring->next_to_clean + 1; 1779 1780 /* fetch, update, and store next to clean */ 1781 ntc = (ntc < rx_ring->count) ? ntc : 0; 1782 rx_ring->next_to_clean = ntc; 1783 1784 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1785 1786 /* update RSC append count if present */ 1787 if (ring_is_rsc_enabled(rx_ring)) { 1788 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1789 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1790 1791 if (unlikely(rsc_enabled)) { 1792 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1793 1794 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1795 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1796 1797 /* update ntc based on RSC value */ 1798 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1799 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1800 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1801 } 1802 } 1803 1804 /* if we are the last buffer then there is nothing else to do */ 1805 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1806 return false; 1807 1808 /* place skb in next buffer to be received */ 1809 rx_ring->rx_buffer_info[ntc].skb = skb; 1810 rx_ring->rx_stats.non_eop_descs++; 1811 1812 return true; 1813 } 1814 1815 /** 1816 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1817 * @rx_ring: rx descriptor ring packet is being transacted on 1818 * @skb: pointer to current skb being adjusted 1819 * 1820 * This function is an ixgbe specific version of __pskb_pull_tail. The 1821 * main difference between this version and the original function is that 1822 * this function can make several assumptions about the state of things 1823 * that allow for significant optimizations versus the standard function. 1824 * As a result we can do things like drop a frag and maintain an accurate 1825 * truesize for the skb. 1826 */ 1827 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1828 struct sk_buff *skb) 1829 { 1830 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 1831 unsigned char *va; 1832 unsigned int pull_len; 1833 1834 /* 1835 * it is valid to use page_address instead of kmap since we are 1836 * working with pages allocated out of the lomem pool per 1837 * alloc_page(GFP_ATOMIC) 1838 */ 1839 va = skb_frag_address(frag); 1840 1841 /* 1842 * we need the header to contain the greater of either ETH_HLEN or 1843 * 60 bytes if the skb->len is less than 60 for skb_pad. 1844 */ 1845 pull_len = eth_get_headlen(skb->dev, va, IXGBE_RX_HDR_SIZE); 1846 1847 /* align pull length to size of long to optimize memcpy performance */ 1848 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1849 1850 /* update all of the pointers */ 1851 skb_frag_size_sub(frag, pull_len); 1852 skb_frag_off_add(frag, pull_len); 1853 skb->data_len -= pull_len; 1854 skb->tail += pull_len; 1855 } 1856 1857 /** 1858 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1859 * @rx_ring: rx descriptor ring packet is being transacted on 1860 * @skb: pointer to current skb being updated 1861 * 1862 * This function provides a basic DMA sync up for the first fragment of an 1863 * skb. The reason for doing this is that the first fragment cannot be 1864 * unmapped until we have reached the end of packet descriptor for a buffer 1865 * chain. 1866 */ 1867 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1868 struct sk_buff *skb) 1869 { 1870 if (ring_uses_build_skb(rx_ring)) { 1871 unsigned long mask = (unsigned long)ixgbe_rx_pg_size(rx_ring) - 1; 1872 unsigned long offset = (unsigned long)(skb->data) & mask; 1873 1874 dma_sync_single_range_for_cpu(rx_ring->dev, 1875 IXGBE_CB(skb)->dma, 1876 offset, 1877 skb_headlen(skb), 1878 DMA_FROM_DEVICE); 1879 } else { 1880 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 1881 1882 dma_sync_single_range_for_cpu(rx_ring->dev, 1883 IXGBE_CB(skb)->dma, 1884 skb_frag_off(frag), 1885 skb_frag_size(frag), 1886 DMA_FROM_DEVICE); 1887 } 1888 1889 /* If the page was released, just unmap it. */ 1890 if (unlikely(IXGBE_CB(skb)->page_released)) { 1891 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma, 1892 ixgbe_rx_pg_size(rx_ring), 1893 DMA_FROM_DEVICE, 1894 IXGBE_RX_DMA_ATTR); 1895 } 1896 } 1897 1898 /** 1899 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1900 * @rx_ring: rx descriptor ring packet is being transacted on 1901 * @rx_desc: pointer to the EOP Rx descriptor 1902 * @skb: pointer to current skb being fixed 1903 * 1904 * Check if the skb is valid in the XDP case it will be an error pointer. 1905 * Return true in this case to abort processing and advance to next 1906 * descriptor. 1907 * 1908 * Check for corrupted packet headers caused by senders on the local L2 1909 * embedded NIC switch not setting up their Tx Descriptors right. These 1910 * should be very rare. 1911 * 1912 * Also address the case where we are pulling data in on pages only 1913 * and as such no data is present in the skb header. 1914 * 1915 * In addition if skb is not at least 60 bytes we need to pad it so that 1916 * it is large enough to qualify as a valid Ethernet frame. 1917 * 1918 * Returns true if an error was encountered and skb was freed. 1919 **/ 1920 bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1921 union ixgbe_adv_rx_desc *rx_desc, 1922 struct sk_buff *skb) 1923 { 1924 struct net_device *netdev = rx_ring->netdev; 1925 1926 /* Verify netdev is present, and that packet does not have any 1927 * errors that would be unacceptable to the netdev. 1928 */ 1929 if (!netdev || 1930 (unlikely(ixgbe_test_staterr(rx_desc, 1931 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1932 !(netdev->features & NETIF_F_RXALL)))) { 1933 dev_kfree_skb_any(skb); 1934 return true; 1935 } 1936 1937 /* place header in linear portion of buffer */ 1938 if (!skb_headlen(skb)) 1939 ixgbe_pull_tail(rx_ring, skb); 1940 1941 #ifdef IXGBE_FCOE 1942 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1943 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1944 return false; 1945 1946 #endif 1947 /* if eth_skb_pad returns an error the skb was freed */ 1948 if (eth_skb_pad(skb)) 1949 return true; 1950 1951 return false; 1952 } 1953 1954 /** 1955 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1956 * @rx_ring: rx descriptor ring to store buffers on 1957 * @old_buff: donor buffer to have page reused 1958 * 1959 * Synchronizes page for reuse by the adapter 1960 **/ 1961 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1962 struct ixgbe_rx_buffer *old_buff) 1963 { 1964 struct ixgbe_rx_buffer *new_buff; 1965 u16 nta = rx_ring->next_to_alloc; 1966 1967 new_buff = &rx_ring->rx_buffer_info[nta]; 1968 1969 /* update, and store next to alloc */ 1970 nta++; 1971 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1972 1973 /* Transfer page from old buffer to new buffer. 1974 * Move each member individually to avoid possible store 1975 * forwarding stalls and unnecessary copy of skb. 1976 */ 1977 new_buff->dma = old_buff->dma; 1978 new_buff->page = old_buff->page; 1979 new_buff->page_offset = old_buff->page_offset; 1980 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1981 } 1982 1983 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer, 1984 int rx_buffer_pgcnt) 1985 { 1986 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1987 struct page *page = rx_buffer->page; 1988 1989 /* avoid re-using remote and pfmemalloc pages */ 1990 if (!dev_page_is_reusable(page)) 1991 return false; 1992 1993 #if (PAGE_SIZE < 8192) 1994 /* if we are only owner of page we can reuse it */ 1995 if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1)) 1996 return false; 1997 #else 1998 /* The last offset is a bit aggressive in that we assume the 1999 * worst case of FCoE being enabled and using a 3K buffer. 2000 * However this should have minimal impact as the 1K extra is 2001 * still less than one buffer in size. 2002 */ 2003 #define IXGBE_LAST_OFFSET \ 2004 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K) 2005 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET) 2006 return false; 2007 #endif 2008 2009 /* If we have drained the page fragment pool we need to update 2010 * the pagecnt_bias and page count so that we fully restock the 2011 * number of references the driver holds. 2012 */ 2013 if (unlikely(pagecnt_bias == 1)) { 2014 page_ref_add(page, USHRT_MAX - 1); 2015 rx_buffer->pagecnt_bias = USHRT_MAX; 2016 } 2017 2018 return true; 2019 } 2020 2021 /** 2022 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 2023 * @rx_ring: rx descriptor ring to transact packets on 2024 * @rx_buffer: buffer containing page to add 2025 * @skb: sk_buff to place the data into 2026 * @size: size of data in rx_buffer 2027 * 2028 * This function will add the data contained in rx_buffer->page to the skb. 2029 * This is done either through a direct copy if the data in the buffer is 2030 * less than the skb header size, otherwise it will just attach the page as 2031 * a frag to the skb. 2032 * 2033 * The function will then update the page offset if necessary and return 2034 * true if the buffer can be reused by the adapter. 2035 **/ 2036 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 2037 struct ixgbe_rx_buffer *rx_buffer, 2038 struct sk_buff *skb, 2039 unsigned int size) 2040 { 2041 #if (PAGE_SIZE < 8192) 2042 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2043 #else 2044 unsigned int truesize = rx_ring->rx_offset ? 2045 SKB_DATA_ALIGN(rx_ring->rx_offset + size) : 2046 SKB_DATA_ALIGN(size); 2047 #endif 2048 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 2049 rx_buffer->page_offset, size, truesize); 2050 #if (PAGE_SIZE < 8192) 2051 rx_buffer->page_offset ^= truesize; 2052 #else 2053 rx_buffer->page_offset += truesize; 2054 #endif 2055 } 2056 2057 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring, 2058 union ixgbe_adv_rx_desc *rx_desc, 2059 struct sk_buff **skb, 2060 const unsigned int size, 2061 int *rx_buffer_pgcnt) 2062 { 2063 struct ixgbe_rx_buffer *rx_buffer; 2064 2065 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 2066 *rx_buffer_pgcnt = 2067 #if (PAGE_SIZE < 8192) 2068 page_count(rx_buffer->page); 2069 #else 2070 0; 2071 #endif 2072 prefetchw(rx_buffer->page); 2073 *skb = rx_buffer->skb; 2074 2075 /* Delay unmapping of the first packet. It carries the header 2076 * information, HW may still access the header after the writeback. 2077 * Only unmap it when EOP is reached 2078 */ 2079 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) { 2080 if (!*skb) 2081 goto skip_sync; 2082 } else { 2083 if (*skb) 2084 ixgbe_dma_sync_frag(rx_ring, *skb); 2085 } 2086 2087 /* we are reusing so sync this buffer for CPU use */ 2088 dma_sync_single_range_for_cpu(rx_ring->dev, 2089 rx_buffer->dma, 2090 rx_buffer->page_offset, 2091 size, 2092 DMA_FROM_DEVICE); 2093 skip_sync: 2094 rx_buffer->pagecnt_bias--; 2095 2096 return rx_buffer; 2097 } 2098 2099 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring, 2100 struct ixgbe_rx_buffer *rx_buffer, 2101 struct sk_buff *skb, 2102 int rx_buffer_pgcnt) 2103 { 2104 if (ixgbe_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) { 2105 /* hand second half of page back to the ring */ 2106 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2107 } else { 2108 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) { 2109 /* the page has been released from the ring */ 2110 IXGBE_CB(skb)->page_released = true; 2111 } else { 2112 /* we are not reusing the buffer so unmap it */ 2113 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2114 ixgbe_rx_pg_size(rx_ring), 2115 DMA_FROM_DEVICE, 2116 IXGBE_RX_DMA_ATTR); 2117 } 2118 __page_frag_cache_drain(rx_buffer->page, 2119 rx_buffer->pagecnt_bias); 2120 } 2121 2122 /* clear contents of rx_buffer */ 2123 rx_buffer->page = NULL; 2124 rx_buffer->skb = NULL; 2125 } 2126 2127 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring, 2128 struct ixgbe_rx_buffer *rx_buffer, 2129 struct xdp_buff *xdp, 2130 union ixgbe_adv_rx_desc *rx_desc) 2131 { 2132 unsigned int size = xdp->data_end - xdp->data; 2133 #if (PAGE_SIZE < 8192) 2134 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2135 #else 2136 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 2137 xdp->data_hard_start); 2138 #endif 2139 struct sk_buff *skb; 2140 2141 /* prefetch first cache line of first page */ 2142 net_prefetch(xdp->data); 2143 2144 /* Note, we get here by enabling legacy-rx via: 2145 * 2146 * ethtool --set-priv-flags <dev> legacy-rx on 2147 * 2148 * In this mode, we currently get 0 extra XDP headroom as 2149 * opposed to having legacy-rx off, where we process XDP 2150 * packets going to stack via ixgbe_build_skb(). The latter 2151 * provides us currently with 192 bytes of headroom. 2152 * 2153 * For ixgbe_construct_skb() mode it means that the 2154 * xdp->data_meta will always point to xdp->data, since 2155 * the helper cannot expand the head. Should this ever 2156 * change in future for legacy-rx mode on, then lets also 2157 * add xdp->data_meta handling here. 2158 */ 2159 2160 /* allocate a skb to store the frags */ 2161 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE); 2162 if (unlikely(!skb)) 2163 return NULL; 2164 2165 if (size > IXGBE_RX_HDR_SIZE) { 2166 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2167 IXGBE_CB(skb)->dma = rx_buffer->dma; 2168 2169 skb_add_rx_frag(skb, 0, rx_buffer->page, 2170 xdp->data - page_address(rx_buffer->page), 2171 size, truesize); 2172 #if (PAGE_SIZE < 8192) 2173 rx_buffer->page_offset ^= truesize; 2174 #else 2175 rx_buffer->page_offset += truesize; 2176 #endif 2177 } else { 2178 memcpy(__skb_put(skb, size), 2179 xdp->data, ALIGN(size, sizeof(long))); 2180 rx_buffer->pagecnt_bias++; 2181 } 2182 2183 return skb; 2184 } 2185 2186 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring, 2187 struct ixgbe_rx_buffer *rx_buffer, 2188 struct xdp_buff *xdp, 2189 union ixgbe_adv_rx_desc *rx_desc) 2190 { 2191 unsigned int metasize = xdp->data - xdp->data_meta; 2192 #if (PAGE_SIZE < 8192) 2193 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2194 #else 2195 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 2196 SKB_DATA_ALIGN(xdp->data_end - 2197 xdp->data_hard_start); 2198 #endif 2199 struct sk_buff *skb; 2200 2201 /* Prefetch first cache line of first page. If xdp->data_meta 2202 * is unused, this points extactly as xdp->data, otherwise we 2203 * likely have a consumer accessing first few bytes of meta 2204 * data, and then actual data. 2205 */ 2206 net_prefetch(xdp->data_meta); 2207 2208 /* build an skb to around the page buffer */ 2209 skb = napi_build_skb(xdp->data_hard_start, truesize); 2210 if (unlikely(!skb)) 2211 return NULL; 2212 2213 /* update pointers within the skb to store the data */ 2214 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2215 __skb_put(skb, xdp->data_end - xdp->data); 2216 if (metasize) 2217 skb_metadata_set(skb, metasize); 2218 2219 /* record DMA address if this is the start of a chain of buffers */ 2220 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2221 IXGBE_CB(skb)->dma = rx_buffer->dma; 2222 2223 /* update buffer offset */ 2224 #if (PAGE_SIZE < 8192) 2225 rx_buffer->page_offset ^= truesize; 2226 #else 2227 rx_buffer->page_offset += truesize; 2228 #endif 2229 2230 return skb; 2231 } 2232 2233 static int ixgbe_run_xdp(struct ixgbe_adapter *adapter, 2234 struct ixgbe_ring *rx_ring, 2235 struct xdp_buff *xdp) 2236 { 2237 int err, result = IXGBE_XDP_PASS; 2238 struct bpf_prog *xdp_prog; 2239 struct ixgbe_ring *ring; 2240 struct xdp_frame *xdpf; 2241 u32 act; 2242 2243 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2244 2245 if (!xdp_prog) 2246 goto xdp_out; 2247 2248 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 2249 2250 act = bpf_prog_run_xdp(xdp_prog, xdp); 2251 switch (act) { 2252 case XDP_PASS: 2253 break; 2254 case XDP_TX: 2255 xdpf = xdp_convert_buff_to_frame(xdp); 2256 if (unlikely(!xdpf)) 2257 goto out_failure; 2258 ring = ixgbe_determine_xdp_ring(adapter); 2259 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 2260 spin_lock(&ring->tx_lock); 2261 result = ixgbe_xmit_xdp_ring(ring, xdpf); 2262 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 2263 spin_unlock(&ring->tx_lock); 2264 if (result == IXGBE_XDP_CONSUMED) 2265 goto out_failure; 2266 break; 2267 case XDP_REDIRECT: 2268 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 2269 if (err) 2270 goto out_failure; 2271 result = IXGBE_XDP_REDIR; 2272 break; 2273 default: 2274 bpf_warn_invalid_xdp_action(rx_ring->netdev, xdp_prog, act); 2275 fallthrough; 2276 case XDP_ABORTED: 2277 out_failure: 2278 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2279 fallthrough; /* handle aborts by dropping packet */ 2280 case XDP_DROP: 2281 result = IXGBE_XDP_CONSUMED; 2282 break; 2283 } 2284 xdp_out: 2285 return result; 2286 } 2287 2288 static unsigned int ixgbe_rx_frame_truesize(struct ixgbe_ring *rx_ring, 2289 unsigned int size) 2290 { 2291 unsigned int truesize; 2292 2293 #if (PAGE_SIZE < 8192) 2294 truesize = ixgbe_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 2295 #else 2296 truesize = rx_ring->rx_offset ? 2297 SKB_DATA_ALIGN(rx_ring->rx_offset + size) + 2298 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 2299 SKB_DATA_ALIGN(size); 2300 #endif 2301 return truesize; 2302 } 2303 2304 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring, 2305 struct ixgbe_rx_buffer *rx_buffer, 2306 unsigned int size) 2307 { 2308 unsigned int truesize = ixgbe_rx_frame_truesize(rx_ring, size); 2309 #if (PAGE_SIZE < 8192) 2310 rx_buffer->page_offset ^= truesize; 2311 #else 2312 rx_buffer->page_offset += truesize; 2313 #endif 2314 } 2315 2316 /** 2317 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2318 * @q_vector: structure containing interrupt and ring information 2319 * @rx_ring: rx descriptor ring to transact packets on 2320 * @budget: Total limit on number of packets to process 2321 * 2322 * This function provides a "bounce buffer" approach to Rx interrupt 2323 * processing. The advantage to this is that on systems that have 2324 * expensive overhead for IOMMU access this provides a means of avoiding 2325 * it by maintaining the mapping of the page to the syste. 2326 * 2327 * Returns amount of work completed 2328 **/ 2329 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2330 struct ixgbe_ring *rx_ring, 2331 const int budget) 2332 { 2333 unsigned int total_rx_bytes = 0, total_rx_packets = 0, frame_sz = 0; 2334 struct ixgbe_adapter *adapter = q_vector->adapter; 2335 #ifdef IXGBE_FCOE 2336 int ddp_bytes; 2337 unsigned int mss = 0; 2338 #endif /* IXGBE_FCOE */ 2339 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2340 unsigned int offset = rx_ring->rx_offset; 2341 unsigned int xdp_xmit = 0; 2342 struct xdp_buff xdp; 2343 int xdp_res = 0; 2344 2345 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 2346 #if (PAGE_SIZE < 8192) 2347 frame_sz = ixgbe_rx_frame_truesize(rx_ring, 0); 2348 #endif 2349 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 2350 2351 while (likely(total_rx_packets < budget)) { 2352 union ixgbe_adv_rx_desc *rx_desc; 2353 struct ixgbe_rx_buffer *rx_buffer; 2354 struct sk_buff *skb; 2355 int rx_buffer_pgcnt; 2356 unsigned int size; 2357 2358 /* return some buffers to hardware, one at a time is too slow */ 2359 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2360 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2361 cleaned_count = 0; 2362 } 2363 2364 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2365 size = le16_to_cpu(rx_desc->wb.upper.length); 2366 if (!size) 2367 break; 2368 2369 /* This memory barrier is needed to keep us from reading 2370 * any other fields out of the rx_desc until we know the 2371 * descriptor has been written back 2372 */ 2373 dma_rmb(); 2374 2375 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size, &rx_buffer_pgcnt); 2376 2377 /* retrieve a buffer from the ring */ 2378 if (!skb) { 2379 unsigned char *hard_start; 2380 2381 hard_start = page_address(rx_buffer->page) + 2382 rx_buffer->page_offset - offset; 2383 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 2384 xdp_buff_clear_frags_flag(&xdp); 2385 #if (PAGE_SIZE > 4096) 2386 /* At larger PAGE_SIZE, frame_sz depend on len size */ 2387 xdp.frame_sz = ixgbe_rx_frame_truesize(rx_ring, size); 2388 #endif 2389 xdp_res = ixgbe_run_xdp(adapter, rx_ring, &xdp); 2390 } 2391 2392 if (xdp_res) { 2393 if (xdp_res & (IXGBE_XDP_TX | IXGBE_XDP_REDIR)) { 2394 xdp_xmit |= xdp_res; 2395 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size); 2396 } else { 2397 rx_buffer->pagecnt_bias++; 2398 } 2399 total_rx_packets++; 2400 total_rx_bytes += size; 2401 } else if (skb) { 2402 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size); 2403 } else if (ring_uses_build_skb(rx_ring)) { 2404 skb = ixgbe_build_skb(rx_ring, rx_buffer, 2405 &xdp, rx_desc); 2406 } else { 2407 skb = ixgbe_construct_skb(rx_ring, rx_buffer, 2408 &xdp, rx_desc); 2409 } 2410 2411 /* exit if we failed to retrieve a buffer */ 2412 if (!xdp_res && !skb) { 2413 rx_ring->rx_stats.alloc_rx_buff_failed++; 2414 rx_buffer->pagecnt_bias++; 2415 break; 2416 } 2417 2418 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt); 2419 cleaned_count++; 2420 2421 /* place incomplete frames back on ring for completion */ 2422 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2423 continue; 2424 2425 /* verify the packet layout is correct */ 2426 if (xdp_res || ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2427 continue; 2428 2429 /* probably a little skewed due to removing CRC */ 2430 total_rx_bytes += skb->len; 2431 2432 /* populate checksum, timestamp, VLAN, and protocol */ 2433 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2434 2435 #ifdef IXGBE_FCOE 2436 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2437 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2438 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2439 /* include DDPed FCoE data */ 2440 if (ddp_bytes > 0) { 2441 if (!mss) { 2442 mss = rx_ring->netdev->mtu - 2443 sizeof(struct fcoe_hdr) - 2444 sizeof(struct fc_frame_header) - 2445 sizeof(struct fcoe_crc_eof); 2446 if (mss > 512) 2447 mss &= ~511; 2448 } 2449 total_rx_bytes += ddp_bytes; 2450 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2451 mss); 2452 } 2453 if (!ddp_bytes) { 2454 dev_kfree_skb_any(skb); 2455 continue; 2456 } 2457 } 2458 2459 #endif /* IXGBE_FCOE */ 2460 ixgbe_rx_skb(q_vector, skb); 2461 2462 /* update budget accounting */ 2463 total_rx_packets++; 2464 } 2465 2466 if (xdp_xmit & IXGBE_XDP_REDIR) 2467 xdp_do_flush(); 2468 2469 if (xdp_xmit & IXGBE_XDP_TX) { 2470 struct ixgbe_ring *ring = ixgbe_determine_xdp_ring(adapter); 2471 2472 ixgbe_xdp_ring_update_tail_locked(ring); 2473 } 2474 2475 ixgbe_update_rx_ring_stats(rx_ring, q_vector, total_rx_packets, 2476 total_rx_bytes); 2477 2478 return total_rx_packets; 2479 } 2480 2481 /** 2482 * ixgbe_configure_msix - Configure MSI-X hardware 2483 * @adapter: board private structure 2484 * 2485 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2486 * interrupts. 2487 **/ 2488 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2489 { 2490 struct ixgbe_q_vector *q_vector; 2491 int v_idx; 2492 u32 mask; 2493 2494 /* Populate MSIX to EITR Select */ 2495 if (adapter->num_vfs > 32) { 2496 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; 2497 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2498 } 2499 2500 /* 2501 * Populate the IVAR table and set the ITR values to the 2502 * corresponding register. 2503 */ 2504 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2505 struct ixgbe_ring *ring; 2506 q_vector = adapter->q_vector[v_idx]; 2507 2508 ixgbe_for_each_ring(ring, q_vector->rx) 2509 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2510 2511 ixgbe_for_each_ring(ring, q_vector->tx) 2512 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2513 2514 ixgbe_write_eitr(q_vector); 2515 } 2516 2517 switch (adapter->hw.mac.type) { 2518 case ixgbe_mac_82598EB: 2519 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2520 v_idx); 2521 break; 2522 case ixgbe_mac_82599EB: 2523 case ixgbe_mac_X540: 2524 case ixgbe_mac_X550: 2525 case ixgbe_mac_X550EM_x: 2526 case ixgbe_mac_x550em_a: 2527 case ixgbe_mac_e610: 2528 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2529 break; 2530 default: 2531 break; 2532 } 2533 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2534 2535 /* set up to autoclear timer, and the vectors */ 2536 mask = IXGBE_EIMS_ENABLE_MASK; 2537 mask &= ~(IXGBE_EIMS_OTHER | 2538 IXGBE_EIMS_MAILBOX | 2539 IXGBE_EIMS_LSC); 2540 2541 if (adapter->hw.mac.type == ixgbe_mac_e610) 2542 mask &= ~IXGBE_EIMS_FW_EVENT; 2543 2544 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2545 } 2546 2547 /** 2548 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2549 * @q_vector: structure containing interrupt and ring information 2550 * @ring_container: structure containing ring performance data 2551 * 2552 * Stores a new ITR value based on packets and byte 2553 * counts during the last interrupt. The advantage of per interrupt 2554 * computation is faster updates and more accurate ITR for the current 2555 * traffic pattern. Constants in this function were computed 2556 * based on theoretical maximum wire speed and thresholds were set based 2557 * on testing data as well as attempting to minimize response time 2558 * while increasing bulk throughput. 2559 **/ 2560 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2561 struct ixgbe_ring_container *ring_container) 2562 { 2563 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS | 2564 IXGBE_ITR_ADAPTIVE_LATENCY; 2565 unsigned int avg_wire_size, packets, bytes; 2566 unsigned long next_update = jiffies; 2567 2568 /* If we don't have any rings just leave ourselves set for maximum 2569 * possible latency so we take ourselves out of the equation. 2570 */ 2571 if (!ring_container->ring) 2572 return; 2573 2574 /* If we didn't update within up to 1 - 2 jiffies we can assume 2575 * that either packets are coming in so slow there hasn't been 2576 * any work, or that there is so much work that NAPI is dealing 2577 * with interrupt moderation and we don't need to do anything. 2578 */ 2579 if (time_after(next_update, ring_container->next_update)) 2580 goto clear_counts; 2581 2582 packets = ring_container->total_packets; 2583 2584 /* We have no packets to actually measure against. This means 2585 * either one of the other queues on this vector is active or 2586 * we are a Tx queue doing TSO with too high of an interrupt rate. 2587 * 2588 * When this occurs just tick up our delay by the minimum value 2589 * and hope that this extra delay will prevent us from being called 2590 * without any work on our queue. 2591 */ 2592 if (!packets) { 2593 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2594 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2595 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2596 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY; 2597 goto clear_counts; 2598 } 2599 2600 bytes = ring_container->total_bytes; 2601 2602 /* If packets are less than 4 or bytes are less than 9000 assume 2603 * insufficient data to use bulk rate limiting approach. We are 2604 * likely latency driven. 2605 */ 2606 if (packets < 4 && bytes < 9000) { 2607 itr = IXGBE_ITR_ADAPTIVE_LATENCY; 2608 goto adjust_by_size; 2609 } 2610 2611 /* Between 4 and 48 we can assume that our current interrupt delay 2612 * is only slightly too low. As such we should increase it by a small 2613 * fixed amount. 2614 */ 2615 if (packets < 48) { 2616 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2617 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2618 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2619 goto clear_counts; 2620 } 2621 2622 /* Between 48 and 96 is our "goldilocks" zone where we are working 2623 * out "just right". Just report that our current ITR is good for us. 2624 */ 2625 if (packets < 96) { 2626 itr = q_vector->itr >> 2; 2627 goto clear_counts; 2628 } 2629 2630 /* If packet count is 96 or greater we are likely looking at a slight 2631 * overrun of the delay we want. Try halving our delay to see if that 2632 * will cut the number of packets in half per interrupt. 2633 */ 2634 if (packets < 256) { 2635 itr = q_vector->itr >> 3; 2636 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS) 2637 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS; 2638 goto clear_counts; 2639 } 2640 2641 /* The paths below assume we are dealing with a bulk ITR since number 2642 * of packets is 256 or greater. We are just going to have to compute 2643 * a value and try to bring the count under control, though for smaller 2644 * packet sizes there isn't much we can do as NAPI polling will likely 2645 * be kicking in sooner rather than later. 2646 */ 2647 itr = IXGBE_ITR_ADAPTIVE_BULK; 2648 2649 adjust_by_size: 2650 /* If packet counts are 256 or greater we can assume we have a gross 2651 * overestimation of what the rate should be. Instead of trying to fine 2652 * tune it just use the formula below to try and dial in an exact value 2653 * give the current packet size of the frame. 2654 */ 2655 avg_wire_size = bytes / packets; 2656 2657 /* The following is a crude approximation of: 2658 * wmem_default / (size + overhead) = desired_pkts_per_int 2659 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 2660 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 2661 * 2662 * Assuming wmem_default is 212992 and overhead is 640 bytes per 2663 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 2664 * formula down to 2665 * 2666 * (170 * (size + 24)) / (size + 640) = ITR 2667 * 2668 * We first do some math on the packet size and then finally bitshift 2669 * by 8 after rounding up. We also have to account for PCIe link speed 2670 * difference as ITR scales based on this. 2671 */ 2672 if (avg_wire_size <= 60) { 2673 /* Start at 50k ints/sec */ 2674 avg_wire_size = 5120; 2675 } else if (avg_wire_size <= 316) { 2676 /* 50K ints/sec to 16K ints/sec */ 2677 avg_wire_size *= 40; 2678 avg_wire_size += 2720; 2679 } else if (avg_wire_size <= 1084) { 2680 /* 16K ints/sec to 9.2K ints/sec */ 2681 avg_wire_size *= 15; 2682 avg_wire_size += 11452; 2683 } else if (avg_wire_size < 1968) { 2684 /* 9.2K ints/sec to 8K ints/sec */ 2685 avg_wire_size *= 5; 2686 avg_wire_size += 22420; 2687 } else { 2688 /* plateau at a limit of 8K ints/sec */ 2689 avg_wire_size = 32256; 2690 } 2691 2692 /* If we are in low latency mode half our delay which doubles the rate 2693 * to somewhere between 100K to 16K ints/sec 2694 */ 2695 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY) 2696 avg_wire_size >>= 1; 2697 2698 /* Resultant value is 256 times larger than it needs to be. This 2699 * gives us room to adjust the value as needed to either increase 2700 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc. 2701 * 2702 * Use addition as we have already recorded the new latency flag 2703 * for the ITR value. 2704 */ 2705 switch (q_vector->adapter->link_speed) { 2706 case IXGBE_LINK_SPEED_10GB_FULL: 2707 case IXGBE_LINK_SPEED_100_FULL: 2708 default: 2709 itr += DIV_ROUND_UP(avg_wire_size, 2710 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) * 2711 IXGBE_ITR_ADAPTIVE_MIN_INC; 2712 break; 2713 case IXGBE_LINK_SPEED_2_5GB_FULL: 2714 case IXGBE_LINK_SPEED_1GB_FULL: 2715 case IXGBE_LINK_SPEED_10_FULL: 2716 if (avg_wire_size > 8064) 2717 avg_wire_size = 8064; 2718 itr += DIV_ROUND_UP(avg_wire_size, 2719 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) * 2720 IXGBE_ITR_ADAPTIVE_MIN_INC; 2721 break; 2722 } 2723 2724 clear_counts: 2725 /* write back value */ 2726 ring_container->itr = itr; 2727 2728 /* next update should occur within next jiffy */ 2729 ring_container->next_update = next_update + 1; 2730 2731 ring_container->total_bytes = 0; 2732 ring_container->total_packets = 0; 2733 } 2734 2735 /** 2736 * ixgbe_write_eitr - write EITR register in hardware specific way 2737 * @q_vector: structure containing interrupt and ring information 2738 * 2739 * This function is made to be called by ethtool and by the driver 2740 * when it needs to update EITR registers at runtime. Hardware 2741 * specific quirks/differences are taken care of here. 2742 */ 2743 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2744 { 2745 struct ixgbe_adapter *adapter = q_vector->adapter; 2746 struct ixgbe_hw *hw = &adapter->hw; 2747 int v_idx = q_vector->v_idx; 2748 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2749 2750 switch (adapter->hw.mac.type) { 2751 case ixgbe_mac_82598EB: 2752 /* must write high and low 16 bits to reset counter */ 2753 itr_reg |= (itr_reg << 16); 2754 break; 2755 case ixgbe_mac_82599EB: 2756 case ixgbe_mac_X540: 2757 case ixgbe_mac_X550: 2758 case ixgbe_mac_X550EM_x: 2759 case ixgbe_mac_x550em_a: 2760 case ixgbe_mac_e610: 2761 /* 2762 * set the WDIS bit to not clear the timer bits and cause an 2763 * immediate assertion of the interrupt 2764 */ 2765 itr_reg |= IXGBE_EITR_CNT_WDIS; 2766 break; 2767 default: 2768 break; 2769 } 2770 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2771 } 2772 2773 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2774 { 2775 u32 new_itr; 2776 2777 ixgbe_update_itr(q_vector, &q_vector->tx); 2778 ixgbe_update_itr(q_vector, &q_vector->rx); 2779 2780 /* use the smallest value of new ITR delay calculations */ 2781 new_itr = min(q_vector->rx.itr, q_vector->tx.itr); 2782 2783 /* Clear latency flag if set, shift into correct position */ 2784 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY; 2785 new_itr <<= 2; 2786 2787 if (new_itr != q_vector->itr) { 2788 /* save the algorithm value here */ 2789 q_vector->itr = new_itr; 2790 2791 ixgbe_write_eitr(q_vector); 2792 } 2793 } 2794 2795 /** 2796 * ixgbe_check_overtemp_subtask - check for over temperature 2797 * @adapter: pointer to adapter 2798 **/ 2799 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2800 { 2801 struct ixgbe_hw *hw = &adapter->hw; 2802 u32 eicr = adapter->interrupt_event; 2803 2804 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2805 return; 2806 2807 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2808 return; 2809 2810 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2811 2812 switch (hw->device_id) { 2813 case IXGBE_DEV_ID_82599_T3_LOM: 2814 /* 2815 * Since the warning interrupt is for both ports 2816 * we don't have to check if: 2817 * - This interrupt wasn't for our port. 2818 * - We may have missed the interrupt so always have to 2819 * check if we got a LSC 2820 */ 2821 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2822 !(eicr & IXGBE_EICR_LSC)) 2823 return; 2824 2825 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2826 u32 speed; 2827 bool link_up = false; 2828 2829 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2830 2831 if (link_up) 2832 return; 2833 } 2834 2835 /* Check if this is not due to overtemp */ 2836 if (!hw->phy.ops.check_overtemp(hw)) 2837 return; 2838 2839 break; 2840 case IXGBE_DEV_ID_X550EM_A_1G_T: 2841 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2842 if (!hw->phy.ops.check_overtemp(hw)) 2843 return; 2844 break; 2845 default: 2846 if (adapter->hw.mac.type >= ixgbe_mac_X540) 2847 return; 2848 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 2849 return; 2850 break; 2851 } 2852 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2853 2854 adapter->interrupt_event = 0; 2855 } 2856 2857 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2858 { 2859 struct ixgbe_hw *hw = &adapter->hw; 2860 2861 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2862 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2863 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2864 /* write to clear the interrupt */ 2865 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2866 } 2867 } 2868 2869 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2870 { 2871 struct ixgbe_hw *hw = &adapter->hw; 2872 2873 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2874 return; 2875 2876 switch (adapter->hw.mac.type) { 2877 case ixgbe_mac_82599EB: 2878 /* 2879 * Need to check link state so complete overtemp check 2880 * on service task 2881 */ 2882 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 2883 (eicr & IXGBE_EICR_LSC)) && 2884 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2885 adapter->interrupt_event = eicr; 2886 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2887 ixgbe_service_event_schedule(adapter); 2888 return; 2889 } 2890 return; 2891 case ixgbe_mac_x550em_a: 2892 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) { 2893 adapter->interrupt_event = eicr; 2894 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2895 ixgbe_service_event_schedule(adapter); 2896 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 2897 IXGBE_EICR_GPI_SDP0_X550EM_a); 2898 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR, 2899 IXGBE_EICR_GPI_SDP0_X550EM_a); 2900 } 2901 return; 2902 case ixgbe_mac_X550: 2903 case ixgbe_mac_X540: 2904 if (!(eicr & IXGBE_EICR_TS)) 2905 return; 2906 break; 2907 default: 2908 return; 2909 } 2910 2911 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2912 } 2913 2914 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 2915 { 2916 switch (hw->mac.type) { 2917 case ixgbe_mac_82598EB: 2918 if (hw->phy.type == ixgbe_phy_nl) 2919 return true; 2920 return false; 2921 case ixgbe_mac_82599EB: 2922 case ixgbe_mac_X550EM_x: 2923 case ixgbe_mac_x550em_a: 2924 switch (hw->mac.ops.get_media_type(hw)) { 2925 case ixgbe_media_type_fiber: 2926 case ixgbe_media_type_fiber_qsfp: 2927 return true; 2928 default: 2929 return false; 2930 } 2931 default: 2932 return false; 2933 } 2934 } 2935 2936 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2937 { 2938 struct ixgbe_hw *hw = &adapter->hw; 2939 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); 2940 2941 if (!ixgbe_is_sfp(hw)) 2942 return; 2943 2944 /* Later MAC's use different SDP */ 2945 if (hw->mac.type >= ixgbe_mac_X540) 2946 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2947 2948 if (eicr & eicr_mask) { 2949 /* Clear the interrupt */ 2950 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2951 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2952 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2953 adapter->sfp_poll_time = 0; 2954 ixgbe_service_event_schedule(adapter); 2955 } 2956 } 2957 2958 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 2959 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2960 /* Clear the interrupt */ 2961 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2962 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2963 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2964 ixgbe_service_event_schedule(adapter); 2965 } 2966 } 2967 } 2968 2969 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2970 { 2971 struct ixgbe_hw *hw = &adapter->hw; 2972 2973 adapter->lsc_int++; 2974 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2975 adapter->link_check_timeout = jiffies; 2976 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2977 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2978 IXGBE_WRITE_FLUSH(hw); 2979 ixgbe_service_event_schedule(adapter); 2980 } 2981 } 2982 2983 /** 2984 * ixgbe_check_phy_fw_load - check if PHY FW load failed 2985 * @adapter: pointer to adapter structure 2986 * @link_cfg_err: bitmap from the link info structure 2987 * 2988 * Check if external PHY FW load failed and print an error message if it did. 2989 */ 2990 static void ixgbe_check_phy_fw_load(struct ixgbe_adapter *adapter, 2991 u8 link_cfg_err) 2992 { 2993 if (!(link_cfg_err & IXGBE_ACI_LINK_EXTERNAL_PHY_LOAD_FAILURE)) { 2994 adapter->flags2 &= ~IXGBE_FLAG2_PHY_FW_LOAD_FAILED; 2995 return; 2996 } 2997 2998 if (adapter->flags2 & IXGBE_FLAG2_PHY_FW_LOAD_FAILED) 2999 return; 3000 3001 if (link_cfg_err & IXGBE_ACI_LINK_EXTERNAL_PHY_LOAD_FAILURE) { 3002 netdev_err(adapter->netdev, "Device failed to load the FW for the external PHY. Please download and install the latest NVM for your device and try again\n"); 3003 adapter->flags2 |= IXGBE_FLAG2_PHY_FW_LOAD_FAILED; 3004 } 3005 } 3006 3007 /** 3008 * ixgbe_check_module_power - check module power level 3009 * @adapter: pointer to adapter structure 3010 * @link_cfg_err: bitmap from the link info structure 3011 * 3012 * Check module power level returned by a previous call to aci_get_link_info 3013 * and print error messages if module power level is not supported. 3014 */ 3015 static void ixgbe_check_module_power(struct ixgbe_adapter *adapter, 3016 u8 link_cfg_err) 3017 { 3018 /* If module power level is supported, clear the flag. */ 3019 if (!(link_cfg_err & (IXGBE_ACI_LINK_INVAL_MAX_POWER_LIMIT | 3020 IXGBE_ACI_LINK_MODULE_POWER_UNSUPPORTED))) { 3021 adapter->flags2 &= ~IXGBE_FLAG2_MOD_POWER_UNSUPPORTED; 3022 return; 3023 } 3024 3025 /* If IXGBE_FLAG2_MOD_POWER_UNSUPPORTED was previously set and the 3026 * above block didn't clear this bit, there's nothing to do. 3027 */ 3028 if (adapter->flags2 & IXGBE_FLAG2_MOD_POWER_UNSUPPORTED) 3029 return; 3030 3031 if (link_cfg_err & IXGBE_ACI_LINK_INVAL_MAX_POWER_LIMIT) { 3032 netdev_err(adapter->netdev, "The installed module is incompatible with the device's NVM image. Cannot start link.\n"); 3033 adapter->flags2 |= IXGBE_FLAG2_MOD_POWER_UNSUPPORTED; 3034 } else if (link_cfg_err & IXGBE_ACI_LINK_MODULE_POWER_UNSUPPORTED) { 3035 netdev_err(adapter->netdev, "The module's power requirements exceed the device's power supply. Cannot start link.\n"); 3036 adapter->flags2 |= IXGBE_FLAG2_MOD_POWER_UNSUPPORTED; 3037 } 3038 } 3039 3040 /** 3041 * ixgbe_check_link_cfg_err - check if link configuration failed 3042 * @adapter: pointer to adapter structure 3043 * @link_cfg_err: bitmap from the link info structure 3044 * 3045 * Print if any link configuration failure happens due to the value in the 3046 * link_cfg_err parameter in the link info structure. 3047 */ 3048 static void ixgbe_check_link_cfg_err(struct ixgbe_adapter *adapter, 3049 u8 link_cfg_err) 3050 { 3051 ixgbe_check_module_power(adapter, link_cfg_err); 3052 ixgbe_check_phy_fw_load(adapter, link_cfg_err); 3053 } 3054 3055 /** 3056 * ixgbe_process_link_status_event - process the link event 3057 * @adapter: pointer to adapter structure 3058 * @link_up: true if the physical link is up and false if it is down 3059 * @link_speed: current link speed received from the link event 3060 * 3061 * Return: 0 on success or negative value on failure. 3062 */ 3063 static int 3064 ixgbe_process_link_status_event(struct ixgbe_adapter *adapter, bool link_up, 3065 u16 link_speed) 3066 { 3067 struct ixgbe_hw *hw = &adapter->hw; 3068 int status; 3069 3070 /* Update the link info structures and re-enable link events, 3071 * don't bail on failure due to other book keeping needed. 3072 */ 3073 status = ixgbe_update_link_info(hw); 3074 if (status) 3075 e_dev_err("Failed to update link status, err %d aq_err %d\n", 3076 status, hw->aci.last_status); 3077 3078 ixgbe_check_link_cfg_err(adapter, hw->link.link_info.link_cfg_err); 3079 3080 /* Check if the link state is up after updating link info, and treat 3081 * this event as an UP event since the link is actually UP now. 3082 */ 3083 if (hw->link.link_info.link_info & IXGBE_ACI_LINK_UP) 3084 link_up = true; 3085 3086 /* Turn off PHY if media was removed. */ 3087 if (!(adapter->flags2 & IXGBE_FLAG2_NO_MEDIA) && 3088 !(hw->link.link_info.link_info & IXGBE_ACI_MEDIA_AVAILABLE)) 3089 adapter->flags2 |= IXGBE_FLAG2_NO_MEDIA; 3090 3091 if (link_up == adapter->link_up && 3092 link_up == netif_carrier_ok(adapter->netdev) && 3093 link_speed == adapter->link_speed) 3094 return 0; 3095 3096 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 3097 adapter->link_check_timeout = jiffies; 3098 ixgbe_watchdog_update_link(adapter); 3099 3100 if (link_up) 3101 ixgbe_watchdog_link_is_up(adapter); 3102 else 3103 ixgbe_watchdog_link_is_down(adapter); 3104 3105 return 0; 3106 } 3107 3108 /** 3109 * ixgbe_handle_link_status_event - handle link status event via ACI 3110 * @adapter: pointer to adapter structure 3111 * @e: event structure containing link status info 3112 */ 3113 static void 3114 ixgbe_handle_link_status_event(struct ixgbe_adapter *adapter, 3115 struct ixgbe_aci_event *e) 3116 { 3117 struct ixgbe_aci_cmd_get_link_status_data *link_data; 3118 u16 link_speed; 3119 bool link_up; 3120 3121 link_data = (struct ixgbe_aci_cmd_get_link_status_data *)e->msg_buf; 3122 3123 link_up = !!(link_data->link_info & IXGBE_ACI_LINK_UP); 3124 link_speed = le16_to_cpu(link_data->link_speed); 3125 3126 if (ixgbe_process_link_status_event(adapter, link_up, link_speed)) 3127 e_dev_warn("Could not process link status event"); 3128 } 3129 3130 /** 3131 * ixgbe_schedule_fw_event - schedule Firmware event 3132 * @adapter: pointer to the adapter structure 3133 * 3134 * If the adapter is not in down, removing or resetting state, 3135 * an event is scheduled. 3136 */ 3137 static void ixgbe_schedule_fw_event(struct ixgbe_adapter *adapter) 3138 { 3139 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 3140 !test_bit(__IXGBE_REMOVING, &adapter->state) && 3141 !test_bit(__IXGBE_RESETTING, &adapter->state)) { 3142 adapter->flags2 |= IXGBE_FLAG2_FW_ASYNC_EVENT; 3143 ixgbe_service_event_schedule(adapter); 3144 } 3145 } 3146 3147 /** 3148 * ixgbe_aci_event_cleanup - release msg_buf memory 3149 * @event: pointer to the event holding msg_buf to be released 3150 * 3151 * Clean memory allocated for event's msg_buf. Implements auto memory cleanup. 3152 */ 3153 static void ixgbe_aci_event_cleanup(struct ixgbe_aci_event *event) 3154 { 3155 kfree(event->msg_buf); 3156 } 3157 3158 /** 3159 * ixgbe_handle_fw_event - handle Firmware event 3160 * @adapter: pointer to the adapter structure 3161 * 3162 * Obtain an event from the ACI and then and then process it according to the 3163 * type of the event and the opcode. 3164 */ 3165 static void ixgbe_handle_fw_event(struct ixgbe_adapter *adapter) 3166 { 3167 struct ixgbe_aci_event event __cleanup(ixgbe_aci_event_cleanup); 3168 struct ixgbe_hw *hw = &adapter->hw; 3169 bool pending = false; 3170 int err; 3171 3172 if (adapter->flags2 & IXGBE_FLAG2_FW_ASYNC_EVENT) 3173 adapter->flags2 &= ~IXGBE_FLAG2_FW_ASYNC_EVENT; 3174 event.buf_len = IXGBE_ACI_MAX_BUFFER_SIZE; 3175 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL); 3176 if (!event.msg_buf) 3177 return; 3178 3179 do { 3180 err = ixgbe_aci_get_event(hw, &event, &pending); 3181 if (err) 3182 break; 3183 3184 switch (le16_to_cpu(event.desc.opcode)) { 3185 case ixgbe_aci_opc_get_link_status: 3186 ixgbe_handle_link_status_event(adapter, &event); 3187 break; 3188 default: 3189 e_warn(hw, "unknown FW async event captured\n"); 3190 break; 3191 } 3192 } while (pending); 3193 } 3194 3195 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 3196 u64 qmask) 3197 { 3198 struct ixgbe_hw *hw = &adapter->hw; 3199 u32 mask; 3200 3201 switch (hw->mac.type) { 3202 case ixgbe_mac_82598EB: 3203 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 3204 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 3205 break; 3206 case ixgbe_mac_82599EB: 3207 case ixgbe_mac_X540: 3208 case ixgbe_mac_X550: 3209 case ixgbe_mac_X550EM_x: 3210 case ixgbe_mac_x550em_a: 3211 case ixgbe_mac_e610: 3212 mask = (qmask & 0xFFFFFFFF); 3213 if (mask) 3214 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 3215 mask = (qmask >> 32); 3216 if (mask) 3217 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 3218 break; 3219 default: 3220 break; 3221 } 3222 /* skip the flush */ 3223 } 3224 3225 /** 3226 * ixgbe_irq_enable - Enable default interrupt generation settings 3227 * @adapter: board private structure 3228 * @queues: enable irqs for queues 3229 * @flush: flush register write 3230 **/ 3231 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 3232 bool flush) 3233 { 3234 struct ixgbe_hw *hw = &adapter->hw; 3235 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 3236 3237 /* don't reenable LSC while waiting for link */ 3238 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 3239 mask &= ~IXGBE_EIMS_LSC; 3240 3241 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 3242 switch (adapter->hw.mac.type) { 3243 case ixgbe_mac_82599EB: 3244 mask |= IXGBE_EIMS_GPI_SDP0(hw); 3245 break; 3246 case ixgbe_mac_X540: 3247 case ixgbe_mac_X550: 3248 case ixgbe_mac_X550EM_x: 3249 case ixgbe_mac_x550em_a: 3250 mask |= IXGBE_EIMS_TS; 3251 break; 3252 default: 3253 break; 3254 } 3255 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 3256 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3257 switch (adapter->hw.mac.type) { 3258 case ixgbe_mac_82599EB: 3259 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3260 mask |= IXGBE_EIMS_GPI_SDP2(hw); 3261 fallthrough; 3262 case ixgbe_mac_X540: 3263 case ixgbe_mac_X550: 3264 case ixgbe_mac_X550EM_x: 3265 case ixgbe_mac_e610: 3266 mask |= IXGBE_EIMS_FW_EVENT; 3267 fallthrough; 3268 case ixgbe_mac_x550em_a: 3269 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || 3270 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || 3271 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) 3272 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); 3273 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 3274 mask |= IXGBE_EICR_GPI_SDP0_X540; 3275 mask |= IXGBE_EIMS_ECC; 3276 mask |= IXGBE_EIMS_MAILBOX; 3277 break; 3278 default: 3279 break; 3280 } 3281 3282 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 3283 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 3284 mask |= IXGBE_EIMS_FLOW_DIR; 3285 3286 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 3287 if (queues) 3288 ixgbe_irq_enable_queues(adapter, ~0); 3289 if (flush) 3290 IXGBE_WRITE_FLUSH(&adapter->hw); 3291 } 3292 3293 static irqreturn_t ixgbe_msix_other(int irq, void *data) 3294 { 3295 struct ixgbe_adapter *adapter = data; 3296 struct ixgbe_hw *hw = &adapter->hw; 3297 u32 eicr; 3298 3299 /* 3300 * Workaround for Silicon errata. Use clear-by-write instead 3301 * of clear-by-read. Reading with EICS will return the 3302 * interrupt causes without clearing, which later be done 3303 * with the write to EICR. 3304 */ 3305 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 3306 3307 /* The lower 16bits of the EICR register are for the queue interrupts 3308 * which should be masked here in order to not accidentally clear them if 3309 * the bits are high when ixgbe_msix_other is called. There is a race 3310 * condition otherwise which results in possible performance loss 3311 * especially if the ixgbe_msix_other interrupt is triggering 3312 * consistently (as it would when PPS is turned on for the X540 device) 3313 */ 3314 eicr &= 0xFFFF0000; 3315 3316 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 3317 3318 if (eicr & IXGBE_EICR_LSC) 3319 ixgbe_check_lsc(adapter); 3320 3321 if (eicr & IXGBE_EICR_MAILBOX) 3322 ixgbe_msg_task(adapter); 3323 3324 if (eicr & IXGBE_EICR_FW_EVENT) 3325 ixgbe_schedule_fw_event(adapter); 3326 3327 switch (hw->mac.type) { 3328 case ixgbe_mac_82599EB: 3329 case ixgbe_mac_X540: 3330 case ixgbe_mac_X550: 3331 case ixgbe_mac_X550EM_x: 3332 case ixgbe_mac_x550em_a: 3333 case ixgbe_mac_e610: 3334 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 3335 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 3336 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 3337 ixgbe_service_event_schedule(adapter); 3338 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3339 IXGBE_EICR_GPI_SDP0_X540); 3340 } 3341 if (eicr & IXGBE_EICR_ECC) { 3342 e_info(link, "Received ECC Err, initiating reset\n"); 3343 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3344 ixgbe_service_event_schedule(adapter); 3345 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3346 } 3347 /* Handle Flow Director Full threshold interrupt */ 3348 if (eicr & IXGBE_EICR_FLOW_DIR) { 3349 int reinit_count = 0; 3350 int i; 3351 for (i = 0; i < adapter->num_tx_queues; i++) { 3352 struct ixgbe_ring *ring = adapter->tx_ring[i]; 3353 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 3354 &ring->state)) 3355 reinit_count++; 3356 } 3357 if (reinit_count) { 3358 /* no more flow director interrupts until after init */ 3359 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 3360 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 3361 ixgbe_service_event_schedule(adapter); 3362 } 3363 } 3364 ixgbe_check_sfp_event(adapter, eicr); 3365 ixgbe_check_overtemp_event(adapter, eicr); 3366 break; 3367 default: 3368 break; 3369 } 3370 3371 ixgbe_check_fan_failure(adapter, eicr); 3372 3373 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3374 ixgbe_ptp_check_pps_event(adapter); 3375 3376 /* re-enable the original interrupt state, no lsc, no queues */ 3377 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3378 ixgbe_irq_enable(adapter, false, false); 3379 3380 return IRQ_HANDLED; 3381 } 3382 3383 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 3384 { 3385 struct ixgbe_q_vector *q_vector = data; 3386 3387 /* EIAM disabled interrupts (on this vector) for us */ 3388 3389 if (q_vector->rx.ring || q_vector->tx.ring) 3390 napi_schedule_irqoff(&q_vector->napi); 3391 3392 return IRQ_HANDLED; 3393 } 3394 3395 /** 3396 * ixgbe_poll - NAPI Rx polling callback 3397 * @napi: structure for representing this polling device 3398 * @budget: how many packets driver is allowed to clean 3399 * 3400 * This function is used for legacy and MSI, NAPI mode 3401 **/ 3402 int ixgbe_poll(struct napi_struct *napi, int budget) 3403 { 3404 struct ixgbe_q_vector *q_vector = 3405 container_of(napi, struct ixgbe_q_vector, napi); 3406 struct ixgbe_adapter *adapter = q_vector->adapter; 3407 struct ixgbe_ring *ring; 3408 int per_ring_budget, work_done = 0; 3409 bool clean_complete = true; 3410 3411 #ifdef CONFIG_IXGBE_DCA 3412 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 3413 ixgbe_update_dca(q_vector); 3414 #endif 3415 3416 ixgbe_for_each_ring(ring, q_vector->tx) { 3417 bool wd = ring->xsk_pool ? 3418 ixgbe_clean_xdp_tx_irq(q_vector, ring, budget) : 3419 ixgbe_clean_tx_irq(q_vector, ring, budget); 3420 3421 if (!wd) 3422 clean_complete = false; 3423 } 3424 3425 /* Exit if we are called by netpoll */ 3426 if (budget <= 0) 3427 return budget; 3428 3429 /* attempt to distribute budget to each queue fairly, but don't allow 3430 * the budget to go below 1 because we'll exit polling */ 3431 if (q_vector->rx.count > 1) 3432 per_ring_budget = max(budget/q_vector->rx.count, 1); 3433 else 3434 per_ring_budget = budget; 3435 3436 ixgbe_for_each_ring(ring, q_vector->rx) { 3437 int cleaned = ring->xsk_pool ? 3438 ixgbe_clean_rx_irq_zc(q_vector, ring, 3439 per_ring_budget) : 3440 ixgbe_clean_rx_irq(q_vector, ring, 3441 per_ring_budget); 3442 3443 work_done += cleaned; 3444 if (cleaned >= per_ring_budget) 3445 clean_complete = false; 3446 } 3447 3448 /* If all work not completed, return budget and keep polling */ 3449 if (!clean_complete) 3450 return budget; 3451 3452 /* all work done, exit the polling mode */ 3453 if (likely(napi_complete_done(napi, work_done))) { 3454 if (adapter->rx_itr_setting & 1) 3455 ixgbe_set_itr(q_vector); 3456 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3457 ixgbe_irq_enable_queues(adapter, 3458 BIT_ULL(q_vector->v_idx)); 3459 } 3460 3461 return min(work_done, budget - 1); 3462 } 3463 3464 /** 3465 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 3466 * @adapter: board private structure 3467 * 3468 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 3469 * interrupts from the kernel. 3470 **/ 3471 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 3472 { 3473 struct net_device *netdev = adapter->netdev; 3474 unsigned int ri = 0, ti = 0; 3475 int vector, err; 3476 3477 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3478 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3479 struct msix_entry *entry = &adapter->msix_entries[vector]; 3480 3481 if (q_vector->tx.ring && q_vector->rx.ring) { 3482 snprintf(q_vector->name, sizeof(q_vector->name), 3483 "%s-TxRx-%u", netdev->name, ri++); 3484 ti++; 3485 } else if (q_vector->rx.ring) { 3486 snprintf(q_vector->name, sizeof(q_vector->name), 3487 "%s-rx-%u", netdev->name, ri++); 3488 } else if (q_vector->tx.ring) { 3489 snprintf(q_vector->name, sizeof(q_vector->name), 3490 "%s-tx-%u", netdev->name, ti++); 3491 } else { 3492 /* skip this unused q_vector */ 3493 continue; 3494 } 3495 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 3496 q_vector->name, q_vector); 3497 if (err) { 3498 e_err(probe, "request_irq failed for MSIX interrupt " 3499 "Error: %d\n", err); 3500 goto free_queue_irqs; 3501 } 3502 /* If Flow Director is enabled, set interrupt affinity */ 3503 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3504 /* assign the mask for this irq */ 3505 irq_update_affinity_hint(entry->vector, 3506 &q_vector->affinity_mask); 3507 } 3508 } 3509 3510 err = request_irq(adapter->msix_entries[vector].vector, 3511 ixgbe_msix_other, 0, netdev->name, adapter); 3512 if (err) { 3513 e_err(probe, "request_irq for msix_other failed: %d\n", err); 3514 goto free_queue_irqs; 3515 } 3516 3517 return 0; 3518 3519 free_queue_irqs: 3520 while (vector) { 3521 vector--; 3522 irq_update_affinity_hint(adapter->msix_entries[vector].vector, 3523 NULL); 3524 free_irq(adapter->msix_entries[vector].vector, 3525 adapter->q_vector[vector]); 3526 } 3527 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 3528 pci_disable_msix(adapter->pdev); 3529 kfree(adapter->msix_entries); 3530 adapter->msix_entries = NULL; 3531 return err; 3532 } 3533 3534 /** 3535 * ixgbe_intr - legacy mode Interrupt Handler 3536 * @irq: interrupt number 3537 * @data: pointer to a network interface device structure 3538 **/ 3539 static irqreturn_t ixgbe_intr(int irq, void *data) 3540 { 3541 struct ixgbe_adapter *adapter = data; 3542 struct ixgbe_hw *hw = &adapter->hw; 3543 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3544 u32 eicr; 3545 3546 /* 3547 * Workaround for silicon errata #26 on 82598. Mask the interrupt 3548 * before the read of EICR. 3549 */ 3550 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 3551 3552 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 3553 * therefore no explicit interrupt disable is necessary */ 3554 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3555 if (!eicr) { 3556 /* 3557 * shared interrupt alert! 3558 * make sure interrupts are enabled because the read will 3559 * have disabled interrupts due to EIAM 3560 * finish the workaround of silicon errata on 82598. Unmask 3561 * the interrupt that we masked before the EICR read. 3562 */ 3563 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3564 ixgbe_irq_enable(adapter, true, true); 3565 return IRQ_NONE; /* Not our interrupt */ 3566 } 3567 3568 if (eicr & IXGBE_EICR_LSC) 3569 ixgbe_check_lsc(adapter); 3570 3571 if (eicr & IXGBE_EICR_FW_EVENT) 3572 ixgbe_schedule_fw_event(adapter); 3573 3574 switch (hw->mac.type) { 3575 case ixgbe_mac_82599EB: 3576 ixgbe_check_sfp_event(adapter, eicr); 3577 fallthrough; 3578 case ixgbe_mac_X540: 3579 case ixgbe_mac_X550: 3580 case ixgbe_mac_X550EM_x: 3581 case ixgbe_mac_x550em_a: 3582 case ixgbe_mac_e610: 3583 if (eicr & IXGBE_EICR_ECC) { 3584 e_info(link, "Received ECC Err, initiating reset\n"); 3585 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3586 ixgbe_service_event_schedule(adapter); 3587 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3588 } 3589 ixgbe_check_overtemp_event(adapter, eicr); 3590 break; 3591 default: 3592 break; 3593 } 3594 3595 ixgbe_check_fan_failure(adapter, eicr); 3596 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3597 ixgbe_ptp_check_pps_event(adapter); 3598 3599 /* would disable interrupts here but EIAM disabled it */ 3600 napi_schedule_irqoff(&q_vector->napi); 3601 3602 /* 3603 * re-enable link(maybe) and non-queue interrupts, no flush. 3604 * ixgbe_poll will re-enable the queue interrupts 3605 */ 3606 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3607 ixgbe_irq_enable(adapter, false, false); 3608 3609 return IRQ_HANDLED; 3610 } 3611 3612 /** 3613 * ixgbe_request_irq - initialize interrupts 3614 * @adapter: board private structure 3615 * 3616 * Attempts to configure interrupts using the best available 3617 * capabilities of the hardware and kernel. 3618 **/ 3619 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 3620 { 3621 struct net_device *netdev = adapter->netdev; 3622 int err; 3623 3624 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 3625 err = ixgbe_request_msix_irqs(adapter); 3626 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 3627 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 3628 netdev->name, adapter); 3629 else 3630 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 3631 netdev->name, adapter); 3632 3633 if (err) 3634 e_err(probe, "request_irq failed, Error %d\n", err); 3635 3636 return err; 3637 } 3638 3639 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 3640 { 3641 int vector; 3642 3643 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3644 free_irq(adapter->pdev->irq, adapter); 3645 return; 3646 } 3647 3648 if (!adapter->msix_entries) 3649 return; 3650 3651 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3652 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3653 struct msix_entry *entry = &adapter->msix_entries[vector]; 3654 3655 /* free only the irqs that were actually requested */ 3656 if (!q_vector->rx.ring && !q_vector->tx.ring) 3657 continue; 3658 3659 /* clear the affinity_mask in the IRQ descriptor */ 3660 irq_update_affinity_hint(entry->vector, NULL); 3661 3662 free_irq(entry->vector, q_vector); 3663 } 3664 3665 free_irq(adapter->msix_entries[vector].vector, adapter); 3666 } 3667 3668 /** 3669 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 3670 * @adapter: board private structure 3671 **/ 3672 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 3673 { 3674 switch (adapter->hw.mac.type) { 3675 case ixgbe_mac_82598EB: 3676 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3677 break; 3678 case ixgbe_mac_82599EB: 3679 case ixgbe_mac_X540: 3680 case ixgbe_mac_X550: 3681 case ixgbe_mac_X550EM_x: 3682 case ixgbe_mac_x550em_a: 3683 case ixgbe_mac_e610: 3684 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3685 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3686 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3687 break; 3688 default: 3689 break; 3690 } 3691 IXGBE_WRITE_FLUSH(&adapter->hw); 3692 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3693 int vector; 3694 3695 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3696 synchronize_irq(adapter->msix_entries[vector].vector); 3697 3698 synchronize_irq(adapter->msix_entries[vector++].vector); 3699 } else { 3700 synchronize_irq(adapter->pdev->irq); 3701 } 3702 } 3703 3704 /** 3705 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3706 * @adapter: board private structure 3707 * 3708 **/ 3709 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3710 { 3711 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3712 3713 ixgbe_write_eitr(q_vector); 3714 3715 ixgbe_set_ivar(adapter, 0, 0, 0); 3716 ixgbe_set_ivar(adapter, 1, 0, 0); 3717 3718 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3719 } 3720 3721 /** 3722 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3723 * @adapter: board private structure 3724 * @ring: structure containing ring specific data 3725 * 3726 * Configure the Tx descriptor ring after a reset. 3727 **/ 3728 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3729 struct ixgbe_ring *ring) 3730 { 3731 struct ixgbe_hw *hw = &adapter->hw; 3732 u64 tdba = ring->dma; 3733 int wait_loop = 10; 3734 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3735 u8 reg_idx = ring->reg_idx; 3736 3737 ring->xsk_pool = NULL; 3738 if (ring_is_xdp(ring)) 3739 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring); 3740 3741 /* disable queue to avoid issues while updating state */ 3742 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3743 IXGBE_WRITE_FLUSH(hw); 3744 3745 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3746 (tdba & DMA_BIT_MASK(32))); 3747 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3748 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3749 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3750 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3751 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3752 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3753 3754 /* 3755 * set WTHRESH to encourage burst writeback, it should not be set 3756 * higher than 1 when: 3757 * - ITR is 0 as it could cause false TX hangs 3758 * - ITR is set to > 100k int/sec and BQL is enabled 3759 * 3760 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3761 * to or less than the number of on chip descriptors, which is 3762 * currently 40. 3763 */ 3764 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3765 txdctl |= 1u << 16; /* WTHRESH = 1 */ 3766 else 3767 txdctl |= 8u << 16; /* WTHRESH = 8 */ 3768 3769 /* 3770 * Setting PTHRESH to 32 both improves performance 3771 * and avoids a TX hang with DFP enabled 3772 */ 3773 txdctl |= (1u << 8) | /* HTHRESH = 1 */ 3774 32; /* PTHRESH = 32 */ 3775 3776 /* reinitialize flowdirector state */ 3777 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3778 ring->atr_sample_rate = adapter->atr_sample_rate; 3779 ring->atr_count = 0; 3780 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3781 } else { 3782 ring->atr_sample_rate = 0; 3783 } 3784 3785 /* initialize XPS */ 3786 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3787 struct ixgbe_q_vector *q_vector = ring->q_vector; 3788 3789 if (q_vector) 3790 netif_set_xps_queue(ring->netdev, 3791 &q_vector->affinity_mask, 3792 ring->queue_index); 3793 } 3794 3795 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3796 3797 /* reinitialize tx_buffer_info */ 3798 memset(ring->tx_buffer_info, 0, 3799 sizeof(struct ixgbe_tx_buffer) * ring->count); 3800 3801 /* enable queue */ 3802 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3803 3804 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3805 if (hw->mac.type == ixgbe_mac_82598EB && 3806 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3807 return; 3808 3809 /* poll to verify queue is enabled */ 3810 do { 3811 usleep_range(1000, 2000); 3812 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3813 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3814 if (!wait_loop) 3815 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); 3816 } 3817 3818 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3819 { 3820 struct ixgbe_hw *hw = &adapter->hw; 3821 u32 rttdcs, mtqc; 3822 u8 tcs = adapter->hw_tcs; 3823 3824 if (hw->mac.type == ixgbe_mac_82598EB) 3825 return; 3826 3827 /* disable the arbiter while setting MTQC */ 3828 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3829 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3830 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3831 3832 /* set transmit pool layout */ 3833 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3834 mtqc = IXGBE_MTQC_VT_ENA; 3835 if (tcs > 4) 3836 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3837 else if (tcs > 1) 3838 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3839 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3840 IXGBE_82599_VMDQ_4Q_MASK) 3841 mtqc |= IXGBE_MTQC_32VF; 3842 else 3843 mtqc |= IXGBE_MTQC_64VF; 3844 } else { 3845 if (tcs > 4) { 3846 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3847 } else if (tcs > 1) { 3848 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3849 } else { 3850 u8 max_txq = adapter->num_tx_queues + 3851 adapter->num_xdp_queues; 3852 if (max_txq > 63) 3853 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3854 else 3855 mtqc = IXGBE_MTQC_64Q_1PB; 3856 } 3857 } 3858 3859 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3860 3861 /* Enable Security TX Buffer IFG for multiple pb */ 3862 if (tcs) { 3863 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3864 sectx |= IXGBE_SECTX_DCB; 3865 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3866 } 3867 3868 /* re-enable the arbiter */ 3869 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3870 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3871 } 3872 3873 /** 3874 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3875 * @adapter: board private structure 3876 * 3877 * Configure the Tx unit of the MAC after a reset. 3878 **/ 3879 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3880 { 3881 struct ixgbe_hw *hw = &adapter->hw; 3882 u32 dmatxctl; 3883 u32 i; 3884 3885 ixgbe_setup_mtqc(adapter); 3886 3887 if (hw->mac.type != ixgbe_mac_82598EB) { 3888 /* DMATXCTL.EN must be before Tx queues are enabled */ 3889 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3890 dmatxctl |= IXGBE_DMATXCTL_TE; 3891 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3892 } 3893 3894 /* Setup the HW Tx Head and Tail descriptor pointers */ 3895 for (i = 0; i < adapter->num_tx_queues; i++) 3896 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3897 for (i = 0; i < adapter->num_xdp_queues; i++) 3898 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]); 3899 } 3900 3901 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3902 struct ixgbe_ring *ring) 3903 { 3904 struct ixgbe_hw *hw = &adapter->hw; 3905 u8 reg_idx = ring->reg_idx; 3906 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3907 3908 srrctl |= IXGBE_SRRCTL_DROP_EN; 3909 3910 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3911 } 3912 3913 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3914 struct ixgbe_ring *ring) 3915 { 3916 struct ixgbe_hw *hw = &adapter->hw; 3917 u8 reg_idx = ring->reg_idx; 3918 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3919 3920 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3921 3922 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3923 } 3924 3925 #ifdef CONFIG_IXGBE_DCB 3926 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3927 #else 3928 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3929 #endif 3930 { 3931 int i; 3932 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3933 3934 if (adapter->ixgbe_ieee_pfc) 3935 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3936 3937 /* 3938 * We should set the drop enable bit if: 3939 * SR-IOV is enabled 3940 * or 3941 * Number of Rx queues > 1 and flow control is disabled 3942 * 3943 * This allows us to avoid head of line blocking for security 3944 * and performance reasons. 3945 */ 3946 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3947 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3948 for (i = 0; i < adapter->num_rx_queues; i++) 3949 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3950 } else { 3951 for (i = 0; i < adapter->num_rx_queues; i++) 3952 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3953 } 3954 } 3955 3956 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3957 3958 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3959 struct ixgbe_ring *rx_ring) 3960 { 3961 struct ixgbe_hw *hw = &adapter->hw; 3962 u32 srrctl; 3963 u8 reg_idx = rx_ring->reg_idx; 3964 3965 if (hw->mac.type == ixgbe_mac_82598EB) { 3966 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3967 3968 /* 3969 * if VMDq is not active we must program one srrctl register 3970 * per RSS queue since we have enabled RDRXCTL.MVMEN 3971 */ 3972 reg_idx &= mask; 3973 } 3974 3975 /* configure header buffer length, needed for RSC */ 3976 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3977 3978 /* configure the packet buffer length */ 3979 if (rx_ring->xsk_pool) { 3980 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(rx_ring->xsk_pool); 3981 3982 /* If the MAC support setting RXDCTL.RLPML, the 3983 * SRRCTL[n].BSIZEPKT is set to PAGE_SIZE and 3984 * RXDCTL.RLPML is set to the actual UMEM buffer 3985 * size. If not, then we are stuck with a 1k buffer 3986 * size resolution. In this case frames larger than 3987 * the UMEM buffer size viewed in a 1k resolution will 3988 * be dropped. 3989 */ 3990 if (hw->mac.type != ixgbe_mac_82599EB) 3991 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3992 else 3993 srrctl |= xsk_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3994 } else if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) { 3995 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3996 } else { 3997 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3998 } 3999 4000 /* configure descriptor type */ 4001 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 4002 4003 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 4004 } 4005 4006 /** 4007 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries 4008 * @adapter: device handle 4009 * 4010 * - 82598/82599/X540: 128 4011 * - X550(non-SRIOV mode): 512 4012 * - X550(SRIOV mode): 64 4013 */ 4014 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 4015 { 4016 if (adapter->hw.mac.type < ixgbe_mac_X550) 4017 return 128; 4018 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 4019 return 64; 4020 else 4021 return 512; 4022 } 4023 4024 /** 4025 * ixgbe_store_key - Write the RSS key to HW 4026 * @adapter: device handle 4027 * 4028 * Write the RSS key stored in adapter.rss_key to HW. 4029 */ 4030 void ixgbe_store_key(struct ixgbe_adapter *adapter) 4031 { 4032 struct ixgbe_hw *hw = &adapter->hw; 4033 int i; 4034 4035 for (i = 0; i < 10; i++) 4036 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 4037 } 4038 4039 /** 4040 * ixgbe_init_rss_key - Initialize adapter RSS key 4041 * @adapter: device handle 4042 * 4043 * Allocates and initializes the RSS key if it is not allocated. 4044 **/ 4045 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter) 4046 { 4047 u32 *rss_key; 4048 4049 if (!adapter->rss_key) { 4050 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL); 4051 if (unlikely(!rss_key)) 4052 return -ENOMEM; 4053 4054 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE); 4055 adapter->rss_key = rss_key; 4056 } 4057 4058 return 0; 4059 } 4060 4061 /** 4062 * ixgbe_store_reta - Write the RETA table to HW 4063 * @adapter: device handle 4064 * 4065 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 4066 */ 4067 void ixgbe_store_reta(struct ixgbe_adapter *adapter) 4068 { 4069 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 4070 struct ixgbe_hw *hw = &adapter->hw; 4071 u32 reta = 0; 4072 u32 indices_multi; 4073 u8 *indir_tbl = adapter->rss_indir_tbl; 4074 4075 /* Fill out the redirection table as follows: 4076 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 4077 * indices. 4078 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 4079 * - X550: 8 bit wide entries containing 6 bit RSS index 4080 */ 4081 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 4082 indices_multi = 0x11; 4083 else 4084 indices_multi = 0x1; 4085 4086 /* Write redirection table to HW */ 4087 for (i = 0; i < reta_entries; i++) { 4088 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 4089 if ((i & 3) == 3) { 4090 if (i < 128) 4091 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 4092 else 4093 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 4094 reta); 4095 reta = 0; 4096 } 4097 } 4098 } 4099 4100 /** 4101 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) 4102 * @adapter: device handle 4103 * 4104 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 4105 */ 4106 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 4107 { 4108 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 4109 struct ixgbe_hw *hw = &adapter->hw; 4110 u32 vfreta = 0; 4111 4112 /* Write redirection table to HW */ 4113 for (i = 0; i < reta_entries; i++) { 4114 u16 pool = adapter->num_rx_pools; 4115 4116 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 4117 if ((i & 3) != 3) 4118 continue; 4119 4120 while (pool--) 4121 IXGBE_WRITE_REG(hw, 4122 IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)), 4123 vfreta); 4124 vfreta = 0; 4125 } 4126 } 4127 4128 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 4129 { 4130 u32 i, j; 4131 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 4132 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 4133 4134 /* Program table for at least 4 queues w/ SR-IOV so that VFs can 4135 * make full use of any rings they may have. We will use the 4136 * PSRTYPE register to control how many rings we use within the PF. 4137 */ 4138 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4)) 4139 rss_i = 4; 4140 4141 /* Fill out hash function seeds */ 4142 ixgbe_store_key(adapter); 4143 4144 /* Fill out redirection table */ 4145 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 4146 4147 for (i = 0, j = 0; i < reta_entries; i++, j++) { 4148 if (j == rss_i) 4149 j = 0; 4150 4151 adapter->rss_indir_tbl[i] = j; 4152 } 4153 4154 ixgbe_store_reta(adapter); 4155 } 4156 4157 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 4158 { 4159 struct ixgbe_hw *hw = &adapter->hw; 4160 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 4161 int i, j; 4162 4163 /* Fill out hash function seeds */ 4164 for (i = 0; i < 10; i++) { 4165 u16 pool = adapter->num_rx_pools; 4166 4167 while (pool--) 4168 IXGBE_WRITE_REG(hw, 4169 IXGBE_PFVFRSSRK(i, VMDQ_P(pool)), 4170 *(adapter->rss_key + i)); 4171 } 4172 4173 /* Fill out the redirection table */ 4174 for (i = 0, j = 0; i < 64; i++, j++) { 4175 if (j == rss_i) 4176 j = 0; 4177 4178 adapter->rss_indir_tbl[i] = j; 4179 } 4180 4181 ixgbe_store_vfreta(adapter); 4182 } 4183 4184 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 4185 { 4186 struct ixgbe_hw *hw = &adapter->hw; 4187 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 4188 u32 rxcsum; 4189 4190 /* Disable indicating checksum in descriptor, enables RSS hash */ 4191 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 4192 rxcsum |= IXGBE_RXCSUM_PCSD; 4193 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 4194 4195 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 4196 if (adapter->ring_feature[RING_F_RSS].mask) 4197 mrqc = IXGBE_MRQC_RSSEN; 4198 } else { 4199 u8 tcs = adapter->hw_tcs; 4200 4201 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 4202 if (tcs > 4) 4203 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 4204 else if (tcs > 1) 4205 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 4206 else if (adapter->ring_feature[RING_F_VMDQ].mask == 4207 IXGBE_82599_VMDQ_4Q_MASK) 4208 mrqc = IXGBE_MRQC_VMDQRSS32EN; 4209 else 4210 mrqc = IXGBE_MRQC_VMDQRSS64EN; 4211 4212 /* Enable L3/L4 for Tx Switched packets only for X550, 4213 * older devices do not support this feature 4214 */ 4215 if (hw->mac.type >= ixgbe_mac_X550) 4216 mrqc |= IXGBE_MRQC_L3L4TXSWEN; 4217 } else { 4218 if (tcs > 4) 4219 mrqc = IXGBE_MRQC_RTRSS8TCEN; 4220 else if (tcs > 1) 4221 mrqc = IXGBE_MRQC_RTRSS4TCEN; 4222 else 4223 mrqc = IXGBE_MRQC_RSSEN; 4224 } 4225 } 4226 4227 /* Perform hash on these packet types */ 4228 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 4229 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 4230 IXGBE_MRQC_RSS_FIELD_IPV6 | 4231 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 4232 4233 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 4234 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 4235 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 4236 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 4237 4238 if ((hw->mac.type >= ixgbe_mac_X550) && 4239 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 4240 u16 pool = adapter->num_rx_pools; 4241 4242 /* Enable VF RSS mode */ 4243 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 4244 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 4245 4246 /* Setup RSS through the VF registers */ 4247 ixgbe_setup_vfreta(adapter); 4248 vfmrqc = IXGBE_MRQC_RSSEN; 4249 vfmrqc |= rss_field; 4250 4251 while (pool--) 4252 IXGBE_WRITE_REG(hw, 4253 IXGBE_PFVFMRQC(VMDQ_P(pool)), 4254 vfmrqc); 4255 } else { 4256 ixgbe_setup_reta(adapter); 4257 mrqc |= rss_field; 4258 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 4259 } 4260 } 4261 4262 /** 4263 * ixgbe_configure_rscctl - enable RSC for the indicated ring 4264 * @adapter: address of board private structure 4265 * @ring: structure containing ring specific data 4266 **/ 4267 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 4268 struct ixgbe_ring *ring) 4269 { 4270 struct ixgbe_hw *hw = &adapter->hw; 4271 u32 rscctrl; 4272 u8 reg_idx = ring->reg_idx; 4273 4274 if (!ring_is_rsc_enabled(ring)) 4275 return; 4276 4277 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 4278 rscctrl |= IXGBE_RSCCTL_RSCEN; 4279 /* 4280 * we must limit the number of descriptors so that the 4281 * total size of max desc * buf_len is not greater 4282 * than 65536 4283 */ 4284 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 4285 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 4286 } 4287 4288 #define IXGBE_MAX_RX_DESC_POLL 10 4289 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 4290 struct ixgbe_ring *ring) 4291 { 4292 struct ixgbe_hw *hw = &adapter->hw; 4293 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4294 u32 rxdctl; 4295 u8 reg_idx = ring->reg_idx; 4296 4297 if (ixgbe_removed(hw->hw_addr)) 4298 return; 4299 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 4300 if (hw->mac.type == ixgbe_mac_82598EB && 4301 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4302 return; 4303 4304 do { 4305 usleep_range(1000, 2000); 4306 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4307 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 4308 4309 if (!wait_loop) { 4310 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 4311 "the polling period\n", reg_idx); 4312 } 4313 } 4314 4315 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 4316 struct ixgbe_ring *ring) 4317 { 4318 struct ixgbe_hw *hw = &adapter->hw; 4319 union ixgbe_adv_rx_desc *rx_desc; 4320 u64 rdba = ring->dma; 4321 u32 rxdctl; 4322 u8 reg_idx = ring->reg_idx; 4323 4324 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4325 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring); 4326 if (ring->xsk_pool) { 4327 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4328 MEM_TYPE_XSK_BUFF_POOL, 4329 NULL)); 4330 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq); 4331 } else { 4332 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4333 MEM_TYPE_PAGE_SHARED, NULL)); 4334 } 4335 4336 /* disable queue to avoid use of these values while updating state */ 4337 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4338 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 4339 4340 /* write value back with RXDCTL.ENABLE bit cleared */ 4341 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4342 IXGBE_WRITE_FLUSH(hw); 4343 4344 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 4345 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 4346 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 4347 ring->count * sizeof(union ixgbe_adv_rx_desc)); 4348 /* Force flushing of IXGBE_RDLEN to prevent MDD */ 4349 IXGBE_WRITE_FLUSH(hw); 4350 4351 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 4352 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 4353 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 4354 4355 ixgbe_configure_srrctl(adapter, ring); 4356 ixgbe_configure_rscctl(adapter, ring); 4357 4358 if (hw->mac.type == ixgbe_mac_82598EB) { 4359 /* 4360 * enable cache line friendly hardware writes: 4361 * PTHRESH=32 descriptors (half the internal cache), 4362 * this also removes ugly rx_no_buffer_count increment 4363 * HTHRESH=4 descriptors (to minimize latency on fetch) 4364 * WTHRESH=8 burst writeback up to two cache lines 4365 */ 4366 rxdctl &= ~0x3FFFFF; 4367 rxdctl |= 0x080420; 4368 #if (PAGE_SIZE < 8192) 4369 /* RXDCTL.RLPML does not work on 82599 */ 4370 } else if (hw->mac.type != ixgbe_mac_82599EB) { 4371 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4372 IXGBE_RXDCTL_RLPML_EN); 4373 4374 /* Limit the maximum frame size so we don't overrun the skb. 4375 * This can happen in SRIOV mode when the MTU of the VF is 4376 * higher than the MTU of the PF. 4377 */ 4378 if (ring_uses_build_skb(ring) && 4379 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 4380 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB | 4381 IXGBE_RXDCTL_RLPML_EN; 4382 #endif 4383 } 4384 4385 ring->rx_offset = ixgbe_rx_offset(ring); 4386 4387 if (ring->xsk_pool && hw->mac.type != ixgbe_mac_82599EB) { 4388 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(ring->xsk_pool); 4389 4390 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4391 IXGBE_RXDCTL_RLPML_EN); 4392 rxdctl |= xsk_buf_len | IXGBE_RXDCTL_RLPML_EN; 4393 4394 ring->rx_buf_len = xsk_buf_len; 4395 } 4396 4397 /* initialize rx_buffer_info */ 4398 memset(ring->rx_buffer_info, 0, 4399 sizeof(struct ixgbe_rx_buffer) * ring->count); 4400 4401 /* initialize Rx descriptor 0 */ 4402 rx_desc = IXGBE_RX_DESC(ring, 0); 4403 rx_desc->wb.upper.length = 0; 4404 4405 /* enable receive descriptor ring */ 4406 rxdctl |= IXGBE_RXDCTL_ENABLE; 4407 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4408 4409 ixgbe_rx_desc_queue_enable(adapter, ring); 4410 if (ring->xsk_pool) 4411 ixgbe_alloc_rx_buffers_zc(ring, ixgbe_desc_unused(ring)); 4412 else 4413 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 4414 } 4415 4416 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 4417 { 4418 struct ixgbe_hw *hw = &adapter->hw; 4419 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 4420 u16 pool = adapter->num_rx_pools; 4421 4422 /* PSRTYPE must be initialized in non 82598 adapters */ 4423 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4424 IXGBE_PSRTYPE_UDPHDR | 4425 IXGBE_PSRTYPE_IPV4HDR | 4426 IXGBE_PSRTYPE_L2HDR | 4427 IXGBE_PSRTYPE_IPV6HDR; 4428 4429 if (hw->mac.type == ixgbe_mac_82598EB) 4430 return; 4431 4432 if (rss_i > 3) 4433 psrtype |= 2u << 29; 4434 else if (rss_i > 1) 4435 psrtype |= 1u << 29; 4436 4437 while (pool--) 4438 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4439 } 4440 4441 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 4442 { 4443 struct ixgbe_hw *hw = &adapter->hw; 4444 u16 pool = adapter->num_rx_pools; 4445 u32 reg_offset, vf_shift, vmolr; 4446 u32 gcr_ext, vmdctl; 4447 int i; 4448 4449 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 4450 return; 4451 4452 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 4453 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 4454 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 4455 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 4456 vmdctl |= IXGBE_VT_CTL_REPLEN; 4457 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 4458 4459 /* accept untagged packets until a vlan tag is 4460 * specifically set for the VMDQ queue/pool 4461 */ 4462 vmolr = IXGBE_VMOLR_AUPE; 4463 while (pool--) 4464 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(pool)), vmolr); 4465 4466 vf_shift = VMDQ_P(0) % 32; 4467 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 4468 4469 /* Enable only the PF's pool for Tx/Rx */ 4470 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); 4471 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 4472 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); 4473 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 4474 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 4475 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 4476 4477 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 4478 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 4479 4480 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 4481 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4482 4483 /* 4484 * Set up VF register offsets for selected VT Mode, 4485 * i.e. 32 or 64 VFs for SR-IOV 4486 */ 4487 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4488 case IXGBE_82599_VMDQ_8Q_MASK: 4489 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 4490 break; 4491 case IXGBE_82599_VMDQ_4Q_MASK: 4492 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 4493 break; 4494 default: 4495 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 4496 break; 4497 } 4498 4499 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4500 4501 for (i = 0; i < adapter->num_vfs; i++) { 4502 /* configure spoof checking */ 4503 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, 4504 adapter->vfinfo[i].spoofchk_enabled); 4505 4506 /* Enable/Disable RSS query feature */ 4507 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 4508 adapter->vfinfo[i].rss_query_enabled); 4509 } 4510 } 4511 4512 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 4513 { 4514 struct ixgbe_hw *hw = &adapter->hw; 4515 struct net_device *netdev = adapter->netdev; 4516 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4517 struct ixgbe_ring *rx_ring; 4518 int i; 4519 u32 mhadd, hlreg0; 4520 4521 #ifdef IXGBE_FCOE 4522 /* adjust max frame to be able to do baby jumbo for FCoE */ 4523 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 4524 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 4525 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4526 4527 #endif /* IXGBE_FCOE */ 4528 4529 /* adjust max frame to be at least the size of a standard frame */ 4530 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 4531 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 4532 4533 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 4534 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 4535 mhadd &= ~IXGBE_MHADD_MFS_MASK; 4536 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 4537 4538 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 4539 } 4540 4541 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4542 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 4543 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4544 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4545 4546 /* 4547 * Setup the HW Rx Head and Tail Descriptor Pointers and 4548 * the Base and Length of the Rx Descriptor Ring 4549 */ 4550 for (i = 0; i < adapter->num_rx_queues; i++) { 4551 rx_ring = adapter->rx_ring[i]; 4552 4553 clear_ring_rsc_enabled(rx_ring); 4554 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4555 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4556 4557 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4558 set_ring_rsc_enabled(rx_ring); 4559 4560 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state)) 4561 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4562 4563 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 4564 continue; 4565 4566 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4567 4568 #if (PAGE_SIZE < 8192) 4569 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4570 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4571 4572 if (IXGBE_2K_TOO_SMALL_WITH_PADDING || 4573 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 4574 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4575 #endif 4576 } 4577 } 4578 4579 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 4580 { 4581 struct ixgbe_hw *hw = &adapter->hw; 4582 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 4583 4584 switch (hw->mac.type) { 4585 case ixgbe_mac_82598EB: 4586 /* 4587 * For VMDq support of different descriptor types or 4588 * buffer sizes through the use of multiple SRRCTL 4589 * registers, RDRXCTL.MVMEN must be set to 1 4590 * 4591 * also, the manual doesn't mention it clearly but DCA hints 4592 * will only use queue 0's tags unless this bit is set. Side 4593 * effects of setting this bit are only that SRRCTL must be 4594 * fully programmed [0..15] 4595 */ 4596 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 4597 break; 4598 case ixgbe_mac_X550: 4599 case ixgbe_mac_X550EM_x: 4600 case ixgbe_mac_x550em_a: 4601 case ixgbe_mac_e610: 4602 if (adapter->num_vfs) 4603 rdrxctl |= IXGBE_RDRXCTL_PSP; 4604 fallthrough; 4605 case ixgbe_mac_82599EB: 4606 case ixgbe_mac_X540: 4607 /* Disable RSC for ACK packets */ 4608 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 4609 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 4610 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 4611 /* hardware requires some bits to be set by default */ 4612 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 4613 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 4614 break; 4615 default: 4616 /* We should do nothing since we don't know this hardware */ 4617 return; 4618 } 4619 4620 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 4621 } 4622 4623 /** 4624 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 4625 * @adapter: board private structure 4626 * 4627 * Configure the Rx unit of the MAC after a reset. 4628 **/ 4629 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 4630 { 4631 struct ixgbe_hw *hw = &adapter->hw; 4632 int i; 4633 u32 rxctrl, rfctl; 4634 4635 /* disable receives while setting up the descriptors */ 4636 hw->mac.ops.disable_rx(hw); 4637 4638 ixgbe_setup_psrtype(adapter); 4639 ixgbe_setup_rdrxctl(adapter); 4640 4641 /* RSC Setup */ 4642 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 4643 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 4644 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 4645 rfctl |= IXGBE_RFCTL_RSC_DIS; 4646 4647 /* disable NFS filtering */ 4648 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS); 4649 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 4650 4651 /* Program registers for the distribution of queues */ 4652 ixgbe_setup_mrqc(adapter); 4653 4654 /* set_rx_buffer_len must be called before ring initialization */ 4655 ixgbe_set_rx_buffer_len(adapter); 4656 4657 /* 4658 * Setup the HW Rx Head and Tail Descriptor Pointers and 4659 * the Base and Length of the Rx Descriptor Ring 4660 */ 4661 for (i = 0; i < adapter->num_rx_queues; i++) 4662 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 4663 4664 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4665 /* disable drop enable for 82598 parts */ 4666 if (hw->mac.type == ixgbe_mac_82598EB) 4667 rxctrl |= IXGBE_RXCTRL_DMBYPS; 4668 4669 /* enable all receives */ 4670 rxctrl |= IXGBE_RXCTRL_RXEN; 4671 hw->mac.ops.enable_rx_dma(hw, rxctrl); 4672 } 4673 4674 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 4675 __be16 proto, u16 vid) 4676 { 4677 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4678 struct ixgbe_hw *hw = &adapter->hw; 4679 4680 /* add VID to filter table */ 4681 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4682 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); 4683 4684 set_bit(vid, adapter->active_vlans); 4685 4686 return 0; 4687 } 4688 4689 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) 4690 { 4691 u32 vlvf; 4692 int idx; 4693 4694 /* short cut the special case */ 4695 if (vlan == 0) 4696 return 0; 4697 4698 /* Search for the vlan id in the VLVF entries */ 4699 for (idx = IXGBE_VLVF_ENTRIES; --idx;) { 4700 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); 4701 if ((vlvf & VLAN_VID_MASK) == vlan) 4702 break; 4703 } 4704 4705 return idx; 4706 } 4707 4708 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) 4709 { 4710 struct ixgbe_hw *hw = &adapter->hw; 4711 u32 bits, word; 4712 int idx; 4713 4714 idx = ixgbe_find_vlvf_entry(hw, vid); 4715 if (!idx) 4716 return; 4717 4718 /* See if any other pools are set for this VLAN filter 4719 * entry other than the PF. 4720 */ 4721 word = idx * 2 + (VMDQ_P(0) / 32); 4722 bits = ~BIT(VMDQ_P(0) % 32); 4723 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4724 4725 /* Disable the filter so this falls into the default pool. */ 4726 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { 4727 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4728 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); 4729 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); 4730 } 4731 } 4732 4733 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 4734 __be16 proto, u16 vid) 4735 { 4736 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4737 struct ixgbe_hw *hw = &adapter->hw; 4738 4739 /* remove VID from filter table */ 4740 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4741 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); 4742 4743 clear_bit(vid, adapter->active_vlans); 4744 4745 return 0; 4746 } 4747 4748 /** 4749 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 4750 * @adapter: driver data 4751 */ 4752 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 4753 { 4754 struct ixgbe_hw *hw = &adapter->hw; 4755 u32 vlnctrl; 4756 int i, j; 4757 4758 switch (hw->mac.type) { 4759 case ixgbe_mac_82598EB: 4760 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4761 vlnctrl &= ~IXGBE_VLNCTRL_VME; 4762 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4763 break; 4764 case ixgbe_mac_82599EB: 4765 case ixgbe_mac_X540: 4766 case ixgbe_mac_X550: 4767 case ixgbe_mac_X550EM_x: 4768 case ixgbe_mac_x550em_a: 4769 case ixgbe_mac_e610: 4770 for (i = 0; i < adapter->num_rx_queues; i++) { 4771 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4772 4773 if (!netif_is_ixgbe(ring->netdev)) 4774 continue; 4775 4776 j = ring->reg_idx; 4777 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4778 vlnctrl &= ~IXGBE_RXDCTL_VME; 4779 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4780 } 4781 break; 4782 default: 4783 break; 4784 } 4785 } 4786 4787 /** 4788 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 4789 * @adapter: driver data 4790 */ 4791 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 4792 { 4793 struct ixgbe_hw *hw = &adapter->hw; 4794 u32 vlnctrl; 4795 int i, j; 4796 4797 switch (hw->mac.type) { 4798 case ixgbe_mac_82598EB: 4799 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4800 vlnctrl |= IXGBE_VLNCTRL_VME; 4801 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4802 break; 4803 case ixgbe_mac_82599EB: 4804 case ixgbe_mac_X540: 4805 case ixgbe_mac_X550: 4806 case ixgbe_mac_X550EM_x: 4807 case ixgbe_mac_x550em_a: 4808 case ixgbe_mac_e610: 4809 for (i = 0; i < adapter->num_rx_queues; i++) { 4810 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4811 4812 if (!netif_is_ixgbe(ring->netdev)) 4813 continue; 4814 4815 j = ring->reg_idx; 4816 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4817 vlnctrl |= IXGBE_RXDCTL_VME; 4818 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4819 } 4820 break; 4821 default: 4822 break; 4823 } 4824 } 4825 4826 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) 4827 { 4828 struct ixgbe_hw *hw = &adapter->hw; 4829 u32 vlnctrl, i; 4830 4831 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4832 4833 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { 4834 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */ 4835 vlnctrl |= IXGBE_VLNCTRL_VFE; 4836 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4837 } else { 4838 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 4839 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4840 return; 4841 } 4842 4843 /* Nothing to do for 82598 */ 4844 if (hw->mac.type == ixgbe_mac_82598EB) 4845 return; 4846 4847 /* We are already in VLAN promisc, nothing to do */ 4848 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) 4849 return; 4850 4851 /* Set flag so we don't redo unnecessary work */ 4852 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; 4853 4854 /* Add PF to all active pools */ 4855 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4856 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); 4857 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); 4858 4859 vlvfb |= BIT(VMDQ_P(0) % 32); 4860 IXGBE_WRITE_REG(hw, reg_offset, vlvfb); 4861 } 4862 4863 /* Set all bits in the VLAN filter table array */ 4864 for (i = hw->mac.vft_size; i--;) 4865 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); 4866 } 4867 4868 #define VFTA_BLOCK_SIZE 8 4869 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) 4870 { 4871 struct ixgbe_hw *hw = &adapter->hw; 4872 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4873 u32 vid_start = vfta_offset * 32; 4874 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4875 u32 i, vid, word, bits; 4876 4877 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4878 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); 4879 4880 /* pull VLAN ID from VLVF */ 4881 vid = vlvf & VLAN_VID_MASK; 4882 4883 /* only concern outselves with a certain range */ 4884 if (vid < vid_start || vid >= vid_end) 4885 continue; 4886 4887 if (vlvf) { 4888 /* record VLAN ID in VFTA */ 4889 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4890 4891 /* if PF is part of this then continue */ 4892 if (test_bit(vid, adapter->active_vlans)) 4893 continue; 4894 } 4895 4896 /* remove PF from the pool */ 4897 word = i * 2 + VMDQ_P(0) / 32; 4898 bits = ~BIT(VMDQ_P(0) % 32); 4899 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4900 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); 4901 } 4902 4903 /* extract values from active_vlans and write back to VFTA */ 4904 for (i = VFTA_BLOCK_SIZE; i--;) { 4905 vid = (vfta_offset + i) * 32; 4906 word = vid / BITS_PER_LONG; 4907 bits = vid % BITS_PER_LONG; 4908 4909 vfta[i] |= adapter->active_vlans[word] >> bits; 4910 4911 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); 4912 } 4913 } 4914 4915 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) 4916 { 4917 struct ixgbe_hw *hw = &adapter->hw; 4918 u32 vlnctrl, i; 4919 4920 /* Set VLAN filtering to enabled */ 4921 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4922 vlnctrl |= IXGBE_VLNCTRL_VFE; 4923 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4924 4925 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) || 4926 hw->mac.type == ixgbe_mac_82598EB) 4927 return; 4928 4929 /* We are not in VLAN promisc, nothing to do */ 4930 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4931 return; 4932 4933 /* Set flag so we don't redo unnecessary work */ 4934 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4935 4936 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) 4937 ixgbe_scrub_vfta(adapter, i); 4938 } 4939 4940 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 4941 { 4942 u16 vid = 1; 4943 4944 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 4945 4946 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 4947 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 4948 } 4949 4950 /** 4951 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 4952 * @netdev: network interface device structure 4953 * 4954 * Writes multicast address list to the MTA hash table. 4955 * Returns: -ENOMEM on failure 4956 * 0 on no addresses written 4957 * X on writing X addresses to MTA 4958 **/ 4959 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 4960 { 4961 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4962 struct ixgbe_hw *hw = &adapter->hw; 4963 4964 if (!netif_running(netdev)) 4965 return 0; 4966 4967 if (hw->mac.ops.update_mc_addr_list) 4968 hw->mac.ops.update_mc_addr_list(hw, netdev); 4969 else 4970 return -ENOMEM; 4971 4972 #ifdef CONFIG_PCI_IOV 4973 ixgbe_restore_vf_multicasts(adapter); 4974 #endif 4975 4976 return netdev_mc_count(netdev); 4977 } 4978 4979 #ifdef CONFIG_PCI_IOV 4980 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 4981 { 4982 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4983 struct ixgbe_hw *hw = &adapter->hw; 4984 int i; 4985 4986 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4987 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4988 4989 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4990 hw->mac.ops.set_rar(hw, i, 4991 mac_table->addr, 4992 mac_table->pool, 4993 IXGBE_RAH_AV); 4994 else 4995 hw->mac.ops.clear_rar(hw, i); 4996 } 4997 } 4998 4999 #endif 5000 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 5001 { 5002 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 5003 struct ixgbe_hw *hw = &adapter->hw; 5004 int i; 5005 5006 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 5007 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) 5008 continue; 5009 5010 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 5011 5012 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 5013 hw->mac.ops.set_rar(hw, i, 5014 mac_table->addr, 5015 mac_table->pool, 5016 IXGBE_RAH_AV); 5017 else 5018 hw->mac.ops.clear_rar(hw, i); 5019 } 5020 } 5021 5022 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 5023 { 5024 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 5025 struct ixgbe_hw *hw = &adapter->hw; 5026 int i; 5027 5028 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 5029 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 5030 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 5031 } 5032 5033 ixgbe_sync_mac_table(adapter); 5034 } 5035 5036 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) 5037 { 5038 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 5039 struct ixgbe_hw *hw = &adapter->hw; 5040 int i, count = 0; 5041 5042 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 5043 /* do not count default RAR as available */ 5044 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) 5045 continue; 5046 5047 /* only count unused and addresses that belong to us */ 5048 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { 5049 if (mac_table->pool != pool) 5050 continue; 5051 } 5052 5053 count++; 5054 } 5055 5056 return count; 5057 } 5058 5059 /* this function destroys the first RAR entry */ 5060 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) 5061 { 5062 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 5063 struct ixgbe_hw *hw = &adapter->hw; 5064 5065 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); 5066 mac_table->pool = VMDQ_P(0); 5067 5068 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; 5069 5070 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, 5071 IXGBE_RAH_AV); 5072 } 5073 5074 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 5075 const u8 *addr, u16 pool) 5076 { 5077 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 5078 struct ixgbe_hw *hw = &adapter->hw; 5079 int i; 5080 5081 if (is_zero_ether_addr(addr)) 5082 return -EINVAL; 5083 5084 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 5085 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 5086 continue; 5087 5088 ether_addr_copy(mac_table->addr, addr); 5089 mac_table->pool = pool; 5090 5091 mac_table->state |= IXGBE_MAC_STATE_MODIFIED | 5092 IXGBE_MAC_STATE_IN_USE; 5093 5094 ixgbe_sync_mac_table(adapter); 5095 5096 return i; 5097 } 5098 5099 return -ENOMEM; 5100 } 5101 5102 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 5103 const u8 *addr, u16 pool) 5104 { 5105 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 5106 struct ixgbe_hw *hw = &adapter->hw; 5107 int i; 5108 5109 if (is_zero_ether_addr(addr)) 5110 return -EINVAL; 5111 5112 /* search table for addr, if found clear IN_USE flag and sync */ 5113 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 5114 /* we can only delete an entry if it is in use */ 5115 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) 5116 continue; 5117 /* we only care about entries that belong to the given pool */ 5118 if (mac_table->pool != pool) 5119 continue; 5120 /* we only care about a specific MAC address */ 5121 if (!ether_addr_equal(addr, mac_table->addr)) 5122 continue; 5123 5124 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 5125 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 5126 5127 ixgbe_sync_mac_table(adapter); 5128 5129 return 0; 5130 } 5131 5132 return -ENOMEM; 5133 } 5134 5135 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) 5136 { 5137 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5138 int ret; 5139 5140 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); 5141 5142 return min_t(int, ret, 0); 5143 } 5144 5145 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) 5146 { 5147 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5148 5149 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); 5150 5151 return 0; 5152 } 5153 5154 /** 5155 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 5156 * @netdev: network interface device structure 5157 * 5158 * The set_rx_method entry point is called whenever the unicast/multicast 5159 * address list or the network interface flags are updated. This routine is 5160 * responsible for configuring the hardware for proper unicast, multicast and 5161 * promiscuous mode. 5162 **/ 5163 void ixgbe_set_rx_mode(struct net_device *netdev) 5164 { 5165 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5166 struct ixgbe_hw *hw = &adapter->hw; 5167 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 5168 netdev_features_t features = netdev->features; 5169 int count; 5170 5171 /* Check for Promiscuous and All Multicast modes */ 5172 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 5173 5174 /* set all bits that we expect to always be set */ 5175 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 5176 fctrl |= IXGBE_FCTRL_BAM; 5177 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 5178 fctrl |= IXGBE_FCTRL_PMCF; 5179 5180 /* clear the bits we are changing the status of */ 5181 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 5182 if (netdev->flags & IFF_PROMISC) { 5183 hw->addr_ctrl.user_set_promisc = true; 5184 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 5185 vmolr |= IXGBE_VMOLR_MPE; 5186 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 5187 } else { 5188 if (netdev->flags & IFF_ALLMULTI) { 5189 fctrl |= IXGBE_FCTRL_MPE; 5190 vmolr |= IXGBE_VMOLR_MPE; 5191 } 5192 hw->addr_ctrl.user_set_promisc = false; 5193 } 5194 5195 /* 5196 * Write addresses to available RAR registers, if there is not 5197 * sufficient space to store all the addresses then enable 5198 * unicast promiscuous mode 5199 */ 5200 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { 5201 fctrl |= IXGBE_FCTRL_UPE; 5202 vmolr |= IXGBE_VMOLR_ROPE; 5203 } 5204 5205 /* Write addresses to the MTA, if the attempt fails 5206 * then we should just turn on promiscuous mode so 5207 * that we can at least receive multicast traffic 5208 */ 5209 count = ixgbe_write_mc_addr_list(netdev); 5210 if (count < 0) { 5211 fctrl |= IXGBE_FCTRL_MPE; 5212 vmolr |= IXGBE_VMOLR_MPE; 5213 } else if (count) { 5214 vmolr |= IXGBE_VMOLR_ROMPE; 5215 } 5216 5217 if (hw->mac.type != ixgbe_mac_82598EB) { 5218 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 5219 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 5220 IXGBE_VMOLR_ROPE); 5221 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 5222 } 5223 5224 /* This is useful for sniffing bad packets. */ 5225 if (features & NETIF_F_RXALL) { 5226 /* UPE and MPE will be handled by normal PROMISC logic 5227 * in e1000e_set_rx_mode */ 5228 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 5229 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 5230 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 5231 5232 fctrl &= ~(IXGBE_FCTRL_DPF); 5233 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 5234 } 5235 5236 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 5237 5238 if (features & NETIF_F_HW_VLAN_CTAG_RX) 5239 ixgbe_vlan_strip_enable(adapter); 5240 else 5241 ixgbe_vlan_strip_disable(adapter); 5242 5243 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 5244 ixgbe_vlan_promisc_disable(adapter); 5245 else 5246 ixgbe_vlan_promisc_enable(adapter); 5247 } 5248 5249 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 5250 { 5251 int q_idx; 5252 5253 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 5254 napi_enable(&adapter->q_vector[q_idx]->napi); 5255 } 5256 5257 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 5258 { 5259 int q_idx; 5260 5261 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 5262 napi_disable(&adapter->q_vector[q_idx]->napi); 5263 } 5264 5265 static int ixgbe_udp_tunnel_sync(struct net_device *dev, unsigned int table) 5266 { 5267 struct ixgbe_adapter *adapter = netdev_priv(dev); 5268 struct ixgbe_hw *hw = &adapter->hw; 5269 struct udp_tunnel_info ti; 5270 5271 udp_tunnel_nic_get_port(dev, table, 0, &ti); 5272 if (ti.type == UDP_TUNNEL_TYPE_VXLAN) 5273 adapter->vxlan_port = ti.port; 5274 else 5275 adapter->geneve_port = ti.port; 5276 5277 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, 5278 ntohs(adapter->vxlan_port) | 5279 ntohs(adapter->geneve_port) << 5280 IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT); 5281 return 0; 5282 } 5283 5284 static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550 = { 5285 .sync_table = ixgbe_udp_tunnel_sync, 5286 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY, 5287 .tables = { 5288 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 5289 }, 5290 }; 5291 5292 static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550em_a = { 5293 .sync_table = ixgbe_udp_tunnel_sync, 5294 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY, 5295 .tables = { 5296 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 5297 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, }, 5298 }, 5299 }; 5300 5301 #ifdef CONFIG_IXGBE_DCB 5302 /** 5303 * ixgbe_configure_dcb - Configure DCB hardware 5304 * @adapter: ixgbe adapter struct 5305 * 5306 * This is called by the driver on open to configure the DCB hardware. 5307 * This is also called by the gennetlink interface when reconfiguring 5308 * the DCB state. 5309 */ 5310 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 5311 { 5312 struct ixgbe_hw *hw = &adapter->hw; 5313 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 5314 5315 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 5316 if (hw->mac.type == ixgbe_mac_82598EB) 5317 netif_set_tso_max_size(adapter->netdev, 65536); 5318 return; 5319 } 5320 5321 if (hw->mac.type == ixgbe_mac_82598EB) 5322 netif_set_tso_max_size(adapter->netdev, 32768); 5323 5324 #ifdef IXGBE_FCOE 5325 if (adapter->netdev->fcoe_mtu) 5326 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 5327 #endif 5328 5329 /* reconfigure the hardware */ 5330 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 5331 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5332 DCB_TX_CONFIG); 5333 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5334 DCB_RX_CONFIG); 5335 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 5336 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 5337 ixgbe_dcb_hw_ets(&adapter->hw, 5338 adapter->ixgbe_ieee_ets, 5339 max_frame); 5340 ixgbe_dcb_hw_pfc_config(&adapter->hw, 5341 adapter->ixgbe_ieee_pfc->pfc_en, 5342 adapter->ixgbe_ieee_ets->prio_tc); 5343 } 5344 5345 /* Enable RSS Hash per TC */ 5346 if (hw->mac.type != ixgbe_mac_82598EB) { 5347 u32 msb = 0; 5348 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 5349 5350 while (rss_i) { 5351 msb++; 5352 rss_i >>= 1; 5353 } 5354 5355 /* write msb to all 8 TCs in one write */ 5356 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 5357 } 5358 } 5359 #endif 5360 5361 /* Additional bittime to account for IXGBE framing */ 5362 #define IXGBE_ETH_FRAMING 20 5363 5364 /** 5365 * ixgbe_hpbthresh - calculate high water mark for flow control 5366 * 5367 * @adapter: board private structure to calculate for 5368 * @pb: packet buffer to calculate 5369 */ 5370 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 5371 { 5372 struct ixgbe_hw *hw = &adapter->hw; 5373 struct net_device *dev = adapter->netdev; 5374 int link, tc, kb, marker; 5375 u32 dv_id, rx_pba; 5376 5377 /* Calculate max LAN frame size */ 5378 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 5379 5380 #ifdef IXGBE_FCOE 5381 /* FCoE traffic class uses FCOE jumbo frames */ 5382 if (dev->fcoe_mtu && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE && 5383 (pb == ixgbe_fcoe_get_tc(adapter))) 5384 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5385 #endif 5386 5387 /* Calculate delay value for device */ 5388 switch (hw->mac.type) { 5389 case ixgbe_mac_X540: 5390 case ixgbe_mac_X550: 5391 case ixgbe_mac_X550EM_x: 5392 case ixgbe_mac_x550em_a: 5393 case ixgbe_mac_e610: 5394 dv_id = IXGBE_DV_X540(link, tc); 5395 break; 5396 default: 5397 dv_id = IXGBE_DV(link, tc); 5398 break; 5399 } 5400 5401 /* Loopback switch introduces additional latency */ 5402 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5403 dv_id += IXGBE_B2BT(tc); 5404 5405 /* Delay value is calculated in bit times convert to KB */ 5406 kb = IXGBE_BT2KB(dv_id); 5407 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 5408 5409 marker = rx_pba - kb; 5410 5411 /* It is possible that the packet buffer is not large enough 5412 * to provide required headroom. In this case throw an error 5413 * to user and a do the best we can. 5414 */ 5415 if (marker < 0) { 5416 e_warn(drv, "Packet Buffer(%i) can not provide enough" 5417 "headroom to support flow control." 5418 "Decrease MTU or number of traffic classes\n", pb); 5419 marker = tc + 1; 5420 } 5421 5422 return marker; 5423 } 5424 5425 /** 5426 * ixgbe_lpbthresh - calculate low water mark for flow control 5427 * 5428 * @adapter: board private structure to calculate for 5429 * @pb: packet buffer to calculate 5430 */ 5431 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 5432 { 5433 struct ixgbe_hw *hw = &adapter->hw; 5434 struct net_device *dev = adapter->netdev; 5435 int tc; 5436 u32 dv_id; 5437 5438 /* Calculate max LAN frame size */ 5439 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 5440 5441 #ifdef IXGBE_FCOE 5442 /* FCoE traffic class uses FCOE jumbo frames */ 5443 if (dev->fcoe_mtu && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE && 5444 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 5445 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5446 #endif 5447 5448 /* Calculate delay value for device */ 5449 switch (hw->mac.type) { 5450 case ixgbe_mac_X540: 5451 case ixgbe_mac_X550: 5452 case ixgbe_mac_X550EM_x: 5453 case ixgbe_mac_x550em_a: 5454 case ixgbe_mac_e610: 5455 dv_id = IXGBE_LOW_DV_X540(tc); 5456 break; 5457 default: 5458 dv_id = IXGBE_LOW_DV(tc); 5459 break; 5460 } 5461 5462 /* Delay value is calculated in bit times convert to KB */ 5463 return IXGBE_BT2KB(dv_id); 5464 } 5465 5466 /* 5467 * ixgbe_pbthresh_setup - calculate and setup high low water marks 5468 */ 5469 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 5470 { 5471 struct ixgbe_hw *hw = &adapter->hw; 5472 int num_tc = adapter->hw_tcs; 5473 int i; 5474 5475 if (!num_tc) 5476 num_tc = 1; 5477 5478 for (i = 0; i < num_tc; i++) { 5479 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 5480 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 5481 5482 /* Low water marks must not be larger than high water marks */ 5483 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 5484 hw->fc.low_water[i] = 0; 5485 } 5486 5487 for (; i < MAX_TRAFFIC_CLASS; i++) 5488 hw->fc.high_water[i] = 0; 5489 } 5490 5491 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 5492 { 5493 struct ixgbe_hw *hw = &adapter->hw; 5494 int hdrm; 5495 u8 tc = adapter->hw_tcs; 5496 5497 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 5498 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 5499 hdrm = 32 << adapter->fdir_pballoc; 5500 else 5501 hdrm = 0; 5502 5503 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 5504 ixgbe_pbthresh_setup(adapter); 5505 } 5506 5507 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 5508 { 5509 struct ixgbe_hw *hw = &adapter->hw; 5510 struct hlist_node *node2; 5511 struct ixgbe_fdir_filter *filter; 5512 u8 queue; 5513 5514 spin_lock(&adapter->fdir_perfect_lock); 5515 5516 if (!hlist_empty(&adapter->fdir_filter_list)) 5517 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 5518 5519 hlist_for_each_entry_safe(filter, node2, 5520 &adapter->fdir_filter_list, fdir_node) { 5521 if (filter->action == IXGBE_FDIR_DROP_QUEUE) { 5522 queue = IXGBE_FDIR_DROP_QUEUE; 5523 } else { 5524 u32 ring = ethtool_get_flow_spec_ring(filter->action); 5525 u8 vf = ethtool_get_flow_spec_ring_vf(filter->action); 5526 5527 if (!vf && (ring >= adapter->num_rx_queues)) { 5528 e_err(drv, "FDIR restore failed without VF, ring: %u\n", 5529 ring); 5530 continue; 5531 } else if (vf && 5532 ((vf > adapter->num_vfs) || 5533 ring >= adapter->num_rx_queues_per_pool)) { 5534 e_err(drv, "FDIR restore failed with VF, vf: %hhu, ring: %u\n", 5535 vf, ring); 5536 continue; 5537 } 5538 5539 /* Map the ring onto the absolute queue index */ 5540 if (!vf) 5541 queue = adapter->rx_ring[ring]->reg_idx; 5542 else 5543 queue = ((vf - 1) * 5544 adapter->num_rx_queues_per_pool) + ring; 5545 } 5546 5547 ixgbe_fdir_write_perfect_filter_82599(hw, 5548 &filter->filter, filter->sw_idx, queue); 5549 } 5550 5551 spin_unlock(&adapter->fdir_perfect_lock); 5552 } 5553 5554 /** 5555 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 5556 * @rx_ring: ring to free buffers from 5557 **/ 5558 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 5559 { 5560 u16 i = rx_ring->next_to_clean; 5561 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 5562 5563 if (rx_ring->xsk_pool) { 5564 ixgbe_xsk_clean_rx_ring(rx_ring); 5565 goto skip_free; 5566 } 5567 5568 /* Free all the Rx ring sk_buffs */ 5569 while (i != rx_ring->next_to_alloc) { 5570 if (rx_buffer->skb) { 5571 struct sk_buff *skb = rx_buffer->skb; 5572 if (IXGBE_CB(skb)->page_released) 5573 dma_unmap_page_attrs(rx_ring->dev, 5574 IXGBE_CB(skb)->dma, 5575 ixgbe_rx_pg_size(rx_ring), 5576 DMA_FROM_DEVICE, 5577 IXGBE_RX_DMA_ATTR); 5578 dev_kfree_skb(skb); 5579 } 5580 5581 /* Invalidate cache lines that may have been written to by 5582 * device so that we avoid corrupting memory. 5583 */ 5584 dma_sync_single_range_for_cpu(rx_ring->dev, 5585 rx_buffer->dma, 5586 rx_buffer->page_offset, 5587 ixgbe_rx_bufsz(rx_ring), 5588 DMA_FROM_DEVICE); 5589 5590 /* free resources associated with mapping */ 5591 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 5592 ixgbe_rx_pg_size(rx_ring), 5593 DMA_FROM_DEVICE, 5594 IXGBE_RX_DMA_ATTR); 5595 __page_frag_cache_drain(rx_buffer->page, 5596 rx_buffer->pagecnt_bias); 5597 5598 i++; 5599 rx_buffer++; 5600 if (i == rx_ring->count) { 5601 i = 0; 5602 rx_buffer = rx_ring->rx_buffer_info; 5603 } 5604 } 5605 5606 skip_free: 5607 rx_ring->next_to_alloc = 0; 5608 rx_ring->next_to_clean = 0; 5609 rx_ring->next_to_use = 0; 5610 } 5611 5612 static int ixgbe_fwd_ring_up(struct ixgbe_adapter *adapter, 5613 struct ixgbe_fwd_adapter *accel) 5614 { 5615 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 5616 int num_tc = netdev_get_num_tc(adapter->netdev); 5617 struct net_device *vdev = accel->netdev; 5618 int i, baseq, err; 5619 5620 baseq = accel->pool * adapter->num_rx_queues_per_pool; 5621 netdev_dbg(vdev, "pool %i:%i queues %i:%i\n", 5622 accel->pool, adapter->num_rx_pools, 5623 baseq, baseq + adapter->num_rx_queues_per_pool); 5624 5625 accel->rx_base_queue = baseq; 5626 accel->tx_base_queue = baseq; 5627 5628 /* record configuration for macvlan interface in vdev */ 5629 for (i = 0; i < num_tc; i++) 5630 netdev_bind_sb_channel_queue(adapter->netdev, vdev, 5631 i, rss_i, baseq + (rss_i * i)); 5632 5633 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5634 adapter->rx_ring[baseq + i]->netdev = vdev; 5635 5636 /* Guarantee all rings are updated before we update the 5637 * MAC address filter. 5638 */ 5639 wmb(); 5640 5641 /* ixgbe_add_mac_filter will return an index if it succeeds, so we 5642 * need to only treat it as an error value if it is negative. 5643 */ 5644 err = ixgbe_add_mac_filter(adapter, vdev->dev_addr, 5645 VMDQ_P(accel->pool)); 5646 if (err >= 0) 5647 return 0; 5648 5649 /* if we cannot add the MAC rule then disable the offload */ 5650 macvlan_release_l2fw_offload(vdev); 5651 5652 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5653 adapter->rx_ring[baseq + i]->netdev = NULL; 5654 5655 netdev_err(vdev, "L2FW offload disabled due to L2 filter error\n"); 5656 5657 /* unbind the queues and drop the subordinate channel config */ 5658 netdev_unbind_sb_channel(adapter->netdev, vdev); 5659 netdev_set_sb_channel(vdev, 0); 5660 5661 clear_bit(accel->pool, adapter->fwd_bitmask); 5662 kfree(accel); 5663 5664 return err; 5665 } 5666 5667 static int ixgbe_macvlan_up(struct net_device *vdev, 5668 struct netdev_nested_priv *priv) 5669 { 5670 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data; 5671 struct ixgbe_fwd_adapter *accel; 5672 5673 if (!netif_is_macvlan(vdev)) 5674 return 0; 5675 5676 accel = macvlan_accel_priv(vdev); 5677 if (!accel) 5678 return 0; 5679 5680 ixgbe_fwd_ring_up(adapter, accel); 5681 5682 return 0; 5683 } 5684 5685 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 5686 { 5687 struct netdev_nested_priv priv = { 5688 .data = (void *)adapter, 5689 }; 5690 5691 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5692 ixgbe_macvlan_up, &priv); 5693 } 5694 5695 static void ixgbe_configure(struct ixgbe_adapter *adapter) 5696 { 5697 struct ixgbe_hw *hw = &adapter->hw; 5698 5699 ixgbe_configure_pb(adapter); 5700 #ifdef CONFIG_IXGBE_DCB 5701 ixgbe_configure_dcb(adapter); 5702 #endif 5703 /* 5704 * We must restore virtualization before VLANs or else 5705 * the VLVF registers will not be populated 5706 */ 5707 ixgbe_configure_virtualization(adapter); 5708 5709 ixgbe_set_rx_mode(adapter->netdev); 5710 ixgbe_restore_vlan(adapter); 5711 ixgbe_ipsec_restore(adapter); 5712 5713 switch (hw->mac.type) { 5714 case ixgbe_mac_82599EB: 5715 case ixgbe_mac_X540: 5716 hw->mac.ops.disable_rx_buff(hw); 5717 break; 5718 default: 5719 break; 5720 } 5721 5722 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 5723 ixgbe_init_fdir_signature_82599(&adapter->hw, 5724 adapter->fdir_pballoc); 5725 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 5726 ixgbe_init_fdir_perfect_82599(&adapter->hw, 5727 adapter->fdir_pballoc); 5728 ixgbe_fdir_filter_restore(adapter); 5729 } 5730 5731 switch (hw->mac.type) { 5732 case ixgbe_mac_82599EB: 5733 case ixgbe_mac_X540: 5734 hw->mac.ops.enable_rx_buff(hw); 5735 break; 5736 default: 5737 break; 5738 } 5739 5740 #ifdef CONFIG_IXGBE_DCA 5741 /* configure DCA */ 5742 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) 5743 ixgbe_setup_dca(adapter); 5744 #endif /* CONFIG_IXGBE_DCA */ 5745 5746 #ifdef IXGBE_FCOE 5747 /* configure FCoE L2 filters, redirection table, and Rx control */ 5748 ixgbe_configure_fcoe(adapter); 5749 5750 #endif /* IXGBE_FCOE */ 5751 ixgbe_configure_tx(adapter); 5752 ixgbe_configure_rx(adapter); 5753 ixgbe_configure_dfwd(adapter); 5754 } 5755 5756 /** 5757 * ixgbe_enable_link_status_events - enable link status events 5758 * @adapter: pointer to the adapter structure 5759 * @mask: event mask to be set 5760 * 5761 * Enables link status events by invoking ixgbe_configure_lse() 5762 * 5763 * Return: the exit code of the operation. 5764 */ 5765 static int ixgbe_enable_link_status_events(struct ixgbe_adapter *adapter, 5766 u16 mask) 5767 { 5768 int err; 5769 5770 err = ixgbe_configure_lse(&adapter->hw, true, mask); 5771 if (err) 5772 return err; 5773 5774 adapter->lse_mask = mask; 5775 return 0; 5776 } 5777 5778 /** 5779 * ixgbe_disable_link_status_events - disable link status events 5780 * @adapter: pointer to the adapter structure 5781 * 5782 * Disables link status events by invoking ixgbe_configure_lse() 5783 * 5784 * Return: the exit code of the operation. 5785 */ 5786 static int ixgbe_disable_link_status_events(struct ixgbe_adapter *adapter) 5787 { 5788 int err; 5789 5790 err = ixgbe_configure_lse(&adapter->hw, false, adapter->lse_mask); 5791 if (err) 5792 return err; 5793 5794 adapter->lse_mask = 0; 5795 return 0; 5796 } 5797 5798 /** 5799 * ixgbe_sfp_link_config - set up SFP+ link 5800 * @adapter: pointer to private adapter struct 5801 **/ 5802 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 5803 { 5804 /* 5805 * We are assuming the worst case scenario here, and that 5806 * is that an SFP was inserted/removed after the reset 5807 * but before SFP detection was enabled. As such the best 5808 * solution is to just start searching as soon as we start 5809 */ 5810 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 5811 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 5812 5813 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 5814 adapter->sfp_poll_time = 0; 5815 } 5816 5817 /** 5818 * ixgbe_non_sfp_link_config - set up non-SFP+ link 5819 * @hw: pointer to private hardware struct 5820 * 5821 * Configure non-SFP link. 5822 * 5823 * Return: 0 on success, negative on failure 5824 **/ 5825 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 5826 { 5827 struct ixgbe_adapter *adapter = container_of(hw, struct ixgbe_adapter, 5828 hw); 5829 u16 mask = ~((u16)(IXGBE_ACI_LINK_EVENT_UPDOWN | 5830 IXGBE_ACI_LINK_EVENT_MEDIA_NA | 5831 IXGBE_ACI_LINK_EVENT_MODULE_QUAL_FAIL | 5832 IXGBE_ACI_LINK_EVENT_PHY_FW_LOAD_FAIL)); 5833 bool autoneg, link_up = false; 5834 int ret = -EIO; 5835 u32 speed; 5836 5837 if (hw->mac.ops.check_link) 5838 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 5839 5840 if (ret) 5841 return ret; 5842 5843 speed = hw->phy.autoneg_advertised; 5844 if (!speed && hw->mac.ops.get_link_capabilities) { 5845 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 5846 &autoneg); 5847 /* remove NBASE-T speeds from default autonegotiation 5848 * to accommodate broken network switches in the field 5849 * which cannot cope with advertised NBASE-T speeds 5850 */ 5851 speed &= ~(IXGBE_LINK_SPEED_5GB_FULL | 5852 IXGBE_LINK_SPEED_2_5GB_FULL); 5853 } 5854 5855 if (ret) 5856 return ret; 5857 5858 if (hw->mac.ops.setup_link) { 5859 if (adapter->hw.mac.type == ixgbe_mac_e610) { 5860 ret = ixgbe_enable_link_status_events(adapter, mask); 5861 if (ret) 5862 return ret; 5863 } 5864 ret = hw->mac.ops.setup_link(hw, speed, link_up); 5865 } 5866 5867 return ret; 5868 } 5869 5870 /** 5871 * ixgbe_check_media_subtask - check for media 5872 * @adapter: pointer to adapter structure 5873 * 5874 * If media is available then initialize PHY user configuration. Configure the 5875 * PHY if the interface is up. 5876 */ 5877 static void ixgbe_check_media_subtask(struct ixgbe_adapter *adapter) 5878 { 5879 struct ixgbe_hw *hw = &adapter->hw; 5880 5881 /* No need to check for media if it's already present */ 5882 if (!(adapter->flags2 & IXGBE_FLAG2_NO_MEDIA)) 5883 return; 5884 5885 /* Refresh link info and check if media is present */ 5886 if (ixgbe_update_link_info(hw)) 5887 return; 5888 5889 ixgbe_check_link_cfg_err(adapter, hw->link.link_info.link_cfg_err); 5890 5891 if (hw->link.link_info.link_info & IXGBE_ACI_MEDIA_AVAILABLE) { 5892 /* PHY settings are reset on media insertion, reconfigure 5893 * PHY to preserve settings. 5894 */ 5895 if (!(ixgbe_non_sfp_link_config(&adapter->hw))) 5896 adapter->flags2 &= ~IXGBE_FLAG2_NO_MEDIA; 5897 5898 /* A Link Status Event will be generated; the event handler 5899 * will complete bringing the interface up 5900 */ 5901 } 5902 } 5903 5904 /** 5905 * ixgbe_clear_vf_stats_counters - Clear out VF stats after reset 5906 * @adapter: board private structure 5907 * 5908 * On a reset we need to clear out the VF stats or accounting gets 5909 * messed up because they're not clear on read. 5910 **/ 5911 static void ixgbe_clear_vf_stats_counters(struct ixgbe_adapter *adapter) 5912 { 5913 struct ixgbe_hw *hw = &adapter->hw; 5914 int i; 5915 5916 for (i = 0; i < adapter->num_vfs; i++) { 5917 adapter->vfinfo[i].last_vfstats.gprc = 5918 IXGBE_READ_REG(hw, IXGBE_PVFGPRC(i)); 5919 adapter->vfinfo[i].saved_rst_vfstats.gprc += 5920 adapter->vfinfo[i].vfstats.gprc; 5921 adapter->vfinfo[i].vfstats.gprc = 0; 5922 adapter->vfinfo[i].last_vfstats.gptc = 5923 IXGBE_READ_REG(hw, IXGBE_PVFGPTC(i)); 5924 adapter->vfinfo[i].saved_rst_vfstats.gptc += 5925 adapter->vfinfo[i].vfstats.gptc; 5926 adapter->vfinfo[i].vfstats.gptc = 0; 5927 adapter->vfinfo[i].last_vfstats.gorc = 5928 IXGBE_READ_REG(hw, IXGBE_PVFGORC_LSB(i)); 5929 adapter->vfinfo[i].saved_rst_vfstats.gorc += 5930 adapter->vfinfo[i].vfstats.gorc; 5931 adapter->vfinfo[i].vfstats.gorc = 0; 5932 adapter->vfinfo[i].last_vfstats.gotc = 5933 IXGBE_READ_REG(hw, IXGBE_PVFGOTC_LSB(i)); 5934 adapter->vfinfo[i].saved_rst_vfstats.gotc += 5935 adapter->vfinfo[i].vfstats.gotc; 5936 adapter->vfinfo[i].vfstats.gotc = 0; 5937 adapter->vfinfo[i].last_vfstats.mprc = 5938 IXGBE_READ_REG(hw, IXGBE_PVFMPRC(i)); 5939 adapter->vfinfo[i].saved_rst_vfstats.mprc += 5940 adapter->vfinfo[i].vfstats.mprc; 5941 adapter->vfinfo[i].vfstats.mprc = 0; 5942 } 5943 } 5944 5945 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 5946 { 5947 struct ixgbe_hw *hw = &adapter->hw; 5948 u32 gpie = 0; 5949 5950 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 5951 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5952 IXGBE_GPIE_OCD; 5953 gpie |= IXGBE_GPIE_EIAME; 5954 /* 5955 * use EIAM to auto-mask when MSI-X interrupt is asserted 5956 * this saves a register write for every interrupt 5957 */ 5958 switch (hw->mac.type) { 5959 case ixgbe_mac_82598EB: 5960 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5961 break; 5962 case ixgbe_mac_82599EB: 5963 case ixgbe_mac_X540: 5964 case ixgbe_mac_X550: 5965 case ixgbe_mac_X550EM_x: 5966 case ixgbe_mac_x550em_a: 5967 case ixgbe_mac_e610: 5968 default: 5969 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5970 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5971 break; 5972 } 5973 } else { 5974 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 5975 * specifically only auto mask tx and rx interrupts */ 5976 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5977 } 5978 5979 /* XXX: to interrupt immediately for EICS writes, enable this */ 5980 /* gpie |= IXGBE_GPIE_EIMEN; */ 5981 5982 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 5983 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 5984 5985 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 5986 case IXGBE_82599_VMDQ_8Q_MASK: 5987 gpie |= IXGBE_GPIE_VTMODE_16; 5988 break; 5989 case IXGBE_82599_VMDQ_4Q_MASK: 5990 gpie |= IXGBE_GPIE_VTMODE_32; 5991 break; 5992 default: 5993 gpie |= IXGBE_GPIE_VTMODE_64; 5994 break; 5995 } 5996 } 5997 5998 /* Enable Thermal over heat sensor interrupt */ 5999 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 6000 switch (adapter->hw.mac.type) { 6001 case ixgbe_mac_82599EB: 6002 gpie |= IXGBE_SDP0_GPIEN_8259X; 6003 break; 6004 default: 6005 break; 6006 } 6007 } 6008 6009 /* Enable fan failure interrupt */ 6010 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 6011 gpie |= IXGBE_SDP1_GPIEN(hw); 6012 6013 switch (hw->mac.type) { 6014 case ixgbe_mac_82599EB: 6015 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; 6016 break; 6017 case ixgbe_mac_X550EM_x: 6018 case ixgbe_mac_x550em_a: 6019 gpie |= IXGBE_SDP0_GPIEN_X540; 6020 break; 6021 default: 6022 break; 6023 } 6024 6025 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 6026 } 6027 6028 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 6029 { 6030 struct ixgbe_hw *hw = &adapter->hw; 6031 int err; 6032 u32 ctrl_ext; 6033 6034 ixgbe_get_hw_control(adapter); 6035 ixgbe_setup_gpie(adapter); 6036 6037 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 6038 ixgbe_configure_msix(adapter); 6039 else 6040 ixgbe_configure_msi_and_legacy(adapter); 6041 6042 /* enable the optics for 82599 SFP+ fiber */ 6043 if (hw->mac.ops.enable_tx_laser) 6044 hw->mac.ops.enable_tx_laser(hw); 6045 6046 if (hw->phy.ops.set_phy_power) 6047 hw->phy.ops.set_phy_power(hw, true); 6048 6049 smp_mb__before_atomic(); 6050 clear_bit(__IXGBE_DOWN, &adapter->state); 6051 ixgbe_napi_enable_all(adapter); 6052 6053 if (ixgbe_is_sfp(hw)) { 6054 ixgbe_sfp_link_config(adapter); 6055 } else { 6056 err = ixgbe_non_sfp_link_config(hw); 6057 if (err) 6058 e_err(probe, "link_config FAILED %d\n", err); 6059 } 6060 6061 /* clear any pending interrupts, may auto mask */ 6062 IXGBE_READ_REG(hw, IXGBE_EICR); 6063 ixgbe_irq_enable(adapter, true, true); 6064 6065 /* 6066 * If this adapter has a fan, check to see if we had a failure 6067 * before we enabled the interrupt. 6068 */ 6069 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 6070 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 6071 if (esdp & IXGBE_ESDP_SDP1) 6072 e_crit(drv, "Fan has stopped, replace the adapter\n"); 6073 } 6074 6075 /* bring the link up in the watchdog, this could race with our first 6076 * link up interrupt but shouldn't be a problem */ 6077 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 6078 adapter->link_check_timeout = jiffies; 6079 mod_timer(&adapter->service_timer, jiffies); 6080 6081 ixgbe_clear_vf_stats_counters(adapter); 6082 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 6083 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 6084 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 6085 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 6086 6087 /* update setting rx tx for all active vfs */ 6088 ixgbe_set_all_vfs(adapter); 6089 } 6090 6091 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 6092 { 6093 /* put off any impending NetWatchDogTimeout */ 6094 netif_trans_update(adapter->netdev); 6095 6096 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 6097 usleep_range(1000, 2000); 6098 if (adapter->hw.phy.type == ixgbe_phy_fw) 6099 ixgbe_watchdog_link_is_down(adapter); 6100 ixgbe_down(adapter); 6101 /* 6102 * If SR-IOV enabled then wait a bit before bringing the adapter 6103 * back up to give the VFs time to respond to the reset. The 6104 * two second wait is based upon the watchdog timer cycle in 6105 * the VF driver. 6106 */ 6107 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 6108 msleep(2000); 6109 ixgbe_up(adapter); 6110 clear_bit(__IXGBE_RESETTING, &adapter->state); 6111 } 6112 6113 void ixgbe_up(struct ixgbe_adapter *adapter) 6114 { 6115 /* hardware has been reset, we need to reload some things */ 6116 ixgbe_configure(adapter); 6117 6118 ixgbe_up_complete(adapter); 6119 } 6120 6121 static unsigned long ixgbe_get_completion_timeout(struct ixgbe_adapter *adapter) 6122 { 6123 u16 devctl2; 6124 6125 pcie_capability_read_word(adapter->pdev, PCI_EXP_DEVCTL2, &devctl2); 6126 6127 switch (devctl2 & IXGBE_PCIDEVCTRL2_TIMEO_MASK) { 6128 case IXGBE_PCIDEVCTRL2_17_34s: 6129 case IXGBE_PCIDEVCTRL2_4_8s: 6130 /* For now we cap the upper limit on delay to 2 seconds 6131 * as we end up going up to 34 seconds of delay in worst 6132 * case timeout value. 6133 */ 6134 case IXGBE_PCIDEVCTRL2_1_2s: 6135 return 2000000ul; /* 2.0 s */ 6136 case IXGBE_PCIDEVCTRL2_260_520ms: 6137 return 520000ul; /* 520 ms */ 6138 case IXGBE_PCIDEVCTRL2_65_130ms: 6139 return 130000ul; /* 130 ms */ 6140 case IXGBE_PCIDEVCTRL2_16_32ms: 6141 return 32000ul; /* 32 ms */ 6142 case IXGBE_PCIDEVCTRL2_1_2ms: 6143 return 2000ul; /* 2 ms */ 6144 case IXGBE_PCIDEVCTRL2_50_100us: 6145 return 100ul; /* 100 us */ 6146 case IXGBE_PCIDEVCTRL2_16_32ms_def: 6147 return 32000ul; /* 32 ms */ 6148 default: 6149 break; 6150 } 6151 6152 /* We shouldn't need to hit this path, but just in case default as 6153 * though completion timeout is not supported and support 32ms. 6154 */ 6155 return 32000ul; 6156 } 6157 6158 void ixgbe_disable_rx(struct ixgbe_adapter *adapter) 6159 { 6160 unsigned long wait_delay, delay_interval; 6161 struct ixgbe_hw *hw = &adapter->hw; 6162 int i, wait_loop; 6163 u32 rxdctl; 6164 6165 /* disable receives */ 6166 hw->mac.ops.disable_rx(hw); 6167 6168 if (ixgbe_removed(hw->hw_addr)) 6169 return; 6170 6171 /* disable all enabled Rx queues */ 6172 for (i = 0; i < adapter->num_rx_queues; i++) { 6173 struct ixgbe_ring *ring = adapter->rx_ring[i]; 6174 u8 reg_idx = ring->reg_idx; 6175 6176 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 6177 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 6178 rxdctl |= IXGBE_RXDCTL_SWFLSH; 6179 6180 /* write value back with RXDCTL.ENABLE bit cleared */ 6181 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 6182 } 6183 6184 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 6185 if (hw->mac.type == ixgbe_mac_82598EB && 6186 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 6187 return; 6188 6189 /* Determine our minimum delay interval. We will increase this value 6190 * with each subsequent test. This way if the device returns quickly 6191 * we should spend as little time as possible waiting, however as 6192 * the time increases we will wait for larger periods of time. 6193 * 6194 * The trick here is that we increase the interval using the 6195 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 6196 * of that wait is that it totals up to 100x whatever interval we 6197 * choose. Since our minimum wait is 100us we can just divide the 6198 * total timeout by 100 to get our minimum delay interval. 6199 */ 6200 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 6201 6202 wait_loop = IXGBE_MAX_RX_DESC_POLL; 6203 wait_delay = delay_interval; 6204 6205 while (wait_loop--) { 6206 usleep_range(wait_delay, wait_delay + 10); 6207 wait_delay += delay_interval * 2; 6208 rxdctl = 0; 6209 6210 /* OR together the reading of all the active RXDCTL registers, 6211 * and then test the result. We need the disable to complete 6212 * before we start freeing the memory and invalidating the 6213 * DMA mappings. 6214 */ 6215 for (i = 0; i < adapter->num_rx_queues; i++) { 6216 struct ixgbe_ring *ring = adapter->rx_ring[i]; 6217 u8 reg_idx = ring->reg_idx; 6218 6219 rxdctl |= IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 6220 } 6221 6222 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 6223 return; 6224 } 6225 6226 e_err(drv, 6227 "RXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 6228 } 6229 6230 void ixgbe_disable_tx(struct ixgbe_adapter *adapter) 6231 { 6232 unsigned long wait_delay, delay_interval; 6233 struct ixgbe_hw *hw = &adapter->hw; 6234 int i, wait_loop; 6235 u32 txdctl; 6236 6237 if (ixgbe_removed(hw->hw_addr)) 6238 return; 6239 6240 /* disable all enabled Tx queues */ 6241 for (i = 0; i < adapter->num_tx_queues; i++) { 6242 struct ixgbe_ring *ring = adapter->tx_ring[i]; 6243 u8 reg_idx = ring->reg_idx; 6244 6245 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 6246 } 6247 6248 /* disable all enabled XDP Tx queues */ 6249 for (i = 0; i < adapter->num_xdp_queues; i++) { 6250 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 6251 u8 reg_idx = ring->reg_idx; 6252 6253 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 6254 } 6255 6256 /* If the link is not up there shouldn't be much in the way of 6257 * pending transactions. Those that are left will be flushed out 6258 * when the reset logic goes through the flush sequence to clean out 6259 * the pending Tx transactions. 6260 */ 6261 if (!(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 6262 goto dma_engine_disable; 6263 6264 /* Determine our minimum delay interval. We will increase this value 6265 * with each subsequent test. This way if the device returns quickly 6266 * we should spend as little time as possible waiting, however as 6267 * the time increases we will wait for larger periods of time. 6268 * 6269 * The trick here is that we increase the interval using the 6270 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 6271 * of that wait is that it totals up to 100x whatever interval we 6272 * choose. Since our minimum wait is 100us we can just divide the 6273 * total timeout by 100 to get our minimum delay interval. 6274 */ 6275 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 6276 6277 wait_loop = IXGBE_MAX_RX_DESC_POLL; 6278 wait_delay = delay_interval; 6279 6280 while (wait_loop--) { 6281 usleep_range(wait_delay, wait_delay + 10); 6282 wait_delay += delay_interval * 2; 6283 txdctl = 0; 6284 6285 /* OR together the reading of all the active TXDCTL registers, 6286 * and then test the result. We need the disable to complete 6287 * before we start freeing the memory and invalidating the 6288 * DMA mappings. 6289 */ 6290 for (i = 0; i < adapter->num_tx_queues; i++) { 6291 struct ixgbe_ring *ring = adapter->tx_ring[i]; 6292 u8 reg_idx = ring->reg_idx; 6293 6294 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 6295 } 6296 for (i = 0; i < adapter->num_xdp_queues; i++) { 6297 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 6298 u8 reg_idx = ring->reg_idx; 6299 6300 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 6301 } 6302 6303 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 6304 goto dma_engine_disable; 6305 } 6306 6307 e_err(drv, 6308 "TXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 6309 6310 dma_engine_disable: 6311 /* Disable the Tx DMA engine on 82599 and later MAC */ 6312 switch (hw->mac.type) { 6313 case ixgbe_mac_82599EB: 6314 case ixgbe_mac_X540: 6315 case ixgbe_mac_X550: 6316 case ixgbe_mac_X550EM_x: 6317 case ixgbe_mac_x550em_a: 6318 case ixgbe_mac_e610: 6319 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 6320 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 6321 ~IXGBE_DMATXCTL_TE)); 6322 fallthrough; 6323 default: 6324 break; 6325 } 6326 } 6327 6328 void ixgbe_reset(struct ixgbe_adapter *adapter) 6329 { 6330 struct ixgbe_hw *hw = &adapter->hw; 6331 struct net_device *netdev = adapter->netdev; 6332 int err; 6333 6334 if (ixgbe_removed(hw->hw_addr)) 6335 return; 6336 /* lock SFP init bit to prevent race conditions with the watchdog */ 6337 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 6338 usleep_range(1000, 2000); 6339 6340 /* clear all SFP and link config related flags while holding SFP_INIT */ 6341 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 6342 IXGBE_FLAG2_SFP_NEEDS_RESET); 6343 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 6344 6345 err = hw->mac.ops.init_hw(hw); 6346 switch (err) { 6347 case 0: 6348 case -ENOENT: 6349 case -EOPNOTSUPP: 6350 break; 6351 case -EALREADY: 6352 e_dev_err("primary disable timed out\n"); 6353 break; 6354 case -EACCES: 6355 /* We are running on a pre-production device, log a warning */ 6356 e_dev_warn("This device is a pre-production adapter/LOM. " 6357 "Please be aware there may be issues associated with " 6358 "your hardware. If you are experiencing problems " 6359 "please contact your Intel or hardware " 6360 "representative who provided you with this " 6361 "hardware.\n"); 6362 break; 6363 default: 6364 e_dev_err("Hardware Error: %d\n", err); 6365 } 6366 6367 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 6368 6369 /* flush entries out of MAC table */ 6370 ixgbe_flush_sw_mac_table(adapter); 6371 __dev_uc_unsync(netdev, NULL); 6372 6373 /* do not flush user set addresses */ 6374 ixgbe_mac_set_default_filter(adapter); 6375 6376 /* update SAN MAC vmdq pool selection */ 6377 if (hw->mac.san_mac_rar_index) 6378 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 6379 6380 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 6381 ixgbe_ptp_reset(adapter); 6382 6383 if (hw->phy.ops.set_phy_power) { 6384 if (!netif_running(adapter->netdev) && !adapter->wol) 6385 hw->phy.ops.set_phy_power(hw, false); 6386 else 6387 hw->phy.ops.set_phy_power(hw, true); 6388 } 6389 } 6390 6391 /** 6392 * ixgbe_clean_tx_ring - Free Tx Buffers 6393 * @tx_ring: ring to be cleaned 6394 **/ 6395 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 6396 { 6397 u16 i = tx_ring->next_to_clean; 6398 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 6399 6400 if (tx_ring->xsk_pool) { 6401 ixgbe_xsk_clean_tx_ring(tx_ring); 6402 goto out; 6403 } 6404 6405 while (i != tx_ring->next_to_use) { 6406 union ixgbe_adv_tx_desc *eop_desc, *tx_desc; 6407 6408 /* Free all the Tx ring sk_buffs */ 6409 if (ring_is_xdp(tx_ring)) 6410 xdp_return_frame(tx_buffer->xdpf); 6411 else 6412 dev_kfree_skb_any(tx_buffer->skb); 6413 6414 /* unmap skb header data */ 6415 dma_unmap_single(tx_ring->dev, 6416 dma_unmap_addr(tx_buffer, dma), 6417 dma_unmap_len(tx_buffer, len), 6418 DMA_TO_DEVICE); 6419 6420 /* check for eop_desc to determine the end of the packet */ 6421 eop_desc = tx_buffer->next_to_watch; 6422 tx_desc = IXGBE_TX_DESC(tx_ring, i); 6423 6424 /* unmap remaining buffers */ 6425 while (tx_desc != eop_desc) { 6426 tx_buffer++; 6427 tx_desc++; 6428 i++; 6429 if (unlikely(i == tx_ring->count)) { 6430 i = 0; 6431 tx_buffer = tx_ring->tx_buffer_info; 6432 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 6433 } 6434 6435 /* unmap any remaining paged data */ 6436 if (dma_unmap_len(tx_buffer, len)) 6437 dma_unmap_page(tx_ring->dev, 6438 dma_unmap_addr(tx_buffer, dma), 6439 dma_unmap_len(tx_buffer, len), 6440 DMA_TO_DEVICE); 6441 } 6442 6443 /* move us one more past the eop_desc for start of next pkt */ 6444 tx_buffer++; 6445 i++; 6446 if (unlikely(i == tx_ring->count)) { 6447 i = 0; 6448 tx_buffer = tx_ring->tx_buffer_info; 6449 } 6450 } 6451 6452 /* reset BQL for queue */ 6453 if (!ring_is_xdp(tx_ring)) 6454 netdev_tx_reset_queue(txring_txq(tx_ring)); 6455 6456 out: 6457 /* reset next_to_use and next_to_clean */ 6458 tx_ring->next_to_use = 0; 6459 tx_ring->next_to_clean = 0; 6460 } 6461 6462 /** 6463 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 6464 * @adapter: board private structure 6465 **/ 6466 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 6467 { 6468 int i; 6469 6470 for (i = 0; i < adapter->num_rx_queues; i++) 6471 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 6472 } 6473 6474 /** 6475 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 6476 * @adapter: board private structure 6477 **/ 6478 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 6479 { 6480 int i; 6481 6482 for (i = 0; i < adapter->num_tx_queues; i++) 6483 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 6484 for (i = 0; i < adapter->num_xdp_queues; i++) 6485 ixgbe_clean_tx_ring(adapter->xdp_ring[i]); 6486 } 6487 6488 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 6489 { 6490 struct hlist_node *node2; 6491 struct ixgbe_fdir_filter *filter; 6492 6493 spin_lock(&adapter->fdir_perfect_lock); 6494 6495 hlist_for_each_entry_safe(filter, node2, 6496 &adapter->fdir_filter_list, fdir_node) { 6497 hlist_del(&filter->fdir_node); 6498 kfree(filter); 6499 } 6500 adapter->fdir_filter_count = 0; 6501 6502 spin_unlock(&adapter->fdir_perfect_lock); 6503 } 6504 6505 void ixgbe_down(struct ixgbe_adapter *adapter) 6506 { 6507 struct net_device *netdev = adapter->netdev; 6508 struct ixgbe_hw *hw = &adapter->hw; 6509 int i; 6510 6511 /* signal that we are down to the interrupt handler */ 6512 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 6513 return; /* do nothing if already down */ 6514 6515 /* Shut off incoming Tx traffic */ 6516 netif_tx_stop_all_queues(netdev); 6517 6518 /* call carrier off first to avoid false dev_watchdog timeouts */ 6519 netif_carrier_off(netdev); 6520 netif_tx_disable(netdev); 6521 6522 /* Disable Rx */ 6523 ixgbe_disable_rx(adapter); 6524 6525 /* synchronize_rcu() needed for pending XDP buffers to drain */ 6526 if (adapter->xdp_ring[0]) 6527 synchronize_rcu(); 6528 6529 ixgbe_irq_disable(adapter); 6530 6531 ixgbe_napi_disable_all(adapter); 6532 6533 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 6534 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 6535 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 6536 6537 del_timer_sync(&adapter->service_timer); 6538 6539 if (adapter->num_vfs) { 6540 /* Clear EITR Select mapping */ 6541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 6542 6543 /* Mark all the VFs as inactive */ 6544 for (i = 0 ; i < adapter->num_vfs; i++) 6545 adapter->vfinfo[i].clear_to_send = false; 6546 6547 /* update setting rx tx for all active vfs */ 6548 ixgbe_set_all_vfs(adapter); 6549 } 6550 6551 /* disable transmits in the hardware now that interrupts are off */ 6552 ixgbe_disable_tx(adapter); 6553 6554 if (!pci_channel_offline(adapter->pdev)) 6555 ixgbe_reset(adapter); 6556 6557 /* power down the optics for 82599 SFP+ fiber */ 6558 if (hw->mac.ops.disable_tx_laser) 6559 hw->mac.ops.disable_tx_laser(hw); 6560 6561 ixgbe_clean_all_tx_rings(adapter); 6562 ixgbe_clean_all_rx_rings(adapter); 6563 if (adapter->hw.mac.type == ixgbe_mac_e610) 6564 ixgbe_disable_link_status_events(adapter); 6565 } 6566 6567 /** 6568 * ixgbe_set_eee_capable - helper function to determine EEE support on X550 6569 * @adapter: board private structure 6570 */ 6571 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter) 6572 { 6573 struct ixgbe_hw *hw = &adapter->hw; 6574 6575 switch (hw->device_id) { 6576 case IXGBE_DEV_ID_X550EM_A_1G_T: 6577 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6578 if (!hw->phy.eee_speeds_supported) 6579 break; 6580 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE; 6581 if (!hw->phy.eee_speeds_advertised) 6582 break; 6583 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 6584 break; 6585 default: 6586 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE; 6587 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 6588 break; 6589 } 6590 } 6591 6592 /** 6593 * ixgbe_tx_timeout - Respond to a Tx Hang 6594 * @netdev: network interface device structure 6595 * @txqueue: queue number that timed out 6596 **/ 6597 static void ixgbe_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6598 { 6599 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6600 6601 /* Do the reset outside of interrupt context */ 6602 ixgbe_tx_timeout_reset(adapter); 6603 } 6604 6605 #ifdef CONFIG_IXGBE_DCB 6606 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) 6607 { 6608 struct ixgbe_hw *hw = &adapter->hw; 6609 struct tc_configuration *tc; 6610 int j; 6611 6612 switch (hw->mac.type) { 6613 case ixgbe_mac_82598EB: 6614 case ixgbe_mac_82599EB: 6615 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 6616 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 6617 break; 6618 case ixgbe_mac_X540: 6619 case ixgbe_mac_X550: 6620 case ixgbe_mac_e610: 6621 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 6622 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 6623 break; 6624 case ixgbe_mac_X550EM_x: 6625 case ixgbe_mac_x550em_a: 6626 default: 6627 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; 6628 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; 6629 break; 6630 } 6631 6632 /* Configure DCB traffic classes */ 6633 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 6634 tc = &adapter->dcb_cfg.tc_config[j]; 6635 tc->path[DCB_TX_CONFIG].bwg_id = 0; 6636 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 6637 tc->path[DCB_RX_CONFIG].bwg_id = 0; 6638 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 6639 tc->dcb_pfc = pfc_disabled; 6640 } 6641 6642 /* Initialize default user to priority mapping, UPx->TC0 */ 6643 tc = &adapter->dcb_cfg.tc_config[0]; 6644 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 6645 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 6646 6647 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 6648 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 6649 adapter->dcb_cfg.pfc_mode_enable = false; 6650 adapter->dcb_set_bitmap = 0x00; 6651 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 6652 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 6653 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 6654 sizeof(adapter->temp_dcb_cfg)); 6655 } 6656 #endif 6657 6658 /** 6659 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 6660 * @adapter: board private structure to initialize 6661 * @ii: pointer to ixgbe_info for device 6662 * 6663 * ixgbe_sw_init initializes the Adapter private data structure. 6664 * Fields are initialized based on PCI device information and 6665 * OS network device settings (MTU size). 6666 **/ 6667 static int ixgbe_sw_init(struct ixgbe_adapter *adapter, 6668 const struct ixgbe_info *ii) 6669 { 6670 struct ixgbe_hw *hw = &adapter->hw; 6671 struct pci_dev *pdev = adapter->pdev; 6672 unsigned int rss, fdir; 6673 u32 fwsm; 6674 int i; 6675 6676 /* PCI config space info */ 6677 6678 hw->vendor_id = pdev->vendor; 6679 hw->device_id = pdev->device; 6680 hw->revision_id = pdev->revision; 6681 hw->subsystem_vendor_id = pdev->subsystem_vendor; 6682 hw->subsystem_device_id = pdev->subsystem_device; 6683 6684 hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME; 6685 6686 /* get_invariants needs the device IDs */ 6687 ii->get_invariants(hw); 6688 6689 /* Set common capability flags and settings */ 6690 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 6691 adapter->ring_feature[RING_F_RSS].limit = rss; 6692 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 6693 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 6694 adapter->atr_sample_rate = 20; 6695 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 6696 adapter->ring_feature[RING_F_FDIR].limit = fdir; 6697 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 6698 adapter->ring_feature[RING_F_VMDQ].limit = 1; 6699 #ifdef CONFIG_IXGBE_DCA 6700 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 6701 #endif 6702 #ifdef CONFIG_IXGBE_DCB 6703 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; 6704 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 6705 #endif 6706 #ifdef IXGBE_FCOE 6707 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 6708 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6709 #ifdef CONFIG_IXGBE_DCB 6710 /* Default traffic class to use for FCoE */ 6711 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 6712 #endif /* CONFIG_IXGBE_DCB */ 6713 #endif /* IXGBE_FCOE */ 6714 6715 /* initialize static ixgbe jump table entries */ 6716 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]), 6717 GFP_KERNEL); 6718 if (!adapter->jump_tables[0]) 6719 return -ENOMEM; 6720 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; 6721 6722 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) 6723 adapter->jump_tables[i] = NULL; 6724 6725 adapter->mac_table = kcalloc(hw->mac.num_rar_entries, 6726 sizeof(struct ixgbe_mac_addr), 6727 GFP_KERNEL); 6728 if (!adapter->mac_table) 6729 return -ENOMEM; 6730 6731 if (ixgbe_init_rss_key(adapter)) 6732 return -ENOMEM; 6733 6734 adapter->af_xdp_zc_qps = bitmap_zalloc(IXGBE_MAX_XDP_QS, GFP_KERNEL); 6735 if (!adapter->af_xdp_zc_qps) 6736 return -ENOMEM; 6737 6738 /* Set MAC specific capability flags and exceptions */ 6739 switch (hw->mac.type) { 6740 case ixgbe_mac_82598EB: 6741 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 6742 6743 if (hw->device_id == IXGBE_DEV_ID_82598AT) 6744 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 6745 6746 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 6747 adapter->ring_feature[RING_F_FDIR].limit = 0; 6748 adapter->atr_sample_rate = 0; 6749 adapter->fdir_pballoc = 0; 6750 #ifdef IXGBE_FCOE 6751 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6752 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6753 #ifdef CONFIG_IXGBE_DCB 6754 adapter->fcoe.up = 0; 6755 #endif /* IXGBE_DCB */ 6756 #endif /* IXGBE_FCOE */ 6757 break; 6758 case ixgbe_mac_82599EB: 6759 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 6760 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6761 break; 6762 case ixgbe_mac_X540: 6763 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 6764 if (fwsm & IXGBE_FWSM_TS_ENABLED) 6765 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6766 break; 6767 case ixgbe_mac_x550em_a: 6768 switch (hw->device_id) { 6769 case IXGBE_DEV_ID_X550EM_A_1G_T: 6770 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6771 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6772 break; 6773 default: 6774 break; 6775 } 6776 fallthrough; 6777 case ixgbe_mac_X550EM_x: 6778 #ifdef CONFIG_IXGBE_DCB 6779 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; 6780 #endif 6781 #ifdef IXGBE_FCOE 6782 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6783 #ifdef CONFIG_IXGBE_DCB 6784 adapter->fcoe.up = 0; 6785 #endif /* IXGBE_DCB */ 6786 #endif /* IXGBE_FCOE */ 6787 fallthrough; 6788 case ixgbe_mac_X550: 6789 if (hw->mac.type == ixgbe_mac_X550) 6790 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6791 #ifdef CONFIG_IXGBE_DCA 6792 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 6793 #endif 6794 break; 6795 default: 6796 break; 6797 } 6798 6799 #ifdef IXGBE_FCOE 6800 /* FCoE support exists, always init the FCoE lock */ 6801 spin_lock_init(&adapter->fcoe.lock); 6802 6803 #endif 6804 /* n-tuple support exists, always init our spinlock */ 6805 spin_lock_init(&adapter->fdir_perfect_lock); 6806 6807 /* init spinlock to avoid concurrency of VF resources */ 6808 spin_lock_init(&adapter->vfs_lock); 6809 6810 #ifdef CONFIG_IXGBE_DCB 6811 ixgbe_init_dcb(adapter); 6812 #endif 6813 ixgbe_init_ipsec_offload(adapter); 6814 6815 /* default flow control settings */ 6816 hw->fc.requested_mode = ixgbe_fc_full; 6817 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 6818 ixgbe_pbthresh_setup(adapter); 6819 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 6820 hw->fc.send_xon = true; 6821 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 6822 6823 #ifdef CONFIG_PCI_IOV 6824 if (max_vfs > 0) 6825 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 6826 6827 /* assign number of SR-IOV VFs */ 6828 if (hw->mac.type != ixgbe_mac_82598EB) { 6829 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 6830 max_vfs = 0; 6831 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 6832 } 6833 } 6834 #endif /* CONFIG_PCI_IOV */ 6835 6836 /* enable itr by default in dynamic mode */ 6837 adapter->rx_itr_setting = 1; 6838 adapter->tx_itr_setting = 1; 6839 6840 /* set default ring sizes */ 6841 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 6842 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 6843 6844 /* set default work limits */ 6845 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 6846 6847 /* initialize eeprom parameters */ 6848 if (ixgbe_init_eeprom_params_generic(hw)) { 6849 e_dev_err("EEPROM initialization failed\n"); 6850 return -EIO; 6851 } 6852 6853 /* PF holds first pool slot */ 6854 set_bit(0, adapter->fwd_bitmask); 6855 set_bit(__IXGBE_DOWN, &adapter->state); 6856 6857 /* enable locking for XDP_TX if we have more CPUs than queues */ 6858 if (nr_cpu_ids > IXGBE_MAX_XDP_QS) 6859 static_branch_enable(&ixgbe_xdp_locking_key); 6860 6861 return 0; 6862 } 6863 6864 /** 6865 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 6866 * @tx_ring: tx descriptor ring (for a specific queue) to setup 6867 * 6868 * Return 0 on success, negative on failure 6869 **/ 6870 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 6871 { 6872 struct device *dev = tx_ring->dev; 6873 int orig_node = dev_to_node(dev); 6874 int ring_node = NUMA_NO_NODE; 6875 int size; 6876 6877 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 6878 6879 if (tx_ring->q_vector) 6880 ring_node = tx_ring->q_vector->numa_node; 6881 6882 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node); 6883 if (!tx_ring->tx_buffer_info) 6884 tx_ring->tx_buffer_info = vmalloc(size); 6885 if (!tx_ring->tx_buffer_info) 6886 goto err; 6887 6888 /* round up to nearest 4K */ 6889 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 6890 tx_ring->size = ALIGN(tx_ring->size, 4096); 6891 6892 set_dev_node(dev, ring_node); 6893 tx_ring->desc = dma_alloc_coherent(dev, 6894 tx_ring->size, 6895 &tx_ring->dma, 6896 GFP_KERNEL); 6897 set_dev_node(dev, orig_node); 6898 if (!tx_ring->desc) 6899 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 6900 &tx_ring->dma, GFP_KERNEL); 6901 if (!tx_ring->desc) 6902 goto err; 6903 6904 tx_ring->next_to_use = 0; 6905 tx_ring->next_to_clean = 0; 6906 return 0; 6907 6908 err: 6909 vfree(tx_ring->tx_buffer_info); 6910 tx_ring->tx_buffer_info = NULL; 6911 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 6912 return -ENOMEM; 6913 } 6914 6915 /** 6916 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 6917 * @adapter: board private structure 6918 * 6919 * If this function returns with an error, then it's possible one or 6920 * more of the rings is populated (while the rest are not). It is the 6921 * callers duty to clean those orphaned rings. 6922 * 6923 * Return 0 on success, negative on failure 6924 **/ 6925 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 6926 { 6927 int i, j = 0, err = 0; 6928 6929 for (i = 0; i < adapter->num_tx_queues; i++) { 6930 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 6931 if (!err) 6932 continue; 6933 6934 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 6935 goto err_setup_tx; 6936 } 6937 for (j = 0; j < adapter->num_xdp_queues; j++) { 6938 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]); 6939 if (!err) 6940 continue; 6941 6942 e_err(probe, "Allocation for Tx Queue %u failed\n", j); 6943 goto err_setup_tx; 6944 } 6945 6946 return 0; 6947 err_setup_tx: 6948 /* rewind the index freeing the rings as we go */ 6949 while (j--) 6950 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 6951 while (i--) 6952 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6953 return err; 6954 } 6955 6956 static int ixgbe_rx_napi_id(struct ixgbe_ring *rx_ring) 6957 { 6958 struct ixgbe_q_vector *q_vector = rx_ring->q_vector; 6959 6960 return q_vector ? q_vector->napi.napi_id : 0; 6961 } 6962 6963 /** 6964 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 6965 * @adapter: pointer to ixgbe_adapter 6966 * @rx_ring: rx descriptor ring (for a specific queue) to setup 6967 * 6968 * Returns 0 on success, negative on failure 6969 **/ 6970 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, 6971 struct ixgbe_ring *rx_ring) 6972 { 6973 struct device *dev = rx_ring->dev; 6974 int orig_node = dev_to_node(dev); 6975 int ring_node = NUMA_NO_NODE; 6976 int size; 6977 6978 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 6979 6980 if (rx_ring->q_vector) 6981 ring_node = rx_ring->q_vector->numa_node; 6982 6983 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node); 6984 if (!rx_ring->rx_buffer_info) 6985 rx_ring->rx_buffer_info = vmalloc(size); 6986 if (!rx_ring->rx_buffer_info) 6987 goto err; 6988 6989 /* Round up to nearest 4K */ 6990 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 6991 rx_ring->size = ALIGN(rx_ring->size, 4096); 6992 6993 set_dev_node(dev, ring_node); 6994 rx_ring->desc = dma_alloc_coherent(dev, 6995 rx_ring->size, 6996 &rx_ring->dma, 6997 GFP_KERNEL); 6998 set_dev_node(dev, orig_node); 6999 if (!rx_ring->desc) 7000 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 7001 &rx_ring->dma, GFP_KERNEL); 7002 if (!rx_ring->desc) 7003 goto err; 7004 7005 rx_ring->next_to_clean = 0; 7006 rx_ring->next_to_use = 0; 7007 7008 /* XDP RX-queue info */ 7009 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev, 7010 rx_ring->queue_index, ixgbe_rx_napi_id(rx_ring)) < 0) 7011 goto err; 7012 7013 WRITE_ONCE(rx_ring->xdp_prog, adapter->xdp_prog); 7014 7015 return 0; 7016 err: 7017 vfree(rx_ring->rx_buffer_info); 7018 rx_ring->rx_buffer_info = NULL; 7019 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 7020 return -ENOMEM; 7021 } 7022 7023 /** 7024 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 7025 * @adapter: board private structure 7026 * 7027 * If this function returns with an error, then it's possible one or 7028 * more of the rings is populated (while the rest are not). It is the 7029 * callers duty to clean those orphaned rings. 7030 * 7031 * Return 0 on success, negative on failure 7032 **/ 7033 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 7034 { 7035 int i, err = 0; 7036 7037 for (i = 0; i < adapter->num_rx_queues; i++) { 7038 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); 7039 if (!err) 7040 continue; 7041 7042 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 7043 goto err_setup_rx; 7044 } 7045 7046 #ifdef IXGBE_FCOE 7047 err = ixgbe_setup_fcoe_ddp_resources(adapter); 7048 if (!err) 7049 #endif 7050 return 0; 7051 err_setup_rx: 7052 /* rewind the index freeing the rings as we go */ 7053 while (i--) 7054 ixgbe_free_rx_resources(adapter->rx_ring[i]); 7055 return err; 7056 } 7057 7058 /** 7059 * ixgbe_free_tx_resources - Free Tx Resources per Queue 7060 * @tx_ring: Tx descriptor ring for a specific queue 7061 * 7062 * Free all transmit software resources 7063 **/ 7064 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 7065 { 7066 ixgbe_clean_tx_ring(tx_ring); 7067 7068 vfree(tx_ring->tx_buffer_info); 7069 tx_ring->tx_buffer_info = NULL; 7070 7071 /* if not set, then don't free */ 7072 if (!tx_ring->desc) 7073 return; 7074 7075 dma_free_coherent(tx_ring->dev, tx_ring->size, 7076 tx_ring->desc, tx_ring->dma); 7077 7078 tx_ring->desc = NULL; 7079 } 7080 7081 /** 7082 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 7083 * @adapter: board private structure 7084 * 7085 * Free all transmit software resources 7086 **/ 7087 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 7088 { 7089 int i; 7090 7091 for (i = 0; i < adapter->num_tx_queues; i++) 7092 if (adapter->tx_ring[i]->desc) 7093 ixgbe_free_tx_resources(adapter->tx_ring[i]); 7094 for (i = 0; i < adapter->num_xdp_queues; i++) 7095 if (adapter->xdp_ring[i]->desc) 7096 ixgbe_free_tx_resources(adapter->xdp_ring[i]); 7097 } 7098 7099 /** 7100 * ixgbe_free_rx_resources - Free Rx Resources 7101 * @rx_ring: ring to clean the resources from 7102 * 7103 * Free all receive software resources 7104 **/ 7105 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 7106 { 7107 ixgbe_clean_rx_ring(rx_ring); 7108 7109 rx_ring->xdp_prog = NULL; 7110 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 7111 vfree(rx_ring->rx_buffer_info); 7112 rx_ring->rx_buffer_info = NULL; 7113 7114 /* if not set, then don't free */ 7115 if (!rx_ring->desc) 7116 return; 7117 7118 dma_free_coherent(rx_ring->dev, rx_ring->size, 7119 rx_ring->desc, rx_ring->dma); 7120 7121 rx_ring->desc = NULL; 7122 } 7123 7124 /** 7125 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 7126 * @adapter: board private structure 7127 * 7128 * Free all receive software resources 7129 **/ 7130 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 7131 { 7132 int i; 7133 7134 #ifdef IXGBE_FCOE 7135 ixgbe_free_fcoe_ddp_resources(adapter); 7136 7137 #endif 7138 for (i = 0; i < adapter->num_rx_queues; i++) 7139 if (adapter->rx_ring[i]->desc) 7140 ixgbe_free_rx_resources(adapter->rx_ring[i]); 7141 } 7142 7143 /** 7144 * ixgbe_max_xdp_frame_size - returns the maximum allowed frame size for XDP 7145 * @adapter: device handle, pointer to adapter 7146 */ 7147 static int ixgbe_max_xdp_frame_size(struct ixgbe_adapter *adapter) 7148 { 7149 if (PAGE_SIZE >= 8192 || adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 7150 return IXGBE_RXBUFFER_2K; 7151 else 7152 return IXGBE_RXBUFFER_3K; 7153 } 7154 7155 /** 7156 * ixgbe_change_mtu - Change the Maximum Transfer Unit 7157 * @netdev: network interface device structure 7158 * @new_mtu: new value for maximum frame size 7159 * 7160 * Returns 0 on success, negative on failure 7161 **/ 7162 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 7163 { 7164 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7165 7166 if (ixgbe_enabled_xdp_adapter(adapter)) { 7167 int new_frame_size = new_mtu + IXGBE_PKT_HDR_PAD; 7168 7169 if (new_frame_size > ixgbe_max_xdp_frame_size(adapter)) { 7170 e_warn(probe, "Requested MTU size is not supported with XDP\n"); 7171 return -EINVAL; 7172 } 7173 } 7174 7175 /* 7176 * For 82599EB we cannot allow legacy VFs to enable their receive 7177 * paths when MTU greater than 1500 is configured. So display a 7178 * warning that legacy VFs will be disabled. 7179 */ 7180 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 7181 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 7182 (new_mtu > ETH_DATA_LEN)) 7183 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 7184 7185 netdev_dbg(netdev, "changing MTU from %d to %d\n", 7186 netdev->mtu, new_mtu); 7187 7188 /* must set new MTU before calling down or up */ 7189 WRITE_ONCE(netdev->mtu, new_mtu); 7190 7191 if (netif_running(netdev)) 7192 ixgbe_reinit_locked(adapter); 7193 7194 return 0; 7195 } 7196 7197 /** 7198 * ixgbe_open - Called when a network interface is made active 7199 * @netdev: network interface device structure 7200 * 7201 * Returns 0 on success, negative value on failure 7202 * 7203 * The open entry point is called when a network interface is made 7204 * active by the system (IFF_UP). At this point all resources needed 7205 * for transmit and receive operations are allocated, the interrupt 7206 * handler is registered with the OS, the watchdog timer is started, 7207 * and the stack is notified that the interface is ready. 7208 **/ 7209 int ixgbe_open(struct net_device *netdev) 7210 { 7211 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7212 struct ixgbe_hw *hw = &adapter->hw; 7213 int err, queues; 7214 7215 /* disallow open during test */ 7216 if (test_bit(__IXGBE_TESTING, &adapter->state)) 7217 return -EBUSY; 7218 7219 netif_carrier_off(netdev); 7220 7221 /* allocate transmit descriptors */ 7222 err = ixgbe_setup_all_tx_resources(adapter); 7223 if (err) 7224 goto err_setup_tx; 7225 7226 /* allocate receive descriptors */ 7227 err = ixgbe_setup_all_rx_resources(adapter); 7228 if (err) 7229 goto err_setup_rx; 7230 7231 ixgbe_configure(adapter); 7232 7233 err = ixgbe_request_irq(adapter); 7234 if (err) 7235 goto err_req_irq; 7236 7237 /* Notify the stack of the actual queue counts. */ 7238 queues = adapter->num_tx_queues; 7239 err = netif_set_real_num_tx_queues(netdev, queues); 7240 if (err) 7241 goto err_set_queues; 7242 7243 queues = adapter->num_rx_queues; 7244 err = netif_set_real_num_rx_queues(netdev, queues); 7245 if (err) 7246 goto err_set_queues; 7247 7248 ixgbe_ptp_init(adapter); 7249 7250 ixgbe_up_complete(adapter); 7251 7252 udp_tunnel_nic_reset_ntf(netdev); 7253 if (adapter->hw.mac.type == ixgbe_mac_e610) { 7254 int err = ixgbe_update_link_info(&adapter->hw); 7255 7256 if (err) 7257 e_dev_err("Failed to update link info, err %d.\n", err); 7258 7259 ixgbe_check_link_cfg_err(adapter, 7260 adapter->hw.link.link_info.link_cfg_err); 7261 7262 err = ixgbe_non_sfp_link_config(&adapter->hw); 7263 if (ixgbe_non_sfp_link_config(&adapter->hw)) 7264 e_dev_err("Link setup failed, err %d.\n", err); 7265 } 7266 7267 return 0; 7268 7269 err_set_queues: 7270 ixgbe_free_irq(adapter); 7271 err_req_irq: 7272 ixgbe_free_all_rx_resources(adapter); 7273 if (hw->phy.ops.set_phy_power && !adapter->wol) 7274 hw->phy.ops.set_phy_power(&adapter->hw, false); 7275 err_setup_rx: 7276 ixgbe_free_all_tx_resources(adapter); 7277 err_setup_tx: 7278 ixgbe_reset(adapter); 7279 7280 return err; 7281 } 7282 7283 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 7284 { 7285 ixgbe_ptp_suspend(adapter); 7286 7287 if (adapter->hw.phy.ops.enter_lplu) { 7288 adapter->hw.phy.reset_disable = true; 7289 ixgbe_down(adapter); 7290 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 7291 adapter->hw.phy.reset_disable = false; 7292 } else { 7293 ixgbe_down(adapter); 7294 } 7295 7296 ixgbe_free_irq(adapter); 7297 7298 ixgbe_free_all_tx_resources(adapter); 7299 ixgbe_free_all_rx_resources(adapter); 7300 } 7301 7302 /** 7303 * ixgbe_close - Disables a network interface 7304 * @netdev: network interface device structure 7305 * 7306 * Returns 0, this is not allowed to fail 7307 * 7308 * The close entry point is called when an interface is de-activated 7309 * by the OS. The hardware is still under the drivers control, but 7310 * needs to be disabled. A global MAC reset is issued to stop the 7311 * hardware, and all transmit and receive resources are freed. 7312 **/ 7313 int ixgbe_close(struct net_device *netdev) 7314 { 7315 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7316 7317 ixgbe_ptp_stop(adapter); 7318 7319 if (netif_device_present(netdev)) 7320 ixgbe_close_suspend(adapter); 7321 7322 ixgbe_fdir_filter_exit(adapter); 7323 7324 ixgbe_release_hw_control(adapter); 7325 7326 return 0; 7327 } 7328 7329 static int ixgbe_resume(struct device *dev_d) 7330 { 7331 struct pci_dev *pdev = to_pci_dev(dev_d); 7332 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 7333 struct net_device *netdev = adapter->netdev; 7334 u32 err; 7335 7336 adapter->hw.hw_addr = adapter->io_addr; 7337 7338 err = pci_enable_device_mem(pdev); 7339 if (err) { 7340 e_dev_err("Cannot enable PCI device from suspend\n"); 7341 return err; 7342 } 7343 smp_mb__before_atomic(); 7344 clear_bit(__IXGBE_DISABLED, &adapter->state); 7345 pci_set_master(pdev); 7346 7347 device_wakeup_disable(dev_d); 7348 7349 ixgbe_reset(adapter); 7350 7351 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 7352 7353 rtnl_lock(); 7354 err = ixgbe_init_interrupt_scheme(adapter); 7355 if (!err && netif_running(netdev)) 7356 err = ixgbe_open(netdev); 7357 7358 7359 if (!err) 7360 netif_device_attach(netdev); 7361 rtnl_unlock(); 7362 7363 return err; 7364 } 7365 7366 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 7367 { 7368 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 7369 struct net_device *netdev = adapter->netdev; 7370 struct ixgbe_hw *hw = &adapter->hw; 7371 u32 ctrl; 7372 u32 wufc = adapter->wol; 7373 7374 rtnl_lock(); 7375 netif_device_detach(netdev); 7376 7377 if (netif_running(netdev)) 7378 ixgbe_close_suspend(adapter); 7379 7380 ixgbe_clear_interrupt_scheme(adapter); 7381 rtnl_unlock(); 7382 7383 if (hw->mac.ops.stop_link_on_d3) 7384 hw->mac.ops.stop_link_on_d3(hw); 7385 7386 if (wufc) { 7387 u32 fctrl; 7388 7389 ixgbe_set_rx_mode(netdev); 7390 7391 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 7392 if (hw->mac.ops.enable_tx_laser) 7393 hw->mac.ops.enable_tx_laser(hw); 7394 7395 /* enable the reception of multicast packets */ 7396 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7397 fctrl |= IXGBE_FCTRL_MPE; 7398 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 7399 7400 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 7401 ctrl |= IXGBE_CTRL_GIO_DIS; 7402 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 7403 7404 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 7405 } else { 7406 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 7407 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 7408 } 7409 7410 switch (hw->mac.type) { 7411 case ixgbe_mac_82598EB: 7412 pci_wake_from_d3(pdev, false); 7413 break; 7414 case ixgbe_mac_82599EB: 7415 case ixgbe_mac_X540: 7416 case ixgbe_mac_X550: 7417 case ixgbe_mac_X550EM_x: 7418 case ixgbe_mac_x550em_a: 7419 case ixgbe_mac_e610: 7420 pci_wake_from_d3(pdev, !!wufc); 7421 break; 7422 default: 7423 break; 7424 } 7425 7426 *enable_wake = !!wufc; 7427 if (hw->phy.ops.set_phy_power && !*enable_wake) 7428 hw->phy.ops.set_phy_power(hw, false); 7429 7430 ixgbe_release_hw_control(adapter); 7431 7432 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 7433 pci_disable_device(pdev); 7434 7435 return 0; 7436 } 7437 7438 static int ixgbe_suspend(struct device *dev_d) 7439 { 7440 struct pci_dev *pdev = to_pci_dev(dev_d); 7441 int retval; 7442 bool wake; 7443 7444 retval = __ixgbe_shutdown(pdev, &wake); 7445 7446 device_set_wakeup_enable(dev_d, wake); 7447 7448 return retval; 7449 } 7450 7451 static void ixgbe_shutdown(struct pci_dev *pdev) 7452 { 7453 bool wake; 7454 7455 __ixgbe_shutdown(pdev, &wake); 7456 7457 if (system_state == SYSTEM_POWER_OFF) { 7458 pci_wake_from_d3(pdev, wake); 7459 pci_set_power_state(pdev, PCI_D3hot); 7460 } 7461 } 7462 7463 /** 7464 * ixgbe_update_stats - Update the board statistics counters. 7465 * @adapter: board private structure 7466 **/ 7467 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 7468 { 7469 struct net_device *netdev = adapter->netdev; 7470 struct ixgbe_hw *hw = &adapter->hw; 7471 struct ixgbe_hw_stats *hwstats = &adapter->stats; 7472 u64 total_mpc = 0; 7473 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 7474 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 7475 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 7476 u64 alloc_rx_page = 0; 7477 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 7478 7479 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7480 test_bit(__IXGBE_RESETTING, &adapter->state)) 7481 return; 7482 7483 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 7484 u64 rsc_count = 0; 7485 u64 rsc_flush = 0; 7486 for (i = 0; i < adapter->num_rx_queues; i++) { 7487 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 7488 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 7489 } 7490 adapter->rsc_total_count = rsc_count; 7491 adapter->rsc_total_flush = rsc_flush; 7492 } 7493 7494 for (i = 0; i < adapter->num_rx_queues; i++) { 7495 struct ixgbe_ring *rx_ring = READ_ONCE(adapter->rx_ring[i]); 7496 7497 if (!rx_ring) 7498 continue; 7499 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 7500 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page; 7501 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 7502 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 7503 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 7504 bytes += rx_ring->stats.bytes; 7505 packets += rx_ring->stats.packets; 7506 } 7507 adapter->non_eop_descs = non_eop_descs; 7508 adapter->alloc_rx_page = alloc_rx_page; 7509 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 7510 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 7511 adapter->hw_csum_rx_error = hw_csum_rx_error; 7512 netdev->stats.rx_bytes = bytes; 7513 netdev->stats.rx_packets = packets; 7514 7515 bytes = 0; 7516 packets = 0; 7517 /* gather some stats to the adapter struct that are per queue */ 7518 for (i = 0; i < adapter->num_tx_queues; i++) { 7519 struct ixgbe_ring *tx_ring = READ_ONCE(adapter->tx_ring[i]); 7520 7521 if (!tx_ring) 7522 continue; 7523 restart_queue += tx_ring->tx_stats.restart_queue; 7524 tx_busy += tx_ring->tx_stats.tx_busy; 7525 bytes += tx_ring->stats.bytes; 7526 packets += tx_ring->stats.packets; 7527 } 7528 for (i = 0; i < adapter->num_xdp_queues; i++) { 7529 struct ixgbe_ring *xdp_ring = READ_ONCE(adapter->xdp_ring[i]); 7530 7531 if (!xdp_ring) 7532 continue; 7533 restart_queue += xdp_ring->tx_stats.restart_queue; 7534 tx_busy += xdp_ring->tx_stats.tx_busy; 7535 bytes += xdp_ring->stats.bytes; 7536 packets += xdp_ring->stats.packets; 7537 } 7538 adapter->restart_queue = restart_queue; 7539 adapter->tx_busy = tx_busy; 7540 netdev->stats.tx_bytes = bytes; 7541 netdev->stats.tx_packets = packets; 7542 7543 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 7544 7545 /* 8 register reads */ 7546 for (i = 0; i < 8; i++) { 7547 /* for packet buffers not used, the register should read 0 */ 7548 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 7549 missed_rx += mpc; 7550 hwstats->mpc[i] += mpc; 7551 total_mpc += hwstats->mpc[i]; 7552 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 7553 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 7554 switch (hw->mac.type) { 7555 case ixgbe_mac_82598EB: 7556 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 7557 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 7558 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 7559 hwstats->pxonrxc[i] += 7560 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 7561 break; 7562 case ixgbe_mac_82599EB: 7563 case ixgbe_mac_X540: 7564 case ixgbe_mac_X550: 7565 case ixgbe_mac_X550EM_x: 7566 case ixgbe_mac_x550em_a: 7567 case ixgbe_mac_e610: 7568 hwstats->pxonrxc[i] += 7569 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 7570 break; 7571 default: 7572 break; 7573 } 7574 } 7575 7576 /*16 register reads */ 7577 for (i = 0; i < 16; i++) { 7578 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 7579 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 7580 if (hw->mac.type == ixgbe_mac_82599EB || 7581 hw->mac.type == ixgbe_mac_X540 || 7582 hw->mac.type == ixgbe_mac_X550 || 7583 hw->mac.type == ixgbe_mac_X550EM_x || 7584 hw->mac.type == ixgbe_mac_x550em_a || 7585 hw->mac.type == ixgbe_mac_e610) { 7586 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 7587 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 7588 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 7589 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 7590 } 7591 } 7592 7593 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 7594 /* work around hardware counting issue */ 7595 hwstats->gprc -= missed_rx; 7596 7597 ixgbe_update_xoff_received(adapter); 7598 7599 /* 82598 hardware only has a 32 bit counter in the high register */ 7600 switch (hw->mac.type) { 7601 case ixgbe_mac_82598EB: 7602 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 7603 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 7604 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 7605 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 7606 break; 7607 case ixgbe_mac_X540: 7608 case ixgbe_mac_X550: 7609 case ixgbe_mac_X550EM_x: 7610 case ixgbe_mac_x550em_a: 7611 case ixgbe_mac_e610: 7612 /* OS2BMC stats are X540 and later */ 7613 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 7614 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 7615 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 7616 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 7617 fallthrough; 7618 case ixgbe_mac_82599EB: 7619 for (i = 0; i < 16; i++) 7620 adapter->hw_rx_no_dma_resources += 7621 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 7622 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 7623 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 7624 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 7625 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 7626 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 7627 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 7628 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 7629 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 7630 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 7631 #ifdef IXGBE_FCOE 7632 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 7633 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 7634 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 7635 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 7636 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 7637 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 7638 /* Add up per cpu counters for total ddp aloc fail */ 7639 if (adapter->fcoe.ddp_pool) { 7640 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 7641 struct ixgbe_fcoe_ddp_pool *ddp_pool; 7642 unsigned int cpu; 7643 u64 noddp = 0, noddp_ext_buff = 0; 7644 for_each_possible_cpu(cpu) { 7645 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 7646 noddp += ddp_pool->noddp; 7647 noddp_ext_buff += ddp_pool->noddp_ext_buff; 7648 } 7649 hwstats->fcoe_noddp = noddp; 7650 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 7651 } 7652 #endif /* IXGBE_FCOE */ 7653 break; 7654 default: 7655 break; 7656 } 7657 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 7658 hwstats->bprc += bprc; 7659 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 7660 if (hw->mac.type == ixgbe_mac_82598EB) 7661 hwstats->mprc -= bprc; 7662 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 7663 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 7664 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 7665 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 7666 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 7667 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 7668 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 7669 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 7670 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 7671 hwstats->lxontxc += lxon; 7672 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 7673 hwstats->lxofftxc += lxoff; 7674 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 7675 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 7676 /* 7677 * 82598 errata - tx of flow control packets is included in tx counters 7678 */ 7679 xon_off_tot = lxon + lxoff; 7680 hwstats->gptc -= xon_off_tot; 7681 hwstats->mptc -= xon_off_tot; 7682 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 7683 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 7684 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 7685 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 7686 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 7687 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 7688 hwstats->ptc64 -= xon_off_tot; 7689 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 7690 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 7691 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 7692 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 7693 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 7694 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 7695 7696 /* Fill out the OS statistics structure */ 7697 netdev->stats.multicast = hwstats->mprc; 7698 7699 /* Rx Errors */ 7700 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 7701 netdev->stats.rx_dropped = 0; 7702 netdev->stats.rx_length_errors = hwstats->rlec; 7703 netdev->stats.rx_crc_errors = hwstats->crcerrs; 7704 netdev->stats.rx_missed_errors = total_mpc; 7705 7706 /* VF Stats Collection - skip while resetting because these 7707 * are not clear on read and otherwise you'll sometimes get 7708 * crazy values. 7709 */ 7710 if (!test_bit(__IXGBE_RESETTING, &adapter->state)) { 7711 for (i = 0; i < adapter->num_vfs; i++) { 7712 UPDATE_VF_COUNTER_32bit(IXGBE_PVFGPRC(i), 7713 adapter->vfinfo[i].last_vfstats.gprc, 7714 adapter->vfinfo[i].vfstats.gprc); 7715 UPDATE_VF_COUNTER_32bit(IXGBE_PVFGPTC(i), 7716 adapter->vfinfo[i].last_vfstats.gptc, 7717 adapter->vfinfo[i].vfstats.gptc); 7718 UPDATE_VF_COUNTER_36bit(IXGBE_PVFGORC_LSB(i), 7719 IXGBE_PVFGORC_MSB(i), 7720 adapter->vfinfo[i].last_vfstats.gorc, 7721 adapter->vfinfo[i].vfstats.gorc); 7722 UPDATE_VF_COUNTER_36bit(IXGBE_PVFGOTC_LSB(i), 7723 IXGBE_PVFGOTC_MSB(i), 7724 adapter->vfinfo[i].last_vfstats.gotc, 7725 adapter->vfinfo[i].vfstats.gotc); 7726 UPDATE_VF_COUNTER_32bit(IXGBE_PVFMPRC(i), 7727 adapter->vfinfo[i].last_vfstats.mprc, 7728 adapter->vfinfo[i].vfstats.mprc); 7729 } 7730 } 7731 } 7732 7733 /** 7734 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 7735 * @adapter: pointer to the device adapter structure 7736 **/ 7737 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 7738 { 7739 struct ixgbe_hw *hw = &adapter->hw; 7740 int i; 7741 7742 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 7743 return; 7744 7745 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 7746 7747 /* if interface is down do nothing */ 7748 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7749 return; 7750 7751 /* do nothing if we are not using signature filters */ 7752 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 7753 return; 7754 7755 adapter->fdir_overflow++; 7756 7757 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 7758 for (i = 0; i < adapter->num_tx_queues; i++) 7759 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7760 &(adapter->tx_ring[i]->state)); 7761 for (i = 0; i < adapter->num_xdp_queues; i++) 7762 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7763 &adapter->xdp_ring[i]->state); 7764 /* re-enable flow director interrupts */ 7765 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 7766 } else { 7767 e_err(probe, "failed to finish FDIR re-initialization, " 7768 "ignored adding FDIR ATR filters\n"); 7769 } 7770 } 7771 7772 /** 7773 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 7774 * @adapter: pointer to the device adapter structure 7775 * 7776 * This function serves two purposes. First it strobes the interrupt lines 7777 * in order to make certain interrupts are occurring. Secondly it sets the 7778 * bits needed to check for TX hangs. As a result we should immediately 7779 * determine if a hang has occurred. 7780 */ 7781 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 7782 { 7783 struct ixgbe_hw *hw = &adapter->hw; 7784 u64 eics = 0; 7785 int i; 7786 7787 /* If we're down, removing or resetting, just bail */ 7788 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7789 test_bit(__IXGBE_REMOVING, &adapter->state) || 7790 test_bit(__IXGBE_RESETTING, &adapter->state)) 7791 return; 7792 7793 /* Force detection of hung controller */ 7794 if (netif_carrier_ok(adapter->netdev)) { 7795 for (i = 0; i < adapter->num_tx_queues; i++) 7796 set_check_for_tx_hang(adapter->tx_ring[i]); 7797 for (i = 0; i < adapter->num_xdp_queues; i++) 7798 set_check_for_tx_hang(adapter->xdp_ring[i]); 7799 } 7800 7801 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 7802 /* 7803 * for legacy and MSI interrupts don't set any bits 7804 * that are enabled for EIAM, because this operation 7805 * would set *both* EIMS and EICS for any bit in EIAM 7806 */ 7807 IXGBE_WRITE_REG(hw, IXGBE_EICS, 7808 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 7809 } else { 7810 /* get one bit for every active tx/rx interrupt vector */ 7811 for (i = 0; i < adapter->num_q_vectors; i++) { 7812 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 7813 if (qv->rx.ring || qv->tx.ring) 7814 eics |= BIT_ULL(i); 7815 } 7816 } 7817 7818 /* Cause software interrupt to ensure rings are cleaned */ 7819 ixgbe_irq_rearm_queues(adapter, eics); 7820 } 7821 7822 /** 7823 * ixgbe_watchdog_update_link - update the link status 7824 * @adapter: pointer to the device adapter structure 7825 **/ 7826 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 7827 { 7828 struct ixgbe_hw *hw = &adapter->hw; 7829 u32 link_speed = adapter->link_speed; 7830 bool link_up = adapter->link_up; 7831 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 7832 7833 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 7834 return; 7835 7836 if (hw->mac.ops.check_link) { 7837 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 7838 } else { 7839 /* always assume link is up, if no check link function */ 7840 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 7841 link_up = true; 7842 } 7843 7844 if (adapter->ixgbe_ieee_pfc) 7845 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 7846 7847 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 7848 hw->mac.ops.fc_enable(hw); 7849 ixgbe_set_rx_drop_en(adapter); 7850 } 7851 7852 if (link_up || 7853 time_after(jiffies, (adapter->link_check_timeout + 7854 IXGBE_TRY_LINK_TIMEOUT))) { 7855 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 7856 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 7857 IXGBE_WRITE_FLUSH(hw); 7858 } 7859 7860 adapter->link_up = link_up; 7861 adapter->link_speed = link_speed; 7862 } 7863 7864 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 7865 { 7866 #ifdef CONFIG_IXGBE_DCB 7867 struct net_device *netdev = adapter->netdev; 7868 struct dcb_app app = { 7869 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 7870 .protocol = 0, 7871 }; 7872 u8 up = 0; 7873 7874 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 7875 up = dcb_ieee_getapp_mask(netdev, &app); 7876 7877 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 7878 #endif 7879 } 7880 7881 /** 7882 * ixgbe_watchdog_link_is_up - update netif_carrier status and 7883 * print link up message 7884 * @adapter: pointer to the device adapter structure 7885 **/ 7886 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 7887 { 7888 struct net_device *netdev = adapter->netdev; 7889 struct ixgbe_hw *hw = &adapter->hw; 7890 u32 link_speed = adapter->link_speed; 7891 const char *speed_str; 7892 bool flow_rx, flow_tx; 7893 7894 /* only continue if link was previously down */ 7895 if (netif_carrier_ok(netdev)) 7896 return; 7897 7898 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 7899 7900 switch (hw->mac.type) { 7901 case ixgbe_mac_82598EB: { 7902 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7903 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 7904 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 7905 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 7906 } 7907 break; 7908 case ixgbe_mac_X540: 7909 case ixgbe_mac_X550: 7910 case ixgbe_mac_X550EM_x: 7911 case ixgbe_mac_x550em_a: 7912 case ixgbe_mac_e610: 7913 case ixgbe_mac_82599EB: { 7914 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 7915 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 7916 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 7917 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 7918 } 7919 break; 7920 default: 7921 flow_tx = false; 7922 flow_rx = false; 7923 break; 7924 } 7925 7926 adapter->last_rx_ptp_check = jiffies; 7927 7928 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7929 ixgbe_ptp_start_cyclecounter(adapter); 7930 7931 switch (link_speed) { 7932 case IXGBE_LINK_SPEED_10GB_FULL: 7933 speed_str = "10 Gbps"; 7934 break; 7935 case IXGBE_LINK_SPEED_5GB_FULL: 7936 speed_str = "5 Gbps"; 7937 break; 7938 case IXGBE_LINK_SPEED_2_5GB_FULL: 7939 speed_str = "2.5 Gbps"; 7940 break; 7941 case IXGBE_LINK_SPEED_1GB_FULL: 7942 speed_str = "1 Gbps"; 7943 break; 7944 case IXGBE_LINK_SPEED_100_FULL: 7945 speed_str = "100 Mbps"; 7946 break; 7947 case IXGBE_LINK_SPEED_10_FULL: 7948 speed_str = "10 Mbps"; 7949 break; 7950 default: 7951 speed_str = "unknown speed"; 7952 break; 7953 } 7954 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, 7955 ((flow_rx && flow_tx) ? "RX/TX" : 7956 (flow_rx ? "RX" : 7957 (flow_tx ? "TX" : "None")))); 7958 7959 netif_carrier_on(netdev); 7960 ixgbe_check_vf_rate_limit(adapter); 7961 7962 /* enable transmits */ 7963 netif_tx_wake_all_queues(adapter->netdev); 7964 7965 /* update the default user priority for VFs */ 7966 ixgbe_update_default_up(adapter); 7967 7968 /* ping all the active vfs to let them know link has changed */ 7969 ixgbe_ping_all_vfs(adapter); 7970 } 7971 7972 /** 7973 * ixgbe_watchdog_link_is_down - update netif_carrier status and 7974 * print link down message 7975 * @adapter: pointer to the adapter structure 7976 **/ 7977 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 7978 { 7979 struct net_device *netdev = adapter->netdev; 7980 struct ixgbe_hw *hw = &adapter->hw; 7981 7982 adapter->link_up = false; 7983 adapter->link_speed = 0; 7984 7985 /* only continue if link was up previously */ 7986 if (!netif_carrier_ok(netdev)) 7987 return; 7988 7989 /* poll for SFP+ cable when link is down */ 7990 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 7991 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 7992 7993 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7994 ixgbe_ptp_start_cyclecounter(adapter); 7995 7996 e_info(drv, "NIC Link is Down\n"); 7997 netif_carrier_off(netdev); 7998 7999 /* ping all the active vfs to let them know link has changed */ 8000 ixgbe_ping_all_vfs(adapter); 8001 } 8002 8003 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 8004 { 8005 int i; 8006 8007 for (i = 0; i < adapter->num_tx_queues; i++) { 8008 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 8009 8010 if (tx_ring->next_to_use != tx_ring->next_to_clean) 8011 return true; 8012 } 8013 8014 for (i = 0; i < adapter->num_xdp_queues; i++) { 8015 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 8016 8017 if (ring->next_to_use != ring->next_to_clean) 8018 return true; 8019 } 8020 8021 return false; 8022 } 8023 8024 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 8025 { 8026 struct ixgbe_hw *hw = &adapter->hw; 8027 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 8028 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 8029 8030 int i, j; 8031 8032 if (!adapter->num_vfs) 8033 return false; 8034 8035 /* resetting the PF is only needed for MAC before X550 */ 8036 if (hw->mac.type >= ixgbe_mac_X550) 8037 return false; 8038 8039 for (i = 0; i < adapter->num_vfs; i++) { 8040 for (j = 0; j < q_per_pool; j++) { 8041 u32 h, t; 8042 8043 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 8044 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 8045 8046 if (h != t) 8047 return true; 8048 } 8049 } 8050 8051 return false; 8052 } 8053 8054 /** 8055 * ixgbe_watchdog_flush_tx - flush queues on link down 8056 * @adapter: pointer to the device adapter structure 8057 **/ 8058 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 8059 { 8060 if (!netif_carrier_ok(adapter->netdev)) { 8061 if (ixgbe_ring_tx_pending(adapter) || 8062 ixgbe_vf_tx_pending(adapter)) { 8063 /* We've lost link, so the controller stops DMA, 8064 * but we've got queued Tx work that's never going 8065 * to get done, so reset controller to flush Tx. 8066 * (Do the reset outside of interrupt context). 8067 */ 8068 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 8069 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 8070 } 8071 } 8072 } 8073 8074 #ifdef CONFIG_PCI_IOV 8075 static void ixgbe_bad_vf_abort(struct ixgbe_adapter *adapter, u32 vf) 8076 { 8077 struct ixgbe_hw *hw = &adapter->hw; 8078 8079 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 8080 adapter->flags2 & IXGBE_FLAG2_AUTO_DISABLE_VF) { 8081 adapter->vfinfo[vf].primary_abort_count++; 8082 if (adapter->vfinfo[vf].primary_abort_count == 8083 IXGBE_PRIMARY_ABORT_LIMIT) { 8084 ixgbe_set_vf_link_state(adapter, vf, 8085 IFLA_VF_LINK_STATE_DISABLE); 8086 adapter->vfinfo[vf].primary_abort_count = 0; 8087 8088 e_info(drv, 8089 "Malicious Driver Detection event detected on PF %d VF %d MAC: %pM mdd-disable-vf=on", 8090 hw->bus.func, vf, 8091 adapter->vfinfo[vf].vf_mac_addresses); 8092 } 8093 } 8094 } 8095 8096 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 8097 { 8098 struct ixgbe_hw *hw = &adapter->hw; 8099 struct pci_dev *pdev = adapter->pdev; 8100 unsigned int vf; 8101 u32 gpc; 8102 8103 if (!(netif_carrier_ok(adapter->netdev))) 8104 return; 8105 8106 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 8107 if (gpc) /* If incrementing then no need for the check below */ 8108 return; 8109 /* Check to see if a bad DMA write target from an errant or 8110 * malicious VF has caused a PCIe error. If so then we can 8111 * issue a VFLR to the offending VF(s) and then resume without 8112 * requesting a full slot reset. 8113 */ 8114 8115 if (!pdev) 8116 return; 8117 8118 /* check status reg for all VFs owned by this PF */ 8119 for (vf = 0; vf < adapter->num_vfs; ++vf) { 8120 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; 8121 u16 status_reg; 8122 8123 if (!vfdev) 8124 continue; 8125 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 8126 if (status_reg != IXGBE_FAILED_READ_CFG_WORD && 8127 status_reg & PCI_STATUS_REC_MASTER_ABORT) { 8128 ixgbe_bad_vf_abort(adapter, vf); 8129 pcie_flr(vfdev); 8130 } 8131 } 8132 } 8133 8134 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 8135 { 8136 u32 ssvpc; 8137 8138 /* Do not perform spoof check for 82598 or if not in IOV mode */ 8139 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 8140 adapter->num_vfs == 0) 8141 return; 8142 8143 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 8144 8145 /* 8146 * ssvpc register is cleared on read, if zero then no 8147 * spoofed packets in the last interval. 8148 */ 8149 if (!ssvpc) 8150 return; 8151 8152 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 8153 } 8154 #else 8155 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 8156 { 8157 } 8158 8159 static void 8160 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 8161 { 8162 } 8163 #endif /* CONFIG_PCI_IOV */ 8164 8165 8166 /** 8167 * ixgbe_watchdog_subtask - check and bring link up 8168 * @adapter: pointer to the device adapter structure 8169 **/ 8170 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 8171 { 8172 /* if interface is down, removing or resetting, do nothing */ 8173 if (test_bit(__IXGBE_DOWN, &adapter->state) || 8174 test_bit(__IXGBE_REMOVING, &adapter->state) || 8175 test_bit(__IXGBE_RESETTING, &adapter->state)) 8176 return; 8177 8178 ixgbe_watchdog_update_link(adapter); 8179 8180 if (adapter->link_up) 8181 ixgbe_watchdog_link_is_up(adapter); 8182 else 8183 ixgbe_watchdog_link_is_down(adapter); 8184 8185 ixgbe_check_for_bad_vf(adapter); 8186 ixgbe_spoof_check(adapter); 8187 ixgbe_update_stats(adapter); 8188 8189 ixgbe_watchdog_flush_tx(adapter); 8190 } 8191 8192 /** 8193 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 8194 * @adapter: the ixgbe adapter structure 8195 **/ 8196 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 8197 { 8198 struct ixgbe_hw *hw = &adapter->hw; 8199 int err; 8200 8201 /* not searching for SFP so there is nothing to do here */ 8202 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 8203 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 8204 return; 8205 8206 if (adapter->sfp_poll_time && 8207 time_after(adapter->sfp_poll_time, jiffies)) 8208 return; /* If not yet time to poll for SFP */ 8209 8210 /* someone else is in init, wait until next service event */ 8211 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 8212 return; 8213 8214 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; 8215 8216 err = hw->phy.ops.identify_sfp(hw); 8217 if (err == -EOPNOTSUPP) 8218 goto sfp_out; 8219 8220 if (err == -ENOENT) { 8221 /* If no cable is present, then we need to reset 8222 * the next time we find a good cable. */ 8223 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 8224 } 8225 8226 /* exit on error */ 8227 if (err) 8228 goto sfp_out; 8229 8230 /* exit if reset not needed */ 8231 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 8232 goto sfp_out; 8233 8234 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 8235 8236 /* 8237 * A module may be identified correctly, but the EEPROM may not have 8238 * support for that module. setup_sfp() will fail in that case, so 8239 * we should not allow that module to load. 8240 */ 8241 if (hw->mac.type == ixgbe_mac_82598EB) 8242 err = hw->phy.ops.reset(hw); 8243 else 8244 err = hw->mac.ops.setup_sfp(hw); 8245 8246 if (err == -EOPNOTSUPP) 8247 goto sfp_out; 8248 8249 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 8250 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 8251 8252 sfp_out: 8253 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 8254 8255 if (err == -EOPNOTSUPP && 8256 adapter->netdev->reg_state == NETREG_REGISTERED) { 8257 e_dev_err("failed to initialize because an unsupported " 8258 "SFP+ module type was detected.\n"); 8259 e_dev_err("Reload the driver after installing a " 8260 "supported module.\n"); 8261 unregister_netdev(adapter->netdev); 8262 } 8263 } 8264 8265 /** 8266 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 8267 * @adapter: the ixgbe adapter structure 8268 **/ 8269 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 8270 { 8271 struct ixgbe_hw *hw = &adapter->hw; 8272 u32 cap_speed; 8273 u32 speed; 8274 bool autoneg = false; 8275 8276 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 8277 return; 8278 8279 /* someone else is in init, wait until next service event */ 8280 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 8281 return; 8282 8283 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 8284 8285 hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg); 8286 8287 /* advertise highest capable link speed */ 8288 if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL)) 8289 speed = IXGBE_LINK_SPEED_10GB_FULL; 8290 else 8291 speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL | 8292 IXGBE_LINK_SPEED_1GB_FULL); 8293 8294 if (hw->mac.ops.setup_link) 8295 hw->mac.ops.setup_link(hw, speed, true); 8296 8297 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 8298 adapter->link_check_timeout = jiffies; 8299 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 8300 } 8301 8302 /** 8303 * ixgbe_service_timer - Timer Call-back 8304 * @t: pointer to timer_list structure 8305 **/ 8306 static void ixgbe_service_timer(struct timer_list *t) 8307 { 8308 struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer); 8309 unsigned long next_event_offset; 8310 8311 /* poll faster when waiting for link */ 8312 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 8313 next_event_offset = HZ / 10; 8314 else 8315 next_event_offset = HZ * 2; 8316 8317 /* Reset the timer */ 8318 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 8319 8320 ixgbe_service_event_schedule(adapter); 8321 } 8322 8323 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 8324 { 8325 struct ixgbe_hw *hw = &adapter->hw; 8326 bool overtemp; 8327 8328 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 8329 return; 8330 8331 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 8332 8333 if (!hw->phy.ops.handle_lasi) 8334 return; 8335 8336 hw->phy.ops.handle_lasi(&adapter->hw, &overtemp); 8337 if (overtemp) 8338 e_crit(drv, "%s\n", ixgbe_overheat_msg); 8339 } 8340 8341 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 8342 { 8343 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state)) 8344 return; 8345 8346 rtnl_lock(); 8347 /* If we're already down, removing or resetting, just bail */ 8348 if (test_bit(__IXGBE_DOWN, &adapter->state) || 8349 test_bit(__IXGBE_REMOVING, &adapter->state) || 8350 test_bit(__IXGBE_RESETTING, &adapter->state)) { 8351 rtnl_unlock(); 8352 return; 8353 } 8354 8355 ixgbe_dump(adapter); 8356 netdev_err(adapter->netdev, "Reset adapter\n"); 8357 adapter->tx_timeout_count++; 8358 8359 ixgbe_reinit_locked(adapter); 8360 rtnl_unlock(); 8361 } 8362 8363 /** 8364 * ixgbe_check_fw_error - Check firmware for errors 8365 * @adapter: the adapter private structure 8366 * 8367 * Check firmware errors in register FWSM 8368 */ 8369 static bool ixgbe_check_fw_error(struct ixgbe_adapter *adapter) 8370 { 8371 struct ixgbe_hw *hw = &adapter->hw; 8372 u32 fwsm; 8373 8374 /* read fwsm.ext_err_ind register and log errors */ 8375 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 8376 8377 if (fwsm & IXGBE_FWSM_EXT_ERR_IND_MASK || 8378 !(fwsm & IXGBE_FWSM_FW_VAL_BIT)) 8379 e_dev_warn("Warning firmware error detected FWSM: 0x%08X\n", 8380 fwsm); 8381 8382 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 8383 e_dev_err("Firmware recovery mode detected. Limiting functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware recovery mode.\n"); 8384 return true; 8385 } 8386 8387 return false; 8388 } 8389 8390 /** 8391 * ixgbe_service_task - manages and runs subtasks 8392 * @work: pointer to work_struct containing our data 8393 **/ 8394 static void ixgbe_service_task(struct work_struct *work) 8395 { 8396 struct ixgbe_adapter *adapter = container_of(work, 8397 struct ixgbe_adapter, 8398 service_task); 8399 if (ixgbe_removed(adapter->hw.hw_addr)) { 8400 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 8401 rtnl_lock(); 8402 ixgbe_down(adapter); 8403 rtnl_unlock(); 8404 } 8405 ixgbe_service_event_complete(adapter); 8406 return; 8407 } 8408 if (ixgbe_check_fw_error(adapter)) { 8409 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 8410 unregister_netdev(adapter->netdev); 8411 ixgbe_service_event_complete(adapter); 8412 return; 8413 } 8414 if (adapter->hw.mac.type == ixgbe_mac_e610) { 8415 if (adapter->flags2 & IXGBE_FLAG2_FW_ASYNC_EVENT) 8416 ixgbe_handle_fw_event(adapter); 8417 ixgbe_check_media_subtask(adapter); 8418 } 8419 ixgbe_reset_subtask(adapter); 8420 ixgbe_phy_interrupt_subtask(adapter); 8421 ixgbe_sfp_detection_subtask(adapter); 8422 ixgbe_sfp_link_config_subtask(adapter); 8423 ixgbe_check_overtemp_subtask(adapter); 8424 ixgbe_watchdog_subtask(adapter); 8425 ixgbe_fdir_reinit_subtask(adapter); 8426 ixgbe_check_hang_subtask(adapter); 8427 8428 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 8429 ixgbe_ptp_overflow_check(adapter); 8430 if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER) 8431 ixgbe_ptp_rx_hang(adapter); 8432 ixgbe_ptp_tx_hang(adapter); 8433 } 8434 8435 ixgbe_service_event_complete(adapter); 8436 } 8437 8438 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 8439 struct ixgbe_tx_buffer *first, 8440 u8 *hdr_len, 8441 struct ixgbe_ipsec_tx_data *itd) 8442 { 8443 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 8444 struct sk_buff *skb = first->skb; 8445 union { 8446 struct iphdr *v4; 8447 struct ipv6hdr *v6; 8448 unsigned char *hdr; 8449 } ip; 8450 union { 8451 struct tcphdr *tcp; 8452 struct udphdr *udp; 8453 unsigned char *hdr; 8454 } l4; 8455 u32 paylen, l4_offset; 8456 u32 fceof_saidx = 0; 8457 int err; 8458 8459 if (skb->ip_summed != CHECKSUM_PARTIAL) 8460 return 0; 8461 8462 if (!skb_is_gso(skb)) 8463 return 0; 8464 8465 err = skb_cow_head(skb, 0); 8466 if (err < 0) 8467 return err; 8468 8469 if (eth_p_mpls(first->protocol)) 8470 ip.hdr = skb_inner_network_header(skb); 8471 else 8472 ip.hdr = skb_network_header(skb); 8473 l4.hdr = skb_checksum_start(skb); 8474 8475 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 8476 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 8477 IXGBE_ADVTXD_TUCMD_L4T_UDP : IXGBE_ADVTXD_TUCMD_L4T_TCP; 8478 8479 /* initialize outer IP header fields */ 8480 if (ip.v4->version == 4) { 8481 unsigned char *csum_start = skb_checksum_start(skb); 8482 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 8483 int len = csum_start - trans_start; 8484 8485 /* IP header will have to cancel out any data that 8486 * is not a part of the outer IP header, so set to 8487 * a reverse csum if needed, else init check to 0. 8488 */ 8489 ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ? 8490 csum_fold(csum_partial(trans_start, 8491 len, 0)) : 0; 8492 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 8493 8494 ip.v4->tot_len = 0; 8495 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 8496 IXGBE_TX_FLAGS_CSUM | 8497 IXGBE_TX_FLAGS_IPV4; 8498 } else { 8499 ip.v6->payload_len = 0; 8500 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 8501 IXGBE_TX_FLAGS_CSUM; 8502 } 8503 8504 /* determine offset of inner transport header */ 8505 l4_offset = l4.hdr - skb->data; 8506 8507 /* remove payload length from inner checksum */ 8508 paylen = skb->len - l4_offset; 8509 8510 if (type_tucmd & IXGBE_ADVTXD_TUCMD_L4T_TCP) { 8511 /* compute length of segmentation header */ 8512 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 8513 csum_replace_by_diff(&l4.tcp->check, 8514 (__force __wsum)htonl(paylen)); 8515 } else { 8516 /* compute length of segmentation header */ 8517 *hdr_len = sizeof(*l4.udp) + l4_offset; 8518 csum_replace_by_diff(&l4.udp->check, 8519 (__force __wsum)htonl(paylen)); 8520 } 8521 8522 /* update gso size and bytecount with header size */ 8523 first->gso_segs = skb_shinfo(skb)->gso_segs; 8524 first->bytecount += (first->gso_segs - 1) * *hdr_len; 8525 8526 /* mss_l4len_id: use 0 as index for TSO */ 8527 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; 8528 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 8529 8530 fceof_saidx |= itd->sa_idx; 8531 type_tucmd |= itd->flags | itd->trailer_len; 8532 8533 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 8534 vlan_macip_lens = l4.hdr - ip.hdr; 8535 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; 8536 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8537 8538 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 8539 mss_l4len_idx); 8540 8541 return 1; 8542 } 8543 8544 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 8545 struct ixgbe_tx_buffer *first, 8546 struct ixgbe_ipsec_tx_data *itd) 8547 { 8548 struct sk_buff *skb = first->skb; 8549 u32 vlan_macip_lens = 0; 8550 u32 fceof_saidx = 0; 8551 u32 type_tucmd = 0; 8552 8553 if (skb->ip_summed != CHECKSUM_PARTIAL) { 8554 csum_failed: 8555 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | 8556 IXGBE_TX_FLAGS_CC))) 8557 return; 8558 goto no_csum; 8559 } 8560 8561 switch (skb->csum_offset) { 8562 case offsetof(struct tcphdr, check): 8563 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 8564 fallthrough; 8565 case offsetof(struct udphdr, check): 8566 break; 8567 case offsetof(struct sctphdr, checksum): 8568 /* validate that this is actually an SCTP request */ 8569 if (skb_csum_is_sctp(skb)) { 8570 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; 8571 break; 8572 } 8573 fallthrough; 8574 default: 8575 skb_checksum_help(skb); 8576 goto csum_failed; 8577 } 8578 8579 /* update TX checksum flag */ 8580 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 8581 vlan_macip_lens = skb_checksum_start_offset(skb) - 8582 skb_network_offset(skb); 8583 no_csum: 8584 /* vlan_macip_lens: MACLEN, VLAN tag */ 8585 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 8586 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8587 8588 fceof_saidx |= itd->sa_idx; 8589 type_tucmd |= itd->flags | itd->trailer_len; 8590 8591 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0); 8592 } 8593 8594 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 8595 ((_flag <= _result) ? \ 8596 ((u32)(_input & _flag) * (_result / _flag)) : \ 8597 ((u32)(_input & _flag) / (_flag / _result))) 8598 8599 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 8600 { 8601 /* set type for advanced descriptor with frame checksum insertion */ 8602 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8603 IXGBE_ADVTXD_DCMD_DEXT | 8604 IXGBE_ADVTXD_DCMD_IFCS; 8605 8606 /* set HW vlan bit if vlan is present */ 8607 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 8608 IXGBE_ADVTXD_DCMD_VLE); 8609 8610 /* set segmentation enable bits for TSO/FSO */ 8611 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 8612 IXGBE_ADVTXD_DCMD_TSE); 8613 8614 /* set timestamp bit if present */ 8615 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 8616 IXGBE_ADVTXD_MAC_TSTAMP); 8617 8618 /* insert frame checksum */ 8619 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 8620 8621 return cmd_type; 8622 } 8623 8624 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 8625 u32 tx_flags, unsigned int paylen) 8626 { 8627 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 8628 8629 /* enable L4 checksum for TSO and TX checksum offload */ 8630 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8631 IXGBE_TX_FLAGS_CSUM, 8632 IXGBE_ADVTXD_POPTS_TXSM); 8633 8634 /* enable IPv4 checksum for TSO */ 8635 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8636 IXGBE_TX_FLAGS_IPV4, 8637 IXGBE_ADVTXD_POPTS_IXSM); 8638 8639 /* enable IPsec */ 8640 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8641 IXGBE_TX_FLAGS_IPSEC, 8642 IXGBE_ADVTXD_POPTS_IPSEC); 8643 8644 /* 8645 * Check Context must be set if Tx switch is enabled, which it 8646 * always is for case where virtual functions are running 8647 */ 8648 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8649 IXGBE_TX_FLAGS_CC, 8650 IXGBE_ADVTXD_CC); 8651 8652 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 8653 } 8654 8655 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8656 { 8657 if (!netif_subqueue_try_stop(tx_ring->netdev, tx_ring->queue_index, 8658 ixgbe_desc_unused(tx_ring), size)) 8659 return -EBUSY; 8660 8661 ++tx_ring->tx_stats.restart_queue; 8662 return 0; 8663 } 8664 8665 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8666 { 8667 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 8668 return 0; 8669 8670 return __ixgbe_maybe_stop_tx(tx_ring, size); 8671 } 8672 8673 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring, 8674 struct ixgbe_tx_buffer *first, 8675 const u8 hdr_len) 8676 { 8677 struct sk_buff *skb = first->skb; 8678 struct ixgbe_tx_buffer *tx_buffer; 8679 union ixgbe_adv_tx_desc *tx_desc; 8680 skb_frag_t *frag; 8681 dma_addr_t dma; 8682 unsigned int data_len, size; 8683 u32 tx_flags = first->tx_flags; 8684 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 8685 u16 i = tx_ring->next_to_use; 8686 8687 tx_desc = IXGBE_TX_DESC(tx_ring, i); 8688 8689 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 8690 8691 size = skb_headlen(skb); 8692 data_len = skb->data_len; 8693 8694 #ifdef IXGBE_FCOE 8695 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 8696 if (data_len < sizeof(struct fcoe_crc_eof)) { 8697 size -= sizeof(struct fcoe_crc_eof) - data_len; 8698 data_len = 0; 8699 } else { 8700 data_len -= sizeof(struct fcoe_crc_eof); 8701 } 8702 } 8703 8704 #endif 8705 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 8706 8707 tx_buffer = first; 8708 8709 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 8710 if (dma_mapping_error(tx_ring->dev, dma)) 8711 goto dma_error; 8712 8713 /* record length, and DMA address */ 8714 dma_unmap_len_set(tx_buffer, len, size); 8715 dma_unmap_addr_set(tx_buffer, dma, dma); 8716 8717 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8718 8719 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 8720 tx_desc->read.cmd_type_len = 8721 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 8722 8723 i++; 8724 tx_desc++; 8725 if (i == tx_ring->count) { 8726 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8727 i = 0; 8728 } 8729 tx_desc->read.olinfo_status = 0; 8730 8731 dma += IXGBE_MAX_DATA_PER_TXD; 8732 size -= IXGBE_MAX_DATA_PER_TXD; 8733 8734 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8735 } 8736 8737 if (likely(!data_len)) 8738 break; 8739 8740 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 8741 8742 i++; 8743 tx_desc++; 8744 if (i == tx_ring->count) { 8745 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8746 i = 0; 8747 } 8748 tx_desc->read.olinfo_status = 0; 8749 8750 #ifdef IXGBE_FCOE 8751 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 8752 #else 8753 size = skb_frag_size(frag); 8754 #endif 8755 data_len -= size; 8756 8757 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 8758 DMA_TO_DEVICE); 8759 8760 tx_buffer = &tx_ring->tx_buffer_info[i]; 8761 } 8762 8763 /* write last descriptor with RS and EOP bits */ 8764 cmd_type |= size | IXGBE_TXD_CMD; 8765 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8766 8767 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 8768 8769 /* set the timestamp */ 8770 first->time_stamp = jiffies; 8771 8772 skb_tx_timestamp(skb); 8773 8774 /* 8775 * Force memory writes to complete before letting h/w know there 8776 * are new descriptors to fetch. (Only applicable for weak-ordered 8777 * memory model archs, such as IA-64). 8778 * 8779 * We also need this memory barrier to make certain all of the 8780 * status bits have been updated before next_to_watch is written. 8781 */ 8782 wmb(); 8783 8784 /* set next_to_watch value indicating a packet is present */ 8785 first->next_to_watch = tx_desc; 8786 8787 i++; 8788 if (i == tx_ring->count) 8789 i = 0; 8790 8791 tx_ring->next_to_use = i; 8792 8793 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 8794 8795 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 8796 writel(i, tx_ring->tail); 8797 } 8798 8799 return 0; 8800 dma_error: 8801 dev_err(tx_ring->dev, "TX DMA map failed\n"); 8802 8803 /* clear dma mappings for failed tx_buffer_info map */ 8804 for (;;) { 8805 tx_buffer = &tx_ring->tx_buffer_info[i]; 8806 if (dma_unmap_len(tx_buffer, len)) 8807 dma_unmap_page(tx_ring->dev, 8808 dma_unmap_addr(tx_buffer, dma), 8809 dma_unmap_len(tx_buffer, len), 8810 DMA_TO_DEVICE); 8811 dma_unmap_len_set(tx_buffer, len, 0); 8812 if (tx_buffer == first) 8813 break; 8814 if (i == 0) 8815 i += tx_ring->count; 8816 i--; 8817 } 8818 8819 dev_kfree_skb_any(first->skb); 8820 first->skb = NULL; 8821 8822 tx_ring->next_to_use = i; 8823 8824 return -1; 8825 } 8826 8827 static void ixgbe_atr(struct ixgbe_ring *ring, 8828 struct ixgbe_tx_buffer *first) 8829 { 8830 struct ixgbe_q_vector *q_vector = ring->q_vector; 8831 union ixgbe_atr_hash_dword input = { .dword = 0 }; 8832 union ixgbe_atr_hash_dword common = { .dword = 0 }; 8833 union { 8834 unsigned char *network; 8835 struct iphdr *ipv4; 8836 struct ipv6hdr *ipv6; 8837 } hdr; 8838 struct tcphdr *th; 8839 unsigned int hlen; 8840 struct sk_buff *skb; 8841 __be16 vlan_id; 8842 int l4_proto; 8843 8844 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 8845 if (!q_vector) 8846 return; 8847 8848 /* do nothing if sampling is disabled */ 8849 if (!ring->atr_sample_rate) 8850 return; 8851 8852 ring->atr_count++; 8853 8854 /* currently only IPv4/IPv6 with TCP is supported */ 8855 if ((first->protocol != htons(ETH_P_IP)) && 8856 (first->protocol != htons(ETH_P_IPV6))) 8857 return; 8858 8859 /* snag network header to get L4 type and address */ 8860 skb = first->skb; 8861 hdr.network = skb_network_header(skb); 8862 if (unlikely(hdr.network <= skb->data)) 8863 return; 8864 if (skb->encapsulation && 8865 first->protocol == htons(ETH_P_IP) && 8866 hdr.ipv4->protocol == IPPROTO_UDP) { 8867 struct ixgbe_adapter *adapter = q_vector->adapter; 8868 8869 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8870 vxlan_headroom(0))) 8871 return; 8872 8873 /* verify the port is recognized as VXLAN */ 8874 if (adapter->vxlan_port && 8875 udp_hdr(skb)->dest == adapter->vxlan_port) 8876 hdr.network = skb_inner_network_header(skb); 8877 8878 if (adapter->geneve_port && 8879 udp_hdr(skb)->dest == adapter->geneve_port) 8880 hdr.network = skb_inner_network_header(skb); 8881 } 8882 8883 /* Make sure we have at least [minimum IPv4 header + TCP] 8884 * or [IPv6 header] bytes 8885 */ 8886 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40)) 8887 return; 8888 8889 /* Currently only IPv4/IPv6 with TCP is supported */ 8890 switch (hdr.ipv4->version) { 8891 case IPVERSION: 8892 /* access ihl as u8 to avoid unaligned access on ia64 */ 8893 hlen = (hdr.network[0] & 0x0F) << 2; 8894 l4_proto = hdr.ipv4->protocol; 8895 break; 8896 case 6: 8897 hlen = hdr.network - skb->data; 8898 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 8899 hlen -= hdr.network - skb->data; 8900 break; 8901 default: 8902 return; 8903 } 8904 8905 if (l4_proto != IPPROTO_TCP) 8906 return; 8907 8908 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8909 hlen + sizeof(struct tcphdr))) 8910 return; 8911 8912 th = (struct tcphdr *)(hdr.network + hlen); 8913 8914 /* skip this packet since the socket is closing */ 8915 if (th->fin) 8916 return; 8917 8918 /* sample on all syn packets or once every atr sample count */ 8919 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 8920 return; 8921 8922 /* reset sample count */ 8923 ring->atr_count = 0; 8924 8925 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 8926 8927 /* 8928 * src and dst are inverted, think how the receiver sees them 8929 * 8930 * The input is broken into two sections, a non-compressed section 8931 * containing vm_pool, vlan_id, and flow_type. The rest of the data 8932 * is XORed together and stored in the compressed dword. 8933 */ 8934 input.formatted.vlan_id = vlan_id; 8935 8936 /* 8937 * since src port and flex bytes occupy the same word XOR them together 8938 * and write the value to source port portion of compressed dword 8939 */ 8940 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 8941 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 8942 else 8943 common.port.src ^= th->dest ^ first->protocol; 8944 common.port.dst ^= th->source; 8945 8946 switch (hdr.ipv4->version) { 8947 case IPVERSION: 8948 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 8949 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 8950 break; 8951 case 6: 8952 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 8953 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 8954 hdr.ipv6->saddr.s6_addr32[1] ^ 8955 hdr.ipv6->saddr.s6_addr32[2] ^ 8956 hdr.ipv6->saddr.s6_addr32[3] ^ 8957 hdr.ipv6->daddr.s6_addr32[0] ^ 8958 hdr.ipv6->daddr.s6_addr32[1] ^ 8959 hdr.ipv6->daddr.s6_addr32[2] ^ 8960 hdr.ipv6->daddr.s6_addr32[3]; 8961 break; 8962 default: 8963 break; 8964 } 8965 8966 if (hdr.network != skb_network_header(skb)) 8967 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 8968 8969 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 8970 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 8971 input, common, ring->queue_index); 8972 } 8973 8974 #ifdef IXGBE_FCOE 8975 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 8976 struct net_device *sb_dev) 8977 { 8978 struct ixgbe_adapter *adapter; 8979 struct ixgbe_ring_feature *f; 8980 int txq; 8981 8982 if (sb_dev) { 8983 u8 tc = netdev_get_prio_tc_map(dev, skb->priority); 8984 struct net_device *vdev = sb_dev; 8985 8986 txq = vdev->tc_to_txq[tc].offset; 8987 txq += reciprocal_scale(skb_get_hash(skb), 8988 vdev->tc_to_txq[tc].count); 8989 8990 return txq; 8991 } 8992 8993 /* 8994 * only execute the code below if protocol is FCoE 8995 * or FIP and we have FCoE enabled on the adapter 8996 */ 8997 switch (vlan_get_protocol(skb)) { 8998 case htons(ETH_P_FCOE): 8999 case htons(ETH_P_FIP): 9000 adapter = netdev_priv(dev); 9001 9002 if (!sb_dev && (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) 9003 break; 9004 fallthrough; 9005 default: 9006 return netdev_pick_tx(dev, skb, sb_dev); 9007 } 9008 9009 f = &adapter->ring_feature[RING_F_FCOE]; 9010 9011 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 9012 smp_processor_id(); 9013 9014 while (txq >= f->indices) 9015 txq -= f->indices; 9016 9017 return txq + f->offset; 9018 } 9019 9020 #endif 9021 int ixgbe_xmit_xdp_ring(struct ixgbe_ring *ring, 9022 struct xdp_frame *xdpf) 9023 { 9024 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 9025 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 9026 u16 i = 0, index = ring->next_to_use; 9027 struct ixgbe_tx_buffer *tx_head = &ring->tx_buffer_info[index]; 9028 struct ixgbe_tx_buffer *tx_buff = tx_head; 9029 union ixgbe_adv_tx_desc *tx_desc = IXGBE_TX_DESC(ring, index); 9030 u32 cmd_type, len = xdpf->len; 9031 void *data = xdpf->data; 9032 9033 if (unlikely(ixgbe_desc_unused(ring) < 1 + nr_frags)) 9034 return IXGBE_XDP_CONSUMED; 9035 9036 tx_head->bytecount = xdp_get_frame_len(xdpf); 9037 tx_head->gso_segs = 1; 9038 tx_head->xdpf = xdpf; 9039 9040 tx_desc->read.olinfo_status = 9041 cpu_to_le32(tx_head->bytecount << IXGBE_ADVTXD_PAYLEN_SHIFT); 9042 9043 for (;;) { 9044 dma_addr_t dma; 9045 9046 dma = dma_map_single(ring->dev, data, len, DMA_TO_DEVICE); 9047 if (dma_mapping_error(ring->dev, dma)) 9048 goto unmap; 9049 9050 dma_unmap_len_set(tx_buff, len, len); 9051 dma_unmap_addr_set(tx_buff, dma, dma); 9052 9053 cmd_type = IXGBE_ADVTXD_DTYP_DATA | IXGBE_ADVTXD_DCMD_DEXT | 9054 IXGBE_ADVTXD_DCMD_IFCS | len; 9055 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 9056 tx_desc->read.buffer_addr = cpu_to_le64(dma); 9057 tx_buff->protocol = 0; 9058 9059 if (++index == ring->count) 9060 index = 0; 9061 9062 if (i == nr_frags) 9063 break; 9064 9065 tx_buff = &ring->tx_buffer_info[index]; 9066 tx_desc = IXGBE_TX_DESC(ring, index); 9067 tx_desc->read.olinfo_status = 0; 9068 9069 data = skb_frag_address(&sinfo->frags[i]); 9070 len = skb_frag_size(&sinfo->frags[i]); 9071 i++; 9072 } 9073 /* put descriptor type bits */ 9074 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD); 9075 9076 /* Avoid any potential race with xdp_xmit and cleanup */ 9077 smp_wmb(); 9078 9079 tx_head->next_to_watch = tx_desc; 9080 ring->next_to_use = index; 9081 9082 return IXGBE_XDP_TX; 9083 9084 unmap: 9085 for (;;) { 9086 tx_buff = &ring->tx_buffer_info[index]; 9087 if (dma_unmap_len(tx_buff, len)) 9088 dma_unmap_page(ring->dev, dma_unmap_addr(tx_buff, dma), 9089 dma_unmap_len(tx_buff, len), 9090 DMA_TO_DEVICE); 9091 dma_unmap_len_set(tx_buff, len, 0); 9092 if (tx_buff == tx_head) 9093 break; 9094 9095 if (!index) 9096 index += ring->count; 9097 index--; 9098 } 9099 9100 return IXGBE_XDP_CONSUMED; 9101 } 9102 9103 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 9104 struct ixgbe_adapter *adapter, 9105 struct ixgbe_ring *tx_ring) 9106 { 9107 struct ixgbe_tx_buffer *first; 9108 int tso; 9109 u32 tx_flags = 0; 9110 unsigned short f; 9111 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 9112 struct ixgbe_ipsec_tx_data ipsec_tx = { 0 }; 9113 __be16 protocol = skb->protocol; 9114 u8 hdr_len = 0; 9115 9116 /* 9117 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 9118 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 9119 * + 2 desc gap to keep tail from touching head, 9120 * + 1 desc for context descriptor, 9121 * otherwise try next time 9122 */ 9123 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 9124 count += TXD_USE_COUNT(skb_frag_size( 9125 &skb_shinfo(skb)->frags[f])); 9126 9127 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 9128 tx_ring->tx_stats.tx_busy++; 9129 return NETDEV_TX_BUSY; 9130 } 9131 9132 /* record the location of the first descriptor for this packet */ 9133 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 9134 first->skb = skb; 9135 first->bytecount = skb->len; 9136 first->gso_segs = 1; 9137 9138 /* if we have a HW VLAN tag being added default to the HW one */ 9139 if (skb_vlan_tag_present(skb)) { 9140 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 9141 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 9142 /* else if it is a SW VLAN check the next protocol and store the tag */ 9143 } else if (protocol == htons(ETH_P_8021Q)) { 9144 struct vlan_hdr *vhdr, _vhdr; 9145 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 9146 if (!vhdr) 9147 goto out_drop; 9148 9149 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 9150 IXGBE_TX_FLAGS_VLAN_SHIFT; 9151 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 9152 } 9153 protocol = vlan_get_protocol(skb); 9154 9155 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 9156 adapter->ptp_clock) { 9157 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 9158 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 9159 &adapter->state)) { 9160 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 9161 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 9162 9163 /* schedule check for Tx timestamp */ 9164 adapter->ptp_tx_skb = skb_get(skb); 9165 adapter->ptp_tx_start = jiffies; 9166 schedule_work(&adapter->ptp_tx_work); 9167 } else { 9168 adapter->tx_hwtstamp_skipped++; 9169 } 9170 } 9171 9172 #ifdef CONFIG_PCI_IOV 9173 /* 9174 * Use the l2switch_enable flag - would be false if the DMA 9175 * Tx switch had been disabled. 9176 */ 9177 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 9178 tx_flags |= IXGBE_TX_FLAGS_CC; 9179 9180 #endif 9181 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 9182 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 9183 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 9184 (skb->priority != TC_PRIO_CONTROL))) { 9185 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 9186 tx_flags |= (skb->priority & 0x7) << 9187 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 9188 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 9189 struct vlan_ethhdr *vhdr; 9190 9191 if (skb_cow_head(skb, 0)) 9192 goto out_drop; 9193 vhdr = skb_vlan_eth_hdr(skb); 9194 vhdr->h_vlan_TCI = htons(tx_flags >> 9195 IXGBE_TX_FLAGS_VLAN_SHIFT); 9196 } else { 9197 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 9198 } 9199 } 9200 9201 /* record initial flags and protocol */ 9202 first->tx_flags = tx_flags; 9203 first->protocol = protocol; 9204 9205 #ifdef IXGBE_FCOE 9206 /* setup tx offload for FCoE */ 9207 if ((protocol == htons(ETH_P_FCOE)) && 9208 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 9209 tso = ixgbe_fso(tx_ring, first, &hdr_len); 9210 if (tso < 0) 9211 goto out_drop; 9212 9213 goto xmit_fcoe; 9214 } 9215 9216 #endif /* IXGBE_FCOE */ 9217 9218 #ifdef CONFIG_IXGBE_IPSEC 9219 if (xfrm_offload(skb) && 9220 !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx)) 9221 goto out_drop; 9222 #endif 9223 tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx); 9224 if (tso < 0) 9225 goto out_drop; 9226 else if (!tso) 9227 ixgbe_tx_csum(tx_ring, first, &ipsec_tx); 9228 9229 /* add the ATR filter if ATR is on */ 9230 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 9231 ixgbe_atr(tx_ring, first); 9232 9233 #ifdef IXGBE_FCOE 9234 xmit_fcoe: 9235 #endif /* IXGBE_FCOE */ 9236 if (ixgbe_tx_map(tx_ring, first, hdr_len)) 9237 goto cleanup_tx_timestamp; 9238 9239 return NETDEV_TX_OK; 9240 9241 out_drop: 9242 dev_kfree_skb_any(first->skb); 9243 first->skb = NULL; 9244 cleanup_tx_timestamp: 9245 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) { 9246 dev_kfree_skb_any(adapter->ptp_tx_skb); 9247 adapter->ptp_tx_skb = NULL; 9248 cancel_work_sync(&adapter->ptp_tx_work); 9249 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state); 9250 } 9251 9252 return NETDEV_TX_OK; 9253 } 9254 9255 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 9256 struct net_device *netdev, 9257 struct ixgbe_ring *ring) 9258 { 9259 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9260 struct ixgbe_ring *tx_ring; 9261 9262 /* 9263 * The minimum packet size for olinfo paylen is 17 so pad the skb 9264 * in order to meet this minimum size requirement. 9265 */ 9266 if (skb_put_padto(skb, 17)) 9267 return NETDEV_TX_OK; 9268 9269 tx_ring = ring ? ring : adapter->tx_ring[skb_get_queue_mapping(skb)]; 9270 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &tx_ring->state))) 9271 return NETDEV_TX_BUSY; 9272 9273 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 9274 } 9275 9276 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 9277 struct net_device *netdev) 9278 { 9279 return __ixgbe_xmit_frame(skb, netdev, NULL); 9280 } 9281 9282 /** 9283 * ixgbe_set_mac - Change the Ethernet Address of the NIC 9284 * @netdev: network interface device structure 9285 * @p: pointer to an address structure 9286 * 9287 * Returns 0 on success, negative on failure 9288 **/ 9289 static int ixgbe_set_mac(struct net_device *netdev, void *p) 9290 { 9291 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9292 struct ixgbe_hw *hw = &adapter->hw; 9293 struct sockaddr *addr = p; 9294 9295 if (!is_valid_ether_addr(addr->sa_data)) 9296 return -EADDRNOTAVAIL; 9297 9298 eth_hw_addr_set(netdev, addr->sa_data); 9299 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 9300 9301 ixgbe_mac_set_default_filter(adapter); 9302 9303 return 0; 9304 } 9305 9306 static int 9307 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 9308 { 9309 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9310 struct ixgbe_hw *hw = &adapter->hw; 9311 u16 value; 9312 int rc; 9313 9314 if (adapter->mii_bus) { 9315 int regnum = addr; 9316 9317 if (devad != MDIO_DEVAD_NONE) 9318 return mdiobus_c45_read(adapter->mii_bus, prtad, 9319 devad, regnum); 9320 9321 return mdiobus_read(adapter->mii_bus, prtad, regnum); 9322 } 9323 9324 if (prtad != hw->phy.mdio.prtad) 9325 return -EINVAL; 9326 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 9327 if (!rc) 9328 rc = value; 9329 return rc; 9330 } 9331 9332 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 9333 u16 addr, u16 value) 9334 { 9335 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9336 struct ixgbe_hw *hw = &adapter->hw; 9337 9338 if (adapter->mii_bus) { 9339 int regnum = addr; 9340 9341 if (devad != MDIO_DEVAD_NONE) 9342 return mdiobus_c45_write(adapter->mii_bus, prtad, devad, 9343 regnum, value); 9344 9345 return mdiobus_write(adapter->mii_bus, prtad, regnum, value); 9346 } 9347 9348 if (prtad != hw->phy.mdio.prtad) 9349 return -EINVAL; 9350 return hw->phy.ops.write_reg(hw, addr, devad, value); 9351 } 9352 9353 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 9354 { 9355 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9356 9357 switch (cmd) { 9358 case SIOCSHWTSTAMP: 9359 return ixgbe_ptp_set_ts_config(adapter, req); 9360 case SIOCGHWTSTAMP: 9361 return ixgbe_ptp_get_ts_config(adapter, req); 9362 case SIOCGMIIPHY: 9363 if (!adapter->hw.phy.ops.read_reg) 9364 return -EOPNOTSUPP; 9365 fallthrough; 9366 default: 9367 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 9368 } 9369 } 9370 9371 /** 9372 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 9373 * netdev->dev_addrs 9374 * @dev: network interface device structure 9375 * 9376 * Returns non-zero on failure 9377 **/ 9378 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 9379 { 9380 int err = 0; 9381 struct ixgbe_adapter *adapter = netdev_priv(dev); 9382 struct ixgbe_hw *hw = &adapter->hw; 9383 9384 if (is_valid_ether_addr(hw->mac.san_addr)) { 9385 rtnl_lock(); 9386 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 9387 rtnl_unlock(); 9388 9389 /* update SAN MAC vmdq pool selection */ 9390 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 9391 } 9392 return err; 9393 } 9394 9395 /** 9396 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 9397 * netdev->dev_addrs 9398 * @dev: network interface device structure 9399 * 9400 * Returns non-zero on failure 9401 **/ 9402 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 9403 { 9404 int err = 0; 9405 struct ixgbe_adapter *adapter = netdev_priv(dev); 9406 struct ixgbe_mac_info *mac = &adapter->hw.mac; 9407 9408 if (is_valid_ether_addr(mac->san_addr)) { 9409 rtnl_lock(); 9410 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 9411 rtnl_unlock(); 9412 } 9413 return err; 9414 } 9415 9416 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats, 9417 struct ixgbe_ring *ring) 9418 { 9419 u64 bytes, packets; 9420 unsigned int start; 9421 9422 if (ring) { 9423 do { 9424 start = u64_stats_fetch_begin(&ring->syncp); 9425 packets = ring->stats.packets; 9426 bytes = ring->stats.bytes; 9427 } while (u64_stats_fetch_retry(&ring->syncp, start)); 9428 stats->tx_packets += packets; 9429 stats->tx_bytes += bytes; 9430 } 9431 } 9432 9433 static void ixgbe_get_stats64(struct net_device *netdev, 9434 struct rtnl_link_stats64 *stats) 9435 { 9436 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9437 int i; 9438 9439 rcu_read_lock(); 9440 for (i = 0; i < adapter->num_rx_queues; i++) { 9441 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]); 9442 u64 bytes, packets; 9443 unsigned int start; 9444 9445 if (ring) { 9446 do { 9447 start = u64_stats_fetch_begin(&ring->syncp); 9448 packets = ring->stats.packets; 9449 bytes = ring->stats.bytes; 9450 } while (u64_stats_fetch_retry(&ring->syncp, start)); 9451 stats->rx_packets += packets; 9452 stats->rx_bytes += bytes; 9453 } 9454 } 9455 9456 for (i = 0; i < adapter->num_tx_queues; i++) { 9457 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]); 9458 9459 ixgbe_get_ring_stats64(stats, ring); 9460 } 9461 for (i = 0; i < adapter->num_xdp_queues; i++) { 9462 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]); 9463 9464 ixgbe_get_ring_stats64(stats, ring); 9465 } 9466 rcu_read_unlock(); 9467 9468 /* following stats updated by ixgbe_watchdog_task() */ 9469 stats->multicast = netdev->stats.multicast; 9470 stats->rx_errors = netdev->stats.rx_errors; 9471 stats->rx_length_errors = netdev->stats.rx_length_errors; 9472 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 9473 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 9474 } 9475 9476 static int ixgbe_ndo_get_vf_stats(struct net_device *netdev, int vf, 9477 struct ifla_vf_stats *vf_stats) 9478 { 9479 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9480 9481 if (vf < 0 || vf >= adapter->num_vfs) 9482 return -EINVAL; 9483 9484 vf_stats->rx_packets = adapter->vfinfo[vf].vfstats.gprc; 9485 vf_stats->rx_bytes = adapter->vfinfo[vf].vfstats.gorc; 9486 vf_stats->tx_packets = adapter->vfinfo[vf].vfstats.gptc; 9487 vf_stats->tx_bytes = adapter->vfinfo[vf].vfstats.gotc; 9488 vf_stats->multicast = adapter->vfinfo[vf].vfstats.mprc; 9489 9490 return 0; 9491 } 9492 9493 #ifdef CONFIG_IXGBE_DCB 9494 /** 9495 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 9496 * @adapter: pointer to ixgbe_adapter 9497 * @tc: number of traffic classes currently enabled 9498 * 9499 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 9500 * 802.1Q priority maps to a packet buffer that exists. 9501 */ 9502 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 9503 { 9504 struct ixgbe_hw *hw = &adapter->hw; 9505 u32 reg, rsave; 9506 int i; 9507 9508 /* 82598 have a static priority to TC mapping that can not 9509 * be changed so no validation is needed. 9510 */ 9511 if (hw->mac.type == ixgbe_mac_82598EB) 9512 return; 9513 9514 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 9515 rsave = reg; 9516 9517 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 9518 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 9519 9520 /* If up2tc is out of bounds default to zero */ 9521 if (up2tc > tc) 9522 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 9523 } 9524 9525 if (reg != rsave) 9526 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 9527 9528 return; 9529 } 9530 9531 /** 9532 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 9533 * @adapter: Pointer to adapter struct 9534 * 9535 * Populate the netdev user priority to tc map 9536 */ 9537 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 9538 { 9539 struct net_device *dev = adapter->netdev; 9540 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 9541 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 9542 u8 prio; 9543 9544 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 9545 u8 tc = 0; 9546 9547 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 9548 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 9549 else if (ets) 9550 tc = ets->prio_tc[prio]; 9551 9552 netdev_set_prio_tc_map(dev, prio, tc); 9553 } 9554 } 9555 9556 #endif /* CONFIG_IXGBE_DCB */ 9557 static int ixgbe_reassign_macvlan_pool(struct net_device *vdev, 9558 struct netdev_nested_priv *priv) 9559 { 9560 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data; 9561 struct ixgbe_fwd_adapter *accel; 9562 int pool; 9563 9564 /* we only care about macvlans... */ 9565 if (!netif_is_macvlan(vdev)) 9566 return 0; 9567 9568 /* that have hardware offload enabled... */ 9569 accel = macvlan_accel_priv(vdev); 9570 if (!accel) 9571 return 0; 9572 9573 /* If we can relocate to a different bit do so */ 9574 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 9575 if (pool < adapter->num_rx_pools) { 9576 set_bit(pool, adapter->fwd_bitmask); 9577 accel->pool = pool; 9578 return 0; 9579 } 9580 9581 /* if we cannot find a free pool then disable the offload */ 9582 netdev_err(vdev, "L2FW offload disabled due to lack of queue resources\n"); 9583 macvlan_release_l2fw_offload(vdev); 9584 9585 /* unbind the queues and drop the subordinate channel config */ 9586 netdev_unbind_sb_channel(adapter->netdev, vdev); 9587 netdev_set_sb_channel(vdev, 0); 9588 9589 kfree(accel); 9590 9591 return 0; 9592 } 9593 9594 static void ixgbe_defrag_macvlan_pools(struct net_device *dev) 9595 { 9596 struct ixgbe_adapter *adapter = netdev_priv(dev); 9597 struct netdev_nested_priv priv = { 9598 .data = (void *)adapter, 9599 }; 9600 9601 /* flush any stale bits out of the fwd bitmask */ 9602 bitmap_clear(adapter->fwd_bitmask, 1, 63); 9603 9604 /* walk through upper devices reassigning pools */ 9605 netdev_walk_all_upper_dev_rcu(dev, ixgbe_reassign_macvlan_pool, 9606 &priv); 9607 } 9608 9609 /** 9610 * ixgbe_setup_tc - configure net_device for multiple traffic classes 9611 * 9612 * @dev: net device to configure 9613 * @tc: number of traffic classes to enable 9614 */ 9615 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 9616 { 9617 struct ixgbe_adapter *adapter = netdev_priv(dev); 9618 struct ixgbe_hw *hw = &adapter->hw; 9619 9620 /* Hardware supports up to 8 traffic classes */ 9621 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 9622 return -EINVAL; 9623 9624 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 9625 return -EINVAL; 9626 9627 /* Hardware has to reinitialize queues and interrupts to 9628 * match packet buffer alignment. Unfortunately, the 9629 * hardware is not flexible enough to do this dynamically. 9630 */ 9631 if (netif_running(dev)) 9632 ixgbe_close(dev); 9633 else 9634 ixgbe_reset(adapter); 9635 9636 ixgbe_clear_interrupt_scheme(adapter); 9637 9638 #ifdef CONFIG_IXGBE_DCB 9639 if (tc) { 9640 if (adapter->xdp_prog) { 9641 e_warn(probe, "DCB is not supported with XDP\n"); 9642 9643 ixgbe_init_interrupt_scheme(adapter); 9644 if (netif_running(dev)) 9645 ixgbe_open(dev); 9646 return -EINVAL; 9647 } 9648 9649 netdev_set_num_tc(dev, tc); 9650 ixgbe_set_prio_tc_map(adapter); 9651 9652 adapter->hw_tcs = tc; 9653 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 9654 9655 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 9656 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 9657 adapter->hw.fc.requested_mode = ixgbe_fc_none; 9658 } 9659 } else { 9660 netdev_reset_tc(dev); 9661 9662 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 9663 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 9664 9665 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 9666 adapter->hw_tcs = tc; 9667 9668 adapter->temp_dcb_cfg.pfc_mode_enable = false; 9669 adapter->dcb_cfg.pfc_mode_enable = false; 9670 } 9671 9672 ixgbe_validate_rtr(adapter, tc); 9673 9674 #endif /* CONFIG_IXGBE_DCB */ 9675 ixgbe_init_interrupt_scheme(adapter); 9676 9677 ixgbe_defrag_macvlan_pools(dev); 9678 9679 if (netif_running(dev)) 9680 return ixgbe_open(dev); 9681 9682 return 0; 9683 } 9684 9685 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, 9686 struct tc_cls_u32_offload *cls) 9687 { 9688 u32 hdl = cls->knode.handle; 9689 u32 uhtid = TC_U32_USERHTID(cls->knode.handle); 9690 u32 loc = cls->knode.handle & 0xfffff; 9691 int err = 0, i, j; 9692 struct ixgbe_jump_table *jump = NULL; 9693 9694 if (loc > IXGBE_MAX_HW_ENTRIES) 9695 return -EINVAL; 9696 9697 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) 9698 return -EINVAL; 9699 9700 /* Clear this filter in the link data it is associated with */ 9701 if (uhtid != 0x800) { 9702 jump = adapter->jump_tables[uhtid]; 9703 if (!jump) 9704 return -EINVAL; 9705 if (!test_bit(loc - 1, jump->child_loc_map)) 9706 return -EINVAL; 9707 clear_bit(loc - 1, jump->child_loc_map); 9708 } 9709 9710 /* Check if the filter being deleted is a link */ 9711 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9712 jump = adapter->jump_tables[i]; 9713 if (jump && jump->link_hdl == hdl) { 9714 /* Delete filters in the hardware in the child hash 9715 * table associated with this link 9716 */ 9717 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) { 9718 if (!test_bit(j, jump->child_loc_map)) 9719 continue; 9720 spin_lock(&adapter->fdir_perfect_lock); 9721 err = ixgbe_update_ethtool_fdir_entry(adapter, 9722 NULL, 9723 j + 1); 9724 spin_unlock(&adapter->fdir_perfect_lock); 9725 clear_bit(j, jump->child_loc_map); 9726 } 9727 /* Remove resources for this link */ 9728 kfree(jump->input); 9729 kfree(jump->mask); 9730 kfree(jump); 9731 adapter->jump_tables[i] = NULL; 9732 return err; 9733 } 9734 } 9735 9736 spin_lock(&adapter->fdir_perfect_lock); 9737 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); 9738 spin_unlock(&adapter->fdir_perfect_lock); 9739 return err; 9740 } 9741 9742 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, 9743 struct tc_cls_u32_offload *cls) 9744 { 9745 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9746 9747 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9748 return -EINVAL; 9749 9750 /* This ixgbe devices do not support hash tables at the moment 9751 * so abort when given hash tables. 9752 */ 9753 if (cls->hnode.divisor > 0) 9754 return -EINVAL; 9755 9756 set_bit(uhtid - 1, &adapter->tables); 9757 return 0; 9758 } 9759 9760 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, 9761 struct tc_cls_u32_offload *cls) 9762 { 9763 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9764 9765 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9766 return -EINVAL; 9767 9768 clear_bit(uhtid - 1, &adapter->tables); 9769 return 0; 9770 } 9771 9772 #ifdef CONFIG_NET_CLS_ACT 9773 struct upper_walk_data { 9774 struct ixgbe_adapter *adapter; 9775 u64 action; 9776 int ifindex; 9777 u8 queue; 9778 }; 9779 9780 static int get_macvlan_queue(struct net_device *upper, 9781 struct netdev_nested_priv *priv) 9782 { 9783 if (netif_is_macvlan(upper)) { 9784 struct ixgbe_fwd_adapter *vadapter = macvlan_accel_priv(upper); 9785 struct ixgbe_adapter *adapter; 9786 struct upper_walk_data *data; 9787 int ifindex; 9788 9789 data = (struct upper_walk_data *)priv->data; 9790 ifindex = data->ifindex; 9791 adapter = data->adapter; 9792 if (vadapter && upper->ifindex == ifindex) { 9793 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; 9794 data->action = data->queue; 9795 return 1; 9796 } 9797 } 9798 9799 return 0; 9800 } 9801 9802 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, 9803 u8 *queue, u64 *action) 9804 { 9805 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 9806 unsigned int num_vfs = adapter->num_vfs, vf; 9807 struct netdev_nested_priv priv; 9808 struct upper_walk_data data; 9809 struct net_device *upper; 9810 9811 /* redirect to a SRIOV VF */ 9812 for (vf = 0; vf < num_vfs; ++vf) { 9813 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); 9814 if (upper->ifindex == ifindex) { 9815 *queue = vf * __ALIGN_MASK(1, ~vmdq->mask); 9816 *action = vf + 1; 9817 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 9818 return 0; 9819 } 9820 } 9821 9822 /* redirect to a offloaded macvlan netdev */ 9823 data.adapter = adapter; 9824 data.ifindex = ifindex; 9825 data.action = 0; 9826 data.queue = 0; 9827 priv.data = (void *)&data; 9828 if (netdev_walk_all_upper_dev_rcu(adapter->netdev, 9829 get_macvlan_queue, &priv)) { 9830 *action = data.action; 9831 *queue = data.queue; 9832 9833 return 0; 9834 } 9835 9836 return -EINVAL; 9837 } 9838 9839 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9840 struct tcf_exts *exts, u64 *action, u8 *queue) 9841 { 9842 const struct tc_action *a; 9843 int i; 9844 9845 if (!tcf_exts_has_actions(exts)) 9846 return -EINVAL; 9847 9848 tcf_exts_for_each_action(i, a, exts) { 9849 /* Drop action */ 9850 if (is_tcf_gact_shot(a)) { 9851 *action = IXGBE_FDIR_DROP_QUEUE; 9852 *queue = IXGBE_FDIR_DROP_QUEUE; 9853 return 0; 9854 } 9855 9856 /* Redirect to a VF or a offloaded macvlan */ 9857 if (is_tcf_mirred_egress_redirect(a)) { 9858 struct net_device *dev = tcf_mirred_dev(a); 9859 9860 if (!dev) 9861 return -EINVAL; 9862 return handle_redirect_action(adapter, dev->ifindex, 9863 queue, action); 9864 } 9865 9866 return -EINVAL; 9867 } 9868 9869 return -EINVAL; 9870 } 9871 #else 9872 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9873 struct tcf_exts *exts, u64 *action, u8 *queue) 9874 { 9875 return -EINVAL; 9876 } 9877 #endif /* CONFIG_NET_CLS_ACT */ 9878 9879 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, 9880 union ixgbe_atr_input *mask, 9881 struct tc_cls_u32_offload *cls, 9882 struct ixgbe_mat_field *field_ptr, 9883 struct ixgbe_nexthdr *nexthdr) 9884 { 9885 int i, j, off; 9886 __be32 val, m; 9887 bool found_entry = false, found_jump_field = false; 9888 9889 for (i = 0; i < cls->knode.sel->nkeys; i++) { 9890 off = cls->knode.sel->keys[i].off; 9891 val = cls->knode.sel->keys[i].val; 9892 m = cls->knode.sel->keys[i].mask; 9893 9894 for (j = 0; field_ptr[j].val; j++) { 9895 if (field_ptr[j].off == off) { 9896 field_ptr[j].val(input, mask, (__force u32)val, 9897 (__force u32)m); 9898 input->filter.formatted.flow_type |= 9899 field_ptr[j].type; 9900 found_entry = true; 9901 break; 9902 } 9903 } 9904 if (nexthdr) { 9905 if (nexthdr->off == cls->knode.sel->keys[i].off && 9906 nexthdr->val == 9907 (__force u32)cls->knode.sel->keys[i].val && 9908 nexthdr->mask == 9909 (__force u32)cls->knode.sel->keys[i].mask) 9910 found_jump_field = true; 9911 else 9912 continue; 9913 } 9914 } 9915 9916 if (nexthdr && !found_jump_field) 9917 return -EINVAL; 9918 9919 if (!found_entry) 9920 return 0; 9921 9922 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 9923 IXGBE_ATR_L4TYPE_MASK; 9924 9925 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 9926 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 9927 9928 return 0; 9929 } 9930 9931 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, 9932 struct tc_cls_u32_offload *cls) 9933 { 9934 __be16 protocol = cls->common.protocol; 9935 u32 loc = cls->knode.handle & 0xfffff; 9936 struct ixgbe_hw *hw = &adapter->hw; 9937 struct ixgbe_mat_field *field_ptr; 9938 struct ixgbe_fdir_filter *input = NULL; 9939 union ixgbe_atr_input *mask = NULL; 9940 struct ixgbe_jump_table *jump = NULL; 9941 int i, err = -EINVAL; 9942 u8 queue; 9943 u32 uhtid, link_uhtid; 9944 9945 uhtid = TC_U32_USERHTID(cls->knode.handle); 9946 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); 9947 9948 /* At the moment cls_u32 jumps to network layer and skips past 9949 * L2 headers. The canonical method to match L2 frames is to use 9950 * negative values. However this is error prone at best but really 9951 * just broken because there is no way to "know" what sort of hdr 9952 * is in front of the network layer. Fix cls_u32 to support L2 9953 * headers when needed. 9954 */ 9955 if (protocol != htons(ETH_P_IP)) 9956 return err; 9957 9958 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { 9959 e_err(drv, "Location out of range\n"); 9960 return err; 9961 } 9962 9963 /* cls u32 is a graph starting at root node 0x800. The driver tracks 9964 * links and also the fields used to advance the parser across each 9965 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map 9966 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h 9967 * To add support for new nodes update ixgbe_model.h parse structures 9968 * this function _should_ be generic try not to hardcode values here. 9969 */ 9970 if (uhtid == 0x800) { 9971 field_ptr = (adapter->jump_tables[0])->mat; 9972 } else { 9973 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9974 return err; 9975 if (!adapter->jump_tables[uhtid]) 9976 return err; 9977 field_ptr = (adapter->jump_tables[uhtid])->mat; 9978 } 9979 9980 if (!field_ptr) 9981 return err; 9982 9983 /* At this point we know the field_ptr is valid and need to either 9984 * build cls_u32 link or attach filter. Because adding a link to 9985 * a handle that does not exist is invalid and the same for adding 9986 * rules to handles that don't exist. 9987 */ 9988 9989 if (link_uhtid) { 9990 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; 9991 9992 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) 9993 return err; 9994 9995 if (!test_bit(link_uhtid - 1, &adapter->tables)) 9996 return err; 9997 9998 /* Multiple filters as links to the same hash table are not 9999 * supported. To add a new filter with the same next header 10000 * but different match/jump conditions, create a new hash table 10001 * and link to it. 10002 */ 10003 if (adapter->jump_tables[link_uhtid] && 10004 (adapter->jump_tables[link_uhtid])->link_hdl) { 10005 e_err(drv, "Link filter exists for link: %x\n", 10006 link_uhtid); 10007 return err; 10008 } 10009 10010 for (i = 0; nexthdr[i].jump; i++) { 10011 if (nexthdr[i].o != cls->knode.sel->offoff || 10012 nexthdr[i].s != cls->knode.sel->offshift || 10013 nexthdr[i].m != 10014 (__force u32)cls->knode.sel->offmask) 10015 return err; 10016 10017 jump = kzalloc(sizeof(*jump), GFP_KERNEL); 10018 if (!jump) 10019 return -ENOMEM; 10020 input = kzalloc(sizeof(*input), GFP_KERNEL); 10021 if (!input) { 10022 err = -ENOMEM; 10023 goto free_jump; 10024 } 10025 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 10026 if (!mask) { 10027 err = -ENOMEM; 10028 goto free_input; 10029 } 10030 jump->input = input; 10031 jump->mask = mask; 10032 jump->link_hdl = cls->knode.handle; 10033 10034 err = ixgbe_clsu32_build_input(input, mask, cls, 10035 field_ptr, &nexthdr[i]); 10036 if (!err) { 10037 jump->mat = nexthdr[i].jump; 10038 adapter->jump_tables[link_uhtid] = jump; 10039 break; 10040 } else { 10041 kfree(mask); 10042 kfree(input); 10043 kfree(jump); 10044 } 10045 } 10046 return 0; 10047 } 10048 10049 input = kzalloc(sizeof(*input), GFP_KERNEL); 10050 if (!input) 10051 return -ENOMEM; 10052 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 10053 if (!mask) { 10054 err = -ENOMEM; 10055 goto free_input; 10056 } 10057 10058 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { 10059 if ((adapter->jump_tables[uhtid])->input) 10060 memcpy(input, (adapter->jump_tables[uhtid])->input, 10061 sizeof(*input)); 10062 if ((adapter->jump_tables[uhtid])->mask) 10063 memcpy(mask, (adapter->jump_tables[uhtid])->mask, 10064 sizeof(*mask)); 10065 10066 /* Lookup in all child hash tables if this location is already 10067 * filled with a filter 10068 */ 10069 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 10070 struct ixgbe_jump_table *link = adapter->jump_tables[i]; 10071 10072 if (link && (test_bit(loc - 1, link->child_loc_map))) { 10073 e_err(drv, "Filter exists in location: %x\n", 10074 loc); 10075 err = -EINVAL; 10076 goto err_out; 10077 } 10078 } 10079 } 10080 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); 10081 if (err) 10082 goto err_out; 10083 10084 err = parse_tc_actions(adapter, cls->knode.exts, &input->action, 10085 &queue); 10086 if (err < 0) 10087 goto err_out; 10088 10089 input->sw_idx = loc; 10090 10091 spin_lock(&adapter->fdir_perfect_lock); 10092 10093 if (hlist_empty(&adapter->fdir_filter_list)) { 10094 memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); 10095 err = ixgbe_fdir_set_input_mask_82599(hw, mask); 10096 if (err) 10097 goto err_out_w_lock; 10098 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { 10099 err = -EINVAL; 10100 goto err_out_w_lock; 10101 } 10102 10103 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); 10104 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, 10105 input->sw_idx, queue); 10106 if (err) 10107 goto err_out_w_lock; 10108 10109 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 10110 spin_unlock(&adapter->fdir_perfect_lock); 10111 10112 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) 10113 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map); 10114 10115 kfree(mask); 10116 return err; 10117 err_out_w_lock: 10118 spin_unlock(&adapter->fdir_perfect_lock); 10119 err_out: 10120 kfree(mask); 10121 free_input: 10122 kfree(input); 10123 free_jump: 10124 kfree(jump); 10125 return err; 10126 } 10127 10128 static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter, 10129 struct tc_cls_u32_offload *cls_u32) 10130 { 10131 switch (cls_u32->command) { 10132 case TC_CLSU32_NEW_KNODE: 10133 case TC_CLSU32_REPLACE_KNODE: 10134 return ixgbe_configure_clsu32(adapter, cls_u32); 10135 case TC_CLSU32_DELETE_KNODE: 10136 return ixgbe_delete_clsu32(adapter, cls_u32); 10137 case TC_CLSU32_NEW_HNODE: 10138 case TC_CLSU32_REPLACE_HNODE: 10139 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32); 10140 case TC_CLSU32_DELETE_HNODE: 10141 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32); 10142 default: 10143 return -EOPNOTSUPP; 10144 } 10145 } 10146 10147 static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 10148 void *cb_priv) 10149 { 10150 struct ixgbe_adapter *adapter = cb_priv; 10151 10152 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 10153 return -EOPNOTSUPP; 10154 10155 switch (type) { 10156 case TC_SETUP_CLSU32: 10157 return ixgbe_setup_tc_cls_u32(adapter, type_data); 10158 default: 10159 return -EOPNOTSUPP; 10160 } 10161 } 10162 10163 static int ixgbe_setup_tc_mqprio(struct net_device *dev, 10164 struct tc_mqprio_qopt *mqprio) 10165 { 10166 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 10167 return ixgbe_setup_tc(dev, mqprio->num_tc); 10168 } 10169 10170 static LIST_HEAD(ixgbe_block_cb_list); 10171 10172 static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type, 10173 void *type_data) 10174 { 10175 struct ixgbe_adapter *adapter = netdev_priv(dev); 10176 10177 switch (type) { 10178 case TC_SETUP_BLOCK: 10179 return flow_block_cb_setup_simple(type_data, 10180 &ixgbe_block_cb_list, 10181 ixgbe_setup_tc_block_cb, 10182 adapter, adapter, true); 10183 case TC_SETUP_QDISC_MQPRIO: 10184 return ixgbe_setup_tc_mqprio(dev, type_data); 10185 default: 10186 return -EOPNOTSUPP; 10187 } 10188 } 10189 10190 #ifdef CONFIG_PCI_IOV 10191 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 10192 { 10193 struct net_device *netdev = adapter->netdev; 10194 10195 rtnl_lock(); 10196 ixgbe_setup_tc(netdev, adapter->hw_tcs); 10197 rtnl_unlock(); 10198 } 10199 10200 #endif 10201 void ixgbe_do_reset(struct net_device *netdev) 10202 { 10203 struct ixgbe_adapter *adapter = netdev_priv(netdev); 10204 10205 if (netif_running(netdev)) 10206 ixgbe_reinit_locked(adapter); 10207 else 10208 ixgbe_reset(adapter); 10209 } 10210 10211 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 10212 netdev_features_t features) 10213 { 10214 struct ixgbe_adapter *adapter = netdev_priv(netdev); 10215 10216 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 10217 if (!(features & NETIF_F_RXCSUM)) 10218 features &= ~NETIF_F_LRO; 10219 10220 /* Turn off LRO if not RSC capable */ 10221 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 10222 features &= ~NETIF_F_LRO; 10223 10224 if (adapter->xdp_prog && (features & NETIF_F_LRO)) { 10225 e_dev_err("LRO is not supported with XDP\n"); 10226 features &= ~NETIF_F_LRO; 10227 } 10228 10229 return features; 10230 } 10231 10232 static void ixgbe_reset_l2fw_offload(struct ixgbe_adapter *adapter) 10233 { 10234 int rss = min_t(int, ixgbe_max_rss_indices(adapter), 10235 num_online_cpus()); 10236 10237 /* go back to full RSS if we're not running SR-IOV */ 10238 if (!adapter->ring_feature[RING_F_VMDQ].offset) 10239 adapter->flags &= ~(IXGBE_FLAG_VMDQ_ENABLED | 10240 IXGBE_FLAG_SRIOV_ENABLED); 10241 10242 adapter->ring_feature[RING_F_RSS].limit = rss; 10243 adapter->ring_feature[RING_F_VMDQ].limit = 1; 10244 10245 ixgbe_setup_tc(adapter->netdev, adapter->hw_tcs); 10246 } 10247 10248 static int ixgbe_set_features(struct net_device *netdev, 10249 netdev_features_t features) 10250 { 10251 struct ixgbe_adapter *adapter = netdev_priv(netdev); 10252 netdev_features_t changed = netdev->features ^ features; 10253 bool need_reset = false; 10254 10255 /* Make sure RSC matches LRO, reset if change */ 10256 if (!(features & NETIF_F_LRO)) { 10257 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 10258 need_reset = true; 10259 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 10260 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 10261 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 10262 if (adapter->rx_itr_setting == 1 || 10263 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 10264 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 10265 need_reset = true; 10266 } else if ((changed ^ features) & NETIF_F_LRO) { 10267 e_info(probe, "rx-usecs set too low, " 10268 "disabling RSC\n"); 10269 } 10270 } 10271 10272 /* 10273 * Check if Flow Director n-tuple support or hw_tc support was 10274 * enabled or disabled. If the state changed, we need to reset. 10275 */ 10276 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { 10277 /* turn off ATR, enable perfect filters and reset */ 10278 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 10279 need_reset = true; 10280 10281 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 10282 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 10283 } else { 10284 /* turn off perfect filters, enable ATR and reset */ 10285 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 10286 need_reset = true; 10287 10288 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 10289 10290 /* We cannot enable ATR if SR-IOV is enabled */ 10291 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || 10292 /* We cannot enable ATR if we have 2 or more tcs */ 10293 (adapter->hw_tcs > 1) || 10294 /* We cannot enable ATR if RSS is disabled */ 10295 (adapter->ring_feature[RING_F_RSS].limit <= 1) || 10296 /* A sample rate of 0 indicates ATR disabled */ 10297 (!adapter->atr_sample_rate)) 10298 ; /* do nothing not supported */ 10299 else /* otherwise supported and set the flag */ 10300 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 10301 } 10302 10303 if (changed & NETIF_F_RXALL) 10304 need_reset = true; 10305 10306 netdev->features = features; 10307 10308 if ((changed & NETIF_F_HW_L2FW_DOFFLOAD) && adapter->num_rx_pools > 1) 10309 ixgbe_reset_l2fw_offload(adapter); 10310 else if (need_reset) 10311 ixgbe_do_reset(netdev); 10312 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | 10313 NETIF_F_HW_VLAN_CTAG_FILTER)) 10314 ixgbe_set_rx_mode(netdev); 10315 10316 return 1; 10317 } 10318 10319 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 10320 struct net_device *dev, 10321 const unsigned char *addr, u16 vid, 10322 u16 flags, bool *notified, 10323 struct netlink_ext_ack *extack) 10324 { 10325 /* guarantee we can provide a unique filter for the unicast address */ 10326 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 10327 struct ixgbe_adapter *adapter = netdev_priv(dev); 10328 u16 pool = VMDQ_P(0); 10329 10330 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) 10331 return -ENOMEM; 10332 } 10333 10334 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 10335 } 10336 10337 /** 10338 * ixgbe_configure_bridge_mode - set various bridge modes 10339 * @adapter: the private structure 10340 * @mode: requested bridge mode 10341 * 10342 * Configure some settings require for various bridge modes. 10343 **/ 10344 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 10345 __u16 mode) 10346 { 10347 struct ixgbe_hw *hw = &adapter->hw; 10348 unsigned int p, num_pools; 10349 u32 vmdctl; 10350 10351 switch (mode) { 10352 case BRIDGE_MODE_VEPA: 10353 /* disable Tx loopback, rely on switch hairpin mode */ 10354 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 10355 10356 /* must enable Rx switching replication to allow multicast 10357 * packet reception on all VFs, and to enable source address 10358 * pruning. 10359 */ 10360 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 10361 vmdctl |= IXGBE_VT_CTL_REPLEN; 10362 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 10363 10364 /* enable Rx source address pruning. Note, this requires 10365 * replication to be enabled or else it does nothing. 10366 */ 10367 num_pools = adapter->num_vfs + adapter->num_rx_pools; 10368 for (p = 0; p < num_pools; p++) { 10369 if (hw->mac.ops.set_source_address_pruning) 10370 hw->mac.ops.set_source_address_pruning(hw, 10371 true, 10372 p); 10373 } 10374 break; 10375 case BRIDGE_MODE_VEB: 10376 /* enable Tx loopback for internal VF/PF communication */ 10377 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 10378 IXGBE_PFDTXGSWC_VT_LBEN); 10379 10380 /* disable Rx switching replication unless we have SR-IOV 10381 * virtual functions 10382 */ 10383 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 10384 if (!adapter->num_vfs) 10385 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 10386 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 10387 10388 /* disable Rx source address pruning, since we don't expect to 10389 * be receiving external loopback of our transmitted frames. 10390 */ 10391 num_pools = adapter->num_vfs + adapter->num_rx_pools; 10392 for (p = 0; p < num_pools; p++) { 10393 if (hw->mac.ops.set_source_address_pruning) 10394 hw->mac.ops.set_source_address_pruning(hw, 10395 false, 10396 p); 10397 } 10398 break; 10399 default: 10400 return -EINVAL; 10401 } 10402 10403 adapter->bridge_mode = mode; 10404 10405 e_info(drv, "enabling bridge mode: %s\n", 10406 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 10407 10408 return 0; 10409 } 10410 10411 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 10412 struct nlmsghdr *nlh, u16 flags, 10413 struct netlink_ext_ack *extack) 10414 { 10415 struct ixgbe_adapter *adapter = netdev_priv(dev); 10416 struct nlattr *attr, *br_spec; 10417 int rem; 10418 10419 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 10420 return -EOPNOTSUPP; 10421 10422 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 10423 if (!br_spec) 10424 return -EINVAL; 10425 10426 nla_for_each_nested_type(attr, IFLA_BRIDGE_MODE, br_spec, rem) { 10427 __u16 mode = nla_get_u16(attr); 10428 int status = ixgbe_configure_bridge_mode(adapter, mode); 10429 10430 if (status) 10431 return status; 10432 10433 break; 10434 } 10435 10436 return 0; 10437 } 10438 10439 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 10440 struct net_device *dev, 10441 u32 filter_mask, int nlflags) 10442 { 10443 struct ixgbe_adapter *adapter = netdev_priv(dev); 10444 10445 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 10446 return 0; 10447 10448 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 10449 adapter->bridge_mode, 0, 0, nlflags, 10450 filter_mask, NULL); 10451 } 10452 10453 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 10454 { 10455 struct ixgbe_adapter *adapter = netdev_priv(pdev); 10456 struct ixgbe_fwd_adapter *accel; 10457 int tcs = adapter->hw_tcs ? : 1; 10458 int pool, err; 10459 10460 if (adapter->xdp_prog) { 10461 e_warn(probe, "L2FW offload is not supported with XDP\n"); 10462 return ERR_PTR(-EINVAL); 10463 } 10464 10465 /* The hardware supported by ixgbe only filters on the destination MAC 10466 * address. In order to avoid issues we only support offloading modes 10467 * where the hardware can actually provide the functionality. 10468 */ 10469 if (!macvlan_supports_dest_filter(vdev)) 10470 return ERR_PTR(-EMEDIUMTYPE); 10471 10472 /* We need to lock down the macvlan to be a single queue device so that 10473 * we can reuse the tc_to_txq field in the macvlan netdev to represent 10474 * the queue mapping to our netdev. 10475 */ 10476 if (netif_is_multiqueue(vdev)) 10477 return ERR_PTR(-ERANGE); 10478 10479 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 10480 if (pool == adapter->num_rx_pools) { 10481 u16 used_pools = adapter->num_vfs + adapter->num_rx_pools; 10482 u16 reserved_pools; 10483 10484 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 10485 adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) || 10486 adapter->num_rx_pools > IXGBE_MAX_MACVLANS) 10487 return ERR_PTR(-EBUSY); 10488 10489 /* Hardware has a limited number of available pools. Each VF, 10490 * and the PF require a pool. Check to ensure we don't 10491 * attempt to use more then the available number of pools. 10492 */ 10493 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 10494 return ERR_PTR(-EBUSY); 10495 10496 /* Enable VMDq flag so device will be set in VM mode */ 10497 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | 10498 IXGBE_FLAG_SRIOV_ENABLED; 10499 10500 /* Try to reserve as many queues per pool as possible, 10501 * we start with the configurations that support 4 queues 10502 * per pools, followed by 2, and then by just 1 per pool. 10503 */ 10504 if (used_pools < 32 && adapter->num_rx_pools < 16) 10505 reserved_pools = min_t(u16, 10506 32 - used_pools, 10507 16 - adapter->num_rx_pools); 10508 else if (adapter->num_rx_pools < 32) 10509 reserved_pools = min_t(u16, 10510 64 - used_pools, 10511 32 - adapter->num_rx_pools); 10512 else 10513 reserved_pools = 64 - used_pools; 10514 10515 10516 if (!reserved_pools) 10517 return ERR_PTR(-EBUSY); 10518 10519 adapter->ring_feature[RING_F_VMDQ].limit += reserved_pools; 10520 10521 /* Force reinit of ring allocation with VMDQ enabled */ 10522 err = ixgbe_setup_tc(pdev, adapter->hw_tcs); 10523 if (err) 10524 return ERR_PTR(err); 10525 10526 if (pool >= adapter->num_rx_pools) 10527 return ERR_PTR(-ENOMEM); 10528 } 10529 10530 accel = kzalloc(sizeof(*accel), GFP_KERNEL); 10531 if (!accel) 10532 return ERR_PTR(-ENOMEM); 10533 10534 set_bit(pool, adapter->fwd_bitmask); 10535 netdev_set_sb_channel(vdev, pool); 10536 accel->pool = pool; 10537 accel->netdev = vdev; 10538 10539 if (!netif_running(pdev)) 10540 return accel; 10541 10542 err = ixgbe_fwd_ring_up(adapter, accel); 10543 if (err) 10544 return ERR_PTR(err); 10545 10546 return accel; 10547 } 10548 10549 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 10550 { 10551 struct ixgbe_fwd_adapter *accel = priv; 10552 struct ixgbe_adapter *adapter = netdev_priv(pdev); 10553 unsigned int rxbase = accel->rx_base_queue; 10554 unsigned int i; 10555 10556 /* delete unicast filter associated with offloaded interface */ 10557 ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr, 10558 VMDQ_P(accel->pool)); 10559 10560 /* Allow remaining Rx packets to get flushed out of the 10561 * Rx FIFO before we drop the netdev for the ring. 10562 */ 10563 usleep_range(10000, 20000); 10564 10565 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 10566 struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i]; 10567 struct ixgbe_q_vector *qv = ring->q_vector; 10568 10569 /* Make sure we aren't processing any packets and clear 10570 * netdev to shut down the ring. 10571 */ 10572 if (netif_running(adapter->netdev)) 10573 napi_synchronize(&qv->napi); 10574 ring->netdev = NULL; 10575 } 10576 10577 /* unbind the queues and drop the subordinate channel config */ 10578 netdev_unbind_sb_channel(pdev, accel->netdev); 10579 netdev_set_sb_channel(accel->netdev, 0); 10580 10581 clear_bit(accel->pool, adapter->fwd_bitmask); 10582 kfree(accel); 10583 } 10584 10585 #define IXGBE_MAX_MAC_HDR_LEN 127 10586 #define IXGBE_MAX_NETWORK_HDR_LEN 511 10587 10588 static netdev_features_t 10589 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 10590 netdev_features_t features) 10591 { 10592 unsigned int network_hdr_len, mac_hdr_len; 10593 10594 /* Make certain the headers can be described by a context descriptor */ 10595 mac_hdr_len = skb_network_offset(skb); 10596 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) 10597 return features & ~(NETIF_F_HW_CSUM | 10598 NETIF_F_SCTP_CRC | 10599 NETIF_F_GSO_UDP_L4 | 10600 NETIF_F_HW_VLAN_CTAG_TX | 10601 NETIF_F_TSO | 10602 NETIF_F_TSO6); 10603 10604 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 10605 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) 10606 return features & ~(NETIF_F_HW_CSUM | 10607 NETIF_F_SCTP_CRC | 10608 NETIF_F_GSO_UDP_L4 | 10609 NETIF_F_TSO | 10610 NETIF_F_TSO6); 10611 10612 /* We can only support IPV4 TSO in tunnels if we can mangle the 10613 * inner IP ID field, so strip TSO if MANGLEID is not supported. 10614 * IPsec offoad sets skb->encapsulation but still can handle 10615 * the TSO, so it's the exception. 10616 */ 10617 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) { 10618 #ifdef CONFIG_IXGBE_IPSEC 10619 if (!secpath_exists(skb)) 10620 #endif 10621 features &= ~NETIF_F_TSO; 10622 } 10623 10624 return features; 10625 } 10626 10627 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog) 10628 { 10629 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 10630 struct ixgbe_adapter *adapter = netdev_priv(dev); 10631 struct bpf_prog *old_prog; 10632 bool need_reset; 10633 int num_queues; 10634 10635 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 10636 return -EINVAL; 10637 10638 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) 10639 return -EINVAL; 10640 10641 /* verify ixgbe ring attributes are sufficient for XDP */ 10642 for (i = 0; i < adapter->num_rx_queues; i++) { 10643 struct ixgbe_ring *ring = adapter->rx_ring[i]; 10644 10645 if (ring_is_rsc_enabled(ring)) 10646 return -EINVAL; 10647 10648 if (frame_size > ixgbe_rx_bufsz(ring)) 10649 return -EINVAL; 10650 } 10651 10652 /* if the number of cpus is much larger than the maximum of queues, 10653 * we should stop it and then return with ENOMEM like before. 10654 */ 10655 if (nr_cpu_ids > IXGBE_MAX_XDP_QS * 2) 10656 return -ENOMEM; 10657 10658 old_prog = xchg(&adapter->xdp_prog, prog); 10659 need_reset = (!!prog != !!old_prog); 10660 10661 /* If transitioning XDP modes reconfigure rings */ 10662 if (need_reset) { 10663 int err; 10664 10665 if (!prog) 10666 /* Wait until ndo_xsk_wakeup completes. */ 10667 synchronize_rcu(); 10668 err = ixgbe_setup_tc(dev, adapter->hw_tcs); 10669 10670 if (err) 10671 return -EINVAL; 10672 if (!prog) 10673 xdp_features_clear_redirect_target(dev); 10674 } else { 10675 for (i = 0; i < adapter->num_rx_queues; i++) { 10676 WRITE_ONCE(adapter->rx_ring[i]->xdp_prog, 10677 adapter->xdp_prog); 10678 } 10679 } 10680 10681 if (old_prog) 10682 bpf_prog_put(old_prog); 10683 10684 /* Kick start the NAPI context if there is an AF_XDP socket open 10685 * on that queue id. This so that receiving will start. 10686 */ 10687 if (need_reset && prog) { 10688 num_queues = min_t(int, adapter->num_rx_queues, 10689 adapter->num_xdp_queues); 10690 for (i = 0; i < num_queues; i++) 10691 if (adapter->xdp_ring[i]->xsk_pool) 10692 (void)ixgbe_xsk_wakeup(adapter->netdev, i, 10693 XDP_WAKEUP_RX); 10694 xdp_features_set_redirect_target(dev, true); 10695 } 10696 10697 return 0; 10698 } 10699 10700 static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp) 10701 { 10702 struct ixgbe_adapter *adapter = netdev_priv(dev); 10703 10704 switch (xdp->command) { 10705 case XDP_SETUP_PROG: 10706 return ixgbe_xdp_setup(dev, xdp->prog); 10707 case XDP_SETUP_XSK_POOL: 10708 return ixgbe_xsk_pool_setup(adapter, xdp->xsk.pool, 10709 xdp->xsk.queue_id); 10710 10711 default: 10712 return -EINVAL; 10713 } 10714 } 10715 10716 void ixgbe_xdp_ring_update_tail(struct ixgbe_ring *ring) 10717 { 10718 /* Force memory writes to complete before letting h/w know there 10719 * are new descriptors to fetch. 10720 */ 10721 wmb(); 10722 writel(ring->next_to_use, ring->tail); 10723 } 10724 10725 void ixgbe_xdp_ring_update_tail_locked(struct ixgbe_ring *ring) 10726 { 10727 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 10728 spin_lock(&ring->tx_lock); 10729 ixgbe_xdp_ring_update_tail(ring); 10730 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 10731 spin_unlock(&ring->tx_lock); 10732 } 10733 10734 static int ixgbe_xdp_xmit(struct net_device *dev, int n, 10735 struct xdp_frame **frames, u32 flags) 10736 { 10737 struct ixgbe_adapter *adapter = netdev_priv(dev); 10738 struct ixgbe_ring *ring; 10739 int nxmit = 0; 10740 int i; 10741 10742 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 10743 return -ENETDOWN; 10744 10745 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 10746 return -EINVAL; 10747 10748 /* During program transitions its possible adapter->xdp_prog is assigned 10749 * but ring has not been configured yet. In this case simply abort xmit. 10750 */ 10751 ring = adapter->xdp_prog ? ixgbe_determine_xdp_ring(adapter) : NULL; 10752 if (unlikely(!ring)) 10753 return -ENXIO; 10754 10755 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &ring->state))) 10756 return -ENXIO; 10757 10758 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 10759 spin_lock(&ring->tx_lock); 10760 10761 for (i = 0; i < n; i++) { 10762 struct xdp_frame *xdpf = frames[i]; 10763 int err; 10764 10765 err = ixgbe_xmit_xdp_ring(ring, xdpf); 10766 if (err != IXGBE_XDP_TX) 10767 break; 10768 nxmit++; 10769 } 10770 10771 if (unlikely(flags & XDP_XMIT_FLUSH)) 10772 ixgbe_xdp_ring_update_tail(ring); 10773 10774 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 10775 spin_unlock(&ring->tx_lock); 10776 10777 return nxmit; 10778 } 10779 10780 static const struct net_device_ops ixgbe_netdev_ops = { 10781 .ndo_open = ixgbe_open, 10782 .ndo_stop = ixgbe_close, 10783 .ndo_start_xmit = ixgbe_xmit_frame, 10784 .ndo_set_rx_mode = ixgbe_set_rx_mode, 10785 .ndo_validate_addr = eth_validate_addr, 10786 .ndo_set_mac_address = ixgbe_set_mac, 10787 .ndo_change_mtu = ixgbe_change_mtu, 10788 .ndo_tx_timeout = ixgbe_tx_timeout, 10789 .ndo_set_tx_maxrate = ixgbe_tx_maxrate, 10790 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 10791 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 10792 .ndo_eth_ioctl = ixgbe_ioctl, 10793 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 10794 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 10795 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 10796 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 10797 .ndo_set_vf_link_state = ixgbe_ndo_set_vf_link_state, 10798 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 10799 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, 10800 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 10801 .ndo_get_vf_stats = ixgbe_ndo_get_vf_stats, 10802 .ndo_get_stats64 = ixgbe_get_stats64, 10803 .ndo_setup_tc = __ixgbe_setup_tc, 10804 #ifdef IXGBE_FCOE 10805 .ndo_select_queue = ixgbe_select_queue, 10806 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 10807 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 10808 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 10809 .ndo_fcoe_enable = ixgbe_fcoe_enable, 10810 .ndo_fcoe_disable = ixgbe_fcoe_disable, 10811 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 10812 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 10813 #endif /* IXGBE_FCOE */ 10814 .ndo_set_features = ixgbe_set_features, 10815 .ndo_fix_features = ixgbe_fix_features, 10816 .ndo_fdb_add = ixgbe_ndo_fdb_add, 10817 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 10818 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 10819 .ndo_dfwd_add_station = ixgbe_fwd_add, 10820 .ndo_dfwd_del_station = ixgbe_fwd_del, 10821 .ndo_features_check = ixgbe_features_check, 10822 .ndo_bpf = ixgbe_xdp, 10823 .ndo_xdp_xmit = ixgbe_xdp_xmit, 10824 .ndo_xsk_wakeup = ixgbe_xsk_wakeup, 10825 }; 10826 10827 static void ixgbe_disable_txr_hw(struct ixgbe_adapter *adapter, 10828 struct ixgbe_ring *tx_ring) 10829 { 10830 unsigned long wait_delay, delay_interval; 10831 struct ixgbe_hw *hw = &adapter->hw; 10832 u8 reg_idx = tx_ring->reg_idx; 10833 int wait_loop; 10834 u32 txdctl; 10835 10836 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 10837 10838 /* delay mechanism from ixgbe_disable_tx */ 10839 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 10840 10841 wait_loop = IXGBE_MAX_RX_DESC_POLL; 10842 wait_delay = delay_interval; 10843 10844 while (wait_loop--) { 10845 usleep_range(wait_delay, wait_delay + 10); 10846 wait_delay += delay_interval * 2; 10847 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 10848 10849 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 10850 return; 10851 } 10852 10853 e_err(drv, "TXDCTL.ENABLE not cleared within the polling period\n"); 10854 } 10855 10856 static void ixgbe_disable_txr(struct ixgbe_adapter *adapter, 10857 struct ixgbe_ring *tx_ring) 10858 { 10859 set_bit(__IXGBE_TX_DISABLED, &tx_ring->state); 10860 ixgbe_disable_txr_hw(adapter, tx_ring); 10861 } 10862 10863 static void ixgbe_disable_rxr_hw(struct ixgbe_adapter *adapter, 10864 struct ixgbe_ring *rx_ring) 10865 { 10866 unsigned long wait_delay, delay_interval; 10867 struct ixgbe_hw *hw = &adapter->hw; 10868 u8 reg_idx = rx_ring->reg_idx; 10869 int wait_loop; 10870 u32 rxdctl; 10871 10872 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 10873 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 10874 rxdctl |= IXGBE_RXDCTL_SWFLSH; 10875 10876 /* write value back with RXDCTL.ENABLE bit cleared */ 10877 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 10878 10879 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 10880 if (hw->mac.type == ixgbe_mac_82598EB && 10881 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 10882 return; 10883 10884 /* delay mechanism from ixgbe_disable_rx */ 10885 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 10886 10887 wait_loop = IXGBE_MAX_RX_DESC_POLL; 10888 wait_delay = delay_interval; 10889 10890 while (wait_loop--) { 10891 usleep_range(wait_delay, wait_delay + 10); 10892 wait_delay += delay_interval * 2; 10893 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 10894 10895 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 10896 return; 10897 } 10898 10899 e_err(drv, "RXDCTL.ENABLE not cleared within the polling period\n"); 10900 } 10901 10902 static void ixgbe_reset_txr_stats(struct ixgbe_ring *tx_ring) 10903 { 10904 memset(&tx_ring->stats, 0, sizeof(tx_ring->stats)); 10905 memset(&tx_ring->tx_stats, 0, sizeof(tx_ring->tx_stats)); 10906 } 10907 10908 static void ixgbe_reset_rxr_stats(struct ixgbe_ring *rx_ring) 10909 { 10910 memset(&rx_ring->stats, 0, sizeof(rx_ring->stats)); 10911 memset(&rx_ring->rx_stats, 0, sizeof(rx_ring->rx_stats)); 10912 } 10913 10914 /** 10915 * ixgbe_irq_disable_single - Disable single IRQ vector 10916 * @adapter: adapter structure 10917 * @ring: ring index 10918 **/ 10919 static void ixgbe_irq_disable_single(struct ixgbe_adapter *adapter, u32 ring) 10920 { 10921 struct ixgbe_hw *hw = &adapter->hw; 10922 u64 qmask = BIT_ULL(ring); 10923 u32 mask; 10924 10925 switch (adapter->hw.mac.type) { 10926 case ixgbe_mac_82598EB: 10927 mask = qmask & IXGBE_EIMC_RTX_QUEUE; 10928 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask); 10929 break; 10930 case ixgbe_mac_82599EB: 10931 case ixgbe_mac_X540: 10932 case ixgbe_mac_X550: 10933 case ixgbe_mac_X550EM_x: 10934 case ixgbe_mac_x550em_a: 10935 mask = (qmask & 0xFFFFFFFF); 10936 if (mask) 10937 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 10938 mask = (qmask >> 32); 10939 if (mask) 10940 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 10941 break; 10942 default: 10943 break; 10944 } 10945 IXGBE_WRITE_FLUSH(&adapter->hw); 10946 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 10947 synchronize_irq(adapter->msix_entries[ring].vector); 10948 else 10949 synchronize_irq(adapter->pdev->irq); 10950 } 10951 10952 /** 10953 * ixgbe_txrx_ring_disable - Disable Rx/Tx/XDP Tx rings 10954 * @adapter: adapter structure 10955 * @ring: ring index 10956 * 10957 * This function disables a certain Rx/Tx/XDP Tx ring. The function 10958 * assumes that the netdev is running. 10959 **/ 10960 void ixgbe_txrx_ring_disable(struct ixgbe_adapter *adapter, int ring) 10961 { 10962 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 10963 10964 rx_ring = adapter->rx_ring[ring]; 10965 tx_ring = adapter->tx_ring[ring]; 10966 xdp_ring = adapter->xdp_ring[ring]; 10967 10968 ixgbe_irq_disable_single(adapter, ring); 10969 10970 /* Rx/Tx/XDP Tx share the same napi context. */ 10971 napi_disable(&rx_ring->q_vector->napi); 10972 10973 ixgbe_disable_txr(adapter, tx_ring); 10974 if (xdp_ring) 10975 ixgbe_disable_txr(adapter, xdp_ring); 10976 ixgbe_disable_rxr_hw(adapter, rx_ring); 10977 10978 if (xdp_ring) 10979 synchronize_rcu(); 10980 10981 ixgbe_clean_tx_ring(tx_ring); 10982 if (xdp_ring) 10983 ixgbe_clean_tx_ring(xdp_ring); 10984 ixgbe_clean_rx_ring(rx_ring); 10985 10986 ixgbe_reset_txr_stats(tx_ring); 10987 if (xdp_ring) 10988 ixgbe_reset_txr_stats(xdp_ring); 10989 ixgbe_reset_rxr_stats(rx_ring); 10990 } 10991 10992 /** 10993 * ixgbe_txrx_ring_enable - Enable Rx/Tx/XDP Tx rings 10994 * @adapter: adapter structure 10995 * @ring: ring index 10996 * 10997 * This function enables a certain Rx/Tx/XDP Tx ring. The function 10998 * assumes that the netdev is running. 10999 **/ 11000 void ixgbe_txrx_ring_enable(struct ixgbe_adapter *adapter, int ring) 11001 { 11002 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 11003 11004 rx_ring = adapter->rx_ring[ring]; 11005 tx_ring = adapter->tx_ring[ring]; 11006 xdp_ring = adapter->xdp_ring[ring]; 11007 11008 ixgbe_configure_tx_ring(adapter, tx_ring); 11009 if (xdp_ring) 11010 ixgbe_configure_tx_ring(adapter, xdp_ring); 11011 ixgbe_configure_rx_ring(adapter, rx_ring); 11012 11013 clear_bit(__IXGBE_TX_DISABLED, &tx_ring->state); 11014 if (xdp_ring) 11015 clear_bit(__IXGBE_TX_DISABLED, &xdp_ring->state); 11016 11017 /* Rx/Tx/XDP Tx share the same napi context. */ 11018 napi_enable(&rx_ring->q_vector->napi); 11019 ixgbe_irq_enable_queues(adapter, BIT_ULL(ring)); 11020 IXGBE_WRITE_FLUSH(&adapter->hw); 11021 } 11022 11023 /** 11024 * ixgbe_enumerate_functions - Get the number of ports this device has 11025 * @adapter: adapter structure 11026 * 11027 * This function enumerates the phsyical functions co-located on a single slot, 11028 * in order to determine how many ports a device has. This is most useful in 11029 * determining the required GT/s of PCIe bandwidth necessary for optimal 11030 * performance. 11031 **/ 11032 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 11033 { 11034 struct pci_dev *entry, *pdev = adapter->pdev; 11035 int physfns = 0; 11036 11037 /* Some cards can not use the generic count PCIe functions method, 11038 * because they are behind a parent switch, so we hardcode these with 11039 * the correct number of functions. 11040 */ 11041 if (ixgbe_pcie_from_parent(&adapter->hw)) 11042 physfns = 4; 11043 11044 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 11045 /* don't count virtual functions */ 11046 if (entry->is_virtfn) 11047 continue; 11048 11049 /* When the devices on the bus don't all match our device ID, 11050 * we can't reliably determine the correct number of 11051 * functions. This can occur if a function has been direct 11052 * attached to a virtual machine using VT-d, for example. In 11053 * this case, simply return -1 to indicate this. 11054 */ 11055 if ((entry->vendor != pdev->vendor) || 11056 (entry->device != pdev->device)) 11057 return -1; 11058 11059 physfns++; 11060 } 11061 11062 return physfns; 11063 } 11064 11065 /** 11066 * ixgbe_wol_supported - Check whether device supports WoL 11067 * @adapter: the adapter private structure 11068 * @device_id: the device ID 11069 * @subdevice_id: the subsystem device ID 11070 * 11071 * This function is used by probe and ethtool to determine 11072 * which devices have WoL support 11073 * 11074 **/ 11075 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 11076 u16 subdevice_id) 11077 { 11078 struct ixgbe_hw *hw = &adapter->hw; 11079 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 11080 11081 /* WOL not supported on 82598 */ 11082 if (hw->mac.type == ixgbe_mac_82598EB) 11083 return false; 11084 11085 /* check eeprom to see if WOL is enabled for X540 and newer */ 11086 if (hw->mac.type >= ixgbe_mac_X540) { 11087 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 11088 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 11089 (hw->bus.func == 0))) 11090 return true; 11091 } 11092 11093 /* WOL is determined based on device IDs for 82599 MACs */ 11094 switch (device_id) { 11095 case IXGBE_DEV_ID_82599_SFP: 11096 /* Only these subdevices could supports WOL */ 11097 switch (subdevice_id) { 11098 case IXGBE_SUBDEV_ID_82599_560FLR: 11099 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: 11100 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 11101 case IXGBE_SUBDEV_ID_82599_SFP_2OCP: 11102 /* only support first port */ 11103 if (hw->bus.func != 0) 11104 break; 11105 fallthrough; 11106 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 11107 case IXGBE_SUBDEV_ID_82599_SFP: 11108 case IXGBE_SUBDEV_ID_82599_RNDC: 11109 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 11110 case IXGBE_SUBDEV_ID_82599_SFP_1OCP: 11111 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: 11112 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: 11113 return true; 11114 } 11115 break; 11116 case IXGBE_DEV_ID_82599EN_SFP: 11117 /* Only these subdevices support WOL */ 11118 switch (subdevice_id) { 11119 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 11120 return true; 11121 } 11122 break; 11123 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 11124 /* All except this subdevice support WOL */ 11125 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 11126 return true; 11127 break; 11128 case IXGBE_DEV_ID_82599_KX4: 11129 return true; 11130 default: 11131 break; 11132 } 11133 11134 return false; 11135 } 11136 11137 /** 11138 * ixgbe_set_fw_version_e610 - Set FW version specifically on E610 adapters 11139 * @adapter: the adapter private structure 11140 * 11141 * This function is used by probe and ethtool to determine the FW version to 11142 * format to display. The FW version is taken from the EEPROM/NVM. 11143 * 11144 */ 11145 static void ixgbe_set_fw_version_e610(struct ixgbe_adapter *adapter) 11146 { 11147 struct ixgbe_orom_info *orom = &adapter->hw.flash.orom; 11148 struct ixgbe_nvm_info *nvm = &adapter->hw.flash.nvm; 11149 11150 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 11151 "%x.%02x 0x%x %d.%d.%d", nvm->major, nvm->minor, 11152 nvm->eetrack, orom->major, orom->build, orom->patch); 11153 } 11154 11155 /** 11156 * ixgbe_set_fw_version - Set FW version 11157 * @adapter: the adapter private structure 11158 * 11159 * This function is used by probe and ethtool to determine the FW version to 11160 * format to display. The FW version is taken from the EEPROM/NVM. 11161 */ 11162 static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter) 11163 { 11164 struct ixgbe_hw *hw = &adapter->hw; 11165 struct ixgbe_nvm_version nvm_ver; 11166 11167 if (adapter->hw.mac.type == ixgbe_mac_e610) { 11168 ixgbe_set_fw_version_e610(adapter); 11169 return; 11170 } 11171 11172 ixgbe_get_oem_prod_version(hw, &nvm_ver); 11173 if (nvm_ver.oem_valid) { 11174 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 11175 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor, 11176 nvm_ver.oem_release); 11177 return; 11178 } 11179 11180 ixgbe_get_etk_id(hw, &nvm_ver); 11181 ixgbe_get_orom_version(hw, &nvm_ver); 11182 11183 if (nvm_ver.or_valid) { 11184 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 11185 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major, 11186 nvm_ver.or_build, nvm_ver.or_patch); 11187 return; 11188 } 11189 11190 /* Set ETrack ID format */ 11191 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 11192 "0x%08x", nvm_ver.etk_id); 11193 } 11194 11195 /** 11196 * ixgbe_probe - Device Initialization Routine 11197 * @pdev: PCI device information struct 11198 * @ent: entry in ixgbe_pci_tbl 11199 * 11200 * Returns 0 on success, negative on failure 11201 * 11202 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 11203 * The OS initialization, configuring of the adapter private structure, 11204 * and a hardware reset occur. 11205 **/ 11206 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 11207 { 11208 struct net_device *netdev; 11209 struct ixgbe_adapter *adapter = NULL; 11210 struct ixgbe_hw *hw; 11211 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 11212 unsigned int indices = MAX_TX_QUEUES; 11213 u8 part_str[IXGBE_PBANUM_LENGTH]; 11214 int i, err, expected_gts; 11215 bool disable_dev = false; 11216 #ifdef IXGBE_FCOE 11217 u16 device_caps; 11218 #endif 11219 u32 eec; 11220 11221 /* Catch broken hardware that put the wrong VF device ID in 11222 * the PCIe SR-IOV capability. 11223 */ 11224 if (pdev->is_virtfn) { 11225 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 11226 pci_name(pdev), pdev->vendor, pdev->device); 11227 return -EINVAL; 11228 } 11229 11230 err = pci_enable_device_mem(pdev); 11231 if (err) 11232 return err; 11233 11234 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 11235 if (err) { 11236 dev_err(&pdev->dev, 11237 "No usable DMA configuration, aborting\n"); 11238 goto err_dma; 11239 } 11240 11241 err = pci_request_mem_regions(pdev, ixgbe_driver_name); 11242 if (err) { 11243 dev_err(&pdev->dev, 11244 "pci_request_selected_regions failed 0x%x\n", err); 11245 goto err_pci_reg; 11246 } 11247 11248 pci_set_master(pdev); 11249 pci_save_state(pdev); 11250 11251 if (ii->mac == ixgbe_mac_82598EB) { 11252 #ifdef CONFIG_IXGBE_DCB 11253 /* 8 TC w/ 4 queues per TC */ 11254 indices = 4 * MAX_TRAFFIC_CLASS; 11255 #else 11256 indices = IXGBE_MAX_RSS_INDICES; 11257 #endif 11258 } else if (ii->mac == ixgbe_mac_e610) { 11259 indices = IXGBE_MAX_RSS_INDICES_X550; 11260 } 11261 11262 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 11263 if (!netdev) { 11264 err = -ENOMEM; 11265 goto err_alloc_etherdev; 11266 } 11267 11268 SET_NETDEV_DEV(netdev, &pdev->dev); 11269 11270 adapter = netdev_priv(netdev); 11271 11272 adapter->netdev = netdev; 11273 adapter->pdev = pdev; 11274 hw = &adapter->hw; 11275 hw->back = adapter; 11276 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 11277 11278 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 11279 pci_resource_len(pdev, 0)); 11280 adapter->io_addr = hw->hw_addr; 11281 if (!hw->hw_addr) { 11282 err = -EIO; 11283 goto err_ioremap; 11284 } 11285 11286 netdev->netdev_ops = &ixgbe_netdev_ops; 11287 ixgbe_set_ethtool_ops(netdev); 11288 netdev->watchdog_timeo = 5 * HZ; 11289 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 11290 11291 /* Setup hw api */ 11292 hw->mac.ops = *ii->mac_ops; 11293 hw->mac.type = ii->mac; 11294 hw->mvals = ii->mvals; 11295 if (ii->link_ops) 11296 hw->link.ops = *ii->link_ops; 11297 11298 /* EEPROM */ 11299 hw->eeprom.ops = *ii->eeprom_ops; 11300 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 11301 if (ixgbe_removed(hw->hw_addr)) { 11302 err = -EIO; 11303 goto err_ioremap; 11304 } 11305 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 11306 if (!(eec & BIT(8))) 11307 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 11308 11309 /* PHY */ 11310 hw->phy.ops = *ii->phy_ops; 11311 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 11312 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 11313 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 11314 hw->phy.mdio.mmds = 0; 11315 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 11316 hw->phy.mdio.dev = netdev; 11317 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 11318 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 11319 11320 /* setup the private structure */ 11321 err = ixgbe_sw_init(adapter, ii); 11322 if (err) 11323 goto err_sw_init; 11324 11325 if (adapter->hw.mac.type == ixgbe_mac_e610) { 11326 err = ixgbe_get_caps(&adapter->hw); 11327 if (err) 11328 dev_err(&pdev->dev, "ixgbe_get_caps failed %d\n", err); 11329 } 11330 11331 if (adapter->hw.mac.type == ixgbe_mac_82599EB) 11332 adapter->flags2 |= IXGBE_FLAG2_AUTO_DISABLE_VF; 11333 11334 switch (adapter->hw.mac.type) { 11335 case ixgbe_mac_X550: 11336 case ixgbe_mac_X550EM_x: 11337 case ixgbe_mac_e610: 11338 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550; 11339 break; 11340 case ixgbe_mac_x550em_a: 11341 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550em_a; 11342 break; 11343 default: 11344 break; 11345 } 11346 11347 /* Make sure the SWFW semaphore is in a valid state */ 11348 if (hw->mac.ops.init_swfw_sync) 11349 hw->mac.ops.init_swfw_sync(hw); 11350 11351 /* Make it possible the adapter to be woken up via WOL */ 11352 switch (adapter->hw.mac.type) { 11353 case ixgbe_mac_82599EB: 11354 case ixgbe_mac_X540: 11355 case ixgbe_mac_X550: 11356 case ixgbe_mac_X550EM_x: 11357 case ixgbe_mac_x550em_a: 11358 case ixgbe_mac_e610: 11359 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 11360 break; 11361 default: 11362 break; 11363 } 11364 11365 /* 11366 * If there is a fan on this device and it has failed log the 11367 * failure. 11368 */ 11369 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 11370 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 11371 if (esdp & IXGBE_ESDP_SDP1) 11372 e_crit(probe, "Fan has stopped, replace the adapter\n"); 11373 } 11374 11375 if (allow_unsupported_sfp) 11376 hw->allow_unsupported_sfp = allow_unsupported_sfp; 11377 11378 /* reset_hw fills in the perm_addr as well */ 11379 hw->phy.reset_if_overtemp = true; 11380 err = hw->mac.ops.reset_hw(hw); 11381 hw->phy.reset_if_overtemp = false; 11382 ixgbe_set_eee_capable(adapter); 11383 if (err == -ENOENT) { 11384 err = 0; 11385 } else if (err == -EOPNOTSUPP) { 11386 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 11387 e_dev_err("Reload the driver after installing a supported module.\n"); 11388 goto err_sw_init; 11389 } else if (err) { 11390 e_dev_err("HW Init failed: %d\n", err); 11391 goto err_sw_init; 11392 } 11393 11394 #ifdef CONFIG_PCI_IOV 11395 /* SR-IOV not supported on the 82598 */ 11396 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 11397 goto skip_sriov; 11398 /* Mailbox */ 11399 ixgbe_init_mbx_params_pf(hw); 11400 hw->mbx.ops = ii->mbx_ops; 11401 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 11402 ixgbe_enable_sriov(adapter, max_vfs); 11403 skip_sriov: 11404 11405 #endif 11406 netdev->features = NETIF_F_SG | 11407 NETIF_F_TSO | 11408 NETIF_F_TSO6 | 11409 NETIF_F_RXHASH | 11410 NETIF_F_RXCSUM | 11411 NETIF_F_HW_CSUM; 11412 11413 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 11414 NETIF_F_GSO_GRE_CSUM | \ 11415 NETIF_F_GSO_IPXIP4 | \ 11416 NETIF_F_GSO_IPXIP6 | \ 11417 NETIF_F_GSO_UDP_TUNNEL | \ 11418 NETIF_F_GSO_UDP_TUNNEL_CSUM) 11419 11420 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; 11421 netdev->features |= NETIF_F_GSO_PARTIAL | 11422 IXGBE_GSO_PARTIAL_FEATURES; 11423 11424 if (hw->mac.type >= ixgbe_mac_82599EB) 11425 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 11426 11427 #ifdef CONFIG_IXGBE_IPSEC 11428 #define IXGBE_ESP_FEATURES (NETIF_F_HW_ESP | \ 11429 NETIF_F_HW_ESP_TX_CSUM | \ 11430 NETIF_F_GSO_ESP) 11431 11432 if (adapter->ipsec) 11433 netdev->features |= IXGBE_ESP_FEATURES; 11434 #endif 11435 /* copy netdev features into list of user selectable features */ 11436 netdev->hw_features |= netdev->features | 11437 NETIF_F_HW_VLAN_CTAG_FILTER | 11438 NETIF_F_HW_VLAN_CTAG_RX | 11439 NETIF_F_HW_VLAN_CTAG_TX | 11440 NETIF_F_RXALL | 11441 NETIF_F_HW_L2FW_DOFFLOAD; 11442 11443 if (hw->mac.type >= ixgbe_mac_82599EB) 11444 netdev->hw_features |= NETIF_F_NTUPLE | 11445 NETIF_F_HW_TC; 11446 11447 netdev->features |= NETIF_F_HIGHDMA; 11448 11449 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 11450 netdev->hw_enc_features |= netdev->vlan_features; 11451 netdev->mpls_features |= NETIF_F_SG | 11452 NETIF_F_TSO | 11453 NETIF_F_TSO6 | 11454 NETIF_F_HW_CSUM; 11455 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES; 11456 11457 /* set this bit last since it cannot be part of vlan_features */ 11458 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 11459 NETIF_F_HW_VLAN_CTAG_RX | 11460 NETIF_F_HW_VLAN_CTAG_TX; 11461 11462 netdev->priv_flags |= IFF_UNICAST_FLT; 11463 netdev->priv_flags |= IFF_SUPP_NOFCS; 11464 11465 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | 11466 NETDEV_XDP_ACT_XSK_ZEROCOPY; 11467 11468 /* MTU range: 68 - 9710 */ 11469 netdev->min_mtu = ETH_MIN_MTU; 11470 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN); 11471 11472 #ifdef CONFIG_IXGBE_DCB 11473 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 11474 netdev->dcbnl_ops = &ixgbe_dcbnl_ops; 11475 #endif 11476 11477 #ifdef IXGBE_FCOE 11478 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 11479 unsigned int fcoe_l; 11480 11481 if (hw->mac.ops.get_device_caps) { 11482 hw->mac.ops.get_device_caps(hw, &device_caps); 11483 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 11484 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 11485 } 11486 11487 11488 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 11489 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 11490 11491 netdev->features |= NETIF_F_FSO | 11492 NETIF_F_FCOE_CRC; 11493 11494 netdev->vlan_features |= NETIF_F_FSO | 11495 NETIF_F_FCOE_CRC; 11496 } 11497 #endif /* IXGBE_FCOE */ 11498 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 11499 netdev->hw_features |= NETIF_F_LRO; 11500 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 11501 netdev->features |= NETIF_F_LRO; 11502 11503 if (ixgbe_check_fw_error(adapter)) { 11504 err = -EIO; 11505 goto err_sw_init; 11506 } 11507 11508 /* make sure the EEPROM is good */ 11509 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 11510 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 11511 err = -EIO; 11512 goto err_sw_init; 11513 } 11514 11515 eth_platform_get_mac_address(&adapter->pdev->dev, 11516 adapter->hw.mac.perm_addr); 11517 11518 eth_hw_addr_set(netdev, hw->mac.perm_addr); 11519 11520 if (!is_valid_ether_addr(netdev->dev_addr)) { 11521 e_dev_err("invalid MAC address\n"); 11522 err = -EIO; 11523 goto err_sw_init; 11524 } 11525 11526 /* Set hw->mac.addr to permanent MAC address */ 11527 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); 11528 ixgbe_mac_set_default_filter(adapter); 11529 11530 if (hw->mac.type == ixgbe_mac_e610) 11531 mutex_init(&hw->aci.lock); 11532 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0); 11533 11534 if (ixgbe_removed(hw->hw_addr)) { 11535 err = -EIO; 11536 goto err_sw_init; 11537 } 11538 INIT_WORK(&adapter->service_task, ixgbe_service_task); 11539 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 11540 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 11541 11542 err = ixgbe_init_interrupt_scheme(adapter); 11543 if (err) 11544 goto err_sw_init; 11545 11546 for (i = 0; i < adapter->num_rx_queues; i++) 11547 u64_stats_init(&adapter->rx_ring[i]->syncp); 11548 for (i = 0; i < adapter->num_tx_queues; i++) 11549 u64_stats_init(&adapter->tx_ring[i]->syncp); 11550 for (i = 0; i < adapter->num_xdp_queues; i++) 11551 u64_stats_init(&adapter->xdp_ring[i]->syncp); 11552 11553 /* WOL not supported for all devices */ 11554 adapter->wol = 0; 11555 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 11556 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 11557 pdev->subsystem_device); 11558 if (hw->wol_enabled) 11559 adapter->wol = IXGBE_WUFC_MAG; 11560 11561 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 11562 11563 /* save off EEPROM version number */ 11564 ixgbe_set_fw_version(adapter); 11565 11566 /* pick up the PCI bus settings for reporting later */ 11567 if (ixgbe_pcie_from_parent(hw)) 11568 ixgbe_get_parent_bus_info(adapter); 11569 else 11570 hw->mac.ops.get_bus_info(hw); 11571 11572 /* calculate the expected PCIe bandwidth required for optimal 11573 * performance. Note that some older parts will never have enough 11574 * bandwidth due to being older generation PCIe parts. We clamp these 11575 * parts to ensure no warning is displayed if it can't be fixed. 11576 */ 11577 switch (hw->mac.type) { 11578 case ixgbe_mac_82598EB: 11579 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 11580 break; 11581 default: 11582 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 11583 break; 11584 } 11585 11586 /* don't check link if we failed to enumerate functions */ 11587 if (expected_gts > 0) 11588 ixgbe_check_minimum_link(adapter, expected_gts); 11589 11590 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 11591 if (err) 11592 strscpy(part_str, "Unknown", sizeof(part_str)); 11593 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 11594 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 11595 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 11596 part_str); 11597 else 11598 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 11599 hw->mac.type, hw->phy.type, part_str); 11600 11601 e_dev_info("%pM\n", netdev->dev_addr); 11602 11603 /* reset the hardware with the new settings */ 11604 err = hw->mac.ops.start_hw(hw); 11605 if (err == -EACCES) { 11606 /* We are running on a pre-production device, log a warning */ 11607 e_dev_warn("This device is a pre-production adapter/LOM. " 11608 "Please be aware there may be issues associated " 11609 "with your hardware. If you are experiencing " 11610 "problems please contact your Intel or hardware " 11611 "representative who provided you with this " 11612 "hardware.\n"); 11613 } 11614 strcpy(netdev->name, "eth%d"); 11615 pci_set_drvdata(pdev, adapter); 11616 err = register_netdev(netdev); 11617 if (err) 11618 goto err_register; 11619 11620 11621 /* power down the optics for 82599 SFP+ fiber */ 11622 if (hw->mac.ops.disable_tx_laser) 11623 hw->mac.ops.disable_tx_laser(hw); 11624 11625 /* carrier off reporting is important to ethtool even BEFORE open */ 11626 netif_carrier_off(netdev); 11627 11628 #ifdef CONFIG_IXGBE_DCA 11629 if (dca_add_requester(&pdev->dev) == 0) { 11630 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 11631 ixgbe_setup_dca(adapter); 11632 } 11633 #endif 11634 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 11635 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 11636 for (i = 0; i < adapter->num_vfs; i++) 11637 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 11638 } 11639 11640 /* firmware requires driver version to be 0xFFFFFFFF 11641 * since os does not support feature 11642 */ 11643 if (hw->mac.ops.set_fw_drv_ver) 11644 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF, 11645 sizeof(UTS_RELEASE) - 1, 11646 UTS_RELEASE); 11647 11648 /* add san mac addr to netdev */ 11649 ixgbe_add_sanmac_netdev(netdev); 11650 11651 e_dev_info("%s\n", ixgbe_default_device_descr); 11652 11653 #ifdef CONFIG_IXGBE_HWMON 11654 if (ixgbe_sysfs_init(adapter)) 11655 e_err(probe, "failed to allocate sysfs resources\n"); 11656 #endif /* CONFIG_IXGBE_HWMON */ 11657 11658 ixgbe_dbg_adapter_init(adapter); 11659 11660 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 11661 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 11662 hw->mac.ops.setup_link(hw, 11663 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 11664 true); 11665 11666 err = ixgbe_mii_bus_init(hw); 11667 if (err) 11668 goto err_netdev; 11669 11670 return 0; 11671 11672 err_netdev: 11673 unregister_netdev(netdev); 11674 err_register: 11675 ixgbe_release_hw_control(adapter); 11676 ixgbe_clear_interrupt_scheme(adapter); 11677 if (hw->mac.type == ixgbe_mac_e610) 11678 mutex_destroy(&adapter->hw.aci.lock); 11679 err_sw_init: 11680 ixgbe_disable_sriov(adapter); 11681 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 11682 iounmap(adapter->io_addr); 11683 kfree(adapter->jump_tables[0]); 11684 kfree(adapter->mac_table); 11685 kfree(adapter->rss_key); 11686 bitmap_free(adapter->af_xdp_zc_qps); 11687 err_ioremap: 11688 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 11689 free_netdev(netdev); 11690 err_alloc_etherdev: 11691 pci_release_mem_regions(pdev); 11692 err_pci_reg: 11693 err_dma: 11694 if (!adapter || disable_dev) 11695 pci_disable_device(pdev); 11696 return err; 11697 } 11698 11699 /** 11700 * ixgbe_remove - Device Removal Routine 11701 * @pdev: PCI device information struct 11702 * 11703 * ixgbe_remove is called by the PCI subsystem to alert the driver 11704 * that it should release a PCI device. The could be caused by a 11705 * Hot-Plug event, or because the driver is going to be removed from 11706 * memory. 11707 **/ 11708 static void ixgbe_remove(struct pci_dev *pdev) 11709 { 11710 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11711 struct net_device *netdev; 11712 bool disable_dev; 11713 int i; 11714 11715 /* if !adapter then we already cleaned up in probe */ 11716 if (!adapter) 11717 return; 11718 11719 netdev = adapter->netdev; 11720 ixgbe_dbg_adapter_exit(adapter); 11721 11722 set_bit(__IXGBE_REMOVING, &adapter->state); 11723 cancel_work_sync(&adapter->service_task); 11724 11725 if (adapter->hw.mac.type == ixgbe_mac_e610) { 11726 ixgbe_disable_link_status_events(adapter); 11727 mutex_destroy(&adapter->hw.aci.lock); 11728 } 11729 11730 if (adapter->mii_bus) 11731 mdiobus_unregister(adapter->mii_bus); 11732 11733 #ifdef CONFIG_IXGBE_DCA 11734 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 11735 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 11736 dca_remove_requester(&pdev->dev); 11737 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 11738 IXGBE_DCA_CTRL_DCA_DISABLE); 11739 } 11740 11741 #endif 11742 #ifdef CONFIG_IXGBE_HWMON 11743 ixgbe_sysfs_exit(adapter); 11744 #endif /* CONFIG_IXGBE_HWMON */ 11745 11746 /* remove the added san mac */ 11747 ixgbe_del_sanmac_netdev(netdev); 11748 11749 #ifdef CONFIG_PCI_IOV 11750 ixgbe_disable_sriov(adapter); 11751 #endif 11752 if (netdev->reg_state == NETREG_REGISTERED) 11753 unregister_netdev(netdev); 11754 11755 ixgbe_stop_ipsec_offload(adapter); 11756 ixgbe_clear_interrupt_scheme(adapter); 11757 11758 ixgbe_release_hw_control(adapter); 11759 11760 #ifdef CONFIG_DCB 11761 kfree(adapter->ixgbe_ieee_pfc); 11762 kfree(adapter->ixgbe_ieee_ets); 11763 11764 #endif 11765 iounmap(adapter->io_addr); 11766 pci_release_mem_regions(pdev); 11767 11768 e_dev_info("complete\n"); 11769 11770 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { 11771 if (adapter->jump_tables[i]) { 11772 kfree(adapter->jump_tables[i]->input); 11773 kfree(adapter->jump_tables[i]->mask); 11774 } 11775 kfree(adapter->jump_tables[i]); 11776 } 11777 11778 kfree(adapter->mac_table); 11779 kfree(adapter->rss_key); 11780 bitmap_free(adapter->af_xdp_zc_qps); 11781 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 11782 free_netdev(netdev); 11783 11784 if (disable_dev) 11785 pci_disable_device(pdev); 11786 } 11787 11788 /** 11789 * ixgbe_io_error_detected - called when PCI error is detected 11790 * @pdev: Pointer to PCI device 11791 * @state: The current pci connection state 11792 * 11793 * This function is called after a PCI bus error affecting 11794 * this device has been detected. 11795 */ 11796 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 11797 pci_channel_state_t state) 11798 { 11799 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11800 struct net_device *netdev = adapter->netdev; 11801 11802 #ifdef CONFIG_PCI_IOV 11803 struct ixgbe_hw *hw = &adapter->hw; 11804 struct pci_dev *bdev, *vfdev; 11805 u32 dw0, dw1, dw2, dw3; 11806 int vf, pos; 11807 u16 req_id, pf_func; 11808 11809 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 11810 adapter->num_vfs == 0) 11811 goto skip_bad_vf_detection; 11812 11813 bdev = pdev->bus->self; 11814 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 11815 bdev = bdev->bus->self; 11816 11817 if (!bdev) 11818 goto skip_bad_vf_detection; 11819 11820 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 11821 if (!pos) 11822 goto skip_bad_vf_detection; 11823 11824 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 11825 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 11826 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 11827 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 11828 if (ixgbe_removed(hw->hw_addr)) 11829 goto skip_bad_vf_detection; 11830 11831 req_id = dw1 >> 16; 11832 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 11833 if (!(req_id & 0x0080)) 11834 goto skip_bad_vf_detection; 11835 11836 pf_func = req_id & 0x01; 11837 if ((pf_func & 1) == (pdev->devfn & 1)) { 11838 unsigned int device_id; 11839 11840 vf = FIELD_GET(0x7F, req_id); 11841 e_dev_err("VF %d has caused a PCIe error\n", vf); 11842 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 11843 "%8.8x\tdw3: %8.8x\n", 11844 dw0, dw1, dw2, dw3); 11845 switch (adapter->hw.mac.type) { 11846 case ixgbe_mac_82599EB: 11847 device_id = IXGBE_82599_VF_DEVICE_ID; 11848 break; 11849 case ixgbe_mac_X540: 11850 device_id = IXGBE_X540_VF_DEVICE_ID; 11851 break; 11852 case ixgbe_mac_X550: 11853 device_id = IXGBE_DEV_ID_X550_VF; 11854 break; 11855 case ixgbe_mac_X550EM_x: 11856 device_id = IXGBE_DEV_ID_X550EM_X_VF; 11857 break; 11858 case ixgbe_mac_x550em_a: 11859 device_id = IXGBE_DEV_ID_X550EM_A_VF; 11860 break; 11861 case ixgbe_mac_e610: 11862 device_id = IXGBE_DEV_ID_E610_VF; 11863 break; 11864 default: 11865 device_id = 0; 11866 break; 11867 } 11868 11869 /* Find the pci device of the offending VF */ 11870 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 11871 while (vfdev) { 11872 if (vfdev->devfn == (req_id & 0xFF)) 11873 break; 11874 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 11875 device_id, vfdev); 11876 } 11877 /* 11878 * There's a slim chance the VF could have been hot plugged, 11879 * so if it is no longer present we don't need to issue the 11880 * VFLR. Just clean up the AER in that case. 11881 */ 11882 if (vfdev) { 11883 pcie_flr(vfdev); 11884 /* Free device reference count */ 11885 pci_dev_put(vfdev); 11886 } 11887 } 11888 11889 /* 11890 * Even though the error may have occurred on the other port 11891 * we still need to increment the vf error reference count for 11892 * both ports because the I/O resume function will be called 11893 * for both of them. 11894 */ 11895 adapter->vferr_refcount++; 11896 11897 return PCI_ERS_RESULT_RECOVERED; 11898 11899 skip_bad_vf_detection: 11900 #endif /* CONFIG_PCI_IOV */ 11901 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 11902 return PCI_ERS_RESULT_DISCONNECT; 11903 11904 if (!netif_device_present(netdev)) 11905 return PCI_ERS_RESULT_DISCONNECT; 11906 11907 rtnl_lock(); 11908 netif_device_detach(netdev); 11909 11910 if (netif_running(netdev)) 11911 ixgbe_close_suspend(adapter); 11912 11913 if (state == pci_channel_io_perm_failure) { 11914 rtnl_unlock(); 11915 return PCI_ERS_RESULT_DISCONNECT; 11916 } 11917 11918 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 11919 pci_disable_device(pdev); 11920 rtnl_unlock(); 11921 11922 /* Request a slot reset. */ 11923 return PCI_ERS_RESULT_NEED_RESET; 11924 } 11925 11926 /** 11927 * ixgbe_io_slot_reset - called after the pci bus has been reset. 11928 * @pdev: Pointer to PCI device 11929 * 11930 * Restart the card from scratch, as if from a cold-boot. 11931 */ 11932 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 11933 { 11934 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11935 pci_ers_result_t result; 11936 11937 if (pci_enable_device_mem(pdev)) { 11938 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 11939 result = PCI_ERS_RESULT_DISCONNECT; 11940 } else { 11941 smp_mb__before_atomic(); 11942 clear_bit(__IXGBE_DISABLED, &adapter->state); 11943 adapter->hw.hw_addr = adapter->io_addr; 11944 pci_set_master(pdev); 11945 pci_restore_state(pdev); 11946 pci_save_state(pdev); 11947 11948 pci_wake_from_d3(pdev, false); 11949 11950 ixgbe_reset(adapter); 11951 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 11952 result = PCI_ERS_RESULT_RECOVERED; 11953 } 11954 11955 return result; 11956 } 11957 11958 /** 11959 * ixgbe_io_resume - called when traffic can start flowing again. 11960 * @pdev: Pointer to PCI device 11961 * 11962 * This callback is called when the error recovery driver tells us that 11963 * its OK to resume normal operation. 11964 */ 11965 static void ixgbe_io_resume(struct pci_dev *pdev) 11966 { 11967 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11968 struct net_device *netdev = adapter->netdev; 11969 11970 #ifdef CONFIG_PCI_IOV 11971 if (adapter->vferr_refcount) { 11972 e_info(drv, "Resuming after VF err\n"); 11973 adapter->vferr_refcount--; 11974 return; 11975 } 11976 11977 #endif 11978 rtnl_lock(); 11979 if (netif_running(netdev)) 11980 ixgbe_open(netdev); 11981 11982 netif_device_attach(netdev); 11983 rtnl_unlock(); 11984 } 11985 11986 static const struct pci_error_handlers ixgbe_err_handler = { 11987 .error_detected = ixgbe_io_error_detected, 11988 .slot_reset = ixgbe_io_slot_reset, 11989 .resume = ixgbe_io_resume, 11990 }; 11991 11992 static DEFINE_SIMPLE_DEV_PM_OPS(ixgbe_pm_ops, ixgbe_suspend, ixgbe_resume); 11993 11994 static struct pci_driver ixgbe_driver = { 11995 .name = ixgbe_driver_name, 11996 .id_table = ixgbe_pci_tbl, 11997 .probe = ixgbe_probe, 11998 .remove = ixgbe_remove, 11999 .driver.pm = pm_sleep_ptr(&ixgbe_pm_ops), 12000 .shutdown = ixgbe_shutdown, 12001 .sriov_configure = ixgbe_pci_sriov_configure, 12002 .err_handler = &ixgbe_err_handler 12003 }; 12004 12005 /** 12006 * ixgbe_init_module - Driver Registration Routine 12007 * 12008 * ixgbe_init_module is the first routine called when the driver is 12009 * loaded. All it does is register with the PCI subsystem. 12010 **/ 12011 static int __init ixgbe_init_module(void) 12012 { 12013 int ret; 12014 pr_info("%s\n", ixgbe_driver_string); 12015 pr_info("%s\n", ixgbe_copyright); 12016 12017 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); 12018 if (!ixgbe_wq) { 12019 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); 12020 return -ENOMEM; 12021 } 12022 12023 ixgbe_dbg_init(); 12024 12025 ret = pci_register_driver(&ixgbe_driver); 12026 if (ret) { 12027 destroy_workqueue(ixgbe_wq); 12028 ixgbe_dbg_exit(); 12029 return ret; 12030 } 12031 12032 #ifdef CONFIG_IXGBE_DCA 12033 dca_register_notify(&dca_notifier); 12034 #endif 12035 12036 return 0; 12037 } 12038 12039 module_init(ixgbe_init_module); 12040 12041 /** 12042 * ixgbe_exit_module - Driver Exit Cleanup Routine 12043 * 12044 * ixgbe_exit_module is called just before the driver is removed 12045 * from memory. 12046 **/ 12047 static void __exit ixgbe_exit_module(void) 12048 { 12049 #ifdef CONFIG_IXGBE_DCA 12050 dca_unregister_notify(&dca_notifier); 12051 #endif 12052 pci_unregister_driver(&ixgbe_driver); 12053 12054 ixgbe_dbg_exit(); 12055 if (ixgbe_wq) { 12056 destroy_workqueue(ixgbe_wq); 12057 ixgbe_wq = NULL; 12058 } 12059 } 12060 12061 #ifdef CONFIG_IXGBE_DCA 12062 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 12063 void *p) 12064 { 12065 int ret_val; 12066 12067 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 12068 __ixgbe_notify_dca); 12069 12070 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 12071 } 12072 12073 #endif /* CONFIG_IXGBE_DCA */ 12074 12075 module_exit(ixgbe_exit_module); 12076 12077 /* ixgbe_main.c */ 12078