1ae06c70bSJeff Kirsher /* SPDX-License-Identifier: GPL-2.0 */ 2*51dce24bSJeff Kirsher /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3dee1ad47SJeff Kirsher 4dee1ad47SJeff Kirsher #ifndef _IXGBE_FCOE_H 5dee1ad47SJeff Kirsher #define _IXGBE_FCOE_H 6dee1ad47SJeff Kirsher 7dee1ad47SJeff Kirsher #include <scsi/fc/fc_fs.h> 8dee1ad47SJeff Kirsher #include <scsi/fc/fc_fcoe.h> 9dee1ad47SJeff Kirsher 10dee1ad47SJeff Kirsher /* shift bits within STAT fo FCSTAT */ 11dee1ad47SJeff Kirsher #define IXGBE_RXDADV_FCSTAT_SHIFT 4 12dee1ad47SJeff Kirsher 13dee1ad47SJeff Kirsher /* ddp user buffer */ 14dee1ad47SJeff Kirsher #define IXGBE_BUFFCNT_MAX 256 /* 8 bits bufcnt */ 15dee1ad47SJeff Kirsher #define IXGBE_FCPTR_ALIGN 16 16dee1ad47SJeff Kirsher #define IXGBE_FCPTR_MAX (IXGBE_BUFFCNT_MAX * sizeof(dma_addr_t)) 17dee1ad47SJeff Kirsher #define IXGBE_FCBUFF_4KB 0x0 18dee1ad47SJeff Kirsher #define IXGBE_FCBUFF_8KB 0x1 19dee1ad47SJeff Kirsher #define IXGBE_FCBUFF_16KB 0x2 20dee1ad47SJeff Kirsher #define IXGBE_FCBUFF_64KB 0x3 21dee1ad47SJeff Kirsher #define IXGBE_FCBUFF_MAX 65536 /* 64KB max */ 22dee1ad47SJeff Kirsher #define IXGBE_FCBUFF_MIN 4096 /* 4KB min */ 23dee1ad47SJeff Kirsher #define IXGBE_FCOE_DDP_MAX 512 /* 9 bits xid */ 24ea412015SVasu Dev #define IXGBE_FCOE_DDP_MAX_X550 2048 /* 11 bits xid */ 25dee1ad47SJeff Kirsher 26dee1ad47SJeff Kirsher /* Default traffic class to use for FCoE */ 27dee1ad47SJeff Kirsher #define IXGBE_FCOE_DEFTC 3 28dee1ad47SJeff Kirsher 29dee1ad47SJeff Kirsher /* fcerr */ 30dee1ad47SJeff Kirsher #define IXGBE_FCERR_BADCRC 0x00100000 31dee1ad47SJeff Kirsher 32dee1ad47SJeff Kirsher /* FCoE DDP for target mode */ 33dee1ad47SJeff Kirsher #define __IXGBE_FCOE_TARGET 1 34dee1ad47SJeff Kirsher 35dee1ad47SJeff Kirsher struct ixgbe_fcoe_ddp { 36dee1ad47SJeff Kirsher int len; 37dee1ad47SJeff Kirsher u32 err; 38dee1ad47SJeff Kirsher unsigned int sgc; 39dee1ad47SJeff Kirsher struct scatterlist *sgl; 40dee1ad47SJeff Kirsher dma_addr_t udp; 41dee1ad47SJeff Kirsher u64 *udl; 421bf91cdcSAlexander Duyck struct dma_pool *pool; 43dee1ad47SJeff Kirsher }; 44dee1ad47SJeff Kirsher 455a1ee270SAlexander Duyck /* per cpu variables */ 465a1ee270SAlexander Duyck struct ixgbe_fcoe_ddp_pool { 475a1ee270SAlexander Duyck struct dma_pool *pool; 485a1ee270SAlexander Duyck u64 noddp; 495a1ee270SAlexander Duyck u64 noddp_ext_buff; 505a1ee270SAlexander Duyck }; 515a1ee270SAlexander Duyck 52dee1ad47SJeff Kirsher struct ixgbe_fcoe { 535a1ee270SAlexander Duyck struct ixgbe_fcoe_ddp_pool __percpu *ddp_pool; 54dee1ad47SJeff Kirsher atomic_t refcnt; 55dee1ad47SJeff Kirsher spinlock_t lock; 56ea412015SVasu Dev struct ixgbe_fcoe_ddp ddp[IXGBE_FCOE_DDP_MAX_X550]; 577c8ae65aSAlexander Duyck void *extra_ddp_buffer; 58dee1ad47SJeff Kirsher dma_addr_t extra_ddp_buffer_dma; 59dee1ad47SJeff Kirsher unsigned long mode; 60dee1ad47SJeff Kirsher u8 up; 61dee1ad47SJeff Kirsher }; 62dee1ad47SJeff Kirsher 63dee1ad47SJeff Kirsher #endif /* _IXGBE_FCOE_H */ 64