1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2011 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 /* ethtool support for ixgbe */ 29 30 #include <linux/interrupt.h> 31 #include <linux/types.h> 32 #include <linux/module.h> 33 #include <linux/slab.h> 34 #include <linux/pci.h> 35 #include <linux/netdevice.h> 36 #include <linux/ethtool.h> 37 #include <linux/vmalloc.h> 38 #include <linux/uaccess.h> 39 40 #include "ixgbe.h" 41 42 43 #define IXGBE_ALL_RAR_ENTRIES 16 44 45 enum {NETDEV_STATS, IXGBE_STATS}; 46 47 struct ixgbe_stats { 48 char stat_string[ETH_GSTRING_LEN]; 49 int type; 50 int sizeof_stat; 51 int stat_offset; 52 }; 53 54 #define IXGBE_STAT(m) IXGBE_STATS, \ 55 sizeof(((struct ixgbe_adapter *)0)->m), \ 56 offsetof(struct ixgbe_adapter, m) 57 #define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \ 58 sizeof(((struct rtnl_link_stats64 *)0)->m), \ 59 offsetof(struct rtnl_link_stats64, m) 60 61 static struct ixgbe_stats ixgbe_gstrings_stats[] = { 62 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)}, 63 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)}, 64 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)}, 65 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)}, 66 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)}, 67 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)}, 68 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)}, 69 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)}, 70 {"lsc_int", IXGBE_STAT(lsc_int)}, 71 {"tx_busy", IXGBE_STAT(tx_busy)}, 72 {"non_eop_descs", IXGBE_STAT(non_eop_descs)}, 73 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)}, 74 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)}, 75 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)}, 76 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)}, 77 {"multicast", IXGBE_NETDEV_STAT(multicast)}, 78 {"broadcast", IXGBE_STAT(stats.bprc)}, 79 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) }, 80 {"collisions", IXGBE_NETDEV_STAT(collisions)}, 81 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)}, 82 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)}, 83 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)}, 84 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)}, 85 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)}, 86 {"fdir_match", IXGBE_STAT(stats.fdirmatch)}, 87 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)}, 88 {"fdir_overflow", IXGBE_STAT(fdir_overflow)}, 89 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)}, 90 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)}, 91 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)}, 92 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)}, 93 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)}, 94 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)}, 95 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)}, 96 {"tx_restart_queue", IXGBE_STAT(restart_queue)}, 97 {"rx_long_length_errors", IXGBE_STAT(stats.roc)}, 98 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)}, 99 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)}, 100 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)}, 101 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)}, 102 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)}, 103 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)}, 104 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)}, 105 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)}, 106 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)}, 107 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)}, 108 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)}, 109 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)}, 110 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)}, 111 #ifdef IXGBE_FCOE 112 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)}, 113 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)}, 114 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)}, 115 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)}, 116 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)}, 117 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)}, 118 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)}, 119 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)}, 120 #endif /* IXGBE_FCOE */ 121 }; 122 123 #define IXGBE_QUEUE_STATS_LEN \ 124 ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \ 125 ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \ 126 (sizeof(struct ixgbe_queue_stats) / sizeof(u64))) 127 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats) 128 #define IXGBE_PB_STATS_LEN ( \ 129 (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \ 130 IXGBE_FLAG_DCB_ENABLED) ? \ 131 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \ 132 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \ 133 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \ 134 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \ 135 / sizeof(u64) : 0) 136 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \ 137 IXGBE_PB_STATS_LEN + \ 138 IXGBE_QUEUE_STATS_LEN) 139 140 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = { 141 "Register test (offline)", "Eeprom test (offline)", 142 "Interrupt test (offline)", "Loopback test (offline)", 143 "Link test (on/offline)" 144 }; 145 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN 146 147 static int ixgbe_get_settings(struct net_device *netdev, 148 struct ethtool_cmd *ecmd) 149 { 150 struct ixgbe_adapter *adapter = netdev_priv(netdev); 151 struct ixgbe_hw *hw = &adapter->hw; 152 u32 link_speed = 0; 153 bool link_up; 154 155 ecmd->supported = SUPPORTED_10000baseT_Full; 156 ecmd->autoneg = AUTONEG_ENABLE; 157 ecmd->transceiver = XCVR_EXTERNAL; 158 if ((hw->phy.media_type == ixgbe_media_type_copper) || 159 (hw->phy.multispeed_fiber)) { 160 ecmd->supported |= (SUPPORTED_1000baseT_Full | 161 SUPPORTED_Autoneg); 162 163 switch (hw->mac.type) { 164 case ixgbe_mac_X540: 165 ecmd->supported |= SUPPORTED_100baseT_Full; 166 break; 167 default: 168 break; 169 } 170 171 ecmd->advertising = ADVERTISED_Autoneg; 172 if (hw->phy.autoneg_advertised) { 173 if (hw->phy.autoneg_advertised & 174 IXGBE_LINK_SPEED_100_FULL) 175 ecmd->advertising |= ADVERTISED_100baseT_Full; 176 if (hw->phy.autoneg_advertised & 177 IXGBE_LINK_SPEED_10GB_FULL) 178 ecmd->advertising |= ADVERTISED_10000baseT_Full; 179 if (hw->phy.autoneg_advertised & 180 IXGBE_LINK_SPEED_1GB_FULL) 181 ecmd->advertising |= ADVERTISED_1000baseT_Full; 182 } else { 183 /* 184 * Default advertised modes in case 185 * phy.autoneg_advertised isn't set. 186 */ 187 ecmd->advertising |= (ADVERTISED_10000baseT_Full | 188 ADVERTISED_1000baseT_Full); 189 if (hw->mac.type == ixgbe_mac_X540) 190 ecmd->advertising |= ADVERTISED_100baseT_Full; 191 } 192 193 if (hw->phy.media_type == ixgbe_media_type_copper) { 194 ecmd->supported |= SUPPORTED_TP; 195 ecmd->advertising |= ADVERTISED_TP; 196 ecmd->port = PORT_TP; 197 } else { 198 ecmd->supported |= SUPPORTED_FIBRE; 199 ecmd->advertising |= ADVERTISED_FIBRE; 200 ecmd->port = PORT_FIBRE; 201 } 202 } else if (hw->phy.media_type == ixgbe_media_type_backplane) { 203 /* Set as FIBRE until SERDES defined in kernel */ 204 if (hw->device_id == IXGBE_DEV_ID_82598_BX) { 205 ecmd->supported = (SUPPORTED_1000baseT_Full | 206 SUPPORTED_FIBRE); 207 ecmd->advertising = (ADVERTISED_1000baseT_Full | 208 ADVERTISED_FIBRE); 209 ecmd->port = PORT_FIBRE; 210 ecmd->autoneg = AUTONEG_DISABLE; 211 } else if ((hw->device_id == IXGBE_DEV_ID_82599_COMBO_BACKPLANE) || 212 (hw->device_id == IXGBE_DEV_ID_82599_KX4_MEZZ)) { 213 ecmd->supported |= (SUPPORTED_1000baseT_Full | 214 SUPPORTED_Autoneg | 215 SUPPORTED_FIBRE); 216 ecmd->advertising = (ADVERTISED_10000baseT_Full | 217 ADVERTISED_1000baseT_Full | 218 ADVERTISED_Autoneg | 219 ADVERTISED_FIBRE); 220 ecmd->port = PORT_FIBRE; 221 } else { 222 ecmd->supported |= (SUPPORTED_1000baseT_Full | 223 SUPPORTED_FIBRE); 224 ecmd->advertising = (ADVERTISED_10000baseT_Full | 225 ADVERTISED_1000baseT_Full | 226 ADVERTISED_FIBRE); 227 ecmd->port = PORT_FIBRE; 228 } 229 } else { 230 ecmd->supported |= SUPPORTED_FIBRE; 231 ecmd->advertising = (ADVERTISED_10000baseT_Full | 232 ADVERTISED_FIBRE); 233 ecmd->port = PORT_FIBRE; 234 ecmd->autoneg = AUTONEG_DISABLE; 235 } 236 237 /* Get PHY type */ 238 switch (adapter->hw.phy.type) { 239 case ixgbe_phy_tn: 240 case ixgbe_phy_aq: 241 case ixgbe_phy_cu_unknown: 242 /* Copper 10G-BASET */ 243 ecmd->port = PORT_TP; 244 break; 245 case ixgbe_phy_qt: 246 ecmd->port = PORT_FIBRE; 247 break; 248 case ixgbe_phy_nl: 249 case ixgbe_phy_sfp_passive_tyco: 250 case ixgbe_phy_sfp_passive_unknown: 251 case ixgbe_phy_sfp_ftl: 252 case ixgbe_phy_sfp_avago: 253 case ixgbe_phy_sfp_intel: 254 case ixgbe_phy_sfp_unknown: 255 switch (adapter->hw.phy.sfp_type) { 256 /* SFP+ devices, further checking needed */ 257 case ixgbe_sfp_type_da_cu: 258 case ixgbe_sfp_type_da_cu_core0: 259 case ixgbe_sfp_type_da_cu_core1: 260 ecmd->port = PORT_DA; 261 break; 262 case ixgbe_sfp_type_sr: 263 case ixgbe_sfp_type_lr: 264 case ixgbe_sfp_type_srlr_core0: 265 case ixgbe_sfp_type_srlr_core1: 266 ecmd->port = PORT_FIBRE; 267 break; 268 case ixgbe_sfp_type_not_present: 269 ecmd->port = PORT_NONE; 270 break; 271 case ixgbe_sfp_type_1g_cu_core0: 272 case ixgbe_sfp_type_1g_cu_core1: 273 ecmd->port = PORT_TP; 274 ecmd->supported = SUPPORTED_TP; 275 ecmd->advertising = (ADVERTISED_1000baseT_Full | 276 ADVERTISED_TP); 277 break; 278 case ixgbe_sfp_type_unknown: 279 default: 280 ecmd->port = PORT_OTHER; 281 break; 282 } 283 break; 284 case ixgbe_phy_xaui: 285 ecmd->port = PORT_NONE; 286 break; 287 case ixgbe_phy_unknown: 288 case ixgbe_phy_generic: 289 case ixgbe_phy_sfp_unsupported: 290 default: 291 ecmd->port = PORT_OTHER; 292 break; 293 } 294 295 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 296 if (link_up) { 297 switch (link_speed) { 298 case IXGBE_LINK_SPEED_10GB_FULL: 299 ethtool_cmd_speed_set(ecmd, SPEED_10000); 300 break; 301 case IXGBE_LINK_SPEED_1GB_FULL: 302 ethtool_cmd_speed_set(ecmd, SPEED_1000); 303 break; 304 case IXGBE_LINK_SPEED_100_FULL: 305 ethtool_cmd_speed_set(ecmd, SPEED_100); 306 break; 307 default: 308 break; 309 } 310 ecmd->duplex = DUPLEX_FULL; 311 } else { 312 ethtool_cmd_speed_set(ecmd, -1); 313 ecmd->duplex = -1; 314 } 315 316 return 0; 317 } 318 319 static int ixgbe_set_settings(struct net_device *netdev, 320 struct ethtool_cmd *ecmd) 321 { 322 struct ixgbe_adapter *adapter = netdev_priv(netdev); 323 struct ixgbe_hw *hw = &adapter->hw; 324 u32 advertised, old; 325 s32 err = 0; 326 327 if ((hw->phy.media_type == ixgbe_media_type_copper) || 328 (hw->phy.multispeed_fiber)) { 329 /* 330 * this function does not support duplex forcing, but can 331 * limit the advertising of the adapter to the specified speed 332 */ 333 if (ecmd->autoneg == AUTONEG_DISABLE) 334 return -EINVAL; 335 336 if (ecmd->advertising & ~ecmd->supported) 337 return -EINVAL; 338 339 old = hw->phy.autoneg_advertised; 340 advertised = 0; 341 if (ecmd->advertising & ADVERTISED_10000baseT_Full) 342 advertised |= IXGBE_LINK_SPEED_10GB_FULL; 343 344 if (ecmd->advertising & ADVERTISED_1000baseT_Full) 345 advertised |= IXGBE_LINK_SPEED_1GB_FULL; 346 347 if (ecmd->advertising & ADVERTISED_100baseT_Full) 348 advertised |= IXGBE_LINK_SPEED_100_FULL; 349 350 if (old == advertised) 351 return err; 352 /* this sets the link speed and restarts auto-neg */ 353 hw->mac.autotry_restart = true; 354 err = hw->mac.ops.setup_link(hw, advertised, true, true); 355 if (err) { 356 e_info(probe, "setup link failed with code %d\n", err); 357 hw->mac.ops.setup_link(hw, old, true, true); 358 } 359 } else { 360 /* in this case we currently only support 10Gb/FULL */ 361 u32 speed = ethtool_cmd_speed(ecmd); 362 if ((ecmd->autoneg == AUTONEG_ENABLE) || 363 (ecmd->advertising != ADVERTISED_10000baseT_Full) || 364 (speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL)) 365 return -EINVAL; 366 } 367 368 return err; 369 } 370 371 static void ixgbe_get_pauseparam(struct net_device *netdev, 372 struct ethtool_pauseparam *pause) 373 { 374 struct ixgbe_adapter *adapter = netdev_priv(netdev); 375 struct ixgbe_hw *hw = &adapter->hw; 376 377 if (hw->fc.disable_fc_autoneg) 378 pause->autoneg = 0; 379 else 380 pause->autoneg = 1; 381 382 if (hw->fc.current_mode == ixgbe_fc_rx_pause) { 383 pause->rx_pause = 1; 384 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) { 385 pause->tx_pause = 1; 386 } else if (hw->fc.current_mode == ixgbe_fc_full) { 387 pause->rx_pause = 1; 388 pause->tx_pause = 1; 389 #ifdef CONFIG_DCB 390 } else if (hw->fc.current_mode == ixgbe_fc_pfc) { 391 pause->rx_pause = 0; 392 pause->tx_pause = 0; 393 #endif 394 } 395 } 396 397 static int ixgbe_set_pauseparam(struct net_device *netdev, 398 struct ethtool_pauseparam *pause) 399 { 400 struct ixgbe_adapter *adapter = netdev_priv(netdev); 401 struct ixgbe_hw *hw = &adapter->hw; 402 struct ixgbe_fc_info fc; 403 404 #ifdef CONFIG_DCB 405 if (adapter->dcb_cfg.pfc_mode_enable || 406 ((hw->mac.type == ixgbe_mac_82598EB) && 407 (adapter->flags & IXGBE_FLAG_DCB_ENABLED))) 408 return -EINVAL; 409 410 #endif 411 fc = hw->fc; 412 413 if (pause->autoneg != AUTONEG_ENABLE) 414 fc.disable_fc_autoneg = true; 415 else 416 fc.disable_fc_autoneg = false; 417 418 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg) 419 fc.requested_mode = ixgbe_fc_full; 420 else if (pause->rx_pause && !pause->tx_pause) 421 fc.requested_mode = ixgbe_fc_rx_pause; 422 else if (!pause->rx_pause && pause->tx_pause) 423 fc.requested_mode = ixgbe_fc_tx_pause; 424 else if (!pause->rx_pause && !pause->tx_pause) 425 fc.requested_mode = ixgbe_fc_none; 426 else 427 return -EINVAL; 428 429 #ifdef CONFIG_DCB 430 adapter->last_lfc_mode = fc.requested_mode; 431 #endif 432 433 /* if the thing changed then we'll update and use new autoneg */ 434 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) { 435 hw->fc = fc; 436 if (netif_running(netdev)) 437 ixgbe_reinit_locked(adapter); 438 else 439 ixgbe_reset(adapter); 440 } 441 442 return 0; 443 } 444 445 static u32 ixgbe_get_msglevel(struct net_device *netdev) 446 { 447 struct ixgbe_adapter *adapter = netdev_priv(netdev); 448 return adapter->msg_enable; 449 } 450 451 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data) 452 { 453 struct ixgbe_adapter *adapter = netdev_priv(netdev); 454 adapter->msg_enable = data; 455 } 456 457 static int ixgbe_get_regs_len(struct net_device *netdev) 458 { 459 #define IXGBE_REGS_LEN 1129 460 return IXGBE_REGS_LEN * sizeof(u32); 461 } 462 463 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_ 464 465 static void ixgbe_get_regs(struct net_device *netdev, 466 struct ethtool_regs *regs, void *p) 467 { 468 struct ixgbe_adapter *adapter = netdev_priv(netdev); 469 struct ixgbe_hw *hw = &adapter->hw; 470 u32 *regs_buff = p; 471 u8 i; 472 473 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32)); 474 475 regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id; 476 477 /* General Registers */ 478 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL); 479 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS); 480 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 481 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP); 482 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP); 483 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 484 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER); 485 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER); 486 487 /* NVM Register */ 488 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC); 489 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD); 490 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA); 491 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL); 492 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA); 493 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL); 494 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA); 495 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT); 496 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP); 497 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC); 498 499 /* Interrupt */ 500 /* don't read EICR because it can clear interrupt causes, instead 501 * read EICS which is a shadow but doesn't clear EICR */ 502 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS); 503 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS); 504 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS); 505 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC); 506 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC); 507 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM); 508 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0)); 509 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0)); 510 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT); 511 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA); 512 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0)); 513 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE); 514 515 /* Flow Control */ 516 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP); 517 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0)); 518 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1)); 519 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2)); 520 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3)); 521 for (i = 0; i < 8; i++) { 522 switch (hw->mac.type) { 523 case ixgbe_mac_82598EB: 524 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i)); 525 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i)); 526 break; 527 case ixgbe_mac_82599EB: 528 case ixgbe_mac_X540: 529 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i)); 530 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 531 break; 532 default: 533 break; 534 } 535 } 536 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV); 537 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS); 538 539 /* Receive DMA */ 540 for (i = 0; i < 64; i++) 541 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 542 for (i = 0; i < 64; i++) 543 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 544 for (i = 0; i < 64; i++) 545 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 546 for (i = 0; i < 64; i++) 547 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 548 for (i = 0; i < 64; i++) 549 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 550 for (i = 0; i < 64; i++) 551 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 552 for (i = 0; i < 16; i++) 553 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 554 for (i = 0; i < 16; i++) 555 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 556 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 557 for (i = 0; i < 8; i++) 558 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)); 559 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 560 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN); 561 562 /* Receive */ 563 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 564 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL); 565 for (i = 0; i < 16; i++) 566 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 567 for (i = 0; i < 16; i++) 568 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 569 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0)); 570 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL); 571 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 572 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL); 573 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC); 574 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 575 for (i = 0; i < 8; i++) 576 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i)); 577 for (i = 0; i < 8; i++) 578 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i)); 579 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP); 580 581 /* Transmit */ 582 for (i = 0; i < 32; i++) 583 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 584 for (i = 0; i < 32; i++) 585 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 586 for (i = 0; i < 32; i++) 587 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 588 for (i = 0; i < 32; i++) 589 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 590 for (i = 0; i < 32; i++) 591 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 592 for (i = 0; i < 32; i++) 593 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 594 for (i = 0; i < 32; i++) 595 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i)); 596 for (i = 0; i < 32; i++) 597 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i)); 598 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL); 599 for (i = 0; i < 16; i++) 600 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); 601 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG); 602 for (i = 0; i < 8; i++) 603 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i)); 604 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP); 605 606 /* Wake Up */ 607 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC); 608 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC); 609 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS); 610 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV); 611 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT); 612 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT); 613 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL); 614 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM); 615 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0)); 616 617 /* DCB */ 618 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); 619 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS); 620 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); 621 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR); 622 for (i = 0; i < 8; i++) 623 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i)); 624 for (i = 0; i < 8; i++) 625 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i)); 626 for (i = 0; i < 8; i++) 627 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i)); 628 for (i = 0; i < 8; i++) 629 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i)); 630 for (i = 0; i < 8; i++) 631 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); 632 for (i = 0; i < 8; i++) 633 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); 634 635 /* Statistics */ 636 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs); 637 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc); 638 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc); 639 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc); 640 for (i = 0; i < 8; i++) 641 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]); 642 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc); 643 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc); 644 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec); 645 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc); 646 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc); 647 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc); 648 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc); 649 for (i = 0; i < 8; i++) 650 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]); 651 for (i = 0; i < 8; i++) 652 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]); 653 for (i = 0; i < 8; i++) 654 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]); 655 for (i = 0; i < 8; i++) 656 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]); 657 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64); 658 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127); 659 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255); 660 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511); 661 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023); 662 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522); 663 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc); 664 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc); 665 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc); 666 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc); 667 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc); 668 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc); 669 for (i = 0; i < 8; i++) 670 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]); 671 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc); 672 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc); 673 regs_buff[956] = IXGBE_GET_STAT(adapter, roc); 674 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc); 675 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc); 676 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc); 677 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc); 678 regs_buff[961] = IXGBE_GET_STAT(adapter, tor); 679 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr); 680 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt); 681 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64); 682 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127); 683 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255); 684 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511); 685 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023); 686 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522); 687 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc); 688 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc); 689 regs_buff[973] = IXGBE_GET_STAT(adapter, xec); 690 for (i = 0; i < 16; i++) 691 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]); 692 for (i = 0; i < 16; i++) 693 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]); 694 for (i = 0; i < 16; i++) 695 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]); 696 for (i = 0; i < 16; i++) 697 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]); 698 699 /* MAC */ 700 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG); 701 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 702 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 703 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0); 704 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1); 705 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 706 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 707 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP); 708 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP); 709 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0); 710 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1); 711 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP); 712 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA); 713 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE); 714 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD); 715 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS); 716 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA); 717 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD); 718 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD); 719 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD); 720 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG); 721 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1); 722 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2); 723 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS); 724 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC); 725 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS); 726 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC); 727 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS); 728 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 729 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3); 730 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1); 731 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2); 732 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 733 734 /* Diagnostic */ 735 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL); 736 for (i = 0; i < 8; i++) 737 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i)); 738 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN); 739 for (i = 0; i < 4; i++) 740 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i)); 741 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE); 742 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL); 743 for (i = 0; i < 8; i++) 744 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i)); 745 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN); 746 for (i = 0; i < 4; i++) 747 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i)); 748 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE); 749 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL); 750 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0); 751 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1); 752 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2); 753 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3); 754 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL); 755 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0); 756 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1); 757 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2); 758 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3); 759 for (i = 0; i < 8; i++) 760 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i)); 761 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL); 762 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1); 763 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2); 764 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1); 765 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2); 766 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS); 767 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL); 768 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC); 769 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC); 770 771 /* 82599 X540 specific registers */ 772 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN); 773 } 774 775 static int ixgbe_get_eeprom_len(struct net_device *netdev) 776 { 777 struct ixgbe_adapter *adapter = netdev_priv(netdev); 778 return adapter->hw.eeprom.word_size * 2; 779 } 780 781 static int ixgbe_get_eeprom(struct net_device *netdev, 782 struct ethtool_eeprom *eeprom, u8 *bytes) 783 { 784 struct ixgbe_adapter *adapter = netdev_priv(netdev); 785 struct ixgbe_hw *hw = &adapter->hw; 786 u16 *eeprom_buff; 787 int first_word, last_word, eeprom_len; 788 int ret_val = 0; 789 u16 i; 790 791 if (eeprom->len == 0) 792 return -EINVAL; 793 794 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 795 796 first_word = eeprom->offset >> 1; 797 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 798 eeprom_len = last_word - first_word + 1; 799 800 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL); 801 if (!eeprom_buff) 802 return -ENOMEM; 803 804 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len, 805 eeprom_buff); 806 807 /* Device's eeprom is always little-endian, word addressable */ 808 for (i = 0; i < eeprom_len; i++) 809 le16_to_cpus(&eeprom_buff[i]); 810 811 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len); 812 kfree(eeprom_buff); 813 814 return ret_val; 815 } 816 817 static int ixgbe_set_eeprom(struct net_device *netdev, 818 struct ethtool_eeprom *eeprom, u8 *bytes) 819 { 820 struct ixgbe_adapter *adapter = netdev_priv(netdev); 821 struct ixgbe_hw *hw = &adapter->hw; 822 u16 *eeprom_buff; 823 void *ptr; 824 int max_len, first_word, last_word, ret_val = 0; 825 u16 i; 826 827 if (eeprom->len == 0) 828 return -EINVAL; 829 830 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 831 return -EINVAL; 832 833 max_len = hw->eeprom.word_size * 2; 834 835 first_word = eeprom->offset >> 1; 836 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 837 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 838 if (!eeprom_buff) 839 return -ENOMEM; 840 841 ptr = eeprom_buff; 842 843 if (eeprom->offset & 1) { 844 /* 845 * need read/modify/write of first changed EEPROM word 846 * only the second byte of the word is being modified 847 */ 848 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]); 849 if (ret_val) 850 goto err; 851 852 ptr++; 853 } 854 if ((eeprom->offset + eeprom->len) & 1) { 855 /* 856 * need read/modify/write of last changed EEPROM word 857 * only the first byte of the word is being modified 858 */ 859 ret_val = hw->eeprom.ops.read(hw, last_word, 860 &eeprom_buff[last_word - first_word]); 861 if (ret_val) 862 goto err; 863 } 864 865 /* Device's eeprom is always little-endian, word addressable */ 866 for (i = 0; i < last_word - first_word + 1; i++) 867 le16_to_cpus(&eeprom_buff[i]); 868 869 memcpy(ptr, bytes, eeprom->len); 870 871 for (i = 0; i < last_word - first_word + 1; i++) 872 cpu_to_le16s(&eeprom_buff[i]); 873 874 ret_val = hw->eeprom.ops.write_buffer(hw, first_word, 875 last_word - first_word + 1, 876 eeprom_buff); 877 878 /* Update the checksum */ 879 if (ret_val == 0) 880 hw->eeprom.ops.update_checksum(hw); 881 882 err: 883 kfree(eeprom_buff); 884 return ret_val; 885 } 886 887 static void ixgbe_get_drvinfo(struct net_device *netdev, 888 struct ethtool_drvinfo *drvinfo) 889 { 890 struct ixgbe_adapter *adapter = netdev_priv(netdev); 891 char firmware_version[32]; 892 u32 nvm_track_id; 893 894 strncpy(drvinfo->driver, ixgbe_driver_name, 895 sizeof(drvinfo->driver) - 1); 896 strncpy(drvinfo->version, ixgbe_driver_version, 897 sizeof(drvinfo->version) - 1); 898 899 nvm_track_id = (adapter->eeprom_verh << 16) | 900 adapter->eeprom_verl; 901 snprintf(firmware_version, sizeof(firmware_version), "0x%08x", 902 nvm_track_id); 903 904 strncpy(drvinfo->fw_version, firmware_version, 905 sizeof(drvinfo->fw_version) - 1); 906 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 907 sizeof(drvinfo->bus_info) - 1); 908 drvinfo->n_stats = IXGBE_STATS_LEN; 909 drvinfo->testinfo_len = IXGBE_TEST_LEN; 910 drvinfo->regdump_len = ixgbe_get_regs_len(netdev); 911 } 912 913 static void ixgbe_get_ringparam(struct net_device *netdev, 914 struct ethtool_ringparam *ring) 915 { 916 struct ixgbe_adapter *adapter = netdev_priv(netdev); 917 struct ixgbe_ring *tx_ring = adapter->tx_ring[0]; 918 struct ixgbe_ring *rx_ring = adapter->rx_ring[0]; 919 920 ring->rx_max_pending = IXGBE_MAX_RXD; 921 ring->tx_max_pending = IXGBE_MAX_TXD; 922 ring->rx_pending = rx_ring->count; 923 ring->tx_pending = tx_ring->count; 924 } 925 926 static int ixgbe_set_ringparam(struct net_device *netdev, 927 struct ethtool_ringparam *ring) 928 { 929 struct ixgbe_adapter *adapter = netdev_priv(netdev); 930 struct ixgbe_ring *temp_tx_ring, *temp_rx_ring; 931 int i, err = 0; 932 u32 new_rx_count, new_tx_count; 933 bool need_update = false; 934 935 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 936 return -EINVAL; 937 938 new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD); 939 new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD); 940 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE); 941 942 new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD); 943 new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD); 944 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE); 945 946 if ((new_tx_count == adapter->tx_ring[0]->count) && 947 (new_rx_count == adapter->rx_ring[0]->count)) { 948 /* nothing to do */ 949 return 0; 950 } 951 952 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 953 usleep_range(1000, 2000); 954 955 if (!netif_running(adapter->netdev)) { 956 for (i = 0; i < adapter->num_tx_queues; i++) 957 adapter->tx_ring[i]->count = new_tx_count; 958 for (i = 0; i < adapter->num_rx_queues; i++) 959 adapter->rx_ring[i]->count = new_rx_count; 960 adapter->tx_ring_count = new_tx_count; 961 adapter->rx_ring_count = new_rx_count; 962 goto clear_reset; 963 } 964 965 temp_tx_ring = vmalloc(adapter->num_tx_queues * sizeof(struct ixgbe_ring)); 966 if (!temp_tx_ring) { 967 err = -ENOMEM; 968 goto clear_reset; 969 } 970 971 if (new_tx_count != adapter->tx_ring_count) { 972 for (i = 0; i < adapter->num_tx_queues; i++) { 973 memcpy(&temp_tx_ring[i], adapter->tx_ring[i], 974 sizeof(struct ixgbe_ring)); 975 temp_tx_ring[i].count = new_tx_count; 976 err = ixgbe_setup_tx_resources(&temp_tx_ring[i]); 977 if (err) { 978 while (i) { 979 i--; 980 ixgbe_free_tx_resources(&temp_tx_ring[i]); 981 } 982 goto clear_reset; 983 } 984 } 985 need_update = true; 986 } 987 988 temp_rx_ring = vmalloc(adapter->num_rx_queues * sizeof(struct ixgbe_ring)); 989 if (!temp_rx_ring) { 990 err = -ENOMEM; 991 goto err_setup; 992 } 993 994 if (new_rx_count != adapter->rx_ring_count) { 995 for (i = 0; i < adapter->num_rx_queues; i++) { 996 memcpy(&temp_rx_ring[i], adapter->rx_ring[i], 997 sizeof(struct ixgbe_ring)); 998 temp_rx_ring[i].count = new_rx_count; 999 err = ixgbe_setup_rx_resources(&temp_rx_ring[i]); 1000 if (err) { 1001 while (i) { 1002 i--; 1003 ixgbe_free_rx_resources(&temp_rx_ring[i]); 1004 } 1005 goto err_setup; 1006 } 1007 } 1008 need_update = true; 1009 } 1010 1011 /* if rings need to be updated, here's the place to do it in one shot */ 1012 if (need_update) { 1013 ixgbe_down(adapter); 1014 1015 /* tx */ 1016 if (new_tx_count != adapter->tx_ring_count) { 1017 for (i = 0; i < adapter->num_tx_queues; i++) { 1018 ixgbe_free_tx_resources(adapter->tx_ring[i]); 1019 memcpy(adapter->tx_ring[i], &temp_tx_ring[i], 1020 sizeof(struct ixgbe_ring)); 1021 } 1022 adapter->tx_ring_count = new_tx_count; 1023 } 1024 1025 /* rx */ 1026 if (new_rx_count != adapter->rx_ring_count) { 1027 for (i = 0; i < adapter->num_rx_queues; i++) { 1028 ixgbe_free_rx_resources(adapter->rx_ring[i]); 1029 memcpy(adapter->rx_ring[i], &temp_rx_ring[i], 1030 sizeof(struct ixgbe_ring)); 1031 } 1032 adapter->rx_ring_count = new_rx_count; 1033 } 1034 ixgbe_up(adapter); 1035 } 1036 1037 vfree(temp_rx_ring); 1038 err_setup: 1039 vfree(temp_tx_ring); 1040 clear_reset: 1041 clear_bit(__IXGBE_RESETTING, &adapter->state); 1042 return err; 1043 } 1044 1045 static int ixgbe_get_sset_count(struct net_device *netdev, int sset) 1046 { 1047 switch (sset) { 1048 case ETH_SS_TEST: 1049 return IXGBE_TEST_LEN; 1050 case ETH_SS_STATS: 1051 return IXGBE_STATS_LEN; 1052 default: 1053 return -EOPNOTSUPP; 1054 } 1055 } 1056 1057 static void ixgbe_get_ethtool_stats(struct net_device *netdev, 1058 struct ethtool_stats *stats, u64 *data) 1059 { 1060 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1061 struct rtnl_link_stats64 temp; 1062 const struct rtnl_link_stats64 *net_stats; 1063 unsigned int start; 1064 struct ixgbe_ring *ring; 1065 int i, j; 1066 char *p = NULL; 1067 1068 ixgbe_update_stats(adapter); 1069 net_stats = dev_get_stats(netdev, &temp); 1070 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 1071 switch (ixgbe_gstrings_stats[i].type) { 1072 case NETDEV_STATS: 1073 p = (char *) net_stats + 1074 ixgbe_gstrings_stats[i].stat_offset; 1075 break; 1076 case IXGBE_STATS: 1077 p = (char *) adapter + 1078 ixgbe_gstrings_stats[i].stat_offset; 1079 break; 1080 } 1081 1082 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat == 1083 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 1084 } 1085 for (j = 0; j < adapter->num_tx_queues; j++) { 1086 ring = adapter->tx_ring[j]; 1087 do { 1088 start = u64_stats_fetch_begin_bh(&ring->syncp); 1089 data[i] = ring->stats.packets; 1090 data[i+1] = ring->stats.bytes; 1091 } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); 1092 i += 2; 1093 } 1094 for (j = 0; j < adapter->num_rx_queues; j++) { 1095 ring = adapter->rx_ring[j]; 1096 do { 1097 start = u64_stats_fetch_begin_bh(&ring->syncp); 1098 data[i] = ring->stats.packets; 1099 data[i+1] = ring->stats.bytes; 1100 } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); 1101 i += 2; 1102 } 1103 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { 1104 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) { 1105 data[i++] = adapter->stats.pxontxc[j]; 1106 data[i++] = adapter->stats.pxofftxc[j]; 1107 } 1108 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) { 1109 data[i++] = adapter->stats.pxonrxc[j]; 1110 data[i++] = adapter->stats.pxoffrxc[j]; 1111 } 1112 } 1113 } 1114 1115 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset, 1116 u8 *data) 1117 { 1118 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1119 char *p = (char *)data; 1120 int i; 1121 1122 switch (stringset) { 1123 case ETH_SS_TEST: 1124 memcpy(data, *ixgbe_gstrings_test, 1125 IXGBE_TEST_LEN * ETH_GSTRING_LEN); 1126 break; 1127 case ETH_SS_STATS: 1128 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 1129 memcpy(p, ixgbe_gstrings_stats[i].stat_string, 1130 ETH_GSTRING_LEN); 1131 p += ETH_GSTRING_LEN; 1132 } 1133 for (i = 0; i < adapter->num_tx_queues; i++) { 1134 sprintf(p, "tx_queue_%u_packets", i); 1135 p += ETH_GSTRING_LEN; 1136 sprintf(p, "tx_queue_%u_bytes", i); 1137 p += ETH_GSTRING_LEN; 1138 } 1139 for (i = 0; i < adapter->num_rx_queues; i++) { 1140 sprintf(p, "rx_queue_%u_packets", i); 1141 p += ETH_GSTRING_LEN; 1142 sprintf(p, "rx_queue_%u_bytes", i); 1143 p += ETH_GSTRING_LEN; 1144 } 1145 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { 1146 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 1147 sprintf(p, "tx_pb_%u_pxon", i); 1148 p += ETH_GSTRING_LEN; 1149 sprintf(p, "tx_pb_%u_pxoff", i); 1150 p += ETH_GSTRING_LEN; 1151 } 1152 for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) { 1153 sprintf(p, "rx_pb_%u_pxon", i); 1154 p += ETH_GSTRING_LEN; 1155 sprintf(p, "rx_pb_%u_pxoff", i); 1156 p += ETH_GSTRING_LEN; 1157 } 1158 } 1159 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */ 1160 break; 1161 } 1162 } 1163 1164 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data) 1165 { 1166 struct ixgbe_hw *hw = &adapter->hw; 1167 bool link_up; 1168 u32 link_speed = 0; 1169 *data = 0; 1170 1171 hw->mac.ops.check_link(hw, &link_speed, &link_up, true); 1172 if (link_up) 1173 return *data; 1174 else 1175 *data = 1; 1176 return *data; 1177 } 1178 1179 /* ethtool register test data */ 1180 struct ixgbe_reg_test { 1181 u16 reg; 1182 u8 array_len; 1183 u8 test_type; 1184 u32 mask; 1185 u32 write; 1186 }; 1187 1188 /* In the hardware, registers are laid out either singly, in arrays 1189 * spaced 0x40 bytes apart, or in contiguous tables. We assume 1190 * most tests take place on arrays or single registers (handled 1191 * as a single-element array) and special-case the tables. 1192 * Table tests are always pattern tests. 1193 * 1194 * We also make provision for some required setup steps by specifying 1195 * registers to be written without any read-back testing. 1196 */ 1197 1198 #define PATTERN_TEST 1 1199 #define SET_READ_TEST 2 1200 #define WRITE_NO_TEST 3 1201 #define TABLE32_TEST 4 1202 #define TABLE64_TEST_LO 5 1203 #define TABLE64_TEST_HI 6 1204 1205 /* default 82599 register test */ 1206 static const struct ixgbe_reg_test reg_test_82599[] = { 1207 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1208 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1209 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1210 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1211 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 }, 1212 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1213 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1214 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1215 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1216 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1217 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1218 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1219 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1220 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1221 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 }, 1222 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 }, 1223 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1224 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF }, 1225 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1226 { 0, 0, 0, 0 } 1227 }; 1228 1229 /* default 82598 register test */ 1230 static const struct ixgbe_reg_test reg_test_82598[] = { 1231 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1232 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1233 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1234 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1235 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1236 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1237 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1238 /* Enable all four RX queues before testing. */ 1239 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1240 /* RDH is read-only for 82598, only test RDT. */ 1241 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1242 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1243 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1244 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1245 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF }, 1246 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1247 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1248 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1249 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 }, 1250 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 }, 1251 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1252 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF }, 1253 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1254 { 0, 0, 0, 0 } 1255 }; 1256 1257 static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg, 1258 u32 mask, u32 write) 1259 { 1260 u32 pat, val, before; 1261 static const u32 test_pattern[] = { 1262 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1263 1264 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) { 1265 before = readl(adapter->hw.hw_addr + reg); 1266 writel((test_pattern[pat] & write), 1267 (adapter->hw.hw_addr + reg)); 1268 val = readl(adapter->hw.hw_addr + reg); 1269 if (val != (test_pattern[pat] & write & mask)) { 1270 e_err(drv, "pattern test reg %04X failed: got " 1271 "0x%08X expected 0x%08X\n", 1272 reg, val, (test_pattern[pat] & write & mask)); 1273 *data = reg; 1274 writel(before, adapter->hw.hw_addr + reg); 1275 return 1; 1276 } 1277 writel(before, adapter->hw.hw_addr + reg); 1278 } 1279 return 0; 1280 } 1281 1282 static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg, 1283 u32 mask, u32 write) 1284 { 1285 u32 val, before; 1286 before = readl(adapter->hw.hw_addr + reg); 1287 writel((write & mask), (adapter->hw.hw_addr + reg)); 1288 val = readl(adapter->hw.hw_addr + reg); 1289 if ((write & mask) != (val & mask)) { 1290 e_err(drv, "set/check reg %04X test failed: got 0x%08X " 1291 "expected 0x%08X\n", reg, (val & mask), (write & mask)); 1292 *data = reg; 1293 writel(before, (adapter->hw.hw_addr + reg)); 1294 return 1; 1295 } 1296 writel(before, (adapter->hw.hw_addr + reg)); 1297 return 0; 1298 } 1299 1300 #define REG_PATTERN_TEST(reg, mask, write) \ 1301 do { \ 1302 if (reg_pattern_test(adapter, data, reg, mask, write)) \ 1303 return 1; \ 1304 } while (0) \ 1305 1306 1307 #define REG_SET_AND_CHECK(reg, mask, write) \ 1308 do { \ 1309 if (reg_set_and_check(adapter, data, reg, mask, write)) \ 1310 return 1; \ 1311 } while (0) \ 1312 1313 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data) 1314 { 1315 const struct ixgbe_reg_test *test; 1316 u32 value, before, after; 1317 u32 i, toggle; 1318 1319 switch (adapter->hw.mac.type) { 1320 case ixgbe_mac_82598EB: 1321 toggle = 0x7FFFF3FF; 1322 test = reg_test_82598; 1323 break; 1324 case ixgbe_mac_82599EB: 1325 case ixgbe_mac_X540: 1326 toggle = 0x7FFFF30F; 1327 test = reg_test_82599; 1328 break; 1329 default: 1330 *data = 1; 1331 return 1; 1332 break; 1333 } 1334 1335 /* 1336 * Because the status register is such a special case, 1337 * we handle it separately from the rest of the register 1338 * tests. Some bits are read-only, some toggle, and some 1339 * are writeable on newer MACs. 1340 */ 1341 before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS); 1342 value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle); 1343 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle); 1344 after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle; 1345 if (value != after) { 1346 e_err(drv, "failed STATUS register test got: 0x%08X " 1347 "expected: 0x%08X\n", after, value); 1348 *data = 1; 1349 return 1; 1350 } 1351 /* restore previous status */ 1352 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before); 1353 1354 /* 1355 * Perform the remainder of the register test, looping through 1356 * the test table until we either fail or reach the null entry. 1357 */ 1358 while (test->reg) { 1359 for (i = 0; i < test->array_len; i++) { 1360 switch (test->test_type) { 1361 case PATTERN_TEST: 1362 REG_PATTERN_TEST(test->reg + (i * 0x40), 1363 test->mask, 1364 test->write); 1365 break; 1366 case SET_READ_TEST: 1367 REG_SET_AND_CHECK(test->reg + (i * 0x40), 1368 test->mask, 1369 test->write); 1370 break; 1371 case WRITE_NO_TEST: 1372 writel(test->write, 1373 (adapter->hw.hw_addr + test->reg) 1374 + (i * 0x40)); 1375 break; 1376 case TABLE32_TEST: 1377 REG_PATTERN_TEST(test->reg + (i * 4), 1378 test->mask, 1379 test->write); 1380 break; 1381 case TABLE64_TEST_LO: 1382 REG_PATTERN_TEST(test->reg + (i * 8), 1383 test->mask, 1384 test->write); 1385 break; 1386 case TABLE64_TEST_HI: 1387 REG_PATTERN_TEST((test->reg + 4) + (i * 8), 1388 test->mask, 1389 test->write); 1390 break; 1391 } 1392 } 1393 test++; 1394 } 1395 1396 *data = 0; 1397 return 0; 1398 } 1399 1400 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data) 1401 { 1402 struct ixgbe_hw *hw = &adapter->hw; 1403 if (hw->eeprom.ops.validate_checksum(hw, NULL)) 1404 *data = 1; 1405 else 1406 *data = 0; 1407 return *data; 1408 } 1409 1410 static irqreturn_t ixgbe_test_intr(int irq, void *data) 1411 { 1412 struct net_device *netdev = (struct net_device *) data; 1413 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1414 1415 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR); 1416 1417 return IRQ_HANDLED; 1418 } 1419 1420 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data) 1421 { 1422 struct net_device *netdev = adapter->netdev; 1423 u32 mask, i = 0, shared_int = true; 1424 u32 irq = adapter->pdev->irq; 1425 1426 *data = 0; 1427 1428 /* Hook up test interrupt handler just for this test */ 1429 if (adapter->msix_entries) { 1430 /* NOTE: we don't test MSI-X interrupts here, yet */ 1431 return 0; 1432 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { 1433 shared_int = false; 1434 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name, 1435 netdev)) { 1436 *data = 1; 1437 return -1; 1438 } 1439 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED, 1440 netdev->name, netdev)) { 1441 shared_int = false; 1442 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED, 1443 netdev->name, netdev)) { 1444 *data = 1; 1445 return -1; 1446 } 1447 e_info(hw, "testing %s interrupt\n", shared_int ? 1448 "shared" : "unshared"); 1449 1450 /* Disable all the interrupts */ 1451 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1452 IXGBE_WRITE_FLUSH(&adapter->hw); 1453 usleep_range(10000, 20000); 1454 1455 /* Test each interrupt */ 1456 for (; i < 10; i++) { 1457 /* Interrupt to test */ 1458 mask = 1 << i; 1459 1460 if (!shared_int) { 1461 /* 1462 * Disable the interrupts to be reported in 1463 * the cause register and then force the same 1464 * interrupt and see if one gets posted. If 1465 * an interrupt was posted to the bus, the 1466 * test failed. 1467 */ 1468 adapter->test_icr = 0; 1469 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 1470 ~mask & 0x00007FFF); 1471 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1472 ~mask & 0x00007FFF); 1473 IXGBE_WRITE_FLUSH(&adapter->hw); 1474 usleep_range(10000, 20000); 1475 1476 if (adapter->test_icr & mask) { 1477 *data = 3; 1478 break; 1479 } 1480 } 1481 1482 /* 1483 * Enable the interrupt to be reported in the cause 1484 * register and then force the same interrupt and see 1485 * if one gets posted. If an interrupt was not posted 1486 * to the bus, the test failed. 1487 */ 1488 adapter->test_icr = 0; 1489 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 1490 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 1491 IXGBE_WRITE_FLUSH(&adapter->hw); 1492 usleep_range(10000, 20000); 1493 1494 if (!(adapter->test_icr &mask)) { 1495 *data = 4; 1496 break; 1497 } 1498 1499 if (!shared_int) { 1500 /* 1501 * Disable the other interrupts to be reported in 1502 * the cause register and then force the other 1503 * interrupts and see if any get posted. If 1504 * an interrupt was posted to the bus, the 1505 * test failed. 1506 */ 1507 adapter->test_icr = 0; 1508 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 1509 ~mask & 0x00007FFF); 1510 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1511 ~mask & 0x00007FFF); 1512 IXGBE_WRITE_FLUSH(&adapter->hw); 1513 usleep_range(10000, 20000); 1514 1515 if (adapter->test_icr) { 1516 *data = 5; 1517 break; 1518 } 1519 } 1520 } 1521 1522 /* Disable all the interrupts */ 1523 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1524 IXGBE_WRITE_FLUSH(&adapter->hw); 1525 usleep_range(10000, 20000); 1526 1527 /* Unhook test interrupt handler */ 1528 free_irq(irq, netdev); 1529 1530 return *data; 1531 } 1532 1533 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter) 1534 { 1535 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1536 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1537 struct ixgbe_hw *hw = &adapter->hw; 1538 u32 reg_ctl; 1539 1540 /* shut down the DMA engines now so they can be reinitialized later */ 1541 1542 /* first Rx */ 1543 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1544 reg_ctl &= ~IXGBE_RXCTRL_RXEN; 1545 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl); 1546 ixgbe_disable_rx_queue(adapter, rx_ring); 1547 1548 /* now Tx */ 1549 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx)); 1550 reg_ctl &= ~IXGBE_TXDCTL_ENABLE; 1551 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl); 1552 1553 switch (hw->mac.type) { 1554 case ixgbe_mac_82599EB: 1555 case ixgbe_mac_X540: 1556 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1557 reg_ctl &= ~IXGBE_DMATXCTL_TE; 1558 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl); 1559 break; 1560 default: 1561 break; 1562 } 1563 1564 ixgbe_reset(adapter); 1565 1566 ixgbe_free_tx_resources(&adapter->test_tx_ring); 1567 ixgbe_free_rx_resources(&adapter->test_rx_ring); 1568 } 1569 1570 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter) 1571 { 1572 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1573 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1574 u32 rctl, reg_data; 1575 int ret_val; 1576 int err; 1577 1578 /* Setup Tx descriptor ring and Tx buffers */ 1579 tx_ring->count = IXGBE_DEFAULT_TXD; 1580 tx_ring->queue_index = 0; 1581 tx_ring->dev = &adapter->pdev->dev; 1582 tx_ring->netdev = adapter->netdev; 1583 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx; 1584 tx_ring->numa_node = adapter->node; 1585 1586 err = ixgbe_setup_tx_resources(tx_ring); 1587 if (err) 1588 return 1; 1589 1590 switch (adapter->hw.mac.type) { 1591 case ixgbe_mac_82599EB: 1592 case ixgbe_mac_X540: 1593 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL); 1594 reg_data |= IXGBE_DMATXCTL_TE; 1595 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data); 1596 break; 1597 default: 1598 break; 1599 } 1600 1601 ixgbe_configure_tx_ring(adapter, tx_ring); 1602 1603 /* Setup Rx Descriptor ring and Rx buffers */ 1604 rx_ring->count = IXGBE_DEFAULT_RXD; 1605 rx_ring->queue_index = 0; 1606 rx_ring->dev = &adapter->pdev->dev; 1607 rx_ring->netdev = adapter->netdev; 1608 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx; 1609 rx_ring->rx_buf_len = IXGBE_RXBUFFER_2K; 1610 rx_ring->numa_node = adapter->node; 1611 1612 err = ixgbe_setup_rx_resources(rx_ring); 1613 if (err) { 1614 ret_val = 4; 1615 goto err_nomem; 1616 } 1617 1618 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL); 1619 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN); 1620 1621 ixgbe_configure_rx_ring(adapter, rx_ring); 1622 1623 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS; 1624 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl); 1625 1626 return 0; 1627 1628 err_nomem: 1629 ixgbe_free_desc_rings(adapter); 1630 return ret_val; 1631 } 1632 1633 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter) 1634 { 1635 struct ixgbe_hw *hw = &adapter->hw; 1636 u32 reg_data; 1637 1638 /* X540 needs to set the MACC.FLU bit to force link up */ 1639 if (adapter->hw.mac.type == ixgbe_mac_X540) { 1640 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC); 1641 reg_data |= IXGBE_MACC_FLU; 1642 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data); 1643 } 1644 1645 /* right now we only support MAC loopback in the driver */ 1646 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0); 1647 /* Setup MAC loopback */ 1648 reg_data |= IXGBE_HLREG0_LPBK; 1649 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data); 1650 1651 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1652 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE; 1653 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data); 1654 1655 reg_data = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1656 reg_data &= ~IXGBE_AUTOC_LMS_MASK; 1657 reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU; 1658 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data); 1659 IXGBE_WRITE_FLUSH(hw); 1660 usleep_range(10000, 20000); 1661 1662 /* Disable Atlas Tx lanes; re-enabled in reset path */ 1663 if (hw->mac.type == ixgbe_mac_82598EB) { 1664 u8 atlas; 1665 1666 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas); 1667 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN; 1668 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas); 1669 1670 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas); 1671 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 1672 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas); 1673 1674 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas); 1675 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 1676 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas); 1677 1678 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas); 1679 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 1680 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas); 1681 } 1682 1683 return 0; 1684 } 1685 1686 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter) 1687 { 1688 u32 reg_data; 1689 1690 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0); 1691 reg_data &= ~IXGBE_HLREG0_LPBK; 1692 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data); 1693 } 1694 1695 static void ixgbe_create_lbtest_frame(struct sk_buff *skb, 1696 unsigned int frame_size) 1697 { 1698 memset(skb->data, 0xFF, frame_size); 1699 frame_size &= ~1; 1700 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1); 1701 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1); 1702 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1); 1703 } 1704 1705 static int ixgbe_check_lbtest_frame(struct sk_buff *skb, 1706 unsigned int frame_size) 1707 { 1708 frame_size &= ~1; 1709 if (*(skb->data + 3) == 0xFF) { 1710 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) && 1711 (*(skb->data + frame_size / 2 + 12) == 0xAF)) { 1712 return 0; 1713 } 1714 } 1715 return 13; 1716 } 1717 1718 static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring, 1719 struct ixgbe_ring *tx_ring, 1720 unsigned int size) 1721 { 1722 union ixgbe_adv_rx_desc *rx_desc; 1723 struct ixgbe_rx_buffer *rx_buffer_info; 1724 struct ixgbe_tx_buffer *tx_buffer_info; 1725 const int bufsz = rx_ring->rx_buf_len; 1726 u32 staterr; 1727 u16 rx_ntc, tx_ntc, count = 0; 1728 1729 /* initialize next to clean and descriptor values */ 1730 rx_ntc = rx_ring->next_to_clean; 1731 tx_ntc = tx_ring->next_to_clean; 1732 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, rx_ntc); 1733 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1734 1735 while (staterr & IXGBE_RXD_STAT_DD) { 1736 /* check Rx buffer */ 1737 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc]; 1738 1739 /* unmap Rx buffer, will be remapped by alloc_rx_buffers */ 1740 dma_unmap_single(rx_ring->dev, 1741 rx_buffer_info->dma, 1742 bufsz, 1743 DMA_FROM_DEVICE); 1744 rx_buffer_info->dma = 0; 1745 1746 /* verify contents of skb */ 1747 if (!ixgbe_check_lbtest_frame(rx_buffer_info->skb, size)) 1748 count++; 1749 1750 /* unmap buffer on Tx side */ 1751 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc]; 1752 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); 1753 1754 /* increment Rx/Tx next to clean counters */ 1755 rx_ntc++; 1756 if (rx_ntc == rx_ring->count) 1757 rx_ntc = 0; 1758 tx_ntc++; 1759 if (tx_ntc == tx_ring->count) 1760 tx_ntc = 0; 1761 1762 /* fetch next descriptor */ 1763 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, rx_ntc); 1764 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1765 } 1766 1767 /* re-map buffers to ring, store next to clean values */ 1768 ixgbe_alloc_rx_buffers(rx_ring, count); 1769 rx_ring->next_to_clean = rx_ntc; 1770 tx_ring->next_to_clean = tx_ntc; 1771 1772 return count; 1773 } 1774 1775 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter) 1776 { 1777 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1778 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1779 int i, j, lc, good_cnt, ret_val = 0; 1780 unsigned int size = 1024; 1781 netdev_tx_t tx_ret_val; 1782 struct sk_buff *skb; 1783 1784 /* allocate test skb */ 1785 skb = alloc_skb(size, GFP_KERNEL); 1786 if (!skb) 1787 return 11; 1788 1789 /* place data into test skb */ 1790 ixgbe_create_lbtest_frame(skb, size); 1791 skb_put(skb, size); 1792 1793 /* 1794 * Calculate the loop count based on the largest descriptor ring 1795 * The idea is to wrap the largest ring a number of times using 64 1796 * send/receive pairs during each loop 1797 */ 1798 1799 if (rx_ring->count <= tx_ring->count) 1800 lc = ((tx_ring->count / 64) * 2) + 1; 1801 else 1802 lc = ((rx_ring->count / 64) * 2) + 1; 1803 1804 for (j = 0; j <= lc; j++) { 1805 /* reset count of good packets */ 1806 good_cnt = 0; 1807 1808 /* place 64 packets on the transmit queue*/ 1809 for (i = 0; i < 64; i++) { 1810 skb_get(skb); 1811 tx_ret_val = ixgbe_xmit_frame_ring(skb, 1812 adapter, 1813 tx_ring); 1814 if (tx_ret_val == NETDEV_TX_OK) 1815 good_cnt++; 1816 } 1817 1818 if (good_cnt != 64) { 1819 ret_val = 12; 1820 break; 1821 } 1822 1823 /* allow 200 milliseconds for packets to go from Tx to Rx */ 1824 msleep(200); 1825 1826 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size); 1827 if (good_cnt != 64) { 1828 ret_val = 13; 1829 break; 1830 } 1831 } 1832 1833 /* free the original skb */ 1834 kfree_skb(skb); 1835 1836 return ret_val; 1837 } 1838 1839 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data) 1840 { 1841 *data = ixgbe_setup_desc_rings(adapter); 1842 if (*data) 1843 goto out; 1844 *data = ixgbe_setup_loopback_test(adapter); 1845 if (*data) 1846 goto err_loopback; 1847 *data = ixgbe_run_loopback_test(adapter); 1848 ixgbe_loopback_cleanup(adapter); 1849 1850 err_loopback: 1851 ixgbe_free_desc_rings(adapter); 1852 out: 1853 return *data; 1854 } 1855 1856 static void ixgbe_diag_test(struct net_device *netdev, 1857 struct ethtool_test *eth_test, u64 *data) 1858 { 1859 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1860 bool if_running = netif_running(netdev); 1861 1862 set_bit(__IXGBE_TESTING, &adapter->state); 1863 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 1864 /* Offline tests */ 1865 1866 e_info(hw, "offline testing starting\n"); 1867 1868 /* Link test performed before hardware reset so autoneg doesn't 1869 * interfere with test result */ 1870 if (ixgbe_link_test(adapter, &data[4])) 1871 eth_test->flags |= ETH_TEST_FL_FAILED; 1872 1873 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 1874 int i; 1875 for (i = 0; i < adapter->num_vfs; i++) { 1876 if (adapter->vfinfo[i].clear_to_send) { 1877 netdev_warn(netdev, "%s", 1878 "offline diagnostic is not " 1879 "supported when VFs are " 1880 "present\n"); 1881 data[0] = 1; 1882 data[1] = 1; 1883 data[2] = 1; 1884 data[3] = 1; 1885 eth_test->flags |= ETH_TEST_FL_FAILED; 1886 clear_bit(__IXGBE_TESTING, 1887 &adapter->state); 1888 goto skip_ol_tests; 1889 } 1890 } 1891 } 1892 1893 if (if_running) 1894 /* indicate we're in test mode */ 1895 dev_close(netdev); 1896 else 1897 ixgbe_reset(adapter); 1898 1899 e_info(hw, "register testing starting\n"); 1900 if (ixgbe_reg_test(adapter, &data[0])) 1901 eth_test->flags |= ETH_TEST_FL_FAILED; 1902 1903 ixgbe_reset(adapter); 1904 e_info(hw, "eeprom testing starting\n"); 1905 if (ixgbe_eeprom_test(adapter, &data[1])) 1906 eth_test->flags |= ETH_TEST_FL_FAILED; 1907 1908 ixgbe_reset(adapter); 1909 e_info(hw, "interrupt testing starting\n"); 1910 if (ixgbe_intr_test(adapter, &data[2])) 1911 eth_test->flags |= ETH_TEST_FL_FAILED; 1912 1913 /* If SRIOV or VMDq is enabled then skip MAC 1914 * loopback diagnostic. */ 1915 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED | 1916 IXGBE_FLAG_VMDQ_ENABLED)) { 1917 e_info(hw, "Skip MAC loopback diagnostic in VT " 1918 "mode\n"); 1919 data[3] = 0; 1920 goto skip_loopback; 1921 } 1922 1923 ixgbe_reset(adapter); 1924 e_info(hw, "loopback testing starting\n"); 1925 if (ixgbe_loopback_test(adapter, &data[3])) 1926 eth_test->flags |= ETH_TEST_FL_FAILED; 1927 1928 skip_loopback: 1929 ixgbe_reset(adapter); 1930 1931 clear_bit(__IXGBE_TESTING, &adapter->state); 1932 if (if_running) 1933 dev_open(netdev); 1934 } else { 1935 e_info(hw, "online testing starting\n"); 1936 /* Online tests */ 1937 if (ixgbe_link_test(adapter, &data[4])) 1938 eth_test->flags |= ETH_TEST_FL_FAILED; 1939 1940 /* Online tests aren't run; pass by default */ 1941 data[0] = 0; 1942 data[1] = 0; 1943 data[2] = 0; 1944 data[3] = 0; 1945 1946 clear_bit(__IXGBE_TESTING, &adapter->state); 1947 } 1948 skip_ol_tests: 1949 msleep_interruptible(4 * 1000); 1950 } 1951 1952 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter, 1953 struct ethtool_wolinfo *wol) 1954 { 1955 struct ixgbe_hw *hw = &adapter->hw; 1956 int retval = 1; 1957 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 1958 1959 /* WOL not supported except for the following */ 1960 switch(hw->device_id) { 1961 case IXGBE_DEV_ID_82599_SFP: 1962 /* Only this subdevice supports WOL */ 1963 if (hw->subsystem_device_id != IXGBE_SUBDEV_ID_82599_SFP) { 1964 wol->supported = 0; 1965 break; 1966 } 1967 retval = 0; 1968 break; 1969 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 1970 /* All except this subdevice support WOL */ 1971 if (hw->subsystem_device_id == 1972 IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) { 1973 wol->supported = 0; 1974 break; 1975 } 1976 retval = 0; 1977 break; 1978 case IXGBE_DEV_ID_82599_KX4: 1979 retval = 0; 1980 break; 1981 case IXGBE_DEV_ID_X540T: 1982 /* check eeprom to see if enabled wol */ 1983 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 1984 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 1985 (hw->bus.func == 0))) { 1986 retval = 0; 1987 break; 1988 } 1989 1990 /* All others not supported */ 1991 wol->supported = 0; 1992 break; 1993 default: 1994 wol->supported = 0; 1995 } 1996 1997 return retval; 1998 } 1999 2000 static void ixgbe_get_wol(struct net_device *netdev, 2001 struct ethtool_wolinfo *wol) 2002 { 2003 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2004 2005 wol->supported = WAKE_UCAST | WAKE_MCAST | 2006 WAKE_BCAST | WAKE_MAGIC; 2007 wol->wolopts = 0; 2008 2009 if (ixgbe_wol_exclusion(adapter, wol) || 2010 !device_can_wakeup(&adapter->pdev->dev)) 2011 return; 2012 2013 if (adapter->wol & IXGBE_WUFC_EX) 2014 wol->wolopts |= WAKE_UCAST; 2015 if (adapter->wol & IXGBE_WUFC_MC) 2016 wol->wolopts |= WAKE_MCAST; 2017 if (adapter->wol & IXGBE_WUFC_BC) 2018 wol->wolopts |= WAKE_BCAST; 2019 if (adapter->wol & IXGBE_WUFC_MAG) 2020 wol->wolopts |= WAKE_MAGIC; 2021 } 2022 2023 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2024 { 2025 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2026 2027 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE)) 2028 return -EOPNOTSUPP; 2029 2030 if (ixgbe_wol_exclusion(adapter, wol)) 2031 return wol->wolopts ? -EOPNOTSUPP : 0; 2032 2033 adapter->wol = 0; 2034 2035 if (wol->wolopts & WAKE_UCAST) 2036 adapter->wol |= IXGBE_WUFC_EX; 2037 if (wol->wolopts & WAKE_MCAST) 2038 adapter->wol |= IXGBE_WUFC_MC; 2039 if (wol->wolopts & WAKE_BCAST) 2040 adapter->wol |= IXGBE_WUFC_BC; 2041 if (wol->wolopts & WAKE_MAGIC) 2042 adapter->wol |= IXGBE_WUFC_MAG; 2043 2044 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2045 2046 return 0; 2047 } 2048 2049 static int ixgbe_nway_reset(struct net_device *netdev) 2050 { 2051 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2052 2053 if (netif_running(netdev)) 2054 ixgbe_reinit_locked(adapter); 2055 2056 return 0; 2057 } 2058 2059 static int ixgbe_set_phys_id(struct net_device *netdev, 2060 enum ethtool_phys_id_state state) 2061 { 2062 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2063 struct ixgbe_hw *hw = &adapter->hw; 2064 2065 switch (state) { 2066 case ETHTOOL_ID_ACTIVE: 2067 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2068 return 2; 2069 2070 case ETHTOOL_ID_ON: 2071 hw->mac.ops.led_on(hw, IXGBE_LED_ON); 2072 break; 2073 2074 case ETHTOOL_ID_OFF: 2075 hw->mac.ops.led_off(hw, IXGBE_LED_ON); 2076 break; 2077 2078 case ETHTOOL_ID_INACTIVE: 2079 /* Restore LED settings */ 2080 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg); 2081 break; 2082 } 2083 2084 return 0; 2085 } 2086 2087 static int ixgbe_get_coalesce(struct net_device *netdev, 2088 struct ethtool_coalesce *ec) 2089 { 2090 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2091 2092 ec->tx_max_coalesced_frames_irq = adapter->tx_work_limit; 2093 2094 /* only valid if in constant ITR mode */ 2095 if (adapter->rx_itr_setting <= 1) 2096 ec->rx_coalesce_usecs = adapter->rx_itr_setting; 2097 else 2098 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; 2099 2100 /* if in mixed tx/rx queues per vector mode, report only rx settings */ 2101 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) 2102 return 0; 2103 2104 /* only valid if in constant ITR mode */ 2105 if (adapter->tx_itr_setting <= 1) 2106 ec->tx_coalesce_usecs = adapter->tx_itr_setting; 2107 else 2108 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; 2109 2110 return 0; 2111 } 2112 2113 /* 2114 * this function must be called before setting the new value of 2115 * rx_itr_setting 2116 */ 2117 static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter, 2118 struct ethtool_coalesce *ec) 2119 { 2120 struct net_device *netdev = adapter->netdev; 2121 2122 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 2123 return false; 2124 2125 /* if interrupt rate is too high then disable RSC */ 2126 if (ec->rx_coalesce_usecs != 1 && 2127 ec->rx_coalesce_usecs <= (IXGBE_MIN_RSC_ITR >> 2)) { 2128 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 2129 e_info(probe, "rx-usecs set too low, disabling RSC\n"); 2130 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 2131 return true; 2132 } 2133 } else { 2134 /* check the feature flag value and enable RSC if necessary */ 2135 if ((netdev->features & NETIF_F_LRO) && 2136 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 2137 e_info(probe, "rx-usecs set to %d, re-enabling RSC\n", 2138 ec->rx_coalesce_usecs); 2139 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 2140 return true; 2141 } 2142 } 2143 return false; 2144 } 2145 2146 static int ixgbe_set_coalesce(struct net_device *netdev, 2147 struct ethtool_coalesce *ec) 2148 { 2149 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2150 struct ixgbe_q_vector *q_vector; 2151 int i; 2152 int num_vectors; 2153 u16 tx_itr_param, rx_itr_param; 2154 bool need_reset = false; 2155 2156 /* don't accept tx specific changes if we've got mixed RxTx vectors */ 2157 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count 2158 && ec->tx_coalesce_usecs) 2159 return -EINVAL; 2160 2161 if (ec->tx_max_coalesced_frames_irq) 2162 adapter->tx_work_limit = ec->tx_max_coalesced_frames_irq; 2163 2164 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) || 2165 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2))) 2166 return -EINVAL; 2167 2168 /* check the old value and enable RSC if necessary */ 2169 need_reset = ixgbe_update_rsc(adapter, ec); 2170 2171 if (ec->rx_coalesce_usecs > 1) 2172 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; 2173 else 2174 adapter->rx_itr_setting = ec->rx_coalesce_usecs; 2175 2176 if (adapter->rx_itr_setting == 1) 2177 rx_itr_param = IXGBE_20K_ITR; 2178 else 2179 rx_itr_param = adapter->rx_itr_setting; 2180 2181 if (ec->tx_coalesce_usecs > 1) 2182 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; 2183 else 2184 adapter->tx_itr_setting = ec->tx_coalesce_usecs; 2185 2186 if (adapter->tx_itr_setting == 1) 2187 tx_itr_param = IXGBE_10K_ITR; 2188 else 2189 tx_itr_param = adapter->tx_itr_setting; 2190 2191 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 2192 num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; 2193 else 2194 num_vectors = 1; 2195 2196 for (i = 0; i < num_vectors; i++) { 2197 q_vector = adapter->q_vector[i]; 2198 q_vector->tx.work_limit = adapter->tx_work_limit; 2199 if (q_vector->tx.count && !q_vector->rx.count) 2200 /* tx only */ 2201 q_vector->itr = tx_itr_param; 2202 else 2203 /* rx only or mixed */ 2204 q_vector->itr = rx_itr_param; 2205 ixgbe_write_eitr(q_vector); 2206 } 2207 2208 /* 2209 * do reset here at the end to make sure EITR==0 case is handled 2210 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings 2211 * also locks in RSC enable/disable which requires reset 2212 */ 2213 if (need_reset) 2214 ixgbe_do_reset(netdev); 2215 2216 return 0; 2217 } 2218 2219 static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2220 struct ethtool_rxnfc *cmd) 2221 { 2222 union ixgbe_atr_input *mask = &adapter->fdir_mask; 2223 struct ethtool_rx_flow_spec *fsp = 2224 (struct ethtool_rx_flow_spec *)&cmd->fs; 2225 struct hlist_node *node, *node2; 2226 struct ixgbe_fdir_filter *rule = NULL; 2227 2228 /* report total rule count */ 2229 cmd->data = (1024 << adapter->fdir_pballoc) - 2; 2230 2231 hlist_for_each_entry_safe(rule, node, node2, 2232 &adapter->fdir_filter_list, fdir_node) { 2233 if (fsp->location <= rule->sw_idx) 2234 break; 2235 } 2236 2237 if (!rule || fsp->location != rule->sw_idx) 2238 return -EINVAL; 2239 2240 /* fill out the flow spec entry */ 2241 2242 /* set flow type field */ 2243 switch (rule->filter.formatted.flow_type) { 2244 case IXGBE_ATR_FLOW_TYPE_TCPV4: 2245 fsp->flow_type = TCP_V4_FLOW; 2246 break; 2247 case IXGBE_ATR_FLOW_TYPE_UDPV4: 2248 fsp->flow_type = UDP_V4_FLOW; 2249 break; 2250 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 2251 fsp->flow_type = SCTP_V4_FLOW; 2252 break; 2253 case IXGBE_ATR_FLOW_TYPE_IPV4: 2254 fsp->flow_type = IP_USER_FLOW; 2255 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 2256 fsp->h_u.usr_ip4_spec.proto = 0; 2257 fsp->m_u.usr_ip4_spec.proto = 0; 2258 break; 2259 default: 2260 return -EINVAL; 2261 } 2262 2263 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port; 2264 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port; 2265 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port; 2266 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port; 2267 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0]; 2268 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0]; 2269 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0]; 2270 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0]; 2271 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id; 2272 fsp->m_ext.vlan_tci = mask->formatted.vlan_id; 2273 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes; 2274 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes; 2275 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool); 2276 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool); 2277 fsp->flow_type |= FLOW_EXT; 2278 2279 /* record action */ 2280 if (rule->action == IXGBE_FDIR_DROP_QUEUE) 2281 fsp->ring_cookie = RX_CLS_FLOW_DISC; 2282 else 2283 fsp->ring_cookie = rule->action; 2284 2285 return 0; 2286 } 2287 2288 static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter, 2289 struct ethtool_rxnfc *cmd, 2290 u32 *rule_locs) 2291 { 2292 struct hlist_node *node, *node2; 2293 struct ixgbe_fdir_filter *rule; 2294 int cnt = 0; 2295 2296 /* report total rule count */ 2297 cmd->data = (1024 << adapter->fdir_pballoc) - 2; 2298 2299 hlist_for_each_entry_safe(rule, node, node2, 2300 &adapter->fdir_filter_list, fdir_node) { 2301 if (cnt == cmd->rule_cnt) 2302 return -EMSGSIZE; 2303 rule_locs[cnt] = rule->sw_idx; 2304 cnt++; 2305 } 2306 2307 cmd->rule_cnt = cnt; 2308 2309 return 0; 2310 } 2311 2312 static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2313 u32 *rule_locs) 2314 { 2315 struct ixgbe_adapter *adapter = netdev_priv(dev); 2316 int ret = -EOPNOTSUPP; 2317 2318 switch (cmd->cmd) { 2319 case ETHTOOL_GRXRINGS: 2320 cmd->data = adapter->num_rx_queues; 2321 ret = 0; 2322 break; 2323 case ETHTOOL_GRXCLSRLCNT: 2324 cmd->rule_cnt = adapter->fdir_filter_count; 2325 ret = 0; 2326 break; 2327 case ETHTOOL_GRXCLSRULE: 2328 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd); 2329 break; 2330 case ETHTOOL_GRXCLSRLALL: 2331 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs); 2332 break; 2333 default: 2334 break; 2335 } 2336 2337 return ret; 2338 } 2339 2340 static int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2341 struct ixgbe_fdir_filter *input, 2342 u16 sw_idx) 2343 { 2344 struct ixgbe_hw *hw = &adapter->hw; 2345 struct hlist_node *node, *node2, *parent; 2346 struct ixgbe_fdir_filter *rule; 2347 int err = -EINVAL; 2348 2349 parent = NULL; 2350 rule = NULL; 2351 2352 hlist_for_each_entry_safe(rule, node, node2, 2353 &adapter->fdir_filter_list, fdir_node) { 2354 /* hash found, or no matching entry */ 2355 if (rule->sw_idx >= sw_idx) 2356 break; 2357 parent = node; 2358 } 2359 2360 /* if there is an old rule occupying our place remove it */ 2361 if (rule && (rule->sw_idx == sw_idx)) { 2362 if (!input || (rule->filter.formatted.bkt_hash != 2363 input->filter.formatted.bkt_hash)) { 2364 err = ixgbe_fdir_erase_perfect_filter_82599(hw, 2365 &rule->filter, 2366 sw_idx); 2367 } 2368 2369 hlist_del(&rule->fdir_node); 2370 kfree(rule); 2371 adapter->fdir_filter_count--; 2372 } 2373 2374 /* 2375 * If no input this was a delete, err should be 0 if a rule was 2376 * successfully found and removed from the list else -EINVAL 2377 */ 2378 if (!input) 2379 return err; 2380 2381 /* initialize node and set software index */ 2382 INIT_HLIST_NODE(&input->fdir_node); 2383 2384 /* add filter to the list */ 2385 if (parent) 2386 hlist_add_after(parent, &input->fdir_node); 2387 else 2388 hlist_add_head(&input->fdir_node, 2389 &adapter->fdir_filter_list); 2390 2391 /* update counts */ 2392 adapter->fdir_filter_count++; 2393 2394 return 0; 2395 } 2396 2397 static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp, 2398 u8 *flow_type) 2399 { 2400 switch (fsp->flow_type & ~FLOW_EXT) { 2401 case TCP_V4_FLOW: 2402 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 2403 break; 2404 case UDP_V4_FLOW: 2405 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 2406 break; 2407 case SCTP_V4_FLOW: 2408 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 2409 break; 2410 case IP_USER_FLOW: 2411 switch (fsp->h_u.usr_ip4_spec.proto) { 2412 case IPPROTO_TCP: 2413 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 2414 break; 2415 case IPPROTO_UDP: 2416 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 2417 break; 2418 case IPPROTO_SCTP: 2419 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 2420 break; 2421 case 0: 2422 if (!fsp->m_u.usr_ip4_spec.proto) { 2423 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4; 2424 break; 2425 } 2426 default: 2427 return 0; 2428 } 2429 break; 2430 default: 2431 return 0; 2432 } 2433 2434 return 1; 2435 } 2436 2437 static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2438 struct ethtool_rxnfc *cmd) 2439 { 2440 struct ethtool_rx_flow_spec *fsp = 2441 (struct ethtool_rx_flow_spec *)&cmd->fs; 2442 struct ixgbe_hw *hw = &adapter->hw; 2443 struct ixgbe_fdir_filter *input; 2444 union ixgbe_atr_input mask; 2445 int err; 2446 2447 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 2448 return -EOPNOTSUPP; 2449 2450 /* 2451 * Don't allow programming if the action is a queue greater than 2452 * the number of online Rx queues. 2453 */ 2454 if ((fsp->ring_cookie != RX_CLS_FLOW_DISC) && 2455 (fsp->ring_cookie >= adapter->num_rx_queues)) 2456 return -EINVAL; 2457 2458 /* Don't allow indexes to exist outside of available space */ 2459 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) { 2460 e_err(drv, "Location out of range\n"); 2461 return -EINVAL; 2462 } 2463 2464 input = kzalloc(sizeof(*input), GFP_ATOMIC); 2465 if (!input) 2466 return -ENOMEM; 2467 2468 memset(&mask, 0, sizeof(union ixgbe_atr_input)); 2469 2470 /* set SW index */ 2471 input->sw_idx = fsp->location; 2472 2473 /* record flow type */ 2474 if (!ixgbe_flowspec_to_flow_type(fsp, 2475 &input->filter.formatted.flow_type)) { 2476 e_err(drv, "Unrecognized flow type\n"); 2477 goto err_out; 2478 } 2479 2480 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 2481 IXGBE_ATR_L4TYPE_MASK; 2482 2483 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 2484 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 2485 2486 /* Copy input into formatted structures */ 2487 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src; 2488 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src; 2489 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst; 2490 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst; 2491 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc; 2492 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc; 2493 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst; 2494 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst; 2495 2496 if (fsp->flow_type & FLOW_EXT) { 2497 input->filter.formatted.vm_pool = 2498 (unsigned char)ntohl(fsp->h_ext.data[1]); 2499 mask.formatted.vm_pool = 2500 (unsigned char)ntohl(fsp->m_ext.data[1]); 2501 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci; 2502 mask.formatted.vlan_id = fsp->m_ext.vlan_tci; 2503 input->filter.formatted.flex_bytes = 2504 fsp->h_ext.vlan_etype; 2505 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype; 2506 } 2507 2508 /* determine if we need to drop or route the packet */ 2509 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) 2510 input->action = IXGBE_FDIR_DROP_QUEUE; 2511 else 2512 input->action = fsp->ring_cookie; 2513 2514 spin_lock(&adapter->fdir_perfect_lock); 2515 2516 if (hlist_empty(&adapter->fdir_filter_list)) { 2517 /* save mask and program input mask into HW */ 2518 memcpy(&adapter->fdir_mask, &mask, sizeof(mask)); 2519 err = ixgbe_fdir_set_input_mask_82599(hw, &mask); 2520 if (err) { 2521 e_err(drv, "Error writing mask\n"); 2522 goto err_out_w_lock; 2523 } 2524 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) { 2525 e_err(drv, "Only one mask supported per port\n"); 2526 goto err_out_w_lock; 2527 } 2528 2529 /* apply mask and compute/store hash */ 2530 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask); 2531 2532 /* program filters to filter memory */ 2533 err = ixgbe_fdir_write_perfect_filter_82599(hw, 2534 &input->filter, input->sw_idx, 2535 (input->action == IXGBE_FDIR_DROP_QUEUE) ? 2536 IXGBE_FDIR_DROP_QUEUE : 2537 adapter->rx_ring[input->action]->reg_idx); 2538 if (err) 2539 goto err_out_w_lock; 2540 2541 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 2542 2543 spin_unlock(&adapter->fdir_perfect_lock); 2544 2545 return err; 2546 err_out_w_lock: 2547 spin_unlock(&adapter->fdir_perfect_lock); 2548 err_out: 2549 kfree(input); 2550 return -EINVAL; 2551 } 2552 2553 static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2554 struct ethtool_rxnfc *cmd) 2555 { 2556 struct ethtool_rx_flow_spec *fsp = 2557 (struct ethtool_rx_flow_spec *)&cmd->fs; 2558 int err; 2559 2560 spin_lock(&adapter->fdir_perfect_lock); 2561 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location); 2562 spin_unlock(&adapter->fdir_perfect_lock); 2563 2564 return err; 2565 } 2566 2567 static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2568 { 2569 struct ixgbe_adapter *adapter = netdev_priv(dev); 2570 int ret = -EOPNOTSUPP; 2571 2572 switch (cmd->cmd) { 2573 case ETHTOOL_SRXCLSRLINS: 2574 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd); 2575 break; 2576 case ETHTOOL_SRXCLSRLDEL: 2577 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd); 2578 break; 2579 default: 2580 break; 2581 } 2582 2583 return ret; 2584 } 2585 2586 static const struct ethtool_ops ixgbe_ethtool_ops = { 2587 .get_settings = ixgbe_get_settings, 2588 .set_settings = ixgbe_set_settings, 2589 .get_drvinfo = ixgbe_get_drvinfo, 2590 .get_regs_len = ixgbe_get_regs_len, 2591 .get_regs = ixgbe_get_regs, 2592 .get_wol = ixgbe_get_wol, 2593 .set_wol = ixgbe_set_wol, 2594 .nway_reset = ixgbe_nway_reset, 2595 .get_link = ethtool_op_get_link, 2596 .get_eeprom_len = ixgbe_get_eeprom_len, 2597 .get_eeprom = ixgbe_get_eeprom, 2598 .set_eeprom = ixgbe_set_eeprom, 2599 .get_ringparam = ixgbe_get_ringparam, 2600 .set_ringparam = ixgbe_set_ringparam, 2601 .get_pauseparam = ixgbe_get_pauseparam, 2602 .set_pauseparam = ixgbe_set_pauseparam, 2603 .get_msglevel = ixgbe_get_msglevel, 2604 .set_msglevel = ixgbe_set_msglevel, 2605 .self_test = ixgbe_diag_test, 2606 .get_strings = ixgbe_get_strings, 2607 .set_phys_id = ixgbe_set_phys_id, 2608 .get_sset_count = ixgbe_get_sset_count, 2609 .get_ethtool_stats = ixgbe_get_ethtool_stats, 2610 .get_coalesce = ixgbe_get_coalesce, 2611 .set_coalesce = ixgbe_set_coalesce, 2612 .get_rxnfc = ixgbe_get_rxnfc, 2613 .set_rxnfc = ixgbe_set_rxnfc, 2614 }; 2615 2616 void ixgbe_set_ethtool_ops(struct net_device *netdev) 2617 { 2618 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops); 2619 } 2620