1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 /* ethtool support for ixgbe */ 29 30 #include <linux/interrupt.h> 31 #include <linux/types.h> 32 #include <linux/module.h> 33 #include <linux/slab.h> 34 #include <linux/pci.h> 35 #include <linux/netdevice.h> 36 #include <linux/ethtool.h> 37 #include <linux/vmalloc.h> 38 #include <linux/highmem.h> 39 #include <linux/uaccess.h> 40 41 #include "ixgbe.h" 42 #include "ixgbe_phy.h" 43 44 45 #define IXGBE_ALL_RAR_ENTRIES 16 46 47 enum {NETDEV_STATS, IXGBE_STATS}; 48 49 struct ixgbe_stats { 50 char stat_string[ETH_GSTRING_LEN]; 51 int type; 52 int sizeof_stat; 53 int stat_offset; 54 }; 55 56 #define IXGBE_STAT(m) IXGBE_STATS, \ 57 sizeof(((struct ixgbe_adapter *)0)->m), \ 58 offsetof(struct ixgbe_adapter, m) 59 #define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \ 60 sizeof(((struct rtnl_link_stats64 *)0)->m), \ 61 offsetof(struct rtnl_link_stats64, m) 62 63 static const struct ixgbe_stats ixgbe_gstrings_stats[] = { 64 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)}, 65 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)}, 66 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)}, 67 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)}, 68 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)}, 69 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)}, 70 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)}, 71 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)}, 72 {"lsc_int", IXGBE_STAT(lsc_int)}, 73 {"tx_busy", IXGBE_STAT(tx_busy)}, 74 {"non_eop_descs", IXGBE_STAT(non_eop_descs)}, 75 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)}, 76 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)}, 77 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)}, 78 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)}, 79 {"multicast", IXGBE_NETDEV_STAT(multicast)}, 80 {"broadcast", IXGBE_STAT(stats.bprc)}, 81 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) }, 82 {"collisions", IXGBE_NETDEV_STAT(collisions)}, 83 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)}, 84 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)}, 85 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)}, 86 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)}, 87 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)}, 88 {"fdir_match", IXGBE_STAT(stats.fdirmatch)}, 89 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)}, 90 {"fdir_overflow", IXGBE_STAT(fdir_overflow)}, 91 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)}, 92 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)}, 93 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)}, 94 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)}, 95 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)}, 96 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)}, 97 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)}, 98 {"tx_restart_queue", IXGBE_STAT(restart_queue)}, 99 {"rx_long_length_errors", IXGBE_STAT(stats.roc)}, 100 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)}, 101 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)}, 102 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)}, 103 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)}, 104 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)}, 105 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)}, 106 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)}, 107 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)}, 108 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)}, 109 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)}, 110 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)}, 111 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)}, 112 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)}, 113 #ifdef IXGBE_FCOE 114 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)}, 115 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)}, 116 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)}, 117 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)}, 118 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)}, 119 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)}, 120 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)}, 121 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)}, 122 #endif /* IXGBE_FCOE */ 123 }; 124 125 /* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so 126 * we set the num_rx_queues to evaluate to num_tx_queues. This is 127 * used because we do not have a good way to get the max number of 128 * rx queues with CONFIG_RPS disabled. 129 */ 130 #define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues 131 132 #define IXGBE_QUEUE_STATS_LEN ( \ 133 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \ 134 (sizeof(struct ixgbe_queue_stats) / sizeof(u64))) 135 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats) 136 #define IXGBE_PB_STATS_LEN ( \ 137 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \ 138 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \ 139 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \ 140 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \ 141 / sizeof(u64)) 142 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \ 143 IXGBE_PB_STATS_LEN + \ 144 IXGBE_QUEUE_STATS_LEN) 145 146 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = { 147 "Register test (offline)", "Eeprom test (offline)", 148 "Interrupt test (offline)", "Loopback test (offline)", 149 "Link test (on/offline)" 150 }; 151 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN 152 153 static int ixgbe_get_settings(struct net_device *netdev, 154 struct ethtool_cmd *ecmd) 155 { 156 struct ixgbe_adapter *adapter = netdev_priv(netdev); 157 struct ixgbe_hw *hw = &adapter->hw; 158 ixgbe_link_speed supported_link; 159 u32 link_speed = 0; 160 bool autoneg = false; 161 bool link_up; 162 163 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg); 164 165 /* set the supported link speeds */ 166 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) 167 ecmd->supported |= SUPPORTED_10000baseT_Full; 168 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL) 169 ecmd->supported |= SUPPORTED_1000baseT_Full; 170 if (supported_link & IXGBE_LINK_SPEED_100_FULL) 171 ecmd->supported |= SUPPORTED_100baseT_Full; 172 173 /* set the advertised speeds */ 174 if (hw->phy.autoneg_advertised) { 175 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 176 ecmd->advertising |= ADVERTISED_100baseT_Full; 177 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 178 ecmd->advertising |= ADVERTISED_10000baseT_Full; 179 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 180 ecmd->advertising |= ADVERTISED_1000baseT_Full; 181 } else { 182 /* default modes in case phy.autoneg_advertised isn't set */ 183 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) 184 ecmd->advertising |= ADVERTISED_10000baseT_Full; 185 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL) 186 ecmd->advertising |= ADVERTISED_1000baseT_Full; 187 if (supported_link & IXGBE_LINK_SPEED_100_FULL) 188 ecmd->advertising |= ADVERTISED_100baseT_Full; 189 } 190 191 if (autoneg) { 192 ecmd->supported |= SUPPORTED_Autoneg; 193 ecmd->advertising |= ADVERTISED_Autoneg; 194 ecmd->autoneg = AUTONEG_ENABLE; 195 } else 196 ecmd->autoneg = AUTONEG_DISABLE; 197 198 ecmd->transceiver = XCVR_EXTERNAL; 199 200 /* Determine the remaining settings based on the PHY type. */ 201 switch (adapter->hw.phy.type) { 202 case ixgbe_phy_tn: 203 case ixgbe_phy_aq: 204 case ixgbe_phy_cu_unknown: 205 ecmd->supported |= SUPPORTED_TP; 206 ecmd->advertising |= ADVERTISED_TP; 207 ecmd->port = PORT_TP; 208 break; 209 case ixgbe_phy_qt: 210 ecmd->supported |= SUPPORTED_FIBRE; 211 ecmd->advertising |= ADVERTISED_FIBRE; 212 ecmd->port = PORT_FIBRE; 213 break; 214 case ixgbe_phy_nl: 215 case ixgbe_phy_sfp_passive_tyco: 216 case ixgbe_phy_sfp_passive_unknown: 217 case ixgbe_phy_sfp_ftl: 218 case ixgbe_phy_sfp_avago: 219 case ixgbe_phy_sfp_intel: 220 case ixgbe_phy_sfp_unknown: 221 /* SFP+ devices, further checking needed */ 222 switch (adapter->hw.phy.sfp_type) { 223 case ixgbe_sfp_type_da_cu: 224 case ixgbe_sfp_type_da_cu_core0: 225 case ixgbe_sfp_type_da_cu_core1: 226 ecmd->supported |= SUPPORTED_FIBRE; 227 ecmd->advertising |= ADVERTISED_FIBRE; 228 ecmd->port = PORT_DA; 229 break; 230 case ixgbe_sfp_type_sr: 231 case ixgbe_sfp_type_lr: 232 case ixgbe_sfp_type_srlr_core0: 233 case ixgbe_sfp_type_srlr_core1: 234 case ixgbe_sfp_type_1g_sx_core0: 235 case ixgbe_sfp_type_1g_sx_core1: 236 case ixgbe_sfp_type_1g_lx_core0: 237 case ixgbe_sfp_type_1g_lx_core1: 238 ecmd->supported |= SUPPORTED_FIBRE; 239 ecmd->advertising |= ADVERTISED_FIBRE; 240 ecmd->port = PORT_FIBRE; 241 break; 242 case ixgbe_sfp_type_not_present: 243 ecmd->supported |= SUPPORTED_FIBRE; 244 ecmd->advertising |= ADVERTISED_FIBRE; 245 ecmd->port = PORT_NONE; 246 break; 247 case ixgbe_sfp_type_1g_cu_core0: 248 case ixgbe_sfp_type_1g_cu_core1: 249 ecmd->supported |= SUPPORTED_TP; 250 ecmd->advertising |= ADVERTISED_TP; 251 ecmd->port = PORT_TP; 252 break; 253 case ixgbe_sfp_type_unknown: 254 default: 255 ecmd->supported |= SUPPORTED_FIBRE; 256 ecmd->advertising |= ADVERTISED_FIBRE; 257 ecmd->port = PORT_OTHER; 258 break; 259 } 260 break; 261 case ixgbe_phy_xaui: 262 ecmd->supported |= SUPPORTED_FIBRE; 263 ecmd->advertising |= ADVERTISED_FIBRE; 264 ecmd->port = PORT_NONE; 265 break; 266 case ixgbe_phy_unknown: 267 case ixgbe_phy_generic: 268 case ixgbe_phy_sfp_unsupported: 269 default: 270 ecmd->supported |= SUPPORTED_FIBRE; 271 ecmd->advertising |= ADVERTISED_FIBRE; 272 ecmd->port = PORT_OTHER; 273 break; 274 } 275 276 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 277 if (link_up) { 278 switch (link_speed) { 279 case IXGBE_LINK_SPEED_10GB_FULL: 280 ethtool_cmd_speed_set(ecmd, SPEED_10000); 281 break; 282 case IXGBE_LINK_SPEED_1GB_FULL: 283 ethtool_cmd_speed_set(ecmd, SPEED_1000); 284 break; 285 case IXGBE_LINK_SPEED_100_FULL: 286 ethtool_cmd_speed_set(ecmd, SPEED_100); 287 break; 288 default: 289 break; 290 } 291 ecmd->duplex = DUPLEX_FULL; 292 } else { 293 ethtool_cmd_speed_set(ecmd, -1); 294 ecmd->duplex = -1; 295 } 296 297 return 0; 298 } 299 300 static int ixgbe_set_settings(struct net_device *netdev, 301 struct ethtool_cmd *ecmd) 302 { 303 struct ixgbe_adapter *adapter = netdev_priv(netdev); 304 struct ixgbe_hw *hw = &adapter->hw; 305 u32 advertised, old; 306 s32 err = 0; 307 308 if ((hw->phy.media_type == ixgbe_media_type_copper) || 309 (hw->phy.multispeed_fiber)) { 310 /* 311 * this function does not support duplex forcing, but can 312 * limit the advertising of the adapter to the specified speed 313 */ 314 if (ecmd->advertising & ~ecmd->supported) 315 return -EINVAL; 316 317 old = hw->phy.autoneg_advertised; 318 advertised = 0; 319 if (ecmd->advertising & ADVERTISED_10000baseT_Full) 320 advertised |= IXGBE_LINK_SPEED_10GB_FULL; 321 322 if (ecmd->advertising & ADVERTISED_1000baseT_Full) 323 advertised |= IXGBE_LINK_SPEED_1GB_FULL; 324 325 if (ecmd->advertising & ADVERTISED_100baseT_Full) 326 advertised |= IXGBE_LINK_SPEED_100_FULL; 327 328 if (old == advertised) 329 return err; 330 /* this sets the link speed and restarts auto-neg */ 331 hw->mac.autotry_restart = true; 332 err = hw->mac.ops.setup_link(hw, advertised, true); 333 if (err) { 334 e_info(probe, "setup link failed with code %d\n", err); 335 hw->mac.ops.setup_link(hw, old, true); 336 } 337 } else { 338 /* in this case we currently only support 10Gb/FULL */ 339 u32 speed = ethtool_cmd_speed(ecmd); 340 if ((ecmd->autoneg == AUTONEG_ENABLE) || 341 (ecmd->advertising != ADVERTISED_10000baseT_Full) || 342 (speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL)) 343 return -EINVAL; 344 } 345 346 return err; 347 } 348 349 static void ixgbe_get_pauseparam(struct net_device *netdev, 350 struct ethtool_pauseparam *pause) 351 { 352 struct ixgbe_adapter *adapter = netdev_priv(netdev); 353 struct ixgbe_hw *hw = &adapter->hw; 354 355 if (ixgbe_device_supports_autoneg_fc(hw) && 356 !hw->fc.disable_fc_autoneg) 357 pause->autoneg = 1; 358 else 359 pause->autoneg = 0; 360 361 if (hw->fc.current_mode == ixgbe_fc_rx_pause) { 362 pause->rx_pause = 1; 363 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) { 364 pause->tx_pause = 1; 365 } else if (hw->fc.current_mode == ixgbe_fc_full) { 366 pause->rx_pause = 1; 367 pause->tx_pause = 1; 368 } 369 } 370 371 static int ixgbe_set_pauseparam(struct net_device *netdev, 372 struct ethtool_pauseparam *pause) 373 { 374 struct ixgbe_adapter *adapter = netdev_priv(netdev); 375 struct ixgbe_hw *hw = &adapter->hw; 376 struct ixgbe_fc_info fc = hw->fc; 377 378 /* 82598 does no support link flow control with DCB enabled */ 379 if ((hw->mac.type == ixgbe_mac_82598EB) && 380 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)) 381 return -EINVAL; 382 383 /* some devices do not support autoneg of link flow control */ 384 if ((pause->autoneg == AUTONEG_ENABLE) && 385 !ixgbe_device_supports_autoneg_fc(hw)) 386 return -EINVAL; 387 388 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE); 389 390 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg) 391 fc.requested_mode = ixgbe_fc_full; 392 else if (pause->rx_pause && !pause->tx_pause) 393 fc.requested_mode = ixgbe_fc_rx_pause; 394 else if (!pause->rx_pause && pause->tx_pause) 395 fc.requested_mode = ixgbe_fc_tx_pause; 396 else 397 fc.requested_mode = ixgbe_fc_none; 398 399 /* if the thing changed then we'll update and use new autoneg */ 400 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) { 401 hw->fc = fc; 402 if (netif_running(netdev)) 403 ixgbe_reinit_locked(adapter); 404 else 405 ixgbe_reset(adapter); 406 } 407 408 return 0; 409 } 410 411 static u32 ixgbe_get_msglevel(struct net_device *netdev) 412 { 413 struct ixgbe_adapter *adapter = netdev_priv(netdev); 414 return adapter->msg_enable; 415 } 416 417 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data) 418 { 419 struct ixgbe_adapter *adapter = netdev_priv(netdev); 420 adapter->msg_enable = data; 421 } 422 423 static int ixgbe_get_regs_len(struct net_device *netdev) 424 { 425 #define IXGBE_REGS_LEN 1129 426 return IXGBE_REGS_LEN * sizeof(u32); 427 } 428 429 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_ 430 431 static void ixgbe_get_regs(struct net_device *netdev, 432 struct ethtool_regs *regs, void *p) 433 { 434 struct ixgbe_adapter *adapter = netdev_priv(netdev); 435 struct ixgbe_hw *hw = &adapter->hw; 436 u32 *regs_buff = p; 437 u8 i; 438 439 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32)); 440 441 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 442 hw->device_id; 443 444 /* General Registers */ 445 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL); 446 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS); 447 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 448 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP); 449 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP); 450 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 451 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER); 452 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER); 453 454 /* NVM Register */ 455 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC); 456 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD); 457 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA); 458 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL); 459 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA); 460 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL); 461 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA); 462 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT); 463 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP); 464 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC); 465 466 /* Interrupt */ 467 /* don't read EICR because it can clear interrupt causes, instead 468 * read EICS which is a shadow but doesn't clear EICR */ 469 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS); 470 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS); 471 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS); 472 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC); 473 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC); 474 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM); 475 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0)); 476 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0)); 477 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT); 478 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA); 479 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0)); 480 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE); 481 482 /* Flow Control */ 483 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP); 484 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0)); 485 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1)); 486 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2)); 487 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3)); 488 for (i = 0; i < 8; i++) { 489 switch (hw->mac.type) { 490 case ixgbe_mac_82598EB: 491 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i)); 492 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i)); 493 break; 494 case ixgbe_mac_82599EB: 495 case ixgbe_mac_X540: 496 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i)); 497 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 498 break; 499 default: 500 break; 501 } 502 } 503 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV); 504 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS); 505 506 /* Receive DMA */ 507 for (i = 0; i < 64; i++) 508 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 509 for (i = 0; i < 64; i++) 510 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 511 for (i = 0; i < 64; i++) 512 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 513 for (i = 0; i < 64; i++) 514 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 515 for (i = 0; i < 64; i++) 516 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 517 for (i = 0; i < 64; i++) 518 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 519 for (i = 0; i < 16; i++) 520 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 521 for (i = 0; i < 16; i++) 522 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 523 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 524 for (i = 0; i < 8; i++) 525 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)); 526 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 527 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN); 528 529 /* Receive */ 530 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 531 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL); 532 for (i = 0; i < 16; i++) 533 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 534 for (i = 0; i < 16; i++) 535 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 536 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0)); 537 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL); 538 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 539 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL); 540 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC); 541 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 542 for (i = 0; i < 8; i++) 543 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i)); 544 for (i = 0; i < 8; i++) 545 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i)); 546 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP); 547 548 /* Transmit */ 549 for (i = 0; i < 32; i++) 550 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 551 for (i = 0; i < 32; i++) 552 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 553 for (i = 0; i < 32; i++) 554 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 555 for (i = 0; i < 32; i++) 556 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 557 for (i = 0; i < 32; i++) 558 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 559 for (i = 0; i < 32; i++) 560 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 561 for (i = 0; i < 32; i++) 562 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i)); 563 for (i = 0; i < 32; i++) 564 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i)); 565 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL); 566 for (i = 0; i < 16; i++) 567 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); 568 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG); 569 for (i = 0; i < 8; i++) 570 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i)); 571 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP); 572 573 /* Wake Up */ 574 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC); 575 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC); 576 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS); 577 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV); 578 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT); 579 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT); 580 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL); 581 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM); 582 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0)); 583 584 /* DCB */ 585 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); 586 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS); 587 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); 588 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR); 589 for (i = 0; i < 8; i++) 590 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i)); 591 for (i = 0; i < 8; i++) 592 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i)); 593 for (i = 0; i < 8; i++) 594 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i)); 595 for (i = 0; i < 8; i++) 596 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i)); 597 for (i = 0; i < 8; i++) 598 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); 599 for (i = 0; i < 8; i++) 600 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); 601 602 /* Statistics */ 603 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs); 604 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc); 605 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc); 606 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc); 607 for (i = 0; i < 8; i++) 608 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]); 609 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc); 610 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc); 611 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec); 612 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc); 613 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc); 614 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc); 615 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc); 616 for (i = 0; i < 8; i++) 617 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]); 618 for (i = 0; i < 8; i++) 619 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]); 620 for (i = 0; i < 8; i++) 621 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]); 622 for (i = 0; i < 8; i++) 623 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]); 624 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64); 625 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127); 626 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255); 627 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511); 628 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023); 629 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522); 630 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc); 631 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc); 632 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc); 633 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc); 634 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc); 635 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc); 636 for (i = 0; i < 8; i++) 637 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]); 638 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc); 639 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc); 640 regs_buff[956] = IXGBE_GET_STAT(adapter, roc); 641 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc); 642 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc); 643 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc); 644 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc); 645 regs_buff[961] = IXGBE_GET_STAT(adapter, tor); 646 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr); 647 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt); 648 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64); 649 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127); 650 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255); 651 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511); 652 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023); 653 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522); 654 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc); 655 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc); 656 regs_buff[973] = IXGBE_GET_STAT(adapter, xec); 657 for (i = 0; i < 16; i++) 658 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]); 659 for (i = 0; i < 16; i++) 660 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]); 661 for (i = 0; i < 16; i++) 662 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]); 663 for (i = 0; i < 16; i++) 664 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]); 665 666 /* MAC */ 667 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG); 668 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 669 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 670 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0); 671 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1); 672 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 673 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 674 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP); 675 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP); 676 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0); 677 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1); 678 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP); 679 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA); 680 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE); 681 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD); 682 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS); 683 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA); 684 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD); 685 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD); 686 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD); 687 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG); 688 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1); 689 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2); 690 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS); 691 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC); 692 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS); 693 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC); 694 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS); 695 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 696 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3); 697 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1); 698 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2); 699 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 700 701 /* Diagnostic */ 702 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL); 703 for (i = 0; i < 8; i++) 704 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i)); 705 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN); 706 for (i = 0; i < 4; i++) 707 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i)); 708 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE); 709 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL); 710 for (i = 0; i < 8; i++) 711 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i)); 712 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN); 713 for (i = 0; i < 4; i++) 714 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i)); 715 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE); 716 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL); 717 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0); 718 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1); 719 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2); 720 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3); 721 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL); 722 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0); 723 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1); 724 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2); 725 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3); 726 for (i = 0; i < 8; i++) 727 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i)); 728 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL); 729 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1); 730 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2); 731 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1); 732 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2); 733 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS); 734 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL); 735 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC); 736 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC); 737 738 /* 82599 X540 specific registers */ 739 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN); 740 } 741 742 static int ixgbe_get_eeprom_len(struct net_device *netdev) 743 { 744 struct ixgbe_adapter *adapter = netdev_priv(netdev); 745 return adapter->hw.eeprom.word_size * 2; 746 } 747 748 static int ixgbe_get_eeprom(struct net_device *netdev, 749 struct ethtool_eeprom *eeprom, u8 *bytes) 750 { 751 struct ixgbe_adapter *adapter = netdev_priv(netdev); 752 struct ixgbe_hw *hw = &adapter->hw; 753 u16 *eeprom_buff; 754 int first_word, last_word, eeprom_len; 755 int ret_val = 0; 756 u16 i; 757 758 if (eeprom->len == 0) 759 return -EINVAL; 760 761 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 762 763 first_word = eeprom->offset >> 1; 764 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 765 eeprom_len = last_word - first_word + 1; 766 767 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL); 768 if (!eeprom_buff) 769 return -ENOMEM; 770 771 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len, 772 eeprom_buff); 773 774 /* Device's eeprom is always little-endian, word addressable */ 775 for (i = 0; i < eeprom_len; i++) 776 le16_to_cpus(&eeprom_buff[i]); 777 778 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len); 779 kfree(eeprom_buff); 780 781 return ret_val; 782 } 783 784 static int ixgbe_set_eeprom(struct net_device *netdev, 785 struct ethtool_eeprom *eeprom, u8 *bytes) 786 { 787 struct ixgbe_adapter *adapter = netdev_priv(netdev); 788 struct ixgbe_hw *hw = &adapter->hw; 789 u16 *eeprom_buff; 790 void *ptr; 791 int max_len, first_word, last_word, ret_val = 0; 792 u16 i; 793 794 if (eeprom->len == 0) 795 return -EINVAL; 796 797 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 798 return -EINVAL; 799 800 max_len = hw->eeprom.word_size * 2; 801 802 first_word = eeprom->offset >> 1; 803 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 804 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 805 if (!eeprom_buff) 806 return -ENOMEM; 807 808 ptr = eeprom_buff; 809 810 if (eeprom->offset & 1) { 811 /* 812 * need read/modify/write of first changed EEPROM word 813 * only the second byte of the word is being modified 814 */ 815 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]); 816 if (ret_val) 817 goto err; 818 819 ptr++; 820 } 821 if ((eeprom->offset + eeprom->len) & 1) { 822 /* 823 * need read/modify/write of last changed EEPROM word 824 * only the first byte of the word is being modified 825 */ 826 ret_val = hw->eeprom.ops.read(hw, last_word, 827 &eeprom_buff[last_word - first_word]); 828 if (ret_val) 829 goto err; 830 } 831 832 /* Device's eeprom is always little-endian, word addressable */ 833 for (i = 0; i < last_word - first_word + 1; i++) 834 le16_to_cpus(&eeprom_buff[i]); 835 836 memcpy(ptr, bytes, eeprom->len); 837 838 for (i = 0; i < last_word - first_word + 1; i++) 839 cpu_to_le16s(&eeprom_buff[i]); 840 841 ret_val = hw->eeprom.ops.write_buffer(hw, first_word, 842 last_word - first_word + 1, 843 eeprom_buff); 844 845 /* Update the checksum */ 846 if (ret_val == 0) 847 hw->eeprom.ops.update_checksum(hw); 848 849 err: 850 kfree(eeprom_buff); 851 return ret_val; 852 } 853 854 static void ixgbe_get_drvinfo(struct net_device *netdev, 855 struct ethtool_drvinfo *drvinfo) 856 { 857 struct ixgbe_adapter *adapter = netdev_priv(netdev); 858 u32 nvm_track_id; 859 860 strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver)); 861 strlcpy(drvinfo->version, ixgbe_driver_version, 862 sizeof(drvinfo->version)); 863 864 nvm_track_id = (adapter->eeprom_verh << 16) | 865 adapter->eeprom_verl; 866 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), "0x%08x", 867 nvm_track_id); 868 869 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 870 sizeof(drvinfo->bus_info)); 871 drvinfo->n_stats = IXGBE_STATS_LEN; 872 drvinfo->testinfo_len = IXGBE_TEST_LEN; 873 drvinfo->regdump_len = ixgbe_get_regs_len(netdev); 874 } 875 876 static void ixgbe_get_ringparam(struct net_device *netdev, 877 struct ethtool_ringparam *ring) 878 { 879 struct ixgbe_adapter *adapter = netdev_priv(netdev); 880 struct ixgbe_ring *tx_ring = adapter->tx_ring[0]; 881 struct ixgbe_ring *rx_ring = adapter->rx_ring[0]; 882 883 ring->rx_max_pending = IXGBE_MAX_RXD; 884 ring->tx_max_pending = IXGBE_MAX_TXD; 885 ring->rx_pending = rx_ring->count; 886 ring->tx_pending = tx_ring->count; 887 } 888 889 static int ixgbe_set_ringparam(struct net_device *netdev, 890 struct ethtool_ringparam *ring) 891 { 892 struct ixgbe_adapter *adapter = netdev_priv(netdev); 893 struct ixgbe_ring *temp_ring; 894 int i, err = 0; 895 u32 new_rx_count, new_tx_count; 896 897 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 898 return -EINVAL; 899 900 new_tx_count = clamp_t(u32, ring->tx_pending, 901 IXGBE_MIN_TXD, IXGBE_MAX_TXD); 902 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE); 903 904 new_rx_count = clamp_t(u32, ring->rx_pending, 905 IXGBE_MIN_RXD, IXGBE_MAX_RXD); 906 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE); 907 908 if ((new_tx_count == adapter->tx_ring_count) && 909 (new_rx_count == adapter->rx_ring_count)) { 910 /* nothing to do */ 911 return 0; 912 } 913 914 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 915 usleep_range(1000, 2000); 916 917 if (!netif_running(adapter->netdev)) { 918 for (i = 0; i < adapter->num_tx_queues; i++) 919 adapter->tx_ring[i]->count = new_tx_count; 920 for (i = 0; i < adapter->num_rx_queues; i++) 921 adapter->rx_ring[i]->count = new_rx_count; 922 adapter->tx_ring_count = new_tx_count; 923 adapter->rx_ring_count = new_rx_count; 924 goto clear_reset; 925 } 926 927 /* allocate temporary buffer to store rings in */ 928 i = max_t(int, adapter->num_tx_queues, adapter->num_rx_queues); 929 temp_ring = vmalloc(i * sizeof(struct ixgbe_ring)); 930 931 if (!temp_ring) { 932 err = -ENOMEM; 933 goto clear_reset; 934 } 935 936 ixgbe_down(adapter); 937 938 /* 939 * Setup new Tx resources and free the old Tx resources in that order. 940 * We can then assign the new resources to the rings via a memcpy. 941 * The advantage to this approach is that we are guaranteed to still 942 * have resources even in the case of an allocation failure. 943 */ 944 if (new_tx_count != adapter->tx_ring_count) { 945 for (i = 0; i < adapter->num_tx_queues; i++) { 946 memcpy(&temp_ring[i], adapter->tx_ring[i], 947 sizeof(struct ixgbe_ring)); 948 949 temp_ring[i].count = new_tx_count; 950 err = ixgbe_setup_tx_resources(&temp_ring[i]); 951 if (err) { 952 while (i) { 953 i--; 954 ixgbe_free_tx_resources(&temp_ring[i]); 955 } 956 goto err_setup; 957 } 958 } 959 960 for (i = 0; i < adapter->num_tx_queues; i++) { 961 ixgbe_free_tx_resources(adapter->tx_ring[i]); 962 963 memcpy(adapter->tx_ring[i], &temp_ring[i], 964 sizeof(struct ixgbe_ring)); 965 } 966 967 adapter->tx_ring_count = new_tx_count; 968 } 969 970 /* Repeat the process for the Rx rings if needed */ 971 if (new_rx_count != adapter->rx_ring_count) { 972 for (i = 0; i < adapter->num_rx_queues; i++) { 973 memcpy(&temp_ring[i], adapter->rx_ring[i], 974 sizeof(struct ixgbe_ring)); 975 976 temp_ring[i].count = new_rx_count; 977 err = ixgbe_setup_rx_resources(&temp_ring[i]); 978 if (err) { 979 while (i) { 980 i--; 981 ixgbe_free_rx_resources(&temp_ring[i]); 982 } 983 goto err_setup; 984 } 985 986 } 987 988 for (i = 0; i < adapter->num_rx_queues; i++) { 989 ixgbe_free_rx_resources(adapter->rx_ring[i]); 990 991 memcpy(adapter->rx_ring[i], &temp_ring[i], 992 sizeof(struct ixgbe_ring)); 993 } 994 995 adapter->rx_ring_count = new_rx_count; 996 } 997 998 err_setup: 999 ixgbe_up(adapter); 1000 vfree(temp_ring); 1001 clear_reset: 1002 clear_bit(__IXGBE_RESETTING, &adapter->state); 1003 return err; 1004 } 1005 1006 static int ixgbe_get_sset_count(struct net_device *netdev, int sset) 1007 { 1008 switch (sset) { 1009 case ETH_SS_TEST: 1010 return IXGBE_TEST_LEN; 1011 case ETH_SS_STATS: 1012 return IXGBE_STATS_LEN; 1013 default: 1014 return -EOPNOTSUPP; 1015 } 1016 } 1017 1018 static void ixgbe_get_ethtool_stats(struct net_device *netdev, 1019 struct ethtool_stats *stats, u64 *data) 1020 { 1021 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1022 struct rtnl_link_stats64 temp; 1023 const struct rtnl_link_stats64 *net_stats; 1024 unsigned int start; 1025 struct ixgbe_ring *ring; 1026 int i, j; 1027 char *p = NULL; 1028 1029 ixgbe_update_stats(adapter); 1030 net_stats = dev_get_stats(netdev, &temp); 1031 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 1032 switch (ixgbe_gstrings_stats[i].type) { 1033 case NETDEV_STATS: 1034 p = (char *) net_stats + 1035 ixgbe_gstrings_stats[i].stat_offset; 1036 break; 1037 case IXGBE_STATS: 1038 p = (char *) adapter + 1039 ixgbe_gstrings_stats[i].stat_offset; 1040 break; 1041 default: 1042 data[i] = 0; 1043 continue; 1044 } 1045 1046 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat == 1047 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 1048 } 1049 for (j = 0; j < netdev->num_tx_queues; j++) { 1050 ring = adapter->tx_ring[j]; 1051 if (!ring) { 1052 data[i] = 0; 1053 data[i+1] = 0; 1054 i += 2; 1055 #ifdef LL_EXTENDED_STATS 1056 data[i] = 0; 1057 data[i+1] = 0; 1058 data[i+2] = 0; 1059 i += 3; 1060 #endif 1061 continue; 1062 } 1063 1064 do { 1065 start = u64_stats_fetch_begin_bh(&ring->syncp); 1066 data[i] = ring->stats.packets; 1067 data[i+1] = ring->stats.bytes; 1068 } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); 1069 i += 2; 1070 #ifdef LL_EXTENDED_STATS 1071 data[i] = ring->stats.yields; 1072 data[i+1] = ring->stats.misses; 1073 data[i+2] = ring->stats.cleaned; 1074 i += 3; 1075 #endif 1076 } 1077 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) { 1078 ring = adapter->rx_ring[j]; 1079 if (!ring) { 1080 data[i] = 0; 1081 data[i+1] = 0; 1082 i += 2; 1083 #ifdef LL_EXTENDED_STATS 1084 data[i] = 0; 1085 data[i+1] = 0; 1086 data[i+2] = 0; 1087 i += 3; 1088 #endif 1089 continue; 1090 } 1091 1092 do { 1093 start = u64_stats_fetch_begin_bh(&ring->syncp); 1094 data[i] = ring->stats.packets; 1095 data[i+1] = ring->stats.bytes; 1096 } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); 1097 i += 2; 1098 #ifdef LL_EXTENDED_STATS 1099 data[i] = ring->stats.yields; 1100 data[i+1] = ring->stats.misses; 1101 data[i+2] = ring->stats.cleaned; 1102 i += 3; 1103 #endif 1104 } 1105 1106 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) { 1107 data[i++] = adapter->stats.pxontxc[j]; 1108 data[i++] = adapter->stats.pxofftxc[j]; 1109 } 1110 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) { 1111 data[i++] = adapter->stats.pxonrxc[j]; 1112 data[i++] = adapter->stats.pxoffrxc[j]; 1113 } 1114 } 1115 1116 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset, 1117 u8 *data) 1118 { 1119 char *p = (char *)data; 1120 int i; 1121 1122 switch (stringset) { 1123 case ETH_SS_TEST: 1124 for (i = 0; i < IXGBE_TEST_LEN; i++) { 1125 memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN); 1126 data += ETH_GSTRING_LEN; 1127 } 1128 break; 1129 case ETH_SS_STATS: 1130 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 1131 memcpy(p, ixgbe_gstrings_stats[i].stat_string, 1132 ETH_GSTRING_LEN); 1133 p += ETH_GSTRING_LEN; 1134 } 1135 for (i = 0; i < netdev->num_tx_queues; i++) { 1136 sprintf(p, "tx_queue_%u_packets", i); 1137 p += ETH_GSTRING_LEN; 1138 sprintf(p, "tx_queue_%u_bytes", i); 1139 p += ETH_GSTRING_LEN; 1140 #ifdef LL_EXTENDED_STATS 1141 sprintf(p, "tx_queue_%u_ll_napi_yield", i); 1142 p += ETH_GSTRING_LEN; 1143 sprintf(p, "tx_queue_%u_ll_misses", i); 1144 p += ETH_GSTRING_LEN; 1145 sprintf(p, "tx_queue_%u_ll_cleaned", i); 1146 p += ETH_GSTRING_LEN; 1147 #endif /* LL_EXTENDED_STATS */ 1148 } 1149 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) { 1150 sprintf(p, "rx_queue_%u_packets", i); 1151 p += ETH_GSTRING_LEN; 1152 sprintf(p, "rx_queue_%u_bytes", i); 1153 p += ETH_GSTRING_LEN; 1154 #ifdef LL_EXTENDED_STATS 1155 sprintf(p, "rx_queue_%u_ll_poll_yield", i); 1156 p += ETH_GSTRING_LEN; 1157 sprintf(p, "rx_queue_%u_ll_misses", i); 1158 p += ETH_GSTRING_LEN; 1159 sprintf(p, "rx_queue_%u_ll_cleaned", i); 1160 p += ETH_GSTRING_LEN; 1161 #endif /* LL_EXTENDED_STATS */ 1162 } 1163 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 1164 sprintf(p, "tx_pb_%u_pxon", i); 1165 p += ETH_GSTRING_LEN; 1166 sprintf(p, "tx_pb_%u_pxoff", i); 1167 p += ETH_GSTRING_LEN; 1168 } 1169 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 1170 sprintf(p, "rx_pb_%u_pxon", i); 1171 p += ETH_GSTRING_LEN; 1172 sprintf(p, "rx_pb_%u_pxoff", i); 1173 p += ETH_GSTRING_LEN; 1174 } 1175 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */ 1176 break; 1177 } 1178 } 1179 1180 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data) 1181 { 1182 struct ixgbe_hw *hw = &adapter->hw; 1183 bool link_up; 1184 u32 link_speed = 0; 1185 *data = 0; 1186 1187 hw->mac.ops.check_link(hw, &link_speed, &link_up, true); 1188 if (link_up) 1189 return *data; 1190 else 1191 *data = 1; 1192 return *data; 1193 } 1194 1195 /* ethtool register test data */ 1196 struct ixgbe_reg_test { 1197 u16 reg; 1198 u8 array_len; 1199 u8 test_type; 1200 u32 mask; 1201 u32 write; 1202 }; 1203 1204 /* In the hardware, registers are laid out either singly, in arrays 1205 * spaced 0x40 bytes apart, or in contiguous tables. We assume 1206 * most tests take place on arrays or single registers (handled 1207 * as a single-element array) and special-case the tables. 1208 * Table tests are always pattern tests. 1209 * 1210 * We also make provision for some required setup steps by specifying 1211 * registers to be written without any read-back testing. 1212 */ 1213 1214 #define PATTERN_TEST 1 1215 #define SET_READ_TEST 2 1216 #define WRITE_NO_TEST 3 1217 #define TABLE32_TEST 4 1218 #define TABLE64_TEST_LO 5 1219 #define TABLE64_TEST_HI 6 1220 1221 /* default 82599 register test */ 1222 static const struct ixgbe_reg_test reg_test_82599[] = { 1223 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1224 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1225 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1226 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1227 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 }, 1228 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1229 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1230 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1231 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1232 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1233 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1234 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1235 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1236 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1237 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 }, 1238 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 }, 1239 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1240 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF }, 1241 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1242 { 0, 0, 0, 0 } 1243 }; 1244 1245 /* default 82598 register test */ 1246 static const struct ixgbe_reg_test reg_test_82598[] = { 1247 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1248 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1249 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1250 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1251 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1252 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1253 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1254 /* Enable all four RX queues before testing. */ 1255 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1256 /* RDH is read-only for 82598, only test RDT. */ 1257 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1258 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1259 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1260 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1261 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF }, 1262 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1263 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1264 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1265 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 }, 1266 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 }, 1267 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1268 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF }, 1269 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1270 { 0, 0, 0, 0 } 1271 }; 1272 1273 static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg, 1274 u32 mask, u32 write) 1275 { 1276 u32 pat, val, before; 1277 static const u32 test_pattern[] = { 1278 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1279 1280 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) { 1281 before = readl(adapter->hw.hw_addr + reg); 1282 writel((test_pattern[pat] & write), 1283 (adapter->hw.hw_addr + reg)); 1284 val = readl(adapter->hw.hw_addr + reg); 1285 if (val != (test_pattern[pat] & write & mask)) { 1286 e_err(drv, "pattern test reg %04X failed: got " 1287 "0x%08X expected 0x%08X\n", 1288 reg, val, (test_pattern[pat] & write & mask)); 1289 *data = reg; 1290 writel(before, adapter->hw.hw_addr + reg); 1291 return 1; 1292 } 1293 writel(before, adapter->hw.hw_addr + reg); 1294 } 1295 return 0; 1296 } 1297 1298 static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg, 1299 u32 mask, u32 write) 1300 { 1301 u32 val, before; 1302 before = readl(adapter->hw.hw_addr + reg); 1303 writel((write & mask), (adapter->hw.hw_addr + reg)); 1304 val = readl(adapter->hw.hw_addr + reg); 1305 if ((write & mask) != (val & mask)) { 1306 e_err(drv, "set/check reg %04X test failed: got 0x%08X " 1307 "expected 0x%08X\n", reg, (val & mask), (write & mask)); 1308 *data = reg; 1309 writel(before, (adapter->hw.hw_addr + reg)); 1310 return 1; 1311 } 1312 writel(before, (adapter->hw.hw_addr + reg)); 1313 return 0; 1314 } 1315 1316 #define REG_PATTERN_TEST(reg, mask, write) \ 1317 do { \ 1318 if (reg_pattern_test(adapter, data, reg, mask, write)) \ 1319 return 1; \ 1320 } while (0) \ 1321 1322 1323 #define REG_SET_AND_CHECK(reg, mask, write) \ 1324 do { \ 1325 if (reg_set_and_check(adapter, data, reg, mask, write)) \ 1326 return 1; \ 1327 } while (0) \ 1328 1329 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data) 1330 { 1331 const struct ixgbe_reg_test *test; 1332 u32 value, before, after; 1333 u32 i, toggle; 1334 1335 switch (adapter->hw.mac.type) { 1336 case ixgbe_mac_82598EB: 1337 toggle = 0x7FFFF3FF; 1338 test = reg_test_82598; 1339 break; 1340 case ixgbe_mac_82599EB: 1341 case ixgbe_mac_X540: 1342 toggle = 0x7FFFF30F; 1343 test = reg_test_82599; 1344 break; 1345 default: 1346 *data = 1; 1347 return 1; 1348 break; 1349 } 1350 1351 /* 1352 * Because the status register is such a special case, 1353 * we handle it separately from the rest of the register 1354 * tests. Some bits are read-only, some toggle, and some 1355 * are writeable on newer MACs. 1356 */ 1357 before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS); 1358 value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle); 1359 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle); 1360 after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle; 1361 if (value != after) { 1362 e_err(drv, "failed STATUS register test got: 0x%08X " 1363 "expected: 0x%08X\n", after, value); 1364 *data = 1; 1365 return 1; 1366 } 1367 /* restore previous status */ 1368 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before); 1369 1370 /* 1371 * Perform the remainder of the register test, looping through 1372 * the test table until we either fail or reach the null entry. 1373 */ 1374 while (test->reg) { 1375 for (i = 0; i < test->array_len; i++) { 1376 switch (test->test_type) { 1377 case PATTERN_TEST: 1378 REG_PATTERN_TEST(test->reg + (i * 0x40), 1379 test->mask, 1380 test->write); 1381 break; 1382 case SET_READ_TEST: 1383 REG_SET_AND_CHECK(test->reg + (i * 0x40), 1384 test->mask, 1385 test->write); 1386 break; 1387 case WRITE_NO_TEST: 1388 writel(test->write, 1389 (adapter->hw.hw_addr + test->reg) 1390 + (i * 0x40)); 1391 break; 1392 case TABLE32_TEST: 1393 REG_PATTERN_TEST(test->reg + (i * 4), 1394 test->mask, 1395 test->write); 1396 break; 1397 case TABLE64_TEST_LO: 1398 REG_PATTERN_TEST(test->reg + (i * 8), 1399 test->mask, 1400 test->write); 1401 break; 1402 case TABLE64_TEST_HI: 1403 REG_PATTERN_TEST((test->reg + 4) + (i * 8), 1404 test->mask, 1405 test->write); 1406 break; 1407 } 1408 } 1409 test++; 1410 } 1411 1412 *data = 0; 1413 return 0; 1414 } 1415 1416 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data) 1417 { 1418 struct ixgbe_hw *hw = &adapter->hw; 1419 if (hw->eeprom.ops.validate_checksum(hw, NULL)) 1420 *data = 1; 1421 else 1422 *data = 0; 1423 return *data; 1424 } 1425 1426 static irqreturn_t ixgbe_test_intr(int irq, void *data) 1427 { 1428 struct net_device *netdev = (struct net_device *) data; 1429 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1430 1431 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR); 1432 1433 return IRQ_HANDLED; 1434 } 1435 1436 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data) 1437 { 1438 struct net_device *netdev = adapter->netdev; 1439 u32 mask, i = 0, shared_int = true; 1440 u32 irq = adapter->pdev->irq; 1441 1442 *data = 0; 1443 1444 /* Hook up test interrupt handler just for this test */ 1445 if (adapter->msix_entries) { 1446 /* NOTE: we don't test MSI-X interrupts here, yet */ 1447 return 0; 1448 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { 1449 shared_int = false; 1450 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name, 1451 netdev)) { 1452 *data = 1; 1453 return -1; 1454 } 1455 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED, 1456 netdev->name, netdev)) { 1457 shared_int = false; 1458 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED, 1459 netdev->name, netdev)) { 1460 *data = 1; 1461 return -1; 1462 } 1463 e_info(hw, "testing %s interrupt\n", shared_int ? 1464 "shared" : "unshared"); 1465 1466 /* Disable all the interrupts */ 1467 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1468 IXGBE_WRITE_FLUSH(&adapter->hw); 1469 usleep_range(10000, 20000); 1470 1471 /* Test each interrupt */ 1472 for (; i < 10; i++) { 1473 /* Interrupt to test */ 1474 mask = 1 << i; 1475 1476 if (!shared_int) { 1477 /* 1478 * Disable the interrupts to be reported in 1479 * the cause register and then force the same 1480 * interrupt and see if one gets posted. If 1481 * an interrupt was posted to the bus, the 1482 * test failed. 1483 */ 1484 adapter->test_icr = 0; 1485 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 1486 ~mask & 0x00007FFF); 1487 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1488 ~mask & 0x00007FFF); 1489 IXGBE_WRITE_FLUSH(&adapter->hw); 1490 usleep_range(10000, 20000); 1491 1492 if (adapter->test_icr & mask) { 1493 *data = 3; 1494 break; 1495 } 1496 } 1497 1498 /* 1499 * Enable the interrupt to be reported in the cause 1500 * register and then force the same interrupt and see 1501 * if one gets posted. If an interrupt was not posted 1502 * to the bus, the test failed. 1503 */ 1504 adapter->test_icr = 0; 1505 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 1506 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 1507 IXGBE_WRITE_FLUSH(&adapter->hw); 1508 usleep_range(10000, 20000); 1509 1510 if (!(adapter->test_icr &mask)) { 1511 *data = 4; 1512 break; 1513 } 1514 1515 if (!shared_int) { 1516 /* 1517 * Disable the other interrupts to be reported in 1518 * the cause register and then force the other 1519 * interrupts and see if any get posted. If 1520 * an interrupt was posted to the bus, the 1521 * test failed. 1522 */ 1523 adapter->test_icr = 0; 1524 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 1525 ~mask & 0x00007FFF); 1526 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1527 ~mask & 0x00007FFF); 1528 IXGBE_WRITE_FLUSH(&adapter->hw); 1529 usleep_range(10000, 20000); 1530 1531 if (adapter->test_icr) { 1532 *data = 5; 1533 break; 1534 } 1535 } 1536 } 1537 1538 /* Disable all the interrupts */ 1539 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1540 IXGBE_WRITE_FLUSH(&adapter->hw); 1541 usleep_range(10000, 20000); 1542 1543 /* Unhook test interrupt handler */ 1544 free_irq(irq, netdev); 1545 1546 return *data; 1547 } 1548 1549 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter) 1550 { 1551 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1552 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1553 struct ixgbe_hw *hw = &adapter->hw; 1554 u32 reg_ctl; 1555 1556 /* shut down the DMA engines now so they can be reinitialized later */ 1557 1558 /* first Rx */ 1559 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1560 reg_ctl &= ~IXGBE_RXCTRL_RXEN; 1561 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl); 1562 ixgbe_disable_rx_queue(adapter, rx_ring); 1563 1564 /* now Tx */ 1565 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx)); 1566 reg_ctl &= ~IXGBE_TXDCTL_ENABLE; 1567 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl); 1568 1569 switch (hw->mac.type) { 1570 case ixgbe_mac_82599EB: 1571 case ixgbe_mac_X540: 1572 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1573 reg_ctl &= ~IXGBE_DMATXCTL_TE; 1574 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl); 1575 break; 1576 default: 1577 break; 1578 } 1579 1580 ixgbe_reset(adapter); 1581 1582 ixgbe_free_tx_resources(&adapter->test_tx_ring); 1583 ixgbe_free_rx_resources(&adapter->test_rx_ring); 1584 } 1585 1586 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter) 1587 { 1588 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1589 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1590 u32 rctl, reg_data; 1591 int ret_val; 1592 int err; 1593 1594 /* Setup Tx descriptor ring and Tx buffers */ 1595 tx_ring->count = IXGBE_DEFAULT_TXD; 1596 tx_ring->queue_index = 0; 1597 tx_ring->dev = &adapter->pdev->dev; 1598 tx_ring->netdev = adapter->netdev; 1599 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx; 1600 1601 err = ixgbe_setup_tx_resources(tx_ring); 1602 if (err) 1603 return 1; 1604 1605 switch (adapter->hw.mac.type) { 1606 case ixgbe_mac_82599EB: 1607 case ixgbe_mac_X540: 1608 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL); 1609 reg_data |= IXGBE_DMATXCTL_TE; 1610 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data); 1611 break; 1612 default: 1613 break; 1614 } 1615 1616 ixgbe_configure_tx_ring(adapter, tx_ring); 1617 1618 /* Setup Rx Descriptor ring and Rx buffers */ 1619 rx_ring->count = IXGBE_DEFAULT_RXD; 1620 rx_ring->queue_index = 0; 1621 rx_ring->dev = &adapter->pdev->dev; 1622 rx_ring->netdev = adapter->netdev; 1623 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx; 1624 1625 err = ixgbe_setup_rx_resources(rx_ring); 1626 if (err) { 1627 ret_val = 4; 1628 goto err_nomem; 1629 } 1630 1631 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL); 1632 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN); 1633 1634 ixgbe_configure_rx_ring(adapter, rx_ring); 1635 1636 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS; 1637 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl); 1638 1639 return 0; 1640 1641 err_nomem: 1642 ixgbe_free_desc_rings(adapter); 1643 return ret_val; 1644 } 1645 1646 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter) 1647 { 1648 struct ixgbe_hw *hw = &adapter->hw; 1649 u32 reg_data; 1650 1651 1652 /* Setup MAC loopback */ 1653 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0); 1654 reg_data |= IXGBE_HLREG0_LPBK; 1655 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data); 1656 1657 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1658 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE; 1659 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data); 1660 1661 /* X540 needs to set the MACC.FLU bit to force link up */ 1662 if (adapter->hw.mac.type == ixgbe_mac_X540) { 1663 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC); 1664 reg_data |= IXGBE_MACC_FLU; 1665 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data); 1666 } else { 1667 if (hw->mac.orig_autoc) { 1668 reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU; 1669 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data); 1670 } else { 1671 return 10; 1672 } 1673 } 1674 IXGBE_WRITE_FLUSH(hw); 1675 usleep_range(10000, 20000); 1676 1677 /* Disable Atlas Tx lanes; re-enabled in reset path */ 1678 if (hw->mac.type == ixgbe_mac_82598EB) { 1679 u8 atlas; 1680 1681 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas); 1682 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN; 1683 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas); 1684 1685 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas); 1686 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 1687 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas); 1688 1689 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas); 1690 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 1691 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas); 1692 1693 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas); 1694 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 1695 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas); 1696 } 1697 1698 return 0; 1699 } 1700 1701 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter) 1702 { 1703 u32 reg_data; 1704 1705 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0); 1706 reg_data &= ~IXGBE_HLREG0_LPBK; 1707 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data); 1708 } 1709 1710 static void ixgbe_create_lbtest_frame(struct sk_buff *skb, 1711 unsigned int frame_size) 1712 { 1713 memset(skb->data, 0xFF, frame_size); 1714 frame_size >>= 1; 1715 memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1); 1716 memset(&skb->data[frame_size + 10], 0xBE, 1); 1717 memset(&skb->data[frame_size + 12], 0xAF, 1); 1718 } 1719 1720 static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer, 1721 unsigned int frame_size) 1722 { 1723 unsigned char *data; 1724 bool match = true; 1725 1726 frame_size >>= 1; 1727 1728 data = kmap(rx_buffer->page) + rx_buffer->page_offset; 1729 1730 if (data[3] != 0xFF || 1731 data[frame_size + 10] != 0xBE || 1732 data[frame_size + 12] != 0xAF) 1733 match = false; 1734 1735 kunmap(rx_buffer->page); 1736 1737 return match; 1738 } 1739 1740 static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring, 1741 struct ixgbe_ring *tx_ring, 1742 unsigned int size) 1743 { 1744 union ixgbe_adv_rx_desc *rx_desc; 1745 struct ixgbe_rx_buffer *rx_buffer; 1746 struct ixgbe_tx_buffer *tx_buffer; 1747 u16 rx_ntc, tx_ntc, count = 0; 1748 1749 /* initialize next to clean and descriptor values */ 1750 rx_ntc = rx_ring->next_to_clean; 1751 tx_ntc = tx_ring->next_to_clean; 1752 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc); 1753 1754 while (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) { 1755 /* check Rx buffer */ 1756 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc]; 1757 1758 /* sync Rx buffer for CPU read */ 1759 dma_sync_single_for_cpu(rx_ring->dev, 1760 rx_buffer->dma, 1761 ixgbe_rx_bufsz(rx_ring), 1762 DMA_FROM_DEVICE); 1763 1764 /* verify contents of skb */ 1765 if (ixgbe_check_lbtest_frame(rx_buffer, size)) 1766 count++; 1767 1768 /* sync Rx buffer for device write */ 1769 dma_sync_single_for_device(rx_ring->dev, 1770 rx_buffer->dma, 1771 ixgbe_rx_bufsz(rx_ring), 1772 DMA_FROM_DEVICE); 1773 1774 /* unmap buffer on Tx side */ 1775 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc]; 1776 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer); 1777 1778 /* increment Rx/Tx next to clean counters */ 1779 rx_ntc++; 1780 if (rx_ntc == rx_ring->count) 1781 rx_ntc = 0; 1782 tx_ntc++; 1783 if (tx_ntc == tx_ring->count) 1784 tx_ntc = 0; 1785 1786 /* fetch next descriptor */ 1787 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc); 1788 } 1789 1790 netdev_tx_reset_queue(txring_txq(tx_ring)); 1791 1792 /* re-map buffers to ring, store next to clean values */ 1793 ixgbe_alloc_rx_buffers(rx_ring, count); 1794 rx_ring->next_to_clean = rx_ntc; 1795 tx_ring->next_to_clean = tx_ntc; 1796 1797 return count; 1798 } 1799 1800 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter) 1801 { 1802 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1803 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1804 int i, j, lc, good_cnt, ret_val = 0; 1805 unsigned int size = 1024; 1806 netdev_tx_t tx_ret_val; 1807 struct sk_buff *skb; 1808 1809 /* allocate test skb */ 1810 skb = alloc_skb(size, GFP_KERNEL); 1811 if (!skb) 1812 return 11; 1813 1814 /* place data into test skb */ 1815 ixgbe_create_lbtest_frame(skb, size); 1816 skb_put(skb, size); 1817 1818 /* 1819 * Calculate the loop count based on the largest descriptor ring 1820 * The idea is to wrap the largest ring a number of times using 64 1821 * send/receive pairs during each loop 1822 */ 1823 1824 if (rx_ring->count <= tx_ring->count) 1825 lc = ((tx_ring->count / 64) * 2) + 1; 1826 else 1827 lc = ((rx_ring->count / 64) * 2) + 1; 1828 1829 for (j = 0; j <= lc; j++) { 1830 /* reset count of good packets */ 1831 good_cnt = 0; 1832 1833 /* place 64 packets on the transmit queue*/ 1834 for (i = 0; i < 64; i++) { 1835 skb_get(skb); 1836 tx_ret_val = ixgbe_xmit_frame_ring(skb, 1837 adapter, 1838 tx_ring); 1839 if (tx_ret_val == NETDEV_TX_OK) 1840 good_cnt++; 1841 } 1842 1843 if (good_cnt != 64) { 1844 ret_val = 12; 1845 break; 1846 } 1847 1848 /* allow 200 milliseconds for packets to go from Tx to Rx */ 1849 msleep(200); 1850 1851 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size); 1852 if (good_cnt != 64) { 1853 ret_val = 13; 1854 break; 1855 } 1856 } 1857 1858 /* free the original skb */ 1859 kfree_skb(skb); 1860 1861 return ret_val; 1862 } 1863 1864 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data) 1865 { 1866 *data = ixgbe_setup_desc_rings(adapter); 1867 if (*data) 1868 goto out; 1869 *data = ixgbe_setup_loopback_test(adapter); 1870 if (*data) 1871 goto err_loopback; 1872 *data = ixgbe_run_loopback_test(adapter); 1873 ixgbe_loopback_cleanup(adapter); 1874 1875 err_loopback: 1876 ixgbe_free_desc_rings(adapter); 1877 out: 1878 return *data; 1879 } 1880 1881 static void ixgbe_diag_test(struct net_device *netdev, 1882 struct ethtool_test *eth_test, u64 *data) 1883 { 1884 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1885 bool if_running = netif_running(netdev); 1886 1887 set_bit(__IXGBE_TESTING, &adapter->state); 1888 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 1889 struct ixgbe_hw *hw = &adapter->hw; 1890 1891 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 1892 int i; 1893 for (i = 0; i < adapter->num_vfs; i++) { 1894 if (adapter->vfinfo[i].clear_to_send) { 1895 netdev_warn(netdev, "%s", 1896 "offline diagnostic is not " 1897 "supported when VFs are " 1898 "present\n"); 1899 data[0] = 1; 1900 data[1] = 1; 1901 data[2] = 1; 1902 data[3] = 1; 1903 eth_test->flags |= ETH_TEST_FL_FAILED; 1904 clear_bit(__IXGBE_TESTING, 1905 &adapter->state); 1906 goto skip_ol_tests; 1907 } 1908 } 1909 } 1910 1911 /* Offline tests */ 1912 e_info(hw, "offline testing starting\n"); 1913 1914 /* Link test performed before hardware reset so autoneg doesn't 1915 * interfere with test result 1916 */ 1917 if (ixgbe_link_test(adapter, &data[4])) 1918 eth_test->flags |= ETH_TEST_FL_FAILED; 1919 1920 if (if_running) 1921 /* indicate we're in test mode */ 1922 dev_close(netdev); 1923 else 1924 ixgbe_reset(adapter); 1925 1926 e_info(hw, "register testing starting\n"); 1927 if (ixgbe_reg_test(adapter, &data[0])) 1928 eth_test->flags |= ETH_TEST_FL_FAILED; 1929 1930 ixgbe_reset(adapter); 1931 e_info(hw, "eeprom testing starting\n"); 1932 if (ixgbe_eeprom_test(adapter, &data[1])) 1933 eth_test->flags |= ETH_TEST_FL_FAILED; 1934 1935 ixgbe_reset(adapter); 1936 e_info(hw, "interrupt testing starting\n"); 1937 if (ixgbe_intr_test(adapter, &data[2])) 1938 eth_test->flags |= ETH_TEST_FL_FAILED; 1939 1940 /* If SRIOV or VMDq is enabled then skip MAC 1941 * loopback diagnostic. */ 1942 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED | 1943 IXGBE_FLAG_VMDQ_ENABLED)) { 1944 e_info(hw, "Skip MAC loopback diagnostic in VT " 1945 "mode\n"); 1946 data[3] = 0; 1947 goto skip_loopback; 1948 } 1949 1950 ixgbe_reset(adapter); 1951 e_info(hw, "loopback testing starting\n"); 1952 if (ixgbe_loopback_test(adapter, &data[3])) 1953 eth_test->flags |= ETH_TEST_FL_FAILED; 1954 1955 skip_loopback: 1956 ixgbe_reset(adapter); 1957 1958 /* clear testing bit and return adapter to previous state */ 1959 clear_bit(__IXGBE_TESTING, &adapter->state); 1960 if (if_running) 1961 dev_open(netdev); 1962 else if (hw->mac.ops.disable_tx_laser) 1963 hw->mac.ops.disable_tx_laser(hw); 1964 } else { 1965 e_info(hw, "online testing starting\n"); 1966 1967 /* Online tests */ 1968 if (ixgbe_link_test(adapter, &data[4])) 1969 eth_test->flags |= ETH_TEST_FL_FAILED; 1970 1971 /* Offline tests aren't run; pass by default */ 1972 data[0] = 0; 1973 data[1] = 0; 1974 data[2] = 0; 1975 data[3] = 0; 1976 1977 clear_bit(__IXGBE_TESTING, &adapter->state); 1978 } 1979 1980 skip_ol_tests: 1981 msleep_interruptible(4 * 1000); 1982 } 1983 1984 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter, 1985 struct ethtool_wolinfo *wol) 1986 { 1987 struct ixgbe_hw *hw = &adapter->hw; 1988 int retval = 0; 1989 1990 /* WOL not supported for all devices */ 1991 if (!ixgbe_wol_supported(adapter, hw->device_id, 1992 hw->subsystem_device_id)) { 1993 retval = 1; 1994 wol->supported = 0; 1995 } 1996 1997 return retval; 1998 } 1999 2000 static void ixgbe_get_wol(struct net_device *netdev, 2001 struct ethtool_wolinfo *wol) 2002 { 2003 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2004 2005 wol->supported = WAKE_UCAST | WAKE_MCAST | 2006 WAKE_BCAST | WAKE_MAGIC; 2007 wol->wolopts = 0; 2008 2009 if (ixgbe_wol_exclusion(adapter, wol) || 2010 !device_can_wakeup(&adapter->pdev->dev)) 2011 return; 2012 2013 if (adapter->wol & IXGBE_WUFC_EX) 2014 wol->wolopts |= WAKE_UCAST; 2015 if (adapter->wol & IXGBE_WUFC_MC) 2016 wol->wolopts |= WAKE_MCAST; 2017 if (adapter->wol & IXGBE_WUFC_BC) 2018 wol->wolopts |= WAKE_BCAST; 2019 if (adapter->wol & IXGBE_WUFC_MAG) 2020 wol->wolopts |= WAKE_MAGIC; 2021 } 2022 2023 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2024 { 2025 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2026 2027 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE)) 2028 return -EOPNOTSUPP; 2029 2030 if (ixgbe_wol_exclusion(adapter, wol)) 2031 return wol->wolopts ? -EOPNOTSUPP : 0; 2032 2033 adapter->wol = 0; 2034 2035 if (wol->wolopts & WAKE_UCAST) 2036 adapter->wol |= IXGBE_WUFC_EX; 2037 if (wol->wolopts & WAKE_MCAST) 2038 adapter->wol |= IXGBE_WUFC_MC; 2039 if (wol->wolopts & WAKE_BCAST) 2040 adapter->wol |= IXGBE_WUFC_BC; 2041 if (wol->wolopts & WAKE_MAGIC) 2042 adapter->wol |= IXGBE_WUFC_MAG; 2043 2044 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2045 2046 return 0; 2047 } 2048 2049 static int ixgbe_nway_reset(struct net_device *netdev) 2050 { 2051 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2052 2053 if (netif_running(netdev)) 2054 ixgbe_reinit_locked(adapter); 2055 2056 return 0; 2057 } 2058 2059 static int ixgbe_set_phys_id(struct net_device *netdev, 2060 enum ethtool_phys_id_state state) 2061 { 2062 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2063 struct ixgbe_hw *hw = &adapter->hw; 2064 2065 switch (state) { 2066 case ETHTOOL_ID_ACTIVE: 2067 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2068 return 2; 2069 2070 case ETHTOOL_ID_ON: 2071 hw->mac.ops.led_on(hw, IXGBE_LED_ON); 2072 break; 2073 2074 case ETHTOOL_ID_OFF: 2075 hw->mac.ops.led_off(hw, IXGBE_LED_ON); 2076 break; 2077 2078 case ETHTOOL_ID_INACTIVE: 2079 /* Restore LED settings */ 2080 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg); 2081 break; 2082 } 2083 2084 return 0; 2085 } 2086 2087 static int ixgbe_get_coalesce(struct net_device *netdev, 2088 struct ethtool_coalesce *ec) 2089 { 2090 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2091 2092 /* only valid if in constant ITR mode */ 2093 if (adapter->rx_itr_setting <= 1) 2094 ec->rx_coalesce_usecs = adapter->rx_itr_setting; 2095 else 2096 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; 2097 2098 /* if in mixed tx/rx queues per vector mode, report only rx settings */ 2099 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) 2100 return 0; 2101 2102 /* only valid if in constant ITR mode */ 2103 if (adapter->tx_itr_setting <= 1) 2104 ec->tx_coalesce_usecs = adapter->tx_itr_setting; 2105 else 2106 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; 2107 2108 return 0; 2109 } 2110 2111 /* 2112 * this function must be called before setting the new value of 2113 * rx_itr_setting 2114 */ 2115 static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter) 2116 { 2117 struct net_device *netdev = adapter->netdev; 2118 2119 /* nothing to do if LRO or RSC are not enabled */ 2120 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) || 2121 !(netdev->features & NETIF_F_LRO)) 2122 return false; 2123 2124 /* check the feature flag value and enable RSC if necessary */ 2125 if (adapter->rx_itr_setting == 1 || 2126 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 2127 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 2128 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 2129 e_info(probe, "rx-usecs value high enough " 2130 "to re-enable RSC\n"); 2131 return true; 2132 } 2133 /* if interrupt rate is too high then disable RSC */ 2134 } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 2135 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 2136 e_info(probe, "rx-usecs set too low, disabling RSC\n"); 2137 return true; 2138 } 2139 return false; 2140 } 2141 2142 static int ixgbe_set_coalesce(struct net_device *netdev, 2143 struct ethtool_coalesce *ec) 2144 { 2145 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2146 struct ixgbe_q_vector *q_vector; 2147 int i; 2148 u16 tx_itr_param, rx_itr_param, tx_itr_prev; 2149 bool need_reset = false; 2150 2151 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) { 2152 /* reject Tx specific changes in case of mixed RxTx vectors */ 2153 if (ec->tx_coalesce_usecs) 2154 return -EINVAL; 2155 tx_itr_prev = adapter->rx_itr_setting; 2156 } else { 2157 tx_itr_prev = adapter->tx_itr_setting; 2158 } 2159 2160 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) || 2161 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2))) 2162 return -EINVAL; 2163 2164 if (ec->rx_coalesce_usecs > 1) 2165 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; 2166 else 2167 adapter->rx_itr_setting = ec->rx_coalesce_usecs; 2168 2169 if (adapter->rx_itr_setting == 1) 2170 rx_itr_param = IXGBE_20K_ITR; 2171 else 2172 rx_itr_param = adapter->rx_itr_setting; 2173 2174 if (ec->tx_coalesce_usecs > 1) 2175 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; 2176 else 2177 adapter->tx_itr_setting = ec->tx_coalesce_usecs; 2178 2179 if (adapter->tx_itr_setting == 1) 2180 tx_itr_param = IXGBE_10K_ITR; 2181 else 2182 tx_itr_param = adapter->tx_itr_setting; 2183 2184 /* mixed Rx/Tx */ 2185 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) 2186 adapter->tx_itr_setting = adapter->rx_itr_setting; 2187 2188 #if IS_ENABLED(CONFIG_BQL) 2189 /* detect ITR changes that require update of TXDCTL.WTHRESH */ 2190 if ((adapter->tx_itr_setting > 1) && 2191 (adapter->tx_itr_setting < IXGBE_100K_ITR)) { 2192 if ((tx_itr_prev == 1) || 2193 (tx_itr_prev > IXGBE_100K_ITR)) 2194 need_reset = true; 2195 } else { 2196 if ((tx_itr_prev > 1) && 2197 (tx_itr_prev < IXGBE_100K_ITR)) 2198 need_reset = true; 2199 } 2200 #endif 2201 /* check the old value and enable RSC if necessary */ 2202 need_reset |= ixgbe_update_rsc(adapter); 2203 2204 for (i = 0; i < adapter->num_q_vectors; i++) { 2205 q_vector = adapter->q_vector[i]; 2206 if (q_vector->tx.count && !q_vector->rx.count) 2207 /* tx only */ 2208 q_vector->itr = tx_itr_param; 2209 else 2210 /* rx only or mixed */ 2211 q_vector->itr = rx_itr_param; 2212 ixgbe_write_eitr(q_vector); 2213 } 2214 2215 /* 2216 * do reset here at the end to make sure EITR==0 case is handled 2217 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings 2218 * also locks in RSC enable/disable which requires reset 2219 */ 2220 if (need_reset) 2221 ixgbe_do_reset(netdev); 2222 2223 return 0; 2224 } 2225 2226 static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2227 struct ethtool_rxnfc *cmd) 2228 { 2229 union ixgbe_atr_input *mask = &adapter->fdir_mask; 2230 struct ethtool_rx_flow_spec *fsp = 2231 (struct ethtool_rx_flow_spec *)&cmd->fs; 2232 struct hlist_node *node2; 2233 struct ixgbe_fdir_filter *rule = NULL; 2234 2235 /* report total rule count */ 2236 cmd->data = (1024 << adapter->fdir_pballoc) - 2; 2237 2238 hlist_for_each_entry_safe(rule, node2, 2239 &adapter->fdir_filter_list, fdir_node) { 2240 if (fsp->location <= rule->sw_idx) 2241 break; 2242 } 2243 2244 if (!rule || fsp->location != rule->sw_idx) 2245 return -EINVAL; 2246 2247 /* fill out the flow spec entry */ 2248 2249 /* set flow type field */ 2250 switch (rule->filter.formatted.flow_type) { 2251 case IXGBE_ATR_FLOW_TYPE_TCPV4: 2252 fsp->flow_type = TCP_V4_FLOW; 2253 break; 2254 case IXGBE_ATR_FLOW_TYPE_UDPV4: 2255 fsp->flow_type = UDP_V4_FLOW; 2256 break; 2257 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 2258 fsp->flow_type = SCTP_V4_FLOW; 2259 break; 2260 case IXGBE_ATR_FLOW_TYPE_IPV4: 2261 fsp->flow_type = IP_USER_FLOW; 2262 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 2263 fsp->h_u.usr_ip4_spec.proto = 0; 2264 fsp->m_u.usr_ip4_spec.proto = 0; 2265 break; 2266 default: 2267 return -EINVAL; 2268 } 2269 2270 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port; 2271 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port; 2272 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port; 2273 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port; 2274 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0]; 2275 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0]; 2276 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0]; 2277 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0]; 2278 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id; 2279 fsp->m_ext.vlan_tci = mask->formatted.vlan_id; 2280 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes; 2281 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes; 2282 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool); 2283 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool); 2284 fsp->flow_type |= FLOW_EXT; 2285 2286 /* record action */ 2287 if (rule->action == IXGBE_FDIR_DROP_QUEUE) 2288 fsp->ring_cookie = RX_CLS_FLOW_DISC; 2289 else 2290 fsp->ring_cookie = rule->action; 2291 2292 return 0; 2293 } 2294 2295 static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter, 2296 struct ethtool_rxnfc *cmd, 2297 u32 *rule_locs) 2298 { 2299 struct hlist_node *node2; 2300 struct ixgbe_fdir_filter *rule; 2301 int cnt = 0; 2302 2303 /* report total rule count */ 2304 cmd->data = (1024 << adapter->fdir_pballoc) - 2; 2305 2306 hlist_for_each_entry_safe(rule, node2, 2307 &adapter->fdir_filter_list, fdir_node) { 2308 if (cnt == cmd->rule_cnt) 2309 return -EMSGSIZE; 2310 rule_locs[cnt] = rule->sw_idx; 2311 cnt++; 2312 } 2313 2314 cmd->rule_cnt = cnt; 2315 2316 return 0; 2317 } 2318 2319 static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter, 2320 struct ethtool_rxnfc *cmd) 2321 { 2322 cmd->data = 0; 2323 2324 /* Report default options for RSS on ixgbe */ 2325 switch (cmd->flow_type) { 2326 case TCP_V4_FLOW: 2327 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2328 case UDP_V4_FLOW: 2329 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 2330 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2331 case SCTP_V4_FLOW: 2332 case AH_ESP_V4_FLOW: 2333 case AH_V4_FLOW: 2334 case ESP_V4_FLOW: 2335 case IPV4_FLOW: 2336 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2337 break; 2338 case TCP_V6_FLOW: 2339 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2340 case UDP_V6_FLOW: 2341 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2342 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2343 case SCTP_V6_FLOW: 2344 case AH_ESP_V6_FLOW: 2345 case AH_V6_FLOW: 2346 case ESP_V6_FLOW: 2347 case IPV6_FLOW: 2348 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2349 break; 2350 default: 2351 return -EINVAL; 2352 } 2353 2354 return 0; 2355 } 2356 2357 static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2358 u32 *rule_locs) 2359 { 2360 struct ixgbe_adapter *adapter = netdev_priv(dev); 2361 int ret = -EOPNOTSUPP; 2362 2363 switch (cmd->cmd) { 2364 case ETHTOOL_GRXRINGS: 2365 cmd->data = adapter->num_rx_queues; 2366 ret = 0; 2367 break; 2368 case ETHTOOL_GRXCLSRLCNT: 2369 cmd->rule_cnt = adapter->fdir_filter_count; 2370 ret = 0; 2371 break; 2372 case ETHTOOL_GRXCLSRULE: 2373 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd); 2374 break; 2375 case ETHTOOL_GRXCLSRLALL: 2376 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs); 2377 break; 2378 case ETHTOOL_GRXFH: 2379 ret = ixgbe_get_rss_hash_opts(adapter, cmd); 2380 break; 2381 default: 2382 break; 2383 } 2384 2385 return ret; 2386 } 2387 2388 static int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2389 struct ixgbe_fdir_filter *input, 2390 u16 sw_idx) 2391 { 2392 struct ixgbe_hw *hw = &adapter->hw; 2393 struct hlist_node *node2; 2394 struct ixgbe_fdir_filter *rule, *parent; 2395 int err = -EINVAL; 2396 2397 parent = NULL; 2398 rule = NULL; 2399 2400 hlist_for_each_entry_safe(rule, node2, 2401 &adapter->fdir_filter_list, fdir_node) { 2402 /* hash found, or no matching entry */ 2403 if (rule->sw_idx >= sw_idx) 2404 break; 2405 parent = rule; 2406 } 2407 2408 /* if there is an old rule occupying our place remove it */ 2409 if (rule && (rule->sw_idx == sw_idx)) { 2410 if (!input || (rule->filter.formatted.bkt_hash != 2411 input->filter.formatted.bkt_hash)) { 2412 err = ixgbe_fdir_erase_perfect_filter_82599(hw, 2413 &rule->filter, 2414 sw_idx); 2415 } 2416 2417 hlist_del(&rule->fdir_node); 2418 kfree(rule); 2419 adapter->fdir_filter_count--; 2420 } 2421 2422 /* 2423 * If no input this was a delete, err should be 0 if a rule was 2424 * successfully found and removed from the list else -EINVAL 2425 */ 2426 if (!input) 2427 return err; 2428 2429 /* initialize node and set software index */ 2430 INIT_HLIST_NODE(&input->fdir_node); 2431 2432 /* add filter to the list */ 2433 if (parent) 2434 hlist_add_after(&parent->fdir_node, &input->fdir_node); 2435 else 2436 hlist_add_head(&input->fdir_node, 2437 &adapter->fdir_filter_list); 2438 2439 /* update counts */ 2440 adapter->fdir_filter_count++; 2441 2442 return 0; 2443 } 2444 2445 static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp, 2446 u8 *flow_type) 2447 { 2448 switch (fsp->flow_type & ~FLOW_EXT) { 2449 case TCP_V4_FLOW: 2450 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 2451 break; 2452 case UDP_V4_FLOW: 2453 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 2454 break; 2455 case SCTP_V4_FLOW: 2456 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 2457 break; 2458 case IP_USER_FLOW: 2459 switch (fsp->h_u.usr_ip4_spec.proto) { 2460 case IPPROTO_TCP: 2461 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 2462 break; 2463 case IPPROTO_UDP: 2464 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 2465 break; 2466 case IPPROTO_SCTP: 2467 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 2468 break; 2469 case 0: 2470 if (!fsp->m_u.usr_ip4_spec.proto) { 2471 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4; 2472 break; 2473 } 2474 default: 2475 return 0; 2476 } 2477 break; 2478 default: 2479 return 0; 2480 } 2481 2482 return 1; 2483 } 2484 2485 static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2486 struct ethtool_rxnfc *cmd) 2487 { 2488 struct ethtool_rx_flow_spec *fsp = 2489 (struct ethtool_rx_flow_spec *)&cmd->fs; 2490 struct ixgbe_hw *hw = &adapter->hw; 2491 struct ixgbe_fdir_filter *input; 2492 union ixgbe_atr_input mask; 2493 int err; 2494 2495 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 2496 return -EOPNOTSUPP; 2497 2498 /* 2499 * Don't allow programming if the action is a queue greater than 2500 * the number of online Rx queues. 2501 */ 2502 if ((fsp->ring_cookie != RX_CLS_FLOW_DISC) && 2503 (fsp->ring_cookie >= adapter->num_rx_queues)) 2504 return -EINVAL; 2505 2506 /* Don't allow indexes to exist outside of available space */ 2507 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) { 2508 e_err(drv, "Location out of range\n"); 2509 return -EINVAL; 2510 } 2511 2512 input = kzalloc(sizeof(*input), GFP_ATOMIC); 2513 if (!input) 2514 return -ENOMEM; 2515 2516 memset(&mask, 0, sizeof(union ixgbe_atr_input)); 2517 2518 /* set SW index */ 2519 input->sw_idx = fsp->location; 2520 2521 /* record flow type */ 2522 if (!ixgbe_flowspec_to_flow_type(fsp, 2523 &input->filter.formatted.flow_type)) { 2524 e_err(drv, "Unrecognized flow type\n"); 2525 goto err_out; 2526 } 2527 2528 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 2529 IXGBE_ATR_L4TYPE_MASK; 2530 2531 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 2532 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 2533 2534 /* Copy input into formatted structures */ 2535 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src; 2536 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src; 2537 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst; 2538 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst; 2539 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc; 2540 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc; 2541 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst; 2542 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst; 2543 2544 if (fsp->flow_type & FLOW_EXT) { 2545 input->filter.formatted.vm_pool = 2546 (unsigned char)ntohl(fsp->h_ext.data[1]); 2547 mask.formatted.vm_pool = 2548 (unsigned char)ntohl(fsp->m_ext.data[1]); 2549 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci; 2550 mask.formatted.vlan_id = fsp->m_ext.vlan_tci; 2551 input->filter.formatted.flex_bytes = 2552 fsp->h_ext.vlan_etype; 2553 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype; 2554 } 2555 2556 /* determine if we need to drop or route the packet */ 2557 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) 2558 input->action = IXGBE_FDIR_DROP_QUEUE; 2559 else 2560 input->action = fsp->ring_cookie; 2561 2562 spin_lock(&adapter->fdir_perfect_lock); 2563 2564 if (hlist_empty(&adapter->fdir_filter_list)) { 2565 /* save mask and program input mask into HW */ 2566 memcpy(&adapter->fdir_mask, &mask, sizeof(mask)); 2567 err = ixgbe_fdir_set_input_mask_82599(hw, &mask); 2568 if (err) { 2569 e_err(drv, "Error writing mask\n"); 2570 goto err_out_w_lock; 2571 } 2572 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) { 2573 e_err(drv, "Only one mask supported per port\n"); 2574 goto err_out_w_lock; 2575 } 2576 2577 /* apply mask and compute/store hash */ 2578 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask); 2579 2580 /* program filters to filter memory */ 2581 err = ixgbe_fdir_write_perfect_filter_82599(hw, 2582 &input->filter, input->sw_idx, 2583 (input->action == IXGBE_FDIR_DROP_QUEUE) ? 2584 IXGBE_FDIR_DROP_QUEUE : 2585 adapter->rx_ring[input->action]->reg_idx); 2586 if (err) 2587 goto err_out_w_lock; 2588 2589 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 2590 2591 spin_unlock(&adapter->fdir_perfect_lock); 2592 2593 return err; 2594 err_out_w_lock: 2595 spin_unlock(&adapter->fdir_perfect_lock); 2596 err_out: 2597 kfree(input); 2598 return -EINVAL; 2599 } 2600 2601 static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2602 struct ethtool_rxnfc *cmd) 2603 { 2604 struct ethtool_rx_flow_spec *fsp = 2605 (struct ethtool_rx_flow_spec *)&cmd->fs; 2606 int err; 2607 2608 spin_lock(&adapter->fdir_perfect_lock); 2609 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location); 2610 spin_unlock(&adapter->fdir_perfect_lock); 2611 2612 return err; 2613 } 2614 2615 #define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \ 2616 IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2617 static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter, 2618 struct ethtool_rxnfc *nfc) 2619 { 2620 u32 flags2 = adapter->flags2; 2621 2622 /* 2623 * RSS does not support anything other than hashing 2624 * to queues on src and dst IPs and ports 2625 */ 2626 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 2627 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 2628 return -EINVAL; 2629 2630 switch (nfc->flow_type) { 2631 case TCP_V4_FLOW: 2632 case TCP_V6_FLOW: 2633 if (!(nfc->data & RXH_IP_SRC) || 2634 !(nfc->data & RXH_IP_DST) || 2635 !(nfc->data & RXH_L4_B_0_1) || 2636 !(nfc->data & RXH_L4_B_2_3)) 2637 return -EINVAL; 2638 break; 2639 case UDP_V4_FLOW: 2640 if (!(nfc->data & RXH_IP_SRC) || 2641 !(nfc->data & RXH_IP_DST)) 2642 return -EINVAL; 2643 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2644 case 0: 2645 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP; 2646 break; 2647 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2648 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP; 2649 break; 2650 default: 2651 return -EINVAL; 2652 } 2653 break; 2654 case UDP_V6_FLOW: 2655 if (!(nfc->data & RXH_IP_SRC) || 2656 !(nfc->data & RXH_IP_DST)) 2657 return -EINVAL; 2658 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2659 case 0: 2660 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP; 2661 break; 2662 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2663 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP; 2664 break; 2665 default: 2666 return -EINVAL; 2667 } 2668 break; 2669 case AH_ESP_V4_FLOW: 2670 case AH_V4_FLOW: 2671 case ESP_V4_FLOW: 2672 case SCTP_V4_FLOW: 2673 case AH_ESP_V6_FLOW: 2674 case AH_V6_FLOW: 2675 case ESP_V6_FLOW: 2676 case SCTP_V6_FLOW: 2677 if (!(nfc->data & RXH_IP_SRC) || 2678 !(nfc->data & RXH_IP_DST) || 2679 (nfc->data & RXH_L4_B_0_1) || 2680 (nfc->data & RXH_L4_B_2_3)) 2681 return -EINVAL; 2682 break; 2683 default: 2684 return -EINVAL; 2685 } 2686 2687 /* if we changed something we need to update flags */ 2688 if (flags2 != adapter->flags2) { 2689 struct ixgbe_hw *hw = &adapter->hw; 2690 u32 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC); 2691 2692 if ((flags2 & UDP_RSS_FLAGS) && 2693 !(adapter->flags2 & UDP_RSS_FLAGS)) 2694 e_warn(drv, "enabling UDP RSS: fragmented packets" 2695 " may arrive out of order to the stack above\n"); 2696 2697 adapter->flags2 = flags2; 2698 2699 /* Perform hash on these packet types */ 2700 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 2701 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP 2702 | IXGBE_MRQC_RSS_FIELD_IPV6 2703 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 2704 2705 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP | 2706 IXGBE_MRQC_RSS_FIELD_IPV6_UDP); 2707 2708 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 2709 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 2710 2711 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2712 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 2713 2714 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 2715 } 2716 2717 return 0; 2718 } 2719 2720 static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2721 { 2722 struct ixgbe_adapter *adapter = netdev_priv(dev); 2723 int ret = -EOPNOTSUPP; 2724 2725 switch (cmd->cmd) { 2726 case ETHTOOL_SRXCLSRLINS: 2727 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd); 2728 break; 2729 case ETHTOOL_SRXCLSRLDEL: 2730 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd); 2731 break; 2732 case ETHTOOL_SRXFH: 2733 ret = ixgbe_set_rss_hash_opt(adapter, cmd); 2734 break; 2735 default: 2736 break; 2737 } 2738 2739 return ret; 2740 } 2741 2742 static int ixgbe_get_ts_info(struct net_device *dev, 2743 struct ethtool_ts_info *info) 2744 { 2745 struct ixgbe_adapter *adapter = netdev_priv(dev); 2746 2747 switch (adapter->hw.mac.type) { 2748 case ixgbe_mac_X540: 2749 case ixgbe_mac_82599EB: 2750 info->so_timestamping = 2751 SOF_TIMESTAMPING_TX_SOFTWARE | 2752 SOF_TIMESTAMPING_RX_SOFTWARE | 2753 SOF_TIMESTAMPING_SOFTWARE | 2754 SOF_TIMESTAMPING_TX_HARDWARE | 2755 SOF_TIMESTAMPING_RX_HARDWARE | 2756 SOF_TIMESTAMPING_RAW_HARDWARE; 2757 2758 if (adapter->ptp_clock) 2759 info->phc_index = ptp_clock_index(adapter->ptp_clock); 2760 else 2761 info->phc_index = -1; 2762 2763 info->tx_types = 2764 (1 << HWTSTAMP_TX_OFF) | 2765 (1 << HWTSTAMP_TX_ON); 2766 2767 info->rx_filters = 2768 (1 << HWTSTAMP_FILTER_NONE) | 2769 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 2770 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 2771 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 2772 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 2773 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 2774 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) | 2775 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 2776 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | 2777 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) | 2778 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 2779 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 2780 break; 2781 default: 2782 return ethtool_op_get_ts_info(dev, info); 2783 break; 2784 } 2785 return 0; 2786 } 2787 2788 static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter) 2789 { 2790 unsigned int max_combined; 2791 u8 tcs = netdev_get_num_tc(adapter->netdev); 2792 2793 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 2794 /* We only support one q_vector without MSI-X */ 2795 max_combined = 1; 2796 } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 2797 /* SR-IOV currently only allows one queue on the PF */ 2798 max_combined = 1; 2799 } else if (tcs > 1) { 2800 /* For DCB report channels per traffic class */ 2801 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 2802 /* 8 TC w/ 4 queues per TC */ 2803 max_combined = 4; 2804 } else if (tcs > 4) { 2805 /* 8 TC w/ 8 queues per TC */ 2806 max_combined = 8; 2807 } else { 2808 /* 4 TC w/ 16 queues per TC */ 2809 max_combined = 16; 2810 } 2811 } else if (adapter->atr_sample_rate) { 2812 /* support up to 64 queues with ATR */ 2813 max_combined = IXGBE_MAX_FDIR_INDICES; 2814 } else { 2815 /* support up to 16 queues with RSS */ 2816 max_combined = IXGBE_MAX_RSS_INDICES; 2817 } 2818 2819 return max_combined; 2820 } 2821 2822 static void ixgbe_get_channels(struct net_device *dev, 2823 struct ethtool_channels *ch) 2824 { 2825 struct ixgbe_adapter *adapter = netdev_priv(dev); 2826 2827 /* report maximum channels */ 2828 ch->max_combined = ixgbe_max_channels(adapter); 2829 2830 /* report info for other vector */ 2831 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 2832 ch->max_other = NON_Q_VECTORS; 2833 ch->other_count = NON_Q_VECTORS; 2834 } 2835 2836 /* record RSS queues */ 2837 ch->combined_count = adapter->ring_feature[RING_F_RSS].indices; 2838 2839 /* nothing else to report if RSS is disabled */ 2840 if (ch->combined_count == 1) 2841 return; 2842 2843 /* we do not support ATR queueing if SR-IOV is enabled */ 2844 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 2845 return; 2846 2847 /* same thing goes for being DCB enabled */ 2848 if (netdev_get_num_tc(dev) > 1) 2849 return; 2850 2851 /* if ATR is disabled we can exit */ 2852 if (!adapter->atr_sample_rate) 2853 return; 2854 2855 /* report flow director queues as maximum channels */ 2856 ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices; 2857 } 2858 2859 static int ixgbe_set_channels(struct net_device *dev, 2860 struct ethtool_channels *ch) 2861 { 2862 struct ixgbe_adapter *adapter = netdev_priv(dev); 2863 unsigned int count = ch->combined_count; 2864 2865 /* verify they are not requesting separate vectors */ 2866 if (!count || ch->rx_count || ch->tx_count) 2867 return -EINVAL; 2868 2869 /* verify other_count has not changed */ 2870 if (ch->other_count != NON_Q_VECTORS) 2871 return -EINVAL; 2872 2873 /* verify the number of channels does not exceed hardware limits */ 2874 if (count > ixgbe_max_channels(adapter)) 2875 return -EINVAL; 2876 2877 /* update feature limits from largest to smallest supported values */ 2878 adapter->ring_feature[RING_F_FDIR].limit = count; 2879 2880 /* cap RSS limit at 16 */ 2881 if (count > IXGBE_MAX_RSS_INDICES) 2882 count = IXGBE_MAX_RSS_INDICES; 2883 adapter->ring_feature[RING_F_RSS].limit = count; 2884 2885 #ifdef IXGBE_FCOE 2886 /* cap FCoE limit at 8 */ 2887 if (count > IXGBE_FCRETA_SIZE) 2888 count = IXGBE_FCRETA_SIZE; 2889 adapter->ring_feature[RING_F_FCOE].limit = count; 2890 2891 #endif 2892 /* use setup TC to update any traffic class queue mapping */ 2893 return ixgbe_setup_tc(dev, netdev_get_num_tc(dev)); 2894 } 2895 2896 static int ixgbe_get_module_info(struct net_device *dev, 2897 struct ethtool_modinfo *modinfo) 2898 { 2899 struct ixgbe_adapter *adapter = netdev_priv(dev); 2900 struct ixgbe_hw *hw = &adapter->hw; 2901 u32 status; 2902 u8 sff8472_rev, addr_mode; 2903 bool page_swap = false; 2904 2905 /* Check whether we support SFF-8472 or not */ 2906 status = hw->phy.ops.read_i2c_eeprom(hw, 2907 IXGBE_SFF_SFF_8472_COMP, 2908 &sff8472_rev); 2909 if (status != 0) 2910 return -EIO; 2911 2912 /* addressing mode is not supported */ 2913 status = hw->phy.ops.read_i2c_eeprom(hw, 2914 IXGBE_SFF_SFF_8472_SWAP, 2915 &addr_mode); 2916 if (status != 0) 2917 return -EIO; 2918 2919 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) { 2920 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n"); 2921 page_swap = true; 2922 } 2923 2924 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) { 2925 /* We have a SFP, but it does not support SFF-8472 */ 2926 modinfo->type = ETH_MODULE_SFF_8079; 2927 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 2928 } else { 2929 /* We have a SFP which supports a revision of SFF-8472. */ 2930 modinfo->type = ETH_MODULE_SFF_8472; 2931 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 2932 } 2933 2934 return 0; 2935 } 2936 2937 static int ixgbe_get_module_eeprom(struct net_device *dev, 2938 struct ethtool_eeprom *ee, 2939 u8 *data) 2940 { 2941 struct ixgbe_adapter *adapter = netdev_priv(dev); 2942 struct ixgbe_hw *hw = &adapter->hw; 2943 u32 status = IXGBE_ERR_PHY_ADDR_INVALID; 2944 u8 databyte = 0xFF; 2945 int i = 0; 2946 2947 if (ee->len == 0) 2948 return -EINVAL; 2949 2950 for (i = ee->offset; i < ee->offset + ee->len; i++) { 2951 /* I2C reads can take long time */ 2952 if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 2953 return -EBUSY; 2954 2955 if (i < ETH_MODULE_SFF_8079_LEN) 2956 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); 2957 else 2958 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); 2959 2960 if (status != 0) 2961 return -EIO; 2962 2963 data[i - ee->offset] = databyte; 2964 } 2965 2966 return 0; 2967 } 2968 2969 static const struct ethtool_ops ixgbe_ethtool_ops = { 2970 .get_settings = ixgbe_get_settings, 2971 .set_settings = ixgbe_set_settings, 2972 .get_drvinfo = ixgbe_get_drvinfo, 2973 .get_regs_len = ixgbe_get_regs_len, 2974 .get_regs = ixgbe_get_regs, 2975 .get_wol = ixgbe_get_wol, 2976 .set_wol = ixgbe_set_wol, 2977 .nway_reset = ixgbe_nway_reset, 2978 .get_link = ethtool_op_get_link, 2979 .get_eeprom_len = ixgbe_get_eeprom_len, 2980 .get_eeprom = ixgbe_get_eeprom, 2981 .set_eeprom = ixgbe_set_eeprom, 2982 .get_ringparam = ixgbe_get_ringparam, 2983 .set_ringparam = ixgbe_set_ringparam, 2984 .get_pauseparam = ixgbe_get_pauseparam, 2985 .set_pauseparam = ixgbe_set_pauseparam, 2986 .get_msglevel = ixgbe_get_msglevel, 2987 .set_msglevel = ixgbe_set_msglevel, 2988 .self_test = ixgbe_diag_test, 2989 .get_strings = ixgbe_get_strings, 2990 .set_phys_id = ixgbe_set_phys_id, 2991 .get_sset_count = ixgbe_get_sset_count, 2992 .get_ethtool_stats = ixgbe_get_ethtool_stats, 2993 .get_coalesce = ixgbe_get_coalesce, 2994 .set_coalesce = ixgbe_set_coalesce, 2995 .get_rxnfc = ixgbe_get_rxnfc, 2996 .set_rxnfc = ixgbe_set_rxnfc, 2997 .get_channels = ixgbe_get_channels, 2998 .set_channels = ixgbe_set_channels, 2999 .get_ts_info = ixgbe_get_ts_info, 3000 .get_module_info = ixgbe_get_module_info, 3001 .get_module_eeprom = ixgbe_get_module_eeprom, 3002 }; 3003 3004 void ixgbe_set_ethtool_ops(struct net_device *netdev) 3005 { 3006 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops); 3007 } 3008