1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 /* ethtool support for ixgbe */ 5 6 #include <linux/interrupt.h> 7 #include <linux/types.h> 8 #include <linux/module.h> 9 #include <linux/slab.h> 10 #include <linux/pci.h> 11 #include <linux/netdevice.h> 12 #include <linux/ethtool.h> 13 #include <linux/vmalloc.h> 14 #include <linux/highmem.h> 15 #include <linux/uaccess.h> 16 17 #include "ixgbe.h" 18 #include "ixgbe_phy.h" 19 20 21 #define IXGBE_ALL_RAR_ENTRIES 16 22 23 enum {NETDEV_STATS, IXGBE_STATS}; 24 25 struct ixgbe_stats { 26 char stat_string[ETH_GSTRING_LEN]; 27 int type; 28 int sizeof_stat; 29 int stat_offset; 30 }; 31 32 #define IXGBE_STAT(m) IXGBE_STATS, \ 33 sizeof(((struct ixgbe_adapter *)0)->m), \ 34 offsetof(struct ixgbe_adapter, m) 35 #define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \ 36 sizeof(((struct rtnl_link_stats64 *)0)->m), \ 37 offsetof(struct rtnl_link_stats64, m) 38 39 static const struct ixgbe_stats ixgbe_gstrings_stats[] = { 40 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)}, 41 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)}, 42 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)}, 43 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)}, 44 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)}, 45 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)}, 46 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)}, 47 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)}, 48 {"lsc_int", IXGBE_STAT(lsc_int)}, 49 {"tx_busy", IXGBE_STAT(tx_busy)}, 50 {"non_eop_descs", IXGBE_STAT(non_eop_descs)}, 51 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)}, 52 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)}, 53 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)}, 54 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)}, 55 {"multicast", IXGBE_NETDEV_STAT(multicast)}, 56 {"broadcast", IXGBE_STAT(stats.bprc)}, 57 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) }, 58 {"collisions", IXGBE_NETDEV_STAT(collisions)}, 59 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)}, 60 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)}, 61 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)}, 62 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)}, 63 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)}, 64 {"fdir_match", IXGBE_STAT(stats.fdirmatch)}, 65 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)}, 66 {"fdir_overflow", IXGBE_STAT(fdir_overflow)}, 67 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)}, 68 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)}, 69 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)}, 70 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)}, 71 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)}, 72 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)}, 73 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)}, 74 {"tx_restart_queue", IXGBE_STAT(restart_queue)}, 75 {"rx_length_errors", IXGBE_STAT(stats.rlec)}, 76 {"rx_long_length_errors", IXGBE_STAT(stats.roc)}, 77 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)}, 78 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)}, 79 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)}, 80 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)}, 81 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)}, 82 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)}, 83 {"alloc_rx_page", IXGBE_STAT(alloc_rx_page)}, 84 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)}, 85 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)}, 86 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)}, 87 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)}, 88 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)}, 89 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)}, 90 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)}, 91 {"tx_hwtstamp_timeouts", IXGBE_STAT(tx_hwtstamp_timeouts)}, 92 {"tx_hwtstamp_skipped", IXGBE_STAT(tx_hwtstamp_skipped)}, 93 {"rx_hwtstamp_cleared", IXGBE_STAT(rx_hwtstamp_cleared)}, 94 {"tx_ipsec", IXGBE_STAT(tx_ipsec)}, 95 {"rx_ipsec", IXGBE_STAT(rx_ipsec)}, 96 #ifdef IXGBE_FCOE 97 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)}, 98 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)}, 99 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)}, 100 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)}, 101 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)}, 102 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)}, 103 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)}, 104 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)}, 105 #endif /* IXGBE_FCOE */ 106 }; 107 108 /* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so 109 * we set the num_rx_queues to evaluate to num_tx_queues. This is 110 * used because we do not have a good way to get the max number of 111 * rx queues with CONFIG_RPS disabled. 112 */ 113 #define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues 114 115 #define IXGBE_QUEUE_STATS_LEN ( \ 116 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \ 117 (sizeof(struct ixgbe_queue_stats) / sizeof(u64))) 118 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats) 119 #define IXGBE_PB_STATS_LEN ( \ 120 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \ 121 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \ 122 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \ 123 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \ 124 / sizeof(u64)) 125 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \ 126 IXGBE_PB_STATS_LEN + \ 127 IXGBE_QUEUE_STATS_LEN) 128 129 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = { 130 "Register test (offline)", "Eeprom test (offline)", 131 "Interrupt test (offline)", "Loopback test (offline)", 132 "Link test (on/offline)" 133 }; 134 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN 135 136 static const char ixgbe_priv_flags_strings[][ETH_GSTRING_LEN] = { 137 #define IXGBE_PRIV_FLAGS_LEGACY_RX BIT(0) 138 "legacy-rx", 139 #define IXGBE_PRIV_FLAGS_VF_IPSEC_EN BIT(1) 140 "vf-ipsec", 141 }; 142 143 #define IXGBE_PRIV_FLAGS_STR_LEN ARRAY_SIZE(ixgbe_priv_flags_strings) 144 145 /* currently supported speeds for 10G */ 146 #define ADVRTSD_MSK_10G (SUPPORTED_10000baseT_Full | \ 147 SUPPORTED_10000baseKX4_Full | \ 148 SUPPORTED_10000baseKR_Full) 149 150 #define ixgbe_isbackplane(type) ((type) == ixgbe_media_type_backplane) 151 152 static u32 ixgbe_get_supported_10gtypes(struct ixgbe_hw *hw) 153 { 154 if (!ixgbe_isbackplane(hw->phy.media_type)) 155 return SUPPORTED_10000baseT_Full; 156 157 switch (hw->device_id) { 158 case IXGBE_DEV_ID_82598: 159 case IXGBE_DEV_ID_82599_KX4: 160 case IXGBE_DEV_ID_82599_KX4_MEZZ: 161 case IXGBE_DEV_ID_X550EM_X_KX4: 162 return SUPPORTED_10000baseKX4_Full; 163 case IXGBE_DEV_ID_82598_BX: 164 case IXGBE_DEV_ID_82599_KR: 165 case IXGBE_DEV_ID_X550EM_X_KR: 166 case IXGBE_DEV_ID_X550EM_X_XFI: 167 return SUPPORTED_10000baseKR_Full; 168 default: 169 return SUPPORTED_10000baseKX4_Full | 170 SUPPORTED_10000baseKR_Full; 171 } 172 } 173 174 static int ixgbe_get_link_ksettings(struct net_device *netdev, 175 struct ethtool_link_ksettings *cmd) 176 { 177 struct ixgbe_adapter *adapter = netdev_priv(netdev); 178 struct ixgbe_hw *hw = &adapter->hw; 179 ixgbe_link_speed supported_link; 180 bool autoneg = false; 181 u32 supported, advertising; 182 183 ethtool_convert_link_mode_to_legacy_u32(&supported, 184 cmd->link_modes.supported); 185 186 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg); 187 188 /* set the supported link speeds */ 189 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) 190 supported |= ixgbe_get_supported_10gtypes(hw); 191 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL) 192 supported |= (ixgbe_isbackplane(hw->phy.media_type)) ? 193 SUPPORTED_1000baseKX_Full : 194 SUPPORTED_1000baseT_Full; 195 if (supported_link & IXGBE_LINK_SPEED_100_FULL) 196 supported |= SUPPORTED_100baseT_Full; 197 if (supported_link & IXGBE_LINK_SPEED_10_FULL) 198 supported |= SUPPORTED_10baseT_Full; 199 200 /* default advertised speed if phy.autoneg_advertised isn't set */ 201 advertising = supported; 202 /* set the advertised speeds */ 203 if (hw->phy.autoneg_advertised) { 204 advertising = 0; 205 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL) 206 advertising |= ADVERTISED_10baseT_Full; 207 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 208 advertising |= ADVERTISED_100baseT_Full; 209 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 210 advertising |= supported & ADVRTSD_MSK_10G; 211 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) { 212 if (supported & SUPPORTED_1000baseKX_Full) 213 advertising |= ADVERTISED_1000baseKX_Full; 214 else 215 advertising |= ADVERTISED_1000baseT_Full; 216 } 217 } else { 218 if (hw->phy.multispeed_fiber && !autoneg) { 219 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) 220 advertising = ADVERTISED_10000baseT_Full; 221 } 222 } 223 224 if (autoneg) { 225 supported |= SUPPORTED_Autoneg; 226 advertising |= ADVERTISED_Autoneg; 227 cmd->base.autoneg = AUTONEG_ENABLE; 228 } else 229 cmd->base.autoneg = AUTONEG_DISABLE; 230 231 /* Determine the remaining settings based on the PHY type. */ 232 switch (adapter->hw.phy.type) { 233 case ixgbe_phy_tn: 234 case ixgbe_phy_aq: 235 case ixgbe_phy_x550em_ext_t: 236 case ixgbe_phy_fw: 237 case ixgbe_phy_cu_unknown: 238 supported |= SUPPORTED_TP; 239 advertising |= ADVERTISED_TP; 240 cmd->base.port = PORT_TP; 241 break; 242 case ixgbe_phy_qt: 243 supported |= SUPPORTED_FIBRE; 244 advertising |= ADVERTISED_FIBRE; 245 cmd->base.port = PORT_FIBRE; 246 break; 247 case ixgbe_phy_nl: 248 case ixgbe_phy_sfp_passive_tyco: 249 case ixgbe_phy_sfp_passive_unknown: 250 case ixgbe_phy_sfp_ftl: 251 case ixgbe_phy_sfp_avago: 252 case ixgbe_phy_sfp_intel: 253 case ixgbe_phy_sfp_unknown: 254 case ixgbe_phy_qsfp_passive_unknown: 255 case ixgbe_phy_qsfp_active_unknown: 256 case ixgbe_phy_qsfp_intel: 257 case ixgbe_phy_qsfp_unknown: 258 /* SFP+ devices, further checking needed */ 259 switch (adapter->hw.phy.sfp_type) { 260 case ixgbe_sfp_type_da_cu: 261 case ixgbe_sfp_type_da_cu_core0: 262 case ixgbe_sfp_type_da_cu_core1: 263 supported |= SUPPORTED_FIBRE; 264 advertising |= ADVERTISED_FIBRE; 265 cmd->base.port = PORT_DA; 266 break; 267 case ixgbe_sfp_type_sr: 268 case ixgbe_sfp_type_lr: 269 case ixgbe_sfp_type_srlr_core0: 270 case ixgbe_sfp_type_srlr_core1: 271 case ixgbe_sfp_type_1g_sx_core0: 272 case ixgbe_sfp_type_1g_sx_core1: 273 case ixgbe_sfp_type_1g_lx_core0: 274 case ixgbe_sfp_type_1g_lx_core1: 275 supported |= SUPPORTED_FIBRE; 276 advertising |= ADVERTISED_FIBRE; 277 cmd->base.port = PORT_FIBRE; 278 break; 279 case ixgbe_sfp_type_not_present: 280 supported |= SUPPORTED_FIBRE; 281 advertising |= ADVERTISED_FIBRE; 282 cmd->base.port = PORT_NONE; 283 break; 284 case ixgbe_sfp_type_1g_cu_core0: 285 case ixgbe_sfp_type_1g_cu_core1: 286 supported |= SUPPORTED_TP; 287 advertising |= ADVERTISED_TP; 288 cmd->base.port = PORT_TP; 289 break; 290 case ixgbe_sfp_type_unknown: 291 default: 292 supported |= SUPPORTED_FIBRE; 293 advertising |= ADVERTISED_FIBRE; 294 cmd->base.port = PORT_OTHER; 295 break; 296 } 297 break; 298 case ixgbe_phy_xaui: 299 supported |= SUPPORTED_FIBRE; 300 advertising |= ADVERTISED_FIBRE; 301 cmd->base.port = PORT_NONE; 302 break; 303 case ixgbe_phy_unknown: 304 case ixgbe_phy_generic: 305 case ixgbe_phy_sfp_unsupported: 306 default: 307 supported |= SUPPORTED_FIBRE; 308 advertising |= ADVERTISED_FIBRE; 309 cmd->base.port = PORT_OTHER; 310 break; 311 } 312 313 /* Indicate pause support */ 314 supported |= SUPPORTED_Pause; 315 316 switch (hw->fc.requested_mode) { 317 case ixgbe_fc_full: 318 advertising |= ADVERTISED_Pause; 319 break; 320 case ixgbe_fc_rx_pause: 321 advertising |= ADVERTISED_Pause | 322 ADVERTISED_Asym_Pause; 323 break; 324 case ixgbe_fc_tx_pause: 325 advertising |= ADVERTISED_Asym_Pause; 326 break; 327 default: 328 advertising &= ~(ADVERTISED_Pause | 329 ADVERTISED_Asym_Pause); 330 } 331 332 if (netif_carrier_ok(netdev)) { 333 switch (adapter->link_speed) { 334 case IXGBE_LINK_SPEED_10GB_FULL: 335 cmd->base.speed = SPEED_10000; 336 break; 337 case IXGBE_LINK_SPEED_5GB_FULL: 338 cmd->base.speed = SPEED_5000; 339 break; 340 case IXGBE_LINK_SPEED_2_5GB_FULL: 341 cmd->base.speed = SPEED_2500; 342 break; 343 case IXGBE_LINK_SPEED_1GB_FULL: 344 cmd->base.speed = SPEED_1000; 345 break; 346 case IXGBE_LINK_SPEED_100_FULL: 347 cmd->base.speed = SPEED_100; 348 break; 349 case IXGBE_LINK_SPEED_10_FULL: 350 cmd->base.speed = SPEED_10; 351 break; 352 default: 353 break; 354 } 355 cmd->base.duplex = DUPLEX_FULL; 356 } else { 357 cmd->base.speed = SPEED_UNKNOWN; 358 cmd->base.duplex = DUPLEX_UNKNOWN; 359 } 360 361 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 362 supported); 363 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 364 advertising); 365 366 return 0; 367 } 368 369 static int ixgbe_set_link_ksettings(struct net_device *netdev, 370 const struct ethtool_link_ksettings *cmd) 371 { 372 struct ixgbe_adapter *adapter = netdev_priv(netdev); 373 struct ixgbe_hw *hw = &adapter->hw; 374 u32 advertised, old; 375 s32 err = 0; 376 u32 supported, advertising; 377 378 ethtool_convert_link_mode_to_legacy_u32(&supported, 379 cmd->link_modes.supported); 380 ethtool_convert_link_mode_to_legacy_u32(&advertising, 381 cmd->link_modes.advertising); 382 383 if ((hw->phy.media_type == ixgbe_media_type_copper) || 384 (hw->phy.multispeed_fiber)) { 385 /* 386 * this function does not support duplex forcing, but can 387 * limit the advertising of the adapter to the specified speed 388 */ 389 if (advertising & ~supported) 390 return -EINVAL; 391 392 /* only allow one speed at a time if no autoneg */ 393 if (!cmd->base.autoneg && hw->phy.multispeed_fiber) { 394 if (advertising == 395 (ADVERTISED_10000baseT_Full | 396 ADVERTISED_1000baseT_Full)) 397 return -EINVAL; 398 } 399 400 old = hw->phy.autoneg_advertised; 401 advertised = 0; 402 if (advertising & ADVERTISED_10000baseT_Full) 403 advertised |= IXGBE_LINK_SPEED_10GB_FULL; 404 405 if (advertising & ADVERTISED_1000baseT_Full) 406 advertised |= IXGBE_LINK_SPEED_1GB_FULL; 407 408 if (advertising & ADVERTISED_100baseT_Full) 409 advertised |= IXGBE_LINK_SPEED_100_FULL; 410 411 if (advertising & ADVERTISED_10baseT_Full) 412 advertised |= IXGBE_LINK_SPEED_10_FULL; 413 414 if (old == advertised) 415 return err; 416 /* this sets the link speed and restarts auto-neg */ 417 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 418 usleep_range(1000, 2000); 419 420 hw->mac.autotry_restart = true; 421 err = hw->mac.ops.setup_link(hw, advertised, true); 422 if (err) { 423 e_info(probe, "setup link failed with code %d\n", err); 424 hw->mac.ops.setup_link(hw, old, true); 425 } 426 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 427 } else { 428 /* in this case we currently only support 10Gb/FULL */ 429 u32 speed = cmd->base.speed; 430 431 if ((cmd->base.autoneg == AUTONEG_ENABLE) || 432 (advertising != ADVERTISED_10000baseT_Full) || 433 (speed + cmd->base.duplex != SPEED_10000 + DUPLEX_FULL)) 434 return -EINVAL; 435 } 436 437 return err; 438 } 439 440 static void ixgbe_get_pauseparam(struct net_device *netdev, 441 struct ethtool_pauseparam *pause) 442 { 443 struct ixgbe_adapter *adapter = netdev_priv(netdev); 444 struct ixgbe_hw *hw = &adapter->hw; 445 446 if (ixgbe_device_supports_autoneg_fc(hw) && 447 !hw->fc.disable_fc_autoneg) 448 pause->autoneg = 1; 449 else 450 pause->autoneg = 0; 451 452 if (hw->fc.current_mode == ixgbe_fc_rx_pause) { 453 pause->rx_pause = 1; 454 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) { 455 pause->tx_pause = 1; 456 } else if (hw->fc.current_mode == ixgbe_fc_full) { 457 pause->rx_pause = 1; 458 pause->tx_pause = 1; 459 } 460 } 461 462 static int ixgbe_set_pauseparam(struct net_device *netdev, 463 struct ethtool_pauseparam *pause) 464 { 465 struct ixgbe_adapter *adapter = netdev_priv(netdev); 466 struct ixgbe_hw *hw = &adapter->hw; 467 struct ixgbe_fc_info fc = hw->fc; 468 469 /* 82598 does no support link flow control with DCB enabled */ 470 if ((hw->mac.type == ixgbe_mac_82598EB) && 471 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)) 472 return -EINVAL; 473 474 /* some devices do not support autoneg of link flow control */ 475 if ((pause->autoneg == AUTONEG_ENABLE) && 476 !ixgbe_device_supports_autoneg_fc(hw)) 477 return -EINVAL; 478 479 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE); 480 481 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg) 482 fc.requested_mode = ixgbe_fc_full; 483 else if (pause->rx_pause && !pause->tx_pause) 484 fc.requested_mode = ixgbe_fc_rx_pause; 485 else if (!pause->rx_pause && pause->tx_pause) 486 fc.requested_mode = ixgbe_fc_tx_pause; 487 else 488 fc.requested_mode = ixgbe_fc_none; 489 490 /* if the thing changed then we'll update and use new autoneg */ 491 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) { 492 hw->fc = fc; 493 if (netif_running(netdev)) 494 ixgbe_reinit_locked(adapter); 495 else 496 ixgbe_reset(adapter); 497 } 498 499 return 0; 500 } 501 502 static u32 ixgbe_get_msglevel(struct net_device *netdev) 503 { 504 struct ixgbe_adapter *adapter = netdev_priv(netdev); 505 return adapter->msg_enable; 506 } 507 508 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data) 509 { 510 struct ixgbe_adapter *adapter = netdev_priv(netdev); 511 adapter->msg_enable = data; 512 } 513 514 static int ixgbe_get_regs_len(struct net_device *netdev) 515 { 516 #define IXGBE_REGS_LEN 1145 517 return IXGBE_REGS_LEN * sizeof(u32); 518 } 519 520 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_ 521 522 static void ixgbe_get_regs(struct net_device *netdev, 523 struct ethtool_regs *regs, void *p) 524 { 525 struct ixgbe_adapter *adapter = netdev_priv(netdev); 526 struct ixgbe_hw *hw = &adapter->hw; 527 u32 *regs_buff = p; 528 u8 i; 529 530 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32)); 531 532 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 533 hw->device_id; 534 535 /* General Registers */ 536 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL); 537 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS); 538 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 539 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP); 540 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP); 541 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 542 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER); 543 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER); 544 545 /* NVM Register */ 546 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 547 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD); 548 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA(hw)); 549 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL); 550 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA); 551 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL); 552 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA); 553 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT); 554 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP); 555 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC(hw)); 556 557 /* Interrupt */ 558 /* don't read EICR because it can clear interrupt causes, instead 559 * read EICS which is a shadow but doesn't clear EICR */ 560 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS); 561 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS); 562 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS); 563 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC); 564 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC); 565 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM); 566 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0)); 567 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0)); 568 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT); 569 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA); 570 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0)); 571 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE); 572 573 /* Flow Control */ 574 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP); 575 for (i = 0; i < 4; i++) 576 regs_buff[31 + i] = IXGBE_READ_REG(hw, IXGBE_FCTTV(i)); 577 for (i = 0; i < 8; i++) { 578 switch (hw->mac.type) { 579 case ixgbe_mac_82598EB: 580 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i)); 581 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i)); 582 break; 583 case ixgbe_mac_82599EB: 584 case ixgbe_mac_X540: 585 case ixgbe_mac_X550: 586 case ixgbe_mac_X550EM_x: 587 case ixgbe_mac_x550em_a: 588 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i)); 589 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 590 break; 591 default: 592 break; 593 } 594 } 595 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV); 596 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS); 597 598 /* Receive DMA */ 599 for (i = 0; i < 64; i++) 600 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 601 for (i = 0; i < 64; i++) 602 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 603 for (i = 0; i < 64; i++) 604 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 605 for (i = 0; i < 64; i++) 606 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 607 for (i = 0; i < 64; i++) 608 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 609 for (i = 0; i < 64; i++) 610 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 611 for (i = 0; i < 16; i++) 612 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 613 for (i = 0; i < 16; i++) 614 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 615 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 616 for (i = 0; i < 8; i++) 617 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)); 618 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 619 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN); 620 621 /* Receive */ 622 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 623 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL); 624 for (i = 0; i < 16; i++) 625 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 626 for (i = 0; i < 16; i++) 627 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 628 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0)); 629 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL); 630 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 631 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL); 632 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC); 633 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 634 for (i = 0; i < 8; i++) 635 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i)); 636 for (i = 0; i < 8; i++) 637 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i)); 638 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP); 639 640 /* Transmit */ 641 for (i = 0; i < 32; i++) 642 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 643 for (i = 0; i < 32; i++) 644 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 645 for (i = 0; i < 32; i++) 646 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 647 for (i = 0; i < 32; i++) 648 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 649 for (i = 0; i < 32; i++) 650 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 651 for (i = 0; i < 32; i++) 652 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 653 for (i = 0; i < 32; i++) 654 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i)); 655 for (i = 0; i < 32; i++) 656 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i)); 657 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL); 658 for (i = 0; i < 16; i++) 659 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); 660 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG); 661 for (i = 0; i < 8; i++) 662 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i)); 663 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP); 664 665 /* Wake Up */ 666 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC); 667 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC); 668 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS); 669 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV); 670 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT); 671 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT); 672 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL); 673 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM); 674 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0)); 675 676 /* DCB */ 677 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); /* same as FCCFG */ 678 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); /* same as RTTPCS */ 679 680 switch (hw->mac.type) { 681 case ixgbe_mac_82598EB: 682 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS); 683 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR); 684 for (i = 0; i < 8; i++) 685 regs_buff[833 + i] = 686 IXGBE_READ_REG(hw, IXGBE_RT2CR(i)); 687 for (i = 0; i < 8; i++) 688 regs_buff[841 + i] = 689 IXGBE_READ_REG(hw, IXGBE_RT2SR(i)); 690 for (i = 0; i < 8; i++) 691 regs_buff[849 + i] = 692 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i)); 693 for (i = 0; i < 8; i++) 694 regs_buff[857 + i] = 695 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i)); 696 break; 697 case ixgbe_mac_82599EB: 698 case ixgbe_mac_X540: 699 case ixgbe_mac_X550: 700 case ixgbe_mac_X550EM_x: 701 case ixgbe_mac_x550em_a: 702 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 703 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS); 704 for (i = 0; i < 8; i++) 705 regs_buff[833 + i] = 706 IXGBE_READ_REG(hw, IXGBE_RTRPT4C(i)); 707 for (i = 0; i < 8; i++) 708 regs_buff[841 + i] = 709 IXGBE_READ_REG(hw, IXGBE_RTRPT4S(i)); 710 for (i = 0; i < 8; i++) 711 regs_buff[849 + i] = 712 IXGBE_READ_REG(hw, IXGBE_RTTDT2C(i)); 713 for (i = 0; i < 8; i++) 714 regs_buff[857 + i] = 715 IXGBE_READ_REG(hw, IXGBE_RTTDT2S(i)); 716 break; 717 default: 718 break; 719 } 720 721 for (i = 0; i < 8; i++) 722 regs_buff[865 + i] = 723 IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); /* same as RTTPT2C */ 724 for (i = 0; i < 8; i++) 725 regs_buff[873 + i] = 726 IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); /* same as RTTPT2S */ 727 728 /* Statistics */ 729 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs); 730 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc); 731 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc); 732 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc); 733 for (i = 0; i < 8; i++) 734 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]); 735 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc); 736 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc); 737 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec); 738 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc); 739 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc); 740 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc); 741 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc); 742 for (i = 0; i < 8; i++) 743 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]); 744 for (i = 0; i < 8; i++) 745 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]); 746 for (i = 0; i < 8; i++) 747 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]); 748 for (i = 0; i < 8; i++) 749 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]); 750 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64); 751 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127); 752 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255); 753 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511); 754 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023); 755 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522); 756 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc); 757 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc); 758 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc); 759 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc); 760 regs_buff[942] = (u32)IXGBE_GET_STAT(adapter, gorc); 761 regs_buff[943] = (u32)(IXGBE_GET_STAT(adapter, gorc) >> 32); 762 regs_buff[944] = (u32)IXGBE_GET_STAT(adapter, gotc); 763 regs_buff[945] = (u32)(IXGBE_GET_STAT(adapter, gotc) >> 32); 764 for (i = 0; i < 8; i++) 765 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]); 766 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc); 767 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc); 768 regs_buff[956] = IXGBE_GET_STAT(adapter, roc); 769 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc); 770 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc); 771 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc); 772 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc); 773 regs_buff[961] = (u32)IXGBE_GET_STAT(adapter, tor); 774 regs_buff[962] = (u32)(IXGBE_GET_STAT(adapter, tor) >> 32); 775 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr); 776 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt); 777 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64); 778 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127); 779 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255); 780 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511); 781 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023); 782 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522); 783 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc); 784 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc); 785 regs_buff[973] = IXGBE_GET_STAT(adapter, xec); 786 for (i = 0; i < 16; i++) 787 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]); 788 for (i = 0; i < 16; i++) 789 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]); 790 for (i = 0; i < 16; i++) 791 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]); 792 for (i = 0; i < 16; i++) 793 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]); 794 795 /* MAC */ 796 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG); 797 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 798 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 799 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0); 800 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1); 801 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 802 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 803 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP); 804 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP); 805 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0); 806 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1); 807 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP); 808 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA); 809 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE); 810 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD); 811 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS); 812 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA); 813 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD); 814 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD); 815 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD); 816 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG); 817 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1); 818 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2); 819 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS); 820 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC); 821 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS); 822 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC); 823 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS); 824 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 825 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3); 826 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1); 827 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2); 828 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 829 830 /* Diagnostic */ 831 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL); 832 for (i = 0; i < 8; i++) 833 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i)); 834 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN); 835 for (i = 0; i < 4; i++) 836 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i)); 837 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE); 838 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL); 839 for (i = 0; i < 8; i++) 840 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i)); 841 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN); 842 for (i = 0; i < 4; i++) 843 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i)); 844 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE); 845 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL); 846 for (i = 0; i < 4; i++) 847 regs_buff[1102 + i] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA(i)); 848 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL); 849 for (i = 0; i < 4; i++) 850 regs_buff[1107 + i] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA(i)); 851 for (i = 0; i < 8; i++) 852 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i)); 853 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL); 854 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1); 855 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2); 856 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1); 857 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2); 858 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS); 859 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL); 860 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC); 861 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC); 862 863 /* 82599 X540 specific registers */ 864 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN); 865 866 /* 82599 X540 specific DCB registers */ 867 regs_buff[1129] = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 868 regs_buff[1130] = IXGBE_READ_REG(hw, IXGBE_RTTUP2TC); 869 for (i = 0; i < 4; i++) 870 regs_buff[1131 + i] = IXGBE_READ_REG(hw, IXGBE_TXLLQ(i)); 871 regs_buff[1135] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRM); 872 /* same as RTTQCNRM */ 873 regs_buff[1136] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRD); 874 /* same as RTTQCNRR */ 875 876 /* X540 specific DCB registers */ 877 regs_buff[1137] = IXGBE_READ_REG(hw, IXGBE_RTTQCNCR); 878 regs_buff[1138] = IXGBE_READ_REG(hw, IXGBE_RTTQCNTG); 879 880 /* Security config registers */ 881 regs_buff[1139] = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 882 regs_buff[1140] = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT); 883 regs_buff[1141] = IXGBE_READ_REG(hw, IXGBE_SECTXBUFFAF); 884 regs_buff[1142] = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 885 regs_buff[1143] = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 886 regs_buff[1144] = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 887 } 888 889 static int ixgbe_get_eeprom_len(struct net_device *netdev) 890 { 891 struct ixgbe_adapter *adapter = netdev_priv(netdev); 892 return adapter->hw.eeprom.word_size * 2; 893 } 894 895 static int ixgbe_get_eeprom(struct net_device *netdev, 896 struct ethtool_eeprom *eeprom, u8 *bytes) 897 { 898 struct ixgbe_adapter *adapter = netdev_priv(netdev); 899 struct ixgbe_hw *hw = &adapter->hw; 900 u16 *eeprom_buff; 901 int first_word, last_word, eeprom_len; 902 int ret_val = 0; 903 u16 i; 904 905 if (eeprom->len == 0) 906 return -EINVAL; 907 908 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 909 910 first_word = eeprom->offset >> 1; 911 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 912 eeprom_len = last_word - first_word + 1; 913 914 eeprom_buff = kmalloc_array(eeprom_len, sizeof(u16), GFP_KERNEL); 915 if (!eeprom_buff) 916 return -ENOMEM; 917 918 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len, 919 eeprom_buff); 920 921 /* Device's eeprom is always little-endian, word addressable */ 922 for (i = 0; i < eeprom_len; i++) 923 le16_to_cpus(&eeprom_buff[i]); 924 925 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len); 926 kfree(eeprom_buff); 927 928 return ret_val; 929 } 930 931 static int ixgbe_set_eeprom(struct net_device *netdev, 932 struct ethtool_eeprom *eeprom, u8 *bytes) 933 { 934 struct ixgbe_adapter *adapter = netdev_priv(netdev); 935 struct ixgbe_hw *hw = &adapter->hw; 936 u16 *eeprom_buff; 937 void *ptr; 938 int max_len, first_word, last_word, ret_val = 0; 939 u16 i; 940 941 if (eeprom->len == 0) 942 return -EINVAL; 943 944 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 945 return -EINVAL; 946 947 max_len = hw->eeprom.word_size * 2; 948 949 first_word = eeprom->offset >> 1; 950 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 951 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 952 if (!eeprom_buff) 953 return -ENOMEM; 954 955 ptr = eeprom_buff; 956 957 if (eeprom->offset & 1) { 958 /* 959 * need read/modify/write of first changed EEPROM word 960 * only the second byte of the word is being modified 961 */ 962 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]); 963 if (ret_val) 964 goto err; 965 966 ptr++; 967 } 968 if ((eeprom->offset + eeprom->len) & 1) { 969 /* 970 * need read/modify/write of last changed EEPROM word 971 * only the first byte of the word is being modified 972 */ 973 ret_val = hw->eeprom.ops.read(hw, last_word, 974 &eeprom_buff[last_word - first_word]); 975 if (ret_val) 976 goto err; 977 } 978 979 /* Device's eeprom is always little-endian, word addressable */ 980 for (i = 0; i < last_word - first_word + 1; i++) 981 le16_to_cpus(&eeprom_buff[i]); 982 983 memcpy(ptr, bytes, eeprom->len); 984 985 for (i = 0; i < last_word - first_word + 1; i++) 986 cpu_to_le16s(&eeprom_buff[i]); 987 988 ret_val = hw->eeprom.ops.write_buffer(hw, first_word, 989 last_word - first_word + 1, 990 eeprom_buff); 991 992 /* Update the checksum */ 993 if (ret_val == 0) 994 hw->eeprom.ops.update_checksum(hw); 995 996 err: 997 kfree(eeprom_buff); 998 return ret_val; 999 } 1000 1001 static void ixgbe_get_drvinfo(struct net_device *netdev, 1002 struct ethtool_drvinfo *drvinfo) 1003 { 1004 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1005 1006 strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver)); 1007 1008 strlcpy(drvinfo->fw_version, adapter->eeprom_id, 1009 sizeof(drvinfo->fw_version)); 1010 1011 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 1012 sizeof(drvinfo->bus_info)); 1013 1014 drvinfo->n_priv_flags = IXGBE_PRIV_FLAGS_STR_LEN; 1015 } 1016 1017 static void ixgbe_get_ringparam(struct net_device *netdev, 1018 struct ethtool_ringparam *ring) 1019 { 1020 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1021 struct ixgbe_ring *tx_ring = adapter->tx_ring[0]; 1022 struct ixgbe_ring *rx_ring = adapter->rx_ring[0]; 1023 1024 ring->rx_max_pending = IXGBE_MAX_RXD; 1025 ring->tx_max_pending = IXGBE_MAX_TXD; 1026 ring->rx_pending = rx_ring->count; 1027 ring->tx_pending = tx_ring->count; 1028 } 1029 1030 static int ixgbe_set_ringparam(struct net_device *netdev, 1031 struct ethtool_ringparam *ring) 1032 { 1033 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1034 struct ixgbe_ring *temp_ring; 1035 int i, j, err = 0; 1036 u32 new_rx_count, new_tx_count; 1037 1038 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 1039 return -EINVAL; 1040 1041 new_tx_count = clamp_t(u32, ring->tx_pending, 1042 IXGBE_MIN_TXD, IXGBE_MAX_TXD); 1043 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE); 1044 1045 new_rx_count = clamp_t(u32, ring->rx_pending, 1046 IXGBE_MIN_RXD, IXGBE_MAX_RXD); 1047 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE); 1048 1049 if ((new_tx_count == adapter->tx_ring_count) && 1050 (new_rx_count == adapter->rx_ring_count)) { 1051 /* nothing to do */ 1052 return 0; 1053 } 1054 1055 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 1056 usleep_range(1000, 2000); 1057 1058 if (!netif_running(adapter->netdev)) { 1059 for (i = 0; i < adapter->num_tx_queues; i++) 1060 adapter->tx_ring[i]->count = new_tx_count; 1061 for (i = 0; i < adapter->num_xdp_queues; i++) 1062 adapter->xdp_ring[i]->count = new_tx_count; 1063 for (i = 0; i < adapter->num_rx_queues; i++) 1064 adapter->rx_ring[i]->count = new_rx_count; 1065 adapter->tx_ring_count = new_tx_count; 1066 adapter->xdp_ring_count = new_tx_count; 1067 adapter->rx_ring_count = new_rx_count; 1068 goto clear_reset; 1069 } 1070 1071 /* allocate temporary buffer to store rings in */ 1072 i = max_t(int, adapter->num_tx_queues + adapter->num_xdp_queues, 1073 adapter->num_rx_queues); 1074 temp_ring = vmalloc(array_size(i, sizeof(struct ixgbe_ring))); 1075 1076 if (!temp_ring) { 1077 err = -ENOMEM; 1078 goto clear_reset; 1079 } 1080 1081 ixgbe_down(adapter); 1082 1083 /* 1084 * Setup new Tx resources and free the old Tx resources in that order. 1085 * We can then assign the new resources to the rings via a memcpy. 1086 * The advantage to this approach is that we are guaranteed to still 1087 * have resources even in the case of an allocation failure. 1088 */ 1089 if (new_tx_count != adapter->tx_ring_count) { 1090 for (i = 0; i < adapter->num_tx_queues; i++) { 1091 memcpy(&temp_ring[i], adapter->tx_ring[i], 1092 sizeof(struct ixgbe_ring)); 1093 1094 temp_ring[i].count = new_tx_count; 1095 err = ixgbe_setup_tx_resources(&temp_ring[i]); 1096 if (err) { 1097 while (i) { 1098 i--; 1099 ixgbe_free_tx_resources(&temp_ring[i]); 1100 } 1101 goto err_setup; 1102 } 1103 } 1104 1105 for (j = 0; j < adapter->num_xdp_queues; j++, i++) { 1106 memcpy(&temp_ring[i], adapter->xdp_ring[j], 1107 sizeof(struct ixgbe_ring)); 1108 1109 temp_ring[i].count = new_tx_count; 1110 err = ixgbe_setup_tx_resources(&temp_ring[i]); 1111 if (err) { 1112 while (i) { 1113 i--; 1114 ixgbe_free_tx_resources(&temp_ring[i]); 1115 } 1116 goto err_setup; 1117 } 1118 } 1119 1120 for (i = 0; i < adapter->num_tx_queues; i++) { 1121 ixgbe_free_tx_resources(adapter->tx_ring[i]); 1122 1123 memcpy(adapter->tx_ring[i], &temp_ring[i], 1124 sizeof(struct ixgbe_ring)); 1125 } 1126 for (j = 0; j < adapter->num_xdp_queues; j++, i++) { 1127 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 1128 1129 memcpy(adapter->xdp_ring[j], &temp_ring[i], 1130 sizeof(struct ixgbe_ring)); 1131 } 1132 1133 adapter->tx_ring_count = new_tx_count; 1134 } 1135 1136 /* Repeat the process for the Rx rings if needed */ 1137 if (new_rx_count != adapter->rx_ring_count) { 1138 for (i = 0; i < adapter->num_rx_queues; i++) { 1139 memcpy(&temp_ring[i], adapter->rx_ring[i], 1140 sizeof(struct ixgbe_ring)); 1141 1142 /* Clear copied XDP RX-queue info */ 1143 memset(&temp_ring[i].xdp_rxq, 0, 1144 sizeof(temp_ring[i].xdp_rxq)); 1145 1146 temp_ring[i].count = new_rx_count; 1147 err = ixgbe_setup_rx_resources(adapter, &temp_ring[i]); 1148 if (err) { 1149 while (i) { 1150 i--; 1151 ixgbe_free_rx_resources(&temp_ring[i]); 1152 } 1153 goto err_setup; 1154 } 1155 1156 } 1157 1158 for (i = 0; i < adapter->num_rx_queues; i++) { 1159 ixgbe_free_rx_resources(adapter->rx_ring[i]); 1160 1161 memcpy(adapter->rx_ring[i], &temp_ring[i], 1162 sizeof(struct ixgbe_ring)); 1163 } 1164 1165 adapter->rx_ring_count = new_rx_count; 1166 } 1167 1168 err_setup: 1169 ixgbe_up(adapter); 1170 vfree(temp_ring); 1171 clear_reset: 1172 clear_bit(__IXGBE_RESETTING, &adapter->state); 1173 return err; 1174 } 1175 1176 static int ixgbe_get_sset_count(struct net_device *netdev, int sset) 1177 { 1178 switch (sset) { 1179 case ETH_SS_TEST: 1180 return IXGBE_TEST_LEN; 1181 case ETH_SS_STATS: 1182 return IXGBE_STATS_LEN; 1183 case ETH_SS_PRIV_FLAGS: 1184 return IXGBE_PRIV_FLAGS_STR_LEN; 1185 default: 1186 return -EOPNOTSUPP; 1187 } 1188 } 1189 1190 static void ixgbe_get_ethtool_stats(struct net_device *netdev, 1191 struct ethtool_stats *stats, u64 *data) 1192 { 1193 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1194 struct rtnl_link_stats64 temp; 1195 const struct rtnl_link_stats64 *net_stats; 1196 unsigned int start; 1197 struct ixgbe_ring *ring; 1198 int i, j; 1199 char *p = NULL; 1200 1201 ixgbe_update_stats(adapter); 1202 net_stats = dev_get_stats(netdev, &temp); 1203 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 1204 switch (ixgbe_gstrings_stats[i].type) { 1205 case NETDEV_STATS: 1206 p = (char *) net_stats + 1207 ixgbe_gstrings_stats[i].stat_offset; 1208 break; 1209 case IXGBE_STATS: 1210 p = (char *) adapter + 1211 ixgbe_gstrings_stats[i].stat_offset; 1212 break; 1213 default: 1214 data[i] = 0; 1215 continue; 1216 } 1217 1218 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat == 1219 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 1220 } 1221 for (j = 0; j < netdev->num_tx_queues; j++) { 1222 ring = adapter->tx_ring[j]; 1223 if (!ring) { 1224 data[i] = 0; 1225 data[i+1] = 0; 1226 i += 2; 1227 continue; 1228 } 1229 1230 do { 1231 start = u64_stats_fetch_begin_irq(&ring->syncp); 1232 data[i] = ring->stats.packets; 1233 data[i+1] = ring->stats.bytes; 1234 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1235 i += 2; 1236 } 1237 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) { 1238 ring = adapter->rx_ring[j]; 1239 if (!ring) { 1240 data[i] = 0; 1241 data[i+1] = 0; 1242 i += 2; 1243 continue; 1244 } 1245 1246 do { 1247 start = u64_stats_fetch_begin_irq(&ring->syncp); 1248 data[i] = ring->stats.packets; 1249 data[i+1] = ring->stats.bytes; 1250 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1251 i += 2; 1252 } 1253 1254 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) { 1255 data[i++] = adapter->stats.pxontxc[j]; 1256 data[i++] = adapter->stats.pxofftxc[j]; 1257 } 1258 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) { 1259 data[i++] = adapter->stats.pxonrxc[j]; 1260 data[i++] = adapter->stats.pxoffrxc[j]; 1261 } 1262 } 1263 1264 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset, 1265 u8 *data) 1266 { 1267 char *p = (char *)data; 1268 unsigned int i; 1269 1270 switch (stringset) { 1271 case ETH_SS_TEST: 1272 for (i = 0; i < IXGBE_TEST_LEN; i++) { 1273 memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN); 1274 data += ETH_GSTRING_LEN; 1275 } 1276 break; 1277 case ETH_SS_STATS: 1278 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 1279 memcpy(p, ixgbe_gstrings_stats[i].stat_string, 1280 ETH_GSTRING_LEN); 1281 p += ETH_GSTRING_LEN; 1282 } 1283 for (i = 0; i < netdev->num_tx_queues; i++) { 1284 sprintf(p, "tx_queue_%u_packets", i); 1285 p += ETH_GSTRING_LEN; 1286 sprintf(p, "tx_queue_%u_bytes", i); 1287 p += ETH_GSTRING_LEN; 1288 } 1289 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) { 1290 sprintf(p, "rx_queue_%u_packets", i); 1291 p += ETH_GSTRING_LEN; 1292 sprintf(p, "rx_queue_%u_bytes", i); 1293 p += ETH_GSTRING_LEN; 1294 } 1295 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 1296 sprintf(p, "tx_pb_%u_pxon", i); 1297 p += ETH_GSTRING_LEN; 1298 sprintf(p, "tx_pb_%u_pxoff", i); 1299 p += ETH_GSTRING_LEN; 1300 } 1301 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 1302 sprintf(p, "rx_pb_%u_pxon", i); 1303 p += ETH_GSTRING_LEN; 1304 sprintf(p, "rx_pb_%u_pxoff", i); 1305 p += ETH_GSTRING_LEN; 1306 } 1307 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */ 1308 break; 1309 case ETH_SS_PRIV_FLAGS: 1310 memcpy(data, ixgbe_priv_flags_strings, 1311 IXGBE_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN); 1312 } 1313 } 1314 1315 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data) 1316 { 1317 struct ixgbe_hw *hw = &adapter->hw; 1318 bool link_up; 1319 u32 link_speed = 0; 1320 1321 if (ixgbe_removed(hw->hw_addr)) { 1322 *data = 1; 1323 return 1; 1324 } 1325 *data = 0; 1326 1327 hw->mac.ops.check_link(hw, &link_speed, &link_up, true); 1328 if (link_up) 1329 return *data; 1330 else 1331 *data = 1; 1332 return *data; 1333 } 1334 1335 /* ethtool register test data */ 1336 struct ixgbe_reg_test { 1337 u16 reg; 1338 u8 array_len; 1339 u8 test_type; 1340 u32 mask; 1341 u32 write; 1342 }; 1343 1344 /* In the hardware, registers are laid out either singly, in arrays 1345 * spaced 0x40 bytes apart, or in contiguous tables. We assume 1346 * most tests take place on arrays or single registers (handled 1347 * as a single-element array) and special-case the tables. 1348 * Table tests are always pattern tests. 1349 * 1350 * We also make provision for some required setup steps by specifying 1351 * registers to be written without any read-back testing. 1352 */ 1353 1354 #define PATTERN_TEST 1 1355 #define SET_READ_TEST 2 1356 #define WRITE_NO_TEST 3 1357 #define TABLE32_TEST 4 1358 #define TABLE64_TEST_LO 5 1359 #define TABLE64_TEST_HI 6 1360 1361 /* default 82599 register test */ 1362 static const struct ixgbe_reg_test reg_test_82599[] = { 1363 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1364 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1365 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1366 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1367 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 }, 1368 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1369 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1370 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1371 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1372 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1373 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1374 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1375 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1376 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1377 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 }, 1378 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 }, 1379 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1380 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF }, 1381 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1382 { .reg = 0 } 1383 }; 1384 1385 /* default 82598 register test */ 1386 static const struct ixgbe_reg_test reg_test_82598[] = { 1387 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1388 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1389 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1390 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1391 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1392 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1393 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1394 /* Enable all four RX queues before testing. */ 1395 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1396 /* RDH is read-only for 82598, only test RDT. */ 1397 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1398 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1399 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1400 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1401 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF }, 1402 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1403 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1404 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1405 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 }, 1406 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 }, 1407 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1408 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF }, 1409 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1410 { .reg = 0 } 1411 }; 1412 1413 static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg, 1414 u32 mask, u32 write) 1415 { 1416 u32 pat, val, before; 1417 static const u32 test_pattern[] = { 1418 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1419 1420 if (ixgbe_removed(adapter->hw.hw_addr)) { 1421 *data = 1; 1422 return true; 1423 } 1424 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) { 1425 before = ixgbe_read_reg(&adapter->hw, reg); 1426 ixgbe_write_reg(&adapter->hw, reg, test_pattern[pat] & write); 1427 val = ixgbe_read_reg(&adapter->hw, reg); 1428 if (val != (test_pattern[pat] & write & mask)) { 1429 e_err(drv, "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n", 1430 reg, val, (test_pattern[pat] & write & mask)); 1431 *data = reg; 1432 ixgbe_write_reg(&adapter->hw, reg, before); 1433 return true; 1434 } 1435 ixgbe_write_reg(&adapter->hw, reg, before); 1436 } 1437 return false; 1438 } 1439 1440 static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg, 1441 u32 mask, u32 write) 1442 { 1443 u32 val, before; 1444 1445 if (ixgbe_removed(adapter->hw.hw_addr)) { 1446 *data = 1; 1447 return true; 1448 } 1449 before = ixgbe_read_reg(&adapter->hw, reg); 1450 ixgbe_write_reg(&adapter->hw, reg, write & mask); 1451 val = ixgbe_read_reg(&adapter->hw, reg); 1452 if ((write & mask) != (val & mask)) { 1453 e_err(drv, "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", 1454 reg, (val & mask), (write & mask)); 1455 *data = reg; 1456 ixgbe_write_reg(&adapter->hw, reg, before); 1457 return true; 1458 } 1459 ixgbe_write_reg(&adapter->hw, reg, before); 1460 return false; 1461 } 1462 1463 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data) 1464 { 1465 const struct ixgbe_reg_test *test; 1466 u32 value, before, after; 1467 u32 i, toggle; 1468 1469 if (ixgbe_removed(adapter->hw.hw_addr)) { 1470 e_err(drv, "Adapter removed - register test blocked\n"); 1471 *data = 1; 1472 return 1; 1473 } 1474 switch (adapter->hw.mac.type) { 1475 case ixgbe_mac_82598EB: 1476 toggle = 0x7FFFF3FF; 1477 test = reg_test_82598; 1478 break; 1479 case ixgbe_mac_82599EB: 1480 case ixgbe_mac_X540: 1481 case ixgbe_mac_X550: 1482 case ixgbe_mac_X550EM_x: 1483 case ixgbe_mac_x550em_a: 1484 toggle = 0x7FFFF30F; 1485 test = reg_test_82599; 1486 break; 1487 default: 1488 *data = 1; 1489 return 1; 1490 } 1491 1492 /* 1493 * Because the status register is such a special case, 1494 * we handle it separately from the rest of the register 1495 * tests. Some bits are read-only, some toggle, and some 1496 * are writeable on newer MACs. 1497 */ 1498 before = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS); 1499 value = (ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle); 1500 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, toggle); 1501 after = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle; 1502 if (value != after) { 1503 e_err(drv, "failed STATUS register test got: 0x%08X expected: 0x%08X\n", 1504 after, value); 1505 *data = 1; 1506 return 1; 1507 } 1508 /* restore previous status */ 1509 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, before); 1510 1511 /* 1512 * Perform the remainder of the register test, looping through 1513 * the test table until we either fail or reach the null entry. 1514 */ 1515 while (test->reg) { 1516 for (i = 0; i < test->array_len; i++) { 1517 bool b = false; 1518 1519 switch (test->test_type) { 1520 case PATTERN_TEST: 1521 b = reg_pattern_test(adapter, data, 1522 test->reg + (i * 0x40), 1523 test->mask, 1524 test->write); 1525 break; 1526 case SET_READ_TEST: 1527 b = reg_set_and_check(adapter, data, 1528 test->reg + (i * 0x40), 1529 test->mask, 1530 test->write); 1531 break; 1532 case WRITE_NO_TEST: 1533 ixgbe_write_reg(&adapter->hw, 1534 test->reg + (i * 0x40), 1535 test->write); 1536 break; 1537 case TABLE32_TEST: 1538 b = reg_pattern_test(adapter, data, 1539 test->reg + (i * 4), 1540 test->mask, 1541 test->write); 1542 break; 1543 case TABLE64_TEST_LO: 1544 b = reg_pattern_test(adapter, data, 1545 test->reg + (i * 8), 1546 test->mask, 1547 test->write); 1548 break; 1549 case TABLE64_TEST_HI: 1550 b = reg_pattern_test(adapter, data, 1551 (test->reg + 4) + (i * 8), 1552 test->mask, 1553 test->write); 1554 break; 1555 } 1556 if (b) 1557 return 1; 1558 } 1559 test++; 1560 } 1561 1562 *data = 0; 1563 return 0; 1564 } 1565 1566 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data) 1567 { 1568 struct ixgbe_hw *hw = &adapter->hw; 1569 if (hw->eeprom.ops.validate_checksum(hw, NULL)) 1570 *data = 1; 1571 else 1572 *data = 0; 1573 return *data; 1574 } 1575 1576 static irqreturn_t ixgbe_test_intr(int irq, void *data) 1577 { 1578 struct net_device *netdev = (struct net_device *) data; 1579 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1580 1581 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR); 1582 1583 return IRQ_HANDLED; 1584 } 1585 1586 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data) 1587 { 1588 struct net_device *netdev = adapter->netdev; 1589 u32 mask, i = 0, shared_int = true; 1590 u32 irq = adapter->pdev->irq; 1591 1592 *data = 0; 1593 1594 /* Hook up test interrupt handler just for this test */ 1595 if (adapter->msix_entries) { 1596 /* NOTE: we don't test MSI-X interrupts here, yet */ 1597 return 0; 1598 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { 1599 shared_int = false; 1600 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name, 1601 netdev)) { 1602 *data = 1; 1603 return -1; 1604 } 1605 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED, 1606 netdev->name, netdev)) { 1607 shared_int = false; 1608 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED, 1609 netdev->name, netdev)) { 1610 *data = 1; 1611 return -1; 1612 } 1613 e_info(hw, "testing %s interrupt\n", shared_int ? 1614 "shared" : "unshared"); 1615 1616 /* Disable all the interrupts */ 1617 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1618 IXGBE_WRITE_FLUSH(&adapter->hw); 1619 usleep_range(10000, 20000); 1620 1621 /* Test each interrupt */ 1622 for (; i < 10; i++) { 1623 /* Interrupt to test */ 1624 mask = BIT(i); 1625 1626 if (!shared_int) { 1627 /* 1628 * Disable the interrupts to be reported in 1629 * the cause register and then force the same 1630 * interrupt and see if one gets posted. If 1631 * an interrupt was posted to the bus, the 1632 * test failed. 1633 */ 1634 adapter->test_icr = 0; 1635 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 1636 ~mask & 0x00007FFF); 1637 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1638 ~mask & 0x00007FFF); 1639 IXGBE_WRITE_FLUSH(&adapter->hw); 1640 usleep_range(10000, 20000); 1641 1642 if (adapter->test_icr & mask) { 1643 *data = 3; 1644 break; 1645 } 1646 } 1647 1648 /* 1649 * Enable the interrupt to be reported in the cause 1650 * register and then force the same interrupt and see 1651 * if one gets posted. If an interrupt was not posted 1652 * to the bus, the test failed. 1653 */ 1654 adapter->test_icr = 0; 1655 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 1656 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 1657 IXGBE_WRITE_FLUSH(&adapter->hw); 1658 usleep_range(10000, 20000); 1659 1660 if (!(adapter->test_icr & mask)) { 1661 *data = 4; 1662 break; 1663 } 1664 1665 if (!shared_int) { 1666 /* 1667 * Disable the other interrupts to be reported in 1668 * the cause register and then force the other 1669 * interrupts and see if any get posted. If 1670 * an interrupt was posted to the bus, the 1671 * test failed. 1672 */ 1673 adapter->test_icr = 0; 1674 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 1675 ~mask & 0x00007FFF); 1676 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1677 ~mask & 0x00007FFF); 1678 IXGBE_WRITE_FLUSH(&adapter->hw); 1679 usleep_range(10000, 20000); 1680 1681 if (adapter->test_icr) { 1682 *data = 5; 1683 break; 1684 } 1685 } 1686 } 1687 1688 /* Disable all the interrupts */ 1689 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1690 IXGBE_WRITE_FLUSH(&adapter->hw); 1691 usleep_range(10000, 20000); 1692 1693 /* Unhook test interrupt handler */ 1694 free_irq(irq, netdev); 1695 1696 return *data; 1697 } 1698 1699 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter) 1700 { 1701 /* Shut down the DMA engines now so they can be reinitialized later, 1702 * since the test rings and normally used rings should overlap on 1703 * queue 0 we can just use the standard disable Rx/Tx calls and they 1704 * will take care of disabling the test rings for us. 1705 */ 1706 1707 /* first Rx */ 1708 ixgbe_disable_rx(adapter); 1709 1710 /* now Tx */ 1711 ixgbe_disable_tx(adapter); 1712 1713 ixgbe_reset(adapter); 1714 1715 ixgbe_free_tx_resources(&adapter->test_tx_ring); 1716 ixgbe_free_rx_resources(&adapter->test_rx_ring); 1717 } 1718 1719 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter) 1720 { 1721 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1722 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1723 struct ixgbe_hw *hw = &adapter->hw; 1724 u32 rctl, reg_data; 1725 int ret_val; 1726 int err; 1727 1728 /* Setup Tx descriptor ring and Tx buffers */ 1729 tx_ring->count = IXGBE_DEFAULT_TXD; 1730 tx_ring->queue_index = 0; 1731 tx_ring->dev = &adapter->pdev->dev; 1732 tx_ring->netdev = adapter->netdev; 1733 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx; 1734 1735 err = ixgbe_setup_tx_resources(tx_ring); 1736 if (err) 1737 return 1; 1738 1739 switch (adapter->hw.mac.type) { 1740 case ixgbe_mac_82599EB: 1741 case ixgbe_mac_X540: 1742 case ixgbe_mac_X550: 1743 case ixgbe_mac_X550EM_x: 1744 case ixgbe_mac_x550em_a: 1745 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL); 1746 reg_data |= IXGBE_DMATXCTL_TE; 1747 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data); 1748 break; 1749 default: 1750 break; 1751 } 1752 1753 ixgbe_configure_tx_ring(adapter, tx_ring); 1754 1755 /* Setup Rx Descriptor ring and Rx buffers */ 1756 rx_ring->count = IXGBE_DEFAULT_RXD; 1757 rx_ring->queue_index = 0; 1758 rx_ring->dev = &adapter->pdev->dev; 1759 rx_ring->netdev = adapter->netdev; 1760 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx; 1761 1762 err = ixgbe_setup_rx_resources(adapter, rx_ring); 1763 if (err) { 1764 ret_val = 4; 1765 goto err_nomem; 1766 } 1767 1768 hw->mac.ops.disable_rx(hw); 1769 1770 ixgbe_configure_rx_ring(adapter, rx_ring); 1771 1772 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL); 1773 rctl |= IXGBE_RXCTRL_DMBYPS; 1774 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl); 1775 1776 hw->mac.ops.enable_rx(hw); 1777 1778 return 0; 1779 1780 err_nomem: 1781 ixgbe_free_desc_rings(adapter); 1782 return ret_val; 1783 } 1784 1785 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter) 1786 { 1787 struct ixgbe_hw *hw = &adapter->hw; 1788 u32 reg_data; 1789 1790 1791 /* Setup MAC loopback */ 1792 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0); 1793 reg_data |= IXGBE_HLREG0_LPBK; 1794 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data); 1795 1796 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1797 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE; 1798 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data); 1799 1800 /* X540 and X550 needs to set the MACC.FLU bit to force link up */ 1801 switch (adapter->hw.mac.type) { 1802 case ixgbe_mac_X540: 1803 case ixgbe_mac_X550: 1804 case ixgbe_mac_X550EM_x: 1805 case ixgbe_mac_x550em_a: 1806 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC); 1807 reg_data |= IXGBE_MACC_FLU; 1808 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data); 1809 break; 1810 default: 1811 if (hw->mac.orig_autoc) { 1812 reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU; 1813 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data); 1814 } else { 1815 return 10; 1816 } 1817 } 1818 IXGBE_WRITE_FLUSH(hw); 1819 usleep_range(10000, 20000); 1820 1821 /* Disable Atlas Tx lanes; re-enabled in reset path */ 1822 if (hw->mac.type == ixgbe_mac_82598EB) { 1823 u8 atlas; 1824 1825 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas); 1826 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN; 1827 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas); 1828 1829 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas); 1830 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 1831 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas); 1832 1833 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas); 1834 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 1835 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas); 1836 1837 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas); 1838 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 1839 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas); 1840 } 1841 1842 return 0; 1843 } 1844 1845 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter) 1846 { 1847 u32 reg_data; 1848 1849 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0); 1850 reg_data &= ~IXGBE_HLREG0_LPBK; 1851 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data); 1852 } 1853 1854 static void ixgbe_create_lbtest_frame(struct sk_buff *skb, 1855 unsigned int frame_size) 1856 { 1857 memset(skb->data, 0xFF, frame_size); 1858 frame_size >>= 1; 1859 memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1); 1860 memset(&skb->data[frame_size + 10], 0xBE, 1); 1861 memset(&skb->data[frame_size + 12], 0xAF, 1); 1862 } 1863 1864 static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer, 1865 unsigned int frame_size) 1866 { 1867 unsigned char *data; 1868 bool match = true; 1869 1870 frame_size >>= 1; 1871 1872 data = kmap(rx_buffer->page) + rx_buffer->page_offset; 1873 1874 if (data[3] != 0xFF || 1875 data[frame_size + 10] != 0xBE || 1876 data[frame_size + 12] != 0xAF) 1877 match = false; 1878 1879 kunmap(rx_buffer->page); 1880 1881 return match; 1882 } 1883 1884 static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring, 1885 struct ixgbe_ring *tx_ring, 1886 unsigned int size) 1887 { 1888 union ixgbe_adv_rx_desc *rx_desc; 1889 u16 rx_ntc, tx_ntc, count = 0; 1890 1891 /* initialize next to clean and descriptor values */ 1892 rx_ntc = rx_ring->next_to_clean; 1893 tx_ntc = tx_ring->next_to_clean; 1894 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc); 1895 1896 while (tx_ntc != tx_ring->next_to_use) { 1897 union ixgbe_adv_tx_desc *tx_desc; 1898 struct ixgbe_tx_buffer *tx_buffer; 1899 1900 tx_desc = IXGBE_TX_DESC(tx_ring, tx_ntc); 1901 1902 /* if DD is not set transmit has not completed */ 1903 if (!(tx_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1904 return count; 1905 1906 /* unmap buffer on Tx side */ 1907 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc]; 1908 1909 /* Free all the Tx ring sk_buffs */ 1910 dev_kfree_skb_any(tx_buffer->skb); 1911 1912 /* unmap skb header data */ 1913 dma_unmap_single(tx_ring->dev, 1914 dma_unmap_addr(tx_buffer, dma), 1915 dma_unmap_len(tx_buffer, len), 1916 DMA_TO_DEVICE); 1917 dma_unmap_len_set(tx_buffer, len, 0); 1918 1919 /* increment Tx next to clean counter */ 1920 tx_ntc++; 1921 if (tx_ntc == tx_ring->count) 1922 tx_ntc = 0; 1923 } 1924 1925 while (rx_desc->wb.upper.length) { 1926 struct ixgbe_rx_buffer *rx_buffer; 1927 1928 /* check Rx buffer */ 1929 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc]; 1930 1931 /* sync Rx buffer for CPU read */ 1932 dma_sync_single_for_cpu(rx_ring->dev, 1933 rx_buffer->dma, 1934 ixgbe_rx_bufsz(rx_ring), 1935 DMA_FROM_DEVICE); 1936 1937 /* verify contents of skb */ 1938 if (ixgbe_check_lbtest_frame(rx_buffer, size)) 1939 count++; 1940 else 1941 break; 1942 1943 /* sync Rx buffer for device write */ 1944 dma_sync_single_for_device(rx_ring->dev, 1945 rx_buffer->dma, 1946 ixgbe_rx_bufsz(rx_ring), 1947 DMA_FROM_DEVICE); 1948 1949 /* increment Rx next to clean counter */ 1950 rx_ntc++; 1951 if (rx_ntc == rx_ring->count) 1952 rx_ntc = 0; 1953 1954 /* fetch next descriptor */ 1955 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc); 1956 } 1957 1958 netdev_tx_reset_queue(txring_txq(tx_ring)); 1959 1960 /* re-map buffers to ring, store next to clean values */ 1961 ixgbe_alloc_rx_buffers(rx_ring, count); 1962 rx_ring->next_to_clean = rx_ntc; 1963 tx_ring->next_to_clean = tx_ntc; 1964 1965 return count; 1966 } 1967 1968 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter) 1969 { 1970 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1971 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1972 int i, j, lc, good_cnt, ret_val = 0; 1973 unsigned int size = 1024; 1974 netdev_tx_t tx_ret_val; 1975 struct sk_buff *skb; 1976 u32 flags_orig = adapter->flags; 1977 1978 /* DCB can modify the frames on Tx */ 1979 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 1980 1981 /* allocate test skb */ 1982 skb = alloc_skb(size, GFP_KERNEL); 1983 if (!skb) 1984 return 11; 1985 1986 /* place data into test skb */ 1987 ixgbe_create_lbtest_frame(skb, size); 1988 skb_put(skb, size); 1989 1990 /* 1991 * Calculate the loop count based on the largest descriptor ring 1992 * The idea is to wrap the largest ring a number of times using 64 1993 * send/receive pairs during each loop 1994 */ 1995 1996 if (rx_ring->count <= tx_ring->count) 1997 lc = ((tx_ring->count / 64) * 2) + 1; 1998 else 1999 lc = ((rx_ring->count / 64) * 2) + 1; 2000 2001 for (j = 0; j <= lc; j++) { 2002 /* reset count of good packets */ 2003 good_cnt = 0; 2004 2005 /* place 64 packets on the transmit queue*/ 2006 for (i = 0; i < 64; i++) { 2007 skb_get(skb); 2008 tx_ret_val = ixgbe_xmit_frame_ring(skb, 2009 adapter, 2010 tx_ring); 2011 if (tx_ret_val == NETDEV_TX_OK) 2012 good_cnt++; 2013 } 2014 2015 if (good_cnt != 64) { 2016 ret_val = 12; 2017 break; 2018 } 2019 2020 /* allow 200 milliseconds for packets to go from Tx to Rx */ 2021 msleep(200); 2022 2023 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size); 2024 if (good_cnt != 64) { 2025 ret_val = 13; 2026 break; 2027 } 2028 } 2029 2030 /* free the original skb */ 2031 kfree_skb(skb); 2032 adapter->flags = flags_orig; 2033 2034 return ret_val; 2035 } 2036 2037 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data) 2038 { 2039 *data = ixgbe_setup_desc_rings(adapter); 2040 if (*data) 2041 goto out; 2042 *data = ixgbe_setup_loopback_test(adapter); 2043 if (*data) 2044 goto err_loopback; 2045 *data = ixgbe_run_loopback_test(adapter); 2046 ixgbe_loopback_cleanup(adapter); 2047 2048 err_loopback: 2049 ixgbe_free_desc_rings(adapter); 2050 out: 2051 return *data; 2052 } 2053 2054 static void ixgbe_diag_test(struct net_device *netdev, 2055 struct ethtool_test *eth_test, u64 *data) 2056 { 2057 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2058 bool if_running = netif_running(netdev); 2059 2060 if (ixgbe_removed(adapter->hw.hw_addr)) { 2061 e_err(hw, "Adapter removed - test blocked\n"); 2062 data[0] = 1; 2063 data[1] = 1; 2064 data[2] = 1; 2065 data[3] = 1; 2066 data[4] = 1; 2067 eth_test->flags |= ETH_TEST_FL_FAILED; 2068 return; 2069 } 2070 set_bit(__IXGBE_TESTING, &adapter->state); 2071 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 2072 struct ixgbe_hw *hw = &adapter->hw; 2073 2074 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 2075 int i; 2076 for (i = 0; i < adapter->num_vfs; i++) { 2077 if (adapter->vfinfo[i].clear_to_send) { 2078 netdev_warn(netdev, "offline diagnostic is not supported when VFs are present\n"); 2079 data[0] = 1; 2080 data[1] = 1; 2081 data[2] = 1; 2082 data[3] = 1; 2083 data[4] = 1; 2084 eth_test->flags |= ETH_TEST_FL_FAILED; 2085 clear_bit(__IXGBE_TESTING, 2086 &adapter->state); 2087 goto skip_ol_tests; 2088 } 2089 } 2090 } 2091 2092 /* Offline tests */ 2093 e_info(hw, "offline testing starting\n"); 2094 2095 /* Link test performed before hardware reset so autoneg doesn't 2096 * interfere with test result 2097 */ 2098 if (ixgbe_link_test(adapter, &data[4])) 2099 eth_test->flags |= ETH_TEST_FL_FAILED; 2100 2101 if (if_running) 2102 /* indicate we're in test mode */ 2103 ixgbe_close(netdev); 2104 else 2105 ixgbe_reset(adapter); 2106 2107 e_info(hw, "register testing starting\n"); 2108 if (ixgbe_reg_test(adapter, &data[0])) 2109 eth_test->flags |= ETH_TEST_FL_FAILED; 2110 2111 ixgbe_reset(adapter); 2112 e_info(hw, "eeprom testing starting\n"); 2113 if (ixgbe_eeprom_test(adapter, &data[1])) 2114 eth_test->flags |= ETH_TEST_FL_FAILED; 2115 2116 ixgbe_reset(adapter); 2117 e_info(hw, "interrupt testing starting\n"); 2118 if (ixgbe_intr_test(adapter, &data[2])) 2119 eth_test->flags |= ETH_TEST_FL_FAILED; 2120 2121 /* If SRIOV or VMDq is enabled then skip MAC 2122 * loopback diagnostic. */ 2123 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED | 2124 IXGBE_FLAG_VMDQ_ENABLED)) { 2125 e_info(hw, "Skip MAC loopback diagnostic in VT mode\n"); 2126 data[3] = 0; 2127 goto skip_loopback; 2128 } 2129 2130 ixgbe_reset(adapter); 2131 e_info(hw, "loopback testing starting\n"); 2132 if (ixgbe_loopback_test(adapter, &data[3])) 2133 eth_test->flags |= ETH_TEST_FL_FAILED; 2134 2135 skip_loopback: 2136 ixgbe_reset(adapter); 2137 2138 /* clear testing bit and return adapter to previous state */ 2139 clear_bit(__IXGBE_TESTING, &adapter->state); 2140 if (if_running) 2141 ixgbe_open(netdev); 2142 else if (hw->mac.ops.disable_tx_laser) 2143 hw->mac.ops.disable_tx_laser(hw); 2144 } else { 2145 e_info(hw, "online testing starting\n"); 2146 2147 /* Online tests */ 2148 if (ixgbe_link_test(adapter, &data[4])) 2149 eth_test->flags |= ETH_TEST_FL_FAILED; 2150 2151 /* Offline tests aren't run; pass by default */ 2152 data[0] = 0; 2153 data[1] = 0; 2154 data[2] = 0; 2155 data[3] = 0; 2156 2157 clear_bit(__IXGBE_TESTING, &adapter->state); 2158 } 2159 2160 skip_ol_tests: 2161 msleep_interruptible(4 * 1000); 2162 } 2163 2164 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter, 2165 struct ethtool_wolinfo *wol) 2166 { 2167 struct ixgbe_hw *hw = &adapter->hw; 2168 int retval = 0; 2169 2170 /* WOL not supported for all devices */ 2171 if (!ixgbe_wol_supported(adapter, hw->device_id, 2172 hw->subsystem_device_id)) { 2173 retval = 1; 2174 wol->supported = 0; 2175 } 2176 2177 return retval; 2178 } 2179 2180 static void ixgbe_get_wol(struct net_device *netdev, 2181 struct ethtool_wolinfo *wol) 2182 { 2183 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2184 2185 wol->supported = WAKE_UCAST | WAKE_MCAST | 2186 WAKE_BCAST | WAKE_MAGIC; 2187 wol->wolopts = 0; 2188 2189 if (ixgbe_wol_exclusion(adapter, wol) || 2190 !device_can_wakeup(&adapter->pdev->dev)) 2191 return; 2192 2193 if (adapter->wol & IXGBE_WUFC_EX) 2194 wol->wolopts |= WAKE_UCAST; 2195 if (adapter->wol & IXGBE_WUFC_MC) 2196 wol->wolopts |= WAKE_MCAST; 2197 if (adapter->wol & IXGBE_WUFC_BC) 2198 wol->wolopts |= WAKE_BCAST; 2199 if (adapter->wol & IXGBE_WUFC_MAG) 2200 wol->wolopts |= WAKE_MAGIC; 2201 } 2202 2203 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2204 { 2205 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2206 2207 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE | 2208 WAKE_FILTER)) 2209 return -EOPNOTSUPP; 2210 2211 if (ixgbe_wol_exclusion(adapter, wol)) 2212 return wol->wolopts ? -EOPNOTSUPP : 0; 2213 2214 adapter->wol = 0; 2215 2216 if (wol->wolopts & WAKE_UCAST) 2217 adapter->wol |= IXGBE_WUFC_EX; 2218 if (wol->wolopts & WAKE_MCAST) 2219 adapter->wol |= IXGBE_WUFC_MC; 2220 if (wol->wolopts & WAKE_BCAST) 2221 adapter->wol |= IXGBE_WUFC_BC; 2222 if (wol->wolopts & WAKE_MAGIC) 2223 adapter->wol |= IXGBE_WUFC_MAG; 2224 2225 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2226 2227 return 0; 2228 } 2229 2230 static int ixgbe_nway_reset(struct net_device *netdev) 2231 { 2232 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2233 2234 if (netif_running(netdev)) 2235 ixgbe_reinit_locked(adapter); 2236 2237 return 0; 2238 } 2239 2240 static int ixgbe_set_phys_id(struct net_device *netdev, 2241 enum ethtool_phys_id_state state) 2242 { 2243 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2244 struct ixgbe_hw *hw = &adapter->hw; 2245 2246 if (!hw->mac.ops.led_on || !hw->mac.ops.led_off) 2247 return -EOPNOTSUPP; 2248 2249 switch (state) { 2250 case ETHTOOL_ID_ACTIVE: 2251 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2252 return 2; 2253 2254 case ETHTOOL_ID_ON: 2255 hw->mac.ops.led_on(hw, hw->mac.led_link_act); 2256 break; 2257 2258 case ETHTOOL_ID_OFF: 2259 hw->mac.ops.led_off(hw, hw->mac.led_link_act); 2260 break; 2261 2262 case ETHTOOL_ID_INACTIVE: 2263 /* Restore LED settings */ 2264 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg); 2265 break; 2266 } 2267 2268 return 0; 2269 } 2270 2271 static int ixgbe_get_coalesce(struct net_device *netdev, 2272 struct ethtool_coalesce *ec) 2273 { 2274 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2275 2276 /* only valid if in constant ITR mode */ 2277 if (adapter->rx_itr_setting <= 1) 2278 ec->rx_coalesce_usecs = adapter->rx_itr_setting; 2279 else 2280 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; 2281 2282 /* if in mixed tx/rx queues per vector mode, report only rx settings */ 2283 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) 2284 return 0; 2285 2286 /* only valid if in constant ITR mode */ 2287 if (adapter->tx_itr_setting <= 1) 2288 ec->tx_coalesce_usecs = adapter->tx_itr_setting; 2289 else 2290 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; 2291 2292 return 0; 2293 } 2294 2295 /* 2296 * this function must be called before setting the new value of 2297 * rx_itr_setting 2298 */ 2299 static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter) 2300 { 2301 struct net_device *netdev = adapter->netdev; 2302 2303 /* nothing to do if LRO or RSC are not enabled */ 2304 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) || 2305 !(netdev->features & NETIF_F_LRO)) 2306 return false; 2307 2308 /* check the feature flag value and enable RSC if necessary */ 2309 if (adapter->rx_itr_setting == 1 || 2310 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 2311 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 2312 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 2313 e_info(probe, "rx-usecs value high enough to re-enable RSC\n"); 2314 return true; 2315 } 2316 /* if interrupt rate is too high then disable RSC */ 2317 } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 2318 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 2319 e_info(probe, "rx-usecs set too low, disabling RSC\n"); 2320 return true; 2321 } 2322 return false; 2323 } 2324 2325 static int ixgbe_set_coalesce(struct net_device *netdev, 2326 struct ethtool_coalesce *ec) 2327 { 2328 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2329 struct ixgbe_q_vector *q_vector; 2330 int i; 2331 u16 tx_itr_param, rx_itr_param, tx_itr_prev; 2332 bool need_reset = false; 2333 2334 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) { 2335 /* reject Tx specific changes in case of mixed RxTx vectors */ 2336 if (ec->tx_coalesce_usecs) 2337 return -EINVAL; 2338 tx_itr_prev = adapter->rx_itr_setting; 2339 } else { 2340 tx_itr_prev = adapter->tx_itr_setting; 2341 } 2342 2343 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) || 2344 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2))) 2345 return -EINVAL; 2346 2347 if (ec->rx_coalesce_usecs > 1) 2348 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; 2349 else 2350 adapter->rx_itr_setting = ec->rx_coalesce_usecs; 2351 2352 if (adapter->rx_itr_setting == 1) 2353 rx_itr_param = IXGBE_20K_ITR; 2354 else 2355 rx_itr_param = adapter->rx_itr_setting; 2356 2357 if (ec->tx_coalesce_usecs > 1) 2358 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; 2359 else 2360 adapter->tx_itr_setting = ec->tx_coalesce_usecs; 2361 2362 if (adapter->tx_itr_setting == 1) 2363 tx_itr_param = IXGBE_12K_ITR; 2364 else 2365 tx_itr_param = adapter->tx_itr_setting; 2366 2367 /* mixed Rx/Tx */ 2368 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) 2369 adapter->tx_itr_setting = adapter->rx_itr_setting; 2370 2371 /* detect ITR changes that require update of TXDCTL.WTHRESH */ 2372 if ((adapter->tx_itr_setting != 1) && 2373 (adapter->tx_itr_setting < IXGBE_100K_ITR)) { 2374 if ((tx_itr_prev == 1) || 2375 (tx_itr_prev >= IXGBE_100K_ITR)) 2376 need_reset = true; 2377 } else { 2378 if ((tx_itr_prev != 1) && 2379 (tx_itr_prev < IXGBE_100K_ITR)) 2380 need_reset = true; 2381 } 2382 2383 /* check the old value and enable RSC if necessary */ 2384 need_reset |= ixgbe_update_rsc(adapter); 2385 2386 for (i = 0; i < adapter->num_q_vectors; i++) { 2387 q_vector = adapter->q_vector[i]; 2388 if (q_vector->tx.count && !q_vector->rx.count) 2389 /* tx only */ 2390 q_vector->itr = tx_itr_param; 2391 else 2392 /* rx only or mixed */ 2393 q_vector->itr = rx_itr_param; 2394 ixgbe_write_eitr(q_vector); 2395 } 2396 2397 /* 2398 * do reset here at the end to make sure EITR==0 case is handled 2399 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings 2400 * also locks in RSC enable/disable which requires reset 2401 */ 2402 if (need_reset) 2403 ixgbe_do_reset(netdev); 2404 2405 return 0; 2406 } 2407 2408 static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2409 struct ethtool_rxnfc *cmd) 2410 { 2411 union ixgbe_atr_input *mask = &adapter->fdir_mask; 2412 struct ethtool_rx_flow_spec *fsp = 2413 (struct ethtool_rx_flow_spec *)&cmd->fs; 2414 struct hlist_node *node2; 2415 struct ixgbe_fdir_filter *rule = NULL; 2416 2417 /* report total rule count */ 2418 cmd->data = (1024 << adapter->fdir_pballoc) - 2; 2419 2420 hlist_for_each_entry_safe(rule, node2, 2421 &adapter->fdir_filter_list, fdir_node) { 2422 if (fsp->location <= rule->sw_idx) 2423 break; 2424 } 2425 2426 if (!rule || fsp->location != rule->sw_idx) 2427 return -EINVAL; 2428 2429 /* fill out the flow spec entry */ 2430 2431 /* set flow type field */ 2432 switch (rule->filter.formatted.flow_type) { 2433 case IXGBE_ATR_FLOW_TYPE_TCPV4: 2434 fsp->flow_type = TCP_V4_FLOW; 2435 break; 2436 case IXGBE_ATR_FLOW_TYPE_UDPV4: 2437 fsp->flow_type = UDP_V4_FLOW; 2438 break; 2439 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 2440 fsp->flow_type = SCTP_V4_FLOW; 2441 break; 2442 case IXGBE_ATR_FLOW_TYPE_IPV4: 2443 fsp->flow_type = IP_USER_FLOW; 2444 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 2445 fsp->h_u.usr_ip4_spec.proto = 0; 2446 fsp->m_u.usr_ip4_spec.proto = 0; 2447 break; 2448 default: 2449 return -EINVAL; 2450 } 2451 2452 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port; 2453 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port; 2454 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port; 2455 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port; 2456 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0]; 2457 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0]; 2458 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0]; 2459 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0]; 2460 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id; 2461 fsp->m_ext.vlan_tci = mask->formatted.vlan_id; 2462 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes; 2463 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes; 2464 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool); 2465 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool); 2466 fsp->flow_type |= FLOW_EXT; 2467 2468 /* record action */ 2469 if (rule->action == IXGBE_FDIR_DROP_QUEUE) 2470 fsp->ring_cookie = RX_CLS_FLOW_DISC; 2471 else 2472 fsp->ring_cookie = rule->action; 2473 2474 return 0; 2475 } 2476 2477 static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter, 2478 struct ethtool_rxnfc *cmd, 2479 u32 *rule_locs) 2480 { 2481 struct hlist_node *node2; 2482 struct ixgbe_fdir_filter *rule; 2483 int cnt = 0; 2484 2485 /* report total rule count */ 2486 cmd->data = (1024 << adapter->fdir_pballoc) - 2; 2487 2488 hlist_for_each_entry_safe(rule, node2, 2489 &adapter->fdir_filter_list, fdir_node) { 2490 if (cnt == cmd->rule_cnt) 2491 return -EMSGSIZE; 2492 rule_locs[cnt] = rule->sw_idx; 2493 cnt++; 2494 } 2495 2496 cmd->rule_cnt = cnt; 2497 2498 return 0; 2499 } 2500 2501 static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter, 2502 struct ethtool_rxnfc *cmd) 2503 { 2504 cmd->data = 0; 2505 2506 /* Report default options for RSS on ixgbe */ 2507 switch (cmd->flow_type) { 2508 case TCP_V4_FLOW: 2509 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2510 /* fallthrough */ 2511 case UDP_V4_FLOW: 2512 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 2513 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2514 /* fallthrough */ 2515 case SCTP_V4_FLOW: 2516 case AH_ESP_V4_FLOW: 2517 case AH_V4_FLOW: 2518 case ESP_V4_FLOW: 2519 case IPV4_FLOW: 2520 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2521 break; 2522 case TCP_V6_FLOW: 2523 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2524 /* fallthrough */ 2525 case UDP_V6_FLOW: 2526 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2527 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2528 /* fallthrough */ 2529 case SCTP_V6_FLOW: 2530 case AH_ESP_V6_FLOW: 2531 case AH_V6_FLOW: 2532 case ESP_V6_FLOW: 2533 case IPV6_FLOW: 2534 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2535 break; 2536 default: 2537 return -EINVAL; 2538 } 2539 2540 return 0; 2541 } 2542 2543 static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2544 u32 *rule_locs) 2545 { 2546 struct ixgbe_adapter *adapter = netdev_priv(dev); 2547 int ret = -EOPNOTSUPP; 2548 2549 switch (cmd->cmd) { 2550 case ETHTOOL_GRXRINGS: 2551 cmd->data = adapter->num_rx_queues; 2552 ret = 0; 2553 break; 2554 case ETHTOOL_GRXCLSRLCNT: 2555 cmd->rule_cnt = adapter->fdir_filter_count; 2556 ret = 0; 2557 break; 2558 case ETHTOOL_GRXCLSRULE: 2559 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd); 2560 break; 2561 case ETHTOOL_GRXCLSRLALL: 2562 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs); 2563 break; 2564 case ETHTOOL_GRXFH: 2565 ret = ixgbe_get_rss_hash_opts(adapter, cmd); 2566 break; 2567 default: 2568 break; 2569 } 2570 2571 return ret; 2572 } 2573 2574 int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2575 struct ixgbe_fdir_filter *input, 2576 u16 sw_idx) 2577 { 2578 struct ixgbe_hw *hw = &adapter->hw; 2579 struct hlist_node *node2; 2580 struct ixgbe_fdir_filter *rule, *parent; 2581 int err = -EINVAL; 2582 2583 parent = NULL; 2584 rule = NULL; 2585 2586 hlist_for_each_entry_safe(rule, node2, 2587 &adapter->fdir_filter_list, fdir_node) { 2588 /* hash found, or no matching entry */ 2589 if (rule->sw_idx >= sw_idx) 2590 break; 2591 parent = rule; 2592 } 2593 2594 /* if there is an old rule occupying our place remove it */ 2595 if (rule && (rule->sw_idx == sw_idx)) { 2596 if (!input || (rule->filter.formatted.bkt_hash != 2597 input->filter.formatted.bkt_hash)) { 2598 err = ixgbe_fdir_erase_perfect_filter_82599(hw, 2599 &rule->filter, 2600 sw_idx); 2601 } 2602 2603 hlist_del(&rule->fdir_node); 2604 kfree(rule); 2605 adapter->fdir_filter_count--; 2606 } 2607 2608 /* 2609 * If no input this was a delete, err should be 0 if a rule was 2610 * successfully found and removed from the list else -EINVAL 2611 */ 2612 if (!input) 2613 return err; 2614 2615 /* initialize node and set software index */ 2616 INIT_HLIST_NODE(&input->fdir_node); 2617 2618 /* add filter to the list */ 2619 if (parent) 2620 hlist_add_behind(&input->fdir_node, &parent->fdir_node); 2621 else 2622 hlist_add_head(&input->fdir_node, 2623 &adapter->fdir_filter_list); 2624 2625 /* update counts */ 2626 adapter->fdir_filter_count++; 2627 2628 return 0; 2629 } 2630 2631 static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp, 2632 u8 *flow_type) 2633 { 2634 switch (fsp->flow_type & ~FLOW_EXT) { 2635 case TCP_V4_FLOW: 2636 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 2637 break; 2638 case UDP_V4_FLOW: 2639 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 2640 break; 2641 case SCTP_V4_FLOW: 2642 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 2643 break; 2644 case IP_USER_FLOW: 2645 switch (fsp->h_u.usr_ip4_spec.proto) { 2646 case IPPROTO_TCP: 2647 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 2648 break; 2649 case IPPROTO_UDP: 2650 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 2651 break; 2652 case IPPROTO_SCTP: 2653 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 2654 break; 2655 case 0: 2656 if (!fsp->m_u.usr_ip4_spec.proto) { 2657 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4; 2658 break; 2659 } 2660 /* fall through */ 2661 default: 2662 return 0; 2663 } 2664 break; 2665 default: 2666 return 0; 2667 } 2668 2669 return 1; 2670 } 2671 2672 static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2673 struct ethtool_rxnfc *cmd) 2674 { 2675 struct ethtool_rx_flow_spec *fsp = 2676 (struct ethtool_rx_flow_spec *)&cmd->fs; 2677 struct ixgbe_hw *hw = &adapter->hw; 2678 struct ixgbe_fdir_filter *input; 2679 union ixgbe_atr_input mask; 2680 u8 queue; 2681 int err; 2682 2683 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 2684 return -EOPNOTSUPP; 2685 2686 /* ring_cookie is a masked into a set of queues and ixgbe pools or 2687 * we use the drop index. 2688 */ 2689 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) { 2690 queue = IXGBE_FDIR_DROP_QUEUE; 2691 } else { 2692 u32 ring = ethtool_get_flow_spec_ring(fsp->ring_cookie); 2693 u8 vf = ethtool_get_flow_spec_ring_vf(fsp->ring_cookie); 2694 2695 if (!vf && (ring >= adapter->num_rx_queues)) 2696 return -EINVAL; 2697 else if (vf && 2698 ((vf > adapter->num_vfs) || 2699 ring >= adapter->num_rx_queues_per_pool)) 2700 return -EINVAL; 2701 2702 /* Map the ring onto the absolute queue index */ 2703 if (!vf) 2704 queue = adapter->rx_ring[ring]->reg_idx; 2705 else 2706 queue = ((vf - 1) * 2707 adapter->num_rx_queues_per_pool) + ring; 2708 } 2709 2710 /* Don't allow indexes to exist outside of available space */ 2711 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) { 2712 e_err(drv, "Location out of range\n"); 2713 return -EINVAL; 2714 } 2715 2716 input = kzalloc(sizeof(*input), GFP_ATOMIC); 2717 if (!input) 2718 return -ENOMEM; 2719 2720 memset(&mask, 0, sizeof(union ixgbe_atr_input)); 2721 2722 /* set SW index */ 2723 input->sw_idx = fsp->location; 2724 2725 /* record flow type */ 2726 if (!ixgbe_flowspec_to_flow_type(fsp, 2727 &input->filter.formatted.flow_type)) { 2728 e_err(drv, "Unrecognized flow type\n"); 2729 goto err_out; 2730 } 2731 2732 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 2733 IXGBE_ATR_L4TYPE_MASK; 2734 2735 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 2736 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 2737 2738 /* Copy input into formatted structures */ 2739 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src; 2740 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src; 2741 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst; 2742 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst; 2743 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc; 2744 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc; 2745 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst; 2746 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst; 2747 2748 if (fsp->flow_type & FLOW_EXT) { 2749 input->filter.formatted.vm_pool = 2750 (unsigned char)ntohl(fsp->h_ext.data[1]); 2751 mask.formatted.vm_pool = 2752 (unsigned char)ntohl(fsp->m_ext.data[1]); 2753 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci; 2754 mask.formatted.vlan_id = fsp->m_ext.vlan_tci; 2755 input->filter.formatted.flex_bytes = 2756 fsp->h_ext.vlan_etype; 2757 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype; 2758 } 2759 2760 /* determine if we need to drop or route the packet */ 2761 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) 2762 input->action = IXGBE_FDIR_DROP_QUEUE; 2763 else 2764 input->action = fsp->ring_cookie; 2765 2766 spin_lock(&adapter->fdir_perfect_lock); 2767 2768 if (hlist_empty(&adapter->fdir_filter_list)) { 2769 /* save mask and program input mask into HW */ 2770 memcpy(&adapter->fdir_mask, &mask, sizeof(mask)); 2771 err = ixgbe_fdir_set_input_mask_82599(hw, &mask); 2772 if (err) { 2773 e_err(drv, "Error writing mask\n"); 2774 goto err_out_w_lock; 2775 } 2776 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) { 2777 e_err(drv, "Only one mask supported per port\n"); 2778 goto err_out_w_lock; 2779 } 2780 2781 /* apply mask and compute/store hash */ 2782 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask); 2783 2784 /* program filters to filter memory */ 2785 err = ixgbe_fdir_write_perfect_filter_82599(hw, 2786 &input->filter, input->sw_idx, queue); 2787 if (err) 2788 goto err_out_w_lock; 2789 2790 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 2791 2792 spin_unlock(&adapter->fdir_perfect_lock); 2793 2794 return err; 2795 err_out_w_lock: 2796 spin_unlock(&adapter->fdir_perfect_lock); 2797 err_out: 2798 kfree(input); 2799 return -EINVAL; 2800 } 2801 2802 static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2803 struct ethtool_rxnfc *cmd) 2804 { 2805 struct ethtool_rx_flow_spec *fsp = 2806 (struct ethtool_rx_flow_spec *)&cmd->fs; 2807 int err; 2808 2809 spin_lock(&adapter->fdir_perfect_lock); 2810 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location); 2811 spin_unlock(&adapter->fdir_perfect_lock); 2812 2813 return err; 2814 } 2815 2816 #define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \ 2817 IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2818 static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter, 2819 struct ethtool_rxnfc *nfc) 2820 { 2821 u32 flags2 = adapter->flags2; 2822 2823 /* 2824 * RSS does not support anything other than hashing 2825 * to queues on src and dst IPs and ports 2826 */ 2827 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 2828 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 2829 return -EINVAL; 2830 2831 switch (nfc->flow_type) { 2832 case TCP_V4_FLOW: 2833 case TCP_V6_FLOW: 2834 if (!(nfc->data & RXH_IP_SRC) || 2835 !(nfc->data & RXH_IP_DST) || 2836 !(nfc->data & RXH_L4_B_0_1) || 2837 !(nfc->data & RXH_L4_B_2_3)) 2838 return -EINVAL; 2839 break; 2840 case UDP_V4_FLOW: 2841 if (!(nfc->data & RXH_IP_SRC) || 2842 !(nfc->data & RXH_IP_DST)) 2843 return -EINVAL; 2844 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2845 case 0: 2846 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP; 2847 break; 2848 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2849 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP; 2850 break; 2851 default: 2852 return -EINVAL; 2853 } 2854 break; 2855 case UDP_V6_FLOW: 2856 if (!(nfc->data & RXH_IP_SRC) || 2857 !(nfc->data & RXH_IP_DST)) 2858 return -EINVAL; 2859 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2860 case 0: 2861 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP; 2862 break; 2863 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2864 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP; 2865 break; 2866 default: 2867 return -EINVAL; 2868 } 2869 break; 2870 case AH_ESP_V4_FLOW: 2871 case AH_V4_FLOW: 2872 case ESP_V4_FLOW: 2873 case SCTP_V4_FLOW: 2874 case AH_ESP_V6_FLOW: 2875 case AH_V6_FLOW: 2876 case ESP_V6_FLOW: 2877 case SCTP_V6_FLOW: 2878 if (!(nfc->data & RXH_IP_SRC) || 2879 !(nfc->data & RXH_IP_DST) || 2880 (nfc->data & RXH_L4_B_0_1) || 2881 (nfc->data & RXH_L4_B_2_3)) 2882 return -EINVAL; 2883 break; 2884 default: 2885 return -EINVAL; 2886 } 2887 2888 /* if we changed something we need to update flags */ 2889 if (flags2 != adapter->flags2) { 2890 struct ixgbe_hw *hw = &adapter->hw; 2891 u32 mrqc; 2892 unsigned int pf_pool = adapter->num_vfs; 2893 2894 if ((hw->mac.type >= ixgbe_mac_X550) && 2895 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 2896 mrqc = IXGBE_READ_REG(hw, IXGBE_PFVFMRQC(pf_pool)); 2897 else 2898 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC); 2899 2900 if ((flags2 & UDP_RSS_FLAGS) && 2901 !(adapter->flags2 & UDP_RSS_FLAGS)) 2902 e_warn(drv, "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n"); 2903 2904 adapter->flags2 = flags2; 2905 2906 /* Perform hash on these packet types */ 2907 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 2908 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP 2909 | IXGBE_MRQC_RSS_FIELD_IPV6 2910 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 2911 2912 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP | 2913 IXGBE_MRQC_RSS_FIELD_IPV6_UDP); 2914 2915 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 2916 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 2917 2918 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2919 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 2920 2921 if ((hw->mac.type >= ixgbe_mac_X550) && 2922 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 2923 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), mrqc); 2924 else 2925 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 2926 } 2927 2928 return 0; 2929 } 2930 2931 static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2932 { 2933 struct ixgbe_adapter *adapter = netdev_priv(dev); 2934 int ret = -EOPNOTSUPP; 2935 2936 switch (cmd->cmd) { 2937 case ETHTOOL_SRXCLSRLINS: 2938 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd); 2939 break; 2940 case ETHTOOL_SRXCLSRLDEL: 2941 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd); 2942 break; 2943 case ETHTOOL_SRXFH: 2944 ret = ixgbe_set_rss_hash_opt(adapter, cmd); 2945 break; 2946 default: 2947 break; 2948 } 2949 2950 return ret; 2951 } 2952 2953 static int ixgbe_rss_indir_tbl_max(struct ixgbe_adapter *adapter) 2954 { 2955 if (adapter->hw.mac.type < ixgbe_mac_X550) 2956 return 16; 2957 else 2958 return 64; 2959 } 2960 2961 static u32 ixgbe_get_rxfh_key_size(struct net_device *netdev) 2962 { 2963 return IXGBE_RSS_KEY_SIZE; 2964 } 2965 2966 static u32 ixgbe_rss_indir_size(struct net_device *netdev) 2967 { 2968 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2969 2970 return ixgbe_rss_indir_tbl_entries(adapter); 2971 } 2972 2973 static void ixgbe_get_reta(struct ixgbe_adapter *adapter, u32 *indir) 2974 { 2975 int i, reta_size = ixgbe_rss_indir_tbl_entries(adapter); 2976 u16 rss_m = adapter->ring_feature[RING_F_RSS].mask; 2977 2978 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 2979 rss_m = adapter->ring_feature[RING_F_RSS].indices - 1; 2980 2981 for (i = 0; i < reta_size; i++) 2982 indir[i] = adapter->rss_indir_tbl[i] & rss_m; 2983 } 2984 2985 static int ixgbe_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, 2986 u8 *hfunc) 2987 { 2988 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2989 2990 if (hfunc) 2991 *hfunc = ETH_RSS_HASH_TOP; 2992 2993 if (indir) 2994 ixgbe_get_reta(adapter, indir); 2995 2996 if (key) 2997 memcpy(key, adapter->rss_key, ixgbe_get_rxfh_key_size(netdev)); 2998 2999 return 0; 3000 } 3001 3002 static int ixgbe_set_rxfh(struct net_device *netdev, const u32 *indir, 3003 const u8 *key, const u8 hfunc) 3004 { 3005 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3006 int i; 3007 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3008 3009 if (hfunc) 3010 return -EINVAL; 3011 3012 /* Fill out the redirection table */ 3013 if (indir) { 3014 int max_queues = min_t(int, adapter->num_rx_queues, 3015 ixgbe_rss_indir_tbl_max(adapter)); 3016 3017 /*Allow at least 2 queues w/ SR-IOV.*/ 3018 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 3019 (max_queues < 2)) 3020 max_queues = 2; 3021 3022 /* Verify user input. */ 3023 for (i = 0; i < reta_entries; i++) 3024 if (indir[i] >= max_queues) 3025 return -EINVAL; 3026 3027 for (i = 0; i < reta_entries; i++) 3028 adapter->rss_indir_tbl[i] = indir[i]; 3029 3030 ixgbe_store_reta(adapter); 3031 } 3032 3033 /* Fill out the rss hash key */ 3034 if (key) { 3035 memcpy(adapter->rss_key, key, ixgbe_get_rxfh_key_size(netdev)); 3036 ixgbe_store_key(adapter); 3037 } 3038 3039 return 0; 3040 } 3041 3042 static int ixgbe_get_ts_info(struct net_device *dev, 3043 struct ethtool_ts_info *info) 3044 { 3045 struct ixgbe_adapter *adapter = netdev_priv(dev); 3046 3047 /* we always support timestamping disabled */ 3048 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE); 3049 3050 switch (adapter->hw.mac.type) { 3051 case ixgbe_mac_X550: 3052 case ixgbe_mac_X550EM_x: 3053 case ixgbe_mac_x550em_a: 3054 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL); 3055 break; 3056 case ixgbe_mac_X540: 3057 case ixgbe_mac_82599EB: 3058 info->rx_filters |= 3059 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 3060 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 3061 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT); 3062 break; 3063 default: 3064 return ethtool_op_get_ts_info(dev, info); 3065 } 3066 3067 info->so_timestamping = 3068 SOF_TIMESTAMPING_TX_SOFTWARE | 3069 SOF_TIMESTAMPING_RX_SOFTWARE | 3070 SOF_TIMESTAMPING_SOFTWARE | 3071 SOF_TIMESTAMPING_TX_HARDWARE | 3072 SOF_TIMESTAMPING_RX_HARDWARE | 3073 SOF_TIMESTAMPING_RAW_HARDWARE; 3074 3075 if (adapter->ptp_clock) 3076 info->phc_index = ptp_clock_index(adapter->ptp_clock); 3077 else 3078 info->phc_index = -1; 3079 3080 info->tx_types = 3081 BIT(HWTSTAMP_TX_OFF) | 3082 BIT(HWTSTAMP_TX_ON); 3083 3084 return 0; 3085 } 3086 3087 static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter) 3088 { 3089 unsigned int max_combined; 3090 u8 tcs = adapter->hw_tcs; 3091 3092 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3093 /* We only support one q_vector without MSI-X */ 3094 max_combined = 1; 3095 } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3096 /* Limit value based on the queue mask */ 3097 max_combined = adapter->ring_feature[RING_F_RSS].mask + 1; 3098 } else if (tcs > 1) { 3099 /* For DCB report channels per traffic class */ 3100 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3101 /* 8 TC w/ 4 queues per TC */ 3102 max_combined = 4; 3103 } else if (tcs > 4) { 3104 /* 8 TC w/ 8 queues per TC */ 3105 max_combined = 8; 3106 } else { 3107 /* 4 TC w/ 16 queues per TC */ 3108 max_combined = 16; 3109 } 3110 } else if (adapter->atr_sample_rate) { 3111 /* support up to 64 queues with ATR */ 3112 max_combined = IXGBE_MAX_FDIR_INDICES; 3113 } else { 3114 /* support up to 16 queues with RSS */ 3115 max_combined = ixgbe_max_rss_indices(adapter); 3116 } 3117 3118 return max_combined; 3119 } 3120 3121 static void ixgbe_get_channels(struct net_device *dev, 3122 struct ethtool_channels *ch) 3123 { 3124 struct ixgbe_adapter *adapter = netdev_priv(dev); 3125 3126 /* report maximum channels */ 3127 ch->max_combined = ixgbe_max_channels(adapter); 3128 3129 /* report info for other vector */ 3130 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3131 ch->max_other = NON_Q_VECTORS; 3132 ch->other_count = NON_Q_VECTORS; 3133 } 3134 3135 /* record RSS queues */ 3136 ch->combined_count = adapter->ring_feature[RING_F_RSS].indices; 3137 3138 /* nothing else to report if RSS is disabled */ 3139 if (ch->combined_count == 1) 3140 return; 3141 3142 /* we do not support ATR queueing if SR-IOV is enabled */ 3143 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3144 return; 3145 3146 /* same thing goes for being DCB enabled */ 3147 if (adapter->hw_tcs > 1) 3148 return; 3149 3150 /* if ATR is disabled we can exit */ 3151 if (!adapter->atr_sample_rate) 3152 return; 3153 3154 /* report flow director queues as maximum channels */ 3155 ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices; 3156 } 3157 3158 static int ixgbe_set_channels(struct net_device *dev, 3159 struct ethtool_channels *ch) 3160 { 3161 struct ixgbe_adapter *adapter = netdev_priv(dev); 3162 unsigned int count = ch->combined_count; 3163 u8 max_rss_indices = ixgbe_max_rss_indices(adapter); 3164 3165 /* verify they are not requesting separate vectors */ 3166 if (!count || ch->rx_count || ch->tx_count) 3167 return -EINVAL; 3168 3169 /* verify other_count has not changed */ 3170 if (ch->other_count != NON_Q_VECTORS) 3171 return -EINVAL; 3172 3173 /* verify the number of channels does not exceed hardware limits */ 3174 if (count > ixgbe_max_channels(adapter)) 3175 return -EINVAL; 3176 3177 /* update feature limits from largest to smallest supported values */ 3178 adapter->ring_feature[RING_F_FDIR].limit = count; 3179 3180 /* cap RSS limit */ 3181 if (count > max_rss_indices) 3182 count = max_rss_indices; 3183 adapter->ring_feature[RING_F_RSS].limit = count; 3184 3185 #ifdef IXGBE_FCOE 3186 /* cap FCoE limit at 8 */ 3187 if (count > IXGBE_FCRETA_SIZE) 3188 count = IXGBE_FCRETA_SIZE; 3189 adapter->ring_feature[RING_F_FCOE].limit = count; 3190 3191 #endif 3192 /* use setup TC to update any traffic class queue mapping */ 3193 return ixgbe_setup_tc(dev, adapter->hw_tcs); 3194 } 3195 3196 static int ixgbe_get_module_info(struct net_device *dev, 3197 struct ethtool_modinfo *modinfo) 3198 { 3199 struct ixgbe_adapter *adapter = netdev_priv(dev); 3200 struct ixgbe_hw *hw = &adapter->hw; 3201 s32 status; 3202 u8 sff8472_rev, addr_mode; 3203 bool page_swap = false; 3204 3205 if (hw->phy.type == ixgbe_phy_fw) 3206 return -ENXIO; 3207 3208 /* Check whether we support SFF-8472 or not */ 3209 status = hw->phy.ops.read_i2c_eeprom(hw, 3210 IXGBE_SFF_SFF_8472_COMP, 3211 &sff8472_rev); 3212 if (status) 3213 return -EIO; 3214 3215 /* addressing mode is not supported */ 3216 status = hw->phy.ops.read_i2c_eeprom(hw, 3217 IXGBE_SFF_SFF_8472_SWAP, 3218 &addr_mode); 3219 if (status) 3220 return -EIO; 3221 3222 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) { 3223 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n"); 3224 page_swap = true; 3225 } 3226 3227 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap || 3228 !(addr_mode & IXGBE_SFF_DDM_IMPLEMENTED)) { 3229 /* We have a SFP, but it does not support SFF-8472 */ 3230 modinfo->type = ETH_MODULE_SFF_8079; 3231 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 3232 } else { 3233 /* We have a SFP which supports a revision of SFF-8472. */ 3234 modinfo->type = ETH_MODULE_SFF_8472; 3235 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 3236 } 3237 3238 return 0; 3239 } 3240 3241 static int ixgbe_get_module_eeprom(struct net_device *dev, 3242 struct ethtool_eeprom *ee, 3243 u8 *data) 3244 { 3245 struct ixgbe_adapter *adapter = netdev_priv(dev); 3246 struct ixgbe_hw *hw = &adapter->hw; 3247 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 3248 u8 databyte = 0xFF; 3249 int i = 0; 3250 3251 if (ee->len == 0) 3252 return -EINVAL; 3253 3254 if (hw->phy.type == ixgbe_phy_fw) 3255 return -ENXIO; 3256 3257 for (i = ee->offset; i < ee->offset + ee->len; i++) { 3258 /* I2C reads can take long time */ 3259 if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 3260 return -EBUSY; 3261 3262 if (i < ETH_MODULE_SFF_8079_LEN) 3263 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); 3264 else 3265 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); 3266 3267 if (status) 3268 return -EIO; 3269 3270 data[i - ee->offset] = databyte; 3271 } 3272 3273 return 0; 3274 } 3275 3276 static const struct { 3277 ixgbe_link_speed mac_speed; 3278 u32 supported; 3279 } ixgbe_ls_map[] = { 3280 { IXGBE_LINK_SPEED_10_FULL, SUPPORTED_10baseT_Full }, 3281 { IXGBE_LINK_SPEED_100_FULL, SUPPORTED_100baseT_Full }, 3282 { IXGBE_LINK_SPEED_1GB_FULL, SUPPORTED_1000baseT_Full }, 3283 { IXGBE_LINK_SPEED_2_5GB_FULL, SUPPORTED_2500baseX_Full }, 3284 { IXGBE_LINK_SPEED_10GB_FULL, SUPPORTED_10000baseT_Full }, 3285 }; 3286 3287 static const struct { 3288 u32 lp_advertised; 3289 u32 mac_speed; 3290 } ixgbe_lp_map[] = { 3291 { FW_PHY_ACT_UD_2_100M_TX_EEE, SUPPORTED_100baseT_Full }, 3292 { FW_PHY_ACT_UD_2_1G_T_EEE, SUPPORTED_1000baseT_Full }, 3293 { FW_PHY_ACT_UD_2_10G_T_EEE, SUPPORTED_10000baseT_Full }, 3294 { FW_PHY_ACT_UD_2_1G_KX_EEE, SUPPORTED_1000baseKX_Full }, 3295 { FW_PHY_ACT_UD_2_10G_KX4_EEE, SUPPORTED_10000baseKX4_Full }, 3296 { FW_PHY_ACT_UD_2_10G_KR_EEE, SUPPORTED_10000baseKR_Full}, 3297 }; 3298 3299 static int 3300 ixgbe_get_eee_fw(struct ixgbe_adapter *adapter, struct ethtool_eee *edata) 3301 { 3302 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 3303 struct ixgbe_hw *hw = &adapter->hw; 3304 s32 rc; 3305 u16 i; 3306 3307 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_UD_2, &info); 3308 if (rc) 3309 return rc; 3310 3311 edata->lp_advertised = 0; 3312 for (i = 0; i < ARRAY_SIZE(ixgbe_lp_map); ++i) { 3313 if (info[0] & ixgbe_lp_map[i].lp_advertised) 3314 edata->lp_advertised |= ixgbe_lp_map[i].mac_speed; 3315 } 3316 3317 edata->supported = 0; 3318 for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) { 3319 if (hw->phy.eee_speeds_supported & ixgbe_ls_map[i].mac_speed) 3320 edata->supported |= ixgbe_ls_map[i].supported; 3321 } 3322 3323 edata->advertised = 0; 3324 for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) { 3325 if (hw->phy.eee_speeds_advertised & ixgbe_ls_map[i].mac_speed) 3326 edata->advertised |= ixgbe_ls_map[i].supported; 3327 } 3328 3329 edata->eee_enabled = !!edata->advertised; 3330 edata->tx_lpi_enabled = edata->eee_enabled; 3331 if (edata->advertised & edata->lp_advertised) 3332 edata->eee_active = true; 3333 3334 return 0; 3335 } 3336 3337 static int ixgbe_get_eee(struct net_device *netdev, struct ethtool_eee *edata) 3338 { 3339 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3340 struct ixgbe_hw *hw = &adapter->hw; 3341 3342 if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE)) 3343 return -EOPNOTSUPP; 3344 3345 if (hw->phy.eee_speeds_supported && hw->phy.type == ixgbe_phy_fw) 3346 return ixgbe_get_eee_fw(adapter, edata); 3347 3348 return -EOPNOTSUPP; 3349 } 3350 3351 static int ixgbe_set_eee(struct net_device *netdev, struct ethtool_eee *edata) 3352 { 3353 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3354 struct ixgbe_hw *hw = &adapter->hw; 3355 struct ethtool_eee eee_data; 3356 s32 ret_val; 3357 3358 if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE)) 3359 return -EOPNOTSUPP; 3360 3361 memset(&eee_data, 0, sizeof(struct ethtool_eee)); 3362 3363 ret_val = ixgbe_get_eee(netdev, &eee_data); 3364 if (ret_val) 3365 return ret_val; 3366 3367 if (eee_data.eee_enabled && !edata->eee_enabled) { 3368 if (eee_data.tx_lpi_enabled != edata->tx_lpi_enabled) { 3369 e_err(drv, "Setting EEE tx-lpi is not supported\n"); 3370 return -EINVAL; 3371 } 3372 3373 if (eee_data.tx_lpi_timer != edata->tx_lpi_timer) { 3374 e_err(drv, 3375 "Setting EEE Tx LPI timer is not supported\n"); 3376 return -EINVAL; 3377 } 3378 3379 if (eee_data.advertised != edata->advertised) { 3380 e_err(drv, 3381 "Setting EEE advertised speeds is not supported\n"); 3382 return -EINVAL; 3383 } 3384 } 3385 3386 if (eee_data.eee_enabled != edata->eee_enabled) { 3387 if (edata->eee_enabled) { 3388 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 3389 hw->phy.eee_speeds_advertised = 3390 hw->phy.eee_speeds_supported; 3391 } else { 3392 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 3393 hw->phy.eee_speeds_advertised = 0; 3394 } 3395 3396 /* reset link */ 3397 if (netif_running(netdev)) 3398 ixgbe_reinit_locked(adapter); 3399 else 3400 ixgbe_reset(adapter); 3401 } 3402 3403 return 0; 3404 } 3405 3406 static u32 ixgbe_get_priv_flags(struct net_device *netdev) 3407 { 3408 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3409 u32 priv_flags = 0; 3410 3411 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 3412 priv_flags |= IXGBE_PRIV_FLAGS_LEGACY_RX; 3413 3414 if (adapter->flags2 & IXGBE_FLAG2_VF_IPSEC_ENABLED) 3415 priv_flags |= IXGBE_PRIV_FLAGS_VF_IPSEC_EN; 3416 3417 return priv_flags; 3418 } 3419 3420 static int ixgbe_set_priv_flags(struct net_device *netdev, u32 priv_flags) 3421 { 3422 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3423 unsigned int flags2 = adapter->flags2; 3424 3425 flags2 &= ~IXGBE_FLAG2_RX_LEGACY; 3426 if (priv_flags & IXGBE_PRIV_FLAGS_LEGACY_RX) 3427 flags2 |= IXGBE_FLAG2_RX_LEGACY; 3428 3429 flags2 &= ~IXGBE_FLAG2_VF_IPSEC_ENABLED; 3430 if (priv_flags & IXGBE_PRIV_FLAGS_VF_IPSEC_EN) 3431 flags2 |= IXGBE_FLAG2_VF_IPSEC_ENABLED; 3432 3433 if (flags2 != adapter->flags2) { 3434 adapter->flags2 = flags2; 3435 3436 /* reset interface to repopulate queues */ 3437 if (netif_running(netdev)) 3438 ixgbe_reinit_locked(adapter); 3439 } 3440 3441 return 0; 3442 } 3443 3444 static const struct ethtool_ops ixgbe_ethtool_ops = { 3445 .supported_coalesce_params = ETHTOOL_COALESCE_USECS, 3446 .get_drvinfo = ixgbe_get_drvinfo, 3447 .get_regs_len = ixgbe_get_regs_len, 3448 .get_regs = ixgbe_get_regs, 3449 .get_wol = ixgbe_get_wol, 3450 .set_wol = ixgbe_set_wol, 3451 .nway_reset = ixgbe_nway_reset, 3452 .get_link = ethtool_op_get_link, 3453 .get_eeprom_len = ixgbe_get_eeprom_len, 3454 .get_eeprom = ixgbe_get_eeprom, 3455 .set_eeprom = ixgbe_set_eeprom, 3456 .get_ringparam = ixgbe_get_ringparam, 3457 .set_ringparam = ixgbe_set_ringparam, 3458 .get_pauseparam = ixgbe_get_pauseparam, 3459 .set_pauseparam = ixgbe_set_pauseparam, 3460 .get_msglevel = ixgbe_get_msglevel, 3461 .set_msglevel = ixgbe_set_msglevel, 3462 .self_test = ixgbe_diag_test, 3463 .get_strings = ixgbe_get_strings, 3464 .set_phys_id = ixgbe_set_phys_id, 3465 .get_sset_count = ixgbe_get_sset_count, 3466 .get_ethtool_stats = ixgbe_get_ethtool_stats, 3467 .get_coalesce = ixgbe_get_coalesce, 3468 .set_coalesce = ixgbe_set_coalesce, 3469 .get_rxnfc = ixgbe_get_rxnfc, 3470 .set_rxnfc = ixgbe_set_rxnfc, 3471 .get_rxfh_indir_size = ixgbe_rss_indir_size, 3472 .get_rxfh_key_size = ixgbe_get_rxfh_key_size, 3473 .get_rxfh = ixgbe_get_rxfh, 3474 .set_rxfh = ixgbe_set_rxfh, 3475 .get_eee = ixgbe_get_eee, 3476 .set_eee = ixgbe_set_eee, 3477 .get_channels = ixgbe_get_channels, 3478 .set_channels = ixgbe_set_channels, 3479 .get_priv_flags = ixgbe_get_priv_flags, 3480 .set_priv_flags = ixgbe_set_priv_flags, 3481 .get_ts_info = ixgbe_get_ts_info, 3482 .get_module_info = ixgbe_get_module_info, 3483 .get_module_eeprom = ixgbe_get_module_eeprom, 3484 .get_link_ksettings = ixgbe_get_link_ksettings, 3485 .set_link_ksettings = ixgbe_set_link_ksettings, 3486 }; 3487 3488 void ixgbe_set_ethtool_ops(struct net_device *netdev) 3489 { 3490 netdev->ethtool_ops = &ixgbe_ethtool_ops; 3491 } 3492