1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2024 Intel Corporation. */ 3 4 /* ethtool support for ixgbe */ 5 6 #include <linux/interrupt.h> 7 #include <linux/types.h> 8 #include <linux/module.h> 9 #include <linux/slab.h> 10 #include <linux/pci.h> 11 #include <linux/netdevice.h> 12 #include <linux/ethtool.h> 13 #include <linux/vmalloc.h> 14 #include <linux/highmem.h> 15 #include <linux/uaccess.h> 16 17 #include "ixgbe.h" 18 #include "ixgbe_phy.h" 19 20 21 enum {NETDEV_STATS, IXGBE_STATS}; 22 23 struct ixgbe_stats { 24 char stat_string[ETH_GSTRING_LEN]; 25 int type; 26 int sizeof_stat; 27 int stat_offset; 28 }; 29 30 #define IXGBE_STAT(m) IXGBE_STATS, \ 31 sizeof(((struct ixgbe_adapter *)0)->m), \ 32 offsetof(struct ixgbe_adapter, m) 33 #define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \ 34 sizeof(((struct rtnl_link_stats64 *)0)->m), \ 35 offsetof(struct rtnl_link_stats64, m) 36 37 static const struct ixgbe_stats ixgbe_gstrings_stats[] = { 38 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)}, 39 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)}, 40 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)}, 41 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)}, 42 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)}, 43 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)}, 44 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)}, 45 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)}, 46 {"lsc_int", IXGBE_STAT(lsc_int)}, 47 {"tx_busy", IXGBE_STAT(tx_busy)}, 48 {"non_eop_descs", IXGBE_STAT(non_eop_descs)}, 49 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)}, 50 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)}, 51 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)}, 52 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)}, 53 {"multicast", IXGBE_NETDEV_STAT(multicast)}, 54 {"broadcast", IXGBE_STAT(stats.bprc)}, 55 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) }, 56 {"collisions", IXGBE_NETDEV_STAT(collisions)}, 57 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)}, 58 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)}, 59 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)}, 60 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)}, 61 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)}, 62 {"fdir_match", IXGBE_STAT(stats.fdirmatch)}, 63 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)}, 64 {"fdir_overflow", IXGBE_STAT(fdir_overflow)}, 65 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)}, 66 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)}, 67 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)}, 68 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)}, 69 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)}, 70 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)}, 71 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)}, 72 {"tx_restart_queue", IXGBE_STAT(restart_queue)}, 73 {"rx_length_errors", IXGBE_STAT(stats.rlec)}, 74 {"rx_long_length_errors", IXGBE_STAT(stats.roc)}, 75 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)}, 76 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)}, 77 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)}, 78 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)}, 79 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)}, 80 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)}, 81 {"alloc_rx_page", IXGBE_STAT(alloc_rx_page)}, 82 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)}, 83 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)}, 84 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)}, 85 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)}, 86 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)}, 87 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)}, 88 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)}, 89 {"tx_hwtstamp_timeouts", IXGBE_STAT(tx_hwtstamp_timeouts)}, 90 {"tx_hwtstamp_skipped", IXGBE_STAT(tx_hwtstamp_skipped)}, 91 {"rx_hwtstamp_cleared", IXGBE_STAT(rx_hwtstamp_cleared)}, 92 {"tx_ipsec", IXGBE_STAT(tx_ipsec)}, 93 {"rx_ipsec", IXGBE_STAT(rx_ipsec)}, 94 #ifdef IXGBE_FCOE 95 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)}, 96 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)}, 97 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)}, 98 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)}, 99 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)}, 100 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)}, 101 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)}, 102 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)}, 103 #endif /* IXGBE_FCOE */ 104 }; 105 106 /* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so 107 * we set the num_rx_queues to evaluate to num_tx_queues. This is 108 * used because we do not have a good way to get the max number of 109 * rx queues with CONFIG_RPS disabled. 110 */ 111 #define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues 112 113 #define IXGBE_QUEUE_STATS_LEN ( \ 114 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \ 115 (sizeof(struct ixgbe_queue_stats) / sizeof(u64))) 116 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats) 117 #define IXGBE_PB_STATS_LEN ( \ 118 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \ 119 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \ 120 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \ 121 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \ 122 / sizeof(u64)) 123 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \ 124 IXGBE_PB_STATS_LEN + \ 125 IXGBE_QUEUE_STATS_LEN) 126 127 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = { 128 "Register test (offline)", "Eeprom test (offline)", 129 "Interrupt test (offline)", "Loopback test (offline)", 130 "Link test (on/offline)" 131 }; 132 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN 133 134 static const char ixgbe_priv_flags_strings[][ETH_GSTRING_LEN] = { 135 #define IXGBE_PRIV_FLAGS_LEGACY_RX BIT(0) 136 "legacy-rx", 137 #define IXGBE_PRIV_FLAGS_VF_IPSEC_EN BIT(1) 138 "vf-ipsec", 139 #define IXGBE_PRIV_FLAGS_AUTO_DISABLE_VF BIT(2) 140 "mdd-disable-vf", 141 }; 142 143 #define IXGBE_PRIV_FLAGS_STR_LEN ARRAY_SIZE(ixgbe_priv_flags_strings) 144 145 #define ixgbe_isbackplane(type) ((type) == ixgbe_media_type_backplane) 146 147 static void ixgbe_set_supported_10gtypes(struct ixgbe_hw *hw, 148 struct ethtool_link_ksettings *cmd) 149 { 150 if (!ixgbe_isbackplane(hw->phy.media_type)) { 151 ethtool_link_ksettings_add_link_mode(cmd, supported, 152 10000baseT_Full); 153 return; 154 } 155 156 switch (hw->device_id) { 157 case IXGBE_DEV_ID_82598: 158 case IXGBE_DEV_ID_82599_KX4: 159 case IXGBE_DEV_ID_82599_KX4_MEZZ: 160 case IXGBE_DEV_ID_X550EM_X_KX4: 161 ethtool_link_ksettings_add_link_mode 162 (cmd, supported, 10000baseKX4_Full); 163 break; 164 case IXGBE_DEV_ID_82598_BX: 165 case IXGBE_DEV_ID_82599_KR: 166 case IXGBE_DEV_ID_X550EM_X_KR: 167 case IXGBE_DEV_ID_X550EM_X_XFI: 168 ethtool_link_ksettings_add_link_mode 169 (cmd, supported, 10000baseKR_Full); 170 break; 171 default: 172 ethtool_link_ksettings_add_link_mode 173 (cmd, supported, 10000baseKX4_Full); 174 ethtool_link_ksettings_add_link_mode 175 (cmd, supported, 10000baseKR_Full); 176 break; 177 } 178 } 179 180 static void ixgbe_set_advertising_10gtypes(struct ixgbe_hw *hw, 181 struct ethtool_link_ksettings *cmd) 182 { 183 if (!ixgbe_isbackplane(hw->phy.media_type)) { 184 ethtool_link_ksettings_add_link_mode(cmd, advertising, 185 10000baseT_Full); 186 return; 187 } 188 189 switch (hw->device_id) { 190 case IXGBE_DEV_ID_82598: 191 case IXGBE_DEV_ID_82599_KX4: 192 case IXGBE_DEV_ID_82599_KX4_MEZZ: 193 case IXGBE_DEV_ID_X550EM_X_KX4: 194 ethtool_link_ksettings_add_link_mode 195 (cmd, advertising, 10000baseKX4_Full); 196 break; 197 case IXGBE_DEV_ID_82598_BX: 198 case IXGBE_DEV_ID_82599_KR: 199 case IXGBE_DEV_ID_X550EM_X_KR: 200 case IXGBE_DEV_ID_X550EM_X_XFI: 201 ethtool_link_ksettings_add_link_mode 202 (cmd, advertising, 10000baseKR_Full); 203 break; 204 default: 205 ethtool_link_ksettings_add_link_mode 206 (cmd, advertising, 10000baseKX4_Full); 207 ethtool_link_ksettings_add_link_mode 208 (cmd, advertising, 10000baseKR_Full); 209 break; 210 } 211 } 212 213 static int ixgbe_get_link_ksettings(struct net_device *netdev, 214 struct ethtool_link_ksettings *cmd) 215 { 216 struct ixgbe_adapter *adapter = netdev_priv(netdev); 217 struct ixgbe_hw *hw = &adapter->hw; 218 ixgbe_link_speed supported_link; 219 bool autoneg = false; 220 221 ethtool_link_ksettings_zero_link_mode(cmd, supported); 222 ethtool_link_ksettings_zero_link_mode(cmd, advertising); 223 224 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg); 225 226 /* set the supported link speeds */ 227 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) { 228 ixgbe_set_supported_10gtypes(hw, cmd); 229 ixgbe_set_advertising_10gtypes(hw, cmd); 230 } 231 if (supported_link & IXGBE_LINK_SPEED_5GB_FULL) 232 ethtool_link_ksettings_add_link_mode(cmd, supported, 233 5000baseT_Full); 234 235 if (supported_link & IXGBE_LINK_SPEED_2_5GB_FULL) 236 ethtool_link_ksettings_add_link_mode(cmd, supported, 237 2500baseT_Full); 238 239 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL) { 240 if (ixgbe_isbackplane(hw->phy.media_type)) { 241 ethtool_link_ksettings_add_link_mode(cmd, supported, 242 1000baseKX_Full); 243 ethtool_link_ksettings_add_link_mode(cmd, advertising, 244 1000baseKX_Full); 245 } else { 246 ethtool_link_ksettings_add_link_mode(cmd, supported, 247 1000baseT_Full); 248 ethtool_link_ksettings_add_link_mode(cmd, advertising, 249 1000baseT_Full); 250 } 251 } 252 if (supported_link & IXGBE_LINK_SPEED_100_FULL) { 253 ethtool_link_ksettings_add_link_mode(cmd, supported, 254 100baseT_Full); 255 ethtool_link_ksettings_add_link_mode(cmd, advertising, 256 100baseT_Full); 257 } 258 if (supported_link & IXGBE_LINK_SPEED_10_FULL) { 259 ethtool_link_ksettings_add_link_mode(cmd, supported, 260 10baseT_Full); 261 ethtool_link_ksettings_add_link_mode(cmd, advertising, 262 10baseT_Full); 263 } 264 265 /* set the advertised speeds */ 266 if (hw->phy.autoneg_advertised) { 267 ethtool_link_ksettings_zero_link_mode(cmd, advertising); 268 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL) 269 ethtool_link_ksettings_add_link_mode(cmd, advertising, 270 10baseT_Full); 271 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 272 ethtool_link_ksettings_add_link_mode(cmd, advertising, 273 100baseT_Full); 274 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 275 ixgbe_set_advertising_10gtypes(hw, cmd); 276 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) { 277 if (ethtool_link_ksettings_test_link_mode 278 (cmd, supported, 1000baseKX_Full)) 279 ethtool_link_ksettings_add_link_mode 280 (cmd, advertising, 1000baseKX_Full); 281 else 282 ethtool_link_ksettings_add_link_mode 283 (cmd, advertising, 1000baseT_Full); 284 } 285 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) 286 ethtool_link_ksettings_add_link_mode(cmd, advertising, 287 5000baseT_Full); 288 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL) 289 ethtool_link_ksettings_add_link_mode(cmd, advertising, 290 2500baseT_Full); 291 } else { 292 if (hw->phy.multispeed_fiber && !autoneg) { 293 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) 294 ethtool_link_ksettings_add_link_mode 295 (cmd, advertising, 10000baseT_Full); 296 } 297 } 298 299 if (autoneg) { 300 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg); 301 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg); 302 cmd->base.autoneg = AUTONEG_ENABLE; 303 } else 304 cmd->base.autoneg = AUTONEG_DISABLE; 305 306 /* Determine the remaining settings based on the PHY type. */ 307 switch (adapter->hw.phy.type) { 308 case ixgbe_phy_tn: 309 case ixgbe_phy_aq: 310 case ixgbe_phy_x550em_ext_t: 311 case ixgbe_phy_fw: 312 case ixgbe_phy_cu_unknown: 313 ethtool_link_ksettings_add_link_mode(cmd, supported, TP); 314 ethtool_link_ksettings_add_link_mode(cmd, advertising, TP); 315 cmd->base.port = PORT_TP; 316 break; 317 case ixgbe_phy_qt: 318 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE); 319 ethtool_link_ksettings_add_link_mode(cmd, advertising, FIBRE); 320 cmd->base.port = PORT_FIBRE; 321 break; 322 case ixgbe_phy_nl: 323 case ixgbe_phy_sfp_passive_tyco: 324 case ixgbe_phy_sfp_passive_unknown: 325 case ixgbe_phy_sfp_ftl: 326 case ixgbe_phy_sfp_avago: 327 case ixgbe_phy_sfp_intel: 328 case ixgbe_phy_sfp_unknown: 329 case ixgbe_phy_qsfp_passive_unknown: 330 case ixgbe_phy_qsfp_active_unknown: 331 case ixgbe_phy_qsfp_intel: 332 case ixgbe_phy_qsfp_unknown: 333 /* SFP+ devices, further checking needed */ 334 switch (adapter->hw.phy.sfp_type) { 335 case ixgbe_sfp_type_da_cu: 336 case ixgbe_sfp_type_da_cu_core0: 337 case ixgbe_sfp_type_da_cu_core1: 338 ethtool_link_ksettings_add_link_mode(cmd, supported, 339 FIBRE); 340 ethtool_link_ksettings_add_link_mode(cmd, advertising, 341 FIBRE); 342 cmd->base.port = PORT_DA; 343 break; 344 case ixgbe_sfp_type_sr: 345 case ixgbe_sfp_type_lr: 346 case ixgbe_sfp_type_srlr_core0: 347 case ixgbe_sfp_type_srlr_core1: 348 case ixgbe_sfp_type_1g_sx_core0: 349 case ixgbe_sfp_type_1g_sx_core1: 350 case ixgbe_sfp_type_1g_lx_core0: 351 case ixgbe_sfp_type_1g_lx_core1: 352 case ixgbe_sfp_type_1g_bx_core0: 353 case ixgbe_sfp_type_1g_bx_core1: 354 ethtool_link_ksettings_add_link_mode(cmd, supported, 355 FIBRE); 356 ethtool_link_ksettings_add_link_mode(cmd, advertising, 357 FIBRE); 358 cmd->base.port = PORT_FIBRE; 359 break; 360 case ixgbe_sfp_type_not_present: 361 ethtool_link_ksettings_add_link_mode(cmd, supported, 362 FIBRE); 363 ethtool_link_ksettings_add_link_mode(cmd, advertising, 364 FIBRE); 365 cmd->base.port = PORT_NONE; 366 break; 367 case ixgbe_sfp_type_1g_cu_core0: 368 case ixgbe_sfp_type_1g_cu_core1: 369 ethtool_link_ksettings_add_link_mode(cmd, supported, 370 TP); 371 ethtool_link_ksettings_add_link_mode(cmd, advertising, 372 TP); 373 cmd->base.port = PORT_TP; 374 break; 375 case ixgbe_sfp_type_unknown: 376 default: 377 ethtool_link_ksettings_add_link_mode(cmd, supported, 378 FIBRE); 379 ethtool_link_ksettings_add_link_mode(cmd, advertising, 380 FIBRE); 381 cmd->base.port = PORT_OTHER; 382 break; 383 } 384 break; 385 case ixgbe_phy_xaui: 386 ethtool_link_ksettings_add_link_mode(cmd, supported, 387 FIBRE); 388 ethtool_link_ksettings_add_link_mode(cmd, advertising, 389 FIBRE); 390 cmd->base.port = PORT_NONE; 391 break; 392 case ixgbe_phy_unknown: 393 case ixgbe_phy_generic: 394 case ixgbe_phy_sfp_unsupported: 395 default: 396 ethtool_link_ksettings_add_link_mode(cmd, supported, 397 FIBRE); 398 ethtool_link_ksettings_add_link_mode(cmd, advertising, 399 FIBRE); 400 cmd->base.port = PORT_OTHER; 401 break; 402 } 403 404 /* Indicate pause support */ 405 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause); 406 407 switch (hw->fc.requested_mode) { 408 case ixgbe_fc_full: 409 ethtool_link_ksettings_add_link_mode(cmd, advertising, Pause); 410 break; 411 case ixgbe_fc_rx_pause: 412 ethtool_link_ksettings_add_link_mode(cmd, advertising, Pause); 413 ethtool_link_ksettings_add_link_mode(cmd, advertising, 414 Asym_Pause); 415 break; 416 case ixgbe_fc_tx_pause: 417 ethtool_link_ksettings_add_link_mode(cmd, advertising, 418 Asym_Pause); 419 break; 420 default: 421 ethtool_link_ksettings_del_link_mode(cmd, advertising, Pause); 422 ethtool_link_ksettings_del_link_mode(cmd, advertising, 423 Asym_Pause); 424 } 425 426 if (netif_carrier_ok(netdev)) { 427 switch (adapter->link_speed) { 428 case IXGBE_LINK_SPEED_10GB_FULL: 429 cmd->base.speed = SPEED_10000; 430 break; 431 case IXGBE_LINK_SPEED_5GB_FULL: 432 cmd->base.speed = SPEED_5000; 433 break; 434 case IXGBE_LINK_SPEED_2_5GB_FULL: 435 cmd->base.speed = SPEED_2500; 436 break; 437 case IXGBE_LINK_SPEED_1GB_FULL: 438 cmd->base.speed = SPEED_1000; 439 break; 440 case IXGBE_LINK_SPEED_100_FULL: 441 cmd->base.speed = SPEED_100; 442 break; 443 case IXGBE_LINK_SPEED_10_FULL: 444 cmd->base.speed = SPEED_10; 445 break; 446 default: 447 break; 448 } 449 cmd->base.duplex = DUPLEX_FULL; 450 } else { 451 cmd->base.speed = SPEED_UNKNOWN; 452 cmd->base.duplex = DUPLEX_UNKNOWN; 453 } 454 455 return 0; 456 } 457 458 static int ixgbe_set_link_ksettings(struct net_device *netdev, 459 const struct ethtool_link_ksettings *cmd) 460 { 461 struct ixgbe_adapter *adapter = netdev_priv(netdev); 462 struct ixgbe_hw *hw = &adapter->hw; 463 u32 advertised, old; 464 int err = 0; 465 466 if ((hw->phy.media_type == ixgbe_media_type_copper) || 467 (hw->phy.multispeed_fiber)) { 468 /* 469 * this function does not support duplex forcing, but can 470 * limit the advertising of the adapter to the specified speed 471 */ 472 if (!linkmode_subset(cmd->link_modes.advertising, 473 cmd->link_modes.supported)) 474 return -EINVAL; 475 476 /* only allow one speed at a time if no autoneg */ 477 if (!cmd->base.autoneg && hw->phy.multispeed_fiber) { 478 if (ethtool_link_ksettings_test_link_mode(cmd, advertising, 479 10000baseT_Full) && 480 ethtool_link_ksettings_test_link_mode(cmd, advertising, 481 1000baseT_Full)) 482 return -EINVAL; 483 } 484 485 old = hw->phy.autoneg_advertised; 486 advertised = 0; 487 if (ethtool_link_ksettings_test_link_mode(cmd, advertising, 488 10000baseT_Full)) 489 advertised |= IXGBE_LINK_SPEED_10GB_FULL; 490 if (ethtool_link_ksettings_test_link_mode(cmd, advertising, 491 5000baseT_Full)) 492 advertised |= IXGBE_LINK_SPEED_5GB_FULL; 493 if (ethtool_link_ksettings_test_link_mode(cmd, advertising, 494 2500baseT_Full)) 495 advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 496 if (ethtool_link_ksettings_test_link_mode(cmd, advertising, 497 1000baseT_Full)) 498 advertised |= IXGBE_LINK_SPEED_1GB_FULL; 499 500 if (ethtool_link_ksettings_test_link_mode(cmd, advertising, 501 100baseT_Full)) 502 advertised |= IXGBE_LINK_SPEED_100_FULL; 503 504 if (ethtool_link_ksettings_test_link_mode(cmd, advertising, 505 10baseT_Full)) 506 advertised |= IXGBE_LINK_SPEED_10_FULL; 507 508 if (old == advertised) 509 return err; 510 /* this sets the link speed and restarts auto-neg */ 511 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 512 usleep_range(1000, 2000); 513 514 hw->mac.autotry_restart = true; 515 err = hw->mac.ops.setup_link(hw, advertised, true); 516 if (err) { 517 e_info(probe, "setup link failed with code %d\n", err); 518 hw->mac.ops.setup_link(hw, old, true); 519 } 520 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 521 } else { 522 /* in this case we currently only support 10Gb/FULL */ 523 u32 speed = cmd->base.speed; 524 525 if ((cmd->base.autoneg == AUTONEG_ENABLE) || 526 (!ethtool_link_ksettings_test_link_mode(cmd, advertising, 527 10000baseT_Full)) || 528 (speed + cmd->base.duplex != SPEED_10000 + DUPLEX_FULL)) 529 return -EINVAL; 530 } 531 532 return err; 533 } 534 535 static void ixgbe_get_pause_stats(struct net_device *netdev, 536 struct ethtool_pause_stats *stats) 537 { 538 struct ixgbe_adapter *adapter = netdev_priv(netdev); 539 struct ixgbe_hw_stats *hwstats = &adapter->stats; 540 541 stats->tx_pause_frames = hwstats->lxontxc + hwstats->lxofftxc; 542 stats->rx_pause_frames = hwstats->lxonrxc + hwstats->lxoffrxc; 543 } 544 545 static void ixgbe_get_pauseparam(struct net_device *netdev, 546 struct ethtool_pauseparam *pause) 547 { 548 struct ixgbe_adapter *adapter = netdev_priv(netdev); 549 struct ixgbe_hw *hw = &adapter->hw; 550 551 if (ixgbe_device_supports_autoneg_fc(hw) && 552 !hw->fc.disable_fc_autoneg) 553 pause->autoneg = 1; 554 else 555 pause->autoneg = 0; 556 557 if (hw->fc.current_mode == ixgbe_fc_rx_pause) { 558 pause->rx_pause = 1; 559 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) { 560 pause->tx_pause = 1; 561 } else if (hw->fc.current_mode == ixgbe_fc_full) { 562 pause->rx_pause = 1; 563 pause->tx_pause = 1; 564 } 565 } 566 567 static int ixgbe_set_pauseparam(struct net_device *netdev, 568 struct ethtool_pauseparam *pause) 569 { 570 struct ixgbe_adapter *adapter = netdev_priv(netdev); 571 struct ixgbe_hw *hw = &adapter->hw; 572 struct ixgbe_fc_info fc = hw->fc; 573 574 /* 82598 does no support link flow control with DCB enabled */ 575 if ((hw->mac.type == ixgbe_mac_82598EB) && 576 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)) 577 return -EINVAL; 578 579 /* some devices do not support autoneg of link flow control */ 580 if ((pause->autoneg == AUTONEG_ENABLE) && 581 !ixgbe_device_supports_autoneg_fc(hw)) 582 return -EINVAL; 583 584 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE); 585 586 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg) 587 fc.requested_mode = ixgbe_fc_full; 588 else if (pause->rx_pause && !pause->tx_pause) 589 fc.requested_mode = ixgbe_fc_rx_pause; 590 else if (!pause->rx_pause && pause->tx_pause) 591 fc.requested_mode = ixgbe_fc_tx_pause; 592 else 593 fc.requested_mode = ixgbe_fc_none; 594 595 /* if the thing changed then we'll update and use new autoneg */ 596 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) { 597 hw->fc = fc; 598 if (netif_running(netdev)) 599 ixgbe_reinit_locked(adapter); 600 else 601 ixgbe_reset(adapter); 602 } 603 604 return 0; 605 } 606 607 static u32 ixgbe_get_msglevel(struct net_device *netdev) 608 { 609 struct ixgbe_adapter *adapter = netdev_priv(netdev); 610 return adapter->msg_enable; 611 } 612 613 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data) 614 { 615 struct ixgbe_adapter *adapter = netdev_priv(netdev); 616 adapter->msg_enable = data; 617 } 618 619 static int ixgbe_get_regs_len(struct net_device *netdev) 620 { 621 #define IXGBE_REGS_LEN 1145 622 return IXGBE_REGS_LEN * sizeof(u32); 623 } 624 625 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_ 626 627 static void ixgbe_get_regs(struct net_device *netdev, 628 struct ethtool_regs *regs, void *p) 629 { 630 struct ixgbe_adapter *adapter = netdev_priv(netdev); 631 struct ixgbe_hw *hw = &adapter->hw; 632 u32 *regs_buff = p; 633 u8 i; 634 635 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32)); 636 637 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 638 hw->device_id; 639 640 /* General Registers */ 641 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL); 642 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS); 643 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 644 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP); 645 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP); 646 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 647 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER); 648 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER); 649 650 /* NVM Register */ 651 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 652 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD); 653 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA(hw)); 654 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL); 655 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA); 656 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL); 657 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA); 658 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT); 659 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP); 660 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC(hw)); 661 662 /* Interrupt */ 663 /* don't read EICR because it can clear interrupt causes, instead 664 * read EICS which is a shadow but doesn't clear EICR */ 665 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS); 666 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS); 667 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS); 668 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC); 669 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC); 670 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM); 671 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0)); 672 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0)); 673 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT); 674 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA); 675 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0)); 676 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE); 677 678 /* Flow Control */ 679 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP); 680 for (i = 0; i < 4; i++) 681 regs_buff[31 + i] = IXGBE_READ_REG(hw, IXGBE_FCTTV(i)); 682 for (i = 0; i < 8; i++) { 683 switch (hw->mac.type) { 684 case ixgbe_mac_82598EB: 685 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i)); 686 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i)); 687 break; 688 case ixgbe_mac_82599EB: 689 case ixgbe_mac_X540: 690 case ixgbe_mac_X550: 691 case ixgbe_mac_X550EM_x: 692 case ixgbe_mac_x550em_a: 693 case ixgbe_mac_e610: 694 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i)); 695 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 696 break; 697 default: 698 break; 699 } 700 } 701 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV); 702 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS); 703 704 /* Receive DMA */ 705 for (i = 0; i < 64; i++) 706 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 707 for (i = 0; i < 64; i++) 708 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 709 for (i = 0; i < 64; i++) 710 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 711 for (i = 0; i < 64; i++) 712 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 713 for (i = 0; i < 64; i++) 714 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 715 for (i = 0; i < 64; i++) 716 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 717 for (i = 0; i < 16; i++) 718 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 719 for (i = 0; i < 16; i++) 720 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 721 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 722 for (i = 0; i < 8; i++) 723 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)); 724 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 725 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN); 726 727 /* Receive */ 728 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 729 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL); 730 for (i = 0; i < 16; i++) 731 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 732 for (i = 0; i < 16; i++) 733 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 734 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0)); 735 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL); 736 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 737 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL); 738 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC); 739 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 740 for (i = 0; i < 8; i++) 741 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i)); 742 for (i = 0; i < 8; i++) 743 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i)); 744 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP); 745 746 /* Transmit */ 747 for (i = 0; i < 32; i++) 748 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 749 for (i = 0; i < 32; i++) 750 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 751 for (i = 0; i < 32; i++) 752 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 753 for (i = 0; i < 32; i++) 754 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 755 for (i = 0; i < 32; i++) 756 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 757 for (i = 0; i < 32; i++) 758 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 759 for (i = 0; i < 32; i++) 760 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i)); 761 for (i = 0; i < 32; i++) 762 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i)); 763 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL); 764 for (i = 0; i < 16; i++) 765 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); 766 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG); 767 for (i = 0; i < 8; i++) 768 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i)); 769 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP); 770 771 /* Wake Up */ 772 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC); 773 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC); 774 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS); 775 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV); 776 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT); 777 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT); 778 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL); 779 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM); 780 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0)); 781 782 /* DCB */ 783 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); /* same as FCCFG */ 784 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); /* same as RTTPCS */ 785 786 switch (hw->mac.type) { 787 case ixgbe_mac_82598EB: 788 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS); 789 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR); 790 for (i = 0; i < 8; i++) 791 regs_buff[833 + i] = 792 IXGBE_READ_REG(hw, IXGBE_RT2CR(i)); 793 for (i = 0; i < 8; i++) 794 regs_buff[841 + i] = 795 IXGBE_READ_REG(hw, IXGBE_RT2SR(i)); 796 for (i = 0; i < 8; i++) 797 regs_buff[849 + i] = 798 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i)); 799 for (i = 0; i < 8; i++) 800 regs_buff[857 + i] = 801 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i)); 802 break; 803 case ixgbe_mac_82599EB: 804 case ixgbe_mac_X540: 805 case ixgbe_mac_X550: 806 case ixgbe_mac_X550EM_x: 807 case ixgbe_mac_x550em_a: 808 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 809 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS); 810 for (i = 0; i < 8; i++) 811 regs_buff[833 + i] = 812 IXGBE_READ_REG(hw, IXGBE_RTRPT4C(i)); 813 for (i = 0; i < 8; i++) 814 regs_buff[841 + i] = 815 IXGBE_READ_REG(hw, IXGBE_RTRPT4S(i)); 816 for (i = 0; i < 8; i++) 817 regs_buff[849 + i] = 818 IXGBE_READ_REG(hw, IXGBE_RTTDT2C(i)); 819 for (i = 0; i < 8; i++) 820 regs_buff[857 + i] = 821 IXGBE_READ_REG(hw, IXGBE_RTTDT2S(i)); 822 break; 823 default: 824 break; 825 } 826 827 for (i = 0; i < 8; i++) 828 regs_buff[865 + i] = 829 IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); /* same as RTTPT2C */ 830 for (i = 0; i < 8; i++) 831 regs_buff[873 + i] = 832 IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); /* same as RTTPT2S */ 833 834 /* Statistics */ 835 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs); 836 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc); 837 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc); 838 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc); 839 for (i = 0; i < 8; i++) 840 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]); 841 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc); 842 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc); 843 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec); 844 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc); 845 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc); 846 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc); 847 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc); 848 for (i = 0; i < 8; i++) 849 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]); 850 for (i = 0; i < 8; i++) 851 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]); 852 for (i = 0; i < 8; i++) 853 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]); 854 for (i = 0; i < 8; i++) 855 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]); 856 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64); 857 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127); 858 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255); 859 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511); 860 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023); 861 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522); 862 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc); 863 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc); 864 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc); 865 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc); 866 regs_buff[942] = (u32)IXGBE_GET_STAT(adapter, gorc); 867 regs_buff[943] = (u32)(IXGBE_GET_STAT(adapter, gorc) >> 32); 868 regs_buff[944] = (u32)IXGBE_GET_STAT(adapter, gotc); 869 regs_buff[945] = (u32)(IXGBE_GET_STAT(adapter, gotc) >> 32); 870 for (i = 0; i < 8; i++) 871 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]); 872 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc); 873 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc); 874 regs_buff[956] = IXGBE_GET_STAT(adapter, roc); 875 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc); 876 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc); 877 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc); 878 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc); 879 regs_buff[961] = (u32)IXGBE_GET_STAT(adapter, tor); 880 regs_buff[962] = (u32)(IXGBE_GET_STAT(adapter, tor) >> 32); 881 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr); 882 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt); 883 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64); 884 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127); 885 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255); 886 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511); 887 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023); 888 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522); 889 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc); 890 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc); 891 regs_buff[973] = IXGBE_GET_STAT(adapter, xec); 892 for (i = 0; i < 16; i++) 893 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]); 894 for (i = 0; i < 16; i++) 895 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]); 896 for (i = 0; i < 16; i++) 897 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]); 898 for (i = 0; i < 16; i++) 899 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]); 900 901 /* MAC */ 902 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG); 903 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 904 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 905 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0); 906 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1); 907 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 908 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 909 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP); 910 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP); 911 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0); 912 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1); 913 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP); 914 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA); 915 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE); 916 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD); 917 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS); 918 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA); 919 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD); 920 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD); 921 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD); 922 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG); 923 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1); 924 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2); 925 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS); 926 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC); 927 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS); 928 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC); 929 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS); 930 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 931 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3); 932 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1); 933 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2); 934 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 935 936 /* Diagnostic */ 937 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL); 938 for (i = 0; i < 8; i++) 939 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i)); 940 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN); 941 for (i = 0; i < 4; i++) 942 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i)); 943 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE); 944 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL); 945 for (i = 0; i < 8; i++) 946 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i)); 947 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN); 948 for (i = 0; i < 4; i++) 949 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i)); 950 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE); 951 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL); 952 for (i = 0; i < 4; i++) 953 regs_buff[1102 + i] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA(i)); 954 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL); 955 for (i = 0; i < 4; i++) 956 regs_buff[1107 + i] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA(i)); 957 for (i = 0; i < 8; i++) 958 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i)); 959 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL); 960 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1); 961 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2); 962 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1); 963 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2); 964 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS); 965 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL); 966 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC); 967 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC); 968 969 /* 82599 X540 specific registers */ 970 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN); 971 972 /* 82599 X540 specific DCB registers */ 973 regs_buff[1129] = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 974 regs_buff[1130] = IXGBE_READ_REG(hw, IXGBE_RTTUP2TC); 975 for (i = 0; i < 4; i++) 976 regs_buff[1131 + i] = IXGBE_READ_REG(hw, IXGBE_TXLLQ(i)); 977 regs_buff[1135] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRM); 978 /* same as RTTQCNRM */ 979 regs_buff[1136] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRD); 980 /* same as RTTQCNRR */ 981 982 /* X540 specific DCB registers */ 983 regs_buff[1137] = IXGBE_READ_REG(hw, IXGBE_RTTQCNCR); 984 regs_buff[1138] = IXGBE_READ_REG(hw, IXGBE_RTTQCNTG); 985 986 /* Security config registers */ 987 regs_buff[1139] = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 988 regs_buff[1140] = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT); 989 regs_buff[1141] = IXGBE_READ_REG(hw, IXGBE_SECTXBUFFAF); 990 regs_buff[1142] = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 991 regs_buff[1143] = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 992 regs_buff[1144] = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 993 } 994 995 static int ixgbe_get_eeprom_len(struct net_device *netdev) 996 { 997 struct ixgbe_adapter *adapter = netdev_priv(netdev); 998 return adapter->hw.eeprom.word_size * 2; 999 } 1000 1001 static int ixgbe_get_eeprom(struct net_device *netdev, 1002 struct ethtool_eeprom *eeprom, u8 *bytes) 1003 { 1004 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1005 struct ixgbe_hw *hw = &adapter->hw; 1006 u16 *eeprom_buff; 1007 int first_word, last_word, eeprom_len; 1008 int ret_val = 0; 1009 u16 i; 1010 1011 if (eeprom->len == 0) 1012 return -EINVAL; 1013 1014 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 1015 1016 first_word = eeprom->offset >> 1; 1017 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 1018 eeprom_len = last_word - first_word + 1; 1019 1020 eeprom_buff = kmalloc_array(eeprom_len, sizeof(u16), GFP_KERNEL); 1021 if (!eeprom_buff) 1022 return -ENOMEM; 1023 1024 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len, 1025 eeprom_buff); 1026 1027 /* Device's eeprom is always little-endian, word addressable */ 1028 for (i = 0; i < eeprom_len; i++) 1029 le16_to_cpus(&eeprom_buff[i]); 1030 1031 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len); 1032 kfree(eeprom_buff); 1033 1034 return ret_val; 1035 } 1036 1037 static int ixgbe_set_eeprom(struct net_device *netdev, 1038 struct ethtool_eeprom *eeprom, u8 *bytes) 1039 { 1040 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1041 struct ixgbe_hw *hw = &adapter->hw; 1042 u16 *eeprom_buff; 1043 void *ptr; 1044 int max_len, first_word, last_word, ret_val = 0; 1045 u16 i; 1046 1047 if (eeprom->len == 0) 1048 return -EINVAL; 1049 1050 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 1051 return -EINVAL; 1052 1053 max_len = hw->eeprom.word_size * 2; 1054 1055 first_word = eeprom->offset >> 1; 1056 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 1057 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 1058 if (!eeprom_buff) 1059 return -ENOMEM; 1060 1061 ptr = eeprom_buff; 1062 1063 if (eeprom->offset & 1) { 1064 /* 1065 * need read/modify/write of first changed EEPROM word 1066 * only the second byte of the word is being modified 1067 */ 1068 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]); 1069 if (ret_val) 1070 goto err; 1071 1072 ptr++; 1073 } 1074 if ((eeprom->offset + eeprom->len) & 1) { 1075 /* 1076 * need read/modify/write of last changed EEPROM word 1077 * only the first byte of the word is being modified 1078 */ 1079 ret_val = hw->eeprom.ops.read(hw, last_word, 1080 &eeprom_buff[last_word - first_word]); 1081 if (ret_val) 1082 goto err; 1083 } 1084 1085 /* Device's eeprom is always little-endian, word addressable */ 1086 for (i = 0; i < last_word - first_word + 1; i++) 1087 le16_to_cpus(&eeprom_buff[i]); 1088 1089 memcpy(ptr, bytes, eeprom->len); 1090 1091 for (i = 0; i < last_word - first_word + 1; i++) 1092 cpu_to_le16s(&eeprom_buff[i]); 1093 1094 ret_val = hw->eeprom.ops.write_buffer(hw, first_word, 1095 last_word - first_word + 1, 1096 eeprom_buff); 1097 1098 /* Update the checksum */ 1099 if (ret_val == 0) 1100 hw->eeprom.ops.update_checksum(hw); 1101 1102 err: 1103 kfree(eeprom_buff); 1104 return ret_val; 1105 } 1106 1107 static void ixgbe_get_drvinfo(struct net_device *netdev, 1108 struct ethtool_drvinfo *drvinfo) 1109 { 1110 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1111 1112 strscpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver)); 1113 1114 strscpy(drvinfo->fw_version, adapter->eeprom_id, 1115 sizeof(drvinfo->fw_version)); 1116 1117 strscpy(drvinfo->bus_info, pci_name(adapter->pdev), 1118 sizeof(drvinfo->bus_info)); 1119 1120 drvinfo->n_priv_flags = IXGBE_PRIV_FLAGS_STR_LEN; 1121 } 1122 1123 static u32 ixgbe_get_max_rxd(struct ixgbe_adapter *adapter) 1124 { 1125 switch (adapter->hw.mac.type) { 1126 case ixgbe_mac_82598EB: 1127 return IXGBE_MAX_RXD_82598; 1128 case ixgbe_mac_82599EB: 1129 return IXGBE_MAX_RXD_82599; 1130 case ixgbe_mac_X540: 1131 return IXGBE_MAX_RXD_X540; 1132 case ixgbe_mac_X550: 1133 case ixgbe_mac_X550EM_x: 1134 case ixgbe_mac_x550em_a: 1135 return IXGBE_MAX_RXD_X550; 1136 default: 1137 return IXGBE_MAX_RXD_82598; 1138 } 1139 } 1140 1141 static u32 ixgbe_get_max_txd(struct ixgbe_adapter *adapter) 1142 { 1143 switch (adapter->hw.mac.type) { 1144 case ixgbe_mac_82598EB: 1145 return IXGBE_MAX_TXD_82598; 1146 case ixgbe_mac_82599EB: 1147 return IXGBE_MAX_TXD_82599; 1148 case ixgbe_mac_X540: 1149 return IXGBE_MAX_TXD_X540; 1150 case ixgbe_mac_X550: 1151 case ixgbe_mac_X550EM_x: 1152 case ixgbe_mac_x550em_a: 1153 return IXGBE_MAX_TXD_X550; 1154 default: 1155 return IXGBE_MAX_TXD_82598; 1156 } 1157 } 1158 1159 static void ixgbe_get_ringparam(struct net_device *netdev, 1160 struct ethtool_ringparam *ring, 1161 struct kernel_ethtool_ringparam *kernel_ring, 1162 struct netlink_ext_ack *extack) 1163 { 1164 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1165 struct ixgbe_ring *tx_ring = adapter->tx_ring[0]; 1166 struct ixgbe_ring *rx_ring = adapter->rx_ring[0]; 1167 1168 ring->rx_max_pending = ixgbe_get_max_rxd(adapter); 1169 ring->tx_max_pending = ixgbe_get_max_txd(adapter); 1170 ring->rx_pending = rx_ring->count; 1171 ring->tx_pending = tx_ring->count; 1172 } 1173 1174 static int ixgbe_set_ringparam(struct net_device *netdev, 1175 struct ethtool_ringparam *ring, 1176 struct kernel_ethtool_ringparam *kernel_ring, 1177 struct netlink_ext_ack *extack) 1178 { 1179 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1180 struct ixgbe_ring *temp_ring; 1181 int i, j, err = 0; 1182 u32 new_rx_count, new_tx_count; 1183 1184 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 1185 return -EINVAL; 1186 1187 new_tx_count = clamp_t(u32, ring->tx_pending, 1188 IXGBE_MIN_TXD, ixgbe_get_max_txd(adapter)); 1189 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE); 1190 1191 new_rx_count = clamp_t(u32, ring->rx_pending, 1192 IXGBE_MIN_RXD, ixgbe_get_max_rxd(adapter)); 1193 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE); 1194 1195 if ((new_tx_count == adapter->tx_ring_count) && 1196 (new_rx_count == adapter->rx_ring_count)) { 1197 /* nothing to do */ 1198 return 0; 1199 } 1200 1201 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 1202 usleep_range(1000, 2000); 1203 1204 if (!netif_running(adapter->netdev)) { 1205 for (i = 0; i < adapter->num_tx_queues; i++) 1206 adapter->tx_ring[i]->count = new_tx_count; 1207 for (i = 0; i < adapter->num_xdp_queues; i++) 1208 adapter->xdp_ring[i]->count = new_tx_count; 1209 for (i = 0; i < adapter->num_rx_queues; i++) 1210 adapter->rx_ring[i]->count = new_rx_count; 1211 adapter->tx_ring_count = new_tx_count; 1212 adapter->xdp_ring_count = new_tx_count; 1213 adapter->rx_ring_count = new_rx_count; 1214 goto clear_reset; 1215 } 1216 1217 /* allocate temporary buffer to store rings in */ 1218 i = max_t(int, adapter->num_tx_queues + adapter->num_xdp_queues, 1219 adapter->num_rx_queues); 1220 temp_ring = vmalloc(array_size(i, sizeof(struct ixgbe_ring))); 1221 1222 if (!temp_ring) { 1223 err = -ENOMEM; 1224 goto clear_reset; 1225 } 1226 1227 ixgbe_down(adapter); 1228 1229 /* 1230 * Setup new Tx resources and free the old Tx resources in that order. 1231 * We can then assign the new resources to the rings via a memcpy. 1232 * The advantage to this approach is that we are guaranteed to still 1233 * have resources even in the case of an allocation failure. 1234 */ 1235 if (new_tx_count != adapter->tx_ring_count) { 1236 for (i = 0; i < adapter->num_tx_queues; i++) { 1237 memcpy(&temp_ring[i], adapter->tx_ring[i], 1238 sizeof(struct ixgbe_ring)); 1239 1240 temp_ring[i].count = new_tx_count; 1241 err = ixgbe_setup_tx_resources(&temp_ring[i]); 1242 if (err) { 1243 while (i) { 1244 i--; 1245 ixgbe_free_tx_resources(&temp_ring[i]); 1246 } 1247 goto err_setup; 1248 } 1249 } 1250 1251 for (j = 0; j < adapter->num_xdp_queues; j++, i++) { 1252 memcpy(&temp_ring[i], adapter->xdp_ring[j], 1253 sizeof(struct ixgbe_ring)); 1254 1255 temp_ring[i].count = new_tx_count; 1256 err = ixgbe_setup_tx_resources(&temp_ring[i]); 1257 if (err) { 1258 while (i) { 1259 i--; 1260 ixgbe_free_tx_resources(&temp_ring[i]); 1261 } 1262 goto err_setup; 1263 } 1264 } 1265 1266 for (i = 0; i < adapter->num_tx_queues; i++) { 1267 ixgbe_free_tx_resources(adapter->tx_ring[i]); 1268 1269 memcpy(adapter->tx_ring[i], &temp_ring[i], 1270 sizeof(struct ixgbe_ring)); 1271 } 1272 for (j = 0; j < adapter->num_xdp_queues; j++, i++) { 1273 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 1274 1275 memcpy(adapter->xdp_ring[j], &temp_ring[i], 1276 sizeof(struct ixgbe_ring)); 1277 } 1278 1279 adapter->tx_ring_count = new_tx_count; 1280 } 1281 1282 /* Repeat the process for the Rx rings if needed */ 1283 if (new_rx_count != adapter->rx_ring_count) { 1284 for (i = 0; i < adapter->num_rx_queues; i++) { 1285 memcpy(&temp_ring[i], adapter->rx_ring[i], 1286 sizeof(struct ixgbe_ring)); 1287 1288 /* Clear copied XDP RX-queue info */ 1289 memset(&temp_ring[i].xdp_rxq, 0, 1290 sizeof(temp_ring[i].xdp_rxq)); 1291 1292 temp_ring[i].count = new_rx_count; 1293 err = ixgbe_setup_rx_resources(adapter, &temp_ring[i]); 1294 if (err) { 1295 while (i) { 1296 i--; 1297 ixgbe_free_rx_resources(&temp_ring[i]); 1298 } 1299 goto err_setup; 1300 } 1301 1302 } 1303 1304 for (i = 0; i < adapter->num_rx_queues; i++) { 1305 ixgbe_free_rx_resources(adapter->rx_ring[i]); 1306 1307 memcpy(adapter->rx_ring[i], &temp_ring[i], 1308 sizeof(struct ixgbe_ring)); 1309 } 1310 1311 adapter->rx_ring_count = new_rx_count; 1312 } 1313 1314 err_setup: 1315 ixgbe_up(adapter); 1316 vfree(temp_ring); 1317 clear_reset: 1318 clear_bit(__IXGBE_RESETTING, &adapter->state); 1319 return err; 1320 } 1321 1322 static int ixgbe_get_sset_count(struct net_device *netdev, int sset) 1323 { 1324 switch (sset) { 1325 case ETH_SS_TEST: 1326 return IXGBE_TEST_LEN; 1327 case ETH_SS_STATS: 1328 return IXGBE_STATS_LEN; 1329 case ETH_SS_PRIV_FLAGS: 1330 return IXGBE_PRIV_FLAGS_STR_LEN; 1331 default: 1332 return -EOPNOTSUPP; 1333 } 1334 } 1335 1336 static void ixgbe_get_ethtool_stats(struct net_device *netdev, 1337 struct ethtool_stats *stats, u64 *data) 1338 { 1339 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1340 struct rtnl_link_stats64 temp; 1341 const struct rtnl_link_stats64 *net_stats; 1342 unsigned int start; 1343 struct ixgbe_ring *ring; 1344 int i, j; 1345 char *p = NULL; 1346 1347 ixgbe_update_stats(adapter); 1348 net_stats = dev_get_stats(netdev, &temp); 1349 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 1350 switch (ixgbe_gstrings_stats[i].type) { 1351 case NETDEV_STATS: 1352 p = (char *) net_stats + 1353 ixgbe_gstrings_stats[i].stat_offset; 1354 break; 1355 case IXGBE_STATS: 1356 p = (char *) adapter + 1357 ixgbe_gstrings_stats[i].stat_offset; 1358 break; 1359 default: 1360 data[i] = 0; 1361 continue; 1362 } 1363 1364 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat == 1365 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 1366 } 1367 for (j = 0; j < netdev->num_tx_queues; j++) { 1368 ring = adapter->tx_ring[j]; 1369 if (!ring) { 1370 data[i] = 0; 1371 data[i+1] = 0; 1372 i += 2; 1373 continue; 1374 } 1375 1376 do { 1377 start = u64_stats_fetch_begin(&ring->syncp); 1378 data[i] = ring->stats.packets; 1379 data[i+1] = ring->stats.bytes; 1380 } while (u64_stats_fetch_retry(&ring->syncp, start)); 1381 i += 2; 1382 } 1383 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) { 1384 ring = adapter->rx_ring[j]; 1385 if (!ring) { 1386 data[i] = 0; 1387 data[i+1] = 0; 1388 i += 2; 1389 continue; 1390 } 1391 1392 do { 1393 start = u64_stats_fetch_begin(&ring->syncp); 1394 data[i] = ring->stats.packets; 1395 data[i+1] = ring->stats.bytes; 1396 } while (u64_stats_fetch_retry(&ring->syncp, start)); 1397 i += 2; 1398 } 1399 1400 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) { 1401 data[i++] = adapter->stats.pxontxc[j]; 1402 data[i++] = adapter->stats.pxofftxc[j]; 1403 } 1404 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) { 1405 data[i++] = adapter->stats.pxonrxc[j]; 1406 data[i++] = adapter->stats.pxoffrxc[j]; 1407 } 1408 } 1409 1410 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset, 1411 u8 *data) 1412 { 1413 unsigned int i; 1414 u8 *p = data; 1415 1416 switch (stringset) { 1417 case ETH_SS_TEST: 1418 for (i = 0; i < IXGBE_TEST_LEN; i++) 1419 ethtool_puts(&p, ixgbe_gstrings_test[i]); 1420 break; 1421 case ETH_SS_STATS: 1422 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) 1423 ethtool_puts(&p, ixgbe_gstrings_stats[i].stat_string); 1424 for (i = 0; i < netdev->num_tx_queues; i++) { 1425 ethtool_sprintf(&p, "tx_queue_%u_packets", i); 1426 ethtool_sprintf(&p, "tx_queue_%u_bytes", i); 1427 } 1428 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) { 1429 ethtool_sprintf(&p, "rx_queue_%u_packets", i); 1430 ethtool_sprintf(&p, "rx_queue_%u_bytes", i); 1431 } 1432 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 1433 ethtool_sprintf(&p, "tx_pb_%u_pxon", i); 1434 ethtool_sprintf(&p, "tx_pb_%u_pxoff", i); 1435 } 1436 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 1437 ethtool_sprintf(&p, "rx_pb_%u_pxon", i); 1438 ethtool_sprintf(&p, "rx_pb_%u_pxoff", i); 1439 } 1440 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */ 1441 break; 1442 case ETH_SS_PRIV_FLAGS: 1443 memcpy(data, ixgbe_priv_flags_strings, 1444 IXGBE_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN); 1445 } 1446 } 1447 1448 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data) 1449 { 1450 struct ixgbe_hw *hw = &adapter->hw; 1451 bool link_up; 1452 u32 link_speed = 0; 1453 1454 if (ixgbe_removed(hw->hw_addr)) { 1455 *data = 1; 1456 return 1; 1457 } 1458 *data = 0; 1459 1460 hw->mac.ops.check_link(hw, &link_speed, &link_up, true); 1461 if (link_up) 1462 return *data; 1463 else 1464 *data = 1; 1465 return *data; 1466 } 1467 1468 /* ethtool register test data */ 1469 struct ixgbe_reg_test { 1470 u16 reg; 1471 u8 array_len; 1472 u8 test_type; 1473 u32 mask; 1474 u32 write; 1475 }; 1476 1477 /* In the hardware, registers are laid out either singly, in arrays 1478 * spaced 0x40 bytes apart, or in contiguous tables. We assume 1479 * most tests take place on arrays or single registers (handled 1480 * as a single-element array) and special-case the tables. 1481 * Table tests are always pattern tests. 1482 * 1483 * We also make provision for some required setup steps by specifying 1484 * registers to be written without any read-back testing. 1485 */ 1486 1487 #define PATTERN_TEST 1 1488 #define SET_READ_TEST 2 1489 #define WRITE_NO_TEST 3 1490 #define TABLE32_TEST 4 1491 #define TABLE64_TEST_LO 5 1492 #define TABLE64_TEST_HI 6 1493 1494 /* default 82599 register test */ 1495 static const struct ixgbe_reg_test reg_test_82599[] = { 1496 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1497 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1498 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1499 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1500 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 }, 1501 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1502 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1503 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1504 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1505 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1506 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1507 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1508 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1509 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1510 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 }, 1511 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 }, 1512 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1513 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF }, 1514 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1515 { .reg = 0 } 1516 }; 1517 1518 /* default 82598 register test */ 1519 static const struct ixgbe_reg_test reg_test_82598[] = { 1520 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1521 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1522 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1523 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1524 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1525 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1526 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1527 /* Enable all four RX queues before testing. */ 1528 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1529 /* RDH is read-only for 82598, only test RDT. */ 1530 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1531 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1532 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1533 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1534 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF }, 1535 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1536 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1537 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1538 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 }, 1539 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 }, 1540 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1541 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF }, 1542 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1543 { .reg = 0 } 1544 }; 1545 1546 static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg, 1547 u32 mask, u32 write) 1548 { 1549 u32 pat, val, before; 1550 static const u32 test_pattern[] = { 1551 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1552 1553 if (ixgbe_removed(adapter->hw.hw_addr)) { 1554 *data = 1; 1555 return true; 1556 } 1557 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) { 1558 before = ixgbe_read_reg(&adapter->hw, reg); 1559 ixgbe_write_reg(&adapter->hw, reg, test_pattern[pat] & write); 1560 val = ixgbe_read_reg(&adapter->hw, reg); 1561 if (val != (test_pattern[pat] & write & mask)) { 1562 e_err(drv, "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n", 1563 reg, val, (test_pattern[pat] & write & mask)); 1564 *data = reg; 1565 ixgbe_write_reg(&adapter->hw, reg, before); 1566 return true; 1567 } 1568 ixgbe_write_reg(&adapter->hw, reg, before); 1569 } 1570 return false; 1571 } 1572 1573 static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg, 1574 u32 mask, u32 write) 1575 { 1576 u32 val, before; 1577 1578 if (ixgbe_removed(adapter->hw.hw_addr)) { 1579 *data = 1; 1580 return true; 1581 } 1582 before = ixgbe_read_reg(&adapter->hw, reg); 1583 ixgbe_write_reg(&adapter->hw, reg, write & mask); 1584 val = ixgbe_read_reg(&adapter->hw, reg); 1585 if ((write & mask) != (val & mask)) { 1586 e_err(drv, "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", 1587 reg, (val & mask), (write & mask)); 1588 *data = reg; 1589 ixgbe_write_reg(&adapter->hw, reg, before); 1590 return true; 1591 } 1592 ixgbe_write_reg(&adapter->hw, reg, before); 1593 return false; 1594 } 1595 1596 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data) 1597 { 1598 const struct ixgbe_reg_test *test; 1599 u32 value, before, after; 1600 u32 i, toggle; 1601 1602 if (ixgbe_removed(adapter->hw.hw_addr)) { 1603 e_err(drv, "Adapter removed - register test blocked\n"); 1604 *data = 1; 1605 return 1; 1606 } 1607 switch (adapter->hw.mac.type) { 1608 case ixgbe_mac_82598EB: 1609 toggle = 0x7FFFF3FF; 1610 test = reg_test_82598; 1611 break; 1612 case ixgbe_mac_82599EB: 1613 case ixgbe_mac_X540: 1614 case ixgbe_mac_X550: 1615 case ixgbe_mac_X550EM_x: 1616 case ixgbe_mac_x550em_a: 1617 case ixgbe_mac_e610: 1618 toggle = 0x7FFFF30F; 1619 test = reg_test_82599; 1620 break; 1621 default: 1622 *data = 1; 1623 return 1; 1624 } 1625 1626 /* 1627 * Because the status register is such a special case, 1628 * we handle it separately from the rest of the register 1629 * tests. Some bits are read-only, some toggle, and some 1630 * are writeable on newer MACs. 1631 */ 1632 before = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS); 1633 value = (ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle); 1634 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, toggle); 1635 after = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle; 1636 if (value != after) { 1637 e_err(drv, "failed STATUS register test got: 0x%08X expected: 0x%08X\n", 1638 after, value); 1639 *data = 1; 1640 return 1; 1641 } 1642 /* restore previous status */ 1643 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, before); 1644 1645 /* 1646 * Perform the remainder of the register test, looping through 1647 * the test table until we either fail or reach the null entry. 1648 */ 1649 while (test->reg) { 1650 for (i = 0; i < test->array_len; i++) { 1651 bool b = false; 1652 1653 switch (test->test_type) { 1654 case PATTERN_TEST: 1655 b = reg_pattern_test(adapter, data, 1656 test->reg + (i * 0x40), 1657 test->mask, 1658 test->write); 1659 break; 1660 case SET_READ_TEST: 1661 b = reg_set_and_check(adapter, data, 1662 test->reg + (i * 0x40), 1663 test->mask, 1664 test->write); 1665 break; 1666 case WRITE_NO_TEST: 1667 ixgbe_write_reg(&adapter->hw, 1668 test->reg + (i * 0x40), 1669 test->write); 1670 break; 1671 case TABLE32_TEST: 1672 b = reg_pattern_test(adapter, data, 1673 test->reg + (i * 4), 1674 test->mask, 1675 test->write); 1676 break; 1677 case TABLE64_TEST_LO: 1678 b = reg_pattern_test(adapter, data, 1679 test->reg + (i * 8), 1680 test->mask, 1681 test->write); 1682 break; 1683 case TABLE64_TEST_HI: 1684 b = reg_pattern_test(adapter, data, 1685 (test->reg + 4) + (i * 8), 1686 test->mask, 1687 test->write); 1688 break; 1689 } 1690 if (b) 1691 return 1; 1692 } 1693 test++; 1694 } 1695 1696 *data = 0; 1697 return 0; 1698 } 1699 1700 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data) 1701 { 1702 struct ixgbe_hw *hw = &adapter->hw; 1703 if (hw->eeprom.ops.validate_checksum(hw, NULL)) 1704 *data = 1; 1705 else 1706 *data = 0; 1707 return *data; 1708 } 1709 1710 static irqreturn_t ixgbe_test_intr(int irq, void *data) 1711 { 1712 struct net_device *netdev = (struct net_device *) data; 1713 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1714 1715 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR); 1716 1717 return IRQ_HANDLED; 1718 } 1719 1720 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data) 1721 { 1722 struct net_device *netdev = adapter->netdev; 1723 u32 mask, i = 0, shared_int = true; 1724 u32 irq = adapter->pdev->irq; 1725 1726 *data = 0; 1727 1728 /* Hook up test interrupt handler just for this test */ 1729 if (adapter->msix_entries) { 1730 /* NOTE: we don't test MSI-X interrupts here, yet */ 1731 return 0; 1732 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { 1733 shared_int = false; 1734 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name, 1735 netdev)) { 1736 *data = 1; 1737 return -1; 1738 } 1739 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED, 1740 netdev->name, netdev)) { 1741 shared_int = false; 1742 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED, 1743 netdev->name, netdev)) { 1744 *data = 1; 1745 return -1; 1746 } 1747 e_info(hw, "testing %s interrupt\n", shared_int ? 1748 "shared" : "unshared"); 1749 1750 /* Disable all the interrupts */ 1751 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1752 IXGBE_WRITE_FLUSH(&adapter->hw); 1753 usleep_range(10000, 20000); 1754 1755 /* Test each interrupt */ 1756 for (; i < 10; i++) { 1757 /* Interrupt to test */ 1758 mask = BIT(i); 1759 1760 if (!shared_int) { 1761 /* 1762 * Disable the interrupts to be reported in 1763 * the cause register and then force the same 1764 * interrupt and see if one gets posted. If 1765 * an interrupt was posted to the bus, the 1766 * test failed. 1767 */ 1768 adapter->test_icr = 0; 1769 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 1770 ~mask & 0x00007FFF); 1771 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1772 ~mask & 0x00007FFF); 1773 IXGBE_WRITE_FLUSH(&adapter->hw); 1774 usleep_range(10000, 20000); 1775 1776 if (adapter->test_icr & mask) { 1777 *data = 3; 1778 break; 1779 } 1780 } 1781 1782 /* 1783 * Enable the interrupt to be reported in the cause 1784 * register and then force the same interrupt and see 1785 * if one gets posted. If an interrupt was not posted 1786 * to the bus, the test failed. 1787 */ 1788 adapter->test_icr = 0; 1789 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 1790 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 1791 IXGBE_WRITE_FLUSH(&adapter->hw); 1792 usleep_range(10000, 20000); 1793 1794 if (!(adapter->test_icr & mask)) { 1795 *data = 4; 1796 break; 1797 } 1798 1799 if (!shared_int) { 1800 /* 1801 * Disable the other interrupts to be reported in 1802 * the cause register and then force the other 1803 * interrupts and see if any get posted. If 1804 * an interrupt was posted to the bus, the 1805 * test failed. 1806 */ 1807 adapter->test_icr = 0; 1808 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 1809 ~mask & 0x00007FFF); 1810 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1811 ~mask & 0x00007FFF); 1812 IXGBE_WRITE_FLUSH(&adapter->hw); 1813 usleep_range(10000, 20000); 1814 1815 if (adapter->test_icr) { 1816 *data = 5; 1817 break; 1818 } 1819 } 1820 } 1821 1822 /* Disable all the interrupts */ 1823 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1824 IXGBE_WRITE_FLUSH(&adapter->hw); 1825 usleep_range(10000, 20000); 1826 1827 /* Unhook test interrupt handler */ 1828 free_irq(irq, netdev); 1829 1830 return *data; 1831 } 1832 1833 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter) 1834 { 1835 /* Shut down the DMA engines now so they can be reinitialized later, 1836 * since the test rings and normally used rings should overlap on 1837 * queue 0 we can just use the standard disable Rx/Tx calls and they 1838 * will take care of disabling the test rings for us. 1839 */ 1840 1841 /* first Rx */ 1842 ixgbe_disable_rx(adapter); 1843 1844 /* now Tx */ 1845 ixgbe_disable_tx(adapter); 1846 1847 ixgbe_reset(adapter); 1848 1849 ixgbe_free_tx_resources(&adapter->test_tx_ring); 1850 ixgbe_free_rx_resources(&adapter->test_rx_ring); 1851 } 1852 1853 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter) 1854 { 1855 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1856 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1857 struct ixgbe_hw *hw = &adapter->hw; 1858 u32 rctl, reg_data; 1859 int ret_val; 1860 int err; 1861 1862 /* Setup Tx descriptor ring and Tx buffers */ 1863 tx_ring->count = IXGBE_DEFAULT_TXD; 1864 tx_ring->queue_index = 0; 1865 tx_ring->dev = &adapter->pdev->dev; 1866 tx_ring->netdev = adapter->netdev; 1867 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx; 1868 1869 err = ixgbe_setup_tx_resources(tx_ring); 1870 if (err) 1871 return 1; 1872 1873 switch (adapter->hw.mac.type) { 1874 case ixgbe_mac_82599EB: 1875 case ixgbe_mac_X540: 1876 case ixgbe_mac_X550: 1877 case ixgbe_mac_X550EM_x: 1878 case ixgbe_mac_x550em_a: 1879 case ixgbe_mac_e610: 1880 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL); 1881 reg_data |= IXGBE_DMATXCTL_TE; 1882 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data); 1883 break; 1884 default: 1885 break; 1886 } 1887 1888 ixgbe_configure_tx_ring(adapter, tx_ring); 1889 1890 /* Setup Rx Descriptor ring and Rx buffers */ 1891 rx_ring->count = IXGBE_DEFAULT_RXD; 1892 rx_ring->queue_index = 0; 1893 rx_ring->dev = &adapter->pdev->dev; 1894 rx_ring->netdev = adapter->netdev; 1895 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx; 1896 1897 err = ixgbe_setup_rx_resources(adapter, rx_ring); 1898 if (err) { 1899 ret_val = 4; 1900 goto err_nomem; 1901 } 1902 1903 hw->mac.ops.disable_rx(hw); 1904 1905 ixgbe_configure_rx_ring(adapter, rx_ring); 1906 1907 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL); 1908 rctl |= IXGBE_RXCTRL_DMBYPS; 1909 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl); 1910 1911 hw->mac.ops.enable_rx(hw); 1912 1913 return 0; 1914 1915 err_nomem: 1916 ixgbe_free_desc_rings(adapter); 1917 return ret_val; 1918 } 1919 1920 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter) 1921 { 1922 struct ixgbe_hw *hw = &adapter->hw; 1923 u32 reg_data; 1924 1925 1926 /* Setup MAC loopback */ 1927 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0); 1928 reg_data |= IXGBE_HLREG0_LPBK; 1929 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data); 1930 1931 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1932 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE; 1933 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data); 1934 1935 /* X540 and X550 needs to set the MACC.FLU bit to force link up */ 1936 switch (adapter->hw.mac.type) { 1937 case ixgbe_mac_X540: 1938 case ixgbe_mac_X550: 1939 case ixgbe_mac_X550EM_x: 1940 case ixgbe_mac_x550em_a: 1941 case ixgbe_mac_e610: 1942 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC); 1943 reg_data |= IXGBE_MACC_FLU; 1944 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data); 1945 break; 1946 default: 1947 if (hw->mac.orig_autoc) { 1948 reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU; 1949 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data); 1950 } else { 1951 return 10; 1952 } 1953 } 1954 IXGBE_WRITE_FLUSH(hw); 1955 usleep_range(10000, 20000); 1956 1957 /* Disable Atlas Tx lanes; re-enabled in reset path */ 1958 if (hw->mac.type == ixgbe_mac_82598EB) { 1959 u8 atlas; 1960 1961 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas); 1962 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN; 1963 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas); 1964 1965 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas); 1966 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 1967 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas); 1968 1969 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas); 1970 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 1971 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas); 1972 1973 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas); 1974 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 1975 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas); 1976 } 1977 1978 return 0; 1979 } 1980 1981 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter) 1982 { 1983 u32 reg_data; 1984 1985 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0); 1986 reg_data &= ~IXGBE_HLREG0_LPBK; 1987 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data); 1988 } 1989 1990 static void ixgbe_create_lbtest_frame(struct sk_buff *skb, 1991 unsigned int frame_size) 1992 { 1993 memset(skb->data, 0xFF, frame_size); 1994 frame_size >>= 1; 1995 memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1); 1996 skb->data[frame_size + 10] = 0xBE; 1997 skb->data[frame_size + 12] = 0xAF; 1998 } 1999 2000 static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer, 2001 unsigned int frame_size) 2002 { 2003 unsigned char *data; 2004 2005 frame_size >>= 1; 2006 2007 data = page_address(rx_buffer->page) + rx_buffer->page_offset; 2008 2009 return data[3] == 0xFF && data[frame_size + 10] == 0xBE && 2010 data[frame_size + 12] == 0xAF; 2011 } 2012 2013 static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring, 2014 struct ixgbe_ring *tx_ring, 2015 unsigned int size) 2016 { 2017 union ixgbe_adv_rx_desc *rx_desc; 2018 u16 rx_ntc, tx_ntc, count = 0; 2019 2020 /* initialize next to clean and descriptor values */ 2021 rx_ntc = rx_ring->next_to_clean; 2022 tx_ntc = tx_ring->next_to_clean; 2023 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc); 2024 2025 while (tx_ntc != tx_ring->next_to_use) { 2026 union ixgbe_adv_tx_desc *tx_desc; 2027 struct ixgbe_tx_buffer *tx_buffer; 2028 2029 tx_desc = IXGBE_TX_DESC(tx_ring, tx_ntc); 2030 2031 /* if DD is not set transmit has not completed */ 2032 if (!(tx_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 2033 return count; 2034 2035 /* unmap buffer on Tx side */ 2036 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc]; 2037 2038 /* Free all the Tx ring sk_buffs */ 2039 dev_kfree_skb_any(tx_buffer->skb); 2040 2041 /* unmap skb header data */ 2042 dma_unmap_single(tx_ring->dev, 2043 dma_unmap_addr(tx_buffer, dma), 2044 dma_unmap_len(tx_buffer, len), 2045 DMA_TO_DEVICE); 2046 dma_unmap_len_set(tx_buffer, len, 0); 2047 2048 /* increment Tx next to clean counter */ 2049 tx_ntc++; 2050 if (tx_ntc == tx_ring->count) 2051 tx_ntc = 0; 2052 } 2053 2054 while (rx_desc->wb.upper.length) { 2055 struct ixgbe_rx_buffer *rx_buffer; 2056 2057 /* check Rx buffer */ 2058 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc]; 2059 2060 /* sync Rx buffer for CPU read */ 2061 dma_sync_single_for_cpu(rx_ring->dev, 2062 rx_buffer->dma, 2063 ixgbe_rx_bufsz(rx_ring), 2064 DMA_FROM_DEVICE); 2065 2066 /* verify contents of skb */ 2067 if (ixgbe_check_lbtest_frame(rx_buffer, size)) 2068 count++; 2069 else 2070 break; 2071 2072 /* sync Rx buffer for device write */ 2073 dma_sync_single_for_device(rx_ring->dev, 2074 rx_buffer->dma, 2075 ixgbe_rx_bufsz(rx_ring), 2076 DMA_FROM_DEVICE); 2077 2078 /* increment Rx next to clean counter */ 2079 rx_ntc++; 2080 if (rx_ntc == rx_ring->count) 2081 rx_ntc = 0; 2082 2083 /* fetch next descriptor */ 2084 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc); 2085 } 2086 2087 netdev_tx_reset_queue(txring_txq(tx_ring)); 2088 2089 /* re-map buffers to ring, store next to clean values */ 2090 ixgbe_alloc_rx_buffers(rx_ring, count); 2091 rx_ring->next_to_clean = rx_ntc; 2092 tx_ring->next_to_clean = tx_ntc; 2093 2094 return count; 2095 } 2096 2097 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter) 2098 { 2099 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 2100 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 2101 int i, j, lc, good_cnt, ret_val = 0; 2102 unsigned int size = 1024; 2103 netdev_tx_t tx_ret_val; 2104 struct sk_buff *skb; 2105 u32 flags_orig = adapter->flags; 2106 2107 /* DCB can modify the frames on Tx */ 2108 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 2109 2110 /* allocate test skb */ 2111 skb = alloc_skb(size, GFP_KERNEL); 2112 if (!skb) 2113 return 11; 2114 2115 /* place data into test skb */ 2116 ixgbe_create_lbtest_frame(skb, size); 2117 skb_put(skb, size); 2118 2119 /* 2120 * Calculate the loop count based on the largest descriptor ring 2121 * The idea is to wrap the largest ring a number of times using 64 2122 * send/receive pairs during each loop 2123 */ 2124 2125 if (rx_ring->count <= tx_ring->count) 2126 lc = ((tx_ring->count / 64) * 2) + 1; 2127 else 2128 lc = ((rx_ring->count / 64) * 2) + 1; 2129 2130 for (j = 0; j <= lc; j++) { 2131 /* reset count of good packets */ 2132 good_cnt = 0; 2133 2134 /* place 64 packets on the transmit queue*/ 2135 for (i = 0; i < 64; i++) { 2136 skb_get(skb); 2137 tx_ret_val = ixgbe_xmit_frame_ring(skb, 2138 adapter, 2139 tx_ring); 2140 if (tx_ret_val == NETDEV_TX_OK) 2141 good_cnt++; 2142 } 2143 2144 if (good_cnt != 64) { 2145 ret_val = 12; 2146 break; 2147 } 2148 2149 /* allow 200 milliseconds for packets to go from Tx to Rx */ 2150 msleep(200); 2151 2152 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size); 2153 if (good_cnt != 64) { 2154 ret_val = 13; 2155 break; 2156 } 2157 } 2158 2159 /* free the original skb */ 2160 kfree_skb(skb); 2161 adapter->flags = flags_orig; 2162 2163 return ret_val; 2164 } 2165 2166 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data) 2167 { 2168 *data = ixgbe_setup_desc_rings(adapter); 2169 if (*data) 2170 goto out; 2171 *data = ixgbe_setup_loopback_test(adapter); 2172 if (*data) 2173 goto err_loopback; 2174 *data = ixgbe_run_loopback_test(adapter); 2175 ixgbe_loopback_cleanup(adapter); 2176 2177 err_loopback: 2178 ixgbe_free_desc_rings(adapter); 2179 out: 2180 return *data; 2181 } 2182 2183 static void ixgbe_diag_test(struct net_device *netdev, 2184 struct ethtool_test *eth_test, u64 *data) 2185 { 2186 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2187 bool if_running = netif_running(netdev); 2188 2189 if (ixgbe_removed(adapter->hw.hw_addr)) { 2190 e_err(hw, "Adapter removed - test blocked\n"); 2191 data[0] = 1; 2192 data[1] = 1; 2193 data[2] = 1; 2194 data[3] = 1; 2195 data[4] = 1; 2196 eth_test->flags |= ETH_TEST_FL_FAILED; 2197 return; 2198 } 2199 set_bit(__IXGBE_TESTING, &adapter->state); 2200 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 2201 struct ixgbe_hw *hw = &adapter->hw; 2202 2203 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 2204 int i; 2205 for (i = 0; i < adapter->num_vfs; i++) { 2206 if (adapter->vfinfo[i].clear_to_send) { 2207 netdev_warn(netdev, "offline diagnostic is not supported when VFs are present\n"); 2208 data[0] = 1; 2209 data[1] = 1; 2210 data[2] = 1; 2211 data[3] = 1; 2212 data[4] = 1; 2213 eth_test->flags |= ETH_TEST_FL_FAILED; 2214 clear_bit(__IXGBE_TESTING, 2215 &adapter->state); 2216 return; 2217 } 2218 } 2219 } 2220 2221 /* Offline tests */ 2222 e_info(hw, "offline testing starting\n"); 2223 2224 /* Link test performed before hardware reset so autoneg doesn't 2225 * interfere with test result 2226 */ 2227 if (ixgbe_link_test(adapter, &data[4])) 2228 eth_test->flags |= ETH_TEST_FL_FAILED; 2229 2230 if (if_running) 2231 /* indicate we're in test mode */ 2232 ixgbe_close(netdev); 2233 else 2234 ixgbe_reset(adapter); 2235 2236 e_info(hw, "register testing starting\n"); 2237 if (ixgbe_reg_test(adapter, &data[0])) 2238 eth_test->flags |= ETH_TEST_FL_FAILED; 2239 2240 ixgbe_reset(adapter); 2241 e_info(hw, "eeprom testing starting\n"); 2242 if (ixgbe_eeprom_test(adapter, &data[1])) 2243 eth_test->flags |= ETH_TEST_FL_FAILED; 2244 2245 ixgbe_reset(adapter); 2246 e_info(hw, "interrupt testing starting\n"); 2247 if (ixgbe_intr_test(adapter, &data[2])) 2248 eth_test->flags |= ETH_TEST_FL_FAILED; 2249 2250 /* If SRIOV or VMDq is enabled then skip MAC 2251 * loopback diagnostic. */ 2252 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED | 2253 IXGBE_FLAG_VMDQ_ENABLED)) { 2254 e_info(hw, "Skip MAC loopback diagnostic in VT mode\n"); 2255 data[3] = 0; 2256 goto skip_loopback; 2257 } 2258 2259 ixgbe_reset(adapter); 2260 e_info(hw, "loopback testing starting\n"); 2261 if (ixgbe_loopback_test(adapter, &data[3])) 2262 eth_test->flags |= ETH_TEST_FL_FAILED; 2263 2264 skip_loopback: 2265 ixgbe_reset(adapter); 2266 2267 /* clear testing bit and return adapter to previous state */ 2268 clear_bit(__IXGBE_TESTING, &adapter->state); 2269 if (if_running) 2270 ixgbe_open(netdev); 2271 else if (hw->mac.ops.disable_tx_laser) 2272 hw->mac.ops.disable_tx_laser(hw); 2273 } else { 2274 e_info(hw, "online testing starting\n"); 2275 2276 /* Online tests */ 2277 if (ixgbe_link_test(adapter, &data[4])) 2278 eth_test->flags |= ETH_TEST_FL_FAILED; 2279 2280 /* Offline tests aren't run; pass by default */ 2281 data[0] = 0; 2282 data[1] = 0; 2283 data[2] = 0; 2284 data[3] = 0; 2285 2286 clear_bit(__IXGBE_TESTING, &adapter->state); 2287 } 2288 } 2289 2290 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter, 2291 struct ethtool_wolinfo *wol) 2292 { 2293 struct ixgbe_hw *hw = &adapter->hw; 2294 int retval = 0; 2295 2296 /* WOL not supported for all devices */ 2297 if (!ixgbe_wol_supported(adapter, hw->device_id, 2298 hw->subsystem_device_id)) { 2299 retval = 1; 2300 wol->supported = 0; 2301 } 2302 2303 return retval; 2304 } 2305 2306 static void ixgbe_get_wol(struct net_device *netdev, 2307 struct ethtool_wolinfo *wol) 2308 { 2309 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2310 2311 wol->supported = WAKE_UCAST | WAKE_MCAST | 2312 WAKE_BCAST | WAKE_MAGIC; 2313 wol->wolopts = 0; 2314 2315 if (ixgbe_wol_exclusion(adapter, wol) || 2316 !device_can_wakeup(&adapter->pdev->dev)) 2317 return; 2318 2319 if (adapter->wol & IXGBE_WUFC_EX) 2320 wol->wolopts |= WAKE_UCAST; 2321 if (adapter->wol & IXGBE_WUFC_MC) 2322 wol->wolopts |= WAKE_MCAST; 2323 if (adapter->wol & IXGBE_WUFC_BC) 2324 wol->wolopts |= WAKE_BCAST; 2325 if (adapter->wol & IXGBE_WUFC_MAG) 2326 wol->wolopts |= WAKE_MAGIC; 2327 } 2328 2329 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2330 { 2331 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2332 2333 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE | 2334 WAKE_FILTER)) 2335 return -EOPNOTSUPP; 2336 2337 if (ixgbe_wol_exclusion(adapter, wol)) 2338 return wol->wolopts ? -EOPNOTSUPP : 0; 2339 2340 adapter->wol = 0; 2341 2342 if (wol->wolopts & WAKE_UCAST) 2343 adapter->wol |= IXGBE_WUFC_EX; 2344 if (wol->wolopts & WAKE_MCAST) 2345 adapter->wol |= IXGBE_WUFC_MC; 2346 if (wol->wolopts & WAKE_BCAST) 2347 adapter->wol |= IXGBE_WUFC_BC; 2348 if (wol->wolopts & WAKE_MAGIC) 2349 adapter->wol |= IXGBE_WUFC_MAG; 2350 2351 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2352 2353 return 0; 2354 } 2355 2356 static int ixgbe_nway_reset(struct net_device *netdev) 2357 { 2358 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2359 2360 if (netif_running(netdev)) 2361 ixgbe_reinit_locked(adapter); 2362 2363 return 0; 2364 } 2365 2366 static int ixgbe_set_phys_id(struct net_device *netdev, 2367 enum ethtool_phys_id_state state) 2368 { 2369 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2370 struct ixgbe_hw *hw = &adapter->hw; 2371 2372 if (!hw->mac.ops.led_on || !hw->mac.ops.led_off) 2373 return -EOPNOTSUPP; 2374 2375 switch (state) { 2376 case ETHTOOL_ID_ACTIVE: 2377 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2378 return 2; 2379 2380 case ETHTOOL_ID_ON: 2381 hw->mac.ops.led_on(hw, hw->mac.led_link_act); 2382 break; 2383 2384 case ETHTOOL_ID_OFF: 2385 hw->mac.ops.led_off(hw, hw->mac.led_link_act); 2386 break; 2387 2388 case ETHTOOL_ID_INACTIVE: 2389 /* Restore LED settings */ 2390 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg); 2391 break; 2392 } 2393 2394 return 0; 2395 } 2396 2397 static int ixgbe_get_coalesce(struct net_device *netdev, 2398 struct ethtool_coalesce *ec, 2399 struct kernel_ethtool_coalesce *kernel_coal, 2400 struct netlink_ext_ack *extack) 2401 { 2402 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2403 2404 /* only valid if in constant ITR mode */ 2405 if (adapter->rx_itr_setting <= 1) 2406 ec->rx_coalesce_usecs = adapter->rx_itr_setting; 2407 else 2408 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; 2409 2410 /* if in mixed tx/rx queues per vector mode, report only rx settings */ 2411 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) 2412 return 0; 2413 2414 /* only valid if in constant ITR mode */ 2415 if (adapter->tx_itr_setting <= 1) 2416 ec->tx_coalesce_usecs = adapter->tx_itr_setting; 2417 else 2418 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; 2419 2420 return 0; 2421 } 2422 2423 /* 2424 * this function must be called before setting the new value of 2425 * rx_itr_setting 2426 */ 2427 static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter) 2428 { 2429 struct net_device *netdev = adapter->netdev; 2430 2431 /* nothing to do if LRO or RSC are not enabled */ 2432 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) || 2433 !(netdev->features & NETIF_F_LRO)) 2434 return false; 2435 2436 /* check the feature flag value and enable RSC if necessary */ 2437 if (adapter->rx_itr_setting == 1 || 2438 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 2439 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 2440 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 2441 e_info(probe, "rx-usecs value high enough to re-enable RSC\n"); 2442 return true; 2443 } 2444 /* if interrupt rate is too high then disable RSC */ 2445 } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 2446 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 2447 e_info(probe, "rx-usecs set too low, disabling RSC\n"); 2448 return true; 2449 } 2450 return false; 2451 } 2452 2453 static int ixgbe_set_coalesce(struct net_device *netdev, 2454 struct ethtool_coalesce *ec, 2455 struct kernel_ethtool_coalesce *kernel_coal, 2456 struct netlink_ext_ack *extack) 2457 { 2458 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2459 struct ixgbe_q_vector *q_vector; 2460 int i; 2461 u16 tx_itr_param, rx_itr_param, tx_itr_prev; 2462 bool need_reset = false; 2463 2464 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) { 2465 /* reject Tx specific changes in case of mixed RxTx vectors */ 2466 if (ec->tx_coalesce_usecs) 2467 return -EINVAL; 2468 tx_itr_prev = adapter->rx_itr_setting; 2469 } else { 2470 tx_itr_prev = adapter->tx_itr_setting; 2471 } 2472 2473 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) || 2474 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2))) 2475 return -EINVAL; 2476 2477 if (ec->rx_coalesce_usecs > 1) 2478 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; 2479 else 2480 adapter->rx_itr_setting = ec->rx_coalesce_usecs; 2481 2482 if (adapter->rx_itr_setting == 1) 2483 rx_itr_param = IXGBE_20K_ITR; 2484 else 2485 rx_itr_param = adapter->rx_itr_setting; 2486 2487 if (ec->tx_coalesce_usecs > 1) 2488 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; 2489 else 2490 adapter->tx_itr_setting = ec->tx_coalesce_usecs; 2491 2492 if (adapter->tx_itr_setting == 1) 2493 tx_itr_param = IXGBE_12K_ITR; 2494 else 2495 tx_itr_param = adapter->tx_itr_setting; 2496 2497 /* mixed Rx/Tx */ 2498 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) 2499 adapter->tx_itr_setting = adapter->rx_itr_setting; 2500 2501 /* detect ITR changes that require update of TXDCTL.WTHRESH */ 2502 if ((adapter->tx_itr_setting != 1) && 2503 (adapter->tx_itr_setting < IXGBE_100K_ITR)) { 2504 if ((tx_itr_prev == 1) || 2505 (tx_itr_prev >= IXGBE_100K_ITR)) 2506 need_reset = true; 2507 } else { 2508 if ((tx_itr_prev != 1) && 2509 (tx_itr_prev < IXGBE_100K_ITR)) 2510 need_reset = true; 2511 } 2512 2513 /* check the old value and enable RSC if necessary */ 2514 need_reset |= ixgbe_update_rsc(adapter); 2515 2516 for (i = 0; i < adapter->num_q_vectors; i++) { 2517 q_vector = adapter->q_vector[i]; 2518 if (q_vector->tx.count && !q_vector->rx.count) 2519 /* tx only */ 2520 q_vector->itr = tx_itr_param; 2521 else 2522 /* rx only or mixed */ 2523 q_vector->itr = rx_itr_param; 2524 ixgbe_write_eitr(q_vector); 2525 } 2526 2527 /* 2528 * do reset here at the end to make sure EITR==0 case is handled 2529 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings 2530 * also locks in RSC enable/disable which requires reset 2531 */ 2532 if (need_reset) 2533 ixgbe_do_reset(netdev); 2534 2535 return 0; 2536 } 2537 2538 static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2539 struct ethtool_rxnfc *cmd) 2540 { 2541 union ixgbe_atr_input *mask = &adapter->fdir_mask; 2542 struct ethtool_rx_flow_spec *fsp = 2543 (struct ethtool_rx_flow_spec *)&cmd->fs; 2544 struct hlist_node *node2; 2545 struct ixgbe_fdir_filter *rule = NULL; 2546 2547 /* report total rule count */ 2548 cmd->data = (1024 << adapter->fdir_pballoc) - 2; 2549 2550 hlist_for_each_entry_safe(rule, node2, 2551 &adapter->fdir_filter_list, fdir_node) { 2552 if (fsp->location <= rule->sw_idx) 2553 break; 2554 } 2555 2556 if (!rule || fsp->location != rule->sw_idx) 2557 return -EINVAL; 2558 2559 /* fill out the flow spec entry */ 2560 2561 /* set flow type field */ 2562 switch (rule->filter.formatted.flow_type) { 2563 case IXGBE_ATR_FLOW_TYPE_TCPV4: 2564 fsp->flow_type = TCP_V4_FLOW; 2565 break; 2566 case IXGBE_ATR_FLOW_TYPE_UDPV4: 2567 fsp->flow_type = UDP_V4_FLOW; 2568 break; 2569 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 2570 fsp->flow_type = SCTP_V4_FLOW; 2571 break; 2572 case IXGBE_ATR_FLOW_TYPE_IPV4: 2573 fsp->flow_type = IP_USER_FLOW; 2574 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 2575 fsp->h_u.usr_ip4_spec.proto = 0; 2576 fsp->m_u.usr_ip4_spec.proto = 0; 2577 break; 2578 default: 2579 return -EINVAL; 2580 } 2581 2582 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port; 2583 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port; 2584 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port; 2585 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port; 2586 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0]; 2587 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0]; 2588 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0]; 2589 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0]; 2590 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id; 2591 fsp->m_ext.vlan_tci = mask->formatted.vlan_id; 2592 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes; 2593 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes; 2594 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool); 2595 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool); 2596 fsp->flow_type |= FLOW_EXT; 2597 2598 /* record action */ 2599 if (rule->action == IXGBE_FDIR_DROP_QUEUE) 2600 fsp->ring_cookie = RX_CLS_FLOW_DISC; 2601 else 2602 fsp->ring_cookie = rule->action; 2603 2604 return 0; 2605 } 2606 2607 static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter, 2608 struct ethtool_rxnfc *cmd, 2609 u32 *rule_locs) 2610 { 2611 struct hlist_node *node2; 2612 struct ixgbe_fdir_filter *rule; 2613 int cnt = 0; 2614 2615 /* report total rule count */ 2616 cmd->data = (1024 << adapter->fdir_pballoc) - 2; 2617 2618 hlist_for_each_entry_safe(rule, node2, 2619 &adapter->fdir_filter_list, fdir_node) { 2620 if (cnt == cmd->rule_cnt) 2621 return -EMSGSIZE; 2622 rule_locs[cnt] = rule->sw_idx; 2623 cnt++; 2624 } 2625 2626 cmd->rule_cnt = cnt; 2627 2628 return 0; 2629 } 2630 2631 static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter, 2632 struct ethtool_rxnfc *cmd) 2633 { 2634 cmd->data = 0; 2635 2636 /* Report default options for RSS on ixgbe */ 2637 switch (cmd->flow_type) { 2638 case TCP_V4_FLOW: 2639 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2640 fallthrough; 2641 case UDP_V4_FLOW: 2642 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 2643 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2644 fallthrough; 2645 case SCTP_V4_FLOW: 2646 case AH_ESP_V4_FLOW: 2647 case AH_V4_FLOW: 2648 case ESP_V4_FLOW: 2649 case IPV4_FLOW: 2650 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2651 break; 2652 case TCP_V6_FLOW: 2653 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2654 fallthrough; 2655 case UDP_V6_FLOW: 2656 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2657 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2658 fallthrough; 2659 case SCTP_V6_FLOW: 2660 case AH_ESP_V6_FLOW: 2661 case AH_V6_FLOW: 2662 case ESP_V6_FLOW: 2663 case IPV6_FLOW: 2664 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2665 break; 2666 default: 2667 return -EINVAL; 2668 } 2669 2670 return 0; 2671 } 2672 2673 static int ixgbe_rss_indir_tbl_max(struct ixgbe_adapter *adapter) 2674 { 2675 if (adapter->hw.mac.type < ixgbe_mac_X550) 2676 return 16; 2677 else 2678 return 64; 2679 } 2680 2681 static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2682 u32 *rule_locs) 2683 { 2684 struct ixgbe_adapter *adapter = netdev_priv(dev); 2685 int ret = -EOPNOTSUPP; 2686 2687 switch (cmd->cmd) { 2688 case ETHTOOL_GRXRINGS: 2689 cmd->data = min_t(int, adapter->num_rx_queues, 2690 ixgbe_rss_indir_tbl_max(adapter)); 2691 ret = 0; 2692 break; 2693 case ETHTOOL_GRXCLSRLCNT: 2694 cmd->rule_cnt = adapter->fdir_filter_count; 2695 ret = 0; 2696 break; 2697 case ETHTOOL_GRXCLSRULE: 2698 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd); 2699 break; 2700 case ETHTOOL_GRXCLSRLALL: 2701 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs); 2702 break; 2703 case ETHTOOL_GRXFH: 2704 ret = ixgbe_get_rss_hash_opts(adapter, cmd); 2705 break; 2706 default: 2707 break; 2708 } 2709 2710 return ret; 2711 } 2712 2713 int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2714 struct ixgbe_fdir_filter *input, 2715 u16 sw_idx) 2716 { 2717 struct ixgbe_hw *hw = &adapter->hw; 2718 struct hlist_node *node2; 2719 struct ixgbe_fdir_filter *rule, *parent; 2720 int err = -EINVAL; 2721 2722 parent = NULL; 2723 rule = NULL; 2724 2725 hlist_for_each_entry_safe(rule, node2, 2726 &adapter->fdir_filter_list, fdir_node) { 2727 /* hash found, or no matching entry */ 2728 if (rule->sw_idx >= sw_idx) 2729 break; 2730 parent = rule; 2731 } 2732 2733 /* if there is an old rule occupying our place remove it */ 2734 if (rule && (rule->sw_idx == sw_idx)) { 2735 if (!input || (rule->filter.formatted.bkt_hash != 2736 input->filter.formatted.bkt_hash)) { 2737 err = ixgbe_fdir_erase_perfect_filter_82599(hw, 2738 &rule->filter, 2739 sw_idx); 2740 } 2741 2742 hlist_del(&rule->fdir_node); 2743 kfree(rule); 2744 adapter->fdir_filter_count--; 2745 } 2746 2747 /* 2748 * If no input this was a delete, err should be 0 if a rule was 2749 * successfully found and removed from the list else -EINVAL 2750 */ 2751 if (!input) 2752 return err; 2753 2754 /* initialize node and set software index */ 2755 INIT_HLIST_NODE(&input->fdir_node); 2756 2757 /* add filter to the list */ 2758 if (parent) 2759 hlist_add_behind(&input->fdir_node, &parent->fdir_node); 2760 else 2761 hlist_add_head(&input->fdir_node, 2762 &adapter->fdir_filter_list); 2763 2764 /* update counts */ 2765 adapter->fdir_filter_count++; 2766 2767 return 0; 2768 } 2769 2770 static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp, 2771 u8 *flow_type) 2772 { 2773 switch (fsp->flow_type & ~FLOW_EXT) { 2774 case TCP_V4_FLOW: 2775 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 2776 break; 2777 case UDP_V4_FLOW: 2778 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 2779 break; 2780 case SCTP_V4_FLOW: 2781 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 2782 break; 2783 case IP_USER_FLOW: 2784 switch (fsp->h_u.usr_ip4_spec.proto) { 2785 case IPPROTO_TCP: 2786 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 2787 break; 2788 case IPPROTO_UDP: 2789 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 2790 break; 2791 case IPPROTO_SCTP: 2792 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 2793 break; 2794 case 0: 2795 if (!fsp->m_u.usr_ip4_spec.proto) { 2796 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4; 2797 break; 2798 } 2799 fallthrough; 2800 default: 2801 return 0; 2802 } 2803 break; 2804 default: 2805 return 0; 2806 } 2807 2808 return 1; 2809 } 2810 2811 static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2812 struct ethtool_rxnfc *cmd) 2813 { 2814 struct ethtool_rx_flow_spec *fsp = 2815 (struct ethtool_rx_flow_spec *)&cmd->fs; 2816 struct ixgbe_hw *hw = &adapter->hw; 2817 struct ixgbe_fdir_filter *input; 2818 union ixgbe_atr_input mask; 2819 u8 queue; 2820 int err; 2821 2822 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 2823 return -EOPNOTSUPP; 2824 2825 /* ring_cookie is a masked into a set of queues and ixgbe pools or 2826 * we use the drop index. 2827 */ 2828 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) { 2829 queue = IXGBE_FDIR_DROP_QUEUE; 2830 } else { 2831 u32 ring = ethtool_get_flow_spec_ring(fsp->ring_cookie); 2832 u8 vf = ethtool_get_flow_spec_ring_vf(fsp->ring_cookie); 2833 2834 if (!vf && (ring >= adapter->num_rx_queues)) 2835 return -EINVAL; 2836 else if (vf && 2837 ((vf > adapter->num_vfs) || 2838 ring >= adapter->num_rx_queues_per_pool)) 2839 return -EINVAL; 2840 2841 /* Map the ring onto the absolute queue index */ 2842 if (!vf) 2843 queue = adapter->rx_ring[ring]->reg_idx; 2844 else 2845 queue = ((vf - 1) * 2846 adapter->num_rx_queues_per_pool) + ring; 2847 } 2848 2849 /* Don't allow indexes to exist outside of available space */ 2850 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) { 2851 e_err(drv, "Location out of range\n"); 2852 return -EINVAL; 2853 } 2854 2855 input = kzalloc(sizeof(*input), GFP_ATOMIC); 2856 if (!input) 2857 return -ENOMEM; 2858 2859 memset(&mask, 0, sizeof(union ixgbe_atr_input)); 2860 2861 /* set SW index */ 2862 input->sw_idx = fsp->location; 2863 2864 /* record flow type */ 2865 if (!ixgbe_flowspec_to_flow_type(fsp, 2866 &input->filter.formatted.flow_type)) { 2867 e_err(drv, "Unrecognized flow type\n"); 2868 goto err_out; 2869 } 2870 2871 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 2872 IXGBE_ATR_L4TYPE_MASK; 2873 2874 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 2875 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 2876 2877 /* Copy input into formatted structures */ 2878 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src; 2879 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src; 2880 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst; 2881 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst; 2882 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc; 2883 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc; 2884 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst; 2885 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst; 2886 2887 if (fsp->flow_type & FLOW_EXT) { 2888 input->filter.formatted.vm_pool = 2889 (unsigned char)ntohl(fsp->h_ext.data[1]); 2890 mask.formatted.vm_pool = 2891 (unsigned char)ntohl(fsp->m_ext.data[1]); 2892 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci; 2893 mask.formatted.vlan_id = fsp->m_ext.vlan_tci; 2894 input->filter.formatted.flex_bytes = 2895 fsp->h_ext.vlan_etype; 2896 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype; 2897 } 2898 2899 /* determine if we need to drop or route the packet */ 2900 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) 2901 input->action = IXGBE_FDIR_DROP_QUEUE; 2902 else 2903 input->action = fsp->ring_cookie; 2904 2905 spin_lock(&adapter->fdir_perfect_lock); 2906 2907 if (hlist_empty(&adapter->fdir_filter_list)) { 2908 /* save mask and program input mask into HW */ 2909 memcpy(&adapter->fdir_mask, &mask, sizeof(mask)); 2910 err = ixgbe_fdir_set_input_mask_82599(hw, &mask); 2911 if (err) { 2912 e_err(drv, "Error writing mask\n"); 2913 goto err_out_w_lock; 2914 } 2915 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) { 2916 e_err(drv, "Only one mask supported per port\n"); 2917 goto err_out_w_lock; 2918 } 2919 2920 /* apply mask and compute/store hash */ 2921 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask); 2922 2923 /* program filters to filter memory */ 2924 err = ixgbe_fdir_write_perfect_filter_82599(hw, 2925 &input->filter, input->sw_idx, queue); 2926 if (err) 2927 goto err_out_w_lock; 2928 2929 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 2930 2931 spin_unlock(&adapter->fdir_perfect_lock); 2932 2933 return err; 2934 err_out_w_lock: 2935 spin_unlock(&adapter->fdir_perfect_lock); 2936 err_out: 2937 kfree(input); 2938 return -EINVAL; 2939 } 2940 2941 static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2942 struct ethtool_rxnfc *cmd) 2943 { 2944 struct ethtool_rx_flow_spec *fsp = 2945 (struct ethtool_rx_flow_spec *)&cmd->fs; 2946 int err; 2947 2948 spin_lock(&adapter->fdir_perfect_lock); 2949 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location); 2950 spin_unlock(&adapter->fdir_perfect_lock); 2951 2952 return err; 2953 } 2954 2955 #define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \ 2956 IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2957 static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter, 2958 struct ethtool_rxnfc *nfc) 2959 { 2960 u32 flags2 = adapter->flags2; 2961 2962 /* 2963 * RSS does not support anything other than hashing 2964 * to queues on src and dst IPs and ports 2965 */ 2966 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 2967 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 2968 return -EINVAL; 2969 2970 switch (nfc->flow_type) { 2971 case TCP_V4_FLOW: 2972 case TCP_V6_FLOW: 2973 if (!(nfc->data & RXH_IP_SRC) || 2974 !(nfc->data & RXH_IP_DST) || 2975 !(nfc->data & RXH_L4_B_0_1) || 2976 !(nfc->data & RXH_L4_B_2_3)) 2977 return -EINVAL; 2978 break; 2979 case UDP_V4_FLOW: 2980 if (!(nfc->data & RXH_IP_SRC) || 2981 !(nfc->data & RXH_IP_DST)) 2982 return -EINVAL; 2983 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2984 case 0: 2985 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP; 2986 break; 2987 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2988 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP; 2989 break; 2990 default: 2991 return -EINVAL; 2992 } 2993 break; 2994 case UDP_V6_FLOW: 2995 if (!(nfc->data & RXH_IP_SRC) || 2996 !(nfc->data & RXH_IP_DST)) 2997 return -EINVAL; 2998 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2999 case 0: 3000 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP; 3001 break; 3002 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 3003 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP; 3004 break; 3005 default: 3006 return -EINVAL; 3007 } 3008 break; 3009 case AH_ESP_V4_FLOW: 3010 case AH_V4_FLOW: 3011 case ESP_V4_FLOW: 3012 case SCTP_V4_FLOW: 3013 case AH_ESP_V6_FLOW: 3014 case AH_V6_FLOW: 3015 case ESP_V6_FLOW: 3016 case SCTP_V6_FLOW: 3017 if (!(nfc->data & RXH_IP_SRC) || 3018 !(nfc->data & RXH_IP_DST) || 3019 (nfc->data & RXH_L4_B_0_1) || 3020 (nfc->data & RXH_L4_B_2_3)) 3021 return -EINVAL; 3022 break; 3023 default: 3024 return -EINVAL; 3025 } 3026 3027 /* if we changed something we need to update flags */ 3028 if (flags2 != adapter->flags2) { 3029 struct ixgbe_hw *hw = &adapter->hw; 3030 u32 mrqc; 3031 unsigned int pf_pool = adapter->num_vfs; 3032 3033 if ((hw->mac.type >= ixgbe_mac_X550) && 3034 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 3035 mrqc = IXGBE_READ_REG(hw, IXGBE_PFVFMRQC(pf_pool)); 3036 else 3037 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC); 3038 3039 if ((flags2 & UDP_RSS_FLAGS) && 3040 !(adapter->flags2 & UDP_RSS_FLAGS)) 3041 e_warn(drv, "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n"); 3042 3043 adapter->flags2 = flags2; 3044 3045 /* Perform hash on these packet types */ 3046 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 3047 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP 3048 | IXGBE_MRQC_RSS_FIELD_IPV6 3049 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3050 3051 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP | 3052 IXGBE_MRQC_RSS_FIELD_IPV6_UDP); 3053 3054 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3055 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3056 3057 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3058 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3059 3060 if ((hw->mac.type >= ixgbe_mac_X550) && 3061 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 3062 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), mrqc); 3063 else 3064 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3065 } 3066 3067 return 0; 3068 } 3069 3070 static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 3071 { 3072 struct ixgbe_adapter *adapter = netdev_priv(dev); 3073 int ret = -EOPNOTSUPP; 3074 3075 switch (cmd->cmd) { 3076 case ETHTOOL_SRXCLSRLINS: 3077 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd); 3078 break; 3079 case ETHTOOL_SRXCLSRLDEL: 3080 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd); 3081 break; 3082 case ETHTOOL_SRXFH: 3083 ret = ixgbe_set_rss_hash_opt(adapter, cmd); 3084 break; 3085 default: 3086 break; 3087 } 3088 3089 return ret; 3090 } 3091 3092 static u32 ixgbe_get_rxfh_key_size(struct net_device *netdev) 3093 { 3094 return IXGBE_RSS_KEY_SIZE; 3095 } 3096 3097 static u32 ixgbe_rss_indir_size(struct net_device *netdev) 3098 { 3099 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3100 3101 return ixgbe_rss_indir_tbl_entries(adapter); 3102 } 3103 3104 static void ixgbe_get_reta(struct ixgbe_adapter *adapter, u32 *indir) 3105 { 3106 int i, reta_size = ixgbe_rss_indir_tbl_entries(adapter); 3107 u16 rss_m = adapter->ring_feature[RING_F_RSS].mask; 3108 3109 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3110 rss_m = adapter->ring_feature[RING_F_RSS].indices - 1; 3111 3112 for (i = 0; i < reta_size; i++) 3113 indir[i] = adapter->rss_indir_tbl[i] & rss_m; 3114 } 3115 3116 static int ixgbe_get_rxfh(struct net_device *netdev, 3117 struct ethtool_rxfh_param *rxfh) 3118 { 3119 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3120 3121 rxfh->hfunc = ETH_RSS_HASH_TOP; 3122 3123 if (rxfh->indir) 3124 ixgbe_get_reta(adapter, rxfh->indir); 3125 3126 if (rxfh->key) 3127 memcpy(rxfh->key, adapter->rss_key, 3128 ixgbe_get_rxfh_key_size(netdev)); 3129 3130 return 0; 3131 } 3132 3133 static int ixgbe_set_rxfh(struct net_device *netdev, 3134 struct ethtool_rxfh_param *rxfh, 3135 struct netlink_ext_ack *extack) 3136 { 3137 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3138 int i; 3139 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3140 3141 if (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE && 3142 rxfh->hfunc != ETH_RSS_HASH_TOP) 3143 return -EOPNOTSUPP; 3144 3145 /* Fill out the redirection table */ 3146 if (rxfh->indir) { 3147 int max_queues = min_t(int, adapter->num_rx_queues, 3148 ixgbe_rss_indir_tbl_max(adapter)); 3149 3150 /*Allow at least 2 queues w/ SR-IOV.*/ 3151 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 3152 (max_queues < 2)) 3153 max_queues = 2; 3154 3155 /* Verify user input. */ 3156 for (i = 0; i < reta_entries; i++) 3157 if (rxfh->indir[i] >= max_queues) 3158 return -EINVAL; 3159 3160 for (i = 0; i < reta_entries; i++) 3161 adapter->rss_indir_tbl[i] = rxfh->indir[i]; 3162 3163 ixgbe_store_reta(adapter); 3164 } 3165 3166 /* Fill out the rss hash key */ 3167 if (rxfh->key) { 3168 memcpy(adapter->rss_key, rxfh->key, 3169 ixgbe_get_rxfh_key_size(netdev)); 3170 ixgbe_store_key(adapter); 3171 } 3172 3173 return 0; 3174 } 3175 3176 static int ixgbe_get_ts_info(struct net_device *dev, 3177 struct kernel_ethtool_ts_info *info) 3178 { 3179 struct ixgbe_adapter *adapter = netdev_priv(dev); 3180 3181 /* we always support timestamping disabled */ 3182 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE); 3183 3184 switch (adapter->hw.mac.type) { 3185 case ixgbe_mac_X550: 3186 case ixgbe_mac_X550EM_x: 3187 case ixgbe_mac_x550em_a: 3188 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL); 3189 break; 3190 case ixgbe_mac_X540: 3191 case ixgbe_mac_82599EB: 3192 info->rx_filters |= 3193 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 3194 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 3195 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT); 3196 break; 3197 default: 3198 return ethtool_op_get_ts_info(dev, info); 3199 } 3200 3201 info->so_timestamping = 3202 SOF_TIMESTAMPING_TX_SOFTWARE | 3203 SOF_TIMESTAMPING_TX_HARDWARE | 3204 SOF_TIMESTAMPING_RX_HARDWARE | 3205 SOF_TIMESTAMPING_RAW_HARDWARE; 3206 3207 if (adapter->ptp_clock) 3208 info->phc_index = ptp_clock_index(adapter->ptp_clock); 3209 3210 info->tx_types = 3211 BIT(HWTSTAMP_TX_OFF) | 3212 BIT(HWTSTAMP_TX_ON); 3213 3214 return 0; 3215 } 3216 3217 static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter) 3218 { 3219 unsigned int max_combined; 3220 u8 tcs = adapter->hw_tcs; 3221 3222 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3223 /* We only support one q_vector without MSI-X */ 3224 max_combined = 1; 3225 } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3226 /* Limit value based on the queue mask */ 3227 max_combined = adapter->ring_feature[RING_F_RSS].mask + 1; 3228 } else if (tcs > 1) { 3229 /* For DCB report channels per traffic class */ 3230 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3231 /* 8 TC w/ 4 queues per TC */ 3232 max_combined = 4; 3233 } else if (tcs > 4) { 3234 /* 8 TC w/ 8 queues per TC */ 3235 max_combined = 8; 3236 } else { 3237 /* 4 TC w/ 16 queues per TC */ 3238 max_combined = 16; 3239 } 3240 } else if (adapter->atr_sample_rate) { 3241 /* support up to 64 queues with ATR */ 3242 max_combined = IXGBE_MAX_FDIR_INDICES; 3243 } else { 3244 /* support up to 16 queues with RSS */ 3245 max_combined = ixgbe_max_rss_indices(adapter); 3246 } 3247 3248 return min_t(int, max_combined, num_online_cpus()); 3249 } 3250 3251 static void ixgbe_get_channels(struct net_device *dev, 3252 struct ethtool_channels *ch) 3253 { 3254 struct ixgbe_adapter *adapter = netdev_priv(dev); 3255 3256 /* report maximum channels */ 3257 ch->max_combined = ixgbe_max_channels(adapter); 3258 3259 /* report info for other vector */ 3260 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3261 ch->max_other = NON_Q_VECTORS; 3262 ch->other_count = NON_Q_VECTORS; 3263 } 3264 3265 /* record RSS queues */ 3266 ch->combined_count = adapter->ring_feature[RING_F_RSS].indices; 3267 3268 /* nothing else to report if RSS is disabled */ 3269 if (ch->combined_count == 1) 3270 return; 3271 3272 /* we do not support ATR queueing if SR-IOV is enabled */ 3273 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3274 return; 3275 3276 /* same thing goes for being DCB enabled */ 3277 if (adapter->hw_tcs > 1) 3278 return; 3279 3280 /* if ATR is disabled we can exit */ 3281 if (!adapter->atr_sample_rate) 3282 return; 3283 3284 /* report flow director queues as maximum channels */ 3285 ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices; 3286 } 3287 3288 static int ixgbe_set_channels(struct net_device *dev, 3289 struct ethtool_channels *ch) 3290 { 3291 struct ixgbe_adapter *adapter = netdev_priv(dev); 3292 unsigned int count = ch->combined_count; 3293 u8 max_rss_indices = ixgbe_max_rss_indices(adapter); 3294 3295 /* verify they are not requesting separate vectors */ 3296 if (!count || ch->rx_count || ch->tx_count) 3297 return -EINVAL; 3298 3299 /* verify other_count has not changed */ 3300 if (ch->other_count != NON_Q_VECTORS) 3301 return -EINVAL; 3302 3303 /* verify the number of channels does not exceed hardware limits */ 3304 if (count > ixgbe_max_channels(adapter)) 3305 return -EINVAL; 3306 3307 /* update feature limits from largest to smallest supported values */ 3308 adapter->ring_feature[RING_F_FDIR].limit = count; 3309 3310 /* cap RSS limit */ 3311 if (count > max_rss_indices) 3312 count = max_rss_indices; 3313 adapter->ring_feature[RING_F_RSS].limit = count; 3314 3315 #ifdef IXGBE_FCOE 3316 /* cap FCoE limit at 8 */ 3317 if (count > IXGBE_FCRETA_SIZE) 3318 count = IXGBE_FCRETA_SIZE; 3319 adapter->ring_feature[RING_F_FCOE].limit = count; 3320 3321 #endif 3322 /* use setup TC to update any traffic class queue mapping */ 3323 return ixgbe_setup_tc(dev, adapter->hw_tcs); 3324 } 3325 3326 static int ixgbe_get_module_info(struct net_device *dev, 3327 struct ethtool_modinfo *modinfo) 3328 { 3329 struct ixgbe_adapter *adapter = netdev_priv(dev); 3330 struct ixgbe_hw *hw = &adapter->hw; 3331 u8 sff8472_rev, addr_mode; 3332 bool page_swap = false; 3333 int status; 3334 3335 if (hw->phy.type == ixgbe_phy_fw) 3336 return -ENXIO; 3337 3338 /* Check whether we support SFF-8472 or not */ 3339 status = hw->phy.ops.read_i2c_eeprom(hw, 3340 IXGBE_SFF_SFF_8472_COMP, 3341 &sff8472_rev); 3342 if (status) 3343 return -EIO; 3344 3345 /* addressing mode is not supported */ 3346 status = hw->phy.ops.read_i2c_eeprom(hw, 3347 IXGBE_SFF_SFF_8472_SWAP, 3348 &addr_mode); 3349 if (status) 3350 return -EIO; 3351 3352 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) { 3353 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n"); 3354 page_swap = true; 3355 } 3356 3357 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap || 3358 !(addr_mode & IXGBE_SFF_DDM_IMPLEMENTED)) { 3359 /* We have a SFP, but it does not support SFF-8472 */ 3360 modinfo->type = ETH_MODULE_SFF_8079; 3361 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 3362 } else { 3363 /* We have a SFP which supports a revision of SFF-8472. */ 3364 modinfo->type = ETH_MODULE_SFF_8472; 3365 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 3366 } 3367 3368 return 0; 3369 } 3370 3371 static int ixgbe_get_module_eeprom(struct net_device *dev, 3372 struct ethtool_eeprom *ee, 3373 u8 *data) 3374 { 3375 struct ixgbe_adapter *adapter = netdev_priv(dev); 3376 struct ixgbe_hw *hw = &adapter->hw; 3377 int status = -EFAULT; 3378 u8 databyte = 0xFF; 3379 int i = 0; 3380 3381 if (ee->len == 0) 3382 return -EINVAL; 3383 3384 if (hw->phy.type == ixgbe_phy_fw) 3385 return -ENXIO; 3386 3387 for (i = ee->offset; i < ee->offset + ee->len; i++) { 3388 /* I2C reads can take long time */ 3389 if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 3390 return -EBUSY; 3391 3392 if (i < ETH_MODULE_SFF_8079_LEN) 3393 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); 3394 else 3395 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); 3396 3397 if (status) 3398 return -EIO; 3399 3400 data[i - ee->offset] = databyte; 3401 } 3402 3403 return 0; 3404 } 3405 3406 static const struct { 3407 ixgbe_link_speed mac_speed; 3408 u32 link_mode; 3409 } ixgbe_ls_map[] = { 3410 { IXGBE_LINK_SPEED_10_FULL, ETHTOOL_LINK_MODE_10baseT_Full_BIT }, 3411 { IXGBE_LINK_SPEED_100_FULL, ETHTOOL_LINK_MODE_100baseT_Full_BIT }, 3412 { IXGBE_LINK_SPEED_1GB_FULL, ETHTOOL_LINK_MODE_1000baseT_Full_BIT }, 3413 { IXGBE_LINK_SPEED_2_5GB_FULL, ETHTOOL_LINK_MODE_2500baseX_Full_BIT }, 3414 { IXGBE_LINK_SPEED_10GB_FULL, ETHTOOL_LINK_MODE_10000baseT_Full_BIT }, 3415 }; 3416 3417 static const struct { 3418 u32 lp_advertised; 3419 u32 link_mode; 3420 } ixgbe_lp_map[] = { 3421 { FW_PHY_ACT_UD_2_100M_TX_EEE, ETHTOOL_LINK_MODE_100baseT_Full_BIT }, 3422 { FW_PHY_ACT_UD_2_1G_T_EEE, ETHTOOL_LINK_MODE_1000baseT_Full_BIT }, 3423 { FW_PHY_ACT_UD_2_10G_T_EEE, ETHTOOL_LINK_MODE_10000baseT_Full_BIT }, 3424 { FW_PHY_ACT_UD_2_1G_KX_EEE, ETHTOOL_LINK_MODE_1000baseKX_Full_BIT }, 3425 { FW_PHY_ACT_UD_2_10G_KX4_EEE, ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT }, 3426 { FW_PHY_ACT_UD_2_10G_KR_EEE, ETHTOOL_LINK_MODE_10000baseKR_Full_BIT}, 3427 }; 3428 3429 static int 3430 ixgbe_get_eee_fw(struct ixgbe_adapter *adapter, struct ethtool_keee *edata) 3431 { 3432 __ETHTOOL_DECLARE_LINK_MODE_MASK(common); 3433 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 3434 struct ixgbe_hw *hw = &adapter->hw; 3435 int rc; 3436 u16 i; 3437 3438 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_UD_2, &info); 3439 if (rc) 3440 return rc; 3441 3442 for (i = 0; i < ARRAY_SIZE(ixgbe_lp_map); ++i) { 3443 if (info[0] & ixgbe_lp_map[i].lp_advertised) 3444 linkmode_set_bit(ixgbe_lp_map[i].link_mode, 3445 edata->lp_advertised); 3446 } 3447 3448 for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) { 3449 if (hw->phy.eee_speeds_supported & ixgbe_ls_map[i].mac_speed) 3450 linkmode_set_bit(ixgbe_lp_map[i].link_mode, 3451 edata->supported); 3452 } 3453 3454 for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) { 3455 if (hw->phy.eee_speeds_advertised & ixgbe_ls_map[i].mac_speed) 3456 linkmode_set_bit(ixgbe_lp_map[i].link_mode, 3457 edata->advertised); 3458 } 3459 3460 edata->eee_enabled = !linkmode_empty(edata->advertised); 3461 edata->tx_lpi_enabled = edata->eee_enabled; 3462 3463 linkmode_and(common, edata->advertised, edata->lp_advertised); 3464 edata->eee_active = !linkmode_empty(common); 3465 3466 return 0; 3467 } 3468 3469 static int ixgbe_get_eee(struct net_device *netdev, struct ethtool_keee *edata) 3470 { 3471 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3472 struct ixgbe_hw *hw = &adapter->hw; 3473 3474 if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE)) 3475 return -EOPNOTSUPP; 3476 3477 if (hw->phy.eee_speeds_supported && hw->phy.type == ixgbe_phy_fw) 3478 return ixgbe_get_eee_fw(adapter, edata); 3479 3480 return -EOPNOTSUPP; 3481 } 3482 3483 static int ixgbe_set_eee(struct net_device *netdev, struct ethtool_keee *edata) 3484 { 3485 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3486 struct ixgbe_hw *hw = &adapter->hw; 3487 struct ethtool_keee eee_data; 3488 int ret_val; 3489 3490 if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE)) 3491 return -EOPNOTSUPP; 3492 3493 memset(&eee_data, 0, sizeof(struct ethtool_keee)); 3494 3495 ret_val = ixgbe_get_eee(netdev, &eee_data); 3496 if (ret_val) 3497 return ret_val; 3498 3499 if (eee_data.eee_enabled && !edata->eee_enabled) { 3500 if (eee_data.tx_lpi_enabled != edata->tx_lpi_enabled) { 3501 e_err(drv, "Setting EEE tx-lpi is not supported\n"); 3502 return -EINVAL; 3503 } 3504 3505 if (eee_data.tx_lpi_timer != edata->tx_lpi_timer) { 3506 e_err(drv, 3507 "Setting EEE Tx LPI timer is not supported\n"); 3508 return -EINVAL; 3509 } 3510 3511 if (!linkmode_equal(eee_data.advertised, edata->advertised)) { 3512 e_err(drv, 3513 "Setting EEE advertised speeds is not supported\n"); 3514 return -EINVAL; 3515 } 3516 } 3517 3518 if (eee_data.eee_enabled != edata->eee_enabled) { 3519 if (edata->eee_enabled) { 3520 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 3521 hw->phy.eee_speeds_advertised = 3522 hw->phy.eee_speeds_supported; 3523 } else { 3524 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 3525 hw->phy.eee_speeds_advertised = 0; 3526 } 3527 3528 /* reset link */ 3529 if (netif_running(netdev)) 3530 ixgbe_reinit_locked(adapter); 3531 else 3532 ixgbe_reset(adapter); 3533 } 3534 3535 return 0; 3536 } 3537 3538 static u32 ixgbe_get_priv_flags(struct net_device *netdev) 3539 { 3540 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3541 u32 priv_flags = 0; 3542 3543 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 3544 priv_flags |= IXGBE_PRIV_FLAGS_LEGACY_RX; 3545 3546 if (adapter->flags2 & IXGBE_FLAG2_VF_IPSEC_ENABLED) 3547 priv_flags |= IXGBE_PRIV_FLAGS_VF_IPSEC_EN; 3548 3549 if (adapter->flags2 & IXGBE_FLAG2_AUTO_DISABLE_VF) 3550 priv_flags |= IXGBE_PRIV_FLAGS_AUTO_DISABLE_VF; 3551 3552 return priv_flags; 3553 } 3554 3555 static int ixgbe_set_priv_flags(struct net_device *netdev, u32 priv_flags) 3556 { 3557 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3558 unsigned int flags2 = adapter->flags2; 3559 unsigned int i; 3560 3561 flags2 &= ~IXGBE_FLAG2_RX_LEGACY; 3562 if (priv_flags & IXGBE_PRIV_FLAGS_LEGACY_RX) 3563 flags2 |= IXGBE_FLAG2_RX_LEGACY; 3564 3565 flags2 &= ~IXGBE_FLAG2_VF_IPSEC_ENABLED; 3566 if (priv_flags & IXGBE_PRIV_FLAGS_VF_IPSEC_EN) 3567 flags2 |= IXGBE_FLAG2_VF_IPSEC_ENABLED; 3568 3569 flags2 &= ~IXGBE_FLAG2_AUTO_DISABLE_VF; 3570 if (priv_flags & IXGBE_PRIV_FLAGS_AUTO_DISABLE_VF) { 3571 if (adapter->hw.mac.type == ixgbe_mac_82599EB) { 3572 /* Reset primary abort counter */ 3573 for (i = 0; i < adapter->num_vfs; i++) 3574 adapter->vfinfo[i].primary_abort_count = 0; 3575 3576 flags2 |= IXGBE_FLAG2_AUTO_DISABLE_VF; 3577 } else { 3578 e_info(probe, 3579 "Cannot set private flags: Operation not supported\n"); 3580 return -EOPNOTSUPP; 3581 } 3582 } 3583 3584 if (flags2 != adapter->flags2) { 3585 adapter->flags2 = flags2; 3586 3587 /* reset interface to repopulate queues */ 3588 if (netif_running(netdev)) 3589 ixgbe_reinit_locked(adapter); 3590 } 3591 3592 return 0; 3593 } 3594 3595 static const struct ethtool_ops ixgbe_ethtool_ops = { 3596 .supported_coalesce_params = ETHTOOL_COALESCE_USECS, 3597 .get_drvinfo = ixgbe_get_drvinfo, 3598 .get_regs_len = ixgbe_get_regs_len, 3599 .get_regs = ixgbe_get_regs, 3600 .get_wol = ixgbe_get_wol, 3601 .set_wol = ixgbe_set_wol, 3602 .nway_reset = ixgbe_nway_reset, 3603 .get_link = ethtool_op_get_link, 3604 .get_eeprom_len = ixgbe_get_eeprom_len, 3605 .get_eeprom = ixgbe_get_eeprom, 3606 .set_eeprom = ixgbe_set_eeprom, 3607 .get_ringparam = ixgbe_get_ringparam, 3608 .set_ringparam = ixgbe_set_ringparam, 3609 .get_pause_stats = ixgbe_get_pause_stats, 3610 .get_pauseparam = ixgbe_get_pauseparam, 3611 .set_pauseparam = ixgbe_set_pauseparam, 3612 .get_msglevel = ixgbe_get_msglevel, 3613 .set_msglevel = ixgbe_set_msglevel, 3614 .self_test = ixgbe_diag_test, 3615 .get_strings = ixgbe_get_strings, 3616 .set_phys_id = ixgbe_set_phys_id, 3617 .get_sset_count = ixgbe_get_sset_count, 3618 .get_ethtool_stats = ixgbe_get_ethtool_stats, 3619 .get_coalesce = ixgbe_get_coalesce, 3620 .set_coalesce = ixgbe_set_coalesce, 3621 .get_rxnfc = ixgbe_get_rxnfc, 3622 .set_rxnfc = ixgbe_set_rxnfc, 3623 .get_rxfh_indir_size = ixgbe_rss_indir_size, 3624 .get_rxfh_key_size = ixgbe_get_rxfh_key_size, 3625 .get_rxfh = ixgbe_get_rxfh, 3626 .set_rxfh = ixgbe_set_rxfh, 3627 .get_eee = ixgbe_get_eee, 3628 .set_eee = ixgbe_set_eee, 3629 .get_channels = ixgbe_get_channels, 3630 .set_channels = ixgbe_set_channels, 3631 .get_priv_flags = ixgbe_get_priv_flags, 3632 .set_priv_flags = ixgbe_set_priv_flags, 3633 .get_ts_info = ixgbe_get_ts_info, 3634 .get_module_info = ixgbe_get_module_info, 3635 .get_module_eeprom = ixgbe_get_module_eeprom, 3636 .get_link_ksettings = ixgbe_get_link_ksettings, 3637 .set_link_ksettings = ixgbe_set_link_ksettings, 3638 }; 3639 3640 void ixgbe_set_ethtool_ops(struct net_device *netdev) 3641 { 3642 netdev->ethtool_ops = &ixgbe_ethtool_ops; 3643 } 3644