1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2024 Intel Corporation. */ 3 4 #include "ixgbe_common.h" 5 #include "ixgbe_e610.h" 6 #include "ixgbe_x550.h" 7 #include "ixgbe_type.h" 8 #include "ixgbe_x540.h" 9 #include "ixgbe_mbx.h" 10 #include "ixgbe_phy.h" 11 12 /** 13 * ixgbe_should_retry_aci_send_cmd_execute - decide if ACI command should 14 * be resent 15 * @opcode: ACI opcode 16 * 17 * Check if ACI command should be sent again depending on the provided opcode. 18 * It may happen when CSR is busy during link state changes. 19 * 20 * Return: true if the sending command routine should be repeated, 21 * otherwise false. 22 */ 23 static bool ixgbe_should_retry_aci_send_cmd_execute(u16 opcode) 24 { 25 switch (opcode) { 26 case ixgbe_aci_opc_disable_rxen: 27 case ixgbe_aci_opc_get_phy_caps: 28 case ixgbe_aci_opc_get_link_status: 29 case ixgbe_aci_opc_get_link_topo: 30 return true; 31 } 32 33 return false; 34 } 35 36 /** 37 * ixgbe_aci_send_cmd_execute - execute sending FW Admin Command to FW Admin 38 * Command Interface 39 * @hw: pointer to the HW struct 40 * @desc: descriptor describing the command 41 * @buf: buffer to use for indirect commands (NULL for direct commands) 42 * @buf_size: size of buffer for indirect commands (0 for direct commands) 43 * 44 * Admin Command is sent using CSR by setting descriptor and buffer in specific 45 * registers. 46 * 47 * Return: the exit code of the operation. 48 * * - 0 - success. 49 * * - -EIO - CSR mechanism is not enabled. 50 * * - -EBUSY - CSR mechanism is busy. 51 * * - -EINVAL - buf_size is too big or 52 * invalid argument buf or buf_size. 53 * * - -ETIME - Admin Command X command timeout. 54 * * - -EIO - Admin Command X invalid state of HICR register or 55 * Admin Command failed because of bad opcode was returned or 56 * Admin Command failed with error Y. 57 */ 58 static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw *hw, 59 struct ixgbe_aci_desc *desc, 60 void *buf, u16 buf_size) 61 { 62 u16 opcode, buf_tail_size = buf_size % 4; 63 u32 *raw_desc = (u32 *)desc; 64 u32 hicr, i, buf_tail = 0; 65 bool valid_buf = false; 66 67 hw->aci.last_status = IXGBE_ACI_RC_OK; 68 69 /* It's necessary to check if mechanism is enabled */ 70 hicr = IXGBE_READ_REG(hw, IXGBE_PF_HICR); 71 72 if (!(hicr & IXGBE_PF_HICR_EN)) 73 return -EIO; 74 75 if (hicr & IXGBE_PF_HICR_C) { 76 hw->aci.last_status = IXGBE_ACI_RC_EBUSY; 77 return -EBUSY; 78 } 79 80 opcode = le16_to_cpu(desc->opcode); 81 82 if (buf_size > IXGBE_ACI_MAX_BUFFER_SIZE) 83 return -EINVAL; 84 85 if (buf) 86 desc->flags |= cpu_to_le16(IXGBE_ACI_FLAG_BUF); 87 88 if (desc->flags & cpu_to_le16(IXGBE_ACI_FLAG_BUF)) { 89 if ((buf && !buf_size) || 90 (!buf && buf_size)) 91 return -EINVAL; 92 if (buf && buf_size) 93 valid_buf = true; 94 } 95 96 if (valid_buf) { 97 if (buf_tail_size) 98 memcpy(&buf_tail, buf + buf_size - buf_tail_size, 99 buf_tail_size); 100 101 if (((buf_size + 3) & ~0x3) > IXGBE_ACI_LG_BUF) 102 desc->flags |= cpu_to_le16(IXGBE_ACI_FLAG_LB); 103 104 desc->datalen = cpu_to_le16(buf_size); 105 106 if (desc->flags & cpu_to_le16(IXGBE_ACI_FLAG_RD)) { 107 for (i = 0; i < buf_size / 4; i++) 108 IXGBE_WRITE_REG(hw, IXGBE_PF_HIBA(i), ((u32 *)buf)[i]); 109 if (buf_tail_size) 110 IXGBE_WRITE_REG(hw, IXGBE_PF_HIBA(i), buf_tail); 111 } 112 } 113 114 /* Descriptor is written to specific registers */ 115 for (i = 0; i < IXGBE_ACI_DESC_SIZE_IN_DWORDS; i++) 116 IXGBE_WRITE_REG(hw, IXGBE_PF_HIDA(i), raw_desc[i]); 117 118 /* SW has to set PF_HICR.C bit and clear PF_HICR.SV and 119 * PF_HICR_EV 120 */ 121 hicr = (IXGBE_READ_REG(hw, IXGBE_PF_HICR) | IXGBE_PF_HICR_C) & 122 ~(IXGBE_PF_HICR_SV | IXGBE_PF_HICR_EV); 123 IXGBE_WRITE_REG(hw, IXGBE_PF_HICR, hicr); 124 125 #define MAX_SLEEP_RESP_US 1000 126 #define MAX_TMOUT_RESP_SYNC_US 100000000 127 128 /* Wait for sync Admin Command response */ 129 read_poll_timeout(IXGBE_READ_REG, hicr, 130 (hicr & IXGBE_PF_HICR_SV) || 131 !(hicr & IXGBE_PF_HICR_C), 132 MAX_SLEEP_RESP_US, MAX_TMOUT_RESP_SYNC_US, true, hw, 133 IXGBE_PF_HICR); 134 135 #define MAX_TMOUT_RESP_ASYNC_US 150000000 136 137 /* Wait for async Admin Command response */ 138 read_poll_timeout(IXGBE_READ_REG, hicr, 139 (hicr & IXGBE_PF_HICR_EV) || 140 !(hicr & IXGBE_PF_HICR_C), 141 MAX_SLEEP_RESP_US, MAX_TMOUT_RESP_ASYNC_US, true, hw, 142 IXGBE_PF_HICR); 143 144 /* Read sync Admin Command response */ 145 if ((hicr & IXGBE_PF_HICR_SV)) { 146 for (i = 0; i < IXGBE_ACI_DESC_SIZE_IN_DWORDS; i++) { 147 raw_desc[i] = IXGBE_READ_REG(hw, IXGBE_PF_HIDA(i)); 148 raw_desc[i] = raw_desc[i]; 149 } 150 } 151 152 /* Read async Admin Command response */ 153 if ((hicr & IXGBE_PF_HICR_EV) && !(hicr & IXGBE_PF_HICR_C)) { 154 for (i = 0; i < IXGBE_ACI_DESC_SIZE_IN_DWORDS; i++) { 155 raw_desc[i] = IXGBE_READ_REG(hw, IXGBE_PF_HIDA_2(i)); 156 raw_desc[i] = raw_desc[i]; 157 } 158 } 159 160 /* Handle timeout and invalid state of HICR register */ 161 if (hicr & IXGBE_PF_HICR_C) 162 return -ETIME; 163 164 if (!(hicr & IXGBE_PF_HICR_SV) && !(hicr & IXGBE_PF_HICR_EV)) 165 return -EIO; 166 167 /* For every command other than 0x0014 treat opcode mismatch 168 * as an error. Response to 0x0014 command read from HIDA_2 169 * is a descriptor of an event which is expected to contain 170 * different opcode than the command. 171 */ 172 if (desc->opcode != cpu_to_le16(opcode) && 173 opcode != ixgbe_aci_opc_get_fw_event) 174 return -EIO; 175 176 if (desc->retval) { 177 hw->aci.last_status = (enum ixgbe_aci_err) 178 le16_to_cpu(desc->retval); 179 return -EIO; 180 } 181 182 /* Write a response values to a buf */ 183 if (valid_buf) { 184 for (i = 0; i < buf_size / 4; i++) 185 ((u32 *)buf)[i] = IXGBE_READ_REG(hw, IXGBE_PF_HIBA(i)); 186 if (buf_tail_size) { 187 buf_tail = IXGBE_READ_REG(hw, IXGBE_PF_HIBA(i)); 188 memcpy(buf + buf_size - buf_tail_size, &buf_tail, 189 buf_tail_size); 190 } 191 } 192 193 return 0; 194 } 195 196 /** 197 * ixgbe_aci_send_cmd - send FW Admin Command to FW Admin Command Interface 198 * @hw: pointer to the HW struct 199 * @desc: descriptor describing the command 200 * @buf: buffer to use for indirect commands (NULL for direct commands) 201 * @buf_size: size of buffer for indirect commands (0 for direct commands) 202 * 203 * Helper function to send FW Admin Commands to the FW Admin Command Interface. 204 * 205 * Retry sending the FW Admin Command multiple times to the FW ACI 206 * if the EBUSY Admin Command error is returned. 207 * 208 * Return: the exit code of the operation. 209 */ 210 int ixgbe_aci_send_cmd(struct ixgbe_hw *hw, struct ixgbe_aci_desc *desc, 211 void *buf, u16 buf_size) 212 { 213 u16 opcode = le16_to_cpu(desc->opcode); 214 struct ixgbe_aci_desc desc_cpy; 215 enum ixgbe_aci_err last_status; 216 u8 idx = 0, *buf_cpy = NULL; 217 bool is_cmd_for_retry; 218 unsigned long timeout; 219 int err; 220 221 is_cmd_for_retry = ixgbe_should_retry_aci_send_cmd_execute(opcode); 222 if (is_cmd_for_retry) { 223 if (buf) { 224 buf_cpy = kmalloc(buf_size, GFP_KERNEL); 225 if (!buf_cpy) 226 return -ENOMEM; 227 *buf_cpy = *(u8 *)buf; 228 } 229 desc_cpy = *desc; 230 } 231 232 timeout = jiffies + msecs_to_jiffies(IXGBE_ACI_SEND_TIMEOUT_MS); 233 do { 234 mutex_lock(&hw->aci.lock); 235 err = ixgbe_aci_send_cmd_execute(hw, desc, buf, buf_size); 236 last_status = hw->aci.last_status; 237 mutex_unlock(&hw->aci.lock); 238 239 if (!is_cmd_for_retry || !err || 240 last_status != IXGBE_ACI_RC_EBUSY) 241 break; 242 243 if (buf) 244 memcpy(buf, buf_cpy, buf_size); 245 *desc = desc_cpy; 246 247 msleep(IXGBE_ACI_SEND_DELAY_TIME_MS); 248 } while (++idx < IXGBE_ACI_SEND_MAX_EXECUTE && 249 time_before(jiffies, timeout)); 250 251 kfree(buf_cpy); 252 253 return err; 254 } 255 256 /** 257 * ixgbe_aci_check_event_pending - check if there are any pending events 258 * @hw: pointer to the HW struct 259 * 260 * Determine if there are any pending events. 261 * 262 * Return: true if there are any currently pending events 263 * otherwise false. 264 */ 265 bool ixgbe_aci_check_event_pending(struct ixgbe_hw *hw) 266 { 267 u32 ep_bit_mask = hw->bus.func ? GL_FWSTS_EP_PF1 : GL_FWSTS_EP_PF0; 268 u32 fwsts = IXGBE_READ_REG(hw, GL_FWSTS); 269 270 return (fwsts & ep_bit_mask) ? true : false; 271 } 272 273 /** 274 * ixgbe_aci_get_event - get an event from ACI 275 * @hw: pointer to the HW struct 276 * @e: event information structure 277 * @pending: optional flag signaling that there are more pending events 278 * 279 * Obtain an event from ACI and return its content 280 * through 'e' using ACI command (0x0014). 281 * Provide information if there are more events 282 * to retrieve through 'pending'. 283 * 284 * Return: the exit code of the operation. 285 */ 286 int ixgbe_aci_get_event(struct ixgbe_hw *hw, struct ixgbe_aci_event *e, 287 bool *pending) 288 { 289 struct ixgbe_aci_desc desc; 290 int err; 291 292 if (!e || (!e->msg_buf && e->buf_len)) 293 return -EINVAL; 294 295 mutex_lock(&hw->aci.lock); 296 297 /* Check if there are any events pending */ 298 if (!ixgbe_aci_check_event_pending(hw)) { 299 err = -ENOENT; 300 goto aci_get_event_exit; 301 } 302 303 /* Obtain pending event */ 304 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_fw_event); 305 err = ixgbe_aci_send_cmd_execute(hw, &desc, e->msg_buf, e->buf_len); 306 if (err) 307 goto aci_get_event_exit; 308 309 /* Returned 0x0014 opcode indicates that no event was obtained */ 310 if (desc.opcode == cpu_to_le16(ixgbe_aci_opc_get_fw_event)) { 311 err = -ENOENT; 312 goto aci_get_event_exit; 313 } 314 315 /* Determine size of event data */ 316 e->msg_len = min_t(u16, le16_to_cpu(desc.datalen), e->buf_len); 317 /* Write event descriptor to event info structure */ 318 memcpy(&e->desc, &desc, sizeof(e->desc)); 319 320 /* Check if there are any further events pending */ 321 if (pending) 322 *pending = ixgbe_aci_check_event_pending(hw); 323 324 aci_get_event_exit: 325 mutex_unlock(&hw->aci.lock); 326 327 return err; 328 } 329 330 /** 331 * ixgbe_fill_dflt_direct_cmd_desc - fill ACI descriptor with default values. 332 * @desc: pointer to the temp descriptor (non DMA mem) 333 * @opcode: the opcode can be used to decide which flags to turn off or on 334 * 335 * Helper function to fill the descriptor desc with default values 336 * and the provided opcode. 337 */ 338 void ixgbe_fill_dflt_direct_cmd_desc(struct ixgbe_aci_desc *desc, u16 opcode) 339 { 340 /* Zero out the desc. */ 341 memset(desc, 0, sizeof(*desc)); 342 desc->opcode = cpu_to_le16(opcode); 343 desc->flags = cpu_to_le16(IXGBE_ACI_FLAG_SI); 344 } 345 346 /** 347 * ixgbe_aci_get_fw_ver - Get the firmware version 348 * @hw: pointer to the HW struct 349 * 350 * Get the firmware version using ACI command (0x0001). 351 * 352 * Return: the exit code of the operation. 353 */ 354 static int ixgbe_aci_get_fw_ver(struct ixgbe_hw *hw) 355 { 356 struct ixgbe_aci_cmd_get_ver *resp; 357 struct ixgbe_aci_desc desc; 358 int err; 359 360 resp = &desc.params.get_ver; 361 362 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_ver); 363 364 err = ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 365 if (!err) { 366 hw->fw_branch = resp->fw_branch; 367 hw->fw_maj_ver = resp->fw_major; 368 hw->fw_min_ver = resp->fw_minor; 369 hw->fw_patch = resp->fw_patch; 370 hw->fw_build = le32_to_cpu(resp->fw_build); 371 hw->api_branch = resp->api_branch; 372 hw->api_maj_ver = resp->api_major; 373 hw->api_min_ver = resp->api_minor; 374 hw->api_patch = resp->api_patch; 375 } 376 377 return err; 378 } 379 380 /** 381 * ixgbe_aci_req_res - request a common resource 382 * @hw: pointer to the HW struct 383 * @res: resource ID 384 * @access: access type 385 * @sdp_number: resource number 386 * @timeout: the maximum time in ms that the driver may hold the resource 387 * 388 * Requests a common resource using the ACI command (0x0008). 389 * Specifies the maximum time the driver may hold the resource. 390 * If the requested resource is currently occupied by some other driver, 391 * a busy return value is returned and the timeout field value indicates the 392 * maximum time the current owner has to free it. 393 * 394 * Return: the exit code of the operation. 395 */ 396 static int ixgbe_aci_req_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res, 397 enum ixgbe_aci_res_access_type access, 398 u8 sdp_number, u32 *timeout) 399 { 400 struct ixgbe_aci_cmd_req_res *cmd_resp; 401 struct ixgbe_aci_desc desc; 402 int err; 403 404 cmd_resp = &desc.params.res_owner; 405 406 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_req_res); 407 408 cmd_resp->res_id = cpu_to_le16(res); 409 cmd_resp->access_type = cpu_to_le16(access); 410 cmd_resp->res_number = cpu_to_le32(sdp_number); 411 cmd_resp->timeout = cpu_to_le32(*timeout); 412 *timeout = 0; 413 414 err = ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 415 416 /* If the resource is held by some other driver, the command completes 417 * with a busy return value and the timeout field indicates the maximum 418 * time the current owner of the resource has to free it. 419 */ 420 if (!err || hw->aci.last_status == IXGBE_ACI_RC_EBUSY) 421 *timeout = le32_to_cpu(cmd_resp->timeout); 422 423 return err; 424 } 425 426 /** 427 * ixgbe_aci_release_res - release a common resource using ACI 428 * @hw: pointer to the HW struct 429 * @res: resource ID 430 * @sdp_number: resource number 431 * 432 * Release a common resource using ACI command (0x0009). 433 * 434 * Return: the exit code of the operation. 435 */ 436 static int ixgbe_aci_release_res(struct ixgbe_hw *hw, 437 enum ixgbe_aci_res_ids res, u8 sdp_number) 438 { 439 struct ixgbe_aci_cmd_req_res *cmd; 440 struct ixgbe_aci_desc desc; 441 442 cmd = &desc.params.res_owner; 443 444 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_release_res); 445 446 cmd->res_id = cpu_to_le16(res); 447 cmd->res_number = cpu_to_le32(sdp_number); 448 449 return ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 450 } 451 452 /** 453 * ixgbe_acquire_res - acquire the ownership of a resource 454 * @hw: pointer to the HW structure 455 * @res: resource ID 456 * @access: access type (read or write) 457 * @timeout: timeout in milliseconds 458 * 459 * Make an attempt to acquire the ownership of a resource using 460 * the ixgbe_aci_req_res to utilize ACI. 461 * In case if some other driver has previously acquired the resource and 462 * performed any necessary updates, the -EALREADY is returned, 463 * and the caller does not obtain the resource and has no further work to do. 464 * If needed, the function will poll until the current lock owner timeouts. 465 * 466 * Return: the exit code of the operation. 467 */ 468 int ixgbe_acquire_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res, 469 enum ixgbe_aci_res_access_type access, u32 timeout) 470 { 471 #define IXGBE_RES_POLLING_DELAY_MS 10 472 u32 delay = IXGBE_RES_POLLING_DELAY_MS; 473 u32 res_timeout = timeout; 474 u32 retry_timeout; 475 int err; 476 477 err = ixgbe_aci_req_res(hw, res, access, 0, &res_timeout); 478 479 /* A return code of -EALREADY means that another driver has 480 * previously acquired the resource and performed any necessary updates; 481 * in this case the caller does not obtain the resource and has no 482 * further work to do. 483 */ 484 if (err == -EALREADY) 485 return err; 486 487 /* If necessary, poll until the current lock owner timeouts. 488 * Set retry_timeout to the timeout value reported by the FW in the 489 * response to the "Request Resource Ownership" (0x0008) Admin Command 490 * as it indicates the maximum time the current owner of the resource 491 * is allowed to hold it. 492 */ 493 retry_timeout = res_timeout; 494 while (err && retry_timeout && res_timeout) { 495 msleep(delay); 496 retry_timeout = (retry_timeout > delay) ? 497 retry_timeout - delay : 0; 498 err = ixgbe_aci_req_res(hw, res, access, 0, &res_timeout); 499 500 /* Success - lock acquired. 501 * -EALREADY - lock free, no work to do. 502 */ 503 if (!err || err == -EALREADY) 504 break; 505 } 506 507 return err; 508 } 509 510 /** 511 * ixgbe_release_res - release a common resource 512 * @hw: pointer to the HW structure 513 * @res: resource ID 514 * 515 * Release a common resource using ixgbe_aci_release_res. 516 */ 517 void ixgbe_release_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res) 518 { 519 u32 total_delay = 0; 520 int err; 521 522 err = ixgbe_aci_release_res(hw, res, 0); 523 524 /* There are some rare cases when trying to release the resource 525 * results in an admin command timeout, so handle them correctly. 526 */ 527 while (err == -ETIME && 528 total_delay < IXGBE_ACI_RELEASE_RES_TIMEOUT) { 529 usleep_range(1000, 1500); 530 err = ixgbe_aci_release_res(hw, res, 0); 531 total_delay++; 532 } 533 } 534 535 /** 536 * ixgbe_parse_e610_caps - Parse common device/function capabilities 537 * @hw: pointer to the HW struct 538 * @caps: pointer to common capabilities structure 539 * @elem: the capability element to parse 540 * @prefix: message prefix for tracing capabilities 541 * 542 * Given a capability element, extract relevant details into the common 543 * capability structure. 544 * 545 * Return: true if the capability matches one of the common capability ids, 546 * false otherwise. 547 */ 548 static bool ixgbe_parse_e610_caps(struct ixgbe_hw *hw, 549 struct ixgbe_hw_caps *caps, 550 struct ixgbe_aci_cmd_list_caps_elem *elem, 551 const char *prefix) 552 { 553 u32 logical_id = le32_to_cpu(elem->logical_id); 554 u32 phys_id = le32_to_cpu(elem->phys_id); 555 u32 number = le32_to_cpu(elem->number); 556 u16 cap = le16_to_cpu(elem->cap); 557 558 switch (cap) { 559 case IXGBE_ACI_CAPS_VALID_FUNCTIONS: 560 caps->valid_functions = number; 561 break; 562 case IXGBE_ACI_CAPS_SRIOV: 563 caps->sr_iov_1_1 = (number == 1); 564 break; 565 case IXGBE_ACI_CAPS_VMDQ: 566 caps->vmdq = (number == 1); 567 break; 568 case IXGBE_ACI_CAPS_DCB: 569 caps->dcb = (number == 1); 570 caps->active_tc_bitmap = logical_id; 571 caps->maxtc = phys_id; 572 break; 573 case IXGBE_ACI_CAPS_RSS: 574 caps->rss_table_size = number; 575 caps->rss_table_entry_width = logical_id; 576 break; 577 case IXGBE_ACI_CAPS_RXQS: 578 caps->num_rxq = number; 579 caps->rxq_first_id = phys_id; 580 break; 581 case IXGBE_ACI_CAPS_TXQS: 582 caps->num_txq = number; 583 caps->txq_first_id = phys_id; 584 break; 585 case IXGBE_ACI_CAPS_MSIX: 586 caps->num_msix_vectors = number; 587 caps->msix_vector_first_id = phys_id; 588 break; 589 case IXGBE_ACI_CAPS_NVM_VER: 590 break; 591 case IXGBE_ACI_CAPS_PENDING_NVM_VER: 592 caps->nvm_update_pending_nvm = true; 593 break; 594 case IXGBE_ACI_CAPS_PENDING_OROM_VER: 595 caps->nvm_update_pending_orom = true; 596 break; 597 case IXGBE_ACI_CAPS_PENDING_NET_VER: 598 caps->nvm_update_pending_netlist = true; 599 break; 600 case IXGBE_ACI_CAPS_NVM_MGMT: 601 caps->nvm_unified_update = 602 (number & IXGBE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 603 true : false; 604 break; 605 case IXGBE_ACI_CAPS_MAX_MTU: 606 caps->max_mtu = number; 607 break; 608 case IXGBE_ACI_CAPS_PCIE_RESET_AVOIDANCE: 609 caps->pcie_reset_avoidance = (number > 0); 610 break; 611 case IXGBE_ACI_CAPS_POST_UPDATE_RESET_RESTRICT: 612 caps->reset_restrict_support = (number == 1); 613 break; 614 case IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG0: 615 case IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG1: 616 case IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG2: 617 case IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG3: 618 { 619 u8 index = cap - IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG0; 620 621 caps->ext_topo_dev_img_ver_high[index] = number; 622 caps->ext_topo_dev_img_ver_low[index] = logical_id; 623 caps->ext_topo_dev_img_part_num[index] = 624 FIELD_GET(IXGBE_EXT_TOPO_DEV_IMG_PART_NUM_M, phys_id); 625 caps->ext_topo_dev_img_load_en[index] = 626 (phys_id & IXGBE_EXT_TOPO_DEV_IMG_LOAD_EN) != 0; 627 caps->ext_topo_dev_img_prog_en[index] = 628 (phys_id & IXGBE_EXT_TOPO_DEV_IMG_PROG_EN) != 0; 629 break; 630 } 631 default: 632 /* Not one of the recognized common capabilities */ 633 return false; 634 } 635 636 return true; 637 } 638 639 /** 640 * ixgbe_parse_valid_functions_cap - Parse IXGBE_ACI_CAPS_VALID_FUNCTIONS caps 641 * @hw: pointer to the HW struct 642 * @dev_p: pointer to device capabilities structure 643 * @cap: capability element to parse 644 * 645 * Parse IXGBE_ACI_CAPS_VALID_FUNCTIONS for device capabilities. 646 */ 647 static void 648 ixgbe_parse_valid_functions_cap(struct ixgbe_hw *hw, 649 struct ixgbe_hw_dev_caps *dev_p, 650 struct ixgbe_aci_cmd_list_caps_elem *cap) 651 { 652 dev_p->num_funcs = hweight32(le32_to_cpu(cap->number)); 653 } 654 655 /** 656 * ixgbe_parse_vf_dev_caps - Parse IXGBE_ACI_CAPS_VF device caps 657 * @hw: pointer to the HW struct 658 * @dev_p: pointer to device capabilities structure 659 * @cap: capability element to parse 660 * 661 * Parse IXGBE_ACI_CAPS_VF for device capabilities. 662 */ 663 static void ixgbe_parse_vf_dev_caps(struct ixgbe_hw *hw, 664 struct ixgbe_hw_dev_caps *dev_p, 665 struct ixgbe_aci_cmd_list_caps_elem *cap) 666 { 667 dev_p->num_vfs_exposed = le32_to_cpu(cap->number); 668 } 669 670 /** 671 * ixgbe_parse_vsi_dev_caps - Parse IXGBE_ACI_CAPS_VSI device caps 672 * @hw: pointer to the HW struct 673 * @dev_p: pointer to device capabilities structure 674 * @cap: capability element to parse 675 * 676 * Parse IXGBE_ACI_CAPS_VSI for device capabilities. 677 */ 678 static void ixgbe_parse_vsi_dev_caps(struct ixgbe_hw *hw, 679 struct ixgbe_hw_dev_caps *dev_p, 680 struct ixgbe_aci_cmd_list_caps_elem *cap) 681 { 682 dev_p->num_vsi_allocd_to_host = le32_to_cpu(cap->number); 683 } 684 685 /** 686 * ixgbe_parse_fdir_dev_caps - Parse IXGBE_ACI_CAPS_FD device caps 687 * @hw: pointer to the HW struct 688 * @dev_p: pointer to device capabilities structure 689 * @cap: capability element to parse 690 * 691 * Parse IXGBE_ACI_CAPS_FD for device capabilities. 692 */ 693 static void ixgbe_parse_fdir_dev_caps(struct ixgbe_hw *hw, 694 struct ixgbe_hw_dev_caps *dev_p, 695 struct ixgbe_aci_cmd_list_caps_elem *cap) 696 { 697 dev_p->num_flow_director_fltr = le32_to_cpu(cap->number); 698 } 699 700 /** 701 * ixgbe_parse_dev_caps - Parse device capabilities 702 * @hw: pointer to the HW struct 703 * @dev_p: pointer to device capabilities structure 704 * @buf: buffer containing the device capability records 705 * @cap_count: the number of capabilities 706 * 707 * Helper device to parse device (0x000B) capabilities list. For 708 * capabilities shared between device and function, this relies on 709 * ixgbe_parse_e610_caps. 710 * 711 * Loop through the list of provided capabilities and extract the relevant 712 * data into the device capabilities structured. 713 */ 714 static void ixgbe_parse_dev_caps(struct ixgbe_hw *hw, 715 struct ixgbe_hw_dev_caps *dev_p, 716 void *buf, u32 cap_count) 717 { 718 struct ixgbe_aci_cmd_list_caps_elem *cap_resp; 719 u32 i; 720 721 cap_resp = (struct ixgbe_aci_cmd_list_caps_elem *)buf; 722 723 memset(dev_p, 0, sizeof(*dev_p)); 724 725 for (i = 0; i < cap_count; i++) { 726 u16 cap = le16_to_cpu(cap_resp[i].cap); 727 728 ixgbe_parse_e610_caps(hw, &dev_p->common_cap, &cap_resp[i], 729 "dev caps"); 730 731 switch (cap) { 732 case IXGBE_ACI_CAPS_VALID_FUNCTIONS: 733 ixgbe_parse_valid_functions_cap(hw, dev_p, 734 &cap_resp[i]); 735 break; 736 case IXGBE_ACI_CAPS_VF: 737 ixgbe_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 738 break; 739 case IXGBE_ACI_CAPS_VSI: 740 ixgbe_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 741 break; 742 case IXGBE_ACI_CAPS_FD: 743 ixgbe_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 744 break; 745 default: 746 /* Don't list common capabilities as unknown */ 747 break; 748 } 749 } 750 } 751 752 /** 753 * ixgbe_parse_vf_func_caps - Parse IXGBE_ACI_CAPS_VF function caps 754 * @hw: pointer to the HW struct 755 * @func_p: pointer to function capabilities structure 756 * @cap: pointer to the capability element to parse 757 * 758 * Extract function capabilities for IXGBE_ACI_CAPS_VF. 759 */ 760 static void ixgbe_parse_vf_func_caps(struct ixgbe_hw *hw, 761 struct ixgbe_hw_func_caps *func_p, 762 struct ixgbe_aci_cmd_list_caps_elem *cap) 763 { 764 func_p->num_allocd_vfs = le32_to_cpu(cap->number); 765 func_p->vf_base_id = le32_to_cpu(cap->logical_id); 766 } 767 768 /** 769 * ixgbe_get_num_per_func - determine number of resources per PF 770 * @hw: pointer to the HW structure 771 * @max: value to be evenly split between each PF 772 * 773 * Determine the number of valid functions by going through the bitmap returned 774 * from parsing capabilities and use this to calculate the number of resources 775 * per PF based on the max value passed in. 776 * 777 * Return: the number of resources per PF or 0, if no PH are available. 778 */ 779 static u32 ixgbe_get_num_per_func(struct ixgbe_hw *hw, u32 max) 780 { 781 #define IXGBE_CAPS_VALID_FUNCS_M GENMASK(7, 0) 782 u8 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 783 IXGBE_CAPS_VALID_FUNCS_M); 784 785 return funcs ? (max / funcs) : 0; 786 } 787 788 /** 789 * ixgbe_parse_vsi_func_caps - Parse IXGBE_ACI_CAPS_VSI function caps 790 * @hw: pointer to the HW struct 791 * @func_p: pointer to function capabilities structure 792 * @cap: pointer to the capability element to parse 793 * 794 * Extract function capabilities for IXGBE_ACI_CAPS_VSI. 795 */ 796 static void ixgbe_parse_vsi_func_caps(struct ixgbe_hw *hw, 797 struct ixgbe_hw_func_caps *func_p, 798 struct ixgbe_aci_cmd_list_caps_elem *cap) 799 { 800 func_p->guar_num_vsi = ixgbe_get_num_per_func(hw, IXGBE_MAX_VSI); 801 } 802 803 /** 804 * ixgbe_parse_func_caps - Parse function capabilities 805 * @hw: pointer to the HW struct 806 * @func_p: pointer to function capabilities structure 807 * @buf: buffer containing the function capability records 808 * @cap_count: the number of capabilities 809 * 810 * Helper function to parse function (0x000A) capabilities list. For 811 * capabilities shared between device and function, this relies on 812 * ixgbe_parse_e610_caps. 813 * 814 * Loop through the list of provided capabilities and extract the relevant 815 * data into the function capabilities structured. 816 */ 817 static void ixgbe_parse_func_caps(struct ixgbe_hw *hw, 818 struct ixgbe_hw_func_caps *func_p, 819 void *buf, u32 cap_count) 820 { 821 struct ixgbe_aci_cmd_list_caps_elem *cap_resp; 822 u32 i; 823 824 cap_resp = (struct ixgbe_aci_cmd_list_caps_elem *)buf; 825 826 memset(func_p, 0, sizeof(*func_p)); 827 828 for (i = 0; i < cap_count; i++) { 829 u16 cap = le16_to_cpu(cap_resp[i].cap); 830 831 ixgbe_parse_e610_caps(hw, &func_p->common_cap, 832 &cap_resp[i], "func caps"); 833 834 switch (cap) { 835 case IXGBE_ACI_CAPS_VF: 836 ixgbe_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 837 break; 838 case IXGBE_ACI_CAPS_VSI: 839 ixgbe_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 840 break; 841 default: 842 /* Don't list common capabilities as unknown */ 843 break; 844 } 845 } 846 } 847 848 /** 849 * ixgbe_aci_list_caps - query function/device capabilities 850 * @hw: pointer to the HW struct 851 * @buf: a buffer to hold the capabilities 852 * @buf_size: size of the buffer 853 * @cap_count: if not NULL, set to the number of capabilities reported 854 * @opc: capabilities type to discover, device or function 855 * 856 * Get the function (0x000A) or device (0x000B) capabilities description from 857 * firmware and store it in the buffer. 858 * 859 * If the cap_count pointer is not NULL, then it is set to the number of 860 * capabilities firmware will report. Note that if the buffer size is too 861 * small, it is possible the command will return -ENOMEM. The 862 * cap_count will still be updated in this case. It is recommended that the 863 * buffer size be set to IXGBE_ACI_MAX_BUFFER_SIZE (the largest possible 864 * buffer that firmware could return) to avoid this. 865 * 866 * Return: the exit code of the operation. 867 * Exit code of -ENOMEM means the buffer size is too small. 868 */ 869 int ixgbe_aci_list_caps(struct ixgbe_hw *hw, void *buf, u16 buf_size, 870 u32 *cap_count, enum ixgbe_aci_opc opc) 871 { 872 struct ixgbe_aci_cmd_list_caps *cmd; 873 struct ixgbe_aci_desc desc; 874 int err; 875 876 cmd = &desc.params.get_cap; 877 878 if (opc != ixgbe_aci_opc_list_func_caps && 879 opc != ixgbe_aci_opc_list_dev_caps) 880 return -EINVAL; 881 882 ixgbe_fill_dflt_direct_cmd_desc(&desc, opc); 883 err = ixgbe_aci_send_cmd(hw, &desc, buf, buf_size); 884 885 if (cap_count) 886 *cap_count = le32_to_cpu(cmd->count); 887 888 return err; 889 } 890 891 /** 892 * ixgbe_discover_dev_caps - Read and extract device capabilities 893 * @hw: pointer to the hardware structure 894 * @dev_caps: pointer to device capabilities structure 895 * 896 * Read the device capabilities and extract them into the dev_caps structure 897 * for later use. 898 * 899 * Return: the exit code of the operation. 900 */ 901 int ixgbe_discover_dev_caps(struct ixgbe_hw *hw, 902 struct ixgbe_hw_dev_caps *dev_caps) 903 { 904 u32 cap_count; 905 u8 *cbuf; 906 int err; 907 908 cbuf = kzalloc(IXGBE_ACI_MAX_BUFFER_SIZE, GFP_KERNEL); 909 if (!cbuf) 910 return -ENOMEM; 911 912 /* Although the driver doesn't know the number of capabilities the 913 * device will return, we can simply send a 4KB buffer, the maximum 914 * possible size that firmware can return. 915 */ 916 cap_count = IXGBE_ACI_MAX_BUFFER_SIZE / 917 sizeof(struct ixgbe_aci_cmd_list_caps_elem); 918 919 err = ixgbe_aci_list_caps(hw, cbuf, IXGBE_ACI_MAX_BUFFER_SIZE, 920 &cap_count, 921 ixgbe_aci_opc_list_dev_caps); 922 if (!err) 923 ixgbe_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 924 925 kfree(cbuf); 926 927 return 0; 928 } 929 930 /** 931 * ixgbe_discover_func_caps - Read and extract function capabilities 932 * @hw: pointer to the hardware structure 933 * @func_caps: pointer to function capabilities structure 934 * 935 * Read the function capabilities and extract them into the func_caps structure 936 * for later use. 937 * 938 * Return: the exit code of the operation. 939 */ 940 int ixgbe_discover_func_caps(struct ixgbe_hw *hw, 941 struct ixgbe_hw_func_caps *func_caps) 942 { 943 u32 cap_count; 944 u8 *cbuf; 945 int err; 946 947 cbuf = kzalloc(IXGBE_ACI_MAX_BUFFER_SIZE, GFP_KERNEL); 948 if (!cbuf) 949 return -ENOMEM; 950 951 /* Although the driver doesn't know the number of capabilities the 952 * device will return, we can simply send a 4KB buffer, the maximum 953 * possible size that firmware can return. 954 */ 955 cap_count = IXGBE_ACI_MAX_BUFFER_SIZE / 956 sizeof(struct ixgbe_aci_cmd_list_caps_elem); 957 958 err = ixgbe_aci_list_caps(hw, cbuf, IXGBE_ACI_MAX_BUFFER_SIZE, 959 &cap_count, 960 ixgbe_aci_opc_list_func_caps); 961 if (!err) 962 ixgbe_parse_func_caps(hw, func_caps, cbuf, cap_count); 963 964 kfree(cbuf); 965 966 return 0; 967 } 968 969 /** 970 * ixgbe_get_caps - get info about the HW 971 * @hw: pointer to the hardware structure 972 * 973 * Retrieve both device and function capabilities. 974 * 975 * Return: the exit code of the operation. 976 */ 977 int ixgbe_get_caps(struct ixgbe_hw *hw) 978 { 979 int err; 980 981 err = ixgbe_discover_dev_caps(hw, &hw->dev_caps); 982 if (err) 983 return err; 984 985 return ixgbe_discover_func_caps(hw, &hw->func_caps); 986 } 987 988 /** 989 * ixgbe_aci_disable_rxen - disable RX 990 * @hw: pointer to the HW struct 991 * 992 * Request a safe disable of Receive Enable using ACI command (0x000C). 993 * 994 * Return: the exit code of the operation. 995 */ 996 int ixgbe_aci_disable_rxen(struct ixgbe_hw *hw) 997 { 998 struct ixgbe_aci_cmd_disable_rxen *cmd; 999 struct ixgbe_aci_desc desc; 1000 1001 cmd = &desc.params.disable_rxen; 1002 1003 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_disable_rxen); 1004 1005 cmd->lport_num = hw->bus.func; 1006 1007 return ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 1008 } 1009 1010 /** 1011 * ixgbe_aci_get_phy_caps - returns PHY capabilities 1012 * @hw: pointer to the HW struct 1013 * @qual_mods: report qualified modules 1014 * @report_mode: report mode capabilities 1015 * @pcaps: structure for PHY capabilities to be filled 1016 * 1017 * Returns the various PHY capabilities supported on the Port 1018 * using ACI command (0x0600). 1019 * 1020 * Return: the exit code of the operation. 1021 */ 1022 int ixgbe_aci_get_phy_caps(struct ixgbe_hw *hw, bool qual_mods, u8 report_mode, 1023 struct ixgbe_aci_cmd_get_phy_caps_data *pcaps) 1024 { 1025 struct ixgbe_aci_cmd_get_phy_caps *cmd; 1026 u16 pcaps_size = sizeof(*pcaps); 1027 struct ixgbe_aci_desc desc; 1028 int err; 1029 1030 cmd = &desc.params.get_phy; 1031 1032 if (!pcaps || (report_mode & ~IXGBE_ACI_REPORT_MODE_M)) 1033 return -EINVAL; 1034 1035 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_phy_caps); 1036 1037 if (qual_mods) 1038 cmd->param0 |= cpu_to_le16(IXGBE_ACI_GET_PHY_RQM); 1039 1040 cmd->param0 |= cpu_to_le16(report_mode); 1041 err = ixgbe_aci_send_cmd(hw, &desc, pcaps, pcaps_size); 1042 if (!err && report_mode == IXGBE_ACI_REPORT_TOPO_CAP_MEDIA) { 1043 hw->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 1044 hw->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 1045 memcpy(hw->link.link_info.module_type, &pcaps->module_type, 1046 sizeof(hw->link.link_info.module_type)); 1047 } 1048 1049 return err; 1050 } 1051 1052 /** 1053 * ixgbe_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 1054 * @caps: PHY ability structure to copy data from 1055 * @cfg: PHY configuration structure to copy data to 1056 * 1057 * Helper function to copy data from PHY capabilities data structure 1058 * to PHY configuration data structure 1059 */ 1060 void ixgbe_copy_phy_caps_to_cfg(struct ixgbe_aci_cmd_get_phy_caps_data *caps, 1061 struct ixgbe_aci_cmd_set_phy_cfg_data *cfg) 1062 { 1063 if (!caps || !cfg) 1064 return; 1065 1066 memset(cfg, 0, sizeof(*cfg)); 1067 cfg->phy_type_low = caps->phy_type_low; 1068 cfg->phy_type_high = caps->phy_type_high; 1069 cfg->caps = caps->caps; 1070 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 1071 cfg->eee_cap = caps->eee_cap; 1072 cfg->eeer_value = caps->eeer_value; 1073 cfg->link_fec_opt = caps->link_fec_options; 1074 cfg->module_compliance_enforcement = 1075 caps->module_compliance_enforcement; 1076 } 1077 1078 /** 1079 * ixgbe_aci_set_phy_cfg - set PHY configuration 1080 * @hw: pointer to the HW struct 1081 * @cfg: structure with PHY configuration data to be set 1082 * 1083 * Set the various PHY configuration parameters supported on the Port 1084 * using ACI command (0x0601). 1085 * One or more of the Set PHY config parameters may be ignored in an MFP 1086 * mode as the PF may not have the privilege to set some of the PHY Config 1087 * parameters. 1088 * 1089 * Return: the exit code of the operation. 1090 */ 1091 int ixgbe_aci_set_phy_cfg(struct ixgbe_hw *hw, 1092 struct ixgbe_aci_cmd_set_phy_cfg_data *cfg) 1093 { 1094 struct ixgbe_aci_desc desc; 1095 int err; 1096 1097 if (!cfg) 1098 return -EINVAL; 1099 1100 /* Ensure that only valid bits of cfg->caps can be turned on. */ 1101 cfg->caps &= IXGBE_ACI_PHY_ENA_VALID_MASK; 1102 1103 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_set_phy_cfg); 1104 desc.params.set_phy.lport_num = hw->bus.func; 1105 desc.flags |= cpu_to_le16(IXGBE_ACI_FLAG_RD); 1106 1107 err = ixgbe_aci_send_cmd(hw, &desc, cfg, sizeof(*cfg)); 1108 if (!err) 1109 hw->phy.curr_user_phy_cfg = *cfg; 1110 1111 return err; 1112 } 1113 1114 /** 1115 * ixgbe_aci_set_link_restart_an - set up link and restart AN 1116 * @hw: pointer to the HW struct 1117 * @ena_link: if true: enable link, if false: disable link 1118 * 1119 * Function sets up the link and restarts the Auto-Negotiation over the link. 1120 * 1121 * Return: the exit code of the operation. 1122 */ 1123 int ixgbe_aci_set_link_restart_an(struct ixgbe_hw *hw, bool ena_link) 1124 { 1125 struct ixgbe_aci_cmd_restart_an *cmd; 1126 struct ixgbe_aci_desc desc; 1127 1128 cmd = &desc.params.restart_an; 1129 1130 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_restart_an); 1131 1132 cmd->cmd_flags = IXGBE_ACI_RESTART_AN_LINK_RESTART; 1133 cmd->lport_num = hw->bus.func; 1134 if (ena_link) 1135 cmd->cmd_flags |= IXGBE_ACI_RESTART_AN_LINK_ENABLE; 1136 else 1137 cmd->cmd_flags &= ~IXGBE_ACI_RESTART_AN_LINK_ENABLE; 1138 1139 return ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 1140 } 1141 1142 /** 1143 * ixgbe_is_media_cage_present - check if media cage is present 1144 * @hw: pointer to the HW struct 1145 * 1146 * Identify presence of media cage using the ACI command (0x06E0). 1147 * 1148 * Return: true if media cage is present, else false. If no cage, then 1149 * media type is backplane or BASE-T. 1150 */ 1151 static bool ixgbe_is_media_cage_present(struct ixgbe_hw *hw) 1152 { 1153 struct ixgbe_aci_cmd_get_link_topo *cmd; 1154 struct ixgbe_aci_desc desc; 1155 1156 cmd = &desc.params.get_link_topo; 1157 1158 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_link_topo); 1159 1160 cmd->addr.topo_params.node_type_ctx = 1161 FIELD_PREP(IXGBE_ACI_LINK_TOPO_NODE_CTX_M, 1162 IXGBE_ACI_LINK_TOPO_NODE_CTX_PORT); 1163 1164 /* Set node type. */ 1165 cmd->addr.topo_params.node_type_ctx |= 1166 FIELD_PREP(IXGBE_ACI_LINK_TOPO_NODE_TYPE_M, 1167 IXGBE_ACI_LINK_TOPO_NODE_TYPE_CAGE); 1168 1169 /* Node type cage can be used to determine if cage is present. If AQC 1170 * returns error (ENOENT), then no cage present. If no cage present then 1171 * connection type is backplane or BASE-T. 1172 */ 1173 return !ixgbe_aci_get_netlist_node(hw, cmd, NULL, NULL); 1174 } 1175 1176 /** 1177 * ixgbe_get_media_type_from_phy_type - Gets media type based on phy type 1178 * @hw: pointer to the HW struct 1179 * 1180 * Try to identify the media type based on the phy type. 1181 * If more than one media type, the ixgbe_media_type_unknown is returned. 1182 * First, phy_type_low is checked, then phy_type_high. 1183 * If none are identified, the ixgbe_media_type_unknown is returned 1184 * 1185 * Return: type of a media based on phy type in form of enum. 1186 */ 1187 static enum ixgbe_media_type 1188 ixgbe_get_media_type_from_phy_type(struct ixgbe_hw *hw) 1189 { 1190 struct ixgbe_link_status *hw_link_info; 1191 1192 if (!hw) 1193 return ixgbe_media_type_unknown; 1194 1195 hw_link_info = &hw->link.link_info; 1196 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 1197 /* If more than one media type is selected, report unknown */ 1198 return ixgbe_media_type_unknown; 1199 1200 if (hw_link_info->phy_type_low) { 1201 /* 1G SGMII is a special case where some DA cable PHYs 1202 * may show this as an option when it really shouldn't 1203 * be since SGMII is meant to be between a MAC and a PHY 1204 * in a backplane. Try to detect this case and handle it 1205 */ 1206 if (hw_link_info->phy_type_low == IXGBE_PHY_TYPE_LOW_1G_SGMII && 1207 (hw_link_info->module_type[IXGBE_ACI_MOD_TYPE_IDENT] == 1208 IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 1209 hw_link_info->module_type[IXGBE_ACI_MOD_TYPE_IDENT] == 1210 IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 1211 return ixgbe_media_type_da; 1212 1213 switch (hw_link_info->phy_type_low) { 1214 case IXGBE_PHY_TYPE_LOW_1000BASE_SX: 1215 case IXGBE_PHY_TYPE_LOW_1000BASE_LX: 1216 case IXGBE_PHY_TYPE_LOW_10GBASE_SR: 1217 case IXGBE_PHY_TYPE_LOW_10GBASE_LR: 1218 case IXGBE_PHY_TYPE_LOW_25GBASE_SR: 1219 case IXGBE_PHY_TYPE_LOW_25GBASE_LR: 1220 return ixgbe_media_type_fiber; 1221 case IXGBE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 1222 case IXGBE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 1223 return ixgbe_media_type_fiber; 1224 case IXGBE_PHY_TYPE_LOW_100BASE_TX: 1225 case IXGBE_PHY_TYPE_LOW_1000BASE_T: 1226 case IXGBE_PHY_TYPE_LOW_2500BASE_T: 1227 case IXGBE_PHY_TYPE_LOW_5GBASE_T: 1228 case IXGBE_PHY_TYPE_LOW_10GBASE_T: 1229 case IXGBE_PHY_TYPE_LOW_25GBASE_T: 1230 return ixgbe_media_type_copper; 1231 case IXGBE_PHY_TYPE_LOW_10G_SFI_DA: 1232 case IXGBE_PHY_TYPE_LOW_25GBASE_CR: 1233 case IXGBE_PHY_TYPE_LOW_25GBASE_CR_S: 1234 case IXGBE_PHY_TYPE_LOW_25GBASE_CR1: 1235 return ixgbe_media_type_da; 1236 case IXGBE_PHY_TYPE_LOW_25G_AUI_C2C: 1237 if (ixgbe_is_media_cage_present(hw)) 1238 return ixgbe_media_type_aui; 1239 fallthrough; 1240 case IXGBE_PHY_TYPE_LOW_1000BASE_KX: 1241 case IXGBE_PHY_TYPE_LOW_2500BASE_KX: 1242 case IXGBE_PHY_TYPE_LOW_2500BASE_X: 1243 case IXGBE_PHY_TYPE_LOW_5GBASE_KR: 1244 case IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1: 1245 case IXGBE_PHY_TYPE_LOW_10G_SFI_C2C: 1246 case IXGBE_PHY_TYPE_LOW_25GBASE_KR: 1247 case IXGBE_PHY_TYPE_LOW_25GBASE_KR1: 1248 case IXGBE_PHY_TYPE_LOW_25GBASE_KR_S: 1249 return ixgbe_media_type_backplane; 1250 } 1251 } else { 1252 switch (hw_link_info->phy_type_high) { 1253 case IXGBE_PHY_TYPE_HIGH_10BASE_T: 1254 return ixgbe_media_type_copper; 1255 } 1256 } 1257 return ixgbe_media_type_unknown; 1258 } 1259 1260 /** 1261 * ixgbe_update_link_info - update status of the HW network link 1262 * @hw: pointer to the HW struct 1263 * 1264 * Update the status of the HW network link. 1265 * 1266 * Return: the exit code of the operation. 1267 */ 1268 int ixgbe_update_link_info(struct ixgbe_hw *hw) 1269 { 1270 struct ixgbe_aci_cmd_get_phy_caps_data *pcaps; 1271 struct ixgbe_link_status *li; 1272 int err; 1273 1274 if (!hw) 1275 return -EINVAL; 1276 1277 li = &hw->link.link_info; 1278 1279 err = ixgbe_aci_get_link_info(hw, true, NULL); 1280 if (err) 1281 return err; 1282 1283 if (!(li->link_info & IXGBE_ACI_MEDIA_AVAILABLE)) 1284 return 0; 1285 1286 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 1287 if (!pcaps) 1288 return -ENOMEM; 1289 1290 err = ixgbe_aci_get_phy_caps(hw, false, IXGBE_ACI_REPORT_TOPO_CAP_MEDIA, 1291 pcaps); 1292 1293 if (!err) 1294 memcpy(li->module_type, &pcaps->module_type, 1295 sizeof(li->module_type)); 1296 1297 kfree(pcaps); 1298 1299 return err; 1300 } 1301 1302 /** 1303 * ixgbe_get_link_status - get status of the HW network link 1304 * @hw: pointer to the HW struct 1305 * @link_up: pointer to bool (true/false = linkup/linkdown) 1306 * 1307 * Variable link_up is true if link is up, false if link is down. 1308 * The variable link_up is invalid if status is non zero. As a 1309 * result of this call, link status reporting becomes enabled 1310 * 1311 * Return: the exit code of the operation. 1312 */ 1313 int ixgbe_get_link_status(struct ixgbe_hw *hw, bool *link_up) 1314 { 1315 if (!hw || !link_up) 1316 return -EINVAL; 1317 1318 if (hw->link.get_link_info) { 1319 int err = ixgbe_update_link_info(hw); 1320 1321 if (err) 1322 return err; 1323 } 1324 1325 *link_up = hw->link.link_info.link_info & IXGBE_ACI_LINK_UP; 1326 1327 return 0; 1328 } 1329 1330 /** 1331 * ixgbe_aci_get_link_info - get the link status 1332 * @hw: pointer to the HW struct 1333 * @ena_lse: enable/disable LinkStatusEvent reporting 1334 * @link: pointer to link status structure - optional 1335 * 1336 * Get the current Link Status using ACI command (0x607). 1337 * The current link can be optionally provided to update 1338 * the status. 1339 * 1340 * Return: the link status of the adapter. 1341 */ 1342 int ixgbe_aci_get_link_info(struct ixgbe_hw *hw, bool ena_lse, 1343 struct ixgbe_link_status *link) 1344 { 1345 struct ixgbe_aci_cmd_get_link_status_data link_data = {}; 1346 struct ixgbe_aci_cmd_get_link_status *resp; 1347 struct ixgbe_link_status *li_old, *li; 1348 struct ixgbe_fc_info *hw_fc_info; 1349 struct ixgbe_aci_desc desc; 1350 bool tx_pause, rx_pause; 1351 u8 cmd_flags; 1352 int err; 1353 1354 if (!hw) 1355 return -EINVAL; 1356 1357 li_old = &hw->link.link_info_old; 1358 li = &hw->link.link_info; 1359 hw_fc_info = &hw->fc; 1360 1361 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_link_status); 1362 cmd_flags = (ena_lse) ? IXGBE_ACI_LSE_ENA : IXGBE_ACI_LSE_DIS; 1363 resp = &desc.params.get_link_status; 1364 resp->cmd_flags = cpu_to_le16(cmd_flags); 1365 resp->lport_num = hw->bus.func; 1366 1367 err = ixgbe_aci_send_cmd(hw, &desc, &link_data, sizeof(link_data)); 1368 if (err) 1369 return err; 1370 1371 /* Save off old link status information. */ 1372 *li_old = *li; 1373 1374 /* Update current link status information. */ 1375 li->link_speed = le16_to_cpu(link_data.link_speed); 1376 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 1377 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 1378 li->link_info = link_data.link_info; 1379 li->link_cfg_err = link_data.link_cfg_err; 1380 li->an_info = link_data.an_info; 1381 li->ext_info = link_data.ext_info; 1382 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 1383 li->fec_info = link_data.cfg & IXGBE_ACI_FEC_MASK; 1384 li->topo_media_conflict = link_data.topo_media_conflict; 1385 li->pacing = link_data.cfg & (IXGBE_ACI_CFG_PACING_M | 1386 IXGBE_ACI_CFG_PACING_TYPE_M); 1387 1388 /* Update fc info. */ 1389 tx_pause = !!(link_data.an_info & IXGBE_ACI_LINK_PAUSE_TX); 1390 rx_pause = !!(link_data.an_info & IXGBE_ACI_LINK_PAUSE_RX); 1391 if (tx_pause && rx_pause) 1392 hw_fc_info->current_mode = ixgbe_fc_full; 1393 else if (tx_pause) 1394 hw_fc_info->current_mode = ixgbe_fc_tx_pause; 1395 else if (rx_pause) 1396 hw_fc_info->current_mode = ixgbe_fc_rx_pause; 1397 else 1398 hw_fc_info->current_mode = ixgbe_fc_none; 1399 1400 li->lse_ena = !!(le16_to_cpu(resp->cmd_flags) & 1401 IXGBE_ACI_LSE_IS_ENABLED); 1402 1403 /* Save link status information. */ 1404 if (link) 1405 *link = *li; 1406 1407 /* Flag cleared so calling functions don't call AQ again. */ 1408 hw->link.get_link_info = false; 1409 1410 return 0; 1411 } 1412 1413 /** 1414 * ixgbe_aci_set_event_mask - set event mask 1415 * @hw: pointer to the HW struct 1416 * @port_num: port number of the physical function 1417 * @mask: event mask to be set 1418 * 1419 * Set the event mask using ACI command (0x0613). 1420 * 1421 * Return: the exit code of the operation. 1422 */ 1423 int ixgbe_aci_set_event_mask(struct ixgbe_hw *hw, u8 port_num, u16 mask) 1424 { 1425 struct ixgbe_aci_cmd_set_event_mask *cmd; 1426 struct ixgbe_aci_desc desc; 1427 1428 cmd = &desc.params.set_event_mask; 1429 1430 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_set_event_mask); 1431 1432 cmd->lport_num = port_num; 1433 1434 cmd->event_mask = cpu_to_le16(mask); 1435 return ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 1436 } 1437 1438 /** 1439 * ixgbe_configure_lse - enable/disable link status events 1440 * @hw: pointer to the HW struct 1441 * @activate: true for enable lse, false otherwise 1442 * @mask: event mask to be set; a set bit means deactivation of the 1443 * corresponding event 1444 * 1445 * Set the event mask and then enable or disable link status events 1446 * 1447 * Return: the exit code of the operation. 1448 */ 1449 int ixgbe_configure_lse(struct ixgbe_hw *hw, bool activate, u16 mask) 1450 { 1451 int err; 1452 1453 err = ixgbe_aci_set_event_mask(hw, (u8)hw->bus.func, mask); 1454 if (err) 1455 return err; 1456 1457 /* Enabling link status events generation by fw. */ 1458 return ixgbe_aci_get_link_info(hw, activate, NULL); 1459 } 1460 1461 /** 1462 * ixgbe_start_hw_e610 - Prepare hardware for Tx/Rx 1463 * @hw: pointer to hardware structure 1464 * 1465 * Get firmware version and start the hardware using the generic 1466 * start_hw() and ixgbe_start_hw_gen2() functions. 1467 * 1468 * Return: the exit code of the operation. 1469 */ 1470 static int ixgbe_start_hw_e610(struct ixgbe_hw *hw) 1471 { 1472 int err; 1473 1474 err = ixgbe_aci_get_fw_ver(hw); 1475 if (err) 1476 return err; 1477 1478 err = ixgbe_start_hw_generic(hw); 1479 if (err) 1480 return err; 1481 1482 ixgbe_start_hw_gen2(hw); 1483 1484 return 0; 1485 } 1486 1487 /** 1488 * ixgbe_get_media_type_e610 - Gets media type 1489 * @hw: pointer to the HW struct 1490 * 1491 * In order to get the media type, the function gets PHY 1492 * capabilities and later on use them to identify the PHY type 1493 * checking phy_type_high and phy_type_low. 1494 * 1495 * Return: the type of media in form of ixgbe_media_type enum 1496 * or ixgbe_media_type_unknown in case of an error. 1497 */ 1498 enum ixgbe_media_type ixgbe_get_media_type_e610(struct ixgbe_hw *hw) 1499 { 1500 struct ixgbe_aci_cmd_get_phy_caps_data pcaps; 1501 int rc; 1502 1503 rc = ixgbe_update_link_info(hw); 1504 if (rc) 1505 return ixgbe_media_type_unknown; 1506 1507 /* If there is no link but PHY (dongle) is available SW should use 1508 * Get PHY Caps admin command instead of Get Link Status, find most 1509 * significant bit that is set in PHY types reported by the command 1510 * and use it to discover media type. 1511 */ 1512 if (!(hw->link.link_info.link_info & IXGBE_ACI_LINK_UP) && 1513 (hw->link.link_info.link_info & IXGBE_ACI_MEDIA_AVAILABLE)) { 1514 int highest_bit; 1515 1516 /* Get PHY Capabilities */ 1517 rc = ixgbe_aci_get_phy_caps(hw, false, 1518 IXGBE_ACI_REPORT_TOPO_CAP_MEDIA, 1519 &pcaps); 1520 if (rc) 1521 return ixgbe_media_type_unknown; 1522 1523 highest_bit = fls64(le64_to_cpu(pcaps.phy_type_high)); 1524 if (highest_bit) { 1525 hw->link.link_info.phy_type_high = 1526 BIT_ULL(highest_bit - 1); 1527 hw->link.link_info.phy_type_low = 0; 1528 } else { 1529 highest_bit = fls64(le64_to_cpu(pcaps.phy_type_low)); 1530 if (highest_bit) { 1531 hw->link.link_info.phy_type_low = 1532 BIT_ULL(highest_bit - 1); 1533 hw->link.link_info.phy_type_high = 0; 1534 } 1535 } 1536 } 1537 1538 /* Based on link status or search above try to discover media type. */ 1539 hw->phy.media_type = ixgbe_get_media_type_from_phy_type(hw); 1540 1541 return hw->phy.media_type; 1542 } 1543 1544 /** 1545 * ixgbe_setup_link_e610 - Set up link 1546 * @hw: pointer to hardware structure 1547 * @speed: new link speed 1548 * @autoneg_wait: true when waiting for completion is needed 1549 * 1550 * Set up the link with the specified speed. 1551 * 1552 * Return: the exit code of the operation. 1553 */ 1554 int ixgbe_setup_link_e610(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1555 bool autoneg_wait) 1556 { 1557 /* Simply request FW to perform proper PHY setup */ 1558 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 1559 } 1560 1561 /** 1562 * ixgbe_check_link_e610 - Determine link and speed status 1563 * @hw: pointer to hardware structure 1564 * @speed: pointer to link speed 1565 * @link_up: true when link is up 1566 * @link_up_wait_to_complete: bool used to wait for link up or not 1567 * 1568 * Determine if the link is up and the current link speed 1569 * using ACI command (0x0607). 1570 * 1571 * Return: the exit code of the operation. 1572 */ 1573 int ixgbe_check_link_e610(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 1574 bool *link_up, bool link_up_wait_to_complete) 1575 { 1576 int err; 1577 u32 i; 1578 1579 if (!speed || !link_up) 1580 return -EINVAL; 1581 1582 /* Set get_link_info flag to ensure that fresh 1583 * link information will be obtained from FW 1584 * by sending Get Link Status admin command. 1585 */ 1586 hw->link.get_link_info = true; 1587 1588 /* Update link information in adapter context. */ 1589 err = ixgbe_get_link_status(hw, link_up); 1590 if (err) 1591 return err; 1592 1593 /* Wait for link up if it was requested. */ 1594 if (link_up_wait_to_complete && !(*link_up)) { 1595 for (i = 0; i < hw->mac.max_link_up_time; i++) { 1596 msleep(100); 1597 hw->link.get_link_info = true; 1598 err = ixgbe_get_link_status(hw, link_up); 1599 if (err) 1600 return err; 1601 if (*link_up) 1602 break; 1603 } 1604 } 1605 1606 /* Use link information in adapter context updated by the call 1607 * to ixgbe_get_link_status() to determine current link speed. 1608 * Link speed information is valid only when link up was 1609 * reported by FW. 1610 */ 1611 if (*link_up) { 1612 switch (hw->link.link_info.link_speed) { 1613 case IXGBE_ACI_LINK_SPEED_10MB: 1614 *speed = IXGBE_LINK_SPEED_10_FULL; 1615 break; 1616 case IXGBE_ACI_LINK_SPEED_100MB: 1617 *speed = IXGBE_LINK_SPEED_100_FULL; 1618 break; 1619 case IXGBE_ACI_LINK_SPEED_1000MB: 1620 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1621 break; 1622 case IXGBE_ACI_LINK_SPEED_2500MB: 1623 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 1624 break; 1625 case IXGBE_ACI_LINK_SPEED_5GB: 1626 *speed = IXGBE_LINK_SPEED_5GB_FULL; 1627 break; 1628 case IXGBE_ACI_LINK_SPEED_10GB: 1629 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1630 break; 1631 default: 1632 *speed = IXGBE_LINK_SPEED_UNKNOWN; 1633 break; 1634 } 1635 } else { 1636 *speed = IXGBE_LINK_SPEED_UNKNOWN; 1637 } 1638 1639 return 0; 1640 } 1641 1642 /** 1643 * ixgbe_get_link_capabilities_e610 - Determine link capabilities 1644 * @hw: pointer to hardware structure 1645 * @speed: pointer to link speed 1646 * @autoneg: true when autoneg or autotry is enabled 1647 * 1648 * Determine speed and AN parameters of a link. 1649 * 1650 * Return: the exit code of the operation. 1651 */ 1652 int ixgbe_get_link_capabilities_e610(struct ixgbe_hw *hw, 1653 ixgbe_link_speed *speed, 1654 bool *autoneg) 1655 { 1656 if (!speed || !autoneg) 1657 return -EINVAL; 1658 1659 *autoneg = true; 1660 *speed = hw->phy.speeds_supported; 1661 1662 return 0; 1663 } 1664 1665 /** 1666 * ixgbe_cfg_phy_fc - Configure PHY Flow Control (FC) data based on FC mode 1667 * @hw: pointer to hardware structure 1668 * @cfg: PHY configuration data to set FC mode 1669 * @req_mode: FC mode to configure 1670 * 1671 * Configures PHY Flow Control according to the provided configuration. 1672 * 1673 * Return: the exit code of the operation. 1674 */ 1675 int ixgbe_cfg_phy_fc(struct ixgbe_hw *hw, 1676 struct ixgbe_aci_cmd_set_phy_cfg_data *cfg, 1677 enum ixgbe_fc_mode req_mode) 1678 { 1679 u8 pause_mask = 0x0; 1680 1681 if (!cfg) 1682 return -EINVAL; 1683 1684 switch (req_mode) { 1685 case ixgbe_fc_full: 1686 pause_mask |= IXGBE_ACI_PHY_EN_TX_LINK_PAUSE; 1687 pause_mask |= IXGBE_ACI_PHY_EN_RX_LINK_PAUSE; 1688 break; 1689 case ixgbe_fc_rx_pause: 1690 pause_mask |= IXGBE_ACI_PHY_EN_RX_LINK_PAUSE; 1691 break; 1692 case ixgbe_fc_tx_pause: 1693 pause_mask |= IXGBE_ACI_PHY_EN_TX_LINK_PAUSE; 1694 break; 1695 default: 1696 break; 1697 } 1698 1699 /* Clear the old pause settings. */ 1700 cfg->caps &= ~(IXGBE_ACI_PHY_EN_TX_LINK_PAUSE | 1701 IXGBE_ACI_PHY_EN_RX_LINK_PAUSE); 1702 1703 /* Set the new capabilities. */ 1704 cfg->caps |= pause_mask; 1705 1706 return 0; 1707 } 1708 1709 /** 1710 * ixgbe_setup_fc_e610 - Set up flow control 1711 * @hw: pointer to hardware structure 1712 * 1713 * Set up flow control. This has to be done during init time. 1714 * 1715 * Return: the exit code of the operation. 1716 */ 1717 int ixgbe_setup_fc_e610(struct ixgbe_hw *hw) 1718 { 1719 struct ixgbe_aci_cmd_get_phy_caps_data pcaps = {}; 1720 struct ixgbe_aci_cmd_set_phy_cfg_data cfg = {}; 1721 int err; 1722 1723 /* Get the current PHY config */ 1724 err = ixgbe_aci_get_phy_caps(hw, false, 1725 IXGBE_ACI_REPORT_ACTIVE_CFG, &pcaps); 1726 if (err) 1727 return err; 1728 1729 ixgbe_copy_phy_caps_to_cfg(&pcaps, &cfg); 1730 1731 /* Configure the set PHY data */ 1732 err = ixgbe_cfg_phy_fc(hw, &cfg, hw->fc.requested_mode); 1733 if (err) 1734 return err; 1735 1736 /* If the capabilities have changed, then set the new config */ 1737 if (cfg.caps != pcaps.caps) { 1738 cfg.caps |= IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT; 1739 1740 err = ixgbe_aci_set_phy_cfg(hw, &cfg); 1741 if (err) 1742 return err; 1743 } 1744 1745 return err; 1746 } 1747 1748 /** 1749 * ixgbe_fc_autoneg_e610 - Configure flow control 1750 * @hw: pointer to hardware structure 1751 * 1752 * Configure Flow Control. 1753 */ 1754 void ixgbe_fc_autoneg_e610(struct ixgbe_hw *hw) 1755 { 1756 int err; 1757 1758 /* Get current link err. 1759 * Current FC mode will be stored in the hw context. 1760 */ 1761 err = ixgbe_aci_get_link_info(hw, false, NULL); 1762 if (err) 1763 goto no_autoneg; 1764 1765 /* Check if the link is up */ 1766 if (!(hw->link.link_info.link_info & IXGBE_ACI_LINK_UP)) 1767 goto no_autoneg; 1768 1769 /* Check if auto-negotiation has completed */ 1770 if (!(hw->link.link_info.an_info & IXGBE_ACI_AN_COMPLETED)) 1771 goto no_autoneg; 1772 1773 hw->fc.fc_was_autonegged = true; 1774 return; 1775 1776 no_autoneg: 1777 hw->fc.fc_was_autonegged = false; 1778 hw->fc.current_mode = hw->fc.requested_mode; 1779 } 1780 1781 /** 1782 * ixgbe_disable_rx_e610 - Disable RX unit 1783 * @hw: pointer to hardware structure 1784 * 1785 * Disable RX DMA unit on E610 with use of ACI command (0x000C). 1786 * 1787 * Return: the exit code of the operation. 1788 */ 1789 void ixgbe_disable_rx_e610(struct ixgbe_hw *hw) 1790 { 1791 u32 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1792 u32 pfdtxgswc; 1793 int err; 1794 1795 if (!(rxctrl & IXGBE_RXCTRL_RXEN)) 1796 return; 1797 1798 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 1799 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 1800 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 1801 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 1802 hw->mac.set_lben = true; 1803 } else { 1804 hw->mac.set_lben = false; 1805 } 1806 1807 err = ixgbe_aci_disable_rxen(hw); 1808 1809 /* If we fail - disable RX using register write */ 1810 if (err) { 1811 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1812 if (rxctrl & IXGBE_RXCTRL_RXEN) { 1813 rxctrl &= ~IXGBE_RXCTRL_RXEN; 1814 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 1815 } 1816 } 1817 } 1818 1819 /** 1820 * ixgbe_init_phy_ops_e610 - PHY specific init 1821 * @hw: pointer to hardware structure 1822 * 1823 * Initialize any function pointers that were not able to be 1824 * set during init_shared_code because the PHY type was not known. 1825 * 1826 * Return: the exit code of the operation. 1827 */ 1828 int ixgbe_init_phy_ops_e610(struct ixgbe_hw *hw) 1829 { 1830 struct ixgbe_mac_info *mac = &hw->mac; 1831 struct ixgbe_phy_info *phy = &hw->phy; 1832 1833 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) 1834 phy->ops.set_phy_power = ixgbe_set_phy_power_e610; 1835 else 1836 phy->ops.set_phy_power = NULL; 1837 1838 /* Identify the PHY */ 1839 return phy->ops.identify(hw); 1840 } 1841 1842 /** 1843 * ixgbe_identify_phy_e610 - Identify PHY 1844 * @hw: pointer to hardware structure 1845 * 1846 * Determine PHY type, supported speeds and PHY ID. 1847 * 1848 * Return: the exit code of the operation. 1849 */ 1850 int ixgbe_identify_phy_e610(struct ixgbe_hw *hw) 1851 { 1852 struct ixgbe_aci_cmd_get_phy_caps_data pcaps; 1853 u64 phy_type_low, phy_type_high; 1854 int err; 1855 1856 /* Set PHY type */ 1857 hw->phy.type = ixgbe_phy_fw; 1858 1859 err = ixgbe_aci_get_phy_caps(hw, false, 1860 IXGBE_ACI_REPORT_TOPO_CAP_MEDIA, &pcaps); 1861 if (err) 1862 return err; 1863 1864 if (!(pcaps.module_compliance_enforcement & 1865 IXGBE_ACI_MOD_ENFORCE_STRICT_MODE)) { 1866 /* Handle lenient mode */ 1867 err = ixgbe_aci_get_phy_caps(hw, false, 1868 IXGBE_ACI_REPORT_TOPO_CAP_NO_MEDIA, 1869 &pcaps); 1870 if (err) 1871 return err; 1872 } 1873 1874 /* Determine supported speeds */ 1875 hw->phy.speeds_supported = IXGBE_LINK_SPEED_UNKNOWN; 1876 phy_type_high = le64_to_cpu(pcaps.phy_type_high); 1877 phy_type_low = le64_to_cpu(pcaps.phy_type_low); 1878 1879 if (phy_type_high & IXGBE_PHY_TYPE_HIGH_10BASE_T || 1880 phy_type_high & IXGBE_PHY_TYPE_HIGH_10M_SGMII) 1881 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10_FULL; 1882 if (phy_type_low & IXGBE_PHY_TYPE_LOW_100BASE_TX || 1883 phy_type_low & IXGBE_PHY_TYPE_LOW_100M_SGMII || 1884 phy_type_high & IXGBE_PHY_TYPE_HIGH_100M_USXGMII) 1885 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 1886 if (phy_type_low & IXGBE_PHY_TYPE_LOW_1000BASE_T || 1887 phy_type_low & IXGBE_PHY_TYPE_LOW_1000BASE_SX || 1888 phy_type_low & IXGBE_PHY_TYPE_LOW_1000BASE_LX || 1889 phy_type_low & IXGBE_PHY_TYPE_LOW_1000BASE_KX || 1890 phy_type_low & IXGBE_PHY_TYPE_LOW_1G_SGMII || 1891 phy_type_high & IXGBE_PHY_TYPE_HIGH_1G_USXGMII) 1892 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 1893 if (phy_type_low & IXGBE_PHY_TYPE_LOW_10GBASE_T || 1894 phy_type_low & IXGBE_PHY_TYPE_LOW_10G_SFI_DA || 1895 phy_type_low & IXGBE_PHY_TYPE_LOW_10GBASE_SR || 1896 phy_type_low & IXGBE_PHY_TYPE_LOW_10GBASE_LR || 1897 phy_type_low & IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1 || 1898 phy_type_low & IXGBE_PHY_TYPE_LOW_10G_SFI_AOC_ACC || 1899 phy_type_low & IXGBE_PHY_TYPE_LOW_10G_SFI_C2C || 1900 phy_type_high & IXGBE_PHY_TYPE_HIGH_10G_USXGMII) 1901 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 1902 1903 /* 2.5 and 5 Gbps link speeds must be excluded from the 1904 * auto-negotiation set used during driver initialization due to 1905 * compatibility issues with certain switches. Those issues do not 1906 * exist in case of E610 2.5G SKU device (0x57b1). 1907 */ 1908 if (!hw->phy.autoneg_advertised && 1909 hw->device_id != IXGBE_DEV_ID_E610_2_5G_T) 1910 hw->phy.autoneg_advertised = hw->phy.speeds_supported; 1911 1912 if (phy_type_low & IXGBE_PHY_TYPE_LOW_2500BASE_T || 1913 phy_type_low & IXGBE_PHY_TYPE_LOW_2500BASE_X || 1914 phy_type_low & IXGBE_PHY_TYPE_LOW_2500BASE_KX || 1915 phy_type_high & IXGBE_PHY_TYPE_HIGH_2500M_SGMII || 1916 phy_type_high & IXGBE_PHY_TYPE_HIGH_2500M_USXGMII) 1917 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 1918 1919 if (!hw->phy.autoneg_advertised && 1920 hw->device_id == IXGBE_DEV_ID_E610_2_5G_T) 1921 hw->phy.autoneg_advertised = hw->phy.speeds_supported; 1922 1923 if (phy_type_low & IXGBE_PHY_TYPE_LOW_5GBASE_T || 1924 phy_type_low & IXGBE_PHY_TYPE_LOW_5GBASE_KR || 1925 phy_type_high & IXGBE_PHY_TYPE_HIGH_5G_USXGMII) 1926 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 1927 1928 /* Set PHY ID */ 1929 memcpy(&hw->phy.id, pcaps.phy_id_oui, sizeof(u32)); 1930 1931 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_10_FULL | 1932 IXGBE_LINK_SPEED_100_FULL | 1933 IXGBE_LINK_SPEED_1GB_FULL; 1934 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported; 1935 1936 return 0; 1937 } 1938 1939 /** 1940 * ixgbe_identify_module_e610 - Identify SFP module type 1941 * @hw: pointer to hardware structure 1942 * 1943 * Identify the SFP module type. 1944 * 1945 * Return: the exit code of the operation. 1946 */ 1947 int ixgbe_identify_module_e610(struct ixgbe_hw *hw) 1948 { 1949 bool media_available; 1950 u8 module_type; 1951 int err; 1952 1953 err = ixgbe_update_link_info(hw); 1954 if (err) 1955 return err; 1956 1957 media_available = 1958 (hw->link.link_info.link_info & IXGBE_ACI_MEDIA_AVAILABLE); 1959 1960 if (media_available) { 1961 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1962 1963 /* Get module type from hw context updated by 1964 * ixgbe_update_link_info() 1965 */ 1966 module_type = hw->link.link_info.module_type[IXGBE_ACI_MOD_TYPE_IDENT]; 1967 1968 if ((module_type & IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE) || 1969 (module_type & IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE)) { 1970 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1971 } else if (module_type & IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_SR) { 1972 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1973 } else if ((module_type & IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_LR) || 1974 (module_type & IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_LRM)) { 1975 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1976 } 1977 } else { 1978 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1979 return -ENOENT; 1980 } 1981 1982 return 0; 1983 } 1984 1985 /** 1986 * ixgbe_setup_phy_link_e610 - Sets up firmware-controlled PHYs 1987 * @hw: pointer to hardware structure 1988 * 1989 * Set the parameters for the firmware-controlled PHYs. 1990 * 1991 * Return: the exit code of the operation. 1992 */ 1993 int ixgbe_setup_phy_link_e610(struct ixgbe_hw *hw) 1994 { 1995 struct ixgbe_aci_cmd_get_phy_caps_data pcaps; 1996 struct ixgbe_aci_cmd_set_phy_cfg_data pcfg; 1997 u8 rmode = IXGBE_ACI_REPORT_TOPO_CAP_MEDIA; 1998 u64 sup_phy_type_low, sup_phy_type_high; 1999 u64 phy_type_low = 0, phy_type_high = 0; 2000 int err; 2001 2002 err = ixgbe_aci_get_link_info(hw, false, NULL); 2003 if (err) 2004 return err; 2005 2006 /* If media is not available get default config. */ 2007 if (!(hw->link.link_info.link_info & IXGBE_ACI_MEDIA_AVAILABLE)) 2008 rmode = IXGBE_ACI_REPORT_DFLT_CFG; 2009 2010 err = ixgbe_aci_get_phy_caps(hw, false, rmode, &pcaps); 2011 if (err) 2012 return err; 2013 2014 sup_phy_type_low = le64_to_cpu(pcaps.phy_type_low); 2015 sup_phy_type_high = le64_to_cpu(pcaps.phy_type_high); 2016 2017 /* Get Active configuration to avoid unintended changes. */ 2018 err = ixgbe_aci_get_phy_caps(hw, false, IXGBE_ACI_REPORT_ACTIVE_CFG, 2019 &pcaps); 2020 if (err) 2021 return err; 2022 2023 ixgbe_copy_phy_caps_to_cfg(&pcaps, &pcfg); 2024 2025 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL) { 2026 phy_type_high |= IXGBE_PHY_TYPE_HIGH_10BASE_T; 2027 phy_type_high |= IXGBE_PHY_TYPE_HIGH_10M_SGMII; 2028 } 2029 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) { 2030 phy_type_low |= IXGBE_PHY_TYPE_LOW_100BASE_TX; 2031 phy_type_low |= IXGBE_PHY_TYPE_LOW_100M_SGMII; 2032 phy_type_high |= IXGBE_PHY_TYPE_HIGH_100M_USXGMII; 2033 } 2034 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) { 2035 phy_type_low |= IXGBE_PHY_TYPE_LOW_1000BASE_T; 2036 phy_type_low |= IXGBE_PHY_TYPE_LOW_1000BASE_SX; 2037 phy_type_low |= IXGBE_PHY_TYPE_LOW_1000BASE_LX; 2038 phy_type_low |= IXGBE_PHY_TYPE_LOW_1000BASE_KX; 2039 phy_type_low |= IXGBE_PHY_TYPE_LOW_1G_SGMII; 2040 phy_type_high |= IXGBE_PHY_TYPE_HIGH_1G_USXGMII; 2041 } 2042 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL) { 2043 phy_type_low |= IXGBE_PHY_TYPE_LOW_2500BASE_T; 2044 phy_type_low |= IXGBE_PHY_TYPE_LOW_2500BASE_X; 2045 phy_type_low |= IXGBE_PHY_TYPE_LOW_2500BASE_KX; 2046 phy_type_high |= IXGBE_PHY_TYPE_HIGH_2500M_SGMII; 2047 phy_type_high |= IXGBE_PHY_TYPE_HIGH_2500M_USXGMII; 2048 } 2049 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) { 2050 phy_type_low |= IXGBE_PHY_TYPE_LOW_5GBASE_T; 2051 phy_type_low |= IXGBE_PHY_TYPE_LOW_5GBASE_KR; 2052 phy_type_high |= IXGBE_PHY_TYPE_HIGH_5G_USXGMII; 2053 } 2054 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) { 2055 phy_type_low |= IXGBE_PHY_TYPE_LOW_10GBASE_T; 2056 phy_type_low |= IXGBE_PHY_TYPE_LOW_10G_SFI_DA; 2057 phy_type_low |= IXGBE_PHY_TYPE_LOW_10GBASE_SR; 2058 phy_type_low |= IXGBE_PHY_TYPE_LOW_10GBASE_LR; 2059 phy_type_low |= IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1; 2060 phy_type_low |= IXGBE_PHY_TYPE_LOW_10G_SFI_AOC_ACC; 2061 phy_type_low |= IXGBE_PHY_TYPE_LOW_10G_SFI_C2C; 2062 phy_type_high |= IXGBE_PHY_TYPE_HIGH_10G_USXGMII; 2063 } 2064 2065 /* Mask the set values to avoid requesting unsupported link types. */ 2066 phy_type_low &= sup_phy_type_low; 2067 pcfg.phy_type_low = cpu_to_le64(phy_type_low); 2068 phy_type_high &= sup_phy_type_high; 2069 pcfg.phy_type_high = cpu_to_le64(phy_type_high); 2070 2071 if (pcfg.phy_type_high != pcaps.phy_type_high || 2072 pcfg.phy_type_low != pcaps.phy_type_low || 2073 pcfg.caps != pcaps.caps) { 2074 pcfg.caps |= IXGBE_ACI_PHY_ENA_LINK; 2075 pcfg.caps |= IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT; 2076 2077 err = ixgbe_aci_set_phy_cfg(hw, &pcfg); 2078 if (err) 2079 return err; 2080 } 2081 2082 return 0; 2083 } 2084 2085 /** 2086 * ixgbe_set_phy_power_e610 - Control power for copper PHY 2087 * @hw: pointer to hardware structure 2088 * @on: true for on, false for off 2089 * 2090 * Set the power on/off of the PHY 2091 * by getting its capabilities and setting the appropriate 2092 * configuration parameters. 2093 * 2094 * Return: the exit code of the operation. 2095 */ 2096 int ixgbe_set_phy_power_e610(struct ixgbe_hw *hw, bool on) 2097 { 2098 struct ixgbe_aci_cmd_get_phy_caps_data phy_caps = {}; 2099 struct ixgbe_aci_cmd_set_phy_cfg_data phy_cfg = {}; 2100 int err; 2101 2102 err = ixgbe_aci_get_phy_caps(hw, false, 2103 IXGBE_ACI_REPORT_ACTIVE_CFG, 2104 &phy_caps); 2105 if (err) 2106 return err; 2107 2108 ixgbe_copy_phy_caps_to_cfg(&phy_caps, &phy_cfg); 2109 2110 if (on) 2111 phy_cfg.caps &= ~IXGBE_ACI_PHY_ENA_LOW_POWER; 2112 else 2113 phy_cfg.caps |= IXGBE_ACI_PHY_ENA_LOW_POWER; 2114 2115 /* PHY is already in requested power mode. */ 2116 if (phy_caps.caps == phy_cfg.caps) 2117 return 0; 2118 2119 phy_cfg.caps |= IXGBE_ACI_PHY_ENA_LINK; 2120 phy_cfg.caps |= IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT; 2121 2122 return ixgbe_aci_set_phy_cfg(hw, &phy_cfg); 2123 } 2124 2125 /** 2126 * ixgbe_enter_lplu_e610 - Transition to low power states 2127 * @hw: pointer to hardware structure 2128 * 2129 * Configures Low Power Link Up on transition to low power states 2130 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the 2131 * X557 PHY immediately prior to entering LPLU. 2132 * 2133 * Return: the exit code of the operation. 2134 */ 2135 int ixgbe_enter_lplu_e610(struct ixgbe_hw *hw) 2136 { 2137 struct ixgbe_aci_cmd_get_phy_caps_data phy_caps = {}; 2138 struct ixgbe_aci_cmd_set_phy_cfg_data phy_cfg = {}; 2139 int err; 2140 2141 err = ixgbe_aci_get_phy_caps(hw, false, 2142 IXGBE_ACI_REPORT_ACTIVE_CFG, 2143 &phy_caps); 2144 if (err) 2145 return err; 2146 2147 ixgbe_copy_phy_caps_to_cfg(&phy_caps, &phy_cfg); 2148 2149 phy_cfg.low_power_ctrl_an |= IXGBE_ACI_PHY_EN_D3COLD_LOW_POWER_AUTONEG; 2150 2151 return ixgbe_aci_set_phy_cfg(hw, &phy_cfg); 2152 } 2153 2154 /** 2155 * ixgbe_init_eeprom_params_e610 - Initialize EEPROM params 2156 * @hw: pointer to hardware structure 2157 * 2158 * Initialize the EEPROM parameters ixgbe_eeprom_info within the ixgbe_hw 2159 * struct in order to set up EEPROM access. 2160 * 2161 * Return: the operation exit code. 2162 */ 2163 int ixgbe_init_eeprom_params_e610(struct ixgbe_hw *hw) 2164 { 2165 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2166 u32 gens_stat; 2167 u8 sr_size; 2168 2169 if (eeprom->type != ixgbe_eeprom_uninitialized) 2170 return 0; 2171 2172 eeprom->type = ixgbe_flash; 2173 2174 gens_stat = IXGBE_READ_REG(hw, GLNVM_GENS); 2175 sr_size = FIELD_GET(GLNVM_GENS_SR_SIZE_M, gens_stat); 2176 2177 /* Switching to words (sr_size contains power of 2). */ 2178 eeprom->word_size = BIT(sr_size) * IXGBE_SR_WORDS_IN_1KB; 2179 2180 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", eeprom->type, 2181 eeprom->word_size); 2182 2183 return 0; 2184 } 2185 2186 /** 2187 * ixgbe_aci_get_netlist_node - get a node handle 2188 * @hw: pointer to the hw struct 2189 * @cmd: get_link_topo AQ structure 2190 * @node_part_number: output node part number if node found 2191 * @node_handle: output node handle parameter if node found 2192 * 2193 * Get the netlist node and assigns it to 2194 * the provided handle using ACI command (0x06E0). 2195 * 2196 * Return: the exit code of the operation. 2197 */ 2198 int ixgbe_aci_get_netlist_node(struct ixgbe_hw *hw, 2199 struct ixgbe_aci_cmd_get_link_topo *cmd, 2200 u8 *node_part_number, u16 *node_handle) 2201 { 2202 struct ixgbe_aci_desc desc; 2203 2204 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_link_topo); 2205 desc.params.get_link_topo = *cmd; 2206 2207 if (ixgbe_aci_send_cmd(hw, &desc, NULL, 0)) 2208 return -EOPNOTSUPP; 2209 2210 if (node_handle) 2211 *node_handle = 2212 le16_to_cpu(desc.params.get_link_topo.addr.handle); 2213 if (node_part_number) 2214 *node_part_number = desc.params.get_link_topo.node_part_num; 2215 2216 return 0; 2217 } 2218 2219 /** 2220 * ixgbe_acquire_nvm - Generic request for acquiring the NVM ownership 2221 * @hw: pointer to the HW structure 2222 * @access: NVM access type (read or write) 2223 * 2224 * Request NVM ownership. 2225 * 2226 * Return: the exit code of the operation. 2227 */ 2228 int ixgbe_acquire_nvm(struct ixgbe_hw *hw, 2229 enum ixgbe_aci_res_access_type access) 2230 { 2231 u32 fla; 2232 2233 /* Skip if we are in blank NVM programming mode */ 2234 fla = IXGBE_READ_REG(hw, IXGBE_GLNVM_FLA); 2235 if ((fla & IXGBE_GLNVM_FLA_LOCKED_M) == 0) 2236 return 0; 2237 2238 return ixgbe_acquire_res(hw, IXGBE_NVM_RES_ID, access, 2239 IXGBE_NVM_TIMEOUT); 2240 } 2241 2242 /** 2243 * ixgbe_release_nvm - Generic request for releasing the NVM ownership 2244 * @hw: pointer to the HW structure 2245 * 2246 * Release NVM ownership. 2247 */ 2248 void ixgbe_release_nvm(struct ixgbe_hw *hw) 2249 { 2250 u32 fla; 2251 2252 /* Skip if we are in blank NVM programming mode */ 2253 fla = IXGBE_READ_REG(hw, IXGBE_GLNVM_FLA); 2254 if ((fla & IXGBE_GLNVM_FLA_LOCKED_M) == 0) 2255 return; 2256 2257 ixgbe_release_res(hw, IXGBE_NVM_RES_ID); 2258 } 2259 2260 /** 2261 * ixgbe_aci_read_nvm - read NVM 2262 * @hw: pointer to the HW struct 2263 * @module_typeid: module pointer location in words from the NVM beginning 2264 * @offset: byte offset from the module beginning 2265 * @length: length of the section to be read (in bytes from the offset) 2266 * @data: command buffer (size [bytes] = length) 2267 * @last_command: tells if this is the last command in a series 2268 * @read_shadow_ram: tell if this is a shadow RAM read 2269 * 2270 * Read the NVM using ACI command (0x0701). 2271 * 2272 * Return: the exit code of the operation. 2273 */ 2274 int ixgbe_aci_read_nvm(struct ixgbe_hw *hw, u16 module_typeid, u32 offset, 2275 u16 length, void *data, bool last_command, 2276 bool read_shadow_ram) 2277 { 2278 struct ixgbe_aci_cmd_nvm *cmd; 2279 struct ixgbe_aci_desc desc; 2280 2281 if (offset > IXGBE_ACI_NVM_MAX_OFFSET) 2282 return -EINVAL; 2283 2284 cmd = &desc.params.nvm; 2285 2286 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_read); 2287 2288 if (!read_shadow_ram && module_typeid == IXGBE_ACI_NVM_START_POINT) 2289 cmd->cmd_flags |= IXGBE_ACI_NVM_FLASH_ONLY; 2290 2291 /* If this is the last command in a series, set the proper flag. */ 2292 if (last_command) 2293 cmd->cmd_flags |= IXGBE_ACI_NVM_LAST_CMD; 2294 cmd->module_typeid = cpu_to_le16(module_typeid); 2295 cmd->offset_low = cpu_to_le16(offset & 0xFFFF); 2296 cmd->offset_high = (offset >> 16) & 0xFF; 2297 cmd->length = cpu_to_le16(length); 2298 2299 return ixgbe_aci_send_cmd(hw, &desc, data, length); 2300 } 2301 2302 /** 2303 * ixgbe_aci_erase_nvm - erase NVM sector 2304 * @hw: pointer to the HW struct 2305 * @module_typeid: module pointer location in words from the NVM beginning 2306 * 2307 * Erase the NVM sector using the ACI command (0x0702). 2308 * 2309 * Return: the exit code of the operation. 2310 */ 2311 int ixgbe_aci_erase_nvm(struct ixgbe_hw *hw, u16 module_typeid) 2312 { 2313 struct ixgbe_aci_cmd_nvm *cmd; 2314 struct ixgbe_aci_desc desc; 2315 __le16 len; 2316 int err; 2317 2318 /* Read a length value from SR, so module_typeid is equal to 0, 2319 * calculate offset where module size is placed from bytes to words 2320 * set last command and read from SR values to true. 2321 */ 2322 err = ixgbe_aci_read_nvm(hw, 0, 2 * module_typeid + 2, 2, &len, true, 2323 true); 2324 if (err) 2325 return err; 2326 2327 cmd = &desc.params.nvm; 2328 2329 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_erase); 2330 2331 cmd->module_typeid = cpu_to_le16(module_typeid); 2332 cmd->length = len; 2333 cmd->offset_low = 0; 2334 cmd->offset_high = 0; 2335 2336 return ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 2337 } 2338 2339 /** 2340 * ixgbe_aci_update_nvm - update NVM 2341 * @hw: pointer to the HW struct 2342 * @module_typeid: module pointer location in words from the NVM beginning 2343 * @offset: byte offset from the module beginning 2344 * @length: length of the section to be written (in bytes from the offset) 2345 * @data: command buffer (size [bytes] = length) 2346 * @last_command: tells if this is the last command in a series 2347 * @command_flags: command parameters 2348 * 2349 * Update the NVM using the ACI command (0x0703). 2350 * 2351 * Return: the exit code of the operation. 2352 */ 2353 int ixgbe_aci_update_nvm(struct ixgbe_hw *hw, u16 module_typeid, 2354 u32 offset, u16 length, void *data, 2355 bool last_command, u8 command_flags) 2356 { 2357 struct ixgbe_aci_cmd_nvm *cmd; 2358 struct ixgbe_aci_desc desc; 2359 2360 cmd = &desc.params.nvm; 2361 2362 /* In offset the highest byte must be zeroed. */ 2363 if (offset & 0xFF000000) 2364 return -EINVAL; 2365 2366 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_write); 2367 2368 cmd->cmd_flags |= command_flags; 2369 2370 /* If this is the last command in a series, set the proper flag. */ 2371 if (last_command) 2372 cmd->cmd_flags |= IXGBE_ACI_NVM_LAST_CMD; 2373 cmd->module_typeid = cpu_to_le16(module_typeid); 2374 cmd->offset_low = cpu_to_le16(offset & 0xFFFF); 2375 cmd->offset_high = FIELD_GET(IXGBE_ACI_NVM_OFFSET_HI_U_MASK, offset); 2376 cmd->length = cpu_to_le16(length); 2377 2378 desc.flags |= cpu_to_le16(IXGBE_ACI_FLAG_RD); 2379 2380 return ixgbe_aci_send_cmd(hw, &desc, data, length); 2381 } 2382 2383 /** 2384 * ixgbe_nvm_write_activate - NVM activate write 2385 * @hw: pointer to the HW struct 2386 * @cmd_flags: flags for write activate command 2387 * @response_flags: response indicators from firmware 2388 * 2389 * Update the control word with the required banks' validity bits 2390 * and dumps the Shadow RAM to flash using ACI command (0x0707). 2391 * 2392 * cmd_flags controls which banks to activate, the preservation level to use 2393 * when activating the NVM bank, and whether an EMP reset is required for 2394 * activation. 2395 * 2396 * Note that the 16bit cmd_flags value is split between two separate 1 byte 2397 * flag values in the descriptor. 2398 * 2399 * On successful return of the firmware command, the response_flags variable 2400 * is updated with the flags reported by firmware indicating certain status, 2401 * such as whether EMP reset is enabled. 2402 * 2403 * Return: the exit code of the operation. 2404 */ 2405 int ixgbe_nvm_write_activate(struct ixgbe_hw *hw, u16 cmd_flags, 2406 u8 *response_flags) 2407 { 2408 struct ixgbe_aci_cmd_nvm *cmd; 2409 struct ixgbe_aci_desc desc; 2410 s32 err; 2411 2412 cmd = &desc.params.nvm; 2413 ixgbe_fill_dflt_direct_cmd_desc(&desc, 2414 ixgbe_aci_opc_nvm_write_activate); 2415 2416 cmd->cmd_flags = (u8)(cmd_flags & 0xFF); 2417 cmd->offset_high = (u8)FIELD_GET(IXGBE_ACI_NVM_OFFSET_HI_A_MASK, 2418 cmd_flags); 2419 2420 err = ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 2421 if (!err && response_flags) 2422 *response_flags = cmd->cmd_flags; 2423 2424 return err; 2425 } 2426 2427 /** 2428 * ixgbe_nvm_validate_checksum - validate checksum 2429 * @hw: pointer to the HW struct 2430 * 2431 * Verify NVM PFA checksum validity using ACI command (0x0706). 2432 * If the checksum verification failed, IXGBE_ERR_NVM_CHECKSUM is returned. 2433 * The function acquires and then releases the NVM ownership. 2434 * 2435 * Return: the exit code of the operation. 2436 */ 2437 int ixgbe_nvm_validate_checksum(struct ixgbe_hw *hw) 2438 { 2439 struct ixgbe_aci_cmd_nvm_checksum *cmd; 2440 struct ixgbe_aci_desc desc; 2441 int err; 2442 2443 err = ixgbe_acquire_nvm(hw, IXGBE_RES_READ); 2444 if (err) 2445 return err; 2446 2447 cmd = &desc.params.nvm_checksum; 2448 2449 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_checksum); 2450 cmd->flags = IXGBE_ACI_NVM_CHECKSUM_VERIFY; 2451 2452 err = ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 2453 2454 ixgbe_release_nvm(hw); 2455 2456 if (!err && cmd->checksum != 2457 cpu_to_le16(IXGBE_ACI_NVM_CHECKSUM_CORRECT)) { 2458 struct ixgbe_adapter *adapter = container_of(hw, struct ixgbe_adapter, 2459 hw); 2460 2461 err = -EIO; 2462 netdev_err(adapter->netdev, "Invalid Shadow Ram checksum"); 2463 } 2464 2465 return err; 2466 } 2467 2468 /** 2469 * ixgbe_discover_flash_size - Discover the available flash size 2470 * @hw: pointer to the HW struct 2471 * 2472 * The device flash could be up to 16MB in size. However, it is possible that 2473 * the actual size is smaller. Use bisection to determine the accessible size 2474 * of flash memory. 2475 * 2476 * Return: the exit code of the operation. 2477 */ 2478 static int ixgbe_discover_flash_size(struct ixgbe_hw *hw) 2479 { 2480 u32 min_size = 0, max_size = IXGBE_ACI_NVM_MAX_OFFSET + 1; 2481 int err; 2482 2483 err = ixgbe_acquire_nvm(hw, IXGBE_RES_READ); 2484 if (err) 2485 return err; 2486 2487 while ((max_size - min_size) > 1) { 2488 u32 offset = (max_size + min_size) / 2; 2489 u32 len = 1; 2490 u8 data; 2491 2492 err = ixgbe_read_flat_nvm(hw, offset, &len, &data, false); 2493 if (err == -EIO && 2494 hw->aci.last_status == IXGBE_ACI_RC_EINVAL) { 2495 err = 0; 2496 max_size = offset; 2497 } else if (!err) { 2498 min_size = offset; 2499 } else { 2500 /* an unexpected error occurred */ 2501 goto err_read_flat_nvm; 2502 } 2503 } 2504 2505 hw->flash.flash_size = max_size; 2506 2507 err_read_flat_nvm: 2508 ixgbe_release_nvm(hw); 2509 2510 return err; 2511 } 2512 2513 /** 2514 * ixgbe_read_sr_base_address - Read the value of a Shadow RAM pointer word 2515 * @hw: pointer to the HW structure 2516 * @offset: the word offset of the Shadow RAM word to read 2517 * @pointer: pointer value read from Shadow RAM 2518 * 2519 * Read the given Shadow RAM word, and convert it to a pointer value specified 2520 * in bytes. This function assumes the specified offset is a valid pointer 2521 * word. 2522 * 2523 * Each pointer word specifies whether it is stored in word size or 4KB 2524 * sector size by using the highest bit. The reported pointer value will be in 2525 * bytes, intended for flat NVM reads. 2526 * 2527 * Return: the exit code of the operation. 2528 */ 2529 static int ixgbe_read_sr_base_address(struct ixgbe_hw *hw, u16 offset, 2530 u32 *pointer) 2531 { 2532 u16 value; 2533 int err; 2534 2535 err = ixgbe_read_ee_aci_e610(hw, offset, &value); 2536 if (err) 2537 return err; 2538 2539 /* Determine if the pointer is in 4KB or word units */ 2540 if (value & IXGBE_SR_NVM_PTR_4KB_UNITS) 2541 *pointer = (value & ~IXGBE_SR_NVM_PTR_4KB_UNITS) * SZ_4K; 2542 else 2543 *pointer = value * sizeof(u16); 2544 2545 return 0; 2546 } 2547 2548 /** 2549 * ixgbe_read_sr_area_size - Read an area size from a Shadow RAM word 2550 * @hw: pointer to the HW structure 2551 * @offset: the word offset of the Shadow RAM to read 2552 * @size: size value read from the Shadow RAM 2553 * 2554 * Read the given Shadow RAM word, and convert it to an area size value 2555 * specified in bytes. This function assumes the specified offset is a valid 2556 * area size word. 2557 * 2558 * Each area size word is specified in 4KB sector units. This function reports 2559 * the size in bytes, intended for flat NVM reads. 2560 * 2561 * Return: the exit code of the operation. 2562 */ 2563 static int ixgbe_read_sr_area_size(struct ixgbe_hw *hw, u16 offset, u32 *size) 2564 { 2565 u16 value; 2566 int err; 2567 2568 err = ixgbe_read_ee_aci_e610(hw, offset, &value); 2569 if (err) 2570 return err; 2571 2572 /* Area sizes are always specified in 4KB units */ 2573 *size = value * SZ_4K; 2574 2575 return 0; 2576 } 2577 2578 /** 2579 * ixgbe_determine_active_flash_banks - Discover active bank for each module 2580 * @hw: pointer to the HW struct 2581 * 2582 * Read the Shadow RAM control word and determine which banks are active for 2583 * the NVM, OROM, and Netlist modules. Also read and calculate the associated 2584 * pointer and size. These values are then cached into the ixgbe_flash_info 2585 * structure for later use in order to calculate the correct offset to read 2586 * from the active module. 2587 * 2588 * Return: the exit code of the operation. 2589 */ 2590 static int ixgbe_determine_active_flash_banks(struct ixgbe_hw *hw) 2591 { 2592 struct ixgbe_bank_info *banks = &hw->flash.banks; 2593 u16 ctrl_word; 2594 int err; 2595 2596 err = ixgbe_read_ee_aci_e610(hw, IXGBE_E610_SR_NVM_CTRL_WORD, 2597 &ctrl_word); 2598 if (err) 2599 return err; 2600 2601 if (FIELD_GET(IXGBE_SR_CTRL_WORD_1_M, ctrl_word) != 2602 IXGBE_SR_CTRL_WORD_VALID) 2603 return -ENODATA; 2604 2605 if (!(ctrl_word & IXGBE_SR_CTRL_WORD_NVM_BANK)) 2606 banks->nvm_bank = IXGBE_1ST_FLASH_BANK; 2607 else 2608 banks->nvm_bank = IXGBE_2ND_FLASH_BANK; 2609 2610 if (!(ctrl_word & IXGBE_SR_CTRL_WORD_OROM_BANK)) 2611 banks->orom_bank = IXGBE_1ST_FLASH_BANK; 2612 else 2613 banks->orom_bank = IXGBE_2ND_FLASH_BANK; 2614 2615 if (!(ctrl_word & IXGBE_SR_CTRL_WORD_NETLIST_BANK)) 2616 banks->netlist_bank = IXGBE_1ST_FLASH_BANK; 2617 else 2618 banks->netlist_bank = IXGBE_2ND_FLASH_BANK; 2619 2620 err = ixgbe_read_sr_base_address(hw, IXGBE_E610_SR_1ST_NVM_BANK_PTR, 2621 &banks->nvm_ptr); 2622 if (err) 2623 return err; 2624 2625 err = ixgbe_read_sr_area_size(hw, IXGBE_E610_SR_NVM_BANK_SIZE, 2626 &banks->nvm_size); 2627 if (err) 2628 return err; 2629 2630 err = ixgbe_read_sr_base_address(hw, IXGBE_E610_SR_1ST_OROM_BANK_PTR, 2631 &banks->orom_ptr); 2632 if (err) 2633 return err; 2634 2635 err = ixgbe_read_sr_area_size(hw, IXGBE_E610_SR_OROM_BANK_SIZE, 2636 &banks->orom_size); 2637 if (err) 2638 return err; 2639 2640 err = ixgbe_read_sr_base_address(hw, IXGBE_E610_SR_NETLIST_BANK_PTR, 2641 &banks->netlist_ptr); 2642 if (err) 2643 return err; 2644 2645 err = ixgbe_read_sr_area_size(hw, IXGBE_E610_SR_NETLIST_BANK_SIZE, 2646 &banks->netlist_size); 2647 2648 return err; 2649 } 2650 2651 /** 2652 * ixgbe_get_flash_bank_offset - Get offset into requested flash bank 2653 * @hw: pointer to the HW structure 2654 * @bank: whether to read from the active or inactive flash bank 2655 * @module: the module to read from 2656 * 2657 * Based on the module, lookup the module offset from the beginning of the 2658 * flash. 2659 * 2660 * Return: the flash offset. Note that a value of zero is invalid and must be 2661 * treated as an error. 2662 */ 2663 static int ixgbe_get_flash_bank_offset(struct ixgbe_hw *hw, 2664 enum ixgbe_bank_select bank, 2665 u16 module) 2666 { 2667 struct ixgbe_bank_info *banks = &hw->flash.banks; 2668 enum ixgbe_flash_bank active_bank; 2669 bool second_bank_active; 2670 u32 offset, size; 2671 2672 switch (module) { 2673 case IXGBE_E610_SR_1ST_NVM_BANK_PTR: 2674 offset = banks->nvm_ptr; 2675 size = banks->nvm_size; 2676 active_bank = banks->nvm_bank; 2677 break; 2678 case IXGBE_E610_SR_1ST_OROM_BANK_PTR: 2679 offset = banks->orom_ptr; 2680 size = banks->orom_size; 2681 active_bank = banks->orom_bank; 2682 break; 2683 case IXGBE_E610_SR_NETLIST_BANK_PTR: 2684 offset = banks->netlist_ptr; 2685 size = banks->netlist_size; 2686 active_bank = banks->netlist_bank; 2687 break; 2688 default: 2689 return 0; 2690 } 2691 2692 switch (active_bank) { 2693 case IXGBE_1ST_FLASH_BANK: 2694 second_bank_active = false; 2695 break; 2696 case IXGBE_2ND_FLASH_BANK: 2697 second_bank_active = true; 2698 break; 2699 default: 2700 return 0; 2701 } 2702 2703 /* The second flash bank is stored immediately following the first 2704 * bank. Based on whether the 1st or 2nd bank is active, and whether 2705 * we want the active or inactive bank, calculate the desired offset. 2706 */ 2707 switch (bank) { 2708 case IXGBE_ACTIVE_FLASH_BANK: 2709 return offset + (second_bank_active ? size : 0); 2710 case IXGBE_INACTIVE_FLASH_BANK: 2711 return offset + (second_bank_active ? 0 : size); 2712 } 2713 2714 return 0; 2715 } 2716 2717 /** 2718 * ixgbe_read_flash_module - Read a word from one of the main NVM modules 2719 * @hw: pointer to the HW structure 2720 * @bank: which bank of the module to read 2721 * @module: the module to read 2722 * @offset: the offset into the module in bytes 2723 * @data: storage for the word read from the flash 2724 * @length: bytes of data to read 2725 * 2726 * Read data from the specified flash module. The bank parameter indicates 2727 * whether or not to read from the active bank or the inactive bank of that 2728 * module. 2729 * 2730 * The word will be read using flat NVM access, and relies on the 2731 * hw->flash.banks data being setup by ixgbe_determine_active_flash_banks() 2732 * during initialization. 2733 * 2734 * Return: the exit code of the operation. 2735 */ 2736 static int ixgbe_read_flash_module(struct ixgbe_hw *hw, 2737 enum ixgbe_bank_select bank, 2738 u16 module, u32 offset, u8 *data, u32 length) 2739 { 2740 u32 start; 2741 int err; 2742 2743 start = ixgbe_get_flash_bank_offset(hw, bank, module); 2744 if (!start) 2745 return -EINVAL; 2746 2747 err = ixgbe_acquire_nvm(hw, IXGBE_RES_READ); 2748 if (err) 2749 return err; 2750 2751 err = ixgbe_read_flat_nvm(hw, start + offset, &length, data, false); 2752 2753 ixgbe_release_nvm(hw); 2754 2755 return err; 2756 } 2757 2758 /** 2759 * ixgbe_read_nvm_module - Read from the active main NVM module 2760 * @hw: pointer to the HW structure 2761 * @bank: whether to read from active or inactive NVM module 2762 * @offset: offset into the NVM module to read, in words 2763 * @data: storage for returned word value 2764 * 2765 * Read the specified word from the active NVM module. This includes the CSS 2766 * header at the start of the NVM module. 2767 * 2768 * Return: the exit code of the operation. 2769 */ 2770 static int ixgbe_read_nvm_module(struct ixgbe_hw *hw, 2771 enum ixgbe_bank_select bank, 2772 u32 offset, u16 *data) 2773 { 2774 __le16 data_local; 2775 int err; 2776 2777 err = ixgbe_read_flash_module(hw, bank, IXGBE_E610_SR_1ST_NVM_BANK_PTR, 2778 offset * sizeof(data_local), 2779 (u8 *)&data_local, 2780 sizeof(data_local)); 2781 if (!err) 2782 *data = le16_to_cpu(data_local); 2783 2784 return err; 2785 } 2786 2787 /** 2788 * ixgbe_read_netlist_module - Read data from the netlist module area 2789 * @hw: pointer to the HW structure 2790 * @bank: whether to read from the active or inactive module 2791 * @offset: offset into the netlist to read from 2792 * @data: storage for returned word value 2793 * 2794 * Read a word from the specified netlist bank. 2795 * 2796 * Return: the exit code of the operation. 2797 */ 2798 static int ixgbe_read_netlist_module(struct ixgbe_hw *hw, 2799 enum ixgbe_bank_select bank, 2800 u32 offset, u16 *data) 2801 { 2802 __le16 data_local; 2803 int err; 2804 2805 err = ixgbe_read_flash_module(hw, bank, IXGBE_E610_SR_NETLIST_BANK_PTR, 2806 offset * sizeof(data_local), 2807 (u8 *)&data_local, sizeof(data_local)); 2808 if (!err) 2809 *data = le16_to_cpu(data_local); 2810 2811 return err; 2812 } 2813 2814 /** 2815 * ixgbe_read_orom_module - Read from the active Option ROM module 2816 * @hw: pointer to the HW structure 2817 * @bank: whether to read from active or inactive OROM module 2818 * @offset: offset into the OROM module to read, in words 2819 * @data: storage for returned word value 2820 * 2821 * Read the specified word from the active Option ROM module of the flash. 2822 * Note that unlike the NVM module, the CSS data is stored at the end of the 2823 * module instead of at the beginning. 2824 * 2825 * Return: the exit code of the operation. 2826 */ 2827 static int ixgbe_read_orom_module(struct ixgbe_hw *hw, 2828 enum ixgbe_bank_select bank, 2829 u32 offset, u16 *data) 2830 { 2831 __le16 data_local; 2832 int err; 2833 2834 err = ixgbe_read_flash_module(hw, bank, IXGBE_E610_SR_1ST_OROM_BANK_PTR, 2835 offset * sizeof(data_local), 2836 (u8 *)&data_local, sizeof(data_local)); 2837 if (!err) 2838 *data = le16_to_cpu(data_local); 2839 2840 return err; 2841 } 2842 2843 /** 2844 * ixgbe_get_nvm_css_hdr_len - Read the CSS header length 2845 * @hw: pointer to the HW struct 2846 * @bank: whether to read from the active or inactive flash bank 2847 * @hdr_len: storage for header length in words 2848 * 2849 * Read the CSS header length from the NVM CSS header and add the 2850 * Authentication header size, and then convert to words. 2851 * 2852 * Return: the exit code of the operation. 2853 */ 2854 static int ixgbe_get_nvm_css_hdr_len(struct ixgbe_hw *hw, 2855 enum ixgbe_bank_select bank, 2856 u32 *hdr_len) 2857 { 2858 u16 hdr_len_l, hdr_len_h; 2859 u32 hdr_len_dword; 2860 int err; 2861 2862 err = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_HDR_LEN_L, 2863 &hdr_len_l); 2864 if (err) 2865 return err; 2866 2867 err = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_HDR_LEN_H, 2868 &hdr_len_h); 2869 if (err) 2870 return err; 2871 2872 /* CSS header length is in DWORD, so convert to words and add 2873 * authentication header size. 2874 */ 2875 hdr_len_dword = (hdr_len_h << 16) | hdr_len_l; 2876 *hdr_len = hdr_len_dword * 2 + IXGBE_NVM_AUTH_HEADER_LEN; 2877 2878 return 0; 2879 } 2880 2881 /** 2882 * ixgbe_read_nvm_sr_copy - Read a word from the Shadow RAM copy 2883 * @hw: pointer to the HW structure 2884 * @bank: whether to read from the active or inactive NVM module 2885 * @offset: offset into the Shadow RAM copy to read, in words 2886 * @data: storage for returned word value 2887 * 2888 * Read the specified word from the copy of the Shadow RAM found in the 2889 * specified NVM module. 2890 * 2891 * Return: the exit code of the operation. 2892 */ 2893 static int ixgbe_read_nvm_sr_copy(struct ixgbe_hw *hw, 2894 enum ixgbe_bank_select bank, 2895 u32 offset, u16 *data) 2896 { 2897 u32 hdr_len; 2898 int err; 2899 2900 err = ixgbe_get_nvm_css_hdr_len(hw, bank, &hdr_len); 2901 if (err) 2902 return err; 2903 2904 hdr_len = round_up(hdr_len, IXGBE_HDR_LEN_ROUNDUP); 2905 2906 return ixgbe_read_nvm_module(hw, bank, hdr_len + offset, data); 2907 } 2908 2909 /** 2910 * ixgbe_get_nvm_srev - Read the security revision from the NVM CSS header 2911 * @hw: pointer to the HW struct 2912 * @bank: whether to read from the active or inactive flash bank 2913 * @srev: storage for security revision 2914 * 2915 * Read the security revision out of the CSS header of the active NVM module 2916 * bank. 2917 * 2918 * Return: the exit code of the operation. 2919 */ 2920 static int ixgbe_get_nvm_srev(struct ixgbe_hw *hw, 2921 enum ixgbe_bank_select bank, u32 *srev) 2922 { 2923 u16 srev_l, srev_h; 2924 int err; 2925 2926 err = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_SREV_L, &srev_l); 2927 if (err) 2928 return err; 2929 2930 err = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_SREV_H, &srev_h); 2931 if (err) 2932 return err; 2933 2934 *srev = (srev_h << 16) | srev_l; 2935 2936 return 0; 2937 } 2938 2939 /** 2940 * ixgbe_get_orom_civd_data - Get the combo version information from Option ROM 2941 * @hw: pointer to the HW struct 2942 * @bank: whether to read from the active or inactive flash module 2943 * @civd: storage for the Option ROM CIVD data. 2944 * 2945 * Searches through the Option ROM flash contents to locate the CIVD data for 2946 * the image. 2947 * 2948 * Return: the exit code of the operation. 2949 */ 2950 static int 2951 ixgbe_get_orom_civd_data(struct ixgbe_hw *hw, enum ixgbe_bank_select bank, 2952 struct ixgbe_orom_civd_info *civd) 2953 { 2954 struct ixgbe_orom_civd_info tmp; 2955 u32 offset; 2956 int err; 2957 2958 /* The CIVD section is located in the Option ROM aligned to 512 bytes. 2959 * The first 4 bytes must contain the ASCII characters "$CIV". 2960 * A simple modulo 256 sum of all of the bytes of the structure must 2961 * equal 0. 2962 */ 2963 for (offset = 0; (offset + SZ_512) <= hw->flash.banks.orom_size; 2964 offset += SZ_512) { 2965 u8 sum = 0; 2966 u32 i; 2967 2968 err = ixgbe_read_flash_module(hw, bank, 2969 IXGBE_E610_SR_1ST_OROM_BANK_PTR, 2970 offset, 2971 (u8 *)&tmp, sizeof(tmp)); 2972 if (err) 2973 return err; 2974 2975 /* Skip forward until we find a matching signature */ 2976 if (memcmp(IXGBE_OROM_CIV_SIGNATURE, tmp.signature, 2977 sizeof(tmp.signature))) 2978 continue; 2979 2980 /* Verify that the simple checksum is zero */ 2981 for (i = 0; i < sizeof(tmp); i++) 2982 sum += ((u8 *)&tmp)[i]; 2983 2984 if (sum) 2985 return -EDOM; 2986 2987 *civd = tmp; 2988 return 0; 2989 } 2990 2991 return -ENODATA; 2992 } 2993 2994 /** 2995 * ixgbe_get_orom_srev - Read the security revision from the OROM CSS header 2996 * @hw: pointer to the HW struct 2997 * @bank: whether to read from active or inactive flash module 2998 * @srev: storage for security revision 2999 * 3000 * Read the security revision out of the CSS header of the active OROM module 3001 * bank. 3002 * 3003 * Return: the exit code of the operation. 3004 */ 3005 static int ixgbe_get_orom_srev(struct ixgbe_hw *hw, 3006 enum ixgbe_bank_select bank, 3007 u32 *srev) 3008 { 3009 u32 orom_size_word = hw->flash.banks.orom_size / 2; 3010 u32 css_start, hdr_len; 3011 u16 srev_l, srev_h; 3012 int err; 3013 3014 err = ixgbe_get_nvm_css_hdr_len(hw, bank, &hdr_len); 3015 if (err) 3016 return err; 3017 3018 if (orom_size_word < hdr_len) 3019 return -EINVAL; 3020 3021 /* Calculate how far into the Option ROM the CSS header starts. Note 3022 * that ixgbe_read_orom_module takes a word offset. 3023 */ 3024 css_start = orom_size_word - hdr_len; 3025 err = ixgbe_read_orom_module(hw, bank, 3026 css_start + IXGBE_NVM_CSS_SREV_L, 3027 &srev_l); 3028 if (err) 3029 return err; 3030 3031 err = ixgbe_read_orom_module(hw, bank, 3032 css_start + IXGBE_NVM_CSS_SREV_H, 3033 &srev_h); 3034 if (err) 3035 return err; 3036 3037 *srev = srev_h << 16 | srev_l; 3038 3039 return 0; 3040 } 3041 3042 /** 3043 * ixgbe_get_orom_ver_info - Read Option ROM version information 3044 * @hw: pointer to the HW struct 3045 * @bank: whether to read from the active or inactive flash module 3046 * @orom: pointer to Option ROM info structure 3047 * 3048 * Read Option ROM version and security revision from the Option ROM flash 3049 * section. 3050 * 3051 * Return: the exit code of the operation. 3052 */ 3053 static int ixgbe_get_orom_ver_info(struct ixgbe_hw *hw, 3054 enum ixgbe_bank_select bank, 3055 struct ixgbe_orom_info *orom) 3056 { 3057 struct ixgbe_orom_civd_info civd; 3058 u32 combo_ver; 3059 int err; 3060 3061 err = ixgbe_get_orom_civd_data(hw, bank, &civd); 3062 if (err) 3063 return err; 3064 3065 combo_ver = le32_to_cpu(civd.combo_ver); 3066 3067 orom->major = (u8)FIELD_GET(IXGBE_OROM_VER_MASK, combo_ver); 3068 orom->patch = (u8)FIELD_GET(IXGBE_OROM_VER_PATCH_MASK, combo_ver); 3069 orom->build = (u16)FIELD_GET(IXGBE_OROM_VER_BUILD_MASK, combo_ver); 3070 3071 return ixgbe_get_orom_srev(hw, bank, &orom->srev); 3072 } 3073 3074 /** 3075 * ixgbe_get_inactive_orom_ver - Read Option ROM version from the inactive bank 3076 * @hw: pointer to the HW structure 3077 * @orom: storage for Option ROM version information 3078 * 3079 * Read the Option ROM version and security revision data for the inactive 3080 * section of flash. Used to access version data for a pending update that has 3081 * not yet been activated. 3082 * 3083 * Return: the exit code of the operation. 3084 */ 3085 int ixgbe_get_inactive_orom_ver(struct ixgbe_hw *hw, 3086 struct ixgbe_orom_info *orom) 3087 { 3088 return ixgbe_get_orom_ver_info(hw, IXGBE_INACTIVE_FLASH_BANK, orom); 3089 } 3090 3091 /** 3092 * ixgbe_get_nvm_ver_info - Read NVM version information 3093 * @hw: pointer to the HW struct 3094 * @bank: whether to read from the active or inactive flash bank 3095 * @nvm: pointer to NVM info structure 3096 * 3097 * Read the NVM EETRACK ID and map version of the main NVM image bank, filling 3098 * in the nvm info structure. 3099 * 3100 * Return: the exit code of the operation. 3101 */ 3102 static int ixgbe_get_nvm_ver_info(struct ixgbe_hw *hw, 3103 enum ixgbe_bank_select bank, 3104 struct ixgbe_nvm_info *nvm) 3105 { 3106 u16 eetrack_lo, eetrack_hi, ver; 3107 int err; 3108 3109 err = ixgbe_read_nvm_sr_copy(hw, bank, 3110 IXGBE_E610_SR_NVM_DEV_STARTER_VER, &ver); 3111 if (err) 3112 return err; 3113 3114 nvm->major = FIELD_GET(IXGBE_E610_NVM_VER_HI_MASK, ver); 3115 nvm->minor = FIELD_GET(IXGBE_E610_NVM_VER_LO_MASK, ver); 3116 3117 err = ixgbe_read_nvm_sr_copy(hw, bank, IXGBE_E610_SR_NVM_EETRACK_LO, 3118 &eetrack_lo); 3119 if (err) 3120 return err; 3121 3122 err = ixgbe_read_nvm_sr_copy(hw, bank, IXGBE_E610_SR_NVM_EETRACK_HI, 3123 &eetrack_hi); 3124 if (err) 3125 return err; 3126 3127 nvm->eetrack = (eetrack_hi << 16) | eetrack_lo; 3128 3129 ixgbe_get_nvm_srev(hw, bank, &nvm->srev); 3130 3131 return 0; 3132 } 3133 3134 /** 3135 * ixgbe_get_inactive_nvm_ver - Read Option ROM version from the inactive bank 3136 * @hw: pointer to the HW structure 3137 * @nvm: storage for Option ROM version information 3138 * 3139 * Read the NVM EETRACK ID, Map version, and security revision of the 3140 * inactive NVM bank. Used to access version data for a pending update that 3141 * has not yet been activated. 3142 * 3143 * Return: the exit code of the operation. 3144 */ 3145 int ixgbe_get_inactive_nvm_ver(struct ixgbe_hw *hw, struct ixgbe_nvm_info *nvm) 3146 { 3147 return ixgbe_get_nvm_ver_info(hw, IXGBE_INACTIVE_FLASH_BANK, nvm); 3148 } 3149 3150 /** 3151 * ixgbe_get_netlist_info - Read the netlist version information 3152 * @hw: pointer to the HW struct 3153 * @bank: whether to read from the active or inactive flash bank 3154 * @netlist: pointer to netlist version info structure 3155 * 3156 * Get the netlist version information from the requested bank. Reads the Link 3157 * Topology section to find the Netlist ID block and extract the relevant 3158 * information into the netlist version structure. 3159 * 3160 * Return: the exit code of the operation. 3161 */ 3162 static int ixgbe_get_netlist_info(struct ixgbe_hw *hw, 3163 enum ixgbe_bank_select bank, 3164 struct ixgbe_netlist_info *netlist) 3165 { 3166 u16 module_id, length, node_count, i; 3167 u16 *id_blk; 3168 int err; 3169 3170 err = ixgbe_read_netlist_module(hw, bank, IXGBE_NETLIST_TYPE_OFFSET, 3171 &module_id); 3172 if (err) 3173 return err; 3174 3175 if (module_id != IXGBE_NETLIST_LINK_TOPO_MOD_ID) 3176 return -EIO; 3177 3178 err = ixgbe_read_netlist_module(hw, bank, IXGBE_LINK_TOPO_MODULE_LEN, 3179 &length); 3180 if (err) 3181 return err; 3182 3183 /* Sanity check that we have at least enough words to store the 3184 * netlist ID block. 3185 */ 3186 if (length < IXGBE_NETLIST_ID_BLK_SIZE) 3187 return -EIO; 3188 3189 err = ixgbe_read_netlist_module(hw, bank, IXGBE_LINK_TOPO_NODE_COUNT, 3190 &node_count); 3191 if (err) 3192 return err; 3193 3194 node_count &= IXGBE_LINK_TOPO_NODE_COUNT_M; 3195 3196 id_blk = kcalloc(IXGBE_NETLIST_ID_BLK_SIZE, sizeof(*id_blk), GFP_KERNEL); 3197 if (!id_blk) 3198 return -ENOMEM; 3199 3200 /* Read out the entire Netlist ID Block at once. */ 3201 err = ixgbe_read_flash_module(hw, bank, IXGBE_E610_SR_NETLIST_BANK_PTR, 3202 IXGBE_NETLIST_ID_BLK_OFFSET(node_count) * 3203 sizeof(*id_blk), (u8 *)id_blk, 3204 IXGBE_NETLIST_ID_BLK_SIZE * 3205 sizeof(*id_blk)); 3206 if (err) 3207 goto free_id_blk; 3208 3209 for (i = 0; i < IXGBE_NETLIST_ID_BLK_SIZE; i++) 3210 id_blk[i] = le16_to_cpu(((__le16 *)id_blk)[i]); 3211 3212 netlist->major = id_blk[IXGBE_NETLIST_ID_BLK_MAJOR_VER_HIGH] << 16 | 3213 id_blk[IXGBE_NETLIST_ID_BLK_MAJOR_VER_LOW]; 3214 netlist->minor = id_blk[IXGBE_NETLIST_ID_BLK_MINOR_VER_HIGH] << 16 | 3215 id_blk[IXGBE_NETLIST_ID_BLK_MINOR_VER_LOW]; 3216 netlist->type = id_blk[IXGBE_NETLIST_ID_BLK_TYPE_HIGH] << 16 | 3217 id_blk[IXGBE_NETLIST_ID_BLK_TYPE_LOW]; 3218 netlist->rev = id_blk[IXGBE_NETLIST_ID_BLK_REV_HIGH] << 16 | 3219 id_blk[IXGBE_NETLIST_ID_BLK_REV_LOW]; 3220 netlist->cust_ver = id_blk[IXGBE_NETLIST_ID_BLK_CUST_VER]; 3221 /* Read the left most 4 bytes of SHA */ 3222 netlist->hash = id_blk[IXGBE_NETLIST_ID_BLK_SHA_HASH_WORD(15)] << 16 | 3223 id_blk[IXGBE_NETLIST_ID_BLK_SHA_HASH_WORD(14)]; 3224 3225 free_id_blk: 3226 kfree(id_blk); 3227 return err; 3228 } 3229 3230 /** 3231 * ixgbe_get_inactive_netlist_ver - Read netlist version from the inactive bank 3232 * @hw: pointer to the HW struct 3233 * @netlist: pointer to netlist version info structure 3234 * 3235 * Read the netlist version data from the inactive netlist bank. Used to 3236 * extract version data of a pending flash update in order to display the 3237 * version data. 3238 * 3239 * Return: the exit code of the operation. 3240 */ 3241 int ixgbe_get_inactive_netlist_ver(struct ixgbe_hw *hw, 3242 struct ixgbe_netlist_info *netlist) 3243 { 3244 return ixgbe_get_netlist_info(hw, IXGBE_INACTIVE_FLASH_BANK, netlist); 3245 } 3246 3247 /** 3248 * ixgbe_get_flash_data - get flash data 3249 * @hw: pointer to the HW struct 3250 * 3251 * Read and populate flash data such as Shadow RAM size, 3252 * max_timeout and blank_nvm_mode 3253 * 3254 * Return: the exit code of the operation. 3255 */ 3256 int ixgbe_get_flash_data(struct ixgbe_hw *hw) 3257 { 3258 struct ixgbe_flash_info *flash = &hw->flash; 3259 u32 fla, gens_stat; 3260 u8 sr_size; 3261 int err; 3262 3263 /* The SR size is stored regardless of the NVM programming mode 3264 * as the blank mode may be used in the factory line. 3265 */ 3266 gens_stat = IXGBE_READ_REG(hw, GLNVM_GENS); 3267 sr_size = FIELD_GET(GLNVM_GENS_SR_SIZE_M, gens_stat); 3268 3269 /* Switching to words (sr_size contains power of 2) */ 3270 flash->sr_words = BIT(sr_size) * (SZ_1K / sizeof(u16)); 3271 3272 /* Check if we are in the normal or blank NVM programming mode */ 3273 fla = IXGBE_READ_REG(hw, IXGBE_GLNVM_FLA); 3274 if (fla & IXGBE_GLNVM_FLA_LOCKED_M) { 3275 flash->blank_nvm_mode = false; 3276 } else { 3277 flash->blank_nvm_mode = true; 3278 return -EIO; 3279 } 3280 3281 err = ixgbe_discover_flash_size(hw); 3282 if (err) 3283 return err; 3284 3285 err = ixgbe_determine_active_flash_banks(hw); 3286 if (err) 3287 return err; 3288 3289 err = ixgbe_get_nvm_ver_info(hw, IXGBE_ACTIVE_FLASH_BANK, 3290 &flash->nvm); 3291 if (err) 3292 return err; 3293 3294 err = ixgbe_get_orom_ver_info(hw, IXGBE_ACTIVE_FLASH_BANK, 3295 &flash->orom); 3296 if (err) 3297 return err; 3298 3299 err = ixgbe_get_netlist_info(hw, IXGBE_ACTIVE_FLASH_BANK, 3300 &flash->netlist); 3301 return err; 3302 } 3303 3304 /** 3305 * ixgbe_aci_nvm_update_empr - update NVM using EMPR 3306 * @hw: pointer to the HW struct 3307 * 3308 * Force EMP reset using ACI command (0x0709). This command allows SW to 3309 * request an EMPR to activate new FW. 3310 * 3311 * Return: the exit code of the operation. 3312 */ 3313 int ixgbe_aci_nvm_update_empr(struct ixgbe_hw *hw) 3314 { 3315 struct ixgbe_aci_desc desc; 3316 3317 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_update_empr); 3318 3319 return ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 3320 } 3321 3322 /* ixgbe_nvm_set_pkg_data - NVM set package data 3323 * @hw: pointer to the HW struct 3324 * @del_pkg_data_flag: If is set then the current pkg_data store by FW 3325 * is deleted. 3326 * If bit is set to 1, then buffer should be size 0. 3327 * @data: pointer to buffer 3328 * @length: length of the buffer 3329 * 3330 * Set package data using ACI command (0x070A). 3331 * This command is equivalent to the reception of 3332 * a PLDM FW Update GetPackageData cmd. This command should be sent 3333 * as part of the NVM update as the first cmd in the flow. 3334 * 3335 * Return: the exit code of the operation. 3336 */ 3337 int ixgbe_nvm_set_pkg_data(struct ixgbe_hw *hw, bool del_pkg_data_flag, 3338 u8 *data, u16 length) 3339 { 3340 struct ixgbe_aci_cmd_nvm_pkg_data *cmd; 3341 struct ixgbe_aci_desc desc; 3342 3343 if (length != 0 && !data) 3344 return -EINVAL; 3345 3346 cmd = &desc.params.pkg_data; 3347 3348 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_pkg_data); 3349 desc.flags |= cpu_to_le16(IXGBE_ACI_FLAG_RD); 3350 3351 if (del_pkg_data_flag) 3352 cmd->cmd_flags |= IXGBE_ACI_NVM_PKG_DELETE; 3353 3354 return ixgbe_aci_send_cmd(hw, &desc, data, length); 3355 } 3356 3357 /* ixgbe_nvm_pass_component_tbl - NVM pass component table 3358 * @hw: pointer to the HW struct 3359 * @data: pointer to buffer 3360 * @length: length of the buffer 3361 * @transfer_flag: parameter for determining stage of the update 3362 * @comp_response: a pointer to the response from the 0x070B ACI. 3363 * @comp_response_code: a pointer to the response code from the 0x070B ACI. 3364 * 3365 * Pass component table using ACI command (0x070B). This command is equivalent 3366 * to the reception of a PLDM FW Update PassComponentTable cmd. 3367 * This command should be sent once per component. It can be only sent after 3368 * Set Package Data cmd and before actual update. FW will assume these 3369 * commands are going to be sent until the TransferFlag is set to End or 3370 * StartAndEnd. 3371 * 3372 * Return: the exit code of the operation. 3373 */ 3374 int ixgbe_nvm_pass_component_tbl(struct ixgbe_hw *hw, u8 *data, u16 length, 3375 u8 transfer_flag, u8 *comp_response, 3376 u8 *comp_response_code) 3377 { 3378 struct ixgbe_aci_cmd_nvm_pass_comp_tbl *cmd; 3379 struct ixgbe_aci_desc desc; 3380 int err; 3381 3382 if (!data || !comp_response || !comp_response_code) 3383 return -EINVAL; 3384 3385 cmd = &desc.params.pass_comp_tbl; 3386 3387 ixgbe_fill_dflt_direct_cmd_desc(&desc, 3388 ixgbe_aci_opc_nvm_pass_component_tbl); 3389 desc.flags |= cpu_to_le16(IXGBE_ACI_FLAG_RD); 3390 3391 cmd->transfer_flag = transfer_flag; 3392 err = ixgbe_aci_send_cmd(hw, &desc, data, length); 3393 if (!err) { 3394 *comp_response = cmd->component_response; 3395 *comp_response_code = cmd->component_response_code; 3396 } 3397 3398 return err; 3399 } 3400 3401 /** 3402 * ixgbe_read_sr_word_aci - Reads Shadow RAM via ACI 3403 * @hw: pointer to the HW structure 3404 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 3405 * @data: word read from the Shadow RAM 3406 * 3407 * Reads one 16 bit word from the Shadow RAM using ixgbe_read_flat_nvm. 3408 * 3409 * Return: the exit code of the operation. 3410 */ 3411 int ixgbe_read_sr_word_aci(struct ixgbe_hw *hw, u16 offset, u16 *data) 3412 { 3413 u32 bytes = sizeof(u16); 3414 u16 data_local; 3415 int err; 3416 3417 err = ixgbe_read_flat_nvm(hw, offset * sizeof(u16), &bytes, 3418 (u8 *)&data_local, true); 3419 if (err) 3420 return err; 3421 3422 *data = data_local; 3423 return 0; 3424 } 3425 3426 /** 3427 * ixgbe_read_flat_nvm - Read portion of NVM by flat offset 3428 * @hw: pointer to the HW struct 3429 * @offset: offset from beginning of NVM 3430 * @length: (in) number of bytes to read; (out) number of bytes actually read 3431 * @data: buffer to return data in (sized to fit the specified length) 3432 * @read_shadow_ram: if true, read from shadow RAM instead of NVM 3433 * 3434 * Reads a portion of the NVM, as a flat memory space. This function correctly 3435 * breaks read requests across Shadow RAM sectors, prevents Shadow RAM size 3436 * from being exceeded in case of Shadow RAM read requests and ensures that no 3437 * single read request exceeds the maximum 4KB read for a single admin command. 3438 * 3439 * Returns an error code on failure. Note that the data pointer may be 3440 * partially updated if some reads succeed before a failure. 3441 * 3442 * Return: the exit code of the operation. 3443 */ 3444 int ixgbe_read_flat_nvm(struct ixgbe_hw *hw, u32 offset, u32 *length, 3445 u8 *data, bool read_shadow_ram) 3446 { 3447 u32 inlen = *length; 3448 u32 bytes_read = 0; 3449 bool last_cmd; 3450 int err; 3451 3452 /* Verify the length of the read if this is for the Shadow RAM */ 3453 if (read_shadow_ram && ((offset + inlen) > 3454 (hw->eeprom.word_size * 2u))) 3455 return -EINVAL; 3456 3457 do { 3458 u32 read_size, sector_offset; 3459 3460 /* ixgbe_aci_read_nvm cannot read more than 4KB at a time. 3461 * Additionally, a read from the Shadow RAM may not cross over 3462 * a sector boundary. Conveniently, the sector size is also 4KB. 3463 */ 3464 sector_offset = offset % IXGBE_ACI_MAX_BUFFER_SIZE; 3465 read_size = min_t(u32, 3466 IXGBE_ACI_MAX_BUFFER_SIZE - sector_offset, 3467 inlen - bytes_read); 3468 3469 last_cmd = !(bytes_read + read_size < inlen); 3470 3471 /* ixgbe_aci_read_nvm takes the length as a u16. Our read_size 3472 * is calculated using a u32, but the IXGBE_ACI_MAX_BUFFER_SIZE 3473 * maximum size guarantees that it will fit within the 2 bytes. 3474 */ 3475 err = ixgbe_aci_read_nvm(hw, IXGBE_ACI_NVM_START_POINT, 3476 offset, (u16)read_size, 3477 data + bytes_read, last_cmd, 3478 read_shadow_ram); 3479 if (err) 3480 break; 3481 3482 bytes_read += read_size; 3483 offset += read_size; 3484 } while (!last_cmd); 3485 3486 *length = bytes_read; 3487 return err; 3488 } 3489 3490 /** 3491 * ixgbe_read_sr_buf_aci - Read Shadow RAM buffer via ACI 3492 * @hw: pointer to the HW structure 3493 * @offset: offset of the Shadow RAM words to read (0x000000 - 0x001FFF) 3494 * @words: (in) number of words to read; (out) number of words actually read 3495 * @data: words read from the Shadow RAM 3496 * 3497 * Read 16 bit words (data buf) from the Shadow RAM. Acquire/release the NVM 3498 * ownership. 3499 * 3500 * Return: the operation exit code. 3501 */ 3502 int ixgbe_read_sr_buf_aci(struct ixgbe_hw *hw, u16 offset, u16 *words, 3503 u16 *data) 3504 { 3505 u32 bytes = *words * 2; 3506 int err; 3507 3508 err = ixgbe_read_flat_nvm(hw, offset * 2, &bytes, (u8 *)data, true); 3509 if (err) 3510 return err; 3511 3512 *words = bytes / 2; 3513 3514 for (int i = 0; i < *words; i++) 3515 data[i] = le16_to_cpu(((__le16 *)data)[i]); 3516 3517 return 0; 3518 } 3519 3520 /** 3521 * ixgbe_read_ee_aci_e610 - Read EEPROM word using the admin command. 3522 * @hw: pointer to hardware structure 3523 * @offset: offset of word in the EEPROM to read 3524 * @data: word read from the EEPROM 3525 * 3526 * Reads a 16 bit word from the EEPROM using the ACI. 3527 * If the EEPROM params are not initialized, the function 3528 * initialize them before proceeding with reading. 3529 * The function acquires and then releases the NVM ownership. 3530 * 3531 * Return: the exit code of the operation. 3532 */ 3533 int ixgbe_read_ee_aci_e610(struct ixgbe_hw *hw, u16 offset, u16 *data) 3534 { 3535 int err; 3536 3537 if (hw->eeprom.type == ixgbe_eeprom_uninitialized) { 3538 err = hw->eeprom.ops.init_params(hw); 3539 if (err) 3540 return err; 3541 } 3542 3543 err = ixgbe_acquire_nvm(hw, IXGBE_RES_READ); 3544 if (err) 3545 return err; 3546 3547 err = ixgbe_read_sr_word_aci(hw, offset, data); 3548 ixgbe_release_nvm(hw); 3549 3550 return err; 3551 } 3552 3553 /** 3554 * ixgbe_read_ee_aci_buffer_e610 - Read EEPROM words via ACI 3555 * @hw: pointer to hardware structure 3556 * @offset: offset of words in the EEPROM to read 3557 * @words: number of words to read 3558 * @data: words to read from the EEPROM 3559 * 3560 * Read 16 bit words from the EEPROM via the ACI. Initialize the EEPROM params 3561 * prior to the read. Acquire/release the NVM ownership. 3562 * 3563 * Return: the operation exit code. 3564 */ 3565 int ixgbe_read_ee_aci_buffer_e610(struct ixgbe_hw *hw, u16 offset, 3566 u16 words, u16 *data) 3567 { 3568 int err; 3569 3570 if (hw->eeprom.type == ixgbe_eeprom_uninitialized) { 3571 err = hw->eeprom.ops.init_params(hw); 3572 if (err) 3573 return err; 3574 } 3575 3576 err = ixgbe_acquire_nvm(hw, IXGBE_RES_READ); 3577 if (err) 3578 return err; 3579 3580 err = ixgbe_read_sr_buf_aci(hw, offset, &words, data); 3581 ixgbe_release_nvm(hw); 3582 3583 return err; 3584 } 3585 3586 /** 3587 * ixgbe_validate_eeprom_checksum_e610 - Validate EEPROM checksum 3588 * @hw: pointer to hardware structure 3589 * @checksum_val: calculated checksum 3590 * 3591 * Performs checksum calculation and validates the EEPROM checksum. If the 3592 * caller does not need checksum_val, the value can be NULL. 3593 * If the EEPROM params are not initialized, the function 3594 * initialize them before proceeding. 3595 * The function acquires and then releases the NVM ownership. 3596 * 3597 * Return: the exit code of the operation. 3598 */ 3599 int ixgbe_validate_eeprom_checksum_e610(struct ixgbe_hw *hw, u16 *checksum_val) 3600 { 3601 int err; 3602 3603 if (hw->eeprom.type == ixgbe_eeprom_uninitialized) { 3604 err = hw->eeprom.ops.init_params(hw); 3605 if (err) 3606 return err; 3607 } 3608 3609 err = ixgbe_nvm_validate_checksum(hw); 3610 if (err) 3611 return err; 3612 3613 if (checksum_val) { 3614 u16 tmp_checksum; 3615 3616 err = ixgbe_acquire_nvm(hw, IXGBE_RES_READ); 3617 if (err) 3618 return err; 3619 3620 err = ixgbe_read_sr_word_aci(hw, IXGBE_E610_SR_SW_CHECKSUM_WORD, 3621 &tmp_checksum); 3622 ixgbe_release_nvm(hw); 3623 3624 if (!err) 3625 *checksum_val = tmp_checksum; 3626 } 3627 3628 return err; 3629 } 3630 3631 /** 3632 * ixgbe_reset_hw_e610 - Perform hardware reset 3633 * @hw: pointer to hardware structure 3634 * 3635 * Resets the hardware by resetting the transmit and receive units, masks 3636 * and clears all interrupts, and performs a reset. 3637 * 3638 * Return: the exit code of the operation. 3639 */ 3640 int ixgbe_reset_hw_e610(struct ixgbe_hw *hw) 3641 { 3642 u32 swfw_mask = hw->phy.phy_semaphore_mask; 3643 u32 ctrl, i; 3644 int err; 3645 3646 /* Call adapter stop to disable tx/rx and clear interrupts */ 3647 err = hw->mac.ops.stop_adapter(hw); 3648 if (err) 3649 goto reset_hw_out; 3650 3651 /* Flush pending Tx transactions. */ 3652 ixgbe_clear_tx_pending(hw); 3653 3654 hw->phy.ops.init(hw); 3655 mac_reset_top: 3656 err = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 3657 if (err) 3658 return -EBUSY; 3659 ctrl = IXGBE_CTRL_RST; 3660 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 3661 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 3662 IXGBE_WRITE_FLUSH(hw); 3663 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3664 3665 /* Poll for reset bit to self-clear indicating reset is complete */ 3666 for (i = 0; i < 10; i++) { 3667 udelay(1); 3668 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 3669 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 3670 break; 3671 } 3672 3673 if (ctrl & IXGBE_CTRL_RST_MASK) { 3674 struct ixgbe_adapter *adapter = container_of(hw, struct ixgbe_adapter, 3675 hw); 3676 3677 err = -EIO; 3678 netdev_err(adapter->netdev, "Reset polling failed to complete."); 3679 } 3680 3681 /* Double resets are required for recovery from certain error 3682 * conditions. Between resets, it is necessary to stall to allow time 3683 * for any pending HW events to complete. 3684 */ 3685 msleep(100); 3686 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 3687 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3688 goto mac_reset_top; 3689 } 3690 3691 /* Set the Rx packet buffer size. */ 3692 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), GENMASK(18, 17)); 3693 3694 /* Store the permanent mac address */ 3695 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 3696 3697 /* Maximum number of Receive Address Registers. */ 3698 #define IXGBE_MAX_NUM_RAR 128 3699 3700 /* Store MAC address from RAR0, clear receive address registers, and 3701 * clear the multicast table. Also reset num_rar_entries to the 3702 * maximum number of Receive Address Registers, since we modify this 3703 * value when programming the SAN MAC address. 3704 */ 3705 hw->mac.num_rar_entries = IXGBE_MAX_NUM_RAR; 3706 hw->mac.ops.init_rx_addrs(hw); 3707 3708 /* Initialize bus function number */ 3709 hw->mac.ops.set_lan_id(hw); 3710 3711 reset_hw_out: 3712 return err; 3713 } 3714 3715 /** 3716 * ixgbe_get_pfa_module_tlv - Read sub module TLV from NVM PFA 3717 * @hw: pointer to hardware structure 3718 * @module_tlv: pointer to module TLV to return 3719 * @module_tlv_len: pointer to module TLV length to return 3720 * @module_type: module type requested 3721 * 3722 * Find the requested sub module TLV type from the Preserved Field 3723 * Area (PFA) and returns the TLV pointer and length. The caller can 3724 * use these to read the variable length TLV value. 3725 * 3726 * Return: the exit code of the operation. 3727 */ 3728 static int ixgbe_get_pfa_module_tlv(struct ixgbe_hw *hw, u16 *module_tlv, 3729 u16 *module_tlv_len, u16 module_type) 3730 { 3731 u16 pfa_len, pfa_ptr, pfa_end_ptr; 3732 u16 next_tlv; 3733 int err; 3734 3735 err = ixgbe_read_ee_aci_e610(hw, IXGBE_E610_SR_PFA_PTR, &pfa_ptr); 3736 if (err) 3737 return err; 3738 3739 err = ixgbe_read_ee_aci_e610(hw, pfa_ptr, &pfa_len); 3740 if (err) 3741 return err; 3742 3743 /* Starting with first TLV after PFA length, iterate through the list 3744 * of TLVs to find the requested one. 3745 */ 3746 next_tlv = pfa_ptr + 1; 3747 pfa_end_ptr = pfa_ptr + pfa_len; 3748 while (next_tlv < pfa_end_ptr) { 3749 u16 tlv_sub_module_type, tlv_len; 3750 3751 /* Read TLV type */ 3752 err = ixgbe_read_ee_aci_e610(hw, next_tlv, 3753 &tlv_sub_module_type); 3754 if (err) 3755 break; 3756 3757 /* Read TLV length */ 3758 err = ixgbe_read_ee_aci_e610(hw, next_tlv + 1, &tlv_len); 3759 if (err) 3760 break; 3761 3762 if (tlv_sub_module_type == module_type) { 3763 if (tlv_len) { 3764 *module_tlv = next_tlv; 3765 *module_tlv_len = tlv_len; 3766 return 0; 3767 } 3768 return -EIO; 3769 } 3770 /* Check next TLV, i.e. current TLV pointer + length + 2 words 3771 * (for current TLV's type and length). 3772 */ 3773 next_tlv = next_tlv + tlv_len + 2; 3774 } 3775 /* Module does not exist */ 3776 return -ENODATA; 3777 } 3778 3779 /** 3780 * ixgbe_read_pba_string_e610 - Read PBA string from NVM 3781 * @hw: pointer to hardware structure 3782 * @pba_num: stores the part number string from the NVM 3783 * @pba_num_size: part number string buffer length 3784 * 3785 * Read the part number string from the NVM. 3786 * 3787 * Return: the exit code of the operation. 3788 */ 3789 static int ixgbe_read_pba_string_e610(struct ixgbe_hw *hw, u8 *pba_num, 3790 u32 pba_num_size) 3791 { 3792 u16 pba_tlv, pba_tlv_len; 3793 u16 pba_word, pba_size; 3794 int err; 3795 3796 *pba_num = '\0'; 3797 3798 err = ixgbe_get_pfa_module_tlv(hw, &pba_tlv, &pba_tlv_len, 3799 IXGBE_E610_SR_PBA_BLOCK_PTR); 3800 if (err) 3801 return err; 3802 3803 /* pba_size is the next word */ 3804 err = ixgbe_read_ee_aci_e610(hw, (pba_tlv + 2), &pba_size); 3805 if (err) 3806 return err; 3807 3808 if (pba_tlv_len < pba_size) 3809 return -EINVAL; 3810 3811 /* Subtract one to get PBA word count (PBA Size word is included in 3812 * total size). 3813 */ 3814 pba_size--; 3815 3816 if (pba_num_size < (((u32)pba_size * 2) + 1)) 3817 return -EINVAL; 3818 3819 for (u16 i = 0; i < pba_size; i++) { 3820 err = ixgbe_read_ee_aci_e610(hw, (pba_tlv + 2 + 1) + i, 3821 &pba_word); 3822 if (err) 3823 return err; 3824 3825 pba_num[(i * 2)] = FIELD_GET(IXGBE_E610_SR_PBA_BLOCK_MASK, 3826 pba_word); 3827 pba_num[(i * 2) + 1] = pba_word & 0xFF; 3828 } 3829 3830 pba_num[(pba_size * 2)] = '\0'; 3831 3832 return err; 3833 } 3834 3835 static const struct ixgbe_mac_operations mac_ops_e610 = { 3836 .init_hw = ixgbe_init_hw_generic, 3837 .start_hw = ixgbe_start_hw_e610, 3838 .clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic, 3839 .enable_rx_dma = ixgbe_enable_rx_dma_generic, 3840 .get_mac_addr = ixgbe_get_mac_addr_generic, 3841 .get_device_caps = ixgbe_get_device_caps_generic, 3842 .stop_adapter = ixgbe_stop_adapter_generic, 3843 .set_lan_id = ixgbe_set_lan_id_multi_port_pcie, 3844 .set_rxpba = ixgbe_set_rxpba_generic, 3845 .check_link = ixgbe_check_link_e610, 3846 .blink_led_start = ixgbe_blink_led_start_X540, 3847 .blink_led_stop = ixgbe_blink_led_stop_X540, 3848 .set_rar = ixgbe_set_rar_generic, 3849 .clear_rar = ixgbe_clear_rar_generic, 3850 .set_vmdq = ixgbe_set_vmdq_generic, 3851 .set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic, 3852 .clear_vmdq = ixgbe_clear_vmdq_generic, 3853 .init_rx_addrs = ixgbe_init_rx_addrs_generic, 3854 .update_mc_addr_list = ixgbe_update_mc_addr_list_generic, 3855 .enable_mc = ixgbe_enable_mc_generic, 3856 .disable_mc = ixgbe_disable_mc_generic, 3857 .clear_vfta = ixgbe_clear_vfta_generic, 3858 .set_vfta = ixgbe_set_vfta_generic, 3859 .fc_enable = ixgbe_fc_enable_generic, 3860 .set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550, 3861 .init_uta_tables = ixgbe_init_uta_tables_generic, 3862 .set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing, 3863 .set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing, 3864 .set_source_address_pruning = 3865 ixgbe_set_source_address_pruning_x550, 3866 .set_ethertype_anti_spoofing = 3867 ixgbe_set_ethertype_anti_spoofing_x550, 3868 .disable_rx_buff = ixgbe_disable_rx_buff_generic, 3869 .enable_rx_buff = ixgbe_enable_rx_buff_generic, 3870 .enable_rx = ixgbe_enable_rx_generic, 3871 .disable_rx = ixgbe_disable_rx_e610, 3872 .led_on = ixgbe_led_on_generic, 3873 .led_off = ixgbe_led_off_generic, 3874 .init_led_link_act = ixgbe_init_led_link_act_generic, 3875 .reset_hw = ixgbe_reset_hw_e610, 3876 .get_media_type = ixgbe_get_media_type_e610, 3877 .setup_link = ixgbe_setup_link_e610, 3878 .get_link_capabilities = ixgbe_get_link_capabilities_e610, 3879 .get_bus_info = ixgbe_get_bus_info_generic, 3880 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540, 3881 .release_swfw_sync = ixgbe_release_swfw_sync_X540, 3882 .init_swfw_sync = ixgbe_init_swfw_sync_X540, 3883 .prot_autoc_read = prot_autoc_read_generic, 3884 .prot_autoc_write = prot_autoc_write_generic, 3885 .setup_fc = ixgbe_setup_fc_e610, 3886 .fc_autoneg = ixgbe_fc_autoneg_e610, 3887 }; 3888 3889 static const struct ixgbe_phy_operations phy_ops_e610 = { 3890 .init = ixgbe_init_phy_ops_e610, 3891 .identify = ixgbe_identify_phy_e610, 3892 .identify_sfp = ixgbe_identify_module_e610, 3893 .setup_link_speed = ixgbe_setup_phy_link_speed_generic, 3894 .setup_link = ixgbe_setup_phy_link_e610, 3895 .enter_lplu = ixgbe_enter_lplu_e610, 3896 }; 3897 3898 static const struct ixgbe_eeprom_operations eeprom_ops_e610 = { 3899 .read = ixgbe_read_ee_aci_e610, 3900 .read_buffer = ixgbe_read_ee_aci_buffer_e610, 3901 .validate_checksum = ixgbe_validate_eeprom_checksum_e610, 3902 .read_pba_string = ixgbe_read_pba_string_e610, 3903 .init_params = ixgbe_init_eeprom_params_e610, 3904 }; 3905 3906 const struct ixgbe_info ixgbe_e610_info = { 3907 .mac = ixgbe_mac_e610, 3908 .get_invariants = ixgbe_get_invariants_X540, 3909 .mac_ops = &mac_ops_e610, 3910 .eeprom_ops = &eeprom_ops_e610, 3911 .phy_ops = &phy_ops_e610, 3912 .mbx_ops = &mbx_ops_generic, 3913 .mvals = ixgbe_mvals_x550em_a, 3914 }; 3915