1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2024 Intel Corporation. */ 3 4 #include "ixgbe_common.h" 5 #include "ixgbe_e610.h" 6 #include "ixgbe_x550.h" 7 #include "ixgbe_type.h" 8 #include "ixgbe_x540.h" 9 #include "ixgbe_mbx.h" 10 #include "ixgbe_phy.h" 11 12 /** 13 * ixgbe_should_retry_aci_send_cmd_execute - decide if ACI command should 14 * be resent 15 * @opcode: ACI opcode 16 * 17 * Check if ACI command should be sent again depending on the provided opcode. 18 * It may happen when CSR is busy during link state changes. 19 * 20 * Return: true if the sending command routine should be repeated, 21 * otherwise false. 22 */ 23 static bool ixgbe_should_retry_aci_send_cmd_execute(u16 opcode) 24 { 25 switch (opcode) { 26 case ixgbe_aci_opc_disable_rxen: 27 case ixgbe_aci_opc_get_phy_caps: 28 case ixgbe_aci_opc_get_link_status: 29 case ixgbe_aci_opc_get_link_topo: 30 return true; 31 } 32 33 return false; 34 } 35 36 /** 37 * ixgbe_aci_send_cmd_execute - execute sending FW Admin Command to FW Admin 38 * Command Interface 39 * @hw: pointer to the HW struct 40 * @desc: descriptor describing the command 41 * @buf: buffer to use for indirect commands (NULL for direct commands) 42 * @buf_size: size of buffer for indirect commands (0 for direct commands) 43 * 44 * Admin Command is sent using CSR by setting descriptor and buffer in specific 45 * registers. 46 * 47 * Return: the exit code of the operation. 48 * * - 0 - success. 49 * * - -EIO - CSR mechanism is not enabled. 50 * * - -EBUSY - CSR mechanism is busy. 51 * * - -EINVAL - buf_size is too big or 52 * invalid argument buf or buf_size. 53 * * - -ETIME - Admin Command X command timeout. 54 * * - -EIO - Admin Command X invalid state of HICR register or 55 * Admin Command failed because of bad opcode was returned or 56 * Admin Command failed with error Y. 57 */ 58 static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw *hw, 59 struct libie_aq_desc *desc, 60 void *buf, u16 buf_size) 61 { 62 u16 opcode, buf_tail_size = buf_size % 4; 63 u32 *raw_desc = (u32 *)desc; 64 u32 hicr, i, buf_tail = 0; 65 bool valid_buf = false; 66 67 hw->aci.last_status = LIBIE_AQ_RC_OK; 68 69 /* It's necessary to check if mechanism is enabled */ 70 hicr = IXGBE_READ_REG(hw, IXGBE_PF_HICR); 71 72 if (!(hicr & IXGBE_PF_HICR_EN)) 73 return -EIO; 74 75 if (hicr & IXGBE_PF_HICR_C) { 76 hw->aci.last_status = LIBIE_AQ_RC_EBUSY; 77 return -EBUSY; 78 } 79 80 opcode = le16_to_cpu(desc->opcode); 81 82 if (buf_size > IXGBE_ACI_MAX_BUFFER_SIZE) 83 return -EINVAL; 84 85 if (buf) 86 desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF); 87 88 if (desc->flags & cpu_to_le16(LIBIE_AQ_FLAG_BUF)) { 89 if ((buf && !buf_size) || 90 (!buf && buf_size)) 91 return -EINVAL; 92 if (buf && buf_size) 93 valid_buf = true; 94 } 95 96 if (valid_buf) { 97 if (buf_tail_size) 98 memcpy(&buf_tail, buf + buf_size - buf_tail_size, 99 buf_tail_size); 100 101 if (((buf_size + 3) & ~0x3) > LIBIE_AQ_LG_BUF) 102 desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_LB); 103 104 desc->datalen = cpu_to_le16(buf_size); 105 106 if (desc->flags & cpu_to_le16(LIBIE_AQ_FLAG_RD)) { 107 for (i = 0; i < buf_size / 4; i++) 108 IXGBE_WRITE_REG(hw, IXGBE_PF_HIBA(i), ((u32 *)buf)[i]); 109 if (buf_tail_size) 110 IXGBE_WRITE_REG(hw, IXGBE_PF_HIBA(i), buf_tail); 111 } 112 } 113 114 /* Descriptor is written to specific registers */ 115 for (i = 0; i < IXGBE_ACI_DESC_SIZE_IN_DWORDS; i++) 116 IXGBE_WRITE_REG(hw, IXGBE_PF_HIDA(i), raw_desc[i]); 117 118 /* SW has to set PF_HICR.C bit and clear PF_HICR.SV and 119 * PF_HICR_EV 120 */ 121 hicr = (IXGBE_READ_REG(hw, IXGBE_PF_HICR) | IXGBE_PF_HICR_C) & 122 ~(IXGBE_PF_HICR_SV | IXGBE_PF_HICR_EV); 123 IXGBE_WRITE_REG(hw, IXGBE_PF_HICR, hicr); 124 125 #define MAX_SLEEP_RESP_US 1000 126 #define MAX_TMOUT_RESP_SYNC_US 100000000 127 128 /* Wait for sync Admin Command response */ 129 read_poll_timeout(IXGBE_READ_REG, hicr, 130 (hicr & IXGBE_PF_HICR_SV) || 131 !(hicr & IXGBE_PF_HICR_C), 132 MAX_SLEEP_RESP_US, MAX_TMOUT_RESP_SYNC_US, true, hw, 133 IXGBE_PF_HICR); 134 135 #define MAX_TMOUT_RESP_ASYNC_US 150000000 136 137 /* Wait for async Admin Command response */ 138 read_poll_timeout(IXGBE_READ_REG, hicr, 139 (hicr & IXGBE_PF_HICR_EV) || 140 !(hicr & IXGBE_PF_HICR_C), 141 MAX_SLEEP_RESP_US, MAX_TMOUT_RESP_ASYNC_US, true, hw, 142 IXGBE_PF_HICR); 143 144 /* Read sync Admin Command response */ 145 if ((hicr & IXGBE_PF_HICR_SV)) { 146 for (i = 0; i < IXGBE_ACI_DESC_SIZE_IN_DWORDS; i++) { 147 raw_desc[i] = IXGBE_READ_REG(hw, IXGBE_PF_HIDA(i)); 148 raw_desc[i] = raw_desc[i]; 149 } 150 } 151 152 /* Read async Admin Command response */ 153 if ((hicr & IXGBE_PF_HICR_EV) && !(hicr & IXGBE_PF_HICR_C)) { 154 for (i = 0; i < IXGBE_ACI_DESC_SIZE_IN_DWORDS; i++) { 155 raw_desc[i] = IXGBE_READ_REG(hw, IXGBE_PF_HIDA_2(i)); 156 raw_desc[i] = raw_desc[i]; 157 } 158 } 159 160 /* Handle timeout and invalid state of HICR register */ 161 if (hicr & IXGBE_PF_HICR_C) 162 return -ETIME; 163 164 if (!(hicr & IXGBE_PF_HICR_SV) && !(hicr & IXGBE_PF_HICR_EV)) 165 return -EIO; 166 167 /* For every command other than 0x0014 treat opcode mismatch 168 * as an error. Response to 0x0014 command read from HIDA_2 169 * is a descriptor of an event which is expected to contain 170 * different opcode than the command. 171 */ 172 if (desc->opcode != cpu_to_le16(opcode) && 173 opcode != ixgbe_aci_opc_get_fw_event) 174 return -EIO; 175 176 if (desc->retval) { 177 hw->aci.last_status = (enum libie_aq_err) 178 le16_to_cpu(desc->retval); 179 return -EIO; 180 } 181 182 /* Write a response values to a buf */ 183 if (valid_buf) { 184 for (i = 0; i < buf_size / 4; i++) 185 ((u32 *)buf)[i] = IXGBE_READ_REG(hw, IXGBE_PF_HIBA(i)); 186 if (buf_tail_size) { 187 buf_tail = IXGBE_READ_REG(hw, IXGBE_PF_HIBA(i)); 188 memcpy(buf + buf_size - buf_tail_size, &buf_tail, 189 buf_tail_size); 190 } 191 } 192 193 return 0; 194 } 195 196 /** 197 * ixgbe_aci_send_cmd - send FW Admin Command to FW Admin Command Interface 198 * @hw: pointer to the HW struct 199 * @desc: descriptor describing the command 200 * @buf: buffer to use for indirect commands (NULL for direct commands) 201 * @buf_size: size of buffer for indirect commands (0 for direct commands) 202 * 203 * Helper function to send FW Admin Commands to the FW Admin Command Interface. 204 * 205 * Retry sending the FW Admin Command multiple times to the FW ACI 206 * if the EBUSY Admin Command error is returned. 207 * 208 * Return: the exit code of the operation. 209 */ 210 int ixgbe_aci_send_cmd(struct ixgbe_hw *hw, struct libie_aq_desc *desc, 211 void *buf, u16 buf_size) 212 { 213 u16 opcode = le16_to_cpu(desc->opcode); 214 struct libie_aq_desc desc_cpy; 215 enum libie_aq_err last_status; 216 u8 idx = 0, *buf_cpy = NULL; 217 bool is_cmd_for_retry; 218 unsigned long timeout; 219 int err; 220 221 is_cmd_for_retry = ixgbe_should_retry_aci_send_cmd_execute(opcode); 222 if (is_cmd_for_retry) { 223 if (buf) { 224 buf_cpy = kmalloc(buf_size, GFP_KERNEL); 225 if (!buf_cpy) 226 return -ENOMEM; 227 *buf_cpy = *(u8 *)buf; 228 } 229 desc_cpy = *desc; 230 } 231 232 timeout = jiffies + msecs_to_jiffies(IXGBE_ACI_SEND_TIMEOUT_MS); 233 do { 234 mutex_lock(&hw->aci.lock); 235 err = ixgbe_aci_send_cmd_execute(hw, desc, buf, buf_size); 236 last_status = hw->aci.last_status; 237 mutex_unlock(&hw->aci.lock); 238 239 if (!is_cmd_for_retry || !err || 240 last_status != LIBIE_AQ_RC_EBUSY) 241 break; 242 243 if (buf) 244 memcpy(buf, buf_cpy, buf_size); 245 *desc = desc_cpy; 246 247 msleep(IXGBE_ACI_SEND_DELAY_TIME_MS); 248 } while (++idx < IXGBE_ACI_SEND_MAX_EXECUTE && 249 time_before(jiffies, timeout)); 250 251 kfree(buf_cpy); 252 253 return err; 254 } 255 256 /** 257 * ixgbe_aci_check_event_pending - check if there are any pending events 258 * @hw: pointer to the HW struct 259 * 260 * Determine if there are any pending events. 261 * 262 * Return: true if there are any currently pending events 263 * otherwise false. 264 */ 265 bool ixgbe_aci_check_event_pending(struct ixgbe_hw *hw) 266 { 267 u32 ep_bit_mask = hw->bus.func ? GL_FWSTS_EP_PF1 : GL_FWSTS_EP_PF0; 268 u32 fwsts = IXGBE_READ_REG(hw, GL_FWSTS); 269 270 return (fwsts & ep_bit_mask) ? true : false; 271 } 272 273 /** 274 * ixgbe_aci_get_event - get an event from ACI 275 * @hw: pointer to the HW struct 276 * @e: event information structure 277 * @pending: optional flag signaling that there are more pending events 278 * 279 * Obtain an event from ACI and return its content 280 * through 'e' using ACI command (0x0014). 281 * Provide information if there are more events 282 * to retrieve through 'pending'. 283 * 284 * Return: the exit code of the operation. 285 */ 286 int ixgbe_aci_get_event(struct ixgbe_hw *hw, struct ixgbe_aci_event *e, 287 bool *pending) 288 { 289 struct libie_aq_desc desc; 290 int err; 291 292 if (!e || (!e->msg_buf && e->buf_len)) 293 return -EINVAL; 294 295 mutex_lock(&hw->aci.lock); 296 297 /* Check if there are any events pending */ 298 if (!ixgbe_aci_check_event_pending(hw)) { 299 err = -ENOENT; 300 goto aci_get_event_exit; 301 } 302 303 /* Obtain pending event */ 304 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_fw_event); 305 err = ixgbe_aci_send_cmd_execute(hw, &desc, e->msg_buf, e->buf_len); 306 if (err) 307 goto aci_get_event_exit; 308 309 /* Returned 0x0014 opcode indicates that no event was obtained */ 310 if (desc.opcode == cpu_to_le16(ixgbe_aci_opc_get_fw_event)) { 311 err = -ENOENT; 312 goto aci_get_event_exit; 313 } 314 315 /* Determine size of event data */ 316 e->msg_len = min_t(u16, le16_to_cpu(desc.datalen), e->buf_len); 317 /* Write event descriptor to event info structure */ 318 memcpy(&e->desc, &desc, sizeof(e->desc)); 319 320 /* Check if there are any further events pending */ 321 if (pending) 322 *pending = ixgbe_aci_check_event_pending(hw); 323 324 aci_get_event_exit: 325 mutex_unlock(&hw->aci.lock); 326 327 return err; 328 } 329 330 /** 331 * ixgbe_fill_dflt_direct_cmd_desc - fill ACI descriptor with default values. 332 * @desc: pointer to the temp descriptor (non DMA mem) 333 * @opcode: the opcode can be used to decide which flags to turn off or on 334 * 335 * Helper function to fill the descriptor desc with default values 336 * and the provided opcode. 337 */ 338 void ixgbe_fill_dflt_direct_cmd_desc(struct libie_aq_desc *desc, u16 opcode) 339 { 340 /* Zero out the desc. */ 341 memset(desc, 0, sizeof(*desc)); 342 desc->opcode = cpu_to_le16(opcode); 343 desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_SI); 344 } 345 346 /** 347 * ixgbe_aci_get_fw_ver - Get the firmware version 348 * @hw: pointer to the HW struct 349 * 350 * Get the firmware version using ACI command (0x0001). 351 * 352 * Return: the exit code of the operation. 353 */ 354 static int ixgbe_aci_get_fw_ver(struct ixgbe_hw *hw) 355 { 356 struct libie_aqc_get_ver *resp; 357 struct libie_aq_desc desc; 358 int err; 359 360 resp = &desc.params.get_ver; 361 362 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_ver); 363 364 err = ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 365 if (!err) { 366 hw->fw_branch = resp->fw_branch; 367 hw->fw_maj_ver = resp->fw_major; 368 hw->fw_min_ver = resp->fw_minor; 369 hw->fw_patch = resp->fw_patch; 370 hw->fw_build = le32_to_cpu(resp->fw_build); 371 hw->api_branch = resp->api_branch; 372 hw->api_maj_ver = resp->api_major; 373 hw->api_min_ver = resp->api_minor; 374 hw->api_patch = resp->api_patch; 375 } 376 377 return err; 378 } 379 380 /** 381 * ixgbe_aci_req_res - request a common resource 382 * @hw: pointer to the HW struct 383 * @res: resource ID 384 * @access: access type 385 * @sdp_number: resource number 386 * @timeout: the maximum time in ms that the driver may hold the resource 387 * 388 * Requests a common resource using the ACI command (0x0008). 389 * Specifies the maximum time the driver may hold the resource. 390 * If the requested resource is currently occupied by some other driver, 391 * a busy return value is returned and the timeout field value indicates the 392 * maximum time the current owner has to free it. 393 * 394 * Return: the exit code of the operation. 395 */ 396 static int ixgbe_aci_req_res(struct ixgbe_hw *hw, enum libie_aq_res_id res, 397 enum libie_aq_res_access_type access, 398 u8 sdp_number, u32 *timeout) 399 { 400 struct libie_aqc_req_res *cmd_resp; 401 struct libie_aq_desc desc; 402 int err; 403 404 cmd_resp = &desc.params.res_owner; 405 406 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_req_res); 407 408 cmd_resp->res_id = cpu_to_le16(res); 409 cmd_resp->access_type = cpu_to_le16(access); 410 cmd_resp->res_number = cpu_to_le32(sdp_number); 411 cmd_resp->timeout = cpu_to_le32(*timeout); 412 *timeout = 0; 413 414 err = ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 415 416 /* If the resource is held by some other driver, the command completes 417 * with a busy return value and the timeout field indicates the maximum 418 * time the current owner of the resource has to free it. 419 */ 420 if (!err || hw->aci.last_status == LIBIE_AQ_RC_EBUSY) 421 *timeout = le32_to_cpu(cmd_resp->timeout); 422 423 return err; 424 } 425 426 /** 427 * ixgbe_aci_release_res - release a common resource using ACI 428 * @hw: pointer to the HW struct 429 * @res: resource ID 430 * @sdp_number: resource number 431 * 432 * Release a common resource using ACI command (0x0009). 433 * 434 * Return: the exit code of the operation. 435 */ 436 static int ixgbe_aci_release_res(struct ixgbe_hw *hw, enum libie_aq_res_id res, 437 u8 sdp_number) 438 { 439 struct libie_aqc_req_res *cmd; 440 struct libie_aq_desc desc; 441 442 cmd = &desc.params.res_owner; 443 444 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_release_res); 445 446 cmd->res_id = cpu_to_le16(res); 447 cmd->res_number = cpu_to_le32(sdp_number); 448 449 return ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 450 } 451 452 /** 453 * ixgbe_acquire_res - acquire the ownership of a resource 454 * @hw: pointer to the HW structure 455 * @res: resource ID 456 * @access: access type (read or write) 457 * @timeout: timeout in milliseconds 458 * 459 * Make an attempt to acquire the ownership of a resource using 460 * the ixgbe_aci_req_res to utilize ACI. 461 * In case if some other driver has previously acquired the resource and 462 * performed any necessary updates, the -EALREADY is returned, 463 * and the caller does not obtain the resource and has no further work to do. 464 * If needed, the function will poll until the current lock owner timeouts. 465 * 466 * Return: the exit code of the operation. 467 */ 468 int ixgbe_acquire_res(struct ixgbe_hw *hw, enum libie_aq_res_id res, 469 enum libie_aq_res_access_type access, u32 timeout) 470 { 471 #define IXGBE_RES_POLLING_DELAY_MS 10 472 u32 delay = IXGBE_RES_POLLING_DELAY_MS; 473 u32 res_timeout = timeout; 474 u32 retry_timeout; 475 int err; 476 477 err = ixgbe_aci_req_res(hw, res, access, 0, &res_timeout); 478 479 /* A return code of -EALREADY means that another driver has 480 * previously acquired the resource and performed any necessary updates; 481 * in this case the caller does not obtain the resource and has no 482 * further work to do. 483 */ 484 if (err == -EALREADY) 485 return err; 486 487 /* If necessary, poll until the current lock owner timeouts. 488 * Set retry_timeout to the timeout value reported by the FW in the 489 * response to the "Request Resource Ownership" (0x0008) Admin Command 490 * as it indicates the maximum time the current owner of the resource 491 * is allowed to hold it. 492 */ 493 retry_timeout = res_timeout; 494 while (err && retry_timeout && res_timeout) { 495 msleep(delay); 496 retry_timeout = (retry_timeout > delay) ? 497 retry_timeout - delay : 0; 498 err = ixgbe_aci_req_res(hw, res, access, 0, &res_timeout); 499 500 /* Success - lock acquired. 501 * -EALREADY - lock free, no work to do. 502 */ 503 if (!err || err == -EALREADY) 504 break; 505 } 506 507 return err; 508 } 509 510 /** 511 * ixgbe_release_res - release a common resource 512 * @hw: pointer to the HW structure 513 * @res: resource ID 514 * 515 * Release a common resource using ixgbe_aci_release_res. 516 */ 517 void ixgbe_release_res(struct ixgbe_hw *hw, enum libie_aq_res_id res) 518 { 519 u32 total_delay = 0; 520 int err; 521 522 err = ixgbe_aci_release_res(hw, res, 0); 523 524 /* There are some rare cases when trying to release the resource 525 * results in an admin command timeout, so handle them correctly. 526 */ 527 while (err == -ETIME && 528 total_delay < IXGBE_ACI_RELEASE_RES_TIMEOUT) { 529 usleep_range(1000, 1500); 530 err = ixgbe_aci_release_res(hw, res, 0); 531 total_delay++; 532 } 533 } 534 535 /** 536 * ixgbe_parse_e610_caps - Parse common device/function capabilities 537 * @hw: pointer to the HW struct 538 * @caps: pointer to common capabilities structure 539 * @elem: the capability element to parse 540 * @prefix: message prefix for tracing capabilities 541 * 542 * Given a capability element, extract relevant details into the common 543 * capability structure. 544 * 545 * Return: true if the capability matches one of the common capability ids, 546 * false otherwise. 547 */ 548 static bool ixgbe_parse_e610_caps(struct ixgbe_hw *hw, 549 struct ixgbe_hw_caps *caps, 550 struct libie_aqc_list_caps_elem *elem, 551 const char *prefix) 552 { 553 u32 logical_id = le32_to_cpu(elem->logical_id); 554 u32 phys_id = le32_to_cpu(elem->phys_id); 555 u32 number = le32_to_cpu(elem->number); 556 u16 cap = le16_to_cpu(elem->cap); 557 558 switch (cap) { 559 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 560 caps->valid_functions = number; 561 break; 562 case LIBIE_AQC_CAPS_SRIOV: 563 caps->sr_iov_1_1 = (number == 1); 564 break; 565 case LIBIE_AQC_CAPS_VMDQ: 566 caps->vmdq = (number == 1); 567 break; 568 case LIBIE_AQC_CAPS_DCB: 569 caps->dcb = (number == 1); 570 caps->active_tc_bitmap = logical_id; 571 caps->maxtc = phys_id; 572 break; 573 case LIBIE_AQC_CAPS_RSS: 574 caps->rss_table_size = number; 575 caps->rss_table_entry_width = logical_id; 576 break; 577 case LIBIE_AQC_CAPS_RXQS: 578 caps->num_rxq = number; 579 caps->rxq_first_id = phys_id; 580 break; 581 case LIBIE_AQC_CAPS_TXQS: 582 caps->num_txq = number; 583 caps->txq_first_id = phys_id; 584 break; 585 case LIBIE_AQC_CAPS_MSIX: 586 caps->num_msix_vectors = number; 587 caps->msix_vector_first_id = phys_id; 588 break; 589 case LIBIE_AQC_CAPS_NVM_VER: 590 break; 591 case LIBIE_AQC_CAPS_PENDING_NVM_VER: 592 caps->nvm_update_pending_nvm = true; 593 break; 594 case LIBIE_AQC_CAPS_PENDING_OROM_VER: 595 caps->nvm_update_pending_orom = true; 596 break; 597 case LIBIE_AQC_CAPS_PENDING_NET_VER: 598 caps->nvm_update_pending_netlist = true; 599 break; 600 case LIBIE_AQC_CAPS_NVM_MGMT: 601 caps->nvm_unified_update = 602 (number & IXGBE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 603 true : false; 604 break; 605 case LIBIE_AQC_CAPS_MAX_MTU: 606 caps->max_mtu = number; 607 break; 608 case LIBIE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 609 caps->pcie_reset_avoidance = (number > 0); 610 break; 611 case LIBIE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 612 caps->reset_restrict_support = (number == 1); 613 break; 614 case LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG0: 615 case LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG1: 616 case LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG2: 617 case LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG3: 618 { 619 u8 index = cap - LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG0; 620 621 caps->ext_topo_dev_img_ver_high[index] = number; 622 caps->ext_topo_dev_img_ver_low[index] = logical_id; 623 caps->ext_topo_dev_img_part_num[index] = 624 FIELD_GET(IXGBE_EXT_TOPO_DEV_IMG_PART_NUM_M, phys_id); 625 caps->ext_topo_dev_img_load_en[index] = 626 (phys_id & IXGBE_EXT_TOPO_DEV_IMG_LOAD_EN) != 0; 627 caps->ext_topo_dev_img_prog_en[index] = 628 (phys_id & IXGBE_EXT_TOPO_DEV_IMG_PROG_EN) != 0; 629 break; 630 } 631 default: 632 /* Not one of the recognized common capabilities */ 633 return false; 634 } 635 636 return true; 637 } 638 639 /** 640 * ixgbe_parse_valid_functions_cap - Parse LIBIE_AQC_CAPS_VALID_FUNCTIONS caps 641 * @hw: pointer to the HW struct 642 * @dev_p: pointer to device capabilities structure 643 * @cap: capability element to parse 644 * 645 * Parse LIBIE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 646 */ 647 static void 648 ixgbe_parse_valid_functions_cap(struct ixgbe_hw *hw, 649 struct ixgbe_hw_dev_caps *dev_p, 650 struct libie_aqc_list_caps_elem *cap) 651 { 652 dev_p->num_funcs = hweight32(le32_to_cpu(cap->number)); 653 } 654 655 /** 656 * ixgbe_parse_vf_dev_caps - Parse LIBIE_AQC_CAPS_VF device caps 657 * @hw: pointer to the HW struct 658 * @dev_p: pointer to device capabilities structure 659 * @cap: capability element to parse 660 * 661 * Parse LIBIE_AQC_CAPS_VF for device capabilities. 662 */ 663 static void ixgbe_parse_vf_dev_caps(struct ixgbe_hw *hw, 664 struct ixgbe_hw_dev_caps *dev_p, 665 struct libie_aqc_list_caps_elem *cap) 666 { 667 dev_p->num_vfs_exposed = le32_to_cpu(cap->number); 668 } 669 670 /** 671 * ixgbe_parse_vsi_dev_caps - Parse LIBIE_AQC_CAPS_VSI device caps 672 * @hw: pointer to the HW struct 673 * @dev_p: pointer to device capabilities structure 674 * @cap: capability element to parse 675 * 676 * Parse LIBIE_AQC_CAPS_VSI for device capabilities. 677 */ 678 static void ixgbe_parse_vsi_dev_caps(struct ixgbe_hw *hw, 679 struct ixgbe_hw_dev_caps *dev_p, 680 struct libie_aqc_list_caps_elem *cap) 681 { 682 dev_p->num_vsi_allocd_to_host = le32_to_cpu(cap->number); 683 } 684 685 /** 686 * ixgbe_parse_fdir_dev_caps - Parse LIBIE_AQC_CAPS_FD device caps 687 * @hw: pointer to the HW struct 688 * @dev_p: pointer to device capabilities structure 689 * @cap: capability element to parse 690 * 691 * Parse LIBIE_AQC_CAPS_FD for device capabilities. 692 */ 693 static void ixgbe_parse_fdir_dev_caps(struct ixgbe_hw *hw, 694 struct ixgbe_hw_dev_caps *dev_p, 695 struct libie_aqc_list_caps_elem *cap) 696 { 697 dev_p->num_flow_director_fltr = le32_to_cpu(cap->number); 698 } 699 700 /** 701 * ixgbe_parse_dev_caps - Parse device capabilities 702 * @hw: pointer to the HW struct 703 * @dev_p: pointer to device capabilities structure 704 * @buf: buffer containing the device capability records 705 * @cap_count: the number of capabilities 706 * 707 * Helper device to parse device (0x000B) capabilities list. For 708 * capabilities shared between device and function, this relies on 709 * ixgbe_parse_e610_caps. 710 * 711 * Loop through the list of provided capabilities and extract the relevant 712 * data into the device capabilities structured. 713 */ 714 static void ixgbe_parse_dev_caps(struct ixgbe_hw *hw, 715 struct ixgbe_hw_dev_caps *dev_p, 716 void *buf, u32 cap_count) 717 { 718 struct libie_aqc_list_caps_elem *cap_resp; 719 u32 i; 720 721 cap_resp = (struct libie_aqc_list_caps_elem *)buf; 722 723 memset(dev_p, 0, sizeof(*dev_p)); 724 725 for (i = 0; i < cap_count; i++) { 726 u16 cap = le16_to_cpu(cap_resp[i].cap); 727 728 ixgbe_parse_e610_caps(hw, &dev_p->common_cap, &cap_resp[i], 729 "dev caps"); 730 731 switch (cap) { 732 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 733 ixgbe_parse_valid_functions_cap(hw, dev_p, 734 &cap_resp[i]); 735 break; 736 case LIBIE_AQC_CAPS_VF: 737 ixgbe_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 738 break; 739 case LIBIE_AQC_CAPS_VSI: 740 ixgbe_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 741 break; 742 case LIBIE_AQC_CAPS_FD: 743 ixgbe_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 744 break; 745 default: 746 /* Don't list common capabilities as unknown */ 747 break; 748 } 749 } 750 } 751 752 /** 753 * ixgbe_parse_vf_func_caps - Parse LIBIE_AQC_CAPS_VF function caps 754 * @hw: pointer to the HW struct 755 * @func_p: pointer to function capabilities structure 756 * @cap: pointer to the capability element to parse 757 * 758 * Extract function capabilities for LIBIE_AQC_CAPS_VF. 759 */ 760 static void ixgbe_parse_vf_func_caps(struct ixgbe_hw *hw, 761 struct ixgbe_hw_func_caps *func_p, 762 struct libie_aqc_list_caps_elem *cap) 763 { 764 func_p->num_allocd_vfs = le32_to_cpu(cap->number); 765 func_p->vf_base_id = le32_to_cpu(cap->logical_id); 766 } 767 768 /** 769 * ixgbe_get_num_per_func - determine number of resources per PF 770 * @hw: pointer to the HW structure 771 * @max: value to be evenly split between each PF 772 * 773 * Determine the number of valid functions by going through the bitmap returned 774 * from parsing capabilities and use this to calculate the number of resources 775 * per PF based on the max value passed in. 776 * 777 * Return: the number of resources per PF or 0, if no PH are available. 778 */ 779 static u32 ixgbe_get_num_per_func(struct ixgbe_hw *hw, u32 max) 780 { 781 #define IXGBE_CAPS_VALID_FUNCS_M GENMASK(7, 0) 782 u8 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 783 IXGBE_CAPS_VALID_FUNCS_M); 784 785 return funcs ? (max / funcs) : 0; 786 } 787 788 /** 789 * ixgbe_parse_vsi_func_caps - Parse LIBIE_AQC_CAPS_VSI function caps 790 * @hw: pointer to the HW struct 791 * @func_p: pointer to function capabilities structure 792 * @cap: pointer to the capability element to parse 793 * 794 * Extract function capabilities for LIBIE_AQC_CAPS_VSI. 795 */ 796 static void ixgbe_parse_vsi_func_caps(struct ixgbe_hw *hw, 797 struct ixgbe_hw_func_caps *func_p, 798 struct libie_aqc_list_caps_elem *cap) 799 { 800 func_p->guar_num_vsi = ixgbe_get_num_per_func(hw, IXGBE_MAX_VSI); 801 } 802 803 /** 804 * ixgbe_parse_func_caps - Parse function capabilities 805 * @hw: pointer to the HW struct 806 * @func_p: pointer to function capabilities structure 807 * @buf: buffer containing the function capability records 808 * @cap_count: the number of capabilities 809 * 810 * Helper function to parse function (0x000A) capabilities list. For 811 * capabilities shared between device and function, this relies on 812 * ixgbe_parse_e610_caps. 813 * 814 * Loop through the list of provided capabilities and extract the relevant 815 * data into the function capabilities structured. 816 */ 817 static void ixgbe_parse_func_caps(struct ixgbe_hw *hw, 818 struct ixgbe_hw_func_caps *func_p, 819 void *buf, u32 cap_count) 820 { 821 struct libie_aqc_list_caps_elem *cap_resp; 822 u32 i; 823 824 cap_resp = (struct libie_aqc_list_caps_elem *)buf; 825 826 memset(func_p, 0, sizeof(*func_p)); 827 828 for (i = 0; i < cap_count; i++) { 829 u16 cap = le16_to_cpu(cap_resp[i].cap); 830 831 ixgbe_parse_e610_caps(hw, &func_p->common_cap, 832 &cap_resp[i], "func caps"); 833 834 switch (cap) { 835 case LIBIE_AQC_CAPS_VF: 836 ixgbe_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 837 break; 838 case LIBIE_AQC_CAPS_VSI: 839 ixgbe_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 840 break; 841 default: 842 /* Don't list common capabilities as unknown */ 843 break; 844 } 845 } 846 } 847 848 /** 849 * ixgbe_aci_list_caps - query function/device capabilities 850 * @hw: pointer to the HW struct 851 * @buf: a buffer to hold the capabilities 852 * @buf_size: size of the buffer 853 * @cap_count: if not NULL, set to the number of capabilities reported 854 * @opc: capabilities type to discover, device or function 855 * 856 * Get the function (0x000A) or device (0x000B) capabilities description from 857 * firmware and store it in the buffer. 858 * 859 * If the cap_count pointer is not NULL, then it is set to the number of 860 * capabilities firmware will report. Note that if the buffer size is too 861 * small, it is possible the command will return -ENOMEM. The 862 * cap_count will still be updated in this case. It is recommended that the 863 * buffer size be set to IXGBE_ACI_MAX_BUFFER_SIZE (the largest possible 864 * buffer that firmware could return) to avoid this. 865 * 866 * Return: the exit code of the operation. 867 * Exit code of -ENOMEM means the buffer size is too small. 868 */ 869 int ixgbe_aci_list_caps(struct ixgbe_hw *hw, void *buf, u16 buf_size, 870 u32 *cap_count, enum ixgbe_aci_opc opc) 871 { 872 struct libie_aqc_list_caps *cmd; 873 struct libie_aq_desc desc; 874 int err; 875 876 cmd = &desc.params.get_cap; 877 878 if (opc != ixgbe_aci_opc_list_func_caps && 879 opc != ixgbe_aci_opc_list_dev_caps) 880 return -EINVAL; 881 882 ixgbe_fill_dflt_direct_cmd_desc(&desc, opc); 883 err = ixgbe_aci_send_cmd(hw, &desc, buf, buf_size); 884 885 if (cap_count) 886 *cap_count = le32_to_cpu(cmd->count); 887 888 return err; 889 } 890 891 /** 892 * ixgbe_discover_dev_caps - Read and extract device capabilities 893 * @hw: pointer to the hardware structure 894 * @dev_caps: pointer to device capabilities structure 895 * 896 * Read the device capabilities and extract them into the dev_caps structure 897 * for later use. 898 * 899 * Return: the exit code of the operation. 900 */ 901 int ixgbe_discover_dev_caps(struct ixgbe_hw *hw, 902 struct ixgbe_hw_dev_caps *dev_caps) 903 { 904 u32 cap_count; 905 u8 *cbuf; 906 int err; 907 908 cbuf = kzalloc(IXGBE_ACI_MAX_BUFFER_SIZE, GFP_KERNEL); 909 if (!cbuf) 910 return -ENOMEM; 911 912 /* Although the driver doesn't know the number of capabilities the 913 * device will return, we can simply send a 4KB buffer, the maximum 914 * possible size that firmware can return. 915 */ 916 cap_count = IXGBE_ACI_MAX_BUFFER_SIZE / 917 sizeof(struct libie_aqc_list_caps_elem); 918 919 err = ixgbe_aci_list_caps(hw, cbuf, IXGBE_ACI_MAX_BUFFER_SIZE, 920 &cap_count, 921 ixgbe_aci_opc_list_dev_caps); 922 if (!err) 923 ixgbe_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 924 925 kfree(cbuf); 926 927 return 0; 928 } 929 930 /** 931 * ixgbe_discover_func_caps - Read and extract function capabilities 932 * @hw: pointer to the hardware structure 933 * @func_caps: pointer to function capabilities structure 934 * 935 * Read the function capabilities and extract them into the func_caps structure 936 * for later use. 937 * 938 * Return: the exit code of the operation. 939 */ 940 int ixgbe_discover_func_caps(struct ixgbe_hw *hw, 941 struct ixgbe_hw_func_caps *func_caps) 942 { 943 u32 cap_count; 944 u8 *cbuf; 945 int err; 946 947 cbuf = kzalloc(IXGBE_ACI_MAX_BUFFER_SIZE, GFP_KERNEL); 948 if (!cbuf) 949 return -ENOMEM; 950 951 /* Although the driver doesn't know the number of capabilities the 952 * device will return, we can simply send a 4KB buffer, the maximum 953 * possible size that firmware can return. 954 */ 955 cap_count = IXGBE_ACI_MAX_BUFFER_SIZE / 956 sizeof(struct libie_aqc_list_caps_elem); 957 958 err = ixgbe_aci_list_caps(hw, cbuf, IXGBE_ACI_MAX_BUFFER_SIZE, 959 &cap_count, 960 ixgbe_aci_opc_list_func_caps); 961 if (!err) 962 ixgbe_parse_func_caps(hw, func_caps, cbuf, cap_count); 963 964 kfree(cbuf); 965 966 return 0; 967 } 968 969 /** 970 * ixgbe_get_caps - get info about the HW 971 * @hw: pointer to the hardware structure 972 * 973 * Retrieve both device and function capabilities. 974 * 975 * Return: the exit code of the operation. 976 */ 977 int ixgbe_get_caps(struct ixgbe_hw *hw) 978 { 979 int err; 980 981 err = ixgbe_discover_dev_caps(hw, &hw->dev_caps); 982 if (err) 983 return err; 984 985 return ixgbe_discover_func_caps(hw, &hw->func_caps); 986 } 987 988 /** 989 * ixgbe_aci_disable_rxen - disable RX 990 * @hw: pointer to the HW struct 991 * 992 * Request a safe disable of Receive Enable using ACI command (0x000C). 993 * 994 * Return: the exit code of the operation. 995 */ 996 int ixgbe_aci_disable_rxen(struct ixgbe_hw *hw) 997 { 998 struct ixgbe_aci_cmd_disable_rxen *cmd; 999 struct libie_aq_desc desc; 1000 1001 cmd = libie_aq_raw(&desc); 1002 1003 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_disable_rxen); 1004 1005 cmd->lport_num = hw->bus.func; 1006 1007 return ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 1008 } 1009 1010 /** 1011 * ixgbe_aci_get_phy_caps - returns PHY capabilities 1012 * @hw: pointer to the HW struct 1013 * @qual_mods: report qualified modules 1014 * @report_mode: report mode capabilities 1015 * @pcaps: structure for PHY capabilities to be filled 1016 * 1017 * Returns the various PHY capabilities supported on the Port 1018 * using ACI command (0x0600). 1019 * 1020 * Return: the exit code of the operation. 1021 */ 1022 int ixgbe_aci_get_phy_caps(struct ixgbe_hw *hw, bool qual_mods, u8 report_mode, 1023 struct ixgbe_aci_cmd_get_phy_caps_data *pcaps) 1024 { 1025 struct ixgbe_aci_cmd_get_phy_caps *cmd; 1026 u16 pcaps_size = sizeof(*pcaps); 1027 struct libie_aq_desc desc; 1028 int err; 1029 1030 cmd = libie_aq_raw(&desc); 1031 1032 if (!pcaps || (report_mode & ~IXGBE_ACI_REPORT_MODE_M)) 1033 return -EINVAL; 1034 1035 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_phy_caps); 1036 1037 if (qual_mods) 1038 cmd->param0 |= cpu_to_le16(IXGBE_ACI_GET_PHY_RQM); 1039 1040 cmd->param0 |= cpu_to_le16(report_mode); 1041 err = ixgbe_aci_send_cmd(hw, &desc, pcaps, pcaps_size); 1042 if (!err && report_mode == IXGBE_ACI_REPORT_TOPO_CAP_MEDIA) { 1043 hw->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 1044 hw->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 1045 memcpy(hw->link.link_info.module_type, &pcaps->module_type, 1046 sizeof(hw->link.link_info.module_type)); 1047 } 1048 1049 return err; 1050 } 1051 1052 /** 1053 * ixgbe_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 1054 * @caps: PHY ability structure to copy data from 1055 * @cfg: PHY configuration structure to copy data to 1056 * 1057 * Helper function to copy data from PHY capabilities data structure 1058 * to PHY configuration data structure 1059 */ 1060 void ixgbe_copy_phy_caps_to_cfg(struct ixgbe_aci_cmd_get_phy_caps_data *caps, 1061 struct ixgbe_aci_cmd_set_phy_cfg_data *cfg) 1062 { 1063 if (!caps || !cfg) 1064 return; 1065 1066 memset(cfg, 0, sizeof(*cfg)); 1067 cfg->phy_type_low = caps->phy_type_low; 1068 cfg->phy_type_high = caps->phy_type_high; 1069 cfg->caps = caps->caps; 1070 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 1071 cfg->eee_cap = caps->eee_cap; 1072 cfg->eeer_value = caps->eeer_value; 1073 cfg->link_fec_opt = caps->link_fec_options; 1074 cfg->module_compliance_enforcement = 1075 caps->module_compliance_enforcement; 1076 } 1077 1078 /** 1079 * ixgbe_aci_set_phy_cfg - set PHY configuration 1080 * @hw: pointer to the HW struct 1081 * @cfg: structure with PHY configuration data to be set 1082 * 1083 * Set the various PHY configuration parameters supported on the Port 1084 * using ACI command (0x0601). 1085 * One or more of the Set PHY config parameters may be ignored in an MFP 1086 * mode as the PF may not have the privilege to set some of the PHY Config 1087 * parameters. 1088 * 1089 * Return: the exit code of the operation. 1090 */ 1091 int ixgbe_aci_set_phy_cfg(struct ixgbe_hw *hw, 1092 struct ixgbe_aci_cmd_set_phy_cfg_data *cfg) 1093 { 1094 struct ixgbe_aci_cmd_set_phy_cfg *cmd; 1095 struct libie_aq_desc desc; 1096 int err; 1097 1098 if (!cfg) 1099 return -EINVAL; 1100 1101 cmd = libie_aq_raw(&desc); 1102 /* Ensure that only valid bits of cfg->caps can be turned on. */ 1103 cfg->caps &= IXGBE_ACI_PHY_ENA_VALID_MASK; 1104 1105 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_set_phy_cfg); 1106 cmd->lport_num = hw->bus.func; 1107 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 1108 1109 err = ixgbe_aci_send_cmd(hw, &desc, cfg, sizeof(*cfg)); 1110 if (!err) 1111 hw->phy.curr_user_phy_cfg = *cfg; 1112 1113 return err; 1114 } 1115 1116 /** 1117 * ixgbe_aci_set_link_restart_an - set up link and restart AN 1118 * @hw: pointer to the HW struct 1119 * @ena_link: if true: enable link, if false: disable link 1120 * 1121 * Function sets up the link and restarts the Auto-Negotiation over the link. 1122 * 1123 * Return: the exit code of the operation. 1124 */ 1125 int ixgbe_aci_set_link_restart_an(struct ixgbe_hw *hw, bool ena_link) 1126 { 1127 struct ixgbe_aci_cmd_restart_an *cmd; 1128 struct libie_aq_desc desc; 1129 1130 cmd = libie_aq_raw(&desc); 1131 1132 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_restart_an); 1133 1134 cmd->cmd_flags = IXGBE_ACI_RESTART_AN_LINK_RESTART; 1135 cmd->lport_num = hw->bus.func; 1136 if (ena_link) 1137 cmd->cmd_flags |= IXGBE_ACI_RESTART_AN_LINK_ENABLE; 1138 else 1139 cmd->cmd_flags &= ~IXGBE_ACI_RESTART_AN_LINK_ENABLE; 1140 1141 return ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 1142 } 1143 1144 /** 1145 * ixgbe_is_media_cage_present - check if media cage is present 1146 * @hw: pointer to the HW struct 1147 * 1148 * Identify presence of media cage using the ACI command (0x06E0). 1149 * 1150 * Return: true if media cage is present, else false. If no cage, then 1151 * media type is backplane or BASE-T. 1152 */ 1153 static bool ixgbe_is_media_cage_present(struct ixgbe_hw *hw) 1154 { 1155 struct ixgbe_aci_cmd_get_link_topo *cmd; 1156 struct libie_aq_desc desc; 1157 1158 cmd = libie_aq_raw(&desc); 1159 1160 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_link_topo); 1161 1162 cmd->addr.topo_params.node_type_ctx = 1163 FIELD_PREP(IXGBE_ACI_LINK_TOPO_NODE_CTX_M, 1164 IXGBE_ACI_LINK_TOPO_NODE_CTX_PORT); 1165 1166 /* Set node type. */ 1167 cmd->addr.topo_params.node_type_ctx |= 1168 FIELD_PREP(IXGBE_ACI_LINK_TOPO_NODE_TYPE_M, 1169 IXGBE_ACI_LINK_TOPO_NODE_TYPE_CAGE); 1170 1171 /* Node type cage can be used to determine if cage is present. If AQC 1172 * returns error (ENOENT), then no cage present. If no cage present then 1173 * connection type is backplane or BASE-T. 1174 */ 1175 return !ixgbe_aci_get_netlist_node(hw, cmd, NULL, NULL); 1176 } 1177 1178 /** 1179 * ixgbe_get_media_type_from_phy_type - Gets media type based on phy type 1180 * @hw: pointer to the HW struct 1181 * 1182 * Try to identify the media type based on the phy type. 1183 * If more than one media type, the ixgbe_media_type_unknown is returned. 1184 * First, phy_type_low is checked, then phy_type_high. 1185 * If none are identified, the ixgbe_media_type_unknown is returned 1186 * 1187 * Return: type of a media based on phy type in form of enum. 1188 */ 1189 static enum ixgbe_media_type 1190 ixgbe_get_media_type_from_phy_type(struct ixgbe_hw *hw) 1191 { 1192 struct ixgbe_link_status *hw_link_info; 1193 1194 if (!hw) 1195 return ixgbe_media_type_unknown; 1196 1197 hw_link_info = &hw->link.link_info; 1198 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 1199 /* If more than one media type is selected, report unknown */ 1200 return ixgbe_media_type_unknown; 1201 1202 if (hw_link_info->phy_type_low) { 1203 /* 1G SGMII is a special case where some DA cable PHYs 1204 * may show this as an option when it really shouldn't 1205 * be since SGMII is meant to be between a MAC and a PHY 1206 * in a backplane. Try to detect this case and handle it 1207 */ 1208 if (hw_link_info->phy_type_low == IXGBE_PHY_TYPE_LOW_1G_SGMII && 1209 (hw_link_info->module_type[IXGBE_ACI_MOD_TYPE_IDENT] == 1210 IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 1211 hw_link_info->module_type[IXGBE_ACI_MOD_TYPE_IDENT] == 1212 IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 1213 return ixgbe_media_type_da; 1214 1215 switch (hw_link_info->phy_type_low) { 1216 case IXGBE_PHY_TYPE_LOW_1000BASE_SX: 1217 case IXGBE_PHY_TYPE_LOW_1000BASE_LX: 1218 case IXGBE_PHY_TYPE_LOW_10GBASE_SR: 1219 case IXGBE_PHY_TYPE_LOW_10GBASE_LR: 1220 case IXGBE_PHY_TYPE_LOW_25GBASE_SR: 1221 case IXGBE_PHY_TYPE_LOW_25GBASE_LR: 1222 return ixgbe_media_type_fiber; 1223 case IXGBE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 1224 case IXGBE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 1225 return ixgbe_media_type_fiber; 1226 case IXGBE_PHY_TYPE_LOW_100BASE_TX: 1227 case IXGBE_PHY_TYPE_LOW_1000BASE_T: 1228 case IXGBE_PHY_TYPE_LOW_2500BASE_T: 1229 case IXGBE_PHY_TYPE_LOW_5GBASE_T: 1230 case IXGBE_PHY_TYPE_LOW_10GBASE_T: 1231 case IXGBE_PHY_TYPE_LOW_25GBASE_T: 1232 return ixgbe_media_type_copper; 1233 case IXGBE_PHY_TYPE_LOW_10G_SFI_DA: 1234 case IXGBE_PHY_TYPE_LOW_25GBASE_CR: 1235 case IXGBE_PHY_TYPE_LOW_25GBASE_CR_S: 1236 case IXGBE_PHY_TYPE_LOW_25GBASE_CR1: 1237 return ixgbe_media_type_da; 1238 case IXGBE_PHY_TYPE_LOW_25G_AUI_C2C: 1239 if (ixgbe_is_media_cage_present(hw)) 1240 return ixgbe_media_type_aui; 1241 fallthrough; 1242 case IXGBE_PHY_TYPE_LOW_1000BASE_KX: 1243 case IXGBE_PHY_TYPE_LOW_2500BASE_KX: 1244 case IXGBE_PHY_TYPE_LOW_2500BASE_X: 1245 case IXGBE_PHY_TYPE_LOW_5GBASE_KR: 1246 case IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1: 1247 case IXGBE_PHY_TYPE_LOW_10G_SFI_C2C: 1248 case IXGBE_PHY_TYPE_LOW_25GBASE_KR: 1249 case IXGBE_PHY_TYPE_LOW_25GBASE_KR1: 1250 case IXGBE_PHY_TYPE_LOW_25GBASE_KR_S: 1251 return ixgbe_media_type_backplane; 1252 } 1253 } else { 1254 switch (hw_link_info->phy_type_high) { 1255 case IXGBE_PHY_TYPE_HIGH_10BASE_T: 1256 return ixgbe_media_type_copper; 1257 } 1258 } 1259 return ixgbe_media_type_unknown; 1260 } 1261 1262 /** 1263 * ixgbe_update_link_info - update status of the HW network link 1264 * @hw: pointer to the HW struct 1265 * 1266 * Update the status of the HW network link. 1267 * 1268 * Return: the exit code of the operation. 1269 */ 1270 int ixgbe_update_link_info(struct ixgbe_hw *hw) 1271 { 1272 struct ixgbe_aci_cmd_get_phy_caps_data *pcaps; 1273 struct ixgbe_link_status *li; 1274 int err; 1275 1276 if (!hw) 1277 return -EINVAL; 1278 1279 li = &hw->link.link_info; 1280 1281 err = ixgbe_aci_get_link_info(hw, true, NULL); 1282 if (err) 1283 return err; 1284 1285 if (!(li->link_info & IXGBE_ACI_MEDIA_AVAILABLE)) 1286 return 0; 1287 1288 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 1289 if (!pcaps) 1290 return -ENOMEM; 1291 1292 err = ixgbe_aci_get_phy_caps(hw, false, IXGBE_ACI_REPORT_TOPO_CAP_MEDIA, 1293 pcaps); 1294 1295 if (!err) 1296 memcpy(li->module_type, &pcaps->module_type, 1297 sizeof(li->module_type)); 1298 1299 kfree(pcaps); 1300 1301 return err; 1302 } 1303 1304 /** 1305 * ixgbe_get_link_status - get status of the HW network link 1306 * @hw: pointer to the HW struct 1307 * @link_up: pointer to bool (true/false = linkup/linkdown) 1308 * 1309 * Variable link_up is true if link is up, false if link is down. 1310 * The variable link_up is invalid if status is non zero. As a 1311 * result of this call, link status reporting becomes enabled 1312 * 1313 * Return: the exit code of the operation. 1314 */ 1315 int ixgbe_get_link_status(struct ixgbe_hw *hw, bool *link_up) 1316 { 1317 if (!hw || !link_up) 1318 return -EINVAL; 1319 1320 if (hw->link.get_link_info) { 1321 int err = ixgbe_update_link_info(hw); 1322 1323 if (err) 1324 return err; 1325 } 1326 1327 *link_up = hw->link.link_info.link_info & IXGBE_ACI_LINK_UP; 1328 1329 return 0; 1330 } 1331 1332 /** 1333 * ixgbe_aci_get_link_info - get the link status 1334 * @hw: pointer to the HW struct 1335 * @ena_lse: enable/disable LinkStatusEvent reporting 1336 * @link: pointer to link status structure - optional 1337 * 1338 * Get the current Link Status using ACI command (0x607). 1339 * The current link can be optionally provided to update 1340 * the status. 1341 * 1342 * Return: the link status of the adapter. 1343 */ 1344 int ixgbe_aci_get_link_info(struct ixgbe_hw *hw, bool ena_lse, 1345 struct ixgbe_link_status *link) 1346 { 1347 struct ixgbe_aci_cmd_get_link_status_data link_data = {}; 1348 struct ixgbe_aci_cmd_get_link_status *resp; 1349 struct ixgbe_link_status *li_old, *li; 1350 struct ixgbe_fc_info *hw_fc_info; 1351 struct libie_aq_desc desc; 1352 bool tx_pause, rx_pause; 1353 u8 cmd_flags; 1354 int err; 1355 1356 if (!hw) 1357 return -EINVAL; 1358 1359 li_old = &hw->link.link_info_old; 1360 li = &hw->link.link_info; 1361 hw_fc_info = &hw->fc; 1362 1363 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_link_status); 1364 cmd_flags = (ena_lse) ? IXGBE_ACI_LSE_ENA : IXGBE_ACI_LSE_DIS; 1365 resp = libie_aq_raw(&desc); 1366 resp->cmd_flags = cpu_to_le16(cmd_flags); 1367 resp->lport_num = hw->bus.func; 1368 1369 err = ixgbe_aci_send_cmd(hw, &desc, &link_data, sizeof(link_data)); 1370 if (err) 1371 return err; 1372 1373 /* Save off old link status information. */ 1374 *li_old = *li; 1375 1376 /* Update current link status information. */ 1377 li->link_speed = le16_to_cpu(link_data.link_speed); 1378 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 1379 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 1380 li->link_info = link_data.link_info; 1381 li->link_cfg_err = link_data.link_cfg_err; 1382 li->an_info = link_data.an_info; 1383 li->ext_info = link_data.ext_info; 1384 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 1385 li->fec_info = link_data.cfg & IXGBE_ACI_FEC_MASK; 1386 li->topo_media_conflict = link_data.topo_media_conflict; 1387 li->pacing = link_data.cfg & (IXGBE_ACI_CFG_PACING_M | 1388 IXGBE_ACI_CFG_PACING_TYPE_M); 1389 1390 /* Update fc info. */ 1391 tx_pause = !!(link_data.an_info & IXGBE_ACI_LINK_PAUSE_TX); 1392 rx_pause = !!(link_data.an_info & IXGBE_ACI_LINK_PAUSE_RX); 1393 if (tx_pause && rx_pause) 1394 hw_fc_info->current_mode = ixgbe_fc_full; 1395 else if (tx_pause) 1396 hw_fc_info->current_mode = ixgbe_fc_tx_pause; 1397 else if (rx_pause) 1398 hw_fc_info->current_mode = ixgbe_fc_rx_pause; 1399 else 1400 hw_fc_info->current_mode = ixgbe_fc_none; 1401 1402 li->lse_ena = !!(le16_to_cpu(resp->cmd_flags) & 1403 IXGBE_ACI_LSE_IS_ENABLED); 1404 1405 /* Save link status information. */ 1406 if (link) 1407 *link = *li; 1408 1409 /* Flag cleared so calling functions don't call AQ again. */ 1410 hw->link.get_link_info = false; 1411 1412 return 0; 1413 } 1414 1415 /** 1416 * ixgbe_aci_set_event_mask - set event mask 1417 * @hw: pointer to the HW struct 1418 * @port_num: port number of the physical function 1419 * @mask: event mask to be set 1420 * 1421 * Set the event mask using ACI command (0x0613). 1422 * 1423 * Return: the exit code of the operation. 1424 */ 1425 int ixgbe_aci_set_event_mask(struct ixgbe_hw *hw, u8 port_num, u16 mask) 1426 { 1427 struct ixgbe_aci_cmd_set_event_mask *cmd; 1428 struct libie_aq_desc desc; 1429 1430 cmd = libie_aq_raw(&desc); 1431 1432 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_set_event_mask); 1433 1434 cmd->lport_num = port_num; 1435 1436 cmd->event_mask = cpu_to_le16(mask); 1437 return ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 1438 } 1439 1440 /** 1441 * ixgbe_configure_lse - enable/disable link status events 1442 * @hw: pointer to the HW struct 1443 * @activate: true for enable lse, false otherwise 1444 * @mask: event mask to be set; a set bit means deactivation of the 1445 * corresponding event 1446 * 1447 * Set the event mask and then enable or disable link status events 1448 * 1449 * Return: the exit code of the operation. 1450 */ 1451 int ixgbe_configure_lse(struct ixgbe_hw *hw, bool activate, u16 mask) 1452 { 1453 int err; 1454 1455 err = ixgbe_aci_set_event_mask(hw, (u8)hw->bus.func, mask); 1456 if (err) 1457 return err; 1458 1459 /* Enabling link status events generation by fw. */ 1460 return ixgbe_aci_get_link_info(hw, activate, NULL); 1461 } 1462 1463 /** 1464 * ixgbe_start_hw_e610 - Prepare hardware for Tx/Rx 1465 * @hw: pointer to hardware structure 1466 * 1467 * Get firmware version and start the hardware using the generic 1468 * start_hw() and ixgbe_start_hw_gen2() functions. 1469 * 1470 * Return: the exit code of the operation. 1471 */ 1472 static int ixgbe_start_hw_e610(struct ixgbe_hw *hw) 1473 { 1474 int err; 1475 1476 err = ixgbe_aci_get_fw_ver(hw); 1477 if (err) 1478 return err; 1479 1480 err = ixgbe_start_hw_generic(hw); 1481 if (err) 1482 return err; 1483 1484 ixgbe_start_hw_gen2(hw); 1485 1486 return 0; 1487 } 1488 1489 /** 1490 * ixgbe_aci_set_port_id_led - set LED value for the given port 1491 * @hw: pointer to the HW struct 1492 * @orig_mode: set LED original mode 1493 * 1494 * Set LED value for the given port (0x06E9) 1495 * 1496 * Return: the exit code of the operation. 1497 */ 1498 int ixgbe_aci_set_port_id_led(struct ixgbe_hw *hw, bool orig_mode) 1499 { 1500 struct ixgbe_aci_cmd_set_port_id_led *cmd; 1501 struct libie_aq_desc desc; 1502 1503 cmd = libie_aq_raw(&desc); 1504 1505 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_set_port_id_led); 1506 1507 cmd->lport_num = (u8)hw->bus.func; 1508 cmd->lport_num_valid = IXGBE_ACI_PORT_ID_PORT_NUM_VALID; 1509 1510 if (orig_mode) 1511 cmd->ident_mode = IXGBE_ACI_PORT_IDENT_LED_ORIG; 1512 else 1513 cmd->ident_mode = IXGBE_ACI_PORT_IDENT_LED_BLINK; 1514 1515 return ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 1516 } 1517 1518 /** 1519 * ixgbe_get_media_type_e610 - Gets media type 1520 * @hw: pointer to the HW struct 1521 * 1522 * In order to get the media type, the function gets PHY 1523 * capabilities and later on use them to identify the PHY type 1524 * checking phy_type_high and phy_type_low. 1525 * 1526 * Return: the type of media in form of ixgbe_media_type enum 1527 * or ixgbe_media_type_unknown in case of an error. 1528 */ 1529 enum ixgbe_media_type ixgbe_get_media_type_e610(struct ixgbe_hw *hw) 1530 { 1531 struct ixgbe_aci_cmd_get_phy_caps_data pcaps; 1532 int rc; 1533 1534 rc = ixgbe_update_link_info(hw); 1535 if (rc) 1536 return ixgbe_media_type_unknown; 1537 1538 /* If there is no link but PHY (dongle) is available SW should use 1539 * Get PHY Caps admin command instead of Get Link Status, find most 1540 * significant bit that is set in PHY types reported by the command 1541 * and use it to discover media type. 1542 */ 1543 if (!(hw->link.link_info.link_info & IXGBE_ACI_LINK_UP) && 1544 (hw->link.link_info.link_info & IXGBE_ACI_MEDIA_AVAILABLE)) { 1545 int highest_bit; 1546 1547 /* Get PHY Capabilities */ 1548 rc = ixgbe_aci_get_phy_caps(hw, false, 1549 IXGBE_ACI_REPORT_TOPO_CAP_MEDIA, 1550 &pcaps); 1551 if (rc) 1552 return ixgbe_media_type_unknown; 1553 1554 highest_bit = fls64(le64_to_cpu(pcaps.phy_type_high)); 1555 if (highest_bit) { 1556 hw->link.link_info.phy_type_high = 1557 BIT_ULL(highest_bit - 1); 1558 hw->link.link_info.phy_type_low = 0; 1559 } else { 1560 highest_bit = fls64(le64_to_cpu(pcaps.phy_type_low)); 1561 if (highest_bit) { 1562 hw->link.link_info.phy_type_low = 1563 BIT_ULL(highest_bit - 1); 1564 hw->link.link_info.phy_type_high = 0; 1565 } 1566 } 1567 } 1568 1569 /* Based on link status or search above try to discover media type. */ 1570 hw->phy.media_type = ixgbe_get_media_type_from_phy_type(hw); 1571 1572 return hw->phy.media_type; 1573 } 1574 1575 /** 1576 * ixgbe_setup_link_e610 - Set up link 1577 * @hw: pointer to hardware structure 1578 * @speed: new link speed 1579 * @autoneg_wait: true when waiting for completion is needed 1580 * 1581 * Set up the link with the specified speed. 1582 * 1583 * Return: the exit code of the operation. 1584 */ 1585 int ixgbe_setup_link_e610(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1586 bool autoneg_wait) 1587 { 1588 /* Simply request FW to perform proper PHY setup */ 1589 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 1590 } 1591 1592 /** 1593 * ixgbe_check_link_e610 - Determine link and speed status 1594 * @hw: pointer to hardware structure 1595 * @speed: pointer to link speed 1596 * @link_up: true when link is up 1597 * @link_up_wait_to_complete: bool used to wait for link up or not 1598 * 1599 * Determine if the link is up and the current link speed 1600 * using ACI command (0x0607). 1601 * 1602 * Return: the exit code of the operation. 1603 */ 1604 int ixgbe_check_link_e610(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 1605 bool *link_up, bool link_up_wait_to_complete) 1606 { 1607 int err; 1608 u32 i; 1609 1610 if (!speed || !link_up) 1611 return -EINVAL; 1612 1613 /* Set get_link_info flag to ensure that fresh 1614 * link information will be obtained from FW 1615 * by sending Get Link Status admin command. 1616 */ 1617 hw->link.get_link_info = true; 1618 1619 /* Update link information in adapter context. */ 1620 err = ixgbe_get_link_status(hw, link_up); 1621 if (err) 1622 return err; 1623 1624 /* Wait for link up if it was requested. */ 1625 if (link_up_wait_to_complete && !(*link_up)) { 1626 for (i = 0; i < hw->mac.max_link_up_time; i++) { 1627 msleep(100); 1628 hw->link.get_link_info = true; 1629 err = ixgbe_get_link_status(hw, link_up); 1630 if (err) 1631 return err; 1632 if (*link_up) 1633 break; 1634 } 1635 } 1636 1637 /* Use link information in adapter context updated by the call 1638 * to ixgbe_get_link_status() to determine current link speed. 1639 * Link speed information is valid only when link up was 1640 * reported by FW. 1641 */ 1642 if (*link_up) { 1643 switch (hw->link.link_info.link_speed) { 1644 case IXGBE_ACI_LINK_SPEED_10MB: 1645 *speed = IXGBE_LINK_SPEED_10_FULL; 1646 break; 1647 case IXGBE_ACI_LINK_SPEED_100MB: 1648 *speed = IXGBE_LINK_SPEED_100_FULL; 1649 break; 1650 case IXGBE_ACI_LINK_SPEED_1000MB: 1651 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1652 break; 1653 case IXGBE_ACI_LINK_SPEED_2500MB: 1654 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 1655 break; 1656 case IXGBE_ACI_LINK_SPEED_5GB: 1657 *speed = IXGBE_LINK_SPEED_5GB_FULL; 1658 break; 1659 case IXGBE_ACI_LINK_SPEED_10GB: 1660 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1661 break; 1662 default: 1663 *speed = IXGBE_LINK_SPEED_UNKNOWN; 1664 break; 1665 } 1666 } else { 1667 *speed = IXGBE_LINK_SPEED_UNKNOWN; 1668 } 1669 1670 return 0; 1671 } 1672 1673 /** 1674 * ixgbe_get_link_capabilities_e610 - Determine link capabilities 1675 * @hw: pointer to hardware structure 1676 * @speed: pointer to link speed 1677 * @autoneg: true when autoneg or autotry is enabled 1678 * 1679 * Determine speed and AN parameters of a link. 1680 * 1681 * Return: the exit code of the operation. 1682 */ 1683 int ixgbe_get_link_capabilities_e610(struct ixgbe_hw *hw, 1684 ixgbe_link_speed *speed, 1685 bool *autoneg) 1686 { 1687 if (!speed || !autoneg) 1688 return -EINVAL; 1689 1690 *autoneg = true; 1691 *speed = hw->phy.speeds_supported; 1692 1693 return 0; 1694 } 1695 1696 /** 1697 * ixgbe_cfg_phy_fc - Configure PHY Flow Control (FC) data based on FC mode 1698 * @hw: pointer to hardware structure 1699 * @cfg: PHY configuration data to set FC mode 1700 * @req_mode: FC mode to configure 1701 * 1702 * Configures PHY Flow Control according to the provided configuration. 1703 * 1704 * Return: the exit code of the operation. 1705 */ 1706 int ixgbe_cfg_phy_fc(struct ixgbe_hw *hw, 1707 struct ixgbe_aci_cmd_set_phy_cfg_data *cfg, 1708 enum ixgbe_fc_mode req_mode) 1709 { 1710 u8 pause_mask = 0x0; 1711 1712 if (!cfg) 1713 return -EINVAL; 1714 1715 switch (req_mode) { 1716 case ixgbe_fc_full: 1717 pause_mask |= IXGBE_ACI_PHY_EN_TX_LINK_PAUSE; 1718 pause_mask |= IXGBE_ACI_PHY_EN_RX_LINK_PAUSE; 1719 break; 1720 case ixgbe_fc_rx_pause: 1721 pause_mask |= IXGBE_ACI_PHY_EN_RX_LINK_PAUSE; 1722 break; 1723 case ixgbe_fc_tx_pause: 1724 pause_mask |= IXGBE_ACI_PHY_EN_TX_LINK_PAUSE; 1725 break; 1726 default: 1727 break; 1728 } 1729 1730 /* Clear the old pause settings. */ 1731 cfg->caps &= ~(IXGBE_ACI_PHY_EN_TX_LINK_PAUSE | 1732 IXGBE_ACI_PHY_EN_RX_LINK_PAUSE); 1733 1734 /* Set the new capabilities. */ 1735 cfg->caps |= pause_mask; 1736 1737 return 0; 1738 } 1739 1740 /** 1741 * ixgbe_setup_fc_e610 - Set up flow control 1742 * @hw: pointer to hardware structure 1743 * 1744 * Set up flow control. This has to be done during init time. 1745 * 1746 * Return: the exit code of the operation. 1747 */ 1748 int ixgbe_setup_fc_e610(struct ixgbe_hw *hw) 1749 { 1750 struct ixgbe_aci_cmd_get_phy_caps_data pcaps = {}; 1751 struct ixgbe_aci_cmd_set_phy_cfg_data cfg = {}; 1752 int err; 1753 1754 /* Get the current PHY config */ 1755 err = ixgbe_aci_get_phy_caps(hw, false, 1756 IXGBE_ACI_REPORT_ACTIVE_CFG, &pcaps); 1757 if (err) 1758 return err; 1759 1760 ixgbe_copy_phy_caps_to_cfg(&pcaps, &cfg); 1761 1762 /* Configure the set PHY data */ 1763 err = ixgbe_cfg_phy_fc(hw, &cfg, hw->fc.requested_mode); 1764 if (err) 1765 return err; 1766 1767 /* If the capabilities have changed, then set the new config */ 1768 if (cfg.caps != pcaps.caps) { 1769 cfg.caps |= IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT; 1770 1771 err = ixgbe_aci_set_phy_cfg(hw, &cfg); 1772 if (err) 1773 return err; 1774 } 1775 1776 return err; 1777 } 1778 1779 /** 1780 * ixgbe_fc_autoneg_e610 - Configure flow control 1781 * @hw: pointer to hardware structure 1782 * 1783 * Configure Flow Control. 1784 */ 1785 void ixgbe_fc_autoneg_e610(struct ixgbe_hw *hw) 1786 { 1787 int err; 1788 1789 /* Get current link err. 1790 * Current FC mode will be stored in the hw context. 1791 */ 1792 err = ixgbe_aci_get_link_info(hw, false, NULL); 1793 if (err) 1794 goto no_autoneg; 1795 1796 /* Check if the link is up */ 1797 if (!(hw->link.link_info.link_info & IXGBE_ACI_LINK_UP)) 1798 goto no_autoneg; 1799 1800 /* Check if auto-negotiation has completed */ 1801 if (!(hw->link.link_info.an_info & IXGBE_ACI_AN_COMPLETED)) 1802 goto no_autoneg; 1803 1804 hw->fc.fc_was_autonegged = true; 1805 return; 1806 1807 no_autoneg: 1808 hw->fc.fc_was_autonegged = false; 1809 hw->fc.current_mode = hw->fc.requested_mode; 1810 } 1811 1812 /** 1813 * ixgbe_disable_rx_e610 - Disable RX unit 1814 * @hw: pointer to hardware structure 1815 * 1816 * Disable RX DMA unit on E610 with use of ACI command (0x000C). 1817 * 1818 * Return: the exit code of the operation. 1819 */ 1820 void ixgbe_disable_rx_e610(struct ixgbe_hw *hw) 1821 { 1822 u32 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1823 u32 pfdtxgswc; 1824 int err; 1825 1826 if (!(rxctrl & IXGBE_RXCTRL_RXEN)) 1827 return; 1828 1829 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 1830 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 1831 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 1832 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 1833 hw->mac.set_lben = true; 1834 } else { 1835 hw->mac.set_lben = false; 1836 } 1837 1838 err = ixgbe_aci_disable_rxen(hw); 1839 1840 /* If we fail - disable RX using register write */ 1841 if (err) { 1842 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1843 if (rxctrl & IXGBE_RXCTRL_RXEN) { 1844 rxctrl &= ~IXGBE_RXCTRL_RXEN; 1845 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 1846 } 1847 } 1848 } 1849 1850 /** 1851 * ixgbe_fw_recovery_mode_e610 - Check FW NVM recovery mode 1852 * @hw: pointer to hardware structure 1853 * 1854 * Check FW NVM recovery mode by reading the value of 1855 * the dedicated register. 1856 * 1857 * Return: true if FW is in recovery mode, otherwise false. 1858 */ 1859 static bool ixgbe_fw_recovery_mode_e610(struct ixgbe_hw *hw) 1860 { 1861 u32 fwsm = IXGBE_READ_REG(hw, IXGBE_GL_MNG_FWSM); 1862 1863 return !!(fwsm & IXGBE_GL_MNG_FWSM_RECOVERY_M); 1864 } 1865 1866 /** 1867 * ixgbe_fw_rollback_mode_e610 - Check FW NVM rollback mode 1868 * @hw: pointer to hardware structure 1869 * 1870 * Check FW NVM rollback mode by reading the value of 1871 * the dedicated register. 1872 * 1873 * Return: true if FW is in rollback mode, otherwise false. 1874 */ 1875 static bool ixgbe_fw_rollback_mode_e610(struct ixgbe_hw *hw) 1876 { 1877 u32 fwsm = IXGBE_READ_REG(hw, IXGBE_GL_MNG_FWSM); 1878 1879 return !!(fwsm & IXGBE_GL_MNG_FWSM_ROLLBACK_M); 1880 } 1881 1882 /** 1883 * ixgbe_init_phy_ops_e610 - PHY specific init 1884 * @hw: pointer to hardware structure 1885 * 1886 * Initialize any function pointers that were not able to be 1887 * set during init_shared_code because the PHY type was not known. 1888 * 1889 * Return: the exit code of the operation. 1890 */ 1891 int ixgbe_init_phy_ops_e610(struct ixgbe_hw *hw) 1892 { 1893 struct ixgbe_mac_info *mac = &hw->mac; 1894 struct ixgbe_phy_info *phy = &hw->phy; 1895 1896 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) 1897 phy->ops.set_phy_power = ixgbe_set_phy_power_e610; 1898 else 1899 phy->ops.set_phy_power = NULL; 1900 1901 /* Identify the PHY */ 1902 return phy->ops.identify(hw); 1903 } 1904 1905 /** 1906 * ixgbe_identify_phy_e610 - Identify PHY 1907 * @hw: pointer to hardware structure 1908 * 1909 * Determine PHY type, supported speeds and PHY ID. 1910 * 1911 * Return: the exit code of the operation. 1912 */ 1913 int ixgbe_identify_phy_e610(struct ixgbe_hw *hw) 1914 { 1915 struct ixgbe_aci_cmd_get_phy_caps_data pcaps; 1916 u64 phy_type_low, phy_type_high; 1917 int err; 1918 1919 /* Set PHY type */ 1920 hw->phy.type = ixgbe_phy_fw; 1921 1922 err = ixgbe_aci_get_phy_caps(hw, false, 1923 IXGBE_ACI_REPORT_TOPO_CAP_MEDIA, &pcaps); 1924 if (err) 1925 return err; 1926 1927 if (!(pcaps.module_compliance_enforcement & 1928 IXGBE_ACI_MOD_ENFORCE_STRICT_MODE)) { 1929 /* Handle lenient mode */ 1930 err = ixgbe_aci_get_phy_caps(hw, false, 1931 IXGBE_ACI_REPORT_TOPO_CAP_NO_MEDIA, 1932 &pcaps); 1933 if (err) 1934 return err; 1935 } 1936 1937 /* Determine supported speeds */ 1938 hw->phy.speeds_supported = IXGBE_LINK_SPEED_UNKNOWN; 1939 phy_type_high = le64_to_cpu(pcaps.phy_type_high); 1940 phy_type_low = le64_to_cpu(pcaps.phy_type_low); 1941 1942 if (phy_type_high & IXGBE_PHY_TYPE_HIGH_10BASE_T || 1943 phy_type_high & IXGBE_PHY_TYPE_HIGH_10M_SGMII) 1944 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10_FULL; 1945 if (phy_type_low & IXGBE_PHY_TYPE_LOW_100BASE_TX || 1946 phy_type_low & IXGBE_PHY_TYPE_LOW_100M_SGMII || 1947 phy_type_high & IXGBE_PHY_TYPE_HIGH_100M_USXGMII) 1948 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 1949 if (phy_type_low & IXGBE_PHY_TYPE_LOW_1000BASE_T || 1950 phy_type_low & IXGBE_PHY_TYPE_LOW_1000BASE_SX || 1951 phy_type_low & IXGBE_PHY_TYPE_LOW_1000BASE_LX || 1952 phy_type_low & IXGBE_PHY_TYPE_LOW_1000BASE_KX || 1953 phy_type_low & IXGBE_PHY_TYPE_LOW_1G_SGMII || 1954 phy_type_high & IXGBE_PHY_TYPE_HIGH_1G_USXGMII) 1955 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 1956 if (phy_type_low & IXGBE_PHY_TYPE_LOW_10GBASE_T || 1957 phy_type_low & IXGBE_PHY_TYPE_LOW_10G_SFI_DA || 1958 phy_type_low & IXGBE_PHY_TYPE_LOW_10GBASE_SR || 1959 phy_type_low & IXGBE_PHY_TYPE_LOW_10GBASE_LR || 1960 phy_type_low & IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1 || 1961 phy_type_low & IXGBE_PHY_TYPE_LOW_10G_SFI_AOC_ACC || 1962 phy_type_low & IXGBE_PHY_TYPE_LOW_10G_SFI_C2C || 1963 phy_type_high & IXGBE_PHY_TYPE_HIGH_10G_USXGMII) 1964 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 1965 1966 /* 2.5 and 5 Gbps link speeds must be excluded from the 1967 * auto-negotiation set used during driver initialization due to 1968 * compatibility issues with certain switches. Those issues do not 1969 * exist in case of E610 2.5G SKU device (0x57b1). 1970 */ 1971 if (!hw->phy.autoneg_advertised && 1972 hw->device_id != IXGBE_DEV_ID_E610_2_5G_T) 1973 hw->phy.autoneg_advertised = hw->phy.speeds_supported; 1974 1975 if (phy_type_low & IXGBE_PHY_TYPE_LOW_2500BASE_T || 1976 phy_type_low & IXGBE_PHY_TYPE_LOW_2500BASE_X || 1977 phy_type_low & IXGBE_PHY_TYPE_LOW_2500BASE_KX || 1978 phy_type_high & IXGBE_PHY_TYPE_HIGH_2500M_SGMII || 1979 phy_type_high & IXGBE_PHY_TYPE_HIGH_2500M_USXGMII) 1980 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 1981 1982 if (!hw->phy.autoneg_advertised && 1983 hw->device_id == IXGBE_DEV_ID_E610_2_5G_T) 1984 hw->phy.autoneg_advertised = hw->phy.speeds_supported; 1985 1986 if (phy_type_low & IXGBE_PHY_TYPE_LOW_5GBASE_T || 1987 phy_type_low & IXGBE_PHY_TYPE_LOW_5GBASE_KR || 1988 phy_type_high & IXGBE_PHY_TYPE_HIGH_5G_USXGMII) 1989 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 1990 1991 /* Set PHY ID */ 1992 memcpy(&hw->phy.id, pcaps.phy_id_oui, sizeof(u32)); 1993 1994 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_10_FULL | 1995 IXGBE_LINK_SPEED_100_FULL | 1996 IXGBE_LINK_SPEED_1GB_FULL; 1997 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported; 1998 1999 return 0; 2000 } 2001 2002 /** 2003 * ixgbe_identify_module_e610 - Identify SFP module type 2004 * @hw: pointer to hardware structure 2005 * 2006 * Identify the SFP module type. 2007 * 2008 * Return: the exit code of the operation. 2009 */ 2010 int ixgbe_identify_module_e610(struct ixgbe_hw *hw) 2011 { 2012 bool media_available; 2013 u8 module_type; 2014 int err; 2015 2016 err = ixgbe_update_link_info(hw); 2017 if (err) 2018 return err; 2019 2020 media_available = 2021 (hw->link.link_info.link_info & IXGBE_ACI_MEDIA_AVAILABLE); 2022 2023 if (media_available) { 2024 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 2025 2026 /* Get module type from hw context updated by 2027 * ixgbe_update_link_info() 2028 */ 2029 module_type = hw->link.link_info.module_type[IXGBE_ACI_MOD_TYPE_IDENT]; 2030 2031 if ((module_type & IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE) || 2032 (module_type & IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE)) { 2033 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 2034 } else if (module_type & IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_SR) { 2035 hw->phy.sfp_type = ixgbe_sfp_type_sr; 2036 } else if ((module_type & IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_LR) || 2037 (module_type & IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_LRM)) { 2038 hw->phy.sfp_type = ixgbe_sfp_type_lr; 2039 } 2040 } else { 2041 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 2042 return -ENOENT; 2043 } 2044 2045 return 0; 2046 } 2047 2048 /** 2049 * ixgbe_setup_phy_link_e610 - Sets up firmware-controlled PHYs 2050 * @hw: pointer to hardware structure 2051 * 2052 * Set the parameters for the firmware-controlled PHYs. 2053 * 2054 * Return: the exit code of the operation. 2055 */ 2056 int ixgbe_setup_phy_link_e610(struct ixgbe_hw *hw) 2057 { 2058 struct ixgbe_aci_cmd_get_phy_caps_data pcaps; 2059 struct ixgbe_aci_cmd_set_phy_cfg_data pcfg; 2060 u8 rmode = IXGBE_ACI_REPORT_TOPO_CAP_MEDIA; 2061 u64 sup_phy_type_low, sup_phy_type_high; 2062 u64 phy_type_low = 0, phy_type_high = 0; 2063 int err; 2064 2065 err = ixgbe_aci_get_link_info(hw, false, NULL); 2066 if (err) 2067 return err; 2068 2069 /* If media is not available get default config. */ 2070 if (!(hw->link.link_info.link_info & IXGBE_ACI_MEDIA_AVAILABLE)) 2071 rmode = IXGBE_ACI_REPORT_DFLT_CFG; 2072 2073 err = ixgbe_aci_get_phy_caps(hw, false, rmode, &pcaps); 2074 if (err) 2075 return err; 2076 2077 sup_phy_type_low = le64_to_cpu(pcaps.phy_type_low); 2078 sup_phy_type_high = le64_to_cpu(pcaps.phy_type_high); 2079 2080 /* Get Active configuration to avoid unintended changes. */ 2081 err = ixgbe_aci_get_phy_caps(hw, false, IXGBE_ACI_REPORT_ACTIVE_CFG, 2082 &pcaps); 2083 if (err) 2084 return err; 2085 2086 ixgbe_copy_phy_caps_to_cfg(&pcaps, &pcfg); 2087 2088 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL) { 2089 phy_type_high |= IXGBE_PHY_TYPE_HIGH_10BASE_T; 2090 phy_type_high |= IXGBE_PHY_TYPE_HIGH_10M_SGMII; 2091 } 2092 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) { 2093 phy_type_low |= IXGBE_PHY_TYPE_LOW_100BASE_TX; 2094 phy_type_low |= IXGBE_PHY_TYPE_LOW_100M_SGMII; 2095 phy_type_high |= IXGBE_PHY_TYPE_HIGH_100M_USXGMII; 2096 } 2097 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) { 2098 phy_type_low |= IXGBE_PHY_TYPE_LOW_1000BASE_T; 2099 phy_type_low |= IXGBE_PHY_TYPE_LOW_1000BASE_SX; 2100 phy_type_low |= IXGBE_PHY_TYPE_LOW_1000BASE_LX; 2101 phy_type_low |= IXGBE_PHY_TYPE_LOW_1000BASE_KX; 2102 phy_type_low |= IXGBE_PHY_TYPE_LOW_1G_SGMII; 2103 phy_type_high |= IXGBE_PHY_TYPE_HIGH_1G_USXGMII; 2104 } 2105 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL) { 2106 phy_type_low |= IXGBE_PHY_TYPE_LOW_2500BASE_T; 2107 phy_type_low |= IXGBE_PHY_TYPE_LOW_2500BASE_X; 2108 phy_type_low |= IXGBE_PHY_TYPE_LOW_2500BASE_KX; 2109 phy_type_high |= IXGBE_PHY_TYPE_HIGH_2500M_SGMII; 2110 phy_type_high |= IXGBE_PHY_TYPE_HIGH_2500M_USXGMII; 2111 } 2112 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) { 2113 phy_type_low |= IXGBE_PHY_TYPE_LOW_5GBASE_T; 2114 phy_type_low |= IXGBE_PHY_TYPE_LOW_5GBASE_KR; 2115 phy_type_high |= IXGBE_PHY_TYPE_HIGH_5G_USXGMII; 2116 } 2117 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) { 2118 phy_type_low |= IXGBE_PHY_TYPE_LOW_10GBASE_T; 2119 phy_type_low |= IXGBE_PHY_TYPE_LOW_10G_SFI_DA; 2120 phy_type_low |= IXGBE_PHY_TYPE_LOW_10GBASE_SR; 2121 phy_type_low |= IXGBE_PHY_TYPE_LOW_10GBASE_LR; 2122 phy_type_low |= IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1; 2123 phy_type_low |= IXGBE_PHY_TYPE_LOW_10G_SFI_AOC_ACC; 2124 phy_type_low |= IXGBE_PHY_TYPE_LOW_10G_SFI_C2C; 2125 phy_type_high |= IXGBE_PHY_TYPE_HIGH_10G_USXGMII; 2126 } 2127 2128 /* Mask the set values to avoid requesting unsupported link types. */ 2129 phy_type_low &= sup_phy_type_low; 2130 pcfg.phy_type_low = cpu_to_le64(phy_type_low); 2131 phy_type_high &= sup_phy_type_high; 2132 pcfg.phy_type_high = cpu_to_le64(phy_type_high); 2133 2134 if (pcfg.phy_type_high != pcaps.phy_type_high || 2135 pcfg.phy_type_low != pcaps.phy_type_low || 2136 pcfg.caps != pcaps.caps) { 2137 pcfg.caps |= IXGBE_ACI_PHY_ENA_LINK; 2138 pcfg.caps |= IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT; 2139 2140 err = ixgbe_aci_set_phy_cfg(hw, &pcfg); 2141 if (err) 2142 return err; 2143 } 2144 2145 return 0; 2146 } 2147 2148 /** 2149 * ixgbe_set_phy_power_e610 - Control power for copper PHY 2150 * @hw: pointer to hardware structure 2151 * @on: true for on, false for off 2152 * 2153 * Set the power on/off of the PHY 2154 * by getting its capabilities and setting the appropriate 2155 * configuration parameters. 2156 * 2157 * Return: the exit code of the operation. 2158 */ 2159 int ixgbe_set_phy_power_e610(struct ixgbe_hw *hw, bool on) 2160 { 2161 struct ixgbe_aci_cmd_get_phy_caps_data phy_caps = {}; 2162 struct ixgbe_aci_cmd_set_phy_cfg_data phy_cfg = {}; 2163 int err; 2164 2165 err = ixgbe_aci_get_phy_caps(hw, false, 2166 IXGBE_ACI_REPORT_ACTIVE_CFG, 2167 &phy_caps); 2168 if (err) 2169 return err; 2170 2171 ixgbe_copy_phy_caps_to_cfg(&phy_caps, &phy_cfg); 2172 2173 if (on) 2174 phy_cfg.caps &= ~IXGBE_ACI_PHY_ENA_LOW_POWER; 2175 else 2176 phy_cfg.caps |= IXGBE_ACI_PHY_ENA_LOW_POWER; 2177 2178 /* PHY is already in requested power mode. */ 2179 if (phy_caps.caps == phy_cfg.caps) 2180 return 0; 2181 2182 phy_cfg.caps |= IXGBE_ACI_PHY_ENA_LINK; 2183 phy_cfg.caps |= IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT; 2184 2185 return ixgbe_aci_set_phy_cfg(hw, &phy_cfg); 2186 } 2187 2188 /** 2189 * ixgbe_enter_lplu_e610 - Transition to low power states 2190 * @hw: pointer to hardware structure 2191 * 2192 * Configures Low Power Link Up on transition to low power states 2193 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the 2194 * X557 PHY immediately prior to entering LPLU. 2195 * 2196 * Return: the exit code of the operation. 2197 */ 2198 int ixgbe_enter_lplu_e610(struct ixgbe_hw *hw) 2199 { 2200 struct ixgbe_aci_cmd_get_phy_caps_data phy_caps = {}; 2201 struct ixgbe_aci_cmd_set_phy_cfg_data phy_cfg = {}; 2202 int err; 2203 2204 err = ixgbe_aci_get_phy_caps(hw, false, 2205 IXGBE_ACI_REPORT_ACTIVE_CFG, 2206 &phy_caps); 2207 if (err) 2208 return err; 2209 2210 ixgbe_copy_phy_caps_to_cfg(&phy_caps, &phy_cfg); 2211 2212 phy_cfg.low_power_ctrl_an |= IXGBE_ACI_PHY_EN_D3COLD_LOW_POWER_AUTONEG; 2213 2214 return ixgbe_aci_set_phy_cfg(hw, &phy_cfg); 2215 } 2216 2217 /** 2218 * ixgbe_init_eeprom_params_e610 - Initialize EEPROM params 2219 * @hw: pointer to hardware structure 2220 * 2221 * Initialize the EEPROM parameters ixgbe_eeprom_info within the ixgbe_hw 2222 * struct in order to set up EEPROM access. 2223 * 2224 * Return: the operation exit code. 2225 */ 2226 int ixgbe_init_eeprom_params_e610(struct ixgbe_hw *hw) 2227 { 2228 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2229 u32 gens_stat; 2230 u8 sr_size; 2231 2232 if (eeprom->type != ixgbe_eeprom_uninitialized) 2233 return 0; 2234 2235 eeprom->type = ixgbe_flash; 2236 2237 gens_stat = IXGBE_READ_REG(hw, GLNVM_GENS); 2238 sr_size = FIELD_GET(GLNVM_GENS_SR_SIZE_M, gens_stat); 2239 2240 /* Switching to words (sr_size contains power of 2). */ 2241 eeprom->word_size = BIT(sr_size) * IXGBE_SR_WORDS_IN_1KB; 2242 2243 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", eeprom->type, 2244 eeprom->word_size); 2245 2246 return 0; 2247 } 2248 2249 /** 2250 * ixgbe_aci_get_netlist_node - get a node handle 2251 * @hw: pointer to the hw struct 2252 * @cmd: get_link_topo AQ structure 2253 * @node_part_number: output node part number if node found 2254 * @node_handle: output node handle parameter if node found 2255 * 2256 * Get the netlist node and assigns it to 2257 * the provided handle using ACI command (0x06E0). 2258 * 2259 * Return: the exit code of the operation. 2260 */ 2261 int ixgbe_aci_get_netlist_node(struct ixgbe_hw *hw, 2262 struct ixgbe_aci_cmd_get_link_topo *cmd, 2263 u8 *node_part_number, u16 *node_handle) 2264 { 2265 struct ixgbe_aci_cmd_get_link_topo *resp; 2266 struct libie_aq_desc desc; 2267 2268 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_link_topo); 2269 resp = libie_aq_raw(&desc); 2270 *resp = *cmd; 2271 2272 if (ixgbe_aci_send_cmd(hw, &desc, NULL, 0)) 2273 return -EOPNOTSUPP; 2274 2275 if (node_handle) 2276 *node_handle = le16_to_cpu(resp->addr.handle); 2277 if (node_part_number) 2278 *node_part_number = resp->node_part_num; 2279 2280 return 0; 2281 } 2282 2283 /** 2284 * ixgbe_acquire_nvm - Generic request for acquiring the NVM ownership 2285 * @hw: pointer to the HW structure 2286 * @access: NVM access type (read or write) 2287 * 2288 * Request NVM ownership. 2289 * 2290 * Return: the exit code of the operation. 2291 */ 2292 int ixgbe_acquire_nvm(struct ixgbe_hw *hw, enum libie_aq_res_access_type access) 2293 { 2294 u32 fla; 2295 2296 /* Skip if we are in blank NVM programming mode */ 2297 fla = IXGBE_READ_REG(hw, IXGBE_GLNVM_FLA); 2298 if ((fla & IXGBE_GLNVM_FLA_LOCKED_M) == 0) 2299 return 0; 2300 2301 return ixgbe_acquire_res(hw, LIBIE_AQC_RES_ID_NVM, access, 2302 IXGBE_NVM_TIMEOUT); 2303 } 2304 2305 /** 2306 * ixgbe_release_nvm - Generic request for releasing the NVM ownership 2307 * @hw: pointer to the HW structure 2308 * 2309 * Release NVM ownership. 2310 */ 2311 void ixgbe_release_nvm(struct ixgbe_hw *hw) 2312 { 2313 u32 fla; 2314 2315 /* Skip if we are in blank NVM programming mode */ 2316 fla = IXGBE_READ_REG(hw, IXGBE_GLNVM_FLA); 2317 if ((fla & IXGBE_GLNVM_FLA_LOCKED_M) == 0) 2318 return; 2319 2320 ixgbe_release_res(hw, LIBIE_AQC_RES_ID_NVM); 2321 } 2322 2323 /** 2324 * ixgbe_aci_read_nvm - read NVM 2325 * @hw: pointer to the HW struct 2326 * @module_typeid: module pointer location in words from the NVM beginning 2327 * @offset: byte offset from the module beginning 2328 * @length: length of the section to be read (in bytes from the offset) 2329 * @data: command buffer (size [bytes] = length) 2330 * @last_command: tells if this is the last command in a series 2331 * @read_shadow_ram: tell if this is a shadow RAM read 2332 * 2333 * Read the NVM using ACI command (0x0701). 2334 * 2335 * Return: the exit code of the operation. 2336 */ 2337 int ixgbe_aci_read_nvm(struct ixgbe_hw *hw, u16 module_typeid, u32 offset, 2338 u16 length, void *data, bool last_command, 2339 bool read_shadow_ram) 2340 { 2341 struct ixgbe_aci_cmd_nvm *cmd; 2342 struct libie_aq_desc desc; 2343 2344 if (offset > IXGBE_ACI_NVM_MAX_OFFSET) 2345 return -EINVAL; 2346 2347 cmd = libie_aq_raw(&desc); 2348 2349 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_read); 2350 2351 if (!read_shadow_ram && module_typeid == IXGBE_ACI_NVM_START_POINT) 2352 cmd->cmd_flags |= IXGBE_ACI_NVM_FLASH_ONLY; 2353 2354 /* If this is the last command in a series, set the proper flag. */ 2355 if (last_command) 2356 cmd->cmd_flags |= IXGBE_ACI_NVM_LAST_CMD; 2357 cmd->module_typeid = cpu_to_le16(module_typeid); 2358 cmd->offset_low = cpu_to_le16(offset & 0xFFFF); 2359 cmd->offset_high = (offset >> 16) & 0xFF; 2360 cmd->length = cpu_to_le16(length); 2361 2362 return ixgbe_aci_send_cmd(hw, &desc, data, length); 2363 } 2364 2365 /** 2366 * ixgbe_aci_erase_nvm - erase NVM sector 2367 * @hw: pointer to the HW struct 2368 * @module_typeid: module pointer location in words from the NVM beginning 2369 * 2370 * Erase the NVM sector using the ACI command (0x0702). 2371 * 2372 * Return: the exit code of the operation. 2373 */ 2374 int ixgbe_aci_erase_nvm(struct ixgbe_hw *hw, u16 module_typeid) 2375 { 2376 struct ixgbe_aci_cmd_nvm *cmd; 2377 struct libie_aq_desc desc; 2378 __le16 len; 2379 int err; 2380 2381 /* Read a length value from SR, so module_typeid is equal to 0, 2382 * calculate offset where module size is placed from bytes to words 2383 * set last command and read from SR values to true. 2384 */ 2385 err = ixgbe_aci_read_nvm(hw, 0, 2 * module_typeid + 2, 2, &len, true, 2386 true); 2387 if (err) 2388 return err; 2389 2390 cmd = libie_aq_raw(&desc); 2391 2392 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_erase); 2393 2394 cmd->module_typeid = cpu_to_le16(module_typeid); 2395 cmd->length = len; 2396 cmd->offset_low = 0; 2397 cmd->offset_high = 0; 2398 2399 return ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 2400 } 2401 2402 /** 2403 * ixgbe_aci_update_nvm - update NVM 2404 * @hw: pointer to the HW struct 2405 * @module_typeid: module pointer location in words from the NVM beginning 2406 * @offset: byte offset from the module beginning 2407 * @length: length of the section to be written (in bytes from the offset) 2408 * @data: command buffer (size [bytes] = length) 2409 * @last_command: tells if this is the last command in a series 2410 * @command_flags: command parameters 2411 * 2412 * Update the NVM using the ACI command (0x0703). 2413 * 2414 * Return: the exit code of the operation. 2415 */ 2416 int ixgbe_aci_update_nvm(struct ixgbe_hw *hw, u16 module_typeid, 2417 u32 offset, u16 length, void *data, 2418 bool last_command, u8 command_flags) 2419 { 2420 struct ixgbe_aci_cmd_nvm *cmd; 2421 struct libie_aq_desc desc; 2422 2423 cmd = libie_aq_raw(&desc); 2424 2425 /* In offset the highest byte must be zeroed. */ 2426 if (offset & 0xFF000000) 2427 return -EINVAL; 2428 2429 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_write); 2430 2431 cmd->cmd_flags |= command_flags; 2432 2433 /* If this is the last command in a series, set the proper flag. */ 2434 if (last_command) 2435 cmd->cmd_flags |= IXGBE_ACI_NVM_LAST_CMD; 2436 cmd->module_typeid = cpu_to_le16(module_typeid); 2437 cmd->offset_low = cpu_to_le16(offset & 0xFFFF); 2438 cmd->offset_high = FIELD_GET(IXGBE_ACI_NVM_OFFSET_HI_U_MASK, offset); 2439 cmd->length = cpu_to_le16(length); 2440 2441 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2442 2443 return ixgbe_aci_send_cmd(hw, &desc, data, length); 2444 } 2445 2446 /** 2447 * ixgbe_nvm_write_activate - NVM activate write 2448 * @hw: pointer to the HW struct 2449 * @cmd_flags: flags for write activate command 2450 * @response_flags: response indicators from firmware 2451 * 2452 * Update the control word with the required banks' validity bits 2453 * and dumps the Shadow RAM to flash using ACI command (0x0707). 2454 * 2455 * cmd_flags controls which banks to activate, the preservation level to use 2456 * when activating the NVM bank, and whether an EMP reset is required for 2457 * activation. 2458 * 2459 * Note that the 16bit cmd_flags value is split between two separate 1 byte 2460 * flag values in the descriptor. 2461 * 2462 * On successful return of the firmware command, the response_flags variable 2463 * is updated with the flags reported by firmware indicating certain status, 2464 * such as whether EMP reset is enabled. 2465 * 2466 * Return: the exit code of the operation. 2467 */ 2468 int ixgbe_nvm_write_activate(struct ixgbe_hw *hw, u16 cmd_flags, 2469 u8 *response_flags) 2470 { 2471 struct ixgbe_aci_cmd_nvm *cmd; 2472 struct libie_aq_desc desc; 2473 s32 err; 2474 2475 cmd = libie_aq_raw(&desc); 2476 ixgbe_fill_dflt_direct_cmd_desc(&desc, 2477 ixgbe_aci_opc_nvm_write_activate); 2478 2479 cmd->cmd_flags = (u8)(cmd_flags & 0xFF); 2480 cmd->offset_high = (u8)FIELD_GET(IXGBE_ACI_NVM_OFFSET_HI_A_MASK, 2481 cmd_flags); 2482 2483 err = ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 2484 if (!err && response_flags) 2485 *response_flags = cmd->cmd_flags; 2486 2487 return err; 2488 } 2489 2490 /** 2491 * ixgbe_nvm_validate_checksum - validate checksum 2492 * @hw: pointer to the HW struct 2493 * 2494 * Verify NVM PFA checksum validity using ACI command (0x0706). 2495 * If the checksum verification failed, IXGBE_ERR_NVM_CHECKSUM is returned. 2496 * The function acquires and then releases the NVM ownership. 2497 * 2498 * Return: the exit code of the operation. 2499 */ 2500 int ixgbe_nvm_validate_checksum(struct ixgbe_hw *hw) 2501 { 2502 struct ixgbe_aci_cmd_nvm_checksum *cmd; 2503 struct libie_aq_desc desc; 2504 int err; 2505 2506 err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ); 2507 if (err) 2508 return err; 2509 2510 cmd = libie_aq_raw(&desc); 2511 2512 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_checksum); 2513 cmd->flags = IXGBE_ACI_NVM_CHECKSUM_VERIFY; 2514 2515 err = ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 2516 2517 ixgbe_release_nvm(hw); 2518 2519 if (!err && cmd->checksum != 2520 cpu_to_le16(IXGBE_ACI_NVM_CHECKSUM_CORRECT)) { 2521 struct ixgbe_adapter *adapter = container_of(hw, struct ixgbe_adapter, 2522 hw); 2523 2524 err = -EIO; 2525 netdev_err(adapter->netdev, "Invalid Shadow Ram checksum"); 2526 } 2527 2528 return err; 2529 } 2530 2531 /** 2532 * ixgbe_discover_flash_size - Discover the available flash size 2533 * @hw: pointer to the HW struct 2534 * 2535 * The device flash could be up to 16MB in size. However, it is possible that 2536 * the actual size is smaller. Use bisection to determine the accessible size 2537 * of flash memory. 2538 * 2539 * Return: the exit code of the operation. 2540 */ 2541 static int ixgbe_discover_flash_size(struct ixgbe_hw *hw) 2542 { 2543 u32 min_size = 0, max_size = IXGBE_ACI_NVM_MAX_OFFSET + 1; 2544 int err; 2545 2546 err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ); 2547 if (err) 2548 return err; 2549 2550 while ((max_size - min_size) > 1) { 2551 u32 offset = (max_size + min_size) / 2; 2552 u32 len = 1; 2553 u8 data; 2554 2555 err = ixgbe_read_flat_nvm(hw, offset, &len, &data, false); 2556 if (err == -EIO && 2557 hw->aci.last_status == LIBIE_AQ_RC_EINVAL) { 2558 err = 0; 2559 max_size = offset; 2560 } else if (!err) { 2561 min_size = offset; 2562 } else { 2563 /* an unexpected error occurred */ 2564 goto err_read_flat_nvm; 2565 } 2566 } 2567 2568 hw->flash.flash_size = max_size; 2569 2570 err_read_flat_nvm: 2571 ixgbe_release_nvm(hw); 2572 2573 return err; 2574 } 2575 2576 /** 2577 * ixgbe_read_sr_base_address - Read the value of a Shadow RAM pointer word 2578 * @hw: pointer to the HW structure 2579 * @offset: the word offset of the Shadow RAM word to read 2580 * @pointer: pointer value read from Shadow RAM 2581 * 2582 * Read the given Shadow RAM word, and convert it to a pointer value specified 2583 * in bytes. This function assumes the specified offset is a valid pointer 2584 * word. 2585 * 2586 * Each pointer word specifies whether it is stored in word size or 4KB 2587 * sector size by using the highest bit. The reported pointer value will be in 2588 * bytes, intended for flat NVM reads. 2589 * 2590 * Return: the exit code of the operation. 2591 */ 2592 static int ixgbe_read_sr_base_address(struct ixgbe_hw *hw, u16 offset, 2593 u32 *pointer) 2594 { 2595 u16 value; 2596 int err; 2597 2598 err = ixgbe_read_ee_aci_e610(hw, offset, &value); 2599 if (err) 2600 return err; 2601 2602 /* Determine if the pointer is in 4KB or word units */ 2603 if (value & IXGBE_SR_NVM_PTR_4KB_UNITS) 2604 *pointer = (value & ~IXGBE_SR_NVM_PTR_4KB_UNITS) * SZ_4K; 2605 else 2606 *pointer = value * sizeof(u16); 2607 2608 return 0; 2609 } 2610 2611 /** 2612 * ixgbe_read_sr_area_size - Read an area size from a Shadow RAM word 2613 * @hw: pointer to the HW structure 2614 * @offset: the word offset of the Shadow RAM to read 2615 * @size: size value read from the Shadow RAM 2616 * 2617 * Read the given Shadow RAM word, and convert it to an area size value 2618 * specified in bytes. This function assumes the specified offset is a valid 2619 * area size word. 2620 * 2621 * Each area size word is specified in 4KB sector units. This function reports 2622 * the size in bytes, intended for flat NVM reads. 2623 * 2624 * Return: the exit code of the operation. 2625 */ 2626 static int ixgbe_read_sr_area_size(struct ixgbe_hw *hw, u16 offset, u32 *size) 2627 { 2628 u16 value; 2629 int err; 2630 2631 err = ixgbe_read_ee_aci_e610(hw, offset, &value); 2632 if (err) 2633 return err; 2634 2635 /* Area sizes are always specified in 4KB units */ 2636 *size = value * SZ_4K; 2637 2638 return 0; 2639 } 2640 2641 /** 2642 * ixgbe_determine_active_flash_banks - Discover active bank for each module 2643 * @hw: pointer to the HW struct 2644 * 2645 * Read the Shadow RAM control word and determine which banks are active for 2646 * the NVM, OROM, and Netlist modules. Also read and calculate the associated 2647 * pointer and size. These values are then cached into the ixgbe_flash_info 2648 * structure for later use in order to calculate the correct offset to read 2649 * from the active module. 2650 * 2651 * Return: the exit code of the operation. 2652 */ 2653 static int ixgbe_determine_active_flash_banks(struct ixgbe_hw *hw) 2654 { 2655 struct ixgbe_bank_info *banks = &hw->flash.banks; 2656 u16 ctrl_word; 2657 int err; 2658 2659 err = ixgbe_read_ee_aci_e610(hw, IXGBE_E610_SR_NVM_CTRL_WORD, 2660 &ctrl_word); 2661 if (err) 2662 return err; 2663 2664 if (FIELD_GET(IXGBE_SR_CTRL_WORD_1_M, ctrl_word) != 2665 IXGBE_SR_CTRL_WORD_VALID) 2666 return -ENODATA; 2667 2668 if (!(ctrl_word & IXGBE_SR_CTRL_WORD_NVM_BANK)) 2669 banks->nvm_bank = IXGBE_1ST_FLASH_BANK; 2670 else 2671 banks->nvm_bank = IXGBE_2ND_FLASH_BANK; 2672 2673 if (!(ctrl_word & IXGBE_SR_CTRL_WORD_OROM_BANK)) 2674 banks->orom_bank = IXGBE_1ST_FLASH_BANK; 2675 else 2676 banks->orom_bank = IXGBE_2ND_FLASH_BANK; 2677 2678 if (!(ctrl_word & IXGBE_SR_CTRL_WORD_NETLIST_BANK)) 2679 banks->netlist_bank = IXGBE_1ST_FLASH_BANK; 2680 else 2681 banks->netlist_bank = IXGBE_2ND_FLASH_BANK; 2682 2683 err = ixgbe_read_sr_base_address(hw, IXGBE_E610_SR_1ST_NVM_BANK_PTR, 2684 &banks->nvm_ptr); 2685 if (err) 2686 return err; 2687 2688 err = ixgbe_read_sr_area_size(hw, IXGBE_E610_SR_NVM_BANK_SIZE, 2689 &banks->nvm_size); 2690 if (err) 2691 return err; 2692 2693 err = ixgbe_read_sr_base_address(hw, IXGBE_E610_SR_1ST_OROM_BANK_PTR, 2694 &banks->orom_ptr); 2695 if (err) 2696 return err; 2697 2698 err = ixgbe_read_sr_area_size(hw, IXGBE_E610_SR_OROM_BANK_SIZE, 2699 &banks->orom_size); 2700 if (err) 2701 return err; 2702 2703 err = ixgbe_read_sr_base_address(hw, IXGBE_E610_SR_NETLIST_BANK_PTR, 2704 &banks->netlist_ptr); 2705 if (err) 2706 return err; 2707 2708 err = ixgbe_read_sr_area_size(hw, IXGBE_E610_SR_NETLIST_BANK_SIZE, 2709 &banks->netlist_size); 2710 2711 return err; 2712 } 2713 2714 /** 2715 * ixgbe_get_flash_bank_offset - Get offset into requested flash bank 2716 * @hw: pointer to the HW structure 2717 * @bank: whether to read from the active or inactive flash bank 2718 * @module: the module to read from 2719 * 2720 * Based on the module, lookup the module offset from the beginning of the 2721 * flash. 2722 * 2723 * Return: the flash offset. Note that a value of zero is invalid and must be 2724 * treated as an error. 2725 */ 2726 static int ixgbe_get_flash_bank_offset(struct ixgbe_hw *hw, 2727 enum ixgbe_bank_select bank, 2728 u16 module) 2729 { 2730 struct ixgbe_bank_info *banks = &hw->flash.banks; 2731 enum ixgbe_flash_bank active_bank; 2732 bool second_bank_active; 2733 u32 offset, size; 2734 2735 switch (module) { 2736 case IXGBE_E610_SR_1ST_NVM_BANK_PTR: 2737 offset = banks->nvm_ptr; 2738 size = banks->nvm_size; 2739 active_bank = banks->nvm_bank; 2740 break; 2741 case IXGBE_E610_SR_1ST_OROM_BANK_PTR: 2742 offset = banks->orom_ptr; 2743 size = banks->orom_size; 2744 active_bank = banks->orom_bank; 2745 break; 2746 case IXGBE_E610_SR_NETLIST_BANK_PTR: 2747 offset = banks->netlist_ptr; 2748 size = banks->netlist_size; 2749 active_bank = banks->netlist_bank; 2750 break; 2751 default: 2752 return 0; 2753 } 2754 2755 switch (active_bank) { 2756 case IXGBE_1ST_FLASH_BANK: 2757 second_bank_active = false; 2758 break; 2759 case IXGBE_2ND_FLASH_BANK: 2760 second_bank_active = true; 2761 break; 2762 default: 2763 return 0; 2764 } 2765 2766 /* The second flash bank is stored immediately following the first 2767 * bank. Based on whether the 1st or 2nd bank is active, and whether 2768 * we want the active or inactive bank, calculate the desired offset. 2769 */ 2770 switch (bank) { 2771 case IXGBE_ACTIVE_FLASH_BANK: 2772 return offset + (second_bank_active ? size : 0); 2773 case IXGBE_INACTIVE_FLASH_BANK: 2774 return offset + (second_bank_active ? 0 : size); 2775 } 2776 2777 return 0; 2778 } 2779 2780 /** 2781 * ixgbe_read_flash_module - Read a word from one of the main NVM modules 2782 * @hw: pointer to the HW structure 2783 * @bank: which bank of the module to read 2784 * @module: the module to read 2785 * @offset: the offset into the module in bytes 2786 * @data: storage for the word read from the flash 2787 * @length: bytes of data to read 2788 * 2789 * Read data from the specified flash module. The bank parameter indicates 2790 * whether or not to read from the active bank or the inactive bank of that 2791 * module. 2792 * 2793 * The word will be read using flat NVM access, and relies on the 2794 * hw->flash.banks data being setup by ixgbe_determine_active_flash_banks() 2795 * during initialization. 2796 * 2797 * Return: the exit code of the operation. 2798 */ 2799 static int ixgbe_read_flash_module(struct ixgbe_hw *hw, 2800 enum ixgbe_bank_select bank, 2801 u16 module, u32 offset, u8 *data, u32 length) 2802 { 2803 u32 start; 2804 int err; 2805 2806 start = ixgbe_get_flash_bank_offset(hw, bank, module); 2807 if (!start) 2808 return -EINVAL; 2809 2810 err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ); 2811 if (err) 2812 return err; 2813 2814 err = ixgbe_read_flat_nvm(hw, start + offset, &length, data, false); 2815 2816 ixgbe_release_nvm(hw); 2817 2818 return err; 2819 } 2820 2821 /** 2822 * ixgbe_read_nvm_module - Read from the active main NVM module 2823 * @hw: pointer to the HW structure 2824 * @bank: whether to read from active or inactive NVM module 2825 * @offset: offset into the NVM module to read, in words 2826 * @data: storage for returned word value 2827 * 2828 * Read the specified word from the active NVM module. This includes the CSS 2829 * header at the start of the NVM module. 2830 * 2831 * Return: the exit code of the operation. 2832 */ 2833 static int ixgbe_read_nvm_module(struct ixgbe_hw *hw, 2834 enum ixgbe_bank_select bank, 2835 u32 offset, u16 *data) 2836 { 2837 __le16 data_local; 2838 int err; 2839 2840 err = ixgbe_read_flash_module(hw, bank, IXGBE_E610_SR_1ST_NVM_BANK_PTR, 2841 offset * sizeof(data_local), 2842 (u8 *)&data_local, 2843 sizeof(data_local)); 2844 if (!err) 2845 *data = le16_to_cpu(data_local); 2846 2847 return err; 2848 } 2849 2850 /** 2851 * ixgbe_read_netlist_module - Read data from the netlist module area 2852 * @hw: pointer to the HW structure 2853 * @bank: whether to read from the active or inactive module 2854 * @offset: offset into the netlist to read from 2855 * @data: storage for returned word value 2856 * 2857 * Read a word from the specified netlist bank. 2858 * 2859 * Return: the exit code of the operation. 2860 */ 2861 static int ixgbe_read_netlist_module(struct ixgbe_hw *hw, 2862 enum ixgbe_bank_select bank, 2863 u32 offset, u16 *data) 2864 { 2865 __le16 data_local; 2866 int err; 2867 2868 err = ixgbe_read_flash_module(hw, bank, IXGBE_E610_SR_NETLIST_BANK_PTR, 2869 offset * sizeof(data_local), 2870 (u8 *)&data_local, sizeof(data_local)); 2871 if (!err) 2872 *data = le16_to_cpu(data_local); 2873 2874 return err; 2875 } 2876 2877 /** 2878 * ixgbe_read_orom_module - Read from the active Option ROM module 2879 * @hw: pointer to the HW structure 2880 * @bank: whether to read from active or inactive OROM module 2881 * @offset: offset into the OROM module to read, in words 2882 * @data: storage for returned word value 2883 * 2884 * Read the specified word from the active Option ROM module of the flash. 2885 * Note that unlike the NVM module, the CSS data is stored at the end of the 2886 * module instead of at the beginning. 2887 * 2888 * Return: the exit code of the operation. 2889 */ 2890 static int ixgbe_read_orom_module(struct ixgbe_hw *hw, 2891 enum ixgbe_bank_select bank, 2892 u32 offset, u16 *data) 2893 { 2894 __le16 data_local; 2895 int err; 2896 2897 err = ixgbe_read_flash_module(hw, bank, IXGBE_E610_SR_1ST_OROM_BANK_PTR, 2898 offset * sizeof(data_local), 2899 (u8 *)&data_local, sizeof(data_local)); 2900 if (!err) 2901 *data = le16_to_cpu(data_local); 2902 2903 return err; 2904 } 2905 2906 /** 2907 * ixgbe_get_nvm_css_hdr_len - Read the CSS header length 2908 * @hw: pointer to the HW struct 2909 * @bank: whether to read from the active or inactive flash bank 2910 * @hdr_len: storage for header length in words 2911 * 2912 * Read the CSS header length from the NVM CSS header and add the 2913 * Authentication header size, and then convert to words. 2914 * 2915 * Return: the exit code of the operation. 2916 */ 2917 static int ixgbe_get_nvm_css_hdr_len(struct ixgbe_hw *hw, 2918 enum ixgbe_bank_select bank, 2919 u32 *hdr_len) 2920 { 2921 u16 hdr_len_l, hdr_len_h; 2922 u32 hdr_len_dword; 2923 int err; 2924 2925 err = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_HDR_LEN_L, 2926 &hdr_len_l); 2927 if (err) 2928 return err; 2929 2930 err = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_HDR_LEN_H, 2931 &hdr_len_h); 2932 if (err) 2933 return err; 2934 2935 /* CSS header length is in DWORD, so convert to words and add 2936 * authentication header size. 2937 */ 2938 hdr_len_dword = (hdr_len_h << 16) | hdr_len_l; 2939 *hdr_len = hdr_len_dword * 2 + IXGBE_NVM_AUTH_HEADER_LEN; 2940 2941 return 0; 2942 } 2943 2944 /** 2945 * ixgbe_read_nvm_sr_copy - Read a word from the Shadow RAM copy 2946 * @hw: pointer to the HW structure 2947 * @bank: whether to read from the active or inactive NVM module 2948 * @offset: offset into the Shadow RAM copy to read, in words 2949 * @data: storage for returned word value 2950 * 2951 * Read the specified word from the copy of the Shadow RAM found in the 2952 * specified NVM module. 2953 * 2954 * Return: the exit code of the operation. 2955 */ 2956 static int ixgbe_read_nvm_sr_copy(struct ixgbe_hw *hw, 2957 enum ixgbe_bank_select bank, 2958 u32 offset, u16 *data) 2959 { 2960 u32 hdr_len; 2961 int err; 2962 2963 err = ixgbe_get_nvm_css_hdr_len(hw, bank, &hdr_len); 2964 if (err) 2965 return err; 2966 2967 hdr_len = round_up(hdr_len, IXGBE_HDR_LEN_ROUNDUP); 2968 2969 return ixgbe_read_nvm_module(hw, bank, hdr_len + offset, data); 2970 } 2971 2972 /** 2973 * ixgbe_get_nvm_srev - Read the security revision from the NVM CSS header 2974 * @hw: pointer to the HW struct 2975 * @bank: whether to read from the active or inactive flash bank 2976 * @srev: storage for security revision 2977 * 2978 * Read the security revision out of the CSS header of the active NVM module 2979 * bank. 2980 * 2981 * Return: the exit code of the operation. 2982 */ 2983 static int ixgbe_get_nvm_srev(struct ixgbe_hw *hw, 2984 enum ixgbe_bank_select bank, u32 *srev) 2985 { 2986 u16 srev_l, srev_h; 2987 int err; 2988 2989 err = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_SREV_L, &srev_l); 2990 if (err) 2991 return err; 2992 2993 err = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_SREV_H, &srev_h); 2994 if (err) 2995 return err; 2996 2997 *srev = (srev_h << 16) | srev_l; 2998 2999 return 0; 3000 } 3001 3002 /** 3003 * ixgbe_get_orom_civd_data - Get the combo version information from Option ROM 3004 * @hw: pointer to the HW struct 3005 * @bank: whether to read from the active or inactive flash module 3006 * @civd: storage for the Option ROM CIVD data. 3007 * 3008 * Searches through the Option ROM flash contents to locate the CIVD data for 3009 * the image. 3010 * 3011 * Return: the exit code of the operation. 3012 */ 3013 static int 3014 ixgbe_get_orom_civd_data(struct ixgbe_hw *hw, enum ixgbe_bank_select bank, 3015 struct ixgbe_orom_civd_info *civd) 3016 { 3017 struct ixgbe_orom_civd_info tmp; 3018 u32 offset; 3019 int err; 3020 3021 /* The CIVD section is located in the Option ROM aligned to 512 bytes. 3022 * The first 4 bytes must contain the ASCII characters "$CIV". 3023 * A simple modulo 256 sum of all of the bytes of the structure must 3024 * equal 0. 3025 */ 3026 for (offset = 0; (offset + SZ_512) <= hw->flash.banks.orom_size; 3027 offset += SZ_512) { 3028 u8 sum = 0; 3029 u32 i; 3030 3031 err = ixgbe_read_flash_module(hw, bank, 3032 IXGBE_E610_SR_1ST_OROM_BANK_PTR, 3033 offset, 3034 (u8 *)&tmp, sizeof(tmp)); 3035 if (err) 3036 return err; 3037 3038 /* Skip forward until we find a matching signature */ 3039 if (memcmp(IXGBE_OROM_CIV_SIGNATURE, tmp.signature, 3040 sizeof(tmp.signature))) 3041 continue; 3042 3043 /* Verify that the simple checksum is zero */ 3044 for (i = 0; i < sizeof(tmp); i++) 3045 sum += ((u8 *)&tmp)[i]; 3046 3047 if (sum) 3048 return -EDOM; 3049 3050 *civd = tmp; 3051 return 0; 3052 } 3053 3054 return -ENODATA; 3055 } 3056 3057 /** 3058 * ixgbe_get_orom_srev - Read the security revision from the OROM CSS header 3059 * @hw: pointer to the HW struct 3060 * @bank: whether to read from active or inactive flash module 3061 * @srev: storage for security revision 3062 * 3063 * Read the security revision out of the CSS header of the active OROM module 3064 * bank. 3065 * 3066 * Return: the exit code of the operation. 3067 */ 3068 static int ixgbe_get_orom_srev(struct ixgbe_hw *hw, 3069 enum ixgbe_bank_select bank, 3070 u32 *srev) 3071 { 3072 u32 orom_size_word = hw->flash.banks.orom_size / 2; 3073 u32 css_start, hdr_len; 3074 u16 srev_l, srev_h; 3075 int err; 3076 3077 err = ixgbe_get_nvm_css_hdr_len(hw, bank, &hdr_len); 3078 if (err) 3079 return err; 3080 3081 if (orom_size_word < hdr_len) 3082 return -EINVAL; 3083 3084 /* Calculate how far into the Option ROM the CSS header starts. Note 3085 * that ixgbe_read_orom_module takes a word offset. 3086 */ 3087 css_start = orom_size_word - hdr_len; 3088 err = ixgbe_read_orom_module(hw, bank, 3089 css_start + IXGBE_NVM_CSS_SREV_L, 3090 &srev_l); 3091 if (err) 3092 return err; 3093 3094 err = ixgbe_read_orom_module(hw, bank, 3095 css_start + IXGBE_NVM_CSS_SREV_H, 3096 &srev_h); 3097 if (err) 3098 return err; 3099 3100 *srev = srev_h << 16 | srev_l; 3101 3102 return 0; 3103 } 3104 3105 /** 3106 * ixgbe_get_orom_ver_info - Read Option ROM version information 3107 * @hw: pointer to the HW struct 3108 * @bank: whether to read from the active or inactive flash module 3109 * @orom: pointer to Option ROM info structure 3110 * 3111 * Read Option ROM version and security revision from the Option ROM flash 3112 * section. 3113 * 3114 * Return: the exit code of the operation. 3115 */ 3116 static int ixgbe_get_orom_ver_info(struct ixgbe_hw *hw, 3117 enum ixgbe_bank_select bank, 3118 struct ixgbe_orom_info *orom) 3119 { 3120 struct ixgbe_orom_civd_info civd; 3121 u32 combo_ver; 3122 int err; 3123 3124 err = ixgbe_get_orom_civd_data(hw, bank, &civd); 3125 if (err) 3126 return err; 3127 3128 combo_ver = get_unaligned_le32(&civd.combo_ver); 3129 3130 orom->major = (u8)FIELD_GET(IXGBE_OROM_VER_MASK, combo_ver); 3131 orom->patch = (u8)FIELD_GET(IXGBE_OROM_VER_PATCH_MASK, combo_ver); 3132 orom->build = (u16)FIELD_GET(IXGBE_OROM_VER_BUILD_MASK, combo_ver); 3133 3134 return ixgbe_get_orom_srev(hw, bank, &orom->srev); 3135 } 3136 3137 /** 3138 * ixgbe_get_inactive_orom_ver - Read Option ROM version from the inactive bank 3139 * @hw: pointer to the HW structure 3140 * @orom: storage for Option ROM version information 3141 * 3142 * Read the Option ROM version and security revision data for the inactive 3143 * section of flash. Used to access version data for a pending update that has 3144 * not yet been activated. 3145 * 3146 * Return: the exit code of the operation. 3147 */ 3148 int ixgbe_get_inactive_orom_ver(struct ixgbe_hw *hw, 3149 struct ixgbe_orom_info *orom) 3150 { 3151 return ixgbe_get_orom_ver_info(hw, IXGBE_INACTIVE_FLASH_BANK, orom); 3152 } 3153 3154 /** 3155 * ixgbe_get_nvm_ver_info - Read NVM version information 3156 * @hw: pointer to the HW struct 3157 * @bank: whether to read from the active or inactive flash bank 3158 * @nvm: pointer to NVM info structure 3159 * 3160 * Read the NVM EETRACK ID and map version of the main NVM image bank, filling 3161 * in the nvm info structure. 3162 * 3163 * Return: the exit code of the operation. 3164 */ 3165 static int ixgbe_get_nvm_ver_info(struct ixgbe_hw *hw, 3166 enum ixgbe_bank_select bank, 3167 struct ixgbe_nvm_info *nvm) 3168 { 3169 u16 eetrack_lo, eetrack_hi, ver; 3170 int err; 3171 3172 err = ixgbe_read_nvm_sr_copy(hw, bank, 3173 IXGBE_E610_SR_NVM_DEV_STARTER_VER, &ver); 3174 if (err) 3175 return err; 3176 3177 nvm->major = FIELD_GET(IXGBE_E610_NVM_VER_HI_MASK, ver); 3178 nvm->minor = FIELD_GET(IXGBE_E610_NVM_VER_LO_MASK, ver); 3179 3180 err = ixgbe_read_nvm_sr_copy(hw, bank, IXGBE_E610_SR_NVM_EETRACK_LO, 3181 &eetrack_lo); 3182 if (err) 3183 return err; 3184 3185 err = ixgbe_read_nvm_sr_copy(hw, bank, IXGBE_E610_SR_NVM_EETRACK_HI, 3186 &eetrack_hi); 3187 if (err) 3188 return err; 3189 3190 nvm->eetrack = (eetrack_hi << 16) | eetrack_lo; 3191 3192 ixgbe_get_nvm_srev(hw, bank, &nvm->srev); 3193 3194 return 0; 3195 } 3196 3197 /** 3198 * ixgbe_get_inactive_nvm_ver - Read Option ROM version from the inactive bank 3199 * @hw: pointer to the HW structure 3200 * @nvm: storage for Option ROM version information 3201 * 3202 * Read the NVM EETRACK ID, Map version, and security revision of the 3203 * inactive NVM bank. Used to access version data for a pending update that 3204 * has not yet been activated. 3205 * 3206 * Return: the exit code of the operation. 3207 */ 3208 int ixgbe_get_inactive_nvm_ver(struct ixgbe_hw *hw, struct ixgbe_nvm_info *nvm) 3209 { 3210 return ixgbe_get_nvm_ver_info(hw, IXGBE_INACTIVE_FLASH_BANK, nvm); 3211 } 3212 3213 /** 3214 * ixgbe_get_active_nvm_ver - Read Option ROM version from the active bank 3215 * @hw: pointer to the HW structure 3216 * @nvm: storage for Option ROM version information 3217 * 3218 * Reads the NVM EETRACK ID, Map version, and security revision of the 3219 * active NVM bank. 3220 * 3221 * Return: the exit code of the operation. 3222 */ 3223 static int ixgbe_get_active_nvm_ver(struct ixgbe_hw *hw, 3224 struct ixgbe_nvm_info *nvm) 3225 { 3226 return ixgbe_get_nvm_ver_info(hw, IXGBE_ACTIVE_FLASH_BANK, nvm); 3227 } 3228 3229 /** 3230 * ixgbe_get_netlist_info - Read the netlist version information 3231 * @hw: pointer to the HW struct 3232 * @bank: whether to read from the active or inactive flash bank 3233 * @netlist: pointer to netlist version info structure 3234 * 3235 * Get the netlist version information from the requested bank. Reads the Link 3236 * Topology section to find the Netlist ID block and extract the relevant 3237 * information into the netlist version structure. 3238 * 3239 * Return: the exit code of the operation. 3240 */ 3241 static int ixgbe_get_netlist_info(struct ixgbe_hw *hw, 3242 enum ixgbe_bank_select bank, 3243 struct ixgbe_netlist_info *netlist) 3244 { 3245 u16 module_id, length, node_count, i; 3246 u16 *id_blk; 3247 int err; 3248 3249 err = ixgbe_read_netlist_module(hw, bank, IXGBE_NETLIST_TYPE_OFFSET, 3250 &module_id); 3251 if (err) 3252 return err; 3253 3254 if (module_id != IXGBE_NETLIST_LINK_TOPO_MOD_ID) 3255 return -EIO; 3256 3257 err = ixgbe_read_netlist_module(hw, bank, IXGBE_LINK_TOPO_MODULE_LEN, 3258 &length); 3259 if (err) 3260 return err; 3261 3262 /* Sanity check that we have at least enough words to store the 3263 * netlist ID block. 3264 */ 3265 if (length < IXGBE_NETLIST_ID_BLK_SIZE) 3266 return -EIO; 3267 3268 err = ixgbe_read_netlist_module(hw, bank, IXGBE_LINK_TOPO_NODE_COUNT, 3269 &node_count); 3270 if (err) 3271 return err; 3272 3273 node_count &= IXGBE_LINK_TOPO_NODE_COUNT_M; 3274 3275 id_blk = kcalloc(IXGBE_NETLIST_ID_BLK_SIZE, sizeof(*id_blk), GFP_KERNEL); 3276 if (!id_blk) 3277 return -ENOMEM; 3278 3279 /* Read out the entire Netlist ID Block at once. */ 3280 err = ixgbe_read_flash_module(hw, bank, IXGBE_E610_SR_NETLIST_BANK_PTR, 3281 IXGBE_NETLIST_ID_BLK_OFFSET(node_count) * 3282 sizeof(*id_blk), (u8 *)id_blk, 3283 IXGBE_NETLIST_ID_BLK_SIZE * 3284 sizeof(*id_blk)); 3285 if (err) 3286 goto free_id_blk; 3287 3288 for (i = 0; i < IXGBE_NETLIST_ID_BLK_SIZE; i++) 3289 id_blk[i] = le16_to_cpu(((__le16 *)id_blk)[i]); 3290 3291 netlist->major = id_blk[IXGBE_NETLIST_ID_BLK_MAJOR_VER_HIGH] << 16 | 3292 id_blk[IXGBE_NETLIST_ID_BLK_MAJOR_VER_LOW]; 3293 netlist->minor = id_blk[IXGBE_NETLIST_ID_BLK_MINOR_VER_HIGH] << 16 | 3294 id_blk[IXGBE_NETLIST_ID_BLK_MINOR_VER_LOW]; 3295 netlist->type = id_blk[IXGBE_NETLIST_ID_BLK_TYPE_HIGH] << 16 | 3296 id_blk[IXGBE_NETLIST_ID_BLK_TYPE_LOW]; 3297 netlist->rev = id_blk[IXGBE_NETLIST_ID_BLK_REV_HIGH] << 16 | 3298 id_blk[IXGBE_NETLIST_ID_BLK_REV_LOW]; 3299 netlist->cust_ver = id_blk[IXGBE_NETLIST_ID_BLK_CUST_VER]; 3300 /* Read the left most 4 bytes of SHA */ 3301 netlist->hash = id_blk[IXGBE_NETLIST_ID_BLK_SHA_HASH_WORD(15)] << 16 | 3302 id_blk[IXGBE_NETLIST_ID_BLK_SHA_HASH_WORD(14)]; 3303 3304 free_id_blk: 3305 kfree(id_blk); 3306 return err; 3307 } 3308 3309 /** 3310 * ixgbe_get_inactive_netlist_ver - Read netlist version from the inactive bank 3311 * @hw: pointer to the HW struct 3312 * @netlist: pointer to netlist version info structure 3313 * 3314 * Read the netlist version data from the inactive netlist bank. Used to 3315 * extract version data of a pending flash update in order to display the 3316 * version data. 3317 * 3318 * Return: the exit code of the operation. 3319 */ 3320 int ixgbe_get_inactive_netlist_ver(struct ixgbe_hw *hw, 3321 struct ixgbe_netlist_info *netlist) 3322 { 3323 return ixgbe_get_netlist_info(hw, IXGBE_INACTIVE_FLASH_BANK, netlist); 3324 } 3325 3326 /** 3327 * ixgbe_get_flash_data - get flash data 3328 * @hw: pointer to the HW struct 3329 * 3330 * Read and populate flash data such as Shadow RAM size, 3331 * max_timeout and blank_nvm_mode 3332 * 3333 * Return: the exit code of the operation. 3334 */ 3335 int ixgbe_get_flash_data(struct ixgbe_hw *hw) 3336 { 3337 struct ixgbe_flash_info *flash = &hw->flash; 3338 u32 fla, gens_stat; 3339 u8 sr_size; 3340 int err; 3341 3342 /* The SR size is stored regardless of the NVM programming mode 3343 * as the blank mode may be used in the factory line. 3344 */ 3345 gens_stat = IXGBE_READ_REG(hw, GLNVM_GENS); 3346 sr_size = FIELD_GET(GLNVM_GENS_SR_SIZE_M, gens_stat); 3347 3348 /* Switching to words (sr_size contains power of 2) */ 3349 flash->sr_words = BIT(sr_size) * (SZ_1K / sizeof(u16)); 3350 3351 /* Check if we are in the normal or blank NVM programming mode */ 3352 fla = IXGBE_READ_REG(hw, IXGBE_GLNVM_FLA); 3353 if (fla & IXGBE_GLNVM_FLA_LOCKED_M) { 3354 flash->blank_nvm_mode = false; 3355 } else { 3356 flash->blank_nvm_mode = true; 3357 return -EIO; 3358 } 3359 3360 err = ixgbe_discover_flash_size(hw); 3361 if (err) 3362 return err; 3363 3364 err = ixgbe_determine_active_flash_banks(hw); 3365 if (err) 3366 return err; 3367 3368 err = ixgbe_get_nvm_ver_info(hw, IXGBE_ACTIVE_FLASH_BANK, 3369 &flash->nvm); 3370 if (err) 3371 return err; 3372 3373 err = ixgbe_get_orom_ver_info(hw, IXGBE_ACTIVE_FLASH_BANK, 3374 &flash->orom); 3375 if (err) 3376 return err; 3377 3378 err = ixgbe_get_netlist_info(hw, IXGBE_ACTIVE_FLASH_BANK, 3379 &flash->netlist); 3380 return err; 3381 } 3382 3383 /** 3384 * ixgbe_aci_nvm_update_empr - update NVM using EMPR 3385 * @hw: pointer to the HW struct 3386 * 3387 * Force EMP reset using ACI command (0x0709). This command allows SW to 3388 * request an EMPR to activate new FW. 3389 * 3390 * Return: the exit code of the operation. 3391 */ 3392 int ixgbe_aci_nvm_update_empr(struct ixgbe_hw *hw) 3393 { 3394 struct libie_aq_desc desc; 3395 3396 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_update_empr); 3397 3398 return ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 3399 } 3400 3401 /* ixgbe_nvm_set_pkg_data - NVM set package data 3402 * @hw: pointer to the HW struct 3403 * @del_pkg_data_flag: If is set then the current pkg_data store by FW 3404 * is deleted. 3405 * If bit is set to 1, then buffer should be size 0. 3406 * @data: pointer to buffer 3407 * @length: length of the buffer 3408 * 3409 * Set package data using ACI command (0x070A). 3410 * This command is equivalent to the reception of 3411 * a PLDM FW Update GetPackageData cmd. This command should be sent 3412 * as part of the NVM update as the first cmd in the flow. 3413 * 3414 * Return: the exit code of the operation. 3415 */ 3416 int ixgbe_nvm_set_pkg_data(struct ixgbe_hw *hw, bool del_pkg_data_flag, 3417 u8 *data, u16 length) 3418 { 3419 struct ixgbe_aci_cmd_nvm_pkg_data *cmd; 3420 struct libie_aq_desc desc; 3421 3422 if (length != 0 && !data) 3423 return -EINVAL; 3424 3425 cmd = libie_aq_raw(&desc); 3426 3427 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_pkg_data); 3428 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 3429 3430 if (del_pkg_data_flag) 3431 cmd->cmd_flags |= IXGBE_ACI_NVM_PKG_DELETE; 3432 3433 return ixgbe_aci_send_cmd(hw, &desc, data, length); 3434 } 3435 3436 /* ixgbe_nvm_pass_component_tbl - NVM pass component table 3437 * @hw: pointer to the HW struct 3438 * @data: pointer to buffer 3439 * @length: length of the buffer 3440 * @transfer_flag: parameter for determining stage of the update 3441 * @comp_response: a pointer to the response from the 0x070B ACI. 3442 * @comp_response_code: a pointer to the response code from the 0x070B ACI. 3443 * 3444 * Pass component table using ACI command (0x070B). This command is equivalent 3445 * to the reception of a PLDM FW Update PassComponentTable cmd. 3446 * This command should be sent once per component. It can be only sent after 3447 * Set Package Data cmd and before actual update. FW will assume these 3448 * commands are going to be sent until the TransferFlag is set to End or 3449 * StartAndEnd. 3450 * 3451 * Return: the exit code of the operation. 3452 */ 3453 int ixgbe_nvm_pass_component_tbl(struct ixgbe_hw *hw, u8 *data, u16 length, 3454 u8 transfer_flag, u8 *comp_response, 3455 u8 *comp_response_code) 3456 { 3457 struct ixgbe_aci_cmd_nvm_pass_comp_tbl *cmd; 3458 struct libie_aq_desc desc; 3459 int err; 3460 3461 if (!data || !comp_response || !comp_response_code) 3462 return -EINVAL; 3463 3464 cmd = libie_aq_raw(&desc); 3465 3466 ixgbe_fill_dflt_direct_cmd_desc(&desc, 3467 ixgbe_aci_opc_nvm_pass_component_tbl); 3468 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 3469 3470 cmd->transfer_flag = transfer_flag; 3471 err = ixgbe_aci_send_cmd(hw, &desc, data, length); 3472 if (!err) { 3473 *comp_response = cmd->component_response; 3474 *comp_response_code = cmd->component_response_code; 3475 } 3476 3477 return err; 3478 } 3479 3480 /** 3481 * ixgbe_read_sr_word_aci - Reads Shadow RAM via ACI 3482 * @hw: pointer to the HW structure 3483 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 3484 * @data: word read from the Shadow RAM 3485 * 3486 * Reads one 16 bit word from the Shadow RAM using ixgbe_read_flat_nvm. 3487 * 3488 * Return: the exit code of the operation. 3489 */ 3490 int ixgbe_read_sr_word_aci(struct ixgbe_hw *hw, u16 offset, u16 *data) 3491 { 3492 u32 bytes = sizeof(u16); 3493 u16 data_local; 3494 int err; 3495 3496 err = ixgbe_read_flat_nvm(hw, offset * sizeof(u16), &bytes, 3497 (u8 *)&data_local, true); 3498 if (err) 3499 return err; 3500 3501 *data = data_local; 3502 return 0; 3503 } 3504 3505 /** 3506 * ixgbe_read_flat_nvm - Read portion of NVM by flat offset 3507 * @hw: pointer to the HW struct 3508 * @offset: offset from beginning of NVM 3509 * @length: (in) number of bytes to read; (out) number of bytes actually read 3510 * @data: buffer to return data in (sized to fit the specified length) 3511 * @read_shadow_ram: if true, read from shadow RAM instead of NVM 3512 * 3513 * Reads a portion of the NVM, as a flat memory space. This function correctly 3514 * breaks read requests across Shadow RAM sectors, prevents Shadow RAM size 3515 * from being exceeded in case of Shadow RAM read requests and ensures that no 3516 * single read request exceeds the maximum 4KB read for a single admin command. 3517 * 3518 * Returns an error code on failure. Note that the data pointer may be 3519 * partially updated if some reads succeed before a failure. 3520 * 3521 * Return: the exit code of the operation. 3522 */ 3523 int ixgbe_read_flat_nvm(struct ixgbe_hw *hw, u32 offset, u32 *length, 3524 u8 *data, bool read_shadow_ram) 3525 { 3526 u32 inlen = *length; 3527 u32 bytes_read = 0; 3528 bool last_cmd; 3529 int err; 3530 3531 /* Verify the length of the read if this is for the Shadow RAM */ 3532 if (read_shadow_ram && ((offset + inlen) > 3533 (hw->eeprom.word_size * 2u))) 3534 return -EINVAL; 3535 3536 do { 3537 u32 read_size, sector_offset; 3538 3539 /* ixgbe_aci_read_nvm cannot read more than 4KB at a time. 3540 * Additionally, a read from the Shadow RAM may not cross over 3541 * a sector boundary. Conveniently, the sector size is also 4KB. 3542 */ 3543 sector_offset = offset % IXGBE_ACI_MAX_BUFFER_SIZE; 3544 read_size = min_t(u32, 3545 IXGBE_ACI_MAX_BUFFER_SIZE - sector_offset, 3546 inlen - bytes_read); 3547 3548 last_cmd = !(bytes_read + read_size < inlen); 3549 3550 /* ixgbe_aci_read_nvm takes the length as a u16. Our read_size 3551 * is calculated using a u32, but the IXGBE_ACI_MAX_BUFFER_SIZE 3552 * maximum size guarantees that it will fit within the 2 bytes. 3553 */ 3554 err = ixgbe_aci_read_nvm(hw, IXGBE_ACI_NVM_START_POINT, 3555 offset, (u16)read_size, 3556 data + bytes_read, last_cmd, 3557 read_shadow_ram); 3558 if (err) 3559 break; 3560 3561 bytes_read += read_size; 3562 offset += read_size; 3563 } while (!last_cmd); 3564 3565 *length = bytes_read; 3566 return err; 3567 } 3568 3569 /** 3570 * ixgbe_read_sr_buf_aci - Read Shadow RAM buffer via ACI 3571 * @hw: pointer to the HW structure 3572 * @offset: offset of the Shadow RAM words to read (0x000000 - 0x001FFF) 3573 * @words: (in) number of words to read; (out) number of words actually read 3574 * @data: words read from the Shadow RAM 3575 * 3576 * Read 16 bit words (data buf) from the Shadow RAM. Acquire/release the NVM 3577 * ownership. 3578 * 3579 * Return: the operation exit code. 3580 */ 3581 int ixgbe_read_sr_buf_aci(struct ixgbe_hw *hw, u16 offset, u16 *words, 3582 u16 *data) 3583 { 3584 u32 bytes = *words * 2; 3585 int err; 3586 3587 err = ixgbe_read_flat_nvm(hw, offset * 2, &bytes, (u8 *)data, true); 3588 if (err) 3589 return err; 3590 3591 *words = bytes / 2; 3592 3593 for (int i = 0; i < *words; i++) 3594 data[i] = le16_to_cpu(((__le16 *)data)[i]); 3595 3596 return 0; 3597 } 3598 3599 /** 3600 * ixgbe_read_ee_aci_e610 - Read EEPROM word using the admin command. 3601 * @hw: pointer to hardware structure 3602 * @offset: offset of word in the EEPROM to read 3603 * @data: word read from the EEPROM 3604 * 3605 * Reads a 16 bit word from the EEPROM using the ACI. 3606 * If the EEPROM params are not initialized, the function 3607 * initialize them before proceeding with reading. 3608 * The function acquires and then releases the NVM ownership. 3609 * 3610 * Return: the exit code of the operation. 3611 */ 3612 int ixgbe_read_ee_aci_e610(struct ixgbe_hw *hw, u16 offset, u16 *data) 3613 { 3614 int err; 3615 3616 if (hw->eeprom.type == ixgbe_eeprom_uninitialized) { 3617 err = hw->eeprom.ops.init_params(hw); 3618 if (err) 3619 return err; 3620 } 3621 3622 err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ); 3623 if (err) 3624 return err; 3625 3626 err = ixgbe_read_sr_word_aci(hw, offset, data); 3627 ixgbe_release_nvm(hw); 3628 3629 return err; 3630 } 3631 3632 /** 3633 * ixgbe_read_ee_aci_buffer_e610 - Read EEPROM words via ACI 3634 * @hw: pointer to hardware structure 3635 * @offset: offset of words in the EEPROM to read 3636 * @words: number of words to read 3637 * @data: words to read from the EEPROM 3638 * 3639 * Read 16 bit words from the EEPROM via the ACI. Initialize the EEPROM params 3640 * prior to the read. Acquire/release the NVM ownership. 3641 * 3642 * Return: the operation exit code. 3643 */ 3644 int ixgbe_read_ee_aci_buffer_e610(struct ixgbe_hw *hw, u16 offset, 3645 u16 words, u16 *data) 3646 { 3647 int err; 3648 3649 if (hw->eeprom.type == ixgbe_eeprom_uninitialized) { 3650 err = hw->eeprom.ops.init_params(hw); 3651 if (err) 3652 return err; 3653 } 3654 3655 err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ); 3656 if (err) 3657 return err; 3658 3659 err = ixgbe_read_sr_buf_aci(hw, offset, &words, data); 3660 ixgbe_release_nvm(hw); 3661 3662 return err; 3663 } 3664 3665 /** 3666 * ixgbe_validate_eeprom_checksum_e610 - Validate EEPROM checksum 3667 * @hw: pointer to hardware structure 3668 * @checksum_val: calculated checksum 3669 * 3670 * Performs checksum calculation and validates the EEPROM checksum. If the 3671 * caller does not need checksum_val, the value can be NULL. 3672 * If the EEPROM params are not initialized, the function 3673 * initialize them before proceeding. 3674 * The function acquires and then releases the NVM ownership. 3675 * 3676 * Return: the exit code of the operation. 3677 */ 3678 int ixgbe_validate_eeprom_checksum_e610(struct ixgbe_hw *hw, u16 *checksum_val) 3679 { 3680 int err; 3681 3682 if (hw->eeprom.type == ixgbe_eeprom_uninitialized) { 3683 err = hw->eeprom.ops.init_params(hw); 3684 if (err) 3685 return err; 3686 } 3687 3688 err = ixgbe_nvm_validate_checksum(hw); 3689 if (err) 3690 return err; 3691 3692 if (checksum_val) { 3693 u16 tmp_checksum; 3694 3695 err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ); 3696 if (err) 3697 return err; 3698 3699 err = ixgbe_read_sr_word_aci(hw, IXGBE_E610_SR_SW_CHECKSUM_WORD, 3700 &tmp_checksum); 3701 ixgbe_release_nvm(hw); 3702 3703 if (!err) 3704 *checksum_val = tmp_checksum; 3705 } 3706 3707 return err; 3708 } 3709 3710 /** 3711 * ixgbe_reset_hw_e610 - Perform hardware reset 3712 * @hw: pointer to hardware structure 3713 * 3714 * Resets the hardware by resetting the transmit and receive units, masks 3715 * and clears all interrupts, and performs a reset. 3716 * 3717 * Return: the exit code of the operation. 3718 */ 3719 int ixgbe_reset_hw_e610(struct ixgbe_hw *hw) 3720 { 3721 u32 swfw_mask = hw->phy.phy_semaphore_mask; 3722 u32 ctrl, i; 3723 int err; 3724 3725 /* Call adapter stop to disable tx/rx and clear interrupts */ 3726 err = hw->mac.ops.stop_adapter(hw); 3727 if (err) 3728 goto reset_hw_out; 3729 3730 /* Flush pending Tx transactions. */ 3731 ixgbe_clear_tx_pending(hw); 3732 3733 hw->phy.ops.init(hw); 3734 mac_reset_top: 3735 err = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 3736 if (err) 3737 return -EBUSY; 3738 ctrl = IXGBE_CTRL_RST; 3739 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 3740 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 3741 IXGBE_WRITE_FLUSH(hw); 3742 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3743 3744 /* Poll for reset bit to self-clear indicating reset is complete */ 3745 for (i = 0; i < 10; i++) { 3746 udelay(1); 3747 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 3748 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 3749 break; 3750 } 3751 3752 if (ctrl & IXGBE_CTRL_RST_MASK) { 3753 struct ixgbe_adapter *adapter = container_of(hw, struct ixgbe_adapter, 3754 hw); 3755 3756 err = -EIO; 3757 netdev_err(adapter->netdev, "Reset polling failed to complete."); 3758 } 3759 3760 /* Double resets are required for recovery from certain error 3761 * conditions. Between resets, it is necessary to stall to allow time 3762 * for any pending HW events to complete. 3763 */ 3764 msleep(100); 3765 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 3766 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3767 goto mac_reset_top; 3768 } 3769 3770 /* Set the Rx packet buffer size. */ 3771 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), GENMASK(18, 17)); 3772 3773 /* Store the permanent mac address */ 3774 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 3775 3776 /* Maximum number of Receive Address Registers. */ 3777 #define IXGBE_MAX_NUM_RAR 128 3778 3779 /* Store MAC address from RAR0, clear receive address registers, and 3780 * clear the multicast table. Also reset num_rar_entries to the 3781 * maximum number of Receive Address Registers, since we modify this 3782 * value when programming the SAN MAC address. 3783 */ 3784 hw->mac.num_rar_entries = IXGBE_MAX_NUM_RAR; 3785 hw->mac.ops.init_rx_addrs(hw); 3786 3787 /* Initialize bus function number */ 3788 hw->mac.ops.set_lan_id(hw); 3789 3790 reset_hw_out: 3791 return err; 3792 } 3793 3794 /** 3795 * ixgbe_get_pfa_module_tlv - Read sub module TLV from NVM PFA 3796 * @hw: pointer to hardware structure 3797 * @module_tlv: pointer to module TLV to return 3798 * @module_tlv_len: pointer to module TLV length to return 3799 * @module_type: module type requested 3800 * 3801 * Find the requested sub module TLV type from the Preserved Field 3802 * Area (PFA) and returns the TLV pointer and length. The caller can 3803 * use these to read the variable length TLV value. 3804 * 3805 * Return: the exit code of the operation. 3806 */ 3807 static int ixgbe_get_pfa_module_tlv(struct ixgbe_hw *hw, u16 *module_tlv, 3808 u16 *module_tlv_len, u16 module_type) 3809 { 3810 u16 pfa_len, pfa_ptr, pfa_end_ptr; 3811 u16 next_tlv; 3812 int err; 3813 3814 err = ixgbe_read_ee_aci_e610(hw, IXGBE_E610_SR_PFA_PTR, &pfa_ptr); 3815 if (err) 3816 return err; 3817 3818 err = ixgbe_read_ee_aci_e610(hw, pfa_ptr, &pfa_len); 3819 if (err) 3820 return err; 3821 3822 /* Starting with first TLV after PFA length, iterate through the list 3823 * of TLVs to find the requested one. 3824 */ 3825 next_tlv = pfa_ptr + 1; 3826 pfa_end_ptr = pfa_ptr + pfa_len; 3827 while (next_tlv < pfa_end_ptr) { 3828 u16 tlv_sub_module_type, tlv_len; 3829 3830 /* Read TLV type */ 3831 err = ixgbe_read_ee_aci_e610(hw, next_tlv, 3832 &tlv_sub_module_type); 3833 if (err) 3834 break; 3835 3836 /* Read TLV length */ 3837 err = ixgbe_read_ee_aci_e610(hw, next_tlv + 1, &tlv_len); 3838 if (err) 3839 break; 3840 3841 if (tlv_sub_module_type == module_type) { 3842 if (tlv_len) { 3843 *module_tlv = next_tlv; 3844 *module_tlv_len = tlv_len; 3845 return 0; 3846 } 3847 return -EIO; 3848 } 3849 /* Check next TLV, i.e. current TLV pointer + length + 2 words 3850 * (for current TLV's type and length). 3851 */ 3852 next_tlv = next_tlv + tlv_len + 2; 3853 } 3854 /* Module does not exist */ 3855 return -ENODATA; 3856 } 3857 3858 /** 3859 * ixgbe_read_pba_string_e610 - Read PBA string from NVM 3860 * @hw: pointer to hardware structure 3861 * @pba_num: stores the part number string from the NVM 3862 * @pba_num_size: part number string buffer length 3863 * 3864 * Read the part number string from the NVM. 3865 * 3866 * Return: the exit code of the operation. 3867 */ 3868 static int ixgbe_read_pba_string_e610(struct ixgbe_hw *hw, u8 *pba_num, 3869 u32 pba_num_size) 3870 { 3871 u16 pba_tlv, pba_tlv_len; 3872 u16 pba_word, pba_size; 3873 int err; 3874 3875 *pba_num = '\0'; 3876 3877 err = ixgbe_get_pfa_module_tlv(hw, &pba_tlv, &pba_tlv_len, 3878 IXGBE_E610_SR_PBA_BLOCK_PTR); 3879 if (err) 3880 return err; 3881 3882 /* pba_size is the next word */ 3883 err = ixgbe_read_ee_aci_e610(hw, (pba_tlv + 2), &pba_size); 3884 if (err) 3885 return err; 3886 3887 if (pba_tlv_len < pba_size) 3888 return -EINVAL; 3889 3890 /* Subtract one to get PBA word count (PBA Size word is included in 3891 * total size). 3892 */ 3893 pba_size--; 3894 3895 if (pba_num_size < (((u32)pba_size * 2) + 1)) 3896 return -EINVAL; 3897 3898 for (u16 i = 0; i < pba_size; i++) { 3899 err = ixgbe_read_ee_aci_e610(hw, (pba_tlv + 2 + 1) + i, 3900 &pba_word); 3901 if (err) 3902 return err; 3903 3904 pba_num[(i * 2)] = FIELD_GET(IXGBE_E610_SR_PBA_BLOCK_MASK, 3905 pba_word); 3906 pba_num[(i * 2) + 1] = pba_word & 0xFF; 3907 } 3908 3909 pba_num[(pba_size * 2)] = '\0'; 3910 3911 return err; 3912 } 3913 3914 static const struct ixgbe_mac_operations mac_ops_e610 = { 3915 .init_hw = ixgbe_init_hw_generic, 3916 .start_hw = ixgbe_start_hw_e610, 3917 .clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic, 3918 .enable_rx_dma = ixgbe_enable_rx_dma_generic, 3919 .get_mac_addr = ixgbe_get_mac_addr_generic, 3920 .get_device_caps = ixgbe_get_device_caps_generic, 3921 .stop_adapter = ixgbe_stop_adapter_generic, 3922 .set_lan_id = ixgbe_set_lan_id_multi_port_pcie, 3923 .set_rxpba = ixgbe_set_rxpba_generic, 3924 .check_link = ixgbe_check_link_e610, 3925 .blink_led_start = ixgbe_blink_led_start_X540, 3926 .blink_led_stop = ixgbe_blink_led_stop_X540, 3927 .set_rar = ixgbe_set_rar_generic, 3928 .clear_rar = ixgbe_clear_rar_generic, 3929 .set_vmdq = ixgbe_set_vmdq_generic, 3930 .set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic, 3931 .clear_vmdq = ixgbe_clear_vmdq_generic, 3932 .init_rx_addrs = ixgbe_init_rx_addrs_generic, 3933 .update_mc_addr_list = ixgbe_update_mc_addr_list_generic, 3934 .enable_mc = ixgbe_enable_mc_generic, 3935 .disable_mc = ixgbe_disable_mc_generic, 3936 .clear_vfta = ixgbe_clear_vfta_generic, 3937 .set_vfta = ixgbe_set_vfta_generic, 3938 .fc_enable = ixgbe_fc_enable_generic, 3939 .set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550, 3940 .init_uta_tables = ixgbe_init_uta_tables_generic, 3941 .set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing, 3942 .set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing, 3943 .set_source_address_pruning = 3944 ixgbe_set_source_address_pruning_x550, 3945 .set_ethertype_anti_spoofing = 3946 ixgbe_set_ethertype_anti_spoofing_x550, 3947 .disable_rx_buff = ixgbe_disable_rx_buff_generic, 3948 .enable_rx_buff = ixgbe_enable_rx_buff_generic, 3949 .enable_rx = ixgbe_enable_rx_generic, 3950 .disable_rx = ixgbe_disable_rx_e610, 3951 .led_on = ixgbe_led_on_generic, 3952 .led_off = ixgbe_led_off_generic, 3953 .init_led_link_act = ixgbe_init_led_link_act_generic, 3954 .reset_hw = ixgbe_reset_hw_e610, 3955 .get_fw_ver = ixgbe_aci_get_fw_ver, 3956 .get_media_type = ixgbe_get_media_type_e610, 3957 .setup_link = ixgbe_setup_link_e610, 3958 .fw_recovery_mode = ixgbe_fw_recovery_mode_e610, 3959 .fw_rollback_mode = ixgbe_fw_rollback_mode_e610, 3960 .get_nvm_ver = ixgbe_get_active_nvm_ver, 3961 .get_link_capabilities = ixgbe_get_link_capabilities_e610, 3962 .get_bus_info = ixgbe_get_bus_info_generic, 3963 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540, 3964 .release_swfw_sync = ixgbe_release_swfw_sync_X540, 3965 .init_swfw_sync = ixgbe_init_swfw_sync_X540, 3966 .prot_autoc_read = prot_autoc_read_generic, 3967 .prot_autoc_write = prot_autoc_write_generic, 3968 .setup_fc = ixgbe_setup_fc_e610, 3969 .fc_autoneg = ixgbe_fc_autoneg_e610, 3970 .enable_mdd = ixgbe_enable_mdd_x550, 3971 .disable_mdd = ixgbe_disable_mdd_x550, 3972 .restore_mdd_vf = ixgbe_restore_mdd_vf_x550, 3973 .handle_mdd = ixgbe_handle_mdd_x550, 3974 }; 3975 3976 static const struct ixgbe_phy_operations phy_ops_e610 = { 3977 .init = ixgbe_init_phy_ops_e610, 3978 .identify = ixgbe_identify_phy_e610, 3979 .identify_sfp = ixgbe_identify_module_e610, 3980 .setup_link_speed = ixgbe_setup_phy_link_speed_generic, 3981 .setup_link = ixgbe_setup_phy_link_e610, 3982 .enter_lplu = ixgbe_enter_lplu_e610, 3983 }; 3984 3985 static const struct ixgbe_eeprom_operations eeprom_ops_e610 = { 3986 .read = ixgbe_read_ee_aci_e610, 3987 .read_buffer = ixgbe_read_ee_aci_buffer_e610, 3988 .validate_checksum = ixgbe_validate_eeprom_checksum_e610, 3989 .read_pba_string = ixgbe_read_pba_string_e610, 3990 .init_params = ixgbe_init_eeprom_params_e610, 3991 }; 3992 3993 const struct ixgbe_info ixgbe_e610_info = { 3994 .mac = ixgbe_mac_e610, 3995 .get_invariants = ixgbe_get_invariants_X540, 3996 .mac_ops = &mac_ops_e610, 3997 .eeprom_ops = &eeprom_ops_e610, 3998 .phy_ops = &phy_ops_e610, 3999 .mbx_ops = &mbx_ops_generic, 4000 .mvals = ixgbe_mvals_x550em_a, 4001 }; 4002