1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /******************************************************************************* 3 4 Intel 10 Gigabit PCI Express Linux driver 5 Copyright(c) 1999 - 2013 Intel Corporation. 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Contact Information: 24 Linux NICS <linux.nics@intel.com> 25 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 26 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 27 28 *******************************************************************************/ 29 30 #ifndef _DCB_82599_CONFIG_H_ 31 #define _DCB_82599_CONFIG_H_ 32 33 /* DCB register definitions */ 34 #define IXGBE_RTTDCS_TDPAC 0x00000001 /* 0 Round Robin, 35 * 1 WSP - Weighted Strict Priority 36 */ 37 #define IXGBE_RTTDCS_VMPAC 0x00000002 /* 0 Round Robin, 38 * 1 WRR - Weighted Round Robin 39 */ 40 #define IXGBE_RTTDCS_TDRM 0x00000010 /* Transmit Recycle Mode */ 41 #define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */ 42 #define IXGBE_RTTDCS_BDPM 0x00400000 /* Bypass Data Pipe - must clear! */ 43 #define IXGBE_RTTDCS_BPBFSM 0x00800000 /* Bypass PB Free Space - must 44 * clear! 45 */ 46 #define IXGBE_RTTDCS_SPEED_CHG 0x80000000 /* Link speed change */ 47 48 /* Receive UP2TC mapping */ 49 #define IXGBE_RTRUP2TC_UP_SHIFT 3 50 #define IXGBE_RTRUP2TC_UP_MASK 7 51 /* Transmit UP2TC mapping */ 52 #define IXGBE_RTTUP2TC_UP_SHIFT 3 53 54 #define IXGBE_RTRPT4C_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */ 55 #define IXGBE_RTRPT4C_BWG_SHIFT 9 /* Offset to BWG index */ 56 #define IXGBE_RTRPT4C_GSP 0x40000000 /* GSP enable bit */ 57 #define IXGBE_RTRPT4C_LSP 0x80000000 /* LSP enable bit */ 58 59 #define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet 60 * buffers enable 61 */ 62 #define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores 63 * (RSS) enable 64 */ 65 66 /* RTRPCS Bit Masks */ 67 #define IXGBE_RTRPCS_RRM 0x00000002 /* Receive Recycle Mode enable */ 68 /* Receive Arbitration Control: 0 Round Robin, 1 DFP */ 69 #define IXGBE_RTRPCS_RAC 0x00000004 70 #define IXGBE_RTRPCS_ARBDIS 0x00000040 /* Arbitration disable bit */ 71 72 /* RTTDT2C Bit Masks */ 73 #define IXGBE_RTTDT2C_MCL_SHIFT 12 74 #define IXGBE_RTTDT2C_BWG_SHIFT 9 75 #define IXGBE_RTTDT2C_GSP 0x40000000 76 #define IXGBE_RTTDT2C_LSP 0x80000000 77 78 #define IXGBE_RTTPT2C_MCL_SHIFT 12 79 #define IXGBE_RTTPT2C_BWG_SHIFT 9 80 #define IXGBE_RTTPT2C_GSP 0x40000000 81 #define IXGBE_RTTPT2C_LSP 0x80000000 82 83 /* RTTPCS Bit Masks */ 84 #define IXGBE_RTTPCS_TPPAC 0x00000020 /* 0 Round Robin, 85 * 1 SP - Strict Priority 86 */ 87 #define IXGBE_RTTPCS_ARBDIS 0x00000040 /* Arbiter disable */ 88 #define IXGBE_RTTPCS_TPRM 0x00000100 /* Transmit Recycle Mode enable */ 89 #define IXGBE_RTTPCS_ARBD_SHIFT 22 90 #define IXGBE_RTTPCS_ARBD_DCB 0x4 /* Arbitration delay in DCB mode */ 91 92 /* SECTXMINIFG DCB */ 93 #define IXGBE_SECTX_DCB 0x00001F00 /* DCB TX Buffer IFG */ 94 95 96 /* DCB hardware-specific driver APIs */ 97 98 /* DCB PFC functions */ 99 s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc); 100 101 /* DCB hw initialization */ 102 s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw, 103 u16 *refill, 104 u16 *max, 105 u8 *bwg_id, 106 u8 *prio_type, 107 u8 *prio_tc); 108 109 s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, 110 u16 *refill, 111 u16 *max, 112 u8 *bwg_id, 113 u8 *prio_type); 114 115 s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, 116 u16 *refill, 117 u16 *max, 118 u8 *bwg_id, 119 u8 *prio_type, 120 u8 *prio_tc); 121 122 s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill, 123 u16 *max, u8 *bwg_id, u8 *prio_type, 124 u8 *prio_tc); 125 126 #endif /* _DCB_82599_CONFIG_H */ 127