1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include "ixgbe.h" 30 #include "ixgbe_type.h" 31 #include "ixgbe_dcb.h" 32 #include "ixgbe_dcb_82598.h" 33 34 /** 35 * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter 36 * @hw: pointer to hardware structure 37 * @refill: refill credits index by traffic class 38 * @max: max credits index by traffic class 39 * @prio_type: priority type indexed by traffic class 40 * 41 * Configure Rx Data Arbiter and credits for each traffic class. 42 */ 43 s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, 44 u16 *refill, 45 u16 *max, 46 u8 *prio_type) 47 { 48 u32 reg = 0; 49 u32 credit_refill = 0; 50 u32 credit_max = 0; 51 u8 i = 0; 52 53 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; 54 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); 55 56 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 57 /* Enable Arbiter */ 58 reg &= ~IXGBE_RMCS_ARBDIS; 59 /* Enable Receive Recycle within the BWG */ 60 reg |= IXGBE_RMCS_RRM; 61 /* Enable Deficit Fixed Priority arbitration*/ 62 reg |= IXGBE_RMCS_DFP; 63 64 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); 65 66 /* Configure traffic class credits and priority */ 67 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 68 credit_refill = refill[i]; 69 credit_max = max[i]; 70 71 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); 72 73 if (prio_type[i] == prio_link) 74 reg |= IXGBE_RT2CR_LSP; 75 76 IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg); 77 } 78 79 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 80 reg |= IXGBE_RDRXCTL_RDMTS_1_2; 81 reg |= IXGBE_RDRXCTL_MPBEN; 82 reg |= IXGBE_RDRXCTL_MCEN; 83 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 84 85 reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 86 /* Make sure there is enough descriptors before arbitration */ 87 reg &= ~IXGBE_RXCTRL_DMBYPS; 88 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg); 89 90 return 0; 91 } 92 93 /** 94 * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter 95 * @hw: pointer to hardware structure 96 * @refill: refill credits index by traffic class 97 * @max: max credits index by traffic class 98 * @bwg_id: bandwidth grouping indexed by traffic class 99 * @prio_type: priority type indexed by traffic class 100 * 101 * Configure Tx Descriptor Arbiter and credits for each traffic class. 102 */ 103 s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw, 104 u16 *refill, 105 u16 *max, 106 u8 *bwg_id, 107 u8 *prio_type) 108 { 109 u32 reg, max_credits; 110 u8 i; 111 112 reg = IXGBE_READ_REG(hw, IXGBE_DPMCS); 113 114 /* Enable arbiter */ 115 reg &= ~IXGBE_DPMCS_ARBDIS; 116 reg |= IXGBE_DPMCS_TSOEF; 117 118 /* Configure Max TSO packet size 34KB including payload and headers */ 119 reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT); 120 121 IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg); 122 123 /* Configure traffic class credits and priority */ 124 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 125 max_credits = max[i]; 126 reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT; 127 reg |= refill[i]; 128 reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT; 129 130 if (prio_type[i] == prio_group) 131 reg |= IXGBE_TDTQ2TCCR_GSP; 132 133 if (prio_type[i] == prio_link) 134 reg |= IXGBE_TDTQ2TCCR_LSP; 135 136 IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg); 137 } 138 139 return 0; 140 } 141 142 /** 143 * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter 144 * @hw: pointer to hardware structure 145 * @refill: refill credits index by traffic class 146 * @max: max credits index by traffic class 147 * @bwg_id: bandwidth grouping indexed by traffic class 148 * @prio_type: priority type indexed by traffic class 149 * 150 * Configure Tx Data Arbiter and credits for each traffic class. 151 */ 152 s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw, 153 u16 *refill, 154 u16 *max, 155 u8 *bwg_id, 156 u8 *prio_type) 157 { 158 u32 reg; 159 u8 i; 160 161 reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS); 162 /* Enable Data Plane Arbiter */ 163 reg &= ~IXGBE_PDPMCS_ARBDIS; 164 /* Enable DFP and Transmit Recycle Mode */ 165 reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM); 166 167 IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg); 168 169 /* Configure traffic class credits and priority */ 170 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 171 reg = refill[i]; 172 reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT; 173 reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT; 174 175 if (prio_type[i] == prio_group) 176 reg |= IXGBE_TDPT2TCCR_GSP; 177 178 if (prio_type[i] == prio_link) 179 reg |= IXGBE_TDPT2TCCR_LSP; 180 181 IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg); 182 } 183 184 /* Enable Tx packet buffer division */ 185 reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL); 186 reg |= IXGBE_DTXCTL_ENDBUBD; 187 IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg); 188 189 return 0; 190 } 191 192 /** 193 * ixgbe_dcb_config_pfc_82598 - Config priority flow control 194 * @hw: pointer to hardware structure 195 * @pfc_en: enabled pfc bitmask 196 * 197 * Configure Priority Flow Control for each traffic class. 198 */ 199 s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en) 200 { 201 u32 fcrtl, reg; 202 u8 i; 203 204 /* Enable Transmit Priority Flow Control */ 205 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 206 reg &= ~IXGBE_RMCS_TFCE_802_3X; 207 reg |= IXGBE_RMCS_TFCE_PRIORITY; 208 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); 209 210 /* Enable Receive Priority Flow Control */ 211 reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 212 reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE); 213 214 if (pfc_en) 215 reg |= IXGBE_FCTRL_RPFCE; 216 217 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg); 218 219 /* Configure PFC Tx thresholds per TC */ 220 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 221 if (!(pfc_en & BIT(i))) { 222 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0); 223 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0); 224 continue; 225 } 226 227 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 228 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 229 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl); 230 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg); 231 } 232 233 /* Configure pause time */ 234 reg = hw->fc.pause_time * 0x00010001; 235 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) 236 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 237 238 /* Configure flow control refresh threshold value */ 239 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 240 241 242 return 0; 243 } 244 245 /** 246 * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics 247 * @hw: pointer to hardware structure 248 * 249 * Configure queue statistics registers, all queues belonging to same traffic 250 * class uses a single set of queue statistics counters. 251 */ 252 static s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw) 253 { 254 u32 reg = 0; 255 u8 i = 0; 256 u8 j = 0; 257 258 /* Receive Queues stats setting - 8 queues per statistics reg */ 259 for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) { 260 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i)); 261 reg |= ((0x1010101) * j); 262 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); 263 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1)); 264 reg |= ((0x1010101) * j); 265 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg); 266 } 267 /* Transmit Queues stats setting - 4 queues per statistics reg */ 268 for (i = 0; i < 8; i++) { 269 reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i)); 270 reg |= ((0x1010101) * i); 271 IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg); 272 } 273 274 return 0; 275 } 276 277 /** 278 * ixgbe_dcb_hw_config_82598 - Config and enable DCB 279 * @hw: pointer to hardware structure 280 * @pfc_en: enabled pfc bitmask 281 * @refill: refill credits index by traffic class 282 * @max: max credits index by traffic class 283 * @bwg_id: bandwidth grouping indexed by traffic class 284 * @prio_type: priority type indexed by traffic class 285 * 286 * Configure dcb settings and enable dcb mode. 287 */ 288 s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill, 289 u16 *max, u8 *bwg_id, u8 *prio_type) 290 { 291 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, prio_type); 292 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, 293 bwg_id, prio_type); 294 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, 295 bwg_id, prio_type); 296 ixgbe_dcb_config_pfc_82598(hw, pfc_en); 297 ixgbe_dcb_config_tc_stats_82598(hw); 298 299 return 0; 300 } 301