1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 30 #include "ixgbe.h" 31 #include "ixgbe_type.h" 32 #include "ixgbe_dcb.h" 33 #include "ixgbe_dcb_82598.h" 34 #include "ixgbe_dcb_82599.h" 35 36 /** 37 * ixgbe_ieee_credits - This calculates the ieee traffic class 38 * credits from the configured bandwidth percentages. Credits 39 * are the smallest unit programmable into the underlying 40 * hardware. The IEEE 802.1Qaz specification do not use bandwidth 41 * groups so this is much simplified from the CEE case. 42 */ 43 static s32 ixgbe_ieee_credits(__u8 *bw, __u16 *refill, 44 __u16 *max, int max_frame) 45 { 46 int min_percent = 100; 47 int min_credit, multiplier; 48 int i; 49 50 min_credit = ((max_frame / 2) + DCB_CREDIT_QUANTUM - 1) / 51 DCB_CREDIT_QUANTUM; 52 53 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 54 if (bw[i] < min_percent && bw[i]) 55 min_percent = bw[i]; 56 } 57 58 multiplier = (min_credit / min_percent) + 1; 59 60 /* Find out the hw credits for each TC */ 61 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 62 int val = min(bw[i] * multiplier, MAX_CREDIT_REFILL); 63 64 if (val < min_credit) 65 val = min_credit; 66 refill[i] = val; 67 68 max[i] = bw[i] ? (bw[i] * MAX_CREDIT)/100 : min_credit; 69 } 70 return 0; 71 } 72 73 /** 74 * ixgbe_dcb_calculate_tc_credits - Calculates traffic class credits 75 * @ixgbe_dcb_config: Struct containing DCB settings. 76 * @direction: Configuring either Tx or Rx. 77 * 78 * This function calculates the credits allocated to each traffic class. 79 * It should be called only after the rules are checked by 80 * ixgbe_dcb_check_config(). 81 */ 82 s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_hw *hw, 83 struct ixgbe_dcb_config *dcb_config, 84 int max_frame, u8 direction) 85 { 86 struct tc_bw_alloc *p; 87 int min_credit; 88 int min_multiplier; 89 int min_percent = 100; 90 /* Initialization values default for Tx settings */ 91 u32 credit_refill = 0; 92 u32 credit_max = 0; 93 u16 link_percentage = 0; 94 u8 bw_percent = 0; 95 u8 i; 96 97 if (!dcb_config) 98 return DCB_ERR_CONFIG; 99 100 min_credit = ((max_frame / 2) + DCB_CREDIT_QUANTUM - 1) / 101 DCB_CREDIT_QUANTUM; 102 103 /* Find smallest link percentage */ 104 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 105 p = &dcb_config->tc_config[i].path[direction]; 106 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id]; 107 link_percentage = p->bwg_percent; 108 109 link_percentage = (link_percentage * bw_percent) / 100; 110 111 if (link_percentage && link_percentage < min_percent) 112 min_percent = link_percentage; 113 } 114 115 /* 116 * The ratio between traffic classes will control the bandwidth 117 * percentages seen on the wire. To calculate this ratio we use 118 * a multiplier. It is required that the refill credits must be 119 * larger than the max frame size so here we find the smallest 120 * multiplier that will allow all bandwidth percentages to be 121 * greater than the max frame size. 122 */ 123 min_multiplier = (min_credit / min_percent) + 1; 124 125 /* Find out the link percentage for each TC first */ 126 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 127 p = &dcb_config->tc_config[i].path[direction]; 128 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id]; 129 130 link_percentage = p->bwg_percent; 131 /* Must be careful of integer division for very small nums */ 132 link_percentage = (link_percentage * bw_percent) / 100; 133 if (p->bwg_percent > 0 && link_percentage == 0) 134 link_percentage = 1; 135 136 /* Save link_percentage for reference */ 137 p->link_percent = (u8)link_percentage; 138 139 /* Calculate credit refill ratio using multiplier */ 140 credit_refill = min(link_percentage * min_multiplier, 141 MAX_CREDIT_REFILL); 142 p->data_credits_refill = (u16)credit_refill; 143 144 /* Calculate maximum credit for the TC */ 145 credit_max = (link_percentage * MAX_CREDIT) / 100; 146 147 /* 148 * Adjustment based on rule checking, if the percentage 149 * of a TC is too small, the maximum credit may not be 150 * enough to send out a jumbo frame in data plane arbitration. 151 */ 152 if (credit_max && (credit_max < min_credit)) 153 credit_max = min_credit; 154 155 if (direction == DCB_TX_CONFIG) { 156 /* 157 * Adjustment based on rule checking, if the 158 * percentage of a TC is too small, the maximum 159 * credit may not be enough to send out a TSO 160 * packet in descriptor plane arbitration. 161 */ 162 if ((hw->mac.type == ixgbe_mac_82598EB) && 163 credit_max && 164 (credit_max < MINIMUM_CREDIT_FOR_TSO)) 165 credit_max = MINIMUM_CREDIT_FOR_TSO; 166 167 dcb_config->tc_config[i].desc_credits_max = 168 (u16)credit_max; 169 } 170 171 p->data_credits_max = (u16)credit_max; 172 } 173 174 return 0; 175 } 176 177 void ixgbe_dcb_unpack_pfc(struct ixgbe_dcb_config *cfg, u8 *pfc_en) 178 { 179 struct tc_configuration *tc_config = &cfg->tc_config[0]; 180 int tc; 181 182 for (*pfc_en = 0, tc = 0; tc < MAX_TRAFFIC_CLASS; tc++) { 183 if (tc_config[tc].dcb_pfc != pfc_disabled) 184 *pfc_en |= 1 << tc; 185 } 186 } 187 188 void ixgbe_dcb_unpack_refill(struct ixgbe_dcb_config *cfg, int direction, 189 u16 *refill) 190 { 191 struct tc_configuration *tc_config = &cfg->tc_config[0]; 192 int tc; 193 194 for (tc = 0; tc < MAX_TRAFFIC_CLASS; tc++) 195 refill[tc] = tc_config[tc].path[direction].data_credits_refill; 196 } 197 198 void ixgbe_dcb_unpack_max(struct ixgbe_dcb_config *cfg, u16 *max) 199 { 200 struct tc_configuration *tc_config = &cfg->tc_config[0]; 201 int tc; 202 203 for (tc = 0; tc < MAX_TRAFFIC_CLASS; tc++) 204 max[tc] = tc_config[tc].desc_credits_max; 205 } 206 207 void ixgbe_dcb_unpack_bwgid(struct ixgbe_dcb_config *cfg, int direction, 208 u8 *bwgid) 209 { 210 struct tc_configuration *tc_config = &cfg->tc_config[0]; 211 int tc; 212 213 for (tc = 0; tc < MAX_TRAFFIC_CLASS; tc++) 214 bwgid[tc] = tc_config[tc].path[direction].bwg_id; 215 } 216 217 void ixgbe_dcb_unpack_prio(struct ixgbe_dcb_config *cfg, int direction, 218 u8 *ptype) 219 { 220 struct tc_configuration *tc_config = &cfg->tc_config[0]; 221 int tc; 222 223 for (tc = 0; tc < MAX_TRAFFIC_CLASS; tc++) 224 ptype[tc] = tc_config[tc].path[direction].prio_type; 225 } 226 227 u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *cfg, int direction, u8 up) 228 { 229 struct tc_configuration *tc_config = &cfg->tc_config[0]; 230 u8 prio_mask = 1 << up; 231 u8 tc = cfg->num_tcs.pg_tcs; 232 233 /* If tc is 0 then DCB is likely not enabled or supported */ 234 if (!tc) 235 return 0; 236 237 /* 238 * Test from maximum TC to 1 and report the first match we find. If 239 * we find no match we can assume that the TC is 0 since the TC must 240 * be set for all user priorities 241 */ 242 for (tc--; tc; tc--) { 243 if (prio_mask & tc_config[tc].path[direction].up_to_tc_bitmap) 244 break; 245 } 246 247 return tc; 248 } 249 250 void ixgbe_dcb_unpack_map(struct ixgbe_dcb_config *cfg, int direction, u8 *map) 251 { 252 u8 up; 253 254 for (up = 0; up < MAX_USER_PRIORITY; up++) 255 map[up] = ixgbe_dcb_get_tc_from_up(cfg, direction, up); 256 } 257 258 /** 259 * ixgbe_dcb_hw_config - Config and enable DCB 260 * @hw: pointer to hardware structure 261 * @dcb_config: pointer to ixgbe_dcb_config structure 262 * 263 * Configure dcb settings and enable dcb mode. 264 */ 265 s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, 266 struct ixgbe_dcb_config *dcb_config) 267 { 268 u8 pfc_en; 269 u8 ptype[MAX_TRAFFIC_CLASS]; 270 u8 bwgid[MAX_TRAFFIC_CLASS]; 271 u8 prio_tc[MAX_TRAFFIC_CLASS]; 272 u16 refill[MAX_TRAFFIC_CLASS]; 273 u16 max[MAX_TRAFFIC_CLASS]; 274 275 /* Unpack CEE standard containers */ 276 ixgbe_dcb_unpack_pfc(dcb_config, &pfc_en); 277 ixgbe_dcb_unpack_refill(dcb_config, DCB_TX_CONFIG, refill); 278 ixgbe_dcb_unpack_max(dcb_config, max); 279 ixgbe_dcb_unpack_bwgid(dcb_config, DCB_TX_CONFIG, bwgid); 280 ixgbe_dcb_unpack_prio(dcb_config, DCB_TX_CONFIG, ptype); 281 ixgbe_dcb_unpack_map(dcb_config, DCB_TX_CONFIG, prio_tc); 282 283 switch (hw->mac.type) { 284 case ixgbe_mac_82598EB: 285 return ixgbe_dcb_hw_config_82598(hw, pfc_en, refill, max, 286 bwgid, ptype); 287 case ixgbe_mac_82599EB: 288 case ixgbe_mac_X540: 289 case ixgbe_mac_X550: 290 case ixgbe_mac_X550EM_x: 291 return ixgbe_dcb_hw_config_82599(hw, pfc_en, refill, max, 292 bwgid, ptype, prio_tc); 293 default: 294 break; 295 } 296 return 0; 297 } 298 299 /* Helper routines to abstract HW specifics from DCB netlink ops */ 300 s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc) 301 { 302 switch (hw->mac.type) { 303 case ixgbe_mac_82598EB: 304 return ixgbe_dcb_config_pfc_82598(hw, pfc_en); 305 case ixgbe_mac_82599EB: 306 case ixgbe_mac_X540: 307 case ixgbe_mac_X550: 308 case ixgbe_mac_X550EM_x: 309 return ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc); 310 default: 311 break; 312 } 313 return -EINVAL; 314 } 315 316 s32 ixgbe_dcb_hw_ets(struct ixgbe_hw *hw, struct ieee_ets *ets, int max_frame) 317 { 318 __u16 refill[IEEE_8021QAZ_MAX_TCS], max[IEEE_8021QAZ_MAX_TCS]; 319 __u8 prio_type[IEEE_8021QAZ_MAX_TCS]; 320 int i; 321 322 /* naively give each TC a bwg to map onto CEE hardware */ 323 __u8 bwg_id[IEEE_8021QAZ_MAX_TCS] = {0, 1, 2, 3, 4, 5, 6, 7}; 324 325 /* Map TSA onto CEE prio type */ 326 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 327 switch (ets->tc_tsa[i]) { 328 case IEEE_8021QAZ_TSA_STRICT: 329 prio_type[i] = 2; 330 break; 331 case IEEE_8021QAZ_TSA_ETS: 332 prio_type[i] = 0; 333 break; 334 default: 335 /* Hardware only supports priority strict or 336 * ETS transmission selection algorithms if 337 * we receive some other value from dcbnl 338 * throw an error 339 */ 340 return -EINVAL; 341 } 342 } 343 344 ixgbe_ieee_credits(ets->tc_tx_bw, refill, max, max_frame); 345 return ixgbe_dcb_hw_ets_config(hw, refill, max, 346 bwg_id, prio_type, ets->prio_tc); 347 } 348 349 s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw, 350 u16 *refill, u16 *max, u8 *bwg_id, 351 u8 *prio_type, u8 *prio_tc) 352 { 353 switch (hw->mac.type) { 354 case ixgbe_mac_82598EB: 355 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, 356 prio_type); 357 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, 358 bwg_id, prio_type); 359 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, 360 bwg_id, prio_type); 361 break; 362 case ixgbe_mac_82599EB: 363 case ixgbe_mac_X540: 364 case ixgbe_mac_X550: 365 case ixgbe_mac_X550EM_x: 366 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, 367 bwg_id, prio_type, prio_tc); 368 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, 369 bwg_id, prio_type); 370 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id, 371 prio_type, prio_tc); 372 break; 373 default: 374 break; 375 } 376 return 0; 377 } 378 379 static void ixgbe_dcb_read_rtrup2tc_82599(struct ixgbe_hw *hw, u8 *map) 380 { 381 u32 reg, i; 382 383 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 384 for (i = 0; i < MAX_USER_PRIORITY; i++) 385 map[i] = IXGBE_RTRUP2TC_UP_MASK & 386 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT)); 387 } 388 389 void ixgbe_dcb_read_rtrup2tc(struct ixgbe_hw *hw, u8 *map) 390 { 391 switch (hw->mac.type) { 392 case ixgbe_mac_82599EB: 393 case ixgbe_mac_X540: 394 case ixgbe_mac_X550: 395 case ixgbe_mac_X550EM_x: 396 ixgbe_dcb_read_rtrup2tc_82599(hw, map); 397 break; 398 default: 399 break; 400 } 401 } 402