1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2016 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/pci.h> 30 #include <linux/delay.h> 31 #include <linux/sched.h> 32 #include <linux/netdevice.h> 33 34 #include "ixgbe.h" 35 #include "ixgbe_common.h" 36 #include "ixgbe_phy.h" 37 38 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 39 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 40 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 41 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 42 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 43 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 44 u16 count); 45 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 46 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 47 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 48 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 49 50 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 51 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg); 52 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 53 u16 words, u16 *data); 54 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 55 u16 words, u16 *data); 56 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 57 u16 offset); 58 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw); 59 60 /* Base table for registers values that change by MAC */ 61 const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT] = { 62 IXGBE_MVALS_INIT(8259X) 63 }; 64 65 /** 66 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow 67 * control 68 * @hw: pointer to hardware structure 69 * 70 * There are several phys that do not support autoneg flow control. This 71 * function check the device id to see if the associated phy supports 72 * autoneg flow control. 73 **/ 74 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 75 { 76 bool supported = false; 77 ixgbe_link_speed speed; 78 bool link_up; 79 80 switch (hw->phy.media_type) { 81 case ixgbe_media_type_fiber: 82 /* flow control autoneg black list */ 83 switch (hw->device_id) { 84 case IXGBE_DEV_ID_X550EM_A_SFP: 85 case IXGBE_DEV_ID_X550EM_A_SFP_N: 86 supported = false; 87 break; 88 default: 89 hw->mac.ops.check_link(hw, &speed, &link_up, false); 90 /* if link is down, assume supported */ 91 if (link_up) 92 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ? 93 true : false; 94 else 95 supported = true; 96 } 97 98 break; 99 case ixgbe_media_type_backplane: 100 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI) 101 supported = false; 102 else 103 supported = true; 104 break; 105 case ixgbe_media_type_copper: 106 /* only some copper devices support flow control autoneg */ 107 switch (hw->device_id) { 108 case IXGBE_DEV_ID_82599_T3_LOM: 109 case IXGBE_DEV_ID_X540T: 110 case IXGBE_DEV_ID_X540T1: 111 case IXGBE_DEV_ID_X550T: 112 case IXGBE_DEV_ID_X550T1: 113 case IXGBE_DEV_ID_X550EM_X_10G_T: 114 case IXGBE_DEV_ID_X550EM_A_10G_T: 115 case IXGBE_DEV_ID_X550EM_A_1G_T: 116 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 117 supported = true; 118 break; 119 default: 120 break; 121 } 122 default: 123 break; 124 } 125 126 if (!supported) 127 hw_dbg(hw, "Device %x does not support flow control autoneg\n", 128 hw->device_id); 129 130 return supported; 131 } 132 133 /** 134 * ixgbe_setup_fc_generic - Set up flow control 135 * @hw: pointer to hardware structure 136 * 137 * Called at init time to set up flow control. 138 **/ 139 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw) 140 { 141 s32 ret_val = 0; 142 u32 reg = 0, reg_bp = 0; 143 u16 reg_cu = 0; 144 bool locked = false; 145 146 /* 147 * Validate the requested mode. Strict IEEE mode does not allow 148 * ixgbe_fc_rx_pause because it will cause us to fail at UNH. 149 */ 150 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 151 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 152 return IXGBE_ERR_INVALID_LINK_SETTINGS; 153 } 154 155 /* 156 * 10gig parts do not have a word in the EEPROM to determine the 157 * default flow control setting, so we explicitly set it to full. 158 */ 159 if (hw->fc.requested_mode == ixgbe_fc_default) 160 hw->fc.requested_mode = ixgbe_fc_full; 161 162 /* 163 * Set up the 1G and 10G flow control advertisement registers so the 164 * HW will be able to do fc autoneg once the cable is plugged in. If 165 * we link at 10G, the 1G advertisement is harmless and vice versa. 166 */ 167 switch (hw->phy.media_type) { 168 case ixgbe_media_type_backplane: 169 /* some MAC's need RMW protection on AUTOC */ 170 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); 171 if (ret_val) 172 return ret_val; 173 174 /* fall through - only backplane uses autoc */ 175 case ixgbe_media_type_fiber: 176 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 177 178 break; 179 case ixgbe_media_type_copper: 180 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 181 MDIO_MMD_AN, ®_cu); 182 break; 183 default: 184 break; 185 } 186 187 /* 188 * The possible values of fc.requested_mode are: 189 * 0: Flow control is completely disabled 190 * 1: Rx flow control is enabled (we can receive pause frames, 191 * but not send pause frames). 192 * 2: Tx flow control is enabled (we can send pause frames but 193 * we do not support receiving pause frames). 194 * 3: Both Rx and Tx flow control (symmetric) are enabled. 195 * other: Invalid. 196 */ 197 switch (hw->fc.requested_mode) { 198 case ixgbe_fc_none: 199 /* Flow control completely disabled by software override. */ 200 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 201 if (hw->phy.media_type == ixgbe_media_type_backplane) 202 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 203 IXGBE_AUTOC_ASM_PAUSE); 204 else if (hw->phy.media_type == ixgbe_media_type_copper) 205 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 206 break; 207 case ixgbe_fc_tx_pause: 208 /* 209 * Tx Flow control is enabled, and Rx Flow control is 210 * disabled by software override. 211 */ 212 reg |= IXGBE_PCS1GANA_ASM_PAUSE; 213 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; 214 if (hw->phy.media_type == ixgbe_media_type_backplane) { 215 reg_bp |= IXGBE_AUTOC_ASM_PAUSE; 216 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; 217 } else if (hw->phy.media_type == ixgbe_media_type_copper) { 218 reg_cu |= IXGBE_TAF_ASM_PAUSE; 219 reg_cu &= ~IXGBE_TAF_SYM_PAUSE; 220 } 221 break; 222 case ixgbe_fc_rx_pause: 223 /* 224 * Rx Flow control is enabled and Tx Flow control is 225 * disabled by software override. Since there really 226 * isn't a way to advertise that we are capable of RX 227 * Pause ONLY, we will advertise that we support both 228 * symmetric and asymmetric Rx PAUSE, as such we fall 229 * through to the fc_full statement. Later, we will 230 * disable the adapter's ability to send PAUSE frames. 231 */ 232 case ixgbe_fc_full: 233 /* Flow control (both Rx and Tx) is enabled by SW override. */ 234 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; 235 if (hw->phy.media_type == ixgbe_media_type_backplane) 236 reg_bp |= IXGBE_AUTOC_SYM_PAUSE | 237 IXGBE_AUTOC_ASM_PAUSE; 238 else if (hw->phy.media_type == ixgbe_media_type_copper) 239 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; 240 break; 241 default: 242 hw_dbg(hw, "Flow control param set incorrectly\n"); 243 return IXGBE_ERR_CONFIG; 244 } 245 246 if (hw->mac.type != ixgbe_mac_X540) { 247 /* 248 * Enable auto-negotiation between the MAC & PHY; 249 * the MAC will advertise clause 37 flow control. 250 */ 251 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 252 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 253 254 /* Disable AN timeout */ 255 if (hw->fc.strict_ieee) 256 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 257 258 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 259 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); 260 } 261 262 /* 263 * AUTOC restart handles negotiation of 1G and 10G on backplane 264 * and copper. There is no need to set the PCS1GCTL register. 265 * 266 */ 267 if (hw->phy.media_type == ixgbe_media_type_backplane) { 268 /* Need the SW/FW semaphore around AUTOC writes if 82599 and 269 * LESM is on, likewise reset_pipeline requries the lock as 270 * it also writes AUTOC. 271 */ 272 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); 273 if (ret_val) 274 return ret_val; 275 276 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 277 ixgbe_device_supports_autoneg_fc(hw)) { 278 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 279 MDIO_MMD_AN, reg_cu); 280 } 281 282 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); 283 return ret_val; 284 } 285 286 /** 287 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 288 * @hw: pointer to hardware structure 289 * 290 * Starts the hardware by filling the bus info structure and media type, clears 291 * all on chip counters, initializes receive address registers, multicast 292 * table, VLAN filter table, calls routine to set up link and flow control 293 * settings, and leaves transmit and receive units disabled and uninitialized 294 **/ 295 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 296 { 297 s32 ret_val; 298 u32 ctrl_ext; 299 u16 device_caps; 300 301 /* Set the media type */ 302 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 303 304 /* Identify the PHY */ 305 hw->phy.ops.identify(hw); 306 307 /* Clear the VLAN filter table */ 308 hw->mac.ops.clear_vfta(hw); 309 310 /* Clear statistics registers */ 311 hw->mac.ops.clear_hw_cntrs(hw); 312 313 /* Set No Snoop Disable */ 314 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 315 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 316 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 317 IXGBE_WRITE_FLUSH(hw); 318 319 /* Setup flow control if method for doing so */ 320 if (hw->mac.ops.setup_fc) { 321 ret_val = hw->mac.ops.setup_fc(hw); 322 if (ret_val) 323 return ret_val; 324 } 325 326 /* Cashe bit indicating need for crosstalk fix */ 327 switch (hw->mac.type) { 328 case ixgbe_mac_82599EB: 329 case ixgbe_mac_X550EM_x: 330 case ixgbe_mac_x550em_a: 331 hw->mac.ops.get_device_caps(hw, &device_caps); 332 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR) 333 hw->need_crosstalk_fix = false; 334 else 335 hw->need_crosstalk_fix = true; 336 break; 337 default: 338 hw->need_crosstalk_fix = false; 339 break; 340 } 341 342 /* Clear adapter stopped flag */ 343 hw->adapter_stopped = false; 344 345 return 0; 346 } 347 348 /** 349 * ixgbe_start_hw_gen2 - Init sequence for common device family 350 * @hw: pointer to hw structure 351 * 352 * Performs the init sequence common to the second generation 353 * of 10 GbE devices. 354 * Devices in the second generation: 355 * 82599 356 * X540 357 **/ 358 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 359 { 360 u32 i; 361 362 /* Clear the rate limiters */ 363 for (i = 0; i < hw->mac.max_tx_queues; i++) { 364 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 365 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 366 } 367 IXGBE_WRITE_FLUSH(hw); 368 369 return 0; 370 } 371 372 /** 373 * ixgbe_init_hw_generic - Generic hardware initialization 374 * @hw: pointer to hardware structure 375 * 376 * Initialize the hardware by resetting the hardware, filling the bus info 377 * structure and media type, clears all on chip counters, initializes receive 378 * address registers, multicast table, VLAN filter table, calls routine to set 379 * up link and flow control settings, and leaves transmit and receive units 380 * disabled and uninitialized 381 **/ 382 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 383 { 384 s32 status; 385 386 /* Reset the hardware */ 387 status = hw->mac.ops.reset_hw(hw); 388 389 if (status == 0) { 390 /* Start the HW */ 391 status = hw->mac.ops.start_hw(hw); 392 } 393 394 /* Initialize the LED link active for LED blink support */ 395 if (hw->mac.ops.init_led_link_act) 396 hw->mac.ops.init_led_link_act(hw); 397 398 return status; 399 } 400 401 /** 402 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 403 * @hw: pointer to hardware structure 404 * 405 * Clears all hardware statistics counters by reading them from the hardware 406 * Statistics counters are clear on read. 407 **/ 408 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 409 { 410 u16 i = 0; 411 412 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 413 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 414 IXGBE_READ_REG(hw, IXGBE_ERRBC); 415 IXGBE_READ_REG(hw, IXGBE_MSPDC); 416 for (i = 0; i < 8; i++) 417 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 418 419 IXGBE_READ_REG(hw, IXGBE_MLFC); 420 IXGBE_READ_REG(hw, IXGBE_MRFC); 421 IXGBE_READ_REG(hw, IXGBE_RLEC); 422 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 423 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 424 if (hw->mac.type >= ixgbe_mac_82599EB) { 425 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 426 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 427 } else { 428 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 429 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 430 } 431 432 for (i = 0; i < 8; i++) { 433 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 434 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 435 if (hw->mac.type >= ixgbe_mac_82599EB) { 436 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 437 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 438 } else { 439 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 440 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 441 } 442 } 443 if (hw->mac.type >= ixgbe_mac_82599EB) 444 for (i = 0; i < 8; i++) 445 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 446 IXGBE_READ_REG(hw, IXGBE_PRC64); 447 IXGBE_READ_REG(hw, IXGBE_PRC127); 448 IXGBE_READ_REG(hw, IXGBE_PRC255); 449 IXGBE_READ_REG(hw, IXGBE_PRC511); 450 IXGBE_READ_REG(hw, IXGBE_PRC1023); 451 IXGBE_READ_REG(hw, IXGBE_PRC1522); 452 IXGBE_READ_REG(hw, IXGBE_GPRC); 453 IXGBE_READ_REG(hw, IXGBE_BPRC); 454 IXGBE_READ_REG(hw, IXGBE_MPRC); 455 IXGBE_READ_REG(hw, IXGBE_GPTC); 456 IXGBE_READ_REG(hw, IXGBE_GORCL); 457 IXGBE_READ_REG(hw, IXGBE_GORCH); 458 IXGBE_READ_REG(hw, IXGBE_GOTCL); 459 IXGBE_READ_REG(hw, IXGBE_GOTCH); 460 if (hw->mac.type == ixgbe_mac_82598EB) 461 for (i = 0; i < 8; i++) 462 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 463 IXGBE_READ_REG(hw, IXGBE_RUC); 464 IXGBE_READ_REG(hw, IXGBE_RFC); 465 IXGBE_READ_REG(hw, IXGBE_ROC); 466 IXGBE_READ_REG(hw, IXGBE_RJC); 467 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 468 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 469 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 470 IXGBE_READ_REG(hw, IXGBE_TORL); 471 IXGBE_READ_REG(hw, IXGBE_TORH); 472 IXGBE_READ_REG(hw, IXGBE_TPR); 473 IXGBE_READ_REG(hw, IXGBE_TPT); 474 IXGBE_READ_REG(hw, IXGBE_PTC64); 475 IXGBE_READ_REG(hw, IXGBE_PTC127); 476 IXGBE_READ_REG(hw, IXGBE_PTC255); 477 IXGBE_READ_REG(hw, IXGBE_PTC511); 478 IXGBE_READ_REG(hw, IXGBE_PTC1023); 479 IXGBE_READ_REG(hw, IXGBE_PTC1522); 480 IXGBE_READ_REG(hw, IXGBE_MPTC); 481 IXGBE_READ_REG(hw, IXGBE_BPTC); 482 for (i = 0; i < 16; i++) { 483 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 484 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 485 if (hw->mac.type >= ixgbe_mac_82599EB) { 486 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 487 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 488 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 489 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 490 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 491 } else { 492 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 493 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 494 } 495 } 496 497 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { 498 if (hw->phy.id == 0) 499 hw->phy.ops.identify(hw); 500 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i); 501 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i); 502 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i); 503 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i); 504 } 505 506 return 0; 507 } 508 509 /** 510 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 511 * @hw: pointer to hardware structure 512 * @pba_num: stores the part number string from the EEPROM 513 * @pba_num_size: part number string buffer length 514 * 515 * Reads the part number string from the EEPROM. 516 **/ 517 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 518 u32 pba_num_size) 519 { 520 s32 ret_val; 521 u16 data; 522 u16 pba_ptr; 523 u16 offset; 524 u16 length; 525 526 if (pba_num == NULL) { 527 hw_dbg(hw, "PBA string buffer was null\n"); 528 return IXGBE_ERR_INVALID_ARGUMENT; 529 } 530 531 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 532 if (ret_val) { 533 hw_dbg(hw, "NVM Read Error\n"); 534 return ret_val; 535 } 536 537 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 538 if (ret_val) { 539 hw_dbg(hw, "NVM Read Error\n"); 540 return ret_val; 541 } 542 543 /* 544 * if data is not ptr guard the PBA must be in legacy format which 545 * means pba_ptr is actually our second data word for the PBA number 546 * and we can decode it into an ascii string 547 */ 548 if (data != IXGBE_PBANUM_PTR_GUARD) { 549 hw_dbg(hw, "NVM PBA number is not stored as string\n"); 550 551 /* we will need 11 characters to store the PBA */ 552 if (pba_num_size < 11) { 553 hw_dbg(hw, "PBA string buffer too small\n"); 554 return IXGBE_ERR_NO_SPACE; 555 } 556 557 /* extract hex string from data and pba_ptr */ 558 pba_num[0] = (data >> 12) & 0xF; 559 pba_num[1] = (data >> 8) & 0xF; 560 pba_num[2] = (data >> 4) & 0xF; 561 pba_num[3] = data & 0xF; 562 pba_num[4] = (pba_ptr >> 12) & 0xF; 563 pba_num[5] = (pba_ptr >> 8) & 0xF; 564 pba_num[6] = '-'; 565 pba_num[7] = 0; 566 pba_num[8] = (pba_ptr >> 4) & 0xF; 567 pba_num[9] = pba_ptr & 0xF; 568 569 /* put a null character on the end of our string */ 570 pba_num[10] = '\0'; 571 572 /* switch all the data but the '-' to hex char */ 573 for (offset = 0; offset < 10; offset++) { 574 if (pba_num[offset] < 0xA) 575 pba_num[offset] += '0'; 576 else if (pba_num[offset] < 0x10) 577 pba_num[offset] += 'A' - 0xA; 578 } 579 580 return 0; 581 } 582 583 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 584 if (ret_val) { 585 hw_dbg(hw, "NVM Read Error\n"); 586 return ret_val; 587 } 588 589 if (length == 0xFFFF || length == 0) { 590 hw_dbg(hw, "NVM PBA number section invalid length\n"); 591 return IXGBE_ERR_PBA_SECTION; 592 } 593 594 /* check if pba_num buffer is big enough */ 595 if (pba_num_size < (((u32)length * 2) - 1)) { 596 hw_dbg(hw, "PBA string buffer too small\n"); 597 return IXGBE_ERR_NO_SPACE; 598 } 599 600 /* trim pba length from start of string */ 601 pba_ptr++; 602 length--; 603 604 for (offset = 0; offset < length; offset++) { 605 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 606 if (ret_val) { 607 hw_dbg(hw, "NVM Read Error\n"); 608 return ret_val; 609 } 610 pba_num[offset * 2] = (u8)(data >> 8); 611 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 612 } 613 pba_num[offset * 2] = '\0'; 614 615 return 0; 616 } 617 618 /** 619 * ixgbe_get_mac_addr_generic - Generic get MAC address 620 * @hw: pointer to hardware structure 621 * @mac_addr: Adapter MAC address 622 * 623 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 624 * A reset of the adapter must be performed prior to calling this function 625 * in order for the MAC address to have been loaded from the EEPROM into RAR0 626 **/ 627 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 628 { 629 u32 rar_high; 630 u32 rar_low; 631 u16 i; 632 633 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 634 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 635 636 for (i = 0; i < 4; i++) 637 mac_addr[i] = (u8)(rar_low >> (i*8)); 638 639 for (i = 0; i < 2; i++) 640 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 641 642 return 0; 643 } 644 645 enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status) 646 { 647 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 648 case IXGBE_PCI_LINK_WIDTH_1: 649 return ixgbe_bus_width_pcie_x1; 650 case IXGBE_PCI_LINK_WIDTH_2: 651 return ixgbe_bus_width_pcie_x2; 652 case IXGBE_PCI_LINK_WIDTH_4: 653 return ixgbe_bus_width_pcie_x4; 654 case IXGBE_PCI_LINK_WIDTH_8: 655 return ixgbe_bus_width_pcie_x8; 656 default: 657 return ixgbe_bus_width_unknown; 658 } 659 } 660 661 enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status) 662 { 663 switch (link_status & IXGBE_PCI_LINK_SPEED) { 664 case IXGBE_PCI_LINK_SPEED_2500: 665 return ixgbe_bus_speed_2500; 666 case IXGBE_PCI_LINK_SPEED_5000: 667 return ixgbe_bus_speed_5000; 668 case IXGBE_PCI_LINK_SPEED_8000: 669 return ixgbe_bus_speed_8000; 670 default: 671 return ixgbe_bus_speed_unknown; 672 } 673 } 674 675 /** 676 * ixgbe_get_bus_info_generic - Generic set PCI bus info 677 * @hw: pointer to hardware structure 678 * 679 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 680 **/ 681 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 682 { 683 u16 link_status; 684 685 hw->bus.type = ixgbe_bus_type_pci_express; 686 687 /* Get the negotiated link width and speed from PCI config space */ 688 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS); 689 690 hw->bus.width = ixgbe_convert_bus_width(link_status); 691 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 692 693 hw->mac.ops.set_lan_id(hw); 694 695 return 0; 696 } 697 698 /** 699 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 700 * @hw: pointer to the HW structure 701 * 702 * Determines the LAN function id by reading memory-mapped registers 703 * and swaps the port value if requested. 704 **/ 705 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 706 { 707 struct ixgbe_bus_info *bus = &hw->bus; 708 u16 ee_ctrl_4; 709 u32 reg; 710 711 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 712 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 713 bus->lan_id = bus->func; 714 715 /* check for a port swap */ 716 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); 717 if (reg & IXGBE_FACTPS_LFS) 718 bus->func ^= 0x1; 719 720 /* Get MAC instance from EEPROM for configuring CS4227 */ 721 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { 722 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); 723 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >> 724 IXGBE_EE_CTRL_4_INST_ID_SHIFT; 725 } 726 } 727 728 /** 729 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 730 * @hw: pointer to hardware structure 731 * 732 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 733 * disables transmit and receive units. The adapter_stopped flag is used by 734 * the shared code and drivers to determine if the adapter is in a stopped 735 * state and should not touch the hardware. 736 **/ 737 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 738 { 739 u32 reg_val; 740 u16 i; 741 742 /* 743 * Set the adapter_stopped flag so other driver functions stop touching 744 * the hardware 745 */ 746 hw->adapter_stopped = true; 747 748 /* Disable the receive unit */ 749 hw->mac.ops.disable_rx(hw); 750 751 /* Clear interrupt mask to stop interrupts from being generated */ 752 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 753 754 /* Clear any pending interrupts, flush previous writes */ 755 IXGBE_READ_REG(hw, IXGBE_EICR); 756 757 /* Disable the transmit unit. Each queue must be disabled. */ 758 for (i = 0; i < hw->mac.max_tx_queues; i++) 759 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 760 761 /* Disable the receive unit by stopping each queue */ 762 for (i = 0; i < hw->mac.max_rx_queues; i++) { 763 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 764 reg_val &= ~IXGBE_RXDCTL_ENABLE; 765 reg_val |= IXGBE_RXDCTL_SWFLSH; 766 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 767 } 768 769 /* flush all queues disables */ 770 IXGBE_WRITE_FLUSH(hw); 771 usleep_range(1000, 2000); 772 773 /* 774 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 775 * access and verify no pending requests 776 */ 777 return ixgbe_disable_pcie_master(hw); 778 } 779 780 /** 781 * ixgbe_init_led_link_act_generic - Store the LED index link/activity. 782 * @hw: pointer to hardware structure 783 * 784 * Store the index for the link active LED. This will be used to support 785 * blinking the LED. 786 **/ 787 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw) 788 { 789 struct ixgbe_mac_info *mac = &hw->mac; 790 u32 led_reg, led_mode; 791 u16 i; 792 793 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 794 795 /* Get LED link active from the LEDCTL register */ 796 for (i = 0; i < 4; i++) { 797 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i); 798 799 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) == 800 IXGBE_LED_LINK_ACTIVE) { 801 mac->led_link_act = i; 802 return 0; 803 } 804 } 805 806 /* If LEDCTL register does not have the LED link active set, then use 807 * known MAC defaults. 808 */ 809 switch (hw->mac.type) { 810 case ixgbe_mac_x550em_a: 811 mac->led_link_act = 0; 812 break; 813 case ixgbe_mac_X550EM_x: 814 mac->led_link_act = 1; 815 break; 816 default: 817 mac->led_link_act = 2; 818 } 819 820 return 0; 821 } 822 823 /** 824 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 825 * @hw: pointer to hardware structure 826 * @index: led number to turn on 827 **/ 828 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 829 { 830 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 831 832 if (index > 3) 833 return IXGBE_ERR_PARAM; 834 835 /* To turn on the LED, set mode to ON. */ 836 led_reg &= ~IXGBE_LED_MODE_MASK(index); 837 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 838 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 839 IXGBE_WRITE_FLUSH(hw); 840 841 return 0; 842 } 843 844 /** 845 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 846 * @hw: pointer to hardware structure 847 * @index: led number to turn off 848 **/ 849 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 850 { 851 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 852 853 if (index > 3) 854 return IXGBE_ERR_PARAM; 855 856 /* To turn off the LED, set mode to OFF. */ 857 led_reg &= ~IXGBE_LED_MODE_MASK(index); 858 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 859 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 860 IXGBE_WRITE_FLUSH(hw); 861 862 return 0; 863 } 864 865 /** 866 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 867 * @hw: pointer to hardware structure 868 * 869 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 870 * ixgbe_hw struct in order to set up EEPROM access. 871 **/ 872 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 873 { 874 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 875 u32 eec; 876 u16 eeprom_size; 877 878 if (eeprom->type == ixgbe_eeprom_uninitialized) { 879 eeprom->type = ixgbe_eeprom_none; 880 /* Set default semaphore delay to 10ms which is a well 881 * tested value */ 882 eeprom->semaphore_delay = 10; 883 /* Clear EEPROM page size, it will be initialized as needed */ 884 eeprom->word_page_size = 0; 885 886 /* 887 * Check for EEPROM present first. 888 * If not present leave as none 889 */ 890 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 891 if (eec & IXGBE_EEC_PRES) { 892 eeprom->type = ixgbe_eeprom_spi; 893 894 /* 895 * SPI EEPROM is assumed here. This code would need to 896 * change if a future EEPROM is not SPI. 897 */ 898 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 899 IXGBE_EEC_SIZE_SHIFT); 900 eeprom->word_size = BIT(eeprom_size + 901 IXGBE_EEPROM_WORD_SIZE_SHIFT); 902 } 903 904 if (eec & IXGBE_EEC_ADDR_SIZE) 905 eeprom->address_bits = 16; 906 else 907 eeprom->address_bits = 8; 908 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n", 909 eeprom->type, eeprom->word_size, eeprom->address_bits); 910 } 911 912 return 0; 913 } 914 915 /** 916 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 917 * @hw: pointer to hardware structure 918 * @offset: offset within the EEPROM to write 919 * @words: number of words 920 * @data: 16 bit word(s) to write to EEPROM 921 * 922 * Reads 16 bit word(s) from EEPROM through bit-bang method 923 **/ 924 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 925 u16 words, u16 *data) 926 { 927 s32 status; 928 u16 i, count; 929 930 hw->eeprom.ops.init_params(hw); 931 932 if (words == 0) 933 return IXGBE_ERR_INVALID_ARGUMENT; 934 935 if (offset + words > hw->eeprom.word_size) 936 return IXGBE_ERR_EEPROM; 937 938 /* 939 * The EEPROM page size cannot be queried from the chip. We do lazy 940 * initialization. It is worth to do that when we write large buffer. 941 */ 942 if ((hw->eeprom.word_page_size == 0) && 943 (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 944 ixgbe_detect_eeprom_page_size_generic(hw, offset); 945 946 /* 947 * We cannot hold synchronization semaphores for too long 948 * to avoid other entity starvation. However it is more efficient 949 * to read in bursts than synchronizing access for each word. 950 */ 951 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 952 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 953 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 954 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 955 count, &data[i]); 956 957 if (status != 0) 958 break; 959 } 960 961 return status; 962 } 963 964 /** 965 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 966 * @hw: pointer to hardware structure 967 * @offset: offset within the EEPROM to be written to 968 * @words: number of word(s) 969 * @data: 16 bit word(s) to be written to the EEPROM 970 * 971 * If ixgbe_eeprom_update_checksum is not called after this function, the 972 * EEPROM will most likely contain an invalid checksum. 973 **/ 974 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 975 u16 words, u16 *data) 976 { 977 s32 status; 978 u16 word; 979 u16 page_size; 980 u16 i; 981 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 982 983 /* Prepare the EEPROM for writing */ 984 status = ixgbe_acquire_eeprom(hw); 985 if (status) 986 return status; 987 988 if (ixgbe_ready_eeprom(hw) != 0) { 989 ixgbe_release_eeprom(hw); 990 return IXGBE_ERR_EEPROM; 991 } 992 993 for (i = 0; i < words; i++) { 994 ixgbe_standby_eeprom(hw); 995 996 /* Send the WRITE ENABLE command (8 bit opcode) */ 997 ixgbe_shift_out_eeprom_bits(hw, 998 IXGBE_EEPROM_WREN_OPCODE_SPI, 999 IXGBE_EEPROM_OPCODE_BITS); 1000 1001 ixgbe_standby_eeprom(hw); 1002 1003 /* Some SPI eeproms use the 8th address bit embedded 1004 * in the opcode 1005 */ 1006 if ((hw->eeprom.address_bits == 8) && 1007 ((offset + i) >= 128)) 1008 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1009 1010 /* Send the Write command (8-bit opcode + addr) */ 1011 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 1012 IXGBE_EEPROM_OPCODE_BITS); 1013 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1014 hw->eeprom.address_bits); 1015 1016 page_size = hw->eeprom.word_page_size; 1017 1018 /* Send the data in burst via SPI */ 1019 do { 1020 word = data[i]; 1021 word = (word >> 8) | (word << 8); 1022 ixgbe_shift_out_eeprom_bits(hw, word, 16); 1023 1024 if (page_size == 0) 1025 break; 1026 1027 /* do not wrap around page */ 1028 if (((offset + i) & (page_size - 1)) == 1029 (page_size - 1)) 1030 break; 1031 } while (++i < words); 1032 1033 ixgbe_standby_eeprom(hw); 1034 usleep_range(10000, 20000); 1035 } 1036 /* Done with writing - release the EEPROM */ 1037 ixgbe_release_eeprom(hw); 1038 1039 return 0; 1040 } 1041 1042 /** 1043 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 1044 * @hw: pointer to hardware structure 1045 * @offset: offset within the EEPROM to be written to 1046 * @data: 16 bit word to be written to the EEPROM 1047 * 1048 * If ixgbe_eeprom_update_checksum is not called after this function, the 1049 * EEPROM will most likely contain an invalid checksum. 1050 **/ 1051 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1052 { 1053 hw->eeprom.ops.init_params(hw); 1054 1055 if (offset >= hw->eeprom.word_size) 1056 return IXGBE_ERR_EEPROM; 1057 1058 return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 1059 } 1060 1061 /** 1062 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 1063 * @hw: pointer to hardware structure 1064 * @offset: offset within the EEPROM to be read 1065 * @words: number of word(s) 1066 * @data: read 16 bit words(s) from EEPROM 1067 * 1068 * Reads 16 bit word(s) from EEPROM through bit-bang method 1069 **/ 1070 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1071 u16 words, u16 *data) 1072 { 1073 s32 status; 1074 u16 i, count; 1075 1076 hw->eeprom.ops.init_params(hw); 1077 1078 if (words == 0) 1079 return IXGBE_ERR_INVALID_ARGUMENT; 1080 1081 if (offset + words > hw->eeprom.word_size) 1082 return IXGBE_ERR_EEPROM; 1083 1084 /* 1085 * We cannot hold synchronization semaphores for too long 1086 * to avoid other entity starvation. However it is more efficient 1087 * to read in bursts than synchronizing access for each word. 1088 */ 1089 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1090 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1091 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1092 1093 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 1094 count, &data[i]); 1095 1096 if (status) 1097 return status; 1098 } 1099 1100 return 0; 1101 } 1102 1103 /** 1104 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 1105 * @hw: pointer to hardware structure 1106 * @offset: offset within the EEPROM to be read 1107 * @words: number of word(s) 1108 * @data: read 16 bit word(s) from EEPROM 1109 * 1110 * Reads 16 bit word(s) from EEPROM through bit-bang method 1111 **/ 1112 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1113 u16 words, u16 *data) 1114 { 1115 s32 status; 1116 u16 word_in; 1117 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 1118 u16 i; 1119 1120 /* Prepare the EEPROM for reading */ 1121 status = ixgbe_acquire_eeprom(hw); 1122 if (status) 1123 return status; 1124 1125 if (ixgbe_ready_eeprom(hw) != 0) { 1126 ixgbe_release_eeprom(hw); 1127 return IXGBE_ERR_EEPROM; 1128 } 1129 1130 for (i = 0; i < words; i++) { 1131 ixgbe_standby_eeprom(hw); 1132 /* Some SPI eeproms use the 8th address bit embedded 1133 * in the opcode 1134 */ 1135 if ((hw->eeprom.address_bits == 8) && 1136 ((offset + i) >= 128)) 1137 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1138 1139 /* Send the READ command (opcode + addr) */ 1140 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 1141 IXGBE_EEPROM_OPCODE_BITS); 1142 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1143 hw->eeprom.address_bits); 1144 1145 /* Read the data. */ 1146 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 1147 data[i] = (word_in >> 8) | (word_in << 8); 1148 } 1149 1150 /* End this read operation */ 1151 ixgbe_release_eeprom(hw); 1152 1153 return 0; 1154 } 1155 1156 /** 1157 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 1158 * @hw: pointer to hardware structure 1159 * @offset: offset within the EEPROM to be read 1160 * @data: read 16 bit value from EEPROM 1161 * 1162 * Reads 16 bit value from EEPROM through bit-bang method 1163 **/ 1164 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1165 u16 *data) 1166 { 1167 hw->eeprom.ops.init_params(hw); 1168 1169 if (offset >= hw->eeprom.word_size) 1170 return IXGBE_ERR_EEPROM; 1171 1172 return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1173 } 1174 1175 /** 1176 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 1177 * @hw: pointer to hardware structure 1178 * @offset: offset of word in the EEPROM to read 1179 * @words: number of word(s) 1180 * @data: 16 bit word(s) from the EEPROM 1181 * 1182 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 1183 **/ 1184 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1185 u16 words, u16 *data) 1186 { 1187 u32 eerd; 1188 s32 status; 1189 u32 i; 1190 1191 hw->eeprom.ops.init_params(hw); 1192 1193 if (words == 0) 1194 return IXGBE_ERR_INVALID_ARGUMENT; 1195 1196 if (offset >= hw->eeprom.word_size) 1197 return IXGBE_ERR_EEPROM; 1198 1199 for (i = 0; i < words; i++) { 1200 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1201 IXGBE_EEPROM_RW_REG_START; 1202 1203 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 1204 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 1205 1206 if (status == 0) { 1207 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 1208 IXGBE_EEPROM_RW_REG_DATA); 1209 } else { 1210 hw_dbg(hw, "Eeprom read timed out\n"); 1211 return status; 1212 } 1213 } 1214 1215 return 0; 1216 } 1217 1218 /** 1219 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 1220 * @hw: pointer to hardware structure 1221 * @offset: offset within the EEPROM to be used as a scratch pad 1222 * 1223 * Discover EEPROM page size by writing marching data at given offset. 1224 * This function is called only when we are writing a new large buffer 1225 * at given offset so the data would be overwritten anyway. 1226 **/ 1227 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 1228 u16 offset) 1229 { 1230 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 1231 s32 status; 1232 u16 i; 1233 1234 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 1235 data[i] = i; 1236 1237 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 1238 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1239 IXGBE_EEPROM_PAGE_SIZE_MAX, data); 1240 hw->eeprom.word_page_size = 0; 1241 if (status) 1242 return status; 1243 1244 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1245 if (status) 1246 return status; 1247 1248 /* 1249 * When writing in burst more than the actual page size 1250 * EEPROM address wraps around current page. 1251 */ 1252 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1253 1254 hw_dbg(hw, "Detected EEPROM page size = %d words.\n", 1255 hw->eeprom.word_page_size); 1256 return 0; 1257 } 1258 1259 /** 1260 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1261 * @hw: pointer to hardware structure 1262 * @offset: offset of word in the EEPROM to read 1263 * @data: word read from the EEPROM 1264 * 1265 * Reads a 16 bit word from the EEPROM using the EERD register. 1266 **/ 1267 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1268 { 1269 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1270 } 1271 1272 /** 1273 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1274 * @hw: pointer to hardware structure 1275 * @offset: offset of word in the EEPROM to write 1276 * @words: number of words 1277 * @data: word(s) write to the EEPROM 1278 * 1279 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1280 **/ 1281 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1282 u16 words, u16 *data) 1283 { 1284 u32 eewr; 1285 s32 status; 1286 u16 i; 1287 1288 hw->eeprom.ops.init_params(hw); 1289 1290 if (words == 0) 1291 return IXGBE_ERR_INVALID_ARGUMENT; 1292 1293 if (offset >= hw->eeprom.word_size) 1294 return IXGBE_ERR_EEPROM; 1295 1296 for (i = 0; i < words; i++) { 1297 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1298 (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1299 IXGBE_EEPROM_RW_REG_START; 1300 1301 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1302 if (status) { 1303 hw_dbg(hw, "Eeprom write EEWR timed out\n"); 1304 return status; 1305 } 1306 1307 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1308 1309 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1310 if (status) { 1311 hw_dbg(hw, "Eeprom write EEWR timed out\n"); 1312 return status; 1313 } 1314 } 1315 1316 return 0; 1317 } 1318 1319 /** 1320 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1321 * @hw: pointer to hardware structure 1322 * @offset: offset of word in the EEPROM to write 1323 * @data: word write to the EEPROM 1324 * 1325 * Write a 16 bit word to the EEPROM using the EEWR register. 1326 **/ 1327 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1328 { 1329 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1330 } 1331 1332 /** 1333 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1334 * @hw: pointer to hardware structure 1335 * @ee_reg: EEPROM flag for polling 1336 * 1337 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1338 * read or write is done respectively. 1339 **/ 1340 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1341 { 1342 u32 i; 1343 u32 reg; 1344 1345 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1346 if (ee_reg == IXGBE_NVM_POLL_READ) 1347 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1348 else 1349 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1350 1351 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1352 return 0; 1353 } 1354 udelay(5); 1355 } 1356 return IXGBE_ERR_EEPROM; 1357 } 1358 1359 /** 1360 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1361 * @hw: pointer to hardware structure 1362 * 1363 * Prepares EEPROM for access using bit-bang method. This function should 1364 * be called before issuing a command to the EEPROM. 1365 **/ 1366 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1367 { 1368 u32 eec; 1369 u32 i; 1370 1371 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0) 1372 return IXGBE_ERR_SWFW_SYNC; 1373 1374 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1375 1376 /* Request EEPROM Access */ 1377 eec |= IXGBE_EEC_REQ; 1378 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1379 1380 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1381 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1382 if (eec & IXGBE_EEC_GNT) 1383 break; 1384 udelay(5); 1385 } 1386 1387 /* Release if grant not acquired */ 1388 if (!(eec & IXGBE_EEC_GNT)) { 1389 eec &= ~IXGBE_EEC_REQ; 1390 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1391 hw_dbg(hw, "Could not acquire EEPROM grant\n"); 1392 1393 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1394 return IXGBE_ERR_EEPROM; 1395 } 1396 1397 /* Setup EEPROM for Read/Write */ 1398 /* Clear CS and SK */ 1399 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1400 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1401 IXGBE_WRITE_FLUSH(hw); 1402 udelay(1); 1403 return 0; 1404 } 1405 1406 /** 1407 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1408 * @hw: pointer to hardware structure 1409 * 1410 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1411 **/ 1412 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1413 { 1414 u32 timeout = 2000; 1415 u32 i; 1416 u32 swsm; 1417 1418 /* Get SMBI software semaphore between device drivers first */ 1419 for (i = 0; i < timeout; i++) { 1420 /* 1421 * If the SMBI bit is 0 when we read it, then the bit will be 1422 * set and we have the semaphore 1423 */ 1424 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1425 if (!(swsm & IXGBE_SWSM_SMBI)) 1426 break; 1427 usleep_range(50, 100); 1428 } 1429 1430 if (i == timeout) { 1431 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n"); 1432 /* this release is particularly important because our attempts 1433 * above to get the semaphore may have succeeded, and if there 1434 * was a timeout, we should unconditionally clear the semaphore 1435 * bits to free the driver to make progress 1436 */ 1437 ixgbe_release_eeprom_semaphore(hw); 1438 1439 usleep_range(50, 100); 1440 /* one last try 1441 * If the SMBI bit is 0 when we read it, then the bit will be 1442 * set and we have the semaphore 1443 */ 1444 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1445 if (swsm & IXGBE_SWSM_SMBI) { 1446 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n"); 1447 return IXGBE_ERR_EEPROM; 1448 } 1449 } 1450 1451 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1452 for (i = 0; i < timeout; i++) { 1453 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1454 1455 /* Set the SW EEPROM semaphore bit to request access */ 1456 swsm |= IXGBE_SWSM_SWESMBI; 1457 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); 1458 1459 /* If we set the bit successfully then we got the 1460 * semaphore. 1461 */ 1462 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1463 if (swsm & IXGBE_SWSM_SWESMBI) 1464 break; 1465 1466 usleep_range(50, 100); 1467 } 1468 1469 /* Release semaphores and return error if SW EEPROM semaphore 1470 * was not granted because we don't have access to the EEPROM 1471 */ 1472 if (i >= timeout) { 1473 hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n"); 1474 ixgbe_release_eeprom_semaphore(hw); 1475 return IXGBE_ERR_EEPROM; 1476 } 1477 1478 return 0; 1479 } 1480 1481 /** 1482 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1483 * @hw: pointer to hardware structure 1484 * 1485 * This function clears hardware semaphore bits. 1486 **/ 1487 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1488 { 1489 u32 swsm; 1490 1491 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1492 1493 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1494 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1495 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); 1496 IXGBE_WRITE_FLUSH(hw); 1497 } 1498 1499 /** 1500 * ixgbe_ready_eeprom - Polls for EEPROM ready 1501 * @hw: pointer to hardware structure 1502 **/ 1503 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 1504 { 1505 u16 i; 1506 u8 spi_stat_reg; 1507 1508 /* 1509 * Read "Status Register" repeatedly until the LSB is cleared. The 1510 * EEPROM will signal that the command has been completed by clearing 1511 * bit 0 of the internal status register. If it's not cleared within 1512 * 5 milliseconds, then error out. 1513 */ 1514 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 1515 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 1516 IXGBE_EEPROM_OPCODE_BITS); 1517 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 1518 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 1519 break; 1520 1521 udelay(5); 1522 ixgbe_standby_eeprom(hw); 1523 } 1524 1525 /* 1526 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 1527 * devices (and only 0-5mSec on 5V devices) 1528 */ 1529 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 1530 hw_dbg(hw, "SPI EEPROM Status error\n"); 1531 return IXGBE_ERR_EEPROM; 1532 } 1533 1534 return 0; 1535 } 1536 1537 /** 1538 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 1539 * @hw: pointer to hardware structure 1540 **/ 1541 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 1542 { 1543 u32 eec; 1544 1545 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1546 1547 /* Toggle CS to flush commands */ 1548 eec |= IXGBE_EEC_CS; 1549 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1550 IXGBE_WRITE_FLUSH(hw); 1551 udelay(1); 1552 eec &= ~IXGBE_EEC_CS; 1553 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1554 IXGBE_WRITE_FLUSH(hw); 1555 udelay(1); 1556 } 1557 1558 /** 1559 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 1560 * @hw: pointer to hardware structure 1561 * @data: data to send to the EEPROM 1562 * @count: number of bits to shift out 1563 **/ 1564 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 1565 u16 count) 1566 { 1567 u32 eec; 1568 u32 mask; 1569 u32 i; 1570 1571 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1572 1573 /* 1574 * Mask is used to shift "count" bits of "data" out to the EEPROM 1575 * one bit at a time. Determine the starting bit based on count 1576 */ 1577 mask = BIT(count - 1); 1578 1579 for (i = 0; i < count; i++) { 1580 /* 1581 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 1582 * "1", and then raising and then lowering the clock (the SK 1583 * bit controls the clock input to the EEPROM). A "0" is 1584 * shifted out to the EEPROM by setting "DI" to "0" and then 1585 * raising and then lowering the clock. 1586 */ 1587 if (data & mask) 1588 eec |= IXGBE_EEC_DI; 1589 else 1590 eec &= ~IXGBE_EEC_DI; 1591 1592 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1593 IXGBE_WRITE_FLUSH(hw); 1594 1595 udelay(1); 1596 1597 ixgbe_raise_eeprom_clk(hw, &eec); 1598 ixgbe_lower_eeprom_clk(hw, &eec); 1599 1600 /* 1601 * Shift mask to signify next bit of data to shift in to the 1602 * EEPROM 1603 */ 1604 mask = mask >> 1; 1605 } 1606 1607 /* We leave the "DI" bit set to "0" when we leave this routine. */ 1608 eec &= ~IXGBE_EEC_DI; 1609 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1610 IXGBE_WRITE_FLUSH(hw); 1611 } 1612 1613 /** 1614 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 1615 * @hw: pointer to hardware structure 1616 **/ 1617 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 1618 { 1619 u32 eec; 1620 u32 i; 1621 u16 data = 0; 1622 1623 /* 1624 * In order to read a register from the EEPROM, we need to shift 1625 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 1626 * the clock input to the EEPROM (setting the SK bit), and then reading 1627 * the value of the "DO" bit. During this "shifting in" process the 1628 * "DI" bit should always be clear. 1629 */ 1630 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1631 1632 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 1633 1634 for (i = 0; i < count; i++) { 1635 data = data << 1; 1636 ixgbe_raise_eeprom_clk(hw, &eec); 1637 1638 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1639 1640 eec &= ~(IXGBE_EEC_DI); 1641 if (eec & IXGBE_EEC_DO) 1642 data |= 1; 1643 1644 ixgbe_lower_eeprom_clk(hw, &eec); 1645 } 1646 1647 return data; 1648 } 1649 1650 /** 1651 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 1652 * @hw: pointer to hardware structure 1653 * @eec: EEC register's current value 1654 **/ 1655 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1656 { 1657 /* 1658 * Raise the clock input to the EEPROM 1659 * (setting the SK bit), then delay 1660 */ 1661 *eec = *eec | IXGBE_EEC_SK; 1662 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); 1663 IXGBE_WRITE_FLUSH(hw); 1664 udelay(1); 1665 } 1666 1667 /** 1668 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 1669 * @hw: pointer to hardware structure 1670 * @eecd: EECD's current value 1671 **/ 1672 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1673 { 1674 /* 1675 * Lower the clock input to the EEPROM (clearing the SK bit), then 1676 * delay 1677 */ 1678 *eec = *eec & ~IXGBE_EEC_SK; 1679 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); 1680 IXGBE_WRITE_FLUSH(hw); 1681 udelay(1); 1682 } 1683 1684 /** 1685 * ixgbe_release_eeprom - Release EEPROM, release semaphores 1686 * @hw: pointer to hardware structure 1687 **/ 1688 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 1689 { 1690 u32 eec; 1691 1692 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1693 1694 eec |= IXGBE_EEC_CS; /* Pull CS high */ 1695 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 1696 1697 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1698 IXGBE_WRITE_FLUSH(hw); 1699 1700 udelay(1); 1701 1702 /* Stop requesting EEPROM access */ 1703 eec &= ~IXGBE_EEC_REQ; 1704 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1705 1706 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1707 1708 /* 1709 * Delay before attempt to obtain semaphore again to allow FW 1710 * access. semaphore_delay is in ms we need us for usleep_range 1711 */ 1712 usleep_range(hw->eeprom.semaphore_delay * 1000, 1713 hw->eeprom.semaphore_delay * 2000); 1714 } 1715 1716 /** 1717 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 1718 * @hw: pointer to hardware structure 1719 **/ 1720 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 1721 { 1722 u16 i; 1723 u16 j; 1724 u16 checksum = 0; 1725 u16 length = 0; 1726 u16 pointer = 0; 1727 u16 word = 0; 1728 1729 /* Include 0x0-0x3F in the checksum */ 1730 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1731 if (hw->eeprom.ops.read(hw, i, &word)) { 1732 hw_dbg(hw, "EEPROM read failed\n"); 1733 break; 1734 } 1735 checksum += word; 1736 } 1737 1738 /* Include all data from pointers except for the fw pointer */ 1739 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1740 if (hw->eeprom.ops.read(hw, i, &pointer)) { 1741 hw_dbg(hw, "EEPROM read failed\n"); 1742 return IXGBE_ERR_EEPROM; 1743 } 1744 1745 /* If the pointer seems invalid */ 1746 if (pointer == 0xFFFF || pointer == 0) 1747 continue; 1748 1749 if (hw->eeprom.ops.read(hw, pointer, &length)) { 1750 hw_dbg(hw, "EEPROM read failed\n"); 1751 return IXGBE_ERR_EEPROM; 1752 } 1753 1754 if (length == 0xFFFF || length == 0) 1755 continue; 1756 1757 for (j = pointer + 1; j <= pointer + length; j++) { 1758 if (hw->eeprom.ops.read(hw, j, &word)) { 1759 hw_dbg(hw, "EEPROM read failed\n"); 1760 return IXGBE_ERR_EEPROM; 1761 } 1762 checksum += word; 1763 } 1764 } 1765 1766 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1767 1768 return (s32)checksum; 1769 } 1770 1771 /** 1772 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1773 * @hw: pointer to hardware structure 1774 * @checksum_val: calculated checksum 1775 * 1776 * Performs checksum calculation and validates the EEPROM checksum. If the 1777 * caller does not need checksum_val, the value can be NULL. 1778 **/ 1779 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1780 u16 *checksum_val) 1781 { 1782 s32 status; 1783 u16 checksum; 1784 u16 read_checksum = 0; 1785 1786 /* 1787 * Read the first word from the EEPROM. If this times out or fails, do 1788 * not continue or we could be in for a very long wait while every 1789 * EEPROM read fails 1790 */ 1791 status = hw->eeprom.ops.read(hw, 0, &checksum); 1792 if (status) { 1793 hw_dbg(hw, "EEPROM read failed\n"); 1794 return status; 1795 } 1796 1797 status = hw->eeprom.ops.calc_checksum(hw); 1798 if (status < 0) 1799 return status; 1800 1801 checksum = (u16)(status & 0xffff); 1802 1803 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1804 if (status) { 1805 hw_dbg(hw, "EEPROM read failed\n"); 1806 return status; 1807 } 1808 1809 /* Verify read checksum from EEPROM is the same as 1810 * calculated checksum 1811 */ 1812 if (read_checksum != checksum) 1813 status = IXGBE_ERR_EEPROM_CHECKSUM; 1814 1815 /* If the user cares, return the calculated checksum */ 1816 if (checksum_val) 1817 *checksum_val = checksum; 1818 1819 return status; 1820 } 1821 1822 /** 1823 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 1824 * @hw: pointer to hardware structure 1825 **/ 1826 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1827 { 1828 s32 status; 1829 u16 checksum; 1830 1831 /* 1832 * Read the first word from the EEPROM. If this times out or fails, do 1833 * not continue or we could be in for a very long wait while every 1834 * EEPROM read fails 1835 */ 1836 status = hw->eeprom.ops.read(hw, 0, &checksum); 1837 if (status) { 1838 hw_dbg(hw, "EEPROM read failed\n"); 1839 return status; 1840 } 1841 1842 status = hw->eeprom.ops.calc_checksum(hw); 1843 if (status < 0) 1844 return status; 1845 1846 checksum = (u16)(status & 0xffff); 1847 1848 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); 1849 1850 return status; 1851 } 1852 1853 /** 1854 * ixgbe_set_rar_generic - Set Rx address register 1855 * @hw: pointer to hardware structure 1856 * @index: Receive address register to write 1857 * @addr: Address to put into receive address register 1858 * @vmdq: VMDq "set" or "pool" index 1859 * @enable_addr: set flag that address is active 1860 * 1861 * Puts an ethernet address into a receive address register. 1862 **/ 1863 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 1864 u32 enable_addr) 1865 { 1866 u32 rar_low, rar_high; 1867 u32 rar_entries = hw->mac.num_rar_entries; 1868 1869 /* Make sure we are using a valid rar index range */ 1870 if (index >= rar_entries) { 1871 hw_dbg(hw, "RAR index %d is out of range.\n", index); 1872 return IXGBE_ERR_INVALID_ARGUMENT; 1873 } 1874 1875 /* setup VMDq pool selection before this RAR gets enabled */ 1876 hw->mac.ops.set_vmdq(hw, index, vmdq); 1877 1878 /* 1879 * HW expects these in little endian so we reverse the byte 1880 * order from network order (big endian) to little endian 1881 */ 1882 rar_low = ((u32)addr[0] | 1883 ((u32)addr[1] << 8) | 1884 ((u32)addr[2] << 16) | 1885 ((u32)addr[3] << 24)); 1886 /* 1887 * Some parts put the VMDq setting in the extra RAH bits, 1888 * so save everything except the lower 16 bits that hold part 1889 * of the address and the address valid bit. 1890 */ 1891 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1892 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1893 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 1894 1895 if (enable_addr != 0) 1896 rar_high |= IXGBE_RAH_AV; 1897 1898 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1899 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1900 1901 return 0; 1902 } 1903 1904 /** 1905 * ixgbe_clear_rar_generic - Remove Rx address register 1906 * @hw: pointer to hardware structure 1907 * @index: Receive address register to write 1908 * 1909 * Clears an ethernet address from a receive address register. 1910 **/ 1911 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 1912 { 1913 u32 rar_high; 1914 u32 rar_entries = hw->mac.num_rar_entries; 1915 1916 /* Make sure we are using a valid rar index range */ 1917 if (index >= rar_entries) { 1918 hw_dbg(hw, "RAR index %d is out of range.\n", index); 1919 return IXGBE_ERR_INVALID_ARGUMENT; 1920 } 1921 1922 /* 1923 * Some parts put the VMDq setting in the extra RAH bits, 1924 * so save everything except the lower 16 bits that hold part 1925 * of the address and the address valid bit. 1926 */ 1927 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1928 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1929 1930 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 1931 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1932 1933 /* clear VMDq pool/queue selection for this RAR */ 1934 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 1935 1936 return 0; 1937 } 1938 1939 /** 1940 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 1941 * @hw: pointer to hardware structure 1942 * 1943 * Places the MAC address in receive address register 0 and clears the rest 1944 * of the receive address registers. Clears the multicast table. Assumes 1945 * the receiver is in reset when the routine is called. 1946 **/ 1947 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 1948 { 1949 u32 i; 1950 u32 rar_entries = hw->mac.num_rar_entries; 1951 1952 /* 1953 * If the current mac address is valid, assume it is a software override 1954 * to the permanent address. 1955 * Otherwise, use the permanent address from the eeprom. 1956 */ 1957 if (!is_valid_ether_addr(hw->mac.addr)) { 1958 /* Get the MAC address from the RAR0 for later reference */ 1959 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 1960 1961 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr); 1962 } else { 1963 /* Setup the receive address. */ 1964 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); 1965 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr); 1966 1967 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 1968 } 1969 1970 /* clear VMDq pool/queue selection for RAR 0 */ 1971 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 1972 1973 hw->addr_ctrl.overflow_promisc = 0; 1974 1975 hw->addr_ctrl.rar_used_count = 1; 1976 1977 /* Zero out the other receive addresses. */ 1978 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1); 1979 for (i = 1; i < rar_entries; i++) { 1980 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1981 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1982 } 1983 1984 /* Clear the MTA */ 1985 hw->addr_ctrl.mta_in_use = 0; 1986 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1987 1988 hw_dbg(hw, " Clearing MTA\n"); 1989 for (i = 0; i < hw->mac.mcft_size; i++) 1990 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1991 1992 if (hw->mac.ops.init_uta_tables) 1993 hw->mac.ops.init_uta_tables(hw); 1994 1995 return 0; 1996 } 1997 1998 /** 1999 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 2000 * @hw: pointer to hardware structure 2001 * @mc_addr: the multicast address 2002 * 2003 * Extracts the 12 bits, from a multicast address, to determine which 2004 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 2005 * incoming rx multicast addresses, to determine the bit-vector to check in 2006 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 2007 * by the MO field of the MCSTCTRL. The MO field is set during initialization 2008 * to mc_filter_type. 2009 **/ 2010 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 2011 { 2012 u32 vector = 0; 2013 2014 switch (hw->mac.mc_filter_type) { 2015 case 0: /* use bits [47:36] of the address */ 2016 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 2017 break; 2018 case 1: /* use bits [46:35] of the address */ 2019 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 2020 break; 2021 case 2: /* use bits [45:34] of the address */ 2022 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 2023 break; 2024 case 3: /* use bits [43:32] of the address */ 2025 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 2026 break; 2027 default: /* Invalid mc_filter_type */ 2028 hw_dbg(hw, "MC filter type param set incorrectly\n"); 2029 break; 2030 } 2031 2032 /* vector can only be 12-bits or boundary will be exceeded */ 2033 vector &= 0xFFF; 2034 return vector; 2035 } 2036 2037 /** 2038 * ixgbe_set_mta - Set bit-vector in multicast table 2039 * @hw: pointer to hardware structure 2040 * @hash_value: Multicast address hash value 2041 * 2042 * Sets the bit-vector in the multicast table. 2043 **/ 2044 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 2045 { 2046 u32 vector; 2047 u32 vector_bit; 2048 u32 vector_reg; 2049 2050 hw->addr_ctrl.mta_in_use++; 2051 2052 vector = ixgbe_mta_vector(hw, mc_addr); 2053 hw_dbg(hw, " bit-vector = 0x%03X\n", vector); 2054 2055 /* 2056 * The MTA is a register array of 128 32-bit registers. It is treated 2057 * like an array of 4096 bits. We want to set bit 2058 * BitArray[vector_value]. So we figure out what register the bit is 2059 * in, read it, OR in the new bit, then write back the new value. The 2060 * register is determined by the upper 7 bits of the vector value and 2061 * the bit within that register are determined by the lower 5 bits of 2062 * the value. 2063 */ 2064 vector_reg = (vector >> 5) & 0x7F; 2065 vector_bit = vector & 0x1F; 2066 hw->mac.mta_shadow[vector_reg] |= BIT(vector_bit); 2067 } 2068 2069 /** 2070 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 2071 * @hw: pointer to hardware structure 2072 * @netdev: pointer to net device structure 2073 * 2074 * The given list replaces any existing list. Clears the MC addrs from receive 2075 * address registers and the multicast table. Uses unused receive address 2076 * registers for the first multicast addresses, and hashes the rest into the 2077 * multicast table. 2078 **/ 2079 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, 2080 struct net_device *netdev) 2081 { 2082 struct netdev_hw_addr *ha; 2083 u32 i; 2084 2085 /* 2086 * Set the new number of MC addresses that we are being requested to 2087 * use. 2088 */ 2089 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev); 2090 hw->addr_ctrl.mta_in_use = 0; 2091 2092 /* Clear mta_shadow */ 2093 hw_dbg(hw, " Clearing MTA\n"); 2094 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 2095 2096 /* Update mta shadow */ 2097 netdev_for_each_mc_addr(ha, netdev) { 2098 hw_dbg(hw, " Adding the multicast addresses:\n"); 2099 ixgbe_set_mta(hw, ha->addr); 2100 } 2101 2102 /* Enable mta */ 2103 for (i = 0; i < hw->mac.mcft_size; i++) 2104 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 2105 hw->mac.mta_shadow[i]); 2106 2107 if (hw->addr_ctrl.mta_in_use > 0) 2108 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 2109 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 2110 2111 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n"); 2112 return 0; 2113 } 2114 2115 /** 2116 * ixgbe_enable_mc_generic - Enable multicast address in RAR 2117 * @hw: pointer to hardware structure 2118 * 2119 * Enables multicast address in RAR and the use of the multicast hash table. 2120 **/ 2121 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 2122 { 2123 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2124 2125 if (a->mta_in_use > 0) 2126 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 2127 hw->mac.mc_filter_type); 2128 2129 return 0; 2130 } 2131 2132 /** 2133 * ixgbe_disable_mc_generic - Disable multicast address in RAR 2134 * @hw: pointer to hardware structure 2135 * 2136 * Disables multicast address in RAR and the use of the multicast hash table. 2137 **/ 2138 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 2139 { 2140 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2141 2142 if (a->mta_in_use > 0) 2143 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2144 2145 return 0; 2146 } 2147 2148 /** 2149 * ixgbe_fc_enable_generic - Enable flow control 2150 * @hw: pointer to hardware structure 2151 * 2152 * Enable flow control according to the current settings. 2153 **/ 2154 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 2155 { 2156 u32 mflcn_reg, fccfg_reg; 2157 u32 reg; 2158 u32 fcrtl, fcrth; 2159 int i; 2160 2161 /* Validate the water mark configuration. */ 2162 if (!hw->fc.pause_time) 2163 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2164 2165 /* Low water mark of zero causes XOFF floods */ 2166 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 2167 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2168 hw->fc.high_water[i]) { 2169 if (!hw->fc.low_water[i] || 2170 hw->fc.low_water[i] >= hw->fc.high_water[i]) { 2171 hw_dbg(hw, "Invalid water mark configuration\n"); 2172 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2173 } 2174 } 2175 } 2176 2177 /* Negotiate the fc mode to use */ 2178 hw->mac.ops.fc_autoneg(hw); 2179 2180 /* Disable any previous flow control settings */ 2181 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2182 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2183 2184 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2185 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2186 2187 /* 2188 * The possible values of fc.current_mode are: 2189 * 0: Flow control is completely disabled 2190 * 1: Rx flow control is enabled (we can receive pause frames, 2191 * but not send pause frames). 2192 * 2: Tx flow control is enabled (we can send pause frames but 2193 * we do not support receiving pause frames). 2194 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2195 * other: Invalid. 2196 */ 2197 switch (hw->fc.current_mode) { 2198 case ixgbe_fc_none: 2199 /* 2200 * Flow control is disabled by software override or autoneg. 2201 * The code below will actually disable it in the HW. 2202 */ 2203 break; 2204 case ixgbe_fc_rx_pause: 2205 /* 2206 * Rx Flow control is enabled and Tx Flow control is 2207 * disabled by software override. Since there really 2208 * isn't a way to advertise that we are capable of RX 2209 * Pause ONLY, we will advertise that we support both 2210 * symmetric and asymmetric Rx PAUSE. Later, we will 2211 * disable the adapter's ability to send PAUSE frames. 2212 */ 2213 mflcn_reg |= IXGBE_MFLCN_RFCE; 2214 break; 2215 case ixgbe_fc_tx_pause: 2216 /* 2217 * Tx Flow control is enabled, and Rx Flow control is 2218 * disabled by software override. 2219 */ 2220 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2221 break; 2222 case ixgbe_fc_full: 2223 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2224 mflcn_reg |= IXGBE_MFLCN_RFCE; 2225 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2226 break; 2227 default: 2228 hw_dbg(hw, "Flow control param set incorrectly\n"); 2229 return IXGBE_ERR_CONFIG; 2230 } 2231 2232 /* Set 802.3x based flow control settings. */ 2233 mflcn_reg |= IXGBE_MFLCN_DPF; 2234 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2235 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2236 2237 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2238 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 2239 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2240 hw->fc.high_water[i]) { 2241 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 2242 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 2243 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 2244 } else { 2245 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 2246 /* 2247 * In order to prevent Tx hangs when the internal Tx 2248 * switch is enabled we must set the high water mark 2249 * to the Rx packet buffer size - 24KB. This allows 2250 * the Tx switch to function even under heavy Rx 2251 * workloads. 2252 */ 2253 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; 2254 } 2255 2256 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2257 } 2258 2259 /* Configure pause time (2 TCs per register) */ 2260 reg = hw->fc.pause_time * 0x00010001; 2261 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) 2262 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 2263 2264 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 2265 2266 return 0; 2267 } 2268 2269 /** 2270 * ixgbe_negotiate_fc - Negotiate flow control 2271 * @hw: pointer to hardware structure 2272 * @adv_reg: flow control advertised settings 2273 * @lp_reg: link partner's flow control settings 2274 * @adv_sym: symmetric pause bit in advertisement 2275 * @adv_asm: asymmetric pause bit in advertisement 2276 * @lp_sym: symmetric pause bit in link partner advertisement 2277 * @lp_asm: asymmetric pause bit in link partner advertisement 2278 * 2279 * Find the intersection between advertised settings and link partner's 2280 * advertised settings 2281 **/ 2282 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2283 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2284 { 2285 if ((!(adv_reg)) || (!(lp_reg))) 2286 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2287 2288 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2289 /* 2290 * Now we need to check if the user selected Rx ONLY 2291 * of pause frames. In this case, we had to advertise 2292 * FULL flow control because we could not advertise RX 2293 * ONLY. Hence, we must now check to see if we need to 2294 * turn OFF the TRANSMISSION of PAUSE frames. 2295 */ 2296 if (hw->fc.requested_mode == ixgbe_fc_full) { 2297 hw->fc.current_mode = ixgbe_fc_full; 2298 hw_dbg(hw, "Flow Control = FULL.\n"); 2299 } else { 2300 hw->fc.current_mode = ixgbe_fc_rx_pause; 2301 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n"); 2302 } 2303 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 2304 (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2305 hw->fc.current_mode = ixgbe_fc_tx_pause; 2306 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); 2307 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 2308 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2309 hw->fc.current_mode = ixgbe_fc_rx_pause; 2310 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); 2311 } else { 2312 hw->fc.current_mode = ixgbe_fc_none; 2313 hw_dbg(hw, "Flow Control = NONE.\n"); 2314 } 2315 return 0; 2316 } 2317 2318 /** 2319 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 2320 * @hw: pointer to hardware structure 2321 * 2322 * Enable flow control according on 1 gig fiber. 2323 **/ 2324 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 2325 { 2326 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 2327 s32 ret_val; 2328 2329 /* 2330 * On multispeed fiber at 1g, bail out if 2331 * - link is up but AN did not complete, or if 2332 * - link is up and AN completed but timed out 2333 */ 2334 2335 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 2336 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 2337 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) 2338 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2339 2340 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 2341 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 2342 2343 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 2344 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 2345 IXGBE_PCS1GANA_ASM_PAUSE, 2346 IXGBE_PCS1GANA_SYM_PAUSE, 2347 IXGBE_PCS1GANA_ASM_PAUSE); 2348 2349 return ret_val; 2350 } 2351 2352 /** 2353 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 2354 * @hw: pointer to hardware structure 2355 * 2356 * Enable flow control according to IEEE clause 37. 2357 **/ 2358 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 2359 { 2360 u32 links2, anlp1_reg, autoc_reg, links; 2361 s32 ret_val; 2362 2363 /* 2364 * On backplane, bail out if 2365 * - backplane autoneg was not completed, or if 2366 * - we are 82599 and link partner is not AN enabled 2367 */ 2368 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 2369 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) 2370 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2371 2372 if (hw->mac.type == ixgbe_mac_82599EB) { 2373 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 2374 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) 2375 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2376 } 2377 /* 2378 * Read the 10g AN autoc and LP ability registers and resolve 2379 * local flow control settings accordingly 2380 */ 2381 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2382 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2383 2384 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 2385 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 2386 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 2387 2388 return ret_val; 2389 } 2390 2391 /** 2392 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 2393 * @hw: pointer to hardware structure 2394 * 2395 * Enable flow control according to IEEE clause 37. 2396 **/ 2397 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 2398 { 2399 u16 technology_ability_reg = 0; 2400 u16 lp_technology_ability_reg = 0; 2401 2402 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 2403 MDIO_MMD_AN, 2404 &technology_ability_reg); 2405 hw->phy.ops.read_reg(hw, MDIO_AN_LPA, 2406 MDIO_MMD_AN, 2407 &lp_technology_ability_reg); 2408 2409 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 2410 (u32)lp_technology_ability_reg, 2411 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 2412 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 2413 } 2414 2415 /** 2416 * ixgbe_fc_autoneg - Configure flow control 2417 * @hw: pointer to hardware structure 2418 * 2419 * Compares our advertised flow control capabilities to those advertised by 2420 * our link partner, and determines the proper flow control mode to use. 2421 **/ 2422 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) 2423 { 2424 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2425 ixgbe_link_speed speed; 2426 bool link_up; 2427 2428 /* 2429 * AN should have completed when the cable was plugged in. 2430 * Look for reasons to bail out. Bail out if: 2431 * - FC autoneg is disabled, or if 2432 * - link is not up. 2433 * 2434 * Since we're being called from an LSC, link is already known to be up. 2435 * So use link_up_wait_to_complete=false. 2436 */ 2437 if (hw->fc.disable_fc_autoneg) 2438 goto out; 2439 2440 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2441 if (!link_up) 2442 goto out; 2443 2444 switch (hw->phy.media_type) { 2445 /* Autoneg flow control on fiber adapters */ 2446 case ixgbe_media_type_fiber: 2447 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 2448 ret_val = ixgbe_fc_autoneg_fiber(hw); 2449 break; 2450 2451 /* Autoneg flow control on backplane adapters */ 2452 case ixgbe_media_type_backplane: 2453 ret_val = ixgbe_fc_autoneg_backplane(hw); 2454 break; 2455 2456 /* Autoneg flow control on copper adapters */ 2457 case ixgbe_media_type_copper: 2458 if (ixgbe_device_supports_autoneg_fc(hw)) 2459 ret_val = ixgbe_fc_autoneg_copper(hw); 2460 break; 2461 2462 default: 2463 break; 2464 } 2465 2466 out: 2467 if (ret_val == 0) { 2468 hw->fc.fc_was_autonegged = true; 2469 } else { 2470 hw->fc.fc_was_autonegged = false; 2471 hw->fc.current_mode = hw->fc.requested_mode; 2472 } 2473 } 2474 2475 /** 2476 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion 2477 * @hw: pointer to hardware structure 2478 * 2479 * System-wide timeout range is encoded in PCIe Device Control2 register. 2480 * 2481 * Add 10% to specified maximum and return the number of times to poll for 2482 * completion timeout, in units of 100 microsec. Never return less than 2483 * 800 = 80 millisec. 2484 **/ 2485 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) 2486 { 2487 s16 devctl2; 2488 u32 pollcnt; 2489 2490 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2); 2491 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; 2492 2493 switch (devctl2) { 2494 case IXGBE_PCIDEVCTRL2_65_130ms: 2495 pollcnt = 1300; /* 130 millisec */ 2496 break; 2497 case IXGBE_PCIDEVCTRL2_260_520ms: 2498 pollcnt = 5200; /* 520 millisec */ 2499 break; 2500 case IXGBE_PCIDEVCTRL2_1_2s: 2501 pollcnt = 20000; /* 2 sec */ 2502 break; 2503 case IXGBE_PCIDEVCTRL2_4_8s: 2504 pollcnt = 80000; /* 8 sec */ 2505 break; 2506 case IXGBE_PCIDEVCTRL2_17_34s: 2507 pollcnt = 34000; /* 34 sec */ 2508 break; 2509 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ 2510 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ 2511 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ 2512 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ 2513 default: 2514 pollcnt = 800; /* 80 millisec minimum */ 2515 break; 2516 } 2517 2518 /* add 10% to spec maximum */ 2519 return (pollcnt * 11) / 10; 2520 } 2521 2522 /** 2523 * ixgbe_disable_pcie_master - Disable PCI-express master access 2524 * @hw: pointer to hardware structure 2525 * 2526 * Disables PCI-Express master access and verifies there are no pending 2527 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 2528 * bit hasn't caused the master requests to be disabled, else 0 2529 * is returned signifying master requests disabled. 2530 **/ 2531 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 2532 { 2533 u32 i, poll; 2534 u16 value; 2535 2536 /* Always set this bit to ensure any future transactions are blocked */ 2537 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 2538 2539 /* Poll for bit to read as set */ 2540 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2541 if (IXGBE_READ_REG(hw, IXGBE_CTRL) & IXGBE_CTRL_GIO_DIS) 2542 break; 2543 usleep_range(100, 120); 2544 } 2545 if (i >= IXGBE_PCI_MASTER_DISABLE_TIMEOUT) { 2546 hw_dbg(hw, "GIO disable did not set - requesting resets\n"); 2547 goto gio_disable_fail; 2548 } 2549 2550 /* Exit if master requests are blocked */ 2551 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || 2552 ixgbe_removed(hw->hw_addr)) 2553 return 0; 2554 2555 /* Poll for master request bit to clear */ 2556 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2557 udelay(100); 2558 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 2559 return 0; 2560 } 2561 2562 /* 2563 * Two consecutive resets are required via CTRL.RST per datasheet 2564 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 2565 * of this need. The first reset prevents new master requests from 2566 * being issued by our device. We then must wait 1usec or more for any 2567 * remaining completions from the PCIe bus to trickle in, and then reset 2568 * again to clear out any effects they may have had on our device. 2569 */ 2570 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n"); 2571 gio_disable_fail: 2572 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 2573 2574 if (hw->mac.type >= ixgbe_mac_X550) 2575 return 0; 2576 2577 /* 2578 * Before proceeding, make sure that the PCIe block does not have 2579 * transactions pending. 2580 */ 2581 poll = ixgbe_pcie_timeout_poll(hw); 2582 for (i = 0; i < poll; i++) { 2583 udelay(100); 2584 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); 2585 if (ixgbe_removed(hw->hw_addr)) 2586 return 0; 2587 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 2588 return 0; 2589 } 2590 2591 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n"); 2592 return IXGBE_ERR_MASTER_REQUESTS_PENDING; 2593 } 2594 2595 /** 2596 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 2597 * @hw: pointer to hardware structure 2598 * @mask: Mask to specify which semaphore to acquire 2599 * 2600 * Acquires the SWFW semaphore through the GSSR register for the specified 2601 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2602 **/ 2603 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) 2604 { 2605 u32 gssr = 0; 2606 u32 swmask = mask; 2607 u32 fwmask = mask << 5; 2608 u32 timeout = 200; 2609 u32 i; 2610 2611 for (i = 0; i < timeout; i++) { 2612 /* 2613 * SW NVM semaphore bit is used for access to all 2614 * SW_FW_SYNC bits (not just NVM) 2615 */ 2616 if (ixgbe_get_eeprom_semaphore(hw)) 2617 return IXGBE_ERR_SWFW_SYNC; 2618 2619 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2620 if (!(gssr & (fwmask | swmask))) { 2621 gssr |= swmask; 2622 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2623 ixgbe_release_eeprom_semaphore(hw); 2624 return 0; 2625 } else { 2626 /* Resource is currently in use by FW or SW */ 2627 ixgbe_release_eeprom_semaphore(hw); 2628 usleep_range(5000, 10000); 2629 } 2630 } 2631 2632 /* If time expired clear the bits holding the lock and retry */ 2633 if (gssr & (fwmask | swmask)) 2634 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); 2635 2636 usleep_range(5000, 10000); 2637 return IXGBE_ERR_SWFW_SYNC; 2638 } 2639 2640 /** 2641 * ixgbe_release_swfw_sync - Release SWFW semaphore 2642 * @hw: pointer to hardware structure 2643 * @mask: Mask to specify which semaphore to release 2644 * 2645 * Releases the SWFW semaphore through the GSSR register for the specified 2646 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2647 **/ 2648 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) 2649 { 2650 u32 gssr; 2651 u32 swmask = mask; 2652 2653 ixgbe_get_eeprom_semaphore(hw); 2654 2655 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2656 gssr &= ~swmask; 2657 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2658 2659 ixgbe_release_eeprom_semaphore(hw); 2660 } 2661 2662 /** 2663 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read 2664 * @hw: pointer to hardware structure 2665 * @reg_val: Value we read from AUTOC 2666 * @locked: bool to indicate whether the SW/FW lock should be taken. Never 2667 * true in this the generic case. 2668 * 2669 * The default case requires no protection so just to the register read. 2670 **/ 2671 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 2672 { 2673 *locked = false; 2674 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2675 return 0; 2676 } 2677 2678 /** 2679 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write 2680 * @hw: pointer to hardware structure 2681 * @reg_val: value to write to AUTOC 2682 * @locked: bool to indicate whether the SW/FW lock was already taken by 2683 * previous read. 2684 **/ 2685 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) 2686 { 2687 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); 2688 return 0; 2689 } 2690 2691 /** 2692 * ixgbe_disable_rx_buff_generic - Stops the receive data path 2693 * @hw: pointer to hardware structure 2694 * 2695 * Stops the receive data path and waits for the HW to internally 2696 * empty the Rx security block. 2697 **/ 2698 s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw) 2699 { 2700 #define IXGBE_MAX_SECRX_POLL 40 2701 int i; 2702 int secrxreg; 2703 2704 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2705 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 2706 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2707 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 2708 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 2709 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 2710 break; 2711 else 2712 /* Use interrupt-safe sleep just in case */ 2713 udelay(1000); 2714 } 2715 2716 /* For informational purposes only */ 2717 if (i >= IXGBE_MAX_SECRX_POLL) 2718 hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n"); 2719 2720 return 0; 2721 2722 } 2723 2724 /** 2725 * ixgbe_enable_rx_buff - Enables the receive data path 2726 * @hw: pointer to hardware structure 2727 * 2728 * Enables the receive data path 2729 **/ 2730 s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw) 2731 { 2732 u32 secrxreg; 2733 2734 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2735 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 2736 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2737 IXGBE_WRITE_FLUSH(hw); 2738 2739 return 0; 2740 } 2741 2742 /** 2743 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 2744 * @hw: pointer to hardware structure 2745 * @regval: register value to write to RXCTRL 2746 * 2747 * Enables the Rx DMA unit 2748 **/ 2749 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 2750 { 2751 if (regval & IXGBE_RXCTRL_RXEN) 2752 hw->mac.ops.enable_rx(hw); 2753 else 2754 hw->mac.ops.disable_rx(hw); 2755 2756 return 0; 2757 } 2758 2759 /** 2760 * ixgbe_blink_led_start_generic - Blink LED based on index. 2761 * @hw: pointer to hardware structure 2762 * @index: led number to blink 2763 **/ 2764 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 2765 { 2766 ixgbe_link_speed speed = 0; 2767 bool link_up = false; 2768 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2769 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2770 bool locked = false; 2771 s32 ret_val; 2772 2773 if (index > 3) 2774 return IXGBE_ERR_PARAM; 2775 2776 /* 2777 * Link must be up to auto-blink the LEDs; 2778 * Force it if link is down. 2779 */ 2780 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2781 2782 if (!link_up) { 2783 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 2784 if (ret_val) 2785 return ret_val; 2786 2787 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2788 autoc_reg |= IXGBE_AUTOC_FLU; 2789 2790 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 2791 if (ret_val) 2792 return ret_val; 2793 2794 IXGBE_WRITE_FLUSH(hw); 2795 2796 usleep_range(10000, 20000); 2797 } 2798 2799 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2800 led_reg |= IXGBE_LED_BLINK(index); 2801 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2802 IXGBE_WRITE_FLUSH(hw); 2803 2804 return 0; 2805 } 2806 2807 /** 2808 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 2809 * @hw: pointer to hardware structure 2810 * @index: led number to stop blinking 2811 **/ 2812 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 2813 { 2814 u32 autoc_reg = 0; 2815 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2816 bool locked = false; 2817 s32 ret_val; 2818 2819 if (index > 3) 2820 return IXGBE_ERR_PARAM; 2821 2822 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 2823 if (ret_val) 2824 return ret_val; 2825 2826 autoc_reg &= ~IXGBE_AUTOC_FLU; 2827 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2828 2829 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 2830 if (ret_val) 2831 return ret_val; 2832 2833 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2834 led_reg &= ~IXGBE_LED_BLINK(index); 2835 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 2836 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2837 IXGBE_WRITE_FLUSH(hw); 2838 2839 return 0; 2840 } 2841 2842 /** 2843 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 2844 * @hw: pointer to hardware structure 2845 * @san_mac_offset: SAN MAC address offset 2846 * 2847 * This function will read the EEPROM location for the SAN MAC address 2848 * pointer, and returns the value at that location. This is used in both 2849 * get and set mac_addr routines. 2850 **/ 2851 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 2852 u16 *san_mac_offset) 2853 { 2854 s32 ret_val; 2855 2856 /* 2857 * First read the EEPROM pointer to see if the MAC addresses are 2858 * available. 2859 */ 2860 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, 2861 san_mac_offset); 2862 if (ret_val) 2863 hw_err(hw, "eeprom read at offset %d failed\n", 2864 IXGBE_SAN_MAC_ADDR_PTR); 2865 2866 return ret_val; 2867 } 2868 2869 /** 2870 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 2871 * @hw: pointer to hardware structure 2872 * @san_mac_addr: SAN MAC address 2873 * 2874 * Reads the SAN MAC address from the EEPROM, if it's available. This is 2875 * per-port, so set_lan_id() must be called before reading the addresses. 2876 * set_lan_id() is called by identify_sfp(), but this cannot be relied 2877 * upon for non-SFP connections, so we must call it here. 2878 **/ 2879 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 2880 { 2881 u16 san_mac_data, san_mac_offset; 2882 u8 i; 2883 s32 ret_val; 2884 2885 /* 2886 * First read the EEPROM pointer to see if the MAC addresses are 2887 * available. If they're not, no point in calling set_lan_id() here. 2888 */ 2889 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 2890 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 2891 2892 goto san_mac_addr_clr; 2893 2894 /* make sure we know which port we need to program */ 2895 hw->mac.ops.set_lan_id(hw); 2896 /* apply the port offset to the address offset */ 2897 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 2898 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 2899 for (i = 0; i < 3; i++) { 2900 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, 2901 &san_mac_data); 2902 if (ret_val) { 2903 hw_err(hw, "eeprom read at offset %d failed\n", 2904 san_mac_offset); 2905 goto san_mac_addr_clr; 2906 } 2907 san_mac_addr[i * 2] = (u8)(san_mac_data); 2908 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 2909 san_mac_offset++; 2910 } 2911 return 0; 2912 2913 san_mac_addr_clr: 2914 /* No addresses available in this EEPROM. It's not necessarily an 2915 * error though, so just wipe the local address and return. 2916 */ 2917 for (i = 0; i < 6; i++) 2918 san_mac_addr[i] = 0xFF; 2919 return ret_val; 2920 } 2921 2922 /** 2923 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 2924 * @hw: pointer to hardware structure 2925 * 2926 * Read PCIe configuration space, and get the MSI-X vector count from 2927 * the capabilities table. 2928 **/ 2929 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 2930 { 2931 u16 msix_count; 2932 u16 max_msix_count; 2933 u16 pcie_offset; 2934 2935 switch (hw->mac.type) { 2936 case ixgbe_mac_82598EB: 2937 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 2938 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 2939 break; 2940 case ixgbe_mac_82599EB: 2941 case ixgbe_mac_X540: 2942 case ixgbe_mac_X550: 2943 case ixgbe_mac_X550EM_x: 2944 case ixgbe_mac_x550em_a: 2945 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 2946 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 2947 break; 2948 default: 2949 return 1; 2950 } 2951 2952 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset); 2953 if (ixgbe_removed(hw->hw_addr)) 2954 msix_count = 0; 2955 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 2956 2957 /* MSI-X count is zero-based in HW */ 2958 msix_count++; 2959 2960 if (msix_count > max_msix_count) 2961 msix_count = max_msix_count; 2962 2963 return msix_count; 2964 } 2965 2966 /** 2967 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 2968 * @hw: pointer to hardware struct 2969 * @rar: receive address register index to disassociate 2970 * @vmdq: VMDq pool index to remove from the rar 2971 **/ 2972 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2973 { 2974 u32 mpsar_lo, mpsar_hi; 2975 u32 rar_entries = hw->mac.num_rar_entries; 2976 2977 /* Make sure we are using a valid rar index range */ 2978 if (rar >= rar_entries) { 2979 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 2980 return IXGBE_ERR_INVALID_ARGUMENT; 2981 } 2982 2983 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2984 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2985 2986 if (ixgbe_removed(hw->hw_addr)) 2987 return 0; 2988 2989 if (!mpsar_lo && !mpsar_hi) 2990 return 0; 2991 2992 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 2993 if (mpsar_lo) { 2994 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 2995 mpsar_lo = 0; 2996 } 2997 if (mpsar_hi) { 2998 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 2999 mpsar_hi = 0; 3000 } 3001 } else if (vmdq < 32) { 3002 mpsar_lo &= ~BIT(vmdq); 3003 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 3004 } else { 3005 mpsar_hi &= ~BIT(vmdq - 32); 3006 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 3007 } 3008 3009 /* was that the last pool using this rar? */ 3010 if (mpsar_lo == 0 && mpsar_hi == 0 && 3011 rar != 0 && rar != hw->mac.san_mac_rar_index) 3012 hw->mac.ops.clear_rar(hw, rar); 3013 3014 return 0; 3015 } 3016 3017 /** 3018 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 3019 * @hw: pointer to hardware struct 3020 * @rar: receive address register index to associate with a VMDq index 3021 * @vmdq: VMDq pool index 3022 **/ 3023 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3024 { 3025 u32 mpsar; 3026 u32 rar_entries = hw->mac.num_rar_entries; 3027 3028 /* Make sure we are using a valid rar index range */ 3029 if (rar >= rar_entries) { 3030 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 3031 return IXGBE_ERR_INVALID_ARGUMENT; 3032 } 3033 3034 if (vmdq < 32) { 3035 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3036 mpsar |= BIT(vmdq); 3037 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 3038 } else { 3039 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3040 mpsar |= BIT(vmdq - 32); 3041 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 3042 } 3043 return 0; 3044 } 3045 3046 /** 3047 * This function should only be involved in the IOV mode. 3048 * In IOV mode, Default pool is next pool after the number of 3049 * VFs advertized and not 0. 3050 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] 3051 * 3052 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address 3053 * @hw: pointer to hardware struct 3054 * @vmdq: VMDq pool index 3055 **/ 3056 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 3057 { 3058 u32 rar = hw->mac.san_mac_rar_index; 3059 3060 if (vmdq < 32) { 3061 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), BIT(vmdq)); 3062 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3063 } else { 3064 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3065 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), BIT(vmdq - 32)); 3066 } 3067 3068 return 0; 3069 } 3070 3071 /** 3072 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 3073 * @hw: pointer to hardware structure 3074 **/ 3075 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 3076 { 3077 int i; 3078 3079 for (i = 0; i < 128; i++) 3080 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 3081 3082 return 0; 3083 } 3084 3085 /** 3086 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 3087 * @hw: pointer to hardware structure 3088 * @vlan: VLAN id to write to VLAN filter 3089 * 3090 * return the VLVF index where this VLAN id should be placed 3091 * 3092 **/ 3093 static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) 3094 { 3095 s32 regindex, first_empty_slot; 3096 u32 bits; 3097 3098 /* short cut the special case */ 3099 if (vlan == 0) 3100 return 0; 3101 3102 /* if vlvf_bypass is set we don't want to use an empty slot, we 3103 * will simply bypass the VLVF if there are no entries present in the 3104 * VLVF that contain our VLAN 3105 */ 3106 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0; 3107 3108 /* add VLAN enable bit for comparison */ 3109 vlan |= IXGBE_VLVF_VIEN; 3110 3111 /* Search for the vlan id in the VLVF entries. Save off the first empty 3112 * slot found along the way. 3113 * 3114 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 3115 */ 3116 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) { 3117 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 3118 if (bits == vlan) 3119 return regindex; 3120 if (!first_empty_slot && !bits) 3121 first_empty_slot = regindex; 3122 } 3123 3124 /* If we are here then we didn't find the VLAN. Return first empty 3125 * slot we found during our search, else error. 3126 */ 3127 if (!first_empty_slot) 3128 hw_dbg(hw, "No space in VLVF.\n"); 3129 3130 return first_empty_slot ? : IXGBE_ERR_NO_SPACE; 3131 } 3132 3133 /** 3134 * ixgbe_set_vfta_generic - Set VLAN filter table 3135 * @hw: pointer to hardware structure 3136 * @vlan: VLAN id to write to VLAN filter 3137 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 3138 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 3139 * @vlvf_bypass: boolean flag indicating updating default pool is okay 3140 * 3141 * Turn on/off specified VLAN in the VLAN filter table. 3142 **/ 3143 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3144 bool vlan_on, bool vlvf_bypass) 3145 { 3146 u32 regidx, vfta_delta, vfta, bits; 3147 s32 vlvf_index; 3148 3149 if ((vlan > 4095) || (vind > 63)) 3150 return IXGBE_ERR_PARAM; 3151 3152 /* 3153 * this is a 2 part operation - first the VFTA, then the 3154 * VLVF and VLVFB if VT Mode is set 3155 * We don't write the VFTA until we know the VLVF part succeeded. 3156 */ 3157 3158 /* Part 1 3159 * The VFTA is a bitstring made up of 128 32-bit registers 3160 * that enable the particular VLAN id, much like the MTA: 3161 * bits[11-5]: which register 3162 * bits[4-0]: which bit in the register 3163 */ 3164 regidx = vlan / 32; 3165 vfta_delta = BIT(vlan % 32); 3166 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); 3167 3168 /* vfta_delta represents the difference between the current value 3169 * of vfta and the value we want in the register. Since the diff 3170 * is an XOR mask we can just update vfta using an XOR. 3171 */ 3172 vfta_delta &= vlan_on ? ~vfta : vfta; 3173 vfta ^= vfta_delta; 3174 3175 /* Part 2 3176 * If VT Mode is set 3177 * Either vlan_on 3178 * make sure the vlan is in VLVF 3179 * set the vind bit in the matching VLVFB 3180 * Or !vlan_on 3181 * clear the pool bit and possibly the vind 3182 */ 3183 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) 3184 goto vfta_update; 3185 3186 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); 3187 if (vlvf_index < 0) { 3188 if (vlvf_bypass) 3189 goto vfta_update; 3190 return vlvf_index; 3191 } 3192 3193 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); 3194 3195 /* set the pool bit */ 3196 bits |= BIT(vind % 32); 3197 if (vlan_on) 3198 goto vlvf_update; 3199 3200 /* clear the pool bit */ 3201 bits ^= BIT(vind % 32); 3202 3203 if (!bits && 3204 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { 3205 /* Clear VFTA first, then disable VLVF. Otherwise 3206 * we run the risk of stray packets leaking into 3207 * the PF via the default pool 3208 */ 3209 if (vfta_delta) 3210 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 3211 3212 /* disable VLVF and clear remaining bit from pool */ 3213 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 3214 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); 3215 3216 return 0; 3217 } 3218 3219 /* If there are still bits set in the VLVFB registers 3220 * for the VLAN ID indicated we need to see if the 3221 * caller is requesting that we clear the VFTA entry bit. 3222 * If the caller has requested that we clear the VFTA 3223 * entry bit but there are still pools/VFs using this VLAN 3224 * ID entry then ignore the request. We're not worried 3225 * about the case where we're turning the VFTA VLAN ID 3226 * entry bit on, only when requested to turn it off as 3227 * there may be multiple pools and/or VFs using the 3228 * VLAN ID entry. In that case we cannot clear the 3229 * VFTA bit until all pools/VFs using that VLAN ID have also 3230 * been cleared. This will be indicated by "bits" being 3231 * zero. 3232 */ 3233 vfta_delta = 0; 3234 3235 vlvf_update: 3236 /* record pool change and enable VLAN ID if not already enabled */ 3237 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); 3238 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); 3239 3240 vfta_update: 3241 /* Update VFTA now that we are ready for traffic */ 3242 if (vfta_delta) 3243 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 3244 3245 return 0; 3246 } 3247 3248 /** 3249 * ixgbe_clear_vfta_generic - Clear VLAN filter table 3250 * @hw: pointer to hardware structure 3251 * 3252 * Clears the VLAN filer table, and the VMDq index associated with the filter 3253 **/ 3254 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 3255 { 3256 u32 offset; 3257 3258 for (offset = 0; offset < hw->mac.vft_size; offset++) 3259 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 3260 3261 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 3262 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 3263 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); 3264 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0); 3265 } 3266 3267 return 0; 3268 } 3269 3270 /** 3271 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix 3272 * @hw: pointer to hardware structure 3273 * 3274 * Contains the logic to identify if we need to verify link for the 3275 * crosstalk fix 3276 **/ 3277 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) 3278 { 3279 /* Does FW say we need the fix */ 3280 if (!hw->need_crosstalk_fix) 3281 return false; 3282 3283 /* Only consider SFP+ PHYs i.e. media type fiber */ 3284 switch (hw->mac.ops.get_media_type(hw)) { 3285 case ixgbe_media_type_fiber: 3286 case ixgbe_media_type_fiber_qsfp: 3287 break; 3288 default: 3289 return false; 3290 } 3291 3292 return true; 3293 } 3294 3295 /** 3296 * ixgbe_check_mac_link_generic - Determine link and speed status 3297 * @hw: pointer to hardware structure 3298 * @speed: pointer to link speed 3299 * @link_up: true when link is up 3300 * @link_up_wait_to_complete: bool used to wait for link up or not 3301 * 3302 * Reads the links register to determine if link is up and the current speed 3303 **/ 3304 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3305 bool *link_up, bool link_up_wait_to_complete) 3306 { 3307 u32 links_reg, links_orig; 3308 u32 i; 3309 3310 /* If Crosstalk fix enabled do the sanity check of making sure 3311 * the SFP+ cage is full. 3312 */ 3313 if (ixgbe_need_crosstalk_fix(hw)) { 3314 u32 sfp_cage_full; 3315 3316 switch (hw->mac.type) { 3317 case ixgbe_mac_82599EB: 3318 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 3319 IXGBE_ESDP_SDP2; 3320 break; 3321 case ixgbe_mac_X550EM_x: 3322 case ixgbe_mac_x550em_a: 3323 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 3324 IXGBE_ESDP_SDP0; 3325 break; 3326 default: 3327 /* sanity check - No SFP+ devices here */ 3328 sfp_cage_full = false; 3329 break; 3330 } 3331 3332 if (!sfp_cage_full) { 3333 *link_up = false; 3334 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3335 return 0; 3336 } 3337 } 3338 3339 /* clear the old state */ 3340 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 3341 3342 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3343 3344 if (links_orig != links_reg) { 3345 hw_dbg(hw, "LINKS changed from %08X to %08X\n", 3346 links_orig, links_reg); 3347 } 3348 3349 if (link_up_wait_to_complete) { 3350 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 3351 if (links_reg & IXGBE_LINKS_UP) { 3352 *link_up = true; 3353 break; 3354 } else { 3355 *link_up = false; 3356 } 3357 msleep(100); 3358 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3359 } 3360 } else { 3361 if (links_reg & IXGBE_LINKS_UP) 3362 *link_up = true; 3363 else 3364 *link_up = false; 3365 } 3366 3367 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 3368 case IXGBE_LINKS_SPEED_10G_82599: 3369 if ((hw->mac.type >= ixgbe_mac_X550) && 3370 (links_reg & IXGBE_LINKS_SPEED_NON_STD)) 3371 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 3372 else 3373 *speed = IXGBE_LINK_SPEED_10GB_FULL; 3374 break; 3375 case IXGBE_LINKS_SPEED_1G_82599: 3376 *speed = IXGBE_LINK_SPEED_1GB_FULL; 3377 break; 3378 case IXGBE_LINKS_SPEED_100_82599: 3379 if ((hw->mac.type >= ixgbe_mac_X550) && 3380 (links_reg & IXGBE_LINKS_SPEED_NON_STD)) 3381 *speed = IXGBE_LINK_SPEED_5GB_FULL; 3382 else 3383 *speed = IXGBE_LINK_SPEED_100_FULL; 3384 break; 3385 case IXGBE_LINKS_SPEED_10_X550EM_A: 3386 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3387 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 3388 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) { 3389 *speed = IXGBE_LINK_SPEED_10_FULL; 3390 } 3391 break; 3392 default: 3393 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3394 } 3395 3396 return 0; 3397 } 3398 3399 /** 3400 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 3401 * the EEPROM 3402 * @hw: pointer to hardware structure 3403 * @wwnn_prefix: the alternative WWNN prefix 3404 * @wwpn_prefix: the alternative WWPN prefix 3405 * 3406 * This function will read the EEPROM from the alternative SAN MAC address 3407 * block to check the support for the alternative WWNN/WWPN prefix support. 3408 **/ 3409 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 3410 u16 *wwpn_prefix) 3411 { 3412 u16 offset, caps; 3413 u16 alt_san_mac_blk_offset; 3414 3415 /* clear output first */ 3416 *wwnn_prefix = 0xFFFF; 3417 *wwpn_prefix = 0xFFFF; 3418 3419 /* check if alternative SAN MAC is supported */ 3420 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR; 3421 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) 3422 goto wwn_prefix_err; 3423 3424 if ((alt_san_mac_blk_offset == 0) || 3425 (alt_san_mac_blk_offset == 0xFFFF)) 3426 return 0; 3427 3428 /* check capability in alternative san mac address block */ 3429 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 3430 if (hw->eeprom.ops.read(hw, offset, &caps)) 3431 goto wwn_prefix_err; 3432 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 3433 return 0; 3434 3435 /* get the corresponding prefix for WWNN/WWPN */ 3436 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 3437 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) 3438 hw_err(hw, "eeprom read at offset %d failed\n", offset); 3439 3440 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 3441 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) 3442 goto wwn_prefix_err; 3443 3444 return 0; 3445 3446 wwn_prefix_err: 3447 hw_err(hw, "eeprom read at offset %d failed\n", offset); 3448 return 0; 3449 } 3450 3451 /** 3452 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 3453 * @hw: pointer to hardware structure 3454 * @enable: enable or disable switch for MAC anti-spoofing 3455 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing 3456 * 3457 **/ 3458 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 3459 { 3460 int vf_target_reg = vf >> 3; 3461 int vf_target_shift = vf % 8; 3462 u32 pfvfspoof; 3463 3464 if (hw->mac.type == ixgbe_mac_82598EB) 3465 return; 3466 3467 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3468 if (enable) 3469 pfvfspoof |= BIT(vf_target_shift); 3470 else 3471 pfvfspoof &= ~BIT(vf_target_shift); 3472 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3473 } 3474 3475 /** 3476 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 3477 * @hw: pointer to hardware structure 3478 * @enable: enable or disable switch for VLAN anti-spoofing 3479 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 3480 * 3481 **/ 3482 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 3483 { 3484 int vf_target_reg = vf >> 3; 3485 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 3486 u32 pfvfspoof; 3487 3488 if (hw->mac.type == ixgbe_mac_82598EB) 3489 return; 3490 3491 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3492 if (enable) 3493 pfvfspoof |= BIT(vf_target_shift); 3494 else 3495 pfvfspoof &= ~BIT(vf_target_shift); 3496 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3497 } 3498 3499 /** 3500 * ixgbe_get_device_caps_generic - Get additional device capabilities 3501 * @hw: pointer to hardware structure 3502 * @device_caps: the EEPROM word with the extra device capabilities 3503 * 3504 * This function will read the EEPROM location for the device capabilities, 3505 * and return the word through device_caps. 3506 **/ 3507 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 3508 { 3509 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 3510 3511 return 0; 3512 } 3513 3514 /** 3515 * ixgbe_set_rxpba_generic - Initialize RX packet buffer 3516 * @hw: pointer to hardware structure 3517 * @num_pb: number of packet buffers to allocate 3518 * @headroom: reserve n KB of headroom 3519 * @strategy: packet buffer allocation strategy 3520 **/ 3521 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, 3522 int num_pb, 3523 u32 headroom, 3524 int strategy) 3525 { 3526 u32 pbsize = hw->mac.rx_pb_size; 3527 int i = 0; 3528 u32 rxpktsize, txpktsize, txpbthresh; 3529 3530 /* Reserve headroom */ 3531 pbsize -= headroom; 3532 3533 if (!num_pb) 3534 num_pb = 1; 3535 3536 /* Divide remaining packet buffer space amongst the number 3537 * of packet buffers requested using supplied strategy. 3538 */ 3539 switch (strategy) { 3540 case (PBA_STRATEGY_WEIGHTED): 3541 /* pba_80_48 strategy weight first half of packet buffer with 3542 * 5/8 of the packet buffer space. 3543 */ 3544 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8)); 3545 pbsize -= rxpktsize * (num_pb / 2); 3546 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 3547 for (; i < (num_pb / 2); i++) 3548 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 3549 /* fall through - configure remaining packet buffers */ 3550 case (PBA_STRATEGY_EQUAL): 3551 /* Divide the remaining Rx packet buffer evenly among the TCs */ 3552 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 3553 for (; i < num_pb; i++) 3554 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 3555 break; 3556 default: 3557 break; 3558 } 3559 3560 /* 3561 * Setup Tx packet buffer and threshold equally for all TCs 3562 * TXPBTHRESH register is set in K so divide by 1024 and subtract 3563 * 10 since the largest packet we support is just over 9K. 3564 */ 3565 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 3566 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 3567 for (i = 0; i < num_pb; i++) { 3568 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 3569 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 3570 } 3571 3572 /* Clear unused TCs, if any, to zero buffer size*/ 3573 for (; i < IXGBE_MAX_PB; i++) { 3574 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 3575 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 3576 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 3577 } 3578 } 3579 3580 /** 3581 * ixgbe_calculate_checksum - Calculate checksum for buffer 3582 * @buffer: pointer to EEPROM 3583 * @length: size of EEPROM to calculate a checksum for 3584 * 3585 * Calculates the checksum for some buffer on a specified length. The 3586 * checksum calculated is returned. 3587 **/ 3588 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 3589 { 3590 u32 i; 3591 u8 sum = 0; 3592 3593 if (!buffer) 3594 return 0; 3595 3596 for (i = 0; i < length; i++) 3597 sum += buffer[i]; 3598 3599 return (u8) (0 - sum); 3600 } 3601 3602 /** 3603 * ixgbe_hic_unlocked - Issue command to manageability block unlocked 3604 * @hw: pointer to the HW structure 3605 * @buffer: command to write and where the return status will be placed 3606 * @length: length of buffer, must be multiple of 4 bytes 3607 * @timeout: time in ms to wait for command completion 3608 * 3609 * Communicates with the manageability block. On success return 0 3610 * else returns semaphore error when encountering an error acquiring 3611 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 3612 * 3613 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held 3614 * by the caller. 3615 **/ 3616 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, 3617 u32 timeout) 3618 { 3619 u32 hicr, i, fwsts; 3620 u16 dword_len; 3621 3622 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 3623 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); 3624 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 3625 } 3626 3627 /* Set bit 9 of FWSTS clearing FW reset indication */ 3628 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); 3629 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); 3630 3631 /* Check that the host interface is enabled. */ 3632 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 3633 if (!(hicr & IXGBE_HICR_EN)) { 3634 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n"); 3635 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 3636 } 3637 3638 /* Calculate length in DWORDs. We must be DWORD aligned */ 3639 if (length % sizeof(u32)) { 3640 hw_dbg(hw, "Buffer length failure, not aligned to dword"); 3641 return IXGBE_ERR_INVALID_ARGUMENT; 3642 } 3643 3644 dword_len = length >> 2; 3645 3646 /* The device driver writes the relevant command block 3647 * into the ram area. 3648 */ 3649 for (i = 0; i < dword_len; i++) 3650 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 3651 i, cpu_to_le32(buffer[i])); 3652 3653 /* Setting this bit tells the ARC that a new command is pending. */ 3654 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 3655 3656 for (i = 0; i < timeout; i++) { 3657 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 3658 if (!(hicr & IXGBE_HICR_C)) 3659 break; 3660 usleep_range(1000, 2000); 3661 } 3662 3663 /* Check command successful completion. */ 3664 if ((timeout && i == timeout) || 3665 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) 3666 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 3667 3668 return 0; 3669 } 3670 3671 /** 3672 * ixgbe_host_interface_command - Issue command to manageability block 3673 * @hw: pointer to the HW structure 3674 * @buffer: contains the command to write and where the return status will 3675 * be placed 3676 * @length: length of buffer, must be multiple of 4 bytes 3677 * @timeout: time in ms to wait for command completion 3678 * @return_data: read and return data from the buffer (true) or not (false) 3679 * Needed because FW structures are big endian and decoding of 3680 * these fields can be 8 bit or 16 bit based on command. Decoding 3681 * is not easily understood without making a table of commands. 3682 * So we will leave this up to the caller to read back the data 3683 * in these cases. 3684 * 3685 * Communicates with the manageability block. On success return 0 3686 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND. 3687 **/ 3688 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *buffer, 3689 u32 length, u32 timeout, 3690 bool return_data) 3691 { 3692 u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 3693 union { 3694 struct ixgbe_hic_hdr hdr; 3695 u32 u32arr[1]; 3696 } *bp = buffer; 3697 u16 buf_len, dword_len; 3698 s32 status; 3699 u32 bi; 3700 3701 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 3702 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); 3703 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 3704 } 3705 /* Take management host interface semaphore */ 3706 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 3707 if (status) 3708 return status; 3709 3710 status = ixgbe_hic_unlocked(hw, buffer, length, timeout); 3711 if (status) 3712 goto rel_out; 3713 3714 if (!return_data) 3715 goto rel_out; 3716 3717 /* Calculate length in DWORDs */ 3718 dword_len = hdr_size >> 2; 3719 3720 /* first pull in the header so we know the buffer length */ 3721 for (bi = 0; bi < dword_len; bi++) { 3722 bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 3723 le32_to_cpus(&bp->u32arr[bi]); 3724 } 3725 3726 /* If there is any thing in data position pull it in */ 3727 buf_len = bp->hdr.buf_len; 3728 if (!buf_len) 3729 goto rel_out; 3730 3731 if (length < round_up(buf_len, 4) + hdr_size) { 3732 hw_dbg(hw, "Buffer not large enough for reply message.\n"); 3733 status = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3734 goto rel_out; 3735 } 3736 3737 /* Calculate length in DWORDs, add 3 for odd lengths */ 3738 dword_len = (buf_len + 3) >> 2; 3739 3740 /* Pull in the rest of the buffer (bi is where we left off) */ 3741 for (; bi <= dword_len; bi++) { 3742 bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 3743 le32_to_cpus(&bp->u32arr[bi]); 3744 } 3745 3746 rel_out: 3747 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 3748 3749 return status; 3750 } 3751 3752 /** 3753 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 3754 * @hw: pointer to the HW structure 3755 * @maj: driver version major number 3756 * @min: driver version minor number 3757 * @build: driver version build number 3758 * @sub: driver version sub build number 3759 * @len: length of driver_ver string 3760 * @driver_ver: driver string 3761 * 3762 * Sends driver version number to firmware through the manageability 3763 * block. On success return 0 3764 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 3765 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 3766 **/ 3767 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, 3768 u8 build, u8 sub, __always_unused u16 len, 3769 __always_unused const char *driver_ver) 3770 { 3771 struct ixgbe_hic_drv_info fw_cmd; 3772 int i; 3773 s32 ret_val; 3774 3775 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 3776 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 3777 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 3778 fw_cmd.port_num = hw->bus.func; 3779 fw_cmd.ver_maj = maj; 3780 fw_cmd.ver_min = min; 3781 fw_cmd.ver_build = build; 3782 fw_cmd.ver_sub = sub; 3783 fw_cmd.hdr.checksum = 0; 3784 fw_cmd.pad = 0; 3785 fw_cmd.pad2 = 0; 3786 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 3787 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 3788 3789 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 3790 ret_val = ixgbe_host_interface_command(hw, &fw_cmd, 3791 sizeof(fw_cmd), 3792 IXGBE_HI_COMMAND_TIMEOUT, 3793 true); 3794 if (ret_val != 0) 3795 continue; 3796 3797 if (fw_cmd.hdr.cmd_or_resp.ret_status == 3798 FW_CEM_RESP_STATUS_SUCCESS) 3799 ret_val = 0; 3800 else 3801 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3802 3803 break; 3804 } 3805 3806 return ret_val; 3807 } 3808 3809 /** 3810 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 3811 * @hw: pointer to the hardware structure 3812 * 3813 * The 82599 and x540 MACs can experience issues if TX work is still pending 3814 * when a reset occurs. This function prevents this by flushing the PCIe 3815 * buffers on the system. 3816 **/ 3817 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 3818 { 3819 u32 gcr_ext, hlreg0, i, poll; 3820 u16 value; 3821 3822 /* 3823 * If double reset is not requested then all transactions should 3824 * already be clear and as such there is no work to do 3825 */ 3826 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 3827 return; 3828 3829 /* 3830 * Set loopback enable to prevent any transmits from being sent 3831 * should the link come up. This assumes that the RXCTRL.RXEN bit 3832 * has already been cleared. 3833 */ 3834 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3835 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 3836 3837 /* wait for a last completion before clearing buffers */ 3838 IXGBE_WRITE_FLUSH(hw); 3839 usleep_range(3000, 6000); 3840 3841 /* Before proceeding, make sure that the PCIe block does not have 3842 * transactions pending. 3843 */ 3844 poll = ixgbe_pcie_timeout_poll(hw); 3845 for (i = 0; i < poll; i++) { 3846 usleep_range(100, 200); 3847 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); 3848 if (ixgbe_removed(hw->hw_addr)) 3849 break; 3850 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 3851 break; 3852 } 3853 3854 /* initiate cleaning flow for buffers in the PCIe transaction layer */ 3855 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 3856 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 3857 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 3858 3859 /* Flush all writes and allow 20usec for all transactions to clear */ 3860 IXGBE_WRITE_FLUSH(hw); 3861 udelay(20); 3862 3863 /* restore previous register values */ 3864 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 3865 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3866 } 3867 3868 static const u8 ixgbe_emc_temp_data[4] = { 3869 IXGBE_EMC_INTERNAL_DATA, 3870 IXGBE_EMC_DIODE1_DATA, 3871 IXGBE_EMC_DIODE2_DATA, 3872 IXGBE_EMC_DIODE3_DATA 3873 }; 3874 static const u8 ixgbe_emc_therm_limit[4] = { 3875 IXGBE_EMC_INTERNAL_THERM_LIMIT, 3876 IXGBE_EMC_DIODE1_THERM_LIMIT, 3877 IXGBE_EMC_DIODE2_THERM_LIMIT, 3878 IXGBE_EMC_DIODE3_THERM_LIMIT 3879 }; 3880 3881 /** 3882 * ixgbe_get_ets_data - Extracts the ETS bit data 3883 * @hw: pointer to hardware structure 3884 * @ets_cfg: extected ETS data 3885 * @ets_offset: offset of ETS data 3886 * 3887 * Returns error code. 3888 **/ 3889 static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg, 3890 u16 *ets_offset) 3891 { 3892 s32 status; 3893 3894 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset); 3895 if (status) 3896 return status; 3897 3898 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF)) 3899 return IXGBE_NOT_IMPLEMENTED; 3900 3901 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg); 3902 if (status) 3903 return status; 3904 3905 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED) 3906 return IXGBE_NOT_IMPLEMENTED; 3907 3908 return 0; 3909 } 3910 3911 /** 3912 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data 3913 * @hw: pointer to hardware structure 3914 * 3915 * Returns the thermal sensor data structure 3916 **/ 3917 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw) 3918 { 3919 s32 status; 3920 u16 ets_offset; 3921 u16 ets_cfg; 3922 u16 ets_sensor; 3923 u8 num_sensors; 3924 u8 i; 3925 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 3926 3927 /* Only support thermal sensors attached to physical port 0 */ 3928 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) 3929 return IXGBE_NOT_IMPLEMENTED; 3930 3931 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); 3932 if (status) 3933 return status; 3934 3935 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 3936 if (num_sensors > IXGBE_MAX_SENSORS) 3937 num_sensors = IXGBE_MAX_SENSORS; 3938 3939 for (i = 0; i < num_sensors; i++) { 3940 u8 sensor_index; 3941 u8 sensor_location; 3942 3943 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i), 3944 &ets_sensor); 3945 if (status) 3946 return status; 3947 3948 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 3949 IXGBE_ETS_DATA_INDEX_SHIFT); 3950 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 3951 IXGBE_ETS_DATA_LOC_SHIFT); 3952 3953 if (sensor_location != 0) { 3954 status = hw->phy.ops.read_i2c_byte(hw, 3955 ixgbe_emc_temp_data[sensor_index], 3956 IXGBE_I2C_THERMAL_SENSOR_ADDR, 3957 &data->sensor[i].temp); 3958 if (status) 3959 return status; 3960 } 3961 } 3962 3963 return 0; 3964 } 3965 3966 /** 3967 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds 3968 * @hw: pointer to hardware structure 3969 * 3970 * Inits the thermal sensor thresholds according to the NVM map 3971 * and save off the threshold and location values into mac.thermal_sensor_data 3972 **/ 3973 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw) 3974 { 3975 s32 status; 3976 u16 ets_offset; 3977 u16 ets_cfg; 3978 u16 ets_sensor; 3979 u8 low_thresh_delta; 3980 u8 num_sensors; 3981 u8 therm_limit; 3982 u8 i; 3983 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 3984 3985 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data)); 3986 3987 /* Only support thermal sensors attached to physical port 0 */ 3988 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) 3989 return IXGBE_NOT_IMPLEMENTED; 3990 3991 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); 3992 if (status) 3993 return status; 3994 3995 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >> 3996 IXGBE_ETS_LTHRES_DELTA_SHIFT); 3997 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 3998 if (num_sensors > IXGBE_MAX_SENSORS) 3999 num_sensors = IXGBE_MAX_SENSORS; 4000 4001 for (i = 0; i < num_sensors; i++) { 4002 u8 sensor_index; 4003 u8 sensor_location; 4004 4005 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) { 4006 hw_err(hw, "eeprom read at offset %d failed\n", 4007 ets_offset + 1 + i); 4008 continue; 4009 } 4010 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 4011 IXGBE_ETS_DATA_INDEX_SHIFT); 4012 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 4013 IXGBE_ETS_DATA_LOC_SHIFT); 4014 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK; 4015 4016 hw->phy.ops.write_i2c_byte(hw, 4017 ixgbe_emc_therm_limit[sensor_index], 4018 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit); 4019 4020 if (sensor_location == 0) 4021 continue; 4022 4023 data->sensor[i].location = sensor_location; 4024 data->sensor[i].caution_thresh = therm_limit; 4025 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta; 4026 } 4027 4028 return 0; 4029 } 4030 4031 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) 4032 { 4033 u32 rxctrl; 4034 4035 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4036 if (rxctrl & IXGBE_RXCTRL_RXEN) { 4037 if (hw->mac.type != ixgbe_mac_82598EB) { 4038 u32 pfdtxgswc; 4039 4040 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 4041 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 4042 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 4043 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 4044 hw->mac.set_lben = true; 4045 } else { 4046 hw->mac.set_lben = false; 4047 } 4048 } 4049 rxctrl &= ~IXGBE_RXCTRL_RXEN; 4050 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 4051 } 4052 } 4053 4054 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) 4055 { 4056 u32 rxctrl; 4057 4058 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4059 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); 4060 4061 if (hw->mac.type != ixgbe_mac_82598EB) { 4062 if (hw->mac.set_lben) { 4063 u32 pfdtxgswc; 4064 4065 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 4066 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN; 4067 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 4068 hw->mac.set_lben = false; 4069 } 4070 } 4071 } 4072 4073 /** ixgbe_mng_present - returns true when management capability is present 4074 * @hw: pointer to hardware structure 4075 **/ 4076 bool ixgbe_mng_present(struct ixgbe_hw *hw) 4077 { 4078 u32 fwsm; 4079 4080 if (hw->mac.type < ixgbe_mac_82599EB) 4081 return false; 4082 4083 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 4084 4085 return !!(fwsm & IXGBE_FWSM_FW_MODE_PT); 4086 } 4087 4088 /** 4089 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 4090 * @hw: pointer to hardware structure 4091 * @speed: new link speed 4092 * @autoneg_wait_to_complete: true when waiting for completion is needed 4093 * 4094 * Set the link speed in the MAC and/or PHY register and restarts link. 4095 */ 4096 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 4097 ixgbe_link_speed speed, 4098 bool autoneg_wait_to_complete) 4099 { 4100 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4101 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4102 s32 status = 0; 4103 u32 speedcnt = 0; 4104 u32 i = 0; 4105 bool autoneg, link_up = false; 4106 4107 /* Mask off requested but non-supported speeds */ 4108 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, &autoneg); 4109 if (status) 4110 return status; 4111 4112 speed &= link_speed; 4113 4114 /* Try each speed one by one, highest priority first. We do this in 4115 * software because 10Gb fiber doesn't support speed autonegotiation. 4116 */ 4117 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 4118 speedcnt++; 4119 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 4120 4121 /* Set the module link speed */ 4122 switch (hw->phy.media_type) { 4123 case ixgbe_media_type_fiber: 4124 hw->mac.ops.set_rate_select_speed(hw, 4125 IXGBE_LINK_SPEED_10GB_FULL); 4126 break; 4127 case ixgbe_media_type_fiber_qsfp: 4128 /* QSFP module automatically detects MAC link speed */ 4129 break; 4130 default: 4131 hw_dbg(hw, "Unexpected media type\n"); 4132 break; 4133 } 4134 4135 /* Allow module to change analog characteristics (1G->10G) */ 4136 msleep(40); 4137 4138 status = hw->mac.ops.setup_mac_link(hw, 4139 IXGBE_LINK_SPEED_10GB_FULL, 4140 autoneg_wait_to_complete); 4141 if (status) 4142 return status; 4143 4144 /* Flap the Tx laser if it has not already been done */ 4145 if (hw->mac.ops.flap_tx_laser) 4146 hw->mac.ops.flap_tx_laser(hw); 4147 4148 /* Wait for the controller to acquire link. Per IEEE 802.3ap, 4149 * Section 73.10.2, we may have to wait up to 500ms if KR is 4150 * attempted. 82599 uses the same timing for 10g SFI. 4151 */ 4152 for (i = 0; i < 5; i++) { 4153 /* Wait for the link partner to also set speed */ 4154 msleep(100); 4155 4156 /* If we have link, just jump out */ 4157 status = hw->mac.ops.check_link(hw, &link_speed, 4158 &link_up, false); 4159 if (status) 4160 return status; 4161 4162 if (link_up) 4163 goto out; 4164 } 4165 } 4166 4167 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 4168 speedcnt++; 4169 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 4170 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 4171 4172 /* Set the module link speed */ 4173 switch (hw->phy.media_type) { 4174 case ixgbe_media_type_fiber: 4175 hw->mac.ops.set_rate_select_speed(hw, 4176 IXGBE_LINK_SPEED_1GB_FULL); 4177 break; 4178 case ixgbe_media_type_fiber_qsfp: 4179 /* QSFP module automatically detects link speed */ 4180 break; 4181 default: 4182 hw_dbg(hw, "Unexpected media type\n"); 4183 break; 4184 } 4185 4186 /* Allow module to change analog characteristics (10G->1G) */ 4187 msleep(40); 4188 4189 status = hw->mac.ops.setup_mac_link(hw, 4190 IXGBE_LINK_SPEED_1GB_FULL, 4191 autoneg_wait_to_complete); 4192 if (status) 4193 return status; 4194 4195 /* Flap the Tx laser if it has not already been done */ 4196 if (hw->mac.ops.flap_tx_laser) 4197 hw->mac.ops.flap_tx_laser(hw); 4198 4199 /* Wait for the link partner to also set speed */ 4200 msleep(100); 4201 4202 /* If we have link, just jump out */ 4203 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 4204 false); 4205 if (status) 4206 return status; 4207 4208 if (link_up) 4209 goto out; 4210 } 4211 4212 /* We didn't get link. Configure back to the highest speed we tried, 4213 * (if there was more than one). We call ourselves back with just the 4214 * single highest speed that the user requested. 4215 */ 4216 if (speedcnt > 1) 4217 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 4218 highest_link_speed, 4219 autoneg_wait_to_complete); 4220 4221 out: 4222 /* Set autoneg_advertised value based on input link speed */ 4223 hw->phy.autoneg_advertised = 0; 4224 4225 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 4226 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 4227 4228 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 4229 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 4230 4231 return status; 4232 } 4233 4234 /** 4235 * ixgbe_set_soft_rate_select_speed - Set module link speed 4236 * @hw: pointer to hardware structure 4237 * @speed: link speed to set 4238 * 4239 * Set module link speed via the soft rate select. 4240 */ 4241 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, 4242 ixgbe_link_speed speed) 4243 { 4244 s32 status; 4245 u8 rs, eeprom_data; 4246 4247 switch (speed) { 4248 case IXGBE_LINK_SPEED_10GB_FULL: 4249 /* one bit mask same as setting on */ 4250 rs = IXGBE_SFF_SOFT_RS_SELECT_10G; 4251 break; 4252 case IXGBE_LINK_SPEED_1GB_FULL: 4253 rs = IXGBE_SFF_SOFT_RS_SELECT_1G; 4254 break; 4255 default: 4256 hw_dbg(hw, "Invalid fixed module speed\n"); 4257 return; 4258 } 4259 4260 /* Set RS0 */ 4261 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 4262 IXGBE_I2C_EEPROM_DEV_ADDR2, 4263 &eeprom_data); 4264 if (status) { 4265 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n"); 4266 return; 4267 } 4268 4269 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 4270 4271 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 4272 IXGBE_I2C_EEPROM_DEV_ADDR2, 4273 eeprom_data); 4274 if (status) { 4275 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n"); 4276 return; 4277 } 4278 4279 /* Set RS1 */ 4280 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 4281 IXGBE_I2C_EEPROM_DEV_ADDR2, 4282 &eeprom_data); 4283 if (status) { 4284 hw_dbg(hw, "Failed to read Rx Rate Select RS1\n"); 4285 return; 4286 } 4287 4288 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 4289 4290 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 4291 IXGBE_I2C_EEPROM_DEV_ADDR2, 4292 eeprom_data); 4293 if (status) { 4294 hw_dbg(hw, "Failed to write Rx Rate Select RS1\n"); 4295 return; 4296 } 4297 } 4298