1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2011 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #include <linux/pci.h> 29 #include <linux/delay.h> 30 #include <linux/sched.h> 31 32 #include "ixgbe.h" 33 #include "ixgbe_phy.h" 34 #include "ixgbe_mbx.h" 35 36 #define IXGBE_82599_MAX_TX_QUEUES 128 37 #define IXGBE_82599_MAX_RX_QUEUES 128 38 #define IXGBE_82599_RAR_ENTRIES 128 39 #define IXGBE_82599_MC_TBL_SIZE 128 40 #define IXGBE_82599_VFT_TBL_SIZE 128 41 #define IXGBE_82599_RX_PB_SIZE 512 42 43 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 44 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 45 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 46 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 47 ixgbe_link_speed speed, 48 bool autoneg, 49 bool autoneg_wait_to_complete); 50 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 51 ixgbe_link_speed speed, 52 bool autoneg, 53 bool autoneg_wait_to_complete); 54 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 55 bool autoneg_wait_to_complete); 56 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 57 ixgbe_link_speed speed, 58 bool autoneg, 59 bool autoneg_wait_to_complete); 60 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 61 ixgbe_link_speed speed, 62 bool autoneg, 63 bool autoneg_wait_to_complete); 64 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 65 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw); 66 67 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 68 { 69 struct ixgbe_mac_info *mac = &hw->mac; 70 71 /* enable the laser control functions for SFP+ fiber */ 72 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) { 73 mac->ops.disable_tx_laser = 74 &ixgbe_disable_tx_laser_multispeed_fiber; 75 mac->ops.enable_tx_laser = 76 &ixgbe_enable_tx_laser_multispeed_fiber; 77 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; 78 } else { 79 mac->ops.disable_tx_laser = NULL; 80 mac->ops.enable_tx_laser = NULL; 81 mac->ops.flap_tx_laser = NULL; 82 } 83 84 if (hw->phy.multispeed_fiber) { 85 /* Set up dual speed SFP+ support */ 86 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; 87 } else { 88 if ((mac->ops.get_media_type(hw) == 89 ixgbe_media_type_backplane) && 90 (hw->phy.smart_speed == ixgbe_smart_speed_auto || 91 hw->phy.smart_speed == ixgbe_smart_speed_on) && 92 !ixgbe_verify_lesm_fw_enabled_82599(hw)) 93 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; 94 else 95 mac->ops.setup_link = &ixgbe_setup_mac_link_82599; 96 } 97 } 98 99 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 100 { 101 s32 ret_val = 0; 102 u32 reg_anlp1 = 0; 103 u32 i = 0; 104 u16 list_offset, data_offset, data_value; 105 106 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 107 ixgbe_init_mac_link_ops_82599(hw); 108 109 hw->phy.ops.reset = NULL; 110 111 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 112 &data_offset); 113 if (ret_val != 0) 114 goto setup_sfp_out; 115 116 /* PHY config will finish before releasing the semaphore */ 117 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 118 IXGBE_GSSR_MAC_CSR_SM); 119 if (ret_val != 0) { 120 ret_val = IXGBE_ERR_SWFW_SYNC; 121 goto setup_sfp_out; 122 } 123 124 hw->eeprom.ops.read(hw, ++data_offset, &data_value); 125 while (data_value != 0xffff) { 126 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); 127 IXGBE_WRITE_FLUSH(hw); 128 hw->eeprom.ops.read(hw, ++data_offset, &data_value); 129 } 130 131 /* Release the semaphore */ 132 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 133 /* 134 * Delay obtaining semaphore again to allow FW access, 135 * semaphore_delay is in ms usleep_range needs us. 136 */ 137 usleep_range(hw->eeprom.semaphore_delay * 1000, 138 hw->eeprom.semaphore_delay * 2000); 139 140 /* Now restart DSP by setting Restart_AN and clearing LMS */ 141 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw, 142 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) | 143 IXGBE_AUTOC_AN_RESTART)); 144 145 /* Wait for AN to leave state 0 */ 146 for (i = 0; i < 10; i++) { 147 usleep_range(4000, 8000); 148 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1); 149 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK) 150 break; 151 } 152 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) { 153 hw_dbg(hw, "sfp module setup not complete\n"); 154 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 155 goto setup_sfp_out; 156 } 157 158 /* Restart DSP by setting Restart_AN and return to SFI mode */ 159 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw, 160 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL | 161 IXGBE_AUTOC_AN_RESTART)); 162 } 163 164 setup_sfp_out: 165 return ret_val; 166 } 167 168 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw) 169 { 170 struct ixgbe_mac_info *mac = &hw->mac; 171 172 ixgbe_init_mac_link_ops_82599(hw); 173 174 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; 175 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; 176 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; 177 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; 178 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; 179 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 180 181 return 0; 182 } 183 184 /** 185 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init 186 * @hw: pointer to hardware structure 187 * 188 * Initialize any function pointers that were not able to be 189 * set during get_invariants because the PHY/SFP type was 190 * not known. Perform the SFP init if necessary. 191 * 192 **/ 193 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 194 { 195 struct ixgbe_mac_info *mac = &hw->mac; 196 struct ixgbe_phy_info *phy = &hw->phy; 197 s32 ret_val = 0; 198 199 /* Identify the PHY or SFP module */ 200 ret_val = phy->ops.identify(hw); 201 202 /* Setup function pointers based on detected SFP module and speeds */ 203 ixgbe_init_mac_link_ops_82599(hw); 204 205 /* If copper media, overwrite with copper function pointers */ 206 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 207 mac->ops.setup_link = &ixgbe_setup_copper_link_82599; 208 mac->ops.get_link_capabilities = 209 &ixgbe_get_copper_link_capabilities_generic; 210 } 211 212 /* Set necessary function pointers based on phy type */ 213 switch (hw->phy.type) { 214 case ixgbe_phy_tn: 215 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 216 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; 217 phy->ops.get_firmware_version = 218 &ixgbe_get_phy_firmware_version_tnx; 219 break; 220 default: 221 break; 222 } 223 224 return ret_val; 225 } 226 227 /** 228 * ixgbe_get_link_capabilities_82599 - Determines link capabilities 229 * @hw: pointer to hardware structure 230 * @speed: pointer to link speed 231 * @negotiation: true when autoneg or autotry is enabled 232 * 233 * Determines the link capabilities by reading the AUTOC register. 234 **/ 235 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 236 ixgbe_link_speed *speed, 237 bool *negotiation) 238 { 239 s32 status = 0; 240 u32 autoc = 0; 241 242 /* Determine 1G link capabilities off of SFP+ type */ 243 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 244 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) { 245 *speed = IXGBE_LINK_SPEED_1GB_FULL; 246 *negotiation = true; 247 goto out; 248 } 249 250 /* 251 * Determine link capabilities based on the stored value of AUTOC, 252 * which represents EEPROM defaults. If AUTOC value has not been 253 * stored, use the current register value. 254 */ 255 if (hw->mac.orig_link_settings_stored) 256 autoc = hw->mac.orig_autoc; 257 else 258 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 259 260 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 261 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 262 *speed = IXGBE_LINK_SPEED_1GB_FULL; 263 *negotiation = false; 264 break; 265 266 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 267 *speed = IXGBE_LINK_SPEED_10GB_FULL; 268 *negotiation = false; 269 break; 270 271 case IXGBE_AUTOC_LMS_1G_AN: 272 *speed = IXGBE_LINK_SPEED_1GB_FULL; 273 *negotiation = true; 274 break; 275 276 case IXGBE_AUTOC_LMS_10G_SERIAL: 277 *speed = IXGBE_LINK_SPEED_10GB_FULL; 278 *negotiation = false; 279 break; 280 281 case IXGBE_AUTOC_LMS_KX4_KX_KR: 282 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 283 *speed = IXGBE_LINK_SPEED_UNKNOWN; 284 if (autoc & IXGBE_AUTOC_KR_SUPP) 285 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 286 if (autoc & IXGBE_AUTOC_KX4_SUPP) 287 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 288 if (autoc & IXGBE_AUTOC_KX_SUPP) 289 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 290 *negotiation = true; 291 break; 292 293 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: 294 *speed = IXGBE_LINK_SPEED_100_FULL; 295 if (autoc & IXGBE_AUTOC_KR_SUPP) 296 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 297 if (autoc & IXGBE_AUTOC_KX4_SUPP) 298 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 299 if (autoc & IXGBE_AUTOC_KX_SUPP) 300 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 301 *negotiation = true; 302 break; 303 304 case IXGBE_AUTOC_LMS_SGMII_1G_100M: 305 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; 306 *negotiation = false; 307 break; 308 309 default: 310 status = IXGBE_ERR_LINK_SETUP; 311 goto out; 312 break; 313 } 314 315 if (hw->phy.multispeed_fiber) { 316 *speed |= IXGBE_LINK_SPEED_10GB_FULL | 317 IXGBE_LINK_SPEED_1GB_FULL; 318 *negotiation = true; 319 } 320 321 out: 322 return status; 323 } 324 325 /** 326 * ixgbe_get_media_type_82599 - Get media type 327 * @hw: pointer to hardware structure 328 * 329 * Returns the media type (fiber, copper, backplane) 330 **/ 331 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 332 { 333 enum ixgbe_media_type media_type; 334 335 /* Detect if there is a copper PHY attached. */ 336 switch (hw->phy.type) { 337 case ixgbe_phy_cu_unknown: 338 case ixgbe_phy_tn: 339 media_type = ixgbe_media_type_copper; 340 goto out; 341 default: 342 break; 343 } 344 345 switch (hw->device_id) { 346 case IXGBE_DEV_ID_82599_KX4: 347 case IXGBE_DEV_ID_82599_KX4_MEZZ: 348 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 349 case IXGBE_DEV_ID_82599_KR: 350 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 351 case IXGBE_DEV_ID_82599_XAUI_LOM: 352 /* Default device ID is mezzanine card KX/KX4 */ 353 media_type = ixgbe_media_type_backplane; 354 break; 355 case IXGBE_DEV_ID_82599_SFP: 356 case IXGBE_DEV_ID_82599_SFP_FCOE: 357 case IXGBE_DEV_ID_82599_SFP_EM: 358 case IXGBE_DEV_ID_82599_SFP_SF2: 359 case IXGBE_DEV_ID_82599EN_SFP: 360 media_type = ixgbe_media_type_fiber; 361 break; 362 case IXGBE_DEV_ID_82599_CX4: 363 media_type = ixgbe_media_type_cx4; 364 break; 365 case IXGBE_DEV_ID_82599_T3_LOM: 366 media_type = ixgbe_media_type_copper; 367 break; 368 case IXGBE_DEV_ID_82599_LS: 369 media_type = ixgbe_media_type_fiber_lco; 370 break; 371 default: 372 media_type = ixgbe_media_type_unknown; 373 break; 374 } 375 out: 376 return media_type; 377 } 378 379 /** 380 * ixgbe_start_mac_link_82599 - Setup MAC link settings 381 * @hw: pointer to hardware structure 382 * @autoneg_wait_to_complete: true when waiting for completion is needed 383 * 384 * Configures link settings based on values in the ixgbe_hw struct. 385 * Restarts the link. Performs autonegotiation if needed. 386 **/ 387 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 388 bool autoneg_wait_to_complete) 389 { 390 u32 autoc_reg; 391 u32 links_reg; 392 u32 i; 393 s32 status = 0; 394 395 /* Restart link */ 396 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 397 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 398 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 399 400 /* Only poll for autoneg to complete if specified to do so */ 401 if (autoneg_wait_to_complete) { 402 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 403 IXGBE_AUTOC_LMS_KX4_KX_KR || 404 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 405 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 406 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 407 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 408 links_reg = 0; /* Just in case Autoneg time = 0 */ 409 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 410 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 411 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 412 break; 413 msleep(100); 414 } 415 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 416 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 417 hw_dbg(hw, "Autoneg did not complete.\n"); 418 } 419 } 420 } 421 422 /* Add delay to filter out noises during initial link setup */ 423 msleep(50); 424 425 return status; 426 } 427 428 /** 429 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser 430 * @hw: pointer to hardware structure 431 * 432 * The base drivers may require better control over SFP+ module 433 * PHY states. This includes selectively shutting down the Tx 434 * laser on the PHY, effectively halting physical link. 435 **/ 436 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 437 { 438 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 439 440 /* Disable tx laser; allow 100us to go dark per spec */ 441 esdp_reg |= IXGBE_ESDP_SDP3; 442 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 443 IXGBE_WRITE_FLUSH(hw); 444 udelay(100); 445 } 446 447 /** 448 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser 449 * @hw: pointer to hardware structure 450 * 451 * The base drivers may require better control over SFP+ module 452 * PHY states. This includes selectively turning on the Tx 453 * laser on the PHY, effectively starting physical link. 454 **/ 455 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 456 { 457 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 458 459 /* Enable tx laser; allow 100ms to light up */ 460 esdp_reg &= ~IXGBE_ESDP_SDP3; 461 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 462 IXGBE_WRITE_FLUSH(hw); 463 msleep(100); 464 } 465 466 /** 467 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser 468 * @hw: pointer to hardware structure 469 * 470 * When the driver changes the link speeds that it can support, 471 * it sets autotry_restart to true to indicate that we need to 472 * initiate a new autotry session with the link partner. To do 473 * so, we set the speed then disable and re-enable the tx laser, to 474 * alert the link partner that it also needs to restart autotry on its 475 * end. This is consistent with true clause 37 autoneg, which also 476 * involves a loss of signal. 477 **/ 478 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 479 { 480 if (hw->mac.autotry_restart) { 481 ixgbe_disable_tx_laser_multispeed_fiber(hw); 482 ixgbe_enable_tx_laser_multispeed_fiber(hw); 483 hw->mac.autotry_restart = false; 484 } 485 } 486 487 /** 488 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 489 * @hw: pointer to hardware structure 490 * @speed: new link speed 491 * @autoneg: true if autonegotiation enabled 492 * @autoneg_wait_to_complete: true when waiting for completion is needed 493 * 494 * Set the link speed in the AUTOC register and restarts link. 495 **/ 496 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 497 ixgbe_link_speed speed, 498 bool autoneg, 499 bool autoneg_wait_to_complete) 500 { 501 s32 status = 0; 502 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 503 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 504 u32 speedcnt = 0; 505 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 506 u32 i = 0; 507 bool link_up = false; 508 bool negotiation; 509 510 /* Mask off requested but non-supported speeds */ 511 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, 512 &negotiation); 513 if (status != 0) 514 return status; 515 516 speed &= link_speed; 517 518 /* 519 * Try each speed one by one, highest priority first. We do this in 520 * software because 10gb fiber doesn't support speed autonegotiation. 521 */ 522 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 523 speedcnt++; 524 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 525 526 /* If we already have link at this speed, just jump out */ 527 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 528 false); 529 if (status != 0) 530 return status; 531 532 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up) 533 goto out; 534 535 /* Set the module link speed */ 536 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); 537 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 538 IXGBE_WRITE_FLUSH(hw); 539 540 /* Allow module to change analog characteristics (1G->10G) */ 541 msleep(40); 542 543 status = ixgbe_setup_mac_link_82599(hw, 544 IXGBE_LINK_SPEED_10GB_FULL, 545 autoneg, 546 autoneg_wait_to_complete); 547 if (status != 0) 548 return status; 549 550 /* Flap the tx laser if it has not already been done */ 551 hw->mac.ops.flap_tx_laser(hw); 552 553 /* 554 * Wait for the controller to acquire link. Per IEEE 802.3ap, 555 * Section 73.10.2, we may have to wait up to 500ms if KR is 556 * attempted. 82599 uses the same timing for 10g SFI. 557 */ 558 for (i = 0; i < 5; i++) { 559 /* Wait for the link partner to also set speed */ 560 msleep(100); 561 562 /* If we have link, just jump out */ 563 status = hw->mac.ops.check_link(hw, &link_speed, 564 &link_up, false); 565 if (status != 0) 566 return status; 567 568 if (link_up) 569 goto out; 570 } 571 } 572 573 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 574 speedcnt++; 575 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 576 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 577 578 /* If we already have link at this speed, just jump out */ 579 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 580 false); 581 if (status != 0) 582 return status; 583 584 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up) 585 goto out; 586 587 /* Set the module link speed */ 588 esdp_reg &= ~IXGBE_ESDP_SDP5; 589 esdp_reg |= IXGBE_ESDP_SDP5_DIR; 590 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 591 IXGBE_WRITE_FLUSH(hw); 592 593 /* Allow module to change analog characteristics (10G->1G) */ 594 msleep(40); 595 596 status = ixgbe_setup_mac_link_82599(hw, 597 IXGBE_LINK_SPEED_1GB_FULL, 598 autoneg, 599 autoneg_wait_to_complete); 600 if (status != 0) 601 return status; 602 603 /* Flap the tx laser if it has not already been done */ 604 hw->mac.ops.flap_tx_laser(hw); 605 606 /* Wait for the link partner to also set speed */ 607 msleep(100); 608 609 /* If we have link, just jump out */ 610 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 611 false); 612 if (status != 0) 613 return status; 614 615 if (link_up) 616 goto out; 617 } 618 619 /* 620 * We didn't get link. Configure back to the highest speed we tried, 621 * (if there was more than one). We call ourselves back with just the 622 * single highest speed that the user requested. 623 */ 624 if (speedcnt > 1) 625 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 626 highest_link_speed, 627 autoneg, 628 autoneg_wait_to_complete); 629 630 out: 631 /* Set autoneg_advertised value based on input link speed */ 632 hw->phy.autoneg_advertised = 0; 633 634 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 635 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 636 637 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 638 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 639 640 return status; 641 } 642 643 /** 644 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed 645 * @hw: pointer to hardware structure 646 * @speed: new link speed 647 * @autoneg: true if autonegotiation enabled 648 * @autoneg_wait_to_complete: true when waiting for completion is needed 649 * 650 * Implements the Intel SmartSpeed algorithm. 651 **/ 652 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 653 ixgbe_link_speed speed, bool autoneg, 654 bool autoneg_wait_to_complete) 655 { 656 s32 status = 0; 657 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 658 s32 i, j; 659 bool link_up = false; 660 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 661 662 /* Set autoneg_advertised value based on input link speed */ 663 hw->phy.autoneg_advertised = 0; 664 665 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 666 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 667 668 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 669 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 670 671 if (speed & IXGBE_LINK_SPEED_100_FULL) 672 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 673 674 /* 675 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the 676 * autoneg advertisement if link is unable to be established at the 677 * highest negotiated rate. This can sometimes happen due to integrity 678 * issues with the physical media connection. 679 */ 680 681 /* First, try to get link with full advertisement */ 682 hw->phy.smart_speed_active = false; 683 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { 684 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 685 autoneg_wait_to_complete); 686 if (status != 0) 687 goto out; 688 689 /* 690 * Wait for the controller to acquire link. Per IEEE 802.3ap, 691 * Section 73.10.2, we may have to wait up to 500ms if KR is 692 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per 693 * Table 9 in the AN MAS. 694 */ 695 for (i = 0; i < 5; i++) { 696 mdelay(100); 697 698 /* If we have link, just jump out */ 699 status = hw->mac.ops.check_link(hw, &link_speed, 700 &link_up, false); 701 if (status != 0) 702 goto out; 703 704 if (link_up) 705 goto out; 706 } 707 } 708 709 /* 710 * We didn't get link. If we advertised KR plus one of KX4/KX 711 * (or BX4/BX), then disable KR and try again. 712 */ 713 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || 714 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) 715 goto out; 716 717 /* Turn SmartSpeed on to disable KR support */ 718 hw->phy.smart_speed_active = true; 719 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 720 autoneg_wait_to_complete); 721 if (status != 0) 722 goto out; 723 724 /* 725 * Wait for the controller to acquire link. 600ms will allow for 726 * the AN link_fail_inhibit_timer as well for multiple cycles of 727 * parallel detect, both 10g and 1g. This allows for the maximum 728 * connect attempts as defined in the AN MAS table 73-7. 729 */ 730 for (i = 0; i < 6; i++) { 731 mdelay(100); 732 733 /* If we have link, just jump out */ 734 status = hw->mac.ops.check_link(hw, &link_speed, 735 &link_up, false); 736 if (status != 0) 737 goto out; 738 739 if (link_up) 740 goto out; 741 } 742 743 /* We didn't get link. Turn SmartSpeed back off. */ 744 hw->phy.smart_speed_active = false; 745 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 746 autoneg_wait_to_complete); 747 748 out: 749 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) 750 hw_dbg(hw, "Smartspeed has downgraded the link speed from " 751 "the maximum advertised\n"); 752 return status; 753 } 754 755 /** 756 * ixgbe_setup_mac_link_82599 - Set MAC link speed 757 * @hw: pointer to hardware structure 758 * @speed: new link speed 759 * @autoneg: true if autonegotiation enabled 760 * @autoneg_wait_to_complete: true when waiting for completion is needed 761 * 762 * Set the link speed in the AUTOC register and restarts link. 763 **/ 764 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 765 ixgbe_link_speed speed, bool autoneg, 766 bool autoneg_wait_to_complete) 767 { 768 s32 status = 0; 769 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 770 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 771 u32 start_autoc = autoc; 772 u32 orig_autoc = 0; 773 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 774 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 775 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 776 u32 links_reg; 777 u32 i; 778 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 779 780 /* Check to see if speed passed in is supported. */ 781 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg); 782 if (status != 0) 783 goto out; 784 785 speed &= link_capabilities; 786 787 if (speed == IXGBE_LINK_SPEED_UNKNOWN) { 788 status = IXGBE_ERR_LINK_SETUP; 789 goto out; 790 } 791 792 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ 793 if (hw->mac.orig_link_settings_stored) 794 orig_autoc = hw->mac.orig_autoc; 795 else 796 orig_autoc = autoc; 797 798 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 799 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 800 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 801 /* Set KX4/KX/KR support according to speed requested */ 802 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); 803 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 804 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) 805 autoc |= IXGBE_AUTOC_KX4_SUPP; 806 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && 807 (hw->phy.smart_speed_active == false)) 808 autoc |= IXGBE_AUTOC_KR_SUPP; 809 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 810 autoc |= IXGBE_AUTOC_KX_SUPP; 811 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && 812 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || 813 link_mode == IXGBE_AUTOC_LMS_1G_AN)) { 814 /* Switch from 1G SFI to 10G SFI if requested */ 815 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 816 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { 817 autoc &= ~IXGBE_AUTOC_LMS_MASK; 818 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; 819 } 820 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && 821 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { 822 /* Switch from 10G SFI to 1G SFI if requested */ 823 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 824 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { 825 autoc &= ~IXGBE_AUTOC_LMS_MASK; 826 if (autoneg) 827 autoc |= IXGBE_AUTOC_LMS_1G_AN; 828 else 829 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 830 } 831 } 832 833 if (autoc != start_autoc) { 834 /* Restart link */ 835 autoc |= IXGBE_AUTOC_AN_RESTART; 836 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 837 838 /* Only poll for autoneg to complete if specified to do so */ 839 if (autoneg_wait_to_complete) { 840 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 841 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 842 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 843 links_reg = 0; /*Just in case Autoneg time=0*/ 844 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 845 links_reg = 846 IXGBE_READ_REG(hw, IXGBE_LINKS); 847 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 848 break; 849 msleep(100); 850 } 851 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 852 status = 853 IXGBE_ERR_AUTONEG_NOT_COMPLETE; 854 hw_dbg(hw, "Autoneg did not " 855 "complete.\n"); 856 } 857 } 858 } 859 860 /* Add delay to filter out noises during initial link setup */ 861 msleep(50); 862 } 863 864 out: 865 return status; 866 } 867 868 /** 869 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field 870 * @hw: pointer to hardware structure 871 * @speed: new link speed 872 * @autoneg: true if autonegotiation enabled 873 * @autoneg_wait_to_complete: true if waiting is needed to complete 874 * 875 * Restarts link on PHY and MAC based on settings passed in. 876 **/ 877 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 878 ixgbe_link_speed speed, 879 bool autoneg, 880 bool autoneg_wait_to_complete) 881 { 882 s32 status; 883 884 /* Setup the PHY according to input speed */ 885 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 886 autoneg_wait_to_complete); 887 /* Set up MAC */ 888 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); 889 890 return status; 891 } 892 893 /** 894 * ixgbe_reset_hw_82599 - Perform hardware reset 895 * @hw: pointer to hardware structure 896 * 897 * Resets the hardware by resetting the transmit and receive units, masks 898 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 899 * reset. 900 **/ 901 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 902 { 903 ixgbe_link_speed link_speed; 904 s32 status; 905 u32 ctrl, i, autoc, autoc2; 906 bool link_up = false; 907 908 /* Call adapter stop to disable tx/rx and clear interrupts */ 909 status = hw->mac.ops.stop_adapter(hw); 910 if (status != 0) 911 goto reset_hw_out; 912 913 /* flush pending Tx transactions */ 914 ixgbe_clear_tx_pending(hw); 915 916 /* PHY ops must be identified and initialized prior to reset */ 917 918 /* Identify PHY and related function pointers */ 919 status = hw->phy.ops.init(hw); 920 921 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 922 goto reset_hw_out; 923 924 /* Setup SFP module if there is one present. */ 925 if (hw->phy.sfp_setup_needed) { 926 status = hw->mac.ops.setup_sfp(hw); 927 hw->phy.sfp_setup_needed = false; 928 } 929 930 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 931 goto reset_hw_out; 932 933 /* Reset PHY */ 934 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) 935 hw->phy.ops.reset(hw); 936 937 mac_reset_top: 938 /* 939 * Issue global reset to the MAC. Needs to be SW reset if link is up. 940 * If link reset is used when link is up, it might reset the PHY when 941 * mng is using it. If link is down or the flag to force full link 942 * reset is set, then perform link reset. 943 */ 944 ctrl = IXGBE_CTRL_LNK_RST; 945 if (!hw->force_full_reset) { 946 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 947 if (link_up) 948 ctrl = IXGBE_CTRL_RST; 949 } 950 951 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 952 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 953 IXGBE_WRITE_FLUSH(hw); 954 955 /* Poll for reset bit to self-clear indicating reset is complete */ 956 for (i = 0; i < 10; i++) { 957 udelay(1); 958 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 959 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 960 break; 961 } 962 963 if (ctrl & IXGBE_CTRL_RST_MASK) { 964 status = IXGBE_ERR_RESET_FAILED; 965 hw_dbg(hw, "Reset polling failed to complete.\n"); 966 } 967 968 msleep(50); 969 970 /* 971 * Double resets are required for recovery from certain error 972 * conditions. Between resets, it is necessary to stall to allow time 973 * for any pending HW events to complete. 974 */ 975 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 976 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 977 goto mac_reset_top; 978 } 979 980 /* 981 * Store the original AUTOC/AUTOC2 values if they have not been 982 * stored off yet. Otherwise restore the stored original 983 * values since the reset operation sets back to defaults. 984 */ 985 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 986 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 987 if (hw->mac.orig_link_settings_stored == false) { 988 hw->mac.orig_autoc = autoc; 989 hw->mac.orig_autoc2 = autoc2; 990 hw->mac.orig_link_settings_stored = true; 991 } else { 992 if (autoc != hw->mac.orig_autoc) 993 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc | 994 IXGBE_AUTOC_AN_RESTART)); 995 996 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != 997 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { 998 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; 999 autoc2 |= (hw->mac.orig_autoc2 & 1000 IXGBE_AUTOC2_UPPER_MASK); 1001 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1002 } 1003 } 1004 1005 /* Store the permanent mac address */ 1006 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1007 1008 /* 1009 * Store MAC address from RAR0, clear receive address registers, and 1010 * clear the multicast table. Also reset num_rar_entries to 128, 1011 * since we modify this value when programming the SAN MAC address. 1012 */ 1013 hw->mac.num_rar_entries = 128; 1014 hw->mac.ops.init_rx_addrs(hw); 1015 1016 /* Store the permanent SAN mac address */ 1017 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 1018 1019 /* Add the SAN MAC address to the RAR only if it's a valid address */ 1020 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 1021 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, 1022 hw->mac.san_addr, 0, IXGBE_RAH_AV); 1023 1024 /* Reserve the last RAR for the SAN MAC address */ 1025 hw->mac.num_rar_entries--; 1026 } 1027 1028 /* Store the alternative WWNN/WWPN prefix */ 1029 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 1030 &hw->mac.wwpn_prefix); 1031 1032 reset_hw_out: 1033 return status; 1034 } 1035 1036 /** 1037 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. 1038 * @hw: pointer to hardware structure 1039 **/ 1040 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) 1041 { 1042 int i; 1043 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1044 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; 1045 1046 /* 1047 * Before starting reinitialization process, 1048 * FDIRCMD.CMD must be zero. 1049 */ 1050 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { 1051 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1052 IXGBE_FDIRCMD_CMD_MASK)) 1053 break; 1054 udelay(10); 1055 } 1056 if (i >= IXGBE_FDIRCMD_CMD_POLL) { 1057 hw_dbg(hw, "Flow Director previous command isn't complete, " 1058 "aborting table re-initialization.\n"); 1059 return IXGBE_ERR_FDIR_REINIT_FAILED; 1060 } 1061 1062 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); 1063 IXGBE_WRITE_FLUSH(hw); 1064 /* 1065 * 82599 adapters flow director init flow cannot be restarted, 1066 * Workaround 82599 silicon errata by performing the following steps 1067 * before re-writing the FDIRCTRL control register with the same value. 1068 * - write 1 to bit 8 of FDIRCMD register & 1069 * - write 0 to bit 8 of FDIRCMD register 1070 */ 1071 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1072 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1073 IXGBE_FDIRCMD_CLEARHT)); 1074 IXGBE_WRITE_FLUSH(hw); 1075 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1076 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1077 ~IXGBE_FDIRCMD_CLEARHT)); 1078 IXGBE_WRITE_FLUSH(hw); 1079 /* 1080 * Clear FDIR Hash register to clear any leftover hashes 1081 * waiting to be programmed. 1082 */ 1083 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); 1084 IXGBE_WRITE_FLUSH(hw); 1085 1086 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1087 IXGBE_WRITE_FLUSH(hw); 1088 1089 /* Poll init-done after we write FDIRCTRL register */ 1090 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1091 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1092 IXGBE_FDIRCTRL_INIT_DONE) 1093 break; 1094 udelay(10); 1095 } 1096 if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 1097 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n"); 1098 return IXGBE_ERR_FDIR_REINIT_FAILED; 1099 } 1100 1101 /* Clear FDIR statistics registers (read to clear) */ 1102 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); 1103 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); 1104 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 1105 IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 1106 IXGBE_READ_REG(hw, IXGBE_FDIRLEN); 1107 1108 return 0; 1109 } 1110 1111 /** 1112 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers 1113 * @hw: pointer to hardware structure 1114 * @fdirctrl: value to write to flow director control register 1115 **/ 1116 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1117 { 1118 int i; 1119 1120 /* Prime the keys for hashing */ 1121 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); 1122 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); 1123 1124 /* 1125 * Poll init-done after we write the register. Estimated times: 1126 * 10G: PBALLOC = 11b, timing is 60us 1127 * 1G: PBALLOC = 11b, timing is 600us 1128 * 100M: PBALLOC = 11b, timing is 6ms 1129 * 1130 * Multiple these timings by 4 if under full Rx load 1131 * 1132 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1133 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1134 * this might not finish in our poll time, but we can live with that 1135 * for now. 1136 */ 1137 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1138 IXGBE_WRITE_FLUSH(hw); 1139 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1140 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1141 IXGBE_FDIRCTRL_INIT_DONE) 1142 break; 1143 usleep_range(1000, 2000); 1144 } 1145 1146 if (i >= IXGBE_FDIR_INIT_DONE_POLL) 1147 hw_dbg(hw, "Flow Director poll time exceeded!\n"); 1148 } 1149 1150 /** 1151 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters 1152 * @hw: pointer to hardware structure 1153 * @fdirctrl: value to write to flow director control register, initially 1154 * contains just the value of the Rx packet buffer allocation 1155 **/ 1156 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1157 { 1158 /* 1159 * Continue setup of fdirctrl register bits: 1160 * Move the flexible bytes to use the ethertype - shift 6 words 1161 * Set the maximum length per hash bucket to 0xA filters 1162 * Send interrupt when 64 filters are left 1163 */ 1164 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1165 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1166 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1167 1168 /* write hashes and fdirctrl register, poll for completion */ 1169 ixgbe_fdir_enable_82599(hw, fdirctrl); 1170 1171 return 0; 1172 } 1173 1174 /** 1175 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters 1176 * @hw: pointer to hardware structure 1177 * @fdirctrl: value to write to flow director control register, initially 1178 * contains just the value of the Rx packet buffer allocation 1179 **/ 1180 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1181 { 1182 /* 1183 * Continue setup of fdirctrl register bits: 1184 * Turn perfect match filtering on 1185 * Report hash in RSS field of Rx wb descriptor 1186 * Initialize the drop queue 1187 * Move the flexible bytes to use the ethertype - shift 6 words 1188 * Set the maximum length per hash bucket to 0xA filters 1189 * Send interrupt when 64 (0x4 * 16) filters are left 1190 */ 1191 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH | 1192 IXGBE_FDIRCTRL_REPORT_STATUS | 1193 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) | 1194 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1195 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1196 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1197 1198 /* write hashes and fdirctrl register, poll for completion */ 1199 ixgbe_fdir_enable_82599(hw, fdirctrl); 1200 1201 return 0; 1202 } 1203 1204 /* 1205 * These defines allow us to quickly generate all of the necessary instructions 1206 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION 1207 * for values 0 through 15 1208 */ 1209 #define IXGBE_ATR_COMMON_HASH_KEY \ 1210 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY) 1211 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \ 1212 do { \ 1213 u32 n = (_n); \ 1214 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \ 1215 common_hash ^= lo_hash_dword >> n; \ 1216 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1217 bucket_hash ^= lo_hash_dword >> n; \ 1218 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \ 1219 sig_hash ^= lo_hash_dword << (16 - n); \ 1220 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \ 1221 common_hash ^= hi_hash_dword >> n; \ 1222 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1223 bucket_hash ^= hi_hash_dword >> n; \ 1224 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \ 1225 sig_hash ^= hi_hash_dword << (16 - n); \ 1226 } while (0); 1227 1228 /** 1229 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash 1230 * @stream: input bitstream to compute the hash on 1231 * 1232 * This function is almost identical to the function above but contains 1233 * several optomizations such as unwinding all of the loops, letting the 1234 * compiler work out all of the conditional ifs since the keys are static 1235 * defines, and computing two keys at once since the hashed dword stream 1236 * will be the same for both keys. 1237 **/ 1238 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, 1239 union ixgbe_atr_hash_dword common) 1240 { 1241 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1242 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0; 1243 1244 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1245 flow_vm_vlan = ntohl(input.dword); 1246 1247 /* generate common hash dword */ 1248 hi_hash_dword = ntohl(common.dword); 1249 1250 /* low dword is word swapped version of common */ 1251 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1252 1253 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1254 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1255 1256 /* Process bits 0 and 16 */ 1257 IXGBE_COMPUTE_SIG_HASH_ITERATION(0); 1258 1259 /* 1260 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1261 * delay this because bit 0 of the stream should not be processed 1262 * so we do not add the vlan until after bit 0 was processed 1263 */ 1264 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1265 1266 /* Process remaining 30 bit of the key */ 1267 IXGBE_COMPUTE_SIG_HASH_ITERATION(1); 1268 IXGBE_COMPUTE_SIG_HASH_ITERATION(2); 1269 IXGBE_COMPUTE_SIG_HASH_ITERATION(3); 1270 IXGBE_COMPUTE_SIG_HASH_ITERATION(4); 1271 IXGBE_COMPUTE_SIG_HASH_ITERATION(5); 1272 IXGBE_COMPUTE_SIG_HASH_ITERATION(6); 1273 IXGBE_COMPUTE_SIG_HASH_ITERATION(7); 1274 IXGBE_COMPUTE_SIG_HASH_ITERATION(8); 1275 IXGBE_COMPUTE_SIG_HASH_ITERATION(9); 1276 IXGBE_COMPUTE_SIG_HASH_ITERATION(10); 1277 IXGBE_COMPUTE_SIG_HASH_ITERATION(11); 1278 IXGBE_COMPUTE_SIG_HASH_ITERATION(12); 1279 IXGBE_COMPUTE_SIG_HASH_ITERATION(13); 1280 IXGBE_COMPUTE_SIG_HASH_ITERATION(14); 1281 IXGBE_COMPUTE_SIG_HASH_ITERATION(15); 1282 1283 /* combine common_hash result with signature and bucket hashes */ 1284 bucket_hash ^= common_hash; 1285 bucket_hash &= IXGBE_ATR_HASH_MASK; 1286 1287 sig_hash ^= common_hash << 16; 1288 sig_hash &= IXGBE_ATR_HASH_MASK << 16; 1289 1290 /* return completed signature hash */ 1291 return sig_hash ^ bucket_hash; 1292 } 1293 1294 /** 1295 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter 1296 * @hw: pointer to hardware structure 1297 * @input: unique input dword 1298 * @common: compressed common input dword 1299 * @queue: queue index to direct traffic to 1300 **/ 1301 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 1302 union ixgbe_atr_hash_dword input, 1303 union ixgbe_atr_hash_dword common, 1304 u8 queue) 1305 { 1306 u64 fdirhashcmd; 1307 u32 fdircmd; 1308 1309 /* 1310 * Get the flow_type in order to program FDIRCMD properly 1311 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 1312 */ 1313 switch (input.formatted.flow_type) { 1314 case IXGBE_ATR_FLOW_TYPE_TCPV4: 1315 case IXGBE_ATR_FLOW_TYPE_UDPV4: 1316 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 1317 case IXGBE_ATR_FLOW_TYPE_TCPV6: 1318 case IXGBE_ATR_FLOW_TYPE_UDPV6: 1319 case IXGBE_ATR_FLOW_TYPE_SCTPV6: 1320 break; 1321 default: 1322 hw_dbg(hw, " Error on flow type input\n"); 1323 return IXGBE_ERR_CONFIG; 1324 } 1325 1326 /* configure FDIRCMD register */ 1327 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1328 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1329 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1330 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1331 1332 /* 1333 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits 1334 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. 1335 */ 1336 fdirhashcmd = (u64)fdircmd << 32; 1337 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common); 1338 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); 1339 1340 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); 1341 1342 return 0; 1343 } 1344 1345 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \ 1346 do { \ 1347 u32 n = (_n); \ 1348 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1349 bucket_hash ^= lo_hash_dword >> n; \ 1350 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1351 bucket_hash ^= hi_hash_dword >> n; \ 1352 } while (0); 1353 1354 /** 1355 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash 1356 * @atr_input: input bitstream to compute the hash on 1357 * @input_mask: mask for the input bitstream 1358 * 1359 * This function serves two main purposes. First it applys the input_mask 1360 * to the atr_input resulting in a cleaned up atr_input data stream. 1361 * Secondly it computes the hash and stores it in the bkt_hash field at 1362 * the end of the input byte stream. This way it will be available for 1363 * future use without needing to recompute the hash. 1364 **/ 1365 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 1366 union ixgbe_atr_input *input_mask) 1367 { 1368 1369 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1370 u32 bucket_hash = 0; 1371 1372 /* Apply masks to input data */ 1373 input->dword_stream[0] &= input_mask->dword_stream[0]; 1374 input->dword_stream[1] &= input_mask->dword_stream[1]; 1375 input->dword_stream[2] &= input_mask->dword_stream[2]; 1376 input->dword_stream[3] &= input_mask->dword_stream[3]; 1377 input->dword_stream[4] &= input_mask->dword_stream[4]; 1378 input->dword_stream[5] &= input_mask->dword_stream[5]; 1379 input->dword_stream[6] &= input_mask->dword_stream[6]; 1380 input->dword_stream[7] &= input_mask->dword_stream[7]; 1381 input->dword_stream[8] &= input_mask->dword_stream[8]; 1382 input->dword_stream[9] &= input_mask->dword_stream[9]; 1383 input->dword_stream[10] &= input_mask->dword_stream[10]; 1384 1385 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1386 flow_vm_vlan = ntohl(input->dword_stream[0]); 1387 1388 /* generate common hash dword */ 1389 hi_hash_dword = ntohl(input->dword_stream[1] ^ 1390 input->dword_stream[2] ^ 1391 input->dword_stream[3] ^ 1392 input->dword_stream[4] ^ 1393 input->dword_stream[5] ^ 1394 input->dword_stream[6] ^ 1395 input->dword_stream[7] ^ 1396 input->dword_stream[8] ^ 1397 input->dword_stream[9] ^ 1398 input->dword_stream[10]); 1399 1400 /* low dword is word swapped version of common */ 1401 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1402 1403 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1404 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1405 1406 /* Process bits 0 and 16 */ 1407 IXGBE_COMPUTE_BKT_HASH_ITERATION(0); 1408 1409 /* 1410 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1411 * delay this because bit 0 of the stream should not be processed 1412 * so we do not add the vlan until after bit 0 was processed 1413 */ 1414 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1415 1416 /* Process remaining 30 bit of the key */ 1417 IXGBE_COMPUTE_BKT_HASH_ITERATION(1); 1418 IXGBE_COMPUTE_BKT_HASH_ITERATION(2); 1419 IXGBE_COMPUTE_BKT_HASH_ITERATION(3); 1420 IXGBE_COMPUTE_BKT_HASH_ITERATION(4); 1421 IXGBE_COMPUTE_BKT_HASH_ITERATION(5); 1422 IXGBE_COMPUTE_BKT_HASH_ITERATION(6); 1423 IXGBE_COMPUTE_BKT_HASH_ITERATION(7); 1424 IXGBE_COMPUTE_BKT_HASH_ITERATION(8); 1425 IXGBE_COMPUTE_BKT_HASH_ITERATION(9); 1426 IXGBE_COMPUTE_BKT_HASH_ITERATION(10); 1427 IXGBE_COMPUTE_BKT_HASH_ITERATION(11); 1428 IXGBE_COMPUTE_BKT_HASH_ITERATION(12); 1429 IXGBE_COMPUTE_BKT_HASH_ITERATION(13); 1430 IXGBE_COMPUTE_BKT_HASH_ITERATION(14); 1431 IXGBE_COMPUTE_BKT_HASH_ITERATION(15); 1432 1433 /* 1434 * Limit hash to 13 bits since max bucket count is 8K. 1435 * Store result at the end of the input stream. 1436 */ 1437 input->formatted.bkt_hash = bucket_hash & 0x1FFF; 1438 } 1439 1440 /** 1441 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks 1442 * @input_mask: mask to be bit swapped 1443 * 1444 * The source and destination port masks for flow director are bit swapped 1445 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to 1446 * generate a correctly swapped value we need to bit swap the mask and that 1447 * is what is accomplished by this function. 1448 **/ 1449 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask) 1450 { 1451 u32 mask = ntohs(input_mask->formatted.dst_port); 1452 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT; 1453 mask |= ntohs(input_mask->formatted.src_port); 1454 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); 1455 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); 1456 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); 1457 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); 1458 } 1459 1460 /* 1461 * These two macros are meant to address the fact that we have registers 1462 * that are either all or in part big-endian. As a result on big-endian 1463 * systems we will end up byte swapping the value to little-endian before 1464 * it is byte swapped again and written to the hardware in the original 1465 * big-endian format. 1466 */ 1467 #define IXGBE_STORE_AS_BE32(_value) \ 1468 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \ 1469 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24)) 1470 1471 #define IXGBE_WRITE_REG_BE32(a, reg, value) \ 1472 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value))) 1473 1474 #define IXGBE_STORE_AS_BE16(_value) \ 1475 ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8)) 1476 1477 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 1478 union ixgbe_atr_input *input_mask) 1479 { 1480 /* mask IPv6 since it is currently not supported */ 1481 u32 fdirm = IXGBE_FDIRM_DIPv6; 1482 u32 fdirtcpm; 1483 1484 /* 1485 * Program the relevant mask registers. If src/dst_port or src/dst_addr 1486 * are zero, then assume a full mask for that field. Also assume that 1487 * a VLAN of 0 is unspecified, so mask that out as well. L4type 1488 * cannot be masked out in this implementation. 1489 * 1490 * This also assumes IPv4 only. IPv6 masking isn't supported at this 1491 * point in time. 1492 */ 1493 1494 /* verify bucket hash is cleared on hash generation */ 1495 if (input_mask->formatted.bkt_hash) 1496 hw_dbg(hw, " bucket hash should always be 0 in mask\n"); 1497 1498 /* Program FDIRM and verify partial masks */ 1499 switch (input_mask->formatted.vm_pool & 0x7F) { 1500 case 0x0: 1501 fdirm |= IXGBE_FDIRM_POOL; 1502 case 0x7F: 1503 break; 1504 default: 1505 hw_dbg(hw, " Error on vm pool mask\n"); 1506 return IXGBE_ERR_CONFIG; 1507 } 1508 1509 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) { 1510 case 0x0: 1511 fdirm |= IXGBE_FDIRM_L4P; 1512 if (input_mask->formatted.dst_port || 1513 input_mask->formatted.src_port) { 1514 hw_dbg(hw, " Error on src/dst port mask\n"); 1515 return IXGBE_ERR_CONFIG; 1516 } 1517 case IXGBE_ATR_L4TYPE_MASK: 1518 break; 1519 default: 1520 hw_dbg(hw, " Error on flow type mask\n"); 1521 return IXGBE_ERR_CONFIG; 1522 } 1523 1524 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) { 1525 case 0x0000: 1526 /* mask VLAN ID, fall through to mask VLAN priority */ 1527 fdirm |= IXGBE_FDIRM_VLANID; 1528 case 0x0FFF: 1529 /* mask VLAN priority */ 1530 fdirm |= IXGBE_FDIRM_VLANP; 1531 break; 1532 case 0xE000: 1533 /* mask VLAN ID only, fall through */ 1534 fdirm |= IXGBE_FDIRM_VLANID; 1535 case 0xEFFF: 1536 /* no VLAN fields masked */ 1537 break; 1538 default: 1539 hw_dbg(hw, " Error on VLAN mask\n"); 1540 return IXGBE_ERR_CONFIG; 1541 } 1542 1543 switch (input_mask->formatted.flex_bytes & 0xFFFF) { 1544 case 0x0000: 1545 /* Mask Flex Bytes, fall through */ 1546 fdirm |= IXGBE_FDIRM_FLEX; 1547 case 0xFFFF: 1548 break; 1549 default: 1550 hw_dbg(hw, " Error on flexible byte mask\n"); 1551 return IXGBE_ERR_CONFIG; 1552 } 1553 1554 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ 1555 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); 1556 1557 /* store the TCP/UDP port masks, bit reversed from port layout */ 1558 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask); 1559 1560 /* write both the same so that UDP and TCP use the same mask */ 1561 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); 1562 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); 1563 1564 /* store source and destination IP masks (big-enian) */ 1565 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 1566 ~input_mask->formatted.src_ip[0]); 1567 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 1568 ~input_mask->formatted.dst_ip[0]); 1569 1570 return 0; 1571 } 1572 1573 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 1574 union ixgbe_atr_input *input, 1575 u16 soft_id, u8 queue) 1576 { 1577 u32 fdirport, fdirvlan, fdirhash, fdircmd; 1578 1579 /* currently IPv6 is not supported, must be programmed with 0 */ 1580 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), 1581 input->formatted.src_ip[0]); 1582 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), 1583 input->formatted.src_ip[1]); 1584 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), 1585 input->formatted.src_ip[2]); 1586 1587 /* record the source address (big-endian) */ 1588 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]); 1589 1590 /* record the first 32 bits of the destination address (big-endian) */ 1591 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]); 1592 1593 /* record source and destination port (little-endian)*/ 1594 fdirport = ntohs(input->formatted.dst_port); 1595 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT; 1596 fdirport |= ntohs(input->formatted.src_port); 1597 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); 1598 1599 /* record vlan (little-endian) and flex_bytes(big-endian) */ 1600 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes); 1601 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; 1602 fdirvlan |= ntohs(input->formatted.vlan_id); 1603 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); 1604 1605 /* configure FDIRHASH register */ 1606 fdirhash = input->formatted.bkt_hash; 1607 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1608 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1609 1610 /* 1611 * flush all previous writes to make certain registers are 1612 * programmed prior to issuing the command 1613 */ 1614 IXGBE_WRITE_FLUSH(hw); 1615 1616 /* configure FDIRCMD register */ 1617 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1618 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1619 if (queue == IXGBE_FDIR_DROP_QUEUE) 1620 fdircmd |= IXGBE_FDIRCMD_DROP; 1621 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1622 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1623 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT; 1624 1625 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); 1626 1627 return 0; 1628 } 1629 1630 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 1631 union ixgbe_atr_input *input, 1632 u16 soft_id) 1633 { 1634 u32 fdirhash; 1635 u32 fdircmd = 0; 1636 u32 retry_count; 1637 s32 err = 0; 1638 1639 /* configure FDIRHASH register */ 1640 fdirhash = input->formatted.bkt_hash; 1641 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1642 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1643 1644 /* flush hash to HW */ 1645 IXGBE_WRITE_FLUSH(hw); 1646 1647 /* Query if filter is present */ 1648 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT); 1649 1650 for (retry_count = 10; retry_count; retry_count--) { 1651 /* allow 10us for query to process */ 1652 udelay(10); 1653 /* verify query completed successfully */ 1654 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD); 1655 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK)) 1656 break; 1657 } 1658 1659 if (!retry_count) 1660 err = IXGBE_ERR_FDIR_REINIT_FAILED; 1661 1662 /* if filter exists in hardware then remove it */ 1663 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) { 1664 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1665 IXGBE_WRITE_FLUSH(hw); 1666 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1667 IXGBE_FDIRCMD_CMD_REMOVE_FLOW); 1668 } 1669 1670 return err; 1671 } 1672 1673 /** 1674 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 1675 * @hw: pointer to hardware structure 1676 * @reg: analog register to read 1677 * @val: read value 1678 * 1679 * Performs read operation to Omer analog register specified. 1680 **/ 1681 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) 1682 { 1683 u32 core_ctl; 1684 1685 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | 1686 (reg << 8)); 1687 IXGBE_WRITE_FLUSH(hw); 1688 udelay(10); 1689 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); 1690 *val = (u8)core_ctl; 1691 1692 return 0; 1693 } 1694 1695 /** 1696 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register 1697 * @hw: pointer to hardware structure 1698 * @reg: atlas register to write 1699 * @val: value to write 1700 * 1701 * Performs write operation to Omer analog register specified. 1702 **/ 1703 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) 1704 { 1705 u32 core_ctl; 1706 1707 core_ctl = (reg << 8) | val; 1708 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); 1709 IXGBE_WRITE_FLUSH(hw); 1710 udelay(10); 1711 1712 return 0; 1713 } 1714 1715 /** 1716 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx 1717 * @hw: pointer to hardware structure 1718 * 1719 * Starts the hardware using the generic start_hw function 1720 * and the generation start_hw function. 1721 * Then performs revision-specific operations, if any. 1722 **/ 1723 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) 1724 { 1725 s32 ret_val = 0; 1726 1727 ret_val = ixgbe_start_hw_generic(hw); 1728 if (ret_val != 0) 1729 goto out; 1730 1731 ret_val = ixgbe_start_hw_gen2(hw); 1732 if (ret_val != 0) 1733 goto out; 1734 1735 /* We need to run link autotry after the driver loads */ 1736 hw->mac.autotry_restart = true; 1737 hw->mac.rx_pb_size = IXGBE_82599_RX_PB_SIZE; 1738 1739 if (ret_val == 0) 1740 ret_val = ixgbe_verify_fw_version_82599(hw); 1741 out: 1742 return ret_val; 1743 } 1744 1745 /** 1746 * ixgbe_identify_phy_82599 - Get physical layer module 1747 * @hw: pointer to hardware structure 1748 * 1749 * Determines the physical layer module found on the current adapter. 1750 * If PHY already detected, maintains current PHY type in hw struct, 1751 * otherwise executes the PHY detection routine. 1752 **/ 1753 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 1754 { 1755 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1756 1757 /* Detect PHY if not unknown - returns success if already detected. */ 1758 status = ixgbe_identify_phy_generic(hw); 1759 if (status != 0) { 1760 /* 82599 10GBASE-T requires an external PHY */ 1761 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) 1762 goto out; 1763 else 1764 status = ixgbe_identify_sfp_module_generic(hw); 1765 } 1766 1767 /* Set PHY type none if no PHY detected */ 1768 if (hw->phy.type == ixgbe_phy_unknown) { 1769 hw->phy.type = ixgbe_phy_none; 1770 status = 0; 1771 } 1772 1773 /* Return error if SFP module has been detected but is not supported */ 1774 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 1775 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1776 1777 out: 1778 return status; 1779 } 1780 1781 /** 1782 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type 1783 * @hw: pointer to hardware structure 1784 * 1785 * Determines physical layer capabilities of the current configuration. 1786 **/ 1787 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) 1788 { 1789 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1790 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1791 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1792 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 1793 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 1794 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1795 u16 ext_ability = 0; 1796 u8 comp_codes_10g = 0; 1797 u8 comp_codes_1g = 0; 1798 1799 hw->phy.ops.identify(hw); 1800 1801 switch (hw->phy.type) { 1802 case ixgbe_phy_tn: 1803 case ixgbe_phy_cu_unknown: 1804 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD, 1805 &ext_ability); 1806 if (ext_ability & MDIO_PMA_EXTABLE_10GBT) 1807 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1808 if (ext_ability & MDIO_PMA_EXTABLE_1000BT) 1809 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1810 if (ext_ability & MDIO_PMA_EXTABLE_100BTX) 1811 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1812 goto out; 1813 default: 1814 break; 1815 } 1816 1817 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1818 case IXGBE_AUTOC_LMS_1G_AN: 1819 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 1820 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { 1821 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | 1822 IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1823 goto out; 1824 } else 1825 /* SFI mode so read SFP module */ 1826 goto sfp_check; 1827 break; 1828 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 1829 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) 1830 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1831 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) 1832 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1833 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) 1834 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; 1835 goto out; 1836 break; 1837 case IXGBE_AUTOC_LMS_10G_SERIAL: 1838 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { 1839 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; 1840 goto out; 1841 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) 1842 goto sfp_check; 1843 break; 1844 case IXGBE_AUTOC_LMS_KX4_KX_KR: 1845 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 1846 if (autoc & IXGBE_AUTOC_KX_SUPP) 1847 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1848 if (autoc & IXGBE_AUTOC_KX4_SUPP) 1849 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1850 if (autoc & IXGBE_AUTOC_KR_SUPP) 1851 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; 1852 goto out; 1853 break; 1854 default: 1855 goto out; 1856 break; 1857 } 1858 1859 sfp_check: 1860 /* SFP check must be done last since DA modules are sometimes used to 1861 * test KR mode - we need to id KR mode correctly before SFP module. 1862 * Call identify_sfp because the pluggable module may have changed */ 1863 hw->phy.ops.identify_sfp(hw); 1864 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1865 goto out; 1866 1867 switch (hw->phy.type) { 1868 case ixgbe_phy_sfp_passive_tyco: 1869 case ixgbe_phy_sfp_passive_unknown: 1870 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1871 break; 1872 case ixgbe_phy_sfp_ftl_active: 1873 case ixgbe_phy_sfp_active_unknown: 1874 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1875 break; 1876 case ixgbe_phy_sfp_avago: 1877 case ixgbe_phy_sfp_ftl: 1878 case ixgbe_phy_sfp_intel: 1879 case ixgbe_phy_sfp_unknown: 1880 hw->phy.ops.read_i2c_eeprom(hw, 1881 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1882 hw->phy.ops.read_i2c_eeprom(hw, 1883 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1884 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1885 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1886 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1887 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1888 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1889 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1890 break; 1891 default: 1892 break; 1893 } 1894 1895 out: 1896 return physical_layer; 1897 } 1898 1899 /** 1900 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 1901 * @hw: pointer to hardware structure 1902 * @regval: register value to write to RXCTRL 1903 * 1904 * Enables the Rx DMA unit for 82599 1905 **/ 1906 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) 1907 { 1908 #define IXGBE_MAX_SECRX_POLL 30 1909 int i; 1910 int secrxreg; 1911 1912 /* 1913 * Workaround for 82599 silicon errata when enabling the Rx datapath. 1914 * If traffic is incoming before we enable the Rx unit, it could hang 1915 * the Rx DMA unit. Therefore, make sure the security engine is 1916 * completely disabled prior to enabling the Rx unit. 1917 */ 1918 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 1919 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 1920 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 1921 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 1922 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 1923 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 1924 break; 1925 else 1926 /* Use interrupt-safe sleep just in case */ 1927 udelay(10); 1928 } 1929 1930 /* For informational purposes only */ 1931 if (i >= IXGBE_MAX_SECRX_POLL) 1932 hw_dbg(hw, "Rx unit being enabled before security " 1933 "path fully disabled. Continuing with init.\n"); 1934 1935 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 1936 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 1937 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 1938 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 1939 IXGBE_WRITE_FLUSH(hw); 1940 1941 return 0; 1942 } 1943 1944 /** 1945 * ixgbe_verify_fw_version_82599 - verify fw version for 82599 1946 * @hw: pointer to hardware structure 1947 * 1948 * Verifies that installed the firmware version is 0.6 or higher 1949 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. 1950 * 1951 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or 1952 * if the FW version is not supported. 1953 **/ 1954 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 1955 { 1956 s32 status = IXGBE_ERR_EEPROM_VERSION; 1957 u16 fw_offset, fw_ptp_cfg_offset; 1958 u16 fw_version = 0; 1959 1960 /* firmware check is only necessary for SFI devices */ 1961 if (hw->phy.media_type != ixgbe_media_type_fiber) { 1962 status = 0; 1963 goto fw_version_out; 1964 } 1965 1966 /* get the offset to the Firmware Module block */ 1967 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 1968 1969 if ((fw_offset == 0) || (fw_offset == 0xFFFF)) 1970 goto fw_version_out; 1971 1972 /* get the offset to the Pass Through Patch Configuration block */ 1973 hw->eeprom.ops.read(hw, (fw_offset + 1974 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), 1975 &fw_ptp_cfg_offset); 1976 1977 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) 1978 goto fw_version_out; 1979 1980 /* get the firmware version */ 1981 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + 1982 IXGBE_FW_PATCH_VERSION_4), 1983 &fw_version); 1984 1985 if (fw_version > 0x5) 1986 status = 0; 1987 1988 fw_version_out: 1989 return status; 1990 } 1991 1992 /** 1993 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state. 1994 * @hw: pointer to hardware structure 1995 * 1996 * Returns true if the LESM FW module is present and enabled. Otherwise 1997 * returns false. Smart Speed must be disabled if LESM FW module is enabled. 1998 **/ 1999 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) 2000 { 2001 bool lesm_enabled = false; 2002 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state; 2003 s32 status; 2004 2005 /* get the offset to the Firmware Module block */ 2006 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 2007 2008 if ((status != 0) || 2009 (fw_offset == 0) || (fw_offset == 0xFFFF)) 2010 goto out; 2011 2012 /* get the offset to the LESM Parameters block */ 2013 status = hw->eeprom.ops.read(hw, (fw_offset + 2014 IXGBE_FW_LESM_PARAMETERS_PTR), 2015 &fw_lesm_param_offset); 2016 2017 if ((status != 0) || 2018 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF)) 2019 goto out; 2020 2021 /* get the lesm state word */ 2022 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + 2023 IXGBE_FW_LESM_STATE_1), 2024 &fw_lesm_state); 2025 2026 if ((status == 0) && 2027 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) 2028 lesm_enabled = true; 2029 2030 out: 2031 return lesm_enabled; 2032 } 2033 2034 /** 2035 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using 2036 * fastest available method 2037 * 2038 * @hw: pointer to hardware structure 2039 * @offset: offset of word in EEPROM to read 2040 * @words: number of words 2041 * @data: word(s) read from the EEPROM 2042 * 2043 * Retrieves 16 bit word(s) read from EEPROM 2044 **/ 2045 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, 2046 u16 words, u16 *data) 2047 { 2048 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2049 s32 ret_val = IXGBE_ERR_CONFIG; 2050 2051 /* 2052 * If EEPROM is detected and can be addressed using 14 bits, 2053 * use EERD otherwise use bit bang 2054 */ 2055 if ((eeprom->type == ixgbe_eeprom_spi) && 2056 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR)) 2057 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words, 2058 data); 2059 else 2060 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset, 2061 words, 2062 data); 2063 2064 return ret_val; 2065 } 2066 2067 /** 2068 * ixgbe_read_eeprom_82599 - Read EEPROM word using 2069 * fastest available method 2070 * 2071 * @hw: pointer to hardware structure 2072 * @offset: offset of word in the EEPROM to read 2073 * @data: word read from the EEPROM 2074 * 2075 * Reads a 16 bit word from the EEPROM 2076 **/ 2077 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 2078 u16 offset, u16 *data) 2079 { 2080 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2081 s32 ret_val = IXGBE_ERR_CONFIG; 2082 2083 /* 2084 * If EEPROM is detected and can be addressed using 14 bits, 2085 * use EERD otherwise use bit bang 2086 */ 2087 if ((eeprom->type == ixgbe_eeprom_spi) && 2088 (offset <= IXGBE_EERD_MAX_ADDR)) 2089 ret_val = ixgbe_read_eerd_generic(hw, offset, data); 2090 else 2091 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data); 2092 2093 return ret_val; 2094 } 2095 2096 static struct ixgbe_mac_operations mac_ops_82599 = { 2097 .init_hw = &ixgbe_init_hw_generic, 2098 .reset_hw = &ixgbe_reset_hw_82599, 2099 .start_hw = &ixgbe_start_hw_82599, 2100 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, 2101 .get_media_type = &ixgbe_get_media_type_82599, 2102 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599, 2103 .enable_rx_dma = &ixgbe_enable_rx_dma_82599, 2104 .get_mac_addr = &ixgbe_get_mac_addr_generic, 2105 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 2106 .get_device_caps = &ixgbe_get_device_caps_generic, 2107 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 2108 .stop_adapter = &ixgbe_stop_adapter_generic, 2109 .get_bus_info = &ixgbe_get_bus_info_generic, 2110 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, 2111 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599, 2112 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599, 2113 .setup_link = &ixgbe_setup_mac_link_82599, 2114 .set_rxpba = &ixgbe_set_rxpba_generic, 2115 .check_link = &ixgbe_check_mac_link_generic, 2116 .get_link_capabilities = &ixgbe_get_link_capabilities_82599, 2117 .led_on = &ixgbe_led_on_generic, 2118 .led_off = &ixgbe_led_off_generic, 2119 .blink_led_start = &ixgbe_blink_led_start_generic, 2120 .blink_led_stop = &ixgbe_blink_led_stop_generic, 2121 .set_rar = &ixgbe_set_rar_generic, 2122 .clear_rar = &ixgbe_clear_rar_generic, 2123 .set_vmdq = &ixgbe_set_vmdq_generic, 2124 .clear_vmdq = &ixgbe_clear_vmdq_generic, 2125 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 2126 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 2127 .enable_mc = &ixgbe_enable_mc_generic, 2128 .disable_mc = &ixgbe_disable_mc_generic, 2129 .clear_vfta = &ixgbe_clear_vfta_generic, 2130 .set_vfta = &ixgbe_set_vfta_generic, 2131 .fc_enable = &ixgbe_fc_enable_generic, 2132 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic, 2133 .init_uta_tables = &ixgbe_init_uta_tables_generic, 2134 .setup_sfp = &ixgbe_setup_sfp_modules_82599, 2135 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, 2136 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, 2137 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync, 2138 .release_swfw_sync = &ixgbe_release_swfw_sync, 2139 2140 }; 2141 2142 static struct ixgbe_eeprom_operations eeprom_ops_82599 = { 2143 .init_params = &ixgbe_init_eeprom_params_generic, 2144 .read = &ixgbe_read_eeprom_82599, 2145 .read_buffer = &ixgbe_read_eeprom_buffer_82599, 2146 .write = &ixgbe_write_eeprom_generic, 2147 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic, 2148 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic, 2149 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, 2150 .update_checksum = &ixgbe_update_eeprom_checksum_generic, 2151 }; 2152 2153 static struct ixgbe_phy_operations phy_ops_82599 = { 2154 .identify = &ixgbe_identify_phy_82599, 2155 .identify_sfp = &ixgbe_identify_sfp_module_generic, 2156 .init = &ixgbe_init_phy_ops_82599, 2157 .reset = &ixgbe_reset_phy_generic, 2158 .read_reg = &ixgbe_read_phy_reg_generic, 2159 .write_reg = &ixgbe_write_phy_reg_generic, 2160 .setup_link = &ixgbe_setup_phy_link_generic, 2161 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, 2162 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, 2163 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, 2164 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, 2165 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, 2166 .check_overtemp = &ixgbe_tn_check_overtemp, 2167 }; 2168 2169 struct ixgbe_info ixgbe_82599_info = { 2170 .mac = ixgbe_mac_82599EB, 2171 .get_invariants = &ixgbe_get_invariants_82599, 2172 .mac_ops = &mac_ops_82599, 2173 .eeprom_ops = &eeprom_ops_82599, 2174 .phy_ops = &phy_ops_82599, 2175 .mbx_ops = &mbx_ops_generic, 2176 }; 2177