1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2015 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/pci.h> 30 #include <linux/delay.h> 31 #include <linux/sched.h> 32 33 #include "ixgbe.h" 34 #include "ixgbe_phy.h" 35 #include "ixgbe_mbx.h" 36 37 #define IXGBE_82599_MAX_TX_QUEUES 128 38 #define IXGBE_82599_MAX_RX_QUEUES 128 39 #define IXGBE_82599_RAR_ENTRIES 128 40 #define IXGBE_82599_MC_TBL_SIZE 128 41 #define IXGBE_82599_VFT_TBL_SIZE 128 42 #define IXGBE_82599_RX_PB_SIZE 512 43 44 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 45 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 46 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 47 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 48 ixgbe_link_speed speed, 49 bool autoneg_wait_to_complete); 50 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 51 ixgbe_link_speed speed, 52 bool autoneg_wait_to_complete); 53 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw); 54 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 55 bool autoneg_wait_to_complete); 56 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 57 ixgbe_link_speed speed, 58 bool autoneg_wait_to_complete); 59 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 60 ixgbe_link_speed speed, 61 bool autoneg_wait_to_complete); 62 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 63 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 64 u8 dev_addr, u8 *data); 65 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 66 u8 dev_addr, u8 data); 67 static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw); 68 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw); 69 70 bool ixgbe_mng_enabled(struct ixgbe_hw *hw) 71 { 72 u32 fwsm, manc, factps; 73 74 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 75 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) 76 return false; 77 78 manc = IXGBE_READ_REG(hw, IXGBE_MANC); 79 if (!(manc & IXGBE_MANC_RCV_TCO_EN)) 80 return false; 81 82 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); 83 if (factps & IXGBE_FACTPS_MNGCG) 84 return false; 85 86 return true; 87 } 88 89 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 90 { 91 struct ixgbe_mac_info *mac = &hw->mac; 92 93 /* enable the laser control functions for SFP+ fiber 94 * and MNG not enabled 95 */ 96 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && 97 !ixgbe_mng_enabled(hw)) { 98 mac->ops.disable_tx_laser = 99 &ixgbe_disable_tx_laser_multispeed_fiber; 100 mac->ops.enable_tx_laser = 101 &ixgbe_enable_tx_laser_multispeed_fiber; 102 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; 103 } else { 104 mac->ops.disable_tx_laser = NULL; 105 mac->ops.enable_tx_laser = NULL; 106 mac->ops.flap_tx_laser = NULL; 107 } 108 109 if (hw->phy.multispeed_fiber) { 110 /* Set up dual speed SFP+ support */ 111 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; 112 } else { 113 if ((mac->ops.get_media_type(hw) == 114 ixgbe_media_type_backplane) && 115 (hw->phy.smart_speed == ixgbe_smart_speed_auto || 116 hw->phy.smart_speed == ixgbe_smart_speed_on) && 117 !ixgbe_verify_lesm_fw_enabled_82599(hw)) 118 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; 119 else 120 mac->ops.setup_link = &ixgbe_setup_mac_link_82599; 121 } 122 } 123 124 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 125 { 126 s32 ret_val; 127 u16 list_offset, data_offset, data_value; 128 129 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 130 ixgbe_init_mac_link_ops_82599(hw); 131 132 hw->phy.ops.reset = NULL; 133 134 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 135 &data_offset); 136 if (ret_val) 137 return ret_val; 138 139 /* PHY config will finish before releasing the semaphore */ 140 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 141 IXGBE_GSSR_MAC_CSR_SM); 142 if (ret_val) 143 return IXGBE_ERR_SWFW_SYNC; 144 145 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 146 goto setup_sfp_err; 147 while (data_value != 0xffff) { 148 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); 149 IXGBE_WRITE_FLUSH(hw); 150 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 151 goto setup_sfp_err; 152 } 153 154 /* Release the semaphore */ 155 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 156 /* 157 * Delay obtaining semaphore again to allow FW access, 158 * semaphore_delay is in ms usleep_range needs us. 159 */ 160 usleep_range(hw->eeprom.semaphore_delay * 1000, 161 hw->eeprom.semaphore_delay * 2000); 162 163 /* Restart DSP and set SFI mode */ 164 ret_val = hw->mac.ops.prot_autoc_write(hw, 165 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL, 166 false); 167 168 if (ret_val) { 169 hw_dbg(hw, " sfp module setup not complete\n"); 170 return IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 171 } 172 } 173 174 return 0; 175 176 setup_sfp_err: 177 /* Release the semaphore */ 178 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 179 /* Delay obtaining semaphore again to allow FW access, 180 * semaphore_delay is in ms usleep_range needs us. 181 */ 182 usleep_range(hw->eeprom.semaphore_delay * 1000, 183 hw->eeprom.semaphore_delay * 2000); 184 hw_err(hw, "eeprom read at offset %d failed\n", data_offset); 185 return IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 186 } 187 188 /** 189 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read 190 * @hw: pointer to hardware structure 191 * @locked: Return the if we locked for this read. 192 * @reg_val: Value we read from AUTOC 193 * 194 * For this part (82599) we need to wrap read-modify-writes with a possible 195 * FW/SW lock. It is assumed this lock will be freed with the next 196 * prot_autoc_write_82599(). Note, that locked can only be true in cases 197 * where this function doesn't return an error. 198 **/ 199 static s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, 200 u32 *reg_val) 201 { 202 s32 ret_val; 203 204 *locked = false; 205 /* If LESM is on then we need to hold the SW/FW semaphore. */ 206 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 207 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 208 IXGBE_GSSR_MAC_CSR_SM); 209 if (ret_val) 210 return IXGBE_ERR_SWFW_SYNC; 211 212 *locked = true; 213 } 214 215 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 216 return 0; 217 } 218 219 /** 220 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write 221 * @hw: pointer to hardware structure 222 * @reg_val: value to write to AUTOC 223 * @locked: bool to indicate whether the SW/FW lock was already taken by 224 * previous proc_autoc_read_82599. 225 * 226 * This part (82599) may need to hold a the SW/FW lock around all writes to 227 * AUTOC. Likewise after a write we need to do a pipeline reset. 228 **/ 229 static s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked) 230 { 231 s32 ret_val = 0; 232 233 /* Blocked by MNG FW so bail */ 234 if (ixgbe_check_reset_blocked(hw)) 235 goto out; 236 237 /* We only need to get the lock if: 238 * - We didn't do it already (in the read part of a read-modify-write) 239 * - LESM is enabled. 240 */ 241 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) { 242 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 243 IXGBE_GSSR_MAC_CSR_SM); 244 if (ret_val) 245 return IXGBE_ERR_SWFW_SYNC; 246 247 locked = true; 248 } 249 250 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 251 ret_val = ixgbe_reset_pipeline_82599(hw); 252 253 out: 254 /* Free the SW/FW semaphore as we either grabbed it here or 255 * already had it when this function was called. 256 */ 257 if (locked) 258 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 259 260 return ret_val; 261 } 262 263 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw) 264 { 265 struct ixgbe_mac_info *mac = &hw->mac; 266 267 ixgbe_init_mac_link_ops_82599(hw); 268 269 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; 270 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; 271 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; 272 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE; 273 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; 274 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; 275 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 276 277 return 0; 278 } 279 280 /** 281 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init 282 * @hw: pointer to hardware structure 283 * 284 * Initialize any function pointers that were not able to be 285 * set during get_invariants because the PHY/SFP type was 286 * not known. Perform the SFP init if necessary. 287 * 288 **/ 289 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 290 { 291 struct ixgbe_mac_info *mac = &hw->mac; 292 struct ixgbe_phy_info *phy = &hw->phy; 293 s32 ret_val; 294 u32 esdp; 295 296 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) { 297 /* Store flag indicating I2C bus access control unit. */ 298 hw->phy.qsfp_shared_i2c_bus = true; 299 300 /* Initialize access to QSFP+ I2C bus */ 301 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 302 esdp |= IXGBE_ESDP_SDP0_DIR; 303 esdp &= ~IXGBE_ESDP_SDP1_DIR; 304 esdp &= ~IXGBE_ESDP_SDP0; 305 esdp &= ~IXGBE_ESDP_SDP0_NATIVE; 306 esdp &= ~IXGBE_ESDP_SDP1_NATIVE; 307 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 308 IXGBE_WRITE_FLUSH(hw); 309 310 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_82599; 311 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_82599; 312 } 313 314 /* Identify the PHY or SFP module */ 315 ret_val = phy->ops.identify(hw); 316 317 /* Setup function pointers based on detected SFP module and speeds */ 318 ixgbe_init_mac_link_ops_82599(hw); 319 320 /* If copper media, overwrite with copper function pointers */ 321 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 322 mac->ops.setup_link = &ixgbe_setup_copper_link_82599; 323 mac->ops.get_link_capabilities = 324 &ixgbe_get_copper_link_capabilities_generic; 325 } 326 327 /* Set necessary function pointers based on phy type */ 328 switch (hw->phy.type) { 329 case ixgbe_phy_tn: 330 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 331 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; 332 phy->ops.get_firmware_version = 333 &ixgbe_get_phy_firmware_version_tnx; 334 break; 335 default: 336 break; 337 } 338 339 return ret_val; 340 } 341 342 /** 343 * ixgbe_get_link_capabilities_82599 - Determines link capabilities 344 * @hw: pointer to hardware structure 345 * @speed: pointer to link speed 346 * @autoneg: true when autoneg or autotry is enabled 347 * 348 * Determines the link capabilities by reading the AUTOC register. 349 **/ 350 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 351 ixgbe_link_speed *speed, 352 bool *autoneg) 353 { 354 u32 autoc = 0; 355 356 /* Determine 1G link capabilities off of SFP+ type */ 357 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 358 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 359 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 360 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 361 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 362 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 363 *speed = IXGBE_LINK_SPEED_1GB_FULL; 364 *autoneg = true; 365 return 0; 366 } 367 368 /* 369 * Determine link capabilities based on the stored value of AUTOC, 370 * which represents EEPROM defaults. If AUTOC value has not been 371 * stored, use the current register value. 372 */ 373 if (hw->mac.orig_link_settings_stored) 374 autoc = hw->mac.orig_autoc; 375 else 376 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 377 378 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 379 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 380 *speed = IXGBE_LINK_SPEED_1GB_FULL; 381 *autoneg = false; 382 break; 383 384 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 385 *speed = IXGBE_LINK_SPEED_10GB_FULL; 386 *autoneg = false; 387 break; 388 389 case IXGBE_AUTOC_LMS_1G_AN: 390 *speed = IXGBE_LINK_SPEED_1GB_FULL; 391 *autoneg = true; 392 break; 393 394 case IXGBE_AUTOC_LMS_10G_SERIAL: 395 *speed = IXGBE_LINK_SPEED_10GB_FULL; 396 *autoneg = false; 397 break; 398 399 case IXGBE_AUTOC_LMS_KX4_KX_KR: 400 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 401 *speed = IXGBE_LINK_SPEED_UNKNOWN; 402 if (autoc & IXGBE_AUTOC_KR_SUPP) 403 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 404 if (autoc & IXGBE_AUTOC_KX4_SUPP) 405 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 406 if (autoc & IXGBE_AUTOC_KX_SUPP) 407 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 408 *autoneg = true; 409 break; 410 411 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: 412 *speed = IXGBE_LINK_SPEED_100_FULL; 413 if (autoc & IXGBE_AUTOC_KR_SUPP) 414 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 415 if (autoc & IXGBE_AUTOC_KX4_SUPP) 416 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 417 if (autoc & IXGBE_AUTOC_KX_SUPP) 418 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 419 *autoneg = true; 420 break; 421 422 case IXGBE_AUTOC_LMS_SGMII_1G_100M: 423 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; 424 *autoneg = false; 425 break; 426 427 default: 428 return IXGBE_ERR_LINK_SETUP; 429 } 430 431 if (hw->phy.multispeed_fiber) { 432 *speed |= IXGBE_LINK_SPEED_10GB_FULL | 433 IXGBE_LINK_SPEED_1GB_FULL; 434 435 /* QSFP must not enable auto-negotiation */ 436 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp) 437 *autoneg = false; 438 else 439 *autoneg = true; 440 } 441 442 return 0; 443 } 444 445 /** 446 * ixgbe_get_media_type_82599 - Get media type 447 * @hw: pointer to hardware structure 448 * 449 * Returns the media type (fiber, copper, backplane) 450 **/ 451 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 452 { 453 /* Detect if there is a copper PHY attached. */ 454 switch (hw->phy.type) { 455 case ixgbe_phy_cu_unknown: 456 case ixgbe_phy_tn: 457 return ixgbe_media_type_copper; 458 459 default: 460 break; 461 } 462 463 switch (hw->device_id) { 464 case IXGBE_DEV_ID_82599_KX4: 465 case IXGBE_DEV_ID_82599_KX4_MEZZ: 466 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 467 case IXGBE_DEV_ID_82599_KR: 468 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 469 case IXGBE_DEV_ID_82599_XAUI_LOM: 470 /* Default device ID is mezzanine card KX/KX4 */ 471 return ixgbe_media_type_backplane; 472 473 case IXGBE_DEV_ID_82599_SFP: 474 case IXGBE_DEV_ID_82599_SFP_FCOE: 475 case IXGBE_DEV_ID_82599_SFP_EM: 476 case IXGBE_DEV_ID_82599_SFP_SF2: 477 case IXGBE_DEV_ID_82599_SFP_SF_QP: 478 case IXGBE_DEV_ID_82599EN_SFP: 479 return ixgbe_media_type_fiber; 480 481 case IXGBE_DEV_ID_82599_CX4: 482 return ixgbe_media_type_cx4; 483 484 case IXGBE_DEV_ID_82599_T3_LOM: 485 return ixgbe_media_type_copper; 486 487 case IXGBE_DEV_ID_82599_LS: 488 return ixgbe_media_type_fiber_lco; 489 490 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 491 return ixgbe_media_type_fiber_qsfp; 492 493 default: 494 return ixgbe_media_type_unknown; 495 } 496 } 497 498 /** 499 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3 500 * @hw: pointer to hardware structure 501 * 502 * Disables link, should be called during D3 power down sequence. 503 * 504 **/ 505 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw) 506 { 507 u32 autoc2_reg; 508 u16 ee_ctrl_2 = 0; 509 510 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2); 511 512 if (!ixgbe_mng_present(hw) && !hw->wol_enabled && 513 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) { 514 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 515 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK; 516 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 517 } 518 } 519 520 /** 521 * ixgbe_start_mac_link_82599 - Setup MAC link settings 522 * @hw: pointer to hardware structure 523 * @autoneg_wait_to_complete: true when waiting for completion is needed 524 * 525 * Configures link settings based on values in the ixgbe_hw struct. 526 * Restarts the link. Performs autonegotiation if needed. 527 **/ 528 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 529 bool autoneg_wait_to_complete) 530 { 531 u32 autoc_reg; 532 u32 links_reg; 533 u32 i; 534 s32 status = 0; 535 bool got_lock = false; 536 537 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 538 status = hw->mac.ops.acquire_swfw_sync(hw, 539 IXGBE_GSSR_MAC_CSR_SM); 540 if (status) 541 return status; 542 543 got_lock = true; 544 } 545 546 /* Restart link */ 547 ixgbe_reset_pipeline_82599(hw); 548 549 if (got_lock) 550 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 551 552 /* Only poll for autoneg to complete if specified to do so */ 553 if (autoneg_wait_to_complete) { 554 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 555 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 556 IXGBE_AUTOC_LMS_KX4_KX_KR || 557 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 558 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 559 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 560 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 561 links_reg = 0; /* Just in case Autoneg time = 0 */ 562 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 563 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 564 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 565 break; 566 msleep(100); 567 } 568 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 569 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 570 hw_dbg(hw, "Autoneg did not complete.\n"); 571 } 572 } 573 } 574 575 /* Add delay to filter out noises during initial link setup */ 576 msleep(50); 577 578 return status; 579 } 580 581 /** 582 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser 583 * @hw: pointer to hardware structure 584 * 585 * The base drivers may require better control over SFP+ module 586 * PHY states. This includes selectively shutting down the Tx 587 * laser on the PHY, effectively halting physical link. 588 **/ 589 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 590 { 591 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 592 593 /* Blocked by MNG FW so bail */ 594 if (ixgbe_check_reset_blocked(hw)) 595 return; 596 597 /* Disable tx laser; allow 100us to go dark per spec */ 598 esdp_reg |= IXGBE_ESDP_SDP3; 599 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 600 IXGBE_WRITE_FLUSH(hw); 601 udelay(100); 602 } 603 604 /** 605 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser 606 * @hw: pointer to hardware structure 607 * 608 * The base drivers may require better control over SFP+ module 609 * PHY states. This includes selectively turning on the Tx 610 * laser on the PHY, effectively starting physical link. 611 **/ 612 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 613 { 614 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 615 616 /* Enable tx laser; allow 100ms to light up */ 617 esdp_reg &= ~IXGBE_ESDP_SDP3; 618 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 619 IXGBE_WRITE_FLUSH(hw); 620 msleep(100); 621 } 622 623 /** 624 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser 625 * @hw: pointer to hardware structure 626 * 627 * When the driver changes the link speeds that it can support, 628 * it sets autotry_restart to true to indicate that we need to 629 * initiate a new autotry session with the link partner. To do 630 * so, we set the speed then disable and re-enable the tx laser, to 631 * alert the link partner that it also needs to restart autotry on its 632 * end. This is consistent with true clause 37 autoneg, which also 633 * involves a loss of signal. 634 **/ 635 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 636 { 637 /* Blocked by MNG FW so bail */ 638 if (ixgbe_check_reset_blocked(hw)) 639 return; 640 641 if (hw->mac.autotry_restart) { 642 ixgbe_disable_tx_laser_multispeed_fiber(hw); 643 ixgbe_enable_tx_laser_multispeed_fiber(hw); 644 hw->mac.autotry_restart = false; 645 } 646 } 647 648 /** 649 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 650 * @hw: pointer to hardware structure 651 * @speed: new link speed 652 * @autoneg_wait_to_complete: true when waiting for completion is needed 653 * 654 * Set the link speed in the AUTOC register and restarts link. 655 **/ 656 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 657 ixgbe_link_speed speed, 658 bool autoneg_wait_to_complete) 659 { 660 s32 status = 0; 661 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 662 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 663 u32 speedcnt = 0; 664 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 665 u32 i = 0; 666 bool link_up = false; 667 bool autoneg = false; 668 669 /* Mask off requested but non-supported speeds */ 670 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, 671 &autoneg); 672 if (status != 0) 673 return status; 674 675 speed &= link_speed; 676 677 /* 678 * Try each speed one by one, highest priority first. We do this in 679 * software because 10gb fiber doesn't support speed autonegotiation. 680 */ 681 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 682 speedcnt++; 683 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 684 685 /* If we already have link at this speed, just jump out */ 686 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 687 false); 688 if (status != 0) 689 return status; 690 691 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up) 692 goto out; 693 694 /* Set the module link speed */ 695 switch (hw->phy.media_type) { 696 case ixgbe_media_type_fiber: 697 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); 698 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 699 IXGBE_WRITE_FLUSH(hw); 700 break; 701 case ixgbe_media_type_fiber_qsfp: 702 /* QSFP module automatically detects MAC link speed */ 703 break; 704 default: 705 hw_dbg(hw, "Unexpected media type.\n"); 706 break; 707 } 708 709 /* Allow module to change analog characteristics (1G->10G) */ 710 msleep(40); 711 712 status = ixgbe_setup_mac_link_82599(hw, 713 IXGBE_LINK_SPEED_10GB_FULL, 714 autoneg_wait_to_complete); 715 if (status != 0) 716 return status; 717 718 /* Flap the tx laser if it has not already been done */ 719 if (hw->mac.ops.flap_tx_laser) 720 hw->mac.ops.flap_tx_laser(hw); 721 722 /* 723 * Wait for the controller to acquire link. Per IEEE 802.3ap, 724 * Section 73.10.2, we may have to wait up to 500ms if KR is 725 * attempted. 82599 uses the same timing for 10g SFI. 726 */ 727 for (i = 0; i < 5; i++) { 728 /* Wait for the link partner to also set speed */ 729 msleep(100); 730 731 /* If we have link, just jump out */ 732 status = hw->mac.ops.check_link(hw, &link_speed, 733 &link_up, false); 734 if (status != 0) 735 return status; 736 737 if (link_up) 738 goto out; 739 } 740 } 741 742 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 743 speedcnt++; 744 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 745 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 746 747 /* If we already have link at this speed, just jump out */ 748 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 749 false); 750 if (status != 0) 751 return status; 752 753 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up) 754 goto out; 755 756 /* Set the module link speed */ 757 switch (hw->phy.media_type) { 758 case ixgbe_media_type_fiber: 759 esdp_reg &= ~IXGBE_ESDP_SDP5; 760 esdp_reg |= IXGBE_ESDP_SDP5_DIR; 761 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 762 IXGBE_WRITE_FLUSH(hw); 763 break; 764 case ixgbe_media_type_fiber_qsfp: 765 /* QSFP module automatically detects MAC link speed */ 766 break; 767 default: 768 hw_dbg(hw, "Unexpected media type.\n"); 769 break; 770 } 771 772 /* Allow module to change analog characteristics (10G->1G) */ 773 msleep(40); 774 775 status = ixgbe_setup_mac_link_82599(hw, 776 IXGBE_LINK_SPEED_1GB_FULL, 777 autoneg_wait_to_complete); 778 if (status != 0) 779 return status; 780 781 /* Flap the tx laser if it has not already been done */ 782 if (hw->mac.ops.flap_tx_laser) 783 hw->mac.ops.flap_tx_laser(hw); 784 785 /* Wait for the link partner to also set speed */ 786 msleep(100); 787 788 /* If we have link, just jump out */ 789 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 790 false); 791 if (status != 0) 792 return status; 793 794 if (link_up) 795 goto out; 796 } 797 798 /* 799 * We didn't get link. Configure back to the highest speed we tried, 800 * (if there was more than one). We call ourselves back with just the 801 * single highest speed that the user requested. 802 */ 803 if (speedcnt > 1) 804 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 805 highest_link_speed, 806 autoneg_wait_to_complete); 807 808 out: 809 /* Set autoneg_advertised value based on input link speed */ 810 hw->phy.autoneg_advertised = 0; 811 812 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 813 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 814 815 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 816 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 817 818 return status; 819 } 820 821 /** 822 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed 823 * @hw: pointer to hardware structure 824 * @speed: new link speed 825 * @autoneg_wait_to_complete: true when waiting for completion is needed 826 * 827 * Implements the Intel SmartSpeed algorithm. 828 **/ 829 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 830 ixgbe_link_speed speed, 831 bool autoneg_wait_to_complete) 832 { 833 s32 status = 0; 834 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 835 s32 i, j; 836 bool link_up = false; 837 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 838 839 /* Set autoneg_advertised value based on input link speed */ 840 hw->phy.autoneg_advertised = 0; 841 842 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 843 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 844 845 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 846 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 847 848 if (speed & IXGBE_LINK_SPEED_100_FULL) 849 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 850 851 /* 852 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the 853 * autoneg advertisement if link is unable to be established at the 854 * highest negotiated rate. This can sometimes happen due to integrity 855 * issues with the physical media connection. 856 */ 857 858 /* First, try to get link with full advertisement */ 859 hw->phy.smart_speed_active = false; 860 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { 861 status = ixgbe_setup_mac_link_82599(hw, speed, 862 autoneg_wait_to_complete); 863 if (status != 0) 864 goto out; 865 866 /* 867 * Wait for the controller to acquire link. Per IEEE 802.3ap, 868 * Section 73.10.2, we may have to wait up to 500ms if KR is 869 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per 870 * Table 9 in the AN MAS. 871 */ 872 for (i = 0; i < 5; i++) { 873 mdelay(100); 874 875 /* If we have link, just jump out */ 876 status = hw->mac.ops.check_link(hw, &link_speed, 877 &link_up, false); 878 if (status != 0) 879 goto out; 880 881 if (link_up) 882 goto out; 883 } 884 } 885 886 /* 887 * We didn't get link. If we advertised KR plus one of KX4/KX 888 * (or BX4/BX), then disable KR and try again. 889 */ 890 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || 891 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) 892 goto out; 893 894 /* Turn SmartSpeed on to disable KR support */ 895 hw->phy.smart_speed_active = true; 896 status = ixgbe_setup_mac_link_82599(hw, speed, 897 autoneg_wait_to_complete); 898 if (status != 0) 899 goto out; 900 901 /* 902 * Wait for the controller to acquire link. 600ms will allow for 903 * the AN link_fail_inhibit_timer as well for multiple cycles of 904 * parallel detect, both 10g and 1g. This allows for the maximum 905 * connect attempts as defined in the AN MAS table 73-7. 906 */ 907 for (i = 0; i < 6; i++) { 908 mdelay(100); 909 910 /* If we have link, just jump out */ 911 status = hw->mac.ops.check_link(hw, &link_speed, 912 &link_up, false); 913 if (status != 0) 914 goto out; 915 916 if (link_up) 917 goto out; 918 } 919 920 /* We didn't get link. Turn SmartSpeed back off. */ 921 hw->phy.smart_speed_active = false; 922 status = ixgbe_setup_mac_link_82599(hw, speed, 923 autoneg_wait_to_complete); 924 925 out: 926 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) 927 hw_dbg(hw, "Smartspeed has downgraded the link speed from the maximum advertised\n"); 928 return status; 929 } 930 931 /** 932 * ixgbe_setup_mac_link_82599 - Set MAC link speed 933 * @hw: pointer to hardware structure 934 * @speed: new link speed 935 * @autoneg_wait_to_complete: true when waiting for completion is needed 936 * 937 * Set the link speed in the AUTOC register and restarts link. 938 **/ 939 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 940 ixgbe_link_speed speed, 941 bool autoneg_wait_to_complete) 942 { 943 bool autoneg = false; 944 s32 status; 945 u32 pma_pmd_1g, link_mode, links_reg, i; 946 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 947 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 948 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 949 950 /* holds the value of AUTOC register at this current point in time */ 951 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 952 /* holds the cached value of AUTOC register */ 953 u32 orig_autoc = 0; 954 /* temporary variable used for comparison purposes */ 955 u32 autoc = current_autoc; 956 957 /* Check to see if speed passed in is supported. */ 958 status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities, 959 &autoneg); 960 if (status) 961 return status; 962 963 speed &= link_capabilities; 964 965 if (speed == IXGBE_LINK_SPEED_UNKNOWN) 966 return IXGBE_ERR_LINK_SETUP; 967 968 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ 969 if (hw->mac.orig_link_settings_stored) 970 orig_autoc = hw->mac.orig_autoc; 971 else 972 orig_autoc = autoc; 973 974 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 975 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 976 977 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 978 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 979 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 980 /* Set KX4/KX/KR support according to speed requested */ 981 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); 982 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 983 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) 984 autoc |= IXGBE_AUTOC_KX4_SUPP; 985 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && 986 (hw->phy.smart_speed_active == false)) 987 autoc |= IXGBE_AUTOC_KR_SUPP; 988 } 989 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 990 autoc |= IXGBE_AUTOC_KX_SUPP; 991 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && 992 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || 993 link_mode == IXGBE_AUTOC_LMS_1G_AN)) { 994 /* Switch from 1G SFI to 10G SFI if requested */ 995 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 996 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { 997 autoc &= ~IXGBE_AUTOC_LMS_MASK; 998 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; 999 } 1000 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && 1001 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { 1002 /* Switch from 10G SFI to 1G SFI if requested */ 1003 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 1004 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { 1005 autoc &= ~IXGBE_AUTOC_LMS_MASK; 1006 if (autoneg) 1007 autoc |= IXGBE_AUTOC_LMS_1G_AN; 1008 else 1009 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 1010 } 1011 } 1012 1013 if (autoc != current_autoc) { 1014 /* Restart link */ 1015 status = hw->mac.ops.prot_autoc_write(hw, autoc, false); 1016 if (status) 1017 return status; 1018 1019 /* Only poll for autoneg to complete if specified to do so */ 1020 if (autoneg_wait_to_complete) { 1021 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 1022 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 1023 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 1024 links_reg = 0; /*Just in case Autoneg time=0*/ 1025 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 1026 links_reg = 1027 IXGBE_READ_REG(hw, IXGBE_LINKS); 1028 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 1029 break; 1030 msleep(100); 1031 } 1032 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 1033 status = 1034 IXGBE_ERR_AUTONEG_NOT_COMPLETE; 1035 hw_dbg(hw, "Autoneg did not complete.\n"); 1036 } 1037 } 1038 } 1039 1040 /* Add delay to filter out noises during initial link setup */ 1041 msleep(50); 1042 } 1043 1044 return status; 1045 } 1046 1047 /** 1048 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field 1049 * @hw: pointer to hardware structure 1050 * @speed: new link speed 1051 * @autoneg_wait_to_complete: true if waiting is needed to complete 1052 * 1053 * Restarts link on PHY and MAC based on settings passed in. 1054 **/ 1055 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 1056 ixgbe_link_speed speed, 1057 bool autoneg_wait_to_complete) 1058 { 1059 s32 status; 1060 1061 /* Setup the PHY according to input speed */ 1062 status = hw->phy.ops.setup_link_speed(hw, speed, 1063 autoneg_wait_to_complete); 1064 /* Set up MAC */ 1065 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); 1066 1067 return status; 1068 } 1069 1070 /** 1071 * ixgbe_reset_hw_82599 - Perform hardware reset 1072 * @hw: pointer to hardware structure 1073 * 1074 * Resets the hardware by resetting the transmit and receive units, masks 1075 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 1076 * reset. 1077 **/ 1078 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 1079 { 1080 ixgbe_link_speed link_speed; 1081 s32 status; 1082 u32 ctrl, i, autoc, autoc2; 1083 u32 curr_lms; 1084 bool link_up = false; 1085 1086 /* Call adapter stop to disable tx/rx and clear interrupts */ 1087 status = hw->mac.ops.stop_adapter(hw); 1088 if (status) 1089 return status; 1090 1091 /* flush pending Tx transactions */ 1092 ixgbe_clear_tx_pending(hw); 1093 1094 /* PHY ops must be identified and initialized prior to reset */ 1095 1096 /* Identify PHY and related function pointers */ 1097 status = hw->phy.ops.init(hw); 1098 1099 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1100 return status; 1101 1102 /* Setup SFP module if there is one present. */ 1103 if (hw->phy.sfp_setup_needed) { 1104 status = hw->mac.ops.setup_sfp(hw); 1105 hw->phy.sfp_setup_needed = false; 1106 } 1107 1108 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1109 return status; 1110 1111 /* Reset PHY */ 1112 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) 1113 hw->phy.ops.reset(hw); 1114 1115 /* remember AUTOC from before we reset */ 1116 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK; 1117 1118 mac_reset_top: 1119 /* 1120 * Issue global reset to the MAC. Needs to be SW reset if link is up. 1121 * If link reset is used when link is up, it might reset the PHY when 1122 * mng is using it. If link is down or the flag to force full link 1123 * reset is set, then perform link reset. 1124 */ 1125 ctrl = IXGBE_CTRL_LNK_RST; 1126 if (!hw->force_full_reset) { 1127 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 1128 if (link_up) 1129 ctrl = IXGBE_CTRL_RST; 1130 } 1131 1132 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 1133 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 1134 IXGBE_WRITE_FLUSH(hw); 1135 1136 /* Poll for reset bit to self-clear indicating reset is complete */ 1137 for (i = 0; i < 10; i++) { 1138 udelay(1); 1139 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1140 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 1141 break; 1142 } 1143 1144 if (ctrl & IXGBE_CTRL_RST_MASK) { 1145 status = IXGBE_ERR_RESET_FAILED; 1146 hw_dbg(hw, "Reset polling failed to complete.\n"); 1147 } 1148 1149 msleep(50); 1150 1151 /* 1152 * Double resets are required for recovery from certain error 1153 * conditions. Between resets, it is necessary to stall to allow time 1154 * for any pending HW events to complete. 1155 */ 1156 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1157 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1158 goto mac_reset_top; 1159 } 1160 1161 /* 1162 * Store the original AUTOC/AUTOC2 values if they have not been 1163 * stored off yet. Otherwise restore the stored original 1164 * values since the reset operation sets back to defaults. 1165 */ 1166 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1167 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1168 1169 /* Enable link if disabled in NVM */ 1170 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 1171 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 1172 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1173 IXGBE_WRITE_FLUSH(hw); 1174 } 1175 1176 if (hw->mac.orig_link_settings_stored == false) { 1177 hw->mac.orig_autoc = autoc; 1178 hw->mac.orig_autoc2 = autoc2; 1179 hw->mac.orig_link_settings_stored = true; 1180 } else { 1181 1182 /* If MNG FW is running on a multi-speed device that 1183 * doesn't autoneg with out driver support we need to 1184 * leave LMS in the state it was before we MAC reset. 1185 * Likewise if we support WoL we don't want change the 1186 * LMS state either. 1187 */ 1188 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) || 1189 hw->wol_enabled) 1190 hw->mac.orig_autoc = 1191 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) | 1192 curr_lms; 1193 1194 if (autoc != hw->mac.orig_autoc) { 1195 status = hw->mac.ops.prot_autoc_write(hw, 1196 hw->mac.orig_autoc, 1197 false); 1198 if (status) 1199 return status; 1200 } 1201 1202 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != 1203 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { 1204 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; 1205 autoc2 |= (hw->mac.orig_autoc2 & 1206 IXGBE_AUTOC2_UPPER_MASK); 1207 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1208 } 1209 } 1210 1211 /* Store the permanent mac address */ 1212 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1213 1214 /* 1215 * Store MAC address from RAR0, clear receive address registers, and 1216 * clear the multicast table. Also reset num_rar_entries to 128, 1217 * since we modify this value when programming the SAN MAC address. 1218 */ 1219 hw->mac.num_rar_entries = 128; 1220 hw->mac.ops.init_rx_addrs(hw); 1221 1222 /* Store the permanent SAN mac address */ 1223 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 1224 1225 /* Add the SAN MAC address to the RAR only if it's a valid address */ 1226 if (is_valid_ether_addr(hw->mac.san_addr)) { 1227 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, 1228 hw->mac.san_addr, 0, IXGBE_RAH_AV); 1229 1230 /* Save the SAN MAC RAR index */ 1231 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 1232 1233 /* Reserve the last RAR for the SAN MAC address */ 1234 hw->mac.num_rar_entries--; 1235 } 1236 1237 /* Store the alternative WWNN/WWPN prefix */ 1238 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 1239 &hw->mac.wwpn_prefix); 1240 1241 return status; 1242 } 1243 1244 /** 1245 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete 1246 * @hw: pointer to hardware structure 1247 * @fdircmd: current value of FDIRCMD register 1248 */ 1249 static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd) 1250 { 1251 int i; 1252 1253 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { 1254 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD); 1255 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK)) 1256 return 0; 1257 udelay(10); 1258 } 1259 1260 return IXGBE_ERR_FDIR_CMD_INCOMPLETE; 1261 } 1262 1263 /** 1264 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. 1265 * @hw: pointer to hardware structure 1266 **/ 1267 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) 1268 { 1269 int i; 1270 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1271 u32 fdircmd; 1272 s32 err; 1273 1274 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; 1275 1276 /* 1277 * Before starting reinitialization process, 1278 * FDIRCMD.CMD must be zero. 1279 */ 1280 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1281 if (err) { 1282 hw_dbg(hw, "Flow Director previous command did not complete, aborting table re-initialization.\n"); 1283 return err; 1284 } 1285 1286 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); 1287 IXGBE_WRITE_FLUSH(hw); 1288 /* 1289 * 82599 adapters flow director init flow cannot be restarted, 1290 * Workaround 82599 silicon errata by performing the following steps 1291 * before re-writing the FDIRCTRL control register with the same value. 1292 * - write 1 to bit 8 of FDIRCMD register & 1293 * - write 0 to bit 8 of FDIRCMD register 1294 */ 1295 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1296 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1297 IXGBE_FDIRCMD_CLEARHT)); 1298 IXGBE_WRITE_FLUSH(hw); 1299 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1300 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1301 ~IXGBE_FDIRCMD_CLEARHT)); 1302 IXGBE_WRITE_FLUSH(hw); 1303 /* 1304 * Clear FDIR Hash register to clear any leftover hashes 1305 * waiting to be programmed. 1306 */ 1307 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); 1308 IXGBE_WRITE_FLUSH(hw); 1309 1310 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1311 IXGBE_WRITE_FLUSH(hw); 1312 1313 /* Poll init-done after we write FDIRCTRL register */ 1314 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1315 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1316 IXGBE_FDIRCTRL_INIT_DONE) 1317 break; 1318 usleep_range(1000, 2000); 1319 } 1320 if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 1321 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n"); 1322 return IXGBE_ERR_FDIR_REINIT_FAILED; 1323 } 1324 1325 /* Clear FDIR statistics registers (read to clear) */ 1326 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); 1327 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); 1328 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 1329 IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 1330 IXGBE_READ_REG(hw, IXGBE_FDIRLEN); 1331 1332 return 0; 1333 } 1334 1335 /** 1336 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers 1337 * @hw: pointer to hardware structure 1338 * @fdirctrl: value to write to flow director control register 1339 **/ 1340 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1341 { 1342 int i; 1343 1344 /* Prime the keys for hashing */ 1345 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); 1346 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); 1347 1348 /* 1349 * Poll init-done after we write the register. Estimated times: 1350 * 10G: PBALLOC = 11b, timing is 60us 1351 * 1G: PBALLOC = 11b, timing is 600us 1352 * 100M: PBALLOC = 11b, timing is 6ms 1353 * 1354 * Multiple these timings by 4 if under full Rx load 1355 * 1356 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1357 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1358 * this might not finish in our poll time, but we can live with that 1359 * for now. 1360 */ 1361 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1362 IXGBE_WRITE_FLUSH(hw); 1363 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1364 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1365 IXGBE_FDIRCTRL_INIT_DONE) 1366 break; 1367 usleep_range(1000, 2000); 1368 } 1369 1370 if (i >= IXGBE_FDIR_INIT_DONE_POLL) 1371 hw_dbg(hw, "Flow Director poll time exceeded!\n"); 1372 } 1373 1374 /** 1375 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters 1376 * @hw: pointer to hardware structure 1377 * @fdirctrl: value to write to flow director control register, initially 1378 * contains just the value of the Rx packet buffer allocation 1379 **/ 1380 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1381 { 1382 /* 1383 * Continue setup of fdirctrl register bits: 1384 * Move the flexible bytes to use the ethertype - shift 6 words 1385 * Set the maximum length per hash bucket to 0xA filters 1386 * Send interrupt when 64 filters are left 1387 */ 1388 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1389 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1390 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1391 1392 /* write hashes and fdirctrl register, poll for completion */ 1393 ixgbe_fdir_enable_82599(hw, fdirctrl); 1394 1395 return 0; 1396 } 1397 1398 /** 1399 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters 1400 * @hw: pointer to hardware structure 1401 * @fdirctrl: value to write to flow director control register, initially 1402 * contains just the value of the Rx packet buffer allocation 1403 **/ 1404 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1405 { 1406 /* 1407 * Continue setup of fdirctrl register bits: 1408 * Turn perfect match filtering on 1409 * Initialize the drop queue 1410 * Move the flexible bytes to use the ethertype - shift 6 words 1411 * Set the maximum length per hash bucket to 0xA filters 1412 * Send interrupt when 64 (0x4 * 16) filters are left 1413 */ 1414 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH | 1415 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) | 1416 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1417 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1418 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1419 1420 /* write hashes and fdirctrl register, poll for completion */ 1421 ixgbe_fdir_enable_82599(hw, fdirctrl); 1422 1423 return 0; 1424 } 1425 1426 /* 1427 * These defines allow us to quickly generate all of the necessary instructions 1428 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION 1429 * for values 0 through 15 1430 */ 1431 #define IXGBE_ATR_COMMON_HASH_KEY \ 1432 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY) 1433 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \ 1434 do { \ 1435 u32 n = (_n); \ 1436 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \ 1437 common_hash ^= lo_hash_dword >> n; \ 1438 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1439 bucket_hash ^= lo_hash_dword >> n; \ 1440 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \ 1441 sig_hash ^= lo_hash_dword << (16 - n); \ 1442 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \ 1443 common_hash ^= hi_hash_dword >> n; \ 1444 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1445 bucket_hash ^= hi_hash_dword >> n; \ 1446 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \ 1447 sig_hash ^= hi_hash_dword << (16 - n); \ 1448 } while (0) 1449 1450 /** 1451 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash 1452 * @stream: input bitstream to compute the hash on 1453 * 1454 * This function is almost identical to the function above but contains 1455 * several optomizations such as unwinding all of the loops, letting the 1456 * compiler work out all of the conditional ifs since the keys are static 1457 * defines, and computing two keys at once since the hashed dword stream 1458 * will be the same for both keys. 1459 **/ 1460 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, 1461 union ixgbe_atr_hash_dword common) 1462 { 1463 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1464 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0; 1465 1466 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1467 flow_vm_vlan = ntohl(input.dword); 1468 1469 /* generate common hash dword */ 1470 hi_hash_dword = ntohl(common.dword); 1471 1472 /* low dword is word swapped version of common */ 1473 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1474 1475 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1476 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1477 1478 /* Process bits 0 and 16 */ 1479 IXGBE_COMPUTE_SIG_HASH_ITERATION(0); 1480 1481 /* 1482 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1483 * delay this because bit 0 of the stream should not be processed 1484 * so we do not add the vlan until after bit 0 was processed 1485 */ 1486 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1487 1488 /* Process remaining 30 bit of the key */ 1489 IXGBE_COMPUTE_SIG_HASH_ITERATION(1); 1490 IXGBE_COMPUTE_SIG_HASH_ITERATION(2); 1491 IXGBE_COMPUTE_SIG_HASH_ITERATION(3); 1492 IXGBE_COMPUTE_SIG_HASH_ITERATION(4); 1493 IXGBE_COMPUTE_SIG_HASH_ITERATION(5); 1494 IXGBE_COMPUTE_SIG_HASH_ITERATION(6); 1495 IXGBE_COMPUTE_SIG_HASH_ITERATION(7); 1496 IXGBE_COMPUTE_SIG_HASH_ITERATION(8); 1497 IXGBE_COMPUTE_SIG_HASH_ITERATION(9); 1498 IXGBE_COMPUTE_SIG_HASH_ITERATION(10); 1499 IXGBE_COMPUTE_SIG_HASH_ITERATION(11); 1500 IXGBE_COMPUTE_SIG_HASH_ITERATION(12); 1501 IXGBE_COMPUTE_SIG_HASH_ITERATION(13); 1502 IXGBE_COMPUTE_SIG_HASH_ITERATION(14); 1503 IXGBE_COMPUTE_SIG_HASH_ITERATION(15); 1504 1505 /* combine common_hash result with signature and bucket hashes */ 1506 bucket_hash ^= common_hash; 1507 bucket_hash &= IXGBE_ATR_HASH_MASK; 1508 1509 sig_hash ^= common_hash << 16; 1510 sig_hash &= IXGBE_ATR_HASH_MASK << 16; 1511 1512 /* return completed signature hash */ 1513 return sig_hash ^ bucket_hash; 1514 } 1515 1516 /** 1517 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter 1518 * @hw: pointer to hardware structure 1519 * @input: unique input dword 1520 * @common: compressed common input dword 1521 * @queue: queue index to direct traffic to 1522 * 1523 * Note that the tunnel bit in input must not be set when the hardware 1524 * tunneling support does not exist. 1525 **/ 1526 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 1527 union ixgbe_atr_hash_dword input, 1528 union ixgbe_atr_hash_dword common, 1529 u8 queue) 1530 { 1531 u64 fdirhashcmd; 1532 u8 flow_type; 1533 bool tunnel; 1534 u32 fdircmd; 1535 1536 /* 1537 * Get the flow_type in order to program FDIRCMD properly 1538 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 1539 */ 1540 tunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK); 1541 flow_type = input.formatted.flow_type & 1542 (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1); 1543 switch (flow_type) { 1544 case IXGBE_ATR_FLOW_TYPE_TCPV4: 1545 case IXGBE_ATR_FLOW_TYPE_UDPV4: 1546 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 1547 case IXGBE_ATR_FLOW_TYPE_TCPV6: 1548 case IXGBE_ATR_FLOW_TYPE_UDPV6: 1549 case IXGBE_ATR_FLOW_TYPE_SCTPV6: 1550 break; 1551 default: 1552 hw_dbg(hw, " Error on flow type input\n"); 1553 return IXGBE_ERR_CONFIG; 1554 } 1555 1556 /* configure FDIRCMD register */ 1557 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1558 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1559 fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1560 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1561 if (tunnel) 1562 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER; 1563 1564 /* 1565 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits 1566 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. 1567 */ 1568 fdirhashcmd = (u64)fdircmd << 32; 1569 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common); 1570 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); 1571 1572 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); 1573 1574 return 0; 1575 } 1576 1577 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \ 1578 do { \ 1579 u32 n = (_n); \ 1580 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1581 bucket_hash ^= lo_hash_dword >> n; \ 1582 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1583 bucket_hash ^= hi_hash_dword >> n; \ 1584 } while (0) 1585 1586 /** 1587 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash 1588 * @atr_input: input bitstream to compute the hash on 1589 * @input_mask: mask for the input bitstream 1590 * 1591 * This function serves two main purposes. First it applys the input_mask 1592 * to the atr_input resulting in a cleaned up atr_input data stream. 1593 * Secondly it computes the hash and stores it in the bkt_hash field at 1594 * the end of the input byte stream. This way it will be available for 1595 * future use without needing to recompute the hash. 1596 **/ 1597 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 1598 union ixgbe_atr_input *input_mask) 1599 { 1600 1601 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1602 u32 bucket_hash = 0, hi_dword = 0; 1603 int i; 1604 1605 /* Apply masks to input data */ 1606 for (i = 0; i <= 10; i++) 1607 input->dword_stream[i] &= input_mask->dword_stream[i]; 1608 1609 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1610 flow_vm_vlan = ntohl(input->dword_stream[0]); 1611 1612 /* generate common hash dword */ 1613 for (i = 1; i <= 10; i++) 1614 hi_dword ^= input->dword_stream[i]; 1615 hi_hash_dword = ntohl(hi_dword); 1616 1617 /* low dword is word swapped version of common */ 1618 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1619 1620 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1621 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1622 1623 /* Process bits 0 and 16 */ 1624 IXGBE_COMPUTE_BKT_HASH_ITERATION(0); 1625 1626 /* 1627 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1628 * delay this because bit 0 of the stream should not be processed 1629 * so we do not add the vlan until after bit 0 was processed 1630 */ 1631 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1632 1633 /* Process remaining 30 bit of the key */ 1634 for (i = 1; i <= 15; i++) 1635 IXGBE_COMPUTE_BKT_HASH_ITERATION(i); 1636 1637 /* 1638 * Limit hash to 13 bits since max bucket count is 8K. 1639 * Store result at the end of the input stream. 1640 */ 1641 input->formatted.bkt_hash = bucket_hash & 0x1FFF; 1642 } 1643 1644 /** 1645 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks 1646 * @input_mask: mask to be bit swapped 1647 * 1648 * The source and destination port masks for flow director are bit swapped 1649 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to 1650 * generate a correctly swapped value we need to bit swap the mask and that 1651 * is what is accomplished by this function. 1652 **/ 1653 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask) 1654 { 1655 u32 mask = ntohs(input_mask->formatted.dst_port); 1656 1657 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT; 1658 mask |= ntohs(input_mask->formatted.src_port); 1659 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); 1660 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); 1661 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); 1662 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); 1663 } 1664 1665 /* 1666 * These two macros are meant to address the fact that we have registers 1667 * that are either all or in part big-endian. As a result on big-endian 1668 * systems we will end up byte swapping the value to little-endian before 1669 * it is byte swapped again and written to the hardware in the original 1670 * big-endian format. 1671 */ 1672 #define IXGBE_STORE_AS_BE32(_value) \ 1673 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \ 1674 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24)) 1675 1676 #define IXGBE_WRITE_REG_BE32(a, reg, value) \ 1677 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value))) 1678 1679 #define IXGBE_STORE_AS_BE16(_value) \ 1680 ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8)) 1681 1682 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 1683 union ixgbe_atr_input *input_mask) 1684 { 1685 /* mask IPv6 since it is currently not supported */ 1686 u32 fdirm = IXGBE_FDIRM_DIPv6; 1687 u32 fdirtcpm; 1688 1689 /* 1690 * Program the relevant mask registers. If src/dst_port or src/dst_addr 1691 * are zero, then assume a full mask for that field. Also assume that 1692 * a VLAN of 0 is unspecified, so mask that out as well. L4type 1693 * cannot be masked out in this implementation. 1694 * 1695 * This also assumes IPv4 only. IPv6 masking isn't supported at this 1696 * point in time. 1697 */ 1698 1699 /* verify bucket hash is cleared on hash generation */ 1700 if (input_mask->formatted.bkt_hash) 1701 hw_dbg(hw, " bucket hash should always be 0 in mask\n"); 1702 1703 /* Program FDIRM and verify partial masks */ 1704 switch (input_mask->formatted.vm_pool & 0x7F) { 1705 case 0x0: 1706 fdirm |= IXGBE_FDIRM_POOL; 1707 case 0x7F: 1708 break; 1709 default: 1710 hw_dbg(hw, " Error on vm pool mask\n"); 1711 return IXGBE_ERR_CONFIG; 1712 } 1713 1714 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) { 1715 case 0x0: 1716 fdirm |= IXGBE_FDIRM_L4P; 1717 if (input_mask->formatted.dst_port || 1718 input_mask->formatted.src_port) { 1719 hw_dbg(hw, " Error on src/dst port mask\n"); 1720 return IXGBE_ERR_CONFIG; 1721 } 1722 case IXGBE_ATR_L4TYPE_MASK: 1723 break; 1724 default: 1725 hw_dbg(hw, " Error on flow type mask\n"); 1726 return IXGBE_ERR_CONFIG; 1727 } 1728 1729 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) { 1730 case 0x0000: 1731 /* mask VLAN ID, fall through to mask VLAN priority */ 1732 fdirm |= IXGBE_FDIRM_VLANID; 1733 case 0x0FFF: 1734 /* mask VLAN priority */ 1735 fdirm |= IXGBE_FDIRM_VLANP; 1736 break; 1737 case 0xE000: 1738 /* mask VLAN ID only, fall through */ 1739 fdirm |= IXGBE_FDIRM_VLANID; 1740 case 0xEFFF: 1741 /* no VLAN fields masked */ 1742 break; 1743 default: 1744 hw_dbg(hw, " Error on VLAN mask\n"); 1745 return IXGBE_ERR_CONFIG; 1746 } 1747 1748 switch (input_mask->formatted.flex_bytes & 0xFFFF) { 1749 case 0x0000: 1750 /* Mask Flex Bytes, fall through */ 1751 fdirm |= IXGBE_FDIRM_FLEX; 1752 case 0xFFFF: 1753 break; 1754 default: 1755 hw_dbg(hw, " Error on flexible byte mask\n"); 1756 return IXGBE_ERR_CONFIG; 1757 } 1758 1759 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ 1760 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); 1761 1762 /* store the TCP/UDP port masks, bit reversed from port layout */ 1763 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask); 1764 1765 /* write both the same so that UDP and TCP use the same mask */ 1766 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); 1767 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); 1768 1769 /* store source and destination IP masks (big-enian) */ 1770 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 1771 ~input_mask->formatted.src_ip[0]); 1772 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 1773 ~input_mask->formatted.dst_ip[0]); 1774 1775 return 0; 1776 } 1777 1778 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 1779 union ixgbe_atr_input *input, 1780 u16 soft_id, u8 queue) 1781 { 1782 u32 fdirport, fdirvlan, fdirhash, fdircmd; 1783 s32 err; 1784 1785 /* currently IPv6 is not supported, must be programmed with 0 */ 1786 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), 1787 input->formatted.src_ip[0]); 1788 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), 1789 input->formatted.src_ip[1]); 1790 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), 1791 input->formatted.src_ip[2]); 1792 1793 /* record the source address (big-endian) */ 1794 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]); 1795 1796 /* record the first 32 bits of the destination address (big-endian) */ 1797 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]); 1798 1799 /* record source and destination port (little-endian)*/ 1800 fdirport = ntohs(input->formatted.dst_port); 1801 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT; 1802 fdirport |= ntohs(input->formatted.src_port); 1803 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); 1804 1805 /* record vlan (little-endian) and flex_bytes(big-endian) */ 1806 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes); 1807 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; 1808 fdirvlan |= ntohs(input->formatted.vlan_id); 1809 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); 1810 1811 /* configure FDIRHASH register */ 1812 fdirhash = input->formatted.bkt_hash; 1813 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1814 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1815 1816 /* 1817 * flush all previous writes to make certain registers are 1818 * programmed prior to issuing the command 1819 */ 1820 IXGBE_WRITE_FLUSH(hw); 1821 1822 /* configure FDIRCMD register */ 1823 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1824 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1825 if (queue == IXGBE_FDIR_DROP_QUEUE) 1826 fdircmd |= IXGBE_FDIRCMD_DROP; 1827 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1828 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1829 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT; 1830 1831 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); 1832 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1833 if (err) { 1834 hw_dbg(hw, "Flow Director command did not complete!\n"); 1835 return err; 1836 } 1837 1838 return 0; 1839 } 1840 1841 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 1842 union ixgbe_atr_input *input, 1843 u16 soft_id) 1844 { 1845 u32 fdirhash; 1846 u32 fdircmd; 1847 s32 err; 1848 1849 /* configure FDIRHASH register */ 1850 fdirhash = input->formatted.bkt_hash; 1851 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1852 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1853 1854 /* flush hash to HW */ 1855 IXGBE_WRITE_FLUSH(hw); 1856 1857 /* Query if filter is present */ 1858 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT); 1859 1860 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1861 if (err) { 1862 hw_dbg(hw, "Flow Director command did not complete!\n"); 1863 return err; 1864 } 1865 1866 /* if filter exists in hardware then remove it */ 1867 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) { 1868 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1869 IXGBE_WRITE_FLUSH(hw); 1870 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1871 IXGBE_FDIRCMD_CMD_REMOVE_FLOW); 1872 } 1873 1874 return 0; 1875 } 1876 1877 /** 1878 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 1879 * @hw: pointer to hardware structure 1880 * @reg: analog register to read 1881 * @val: read value 1882 * 1883 * Performs read operation to Omer analog register specified. 1884 **/ 1885 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) 1886 { 1887 u32 core_ctl; 1888 1889 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | 1890 (reg << 8)); 1891 IXGBE_WRITE_FLUSH(hw); 1892 udelay(10); 1893 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); 1894 *val = (u8)core_ctl; 1895 1896 return 0; 1897 } 1898 1899 /** 1900 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register 1901 * @hw: pointer to hardware structure 1902 * @reg: atlas register to write 1903 * @val: value to write 1904 * 1905 * Performs write operation to Omer analog register specified. 1906 **/ 1907 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) 1908 { 1909 u32 core_ctl; 1910 1911 core_ctl = (reg << 8) | val; 1912 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); 1913 IXGBE_WRITE_FLUSH(hw); 1914 udelay(10); 1915 1916 return 0; 1917 } 1918 1919 /** 1920 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx 1921 * @hw: pointer to hardware structure 1922 * 1923 * Starts the hardware using the generic start_hw function 1924 * and the generation start_hw function. 1925 * Then performs revision-specific operations, if any. 1926 **/ 1927 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) 1928 { 1929 s32 ret_val = 0; 1930 1931 ret_val = ixgbe_start_hw_generic(hw); 1932 if (ret_val) 1933 return ret_val; 1934 1935 ret_val = ixgbe_start_hw_gen2(hw); 1936 if (ret_val) 1937 return ret_val; 1938 1939 /* We need to run link autotry after the driver loads */ 1940 hw->mac.autotry_restart = true; 1941 1942 if (ret_val) 1943 return ret_val; 1944 1945 return ixgbe_verify_fw_version_82599(hw); 1946 } 1947 1948 /** 1949 * ixgbe_identify_phy_82599 - Get physical layer module 1950 * @hw: pointer to hardware structure 1951 * 1952 * Determines the physical layer module found on the current adapter. 1953 * If PHY already detected, maintains current PHY type in hw struct, 1954 * otherwise executes the PHY detection routine. 1955 **/ 1956 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 1957 { 1958 s32 status; 1959 1960 /* Detect PHY if not unknown - returns success if already detected. */ 1961 status = ixgbe_identify_phy_generic(hw); 1962 if (status) { 1963 /* 82599 10GBASE-T requires an external PHY */ 1964 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) 1965 return status; 1966 status = ixgbe_identify_module_generic(hw); 1967 } 1968 1969 /* Set PHY type none if no PHY detected */ 1970 if (hw->phy.type == ixgbe_phy_unknown) { 1971 hw->phy.type = ixgbe_phy_none; 1972 status = 0; 1973 } 1974 1975 /* Return error if SFP module has been detected but is not supported */ 1976 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 1977 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1978 1979 return status; 1980 } 1981 1982 /** 1983 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 1984 * @hw: pointer to hardware structure 1985 * @regval: register value to write to RXCTRL 1986 * 1987 * Enables the Rx DMA unit for 82599 1988 **/ 1989 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) 1990 { 1991 /* 1992 * Workaround for 82599 silicon errata when enabling the Rx datapath. 1993 * If traffic is incoming before we enable the Rx unit, it could hang 1994 * the Rx DMA unit. Therefore, make sure the security engine is 1995 * completely disabled prior to enabling the Rx unit. 1996 */ 1997 hw->mac.ops.disable_rx_buff(hw); 1998 1999 if (regval & IXGBE_RXCTRL_RXEN) 2000 hw->mac.ops.enable_rx(hw); 2001 else 2002 hw->mac.ops.disable_rx(hw); 2003 2004 hw->mac.ops.enable_rx_buff(hw); 2005 2006 return 0; 2007 } 2008 2009 /** 2010 * ixgbe_verify_fw_version_82599 - verify fw version for 82599 2011 * @hw: pointer to hardware structure 2012 * 2013 * Verifies that installed the firmware version is 0.6 or higher 2014 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. 2015 * 2016 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or 2017 * if the FW version is not supported. 2018 **/ 2019 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 2020 { 2021 s32 status = IXGBE_ERR_EEPROM_VERSION; 2022 u16 fw_offset, fw_ptp_cfg_offset; 2023 u16 offset; 2024 u16 fw_version = 0; 2025 2026 /* firmware check is only necessary for SFI devices */ 2027 if (hw->phy.media_type != ixgbe_media_type_fiber) 2028 return 0; 2029 2030 /* get the offset to the Firmware Module block */ 2031 offset = IXGBE_FW_PTR; 2032 if (hw->eeprom.ops.read(hw, offset, &fw_offset)) 2033 goto fw_version_err; 2034 2035 if (fw_offset == 0 || fw_offset == 0xFFFF) 2036 return IXGBE_ERR_EEPROM_VERSION; 2037 2038 /* get the offset to the Pass Through Patch Configuration block */ 2039 offset = fw_offset + IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR; 2040 if (hw->eeprom.ops.read(hw, offset, &fw_ptp_cfg_offset)) 2041 goto fw_version_err; 2042 2043 if (fw_ptp_cfg_offset == 0 || fw_ptp_cfg_offset == 0xFFFF) 2044 return IXGBE_ERR_EEPROM_VERSION; 2045 2046 /* get the firmware version */ 2047 offset = fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4; 2048 if (hw->eeprom.ops.read(hw, offset, &fw_version)) 2049 goto fw_version_err; 2050 2051 if (fw_version > 0x5) 2052 status = 0; 2053 2054 return status; 2055 2056 fw_version_err: 2057 hw_err(hw, "eeprom read at offset %d failed\n", offset); 2058 return IXGBE_ERR_EEPROM_VERSION; 2059 } 2060 2061 /** 2062 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state. 2063 * @hw: pointer to hardware structure 2064 * 2065 * Returns true if the LESM FW module is present and enabled. Otherwise 2066 * returns false. Smart Speed must be disabled if LESM FW module is enabled. 2067 **/ 2068 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) 2069 { 2070 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state; 2071 s32 status; 2072 2073 /* get the offset to the Firmware Module block */ 2074 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 2075 2076 if (status || fw_offset == 0 || fw_offset == 0xFFFF) 2077 return false; 2078 2079 /* get the offset to the LESM Parameters block */ 2080 status = hw->eeprom.ops.read(hw, (fw_offset + 2081 IXGBE_FW_LESM_PARAMETERS_PTR), 2082 &fw_lesm_param_offset); 2083 2084 if (status || 2085 fw_lesm_param_offset == 0 || fw_lesm_param_offset == 0xFFFF) 2086 return false; 2087 2088 /* get the lesm state word */ 2089 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + 2090 IXGBE_FW_LESM_STATE_1), 2091 &fw_lesm_state); 2092 2093 if (!status && (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) 2094 return true; 2095 2096 return false; 2097 } 2098 2099 /** 2100 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using 2101 * fastest available method 2102 * 2103 * @hw: pointer to hardware structure 2104 * @offset: offset of word in EEPROM to read 2105 * @words: number of words 2106 * @data: word(s) read from the EEPROM 2107 * 2108 * Retrieves 16 bit word(s) read from EEPROM 2109 **/ 2110 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, 2111 u16 words, u16 *data) 2112 { 2113 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2114 2115 /* If EEPROM is detected and can be addressed using 14 bits, 2116 * use EERD otherwise use bit bang 2117 */ 2118 if (eeprom->type == ixgbe_eeprom_spi && 2119 offset + (words - 1) <= IXGBE_EERD_MAX_ADDR) 2120 return ixgbe_read_eerd_buffer_generic(hw, offset, words, data); 2121 2122 return ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset, words, 2123 data); 2124 } 2125 2126 /** 2127 * ixgbe_read_eeprom_82599 - Read EEPROM word using 2128 * fastest available method 2129 * 2130 * @hw: pointer to hardware structure 2131 * @offset: offset of word in the EEPROM to read 2132 * @data: word read from the EEPROM 2133 * 2134 * Reads a 16 bit word from the EEPROM 2135 **/ 2136 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 2137 u16 offset, u16 *data) 2138 { 2139 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2140 2141 /* 2142 * If EEPROM is detected and can be addressed using 14 bits, 2143 * use EERD otherwise use bit bang 2144 */ 2145 if (eeprom->type == ixgbe_eeprom_spi && offset <= IXGBE_EERD_MAX_ADDR) 2146 return ixgbe_read_eerd_generic(hw, offset, data); 2147 2148 return ixgbe_read_eeprom_bit_bang_generic(hw, offset, data); 2149 } 2150 2151 /** 2152 * ixgbe_reset_pipeline_82599 - perform pipeline reset 2153 * 2154 * @hw: pointer to hardware structure 2155 * 2156 * Reset pipeline by asserting Restart_AN together with LMS change to ensure 2157 * full pipeline reset. Note - We must hold the SW/FW semaphore before writing 2158 * to AUTOC, so this function assumes the semaphore is held. 2159 **/ 2160 static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw) 2161 { 2162 s32 ret_val; 2163 u32 anlp1_reg = 0; 2164 u32 i, autoc_reg, autoc2_reg; 2165 2166 /* Enable link if disabled in NVM */ 2167 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 2168 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 2169 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 2170 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 2171 IXGBE_WRITE_FLUSH(hw); 2172 } 2173 2174 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2175 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2176 2177 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */ 2178 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, 2179 autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT)); 2180 2181 /* Wait for AN to leave state 0 */ 2182 for (i = 0; i < 10; i++) { 2183 usleep_range(4000, 8000); 2184 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2185 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK) 2186 break; 2187 } 2188 2189 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) { 2190 hw_dbg(hw, "auto negotiation not completed\n"); 2191 ret_val = IXGBE_ERR_RESET_FAILED; 2192 goto reset_pipeline_out; 2193 } 2194 2195 ret_val = 0; 2196 2197 reset_pipeline_out: 2198 /* Write AUTOC register with original LMS field and Restart_AN */ 2199 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2200 IXGBE_WRITE_FLUSH(hw); 2201 2202 return ret_val; 2203 } 2204 2205 /** 2206 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C 2207 * @hw: pointer to hardware structure 2208 * @byte_offset: byte offset to read 2209 * @data: value read 2210 * 2211 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2212 * a specified device address. 2213 **/ 2214 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 2215 u8 dev_addr, u8 *data) 2216 { 2217 u32 esdp; 2218 s32 status; 2219 s32 timeout = 200; 2220 2221 if (hw->phy.qsfp_shared_i2c_bus == true) { 2222 /* Acquire I2C bus ownership. */ 2223 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2224 esdp |= IXGBE_ESDP_SDP0; 2225 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2226 IXGBE_WRITE_FLUSH(hw); 2227 2228 while (timeout) { 2229 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2230 if (esdp & IXGBE_ESDP_SDP1) 2231 break; 2232 2233 usleep_range(5000, 10000); 2234 timeout--; 2235 } 2236 2237 if (!timeout) { 2238 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n"); 2239 status = IXGBE_ERR_I2C; 2240 goto release_i2c_access; 2241 } 2242 } 2243 2244 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data); 2245 2246 release_i2c_access: 2247 if (hw->phy.qsfp_shared_i2c_bus == true) { 2248 /* Release I2C bus ownership. */ 2249 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2250 esdp &= ~IXGBE_ESDP_SDP0; 2251 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2252 IXGBE_WRITE_FLUSH(hw); 2253 } 2254 2255 return status; 2256 } 2257 2258 /** 2259 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C 2260 * @hw: pointer to hardware structure 2261 * @byte_offset: byte offset to write 2262 * @data: value to write 2263 * 2264 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2265 * a specified device address. 2266 **/ 2267 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 2268 u8 dev_addr, u8 data) 2269 { 2270 u32 esdp; 2271 s32 status; 2272 s32 timeout = 200; 2273 2274 if (hw->phy.qsfp_shared_i2c_bus == true) { 2275 /* Acquire I2C bus ownership. */ 2276 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2277 esdp |= IXGBE_ESDP_SDP0; 2278 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2279 IXGBE_WRITE_FLUSH(hw); 2280 2281 while (timeout) { 2282 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2283 if (esdp & IXGBE_ESDP_SDP1) 2284 break; 2285 2286 usleep_range(5000, 10000); 2287 timeout--; 2288 } 2289 2290 if (!timeout) { 2291 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n"); 2292 status = IXGBE_ERR_I2C; 2293 goto release_i2c_access; 2294 } 2295 } 2296 2297 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data); 2298 2299 release_i2c_access: 2300 if (hw->phy.qsfp_shared_i2c_bus == true) { 2301 /* Release I2C bus ownership. */ 2302 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2303 esdp &= ~IXGBE_ESDP_SDP0; 2304 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2305 IXGBE_WRITE_FLUSH(hw); 2306 } 2307 2308 return status; 2309 } 2310 2311 static struct ixgbe_mac_operations mac_ops_82599 = { 2312 .init_hw = &ixgbe_init_hw_generic, 2313 .reset_hw = &ixgbe_reset_hw_82599, 2314 .start_hw = &ixgbe_start_hw_82599, 2315 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, 2316 .get_media_type = &ixgbe_get_media_type_82599, 2317 .enable_rx_dma = &ixgbe_enable_rx_dma_82599, 2318 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, 2319 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, 2320 .get_mac_addr = &ixgbe_get_mac_addr_generic, 2321 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 2322 .get_device_caps = &ixgbe_get_device_caps_generic, 2323 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 2324 .stop_adapter = &ixgbe_stop_adapter_generic, 2325 .get_bus_info = &ixgbe_get_bus_info_generic, 2326 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, 2327 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599, 2328 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599, 2329 .stop_link_on_d3 = &ixgbe_stop_mac_link_on_d3_82599, 2330 .setup_link = &ixgbe_setup_mac_link_82599, 2331 .set_rxpba = &ixgbe_set_rxpba_generic, 2332 .check_link = &ixgbe_check_mac_link_generic, 2333 .get_link_capabilities = &ixgbe_get_link_capabilities_82599, 2334 .led_on = &ixgbe_led_on_generic, 2335 .led_off = &ixgbe_led_off_generic, 2336 .blink_led_start = &ixgbe_blink_led_start_generic, 2337 .blink_led_stop = &ixgbe_blink_led_stop_generic, 2338 .set_rar = &ixgbe_set_rar_generic, 2339 .clear_rar = &ixgbe_clear_rar_generic, 2340 .set_vmdq = &ixgbe_set_vmdq_generic, 2341 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, 2342 .clear_vmdq = &ixgbe_clear_vmdq_generic, 2343 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 2344 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 2345 .enable_mc = &ixgbe_enable_mc_generic, 2346 .disable_mc = &ixgbe_disable_mc_generic, 2347 .clear_vfta = &ixgbe_clear_vfta_generic, 2348 .set_vfta = &ixgbe_set_vfta_generic, 2349 .fc_enable = &ixgbe_fc_enable_generic, 2350 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic, 2351 .init_uta_tables = &ixgbe_init_uta_tables_generic, 2352 .setup_sfp = &ixgbe_setup_sfp_modules_82599, 2353 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, 2354 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, 2355 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync, 2356 .release_swfw_sync = &ixgbe_release_swfw_sync, 2357 .get_thermal_sensor_data = &ixgbe_get_thermal_sensor_data_generic, 2358 .init_thermal_sensor_thresh = &ixgbe_init_thermal_sensor_thresh_generic, 2359 .prot_autoc_read = &prot_autoc_read_82599, 2360 .prot_autoc_write = &prot_autoc_write_82599, 2361 .enable_rx = &ixgbe_enable_rx_generic, 2362 .disable_rx = &ixgbe_disable_rx_generic, 2363 }; 2364 2365 static struct ixgbe_eeprom_operations eeprom_ops_82599 = { 2366 .init_params = &ixgbe_init_eeprom_params_generic, 2367 .read = &ixgbe_read_eeprom_82599, 2368 .read_buffer = &ixgbe_read_eeprom_buffer_82599, 2369 .write = &ixgbe_write_eeprom_generic, 2370 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic, 2371 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic, 2372 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, 2373 .update_checksum = &ixgbe_update_eeprom_checksum_generic, 2374 }; 2375 2376 static struct ixgbe_phy_operations phy_ops_82599 = { 2377 .identify = &ixgbe_identify_phy_82599, 2378 .identify_sfp = &ixgbe_identify_module_generic, 2379 .init = &ixgbe_init_phy_ops_82599, 2380 .reset = &ixgbe_reset_phy_generic, 2381 .read_reg = &ixgbe_read_phy_reg_generic, 2382 .write_reg = &ixgbe_write_phy_reg_generic, 2383 .setup_link = &ixgbe_setup_phy_link_generic, 2384 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, 2385 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, 2386 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, 2387 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, 2388 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, 2389 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, 2390 .check_overtemp = &ixgbe_tn_check_overtemp, 2391 }; 2392 2393 struct ixgbe_info ixgbe_82599_info = { 2394 .mac = ixgbe_mac_82599EB, 2395 .get_invariants = &ixgbe_get_invariants_82599, 2396 .mac_ops = &mac_ops_82599, 2397 .eeprom_ops = &eeprom_ops_82599, 2398 .phy_ops = &phy_ops_82599, 2399 .mbx_ops = &mbx_ops_generic, 2400 .mvals = ixgbe_mvals_8259X, 2401 }; 2402