1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2024 Intel Corporation. */ 3 4 #include <linux/pci.h> 5 #include <linux/delay.h> 6 #include <linux/sched.h> 7 8 #include "ixgbe.h" 9 #include "ixgbe_phy.h" 10 #include "ixgbe_mbx.h" 11 12 #define IXGBE_82599_MAX_TX_QUEUES 128 13 #define IXGBE_82599_MAX_RX_QUEUES 128 14 #define IXGBE_82599_RAR_ENTRIES 128 15 #define IXGBE_82599_MC_TBL_SIZE 128 16 #define IXGBE_82599_VFT_TBL_SIZE 128 17 #define IXGBE_82599_RX_PB_SIZE 512 18 19 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 20 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 21 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 22 static void 23 ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *, ixgbe_link_speed); 24 static int ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 25 ixgbe_link_speed speed, 26 bool autoneg_wait_to_complete); 27 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw); 28 static int ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 29 bool autoneg_wait_to_complete); 30 static int ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 31 ixgbe_link_speed speed, 32 bool autoneg_wait_to_complete); 33 static int ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 34 ixgbe_link_speed speed, 35 bool autoneg_wait_to_complete); 36 static int ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 37 static int ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 38 u8 dev_addr, u8 *data); 39 static int ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 40 u8 dev_addr, u8 data); 41 static int ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw); 42 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw); 43 44 bool ixgbe_mng_enabled(struct ixgbe_hw *hw) 45 { 46 u32 fwsm, manc, factps; 47 48 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 49 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) 50 return false; 51 52 manc = IXGBE_READ_REG(hw, IXGBE_MANC); 53 if (!(manc & IXGBE_MANC_RCV_TCO_EN)) 54 return false; 55 56 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); 57 if (factps & IXGBE_FACTPS_MNGCG) 58 return false; 59 60 return true; 61 } 62 63 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 64 { 65 struct ixgbe_mac_info *mac = &hw->mac; 66 67 /* enable the laser control functions for SFP+ fiber 68 * and MNG not enabled 69 */ 70 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && 71 !ixgbe_mng_enabled(hw)) { 72 mac->ops.disable_tx_laser = 73 &ixgbe_disable_tx_laser_multispeed_fiber; 74 mac->ops.enable_tx_laser = 75 &ixgbe_enable_tx_laser_multispeed_fiber; 76 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; 77 } else { 78 mac->ops.disable_tx_laser = NULL; 79 mac->ops.enable_tx_laser = NULL; 80 mac->ops.flap_tx_laser = NULL; 81 } 82 83 if (hw->phy.multispeed_fiber) { 84 /* Set up dual speed SFP+ support */ 85 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; 86 mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599; 87 mac->ops.set_rate_select_speed = 88 ixgbe_set_hard_rate_select_speed; 89 } else { 90 if ((mac->ops.get_media_type(hw) == 91 ixgbe_media_type_backplane) && 92 (hw->phy.smart_speed == ixgbe_smart_speed_auto || 93 hw->phy.smart_speed == ixgbe_smart_speed_on) && 94 !ixgbe_verify_lesm_fw_enabled_82599(hw)) 95 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; 96 else 97 mac->ops.setup_link = &ixgbe_setup_mac_link_82599; 98 } 99 } 100 101 static int ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 102 { 103 u16 list_offset, data_offset, data_value; 104 int ret_val; 105 106 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 107 ixgbe_init_mac_link_ops_82599(hw); 108 109 hw->phy.ops.reset = NULL; 110 111 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 112 &data_offset); 113 if (ret_val) 114 return ret_val; 115 116 /* PHY config will finish before releasing the semaphore */ 117 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 118 IXGBE_GSSR_MAC_CSR_SM); 119 if (ret_val) 120 return -EBUSY; 121 122 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 123 goto setup_sfp_err; 124 while (data_value != 0xffff) { 125 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); 126 IXGBE_WRITE_FLUSH(hw); 127 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 128 goto setup_sfp_err; 129 } 130 131 /* Release the semaphore */ 132 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 133 /* 134 * Delay obtaining semaphore again to allow FW access, 135 * semaphore_delay is in ms usleep_range needs us. 136 */ 137 usleep_range(hw->eeprom.semaphore_delay * 1000, 138 hw->eeprom.semaphore_delay * 2000); 139 140 /* Restart DSP and set SFI mode */ 141 ret_val = hw->mac.ops.prot_autoc_write(hw, 142 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL, 143 false); 144 145 if (ret_val) { 146 hw_dbg(hw, " sfp module setup not complete\n"); 147 return -EIO; 148 } 149 } 150 151 return 0; 152 153 setup_sfp_err: 154 /* Release the semaphore */ 155 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 156 /* Delay obtaining semaphore again to allow FW access, 157 * semaphore_delay is in ms usleep_range needs us. 158 */ 159 usleep_range(hw->eeprom.semaphore_delay * 1000, 160 hw->eeprom.semaphore_delay * 2000); 161 hw_err(hw, "eeprom read at offset %d failed\n", data_offset); 162 return -EIO; 163 } 164 165 /** 166 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read 167 * @hw: pointer to hardware structure 168 * @locked: Return the if we locked for this read. 169 * @reg_val: Value we read from AUTOC 170 * 171 * For this part (82599) we need to wrap read-modify-writes with a possible 172 * FW/SW lock. It is assumed this lock will be freed with the next 173 * prot_autoc_write_82599(). Note, that locked can only be true in cases 174 * where this function doesn't return an error. 175 **/ 176 static int prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, 177 u32 *reg_val) 178 { 179 int ret_val; 180 181 *locked = false; 182 /* If LESM is on then we need to hold the SW/FW semaphore. */ 183 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 184 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 185 IXGBE_GSSR_MAC_CSR_SM); 186 if (ret_val) 187 return -EBUSY; 188 189 *locked = true; 190 } 191 192 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 193 return 0; 194 } 195 196 /** 197 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write 198 * @hw: pointer to hardware structure 199 * @autoc: value to write to AUTOC 200 * @locked: bool to indicate whether the SW/FW lock was already taken by 201 * previous prot_autoc_read_82599. 202 * 203 * This part (82599) may need to hold a the SW/FW lock around all writes to 204 * AUTOC. Likewise after a write we need to do a pipeline reset. 205 **/ 206 static int prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked) 207 { 208 int ret_val = 0; 209 210 /* Blocked by MNG FW so bail */ 211 if (ixgbe_check_reset_blocked(hw)) 212 goto out; 213 214 /* We only need to get the lock if: 215 * - We didn't do it already (in the read part of a read-modify-write) 216 * - LESM is enabled. 217 */ 218 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) { 219 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 220 IXGBE_GSSR_MAC_CSR_SM); 221 if (ret_val) 222 return -EBUSY; 223 224 locked = true; 225 } 226 227 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 228 ret_val = ixgbe_reset_pipeline_82599(hw); 229 230 out: 231 /* Free the SW/FW semaphore as we either grabbed it here or 232 * already had it when this function was called. 233 */ 234 if (locked) 235 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 236 237 return ret_val; 238 } 239 240 static int ixgbe_get_invariants_82599(struct ixgbe_hw *hw) 241 { 242 struct ixgbe_mac_info *mac = &hw->mac; 243 244 ixgbe_init_mac_link_ops_82599(hw); 245 246 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; 247 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; 248 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; 249 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE; 250 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; 251 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; 252 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 253 254 return 0; 255 } 256 257 /** 258 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init 259 * @hw: pointer to hardware structure 260 * 261 * Initialize any function pointers that were not able to be 262 * set during get_invariants because the PHY/SFP type was 263 * not known. Perform the SFP init if necessary. 264 * 265 **/ 266 static int ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 267 { 268 struct ixgbe_mac_info *mac = &hw->mac; 269 struct ixgbe_phy_info *phy = &hw->phy; 270 int ret_val; 271 u32 esdp; 272 273 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) { 274 /* Store flag indicating I2C bus access control unit. */ 275 hw->phy.qsfp_shared_i2c_bus = true; 276 277 /* Initialize access to QSFP+ I2C bus */ 278 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 279 esdp |= IXGBE_ESDP_SDP0_DIR; 280 esdp &= ~IXGBE_ESDP_SDP1_DIR; 281 esdp &= ~IXGBE_ESDP_SDP0; 282 esdp &= ~IXGBE_ESDP_SDP0_NATIVE; 283 esdp &= ~IXGBE_ESDP_SDP1_NATIVE; 284 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 285 IXGBE_WRITE_FLUSH(hw); 286 287 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_82599; 288 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_82599; 289 } 290 291 /* Identify the PHY or SFP module */ 292 ret_val = phy->ops.identify(hw); 293 294 /* Setup function pointers based on detected SFP module and speeds */ 295 ixgbe_init_mac_link_ops_82599(hw); 296 297 /* If copper media, overwrite with copper function pointers */ 298 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 299 mac->ops.setup_link = &ixgbe_setup_copper_link_82599; 300 mac->ops.get_link_capabilities = 301 &ixgbe_get_copper_link_capabilities_generic; 302 } 303 304 /* Set necessary function pointers based on phy type */ 305 switch (hw->phy.type) { 306 case ixgbe_phy_tn: 307 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 308 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; 309 break; 310 default: 311 break; 312 } 313 314 return ret_val; 315 } 316 317 /** 318 * ixgbe_get_link_capabilities_82599 - Determines link capabilities 319 * @hw: pointer to hardware structure 320 * @speed: pointer to link speed 321 * @autoneg: true when autoneg or autotry is enabled 322 * 323 * Determines the link capabilities by reading the AUTOC register. 324 **/ 325 static int ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 326 ixgbe_link_speed *speed, 327 bool *autoneg) 328 { 329 u32 autoc = 0; 330 331 /* Determine 1G link capabilities off of SFP+ type */ 332 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 333 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 334 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 335 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 336 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 337 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 || 338 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core0 || 339 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core1) { 340 *speed = IXGBE_LINK_SPEED_1GB_FULL; 341 *autoneg = true; 342 return 0; 343 } 344 345 if (hw->phy.sfp_type == ixgbe_sfp_type_10g_bx_core0 || 346 hw->phy.sfp_type == ixgbe_sfp_type_10g_bx_core1) { 347 *speed = IXGBE_LINK_SPEED_10GB_FULL; 348 *autoneg = false; 349 return 0; 350 } 351 352 /* 353 * Determine link capabilities based on the stored value of AUTOC, 354 * which represents EEPROM defaults. If AUTOC value has not been 355 * stored, use the current register value. 356 */ 357 if (hw->mac.orig_link_settings_stored) 358 autoc = hw->mac.orig_autoc; 359 else 360 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 361 362 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 363 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 364 *speed = IXGBE_LINK_SPEED_1GB_FULL; 365 *autoneg = false; 366 break; 367 368 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 369 *speed = IXGBE_LINK_SPEED_10GB_FULL; 370 *autoneg = false; 371 break; 372 373 case IXGBE_AUTOC_LMS_1G_AN: 374 *speed = IXGBE_LINK_SPEED_1GB_FULL; 375 *autoneg = true; 376 break; 377 378 case IXGBE_AUTOC_LMS_10G_SERIAL: 379 *speed = IXGBE_LINK_SPEED_10GB_FULL; 380 *autoneg = false; 381 break; 382 383 case IXGBE_AUTOC_LMS_KX4_KX_KR: 384 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 385 *speed = IXGBE_LINK_SPEED_UNKNOWN; 386 if (autoc & IXGBE_AUTOC_KR_SUPP) 387 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 388 if (autoc & IXGBE_AUTOC_KX4_SUPP) 389 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 390 if (autoc & IXGBE_AUTOC_KX_SUPP) 391 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 392 *autoneg = true; 393 break; 394 395 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: 396 *speed = IXGBE_LINK_SPEED_100_FULL; 397 if (autoc & IXGBE_AUTOC_KR_SUPP) 398 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 399 if (autoc & IXGBE_AUTOC_KX4_SUPP) 400 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 401 if (autoc & IXGBE_AUTOC_KX_SUPP) 402 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 403 *autoneg = true; 404 break; 405 406 case IXGBE_AUTOC_LMS_SGMII_1G_100M: 407 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; 408 *autoneg = false; 409 break; 410 411 default: 412 return -EIO; 413 } 414 415 if (hw->phy.multispeed_fiber) { 416 *speed |= IXGBE_LINK_SPEED_10GB_FULL | 417 IXGBE_LINK_SPEED_1GB_FULL; 418 419 /* QSFP must not enable auto-negotiation */ 420 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp) 421 *autoneg = false; 422 else 423 *autoneg = true; 424 } 425 426 return 0; 427 } 428 429 /** 430 * ixgbe_get_media_type_82599 - Get media type 431 * @hw: pointer to hardware structure 432 * 433 * Returns the media type (fiber, copper, backplane) 434 **/ 435 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 436 { 437 /* Detect if there is a copper PHY attached. */ 438 switch (hw->phy.type) { 439 case ixgbe_phy_cu_unknown: 440 case ixgbe_phy_tn: 441 return ixgbe_media_type_copper; 442 443 default: 444 break; 445 } 446 447 switch (hw->device_id) { 448 case IXGBE_DEV_ID_82599_KX4: 449 case IXGBE_DEV_ID_82599_KX4_MEZZ: 450 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 451 case IXGBE_DEV_ID_82599_KR: 452 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 453 case IXGBE_DEV_ID_82599_XAUI_LOM: 454 /* Default device ID is mezzanine card KX/KX4 */ 455 return ixgbe_media_type_backplane; 456 457 case IXGBE_DEV_ID_82599_SFP: 458 case IXGBE_DEV_ID_82599_SFP_FCOE: 459 case IXGBE_DEV_ID_82599_SFP_EM: 460 case IXGBE_DEV_ID_82599_SFP_SF2: 461 case IXGBE_DEV_ID_82599_SFP_SF_QP: 462 case IXGBE_DEV_ID_82599EN_SFP: 463 return ixgbe_media_type_fiber; 464 465 case IXGBE_DEV_ID_82599_CX4: 466 return ixgbe_media_type_cx4; 467 468 case IXGBE_DEV_ID_82599_T3_LOM: 469 return ixgbe_media_type_copper; 470 471 case IXGBE_DEV_ID_82599_LS: 472 return ixgbe_media_type_fiber_lco; 473 474 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 475 return ixgbe_media_type_fiber_qsfp; 476 477 default: 478 return ixgbe_media_type_unknown; 479 } 480 } 481 482 /** 483 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3 484 * @hw: pointer to hardware structure 485 * 486 * Disables link, should be called during D3 power down sequence. 487 * 488 **/ 489 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw) 490 { 491 u32 autoc2_reg; 492 u16 ee_ctrl_2 = 0; 493 494 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2); 495 496 if (!ixgbe_mng_present(hw) && !hw->wol_enabled && 497 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) { 498 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 499 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK; 500 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 501 } 502 } 503 504 /** 505 * ixgbe_start_mac_link_82599 - Setup MAC link settings 506 * @hw: pointer to hardware structure 507 * @autoneg_wait_to_complete: true when waiting for completion is needed 508 * 509 * Configures link settings based on values in the ixgbe_hw struct. 510 * Restarts the link. Performs autonegotiation if needed. 511 **/ 512 static int ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 513 bool autoneg_wait_to_complete) 514 { 515 bool got_lock = false; 516 int status = 0; 517 u32 autoc_reg; 518 u32 links_reg; 519 u32 i; 520 521 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 522 status = hw->mac.ops.acquire_swfw_sync(hw, 523 IXGBE_GSSR_MAC_CSR_SM); 524 if (status) 525 return status; 526 527 got_lock = true; 528 } 529 530 /* Restart link */ 531 ixgbe_reset_pipeline_82599(hw); 532 533 if (got_lock) 534 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 535 536 /* Only poll for autoneg to complete if specified to do so */ 537 if (autoneg_wait_to_complete) { 538 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 539 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 540 IXGBE_AUTOC_LMS_KX4_KX_KR || 541 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 542 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 543 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 544 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 545 links_reg = 0; /* Just in case Autoneg time = 0 */ 546 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 547 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 548 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 549 break; 550 msleep(100); 551 } 552 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 553 status = -EIO; 554 hw_dbg(hw, "Autoneg did not complete.\n"); 555 } 556 } 557 } 558 559 /* Add delay to filter out noises during initial link setup */ 560 msleep(50); 561 562 return status; 563 } 564 565 /** 566 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser 567 * @hw: pointer to hardware structure 568 * 569 * The base drivers may require better control over SFP+ module 570 * PHY states. This includes selectively shutting down the Tx 571 * laser on the PHY, effectively halting physical link. 572 **/ 573 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 574 { 575 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 576 577 /* Blocked by MNG FW so bail */ 578 if (ixgbe_check_reset_blocked(hw)) 579 return; 580 581 /* Disable tx laser; allow 100us to go dark per spec */ 582 esdp_reg |= IXGBE_ESDP_SDP3; 583 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 584 IXGBE_WRITE_FLUSH(hw); 585 udelay(100); 586 } 587 588 /** 589 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser 590 * @hw: pointer to hardware structure 591 * 592 * The base drivers may require better control over SFP+ module 593 * PHY states. This includes selectively turning on the Tx 594 * laser on the PHY, effectively starting physical link. 595 **/ 596 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 597 { 598 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 599 600 /* Enable tx laser; allow 100ms to light up */ 601 esdp_reg &= ~IXGBE_ESDP_SDP3; 602 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 603 IXGBE_WRITE_FLUSH(hw); 604 msleep(100); 605 } 606 607 /** 608 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser 609 * @hw: pointer to hardware structure 610 * 611 * When the driver changes the link speeds that it can support, 612 * it sets autotry_restart to true to indicate that we need to 613 * initiate a new autotry session with the link partner. To do 614 * so, we set the speed then disable and re-enable the tx laser, to 615 * alert the link partner that it also needs to restart autotry on its 616 * end. This is consistent with true clause 37 autoneg, which also 617 * involves a loss of signal. 618 **/ 619 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 620 { 621 /* Blocked by MNG FW so bail */ 622 if (ixgbe_check_reset_blocked(hw)) 623 return; 624 625 if (hw->mac.autotry_restart) { 626 ixgbe_disable_tx_laser_multispeed_fiber(hw); 627 ixgbe_enable_tx_laser_multispeed_fiber(hw); 628 hw->mac.autotry_restart = false; 629 } 630 } 631 632 /** 633 * ixgbe_set_hard_rate_select_speed - Set module link speed 634 * @hw: pointer to hardware structure 635 * @speed: link speed to set 636 * 637 * Set module link speed via RS0/RS1 rate select pins. 638 */ 639 static void 640 ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 641 { 642 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 643 644 switch (speed) { 645 case IXGBE_LINK_SPEED_10GB_FULL: 646 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); 647 break; 648 case IXGBE_LINK_SPEED_1GB_FULL: 649 esdp_reg &= ~IXGBE_ESDP_SDP5; 650 esdp_reg |= IXGBE_ESDP_SDP5_DIR; 651 break; 652 default: 653 hw_dbg(hw, "Invalid fixed module speed\n"); 654 return; 655 } 656 657 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 658 IXGBE_WRITE_FLUSH(hw); 659 } 660 661 /** 662 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed 663 * @hw: pointer to hardware structure 664 * @speed: new link speed 665 * @autoneg_wait_to_complete: true when waiting for completion is needed 666 * 667 * Implements the Intel SmartSpeed algorithm. 668 **/ 669 static int ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 670 ixgbe_link_speed speed, 671 bool autoneg_wait_to_complete) 672 { 673 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 674 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 675 bool link_up = false; 676 int status = 0; 677 s32 i, j; 678 679 /* Set autoneg_advertised value based on input link speed */ 680 hw->phy.autoneg_advertised = 0; 681 682 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 683 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 684 685 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 686 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 687 688 if (speed & IXGBE_LINK_SPEED_100_FULL) 689 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 690 691 /* 692 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the 693 * autoneg advertisement if link is unable to be established at the 694 * highest negotiated rate. This can sometimes happen due to integrity 695 * issues with the physical media connection. 696 */ 697 698 /* First, try to get link with full advertisement */ 699 hw->phy.smart_speed_active = false; 700 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { 701 status = ixgbe_setup_mac_link_82599(hw, speed, 702 autoneg_wait_to_complete); 703 if (status != 0) 704 goto out; 705 706 /* 707 * Wait for the controller to acquire link. Per IEEE 802.3ap, 708 * Section 73.10.2, we may have to wait up to 500ms if KR is 709 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per 710 * Table 9 in the AN MAS. 711 */ 712 for (i = 0; i < 5; i++) { 713 mdelay(100); 714 715 /* If we have link, just jump out */ 716 status = hw->mac.ops.check_link(hw, &link_speed, 717 &link_up, false); 718 if (status != 0) 719 goto out; 720 721 if (link_up) 722 goto out; 723 } 724 } 725 726 /* 727 * We didn't get link. If we advertised KR plus one of KX4/KX 728 * (or BX4/BX), then disable KR and try again. 729 */ 730 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || 731 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) 732 goto out; 733 734 /* Turn SmartSpeed on to disable KR support */ 735 hw->phy.smart_speed_active = true; 736 status = ixgbe_setup_mac_link_82599(hw, speed, 737 autoneg_wait_to_complete); 738 if (status != 0) 739 goto out; 740 741 /* 742 * Wait for the controller to acquire link. 600ms will allow for 743 * the AN link_fail_inhibit_timer as well for multiple cycles of 744 * parallel detect, both 10g and 1g. This allows for the maximum 745 * connect attempts as defined in the AN MAS table 73-7. 746 */ 747 for (i = 0; i < 6; i++) { 748 mdelay(100); 749 750 /* If we have link, just jump out */ 751 status = hw->mac.ops.check_link(hw, &link_speed, 752 &link_up, false); 753 if (status != 0) 754 goto out; 755 756 if (link_up) 757 goto out; 758 } 759 760 /* We didn't get link. Turn SmartSpeed back off. */ 761 hw->phy.smart_speed_active = false; 762 status = ixgbe_setup_mac_link_82599(hw, speed, 763 autoneg_wait_to_complete); 764 765 out: 766 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) 767 hw_dbg(hw, "Smartspeed has downgraded the link speed from the maximum advertised\n"); 768 return status; 769 } 770 771 /** 772 * ixgbe_setup_mac_link_82599 - Set MAC link speed 773 * @hw: pointer to hardware structure 774 * @speed: new link speed 775 * @autoneg_wait_to_complete: true when waiting for completion is needed 776 * 777 * Set the link speed in the AUTOC register and restarts link. 778 **/ 779 static int ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 780 ixgbe_link_speed speed, 781 bool autoneg_wait_to_complete) 782 { 783 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 784 u32 pma_pmd_10g_serial, pma_pmd_1g, link_mode, links_reg, i; 785 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 786 bool autoneg = false; 787 int status; 788 789 /* holds the value of AUTOC register at this current point in time */ 790 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 791 /* holds the cached value of AUTOC register */ 792 u32 orig_autoc = 0; 793 /* temporary variable used for comparison purposes */ 794 u32 autoc = current_autoc; 795 796 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 797 798 /* Check to see if speed passed in is supported. */ 799 status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities, 800 &autoneg); 801 if (status) 802 return status; 803 804 speed &= link_capabilities; 805 806 if (speed == IXGBE_LINK_SPEED_UNKNOWN) 807 return -EINVAL; 808 809 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ 810 if (hw->mac.orig_link_settings_stored) 811 orig_autoc = hw->mac.orig_autoc; 812 else 813 orig_autoc = autoc; 814 815 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 816 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 817 818 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 819 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 820 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 821 /* Set KX4/KX/KR support according to speed requested */ 822 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); 823 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 824 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) 825 autoc |= IXGBE_AUTOC_KX4_SUPP; 826 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && 827 (hw->phy.smart_speed_active == false)) 828 autoc |= IXGBE_AUTOC_KR_SUPP; 829 } 830 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 831 autoc |= IXGBE_AUTOC_KX_SUPP; 832 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && 833 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || 834 link_mode == IXGBE_AUTOC_LMS_1G_AN)) { 835 /* Switch from 1G SFI to 10G SFI if requested */ 836 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 837 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { 838 autoc &= ~IXGBE_AUTOC_LMS_MASK; 839 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; 840 } 841 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && 842 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { 843 /* Switch from 10G SFI to 1G SFI if requested */ 844 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 845 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { 846 autoc &= ~IXGBE_AUTOC_LMS_MASK; 847 if (autoneg) 848 autoc |= IXGBE_AUTOC_LMS_1G_AN; 849 else 850 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 851 } 852 } 853 854 if (autoc != current_autoc) { 855 /* Restart link */ 856 status = hw->mac.ops.prot_autoc_write(hw, autoc, false); 857 if (status) 858 return status; 859 860 /* Only poll for autoneg to complete if specified to do so */ 861 if (autoneg_wait_to_complete) { 862 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 863 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 864 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 865 links_reg = 0; /*Just in case Autoneg time=0*/ 866 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 867 links_reg = 868 IXGBE_READ_REG(hw, IXGBE_LINKS); 869 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 870 break; 871 msleep(100); 872 } 873 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 874 status = -EIO; 875 hw_dbg(hw, "Autoneg did not complete.\n"); 876 } 877 } 878 } 879 880 /* Add delay to filter out noises during initial link setup */ 881 msleep(50); 882 } 883 884 return status; 885 } 886 887 /** 888 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field 889 * @hw: pointer to hardware structure 890 * @speed: new link speed 891 * @autoneg_wait_to_complete: true if waiting is needed to complete 892 * 893 * Restarts link on PHY and MAC based on settings passed in. 894 **/ 895 static int ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 896 ixgbe_link_speed speed, 897 bool autoneg_wait_to_complete) 898 { 899 int status; 900 901 /* Setup the PHY according to input speed */ 902 status = hw->phy.ops.setup_link_speed(hw, speed, 903 autoneg_wait_to_complete); 904 /* Set up MAC */ 905 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); 906 907 return status; 908 } 909 910 /** 911 * ixgbe_reset_hw_82599 - Perform hardware reset 912 * @hw: pointer to hardware structure 913 * 914 * Resets the hardware by resetting the transmit and receive units, masks 915 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 916 * reset. 917 **/ 918 static int ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 919 { 920 ixgbe_link_speed link_speed; 921 u32 ctrl, i, autoc, autoc2; 922 bool link_up = false; 923 u32 curr_lms; 924 int status; 925 926 /* Call adapter stop to disable tx/rx and clear interrupts */ 927 status = hw->mac.ops.stop_adapter(hw); 928 if (status) 929 return status; 930 931 /* flush pending Tx transactions */ 932 ixgbe_clear_tx_pending(hw); 933 934 /* PHY ops must be identified and initialized prior to reset */ 935 936 /* Identify PHY and related function pointers */ 937 status = hw->phy.ops.init(hw); 938 939 if (status == -EOPNOTSUPP) 940 return status; 941 942 /* Setup SFP module if there is one present. */ 943 if (hw->phy.sfp_setup_needed) { 944 status = hw->mac.ops.setup_sfp(hw); 945 hw->phy.sfp_setup_needed = false; 946 } 947 948 if (status == -EOPNOTSUPP) 949 return status; 950 951 /* Reset PHY */ 952 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) 953 hw->phy.ops.reset(hw); 954 955 /* remember AUTOC from before we reset */ 956 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK; 957 958 mac_reset_top: 959 /* 960 * Issue global reset to the MAC. Needs to be SW reset if link is up. 961 * If link reset is used when link is up, it might reset the PHY when 962 * mng is using it. If link is down or the flag to force full link 963 * reset is set, then perform link reset. 964 */ 965 ctrl = IXGBE_CTRL_LNK_RST; 966 if (!hw->force_full_reset) { 967 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 968 if (link_up) 969 ctrl = IXGBE_CTRL_RST; 970 } 971 972 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 973 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 974 IXGBE_WRITE_FLUSH(hw); 975 usleep_range(1000, 1200); 976 977 /* Poll for reset bit to self-clear indicating reset is complete */ 978 for (i = 0; i < 10; i++) { 979 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 980 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 981 break; 982 udelay(1); 983 } 984 985 if (ctrl & IXGBE_CTRL_RST_MASK) { 986 status = -EIO; 987 hw_dbg(hw, "Reset polling failed to complete.\n"); 988 } 989 990 msleep(50); 991 992 /* 993 * Double resets are required for recovery from certain error 994 * conditions. Between resets, it is necessary to stall to allow time 995 * for any pending HW events to complete. 996 */ 997 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 998 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 999 goto mac_reset_top; 1000 } 1001 1002 /* 1003 * Store the original AUTOC/AUTOC2 values if they have not been 1004 * stored off yet. Otherwise restore the stored original 1005 * values since the reset operation sets back to defaults. 1006 */ 1007 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1008 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1009 1010 /* Enable link if disabled in NVM */ 1011 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 1012 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 1013 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1014 IXGBE_WRITE_FLUSH(hw); 1015 } 1016 1017 if (hw->mac.orig_link_settings_stored == false) { 1018 hw->mac.orig_autoc = autoc; 1019 hw->mac.orig_autoc2 = autoc2; 1020 hw->mac.orig_link_settings_stored = true; 1021 } else { 1022 1023 /* If MNG FW is running on a multi-speed device that 1024 * doesn't autoneg with out driver support we need to 1025 * leave LMS in the state it was before we MAC reset. 1026 * Likewise if we support WoL we don't want change the 1027 * LMS state either. 1028 */ 1029 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) || 1030 hw->wol_enabled) 1031 hw->mac.orig_autoc = 1032 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) | 1033 curr_lms; 1034 1035 if (autoc != hw->mac.orig_autoc) { 1036 status = hw->mac.ops.prot_autoc_write(hw, 1037 hw->mac.orig_autoc, 1038 false); 1039 if (status) 1040 return status; 1041 } 1042 1043 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != 1044 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { 1045 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; 1046 autoc2 |= (hw->mac.orig_autoc2 & 1047 IXGBE_AUTOC2_UPPER_MASK); 1048 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1049 } 1050 } 1051 1052 /* Store the permanent mac address */ 1053 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1054 1055 /* 1056 * Store MAC address from RAR0, clear receive address registers, and 1057 * clear the multicast table. Also reset num_rar_entries to 128, 1058 * since we modify this value when programming the SAN MAC address. 1059 */ 1060 hw->mac.num_rar_entries = IXGBE_82599_RAR_ENTRIES; 1061 hw->mac.ops.init_rx_addrs(hw); 1062 1063 /* Store the permanent SAN mac address */ 1064 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 1065 1066 /* Add the SAN MAC address to the RAR only if it's a valid address */ 1067 if (is_valid_ether_addr(hw->mac.san_addr)) { 1068 /* Save the SAN MAC RAR index */ 1069 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 1070 1071 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, 1072 hw->mac.san_addr, 0, IXGBE_RAH_AV); 1073 1074 /* clear VMDq pool/queue selection for this RAR */ 1075 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, 1076 IXGBE_CLEAR_VMDQ_ALL); 1077 1078 /* Reserve the last RAR for the SAN MAC address */ 1079 hw->mac.num_rar_entries--; 1080 } 1081 1082 /* Store the alternative WWNN/WWPN prefix */ 1083 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 1084 &hw->mac.wwpn_prefix); 1085 1086 return status; 1087 } 1088 1089 /** 1090 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete 1091 * @hw: pointer to hardware structure 1092 * @fdircmd: current value of FDIRCMD register 1093 */ 1094 static int ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd) 1095 { 1096 int i; 1097 1098 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { 1099 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD); 1100 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK)) 1101 return 0; 1102 udelay(10); 1103 } 1104 1105 return -EIO; 1106 } 1107 1108 /** 1109 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. 1110 * @hw: pointer to hardware structure 1111 **/ 1112 int ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) 1113 { 1114 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1115 u32 fdircmd; 1116 int err; 1117 int i; 1118 1119 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; 1120 1121 /* 1122 * Before starting reinitialization process, 1123 * FDIRCMD.CMD must be zero. 1124 */ 1125 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1126 if (err) { 1127 hw_dbg(hw, "Flow Director previous command did not complete, aborting table re-initialization.\n"); 1128 return err; 1129 } 1130 1131 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); 1132 IXGBE_WRITE_FLUSH(hw); 1133 /* 1134 * 82599 adapters flow director init flow cannot be restarted, 1135 * Workaround 82599 silicon errata by performing the following steps 1136 * before re-writing the FDIRCTRL control register with the same value. 1137 * - write 1 to bit 8 of FDIRCMD register & 1138 * - write 0 to bit 8 of FDIRCMD register 1139 */ 1140 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1141 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1142 IXGBE_FDIRCMD_CLEARHT)); 1143 IXGBE_WRITE_FLUSH(hw); 1144 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1145 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1146 ~IXGBE_FDIRCMD_CLEARHT)); 1147 IXGBE_WRITE_FLUSH(hw); 1148 /* 1149 * Clear FDIR Hash register to clear any leftover hashes 1150 * waiting to be programmed. 1151 */ 1152 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); 1153 IXGBE_WRITE_FLUSH(hw); 1154 1155 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1156 IXGBE_WRITE_FLUSH(hw); 1157 1158 /* Poll init-done after we write FDIRCTRL register */ 1159 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1160 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1161 IXGBE_FDIRCTRL_INIT_DONE) 1162 break; 1163 usleep_range(1000, 2000); 1164 } 1165 if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 1166 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n"); 1167 return -EIO; 1168 } 1169 1170 /* Clear FDIR statistics registers (read to clear) */ 1171 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); 1172 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); 1173 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 1174 IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 1175 IXGBE_READ_REG(hw, IXGBE_FDIRLEN); 1176 1177 return 0; 1178 } 1179 1180 /** 1181 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers 1182 * @hw: pointer to hardware structure 1183 * @fdirctrl: value to write to flow director control register 1184 **/ 1185 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1186 { 1187 int i; 1188 1189 /* Prime the keys for hashing */ 1190 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); 1191 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); 1192 1193 /* 1194 * Poll init-done after we write the register. Estimated times: 1195 * 10G: PBALLOC = 11b, timing is 60us 1196 * 1G: PBALLOC = 11b, timing is 600us 1197 * 100M: PBALLOC = 11b, timing is 6ms 1198 * 1199 * Multiple these timings by 4 if under full Rx load 1200 * 1201 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1202 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1203 * this might not finish in our poll time, but we can live with that 1204 * for now. 1205 */ 1206 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1207 IXGBE_WRITE_FLUSH(hw); 1208 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1209 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1210 IXGBE_FDIRCTRL_INIT_DONE) 1211 break; 1212 usleep_range(1000, 2000); 1213 } 1214 1215 if (i >= IXGBE_FDIR_INIT_DONE_POLL) 1216 hw_dbg(hw, "Flow Director poll time exceeded!\n"); 1217 } 1218 1219 /** 1220 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters 1221 * @hw: pointer to hardware structure 1222 * @fdirctrl: value to write to flow director control register, initially 1223 * contains just the value of the Rx packet buffer allocation 1224 **/ 1225 int ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1226 { 1227 /* 1228 * Continue setup of fdirctrl register bits: 1229 * Move the flexible bytes to use the ethertype - shift 6 words 1230 * Set the maximum length per hash bucket to 0xA filters 1231 * Send interrupt when 64 filters are left 1232 */ 1233 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1234 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1235 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1236 1237 /* write hashes and fdirctrl register, poll for completion */ 1238 ixgbe_fdir_enable_82599(hw, fdirctrl); 1239 1240 return 0; 1241 } 1242 1243 /** 1244 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters 1245 * @hw: pointer to hardware structure 1246 * @fdirctrl: value to write to flow director control register, initially 1247 * contains just the value of the Rx packet buffer allocation 1248 **/ 1249 int ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1250 { 1251 /* 1252 * Continue setup of fdirctrl register bits: 1253 * Turn perfect match filtering on 1254 * Initialize the drop queue 1255 * Move the flexible bytes to use the ethertype - shift 6 words 1256 * Set the maximum length per hash bucket to 0xA filters 1257 * Send interrupt when 64 (0x4 * 16) filters are left 1258 */ 1259 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH | 1260 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) | 1261 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1262 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1263 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1264 1265 /* write hashes and fdirctrl register, poll for completion */ 1266 ixgbe_fdir_enable_82599(hw, fdirctrl); 1267 1268 return 0; 1269 } 1270 1271 /* 1272 * These defines allow us to quickly generate all of the necessary instructions 1273 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION 1274 * for values 0 through 15 1275 */ 1276 #define IXGBE_ATR_COMMON_HASH_KEY \ 1277 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY) 1278 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \ 1279 do { \ 1280 u32 n = (_n); \ 1281 if (IXGBE_ATR_COMMON_HASH_KEY & BIT(n)) \ 1282 common_hash ^= lo_hash_dword >> n; \ 1283 else if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n)) \ 1284 bucket_hash ^= lo_hash_dword >> n; \ 1285 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & BIT(n)) \ 1286 sig_hash ^= lo_hash_dword << (16 - n); \ 1287 if (IXGBE_ATR_COMMON_HASH_KEY & BIT(n + 16)) \ 1288 common_hash ^= hi_hash_dword >> n; \ 1289 else if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n + 16)) \ 1290 bucket_hash ^= hi_hash_dword >> n; \ 1291 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & BIT(n + 16)) \ 1292 sig_hash ^= hi_hash_dword << (16 - n); \ 1293 } while (0) 1294 1295 /** 1296 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash 1297 * @input: input bitstream to compute the hash on 1298 * @common: compressed common input dword 1299 * 1300 * This function is almost identical to the function above but contains 1301 * several optimizations such as unwinding all of the loops, letting the 1302 * compiler work out all of the conditional ifs since the keys are static 1303 * defines, and computing two keys at once since the hashed dword stream 1304 * will be the same for both keys. 1305 **/ 1306 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, 1307 union ixgbe_atr_hash_dword common) 1308 { 1309 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1310 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0; 1311 1312 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1313 flow_vm_vlan = ntohl(input.dword); 1314 1315 /* generate common hash dword */ 1316 hi_hash_dword = ntohl(common.dword); 1317 1318 /* low dword is word swapped version of common */ 1319 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1320 1321 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1322 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1323 1324 /* Process bits 0 and 16 */ 1325 IXGBE_COMPUTE_SIG_HASH_ITERATION(0); 1326 1327 /* 1328 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1329 * delay this because bit 0 of the stream should not be processed 1330 * so we do not add the vlan until after bit 0 was processed 1331 */ 1332 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1333 1334 /* Process remaining 30 bit of the key */ 1335 IXGBE_COMPUTE_SIG_HASH_ITERATION(1); 1336 IXGBE_COMPUTE_SIG_HASH_ITERATION(2); 1337 IXGBE_COMPUTE_SIG_HASH_ITERATION(3); 1338 IXGBE_COMPUTE_SIG_HASH_ITERATION(4); 1339 IXGBE_COMPUTE_SIG_HASH_ITERATION(5); 1340 IXGBE_COMPUTE_SIG_HASH_ITERATION(6); 1341 IXGBE_COMPUTE_SIG_HASH_ITERATION(7); 1342 IXGBE_COMPUTE_SIG_HASH_ITERATION(8); 1343 IXGBE_COMPUTE_SIG_HASH_ITERATION(9); 1344 IXGBE_COMPUTE_SIG_HASH_ITERATION(10); 1345 IXGBE_COMPUTE_SIG_HASH_ITERATION(11); 1346 IXGBE_COMPUTE_SIG_HASH_ITERATION(12); 1347 IXGBE_COMPUTE_SIG_HASH_ITERATION(13); 1348 IXGBE_COMPUTE_SIG_HASH_ITERATION(14); 1349 IXGBE_COMPUTE_SIG_HASH_ITERATION(15); 1350 1351 /* combine common_hash result with signature and bucket hashes */ 1352 bucket_hash ^= common_hash; 1353 bucket_hash &= IXGBE_ATR_HASH_MASK; 1354 1355 sig_hash ^= common_hash << 16; 1356 sig_hash &= IXGBE_ATR_HASH_MASK << 16; 1357 1358 /* return completed signature hash */ 1359 return sig_hash ^ bucket_hash; 1360 } 1361 1362 /** 1363 * ixgbe_fdir_add_signature_filter_82599 - Adds a signature hash filter 1364 * @hw: pointer to hardware structure 1365 * @input: unique input dword 1366 * @common: compressed common input dword 1367 * @queue: queue index to direct traffic to 1368 * 1369 * Note that the tunnel bit in input must not be set when the hardware 1370 * tunneling support does not exist. 1371 **/ 1372 int ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 1373 union ixgbe_atr_hash_dword input, 1374 union ixgbe_atr_hash_dword common, 1375 u8 queue) 1376 { 1377 u64 fdirhashcmd; 1378 u8 flow_type; 1379 bool tunnel; 1380 u32 fdircmd; 1381 1382 /* 1383 * Get the flow_type in order to program FDIRCMD properly 1384 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 1385 */ 1386 tunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK); 1387 flow_type = input.formatted.flow_type & 1388 (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1); 1389 switch (flow_type) { 1390 case IXGBE_ATR_FLOW_TYPE_TCPV4: 1391 case IXGBE_ATR_FLOW_TYPE_UDPV4: 1392 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 1393 case IXGBE_ATR_FLOW_TYPE_TCPV6: 1394 case IXGBE_ATR_FLOW_TYPE_UDPV6: 1395 case IXGBE_ATR_FLOW_TYPE_SCTPV6: 1396 break; 1397 default: 1398 hw_dbg(hw, " Error on flow type input\n"); 1399 return -EIO; 1400 } 1401 1402 /* configure FDIRCMD register */ 1403 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1404 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1405 fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1406 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1407 if (tunnel) 1408 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER; 1409 1410 /* 1411 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits 1412 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. 1413 */ 1414 fdirhashcmd = (u64)fdircmd << 32; 1415 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common); 1416 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); 1417 1418 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); 1419 1420 return 0; 1421 } 1422 1423 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \ 1424 do { \ 1425 u32 n = (_n); \ 1426 if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n)) \ 1427 bucket_hash ^= lo_hash_dword >> n; \ 1428 if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n + 16)) \ 1429 bucket_hash ^= hi_hash_dword >> n; \ 1430 } while (0) 1431 1432 /** 1433 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash 1434 * @input: input bitstream to compute the hash on 1435 * @input_mask: mask for the input bitstream 1436 * 1437 * This function serves two main purposes. First it applies the input_mask 1438 * to the atr_input resulting in a cleaned up atr_input data stream. 1439 * Secondly it computes the hash and stores it in the bkt_hash field at 1440 * the end of the input byte stream. This way it will be available for 1441 * future use without needing to recompute the hash. 1442 **/ 1443 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 1444 union ixgbe_atr_input *input_mask) 1445 { 1446 1447 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1448 u32 bucket_hash = 0; 1449 __be32 hi_dword = 0; 1450 int i; 1451 1452 /* Apply masks to input data */ 1453 for (i = 0; i <= 10; i++) 1454 input->dword_stream[i] &= input_mask->dword_stream[i]; 1455 1456 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1457 flow_vm_vlan = ntohl(input->dword_stream[0]); 1458 1459 /* generate common hash dword */ 1460 for (i = 1; i <= 10; i++) 1461 hi_dword ^= input->dword_stream[i]; 1462 hi_hash_dword = ntohl(hi_dword); 1463 1464 /* low dword is word swapped version of common */ 1465 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1466 1467 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1468 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1469 1470 /* Process bits 0 and 16 */ 1471 IXGBE_COMPUTE_BKT_HASH_ITERATION(0); 1472 1473 /* 1474 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1475 * delay this because bit 0 of the stream should not be processed 1476 * so we do not add the vlan until after bit 0 was processed 1477 */ 1478 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1479 1480 /* Process remaining 30 bit of the key */ 1481 for (i = 1; i <= 15; i++) 1482 IXGBE_COMPUTE_BKT_HASH_ITERATION(i); 1483 1484 /* 1485 * Limit hash to 13 bits since max bucket count is 8K. 1486 * Store result at the end of the input stream. 1487 */ 1488 input->formatted.bkt_hash = (__force __be16)(bucket_hash & 0x1FFF); 1489 } 1490 1491 /** 1492 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks 1493 * @input_mask: mask to be bit swapped 1494 * 1495 * The source and destination port masks for flow director are bit swapped 1496 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to 1497 * generate a correctly swapped value we need to bit swap the mask and that 1498 * is what is accomplished by this function. 1499 **/ 1500 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask) 1501 { 1502 u32 mask = ntohs(input_mask->formatted.dst_port); 1503 1504 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT; 1505 mask |= ntohs(input_mask->formatted.src_port); 1506 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); 1507 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); 1508 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); 1509 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); 1510 } 1511 1512 /* 1513 * These two macros are meant to address the fact that we have registers 1514 * that are either all or in part big-endian. As a result on big-endian 1515 * systems we will end up byte swapping the value to little-endian before 1516 * it is byte swapped again and written to the hardware in the original 1517 * big-endian format. 1518 */ 1519 #define IXGBE_STORE_AS_BE32(_value) \ 1520 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \ 1521 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24)) 1522 1523 #define IXGBE_WRITE_REG_BE32(a, reg, value) \ 1524 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value))) 1525 1526 #define IXGBE_STORE_AS_BE16(_value) __swab16(ntohs((_value))) 1527 1528 int ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 1529 union ixgbe_atr_input *input_mask) 1530 { 1531 /* mask IPv6 since it is currently not supported */ 1532 u32 fdirm = IXGBE_FDIRM_DIPv6; 1533 u32 fdirtcpm; 1534 1535 /* 1536 * Program the relevant mask registers. If src/dst_port or src/dst_addr 1537 * are zero, then assume a full mask for that field. Also assume that 1538 * a VLAN of 0 is unspecified, so mask that out as well. L4type 1539 * cannot be masked out in this implementation. 1540 * 1541 * This also assumes IPv4 only. IPv6 masking isn't supported at this 1542 * point in time. 1543 */ 1544 1545 /* verify bucket hash is cleared on hash generation */ 1546 if (input_mask->formatted.bkt_hash) 1547 hw_dbg(hw, " bucket hash should always be 0 in mask\n"); 1548 1549 /* Program FDIRM and verify partial masks */ 1550 switch (input_mask->formatted.vm_pool & 0x7F) { 1551 case 0x0: 1552 fdirm |= IXGBE_FDIRM_POOL; 1553 break; 1554 case 0x7F: 1555 break; 1556 default: 1557 hw_dbg(hw, " Error on vm pool mask\n"); 1558 return -EIO; 1559 } 1560 1561 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) { 1562 case 0x0: 1563 fdirm |= IXGBE_FDIRM_L4P; 1564 if (input_mask->formatted.dst_port || 1565 input_mask->formatted.src_port) { 1566 hw_dbg(hw, " Error on src/dst port mask\n"); 1567 return -EIO; 1568 } 1569 break; 1570 case IXGBE_ATR_L4TYPE_MASK: 1571 break; 1572 default: 1573 hw_dbg(hw, " Error on flow type mask\n"); 1574 return -EIO; 1575 } 1576 1577 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) { 1578 case 0x0000: 1579 /* mask VLAN ID */ 1580 fdirm |= IXGBE_FDIRM_VLANID; 1581 fallthrough; 1582 case 0x0FFF: 1583 /* mask VLAN priority */ 1584 fdirm |= IXGBE_FDIRM_VLANP; 1585 break; 1586 case 0xE000: 1587 /* mask VLAN ID only */ 1588 fdirm |= IXGBE_FDIRM_VLANID; 1589 fallthrough; 1590 case 0xEFFF: 1591 /* no VLAN fields masked */ 1592 break; 1593 default: 1594 hw_dbg(hw, " Error on VLAN mask\n"); 1595 return -EIO; 1596 } 1597 1598 switch ((__force u16)input_mask->formatted.flex_bytes & 0xFFFF) { 1599 case 0x0000: 1600 /* Mask Flex Bytes */ 1601 fdirm |= IXGBE_FDIRM_FLEX; 1602 fallthrough; 1603 case 0xFFFF: 1604 break; 1605 default: 1606 hw_dbg(hw, " Error on flexible byte mask\n"); 1607 return -EIO; 1608 } 1609 1610 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ 1611 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); 1612 1613 /* store the TCP/UDP port masks, bit reversed from port layout */ 1614 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask); 1615 1616 /* write both the same so that UDP and TCP use the same mask */ 1617 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); 1618 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); 1619 1620 /* also use it for SCTP */ 1621 switch (hw->mac.type) { 1622 case ixgbe_mac_X550: 1623 case ixgbe_mac_X550EM_x: 1624 case ixgbe_mac_x550em_a: 1625 case ixgbe_mac_e610: 1626 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm); 1627 break; 1628 default: 1629 break; 1630 } 1631 1632 /* store source and destination IP masks (big-endian) */ 1633 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 1634 ~input_mask->formatted.src_ip[0]); 1635 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 1636 ~input_mask->formatted.dst_ip[0]); 1637 1638 return 0; 1639 } 1640 1641 int ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 1642 union ixgbe_atr_input *input, 1643 u16 soft_id, u8 queue) 1644 { 1645 u32 fdirport, fdirvlan, fdirhash, fdircmd; 1646 int err; 1647 1648 /* currently IPv6 is not supported, must be programmed with 0 */ 1649 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), 1650 input->formatted.src_ip[0]); 1651 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), 1652 input->formatted.src_ip[1]); 1653 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), 1654 input->formatted.src_ip[2]); 1655 1656 /* record the source address (big-endian) */ 1657 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]); 1658 1659 /* record the first 32 bits of the destination address (big-endian) */ 1660 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]); 1661 1662 /* record source and destination port (little-endian)*/ 1663 fdirport = be16_to_cpu(input->formatted.dst_port); 1664 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT; 1665 fdirport |= be16_to_cpu(input->formatted.src_port); 1666 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); 1667 1668 /* record vlan (little-endian) and flex_bytes(big-endian) */ 1669 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes); 1670 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; 1671 fdirvlan |= ntohs(input->formatted.vlan_id); 1672 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); 1673 1674 /* configure FDIRHASH register */ 1675 fdirhash = (__force u32)input->formatted.bkt_hash; 1676 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1677 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1678 1679 /* 1680 * flush all previous writes to make certain registers are 1681 * programmed prior to issuing the command 1682 */ 1683 IXGBE_WRITE_FLUSH(hw); 1684 1685 /* configure FDIRCMD register */ 1686 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1687 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1688 if (queue == IXGBE_FDIR_DROP_QUEUE) 1689 fdircmd |= IXGBE_FDIRCMD_DROP; 1690 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1691 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1692 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT; 1693 1694 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); 1695 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1696 if (err) { 1697 hw_dbg(hw, "Flow Director command did not complete!\n"); 1698 return err; 1699 } 1700 1701 return 0; 1702 } 1703 1704 int ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 1705 union ixgbe_atr_input *input, 1706 u16 soft_id) 1707 { 1708 u32 fdirhash; 1709 u32 fdircmd; 1710 int err; 1711 1712 /* configure FDIRHASH register */ 1713 fdirhash = (__force u32)input->formatted.bkt_hash; 1714 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1715 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1716 1717 /* flush hash to HW */ 1718 IXGBE_WRITE_FLUSH(hw); 1719 1720 /* Query if filter is present */ 1721 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT); 1722 1723 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1724 if (err) { 1725 hw_dbg(hw, "Flow Director command did not complete!\n"); 1726 return err; 1727 } 1728 1729 /* if filter exists in hardware then remove it */ 1730 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) { 1731 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1732 IXGBE_WRITE_FLUSH(hw); 1733 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1734 IXGBE_FDIRCMD_CMD_REMOVE_FLOW); 1735 } 1736 1737 return 0; 1738 } 1739 1740 /** 1741 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 1742 * @hw: pointer to hardware structure 1743 * @reg: analog register to read 1744 * @val: read value 1745 * 1746 * Performs read operation to Omer analog register specified. 1747 **/ 1748 static int ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) 1749 { 1750 u32 core_ctl; 1751 1752 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | 1753 (reg << 8)); 1754 IXGBE_WRITE_FLUSH(hw); 1755 udelay(10); 1756 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); 1757 *val = (u8)core_ctl; 1758 1759 return 0; 1760 } 1761 1762 /** 1763 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register 1764 * @hw: pointer to hardware structure 1765 * @reg: atlas register to write 1766 * @val: value to write 1767 * 1768 * Performs write operation to Omer analog register specified. 1769 **/ 1770 static int ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) 1771 { 1772 u32 core_ctl; 1773 1774 core_ctl = (reg << 8) | val; 1775 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); 1776 IXGBE_WRITE_FLUSH(hw); 1777 udelay(10); 1778 1779 return 0; 1780 } 1781 1782 /** 1783 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx 1784 * @hw: pointer to hardware structure 1785 * 1786 * Starts the hardware using the generic start_hw function 1787 * and the generation start_hw function. 1788 * Then performs revision-specific operations, if any. 1789 **/ 1790 static int ixgbe_start_hw_82599(struct ixgbe_hw *hw) 1791 { 1792 int ret_val = 0; 1793 1794 ret_val = ixgbe_start_hw_generic(hw); 1795 if (ret_val) 1796 return ret_val; 1797 1798 ret_val = ixgbe_start_hw_gen2(hw); 1799 if (ret_val) 1800 return ret_val; 1801 1802 /* We need to run link autotry after the driver loads */ 1803 hw->mac.autotry_restart = true; 1804 1805 return ixgbe_verify_fw_version_82599(hw); 1806 } 1807 1808 /** 1809 * ixgbe_identify_phy_82599 - Get physical layer module 1810 * @hw: pointer to hardware structure 1811 * 1812 * Determines the physical layer module found on the current adapter. 1813 * If PHY already detected, maintains current PHY type in hw struct, 1814 * otherwise executes the PHY detection routine. 1815 **/ 1816 static int ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 1817 { 1818 int status; 1819 1820 /* Detect PHY if not unknown - returns success if already detected. */ 1821 status = ixgbe_identify_phy_generic(hw); 1822 if (status) { 1823 /* 82599 10GBASE-T requires an external PHY */ 1824 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) 1825 return status; 1826 status = ixgbe_identify_module_generic(hw); 1827 } 1828 1829 /* Set PHY type none if no PHY detected */ 1830 if (hw->phy.type == ixgbe_phy_unknown) { 1831 hw->phy.type = ixgbe_phy_none; 1832 status = 0; 1833 } 1834 1835 /* Return error if SFP module has been detected but is not supported */ 1836 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 1837 return -EOPNOTSUPP; 1838 1839 return status; 1840 } 1841 1842 /** 1843 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 1844 * @hw: pointer to hardware structure 1845 * @regval: register value to write to RXCTRL 1846 * 1847 * Enables the Rx DMA unit for 82599 1848 **/ 1849 static int ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) 1850 { 1851 /* 1852 * Workaround for 82599 silicon errata when enabling the Rx datapath. 1853 * If traffic is incoming before we enable the Rx unit, it could hang 1854 * the Rx DMA unit. Therefore, make sure the security engine is 1855 * completely disabled prior to enabling the Rx unit. 1856 */ 1857 hw->mac.ops.disable_rx_buff(hw); 1858 1859 if (regval & IXGBE_RXCTRL_RXEN) 1860 hw->mac.ops.enable_rx(hw); 1861 else 1862 hw->mac.ops.disable_rx(hw); 1863 1864 hw->mac.ops.enable_rx_buff(hw); 1865 1866 return 0; 1867 } 1868 1869 /** 1870 * ixgbe_verify_fw_version_82599 - verify fw version for 82599 1871 * @hw: pointer to hardware structure 1872 * 1873 * Verifies that installed the firmware version is 0.6 or higher 1874 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. 1875 * 1876 * Return: -EACCES if the FW is not present or if the FW version is 1877 * not supported. 1878 **/ 1879 static int ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 1880 { 1881 u16 fw_offset, fw_ptp_cfg_offset; 1882 int status = -EACCES; 1883 u16 fw_version = 0; 1884 u16 offset; 1885 1886 /* firmware check is only necessary for SFI devices */ 1887 if (hw->phy.media_type != ixgbe_media_type_fiber) 1888 return 0; 1889 1890 /* get the offset to the Firmware Module block */ 1891 offset = IXGBE_FW_PTR; 1892 if (hw->eeprom.ops.read(hw, offset, &fw_offset)) 1893 goto fw_version_err; 1894 1895 if (fw_offset == 0 || fw_offset == 0xFFFF) 1896 return -EACCES; 1897 1898 /* get the offset to the Pass Through Patch Configuration block */ 1899 offset = fw_offset + IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR; 1900 if (hw->eeprom.ops.read(hw, offset, &fw_ptp_cfg_offset)) 1901 goto fw_version_err; 1902 1903 if (fw_ptp_cfg_offset == 0 || fw_ptp_cfg_offset == 0xFFFF) 1904 return -EACCES; 1905 1906 /* get the firmware version */ 1907 offset = fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4; 1908 if (hw->eeprom.ops.read(hw, offset, &fw_version)) 1909 goto fw_version_err; 1910 1911 if (fw_version > 0x5) 1912 status = 0; 1913 1914 return status; 1915 1916 fw_version_err: 1917 hw_err(hw, "eeprom read at offset %d failed\n", offset); 1918 return -EACCES; 1919 } 1920 1921 /** 1922 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state. 1923 * @hw: pointer to hardware structure 1924 * 1925 * Returns true if the LESM FW module is present and enabled. Otherwise 1926 * returns false. Smart Speed must be disabled if LESM FW module is enabled. 1927 **/ 1928 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) 1929 { 1930 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state; 1931 int status; 1932 1933 /* get the offset to the Firmware Module block */ 1934 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 1935 1936 if (status || fw_offset == 0 || fw_offset == 0xFFFF) 1937 return false; 1938 1939 /* get the offset to the LESM Parameters block */ 1940 status = hw->eeprom.ops.read(hw, (fw_offset + 1941 IXGBE_FW_LESM_PARAMETERS_PTR), 1942 &fw_lesm_param_offset); 1943 1944 if (status || 1945 fw_lesm_param_offset == 0 || fw_lesm_param_offset == 0xFFFF) 1946 return false; 1947 1948 /* get the lesm state word */ 1949 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + 1950 IXGBE_FW_LESM_STATE_1), 1951 &fw_lesm_state); 1952 1953 if (!status && (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) 1954 return true; 1955 1956 return false; 1957 } 1958 1959 /** 1960 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using 1961 * fastest available method 1962 * 1963 * @hw: pointer to hardware structure 1964 * @offset: offset of word in EEPROM to read 1965 * @words: number of words 1966 * @data: word(s) read from the EEPROM 1967 * 1968 * Retrieves 16 bit word(s) read from EEPROM 1969 **/ 1970 static int ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, 1971 u16 words, u16 *data) 1972 { 1973 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1974 1975 /* If EEPROM is detected and can be addressed using 14 bits, 1976 * use EERD otherwise use bit bang 1977 */ 1978 if (eeprom->type == ixgbe_eeprom_spi && 1979 offset + (words - 1) <= IXGBE_EERD_MAX_ADDR) 1980 return ixgbe_read_eerd_buffer_generic(hw, offset, words, data); 1981 1982 return ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset, words, 1983 data); 1984 } 1985 1986 /** 1987 * ixgbe_read_eeprom_82599 - Read EEPROM word using 1988 * fastest available method 1989 * 1990 * @hw: pointer to hardware structure 1991 * @offset: offset of word in the EEPROM to read 1992 * @data: word read from the EEPROM 1993 * 1994 * Reads a 16 bit word from the EEPROM 1995 **/ 1996 static int ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 1997 u16 offset, u16 *data) 1998 { 1999 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2000 2001 /* 2002 * If EEPROM is detected and can be addressed using 14 bits, 2003 * use EERD otherwise use bit bang 2004 */ 2005 if (eeprom->type == ixgbe_eeprom_spi && offset <= IXGBE_EERD_MAX_ADDR) 2006 return ixgbe_read_eerd_generic(hw, offset, data); 2007 2008 return ixgbe_read_eeprom_bit_bang_generic(hw, offset, data); 2009 } 2010 2011 /** 2012 * ixgbe_reset_pipeline_82599 - perform pipeline reset 2013 * 2014 * @hw: pointer to hardware structure 2015 * 2016 * Reset pipeline by asserting Restart_AN together with LMS change to ensure 2017 * full pipeline reset. Note - We must hold the SW/FW semaphore before writing 2018 * to AUTOC, so this function assumes the semaphore is held. 2019 **/ 2020 static int ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw) 2021 { 2022 u32 i, autoc_reg, autoc2_reg; 2023 u32 anlp1_reg = 0; 2024 int ret_val; 2025 2026 /* Enable link if disabled in NVM */ 2027 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 2028 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 2029 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 2030 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 2031 IXGBE_WRITE_FLUSH(hw); 2032 } 2033 2034 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2035 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2036 2037 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */ 2038 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, 2039 autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT)); 2040 2041 /* Wait for AN to leave state 0 */ 2042 for (i = 0; i < 10; i++) { 2043 usleep_range(4000, 8000); 2044 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2045 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK) 2046 break; 2047 } 2048 2049 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) { 2050 hw_dbg(hw, "auto negotiation not completed\n"); 2051 ret_val = -EIO; 2052 goto reset_pipeline_out; 2053 } 2054 2055 ret_val = 0; 2056 2057 reset_pipeline_out: 2058 /* Write AUTOC register with original LMS field and Restart_AN */ 2059 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2060 IXGBE_WRITE_FLUSH(hw); 2061 2062 return ret_val; 2063 } 2064 2065 /** 2066 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C 2067 * @hw: pointer to hardware structure 2068 * @byte_offset: byte offset to read 2069 * @dev_addr: address to read from 2070 * @data: value read 2071 * 2072 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2073 * a specified device address. 2074 **/ 2075 static int ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 2076 u8 dev_addr, u8 *data) 2077 { 2078 s32 timeout = 200; 2079 int status; 2080 u32 esdp; 2081 2082 if (hw->phy.qsfp_shared_i2c_bus == true) { 2083 /* Acquire I2C bus ownership. */ 2084 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2085 esdp |= IXGBE_ESDP_SDP0; 2086 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2087 IXGBE_WRITE_FLUSH(hw); 2088 2089 while (timeout) { 2090 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2091 if (esdp & IXGBE_ESDP_SDP1) 2092 break; 2093 2094 usleep_range(5000, 10000); 2095 timeout--; 2096 } 2097 2098 if (!timeout) { 2099 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n"); 2100 status = -EIO; 2101 goto release_i2c_access; 2102 } 2103 } 2104 2105 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data); 2106 2107 release_i2c_access: 2108 if (hw->phy.qsfp_shared_i2c_bus == true) { 2109 /* Release I2C bus ownership. */ 2110 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2111 esdp &= ~IXGBE_ESDP_SDP0; 2112 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2113 IXGBE_WRITE_FLUSH(hw); 2114 } 2115 2116 return status; 2117 } 2118 2119 /** 2120 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C 2121 * @hw: pointer to hardware structure 2122 * @byte_offset: byte offset to write 2123 * @dev_addr: address to write to 2124 * @data: value to write 2125 * 2126 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2127 * a specified device address. 2128 **/ 2129 static int ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 2130 u8 dev_addr, u8 data) 2131 { 2132 s32 timeout = 200; 2133 int status; 2134 u32 esdp; 2135 2136 if (hw->phy.qsfp_shared_i2c_bus == true) { 2137 /* Acquire I2C bus ownership. */ 2138 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2139 esdp |= IXGBE_ESDP_SDP0; 2140 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2141 IXGBE_WRITE_FLUSH(hw); 2142 2143 while (timeout) { 2144 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2145 if (esdp & IXGBE_ESDP_SDP1) 2146 break; 2147 2148 usleep_range(5000, 10000); 2149 timeout--; 2150 } 2151 2152 if (!timeout) { 2153 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n"); 2154 status = -EIO; 2155 goto release_i2c_access; 2156 } 2157 } 2158 2159 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data); 2160 2161 release_i2c_access: 2162 if (hw->phy.qsfp_shared_i2c_bus == true) { 2163 /* Release I2C bus ownership. */ 2164 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2165 esdp &= ~IXGBE_ESDP_SDP0; 2166 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2167 IXGBE_WRITE_FLUSH(hw); 2168 } 2169 2170 return status; 2171 } 2172 2173 static const struct ixgbe_mac_operations mac_ops_82599 = { 2174 .init_hw = &ixgbe_init_hw_generic, 2175 .reset_hw = &ixgbe_reset_hw_82599, 2176 .start_hw = &ixgbe_start_hw_82599, 2177 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, 2178 .get_media_type = &ixgbe_get_media_type_82599, 2179 .enable_rx_dma = &ixgbe_enable_rx_dma_82599, 2180 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, 2181 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, 2182 .get_mac_addr = &ixgbe_get_mac_addr_generic, 2183 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 2184 .get_device_caps = &ixgbe_get_device_caps_generic, 2185 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 2186 .stop_adapter = &ixgbe_stop_adapter_generic, 2187 .get_bus_info = &ixgbe_get_bus_info_generic, 2188 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, 2189 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599, 2190 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599, 2191 .stop_link_on_d3 = &ixgbe_stop_mac_link_on_d3_82599, 2192 .setup_link = &ixgbe_setup_mac_link_82599, 2193 .set_rxpba = &ixgbe_set_rxpba_generic, 2194 .check_link = &ixgbe_check_mac_link_generic, 2195 .get_link_capabilities = &ixgbe_get_link_capabilities_82599, 2196 .led_on = &ixgbe_led_on_generic, 2197 .led_off = &ixgbe_led_off_generic, 2198 .init_led_link_act = ixgbe_init_led_link_act_generic, 2199 .blink_led_start = &ixgbe_blink_led_start_generic, 2200 .blink_led_stop = &ixgbe_blink_led_stop_generic, 2201 .set_rar = &ixgbe_set_rar_generic, 2202 .clear_rar = &ixgbe_clear_rar_generic, 2203 .set_vmdq = &ixgbe_set_vmdq_generic, 2204 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, 2205 .clear_vmdq = &ixgbe_clear_vmdq_generic, 2206 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 2207 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 2208 .enable_mc = &ixgbe_enable_mc_generic, 2209 .disable_mc = &ixgbe_disable_mc_generic, 2210 .clear_vfta = &ixgbe_clear_vfta_generic, 2211 .set_vfta = &ixgbe_set_vfta_generic, 2212 .fc_enable = &ixgbe_fc_enable_generic, 2213 .setup_fc = ixgbe_setup_fc_generic, 2214 .fc_autoneg = ixgbe_fc_autoneg, 2215 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic, 2216 .init_uta_tables = &ixgbe_init_uta_tables_generic, 2217 .setup_sfp = &ixgbe_setup_sfp_modules_82599, 2218 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, 2219 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, 2220 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync, 2221 .release_swfw_sync = &ixgbe_release_swfw_sync, 2222 .init_swfw_sync = NULL, 2223 .get_thermal_sensor_data = &ixgbe_get_thermal_sensor_data_generic, 2224 .init_thermal_sensor_thresh = &ixgbe_init_thermal_sensor_thresh_generic, 2225 .prot_autoc_read = &prot_autoc_read_82599, 2226 .prot_autoc_write = &prot_autoc_write_82599, 2227 .enable_rx = &ixgbe_enable_rx_generic, 2228 .disable_rx = &ixgbe_disable_rx_generic, 2229 }; 2230 2231 static const struct ixgbe_eeprom_operations eeprom_ops_82599 = { 2232 .init_params = &ixgbe_init_eeprom_params_generic, 2233 .read = &ixgbe_read_eeprom_82599, 2234 .read_buffer = &ixgbe_read_eeprom_buffer_82599, 2235 .write = &ixgbe_write_eeprom_generic, 2236 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic, 2237 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic, 2238 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, 2239 .update_checksum = &ixgbe_update_eeprom_checksum_generic, 2240 .read_pba_string = &ixgbe_read_pba_string_generic, 2241 }; 2242 2243 static const struct ixgbe_phy_operations phy_ops_82599 = { 2244 .identify = &ixgbe_identify_phy_82599, 2245 .identify_sfp = &ixgbe_identify_module_generic, 2246 .init = &ixgbe_init_phy_ops_82599, 2247 .reset = &ixgbe_reset_phy_generic, 2248 .read_reg = &ixgbe_read_phy_reg_generic, 2249 .write_reg = &ixgbe_write_phy_reg_generic, 2250 .setup_link = &ixgbe_setup_phy_link_generic, 2251 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, 2252 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, 2253 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, 2254 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, 2255 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, 2256 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, 2257 .check_overtemp = &ixgbe_tn_check_overtemp, 2258 }; 2259 2260 const struct ixgbe_info ixgbe_82599_info = { 2261 .mac = ixgbe_mac_82599EB, 2262 .get_invariants = &ixgbe_get_invariants_82599, 2263 .mac_ops = &mac_ops_82599, 2264 .eeprom_ops = &eeprom_ops_82599, 2265 .phy_ops = &phy_ops_82599, 2266 .mbx_ops = &mbx_ops_generic, 2267 .mvals = ixgbe_mvals_8259X, 2268 }; 2269