1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #include <linux/pci.h> 29 #include <linux/delay.h> 30 #include <linux/sched.h> 31 32 #include "ixgbe.h" 33 #include "ixgbe_phy.h" 34 #include "ixgbe_mbx.h" 35 36 #define IXGBE_82599_MAX_TX_QUEUES 128 37 #define IXGBE_82599_MAX_RX_QUEUES 128 38 #define IXGBE_82599_RAR_ENTRIES 128 39 #define IXGBE_82599_MC_TBL_SIZE 128 40 #define IXGBE_82599_VFT_TBL_SIZE 128 41 #define IXGBE_82599_RX_PB_SIZE 512 42 43 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 44 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 45 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 46 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 47 ixgbe_link_speed speed, 48 bool autoneg, 49 bool autoneg_wait_to_complete); 50 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 51 ixgbe_link_speed speed, 52 bool autoneg, 53 bool autoneg_wait_to_complete); 54 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 55 bool autoneg_wait_to_complete); 56 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 57 ixgbe_link_speed speed, 58 bool autoneg, 59 bool autoneg_wait_to_complete); 60 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 61 ixgbe_link_speed speed, 62 bool autoneg, 63 bool autoneg_wait_to_complete); 64 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 65 66 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 67 { 68 struct ixgbe_mac_info *mac = &hw->mac; 69 70 /* enable the laser control functions for SFP+ fiber */ 71 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) { 72 mac->ops.disable_tx_laser = 73 &ixgbe_disable_tx_laser_multispeed_fiber; 74 mac->ops.enable_tx_laser = 75 &ixgbe_enable_tx_laser_multispeed_fiber; 76 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; 77 } else { 78 mac->ops.disable_tx_laser = NULL; 79 mac->ops.enable_tx_laser = NULL; 80 mac->ops.flap_tx_laser = NULL; 81 } 82 83 if (hw->phy.multispeed_fiber) { 84 /* Set up dual speed SFP+ support */ 85 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; 86 } else { 87 if ((mac->ops.get_media_type(hw) == 88 ixgbe_media_type_backplane) && 89 (hw->phy.smart_speed == ixgbe_smart_speed_auto || 90 hw->phy.smart_speed == ixgbe_smart_speed_on) && 91 !ixgbe_verify_lesm_fw_enabled_82599(hw)) 92 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; 93 else 94 mac->ops.setup_link = &ixgbe_setup_mac_link_82599; 95 } 96 } 97 98 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 99 { 100 s32 ret_val = 0; 101 u16 list_offset, data_offset, data_value; 102 bool got_lock = false; 103 104 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 105 ixgbe_init_mac_link_ops_82599(hw); 106 107 hw->phy.ops.reset = NULL; 108 109 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 110 &data_offset); 111 if (ret_val != 0) 112 goto setup_sfp_out; 113 114 /* PHY config will finish before releasing the semaphore */ 115 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 116 IXGBE_GSSR_MAC_CSR_SM); 117 if (ret_val != 0) { 118 ret_val = IXGBE_ERR_SWFW_SYNC; 119 goto setup_sfp_out; 120 } 121 122 hw->eeprom.ops.read(hw, ++data_offset, &data_value); 123 while (data_value != 0xffff) { 124 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); 125 IXGBE_WRITE_FLUSH(hw); 126 hw->eeprom.ops.read(hw, ++data_offset, &data_value); 127 } 128 129 /* Release the semaphore */ 130 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 131 /* 132 * Delay obtaining semaphore again to allow FW access, 133 * semaphore_delay is in ms usleep_range needs us. 134 */ 135 usleep_range(hw->eeprom.semaphore_delay * 1000, 136 hw->eeprom.semaphore_delay * 2000); 137 138 /* Need SW/FW semaphore around AUTOC writes if LESM on, 139 * likewise reset_pipeline requires lock as it also writes 140 * AUTOC. 141 */ 142 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 143 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 144 IXGBE_GSSR_MAC_CSR_SM); 145 if (ret_val) 146 goto setup_sfp_out; 147 148 got_lock = true; 149 } 150 151 /* Restart DSP and set SFI mode */ 152 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw, 153 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL)); 154 155 ret_val = ixgbe_reset_pipeline_82599(hw); 156 157 if (got_lock) { 158 hw->mac.ops.release_swfw_sync(hw, 159 IXGBE_GSSR_MAC_CSR_SM); 160 got_lock = false; 161 } 162 163 if (ret_val) { 164 hw_dbg(hw, " sfp module setup not complete\n"); 165 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 166 goto setup_sfp_out; 167 } 168 } 169 170 setup_sfp_out: 171 return ret_val; 172 } 173 174 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw) 175 { 176 struct ixgbe_mac_info *mac = &hw->mac; 177 178 ixgbe_init_mac_link_ops_82599(hw); 179 180 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; 181 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; 182 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; 183 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; 184 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; 185 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 186 187 return 0; 188 } 189 190 /** 191 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init 192 * @hw: pointer to hardware structure 193 * 194 * Initialize any function pointers that were not able to be 195 * set during get_invariants because the PHY/SFP type was 196 * not known. Perform the SFP init if necessary. 197 * 198 **/ 199 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 200 { 201 struct ixgbe_mac_info *mac = &hw->mac; 202 struct ixgbe_phy_info *phy = &hw->phy; 203 s32 ret_val = 0; 204 205 /* Identify the PHY or SFP module */ 206 ret_val = phy->ops.identify(hw); 207 208 /* Setup function pointers based on detected SFP module and speeds */ 209 ixgbe_init_mac_link_ops_82599(hw); 210 211 /* If copper media, overwrite with copper function pointers */ 212 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 213 mac->ops.setup_link = &ixgbe_setup_copper_link_82599; 214 mac->ops.get_link_capabilities = 215 &ixgbe_get_copper_link_capabilities_generic; 216 } 217 218 /* Set necessary function pointers based on phy type */ 219 switch (hw->phy.type) { 220 case ixgbe_phy_tn: 221 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 222 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; 223 phy->ops.get_firmware_version = 224 &ixgbe_get_phy_firmware_version_tnx; 225 break; 226 default: 227 break; 228 } 229 230 return ret_val; 231 } 232 233 /** 234 * ixgbe_get_link_capabilities_82599 - Determines link capabilities 235 * @hw: pointer to hardware structure 236 * @speed: pointer to link speed 237 * @negotiation: true when autoneg or autotry is enabled 238 * 239 * Determines the link capabilities by reading the AUTOC register. 240 **/ 241 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 242 ixgbe_link_speed *speed, 243 bool *negotiation) 244 { 245 s32 status = 0; 246 u32 autoc = 0; 247 248 /* Determine 1G link capabilities off of SFP+ type */ 249 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 250 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 251 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 252 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 253 *speed = IXGBE_LINK_SPEED_1GB_FULL; 254 *negotiation = true; 255 goto out; 256 } 257 258 /* 259 * Determine link capabilities based on the stored value of AUTOC, 260 * which represents EEPROM defaults. If AUTOC value has not been 261 * stored, use the current register value. 262 */ 263 if (hw->mac.orig_link_settings_stored) 264 autoc = hw->mac.orig_autoc; 265 else 266 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 267 268 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 269 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 270 *speed = IXGBE_LINK_SPEED_1GB_FULL; 271 *negotiation = false; 272 break; 273 274 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 275 *speed = IXGBE_LINK_SPEED_10GB_FULL; 276 *negotiation = false; 277 break; 278 279 case IXGBE_AUTOC_LMS_1G_AN: 280 *speed = IXGBE_LINK_SPEED_1GB_FULL; 281 *negotiation = true; 282 break; 283 284 case IXGBE_AUTOC_LMS_10G_SERIAL: 285 *speed = IXGBE_LINK_SPEED_10GB_FULL; 286 *negotiation = false; 287 break; 288 289 case IXGBE_AUTOC_LMS_KX4_KX_KR: 290 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 291 *speed = IXGBE_LINK_SPEED_UNKNOWN; 292 if (autoc & IXGBE_AUTOC_KR_SUPP) 293 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 294 if (autoc & IXGBE_AUTOC_KX4_SUPP) 295 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 296 if (autoc & IXGBE_AUTOC_KX_SUPP) 297 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 298 *negotiation = true; 299 break; 300 301 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: 302 *speed = IXGBE_LINK_SPEED_100_FULL; 303 if (autoc & IXGBE_AUTOC_KR_SUPP) 304 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 305 if (autoc & IXGBE_AUTOC_KX4_SUPP) 306 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 307 if (autoc & IXGBE_AUTOC_KX_SUPP) 308 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 309 *negotiation = true; 310 break; 311 312 case IXGBE_AUTOC_LMS_SGMII_1G_100M: 313 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; 314 *negotiation = false; 315 break; 316 317 default: 318 status = IXGBE_ERR_LINK_SETUP; 319 goto out; 320 break; 321 } 322 323 if (hw->phy.multispeed_fiber) { 324 *speed |= IXGBE_LINK_SPEED_10GB_FULL | 325 IXGBE_LINK_SPEED_1GB_FULL; 326 *negotiation = true; 327 } 328 329 out: 330 return status; 331 } 332 333 /** 334 * ixgbe_get_media_type_82599 - Get media type 335 * @hw: pointer to hardware structure 336 * 337 * Returns the media type (fiber, copper, backplane) 338 **/ 339 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 340 { 341 enum ixgbe_media_type media_type; 342 343 /* Detect if there is a copper PHY attached. */ 344 switch (hw->phy.type) { 345 case ixgbe_phy_cu_unknown: 346 case ixgbe_phy_tn: 347 media_type = ixgbe_media_type_copper; 348 goto out; 349 default: 350 break; 351 } 352 353 switch (hw->device_id) { 354 case IXGBE_DEV_ID_82599_KX4: 355 case IXGBE_DEV_ID_82599_KX4_MEZZ: 356 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 357 case IXGBE_DEV_ID_82599_KR: 358 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 359 case IXGBE_DEV_ID_82599_XAUI_LOM: 360 /* Default device ID is mezzanine card KX/KX4 */ 361 media_type = ixgbe_media_type_backplane; 362 break; 363 case IXGBE_DEV_ID_82599_SFP: 364 case IXGBE_DEV_ID_82599_SFP_FCOE: 365 case IXGBE_DEV_ID_82599_SFP_EM: 366 case IXGBE_DEV_ID_82599_SFP_SF2: 367 case IXGBE_DEV_ID_82599_SFP_SF_QP: 368 case IXGBE_DEV_ID_82599EN_SFP: 369 media_type = ixgbe_media_type_fiber; 370 break; 371 case IXGBE_DEV_ID_82599_CX4: 372 media_type = ixgbe_media_type_cx4; 373 break; 374 case IXGBE_DEV_ID_82599_T3_LOM: 375 media_type = ixgbe_media_type_copper; 376 break; 377 case IXGBE_DEV_ID_82599_LS: 378 media_type = ixgbe_media_type_fiber_lco; 379 break; 380 default: 381 media_type = ixgbe_media_type_unknown; 382 break; 383 } 384 out: 385 return media_type; 386 } 387 388 /** 389 * ixgbe_start_mac_link_82599 - Setup MAC link settings 390 * @hw: pointer to hardware structure 391 * @autoneg_wait_to_complete: true when waiting for completion is needed 392 * 393 * Configures link settings based on values in the ixgbe_hw struct. 394 * Restarts the link. Performs autonegotiation if needed. 395 **/ 396 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 397 bool autoneg_wait_to_complete) 398 { 399 u32 autoc_reg; 400 u32 links_reg; 401 u32 i; 402 s32 status = 0; 403 bool got_lock = false; 404 405 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 406 status = hw->mac.ops.acquire_swfw_sync(hw, 407 IXGBE_GSSR_MAC_CSR_SM); 408 if (status) 409 goto out; 410 411 got_lock = true; 412 } 413 414 /* Restart link */ 415 ixgbe_reset_pipeline_82599(hw); 416 417 if (got_lock) 418 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 419 420 /* Only poll for autoneg to complete if specified to do so */ 421 if (autoneg_wait_to_complete) { 422 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 423 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 424 IXGBE_AUTOC_LMS_KX4_KX_KR || 425 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 426 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 427 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 428 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 429 links_reg = 0; /* Just in case Autoneg time = 0 */ 430 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 431 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 432 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 433 break; 434 msleep(100); 435 } 436 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 437 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 438 hw_dbg(hw, "Autoneg did not complete.\n"); 439 } 440 } 441 } 442 443 /* Add delay to filter out noises during initial link setup */ 444 msleep(50); 445 446 out: 447 return status; 448 } 449 450 /** 451 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser 452 * @hw: pointer to hardware structure 453 * 454 * The base drivers may require better control over SFP+ module 455 * PHY states. This includes selectively shutting down the Tx 456 * laser on the PHY, effectively halting physical link. 457 **/ 458 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 459 { 460 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 461 462 /* Disable tx laser; allow 100us to go dark per spec */ 463 esdp_reg |= IXGBE_ESDP_SDP3; 464 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 465 IXGBE_WRITE_FLUSH(hw); 466 udelay(100); 467 } 468 469 /** 470 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser 471 * @hw: pointer to hardware structure 472 * 473 * The base drivers may require better control over SFP+ module 474 * PHY states. This includes selectively turning on the Tx 475 * laser on the PHY, effectively starting physical link. 476 **/ 477 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 478 { 479 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 480 481 /* Enable tx laser; allow 100ms to light up */ 482 esdp_reg &= ~IXGBE_ESDP_SDP3; 483 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 484 IXGBE_WRITE_FLUSH(hw); 485 msleep(100); 486 } 487 488 /** 489 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser 490 * @hw: pointer to hardware structure 491 * 492 * When the driver changes the link speeds that it can support, 493 * it sets autotry_restart to true to indicate that we need to 494 * initiate a new autotry session with the link partner. To do 495 * so, we set the speed then disable and re-enable the tx laser, to 496 * alert the link partner that it also needs to restart autotry on its 497 * end. This is consistent with true clause 37 autoneg, which also 498 * involves a loss of signal. 499 **/ 500 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 501 { 502 if (hw->mac.autotry_restart) { 503 ixgbe_disable_tx_laser_multispeed_fiber(hw); 504 ixgbe_enable_tx_laser_multispeed_fiber(hw); 505 hw->mac.autotry_restart = false; 506 } 507 } 508 509 /** 510 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 511 * @hw: pointer to hardware structure 512 * @speed: new link speed 513 * @autoneg: true if autonegotiation enabled 514 * @autoneg_wait_to_complete: true when waiting for completion is needed 515 * 516 * Set the link speed in the AUTOC register and restarts link. 517 **/ 518 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 519 ixgbe_link_speed speed, 520 bool autoneg, 521 bool autoneg_wait_to_complete) 522 { 523 s32 status = 0; 524 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 525 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 526 u32 speedcnt = 0; 527 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 528 u32 i = 0; 529 bool link_up = false; 530 bool negotiation; 531 532 /* Mask off requested but non-supported speeds */ 533 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, 534 &negotiation); 535 if (status != 0) 536 return status; 537 538 speed &= link_speed; 539 540 /* 541 * Try each speed one by one, highest priority first. We do this in 542 * software because 10gb fiber doesn't support speed autonegotiation. 543 */ 544 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 545 speedcnt++; 546 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 547 548 /* If we already have link at this speed, just jump out */ 549 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 550 false); 551 if (status != 0) 552 return status; 553 554 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up) 555 goto out; 556 557 /* Set the module link speed */ 558 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); 559 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 560 IXGBE_WRITE_FLUSH(hw); 561 562 /* Allow module to change analog characteristics (1G->10G) */ 563 msleep(40); 564 565 status = ixgbe_setup_mac_link_82599(hw, 566 IXGBE_LINK_SPEED_10GB_FULL, 567 autoneg, 568 autoneg_wait_to_complete); 569 if (status != 0) 570 return status; 571 572 /* Flap the tx laser if it has not already been done */ 573 hw->mac.ops.flap_tx_laser(hw); 574 575 /* 576 * Wait for the controller to acquire link. Per IEEE 802.3ap, 577 * Section 73.10.2, we may have to wait up to 500ms if KR is 578 * attempted. 82599 uses the same timing for 10g SFI. 579 */ 580 for (i = 0; i < 5; i++) { 581 /* Wait for the link partner to also set speed */ 582 msleep(100); 583 584 /* If we have link, just jump out */ 585 status = hw->mac.ops.check_link(hw, &link_speed, 586 &link_up, false); 587 if (status != 0) 588 return status; 589 590 if (link_up) 591 goto out; 592 } 593 } 594 595 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 596 speedcnt++; 597 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 598 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 599 600 /* If we already have link at this speed, just jump out */ 601 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 602 false); 603 if (status != 0) 604 return status; 605 606 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up) 607 goto out; 608 609 /* Set the module link speed */ 610 esdp_reg &= ~IXGBE_ESDP_SDP5; 611 esdp_reg |= IXGBE_ESDP_SDP5_DIR; 612 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 613 IXGBE_WRITE_FLUSH(hw); 614 615 /* Allow module to change analog characteristics (10G->1G) */ 616 msleep(40); 617 618 status = ixgbe_setup_mac_link_82599(hw, 619 IXGBE_LINK_SPEED_1GB_FULL, 620 autoneg, 621 autoneg_wait_to_complete); 622 if (status != 0) 623 return status; 624 625 /* Flap the tx laser if it has not already been done */ 626 hw->mac.ops.flap_tx_laser(hw); 627 628 /* Wait for the link partner to also set speed */ 629 msleep(100); 630 631 /* If we have link, just jump out */ 632 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 633 false); 634 if (status != 0) 635 return status; 636 637 if (link_up) 638 goto out; 639 } 640 641 /* 642 * We didn't get link. Configure back to the highest speed we tried, 643 * (if there was more than one). We call ourselves back with just the 644 * single highest speed that the user requested. 645 */ 646 if (speedcnt > 1) 647 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 648 highest_link_speed, 649 autoneg, 650 autoneg_wait_to_complete); 651 652 out: 653 /* Set autoneg_advertised value based on input link speed */ 654 hw->phy.autoneg_advertised = 0; 655 656 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 657 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 658 659 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 660 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 661 662 return status; 663 } 664 665 /** 666 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed 667 * @hw: pointer to hardware structure 668 * @speed: new link speed 669 * @autoneg: true if autonegotiation enabled 670 * @autoneg_wait_to_complete: true when waiting for completion is needed 671 * 672 * Implements the Intel SmartSpeed algorithm. 673 **/ 674 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 675 ixgbe_link_speed speed, bool autoneg, 676 bool autoneg_wait_to_complete) 677 { 678 s32 status = 0; 679 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 680 s32 i, j; 681 bool link_up = false; 682 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 683 684 /* Set autoneg_advertised value based on input link speed */ 685 hw->phy.autoneg_advertised = 0; 686 687 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 688 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 689 690 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 691 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 692 693 if (speed & IXGBE_LINK_SPEED_100_FULL) 694 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 695 696 /* 697 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the 698 * autoneg advertisement if link is unable to be established at the 699 * highest negotiated rate. This can sometimes happen due to integrity 700 * issues with the physical media connection. 701 */ 702 703 /* First, try to get link with full advertisement */ 704 hw->phy.smart_speed_active = false; 705 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { 706 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 707 autoneg_wait_to_complete); 708 if (status != 0) 709 goto out; 710 711 /* 712 * Wait for the controller to acquire link. Per IEEE 802.3ap, 713 * Section 73.10.2, we may have to wait up to 500ms if KR is 714 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per 715 * Table 9 in the AN MAS. 716 */ 717 for (i = 0; i < 5; i++) { 718 mdelay(100); 719 720 /* If we have link, just jump out */ 721 status = hw->mac.ops.check_link(hw, &link_speed, 722 &link_up, false); 723 if (status != 0) 724 goto out; 725 726 if (link_up) 727 goto out; 728 } 729 } 730 731 /* 732 * We didn't get link. If we advertised KR plus one of KX4/KX 733 * (or BX4/BX), then disable KR and try again. 734 */ 735 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || 736 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) 737 goto out; 738 739 /* Turn SmartSpeed on to disable KR support */ 740 hw->phy.smart_speed_active = true; 741 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 742 autoneg_wait_to_complete); 743 if (status != 0) 744 goto out; 745 746 /* 747 * Wait for the controller to acquire link. 600ms will allow for 748 * the AN link_fail_inhibit_timer as well for multiple cycles of 749 * parallel detect, both 10g and 1g. This allows for the maximum 750 * connect attempts as defined in the AN MAS table 73-7. 751 */ 752 for (i = 0; i < 6; i++) { 753 mdelay(100); 754 755 /* If we have link, just jump out */ 756 status = hw->mac.ops.check_link(hw, &link_speed, 757 &link_up, false); 758 if (status != 0) 759 goto out; 760 761 if (link_up) 762 goto out; 763 } 764 765 /* We didn't get link. Turn SmartSpeed back off. */ 766 hw->phy.smart_speed_active = false; 767 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 768 autoneg_wait_to_complete); 769 770 out: 771 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) 772 hw_dbg(hw, "Smartspeed has downgraded the link speed from " 773 "the maximum advertised\n"); 774 return status; 775 } 776 777 /** 778 * ixgbe_setup_mac_link_82599 - Set MAC link speed 779 * @hw: pointer to hardware structure 780 * @speed: new link speed 781 * @autoneg: true if autonegotiation enabled 782 * @autoneg_wait_to_complete: true when waiting for completion is needed 783 * 784 * Set the link speed in the AUTOC register and restarts link. 785 **/ 786 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 787 ixgbe_link_speed speed, bool autoneg, 788 bool autoneg_wait_to_complete) 789 { 790 s32 status = 0; 791 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 792 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 793 u32 start_autoc = autoc; 794 u32 orig_autoc = 0; 795 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 796 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 797 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 798 u32 links_reg; 799 u32 i; 800 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 801 bool got_lock = false; 802 803 /* Check to see if speed passed in is supported. */ 804 status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities, 805 &autoneg); 806 if (status != 0) 807 goto out; 808 809 speed &= link_capabilities; 810 811 if (speed == IXGBE_LINK_SPEED_UNKNOWN) { 812 status = IXGBE_ERR_LINK_SETUP; 813 goto out; 814 } 815 816 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ 817 if (hw->mac.orig_link_settings_stored) 818 orig_autoc = hw->mac.orig_autoc; 819 else 820 orig_autoc = autoc; 821 822 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 823 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 824 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 825 /* Set KX4/KX/KR support according to speed requested */ 826 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); 827 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 828 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) 829 autoc |= IXGBE_AUTOC_KX4_SUPP; 830 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && 831 (hw->phy.smart_speed_active == false)) 832 autoc |= IXGBE_AUTOC_KR_SUPP; 833 } 834 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 835 autoc |= IXGBE_AUTOC_KX_SUPP; 836 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && 837 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || 838 link_mode == IXGBE_AUTOC_LMS_1G_AN)) { 839 /* Switch from 1G SFI to 10G SFI if requested */ 840 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 841 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { 842 autoc &= ~IXGBE_AUTOC_LMS_MASK; 843 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; 844 } 845 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && 846 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { 847 /* Switch from 10G SFI to 1G SFI if requested */ 848 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 849 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { 850 autoc &= ~IXGBE_AUTOC_LMS_MASK; 851 if (autoneg) 852 autoc |= IXGBE_AUTOC_LMS_1G_AN; 853 else 854 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 855 } 856 } 857 858 if (autoc != start_autoc) { 859 /* Need SW/FW semaphore around AUTOC writes if LESM is on, 860 * likewise reset_pipeline requires us to hold this lock as 861 * it also writes to AUTOC. 862 */ 863 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 864 status = hw->mac.ops.acquire_swfw_sync(hw, 865 IXGBE_GSSR_MAC_CSR_SM); 866 if (status != 0) 867 goto out; 868 869 got_lock = true; 870 } 871 872 /* Restart link */ 873 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 874 ixgbe_reset_pipeline_82599(hw); 875 876 if (got_lock) 877 hw->mac.ops.release_swfw_sync(hw, 878 IXGBE_GSSR_MAC_CSR_SM); 879 880 /* Only poll for autoneg to complete if specified to do so */ 881 if (autoneg_wait_to_complete) { 882 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 883 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 884 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 885 links_reg = 0; /*Just in case Autoneg time=0*/ 886 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 887 links_reg = 888 IXGBE_READ_REG(hw, IXGBE_LINKS); 889 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 890 break; 891 msleep(100); 892 } 893 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 894 status = 895 IXGBE_ERR_AUTONEG_NOT_COMPLETE; 896 hw_dbg(hw, "Autoneg did not " 897 "complete.\n"); 898 } 899 } 900 } 901 902 /* Add delay to filter out noises during initial link setup */ 903 msleep(50); 904 } 905 906 out: 907 return status; 908 } 909 910 /** 911 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field 912 * @hw: pointer to hardware structure 913 * @speed: new link speed 914 * @autoneg: true if autonegotiation enabled 915 * @autoneg_wait_to_complete: true if waiting is needed to complete 916 * 917 * Restarts link on PHY and MAC based on settings passed in. 918 **/ 919 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 920 ixgbe_link_speed speed, 921 bool autoneg, 922 bool autoneg_wait_to_complete) 923 { 924 s32 status; 925 926 /* Setup the PHY according to input speed */ 927 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 928 autoneg_wait_to_complete); 929 /* Set up MAC */ 930 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); 931 932 return status; 933 } 934 935 /** 936 * ixgbe_reset_hw_82599 - Perform hardware reset 937 * @hw: pointer to hardware structure 938 * 939 * Resets the hardware by resetting the transmit and receive units, masks 940 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 941 * reset. 942 **/ 943 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 944 { 945 ixgbe_link_speed link_speed; 946 s32 status; 947 u32 ctrl, i, autoc, autoc2; 948 bool link_up = false; 949 950 /* Call adapter stop to disable tx/rx and clear interrupts */ 951 status = hw->mac.ops.stop_adapter(hw); 952 if (status != 0) 953 goto reset_hw_out; 954 955 /* flush pending Tx transactions */ 956 ixgbe_clear_tx_pending(hw); 957 958 /* PHY ops must be identified and initialized prior to reset */ 959 960 /* Identify PHY and related function pointers */ 961 status = hw->phy.ops.init(hw); 962 963 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 964 goto reset_hw_out; 965 966 /* Setup SFP module if there is one present. */ 967 if (hw->phy.sfp_setup_needed) { 968 status = hw->mac.ops.setup_sfp(hw); 969 hw->phy.sfp_setup_needed = false; 970 } 971 972 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 973 goto reset_hw_out; 974 975 /* Reset PHY */ 976 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) 977 hw->phy.ops.reset(hw); 978 979 mac_reset_top: 980 /* 981 * Issue global reset to the MAC. Needs to be SW reset if link is up. 982 * If link reset is used when link is up, it might reset the PHY when 983 * mng is using it. If link is down or the flag to force full link 984 * reset is set, then perform link reset. 985 */ 986 ctrl = IXGBE_CTRL_LNK_RST; 987 if (!hw->force_full_reset) { 988 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 989 if (link_up) 990 ctrl = IXGBE_CTRL_RST; 991 } 992 993 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 994 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 995 IXGBE_WRITE_FLUSH(hw); 996 997 /* Poll for reset bit to self-clear indicating reset is complete */ 998 for (i = 0; i < 10; i++) { 999 udelay(1); 1000 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1001 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 1002 break; 1003 } 1004 1005 if (ctrl & IXGBE_CTRL_RST_MASK) { 1006 status = IXGBE_ERR_RESET_FAILED; 1007 hw_dbg(hw, "Reset polling failed to complete.\n"); 1008 } 1009 1010 msleep(50); 1011 1012 /* 1013 * Double resets are required for recovery from certain error 1014 * conditions. Between resets, it is necessary to stall to allow time 1015 * for any pending HW events to complete. 1016 */ 1017 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1018 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1019 goto mac_reset_top; 1020 } 1021 1022 /* 1023 * Store the original AUTOC/AUTOC2 values if they have not been 1024 * stored off yet. Otherwise restore the stored original 1025 * values since the reset operation sets back to defaults. 1026 */ 1027 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1028 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1029 if (hw->mac.orig_link_settings_stored == false) { 1030 hw->mac.orig_autoc = autoc; 1031 hw->mac.orig_autoc2 = autoc2; 1032 hw->mac.orig_link_settings_stored = true; 1033 } else { 1034 if (autoc != hw->mac.orig_autoc) { 1035 /* Need SW/FW semaphore around AUTOC writes if LESM is 1036 * on, likewise reset_pipeline requires us to hold 1037 * this lock as it also writes to AUTOC. 1038 */ 1039 bool got_lock = false; 1040 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 1041 status = hw->mac.ops.acquire_swfw_sync(hw, 1042 IXGBE_GSSR_MAC_CSR_SM); 1043 if (status) 1044 goto reset_hw_out; 1045 1046 got_lock = true; 1047 } 1048 1049 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); 1050 ixgbe_reset_pipeline_82599(hw); 1051 1052 if (got_lock) 1053 hw->mac.ops.release_swfw_sync(hw, 1054 IXGBE_GSSR_MAC_CSR_SM); 1055 } 1056 1057 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != 1058 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { 1059 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; 1060 autoc2 |= (hw->mac.orig_autoc2 & 1061 IXGBE_AUTOC2_UPPER_MASK); 1062 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1063 } 1064 } 1065 1066 /* Store the permanent mac address */ 1067 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1068 1069 /* 1070 * Store MAC address from RAR0, clear receive address registers, and 1071 * clear the multicast table. Also reset num_rar_entries to 128, 1072 * since we modify this value when programming the SAN MAC address. 1073 */ 1074 hw->mac.num_rar_entries = 128; 1075 hw->mac.ops.init_rx_addrs(hw); 1076 1077 /* Store the permanent SAN mac address */ 1078 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 1079 1080 /* Add the SAN MAC address to the RAR only if it's a valid address */ 1081 if (is_valid_ether_addr(hw->mac.san_addr)) { 1082 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, 1083 hw->mac.san_addr, 0, IXGBE_RAH_AV); 1084 1085 /* Save the SAN MAC RAR index */ 1086 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 1087 1088 /* Reserve the last RAR for the SAN MAC address */ 1089 hw->mac.num_rar_entries--; 1090 } 1091 1092 /* Store the alternative WWNN/WWPN prefix */ 1093 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 1094 &hw->mac.wwpn_prefix); 1095 1096 reset_hw_out: 1097 return status; 1098 } 1099 1100 /** 1101 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. 1102 * @hw: pointer to hardware structure 1103 **/ 1104 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) 1105 { 1106 int i; 1107 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1108 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; 1109 1110 /* 1111 * Before starting reinitialization process, 1112 * FDIRCMD.CMD must be zero. 1113 */ 1114 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { 1115 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1116 IXGBE_FDIRCMD_CMD_MASK)) 1117 break; 1118 udelay(10); 1119 } 1120 if (i >= IXGBE_FDIRCMD_CMD_POLL) { 1121 hw_dbg(hw, "Flow Director previous command isn't complete, " 1122 "aborting table re-initialization.\n"); 1123 return IXGBE_ERR_FDIR_REINIT_FAILED; 1124 } 1125 1126 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); 1127 IXGBE_WRITE_FLUSH(hw); 1128 /* 1129 * 82599 adapters flow director init flow cannot be restarted, 1130 * Workaround 82599 silicon errata by performing the following steps 1131 * before re-writing the FDIRCTRL control register with the same value. 1132 * - write 1 to bit 8 of FDIRCMD register & 1133 * - write 0 to bit 8 of FDIRCMD register 1134 */ 1135 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1136 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1137 IXGBE_FDIRCMD_CLEARHT)); 1138 IXGBE_WRITE_FLUSH(hw); 1139 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1140 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1141 ~IXGBE_FDIRCMD_CLEARHT)); 1142 IXGBE_WRITE_FLUSH(hw); 1143 /* 1144 * Clear FDIR Hash register to clear any leftover hashes 1145 * waiting to be programmed. 1146 */ 1147 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); 1148 IXGBE_WRITE_FLUSH(hw); 1149 1150 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1151 IXGBE_WRITE_FLUSH(hw); 1152 1153 /* Poll init-done after we write FDIRCTRL register */ 1154 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1155 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1156 IXGBE_FDIRCTRL_INIT_DONE) 1157 break; 1158 usleep_range(1000, 2000); 1159 } 1160 if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 1161 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n"); 1162 return IXGBE_ERR_FDIR_REINIT_FAILED; 1163 } 1164 1165 /* Clear FDIR statistics registers (read to clear) */ 1166 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); 1167 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); 1168 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 1169 IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 1170 IXGBE_READ_REG(hw, IXGBE_FDIRLEN); 1171 1172 return 0; 1173 } 1174 1175 /** 1176 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers 1177 * @hw: pointer to hardware structure 1178 * @fdirctrl: value to write to flow director control register 1179 **/ 1180 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1181 { 1182 int i; 1183 1184 /* Prime the keys for hashing */ 1185 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); 1186 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); 1187 1188 /* 1189 * Poll init-done after we write the register. Estimated times: 1190 * 10G: PBALLOC = 11b, timing is 60us 1191 * 1G: PBALLOC = 11b, timing is 600us 1192 * 100M: PBALLOC = 11b, timing is 6ms 1193 * 1194 * Multiple these timings by 4 if under full Rx load 1195 * 1196 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1197 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1198 * this might not finish in our poll time, but we can live with that 1199 * for now. 1200 */ 1201 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1202 IXGBE_WRITE_FLUSH(hw); 1203 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1204 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1205 IXGBE_FDIRCTRL_INIT_DONE) 1206 break; 1207 usleep_range(1000, 2000); 1208 } 1209 1210 if (i >= IXGBE_FDIR_INIT_DONE_POLL) 1211 hw_dbg(hw, "Flow Director poll time exceeded!\n"); 1212 } 1213 1214 /** 1215 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters 1216 * @hw: pointer to hardware structure 1217 * @fdirctrl: value to write to flow director control register, initially 1218 * contains just the value of the Rx packet buffer allocation 1219 **/ 1220 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1221 { 1222 /* 1223 * Continue setup of fdirctrl register bits: 1224 * Move the flexible bytes to use the ethertype - shift 6 words 1225 * Set the maximum length per hash bucket to 0xA filters 1226 * Send interrupt when 64 filters are left 1227 */ 1228 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1229 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1230 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1231 1232 /* write hashes and fdirctrl register, poll for completion */ 1233 ixgbe_fdir_enable_82599(hw, fdirctrl); 1234 1235 return 0; 1236 } 1237 1238 /** 1239 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters 1240 * @hw: pointer to hardware structure 1241 * @fdirctrl: value to write to flow director control register, initially 1242 * contains just the value of the Rx packet buffer allocation 1243 **/ 1244 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1245 { 1246 /* 1247 * Continue setup of fdirctrl register bits: 1248 * Turn perfect match filtering on 1249 * Report hash in RSS field of Rx wb descriptor 1250 * Initialize the drop queue 1251 * Move the flexible bytes to use the ethertype - shift 6 words 1252 * Set the maximum length per hash bucket to 0xA filters 1253 * Send interrupt when 64 (0x4 * 16) filters are left 1254 */ 1255 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH | 1256 IXGBE_FDIRCTRL_REPORT_STATUS | 1257 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) | 1258 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1259 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1260 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1261 1262 /* write hashes and fdirctrl register, poll for completion */ 1263 ixgbe_fdir_enable_82599(hw, fdirctrl); 1264 1265 return 0; 1266 } 1267 1268 /* 1269 * These defines allow us to quickly generate all of the necessary instructions 1270 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION 1271 * for values 0 through 15 1272 */ 1273 #define IXGBE_ATR_COMMON_HASH_KEY \ 1274 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY) 1275 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \ 1276 do { \ 1277 u32 n = (_n); \ 1278 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \ 1279 common_hash ^= lo_hash_dword >> n; \ 1280 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1281 bucket_hash ^= lo_hash_dword >> n; \ 1282 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \ 1283 sig_hash ^= lo_hash_dword << (16 - n); \ 1284 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \ 1285 common_hash ^= hi_hash_dword >> n; \ 1286 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1287 bucket_hash ^= hi_hash_dword >> n; \ 1288 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \ 1289 sig_hash ^= hi_hash_dword << (16 - n); \ 1290 } while (0); 1291 1292 /** 1293 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash 1294 * @stream: input bitstream to compute the hash on 1295 * 1296 * This function is almost identical to the function above but contains 1297 * several optomizations such as unwinding all of the loops, letting the 1298 * compiler work out all of the conditional ifs since the keys are static 1299 * defines, and computing two keys at once since the hashed dword stream 1300 * will be the same for both keys. 1301 **/ 1302 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, 1303 union ixgbe_atr_hash_dword common) 1304 { 1305 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1306 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0; 1307 1308 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1309 flow_vm_vlan = ntohl(input.dword); 1310 1311 /* generate common hash dword */ 1312 hi_hash_dword = ntohl(common.dword); 1313 1314 /* low dword is word swapped version of common */ 1315 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1316 1317 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1318 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1319 1320 /* Process bits 0 and 16 */ 1321 IXGBE_COMPUTE_SIG_HASH_ITERATION(0); 1322 1323 /* 1324 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1325 * delay this because bit 0 of the stream should not be processed 1326 * so we do not add the vlan until after bit 0 was processed 1327 */ 1328 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1329 1330 /* Process remaining 30 bit of the key */ 1331 IXGBE_COMPUTE_SIG_HASH_ITERATION(1); 1332 IXGBE_COMPUTE_SIG_HASH_ITERATION(2); 1333 IXGBE_COMPUTE_SIG_HASH_ITERATION(3); 1334 IXGBE_COMPUTE_SIG_HASH_ITERATION(4); 1335 IXGBE_COMPUTE_SIG_HASH_ITERATION(5); 1336 IXGBE_COMPUTE_SIG_HASH_ITERATION(6); 1337 IXGBE_COMPUTE_SIG_HASH_ITERATION(7); 1338 IXGBE_COMPUTE_SIG_HASH_ITERATION(8); 1339 IXGBE_COMPUTE_SIG_HASH_ITERATION(9); 1340 IXGBE_COMPUTE_SIG_HASH_ITERATION(10); 1341 IXGBE_COMPUTE_SIG_HASH_ITERATION(11); 1342 IXGBE_COMPUTE_SIG_HASH_ITERATION(12); 1343 IXGBE_COMPUTE_SIG_HASH_ITERATION(13); 1344 IXGBE_COMPUTE_SIG_HASH_ITERATION(14); 1345 IXGBE_COMPUTE_SIG_HASH_ITERATION(15); 1346 1347 /* combine common_hash result with signature and bucket hashes */ 1348 bucket_hash ^= common_hash; 1349 bucket_hash &= IXGBE_ATR_HASH_MASK; 1350 1351 sig_hash ^= common_hash << 16; 1352 sig_hash &= IXGBE_ATR_HASH_MASK << 16; 1353 1354 /* return completed signature hash */ 1355 return sig_hash ^ bucket_hash; 1356 } 1357 1358 /** 1359 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter 1360 * @hw: pointer to hardware structure 1361 * @input: unique input dword 1362 * @common: compressed common input dword 1363 * @queue: queue index to direct traffic to 1364 **/ 1365 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 1366 union ixgbe_atr_hash_dword input, 1367 union ixgbe_atr_hash_dword common, 1368 u8 queue) 1369 { 1370 u64 fdirhashcmd; 1371 u32 fdircmd; 1372 1373 /* 1374 * Get the flow_type in order to program FDIRCMD properly 1375 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 1376 */ 1377 switch (input.formatted.flow_type) { 1378 case IXGBE_ATR_FLOW_TYPE_TCPV4: 1379 case IXGBE_ATR_FLOW_TYPE_UDPV4: 1380 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 1381 case IXGBE_ATR_FLOW_TYPE_TCPV6: 1382 case IXGBE_ATR_FLOW_TYPE_UDPV6: 1383 case IXGBE_ATR_FLOW_TYPE_SCTPV6: 1384 break; 1385 default: 1386 hw_dbg(hw, " Error on flow type input\n"); 1387 return IXGBE_ERR_CONFIG; 1388 } 1389 1390 /* configure FDIRCMD register */ 1391 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1392 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1393 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1394 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1395 1396 /* 1397 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits 1398 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. 1399 */ 1400 fdirhashcmd = (u64)fdircmd << 32; 1401 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common); 1402 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); 1403 1404 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); 1405 1406 return 0; 1407 } 1408 1409 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \ 1410 do { \ 1411 u32 n = (_n); \ 1412 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1413 bucket_hash ^= lo_hash_dword >> n; \ 1414 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1415 bucket_hash ^= hi_hash_dword >> n; \ 1416 } while (0); 1417 1418 /** 1419 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash 1420 * @atr_input: input bitstream to compute the hash on 1421 * @input_mask: mask for the input bitstream 1422 * 1423 * This function serves two main purposes. First it applys the input_mask 1424 * to the atr_input resulting in a cleaned up atr_input data stream. 1425 * Secondly it computes the hash and stores it in the bkt_hash field at 1426 * the end of the input byte stream. This way it will be available for 1427 * future use without needing to recompute the hash. 1428 **/ 1429 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 1430 union ixgbe_atr_input *input_mask) 1431 { 1432 1433 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1434 u32 bucket_hash = 0; 1435 1436 /* Apply masks to input data */ 1437 input->dword_stream[0] &= input_mask->dword_stream[0]; 1438 input->dword_stream[1] &= input_mask->dword_stream[1]; 1439 input->dword_stream[2] &= input_mask->dword_stream[2]; 1440 input->dword_stream[3] &= input_mask->dword_stream[3]; 1441 input->dword_stream[4] &= input_mask->dword_stream[4]; 1442 input->dword_stream[5] &= input_mask->dword_stream[5]; 1443 input->dword_stream[6] &= input_mask->dword_stream[6]; 1444 input->dword_stream[7] &= input_mask->dword_stream[7]; 1445 input->dword_stream[8] &= input_mask->dword_stream[8]; 1446 input->dword_stream[9] &= input_mask->dword_stream[9]; 1447 input->dword_stream[10] &= input_mask->dword_stream[10]; 1448 1449 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1450 flow_vm_vlan = ntohl(input->dword_stream[0]); 1451 1452 /* generate common hash dword */ 1453 hi_hash_dword = ntohl(input->dword_stream[1] ^ 1454 input->dword_stream[2] ^ 1455 input->dword_stream[3] ^ 1456 input->dword_stream[4] ^ 1457 input->dword_stream[5] ^ 1458 input->dword_stream[6] ^ 1459 input->dword_stream[7] ^ 1460 input->dword_stream[8] ^ 1461 input->dword_stream[9] ^ 1462 input->dword_stream[10]); 1463 1464 /* low dword is word swapped version of common */ 1465 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1466 1467 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1468 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1469 1470 /* Process bits 0 and 16 */ 1471 IXGBE_COMPUTE_BKT_HASH_ITERATION(0); 1472 1473 /* 1474 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1475 * delay this because bit 0 of the stream should not be processed 1476 * so we do not add the vlan until after bit 0 was processed 1477 */ 1478 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1479 1480 /* Process remaining 30 bit of the key */ 1481 IXGBE_COMPUTE_BKT_HASH_ITERATION(1); 1482 IXGBE_COMPUTE_BKT_HASH_ITERATION(2); 1483 IXGBE_COMPUTE_BKT_HASH_ITERATION(3); 1484 IXGBE_COMPUTE_BKT_HASH_ITERATION(4); 1485 IXGBE_COMPUTE_BKT_HASH_ITERATION(5); 1486 IXGBE_COMPUTE_BKT_HASH_ITERATION(6); 1487 IXGBE_COMPUTE_BKT_HASH_ITERATION(7); 1488 IXGBE_COMPUTE_BKT_HASH_ITERATION(8); 1489 IXGBE_COMPUTE_BKT_HASH_ITERATION(9); 1490 IXGBE_COMPUTE_BKT_HASH_ITERATION(10); 1491 IXGBE_COMPUTE_BKT_HASH_ITERATION(11); 1492 IXGBE_COMPUTE_BKT_HASH_ITERATION(12); 1493 IXGBE_COMPUTE_BKT_HASH_ITERATION(13); 1494 IXGBE_COMPUTE_BKT_HASH_ITERATION(14); 1495 IXGBE_COMPUTE_BKT_HASH_ITERATION(15); 1496 1497 /* 1498 * Limit hash to 13 bits since max bucket count is 8K. 1499 * Store result at the end of the input stream. 1500 */ 1501 input->formatted.bkt_hash = bucket_hash & 0x1FFF; 1502 } 1503 1504 /** 1505 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks 1506 * @input_mask: mask to be bit swapped 1507 * 1508 * The source and destination port masks for flow director are bit swapped 1509 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to 1510 * generate a correctly swapped value we need to bit swap the mask and that 1511 * is what is accomplished by this function. 1512 **/ 1513 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask) 1514 { 1515 u32 mask = ntohs(input_mask->formatted.dst_port); 1516 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT; 1517 mask |= ntohs(input_mask->formatted.src_port); 1518 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); 1519 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); 1520 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); 1521 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); 1522 } 1523 1524 /* 1525 * These two macros are meant to address the fact that we have registers 1526 * that are either all or in part big-endian. As a result on big-endian 1527 * systems we will end up byte swapping the value to little-endian before 1528 * it is byte swapped again and written to the hardware in the original 1529 * big-endian format. 1530 */ 1531 #define IXGBE_STORE_AS_BE32(_value) \ 1532 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \ 1533 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24)) 1534 1535 #define IXGBE_WRITE_REG_BE32(a, reg, value) \ 1536 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value))) 1537 1538 #define IXGBE_STORE_AS_BE16(_value) \ 1539 ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8)) 1540 1541 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 1542 union ixgbe_atr_input *input_mask) 1543 { 1544 /* mask IPv6 since it is currently not supported */ 1545 u32 fdirm = IXGBE_FDIRM_DIPv6; 1546 u32 fdirtcpm; 1547 1548 /* 1549 * Program the relevant mask registers. If src/dst_port or src/dst_addr 1550 * are zero, then assume a full mask for that field. Also assume that 1551 * a VLAN of 0 is unspecified, so mask that out as well. L4type 1552 * cannot be masked out in this implementation. 1553 * 1554 * This also assumes IPv4 only. IPv6 masking isn't supported at this 1555 * point in time. 1556 */ 1557 1558 /* verify bucket hash is cleared on hash generation */ 1559 if (input_mask->formatted.bkt_hash) 1560 hw_dbg(hw, " bucket hash should always be 0 in mask\n"); 1561 1562 /* Program FDIRM and verify partial masks */ 1563 switch (input_mask->formatted.vm_pool & 0x7F) { 1564 case 0x0: 1565 fdirm |= IXGBE_FDIRM_POOL; 1566 case 0x7F: 1567 break; 1568 default: 1569 hw_dbg(hw, " Error on vm pool mask\n"); 1570 return IXGBE_ERR_CONFIG; 1571 } 1572 1573 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) { 1574 case 0x0: 1575 fdirm |= IXGBE_FDIRM_L4P; 1576 if (input_mask->formatted.dst_port || 1577 input_mask->formatted.src_port) { 1578 hw_dbg(hw, " Error on src/dst port mask\n"); 1579 return IXGBE_ERR_CONFIG; 1580 } 1581 case IXGBE_ATR_L4TYPE_MASK: 1582 break; 1583 default: 1584 hw_dbg(hw, " Error on flow type mask\n"); 1585 return IXGBE_ERR_CONFIG; 1586 } 1587 1588 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) { 1589 case 0x0000: 1590 /* mask VLAN ID, fall through to mask VLAN priority */ 1591 fdirm |= IXGBE_FDIRM_VLANID; 1592 case 0x0FFF: 1593 /* mask VLAN priority */ 1594 fdirm |= IXGBE_FDIRM_VLANP; 1595 break; 1596 case 0xE000: 1597 /* mask VLAN ID only, fall through */ 1598 fdirm |= IXGBE_FDIRM_VLANID; 1599 case 0xEFFF: 1600 /* no VLAN fields masked */ 1601 break; 1602 default: 1603 hw_dbg(hw, " Error on VLAN mask\n"); 1604 return IXGBE_ERR_CONFIG; 1605 } 1606 1607 switch (input_mask->formatted.flex_bytes & 0xFFFF) { 1608 case 0x0000: 1609 /* Mask Flex Bytes, fall through */ 1610 fdirm |= IXGBE_FDIRM_FLEX; 1611 case 0xFFFF: 1612 break; 1613 default: 1614 hw_dbg(hw, " Error on flexible byte mask\n"); 1615 return IXGBE_ERR_CONFIG; 1616 } 1617 1618 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ 1619 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); 1620 1621 /* store the TCP/UDP port masks, bit reversed from port layout */ 1622 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask); 1623 1624 /* write both the same so that UDP and TCP use the same mask */ 1625 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); 1626 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); 1627 1628 /* store source and destination IP masks (big-enian) */ 1629 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 1630 ~input_mask->formatted.src_ip[0]); 1631 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 1632 ~input_mask->formatted.dst_ip[0]); 1633 1634 return 0; 1635 } 1636 1637 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 1638 union ixgbe_atr_input *input, 1639 u16 soft_id, u8 queue) 1640 { 1641 u32 fdirport, fdirvlan, fdirhash, fdircmd; 1642 1643 /* currently IPv6 is not supported, must be programmed with 0 */ 1644 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), 1645 input->formatted.src_ip[0]); 1646 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), 1647 input->formatted.src_ip[1]); 1648 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), 1649 input->formatted.src_ip[2]); 1650 1651 /* record the source address (big-endian) */ 1652 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]); 1653 1654 /* record the first 32 bits of the destination address (big-endian) */ 1655 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]); 1656 1657 /* record source and destination port (little-endian)*/ 1658 fdirport = ntohs(input->formatted.dst_port); 1659 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT; 1660 fdirport |= ntohs(input->formatted.src_port); 1661 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); 1662 1663 /* record vlan (little-endian) and flex_bytes(big-endian) */ 1664 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes); 1665 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; 1666 fdirvlan |= ntohs(input->formatted.vlan_id); 1667 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); 1668 1669 /* configure FDIRHASH register */ 1670 fdirhash = input->formatted.bkt_hash; 1671 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1672 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1673 1674 /* 1675 * flush all previous writes to make certain registers are 1676 * programmed prior to issuing the command 1677 */ 1678 IXGBE_WRITE_FLUSH(hw); 1679 1680 /* configure FDIRCMD register */ 1681 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1682 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1683 if (queue == IXGBE_FDIR_DROP_QUEUE) 1684 fdircmd |= IXGBE_FDIRCMD_DROP; 1685 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1686 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1687 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT; 1688 1689 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); 1690 1691 return 0; 1692 } 1693 1694 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 1695 union ixgbe_atr_input *input, 1696 u16 soft_id) 1697 { 1698 u32 fdirhash; 1699 u32 fdircmd = 0; 1700 u32 retry_count; 1701 s32 err = 0; 1702 1703 /* configure FDIRHASH register */ 1704 fdirhash = input->formatted.bkt_hash; 1705 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1706 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1707 1708 /* flush hash to HW */ 1709 IXGBE_WRITE_FLUSH(hw); 1710 1711 /* Query if filter is present */ 1712 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT); 1713 1714 for (retry_count = 10; retry_count; retry_count--) { 1715 /* allow 10us for query to process */ 1716 udelay(10); 1717 /* verify query completed successfully */ 1718 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD); 1719 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK)) 1720 break; 1721 } 1722 1723 if (!retry_count) 1724 err = IXGBE_ERR_FDIR_REINIT_FAILED; 1725 1726 /* if filter exists in hardware then remove it */ 1727 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) { 1728 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1729 IXGBE_WRITE_FLUSH(hw); 1730 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1731 IXGBE_FDIRCMD_CMD_REMOVE_FLOW); 1732 } 1733 1734 return err; 1735 } 1736 1737 /** 1738 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 1739 * @hw: pointer to hardware structure 1740 * @reg: analog register to read 1741 * @val: read value 1742 * 1743 * Performs read operation to Omer analog register specified. 1744 **/ 1745 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) 1746 { 1747 u32 core_ctl; 1748 1749 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | 1750 (reg << 8)); 1751 IXGBE_WRITE_FLUSH(hw); 1752 udelay(10); 1753 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); 1754 *val = (u8)core_ctl; 1755 1756 return 0; 1757 } 1758 1759 /** 1760 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register 1761 * @hw: pointer to hardware structure 1762 * @reg: atlas register to write 1763 * @val: value to write 1764 * 1765 * Performs write operation to Omer analog register specified. 1766 **/ 1767 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) 1768 { 1769 u32 core_ctl; 1770 1771 core_ctl = (reg << 8) | val; 1772 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); 1773 IXGBE_WRITE_FLUSH(hw); 1774 udelay(10); 1775 1776 return 0; 1777 } 1778 1779 /** 1780 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx 1781 * @hw: pointer to hardware structure 1782 * 1783 * Starts the hardware using the generic start_hw function 1784 * and the generation start_hw function. 1785 * Then performs revision-specific operations, if any. 1786 **/ 1787 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) 1788 { 1789 s32 ret_val = 0; 1790 1791 ret_val = ixgbe_start_hw_generic(hw); 1792 if (ret_val != 0) 1793 goto out; 1794 1795 ret_val = ixgbe_start_hw_gen2(hw); 1796 if (ret_val != 0) 1797 goto out; 1798 1799 /* We need to run link autotry after the driver loads */ 1800 hw->mac.autotry_restart = true; 1801 hw->mac.rx_pb_size = IXGBE_82599_RX_PB_SIZE; 1802 1803 if (ret_val == 0) 1804 ret_val = ixgbe_verify_fw_version_82599(hw); 1805 out: 1806 return ret_val; 1807 } 1808 1809 /** 1810 * ixgbe_identify_phy_82599 - Get physical layer module 1811 * @hw: pointer to hardware structure 1812 * 1813 * Determines the physical layer module found on the current adapter. 1814 * If PHY already detected, maintains current PHY type in hw struct, 1815 * otherwise executes the PHY detection routine. 1816 **/ 1817 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 1818 { 1819 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1820 1821 /* Detect PHY if not unknown - returns success if already detected. */ 1822 status = ixgbe_identify_phy_generic(hw); 1823 if (status != 0) { 1824 /* 82599 10GBASE-T requires an external PHY */ 1825 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) 1826 goto out; 1827 else 1828 status = ixgbe_identify_sfp_module_generic(hw); 1829 } 1830 1831 /* Set PHY type none if no PHY detected */ 1832 if (hw->phy.type == ixgbe_phy_unknown) { 1833 hw->phy.type = ixgbe_phy_none; 1834 status = 0; 1835 } 1836 1837 /* Return error if SFP module has been detected but is not supported */ 1838 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 1839 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1840 1841 out: 1842 return status; 1843 } 1844 1845 /** 1846 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type 1847 * @hw: pointer to hardware structure 1848 * 1849 * Determines physical layer capabilities of the current configuration. 1850 **/ 1851 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) 1852 { 1853 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1854 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1855 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1856 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 1857 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 1858 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1859 u16 ext_ability = 0; 1860 u8 comp_codes_10g = 0; 1861 u8 comp_codes_1g = 0; 1862 1863 hw->phy.ops.identify(hw); 1864 1865 switch (hw->phy.type) { 1866 case ixgbe_phy_tn: 1867 case ixgbe_phy_cu_unknown: 1868 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD, 1869 &ext_ability); 1870 if (ext_ability & MDIO_PMA_EXTABLE_10GBT) 1871 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1872 if (ext_ability & MDIO_PMA_EXTABLE_1000BT) 1873 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1874 if (ext_ability & MDIO_PMA_EXTABLE_100BTX) 1875 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1876 goto out; 1877 default: 1878 break; 1879 } 1880 1881 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1882 case IXGBE_AUTOC_LMS_1G_AN: 1883 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 1884 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { 1885 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | 1886 IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1887 goto out; 1888 } else 1889 /* SFI mode so read SFP module */ 1890 goto sfp_check; 1891 break; 1892 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 1893 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) 1894 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1895 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) 1896 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1897 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) 1898 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; 1899 goto out; 1900 break; 1901 case IXGBE_AUTOC_LMS_10G_SERIAL: 1902 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { 1903 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; 1904 goto out; 1905 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) 1906 goto sfp_check; 1907 break; 1908 case IXGBE_AUTOC_LMS_KX4_KX_KR: 1909 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 1910 if (autoc & IXGBE_AUTOC_KX_SUPP) 1911 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1912 if (autoc & IXGBE_AUTOC_KX4_SUPP) 1913 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1914 if (autoc & IXGBE_AUTOC_KR_SUPP) 1915 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; 1916 goto out; 1917 break; 1918 default: 1919 goto out; 1920 break; 1921 } 1922 1923 sfp_check: 1924 /* SFP check must be done last since DA modules are sometimes used to 1925 * test KR mode - we need to id KR mode correctly before SFP module. 1926 * Call identify_sfp because the pluggable module may have changed */ 1927 hw->phy.ops.identify_sfp(hw); 1928 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1929 goto out; 1930 1931 switch (hw->phy.type) { 1932 case ixgbe_phy_sfp_passive_tyco: 1933 case ixgbe_phy_sfp_passive_unknown: 1934 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1935 break; 1936 case ixgbe_phy_sfp_ftl_active: 1937 case ixgbe_phy_sfp_active_unknown: 1938 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1939 break; 1940 case ixgbe_phy_sfp_avago: 1941 case ixgbe_phy_sfp_ftl: 1942 case ixgbe_phy_sfp_intel: 1943 case ixgbe_phy_sfp_unknown: 1944 hw->phy.ops.read_i2c_eeprom(hw, 1945 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1946 hw->phy.ops.read_i2c_eeprom(hw, 1947 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1948 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1949 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1950 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1951 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1952 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1953 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1954 break; 1955 default: 1956 break; 1957 } 1958 1959 out: 1960 return physical_layer; 1961 } 1962 1963 /** 1964 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 1965 * @hw: pointer to hardware structure 1966 * @regval: register value to write to RXCTRL 1967 * 1968 * Enables the Rx DMA unit for 82599 1969 **/ 1970 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) 1971 { 1972 /* 1973 * Workaround for 82599 silicon errata when enabling the Rx datapath. 1974 * If traffic is incoming before we enable the Rx unit, it could hang 1975 * the Rx DMA unit. Therefore, make sure the security engine is 1976 * completely disabled prior to enabling the Rx unit. 1977 */ 1978 hw->mac.ops.disable_rx_buff(hw); 1979 1980 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 1981 1982 hw->mac.ops.enable_rx_buff(hw); 1983 1984 return 0; 1985 } 1986 1987 /** 1988 * ixgbe_verify_fw_version_82599 - verify fw version for 82599 1989 * @hw: pointer to hardware structure 1990 * 1991 * Verifies that installed the firmware version is 0.6 or higher 1992 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. 1993 * 1994 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or 1995 * if the FW version is not supported. 1996 **/ 1997 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 1998 { 1999 s32 status = IXGBE_ERR_EEPROM_VERSION; 2000 u16 fw_offset, fw_ptp_cfg_offset; 2001 u16 fw_version = 0; 2002 2003 /* firmware check is only necessary for SFI devices */ 2004 if (hw->phy.media_type != ixgbe_media_type_fiber) { 2005 status = 0; 2006 goto fw_version_out; 2007 } 2008 2009 /* get the offset to the Firmware Module block */ 2010 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 2011 2012 if ((fw_offset == 0) || (fw_offset == 0xFFFF)) 2013 goto fw_version_out; 2014 2015 /* get the offset to the Pass Through Patch Configuration block */ 2016 hw->eeprom.ops.read(hw, (fw_offset + 2017 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), 2018 &fw_ptp_cfg_offset); 2019 2020 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) 2021 goto fw_version_out; 2022 2023 /* get the firmware version */ 2024 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + 2025 IXGBE_FW_PATCH_VERSION_4), 2026 &fw_version); 2027 2028 if (fw_version > 0x5) 2029 status = 0; 2030 2031 fw_version_out: 2032 return status; 2033 } 2034 2035 /** 2036 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state. 2037 * @hw: pointer to hardware structure 2038 * 2039 * Returns true if the LESM FW module is present and enabled. Otherwise 2040 * returns false. Smart Speed must be disabled if LESM FW module is enabled. 2041 **/ 2042 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) 2043 { 2044 bool lesm_enabled = false; 2045 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state; 2046 s32 status; 2047 2048 /* get the offset to the Firmware Module block */ 2049 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 2050 2051 if ((status != 0) || 2052 (fw_offset == 0) || (fw_offset == 0xFFFF)) 2053 goto out; 2054 2055 /* get the offset to the LESM Parameters block */ 2056 status = hw->eeprom.ops.read(hw, (fw_offset + 2057 IXGBE_FW_LESM_PARAMETERS_PTR), 2058 &fw_lesm_param_offset); 2059 2060 if ((status != 0) || 2061 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF)) 2062 goto out; 2063 2064 /* get the lesm state word */ 2065 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + 2066 IXGBE_FW_LESM_STATE_1), 2067 &fw_lesm_state); 2068 2069 if ((status == 0) && 2070 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) 2071 lesm_enabled = true; 2072 2073 out: 2074 return lesm_enabled; 2075 } 2076 2077 /** 2078 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using 2079 * fastest available method 2080 * 2081 * @hw: pointer to hardware structure 2082 * @offset: offset of word in EEPROM to read 2083 * @words: number of words 2084 * @data: word(s) read from the EEPROM 2085 * 2086 * Retrieves 16 bit word(s) read from EEPROM 2087 **/ 2088 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, 2089 u16 words, u16 *data) 2090 { 2091 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2092 s32 ret_val = IXGBE_ERR_CONFIG; 2093 2094 /* 2095 * If EEPROM is detected and can be addressed using 14 bits, 2096 * use EERD otherwise use bit bang 2097 */ 2098 if ((eeprom->type == ixgbe_eeprom_spi) && 2099 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR)) 2100 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words, 2101 data); 2102 else 2103 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset, 2104 words, 2105 data); 2106 2107 return ret_val; 2108 } 2109 2110 /** 2111 * ixgbe_read_eeprom_82599 - Read EEPROM word using 2112 * fastest available method 2113 * 2114 * @hw: pointer to hardware structure 2115 * @offset: offset of word in the EEPROM to read 2116 * @data: word read from the EEPROM 2117 * 2118 * Reads a 16 bit word from the EEPROM 2119 **/ 2120 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 2121 u16 offset, u16 *data) 2122 { 2123 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2124 s32 ret_val = IXGBE_ERR_CONFIG; 2125 2126 /* 2127 * If EEPROM is detected and can be addressed using 14 bits, 2128 * use EERD otherwise use bit bang 2129 */ 2130 if ((eeprom->type == ixgbe_eeprom_spi) && 2131 (offset <= IXGBE_EERD_MAX_ADDR)) 2132 ret_val = ixgbe_read_eerd_generic(hw, offset, data); 2133 else 2134 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data); 2135 2136 return ret_val; 2137 } 2138 2139 /** 2140 * ixgbe_reset_pipeline_82599 - perform pipeline reset 2141 * 2142 * @hw: pointer to hardware structure 2143 * 2144 * Reset pipeline by asserting Restart_AN together with LMS change to ensure 2145 * full pipeline reset. Note - We must hold the SW/FW semaphore before writing 2146 * to AUTOC, so this function assumes the semaphore is held. 2147 **/ 2148 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw) 2149 { 2150 s32 i, autoc_reg, ret_val; 2151 s32 anlp1_reg = 0; 2152 2153 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2154 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2155 2156 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */ 2157 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg ^ IXGBE_AUTOC_LMS_1G_AN); 2158 2159 /* Wait for AN to leave state 0 */ 2160 for (i = 0; i < 10; i++) { 2161 usleep_range(4000, 8000); 2162 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2163 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK) 2164 break; 2165 } 2166 2167 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) { 2168 hw_dbg(hw, "auto negotiation not completed\n"); 2169 ret_val = IXGBE_ERR_RESET_FAILED; 2170 goto reset_pipeline_out; 2171 } 2172 2173 ret_val = 0; 2174 2175 reset_pipeline_out: 2176 /* Write AUTOC register with original LMS field and Restart_AN */ 2177 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2178 IXGBE_WRITE_FLUSH(hw); 2179 2180 return ret_val; 2181 } 2182 2183 static struct ixgbe_mac_operations mac_ops_82599 = { 2184 .init_hw = &ixgbe_init_hw_generic, 2185 .reset_hw = &ixgbe_reset_hw_82599, 2186 .start_hw = &ixgbe_start_hw_82599, 2187 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, 2188 .get_media_type = &ixgbe_get_media_type_82599, 2189 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599, 2190 .enable_rx_dma = &ixgbe_enable_rx_dma_82599, 2191 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, 2192 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, 2193 .get_mac_addr = &ixgbe_get_mac_addr_generic, 2194 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 2195 .get_device_caps = &ixgbe_get_device_caps_generic, 2196 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 2197 .stop_adapter = &ixgbe_stop_adapter_generic, 2198 .get_bus_info = &ixgbe_get_bus_info_generic, 2199 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, 2200 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599, 2201 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599, 2202 .setup_link = &ixgbe_setup_mac_link_82599, 2203 .set_rxpba = &ixgbe_set_rxpba_generic, 2204 .check_link = &ixgbe_check_mac_link_generic, 2205 .get_link_capabilities = &ixgbe_get_link_capabilities_82599, 2206 .led_on = &ixgbe_led_on_generic, 2207 .led_off = &ixgbe_led_off_generic, 2208 .blink_led_start = &ixgbe_blink_led_start_generic, 2209 .blink_led_stop = &ixgbe_blink_led_stop_generic, 2210 .set_rar = &ixgbe_set_rar_generic, 2211 .clear_rar = &ixgbe_clear_rar_generic, 2212 .set_vmdq = &ixgbe_set_vmdq_generic, 2213 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, 2214 .clear_vmdq = &ixgbe_clear_vmdq_generic, 2215 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 2216 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 2217 .enable_mc = &ixgbe_enable_mc_generic, 2218 .disable_mc = &ixgbe_disable_mc_generic, 2219 .clear_vfta = &ixgbe_clear_vfta_generic, 2220 .set_vfta = &ixgbe_set_vfta_generic, 2221 .fc_enable = &ixgbe_fc_enable_generic, 2222 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic, 2223 .init_uta_tables = &ixgbe_init_uta_tables_generic, 2224 .setup_sfp = &ixgbe_setup_sfp_modules_82599, 2225 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, 2226 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, 2227 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync, 2228 .release_swfw_sync = &ixgbe_release_swfw_sync, 2229 .get_thermal_sensor_data = &ixgbe_get_thermal_sensor_data_generic, 2230 .init_thermal_sensor_thresh = &ixgbe_init_thermal_sensor_thresh_generic, 2231 2232 }; 2233 2234 static struct ixgbe_eeprom_operations eeprom_ops_82599 = { 2235 .init_params = &ixgbe_init_eeprom_params_generic, 2236 .read = &ixgbe_read_eeprom_82599, 2237 .read_buffer = &ixgbe_read_eeprom_buffer_82599, 2238 .write = &ixgbe_write_eeprom_generic, 2239 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic, 2240 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic, 2241 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, 2242 .update_checksum = &ixgbe_update_eeprom_checksum_generic, 2243 }; 2244 2245 static struct ixgbe_phy_operations phy_ops_82599 = { 2246 .identify = &ixgbe_identify_phy_82599, 2247 .identify_sfp = &ixgbe_identify_sfp_module_generic, 2248 .init = &ixgbe_init_phy_ops_82599, 2249 .reset = &ixgbe_reset_phy_generic, 2250 .read_reg = &ixgbe_read_phy_reg_generic, 2251 .write_reg = &ixgbe_write_phy_reg_generic, 2252 .setup_link = &ixgbe_setup_phy_link_generic, 2253 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, 2254 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, 2255 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, 2256 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, 2257 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, 2258 .check_overtemp = &ixgbe_tn_check_overtemp, 2259 }; 2260 2261 struct ixgbe_info ixgbe_82599_info = { 2262 .mac = ixgbe_mac_82599EB, 2263 .get_invariants = &ixgbe_get_invariants_82599, 2264 .mac_ops = &mac_ops_82599, 2265 .eeprom_ops = &eeprom_ops_82599, 2266 .phy_ops = &phy_ops_82599, 2267 .mbx_ops = &mbx_ops_generic, 2268 }; 2269