1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #ifndef _IXGBE_H_ 30 #define _IXGBE_H_ 31 32 #include <linux/bitops.h> 33 #include <linux/types.h> 34 #include <linux/pci.h> 35 #include <linux/netdevice.h> 36 #include <linux/cpumask.h> 37 #include <linux/aer.h> 38 #include <linux/if_vlan.h> 39 #include <linux/jiffies.h> 40 41 #include <linux/clocksource.h> 42 #include <linux/net_tstamp.h> 43 #include <linux/ptp_clock_kernel.h> 44 45 #include "ixgbe_type.h" 46 #include "ixgbe_common.h" 47 #include "ixgbe_dcb.h" 48 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) 49 #define IXGBE_FCOE 50 #include "ixgbe_fcoe.h" 51 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */ 52 #ifdef CONFIG_IXGBE_DCA 53 #include <linux/dca.h> 54 #endif 55 56 #include <net/busy_poll.h> 57 58 #ifdef CONFIG_NET_RX_BUSY_POLL 59 #define BP_EXTENDED_STATS 60 #endif 61 /* common prefix used by pr_<> macros */ 62 #undef pr_fmt 63 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 64 65 /* TX/RX descriptor defines */ 66 #define IXGBE_DEFAULT_TXD 512 67 #define IXGBE_DEFAULT_TX_WORK 256 68 #define IXGBE_MAX_TXD 4096 69 #define IXGBE_MIN_TXD 64 70 71 #if (PAGE_SIZE < 8192) 72 #define IXGBE_DEFAULT_RXD 512 73 #else 74 #define IXGBE_DEFAULT_RXD 128 75 #endif 76 #define IXGBE_MAX_RXD 4096 77 #define IXGBE_MIN_RXD 64 78 79 /* flow control */ 80 #define IXGBE_MIN_FCRTL 0x40 81 #define IXGBE_MAX_FCRTL 0x7FF80 82 #define IXGBE_MIN_FCRTH 0x600 83 #define IXGBE_MAX_FCRTH 0x7FFF0 84 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF 85 #define IXGBE_MIN_FCPAUSE 0 86 #define IXGBE_MAX_FCPAUSE 0xFFFF 87 88 /* Supported Rx Buffer Sizes */ 89 #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ 90 #define IXGBE_RXBUFFER_2K 2048 91 #define IXGBE_RXBUFFER_3K 3072 92 #define IXGBE_RXBUFFER_4K 4096 93 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ 94 95 /* 96 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 97 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more, 98 * this adds up to 448 bytes of extra data. 99 * 100 * Since netdev_alloc_skb now allocates a page fragment we can use a value 101 * of 256 and the resultant skb will have a truesize of 960 or less. 102 */ 103 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 104 105 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 106 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 107 108 enum ixgbe_tx_flags { 109 /* cmd_type flags */ 110 IXGBE_TX_FLAGS_HW_VLAN = 0x01, 111 IXGBE_TX_FLAGS_TSO = 0x02, 112 IXGBE_TX_FLAGS_TSTAMP = 0x04, 113 114 /* olinfo flags */ 115 IXGBE_TX_FLAGS_CC = 0x08, 116 IXGBE_TX_FLAGS_IPV4 = 0x10, 117 IXGBE_TX_FLAGS_CSUM = 0x20, 118 119 /* software defined flags */ 120 IXGBE_TX_FLAGS_SW_VLAN = 0x40, 121 IXGBE_TX_FLAGS_FCOE = 0x80, 122 }; 123 124 /* VLAN info */ 125 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 126 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 127 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 128 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 129 130 #define IXGBE_MAX_VF_MC_ENTRIES 30 131 #define IXGBE_MAX_VF_FUNCTIONS 64 132 #define IXGBE_MAX_VFTA_ENTRIES 128 133 #define MAX_EMULATION_MAC_ADDRS 16 134 #define IXGBE_MAX_PF_MACVLANS 15 135 #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset) 136 #define IXGBE_82599_VF_DEVICE_ID 0x10ED 137 #define IXGBE_X540_VF_DEVICE_ID 0x1515 138 139 struct vf_data_storage { 140 unsigned char vf_mac_addresses[ETH_ALEN]; 141 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; 142 u16 num_vf_mc_hashes; 143 u16 default_vf_vlan_id; 144 u16 vlans_enabled; 145 bool clear_to_send; 146 bool pf_set_mac; 147 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 148 u16 pf_qos; 149 u16 tx_rate; 150 u16 vlan_count; 151 u8 spoofchk_enabled; 152 unsigned int vf_api; 153 }; 154 155 struct vf_macvlans { 156 struct list_head l; 157 int vf; 158 bool free; 159 bool is_macvlan; 160 u8 vf_macvlan[ETH_ALEN]; 161 }; 162 163 #define IXGBE_MAX_TXD_PWR 14 164 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) 165 166 /* Tx Descriptors needed, worst case */ 167 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) 168 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 169 170 /* wrapper around a pointer to a socket buffer, 171 * so a DMA handle can be stored along with the buffer */ 172 struct ixgbe_tx_buffer { 173 union ixgbe_adv_tx_desc *next_to_watch; 174 unsigned long time_stamp; 175 struct sk_buff *skb; 176 unsigned int bytecount; 177 unsigned short gso_segs; 178 __be16 protocol; 179 DEFINE_DMA_UNMAP_ADDR(dma); 180 DEFINE_DMA_UNMAP_LEN(len); 181 u32 tx_flags; 182 }; 183 184 struct ixgbe_rx_buffer { 185 struct sk_buff *skb; 186 dma_addr_t dma; 187 struct page *page; 188 unsigned int page_offset; 189 }; 190 191 struct ixgbe_queue_stats { 192 u64 packets; 193 u64 bytes; 194 #ifdef BP_EXTENDED_STATS 195 u64 yields; 196 u64 misses; 197 u64 cleaned; 198 #endif /* BP_EXTENDED_STATS */ 199 }; 200 201 struct ixgbe_tx_queue_stats { 202 u64 restart_queue; 203 u64 tx_busy; 204 u64 tx_done_old; 205 }; 206 207 struct ixgbe_rx_queue_stats { 208 u64 rsc_count; 209 u64 rsc_flush; 210 u64 non_eop_descs; 211 u64 alloc_rx_page_failed; 212 u64 alloc_rx_buff_failed; 213 u64 csum_err; 214 }; 215 216 enum ixgbe_ring_state_t { 217 __IXGBE_TX_FDIR_INIT_DONE, 218 __IXGBE_TX_XPS_INIT_DONE, 219 __IXGBE_TX_DETECT_HANG, 220 __IXGBE_HANG_CHECK_ARMED, 221 __IXGBE_RX_RSC_ENABLED, 222 __IXGBE_RX_CSUM_UDP_ZERO_ERR, 223 __IXGBE_RX_FCOE, 224 }; 225 226 struct ixgbe_fwd_adapter { 227 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 228 struct net_device *netdev; 229 struct ixgbe_adapter *real_adapter; 230 unsigned int tx_base_queue; 231 unsigned int rx_base_queue; 232 int pool; 233 }; 234 235 #define check_for_tx_hang(ring) \ 236 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 237 #define set_check_for_tx_hang(ring) \ 238 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 239 #define clear_check_for_tx_hang(ring) \ 240 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 241 #define ring_is_rsc_enabled(ring) \ 242 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 243 #define set_ring_rsc_enabled(ring) \ 244 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 245 #define clear_ring_rsc_enabled(ring) \ 246 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 247 struct ixgbe_ring { 248 struct ixgbe_ring *next; /* pointer to next ring in q_vector */ 249 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ 250 struct net_device *netdev; /* netdev ring belongs to */ 251 struct device *dev; /* device for DMA mapping */ 252 struct ixgbe_fwd_adapter *l2_accel_priv; 253 void *desc; /* descriptor ring memory */ 254 union { 255 struct ixgbe_tx_buffer *tx_buffer_info; 256 struct ixgbe_rx_buffer *rx_buffer_info; 257 }; 258 unsigned long state; 259 u8 __iomem *tail; 260 dma_addr_t dma; /* phys. address of descriptor ring */ 261 unsigned int size; /* length in bytes */ 262 263 u16 count; /* amount of descriptors */ 264 265 u8 queue_index; /* needed for multiqueue queue management */ 266 u8 reg_idx; /* holds the special value that gets 267 * the hardware register offset 268 * associated with this ring, which is 269 * different for DCB and RSS modes 270 */ 271 u16 next_to_use; 272 u16 next_to_clean; 273 274 union { 275 u16 next_to_alloc; 276 struct { 277 u8 atr_sample_rate; 278 u8 atr_count; 279 }; 280 }; 281 282 u8 dcb_tc; 283 struct ixgbe_queue_stats stats; 284 struct u64_stats_sync syncp; 285 union { 286 struct ixgbe_tx_queue_stats tx_stats; 287 struct ixgbe_rx_queue_stats rx_stats; 288 }; 289 } ____cacheline_internodealigned_in_smp; 290 291 enum ixgbe_ring_f_enum { 292 RING_F_NONE = 0, 293 RING_F_VMDQ, /* SR-IOV uses the same ring feature */ 294 RING_F_RSS, 295 RING_F_FDIR, 296 #ifdef IXGBE_FCOE 297 RING_F_FCOE, 298 #endif /* IXGBE_FCOE */ 299 300 RING_F_ARRAY_SIZE /* must be last in enum set */ 301 }; 302 303 #define IXGBE_MAX_RSS_INDICES 16 304 #define IXGBE_MAX_VMDQ_INDICES 64 305 #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */ 306 #define IXGBE_MAX_FCOE_INDICES 8 307 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 308 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 309 #define IXGBE_MAX_L2A_QUEUES 4 310 #define IXGBE_MAX_L2A_QUEUES 4 311 #define IXGBE_BAD_L2A_QUEUE 3 312 #define IXGBE_MAX_MACVLANS 31 313 #define IXGBE_MAX_DCBMACVLANS 8 314 315 struct ixgbe_ring_feature { 316 u16 limit; /* upper limit on feature indices */ 317 u16 indices; /* current value of indices */ 318 u16 mask; /* Mask used for feature to ring mapping */ 319 u16 offset; /* offset to start of feature */ 320 } ____cacheline_internodealigned_in_smp; 321 322 #define IXGBE_82599_VMDQ_8Q_MASK 0x78 323 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C 324 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E 325 326 /* 327 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since 328 * this is twice the size of a half page we need to double the page order 329 * for FCoE enabled Rx queues. 330 */ 331 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring) 332 { 333 #ifdef IXGBE_FCOE 334 if (test_bit(__IXGBE_RX_FCOE, &ring->state)) 335 return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K : 336 IXGBE_RXBUFFER_3K; 337 #endif 338 return IXGBE_RXBUFFER_2K; 339 } 340 341 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) 342 { 343 #ifdef IXGBE_FCOE 344 if (test_bit(__IXGBE_RX_FCOE, &ring->state)) 345 return (PAGE_SIZE < 8192) ? 1 : 0; 346 #endif 347 return 0; 348 } 349 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) 350 351 struct ixgbe_ring_container { 352 struct ixgbe_ring *ring; /* pointer to linked list of rings */ 353 unsigned int total_bytes; /* total bytes processed this int */ 354 unsigned int total_packets; /* total packets processed this int */ 355 u16 work_limit; /* total work allowed per interrupt */ 356 u8 count; /* total number of rings in vector */ 357 u8 itr; /* current ITR setting for ring */ 358 }; 359 360 /* iterator for handling rings in ring container */ 361 #define ixgbe_for_each_ring(pos, head) \ 362 for (pos = (head).ring; pos != NULL; pos = pos->next) 363 364 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ 365 ? 8 : 1) 366 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS 367 368 /* MAX_Q_VECTORS of these are allocated, 369 * but we only use one per queue-specific vector. 370 */ 371 struct ixgbe_q_vector { 372 struct ixgbe_adapter *adapter; 373 #ifdef CONFIG_IXGBE_DCA 374 int cpu; /* CPU for DCA */ 375 #endif 376 u16 v_idx; /* index of q_vector within array, also used for 377 * finding the bit in EICR and friends that 378 * represents the vector for this ring */ 379 u16 itr; /* Interrupt throttle rate written to EITR */ 380 struct ixgbe_ring_container rx, tx; 381 382 struct napi_struct napi; 383 cpumask_t affinity_mask; 384 int numa_node; 385 struct rcu_head rcu; /* to avoid race with update stats on free */ 386 char name[IFNAMSIZ + 9]; 387 388 #ifdef CONFIG_NET_RX_BUSY_POLL 389 unsigned int state; 390 #define IXGBE_QV_STATE_IDLE 0 391 #define IXGBE_QV_STATE_NAPI 1 /* NAPI owns this QV */ 392 #define IXGBE_QV_STATE_POLL 2 /* poll owns this QV */ 393 #define IXGBE_QV_STATE_DISABLED 4 /* QV is disabled */ 394 #define IXGBE_QV_OWNED (IXGBE_QV_STATE_NAPI | IXGBE_QV_STATE_POLL) 395 #define IXGBE_QV_LOCKED (IXGBE_QV_OWNED | IXGBE_QV_STATE_DISABLED) 396 #define IXGBE_QV_STATE_NAPI_YIELD 8 /* NAPI yielded this QV */ 397 #define IXGBE_QV_STATE_POLL_YIELD 16 /* poll yielded this QV */ 398 #define IXGBE_QV_YIELD (IXGBE_QV_STATE_NAPI_YIELD | IXGBE_QV_STATE_POLL_YIELD) 399 #define IXGBE_QV_USER_PEND (IXGBE_QV_STATE_POLL | IXGBE_QV_STATE_POLL_YIELD) 400 spinlock_t lock; 401 #endif /* CONFIG_NET_RX_BUSY_POLL */ 402 403 /* for dynamic allocation of rings associated with this q_vector */ 404 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp; 405 }; 406 #ifdef CONFIG_NET_RX_BUSY_POLL 407 static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) 408 { 409 410 spin_lock_init(&q_vector->lock); 411 q_vector->state = IXGBE_QV_STATE_IDLE; 412 } 413 414 /* called from the device poll routine to get ownership of a q_vector */ 415 static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) 416 { 417 int rc = true; 418 spin_lock_bh(&q_vector->lock); 419 if (q_vector->state & IXGBE_QV_LOCKED) { 420 WARN_ON(q_vector->state & IXGBE_QV_STATE_NAPI); 421 q_vector->state |= IXGBE_QV_STATE_NAPI_YIELD; 422 rc = false; 423 #ifdef BP_EXTENDED_STATS 424 q_vector->tx.ring->stats.yields++; 425 #endif 426 } else { 427 /* we don't care if someone yielded */ 428 q_vector->state = IXGBE_QV_STATE_NAPI; 429 } 430 spin_unlock_bh(&q_vector->lock); 431 return rc; 432 } 433 434 /* returns true is someone tried to get the qv while napi had it */ 435 static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) 436 { 437 int rc = false; 438 spin_lock_bh(&q_vector->lock); 439 WARN_ON(q_vector->state & (IXGBE_QV_STATE_POLL | 440 IXGBE_QV_STATE_NAPI_YIELD)); 441 442 if (q_vector->state & IXGBE_QV_STATE_POLL_YIELD) 443 rc = true; 444 /* will reset state to idle, unless QV is disabled */ 445 q_vector->state &= IXGBE_QV_STATE_DISABLED; 446 spin_unlock_bh(&q_vector->lock); 447 return rc; 448 } 449 450 /* called from ixgbe_low_latency_poll() */ 451 static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) 452 { 453 int rc = true; 454 spin_lock_bh(&q_vector->lock); 455 if ((q_vector->state & IXGBE_QV_LOCKED)) { 456 q_vector->state |= IXGBE_QV_STATE_POLL_YIELD; 457 rc = false; 458 #ifdef BP_EXTENDED_STATS 459 q_vector->rx.ring->stats.yields++; 460 #endif 461 } else { 462 /* preserve yield marks */ 463 q_vector->state |= IXGBE_QV_STATE_POLL; 464 } 465 spin_unlock_bh(&q_vector->lock); 466 return rc; 467 } 468 469 /* returns true if someone tried to get the qv while it was locked */ 470 static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) 471 { 472 int rc = false; 473 spin_lock_bh(&q_vector->lock); 474 WARN_ON(q_vector->state & (IXGBE_QV_STATE_NAPI)); 475 476 if (q_vector->state & IXGBE_QV_STATE_POLL_YIELD) 477 rc = true; 478 /* will reset state to idle, unless QV is disabled */ 479 q_vector->state &= IXGBE_QV_STATE_DISABLED; 480 spin_unlock_bh(&q_vector->lock); 481 return rc; 482 } 483 484 /* true if a socket is polling, even if it did not get the lock */ 485 static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) 486 { 487 WARN_ON(!(q_vector->state & IXGBE_QV_OWNED)); 488 return q_vector->state & IXGBE_QV_USER_PEND; 489 } 490 491 /* false if QV is currently owned */ 492 static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) 493 { 494 int rc = true; 495 spin_lock_bh(&q_vector->lock); 496 if (q_vector->state & IXGBE_QV_OWNED) 497 rc = false; 498 q_vector->state |= IXGBE_QV_STATE_DISABLED; 499 spin_unlock_bh(&q_vector->lock); 500 501 return rc; 502 } 503 504 #else /* CONFIG_NET_RX_BUSY_POLL */ 505 static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) 506 { 507 } 508 509 static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) 510 { 511 return true; 512 } 513 514 static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) 515 { 516 return false; 517 } 518 519 static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) 520 { 521 return false; 522 } 523 524 static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) 525 { 526 return false; 527 } 528 529 static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) 530 { 531 return false; 532 } 533 534 static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) 535 { 536 return true; 537 } 538 539 #endif /* CONFIG_NET_RX_BUSY_POLL */ 540 541 #ifdef CONFIG_IXGBE_HWMON 542 543 #define IXGBE_HWMON_TYPE_LOC 0 544 #define IXGBE_HWMON_TYPE_TEMP 1 545 #define IXGBE_HWMON_TYPE_CAUTION 2 546 #define IXGBE_HWMON_TYPE_MAX 3 547 548 struct hwmon_attr { 549 struct device_attribute dev_attr; 550 struct ixgbe_hw *hw; 551 struct ixgbe_thermal_diode_data *sensor; 552 char name[12]; 553 }; 554 555 struct hwmon_buff { 556 struct attribute_group group; 557 const struct attribute_group *groups[2]; 558 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1]; 559 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4]; 560 unsigned int n_hwmon; 561 }; 562 #endif /* CONFIG_IXGBE_HWMON */ 563 564 /* 565 * microsecond values for various ITR rates shifted by 2 to fit itr register 566 * with the first 3 bits reserved 0 567 */ 568 #define IXGBE_MIN_RSC_ITR 24 569 #define IXGBE_100K_ITR 40 570 #define IXGBE_20K_ITR 200 571 #define IXGBE_10K_ITR 400 572 #define IXGBE_8K_ITR 500 573 574 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ 575 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, 576 const u32 stat_err_bits) 577 { 578 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 579 } 580 581 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) 582 { 583 u16 ntc = ring->next_to_clean; 584 u16 ntu = ring->next_to_use; 585 586 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 587 } 588 589 static inline void ixgbe_write_tail(struct ixgbe_ring *ring, u32 value) 590 { 591 writel(value, ring->tail); 592 } 593 594 #define IXGBE_RX_DESC(R, i) \ 595 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) 596 #define IXGBE_TX_DESC(R, i) \ 597 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) 598 #define IXGBE_TX_CTXTDESC(R, i) \ 599 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) 600 601 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ 602 #ifdef IXGBE_FCOE 603 /* Use 3K as the baby jumbo frame size for FCoE */ 604 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 605 #endif /* IXGBE_FCOE */ 606 607 #define OTHER_VECTOR 1 608 #define NON_Q_VECTORS (OTHER_VECTOR) 609 610 #define MAX_MSIX_VECTORS_82599 64 611 #define MAX_Q_VECTORS_82599 64 612 #define MAX_MSIX_VECTORS_82598 18 613 #define MAX_Q_VECTORS_82598 16 614 615 struct ixgbe_mac_addr { 616 u8 addr[ETH_ALEN]; 617 u16 queue; 618 u16 state; /* bitmask */ 619 }; 620 #define IXGBE_MAC_STATE_DEFAULT 0x1 621 #define IXGBE_MAC_STATE_MODIFIED 0x2 622 #define IXGBE_MAC_STATE_IN_USE 0x4 623 624 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599 625 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 626 627 #define MIN_MSIX_Q_VECTORS 1 628 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) 629 630 /* default to trying for four seconds */ 631 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) 632 633 /* board specific private data structure */ 634 struct ixgbe_adapter { 635 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 636 /* OS defined structs */ 637 struct net_device *netdev; 638 struct pci_dev *pdev; 639 640 unsigned long state; 641 642 /* Some features need tri-state capability, 643 * thus the additional *_CAPABLE flags. 644 */ 645 u32 flags; 646 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 0) 647 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1) 648 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 2) 649 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3) 650 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 4) 651 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 5) 652 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 6) 653 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 7) 654 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8) 655 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 9) 656 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 10) 657 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 11) 658 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 12) 659 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 13) 660 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 14) 661 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 15) 662 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 16) 663 #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 17) 664 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 18) 665 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 19) 666 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 20) 667 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 21) 668 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 22) 669 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 23) 670 671 u32 flags2; 672 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1 << 0) 673 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1) 674 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2) 675 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3) 676 #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4) 677 #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5) 678 #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6) 679 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7) 680 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8) 681 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9) 682 #define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 10) 683 #define IXGBE_FLAG2_BRIDGE_MODE_VEB (u32)(1 << 11) 684 685 /* Tx fast path data */ 686 int num_tx_queues; 687 u16 tx_itr_setting; 688 u16 tx_work_limit; 689 690 /* Rx fast path data */ 691 int num_rx_queues; 692 u16 rx_itr_setting; 693 694 /* TX */ 695 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; 696 697 u64 restart_queue; 698 u64 lsc_int; 699 u32 tx_timeout_count; 700 701 /* RX */ 702 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; 703 int num_rx_pools; /* == num_rx_queues in 82598 */ 704 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ 705 u64 hw_csum_rx_error; 706 u64 hw_rx_no_dma_resources; 707 u64 rsc_total_count; 708 u64 rsc_total_flush; 709 u64 non_eop_descs; 710 u32 alloc_rx_page_failed; 711 u32 alloc_rx_buff_failed; 712 713 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; 714 715 /* DCB parameters */ 716 struct ieee_pfc *ixgbe_ieee_pfc; 717 struct ieee_ets *ixgbe_ieee_ets; 718 struct ixgbe_dcb_config dcb_cfg; 719 struct ixgbe_dcb_config temp_dcb_cfg; 720 u8 dcb_set_bitmap; 721 u8 dcbx_cap; 722 enum ixgbe_fc_mode last_lfc_mode; 723 724 int num_q_vectors; /* current number of q_vectors for device */ 725 int max_q_vectors; /* true count of q_vectors for device */ 726 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; 727 struct msix_entry *msix_entries; 728 729 u32 test_icr; 730 struct ixgbe_ring test_tx_ring; 731 struct ixgbe_ring test_rx_ring; 732 733 /* structs defined in ixgbe_hw.h */ 734 struct ixgbe_hw hw; 735 u16 msg_enable; 736 struct ixgbe_hw_stats stats; 737 738 u64 tx_busy; 739 unsigned int tx_ring_count; 740 unsigned int rx_ring_count; 741 742 u32 link_speed; 743 bool link_up; 744 unsigned long link_check_timeout; 745 746 struct timer_list service_timer; 747 struct work_struct service_task; 748 749 struct hlist_head fdir_filter_list; 750 unsigned long fdir_overflow; /* number of times ATR was backed off */ 751 union ixgbe_atr_input fdir_mask; 752 int fdir_filter_count; 753 u32 fdir_pballoc; 754 u32 atr_sample_rate; 755 spinlock_t fdir_perfect_lock; 756 757 #ifdef IXGBE_FCOE 758 struct ixgbe_fcoe fcoe; 759 #endif /* IXGBE_FCOE */ 760 u8 __iomem *io_addr; /* Mainly for iounmap use */ 761 u32 wol; 762 763 u16 bd_number; 764 765 u16 eeprom_verh; 766 u16 eeprom_verl; 767 u16 eeprom_cap; 768 769 u32 interrupt_event; 770 u32 led_reg; 771 772 struct ptp_clock *ptp_clock; 773 struct ptp_clock_info ptp_caps; 774 struct work_struct ptp_tx_work; 775 struct sk_buff *ptp_tx_skb; 776 struct hwtstamp_config tstamp_config; 777 unsigned long ptp_tx_start; 778 unsigned long last_overflow_check; 779 unsigned long last_rx_ptp_check; 780 unsigned long last_rx_timestamp; 781 spinlock_t tmreg_lock; 782 struct cyclecounter cc; 783 struct timecounter tc; 784 u32 base_incval; 785 786 /* SR-IOV */ 787 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); 788 unsigned int num_vfs; 789 struct vf_data_storage *vfinfo; 790 int vf_rate_link_speed; 791 struct vf_macvlans vf_mvs; 792 struct vf_macvlans *mv_list; 793 794 u32 timer_event_accumulator; 795 u32 vferr_refcount; 796 struct ixgbe_mac_addr *mac_table; 797 struct kobject *info_kobj; 798 #ifdef CONFIG_IXGBE_HWMON 799 struct hwmon_buff *ixgbe_hwmon_buff; 800 #endif /* CONFIG_IXGBE_HWMON */ 801 #ifdef CONFIG_DEBUG_FS 802 struct dentry *ixgbe_dbg_adapter; 803 #endif /*CONFIG_DEBUG_FS*/ 804 805 u8 default_up; 806 unsigned long fwd_bitmask; /* Bitmask indicating in use pools */ 807 }; 808 809 struct ixgbe_fdir_filter { 810 struct hlist_node fdir_node; 811 union ixgbe_atr_input filter; 812 u16 sw_idx; 813 u16 action; 814 }; 815 816 enum ixgbe_state_t { 817 __IXGBE_TESTING, 818 __IXGBE_RESETTING, 819 __IXGBE_DOWN, 820 __IXGBE_DISABLED, 821 __IXGBE_REMOVING, 822 __IXGBE_SERVICE_SCHED, 823 __IXGBE_SERVICE_INITED, 824 __IXGBE_IN_SFP_INIT, 825 __IXGBE_PTP_RUNNING, 826 __IXGBE_PTP_TX_IN_PROGRESS, 827 }; 828 829 struct ixgbe_cb { 830 union { /* Union defining head/tail partner */ 831 struct sk_buff *head; 832 struct sk_buff *tail; 833 }; 834 dma_addr_t dma; 835 u16 append_cnt; 836 bool page_released; 837 }; 838 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) 839 840 enum ixgbe_boards { 841 board_82598, 842 board_82599, 843 board_X540, 844 }; 845 846 extern struct ixgbe_info ixgbe_82598_info; 847 extern struct ixgbe_info ixgbe_82599_info; 848 extern struct ixgbe_info ixgbe_X540_info; 849 #ifdef CONFIG_IXGBE_DCB 850 extern const struct dcbnl_rtnl_ops dcbnl_ops; 851 #endif 852 853 extern char ixgbe_driver_name[]; 854 extern const char ixgbe_driver_version[]; 855 #ifdef IXGBE_FCOE 856 extern char ixgbe_default_device_descr[]; 857 #endif /* IXGBE_FCOE */ 858 859 void ixgbe_up(struct ixgbe_adapter *adapter); 860 void ixgbe_down(struct ixgbe_adapter *adapter); 861 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); 862 void ixgbe_reset(struct ixgbe_adapter *adapter); 863 void ixgbe_set_ethtool_ops(struct net_device *netdev); 864 int ixgbe_setup_rx_resources(struct ixgbe_ring *); 865 int ixgbe_setup_tx_resources(struct ixgbe_ring *); 866 void ixgbe_free_rx_resources(struct ixgbe_ring *); 867 void ixgbe_free_tx_resources(struct ixgbe_ring *); 868 void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 869 void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 870 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *); 871 void ixgbe_update_stats(struct ixgbe_adapter *adapter); 872 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); 873 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 874 u16 subdevice_id); 875 #ifdef CONFIG_PCI_IOV 876 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter); 877 #endif 878 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 879 u8 *addr, u16 queue); 880 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 881 u8 *addr, u16 queue); 882 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); 883 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *, 884 struct ixgbe_ring *); 885 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, 886 struct ixgbe_tx_buffer *); 887 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); 888 void ixgbe_write_eitr(struct ixgbe_q_vector *); 889 int ixgbe_poll(struct napi_struct *napi, int budget); 890 int ethtool_ioctl(struct ifreq *ifr); 891 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); 892 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); 893 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); 894 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 895 union ixgbe_atr_hash_dword input, 896 union ixgbe_atr_hash_dword common, 897 u8 queue); 898 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 899 union ixgbe_atr_input *input_mask); 900 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 901 union ixgbe_atr_input *input, 902 u16 soft_id, u8 queue); 903 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 904 union ixgbe_atr_input *input, 905 u16 soft_id); 906 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 907 union ixgbe_atr_input *mask); 908 void ixgbe_set_rx_mode(struct net_device *netdev); 909 #ifdef CONFIG_IXGBE_DCB 910 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); 911 #endif 912 int ixgbe_setup_tc(struct net_device *dev, u8 tc); 913 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); 914 void ixgbe_do_reset(struct net_device *netdev); 915 #ifdef CONFIG_IXGBE_HWMON 916 void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); 917 int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); 918 #endif /* CONFIG_IXGBE_HWMON */ 919 #ifdef IXGBE_FCOE 920 void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); 921 int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, 922 u8 *hdr_len); 923 int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, 924 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb); 925 int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, 926 struct scatterlist *sgl, unsigned int sgc); 927 int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, 928 struct scatterlist *sgl, unsigned int sgc); 929 int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); 930 int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 931 void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 932 int ixgbe_fcoe_enable(struct net_device *netdev); 933 int ixgbe_fcoe_disable(struct net_device *netdev); 934 #ifdef CONFIG_IXGBE_DCB 935 u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); 936 u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); 937 #endif /* CONFIG_IXGBE_DCB */ 938 int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); 939 int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, 940 struct netdev_fcoe_hbainfo *info); 941 u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); 942 #endif /* IXGBE_FCOE */ 943 #ifdef CONFIG_DEBUG_FS 944 void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter); 945 void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter); 946 void ixgbe_dbg_init(void); 947 void ixgbe_dbg_exit(void); 948 #else 949 static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {} 950 static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {} 951 static inline void ixgbe_dbg_init(void) {} 952 static inline void ixgbe_dbg_exit(void) {} 953 #endif /* CONFIG_DEBUG_FS */ 954 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) 955 { 956 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 957 } 958 959 void ixgbe_ptp_init(struct ixgbe_adapter *adapter); 960 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter); 961 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); 962 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); 963 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter); 964 void ixgbe_ptp_rx_hwtstamp(struct ixgbe_adapter *adapter, struct sk_buff *skb); 965 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 966 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 967 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); 968 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter); 969 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr); 970 #ifdef CONFIG_PCI_IOV 971 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter); 972 #endif 973 974 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 975 struct ixgbe_adapter *adapter, 976 struct ixgbe_ring *tx_ring); 977 #endif /* _IXGBE_H_ */ 978