1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #ifndef _IXGBE_H_ 30 #define _IXGBE_H_ 31 32 #include <linux/bitops.h> 33 #include <linux/types.h> 34 #include <linux/pci.h> 35 #include <linux/netdevice.h> 36 #include <linux/cpumask.h> 37 #include <linux/aer.h> 38 #include <linux/if_vlan.h> 39 #include <linux/jiffies.h> 40 41 #include <linux/timecounter.h> 42 #include <linux/net_tstamp.h> 43 #include <linux/ptp_clock_kernel.h> 44 45 #include "ixgbe_type.h" 46 #include "ixgbe_common.h" 47 #include "ixgbe_dcb.h" 48 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) 49 #define IXGBE_FCOE 50 #include "ixgbe_fcoe.h" 51 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */ 52 #ifdef CONFIG_IXGBE_DCA 53 #include <linux/dca.h> 54 #endif 55 56 #include <net/busy_poll.h> 57 58 #ifdef CONFIG_NET_RX_BUSY_POLL 59 #define BP_EXTENDED_STATS 60 #endif 61 /* common prefix used by pr_<> macros */ 62 #undef pr_fmt 63 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 64 65 /* TX/RX descriptor defines */ 66 #define IXGBE_DEFAULT_TXD 512 67 #define IXGBE_DEFAULT_TX_WORK 256 68 #define IXGBE_MAX_TXD 4096 69 #define IXGBE_MIN_TXD 64 70 71 #if (PAGE_SIZE < 8192) 72 #define IXGBE_DEFAULT_RXD 512 73 #else 74 #define IXGBE_DEFAULT_RXD 128 75 #endif 76 #define IXGBE_MAX_RXD 4096 77 #define IXGBE_MIN_RXD 64 78 79 #define IXGBE_ETH_P_LLDP 0x88CC 80 81 /* flow control */ 82 #define IXGBE_MIN_FCRTL 0x40 83 #define IXGBE_MAX_FCRTL 0x7FF80 84 #define IXGBE_MIN_FCRTH 0x600 85 #define IXGBE_MAX_FCRTH 0x7FFF0 86 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF 87 #define IXGBE_MIN_FCPAUSE 0 88 #define IXGBE_MAX_FCPAUSE 0xFFFF 89 90 /* Supported Rx Buffer Sizes */ 91 #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ 92 #define IXGBE_RXBUFFER_2K 2048 93 #define IXGBE_RXBUFFER_3K 3072 94 #define IXGBE_RXBUFFER_4K 4096 95 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ 96 97 /* 98 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 99 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more, 100 * this adds up to 448 bytes of extra data. 101 * 102 * Since netdev_alloc_skb now allocates a page fragment we can use a value 103 * of 256 and the resultant skb will have a truesize of 960 or less. 104 */ 105 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 106 107 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 108 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 109 110 enum ixgbe_tx_flags { 111 /* cmd_type flags */ 112 IXGBE_TX_FLAGS_HW_VLAN = 0x01, 113 IXGBE_TX_FLAGS_TSO = 0x02, 114 IXGBE_TX_FLAGS_TSTAMP = 0x04, 115 116 /* olinfo flags */ 117 IXGBE_TX_FLAGS_CC = 0x08, 118 IXGBE_TX_FLAGS_IPV4 = 0x10, 119 IXGBE_TX_FLAGS_CSUM = 0x20, 120 121 /* software defined flags */ 122 IXGBE_TX_FLAGS_SW_VLAN = 0x40, 123 IXGBE_TX_FLAGS_FCOE = 0x80, 124 }; 125 126 /* VLAN info */ 127 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 128 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 129 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 130 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 131 132 #define IXGBE_MAX_VF_MC_ENTRIES 30 133 #define IXGBE_MAX_VF_FUNCTIONS 64 134 #define IXGBE_MAX_VFTA_ENTRIES 128 135 #define MAX_EMULATION_MAC_ADDRS 16 136 #define IXGBE_MAX_PF_MACVLANS 15 137 #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset) 138 #define IXGBE_82599_VF_DEVICE_ID 0x10ED 139 #define IXGBE_X540_VF_DEVICE_ID 0x1515 140 141 struct vf_data_storage { 142 unsigned char vf_mac_addresses[ETH_ALEN]; 143 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; 144 u16 num_vf_mc_hashes; 145 u16 default_vf_vlan_id; 146 u16 vlans_enabled; 147 bool clear_to_send; 148 bool pf_set_mac; 149 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 150 u16 pf_qos; 151 u16 tx_rate; 152 u16 vlan_count; 153 u8 spoofchk_enabled; 154 unsigned int vf_api; 155 }; 156 157 struct vf_macvlans { 158 struct list_head l; 159 int vf; 160 bool free; 161 bool is_macvlan; 162 u8 vf_macvlan[ETH_ALEN]; 163 }; 164 165 #define IXGBE_MAX_TXD_PWR 14 166 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) 167 168 /* Tx Descriptors needed, worst case */ 169 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) 170 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 171 172 /* wrapper around a pointer to a socket buffer, 173 * so a DMA handle can be stored along with the buffer */ 174 struct ixgbe_tx_buffer { 175 union ixgbe_adv_tx_desc *next_to_watch; 176 unsigned long time_stamp; 177 struct sk_buff *skb; 178 unsigned int bytecount; 179 unsigned short gso_segs; 180 __be16 protocol; 181 DEFINE_DMA_UNMAP_ADDR(dma); 182 DEFINE_DMA_UNMAP_LEN(len); 183 u32 tx_flags; 184 }; 185 186 struct ixgbe_rx_buffer { 187 struct sk_buff *skb; 188 dma_addr_t dma; 189 struct page *page; 190 unsigned int page_offset; 191 }; 192 193 struct ixgbe_queue_stats { 194 u64 packets; 195 u64 bytes; 196 #ifdef BP_EXTENDED_STATS 197 u64 yields; 198 u64 misses; 199 u64 cleaned; 200 #endif /* BP_EXTENDED_STATS */ 201 }; 202 203 struct ixgbe_tx_queue_stats { 204 u64 restart_queue; 205 u64 tx_busy; 206 u64 tx_done_old; 207 }; 208 209 struct ixgbe_rx_queue_stats { 210 u64 rsc_count; 211 u64 rsc_flush; 212 u64 non_eop_descs; 213 u64 alloc_rx_page_failed; 214 u64 alloc_rx_buff_failed; 215 u64 csum_err; 216 }; 217 218 enum ixgbe_ring_state_t { 219 __IXGBE_TX_FDIR_INIT_DONE, 220 __IXGBE_TX_XPS_INIT_DONE, 221 __IXGBE_TX_DETECT_HANG, 222 __IXGBE_HANG_CHECK_ARMED, 223 __IXGBE_RX_RSC_ENABLED, 224 __IXGBE_RX_CSUM_UDP_ZERO_ERR, 225 __IXGBE_RX_FCOE, 226 }; 227 228 struct ixgbe_fwd_adapter { 229 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 230 struct net_device *netdev; 231 struct ixgbe_adapter *real_adapter; 232 unsigned int tx_base_queue; 233 unsigned int rx_base_queue; 234 int pool; 235 }; 236 237 #define check_for_tx_hang(ring) \ 238 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 239 #define set_check_for_tx_hang(ring) \ 240 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 241 #define clear_check_for_tx_hang(ring) \ 242 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 243 #define ring_is_rsc_enabled(ring) \ 244 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 245 #define set_ring_rsc_enabled(ring) \ 246 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 247 #define clear_ring_rsc_enabled(ring) \ 248 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 249 struct ixgbe_ring { 250 struct ixgbe_ring *next; /* pointer to next ring in q_vector */ 251 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ 252 struct net_device *netdev; /* netdev ring belongs to */ 253 struct device *dev; /* device for DMA mapping */ 254 struct ixgbe_fwd_adapter *l2_accel_priv; 255 void *desc; /* descriptor ring memory */ 256 union { 257 struct ixgbe_tx_buffer *tx_buffer_info; 258 struct ixgbe_rx_buffer *rx_buffer_info; 259 }; 260 unsigned long state; 261 u8 __iomem *tail; 262 dma_addr_t dma; /* phys. address of descriptor ring */ 263 unsigned int size; /* length in bytes */ 264 265 u16 count; /* amount of descriptors */ 266 267 u8 queue_index; /* needed for multiqueue queue management */ 268 u8 reg_idx; /* holds the special value that gets 269 * the hardware register offset 270 * associated with this ring, which is 271 * different for DCB and RSS modes 272 */ 273 u16 next_to_use; 274 u16 next_to_clean; 275 276 union { 277 u16 next_to_alloc; 278 struct { 279 u8 atr_sample_rate; 280 u8 atr_count; 281 }; 282 }; 283 284 u8 dcb_tc; 285 struct ixgbe_queue_stats stats; 286 struct u64_stats_sync syncp; 287 union { 288 struct ixgbe_tx_queue_stats tx_stats; 289 struct ixgbe_rx_queue_stats rx_stats; 290 }; 291 } ____cacheline_internodealigned_in_smp; 292 293 enum ixgbe_ring_f_enum { 294 RING_F_NONE = 0, 295 RING_F_VMDQ, /* SR-IOV uses the same ring feature */ 296 RING_F_RSS, 297 RING_F_FDIR, 298 #ifdef IXGBE_FCOE 299 RING_F_FCOE, 300 #endif /* IXGBE_FCOE */ 301 302 RING_F_ARRAY_SIZE /* must be last in enum set */ 303 }; 304 305 #define IXGBE_MAX_RSS_INDICES 16 306 #define IXGBE_MAX_RSS_INDICES_X550 64 307 #define IXGBE_MAX_VMDQ_INDICES 64 308 #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */ 309 #define IXGBE_MAX_FCOE_INDICES 8 310 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 311 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 312 #define IXGBE_MAX_L2A_QUEUES 4 313 #define IXGBE_BAD_L2A_QUEUE 3 314 #define IXGBE_MAX_MACVLANS 31 315 #define IXGBE_MAX_DCBMACVLANS 8 316 317 struct ixgbe_ring_feature { 318 u16 limit; /* upper limit on feature indices */ 319 u16 indices; /* current value of indices */ 320 u16 mask; /* Mask used for feature to ring mapping */ 321 u16 offset; /* offset to start of feature */ 322 } ____cacheline_internodealigned_in_smp; 323 324 #define IXGBE_82599_VMDQ_8Q_MASK 0x78 325 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C 326 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E 327 328 /* 329 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since 330 * this is twice the size of a half page we need to double the page order 331 * for FCoE enabled Rx queues. 332 */ 333 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring) 334 { 335 #ifdef IXGBE_FCOE 336 if (test_bit(__IXGBE_RX_FCOE, &ring->state)) 337 return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K : 338 IXGBE_RXBUFFER_3K; 339 #endif 340 return IXGBE_RXBUFFER_2K; 341 } 342 343 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) 344 { 345 #ifdef IXGBE_FCOE 346 if (test_bit(__IXGBE_RX_FCOE, &ring->state)) 347 return (PAGE_SIZE < 8192) ? 1 : 0; 348 #endif 349 return 0; 350 } 351 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) 352 353 struct ixgbe_ring_container { 354 struct ixgbe_ring *ring; /* pointer to linked list of rings */ 355 unsigned int total_bytes; /* total bytes processed this int */ 356 unsigned int total_packets; /* total packets processed this int */ 357 u16 work_limit; /* total work allowed per interrupt */ 358 u8 count; /* total number of rings in vector */ 359 u8 itr; /* current ITR setting for ring */ 360 }; 361 362 /* iterator for handling rings in ring container */ 363 #define ixgbe_for_each_ring(pos, head) \ 364 for (pos = (head).ring; pos != NULL; pos = pos->next) 365 366 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ 367 ? 8 : 1) 368 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS 369 370 /* MAX_Q_VECTORS of these are allocated, 371 * but we only use one per queue-specific vector. 372 */ 373 struct ixgbe_q_vector { 374 struct ixgbe_adapter *adapter; 375 #ifdef CONFIG_IXGBE_DCA 376 int cpu; /* CPU for DCA */ 377 #endif 378 u16 v_idx; /* index of q_vector within array, also used for 379 * finding the bit in EICR and friends that 380 * represents the vector for this ring */ 381 u16 itr; /* Interrupt throttle rate written to EITR */ 382 struct ixgbe_ring_container rx, tx; 383 384 struct napi_struct napi; 385 cpumask_t affinity_mask; 386 int numa_node; 387 struct rcu_head rcu; /* to avoid race with update stats on free */ 388 char name[IFNAMSIZ + 9]; 389 390 #ifdef CONFIG_NET_RX_BUSY_POLL 391 atomic_t state; 392 #endif /* CONFIG_NET_RX_BUSY_POLL */ 393 394 /* for dynamic allocation of rings associated with this q_vector */ 395 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp; 396 }; 397 398 #ifdef CONFIG_NET_RX_BUSY_POLL 399 enum ixgbe_qv_state_t { 400 IXGBE_QV_STATE_IDLE = 0, 401 IXGBE_QV_STATE_NAPI, 402 IXGBE_QV_STATE_POLL, 403 IXGBE_QV_STATE_DISABLE 404 }; 405 406 static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) 407 { 408 /* reset state to idle */ 409 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); 410 } 411 412 /* called from the device poll routine to get ownership of a q_vector */ 413 static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) 414 { 415 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, 416 IXGBE_QV_STATE_NAPI); 417 #ifdef BP_EXTENDED_STATS 418 if (rc != IXGBE_QV_STATE_IDLE) 419 q_vector->tx.ring->stats.yields++; 420 #endif 421 422 return rc == IXGBE_QV_STATE_IDLE; 423 } 424 425 /* returns true is someone tried to get the qv while napi had it */ 426 static inline void ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) 427 { 428 WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_NAPI); 429 430 /* flush any outstanding Rx frames */ 431 if (q_vector->napi.gro_list) 432 napi_gro_flush(&q_vector->napi, false); 433 434 /* reset state to idle */ 435 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); 436 } 437 438 /* called from ixgbe_low_latency_poll() */ 439 static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) 440 { 441 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, 442 IXGBE_QV_STATE_POLL); 443 #ifdef BP_EXTENDED_STATS 444 if (rc != IXGBE_QV_STATE_IDLE) 445 q_vector->tx.ring->stats.yields++; 446 #endif 447 return rc == IXGBE_QV_STATE_IDLE; 448 } 449 450 /* returns true if someone tried to get the qv while it was locked */ 451 static inline void ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) 452 { 453 WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_POLL); 454 455 /* reset state to idle */ 456 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); 457 } 458 459 /* true if a socket is polling, even if it did not get the lock */ 460 static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) 461 { 462 return atomic_read(&q_vector->state) == IXGBE_QV_STATE_POLL; 463 } 464 465 /* false if QV is currently owned */ 466 static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) 467 { 468 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, 469 IXGBE_QV_STATE_DISABLE); 470 471 return rc == IXGBE_QV_STATE_IDLE; 472 } 473 474 #else /* CONFIG_NET_RX_BUSY_POLL */ 475 static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) 476 { 477 } 478 479 static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) 480 { 481 return true; 482 } 483 484 static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) 485 { 486 return false; 487 } 488 489 static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) 490 { 491 return false; 492 } 493 494 static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) 495 { 496 return false; 497 } 498 499 static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) 500 { 501 return false; 502 } 503 504 static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) 505 { 506 return true; 507 } 508 509 #endif /* CONFIG_NET_RX_BUSY_POLL */ 510 511 #ifdef CONFIG_IXGBE_HWMON 512 513 #define IXGBE_HWMON_TYPE_LOC 0 514 #define IXGBE_HWMON_TYPE_TEMP 1 515 #define IXGBE_HWMON_TYPE_CAUTION 2 516 #define IXGBE_HWMON_TYPE_MAX 3 517 518 struct hwmon_attr { 519 struct device_attribute dev_attr; 520 struct ixgbe_hw *hw; 521 struct ixgbe_thermal_diode_data *sensor; 522 char name[12]; 523 }; 524 525 struct hwmon_buff { 526 struct attribute_group group; 527 const struct attribute_group *groups[2]; 528 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1]; 529 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4]; 530 unsigned int n_hwmon; 531 }; 532 #endif /* CONFIG_IXGBE_HWMON */ 533 534 /* 535 * microsecond values for various ITR rates shifted by 2 to fit itr register 536 * with the first 3 bits reserved 0 537 */ 538 #define IXGBE_MIN_RSC_ITR 24 539 #define IXGBE_100K_ITR 40 540 #define IXGBE_20K_ITR 200 541 #define IXGBE_10K_ITR 400 542 #define IXGBE_8K_ITR 500 543 544 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ 545 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, 546 const u32 stat_err_bits) 547 { 548 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 549 } 550 551 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) 552 { 553 u16 ntc = ring->next_to_clean; 554 u16 ntu = ring->next_to_use; 555 556 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 557 } 558 559 #define IXGBE_RX_DESC(R, i) \ 560 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) 561 #define IXGBE_TX_DESC(R, i) \ 562 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) 563 #define IXGBE_TX_CTXTDESC(R, i) \ 564 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) 565 566 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ 567 #ifdef IXGBE_FCOE 568 /* Use 3K as the baby jumbo frame size for FCoE */ 569 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 570 #endif /* IXGBE_FCOE */ 571 572 #define OTHER_VECTOR 1 573 #define NON_Q_VECTORS (OTHER_VECTOR) 574 575 #define MAX_MSIX_VECTORS_82599 64 576 #define MAX_Q_VECTORS_82599 64 577 #define MAX_MSIX_VECTORS_82598 18 578 #define MAX_Q_VECTORS_82598 16 579 580 struct ixgbe_mac_addr { 581 u8 addr[ETH_ALEN]; 582 u16 queue; 583 u16 state; /* bitmask */ 584 }; 585 #define IXGBE_MAC_STATE_DEFAULT 0x1 586 #define IXGBE_MAC_STATE_MODIFIED 0x2 587 #define IXGBE_MAC_STATE_IN_USE 0x4 588 589 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599 590 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 591 592 #define MIN_MSIX_Q_VECTORS 1 593 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) 594 595 /* default to trying for four seconds */ 596 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) 597 598 /* board specific private data structure */ 599 struct ixgbe_adapter { 600 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 601 /* OS defined structs */ 602 struct net_device *netdev; 603 struct pci_dev *pdev; 604 605 unsigned long state; 606 607 /* Some features need tri-state capability, 608 * thus the additional *_CAPABLE flags. 609 */ 610 u32 flags; 611 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1) 612 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3) 613 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 4) 614 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 5) 615 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 6) 616 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 7) 617 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8) 618 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 9) 619 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 10) 620 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 11) 621 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 12) 622 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 13) 623 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 14) 624 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 15) 625 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 16) 626 #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 17) 627 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 18) 628 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 19) 629 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 20) 630 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 21) 631 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 22) 632 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 23) 633 634 u32 flags2; 635 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1 << 0) 636 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1) 637 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2) 638 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3) 639 #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4) 640 #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5) 641 #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6) 642 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7) 643 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8) 644 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9) 645 #define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 10) 646 #define IXGBE_FLAG2_BRIDGE_MODE_VEB (u32)(1 << 11) 647 648 /* Tx fast path data */ 649 int num_tx_queues; 650 u16 tx_itr_setting; 651 u16 tx_work_limit; 652 653 /* Rx fast path data */ 654 int num_rx_queues; 655 u16 rx_itr_setting; 656 657 /* TX */ 658 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; 659 660 u64 restart_queue; 661 u64 lsc_int; 662 u32 tx_timeout_count; 663 664 /* RX */ 665 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; 666 int num_rx_pools; /* == num_rx_queues in 82598 */ 667 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ 668 u64 hw_csum_rx_error; 669 u64 hw_rx_no_dma_resources; 670 u64 rsc_total_count; 671 u64 rsc_total_flush; 672 u64 non_eop_descs; 673 u32 alloc_rx_page_failed; 674 u32 alloc_rx_buff_failed; 675 676 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; 677 678 /* DCB parameters */ 679 struct ieee_pfc *ixgbe_ieee_pfc; 680 struct ieee_ets *ixgbe_ieee_ets; 681 struct ixgbe_dcb_config dcb_cfg; 682 struct ixgbe_dcb_config temp_dcb_cfg; 683 u8 dcb_set_bitmap; 684 u8 dcbx_cap; 685 enum ixgbe_fc_mode last_lfc_mode; 686 687 int num_q_vectors; /* current number of q_vectors for device */ 688 int max_q_vectors; /* true count of q_vectors for device */ 689 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; 690 struct msix_entry *msix_entries; 691 692 u32 test_icr; 693 struct ixgbe_ring test_tx_ring; 694 struct ixgbe_ring test_rx_ring; 695 696 /* structs defined in ixgbe_hw.h */ 697 struct ixgbe_hw hw; 698 u16 msg_enable; 699 struct ixgbe_hw_stats stats; 700 701 u64 tx_busy; 702 unsigned int tx_ring_count; 703 unsigned int rx_ring_count; 704 705 u32 link_speed; 706 bool link_up; 707 unsigned long link_check_timeout; 708 709 struct timer_list service_timer; 710 struct work_struct service_task; 711 712 struct hlist_head fdir_filter_list; 713 unsigned long fdir_overflow; /* number of times ATR was backed off */ 714 union ixgbe_atr_input fdir_mask; 715 int fdir_filter_count; 716 u32 fdir_pballoc; 717 u32 atr_sample_rate; 718 spinlock_t fdir_perfect_lock; 719 720 #ifdef IXGBE_FCOE 721 struct ixgbe_fcoe fcoe; 722 #endif /* IXGBE_FCOE */ 723 u8 __iomem *io_addr; /* Mainly for iounmap use */ 724 u32 wol; 725 726 u16 eeprom_verh; 727 u16 eeprom_verl; 728 u16 eeprom_cap; 729 730 u32 interrupt_event; 731 u32 led_reg; 732 733 struct ptp_clock *ptp_clock; 734 struct ptp_clock_info ptp_caps; 735 struct work_struct ptp_tx_work; 736 struct sk_buff *ptp_tx_skb; 737 struct hwtstamp_config tstamp_config; 738 unsigned long ptp_tx_start; 739 unsigned long last_overflow_check; 740 unsigned long last_rx_ptp_check; 741 unsigned long last_rx_timestamp; 742 spinlock_t tmreg_lock; 743 struct cyclecounter cc; 744 struct timecounter tc; 745 u32 base_incval; 746 747 /* SR-IOV */ 748 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); 749 unsigned int num_vfs; 750 struct vf_data_storage *vfinfo; 751 int vf_rate_link_speed; 752 struct vf_macvlans vf_mvs; 753 struct vf_macvlans *mv_list; 754 755 u32 timer_event_accumulator; 756 u32 vferr_refcount; 757 struct ixgbe_mac_addr *mac_table; 758 u16 vxlan_port; 759 struct kobject *info_kobj; 760 #ifdef CONFIG_IXGBE_HWMON 761 struct hwmon_buff *ixgbe_hwmon_buff; 762 #endif /* CONFIG_IXGBE_HWMON */ 763 #ifdef CONFIG_DEBUG_FS 764 struct dentry *ixgbe_dbg_adapter; 765 #endif /*CONFIG_DEBUG_FS*/ 766 767 u8 default_up; 768 unsigned long fwd_bitmask; /* Bitmask indicating in use pools */ 769 }; 770 771 static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter) 772 { 773 switch (adapter->hw.mac.type) { 774 case ixgbe_mac_82598EB: 775 case ixgbe_mac_82599EB: 776 case ixgbe_mac_X540: 777 return IXGBE_MAX_RSS_INDICES; 778 case ixgbe_mac_X550: 779 case ixgbe_mac_X550EM_x: 780 return IXGBE_MAX_RSS_INDICES_X550; 781 default: 782 return 0; 783 } 784 } 785 786 struct ixgbe_fdir_filter { 787 struct hlist_node fdir_node; 788 union ixgbe_atr_input filter; 789 u16 sw_idx; 790 u16 action; 791 }; 792 793 enum ixgbe_state_t { 794 __IXGBE_TESTING, 795 __IXGBE_RESETTING, 796 __IXGBE_DOWN, 797 __IXGBE_DISABLED, 798 __IXGBE_REMOVING, 799 __IXGBE_SERVICE_SCHED, 800 __IXGBE_SERVICE_INITED, 801 __IXGBE_IN_SFP_INIT, 802 __IXGBE_PTP_RUNNING, 803 __IXGBE_PTP_TX_IN_PROGRESS, 804 }; 805 806 struct ixgbe_cb { 807 union { /* Union defining head/tail partner */ 808 struct sk_buff *head; 809 struct sk_buff *tail; 810 }; 811 dma_addr_t dma; 812 u16 append_cnt; 813 bool page_released; 814 }; 815 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) 816 817 enum ixgbe_boards { 818 board_82598, 819 board_82599, 820 board_X540, 821 board_X550, 822 board_X550EM_x, 823 }; 824 825 extern struct ixgbe_info ixgbe_82598_info; 826 extern struct ixgbe_info ixgbe_82599_info; 827 extern struct ixgbe_info ixgbe_X540_info; 828 extern struct ixgbe_info ixgbe_X550_info; 829 extern struct ixgbe_info ixgbe_X550EM_x_info; 830 #ifdef CONFIG_IXGBE_DCB 831 extern const struct dcbnl_rtnl_ops dcbnl_ops; 832 #endif 833 834 extern char ixgbe_driver_name[]; 835 extern const char ixgbe_driver_version[]; 836 #ifdef IXGBE_FCOE 837 extern char ixgbe_default_device_descr[]; 838 #endif /* IXGBE_FCOE */ 839 840 void ixgbe_up(struct ixgbe_adapter *adapter); 841 void ixgbe_down(struct ixgbe_adapter *adapter); 842 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); 843 void ixgbe_reset(struct ixgbe_adapter *adapter); 844 void ixgbe_set_ethtool_ops(struct net_device *netdev); 845 int ixgbe_setup_rx_resources(struct ixgbe_ring *); 846 int ixgbe_setup_tx_resources(struct ixgbe_ring *); 847 void ixgbe_free_rx_resources(struct ixgbe_ring *); 848 void ixgbe_free_tx_resources(struct ixgbe_ring *); 849 void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 850 void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 851 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *); 852 void ixgbe_update_stats(struct ixgbe_adapter *adapter); 853 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); 854 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 855 u16 subdevice_id); 856 #ifdef CONFIG_PCI_IOV 857 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter); 858 #endif 859 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 860 u8 *addr, u16 queue); 861 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 862 u8 *addr, u16 queue); 863 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); 864 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *, 865 struct ixgbe_ring *); 866 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, 867 struct ixgbe_tx_buffer *); 868 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); 869 void ixgbe_write_eitr(struct ixgbe_q_vector *); 870 int ixgbe_poll(struct napi_struct *napi, int budget); 871 int ethtool_ioctl(struct ifreq *ifr); 872 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); 873 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); 874 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); 875 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 876 union ixgbe_atr_hash_dword input, 877 union ixgbe_atr_hash_dword common, 878 u8 queue); 879 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 880 union ixgbe_atr_input *input_mask); 881 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 882 union ixgbe_atr_input *input, 883 u16 soft_id, u8 queue); 884 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 885 union ixgbe_atr_input *input, 886 u16 soft_id); 887 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 888 union ixgbe_atr_input *mask); 889 void ixgbe_set_rx_mode(struct net_device *netdev); 890 #ifdef CONFIG_IXGBE_DCB 891 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); 892 #endif 893 int ixgbe_setup_tc(struct net_device *dev, u8 tc); 894 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); 895 void ixgbe_do_reset(struct net_device *netdev); 896 #ifdef CONFIG_IXGBE_HWMON 897 void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); 898 int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); 899 #endif /* CONFIG_IXGBE_HWMON */ 900 #ifdef IXGBE_FCOE 901 void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); 902 int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, 903 u8 *hdr_len); 904 int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, 905 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb); 906 int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, 907 struct scatterlist *sgl, unsigned int sgc); 908 int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, 909 struct scatterlist *sgl, unsigned int sgc); 910 int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); 911 int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 912 void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 913 int ixgbe_fcoe_enable(struct net_device *netdev); 914 int ixgbe_fcoe_disable(struct net_device *netdev); 915 #ifdef CONFIG_IXGBE_DCB 916 u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); 917 u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); 918 #endif /* CONFIG_IXGBE_DCB */ 919 int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); 920 int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, 921 struct netdev_fcoe_hbainfo *info); 922 u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); 923 #endif /* IXGBE_FCOE */ 924 #ifdef CONFIG_DEBUG_FS 925 void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter); 926 void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter); 927 void ixgbe_dbg_init(void); 928 void ixgbe_dbg_exit(void); 929 #else 930 static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {} 931 static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {} 932 static inline void ixgbe_dbg_init(void) {} 933 static inline void ixgbe_dbg_exit(void) {} 934 #endif /* CONFIG_DEBUG_FS */ 935 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) 936 { 937 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 938 } 939 940 void ixgbe_ptp_init(struct ixgbe_adapter *adapter); 941 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter); 942 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); 943 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); 944 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter); 945 void ixgbe_ptp_rx_hwtstamp(struct ixgbe_adapter *adapter, struct sk_buff *skb); 946 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 947 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 948 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); 949 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter); 950 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr); 951 #ifdef CONFIG_PCI_IOV 952 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter); 953 #endif 954 955 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 956 struct ixgbe_adapter *adapter, 957 struct ixgbe_ring *tx_ring); 958 #endif /* _IXGBE_H_ */ 959