1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #ifndef _IXGBE_H_ 5 #define _IXGBE_H_ 6 7 #include <linux/bitops.h> 8 #include <linux/types.h> 9 #include <linux/pci.h> 10 #include <linux/netdevice.h> 11 #include <linux/cpumask.h> 12 #include <linux/aer.h> 13 #include <linux/if_vlan.h> 14 #include <linux/jiffies.h> 15 16 #include <linux/timecounter.h> 17 #include <linux/net_tstamp.h> 18 #include <linux/ptp_clock_kernel.h> 19 20 #include "ixgbe_type.h" 21 #include "ixgbe_common.h" 22 #include "ixgbe_dcb.h" 23 #if IS_ENABLED(CONFIG_FCOE) 24 #define IXGBE_FCOE 25 #include "ixgbe_fcoe.h" 26 #endif /* IS_ENABLED(CONFIG_FCOE) */ 27 #ifdef CONFIG_IXGBE_DCA 28 #include <linux/dca.h> 29 #endif 30 #include "ixgbe_ipsec.h" 31 32 #include <net/xdp.h> 33 34 /* common prefix used by pr_<> macros */ 35 #undef pr_fmt 36 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 37 38 /* TX/RX descriptor defines */ 39 #define IXGBE_DEFAULT_TXD 512 40 #define IXGBE_DEFAULT_TX_WORK 256 41 #define IXGBE_MAX_TXD 4096 42 #define IXGBE_MIN_TXD 64 43 44 #if (PAGE_SIZE < 8192) 45 #define IXGBE_DEFAULT_RXD 512 46 #else 47 #define IXGBE_DEFAULT_RXD 128 48 #endif 49 #define IXGBE_MAX_RXD 4096 50 #define IXGBE_MIN_RXD 64 51 52 #define IXGBE_ETH_P_LLDP 0x88CC 53 54 /* flow control */ 55 #define IXGBE_MIN_FCRTL 0x40 56 #define IXGBE_MAX_FCRTL 0x7FF80 57 #define IXGBE_MIN_FCRTH 0x600 58 #define IXGBE_MAX_FCRTH 0x7FFF0 59 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF 60 #define IXGBE_MIN_FCPAUSE 0 61 #define IXGBE_MAX_FCPAUSE 0xFFFF 62 63 /* Supported Rx Buffer Sizes */ 64 #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ 65 #define IXGBE_RXBUFFER_1536 1536 66 #define IXGBE_RXBUFFER_2K 2048 67 #define IXGBE_RXBUFFER_3K 3072 68 #define IXGBE_RXBUFFER_4K 4096 69 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ 70 71 /* Attempt to maximize the headroom available for incoming frames. We 72 * use a 2K buffer for receives and need 1536/1534 to store the data for 73 * the frame. This leaves us with 512 bytes of room. From that we need 74 * to deduct the space needed for the shared info and the padding needed 75 * to IP align the frame. 76 * 77 * Note: For cache line sizes 256 or larger this value is going to end 78 * up negative. In these cases we should fall back to the 3K 79 * buffers. 80 */ 81 #if (PAGE_SIZE < 8192) 82 #define IXGBE_MAX_2K_FRAME_BUILD_SKB (IXGBE_RXBUFFER_1536 - NET_IP_ALIGN) 83 #define IXGBE_2K_TOO_SMALL_WITH_PADDING \ 84 ((NET_SKB_PAD + IXGBE_RXBUFFER_1536) > SKB_WITH_OVERHEAD(IXGBE_RXBUFFER_2K)) 85 86 static inline int ixgbe_compute_pad(int rx_buf_len) 87 { 88 int page_size, pad_size; 89 90 page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2); 91 pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len; 92 93 return pad_size; 94 } 95 96 static inline int ixgbe_skb_pad(void) 97 { 98 int rx_buf_len; 99 100 /* If a 2K buffer cannot handle a standard Ethernet frame then 101 * optimize padding for a 3K buffer instead of a 1.5K buffer. 102 * 103 * For a 3K buffer we need to add enough padding to allow for 104 * tailroom due to NET_IP_ALIGN possibly shifting us out of 105 * cache-line alignment. 106 */ 107 if (IXGBE_2K_TOO_SMALL_WITH_PADDING) 108 rx_buf_len = IXGBE_RXBUFFER_3K + SKB_DATA_ALIGN(NET_IP_ALIGN); 109 else 110 rx_buf_len = IXGBE_RXBUFFER_1536; 111 112 /* if needed make room for NET_IP_ALIGN */ 113 rx_buf_len -= NET_IP_ALIGN; 114 115 return ixgbe_compute_pad(rx_buf_len); 116 } 117 118 #define IXGBE_SKB_PAD ixgbe_skb_pad() 119 #else 120 #define IXGBE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 121 #endif 122 123 /* 124 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 125 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more, 126 * this adds up to 448 bytes of extra data. 127 * 128 * Since netdev_alloc_skb now allocates a page fragment we can use a value 129 * of 256 and the resultant skb will have a truesize of 960 or less. 130 */ 131 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 132 133 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 134 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 135 136 #define IXGBE_RX_DMA_ATTR \ 137 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 138 139 enum ixgbe_tx_flags { 140 /* cmd_type flags */ 141 IXGBE_TX_FLAGS_HW_VLAN = 0x01, 142 IXGBE_TX_FLAGS_TSO = 0x02, 143 IXGBE_TX_FLAGS_TSTAMP = 0x04, 144 145 /* olinfo flags */ 146 IXGBE_TX_FLAGS_CC = 0x08, 147 IXGBE_TX_FLAGS_IPV4 = 0x10, 148 IXGBE_TX_FLAGS_CSUM = 0x20, 149 IXGBE_TX_FLAGS_IPSEC = 0x40, 150 151 /* software defined flags */ 152 IXGBE_TX_FLAGS_SW_VLAN = 0x80, 153 IXGBE_TX_FLAGS_FCOE = 0x100, 154 }; 155 156 /* VLAN info */ 157 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 158 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 159 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 160 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 161 162 #define IXGBE_MAX_VF_MC_ENTRIES 30 163 #define IXGBE_MAX_VF_FUNCTIONS 64 164 #define IXGBE_MAX_VFTA_ENTRIES 128 165 #define MAX_EMULATION_MAC_ADDRS 16 166 #define IXGBE_MAX_PF_MACVLANS 15 167 #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset) 168 #define IXGBE_82599_VF_DEVICE_ID 0x10ED 169 #define IXGBE_X540_VF_DEVICE_ID 0x1515 170 171 struct vf_data_storage { 172 struct pci_dev *vfdev; 173 unsigned char vf_mac_addresses[ETH_ALEN]; 174 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; 175 u16 num_vf_mc_hashes; 176 bool clear_to_send; 177 bool pf_set_mac; 178 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 179 u16 pf_qos; 180 u16 tx_rate; 181 u8 spoofchk_enabled; 182 bool rss_query_enabled; 183 u8 trusted; 184 int xcast_mode; 185 unsigned int vf_api; 186 }; 187 188 enum ixgbevf_xcast_modes { 189 IXGBEVF_XCAST_MODE_NONE = 0, 190 IXGBEVF_XCAST_MODE_MULTI, 191 IXGBEVF_XCAST_MODE_ALLMULTI, 192 IXGBEVF_XCAST_MODE_PROMISC, 193 }; 194 195 struct vf_macvlans { 196 struct list_head l; 197 int vf; 198 bool free; 199 bool is_macvlan; 200 u8 vf_macvlan[ETH_ALEN]; 201 }; 202 203 #define IXGBE_MAX_TXD_PWR 14 204 #define IXGBE_MAX_DATA_PER_TXD (1u << IXGBE_MAX_TXD_PWR) 205 206 /* Tx Descriptors needed, worst case */ 207 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) 208 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 209 210 /* wrapper around a pointer to a socket buffer, 211 * so a DMA handle can be stored along with the buffer */ 212 struct ixgbe_tx_buffer { 213 union ixgbe_adv_tx_desc *next_to_watch; 214 unsigned long time_stamp; 215 union { 216 struct sk_buff *skb; 217 struct xdp_frame *xdpf; 218 }; 219 unsigned int bytecount; 220 unsigned short gso_segs; 221 __be16 protocol; 222 DEFINE_DMA_UNMAP_ADDR(dma); 223 DEFINE_DMA_UNMAP_LEN(len); 224 u32 tx_flags; 225 }; 226 227 struct ixgbe_rx_buffer { 228 struct sk_buff *skb; 229 dma_addr_t dma; 230 union { 231 struct { 232 struct page *page; 233 __u32 page_offset; 234 __u16 pagecnt_bias; 235 }; 236 struct { 237 void *addr; 238 u64 handle; 239 }; 240 }; 241 }; 242 243 struct ixgbe_queue_stats { 244 u64 packets; 245 u64 bytes; 246 }; 247 248 struct ixgbe_tx_queue_stats { 249 u64 restart_queue; 250 u64 tx_busy; 251 u64 tx_done_old; 252 }; 253 254 struct ixgbe_rx_queue_stats { 255 u64 rsc_count; 256 u64 rsc_flush; 257 u64 non_eop_descs; 258 u64 alloc_rx_page; 259 u64 alloc_rx_page_failed; 260 u64 alloc_rx_buff_failed; 261 u64 csum_err; 262 }; 263 264 #define IXGBE_TS_HDR_LEN 8 265 266 enum ixgbe_ring_state_t { 267 __IXGBE_RX_3K_BUFFER, 268 __IXGBE_RX_BUILD_SKB_ENABLED, 269 __IXGBE_RX_RSC_ENABLED, 270 __IXGBE_RX_CSUM_UDP_ZERO_ERR, 271 __IXGBE_RX_FCOE, 272 __IXGBE_TX_FDIR_INIT_DONE, 273 __IXGBE_TX_XPS_INIT_DONE, 274 __IXGBE_TX_DETECT_HANG, 275 __IXGBE_HANG_CHECK_ARMED, 276 __IXGBE_TX_XDP_RING, 277 __IXGBE_TX_DISABLED, 278 }; 279 280 #define ring_uses_build_skb(ring) \ 281 test_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &(ring)->state) 282 283 struct ixgbe_fwd_adapter { 284 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 285 struct net_device *netdev; 286 unsigned int tx_base_queue; 287 unsigned int rx_base_queue; 288 int pool; 289 }; 290 291 #define check_for_tx_hang(ring) \ 292 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 293 #define set_check_for_tx_hang(ring) \ 294 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 295 #define clear_check_for_tx_hang(ring) \ 296 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 297 #define ring_is_rsc_enabled(ring) \ 298 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 299 #define set_ring_rsc_enabled(ring) \ 300 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 301 #define clear_ring_rsc_enabled(ring) \ 302 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 303 #define ring_is_xdp(ring) \ 304 test_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 305 #define set_ring_xdp(ring) \ 306 set_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 307 #define clear_ring_xdp(ring) \ 308 clear_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 309 struct ixgbe_ring { 310 struct ixgbe_ring *next; /* pointer to next ring in q_vector */ 311 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ 312 struct net_device *netdev; /* netdev ring belongs to */ 313 struct bpf_prog *xdp_prog; 314 struct device *dev; /* device for DMA mapping */ 315 void *desc; /* descriptor ring memory */ 316 union { 317 struct ixgbe_tx_buffer *tx_buffer_info; 318 struct ixgbe_rx_buffer *rx_buffer_info; 319 }; 320 unsigned long state; 321 u8 __iomem *tail; 322 dma_addr_t dma; /* phys. address of descriptor ring */ 323 unsigned int size; /* length in bytes */ 324 325 u16 count; /* amount of descriptors */ 326 327 u8 queue_index; /* needed for multiqueue queue management */ 328 u8 reg_idx; /* holds the special value that gets 329 * the hardware register offset 330 * associated with this ring, which is 331 * different for DCB and RSS modes 332 */ 333 u16 next_to_use; 334 u16 next_to_clean; 335 336 unsigned long last_rx_timestamp; 337 338 union { 339 u16 next_to_alloc; 340 struct { 341 u8 atr_sample_rate; 342 u8 atr_count; 343 }; 344 }; 345 346 u8 dcb_tc; 347 struct ixgbe_queue_stats stats; 348 struct u64_stats_sync syncp; 349 union { 350 struct ixgbe_tx_queue_stats tx_stats; 351 struct ixgbe_rx_queue_stats rx_stats; 352 }; 353 struct xdp_rxq_info xdp_rxq; 354 struct xdp_umem *xsk_umem; 355 struct zero_copy_allocator zca; /* ZC allocator anchor */ 356 u16 ring_idx; /* {rx,tx,xdp}_ring back reference idx */ 357 u16 rx_buf_len; 358 } ____cacheline_internodealigned_in_smp; 359 360 enum ixgbe_ring_f_enum { 361 RING_F_NONE = 0, 362 RING_F_VMDQ, /* SR-IOV uses the same ring feature */ 363 RING_F_RSS, 364 RING_F_FDIR, 365 #ifdef IXGBE_FCOE 366 RING_F_FCOE, 367 #endif /* IXGBE_FCOE */ 368 369 RING_F_ARRAY_SIZE /* must be last in enum set */ 370 }; 371 372 #define IXGBE_MAX_RSS_INDICES 16 373 #define IXGBE_MAX_RSS_INDICES_X550 63 374 #define IXGBE_MAX_VMDQ_INDICES 64 375 #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */ 376 #define IXGBE_MAX_FCOE_INDICES 8 377 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 378 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 379 #define MAX_XDP_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 380 #define IXGBE_MAX_L2A_QUEUES 4 381 #define IXGBE_BAD_L2A_QUEUE 3 382 #define IXGBE_MAX_MACVLANS 63 383 384 struct ixgbe_ring_feature { 385 u16 limit; /* upper limit on feature indices */ 386 u16 indices; /* current value of indices */ 387 u16 mask; /* Mask used for feature to ring mapping */ 388 u16 offset; /* offset to start of feature */ 389 } ____cacheline_internodealigned_in_smp; 390 391 #define IXGBE_82599_VMDQ_8Q_MASK 0x78 392 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C 393 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E 394 395 /* 396 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since 397 * this is twice the size of a half page we need to double the page order 398 * for FCoE enabled Rx queues. 399 */ 400 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring) 401 { 402 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 403 return IXGBE_RXBUFFER_3K; 404 #if (PAGE_SIZE < 8192) 405 if (ring_uses_build_skb(ring)) 406 return IXGBE_MAX_2K_FRAME_BUILD_SKB; 407 #endif 408 return IXGBE_RXBUFFER_2K; 409 } 410 411 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) 412 { 413 #if (PAGE_SIZE < 8192) 414 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 415 return 1; 416 #endif 417 return 0; 418 } 419 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) 420 421 #define IXGBE_ITR_ADAPTIVE_MIN_INC 2 422 #define IXGBE_ITR_ADAPTIVE_MIN_USECS 10 423 #define IXGBE_ITR_ADAPTIVE_MAX_USECS 126 424 #define IXGBE_ITR_ADAPTIVE_LATENCY 0x80 425 #define IXGBE_ITR_ADAPTIVE_BULK 0x00 426 427 struct ixgbe_ring_container { 428 struct ixgbe_ring *ring; /* pointer to linked list of rings */ 429 unsigned long next_update; /* jiffies value of last update */ 430 unsigned int total_bytes; /* total bytes processed this int */ 431 unsigned int total_packets; /* total packets processed this int */ 432 u16 work_limit; /* total work allowed per interrupt */ 433 u8 count; /* total number of rings in vector */ 434 u8 itr; /* current ITR setting for ring */ 435 }; 436 437 /* iterator for handling rings in ring container */ 438 #define ixgbe_for_each_ring(pos, head) \ 439 for (pos = (head).ring; pos != NULL; pos = pos->next) 440 441 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ 442 ? 8 : 1) 443 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS 444 445 /* MAX_Q_VECTORS of these are allocated, 446 * but we only use one per queue-specific vector. 447 */ 448 struct ixgbe_q_vector { 449 struct ixgbe_adapter *adapter; 450 #ifdef CONFIG_IXGBE_DCA 451 int cpu; /* CPU for DCA */ 452 #endif 453 u16 v_idx; /* index of q_vector within array, also used for 454 * finding the bit in EICR and friends that 455 * represents the vector for this ring */ 456 u16 itr; /* Interrupt throttle rate written to EITR */ 457 struct ixgbe_ring_container rx, tx; 458 459 struct napi_struct napi; 460 cpumask_t affinity_mask; 461 int numa_node; 462 struct rcu_head rcu; /* to avoid race with update stats on free */ 463 char name[IFNAMSIZ + 9]; 464 465 /* for dynamic allocation of rings associated with this q_vector */ 466 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp; 467 }; 468 469 #ifdef CONFIG_IXGBE_HWMON 470 471 #define IXGBE_HWMON_TYPE_LOC 0 472 #define IXGBE_HWMON_TYPE_TEMP 1 473 #define IXGBE_HWMON_TYPE_CAUTION 2 474 #define IXGBE_HWMON_TYPE_MAX 3 475 476 struct hwmon_attr { 477 struct device_attribute dev_attr; 478 struct ixgbe_hw *hw; 479 struct ixgbe_thermal_diode_data *sensor; 480 char name[12]; 481 }; 482 483 struct hwmon_buff { 484 struct attribute_group group; 485 const struct attribute_group *groups[2]; 486 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1]; 487 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4]; 488 unsigned int n_hwmon; 489 }; 490 #endif /* CONFIG_IXGBE_HWMON */ 491 492 /* 493 * microsecond values for various ITR rates shifted by 2 to fit itr register 494 * with the first 3 bits reserved 0 495 */ 496 #define IXGBE_MIN_RSC_ITR 24 497 #define IXGBE_100K_ITR 40 498 #define IXGBE_20K_ITR 200 499 #define IXGBE_12K_ITR 336 500 501 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ 502 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, 503 const u32 stat_err_bits) 504 { 505 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 506 } 507 508 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) 509 { 510 u16 ntc = ring->next_to_clean; 511 u16 ntu = ring->next_to_use; 512 513 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 514 } 515 516 #define IXGBE_RX_DESC(R, i) \ 517 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) 518 #define IXGBE_TX_DESC(R, i) \ 519 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) 520 #define IXGBE_TX_CTXTDESC(R, i) \ 521 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) 522 523 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ 524 #ifdef IXGBE_FCOE 525 /* Use 3K as the baby jumbo frame size for FCoE */ 526 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 527 #endif /* IXGBE_FCOE */ 528 529 #define OTHER_VECTOR 1 530 #define NON_Q_VECTORS (OTHER_VECTOR) 531 532 #define MAX_MSIX_VECTORS_82599 64 533 #define MAX_Q_VECTORS_82599 64 534 #define MAX_MSIX_VECTORS_82598 18 535 #define MAX_Q_VECTORS_82598 16 536 537 struct ixgbe_mac_addr { 538 u8 addr[ETH_ALEN]; 539 u16 pool; 540 u16 state; /* bitmask */ 541 }; 542 543 #define IXGBE_MAC_STATE_DEFAULT 0x1 544 #define IXGBE_MAC_STATE_MODIFIED 0x2 545 #define IXGBE_MAC_STATE_IN_USE 0x4 546 547 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599 548 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 549 550 #define MIN_MSIX_Q_VECTORS 1 551 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) 552 553 /* default to trying for four seconds */ 554 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) 555 #define IXGBE_SFP_POLL_JIFFIES (2 * HZ) /* SFP poll every 2 seconds */ 556 557 /* board specific private data structure */ 558 struct ixgbe_adapter { 559 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 560 /* OS defined structs */ 561 struct net_device *netdev; 562 struct bpf_prog *xdp_prog; 563 struct pci_dev *pdev; 564 565 unsigned long state; 566 567 /* Some features need tri-state capability, 568 * thus the additional *_CAPABLE flags. 569 */ 570 u32 flags; 571 #define IXGBE_FLAG_MSI_ENABLED BIT(1) 572 #define IXGBE_FLAG_MSIX_ENABLED BIT(3) 573 #define IXGBE_FLAG_RX_1BUF_CAPABLE BIT(4) 574 #define IXGBE_FLAG_RX_PS_CAPABLE BIT(5) 575 #define IXGBE_FLAG_RX_PS_ENABLED BIT(6) 576 #define IXGBE_FLAG_DCA_ENABLED BIT(8) 577 #define IXGBE_FLAG_DCA_CAPABLE BIT(9) 578 #define IXGBE_FLAG_IMIR_ENABLED BIT(10) 579 #define IXGBE_FLAG_MQ_CAPABLE BIT(11) 580 #define IXGBE_FLAG_DCB_ENABLED BIT(12) 581 #define IXGBE_FLAG_VMDQ_CAPABLE BIT(13) 582 #define IXGBE_FLAG_VMDQ_ENABLED BIT(14) 583 #define IXGBE_FLAG_FAN_FAIL_CAPABLE BIT(15) 584 #define IXGBE_FLAG_NEED_LINK_UPDATE BIT(16) 585 #define IXGBE_FLAG_NEED_LINK_CONFIG BIT(17) 586 #define IXGBE_FLAG_FDIR_HASH_CAPABLE BIT(18) 587 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE BIT(19) 588 #define IXGBE_FLAG_FCOE_CAPABLE BIT(20) 589 #define IXGBE_FLAG_FCOE_ENABLED BIT(21) 590 #define IXGBE_FLAG_SRIOV_CAPABLE BIT(22) 591 #define IXGBE_FLAG_SRIOV_ENABLED BIT(23) 592 #define IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE BIT(24) 593 #define IXGBE_FLAG_RX_HWTSTAMP_ENABLED BIT(25) 594 #define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER BIT(26) 595 #define IXGBE_FLAG_DCB_CAPABLE BIT(27) 596 #define IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE BIT(28) 597 598 u32 flags2; 599 #define IXGBE_FLAG2_RSC_CAPABLE BIT(0) 600 #define IXGBE_FLAG2_RSC_ENABLED BIT(1) 601 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE BIT(2) 602 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT BIT(3) 603 #define IXGBE_FLAG2_SEARCH_FOR_SFP BIT(4) 604 #define IXGBE_FLAG2_SFP_NEEDS_RESET BIT(5) 605 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT BIT(7) 606 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP BIT(8) 607 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP BIT(9) 608 #define IXGBE_FLAG2_PTP_PPS_ENABLED BIT(10) 609 #define IXGBE_FLAG2_PHY_INTERRUPT BIT(11) 610 #define IXGBE_FLAG2_UDP_TUN_REREG_NEEDED BIT(12) 611 #define IXGBE_FLAG2_VLAN_PROMISC BIT(13) 612 #define IXGBE_FLAG2_EEE_CAPABLE BIT(14) 613 #define IXGBE_FLAG2_EEE_ENABLED BIT(15) 614 #define IXGBE_FLAG2_RX_LEGACY BIT(16) 615 #define IXGBE_FLAG2_IPSEC_ENABLED BIT(17) 616 #define IXGBE_FLAG2_VF_IPSEC_ENABLED BIT(18) 617 618 /* Tx fast path data */ 619 int num_tx_queues; 620 u16 tx_itr_setting; 621 u16 tx_work_limit; 622 u64 tx_ipsec; 623 624 /* Rx fast path data */ 625 int num_rx_queues; 626 u16 rx_itr_setting; 627 u64 rx_ipsec; 628 629 /* Port number used to identify VXLAN traffic */ 630 __be16 vxlan_port; 631 __be16 geneve_port; 632 633 /* XDP */ 634 int num_xdp_queues; 635 struct ixgbe_ring *xdp_ring[MAX_XDP_QUEUES]; 636 637 /* TX */ 638 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; 639 640 u64 restart_queue; 641 u64 lsc_int; 642 u32 tx_timeout_count; 643 644 /* RX */ 645 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; 646 int num_rx_pools; /* == num_rx_queues in 82598 */ 647 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ 648 u64 hw_csum_rx_error; 649 u64 hw_rx_no_dma_resources; 650 u64 rsc_total_count; 651 u64 rsc_total_flush; 652 u64 non_eop_descs; 653 u32 alloc_rx_page; 654 u32 alloc_rx_page_failed; 655 u32 alloc_rx_buff_failed; 656 657 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; 658 659 /* DCB parameters */ 660 struct ieee_pfc *ixgbe_ieee_pfc; 661 struct ieee_ets *ixgbe_ieee_ets; 662 struct ixgbe_dcb_config dcb_cfg; 663 struct ixgbe_dcb_config temp_dcb_cfg; 664 u8 hw_tcs; 665 u8 dcb_set_bitmap; 666 u8 dcbx_cap; 667 enum ixgbe_fc_mode last_lfc_mode; 668 669 int num_q_vectors; /* current number of q_vectors for device */ 670 int max_q_vectors; /* true count of q_vectors for device */ 671 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; 672 struct msix_entry *msix_entries; 673 674 u32 test_icr; 675 struct ixgbe_ring test_tx_ring; 676 struct ixgbe_ring test_rx_ring; 677 678 /* structs defined in ixgbe_hw.h */ 679 struct ixgbe_hw hw; 680 u16 msg_enable; 681 struct ixgbe_hw_stats stats; 682 683 u64 tx_busy; 684 unsigned int tx_ring_count; 685 unsigned int xdp_ring_count; 686 unsigned int rx_ring_count; 687 688 u32 link_speed; 689 bool link_up; 690 unsigned long sfp_poll_time; 691 unsigned long link_check_timeout; 692 693 struct timer_list service_timer; 694 struct work_struct service_task; 695 696 struct hlist_head fdir_filter_list; 697 unsigned long fdir_overflow; /* number of times ATR was backed off */ 698 union ixgbe_atr_input fdir_mask; 699 int fdir_filter_count; 700 u32 fdir_pballoc; 701 u32 atr_sample_rate; 702 spinlock_t fdir_perfect_lock; 703 704 #ifdef IXGBE_FCOE 705 struct ixgbe_fcoe fcoe; 706 #endif /* IXGBE_FCOE */ 707 u8 __iomem *io_addr; /* Mainly for iounmap use */ 708 u32 wol; 709 710 u16 bridge_mode; 711 712 char eeprom_id[NVM_VER_SIZE]; 713 u16 eeprom_cap; 714 715 u32 interrupt_event; 716 u32 led_reg; 717 718 struct ptp_clock *ptp_clock; 719 struct ptp_clock_info ptp_caps; 720 struct work_struct ptp_tx_work; 721 struct sk_buff *ptp_tx_skb; 722 struct hwtstamp_config tstamp_config; 723 unsigned long ptp_tx_start; 724 unsigned long last_overflow_check; 725 unsigned long last_rx_ptp_check; 726 unsigned long last_rx_timestamp; 727 spinlock_t tmreg_lock; 728 struct cyclecounter hw_cc; 729 struct timecounter hw_tc; 730 u32 base_incval; 731 u32 tx_hwtstamp_timeouts; 732 u32 tx_hwtstamp_skipped; 733 u32 rx_hwtstamp_cleared; 734 void (*ptp_setup_sdp)(struct ixgbe_adapter *); 735 736 /* SR-IOV */ 737 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); 738 unsigned int num_vfs; 739 struct vf_data_storage *vfinfo; 740 int vf_rate_link_speed; 741 struct vf_macvlans vf_mvs; 742 struct vf_macvlans *mv_list; 743 744 u32 timer_event_accumulator; 745 u32 vferr_refcount; 746 struct ixgbe_mac_addr *mac_table; 747 struct kobject *info_kobj; 748 #ifdef CONFIG_IXGBE_HWMON 749 struct hwmon_buff *ixgbe_hwmon_buff; 750 #endif /* CONFIG_IXGBE_HWMON */ 751 #ifdef CONFIG_DEBUG_FS 752 struct dentry *ixgbe_dbg_adapter; 753 #endif /*CONFIG_DEBUG_FS*/ 754 755 u8 default_up; 756 /* Bitmask indicating in use pools */ 757 DECLARE_BITMAP(fwd_bitmask, IXGBE_MAX_MACVLANS + 1); 758 759 #define IXGBE_MAX_LINK_HANDLE 10 760 struct ixgbe_jump_table *jump_tables[IXGBE_MAX_LINK_HANDLE]; 761 unsigned long tables; 762 763 /* maximum number of RETA entries among all devices supported by ixgbe 764 * driver: currently it's x550 device in non-SRIOV mode 765 */ 766 #define IXGBE_MAX_RETA_ENTRIES 512 767 u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES]; 768 769 #define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */ 770 u32 *rss_key; 771 772 #ifdef CONFIG_IXGBE_IPSEC 773 struct ixgbe_ipsec *ipsec; 774 #endif /* CONFIG_IXGBE_IPSEC */ 775 776 /* AF_XDP zero-copy */ 777 struct xdp_umem **xsk_umems; 778 u16 num_xsk_umems_used; 779 u16 num_xsk_umems; 780 }; 781 782 static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter) 783 { 784 switch (adapter->hw.mac.type) { 785 case ixgbe_mac_82598EB: 786 case ixgbe_mac_82599EB: 787 case ixgbe_mac_X540: 788 return IXGBE_MAX_RSS_INDICES; 789 case ixgbe_mac_X550: 790 case ixgbe_mac_X550EM_x: 791 case ixgbe_mac_x550em_a: 792 return IXGBE_MAX_RSS_INDICES_X550; 793 default: 794 return 0; 795 } 796 } 797 798 struct ixgbe_fdir_filter { 799 struct hlist_node fdir_node; 800 union ixgbe_atr_input filter; 801 u16 sw_idx; 802 u64 action; 803 }; 804 805 enum ixgbe_state_t { 806 __IXGBE_TESTING, 807 __IXGBE_RESETTING, 808 __IXGBE_DOWN, 809 __IXGBE_DISABLED, 810 __IXGBE_REMOVING, 811 __IXGBE_SERVICE_SCHED, 812 __IXGBE_SERVICE_INITED, 813 __IXGBE_IN_SFP_INIT, 814 __IXGBE_PTP_RUNNING, 815 __IXGBE_PTP_TX_IN_PROGRESS, 816 __IXGBE_RESET_REQUESTED, 817 }; 818 819 struct ixgbe_cb { 820 union { /* Union defining head/tail partner */ 821 struct sk_buff *head; 822 struct sk_buff *tail; 823 }; 824 dma_addr_t dma; 825 u16 append_cnt; 826 bool page_released; 827 }; 828 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) 829 830 enum ixgbe_boards { 831 board_82598, 832 board_82599, 833 board_X540, 834 board_X550, 835 board_X550EM_x, 836 board_x550em_x_fw, 837 board_x550em_a, 838 board_x550em_a_fw, 839 }; 840 841 extern const struct ixgbe_info ixgbe_82598_info; 842 extern const struct ixgbe_info ixgbe_82599_info; 843 extern const struct ixgbe_info ixgbe_X540_info; 844 extern const struct ixgbe_info ixgbe_X550_info; 845 extern const struct ixgbe_info ixgbe_X550EM_x_info; 846 extern const struct ixgbe_info ixgbe_x550em_x_fw_info; 847 extern const struct ixgbe_info ixgbe_x550em_a_info; 848 extern const struct ixgbe_info ixgbe_x550em_a_fw_info; 849 #ifdef CONFIG_IXGBE_DCB 850 extern const struct dcbnl_rtnl_ops ixgbe_dcbnl_ops; 851 #endif 852 853 extern char ixgbe_driver_name[]; 854 extern const char ixgbe_driver_version[]; 855 #ifdef IXGBE_FCOE 856 extern char ixgbe_default_device_descr[]; 857 #endif /* IXGBE_FCOE */ 858 859 int ixgbe_open(struct net_device *netdev); 860 int ixgbe_close(struct net_device *netdev); 861 void ixgbe_up(struct ixgbe_adapter *adapter); 862 void ixgbe_down(struct ixgbe_adapter *adapter); 863 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); 864 void ixgbe_reset(struct ixgbe_adapter *adapter); 865 void ixgbe_set_ethtool_ops(struct net_device *netdev); 866 int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); 867 int ixgbe_setup_tx_resources(struct ixgbe_ring *); 868 void ixgbe_free_rx_resources(struct ixgbe_ring *); 869 void ixgbe_free_tx_resources(struct ixgbe_ring *); 870 void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 871 void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 872 void ixgbe_disable_rx(struct ixgbe_adapter *adapter); 873 void ixgbe_disable_tx(struct ixgbe_adapter *adapter); 874 void ixgbe_update_stats(struct ixgbe_adapter *adapter); 875 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); 876 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 877 u16 subdevice_id); 878 #ifdef CONFIG_PCI_IOV 879 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter); 880 #endif 881 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 882 const u8 *addr, u16 queue); 883 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 884 const u8 *addr, u16 queue); 885 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid); 886 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); 887 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *, 888 struct ixgbe_ring *); 889 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, 890 struct ixgbe_tx_buffer *); 891 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); 892 void ixgbe_write_eitr(struct ixgbe_q_vector *); 893 int ixgbe_poll(struct napi_struct *napi, int budget); 894 int ethtool_ioctl(struct ifreq *ifr); 895 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); 896 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); 897 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); 898 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 899 union ixgbe_atr_hash_dword input, 900 union ixgbe_atr_hash_dword common, 901 u8 queue); 902 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 903 union ixgbe_atr_input *input_mask); 904 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 905 union ixgbe_atr_input *input, 906 u16 soft_id, u8 queue); 907 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 908 union ixgbe_atr_input *input, 909 u16 soft_id); 910 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 911 union ixgbe_atr_input *mask); 912 int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 913 struct ixgbe_fdir_filter *input, 914 u16 sw_idx); 915 void ixgbe_set_rx_mode(struct net_device *netdev); 916 #ifdef CONFIG_IXGBE_DCB 917 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); 918 #endif 919 int ixgbe_setup_tc(struct net_device *dev, u8 tc); 920 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); 921 void ixgbe_do_reset(struct net_device *netdev); 922 #ifdef CONFIG_IXGBE_HWMON 923 void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); 924 int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); 925 #endif /* CONFIG_IXGBE_HWMON */ 926 #ifdef IXGBE_FCOE 927 void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); 928 int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, 929 u8 *hdr_len); 930 int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, 931 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb); 932 int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, 933 struct scatterlist *sgl, unsigned int sgc); 934 int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, 935 struct scatterlist *sgl, unsigned int sgc); 936 int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); 937 int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 938 void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 939 int ixgbe_fcoe_enable(struct net_device *netdev); 940 int ixgbe_fcoe_disable(struct net_device *netdev); 941 #ifdef CONFIG_IXGBE_DCB 942 u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); 943 u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); 944 #endif /* CONFIG_IXGBE_DCB */ 945 int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); 946 int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, 947 struct netdev_fcoe_hbainfo *info); 948 u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); 949 #endif /* IXGBE_FCOE */ 950 #ifdef CONFIG_DEBUG_FS 951 void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter); 952 void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter); 953 void ixgbe_dbg_init(void); 954 void ixgbe_dbg_exit(void); 955 #else 956 static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {} 957 static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {} 958 static inline void ixgbe_dbg_init(void) {} 959 static inline void ixgbe_dbg_exit(void) {} 960 #endif /* CONFIG_DEBUG_FS */ 961 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) 962 { 963 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 964 } 965 966 void ixgbe_ptp_init(struct ixgbe_adapter *adapter); 967 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter); 968 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); 969 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); 970 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter); 971 void ixgbe_ptp_tx_hang(struct ixgbe_adapter *adapter); 972 void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *, struct sk_buff *); 973 void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *, struct sk_buff *skb); 974 static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring, 975 union ixgbe_adv_rx_desc *rx_desc, 976 struct sk_buff *skb) 977 { 978 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_TSIP))) { 979 ixgbe_ptp_rx_pktstamp(rx_ring->q_vector, skb); 980 return; 981 } 982 983 if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))) 984 return; 985 986 ixgbe_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 987 988 /* Update the last_rx_timestamp timer in order to enable watchdog check 989 * for error case of latched timestamp on a dropped packet. 990 */ 991 rx_ring->last_rx_timestamp = jiffies; 992 } 993 994 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 995 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 996 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); 997 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter); 998 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter); 999 #ifdef CONFIG_PCI_IOV 1000 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter); 1001 #endif 1002 1003 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 1004 struct ixgbe_adapter *adapter, 1005 struct ixgbe_ring *tx_ring); 1006 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter); 1007 void ixgbe_store_key(struct ixgbe_adapter *adapter); 1008 void ixgbe_store_reta(struct ixgbe_adapter *adapter); 1009 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 1010 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm); 1011 #ifdef CONFIG_IXGBE_IPSEC 1012 void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter); 1013 void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter); 1014 void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter); 1015 void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring, 1016 union ixgbe_adv_rx_desc *rx_desc, 1017 struct sk_buff *skb); 1018 int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, 1019 struct ixgbe_ipsec_tx_data *itd); 1020 void ixgbe_ipsec_vf_clear(struct ixgbe_adapter *adapter, u32 vf); 1021 int ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter *adapter, u32 *mbuf, u32 vf); 1022 int ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter *adapter, u32 *mbuf, u32 vf); 1023 #else 1024 static inline void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter) { } 1025 static inline void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter) { } 1026 static inline void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter) { } 1027 static inline void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring, 1028 union ixgbe_adv_rx_desc *rx_desc, 1029 struct sk_buff *skb) { } 1030 static inline int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring, 1031 struct ixgbe_tx_buffer *first, 1032 struct ixgbe_ipsec_tx_data *itd) { return 0; } 1033 static inline void ixgbe_ipsec_vf_clear(struct ixgbe_adapter *adapter, 1034 u32 vf) { } 1035 static inline int ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter *adapter, 1036 u32 *mbuf, u32 vf) { return -EACCES; } 1037 static inline int ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter *adapter, 1038 u32 *mbuf, u32 vf) { return -EACCES; } 1039 #endif /* CONFIG_IXGBE_IPSEC */ 1040 #endif /* _IXGBE_H_ */ 1041