1bea44e38SLarysa Zaremba /* SPDX-License-Identifier: GPL-2.0-only */ 2bea44e38SLarysa Zaremba /* Copyright (C) 2025 Intel Corporation */ 3bea44e38SLarysa Zaremba 4bea44e38SLarysa Zaremba #ifndef _IXD_LAN_REGS_H_ 5bea44e38SLarysa Zaremba #define _IXD_LAN_REGS_H_ 6bea44e38SLarysa Zaremba 7bea44e38SLarysa Zaremba /* Control Plane Function PCI ID */ 8bea44e38SLarysa Zaremba #define IXD_DEV_ID_CPF 0x1efe 9bea44e38SLarysa Zaremba 10bea44e38SLarysa Zaremba /* Control Queue (Mailbox) */ 11bea44e38SLarysa Zaremba #define PF_FW_MBX_REG_LEN 4096 12bea44e38SLarysa Zaremba #define PF_FW_MBX 0x08400000 13bea44e38SLarysa Zaremba 14*31ddf796SLarysa Zaremba #define PF_FW_ARQBAL (PF_FW_MBX) 15*31ddf796SLarysa Zaremba #define PF_FW_ARQBAH (PF_FW_MBX + 0x4) 16*31ddf796SLarysa Zaremba #define PF_FW_ARQLEN (PF_FW_MBX + 0x8) 17*31ddf796SLarysa Zaremba #define PF_FW_ARQLEN_ARQLEN_M GENMASK(12, 0) 18*31ddf796SLarysa Zaremba #define PF_FW_ARQLEN_ARQENABLE_S 31 19*31ddf796SLarysa Zaremba #define PF_FW_ARQLEN_ARQENABLE_M BIT(PF_FW_ARQLEN_ARQENABLE_S) 20*31ddf796SLarysa Zaremba #define PF_FW_ARQH_ARQH_M GENMASK(12, 0) 21*31ddf796SLarysa Zaremba #define PF_FW_ARQH (PF_FW_MBX + 0xC) 22*31ddf796SLarysa Zaremba #define PF_FW_ARQT (PF_FW_MBX + 0x10) 23*31ddf796SLarysa Zaremba 24*31ddf796SLarysa Zaremba #define PF_FW_ATQBAL (PF_FW_MBX + 0x14) 25*31ddf796SLarysa Zaremba #define PF_FW_ATQBAH (PF_FW_MBX + 0x18) 26*31ddf796SLarysa Zaremba #define PF_FW_ATQLEN (PF_FW_MBX + 0x1C) 27*31ddf796SLarysa Zaremba #define PF_FW_ATQLEN_ATQLEN_M GENMASK(9, 0) 28*31ddf796SLarysa Zaremba #define PF_FW_ATQLEN_ATQENABLE_S 31 29*31ddf796SLarysa Zaremba #define PF_FW_ATQLEN_ATQENABLE_M BIT(PF_FW_ATQLEN_ATQENABLE_S) 30*31ddf796SLarysa Zaremba #define PF_FW_ATQH_ATQH_M GENMASK(9, 0) 31*31ddf796SLarysa Zaremba #define PF_FW_ATQH (PF_FW_MBX + 0x20) 32*31ddf796SLarysa Zaremba #define PF_FW_ATQT (PF_FW_MBX + 0x24) 33*31ddf796SLarysa Zaremba 34bea44e38SLarysa Zaremba /* Reset registers */ 35bea44e38SLarysa Zaremba #define PFGEN_RTRIG_REG_LEN 2048 36bea44e38SLarysa Zaremba #define PFGEN_RTRIG 0x08407000 /* Device resets */ 37*31ddf796SLarysa Zaremba #define PFGEN_RSTAT 0x08407008 /* PFR status */ 38*31ddf796SLarysa Zaremba #define PFGEN_RSTAT_PFR_STATE_M GENMASK(1, 0) 39*31ddf796SLarysa Zaremba #define PFGEN_CTRL 0x0840700C /* PFR trigger */ 40*31ddf796SLarysa Zaremba #define PFGEN_CTRL_PFSWR BIT(0) 41bea44e38SLarysa Zaremba 42bea44e38SLarysa Zaremba /** 43bea44e38SLarysa Zaremba * struct ixd_bar_region - BAR region description 44bea44e38SLarysa Zaremba * @offset: BAR region offset 45bea44e38SLarysa Zaremba * @size: BAR region size 46bea44e38SLarysa Zaremba */ 47bea44e38SLarysa Zaremba struct ixd_bar_region { 48bea44e38SLarysa Zaremba resource_size_t offset; 49bea44e38SLarysa Zaremba resource_size_t size; 50bea44e38SLarysa Zaremba }; 51bea44e38SLarysa Zaremba 52*31ddf796SLarysa Zaremba /** 53*31ddf796SLarysa Zaremba * struct ixd_reset_reg - structure for reset registers 54*31ddf796SLarysa Zaremba * @rstat: offset of status in register 55*31ddf796SLarysa Zaremba * @rstat_m: status mask 56*31ddf796SLarysa Zaremba * @rstat_ok_v: value that indicates PFR completed status 57*31ddf796SLarysa Zaremba * @rtrigger: offset of reset trigger in register 58*31ddf796SLarysa Zaremba * @rtrigger_m: reset trigger mask 59*31ddf796SLarysa Zaremba */ 60*31ddf796SLarysa Zaremba struct ixd_reset_reg { 61*31ddf796SLarysa Zaremba u32 rstat; 62*31ddf796SLarysa Zaremba u32 rstat_m; 63*31ddf796SLarysa Zaremba u32 rstat_ok_v; 64*31ddf796SLarysa Zaremba u32 rtrigger; 65*31ddf796SLarysa Zaremba u32 rtrigger_m; 66*31ddf796SLarysa Zaremba }; 67*31ddf796SLarysa Zaremba 68bea44e38SLarysa Zaremba #endif /* _IXD_LAN_REGS_H_ */ 69