1*31ddf796SLarysa Zaremba // SPDX-License-Identifier: GPL-2.0-only
2*31ddf796SLarysa Zaremba /* Copyright (C) 2025 Intel Corporation */
3*31ddf796SLarysa Zaremba
4*31ddf796SLarysa Zaremba #include "ixd.h"
5*31ddf796SLarysa Zaremba #include "ixd_lan_regs.h"
6*31ddf796SLarysa Zaremba
7*31ddf796SLarysa Zaremba /**
8*31ddf796SLarysa Zaremba * ixd_ctlq_reg_init - Initialize default mailbox registers
9*31ddf796SLarysa Zaremba * @adapter: PCI device driver-specific private data
10*31ddf796SLarysa Zaremba * @ctlq_reg_tx: Transmit queue registers info to be filled
11*31ddf796SLarysa Zaremba * @ctlq_reg_rx: Receive queue registers info to be filled
12*31ddf796SLarysa Zaremba */
ixd_ctlq_reg_init(struct ixd_adapter * adapter,struct libie_ctlq_reg * ctlq_reg_tx,struct libie_ctlq_reg * ctlq_reg_rx)13*31ddf796SLarysa Zaremba void ixd_ctlq_reg_init(struct ixd_adapter *adapter,
14*31ddf796SLarysa Zaremba struct libie_ctlq_reg *ctlq_reg_tx,
15*31ddf796SLarysa Zaremba struct libie_ctlq_reg *ctlq_reg_rx)
16*31ddf796SLarysa Zaremba {
17*31ddf796SLarysa Zaremba struct libie_mmio_info *mmio_info = &adapter->cp_ctx.mmio_info;
18*31ddf796SLarysa Zaremba *ctlq_reg_tx = (struct libie_ctlq_reg) {
19*31ddf796SLarysa Zaremba .head = libie_pci_get_mmio_addr(mmio_info, PF_FW_ATQH),
20*31ddf796SLarysa Zaremba .tail = libie_pci_get_mmio_addr(mmio_info, PF_FW_ATQT),
21*31ddf796SLarysa Zaremba .len = libie_pci_get_mmio_addr(mmio_info, PF_FW_ATQLEN),
22*31ddf796SLarysa Zaremba .addr_high = libie_pci_get_mmio_addr(mmio_info, PF_FW_ATQBAH),
23*31ddf796SLarysa Zaremba .addr_low = libie_pci_get_mmio_addr(mmio_info, PF_FW_ATQBAL),
24*31ddf796SLarysa Zaremba .len_mask = PF_FW_ATQLEN_ATQLEN_M,
25*31ddf796SLarysa Zaremba .len_ena_mask = PF_FW_ATQLEN_ATQENABLE_M,
26*31ddf796SLarysa Zaremba .head_mask = PF_FW_ATQH_ATQH_M,
27*31ddf796SLarysa Zaremba };
28*31ddf796SLarysa Zaremba
29*31ddf796SLarysa Zaremba *ctlq_reg_rx = (struct libie_ctlq_reg) {
30*31ddf796SLarysa Zaremba .head = libie_pci_get_mmio_addr(mmio_info, PF_FW_ARQH),
31*31ddf796SLarysa Zaremba .tail = libie_pci_get_mmio_addr(mmio_info, PF_FW_ARQT),
32*31ddf796SLarysa Zaremba .len = libie_pci_get_mmio_addr(mmio_info, PF_FW_ARQLEN),
33*31ddf796SLarysa Zaremba .addr_high = libie_pci_get_mmio_addr(mmio_info, PF_FW_ARQBAH),
34*31ddf796SLarysa Zaremba .addr_low = libie_pci_get_mmio_addr(mmio_info, PF_FW_ARQBAL),
35*31ddf796SLarysa Zaremba .len_mask = PF_FW_ARQLEN_ARQLEN_M,
36*31ddf796SLarysa Zaremba .len_ena_mask = PF_FW_ARQLEN_ARQENABLE_M,
37*31ddf796SLarysa Zaremba .head_mask = PF_FW_ARQH_ARQH_M,
38*31ddf796SLarysa Zaremba };
39*31ddf796SLarysa Zaremba }
40*31ddf796SLarysa Zaremba
41*31ddf796SLarysa Zaremba static const struct ixd_reset_reg ixd_reset_reg = {
42*31ddf796SLarysa Zaremba .rstat = PFGEN_RSTAT,
43*31ddf796SLarysa Zaremba .rstat_m = PFGEN_RSTAT_PFR_STATE_M,
44*31ddf796SLarysa Zaremba .rstat_ok_v = 0b01,
45*31ddf796SLarysa Zaremba .rtrigger = PFGEN_CTRL,
46*31ddf796SLarysa Zaremba .rtrigger_m = PFGEN_CTRL_PFSWR,
47*31ddf796SLarysa Zaremba };
48*31ddf796SLarysa Zaremba
49*31ddf796SLarysa Zaremba /**
50*31ddf796SLarysa Zaremba * ixd_trigger_reset - Trigger PFR reset
51*31ddf796SLarysa Zaremba * @adapter: the device with mapped reset register
52*31ddf796SLarysa Zaremba */
ixd_trigger_reset(struct ixd_adapter * adapter)53*31ddf796SLarysa Zaremba void ixd_trigger_reset(struct ixd_adapter *adapter)
54*31ddf796SLarysa Zaremba {
55*31ddf796SLarysa Zaremba void __iomem *addr;
56*31ddf796SLarysa Zaremba u32 reg_val;
57*31ddf796SLarysa Zaremba
58*31ddf796SLarysa Zaremba addr = libie_pci_get_mmio_addr(&adapter->cp_ctx.mmio_info,
59*31ddf796SLarysa Zaremba ixd_reset_reg.rtrigger);
60*31ddf796SLarysa Zaremba reg_val = readl(addr);
61*31ddf796SLarysa Zaremba writel(reg_val | ixd_reset_reg.rtrigger_m, addr);
62*31ddf796SLarysa Zaremba }
63*31ddf796SLarysa Zaremba
64*31ddf796SLarysa Zaremba /**
65*31ddf796SLarysa Zaremba * ixd_check_reset_complete - Check if the PFR reset is completed
66*31ddf796SLarysa Zaremba * @adapter: CPF being reset
67*31ddf796SLarysa Zaremba *
68*31ddf796SLarysa Zaremba * Return: %true if the register read indicates reset has been finished,
69*31ddf796SLarysa Zaremba * %false otherwise
70*31ddf796SLarysa Zaremba */
ixd_check_reset_complete(struct ixd_adapter * adapter)71*31ddf796SLarysa Zaremba bool ixd_check_reset_complete(struct ixd_adapter *adapter)
72*31ddf796SLarysa Zaremba {
73*31ddf796SLarysa Zaremba u32 reg_val, reset_status;
74*31ddf796SLarysa Zaremba void __iomem *addr;
75*31ddf796SLarysa Zaremba
76*31ddf796SLarysa Zaremba addr = libie_pci_get_mmio_addr(&adapter->cp_ctx.mmio_info,
77*31ddf796SLarysa Zaremba ixd_reset_reg.rstat);
78*31ddf796SLarysa Zaremba reg_val = readl(addr);
79*31ddf796SLarysa Zaremba reset_status = reg_val & ixd_reset_reg.rstat_m;
80*31ddf796SLarysa Zaremba
81*31ddf796SLarysa Zaremba /* 0xFFFFFFFF might be read if the other side hasn't cleared
82*31ddf796SLarysa Zaremba * the register for us yet.
83*31ddf796SLarysa Zaremba */
84*31ddf796SLarysa Zaremba if (reg_val != GENMASK(31, 0) &&
85*31ddf796SLarysa Zaremba reset_status == ixd_reset_reg.rstat_ok_v)
86*31ddf796SLarysa Zaremba return true;
87*31ddf796SLarysa Zaremba
88*31ddf796SLarysa Zaremba return false;
89*31ddf796SLarysa Zaremba }
90