1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #include <linux/module.h> 5 #include <linux/types.h> 6 #include <linux/if_vlan.h> 7 #include <linux/tcp.h> 8 #include <linux/udp.h> 9 #include <linux/ip.h> 10 #include <linux/pm_runtime.h> 11 #include <net/pkt_sched.h> 12 #include <linux/bpf_trace.h> 13 #include <net/xdp_sock_drv.h> 14 #include <linux/pci.h> 15 #include <linux/mdio.h> 16 17 #include <net/ipv6.h> 18 19 #include "igc.h" 20 #include "igc_hw.h" 21 #include "igc_tsn.h" 22 #include "igc_xdp.h" 23 24 #define DRV_SUMMARY "Intel(R) 2.5G Ethernet Linux Driver" 25 26 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 27 28 #define IGC_XDP_PASS 0 29 #define IGC_XDP_CONSUMED BIT(0) 30 #define IGC_XDP_TX BIT(1) 31 #define IGC_XDP_REDIRECT BIT(2) 32 33 static int debug = -1; 34 35 MODULE_DESCRIPTION(DRV_SUMMARY); 36 MODULE_LICENSE("GPL v2"); 37 module_param(debug, int, 0); 38 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 39 40 char igc_driver_name[] = "igc"; 41 static const char igc_driver_string[] = DRV_SUMMARY; 42 static const char igc_copyright[] = 43 "Copyright(c) 2018 Intel Corporation."; 44 45 static const struct igc_info *igc_info_tbl[] = { 46 [board_base] = &igc_base_info, 47 }; 48 49 static const struct pci_device_id igc_pci_tbl[] = { 50 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_LM), board_base }, 51 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_V), board_base }, 52 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_I), board_base }, 53 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I220_V), board_base }, 54 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_K), board_base }, 55 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_K2), board_base }, 56 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_K), board_base }, 57 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_LMVP), board_base }, 58 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_LMVP), board_base }, 59 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_IT), board_base }, 60 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_LM), board_base }, 61 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_V), board_base }, 62 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_IT), board_base }, 63 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I221_V), board_base }, 64 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_BLANK_NVM), board_base }, 65 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_BLANK_NVM), board_base }, 66 /* required last entry */ 67 {0, } 68 }; 69 70 MODULE_DEVICE_TABLE(pci, igc_pci_tbl); 71 72 enum latency_range { 73 lowest_latency = 0, 74 low_latency = 1, 75 bulk_latency = 2, 76 latency_invalid = 255 77 }; 78 79 void igc_reset(struct igc_adapter *adapter) 80 { 81 struct net_device *dev = adapter->netdev; 82 struct igc_hw *hw = &adapter->hw; 83 struct igc_fc_info *fc = &hw->fc; 84 u32 pba, hwm; 85 86 /* Repartition PBA for greater than 9k MTU if required */ 87 pba = IGC_PBA_34K; 88 89 /* flow control settings 90 * The high water mark must be low enough to fit one full frame 91 * after transmitting the pause frame. As such we must have enough 92 * space to allow for us to complete our current transmit and then 93 * receive the frame that is in progress from the link partner. 94 * Set it to: 95 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 96 */ 97 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 98 99 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 100 fc->low_water = fc->high_water - 16; 101 fc->pause_time = 0xFFFF; 102 fc->send_xon = 1; 103 fc->current_mode = fc->requested_mode; 104 105 hw->mac.ops.reset_hw(hw); 106 107 if (hw->mac.ops.init_hw(hw)) 108 netdev_err(dev, "Error on hardware initialization\n"); 109 110 /* Re-establish EEE setting */ 111 igc_set_eee_i225(hw, true, true, true); 112 113 if (!netif_running(adapter->netdev)) 114 igc_power_down_phy_copper_base(&adapter->hw); 115 116 /* Enable HW to recognize an 802.1Q VLAN Ethernet packet */ 117 wr32(IGC_VET, ETH_P_8021Q); 118 119 /* Re-enable PTP, where applicable. */ 120 igc_ptp_reset(adapter); 121 122 /* Re-enable TSN offloading, where applicable. */ 123 igc_tsn_reset(adapter); 124 125 igc_get_phy_info(hw); 126 } 127 128 /** 129 * igc_power_up_link - Power up the phy link 130 * @adapter: address of board private structure 131 */ 132 static void igc_power_up_link(struct igc_adapter *adapter) 133 { 134 igc_reset_phy(&adapter->hw); 135 136 igc_power_up_phy_copper(&adapter->hw); 137 138 igc_setup_link(&adapter->hw); 139 } 140 141 /** 142 * igc_release_hw_control - release control of the h/w to f/w 143 * @adapter: address of board private structure 144 * 145 * igc_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 146 * For ASF and Pass Through versions of f/w this means that the 147 * driver is no longer loaded. 148 */ 149 static void igc_release_hw_control(struct igc_adapter *adapter) 150 { 151 struct igc_hw *hw = &adapter->hw; 152 u32 ctrl_ext; 153 154 if (!pci_device_is_present(adapter->pdev)) 155 return; 156 157 /* Let firmware take over control of h/w */ 158 ctrl_ext = rd32(IGC_CTRL_EXT); 159 wr32(IGC_CTRL_EXT, 160 ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD); 161 } 162 163 /** 164 * igc_get_hw_control - get control of the h/w from f/w 165 * @adapter: address of board private structure 166 * 167 * igc_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 168 * For ASF and Pass Through versions of f/w this means that 169 * the driver is loaded. 170 */ 171 static void igc_get_hw_control(struct igc_adapter *adapter) 172 { 173 struct igc_hw *hw = &adapter->hw; 174 u32 ctrl_ext; 175 176 /* Let firmware know the driver has taken over */ 177 ctrl_ext = rd32(IGC_CTRL_EXT); 178 wr32(IGC_CTRL_EXT, 179 ctrl_ext | IGC_CTRL_EXT_DRV_LOAD); 180 } 181 182 static void igc_unmap_tx_buffer(struct device *dev, struct igc_tx_buffer *buf) 183 { 184 dma_unmap_single(dev, dma_unmap_addr(buf, dma), 185 dma_unmap_len(buf, len), DMA_TO_DEVICE); 186 187 dma_unmap_len_set(buf, len, 0); 188 } 189 190 /** 191 * igc_clean_tx_ring - Free Tx Buffers 192 * @tx_ring: ring to be cleaned 193 */ 194 static void igc_clean_tx_ring(struct igc_ring *tx_ring) 195 { 196 u16 i = tx_ring->next_to_clean; 197 struct igc_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 198 u32 xsk_frames = 0; 199 200 while (i != tx_ring->next_to_use) { 201 union igc_adv_tx_desc *eop_desc, *tx_desc; 202 203 switch (tx_buffer->type) { 204 case IGC_TX_BUFFER_TYPE_XSK: 205 xsk_frames++; 206 break; 207 case IGC_TX_BUFFER_TYPE_XDP: 208 xdp_return_frame(tx_buffer->xdpf); 209 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 210 break; 211 case IGC_TX_BUFFER_TYPE_SKB: 212 dev_kfree_skb_any(tx_buffer->skb); 213 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 214 break; 215 default: 216 netdev_warn_once(tx_ring->netdev, "Unknown Tx buffer type\n"); 217 break; 218 } 219 220 /* check for eop_desc to determine the end of the packet */ 221 eop_desc = tx_buffer->next_to_watch; 222 tx_desc = IGC_TX_DESC(tx_ring, i); 223 224 /* unmap remaining buffers */ 225 while (tx_desc != eop_desc) { 226 tx_buffer++; 227 tx_desc++; 228 i++; 229 if (unlikely(i == tx_ring->count)) { 230 i = 0; 231 tx_buffer = tx_ring->tx_buffer_info; 232 tx_desc = IGC_TX_DESC(tx_ring, 0); 233 } 234 235 /* unmap any remaining paged data */ 236 if (dma_unmap_len(tx_buffer, len)) 237 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 238 } 239 240 tx_buffer->next_to_watch = NULL; 241 242 /* move us one more past the eop_desc for start of next pkt */ 243 tx_buffer++; 244 i++; 245 if (unlikely(i == tx_ring->count)) { 246 i = 0; 247 tx_buffer = tx_ring->tx_buffer_info; 248 } 249 } 250 251 if (tx_ring->xsk_pool && xsk_frames) 252 xsk_tx_completed(tx_ring->xsk_pool, xsk_frames); 253 254 /* reset BQL for queue */ 255 netdev_tx_reset_queue(txring_txq(tx_ring)); 256 257 /* Zero out the buffer ring */ 258 memset(tx_ring->tx_buffer_info, 0, 259 sizeof(*tx_ring->tx_buffer_info) * tx_ring->count); 260 261 /* Zero out the descriptor ring */ 262 memset(tx_ring->desc, 0, tx_ring->size); 263 264 /* reset next_to_use and next_to_clean */ 265 tx_ring->next_to_use = 0; 266 tx_ring->next_to_clean = 0; 267 } 268 269 /** 270 * igc_free_tx_resources - Free Tx Resources per Queue 271 * @tx_ring: Tx descriptor ring for a specific queue 272 * 273 * Free all transmit software resources 274 */ 275 void igc_free_tx_resources(struct igc_ring *tx_ring) 276 { 277 igc_disable_tx_ring(tx_ring); 278 279 vfree(tx_ring->tx_buffer_info); 280 tx_ring->tx_buffer_info = NULL; 281 282 /* if not set, then don't free */ 283 if (!tx_ring->desc) 284 return; 285 286 dma_free_coherent(tx_ring->dev, tx_ring->size, 287 tx_ring->desc, tx_ring->dma); 288 289 tx_ring->desc = NULL; 290 } 291 292 /** 293 * igc_free_all_tx_resources - Free Tx Resources for All Queues 294 * @adapter: board private structure 295 * 296 * Free all transmit software resources 297 */ 298 static void igc_free_all_tx_resources(struct igc_adapter *adapter) 299 { 300 int i; 301 302 for (i = 0; i < adapter->num_tx_queues; i++) 303 igc_free_tx_resources(adapter->tx_ring[i]); 304 } 305 306 /** 307 * igc_clean_all_tx_rings - Free Tx Buffers for all queues 308 * @adapter: board private structure 309 */ 310 static void igc_clean_all_tx_rings(struct igc_adapter *adapter) 311 { 312 int i; 313 314 for (i = 0; i < adapter->num_tx_queues; i++) 315 if (adapter->tx_ring[i]) 316 igc_clean_tx_ring(adapter->tx_ring[i]); 317 } 318 319 static void igc_disable_tx_ring_hw(struct igc_ring *ring) 320 { 321 struct igc_hw *hw = &ring->q_vector->adapter->hw; 322 u8 idx = ring->reg_idx; 323 u32 txdctl; 324 325 txdctl = rd32(IGC_TXDCTL(idx)); 326 txdctl &= ~IGC_TXDCTL_QUEUE_ENABLE; 327 txdctl |= IGC_TXDCTL_SWFLUSH; 328 wr32(IGC_TXDCTL(idx), txdctl); 329 } 330 331 /** 332 * igc_disable_all_tx_rings_hw - Disable all transmit queue operation 333 * @adapter: board private structure 334 */ 335 static void igc_disable_all_tx_rings_hw(struct igc_adapter *adapter) 336 { 337 int i; 338 339 for (i = 0; i < adapter->num_tx_queues; i++) { 340 struct igc_ring *tx_ring = adapter->tx_ring[i]; 341 342 igc_disable_tx_ring_hw(tx_ring); 343 } 344 } 345 346 /** 347 * igc_setup_tx_resources - allocate Tx resources (Descriptors) 348 * @tx_ring: tx descriptor ring (for a specific queue) to setup 349 * 350 * Return 0 on success, negative on failure 351 */ 352 int igc_setup_tx_resources(struct igc_ring *tx_ring) 353 { 354 struct net_device *ndev = tx_ring->netdev; 355 struct device *dev = tx_ring->dev; 356 int size = 0; 357 358 size = sizeof(struct igc_tx_buffer) * tx_ring->count; 359 tx_ring->tx_buffer_info = vzalloc(size); 360 if (!tx_ring->tx_buffer_info) 361 goto err; 362 363 /* round up to nearest 4K */ 364 tx_ring->size = tx_ring->count * sizeof(union igc_adv_tx_desc); 365 tx_ring->size = ALIGN(tx_ring->size, 4096); 366 367 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 368 &tx_ring->dma, GFP_KERNEL); 369 370 if (!tx_ring->desc) 371 goto err; 372 373 tx_ring->next_to_use = 0; 374 tx_ring->next_to_clean = 0; 375 376 return 0; 377 378 err: 379 vfree(tx_ring->tx_buffer_info); 380 netdev_err(ndev, "Unable to allocate memory for Tx descriptor ring\n"); 381 return -ENOMEM; 382 } 383 384 /** 385 * igc_setup_all_tx_resources - wrapper to allocate Tx resources for all queues 386 * @adapter: board private structure 387 * 388 * Return 0 on success, negative on failure 389 */ 390 static int igc_setup_all_tx_resources(struct igc_adapter *adapter) 391 { 392 struct net_device *dev = adapter->netdev; 393 int i, err = 0; 394 395 for (i = 0; i < adapter->num_tx_queues; i++) { 396 err = igc_setup_tx_resources(adapter->tx_ring[i]); 397 if (err) { 398 netdev_err(dev, "Error on Tx queue %u setup\n", i); 399 for (i--; i >= 0; i--) 400 igc_free_tx_resources(adapter->tx_ring[i]); 401 break; 402 } 403 } 404 405 return err; 406 } 407 408 static void igc_clean_rx_ring_page_shared(struct igc_ring *rx_ring) 409 { 410 u16 i = rx_ring->next_to_clean; 411 412 dev_kfree_skb(rx_ring->skb); 413 rx_ring->skb = NULL; 414 415 /* Free all the Rx ring sk_buffs */ 416 while (i != rx_ring->next_to_alloc) { 417 struct igc_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 418 419 /* Invalidate cache lines that may have been written to by 420 * device so that we avoid corrupting memory. 421 */ 422 dma_sync_single_range_for_cpu(rx_ring->dev, 423 buffer_info->dma, 424 buffer_info->page_offset, 425 igc_rx_bufsz(rx_ring), 426 DMA_FROM_DEVICE); 427 428 /* free resources associated with mapping */ 429 dma_unmap_page_attrs(rx_ring->dev, 430 buffer_info->dma, 431 igc_rx_pg_size(rx_ring), 432 DMA_FROM_DEVICE, 433 IGC_RX_DMA_ATTR); 434 __page_frag_cache_drain(buffer_info->page, 435 buffer_info->pagecnt_bias); 436 437 i++; 438 if (i == rx_ring->count) 439 i = 0; 440 } 441 } 442 443 static void igc_clean_rx_ring_xsk_pool(struct igc_ring *ring) 444 { 445 struct igc_rx_buffer *bi; 446 u16 i; 447 448 for (i = 0; i < ring->count; i++) { 449 bi = &ring->rx_buffer_info[i]; 450 if (!bi->xdp) 451 continue; 452 453 xsk_buff_free(bi->xdp); 454 bi->xdp = NULL; 455 } 456 } 457 458 /** 459 * igc_clean_rx_ring - Free Rx Buffers per Queue 460 * @ring: ring to free buffers from 461 */ 462 static void igc_clean_rx_ring(struct igc_ring *ring) 463 { 464 if (ring->xsk_pool) 465 igc_clean_rx_ring_xsk_pool(ring); 466 else 467 igc_clean_rx_ring_page_shared(ring); 468 469 clear_ring_uses_large_buffer(ring); 470 471 ring->next_to_alloc = 0; 472 ring->next_to_clean = 0; 473 ring->next_to_use = 0; 474 } 475 476 /** 477 * igc_clean_all_rx_rings - Free Rx Buffers for all queues 478 * @adapter: board private structure 479 */ 480 static void igc_clean_all_rx_rings(struct igc_adapter *adapter) 481 { 482 int i; 483 484 for (i = 0; i < adapter->num_rx_queues; i++) 485 if (adapter->rx_ring[i]) 486 igc_clean_rx_ring(adapter->rx_ring[i]); 487 } 488 489 /** 490 * igc_free_rx_resources - Free Rx Resources 491 * @rx_ring: ring to clean the resources from 492 * 493 * Free all receive software resources 494 */ 495 void igc_free_rx_resources(struct igc_ring *rx_ring) 496 { 497 igc_clean_rx_ring(rx_ring); 498 499 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 500 501 vfree(rx_ring->rx_buffer_info); 502 rx_ring->rx_buffer_info = NULL; 503 504 /* if not set, then don't free */ 505 if (!rx_ring->desc) 506 return; 507 508 dma_free_coherent(rx_ring->dev, rx_ring->size, 509 rx_ring->desc, rx_ring->dma); 510 511 rx_ring->desc = NULL; 512 } 513 514 /** 515 * igc_free_all_rx_resources - Free Rx Resources for All Queues 516 * @adapter: board private structure 517 * 518 * Free all receive software resources 519 */ 520 static void igc_free_all_rx_resources(struct igc_adapter *adapter) 521 { 522 int i; 523 524 for (i = 0; i < adapter->num_rx_queues; i++) 525 igc_free_rx_resources(adapter->rx_ring[i]); 526 } 527 528 /** 529 * igc_setup_rx_resources - allocate Rx resources (Descriptors) 530 * @rx_ring: rx descriptor ring (for a specific queue) to setup 531 * 532 * Returns 0 on success, negative on failure 533 */ 534 int igc_setup_rx_resources(struct igc_ring *rx_ring) 535 { 536 struct net_device *ndev = rx_ring->netdev; 537 struct device *dev = rx_ring->dev; 538 u8 index = rx_ring->queue_index; 539 int size, desc_len, res; 540 541 /* XDP RX-queue info */ 542 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq)) 543 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 544 res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, ndev, index, 545 rx_ring->q_vector->napi.napi_id); 546 if (res < 0) { 547 netdev_err(ndev, "Failed to register xdp_rxq index %u\n", 548 index); 549 return res; 550 } 551 552 size = sizeof(struct igc_rx_buffer) * rx_ring->count; 553 rx_ring->rx_buffer_info = vzalloc(size); 554 if (!rx_ring->rx_buffer_info) 555 goto err; 556 557 desc_len = sizeof(union igc_adv_rx_desc); 558 559 /* Round up to nearest 4K */ 560 rx_ring->size = rx_ring->count * desc_len; 561 rx_ring->size = ALIGN(rx_ring->size, 4096); 562 563 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 564 &rx_ring->dma, GFP_KERNEL); 565 566 if (!rx_ring->desc) 567 goto err; 568 569 rx_ring->next_to_alloc = 0; 570 rx_ring->next_to_clean = 0; 571 rx_ring->next_to_use = 0; 572 573 return 0; 574 575 err: 576 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 577 vfree(rx_ring->rx_buffer_info); 578 rx_ring->rx_buffer_info = NULL; 579 netdev_err(ndev, "Unable to allocate memory for Rx descriptor ring\n"); 580 return -ENOMEM; 581 } 582 583 /** 584 * igc_setup_all_rx_resources - wrapper to allocate Rx resources 585 * (Descriptors) for all queues 586 * @adapter: board private structure 587 * 588 * Return 0 on success, negative on failure 589 */ 590 static int igc_setup_all_rx_resources(struct igc_adapter *adapter) 591 { 592 struct net_device *dev = adapter->netdev; 593 int i, err = 0; 594 595 for (i = 0; i < adapter->num_rx_queues; i++) { 596 err = igc_setup_rx_resources(adapter->rx_ring[i]); 597 if (err) { 598 netdev_err(dev, "Error on Rx queue %u setup\n", i); 599 for (i--; i >= 0; i--) 600 igc_free_rx_resources(adapter->rx_ring[i]); 601 break; 602 } 603 } 604 605 return err; 606 } 607 608 static struct xsk_buff_pool *igc_get_xsk_pool(struct igc_adapter *adapter, 609 struct igc_ring *ring) 610 { 611 if (!igc_xdp_is_enabled(adapter) || 612 !test_bit(IGC_RING_FLAG_AF_XDP_ZC, &ring->flags)) 613 return NULL; 614 615 return xsk_get_pool_from_qid(ring->netdev, ring->queue_index); 616 } 617 618 /** 619 * igc_configure_rx_ring - Configure a receive ring after Reset 620 * @adapter: board private structure 621 * @ring: receive ring to be configured 622 * 623 * Configure the Rx unit of the MAC after a reset. 624 */ 625 static void igc_configure_rx_ring(struct igc_adapter *adapter, 626 struct igc_ring *ring) 627 { 628 struct igc_hw *hw = &adapter->hw; 629 union igc_adv_rx_desc *rx_desc; 630 int reg_idx = ring->reg_idx; 631 u32 srrctl = 0, rxdctl = 0; 632 u64 rdba = ring->dma; 633 u32 buf_size; 634 635 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 636 ring->xsk_pool = igc_get_xsk_pool(adapter, ring); 637 if (ring->xsk_pool) { 638 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 639 MEM_TYPE_XSK_BUFF_POOL, 640 NULL)); 641 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq); 642 } else { 643 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 644 MEM_TYPE_PAGE_SHARED, 645 NULL)); 646 } 647 648 if (igc_xdp_is_enabled(adapter)) 649 set_ring_uses_large_buffer(ring); 650 651 /* disable the queue */ 652 wr32(IGC_RXDCTL(reg_idx), 0); 653 654 /* Set DMA base address registers */ 655 wr32(IGC_RDBAL(reg_idx), 656 rdba & 0x00000000ffffffffULL); 657 wr32(IGC_RDBAH(reg_idx), rdba >> 32); 658 wr32(IGC_RDLEN(reg_idx), 659 ring->count * sizeof(union igc_adv_rx_desc)); 660 661 /* initialize head and tail */ 662 ring->tail = adapter->io_addr + IGC_RDT(reg_idx); 663 wr32(IGC_RDH(reg_idx), 0); 664 writel(0, ring->tail); 665 666 /* reset next-to- use/clean to place SW in sync with hardware */ 667 ring->next_to_clean = 0; 668 ring->next_to_use = 0; 669 670 if (ring->xsk_pool) 671 buf_size = xsk_pool_get_rx_frame_size(ring->xsk_pool); 672 else if (ring_uses_large_buffer(ring)) 673 buf_size = IGC_RXBUFFER_3072; 674 else 675 buf_size = IGC_RXBUFFER_2048; 676 677 srrctl = rd32(IGC_SRRCTL(reg_idx)); 678 srrctl &= ~(IGC_SRRCTL_BSIZEPKT_MASK | IGC_SRRCTL_BSIZEHDR_MASK | 679 IGC_SRRCTL_DESCTYPE_MASK); 680 srrctl |= IGC_SRRCTL_BSIZEHDR(IGC_RX_HDR_LEN); 681 srrctl |= IGC_SRRCTL_BSIZEPKT(buf_size); 682 srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF; 683 684 wr32(IGC_SRRCTL(reg_idx), srrctl); 685 686 rxdctl |= IGC_RX_PTHRESH; 687 rxdctl |= IGC_RX_HTHRESH << 8; 688 rxdctl |= IGC_RX_WTHRESH << 16; 689 690 /* initialize rx_buffer_info */ 691 memset(ring->rx_buffer_info, 0, 692 sizeof(struct igc_rx_buffer) * ring->count); 693 694 /* initialize Rx descriptor 0 */ 695 rx_desc = IGC_RX_DESC(ring, 0); 696 rx_desc->wb.upper.length = 0; 697 698 /* enable receive descriptor fetching */ 699 rxdctl |= IGC_RXDCTL_QUEUE_ENABLE; 700 701 wr32(IGC_RXDCTL(reg_idx), rxdctl); 702 } 703 704 /** 705 * igc_configure_rx - Configure receive Unit after Reset 706 * @adapter: board private structure 707 * 708 * Configure the Rx unit of the MAC after a reset. 709 */ 710 static void igc_configure_rx(struct igc_adapter *adapter) 711 { 712 int i; 713 714 /* Setup the HW Rx Head and Tail Descriptor Pointers and 715 * the Base and Length of the Rx Descriptor Ring 716 */ 717 for (i = 0; i < adapter->num_rx_queues; i++) 718 igc_configure_rx_ring(adapter, adapter->rx_ring[i]); 719 } 720 721 /** 722 * igc_configure_tx_ring - Configure transmit ring after Reset 723 * @adapter: board private structure 724 * @ring: tx ring to configure 725 * 726 * Configure a transmit ring after a reset. 727 */ 728 static void igc_configure_tx_ring(struct igc_adapter *adapter, 729 struct igc_ring *ring) 730 { 731 struct igc_hw *hw = &adapter->hw; 732 int reg_idx = ring->reg_idx; 733 u64 tdba = ring->dma; 734 u32 txdctl = 0; 735 736 ring->xsk_pool = igc_get_xsk_pool(adapter, ring); 737 738 /* disable the queue */ 739 wr32(IGC_TXDCTL(reg_idx), 0); 740 wrfl(); 741 742 wr32(IGC_TDLEN(reg_idx), 743 ring->count * sizeof(union igc_adv_tx_desc)); 744 wr32(IGC_TDBAL(reg_idx), 745 tdba & 0x00000000ffffffffULL); 746 wr32(IGC_TDBAH(reg_idx), tdba >> 32); 747 748 ring->tail = adapter->io_addr + IGC_TDT(reg_idx); 749 wr32(IGC_TDH(reg_idx), 0); 750 writel(0, ring->tail); 751 752 txdctl |= IGC_TX_PTHRESH; 753 txdctl |= IGC_TX_HTHRESH << 8; 754 txdctl |= IGC_TX_WTHRESH << 16; 755 756 txdctl |= IGC_TXDCTL_QUEUE_ENABLE; 757 wr32(IGC_TXDCTL(reg_idx), txdctl); 758 } 759 760 /** 761 * igc_configure_tx - Configure transmit Unit after Reset 762 * @adapter: board private structure 763 * 764 * Configure the Tx unit of the MAC after a reset. 765 */ 766 static void igc_configure_tx(struct igc_adapter *adapter) 767 { 768 int i; 769 770 for (i = 0; i < adapter->num_tx_queues; i++) 771 igc_configure_tx_ring(adapter, adapter->tx_ring[i]); 772 } 773 774 /** 775 * igc_setup_mrqc - configure the multiple receive queue control registers 776 * @adapter: Board private structure 777 */ 778 static void igc_setup_mrqc(struct igc_adapter *adapter) 779 { 780 struct igc_hw *hw = &adapter->hw; 781 u32 j, num_rx_queues; 782 u32 mrqc, rxcsum; 783 u32 rss_key[10]; 784 785 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 786 for (j = 0; j < 10; j++) 787 wr32(IGC_RSSRK(j), rss_key[j]); 788 789 num_rx_queues = adapter->rss_queues; 790 791 if (adapter->rss_indir_tbl_init != num_rx_queues) { 792 for (j = 0; j < IGC_RETA_SIZE; j++) 793 adapter->rss_indir_tbl[j] = 794 (j * num_rx_queues) / IGC_RETA_SIZE; 795 adapter->rss_indir_tbl_init = num_rx_queues; 796 } 797 igc_write_rss_indir_tbl(adapter); 798 799 /* Disable raw packet checksumming so that RSS hash is placed in 800 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 801 * offloads as they are enabled by default 802 */ 803 rxcsum = rd32(IGC_RXCSUM); 804 rxcsum |= IGC_RXCSUM_PCSD; 805 806 /* Enable Receive Checksum Offload for SCTP */ 807 rxcsum |= IGC_RXCSUM_CRCOFL; 808 809 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 810 wr32(IGC_RXCSUM, rxcsum); 811 812 /* Generate RSS hash based on packet types, TCP/UDP 813 * port numbers and/or IPv4/v6 src and dst addresses 814 */ 815 mrqc = IGC_MRQC_RSS_FIELD_IPV4 | 816 IGC_MRQC_RSS_FIELD_IPV4_TCP | 817 IGC_MRQC_RSS_FIELD_IPV6 | 818 IGC_MRQC_RSS_FIELD_IPV6_TCP | 819 IGC_MRQC_RSS_FIELD_IPV6_TCP_EX; 820 821 if (adapter->flags & IGC_FLAG_RSS_FIELD_IPV4_UDP) 822 mrqc |= IGC_MRQC_RSS_FIELD_IPV4_UDP; 823 if (adapter->flags & IGC_FLAG_RSS_FIELD_IPV6_UDP) 824 mrqc |= IGC_MRQC_RSS_FIELD_IPV6_UDP; 825 826 mrqc |= IGC_MRQC_ENABLE_RSS_MQ; 827 828 wr32(IGC_MRQC, mrqc); 829 } 830 831 /** 832 * igc_setup_rctl - configure the receive control registers 833 * @adapter: Board private structure 834 */ 835 static void igc_setup_rctl(struct igc_adapter *adapter) 836 { 837 struct igc_hw *hw = &adapter->hw; 838 u32 rctl; 839 840 rctl = rd32(IGC_RCTL); 841 842 rctl &= ~(3 << IGC_RCTL_MO_SHIFT); 843 rctl &= ~(IGC_RCTL_LBM_TCVR | IGC_RCTL_LBM_MAC); 844 845 rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | IGC_RCTL_RDMTS_HALF | 846 (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT); 847 848 /* enable stripping of CRC. Newer features require 849 * that the HW strips the CRC. 850 */ 851 rctl |= IGC_RCTL_SECRC; 852 853 /* disable store bad packets and clear size bits. */ 854 rctl &= ~(IGC_RCTL_SBP | IGC_RCTL_SZ_256); 855 856 /* enable LPE to allow for reception of jumbo frames */ 857 rctl |= IGC_RCTL_LPE; 858 859 /* disable queue 0 to prevent tail write w/o re-config */ 860 wr32(IGC_RXDCTL(0), 0); 861 862 /* This is useful for sniffing bad packets. */ 863 if (adapter->netdev->features & NETIF_F_RXALL) { 864 /* UPE and MPE will be handled by normal PROMISC logic 865 * in set_rx_mode 866 */ 867 rctl |= (IGC_RCTL_SBP | /* Receive bad packets */ 868 IGC_RCTL_BAM | /* RX All Bcast Pkts */ 869 IGC_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 870 871 rctl &= ~(IGC_RCTL_DPF | /* Allow filtered pause */ 872 IGC_RCTL_CFIEN); /* Disable VLAN CFIEN Filter */ 873 } 874 875 wr32(IGC_RCTL, rctl); 876 } 877 878 /** 879 * igc_setup_tctl - configure the transmit control registers 880 * @adapter: Board private structure 881 */ 882 static void igc_setup_tctl(struct igc_adapter *adapter) 883 { 884 struct igc_hw *hw = &adapter->hw; 885 u32 tctl; 886 887 /* disable queue 0 which icould be enabled by default */ 888 wr32(IGC_TXDCTL(0), 0); 889 890 /* Program the Transmit Control Register */ 891 tctl = rd32(IGC_TCTL); 892 tctl &= ~IGC_TCTL_CT; 893 tctl |= IGC_TCTL_PSP | IGC_TCTL_RTLC | 894 (IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT); 895 896 /* Enable transmits */ 897 tctl |= IGC_TCTL_EN; 898 899 wr32(IGC_TCTL, tctl); 900 } 901 902 /** 903 * igc_set_mac_filter_hw() - Set MAC address filter in hardware 904 * @adapter: Pointer to adapter where the filter should be set 905 * @index: Filter index 906 * @type: MAC address filter type (source or destination) 907 * @addr: MAC address 908 * @queue: If non-negative, queue assignment feature is enabled and frames 909 * matching the filter are enqueued onto 'queue'. Otherwise, queue 910 * assignment is disabled. 911 */ 912 static void igc_set_mac_filter_hw(struct igc_adapter *adapter, int index, 913 enum igc_mac_filter_type type, 914 const u8 *addr, int queue) 915 { 916 struct net_device *dev = adapter->netdev; 917 struct igc_hw *hw = &adapter->hw; 918 u32 ral, rah; 919 920 if (WARN_ON(index >= hw->mac.rar_entry_count)) 921 return; 922 923 ral = le32_to_cpup((__le32 *)(addr)); 924 rah = le16_to_cpup((__le16 *)(addr + 4)); 925 926 if (type == IGC_MAC_FILTER_TYPE_SRC) { 927 rah &= ~IGC_RAH_ASEL_MASK; 928 rah |= IGC_RAH_ASEL_SRC_ADDR; 929 } 930 931 if (queue >= 0) { 932 rah &= ~IGC_RAH_QSEL_MASK; 933 rah |= (queue << IGC_RAH_QSEL_SHIFT); 934 rah |= IGC_RAH_QSEL_ENABLE; 935 } 936 937 rah |= IGC_RAH_AV; 938 939 wr32(IGC_RAL(index), ral); 940 wr32(IGC_RAH(index), rah); 941 942 netdev_dbg(dev, "MAC address filter set in HW: index %d", index); 943 } 944 945 /** 946 * igc_clear_mac_filter_hw() - Clear MAC address filter in hardware 947 * @adapter: Pointer to adapter where the filter should be cleared 948 * @index: Filter index 949 */ 950 static void igc_clear_mac_filter_hw(struct igc_adapter *adapter, int index) 951 { 952 struct net_device *dev = adapter->netdev; 953 struct igc_hw *hw = &adapter->hw; 954 955 if (WARN_ON(index >= hw->mac.rar_entry_count)) 956 return; 957 958 wr32(IGC_RAL(index), 0); 959 wr32(IGC_RAH(index), 0); 960 961 netdev_dbg(dev, "MAC address filter cleared in HW: index %d", index); 962 } 963 964 /* Set default MAC address for the PF in the first RAR entry */ 965 static void igc_set_default_mac_filter(struct igc_adapter *adapter) 966 { 967 struct net_device *dev = adapter->netdev; 968 u8 *addr = adapter->hw.mac.addr; 969 970 netdev_dbg(dev, "Set default MAC address filter: address %pM", addr); 971 972 igc_set_mac_filter_hw(adapter, 0, IGC_MAC_FILTER_TYPE_DST, addr, -1); 973 } 974 975 /** 976 * igc_set_mac - Change the Ethernet Address of the NIC 977 * @netdev: network interface device structure 978 * @p: pointer to an address structure 979 * 980 * Returns 0 on success, negative on failure 981 */ 982 static int igc_set_mac(struct net_device *netdev, void *p) 983 { 984 struct igc_adapter *adapter = netdev_priv(netdev); 985 struct igc_hw *hw = &adapter->hw; 986 struct sockaddr *addr = p; 987 988 if (!is_valid_ether_addr(addr->sa_data)) 989 return -EADDRNOTAVAIL; 990 991 eth_hw_addr_set(netdev, addr->sa_data); 992 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 993 994 /* set the correct pool for the new PF MAC address in entry 0 */ 995 igc_set_default_mac_filter(adapter); 996 997 return 0; 998 } 999 1000 /** 1001 * igc_write_mc_addr_list - write multicast addresses to MTA 1002 * @netdev: network interface device structure 1003 * 1004 * Writes multicast address list to the MTA hash table. 1005 * Returns: -ENOMEM on failure 1006 * 0 on no addresses written 1007 * X on writing X addresses to MTA 1008 **/ 1009 static int igc_write_mc_addr_list(struct net_device *netdev) 1010 { 1011 struct igc_adapter *adapter = netdev_priv(netdev); 1012 struct igc_hw *hw = &adapter->hw; 1013 struct netdev_hw_addr *ha; 1014 u8 *mta_list; 1015 int i; 1016 1017 if (netdev_mc_empty(netdev)) { 1018 /* nothing to program, so clear mc list */ 1019 igc_update_mc_addr_list(hw, NULL, 0); 1020 return 0; 1021 } 1022 1023 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 1024 if (!mta_list) 1025 return -ENOMEM; 1026 1027 /* The shared function expects a packed array of only addresses. */ 1028 i = 0; 1029 netdev_for_each_mc_addr(ha, netdev) 1030 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 1031 1032 igc_update_mc_addr_list(hw, mta_list, i); 1033 kfree(mta_list); 1034 1035 return netdev_mc_count(netdev); 1036 } 1037 1038 static __le32 igc_tx_launchtime(struct igc_ring *ring, ktime_t txtime, 1039 bool *first_flag, bool *insert_empty) 1040 { 1041 struct igc_adapter *adapter = netdev_priv(ring->netdev); 1042 ktime_t cycle_time = adapter->cycle_time; 1043 ktime_t base_time = adapter->base_time; 1044 ktime_t now = ktime_get_clocktai(); 1045 ktime_t baset_est, end_of_cycle; 1046 s32 launchtime; 1047 s64 n; 1048 1049 n = div64_s64(ktime_sub_ns(now, base_time), cycle_time); 1050 1051 baset_est = ktime_add_ns(base_time, cycle_time * (n)); 1052 end_of_cycle = ktime_add_ns(baset_est, cycle_time); 1053 1054 if (ktime_compare(txtime, end_of_cycle) >= 0) { 1055 if (baset_est != ring->last_ff_cycle) { 1056 *first_flag = true; 1057 ring->last_ff_cycle = baset_est; 1058 1059 if (ktime_compare(end_of_cycle, ring->last_tx_cycle) > 0) 1060 *insert_empty = true; 1061 } 1062 } 1063 1064 /* Introducing a window at end of cycle on which packets 1065 * potentially not honor launchtime. Window of 5us chosen 1066 * considering software update the tail pointer and packets 1067 * are dma'ed to packet buffer. 1068 */ 1069 if ((ktime_sub_ns(end_of_cycle, now) < 5 * NSEC_PER_USEC)) 1070 netdev_warn(ring->netdev, "Packet with txtime=%llu may not be honoured\n", 1071 txtime); 1072 1073 ring->last_tx_cycle = end_of_cycle; 1074 1075 launchtime = ktime_sub_ns(txtime, baset_est); 1076 if (launchtime > 0) 1077 div_s64_rem(launchtime, cycle_time, &launchtime); 1078 else 1079 launchtime = 0; 1080 1081 return cpu_to_le32(launchtime); 1082 } 1083 1084 static int igc_init_empty_frame(struct igc_ring *ring, 1085 struct igc_tx_buffer *buffer, 1086 struct sk_buff *skb) 1087 { 1088 unsigned int size; 1089 dma_addr_t dma; 1090 1091 size = skb_headlen(skb); 1092 1093 dma = dma_map_single(ring->dev, skb->data, size, DMA_TO_DEVICE); 1094 if (dma_mapping_error(ring->dev, dma)) { 1095 netdev_err_once(ring->netdev, "Failed to map DMA for TX\n"); 1096 return -ENOMEM; 1097 } 1098 1099 buffer->skb = skb; 1100 buffer->protocol = 0; 1101 buffer->bytecount = skb->len; 1102 buffer->gso_segs = 1; 1103 buffer->time_stamp = jiffies; 1104 dma_unmap_len_set(buffer, len, skb->len); 1105 dma_unmap_addr_set(buffer, dma, dma); 1106 1107 return 0; 1108 } 1109 1110 static int igc_init_tx_empty_descriptor(struct igc_ring *ring, 1111 struct sk_buff *skb, 1112 struct igc_tx_buffer *first) 1113 { 1114 union igc_adv_tx_desc *desc; 1115 u32 cmd_type, olinfo_status; 1116 int err; 1117 1118 if (!igc_desc_unused(ring)) 1119 return -EBUSY; 1120 1121 err = igc_init_empty_frame(ring, first, skb); 1122 if (err) 1123 return err; 1124 1125 cmd_type = IGC_ADVTXD_DTYP_DATA | IGC_ADVTXD_DCMD_DEXT | 1126 IGC_ADVTXD_DCMD_IFCS | IGC_TXD_DCMD | 1127 first->bytecount; 1128 olinfo_status = first->bytecount << IGC_ADVTXD_PAYLEN_SHIFT; 1129 1130 desc = IGC_TX_DESC(ring, ring->next_to_use); 1131 desc->read.cmd_type_len = cpu_to_le32(cmd_type); 1132 desc->read.olinfo_status = cpu_to_le32(olinfo_status); 1133 desc->read.buffer_addr = cpu_to_le64(dma_unmap_addr(first, dma)); 1134 1135 netdev_tx_sent_queue(txring_txq(ring), skb->len); 1136 1137 first->next_to_watch = desc; 1138 1139 ring->next_to_use++; 1140 if (ring->next_to_use == ring->count) 1141 ring->next_to_use = 0; 1142 1143 return 0; 1144 } 1145 1146 #define IGC_EMPTY_FRAME_SIZE 60 1147 1148 static void igc_tx_ctxtdesc(struct igc_ring *tx_ring, 1149 __le32 launch_time, bool first_flag, 1150 u32 vlan_macip_lens, u32 type_tucmd, 1151 u32 mss_l4len_idx) 1152 { 1153 struct igc_adv_tx_context_desc *context_desc; 1154 u16 i = tx_ring->next_to_use; 1155 1156 context_desc = IGC_TX_CTXTDESC(tx_ring, i); 1157 1158 i++; 1159 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 1160 1161 /* set bits to identify this as an advanced context descriptor */ 1162 type_tucmd |= IGC_TXD_CMD_DEXT | IGC_ADVTXD_DTYP_CTXT; 1163 1164 /* For i225, context index must be unique per ring. */ 1165 if (test_bit(IGC_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 1166 mss_l4len_idx |= tx_ring->reg_idx << 4; 1167 1168 if (first_flag) 1169 mss_l4len_idx |= IGC_ADVTXD_TSN_CNTX_FIRST; 1170 1171 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 1172 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 1173 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 1174 context_desc->launch_time = launch_time; 1175 } 1176 1177 static void igc_tx_csum(struct igc_ring *tx_ring, struct igc_tx_buffer *first, 1178 __le32 launch_time, bool first_flag) 1179 { 1180 struct sk_buff *skb = first->skb; 1181 u32 vlan_macip_lens = 0; 1182 u32 type_tucmd = 0; 1183 1184 if (skb->ip_summed != CHECKSUM_PARTIAL) { 1185 csum_failed: 1186 if (!(first->tx_flags & IGC_TX_FLAGS_VLAN) && 1187 !tx_ring->launchtime_enable) 1188 return; 1189 goto no_csum; 1190 } 1191 1192 switch (skb->csum_offset) { 1193 case offsetof(struct tcphdr, check): 1194 type_tucmd = IGC_ADVTXD_TUCMD_L4T_TCP; 1195 fallthrough; 1196 case offsetof(struct udphdr, check): 1197 break; 1198 case offsetof(struct sctphdr, checksum): 1199 /* validate that this is actually an SCTP request */ 1200 if (skb_csum_is_sctp(skb)) { 1201 type_tucmd = IGC_ADVTXD_TUCMD_L4T_SCTP; 1202 break; 1203 } 1204 fallthrough; 1205 default: 1206 skb_checksum_help(skb); 1207 goto csum_failed; 1208 } 1209 1210 /* update TX checksum flag */ 1211 first->tx_flags |= IGC_TX_FLAGS_CSUM; 1212 vlan_macip_lens = skb_checksum_start_offset(skb) - 1213 skb_network_offset(skb); 1214 no_csum: 1215 vlan_macip_lens |= skb_network_offset(skb) << IGC_ADVTXD_MACLEN_SHIFT; 1216 vlan_macip_lens |= first->tx_flags & IGC_TX_FLAGS_VLAN_MASK; 1217 1218 igc_tx_ctxtdesc(tx_ring, launch_time, first_flag, 1219 vlan_macip_lens, type_tucmd, 0); 1220 } 1221 1222 static int __igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size) 1223 { 1224 struct net_device *netdev = tx_ring->netdev; 1225 1226 netif_stop_subqueue(netdev, tx_ring->queue_index); 1227 1228 /* memory barriier comment */ 1229 smp_mb(); 1230 1231 /* We need to check again in a case another CPU has just 1232 * made room available. 1233 */ 1234 if (igc_desc_unused(tx_ring) < size) 1235 return -EBUSY; 1236 1237 /* A reprieve! */ 1238 netif_wake_subqueue(netdev, tx_ring->queue_index); 1239 1240 u64_stats_update_begin(&tx_ring->tx_syncp2); 1241 tx_ring->tx_stats.restart_queue2++; 1242 u64_stats_update_end(&tx_ring->tx_syncp2); 1243 1244 return 0; 1245 } 1246 1247 static inline int igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size) 1248 { 1249 if (igc_desc_unused(tx_ring) >= size) 1250 return 0; 1251 return __igc_maybe_stop_tx(tx_ring, size); 1252 } 1253 1254 #define IGC_SET_FLAG(_input, _flag, _result) \ 1255 (((_flag) <= (_result)) ? \ 1256 ((u32)((_input) & (_flag)) * ((_result) / (_flag))) : \ 1257 ((u32)((_input) & (_flag)) / ((_flag) / (_result)))) 1258 1259 static u32 igc_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 1260 { 1261 /* set type for advanced descriptor with frame checksum insertion */ 1262 u32 cmd_type = IGC_ADVTXD_DTYP_DATA | 1263 IGC_ADVTXD_DCMD_DEXT | 1264 IGC_ADVTXD_DCMD_IFCS; 1265 1266 /* set HW vlan bit if vlan is present */ 1267 cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_VLAN, 1268 IGC_ADVTXD_DCMD_VLE); 1269 1270 /* set segmentation bits for TSO */ 1271 cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSO, 1272 (IGC_ADVTXD_DCMD_TSE)); 1273 1274 /* set timestamp bit if present, will select the register set 1275 * based on the _TSTAMP(_X) bit. 1276 */ 1277 cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP, 1278 (IGC_ADVTXD_MAC_TSTAMP)); 1279 1280 cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP_1, 1281 (IGC_ADVTXD_TSTAMP_REG_1)); 1282 1283 cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP_2, 1284 (IGC_ADVTXD_TSTAMP_REG_2)); 1285 1286 cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP_3, 1287 (IGC_ADVTXD_TSTAMP_REG_3)); 1288 1289 /* insert frame checksum */ 1290 cmd_type ^= IGC_SET_FLAG(skb->no_fcs, 1, IGC_ADVTXD_DCMD_IFCS); 1291 1292 return cmd_type; 1293 } 1294 1295 static void igc_tx_olinfo_status(struct igc_ring *tx_ring, 1296 union igc_adv_tx_desc *tx_desc, 1297 u32 tx_flags, unsigned int paylen) 1298 { 1299 u32 olinfo_status = paylen << IGC_ADVTXD_PAYLEN_SHIFT; 1300 1301 /* insert L4 checksum */ 1302 olinfo_status |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_CSUM, 1303 (IGC_TXD_POPTS_TXSM << 8)); 1304 1305 /* insert IPv4 checksum */ 1306 olinfo_status |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_IPV4, 1307 (IGC_TXD_POPTS_IXSM << 8)); 1308 1309 /* Use the second timer (free running, in general) for the timestamp */ 1310 olinfo_status |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP_TIMER_1, 1311 IGC_TXD_PTP2_TIMER_1); 1312 1313 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 1314 } 1315 1316 static int igc_tx_map(struct igc_ring *tx_ring, 1317 struct igc_tx_buffer *first, 1318 const u8 hdr_len) 1319 { 1320 struct sk_buff *skb = first->skb; 1321 struct igc_tx_buffer *tx_buffer; 1322 union igc_adv_tx_desc *tx_desc; 1323 u32 tx_flags = first->tx_flags; 1324 skb_frag_t *frag; 1325 u16 i = tx_ring->next_to_use; 1326 unsigned int data_len, size; 1327 dma_addr_t dma; 1328 u32 cmd_type; 1329 1330 cmd_type = igc_tx_cmd_type(skb, tx_flags); 1331 tx_desc = IGC_TX_DESC(tx_ring, i); 1332 1333 igc_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 1334 1335 size = skb_headlen(skb); 1336 data_len = skb->data_len; 1337 1338 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 1339 1340 tx_buffer = first; 1341 1342 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 1343 if (dma_mapping_error(tx_ring->dev, dma)) 1344 goto dma_error; 1345 1346 /* record length, and DMA address */ 1347 dma_unmap_len_set(tx_buffer, len, size); 1348 dma_unmap_addr_set(tx_buffer, dma, dma); 1349 1350 tx_desc->read.buffer_addr = cpu_to_le64(dma); 1351 1352 while (unlikely(size > IGC_MAX_DATA_PER_TXD)) { 1353 tx_desc->read.cmd_type_len = 1354 cpu_to_le32(cmd_type ^ IGC_MAX_DATA_PER_TXD); 1355 1356 i++; 1357 tx_desc++; 1358 if (i == tx_ring->count) { 1359 tx_desc = IGC_TX_DESC(tx_ring, 0); 1360 i = 0; 1361 } 1362 tx_desc->read.olinfo_status = 0; 1363 1364 dma += IGC_MAX_DATA_PER_TXD; 1365 size -= IGC_MAX_DATA_PER_TXD; 1366 1367 tx_desc->read.buffer_addr = cpu_to_le64(dma); 1368 } 1369 1370 if (likely(!data_len)) 1371 break; 1372 1373 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 1374 1375 i++; 1376 tx_desc++; 1377 if (i == tx_ring->count) { 1378 tx_desc = IGC_TX_DESC(tx_ring, 0); 1379 i = 0; 1380 } 1381 tx_desc->read.olinfo_status = 0; 1382 1383 size = skb_frag_size(frag); 1384 data_len -= size; 1385 1386 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 1387 size, DMA_TO_DEVICE); 1388 1389 tx_buffer = &tx_ring->tx_buffer_info[i]; 1390 } 1391 1392 /* write last descriptor with RS and EOP bits */ 1393 cmd_type |= size | IGC_TXD_DCMD; 1394 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 1395 1396 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 1397 1398 /* set the timestamp */ 1399 first->time_stamp = jiffies; 1400 1401 skb_tx_timestamp(skb); 1402 1403 /* Force memory writes to complete before letting h/w know there 1404 * are new descriptors to fetch. (Only applicable for weak-ordered 1405 * memory model archs, such as IA-64). 1406 * 1407 * We also need this memory barrier to make certain all of the 1408 * status bits have been updated before next_to_watch is written. 1409 */ 1410 wmb(); 1411 1412 /* set next_to_watch value indicating a packet is present */ 1413 first->next_to_watch = tx_desc; 1414 1415 i++; 1416 if (i == tx_ring->count) 1417 i = 0; 1418 1419 tx_ring->next_to_use = i; 1420 1421 /* Make sure there is space in the ring for the next send. */ 1422 igc_maybe_stop_tx(tx_ring, DESC_NEEDED); 1423 1424 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 1425 writel(i, tx_ring->tail); 1426 } 1427 1428 return 0; 1429 dma_error: 1430 netdev_err(tx_ring->netdev, "TX DMA map failed\n"); 1431 tx_buffer = &tx_ring->tx_buffer_info[i]; 1432 1433 /* clear dma mappings for failed tx_buffer_info map */ 1434 while (tx_buffer != first) { 1435 if (dma_unmap_len(tx_buffer, len)) 1436 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 1437 1438 if (i-- == 0) 1439 i += tx_ring->count; 1440 tx_buffer = &tx_ring->tx_buffer_info[i]; 1441 } 1442 1443 if (dma_unmap_len(tx_buffer, len)) 1444 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 1445 1446 dev_kfree_skb_any(tx_buffer->skb); 1447 tx_buffer->skb = NULL; 1448 1449 tx_ring->next_to_use = i; 1450 1451 return -1; 1452 } 1453 1454 static int igc_tso(struct igc_ring *tx_ring, 1455 struct igc_tx_buffer *first, 1456 __le32 launch_time, bool first_flag, 1457 u8 *hdr_len) 1458 { 1459 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 1460 struct sk_buff *skb = first->skb; 1461 union { 1462 struct iphdr *v4; 1463 struct ipv6hdr *v6; 1464 unsigned char *hdr; 1465 } ip; 1466 union { 1467 struct tcphdr *tcp; 1468 struct udphdr *udp; 1469 unsigned char *hdr; 1470 } l4; 1471 u32 paylen, l4_offset; 1472 int err; 1473 1474 if (skb->ip_summed != CHECKSUM_PARTIAL) 1475 return 0; 1476 1477 if (!skb_is_gso(skb)) 1478 return 0; 1479 1480 err = skb_cow_head(skb, 0); 1481 if (err < 0) 1482 return err; 1483 1484 ip.hdr = skb_network_header(skb); 1485 l4.hdr = skb_checksum_start(skb); 1486 1487 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 1488 type_tucmd = IGC_ADVTXD_TUCMD_L4T_TCP; 1489 1490 /* initialize outer IP header fields */ 1491 if (ip.v4->version == 4) { 1492 unsigned char *csum_start = skb_checksum_start(skb); 1493 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 1494 1495 /* IP header will have to cancel out any data that 1496 * is not a part of the outer IP header 1497 */ 1498 ip.v4->check = csum_fold(csum_partial(trans_start, 1499 csum_start - trans_start, 1500 0)); 1501 type_tucmd |= IGC_ADVTXD_TUCMD_IPV4; 1502 1503 ip.v4->tot_len = 0; 1504 first->tx_flags |= IGC_TX_FLAGS_TSO | 1505 IGC_TX_FLAGS_CSUM | 1506 IGC_TX_FLAGS_IPV4; 1507 } else { 1508 ip.v6->payload_len = 0; 1509 first->tx_flags |= IGC_TX_FLAGS_TSO | 1510 IGC_TX_FLAGS_CSUM; 1511 } 1512 1513 /* determine offset of inner transport header */ 1514 l4_offset = l4.hdr - skb->data; 1515 1516 /* remove payload length from inner checksum */ 1517 paylen = skb->len - l4_offset; 1518 if (type_tucmd & IGC_ADVTXD_TUCMD_L4T_TCP) { 1519 /* compute length of segmentation header */ 1520 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 1521 csum_replace_by_diff(&l4.tcp->check, 1522 (__force __wsum)htonl(paylen)); 1523 } else { 1524 /* compute length of segmentation header */ 1525 *hdr_len = sizeof(*l4.udp) + l4_offset; 1526 csum_replace_by_diff(&l4.udp->check, 1527 (__force __wsum)htonl(paylen)); 1528 } 1529 1530 /* update gso size and bytecount with header size */ 1531 first->gso_segs = skb_shinfo(skb)->gso_segs; 1532 first->bytecount += (first->gso_segs - 1) * *hdr_len; 1533 1534 /* MSS L4LEN IDX */ 1535 mss_l4len_idx = (*hdr_len - l4_offset) << IGC_ADVTXD_L4LEN_SHIFT; 1536 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IGC_ADVTXD_MSS_SHIFT; 1537 1538 /* VLAN MACLEN IPLEN */ 1539 vlan_macip_lens = l4.hdr - ip.hdr; 1540 vlan_macip_lens |= (ip.hdr - skb->data) << IGC_ADVTXD_MACLEN_SHIFT; 1541 vlan_macip_lens |= first->tx_flags & IGC_TX_FLAGS_VLAN_MASK; 1542 1543 igc_tx_ctxtdesc(tx_ring, launch_time, first_flag, 1544 vlan_macip_lens, type_tucmd, mss_l4len_idx); 1545 1546 return 1; 1547 } 1548 1549 static bool igc_request_tx_tstamp(struct igc_adapter *adapter, struct sk_buff *skb, u32 *flags) 1550 { 1551 int i; 1552 1553 for (i = 0; i < IGC_MAX_TX_TSTAMP_REGS; i++) { 1554 struct igc_tx_timestamp_request *tstamp = &adapter->tx_tstamp[i]; 1555 1556 if (tstamp->skb) 1557 continue; 1558 1559 tstamp->skb = skb_get(skb); 1560 tstamp->start = jiffies; 1561 *flags = tstamp->flags; 1562 1563 return true; 1564 } 1565 1566 return false; 1567 } 1568 1569 static netdev_tx_t igc_xmit_frame_ring(struct sk_buff *skb, 1570 struct igc_ring *tx_ring) 1571 { 1572 struct igc_adapter *adapter = netdev_priv(tx_ring->netdev); 1573 bool first_flag = false, insert_empty = false; 1574 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 1575 __be16 protocol = vlan_get_protocol(skb); 1576 struct igc_tx_buffer *first; 1577 __le32 launch_time = 0; 1578 u32 tx_flags = 0; 1579 unsigned short f; 1580 ktime_t txtime; 1581 u8 hdr_len = 0; 1582 int tso = 0; 1583 1584 /* need: 1 descriptor per page * PAGE_SIZE/IGC_MAX_DATA_PER_TXD, 1585 * + 1 desc for skb_headlen/IGC_MAX_DATA_PER_TXD, 1586 * + 2 desc gap to keep tail from touching head, 1587 * + 1 desc for context descriptor, 1588 * otherwise try next time 1589 */ 1590 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 1591 count += TXD_USE_COUNT(skb_frag_size( 1592 &skb_shinfo(skb)->frags[f])); 1593 1594 if (igc_maybe_stop_tx(tx_ring, count + 5)) { 1595 /* this is a hard error */ 1596 return NETDEV_TX_BUSY; 1597 } 1598 1599 if (!tx_ring->launchtime_enable) 1600 goto done; 1601 1602 txtime = skb->tstamp; 1603 skb->tstamp = ktime_set(0, 0); 1604 launch_time = igc_tx_launchtime(tx_ring, txtime, &first_flag, &insert_empty); 1605 1606 if (insert_empty) { 1607 struct igc_tx_buffer *empty_info; 1608 struct sk_buff *empty; 1609 void *data; 1610 1611 empty_info = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 1612 empty = alloc_skb(IGC_EMPTY_FRAME_SIZE, GFP_ATOMIC); 1613 if (!empty) 1614 goto done; 1615 1616 data = skb_put(empty, IGC_EMPTY_FRAME_SIZE); 1617 memset(data, 0, IGC_EMPTY_FRAME_SIZE); 1618 1619 igc_tx_ctxtdesc(tx_ring, 0, false, 0, 0, 0); 1620 1621 if (igc_init_tx_empty_descriptor(tx_ring, 1622 empty, 1623 empty_info) < 0) 1624 dev_kfree_skb_any(empty); 1625 } 1626 1627 done: 1628 /* record the location of the first descriptor for this packet */ 1629 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 1630 first->type = IGC_TX_BUFFER_TYPE_SKB; 1631 first->skb = skb; 1632 first->bytecount = skb->len; 1633 first->gso_segs = 1; 1634 1635 if (adapter->qbv_transition || tx_ring->oper_gate_closed) 1636 goto out_drop; 1637 1638 if (tx_ring->max_sdu > 0 && first->bytecount > tx_ring->max_sdu) { 1639 adapter->stats.txdrop++; 1640 goto out_drop; 1641 } 1642 1643 if (unlikely(test_bit(IGC_RING_FLAG_TX_HWTSTAMP, &tx_ring->flags) && 1644 skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 1645 unsigned long flags; 1646 u32 tstamp_flags; 1647 1648 spin_lock_irqsave(&adapter->ptp_tx_lock, flags); 1649 if (igc_request_tx_tstamp(adapter, skb, &tstamp_flags)) { 1650 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1651 tx_flags |= IGC_TX_FLAGS_TSTAMP | tstamp_flags; 1652 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP_USE_CYCLES) 1653 tx_flags |= IGC_TX_FLAGS_TSTAMP_TIMER_1; 1654 } else { 1655 adapter->tx_hwtstamp_skipped++; 1656 } 1657 1658 spin_unlock_irqrestore(&adapter->ptp_tx_lock, flags); 1659 } 1660 1661 if (skb_vlan_tag_present(skb)) { 1662 tx_flags |= IGC_TX_FLAGS_VLAN; 1663 tx_flags |= (skb_vlan_tag_get(skb) << IGC_TX_FLAGS_VLAN_SHIFT); 1664 } 1665 1666 /* record initial flags and protocol */ 1667 first->tx_flags = tx_flags; 1668 first->protocol = protocol; 1669 1670 tso = igc_tso(tx_ring, first, launch_time, first_flag, &hdr_len); 1671 if (tso < 0) 1672 goto out_drop; 1673 else if (!tso) 1674 igc_tx_csum(tx_ring, first, launch_time, first_flag); 1675 1676 igc_tx_map(tx_ring, first, hdr_len); 1677 1678 return NETDEV_TX_OK; 1679 1680 out_drop: 1681 dev_kfree_skb_any(first->skb); 1682 first->skb = NULL; 1683 1684 return NETDEV_TX_OK; 1685 } 1686 1687 static inline struct igc_ring *igc_tx_queue_mapping(struct igc_adapter *adapter, 1688 struct sk_buff *skb) 1689 { 1690 unsigned int r_idx = skb->queue_mapping; 1691 1692 if (r_idx >= adapter->num_tx_queues) 1693 r_idx = r_idx % adapter->num_tx_queues; 1694 1695 return adapter->tx_ring[r_idx]; 1696 } 1697 1698 static netdev_tx_t igc_xmit_frame(struct sk_buff *skb, 1699 struct net_device *netdev) 1700 { 1701 struct igc_adapter *adapter = netdev_priv(netdev); 1702 1703 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 1704 * in order to meet this minimum size requirement. 1705 */ 1706 if (skb->len < 17) { 1707 if (skb_padto(skb, 17)) 1708 return NETDEV_TX_OK; 1709 skb->len = 17; 1710 } 1711 1712 return igc_xmit_frame_ring(skb, igc_tx_queue_mapping(adapter, skb)); 1713 } 1714 1715 static void igc_rx_checksum(struct igc_ring *ring, 1716 union igc_adv_rx_desc *rx_desc, 1717 struct sk_buff *skb) 1718 { 1719 skb_checksum_none_assert(skb); 1720 1721 /* Ignore Checksum bit is set */ 1722 if (igc_test_staterr(rx_desc, IGC_RXD_STAT_IXSM)) 1723 return; 1724 1725 /* Rx checksum disabled via ethtool */ 1726 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1727 return; 1728 1729 /* TCP/UDP checksum error bit is set */ 1730 if (igc_test_staterr(rx_desc, 1731 IGC_RXDEXT_STATERR_L4E | 1732 IGC_RXDEXT_STATERR_IPE)) { 1733 /* work around errata with sctp packets where the TCPE aka 1734 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 1735 * packets (aka let the stack check the crc32c) 1736 */ 1737 if (!(skb->len == 60 && 1738 test_bit(IGC_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 1739 u64_stats_update_begin(&ring->rx_syncp); 1740 ring->rx_stats.csum_err++; 1741 u64_stats_update_end(&ring->rx_syncp); 1742 } 1743 /* let the stack verify checksum errors */ 1744 return; 1745 } 1746 /* It must be a TCP or UDP packet with a valid checksum */ 1747 if (igc_test_staterr(rx_desc, IGC_RXD_STAT_TCPCS | 1748 IGC_RXD_STAT_UDPCS)) 1749 skb->ip_summed = CHECKSUM_UNNECESSARY; 1750 1751 netdev_dbg(ring->netdev, "cksum success: bits %08X\n", 1752 le32_to_cpu(rx_desc->wb.upper.status_error)); 1753 } 1754 1755 /* Mapping HW RSS Type to enum pkt_hash_types */ 1756 static const enum pkt_hash_types igc_rss_type_table[IGC_RSS_TYPE_MAX_TABLE] = { 1757 [IGC_RSS_TYPE_NO_HASH] = PKT_HASH_TYPE_L2, 1758 [IGC_RSS_TYPE_HASH_TCP_IPV4] = PKT_HASH_TYPE_L4, 1759 [IGC_RSS_TYPE_HASH_IPV4] = PKT_HASH_TYPE_L3, 1760 [IGC_RSS_TYPE_HASH_TCP_IPV6] = PKT_HASH_TYPE_L4, 1761 [IGC_RSS_TYPE_HASH_IPV6_EX] = PKT_HASH_TYPE_L3, 1762 [IGC_RSS_TYPE_HASH_IPV6] = PKT_HASH_TYPE_L3, 1763 [IGC_RSS_TYPE_HASH_TCP_IPV6_EX] = PKT_HASH_TYPE_L4, 1764 [IGC_RSS_TYPE_HASH_UDP_IPV4] = PKT_HASH_TYPE_L4, 1765 [IGC_RSS_TYPE_HASH_UDP_IPV6] = PKT_HASH_TYPE_L4, 1766 [IGC_RSS_TYPE_HASH_UDP_IPV6_EX] = PKT_HASH_TYPE_L4, 1767 [10] = PKT_HASH_TYPE_NONE, /* RSS Type above 9 "Reserved" by HW */ 1768 [11] = PKT_HASH_TYPE_NONE, /* keep array sized for SW bit-mask */ 1769 [12] = PKT_HASH_TYPE_NONE, /* to handle future HW revisons */ 1770 [13] = PKT_HASH_TYPE_NONE, 1771 [14] = PKT_HASH_TYPE_NONE, 1772 [15] = PKT_HASH_TYPE_NONE, 1773 }; 1774 1775 static inline void igc_rx_hash(struct igc_ring *ring, 1776 union igc_adv_rx_desc *rx_desc, 1777 struct sk_buff *skb) 1778 { 1779 if (ring->netdev->features & NETIF_F_RXHASH) { 1780 u32 rss_hash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); 1781 u32 rss_type = igc_rss_type(rx_desc); 1782 1783 skb_set_hash(skb, rss_hash, igc_rss_type_table[rss_type]); 1784 } 1785 } 1786 1787 static void igc_rx_vlan(struct igc_ring *rx_ring, 1788 union igc_adv_rx_desc *rx_desc, 1789 struct sk_buff *skb) 1790 { 1791 struct net_device *dev = rx_ring->netdev; 1792 u16 vid; 1793 1794 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1795 igc_test_staterr(rx_desc, IGC_RXD_STAT_VP)) { 1796 if (igc_test_staterr(rx_desc, IGC_RXDEXT_STATERR_LB) && 1797 test_bit(IGC_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 1798 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan); 1799 else 1800 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1801 1802 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1803 } 1804 } 1805 1806 /** 1807 * igc_process_skb_fields - Populate skb header fields from Rx descriptor 1808 * @rx_ring: rx descriptor ring packet is being transacted on 1809 * @rx_desc: pointer to the EOP Rx descriptor 1810 * @skb: pointer to current skb being populated 1811 * 1812 * This function checks the ring, descriptor, and packet information in order 1813 * to populate the hash, checksum, VLAN, protocol, and other fields within the 1814 * skb. 1815 */ 1816 static void igc_process_skb_fields(struct igc_ring *rx_ring, 1817 union igc_adv_rx_desc *rx_desc, 1818 struct sk_buff *skb) 1819 { 1820 igc_rx_hash(rx_ring, rx_desc, skb); 1821 1822 igc_rx_checksum(rx_ring, rx_desc, skb); 1823 1824 igc_rx_vlan(rx_ring, rx_desc, skb); 1825 1826 skb_record_rx_queue(skb, rx_ring->queue_index); 1827 1828 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 1829 } 1830 1831 static void igc_vlan_mode(struct net_device *netdev, netdev_features_t features) 1832 { 1833 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 1834 struct igc_adapter *adapter = netdev_priv(netdev); 1835 struct igc_hw *hw = &adapter->hw; 1836 u32 ctrl; 1837 1838 ctrl = rd32(IGC_CTRL); 1839 1840 if (enable) { 1841 /* enable VLAN tag insert/strip */ 1842 ctrl |= IGC_CTRL_VME; 1843 } else { 1844 /* disable VLAN tag insert/strip */ 1845 ctrl &= ~IGC_CTRL_VME; 1846 } 1847 wr32(IGC_CTRL, ctrl); 1848 } 1849 1850 static void igc_restore_vlan(struct igc_adapter *adapter) 1851 { 1852 igc_vlan_mode(adapter->netdev, adapter->netdev->features); 1853 } 1854 1855 static struct igc_rx_buffer *igc_get_rx_buffer(struct igc_ring *rx_ring, 1856 const unsigned int size, 1857 int *rx_buffer_pgcnt) 1858 { 1859 struct igc_rx_buffer *rx_buffer; 1860 1861 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 1862 *rx_buffer_pgcnt = 1863 #if (PAGE_SIZE < 8192) 1864 page_count(rx_buffer->page); 1865 #else 1866 0; 1867 #endif 1868 prefetchw(rx_buffer->page); 1869 1870 /* we are reusing so sync this buffer for CPU use */ 1871 dma_sync_single_range_for_cpu(rx_ring->dev, 1872 rx_buffer->dma, 1873 rx_buffer->page_offset, 1874 size, 1875 DMA_FROM_DEVICE); 1876 1877 rx_buffer->pagecnt_bias--; 1878 1879 return rx_buffer; 1880 } 1881 1882 static void igc_rx_buffer_flip(struct igc_rx_buffer *buffer, 1883 unsigned int truesize) 1884 { 1885 #if (PAGE_SIZE < 8192) 1886 buffer->page_offset ^= truesize; 1887 #else 1888 buffer->page_offset += truesize; 1889 #endif 1890 } 1891 1892 static unsigned int igc_get_rx_frame_truesize(struct igc_ring *ring, 1893 unsigned int size) 1894 { 1895 unsigned int truesize; 1896 1897 #if (PAGE_SIZE < 8192) 1898 truesize = igc_rx_pg_size(ring) / 2; 1899 #else 1900 truesize = ring_uses_build_skb(ring) ? 1901 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 1902 SKB_DATA_ALIGN(IGC_SKB_PAD + size) : 1903 SKB_DATA_ALIGN(size); 1904 #endif 1905 return truesize; 1906 } 1907 1908 /** 1909 * igc_add_rx_frag - Add contents of Rx buffer to sk_buff 1910 * @rx_ring: rx descriptor ring to transact packets on 1911 * @rx_buffer: buffer containing page to add 1912 * @skb: sk_buff to place the data into 1913 * @size: size of buffer to be added 1914 * 1915 * This function will add the data contained in rx_buffer->page to the skb. 1916 */ 1917 static void igc_add_rx_frag(struct igc_ring *rx_ring, 1918 struct igc_rx_buffer *rx_buffer, 1919 struct sk_buff *skb, 1920 unsigned int size) 1921 { 1922 unsigned int truesize; 1923 1924 #if (PAGE_SIZE < 8192) 1925 truesize = igc_rx_pg_size(rx_ring) / 2; 1926 #else 1927 truesize = ring_uses_build_skb(rx_ring) ? 1928 SKB_DATA_ALIGN(IGC_SKB_PAD + size) : 1929 SKB_DATA_ALIGN(size); 1930 #endif 1931 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 1932 rx_buffer->page_offset, size, truesize); 1933 1934 igc_rx_buffer_flip(rx_buffer, truesize); 1935 } 1936 1937 static struct sk_buff *igc_build_skb(struct igc_ring *rx_ring, 1938 struct igc_rx_buffer *rx_buffer, 1939 struct xdp_buff *xdp) 1940 { 1941 unsigned int size = xdp->data_end - xdp->data; 1942 unsigned int truesize = igc_get_rx_frame_truesize(rx_ring, size); 1943 unsigned int metasize = xdp->data - xdp->data_meta; 1944 struct sk_buff *skb; 1945 1946 /* prefetch first cache line of first page */ 1947 net_prefetch(xdp->data_meta); 1948 1949 /* build an skb around the page buffer */ 1950 skb = napi_build_skb(xdp->data_hard_start, truesize); 1951 if (unlikely(!skb)) 1952 return NULL; 1953 1954 /* update pointers within the skb to store the data */ 1955 skb_reserve(skb, xdp->data - xdp->data_hard_start); 1956 __skb_put(skb, size); 1957 if (metasize) 1958 skb_metadata_set(skb, metasize); 1959 1960 igc_rx_buffer_flip(rx_buffer, truesize); 1961 return skb; 1962 } 1963 1964 static struct sk_buff *igc_construct_skb(struct igc_ring *rx_ring, 1965 struct igc_rx_buffer *rx_buffer, 1966 struct igc_xdp_buff *ctx) 1967 { 1968 struct xdp_buff *xdp = &ctx->xdp; 1969 unsigned int metasize = xdp->data - xdp->data_meta; 1970 unsigned int size = xdp->data_end - xdp->data; 1971 unsigned int truesize = igc_get_rx_frame_truesize(rx_ring, size); 1972 void *va = xdp->data; 1973 unsigned int headlen; 1974 struct sk_buff *skb; 1975 1976 /* prefetch first cache line of first page */ 1977 net_prefetch(xdp->data_meta); 1978 1979 /* allocate a skb to store the frags */ 1980 skb = napi_alloc_skb(&rx_ring->q_vector->napi, 1981 IGC_RX_HDR_LEN + metasize); 1982 if (unlikely(!skb)) 1983 return NULL; 1984 1985 if (ctx->rx_ts) { 1986 skb_shinfo(skb)->tx_flags |= SKBTX_HW_TSTAMP_NETDEV; 1987 skb_hwtstamps(skb)->netdev_data = ctx->rx_ts; 1988 } 1989 1990 /* Determine available headroom for copy */ 1991 headlen = size; 1992 if (headlen > IGC_RX_HDR_LEN) 1993 headlen = eth_get_headlen(skb->dev, va, IGC_RX_HDR_LEN); 1994 1995 /* align pull length to size of long to optimize memcpy performance */ 1996 memcpy(__skb_put(skb, headlen + metasize), xdp->data_meta, 1997 ALIGN(headlen + metasize, sizeof(long))); 1998 1999 if (metasize) { 2000 skb_metadata_set(skb, metasize); 2001 __skb_pull(skb, metasize); 2002 } 2003 2004 /* update all of the pointers */ 2005 size -= headlen; 2006 if (size) { 2007 skb_add_rx_frag(skb, 0, rx_buffer->page, 2008 (va + headlen) - page_address(rx_buffer->page), 2009 size, truesize); 2010 igc_rx_buffer_flip(rx_buffer, truesize); 2011 } else { 2012 rx_buffer->pagecnt_bias++; 2013 } 2014 2015 return skb; 2016 } 2017 2018 /** 2019 * igc_reuse_rx_page - page flip buffer and store it back on the ring 2020 * @rx_ring: rx descriptor ring to store buffers on 2021 * @old_buff: donor buffer to have page reused 2022 * 2023 * Synchronizes page for reuse by the adapter 2024 */ 2025 static void igc_reuse_rx_page(struct igc_ring *rx_ring, 2026 struct igc_rx_buffer *old_buff) 2027 { 2028 u16 nta = rx_ring->next_to_alloc; 2029 struct igc_rx_buffer *new_buff; 2030 2031 new_buff = &rx_ring->rx_buffer_info[nta]; 2032 2033 /* update, and store next to alloc */ 2034 nta++; 2035 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 2036 2037 /* Transfer page from old buffer to new buffer. 2038 * Move each member individually to avoid possible store 2039 * forwarding stalls. 2040 */ 2041 new_buff->dma = old_buff->dma; 2042 new_buff->page = old_buff->page; 2043 new_buff->page_offset = old_buff->page_offset; 2044 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 2045 } 2046 2047 static bool igc_can_reuse_rx_page(struct igc_rx_buffer *rx_buffer, 2048 int rx_buffer_pgcnt) 2049 { 2050 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 2051 struct page *page = rx_buffer->page; 2052 2053 /* avoid re-using remote and pfmemalloc pages */ 2054 if (!dev_page_is_reusable(page)) 2055 return false; 2056 2057 #if (PAGE_SIZE < 8192) 2058 /* if we are only owner of page we can reuse it */ 2059 if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1)) 2060 return false; 2061 #else 2062 #define IGC_LAST_OFFSET \ 2063 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGC_RXBUFFER_2048) 2064 2065 if (rx_buffer->page_offset > IGC_LAST_OFFSET) 2066 return false; 2067 #endif 2068 2069 /* If we have drained the page fragment pool we need to update 2070 * the pagecnt_bias and page count so that we fully restock the 2071 * number of references the driver holds. 2072 */ 2073 if (unlikely(pagecnt_bias == 1)) { 2074 page_ref_add(page, USHRT_MAX - 1); 2075 rx_buffer->pagecnt_bias = USHRT_MAX; 2076 } 2077 2078 return true; 2079 } 2080 2081 /** 2082 * igc_is_non_eop - process handling of non-EOP buffers 2083 * @rx_ring: Rx ring being processed 2084 * @rx_desc: Rx descriptor for current buffer 2085 * 2086 * This function updates next to clean. If the buffer is an EOP buffer 2087 * this function exits returning false, otherwise it will place the 2088 * sk_buff in the next buffer to be chained and return true indicating 2089 * that this is in fact a non-EOP buffer. 2090 */ 2091 static bool igc_is_non_eop(struct igc_ring *rx_ring, 2092 union igc_adv_rx_desc *rx_desc) 2093 { 2094 u32 ntc = rx_ring->next_to_clean + 1; 2095 2096 /* fetch, update, and store next to clean */ 2097 ntc = (ntc < rx_ring->count) ? ntc : 0; 2098 rx_ring->next_to_clean = ntc; 2099 2100 prefetch(IGC_RX_DESC(rx_ring, ntc)); 2101 2102 if (likely(igc_test_staterr(rx_desc, IGC_RXD_STAT_EOP))) 2103 return false; 2104 2105 return true; 2106 } 2107 2108 /** 2109 * igc_cleanup_headers - Correct corrupted or empty headers 2110 * @rx_ring: rx descriptor ring packet is being transacted on 2111 * @rx_desc: pointer to the EOP Rx descriptor 2112 * @skb: pointer to current skb being fixed 2113 * 2114 * Address the case where we are pulling data in on pages only 2115 * and as such no data is present in the skb header. 2116 * 2117 * In addition if skb is not at least 60 bytes we need to pad it so that 2118 * it is large enough to qualify as a valid Ethernet frame. 2119 * 2120 * Returns true if an error was encountered and skb was freed. 2121 */ 2122 static bool igc_cleanup_headers(struct igc_ring *rx_ring, 2123 union igc_adv_rx_desc *rx_desc, 2124 struct sk_buff *skb) 2125 { 2126 if (unlikely(igc_test_staterr(rx_desc, IGC_RXDEXT_STATERR_RXE))) { 2127 struct net_device *netdev = rx_ring->netdev; 2128 2129 if (!(netdev->features & NETIF_F_RXALL)) { 2130 dev_kfree_skb_any(skb); 2131 return true; 2132 } 2133 } 2134 2135 /* if eth_skb_pad returns an error the skb was freed */ 2136 if (eth_skb_pad(skb)) 2137 return true; 2138 2139 return false; 2140 } 2141 2142 static void igc_put_rx_buffer(struct igc_ring *rx_ring, 2143 struct igc_rx_buffer *rx_buffer, 2144 int rx_buffer_pgcnt) 2145 { 2146 if (igc_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) { 2147 /* hand second half of page back to the ring */ 2148 igc_reuse_rx_page(rx_ring, rx_buffer); 2149 } else { 2150 /* We are not reusing the buffer so unmap it and free 2151 * any references we are holding to it 2152 */ 2153 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2154 igc_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 2155 IGC_RX_DMA_ATTR); 2156 __page_frag_cache_drain(rx_buffer->page, 2157 rx_buffer->pagecnt_bias); 2158 } 2159 2160 /* clear contents of rx_buffer */ 2161 rx_buffer->page = NULL; 2162 } 2163 2164 static inline unsigned int igc_rx_offset(struct igc_ring *rx_ring) 2165 { 2166 struct igc_adapter *adapter = rx_ring->q_vector->adapter; 2167 2168 if (ring_uses_build_skb(rx_ring)) 2169 return IGC_SKB_PAD; 2170 if (igc_xdp_is_enabled(adapter)) 2171 return XDP_PACKET_HEADROOM; 2172 2173 return 0; 2174 } 2175 2176 static bool igc_alloc_mapped_page(struct igc_ring *rx_ring, 2177 struct igc_rx_buffer *bi) 2178 { 2179 struct page *page = bi->page; 2180 dma_addr_t dma; 2181 2182 /* since we are recycling buffers we should seldom need to alloc */ 2183 if (likely(page)) 2184 return true; 2185 2186 /* alloc new page for storage */ 2187 page = dev_alloc_pages(igc_rx_pg_order(rx_ring)); 2188 if (unlikely(!page)) { 2189 rx_ring->rx_stats.alloc_failed++; 2190 set_bit(IGC_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 2191 return false; 2192 } 2193 2194 /* map page for use */ 2195 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 2196 igc_rx_pg_size(rx_ring), 2197 DMA_FROM_DEVICE, 2198 IGC_RX_DMA_ATTR); 2199 2200 /* if mapping failed free memory back to system since 2201 * there isn't much point in holding memory we can't use 2202 */ 2203 if (dma_mapping_error(rx_ring->dev, dma)) { 2204 __free_page(page); 2205 2206 rx_ring->rx_stats.alloc_failed++; 2207 set_bit(IGC_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 2208 return false; 2209 } 2210 2211 bi->dma = dma; 2212 bi->page = page; 2213 bi->page_offset = igc_rx_offset(rx_ring); 2214 page_ref_add(page, USHRT_MAX - 1); 2215 bi->pagecnt_bias = USHRT_MAX; 2216 2217 return true; 2218 } 2219 2220 /** 2221 * igc_alloc_rx_buffers - Replace used receive buffers; packet split 2222 * @rx_ring: rx descriptor ring 2223 * @cleaned_count: number of buffers to clean 2224 */ 2225 static void igc_alloc_rx_buffers(struct igc_ring *rx_ring, u16 cleaned_count) 2226 { 2227 union igc_adv_rx_desc *rx_desc; 2228 u16 i = rx_ring->next_to_use; 2229 struct igc_rx_buffer *bi; 2230 u16 bufsz; 2231 2232 /* nothing to do */ 2233 if (!cleaned_count) 2234 return; 2235 2236 rx_desc = IGC_RX_DESC(rx_ring, i); 2237 bi = &rx_ring->rx_buffer_info[i]; 2238 i -= rx_ring->count; 2239 2240 bufsz = igc_rx_bufsz(rx_ring); 2241 2242 do { 2243 if (!igc_alloc_mapped_page(rx_ring, bi)) 2244 break; 2245 2246 /* sync the buffer for use by the device */ 2247 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 2248 bi->page_offset, bufsz, 2249 DMA_FROM_DEVICE); 2250 2251 /* Refresh the desc even if buffer_addrs didn't change 2252 * because each write-back erases this info. 2253 */ 2254 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 2255 2256 rx_desc++; 2257 bi++; 2258 i++; 2259 if (unlikely(!i)) { 2260 rx_desc = IGC_RX_DESC(rx_ring, 0); 2261 bi = rx_ring->rx_buffer_info; 2262 i -= rx_ring->count; 2263 } 2264 2265 /* clear the length for the next_to_use descriptor */ 2266 rx_desc->wb.upper.length = 0; 2267 2268 cleaned_count--; 2269 } while (cleaned_count); 2270 2271 i += rx_ring->count; 2272 2273 if (rx_ring->next_to_use != i) { 2274 /* record the next descriptor to use */ 2275 rx_ring->next_to_use = i; 2276 2277 /* update next to alloc since we have filled the ring */ 2278 rx_ring->next_to_alloc = i; 2279 2280 /* Force memory writes to complete before letting h/w 2281 * know there are new descriptors to fetch. (Only 2282 * applicable for weak-ordered memory model archs, 2283 * such as IA-64). 2284 */ 2285 wmb(); 2286 writel(i, rx_ring->tail); 2287 } 2288 } 2289 2290 static bool igc_alloc_rx_buffers_zc(struct igc_ring *ring, u16 count) 2291 { 2292 union igc_adv_rx_desc *desc; 2293 u16 i = ring->next_to_use; 2294 struct igc_rx_buffer *bi; 2295 dma_addr_t dma; 2296 bool ok = true; 2297 2298 if (!count) 2299 return ok; 2300 2301 XSK_CHECK_PRIV_TYPE(struct igc_xdp_buff); 2302 2303 desc = IGC_RX_DESC(ring, i); 2304 bi = &ring->rx_buffer_info[i]; 2305 i -= ring->count; 2306 2307 do { 2308 bi->xdp = xsk_buff_alloc(ring->xsk_pool); 2309 if (!bi->xdp) { 2310 ok = false; 2311 break; 2312 } 2313 2314 dma = xsk_buff_xdp_get_dma(bi->xdp); 2315 desc->read.pkt_addr = cpu_to_le64(dma); 2316 2317 desc++; 2318 bi++; 2319 i++; 2320 if (unlikely(!i)) { 2321 desc = IGC_RX_DESC(ring, 0); 2322 bi = ring->rx_buffer_info; 2323 i -= ring->count; 2324 } 2325 2326 /* Clear the length for the next_to_use descriptor. */ 2327 desc->wb.upper.length = 0; 2328 2329 count--; 2330 } while (count); 2331 2332 i += ring->count; 2333 2334 if (ring->next_to_use != i) { 2335 ring->next_to_use = i; 2336 2337 /* Force memory writes to complete before letting h/w 2338 * know there are new descriptors to fetch. (Only 2339 * applicable for weak-ordered memory model archs, 2340 * such as IA-64). 2341 */ 2342 wmb(); 2343 writel(i, ring->tail); 2344 } 2345 2346 return ok; 2347 } 2348 2349 /* This function requires __netif_tx_lock is held by the caller. */ 2350 static int igc_xdp_init_tx_descriptor(struct igc_ring *ring, 2351 struct xdp_frame *xdpf) 2352 { 2353 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 2354 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 2355 u16 count, index = ring->next_to_use; 2356 struct igc_tx_buffer *head = &ring->tx_buffer_info[index]; 2357 struct igc_tx_buffer *buffer = head; 2358 union igc_adv_tx_desc *desc = IGC_TX_DESC(ring, index); 2359 u32 olinfo_status, len = xdpf->len, cmd_type; 2360 void *data = xdpf->data; 2361 u16 i; 2362 2363 count = TXD_USE_COUNT(len); 2364 for (i = 0; i < nr_frags; i++) 2365 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i])); 2366 2367 if (igc_maybe_stop_tx(ring, count + 3)) { 2368 /* this is a hard error */ 2369 return -EBUSY; 2370 } 2371 2372 i = 0; 2373 head->bytecount = xdp_get_frame_len(xdpf); 2374 head->type = IGC_TX_BUFFER_TYPE_XDP; 2375 head->gso_segs = 1; 2376 head->xdpf = xdpf; 2377 2378 olinfo_status = head->bytecount << IGC_ADVTXD_PAYLEN_SHIFT; 2379 desc->read.olinfo_status = cpu_to_le32(olinfo_status); 2380 2381 for (;;) { 2382 dma_addr_t dma; 2383 2384 dma = dma_map_single(ring->dev, data, len, DMA_TO_DEVICE); 2385 if (dma_mapping_error(ring->dev, dma)) { 2386 netdev_err_once(ring->netdev, 2387 "Failed to map DMA for TX\n"); 2388 goto unmap; 2389 } 2390 2391 dma_unmap_len_set(buffer, len, len); 2392 dma_unmap_addr_set(buffer, dma, dma); 2393 2394 cmd_type = IGC_ADVTXD_DTYP_DATA | IGC_ADVTXD_DCMD_DEXT | 2395 IGC_ADVTXD_DCMD_IFCS | len; 2396 2397 desc->read.cmd_type_len = cpu_to_le32(cmd_type); 2398 desc->read.buffer_addr = cpu_to_le64(dma); 2399 2400 buffer->protocol = 0; 2401 2402 if (++index == ring->count) 2403 index = 0; 2404 2405 if (i == nr_frags) 2406 break; 2407 2408 buffer = &ring->tx_buffer_info[index]; 2409 desc = IGC_TX_DESC(ring, index); 2410 desc->read.olinfo_status = 0; 2411 2412 data = skb_frag_address(&sinfo->frags[i]); 2413 len = skb_frag_size(&sinfo->frags[i]); 2414 i++; 2415 } 2416 desc->read.cmd_type_len |= cpu_to_le32(IGC_TXD_DCMD); 2417 2418 netdev_tx_sent_queue(txring_txq(ring), head->bytecount); 2419 /* set the timestamp */ 2420 head->time_stamp = jiffies; 2421 /* set next_to_watch value indicating a packet is present */ 2422 head->next_to_watch = desc; 2423 ring->next_to_use = index; 2424 2425 return 0; 2426 2427 unmap: 2428 for (;;) { 2429 buffer = &ring->tx_buffer_info[index]; 2430 if (dma_unmap_len(buffer, len)) 2431 dma_unmap_page(ring->dev, 2432 dma_unmap_addr(buffer, dma), 2433 dma_unmap_len(buffer, len), 2434 DMA_TO_DEVICE); 2435 dma_unmap_len_set(buffer, len, 0); 2436 if (buffer == head) 2437 break; 2438 2439 if (!index) 2440 index += ring->count; 2441 index--; 2442 } 2443 2444 return -ENOMEM; 2445 } 2446 2447 static struct igc_ring *igc_xdp_get_tx_ring(struct igc_adapter *adapter, 2448 int cpu) 2449 { 2450 int index = cpu; 2451 2452 if (unlikely(index < 0)) 2453 index = 0; 2454 2455 while (index >= adapter->num_tx_queues) 2456 index -= adapter->num_tx_queues; 2457 2458 return adapter->tx_ring[index]; 2459 } 2460 2461 static int igc_xdp_xmit_back(struct igc_adapter *adapter, struct xdp_buff *xdp) 2462 { 2463 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2464 int cpu = smp_processor_id(); 2465 struct netdev_queue *nq; 2466 struct igc_ring *ring; 2467 int res; 2468 2469 if (unlikely(!xdpf)) 2470 return -EFAULT; 2471 2472 ring = igc_xdp_get_tx_ring(adapter, cpu); 2473 nq = txring_txq(ring); 2474 2475 __netif_tx_lock(nq, cpu); 2476 /* Avoid transmit queue timeout since we share it with the slow path */ 2477 txq_trans_cond_update(nq); 2478 res = igc_xdp_init_tx_descriptor(ring, xdpf); 2479 __netif_tx_unlock(nq); 2480 return res; 2481 } 2482 2483 /* This function assumes rcu_read_lock() is held by the caller. */ 2484 static int __igc_xdp_run_prog(struct igc_adapter *adapter, 2485 struct bpf_prog *prog, 2486 struct xdp_buff *xdp) 2487 { 2488 u32 act = bpf_prog_run_xdp(prog, xdp); 2489 2490 switch (act) { 2491 case XDP_PASS: 2492 return IGC_XDP_PASS; 2493 case XDP_TX: 2494 if (igc_xdp_xmit_back(adapter, xdp) < 0) 2495 goto out_failure; 2496 return IGC_XDP_TX; 2497 case XDP_REDIRECT: 2498 if (xdp_do_redirect(adapter->netdev, xdp, prog) < 0) 2499 goto out_failure; 2500 return IGC_XDP_REDIRECT; 2501 break; 2502 default: 2503 bpf_warn_invalid_xdp_action(adapter->netdev, prog, act); 2504 fallthrough; 2505 case XDP_ABORTED: 2506 out_failure: 2507 trace_xdp_exception(adapter->netdev, prog, act); 2508 fallthrough; 2509 case XDP_DROP: 2510 return IGC_XDP_CONSUMED; 2511 } 2512 } 2513 2514 static int igc_xdp_run_prog(struct igc_adapter *adapter, struct xdp_buff *xdp) 2515 { 2516 struct bpf_prog *prog; 2517 int res; 2518 2519 prog = READ_ONCE(adapter->xdp_prog); 2520 if (!prog) { 2521 res = IGC_XDP_PASS; 2522 goto out; 2523 } 2524 2525 res = __igc_xdp_run_prog(adapter, prog, xdp); 2526 2527 out: 2528 return res; 2529 } 2530 2531 /* This function assumes __netif_tx_lock is held by the caller. */ 2532 static void igc_flush_tx_descriptors(struct igc_ring *ring) 2533 { 2534 /* Once tail pointer is updated, hardware can fetch the descriptors 2535 * any time so we issue a write membar here to ensure all memory 2536 * writes are complete before the tail pointer is updated. 2537 */ 2538 wmb(); 2539 writel(ring->next_to_use, ring->tail); 2540 } 2541 2542 static void igc_finalize_xdp(struct igc_adapter *adapter, int status) 2543 { 2544 int cpu = smp_processor_id(); 2545 struct netdev_queue *nq; 2546 struct igc_ring *ring; 2547 2548 if (status & IGC_XDP_TX) { 2549 ring = igc_xdp_get_tx_ring(adapter, cpu); 2550 nq = txring_txq(ring); 2551 2552 __netif_tx_lock(nq, cpu); 2553 igc_flush_tx_descriptors(ring); 2554 __netif_tx_unlock(nq); 2555 } 2556 2557 if (status & IGC_XDP_REDIRECT) 2558 xdp_do_flush(); 2559 } 2560 2561 static void igc_update_rx_stats(struct igc_q_vector *q_vector, 2562 unsigned int packets, unsigned int bytes) 2563 { 2564 struct igc_ring *ring = q_vector->rx.ring; 2565 2566 u64_stats_update_begin(&ring->rx_syncp); 2567 ring->rx_stats.packets += packets; 2568 ring->rx_stats.bytes += bytes; 2569 u64_stats_update_end(&ring->rx_syncp); 2570 2571 q_vector->rx.total_packets += packets; 2572 q_vector->rx.total_bytes += bytes; 2573 } 2574 2575 static int igc_clean_rx_irq(struct igc_q_vector *q_vector, const int budget) 2576 { 2577 unsigned int total_bytes = 0, total_packets = 0; 2578 struct igc_adapter *adapter = q_vector->adapter; 2579 struct igc_ring *rx_ring = q_vector->rx.ring; 2580 struct sk_buff *skb = rx_ring->skb; 2581 u16 cleaned_count = igc_desc_unused(rx_ring); 2582 int xdp_status = 0, rx_buffer_pgcnt; 2583 int xdp_res = 0; 2584 2585 while (likely(total_packets < budget)) { 2586 struct igc_xdp_buff ctx = { .rx_ts = NULL }; 2587 struct igc_rx_buffer *rx_buffer; 2588 union igc_adv_rx_desc *rx_desc; 2589 unsigned int size, truesize; 2590 int pkt_offset = 0; 2591 void *pktbuf; 2592 2593 /* return some buffers to hardware, one at a time is too slow */ 2594 if (cleaned_count >= IGC_RX_BUFFER_WRITE) { 2595 igc_alloc_rx_buffers(rx_ring, cleaned_count); 2596 cleaned_count = 0; 2597 } 2598 2599 rx_desc = IGC_RX_DESC(rx_ring, rx_ring->next_to_clean); 2600 size = le16_to_cpu(rx_desc->wb.upper.length); 2601 if (!size) 2602 break; 2603 2604 /* This memory barrier is needed to keep us from reading 2605 * any other fields out of the rx_desc until we know the 2606 * descriptor has been written back 2607 */ 2608 dma_rmb(); 2609 2610 rx_buffer = igc_get_rx_buffer(rx_ring, size, &rx_buffer_pgcnt); 2611 truesize = igc_get_rx_frame_truesize(rx_ring, size); 2612 2613 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset; 2614 2615 if (igc_test_staterr(rx_desc, IGC_RXDADV_STAT_TSIP)) { 2616 ctx.rx_ts = pktbuf; 2617 pkt_offset = IGC_TS_HDR_LEN; 2618 size -= IGC_TS_HDR_LEN; 2619 } 2620 2621 if (!skb) { 2622 xdp_init_buff(&ctx.xdp, truesize, &rx_ring->xdp_rxq); 2623 xdp_prepare_buff(&ctx.xdp, pktbuf - igc_rx_offset(rx_ring), 2624 igc_rx_offset(rx_ring) + pkt_offset, 2625 size, true); 2626 xdp_buff_clear_frags_flag(&ctx.xdp); 2627 ctx.rx_desc = rx_desc; 2628 2629 xdp_res = igc_xdp_run_prog(adapter, &ctx.xdp); 2630 } 2631 2632 if (xdp_res) { 2633 switch (xdp_res) { 2634 case IGC_XDP_CONSUMED: 2635 rx_buffer->pagecnt_bias++; 2636 break; 2637 case IGC_XDP_TX: 2638 case IGC_XDP_REDIRECT: 2639 igc_rx_buffer_flip(rx_buffer, truesize); 2640 xdp_status |= xdp_res; 2641 break; 2642 } 2643 2644 total_packets++; 2645 total_bytes += size; 2646 } else if (skb) 2647 igc_add_rx_frag(rx_ring, rx_buffer, skb, size); 2648 else if (ring_uses_build_skb(rx_ring)) 2649 skb = igc_build_skb(rx_ring, rx_buffer, &ctx.xdp); 2650 else 2651 skb = igc_construct_skb(rx_ring, rx_buffer, &ctx); 2652 2653 /* exit if we failed to retrieve a buffer */ 2654 if (!xdp_res && !skb) { 2655 rx_ring->rx_stats.alloc_failed++; 2656 rx_buffer->pagecnt_bias++; 2657 set_bit(IGC_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 2658 break; 2659 } 2660 2661 igc_put_rx_buffer(rx_ring, rx_buffer, rx_buffer_pgcnt); 2662 cleaned_count++; 2663 2664 /* fetch next buffer in frame if non-eop */ 2665 if (igc_is_non_eop(rx_ring, rx_desc)) 2666 continue; 2667 2668 /* verify the packet layout is correct */ 2669 if (xdp_res || igc_cleanup_headers(rx_ring, rx_desc, skb)) { 2670 skb = NULL; 2671 continue; 2672 } 2673 2674 /* probably a little skewed due to removing CRC */ 2675 total_bytes += skb->len; 2676 2677 /* populate checksum, VLAN, and protocol */ 2678 igc_process_skb_fields(rx_ring, rx_desc, skb); 2679 2680 napi_gro_receive(&q_vector->napi, skb); 2681 2682 /* reset skb pointer */ 2683 skb = NULL; 2684 2685 /* update budget accounting */ 2686 total_packets++; 2687 } 2688 2689 if (xdp_status) 2690 igc_finalize_xdp(adapter, xdp_status); 2691 2692 /* place incomplete frames back on ring for completion */ 2693 rx_ring->skb = skb; 2694 2695 igc_update_rx_stats(q_vector, total_packets, total_bytes); 2696 2697 if (cleaned_count) 2698 igc_alloc_rx_buffers(rx_ring, cleaned_count); 2699 2700 return total_packets; 2701 } 2702 2703 static struct sk_buff *igc_construct_skb_zc(struct igc_ring *ring, 2704 struct xdp_buff *xdp) 2705 { 2706 unsigned int totalsize = xdp->data_end - xdp->data_meta; 2707 unsigned int metasize = xdp->data - xdp->data_meta; 2708 struct sk_buff *skb; 2709 2710 net_prefetch(xdp->data_meta); 2711 2712 skb = napi_alloc_skb(&ring->q_vector->napi, totalsize); 2713 if (unlikely(!skb)) 2714 return NULL; 2715 2716 memcpy(__skb_put(skb, totalsize), xdp->data_meta, 2717 ALIGN(totalsize, sizeof(long))); 2718 2719 if (metasize) { 2720 skb_metadata_set(skb, metasize); 2721 __skb_pull(skb, metasize); 2722 } 2723 2724 return skb; 2725 } 2726 2727 static void igc_dispatch_skb_zc(struct igc_q_vector *q_vector, 2728 union igc_adv_rx_desc *desc, 2729 struct xdp_buff *xdp, 2730 ktime_t timestamp) 2731 { 2732 struct igc_ring *ring = q_vector->rx.ring; 2733 struct sk_buff *skb; 2734 2735 skb = igc_construct_skb_zc(ring, xdp); 2736 if (!skb) { 2737 ring->rx_stats.alloc_failed++; 2738 set_bit(IGC_RING_FLAG_RX_ALLOC_FAILED, &ring->flags); 2739 return; 2740 } 2741 2742 if (timestamp) 2743 skb_hwtstamps(skb)->hwtstamp = timestamp; 2744 2745 if (igc_cleanup_headers(ring, desc, skb)) 2746 return; 2747 2748 igc_process_skb_fields(ring, desc, skb); 2749 napi_gro_receive(&q_vector->napi, skb); 2750 } 2751 2752 static struct igc_xdp_buff *xsk_buff_to_igc_ctx(struct xdp_buff *xdp) 2753 { 2754 /* xdp_buff pointer used by ZC code path is alloc as xdp_buff_xsk. The 2755 * igc_xdp_buff shares its layout with xdp_buff_xsk and private 2756 * igc_xdp_buff fields fall into xdp_buff_xsk->cb 2757 */ 2758 return (struct igc_xdp_buff *)xdp; 2759 } 2760 2761 static int igc_clean_rx_irq_zc(struct igc_q_vector *q_vector, const int budget) 2762 { 2763 struct igc_adapter *adapter = q_vector->adapter; 2764 struct igc_ring *ring = q_vector->rx.ring; 2765 u16 cleaned_count = igc_desc_unused(ring); 2766 int total_bytes = 0, total_packets = 0; 2767 u16 ntc = ring->next_to_clean; 2768 struct bpf_prog *prog; 2769 bool failure = false; 2770 int xdp_status = 0; 2771 2772 rcu_read_lock(); 2773 2774 prog = READ_ONCE(adapter->xdp_prog); 2775 2776 while (likely(total_packets < budget)) { 2777 union igc_adv_rx_desc *desc; 2778 struct igc_rx_buffer *bi; 2779 struct igc_xdp_buff *ctx; 2780 ktime_t timestamp = 0; 2781 unsigned int size; 2782 int res; 2783 2784 desc = IGC_RX_DESC(ring, ntc); 2785 size = le16_to_cpu(desc->wb.upper.length); 2786 if (!size) 2787 break; 2788 2789 /* This memory barrier is needed to keep us from reading 2790 * any other fields out of the rx_desc until we know the 2791 * descriptor has been written back 2792 */ 2793 dma_rmb(); 2794 2795 bi = &ring->rx_buffer_info[ntc]; 2796 2797 ctx = xsk_buff_to_igc_ctx(bi->xdp); 2798 ctx->rx_desc = desc; 2799 2800 if (igc_test_staterr(desc, IGC_RXDADV_STAT_TSIP)) { 2801 ctx->rx_ts = bi->xdp->data; 2802 2803 bi->xdp->data += IGC_TS_HDR_LEN; 2804 2805 /* HW timestamp has been copied into local variable. Metadata 2806 * length when XDP program is called should be 0. 2807 */ 2808 bi->xdp->data_meta += IGC_TS_HDR_LEN; 2809 size -= IGC_TS_HDR_LEN; 2810 } 2811 2812 bi->xdp->data_end = bi->xdp->data + size; 2813 xsk_buff_dma_sync_for_cpu(bi->xdp); 2814 2815 res = __igc_xdp_run_prog(adapter, prog, bi->xdp); 2816 switch (res) { 2817 case IGC_XDP_PASS: 2818 igc_dispatch_skb_zc(q_vector, desc, bi->xdp, timestamp); 2819 fallthrough; 2820 case IGC_XDP_CONSUMED: 2821 xsk_buff_free(bi->xdp); 2822 break; 2823 case IGC_XDP_TX: 2824 case IGC_XDP_REDIRECT: 2825 xdp_status |= res; 2826 break; 2827 } 2828 2829 bi->xdp = NULL; 2830 total_bytes += size; 2831 total_packets++; 2832 cleaned_count++; 2833 ntc++; 2834 if (ntc == ring->count) 2835 ntc = 0; 2836 } 2837 2838 ring->next_to_clean = ntc; 2839 rcu_read_unlock(); 2840 2841 if (cleaned_count >= IGC_RX_BUFFER_WRITE) 2842 failure = !igc_alloc_rx_buffers_zc(ring, cleaned_count); 2843 2844 if (xdp_status) 2845 igc_finalize_xdp(adapter, xdp_status); 2846 2847 igc_update_rx_stats(q_vector, total_packets, total_bytes); 2848 2849 if (xsk_uses_need_wakeup(ring->xsk_pool)) { 2850 if (failure || ring->next_to_clean == ring->next_to_use) 2851 xsk_set_rx_need_wakeup(ring->xsk_pool); 2852 else 2853 xsk_clear_rx_need_wakeup(ring->xsk_pool); 2854 return total_packets; 2855 } 2856 2857 return failure ? budget : total_packets; 2858 } 2859 2860 static void igc_update_tx_stats(struct igc_q_vector *q_vector, 2861 unsigned int packets, unsigned int bytes) 2862 { 2863 struct igc_ring *ring = q_vector->tx.ring; 2864 2865 u64_stats_update_begin(&ring->tx_syncp); 2866 ring->tx_stats.bytes += bytes; 2867 ring->tx_stats.packets += packets; 2868 u64_stats_update_end(&ring->tx_syncp); 2869 2870 q_vector->tx.total_bytes += bytes; 2871 q_vector->tx.total_packets += packets; 2872 } 2873 2874 static void igc_xsk_request_timestamp(void *_priv) 2875 { 2876 struct igc_metadata_request *meta_req = _priv; 2877 struct igc_ring *tx_ring = meta_req->tx_ring; 2878 struct igc_tx_timestamp_request *tstamp; 2879 u32 tx_flags = IGC_TX_FLAGS_TSTAMP; 2880 struct igc_adapter *adapter; 2881 unsigned long lock_flags; 2882 bool found = false; 2883 int i; 2884 2885 if (test_bit(IGC_RING_FLAG_TX_HWTSTAMP, &tx_ring->flags)) { 2886 adapter = netdev_priv(tx_ring->netdev); 2887 2888 spin_lock_irqsave(&adapter->ptp_tx_lock, lock_flags); 2889 2890 /* Search for available tstamp regs */ 2891 for (i = 0; i < IGC_MAX_TX_TSTAMP_REGS; i++) { 2892 tstamp = &adapter->tx_tstamp[i]; 2893 2894 /* tstamp->skb and tstamp->xsk_tx_buffer are in union. 2895 * When tstamp->skb is equal to NULL, 2896 * tstamp->xsk_tx_buffer is equal to NULL as well. 2897 * This condition means that the particular tstamp reg 2898 * is not occupied by other packet. 2899 */ 2900 if (!tstamp->skb) { 2901 found = true; 2902 break; 2903 } 2904 } 2905 2906 /* Return if no available tstamp regs */ 2907 if (!found) { 2908 adapter->tx_hwtstamp_skipped++; 2909 spin_unlock_irqrestore(&adapter->ptp_tx_lock, 2910 lock_flags); 2911 return; 2912 } 2913 2914 tstamp->start = jiffies; 2915 tstamp->xsk_queue_index = tx_ring->queue_index; 2916 tstamp->xsk_tx_buffer = meta_req->tx_buffer; 2917 tstamp->buffer_type = IGC_TX_BUFFER_TYPE_XSK; 2918 2919 /* Hold the transmit completion until timestamp is ready */ 2920 meta_req->tx_buffer->xsk_pending_ts = true; 2921 2922 /* Keep the pointer to tx_timestamp, which is located in XDP 2923 * metadata area. It is the location to store the value of 2924 * tx hardware timestamp. 2925 */ 2926 xsk_tx_metadata_to_compl(meta_req->meta, &tstamp->xsk_meta); 2927 2928 /* Set timestamp bit based on the _TSTAMP(_X) bit. */ 2929 tx_flags |= tstamp->flags; 2930 meta_req->cmd_type |= IGC_SET_FLAG(tx_flags, 2931 IGC_TX_FLAGS_TSTAMP, 2932 (IGC_ADVTXD_MAC_TSTAMP)); 2933 meta_req->cmd_type |= IGC_SET_FLAG(tx_flags, 2934 IGC_TX_FLAGS_TSTAMP_1, 2935 (IGC_ADVTXD_TSTAMP_REG_1)); 2936 meta_req->cmd_type |= IGC_SET_FLAG(tx_flags, 2937 IGC_TX_FLAGS_TSTAMP_2, 2938 (IGC_ADVTXD_TSTAMP_REG_2)); 2939 meta_req->cmd_type |= IGC_SET_FLAG(tx_flags, 2940 IGC_TX_FLAGS_TSTAMP_3, 2941 (IGC_ADVTXD_TSTAMP_REG_3)); 2942 2943 spin_unlock_irqrestore(&adapter->ptp_tx_lock, lock_flags); 2944 } 2945 } 2946 2947 static u64 igc_xsk_fill_timestamp(void *_priv) 2948 { 2949 return *(u64 *)_priv; 2950 } 2951 2952 const struct xsk_tx_metadata_ops igc_xsk_tx_metadata_ops = { 2953 .tmo_request_timestamp = igc_xsk_request_timestamp, 2954 .tmo_fill_timestamp = igc_xsk_fill_timestamp, 2955 }; 2956 2957 static void igc_xdp_xmit_zc(struct igc_ring *ring) 2958 { 2959 struct xsk_buff_pool *pool = ring->xsk_pool; 2960 struct netdev_queue *nq = txring_txq(ring); 2961 union igc_adv_tx_desc *tx_desc = NULL; 2962 int cpu = smp_processor_id(); 2963 struct xdp_desc xdp_desc; 2964 u16 budget, ntu; 2965 2966 if (!netif_carrier_ok(ring->netdev)) 2967 return; 2968 2969 __netif_tx_lock(nq, cpu); 2970 2971 /* Avoid transmit queue timeout since we share it with the slow path */ 2972 txq_trans_cond_update(nq); 2973 2974 ntu = ring->next_to_use; 2975 budget = igc_desc_unused(ring); 2976 2977 while (xsk_tx_peek_desc(pool, &xdp_desc) && budget--) { 2978 struct igc_metadata_request meta_req; 2979 struct xsk_tx_metadata *meta = NULL; 2980 struct igc_tx_buffer *bi; 2981 u32 olinfo_status; 2982 dma_addr_t dma; 2983 2984 meta_req.cmd_type = IGC_ADVTXD_DTYP_DATA | 2985 IGC_ADVTXD_DCMD_DEXT | 2986 IGC_ADVTXD_DCMD_IFCS | 2987 IGC_TXD_DCMD | xdp_desc.len; 2988 olinfo_status = xdp_desc.len << IGC_ADVTXD_PAYLEN_SHIFT; 2989 2990 dma = xsk_buff_raw_get_dma(pool, xdp_desc.addr); 2991 meta = xsk_buff_get_metadata(pool, xdp_desc.addr); 2992 xsk_buff_raw_dma_sync_for_device(pool, dma, xdp_desc.len); 2993 bi = &ring->tx_buffer_info[ntu]; 2994 2995 meta_req.tx_ring = ring; 2996 meta_req.tx_buffer = bi; 2997 meta_req.meta = meta; 2998 xsk_tx_metadata_request(meta, &igc_xsk_tx_metadata_ops, 2999 &meta_req); 3000 3001 tx_desc = IGC_TX_DESC(ring, ntu); 3002 tx_desc->read.cmd_type_len = cpu_to_le32(meta_req.cmd_type); 3003 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 3004 tx_desc->read.buffer_addr = cpu_to_le64(dma); 3005 3006 bi->type = IGC_TX_BUFFER_TYPE_XSK; 3007 bi->protocol = 0; 3008 bi->bytecount = xdp_desc.len; 3009 bi->gso_segs = 1; 3010 bi->time_stamp = jiffies; 3011 bi->next_to_watch = tx_desc; 3012 3013 netdev_tx_sent_queue(txring_txq(ring), xdp_desc.len); 3014 3015 ntu++; 3016 if (ntu == ring->count) 3017 ntu = 0; 3018 } 3019 3020 ring->next_to_use = ntu; 3021 if (tx_desc) { 3022 igc_flush_tx_descriptors(ring); 3023 xsk_tx_release(pool); 3024 } 3025 3026 __netif_tx_unlock(nq); 3027 } 3028 3029 /** 3030 * igc_clean_tx_irq - Reclaim resources after transmit completes 3031 * @q_vector: pointer to q_vector containing needed info 3032 * @napi_budget: Used to determine if we are in netpoll 3033 * 3034 * returns true if ring is completely cleaned 3035 */ 3036 static bool igc_clean_tx_irq(struct igc_q_vector *q_vector, int napi_budget) 3037 { 3038 struct igc_adapter *adapter = q_vector->adapter; 3039 unsigned int total_bytes = 0, total_packets = 0; 3040 unsigned int budget = q_vector->tx.work_limit; 3041 struct igc_ring *tx_ring = q_vector->tx.ring; 3042 unsigned int i = tx_ring->next_to_clean; 3043 struct igc_tx_buffer *tx_buffer; 3044 union igc_adv_tx_desc *tx_desc; 3045 u32 xsk_frames = 0; 3046 3047 if (test_bit(__IGC_DOWN, &adapter->state)) 3048 return true; 3049 3050 tx_buffer = &tx_ring->tx_buffer_info[i]; 3051 tx_desc = IGC_TX_DESC(tx_ring, i); 3052 i -= tx_ring->count; 3053 3054 do { 3055 union igc_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 3056 3057 /* if next_to_watch is not set then there is no work pending */ 3058 if (!eop_desc) 3059 break; 3060 3061 /* prevent any other reads prior to eop_desc */ 3062 smp_rmb(); 3063 3064 /* if DD is not set pending work has not been completed */ 3065 if (!(eop_desc->wb.status & cpu_to_le32(IGC_TXD_STAT_DD))) 3066 break; 3067 3068 /* Hold the completions while there's a pending tx hardware 3069 * timestamp request from XDP Tx metadata. 3070 */ 3071 if (tx_buffer->type == IGC_TX_BUFFER_TYPE_XSK && 3072 tx_buffer->xsk_pending_ts) 3073 break; 3074 3075 /* clear next_to_watch to prevent false hangs */ 3076 tx_buffer->next_to_watch = NULL; 3077 3078 /* update the statistics for this packet */ 3079 total_bytes += tx_buffer->bytecount; 3080 total_packets += tx_buffer->gso_segs; 3081 3082 switch (tx_buffer->type) { 3083 case IGC_TX_BUFFER_TYPE_XSK: 3084 xsk_frames++; 3085 break; 3086 case IGC_TX_BUFFER_TYPE_XDP: 3087 xdp_return_frame(tx_buffer->xdpf); 3088 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 3089 break; 3090 case IGC_TX_BUFFER_TYPE_SKB: 3091 napi_consume_skb(tx_buffer->skb, napi_budget); 3092 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 3093 break; 3094 default: 3095 netdev_warn_once(tx_ring->netdev, "Unknown Tx buffer type\n"); 3096 break; 3097 } 3098 3099 /* clear last DMA location and unmap remaining buffers */ 3100 while (tx_desc != eop_desc) { 3101 tx_buffer++; 3102 tx_desc++; 3103 i++; 3104 if (unlikely(!i)) { 3105 i -= tx_ring->count; 3106 tx_buffer = tx_ring->tx_buffer_info; 3107 tx_desc = IGC_TX_DESC(tx_ring, 0); 3108 } 3109 3110 /* unmap any remaining paged data */ 3111 if (dma_unmap_len(tx_buffer, len)) 3112 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 3113 } 3114 3115 /* move us one more past the eop_desc for start of next pkt */ 3116 tx_buffer++; 3117 tx_desc++; 3118 i++; 3119 if (unlikely(!i)) { 3120 i -= tx_ring->count; 3121 tx_buffer = tx_ring->tx_buffer_info; 3122 tx_desc = IGC_TX_DESC(tx_ring, 0); 3123 } 3124 3125 /* issue prefetch for next Tx descriptor */ 3126 prefetch(tx_desc); 3127 3128 /* update budget accounting */ 3129 budget--; 3130 } while (likely(budget)); 3131 3132 netdev_tx_completed_queue(txring_txq(tx_ring), 3133 total_packets, total_bytes); 3134 3135 i += tx_ring->count; 3136 tx_ring->next_to_clean = i; 3137 3138 igc_update_tx_stats(q_vector, total_packets, total_bytes); 3139 3140 if (tx_ring->xsk_pool) { 3141 if (xsk_frames) 3142 xsk_tx_completed(tx_ring->xsk_pool, xsk_frames); 3143 if (xsk_uses_need_wakeup(tx_ring->xsk_pool)) 3144 xsk_set_tx_need_wakeup(tx_ring->xsk_pool); 3145 igc_xdp_xmit_zc(tx_ring); 3146 } 3147 3148 if (test_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 3149 struct igc_hw *hw = &adapter->hw; 3150 3151 /* Detect a transmit hang in hardware, this serializes the 3152 * check with the clearing of time_stamp and movement of i 3153 */ 3154 clear_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 3155 if (tx_buffer->next_to_watch && 3156 time_after(jiffies, tx_buffer->time_stamp + 3157 (adapter->tx_timeout_factor * HZ)) && 3158 !(rd32(IGC_STATUS) & IGC_STATUS_TXOFF) && 3159 (rd32(IGC_TDH(tx_ring->reg_idx)) != readl(tx_ring->tail)) && 3160 !tx_ring->oper_gate_closed) { 3161 /* detected Tx unit hang */ 3162 netdev_err(tx_ring->netdev, 3163 "Detected Tx Unit Hang\n" 3164 " Tx Queue <%d>\n" 3165 " TDH <%x>\n" 3166 " TDT <%x>\n" 3167 " next_to_use <%x>\n" 3168 " next_to_clean <%x>\n" 3169 "buffer_info[next_to_clean]\n" 3170 " time_stamp <%lx>\n" 3171 " next_to_watch <%p>\n" 3172 " jiffies <%lx>\n" 3173 " desc.status <%x>\n", 3174 tx_ring->queue_index, 3175 rd32(IGC_TDH(tx_ring->reg_idx)), 3176 readl(tx_ring->tail), 3177 tx_ring->next_to_use, 3178 tx_ring->next_to_clean, 3179 tx_buffer->time_stamp, 3180 tx_buffer->next_to_watch, 3181 jiffies, 3182 tx_buffer->next_to_watch->wb.status); 3183 netif_stop_subqueue(tx_ring->netdev, 3184 tx_ring->queue_index); 3185 3186 /* we are about to reset, no point in enabling stuff */ 3187 return true; 3188 } 3189 } 3190 3191 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 3192 if (unlikely(total_packets && 3193 netif_carrier_ok(tx_ring->netdev) && 3194 igc_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 3195 /* Make sure that anybody stopping the queue after this 3196 * sees the new next_to_clean. 3197 */ 3198 smp_mb(); 3199 if (__netif_subqueue_stopped(tx_ring->netdev, 3200 tx_ring->queue_index) && 3201 !(test_bit(__IGC_DOWN, &adapter->state))) { 3202 netif_wake_subqueue(tx_ring->netdev, 3203 tx_ring->queue_index); 3204 3205 u64_stats_update_begin(&tx_ring->tx_syncp); 3206 tx_ring->tx_stats.restart_queue++; 3207 u64_stats_update_end(&tx_ring->tx_syncp); 3208 } 3209 } 3210 3211 return !!budget; 3212 } 3213 3214 static int igc_find_mac_filter(struct igc_adapter *adapter, 3215 enum igc_mac_filter_type type, const u8 *addr) 3216 { 3217 struct igc_hw *hw = &adapter->hw; 3218 int max_entries = hw->mac.rar_entry_count; 3219 u32 ral, rah; 3220 int i; 3221 3222 for (i = 0; i < max_entries; i++) { 3223 ral = rd32(IGC_RAL(i)); 3224 rah = rd32(IGC_RAH(i)); 3225 3226 if (!(rah & IGC_RAH_AV)) 3227 continue; 3228 if (!!(rah & IGC_RAH_ASEL_SRC_ADDR) != type) 3229 continue; 3230 if ((rah & IGC_RAH_RAH_MASK) != 3231 le16_to_cpup((__le16 *)(addr + 4))) 3232 continue; 3233 if (ral != le32_to_cpup((__le32 *)(addr))) 3234 continue; 3235 3236 return i; 3237 } 3238 3239 return -1; 3240 } 3241 3242 static int igc_get_avail_mac_filter_slot(struct igc_adapter *adapter) 3243 { 3244 struct igc_hw *hw = &adapter->hw; 3245 int max_entries = hw->mac.rar_entry_count; 3246 u32 rah; 3247 int i; 3248 3249 for (i = 0; i < max_entries; i++) { 3250 rah = rd32(IGC_RAH(i)); 3251 3252 if (!(rah & IGC_RAH_AV)) 3253 return i; 3254 } 3255 3256 return -1; 3257 } 3258 3259 /** 3260 * igc_add_mac_filter() - Add MAC address filter 3261 * @adapter: Pointer to adapter where the filter should be added 3262 * @type: MAC address filter type (source or destination) 3263 * @addr: MAC address 3264 * @queue: If non-negative, queue assignment feature is enabled and frames 3265 * matching the filter are enqueued onto 'queue'. Otherwise, queue 3266 * assignment is disabled. 3267 * 3268 * Return: 0 in case of success, negative errno code otherwise. 3269 */ 3270 static int igc_add_mac_filter(struct igc_adapter *adapter, 3271 enum igc_mac_filter_type type, const u8 *addr, 3272 int queue) 3273 { 3274 struct net_device *dev = adapter->netdev; 3275 int index; 3276 3277 index = igc_find_mac_filter(adapter, type, addr); 3278 if (index >= 0) 3279 goto update_filter; 3280 3281 index = igc_get_avail_mac_filter_slot(adapter); 3282 if (index < 0) 3283 return -ENOSPC; 3284 3285 netdev_dbg(dev, "Add MAC address filter: index %d type %s address %pM queue %d\n", 3286 index, type == IGC_MAC_FILTER_TYPE_DST ? "dst" : "src", 3287 addr, queue); 3288 3289 update_filter: 3290 igc_set_mac_filter_hw(adapter, index, type, addr, queue); 3291 return 0; 3292 } 3293 3294 /** 3295 * igc_del_mac_filter() - Delete MAC address filter 3296 * @adapter: Pointer to adapter where the filter should be deleted from 3297 * @type: MAC address filter type (source or destination) 3298 * @addr: MAC address 3299 */ 3300 static void igc_del_mac_filter(struct igc_adapter *adapter, 3301 enum igc_mac_filter_type type, const u8 *addr) 3302 { 3303 struct net_device *dev = adapter->netdev; 3304 int index; 3305 3306 index = igc_find_mac_filter(adapter, type, addr); 3307 if (index < 0) 3308 return; 3309 3310 if (index == 0) { 3311 /* If this is the default filter, we don't actually delete it. 3312 * We just reset to its default value i.e. disable queue 3313 * assignment. 3314 */ 3315 netdev_dbg(dev, "Disable default MAC filter queue assignment"); 3316 3317 igc_set_mac_filter_hw(adapter, 0, type, addr, -1); 3318 } else { 3319 netdev_dbg(dev, "Delete MAC address filter: index %d type %s address %pM\n", 3320 index, 3321 type == IGC_MAC_FILTER_TYPE_DST ? "dst" : "src", 3322 addr); 3323 3324 igc_clear_mac_filter_hw(adapter, index); 3325 } 3326 } 3327 3328 /** 3329 * igc_add_vlan_prio_filter() - Add VLAN priority filter 3330 * @adapter: Pointer to adapter where the filter should be added 3331 * @prio: VLAN priority value 3332 * @queue: Queue number which matching frames are assigned to 3333 * 3334 * Return: 0 in case of success, negative errno code otherwise. 3335 */ 3336 static int igc_add_vlan_prio_filter(struct igc_adapter *adapter, int prio, 3337 int queue) 3338 { 3339 struct net_device *dev = adapter->netdev; 3340 struct igc_hw *hw = &adapter->hw; 3341 u32 vlanpqf; 3342 3343 vlanpqf = rd32(IGC_VLANPQF); 3344 3345 if (vlanpqf & IGC_VLANPQF_VALID(prio)) { 3346 netdev_dbg(dev, "VLAN priority filter already in use\n"); 3347 return -EEXIST; 3348 } 3349 3350 vlanpqf |= IGC_VLANPQF_QSEL(prio, queue); 3351 vlanpqf |= IGC_VLANPQF_VALID(prio); 3352 3353 wr32(IGC_VLANPQF, vlanpqf); 3354 3355 netdev_dbg(dev, "Add VLAN priority filter: prio %d queue %d\n", 3356 prio, queue); 3357 return 0; 3358 } 3359 3360 /** 3361 * igc_del_vlan_prio_filter() - Delete VLAN priority filter 3362 * @adapter: Pointer to adapter where the filter should be deleted from 3363 * @prio: VLAN priority value 3364 */ 3365 static void igc_del_vlan_prio_filter(struct igc_adapter *adapter, int prio) 3366 { 3367 struct igc_hw *hw = &adapter->hw; 3368 u32 vlanpqf; 3369 3370 vlanpqf = rd32(IGC_VLANPQF); 3371 3372 vlanpqf &= ~IGC_VLANPQF_VALID(prio); 3373 vlanpqf &= ~IGC_VLANPQF_QSEL(prio, IGC_VLANPQF_QUEUE_MASK); 3374 3375 wr32(IGC_VLANPQF, vlanpqf); 3376 3377 netdev_dbg(adapter->netdev, "Delete VLAN priority filter: prio %d\n", 3378 prio); 3379 } 3380 3381 static int igc_get_avail_etype_filter_slot(struct igc_adapter *adapter) 3382 { 3383 struct igc_hw *hw = &adapter->hw; 3384 int i; 3385 3386 for (i = 0; i < MAX_ETYPE_FILTER; i++) { 3387 u32 etqf = rd32(IGC_ETQF(i)); 3388 3389 if (!(etqf & IGC_ETQF_FILTER_ENABLE)) 3390 return i; 3391 } 3392 3393 return -1; 3394 } 3395 3396 /** 3397 * igc_add_etype_filter() - Add ethertype filter 3398 * @adapter: Pointer to adapter where the filter should be added 3399 * @etype: Ethertype value 3400 * @queue: If non-negative, queue assignment feature is enabled and frames 3401 * matching the filter are enqueued onto 'queue'. Otherwise, queue 3402 * assignment is disabled. 3403 * 3404 * Return: 0 in case of success, negative errno code otherwise. 3405 */ 3406 static int igc_add_etype_filter(struct igc_adapter *adapter, u16 etype, 3407 int queue) 3408 { 3409 struct igc_hw *hw = &adapter->hw; 3410 int index; 3411 u32 etqf; 3412 3413 index = igc_get_avail_etype_filter_slot(adapter); 3414 if (index < 0) 3415 return -ENOSPC; 3416 3417 etqf = rd32(IGC_ETQF(index)); 3418 3419 etqf &= ~IGC_ETQF_ETYPE_MASK; 3420 etqf |= etype; 3421 3422 if (queue >= 0) { 3423 etqf &= ~IGC_ETQF_QUEUE_MASK; 3424 etqf |= (queue << IGC_ETQF_QUEUE_SHIFT); 3425 etqf |= IGC_ETQF_QUEUE_ENABLE; 3426 } 3427 3428 etqf |= IGC_ETQF_FILTER_ENABLE; 3429 3430 wr32(IGC_ETQF(index), etqf); 3431 3432 netdev_dbg(adapter->netdev, "Add ethertype filter: etype %04x queue %d\n", 3433 etype, queue); 3434 return 0; 3435 } 3436 3437 static int igc_find_etype_filter(struct igc_adapter *adapter, u16 etype) 3438 { 3439 struct igc_hw *hw = &adapter->hw; 3440 int i; 3441 3442 for (i = 0; i < MAX_ETYPE_FILTER; i++) { 3443 u32 etqf = rd32(IGC_ETQF(i)); 3444 3445 if ((etqf & IGC_ETQF_ETYPE_MASK) == etype) 3446 return i; 3447 } 3448 3449 return -1; 3450 } 3451 3452 /** 3453 * igc_del_etype_filter() - Delete ethertype filter 3454 * @adapter: Pointer to adapter where the filter should be deleted from 3455 * @etype: Ethertype value 3456 */ 3457 static void igc_del_etype_filter(struct igc_adapter *adapter, u16 etype) 3458 { 3459 struct igc_hw *hw = &adapter->hw; 3460 int index; 3461 3462 index = igc_find_etype_filter(adapter, etype); 3463 if (index < 0) 3464 return; 3465 3466 wr32(IGC_ETQF(index), 0); 3467 3468 netdev_dbg(adapter->netdev, "Delete ethertype filter: etype %04x\n", 3469 etype); 3470 } 3471 3472 static int igc_flex_filter_select(struct igc_adapter *adapter, 3473 struct igc_flex_filter *input, 3474 u32 *fhft) 3475 { 3476 struct igc_hw *hw = &adapter->hw; 3477 u8 fhft_index; 3478 u32 fhftsl; 3479 3480 if (input->index >= MAX_FLEX_FILTER) { 3481 netdev_err(adapter->netdev, "Wrong Flex Filter index selected!\n"); 3482 return -EINVAL; 3483 } 3484 3485 /* Indirect table select register */ 3486 fhftsl = rd32(IGC_FHFTSL); 3487 fhftsl &= ~IGC_FHFTSL_FTSL_MASK; 3488 switch (input->index) { 3489 case 0 ... 7: 3490 fhftsl |= 0x00; 3491 break; 3492 case 8 ... 15: 3493 fhftsl |= 0x01; 3494 break; 3495 case 16 ... 23: 3496 fhftsl |= 0x02; 3497 break; 3498 case 24 ... 31: 3499 fhftsl |= 0x03; 3500 break; 3501 } 3502 wr32(IGC_FHFTSL, fhftsl); 3503 3504 /* Normalize index down to host table register */ 3505 fhft_index = input->index % 8; 3506 3507 *fhft = (fhft_index < 4) ? IGC_FHFT(fhft_index) : 3508 IGC_FHFT_EXT(fhft_index - 4); 3509 3510 return 0; 3511 } 3512 3513 static int igc_write_flex_filter_ll(struct igc_adapter *adapter, 3514 struct igc_flex_filter *input) 3515 { 3516 struct igc_hw *hw = &adapter->hw; 3517 u8 *data = input->data; 3518 u8 *mask = input->mask; 3519 u32 queuing; 3520 u32 fhft; 3521 u32 wufc; 3522 int ret; 3523 int i; 3524 3525 /* Length has to be aligned to 8. Otherwise the filter will fail. Bail 3526 * out early to avoid surprises later. 3527 */ 3528 if (input->length % 8 != 0) { 3529 netdev_err(adapter->netdev, "The length of a flex filter has to be 8 byte aligned!\n"); 3530 return -EINVAL; 3531 } 3532 3533 /* Select corresponding flex filter register and get base for host table. */ 3534 ret = igc_flex_filter_select(adapter, input, &fhft); 3535 if (ret) 3536 return ret; 3537 3538 /* When adding a filter globally disable flex filter feature. That is 3539 * recommended within the datasheet. 3540 */ 3541 wufc = rd32(IGC_WUFC); 3542 wufc &= ~IGC_WUFC_FLEX_HQ; 3543 wr32(IGC_WUFC, wufc); 3544 3545 /* Configure filter */ 3546 queuing = input->length & IGC_FHFT_LENGTH_MASK; 3547 queuing |= FIELD_PREP(IGC_FHFT_QUEUE_MASK, input->rx_queue); 3548 queuing |= FIELD_PREP(IGC_FHFT_PRIO_MASK, input->prio); 3549 3550 if (input->immediate_irq) 3551 queuing |= IGC_FHFT_IMM_INT; 3552 3553 if (input->drop) 3554 queuing |= IGC_FHFT_DROP; 3555 3556 wr32(fhft + 0xFC, queuing); 3557 3558 /* Write data (128 byte) and mask (128 bit) */ 3559 for (i = 0; i < 16; ++i) { 3560 const size_t data_idx = i * 8; 3561 const size_t row_idx = i * 16; 3562 u32 dw0 = 3563 (data[data_idx + 0] << 0) | 3564 (data[data_idx + 1] << 8) | 3565 (data[data_idx + 2] << 16) | 3566 (data[data_idx + 3] << 24); 3567 u32 dw1 = 3568 (data[data_idx + 4] << 0) | 3569 (data[data_idx + 5] << 8) | 3570 (data[data_idx + 6] << 16) | 3571 (data[data_idx + 7] << 24); 3572 u32 tmp; 3573 3574 /* Write row: dw0, dw1 and mask */ 3575 wr32(fhft + row_idx, dw0); 3576 wr32(fhft + row_idx + 4, dw1); 3577 3578 /* mask is only valid for MASK(7, 0) */ 3579 tmp = rd32(fhft + row_idx + 8); 3580 tmp &= ~GENMASK(7, 0); 3581 tmp |= mask[i]; 3582 wr32(fhft + row_idx + 8, tmp); 3583 } 3584 3585 /* Enable filter. */ 3586 wufc |= IGC_WUFC_FLEX_HQ; 3587 if (input->index > 8) { 3588 /* Filter 0-7 are enabled via WUFC. The other 24 filters are not. */ 3589 u32 wufc_ext = rd32(IGC_WUFC_EXT); 3590 3591 wufc_ext |= (IGC_WUFC_EXT_FLX8 << (input->index - 8)); 3592 3593 wr32(IGC_WUFC_EXT, wufc_ext); 3594 } else { 3595 wufc |= (IGC_WUFC_FLX0 << input->index); 3596 } 3597 wr32(IGC_WUFC, wufc); 3598 3599 netdev_dbg(adapter->netdev, "Added flex filter %u to HW.\n", 3600 input->index); 3601 3602 return 0; 3603 } 3604 3605 static void igc_flex_filter_add_field(struct igc_flex_filter *flex, 3606 const void *src, unsigned int offset, 3607 size_t len, const void *mask) 3608 { 3609 int i; 3610 3611 /* data */ 3612 memcpy(&flex->data[offset], src, len); 3613 3614 /* mask */ 3615 for (i = 0; i < len; ++i) { 3616 const unsigned int idx = i + offset; 3617 const u8 *ptr = mask; 3618 3619 if (mask) { 3620 if (ptr[i] & 0xff) 3621 flex->mask[idx / 8] |= BIT(idx % 8); 3622 3623 continue; 3624 } 3625 3626 flex->mask[idx / 8] |= BIT(idx % 8); 3627 } 3628 } 3629 3630 static int igc_find_avail_flex_filter_slot(struct igc_adapter *adapter) 3631 { 3632 struct igc_hw *hw = &adapter->hw; 3633 u32 wufc, wufc_ext; 3634 int i; 3635 3636 wufc = rd32(IGC_WUFC); 3637 wufc_ext = rd32(IGC_WUFC_EXT); 3638 3639 for (i = 0; i < MAX_FLEX_FILTER; i++) { 3640 if (i < 8) { 3641 if (!(wufc & (IGC_WUFC_FLX0 << i))) 3642 return i; 3643 } else { 3644 if (!(wufc_ext & (IGC_WUFC_EXT_FLX8 << (i - 8)))) 3645 return i; 3646 } 3647 } 3648 3649 return -ENOSPC; 3650 } 3651 3652 static bool igc_flex_filter_in_use(struct igc_adapter *adapter) 3653 { 3654 struct igc_hw *hw = &adapter->hw; 3655 u32 wufc, wufc_ext; 3656 3657 wufc = rd32(IGC_WUFC); 3658 wufc_ext = rd32(IGC_WUFC_EXT); 3659 3660 if (wufc & IGC_WUFC_FILTER_MASK) 3661 return true; 3662 3663 if (wufc_ext & IGC_WUFC_EXT_FILTER_MASK) 3664 return true; 3665 3666 return false; 3667 } 3668 3669 static int igc_add_flex_filter(struct igc_adapter *adapter, 3670 struct igc_nfc_rule *rule) 3671 { 3672 struct igc_nfc_filter *filter = &rule->filter; 3673 unsigned int eth_offset, user_offset; 3674 struct igc_flex_filter flex = { }; 3675 int ret, index; 3676 bool vlan; 3677 3678 index = igc_find_avail_flex_filter_slot(adapter); 3679 if (index < 0) 3680 return -ENOSPC; 3681 3682 /* Construct the flex filter: 3683 * -> dest_mac [6] 3684 * -> src_mac [6] 3685 * -> tpid [2] 3686 * -> vlan tci [2] 3687 * -> ether type [2] 3688 * -> user data [8] 3689 * -> = 26 bytes => 32 length 3690 */ 3691 flex.index = index; 3692 flex.length = 32; 3693 flex.rx_queue = rule->action; 3694 3695 vlan = rule->filter.vlan_tci || rule->filter.vlan_etype; 3696 eth_offset = vlan ? 16 : 12; 3697 user_offset = vlan ? 18 : 14; 3698 3699 /* Add destination MAC */ 3700 if (rule->filter.match_flags & IGC_FILTER_FLAG_DST_MAC_ADDR) 3701 igc_flex_filter_add_field(&flex, &filter->dst_addr, 0, 3702 ETH_ALEN, NULL); 3703 3704 /* Add source MAC */ 3705 if (rule->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR) 3706 igc_flex_filter_add_field(&flex, &filter->src_addr, 6, 3707 ETH_ALEN, NULL); 3708 3709 /* Add VLAN etype */ 3710 if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_ETYPE) { 3711 __be16 vlan_etype = cpu_to_be16(filter->vlan_etype); 3712 3713 igc_flex_filter_add_field(&flex, &vlan_etype, 12, 3714 sizeof(vlan_etype), NULL); 3715 } 3716 3717 /* Add VLAN TCI */ 3718 if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI) 3719 igc_flex_filter_add_field(&flex, &filter->vlan_tci, 14, 3720 sizeof(filter->vlan_tci), NULL); 3721 3722 /* Add Ether type */ 3723 if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE) { 3724 __be16 etype = cpu_to_be16(filter->etype); 3725 3726 igc_flex_filter_add_field(&flex, &etype, eth_offset, 3727 sizeof(etype), NULL); 3728 } 3729 3730 /* Add user data */ 3731 if (rule->filter.match_flags & IGC_FILTER_FLAG_USER_DATA) 3732 igc_flex_filter_add_field(&flex, &filter->user_data, 3733 user_offset, 3734 sizeof(filter->user_data), 3735 filter->user_mask); 3736 3737 /* Add it down to the hardware and enable it. */ 3738 ret = igc_write_flex_filter_ll(adapter, &flex); 3739 if (ret) 3740 return ret; 3741 3742 filter->flex_index = index; 3743 3744 return 0; 3745 } 3746 3747 static void igc_del_flex_filter(struct igc_adapter *adapter, 3748 u16 reg_index) 3749 { 3750 struct igc_hw *hw = &adapter->hw; 3751 u32 wufc; 3752 3753 /* Just disable the filter. The filter table itself is kept 3754 * intact. Another flex_filter_add() should override the "old" data 3755 * then. 3756 */ 3757 if (reg_index > 8) { 3758 u32 wufc_ext = rd32(IGC_WUFC_EXT); 3759 3760 wufc_ext &= ~(IGC_WUFC_EXT_FLX8 << (reg_index - 8)); 3761 wr32(IGC_WUFC_EXT, wufc_ext); 3762 } else { 3763 wufc = rd32(IGC_WUFC); 3764 3765 wufc &= ~(IGC_WUFC_FLX0 << reg_index); 3766 wr32(IGC_WUFC, wufc); 3767 } 3768 3769 if (igc_flex_filter_in_use(adapter)) 3770 return; 3771 3772 /* No filters are in use, we may disable flex filters */ 3773 wufc = rd32(IGC_WUFC); 3774 wufc &= ~IGC_WUFC_FLEX_HQ; 3775 wr32(IGC_WUFC, wufc); 3776 } 3777 3778 static int igc_enable_nfc_rule(struct igc_adapter *adapter, 3779 struct igc_nfc_rule *rule) 3780 { 3781 int err; 3782 3783 if (rule->flex) { 3784 return igc_add_flex_filter(adapter, rule); 3785 } 3786 3787 if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE) { 3788 err = igc_add_etype_filter(adapter, rule->filter.etype, 3789 rule->action); 3790 if (err) 3791 return err; 3792 } 3793 3794 if (rule->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR) { 3795 err = igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_SRC, 3796 rule->filter.src_addr, rule->action); 3797 if (err) 3798 return err; 3799 } 3800 3801 if (rule->filter.match_flags & IGC_FILTER_FLAG_DST_MAC_ADDR) { 3802 err = igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST, 3803 rule->filter.dst_addr, rule->action); 3804 if (err) 3805 return err; 3806 } 3807 3808 if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI) { 3809 int prio = FIELD_GET(VLAN_PRIO_MASK, rule->filter.vlan_tci); 3810 3811 err = igc_add_vlan_prio_filter(adapter, prio, rule->action); 3812 if (err) 3813 return err; 3814 } 3815 3816 return 0; 3817 } 3818 3819 static void igc_disable_nfc_rule(struct igc_adapter *adapter, 3820 const struct igc_nfc_rule *rule) 3821 { 3822 if (rule->flex) { 3823 igc_del_flex_filter(adapter, rule->filter.flex_index); 3824 return; 3825 } 3826 3827 if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE) 3828 igc_del_etype_filter(adapter, rule->filter.etype); 3829 3830 if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI) { 3831 int prio = FIELD_GET(VLAN_PRIO_MASK, rule->filter.vlan_tci); 3832 3833 igc_del_vlan_prio_filter(adapter, prio); 3834 } 3835 3836 if (rule->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR) 3837 igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_SRC, 3838 rule->filter.src_addr); 3839 3840 if (rule->filter.match_flags & IGC_FILTER_FLAG_DST_MAC_ADDR) 3841 igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST, 3842 rule->filter.dst_addr); 3843 } 3844 3845 /** 3846 * igc_get_nfc_rule() - Get NFC rule 3847 * @adapter: Pointer to adapter 3848 * @location: Rule location 3849 * 3850 * Context: Expects adapter->nfc_rule_lock to be held by caller. 3851 * 3852 * Return: Pointer to NFC rule at @location. If not found, NULL. 3853 */ 3854 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter, 3855 u32 location) 3856 { 3857 struct igc_nfc_rule *rule; 3858 3859 list_for_each_entry(rule, &adapter->nfc_rule_list, list) { 3860 if (rule->location == location) 3861 return rule; 3862 if (rule->location > location) 3863 break; 3864 } 3865 3866 return NULL; 3867 } 3868 3869 /** 3870 * igc_del_nfc_rule() - Delete NFC rule 3871 * @adapter: Pointer to adapter 3872 * @rule: Pointer to rule to be deleted 3873 * 3874 * Disable NFC rule in hardware and delete it from adapter. 3875 * 3876 * Context: Expects adapter->nfc_rule_lock to be held by caller. 3877 */ 3878 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule) 3879 { 3880 igc_disable_nfc_rule(adapter, rule); 3881 3882 list_del(&rule->list); 3883 adapter->nfc_rule_count--; 3884 3885 kfree(rule); 3886 } 3887 3888 static void igc_flush_nfc_rules(struct igc_adapter *adapter) 3889 { 3890 struct igc_nfc_rule *rule, *tmp; 3891 3892 mutex_lock(&adapter->nfc_rule_lock); 3893 3894 list_for_each_entry_safe(rule, tmp, &adapter->nfc_rule_list, list) 3895 igc_del_nfc_rule(adapter, rule); 3896 3897 mutex_unlock(&adapter->nfc_rule_lock); 3898 } 3899 3900 /** 3901 * igc_add_nfc_rule() - Add NFC rule 3902 * @adapter: Pointer to adapter 3903 * @rule: Pointer to rule to be added 3904 * 3905 * Enable NFC rule in hardware and add it to adapter. 3906 * 3907 * Context: Expects adapter->nfc_rule_lock to be held by caller. 3908 * 3909 * Return: 0 on success, negative errno on failure. 3910 */ 3911 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule) 3912 { 3913 struct igc_nfc_rule *pred, *cur; 3914 int err; 3915 3916 err = igc_enable_nfc_rule(adapter, rule); 3917 if (err) 3918 return err; 3919 3920 pred = NULL; 3921 list_for_each_entry(cur, &adapter->nfc_rule_list, list) { 3922 if (cur->location >= rule->location) 3923 break; 3924 pred = cur; 3925 } 3926 3927 list_add(&rule->list, pred ? &pred->list : &adapter->nfc_rule_list); 3928 adapter->nfc_rule_count++; 3929 return 0; 3930 } 3931 3932 static void igc_restore_nfc_rules(struct igc_adapter *adapter) 3933 { 3934 struct igc_nfc_rule *rule; 3935 3936 mutex_lock(&adapter->nfc_rule_lock); 3937 3938 list_for_each_entry_reverse(rule, &adapter->nfc_rule_list, list) 3939 igc_enable_nfc_rule(adapter, rule); 3940 3941 mutex_unlock(&adapter->nfc_rule_lock); 3942 } 3943 3944 static int igc_uc_sync(struct net_device *netdev, const unsigned char *addr) 3945 { 3946 struct igc_adapter *adapter = netdev_priv(netdev); 3947 3948 return igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST, addr, -1); 3949 } 3950 3951 static int igc_uc_unsync(struct net_device *netdev, const unsigned char *addr) 3952 { 3953 struct igc_adapter *adapter = netdev_priv(netdev); 3954 3955 igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST, addr); 3956 return 0; 3957 } 3958 3959 /** 3960 * igc_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 3961 * @netdev: network interface device structure 3962 * 3963 * The set_rx_mode entry point is called whenever the unicast or multicast 3964 * address lists or the network interface flags are updated. This routine is 3965 * responsible for configuring the hardware for proper unicast, multicast, 3966 * promiscuous mode, and all-multi behavior. 3967 */ 3968 static void igc_set_rx_mode(struct net_device *netdev) 3969 { 3970 struct igc_adapter *adapter = netdev_priv(netdev); 3971 struct igc_hw *hw = &adapter->hw; 3972 u32 rctl = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 3973 int count; 3974 3975 /* Check for Promiscuous and All Multicast modes */ 3976 if (netdev->flags & IFF_PROMISC) { 3977 rctl |= IGC_RCTL_UPE | IGC_RCTL_MPE; 3978 } else { 3979 if (netdev->flags & IFF_ALLMULTI) { 3980 rctl |= IGC_RCTL_MPE; 3981 } else { 3982 /* Write addresses to the MTA, if the attempt fails 3983 * then we should just turn on promiscuous mode so 3984 * that we can at least receive multicast traffic 3985 */ 3986 count = igc_write_mc_addr_list(netdev); 3987 if (count < 0) 3988 rctl |= IGC_RCTL_MPE; 3989 } 3990 } 3991 3992 /* Write addresses to available RAR registers, if there is not 3993 * sufficient space to store all the addresses then enable 3994 * unicast promiscuous mode 3995 */ 3996 if (__dev_uc_sync(netdev, igc_uc_sync, igc_uc_unsync)) 3997 rctl |= IGC_RCTL_UPE; 3998 3999 /* update state of unicast and multicast */ 4000 rctl |= rd32(IGC_RCTL) & ~(IGC_RCTL_UPE | IGC_RCTL_MPE); 4001 wr32(IGC_RCTL, rctl); 4002 4003 #if (PAGE_SIZE < 8192) 4004 if (adapter->max_frame_size <= IGC_MAX_FRAME_BUILD_SKB) 4005 rlpml = IGC_MAX_FRAME_BUILD_SKB; 4006 #endif 4007 wr32(IGC_RLPML, rlpml); 4008 } 4009 4010 /** 4011 * igc_configure - configure the hardware for RX and TX 4012 * @adapter: private board structure 4013 */ 4014 static void igc_configure(struct igc_adapter *adapter) 4015 { 4016 struct net_device *netdev = adapter->netdev; 4017 int i = 0; 4018 4019 igc_get_hw_control(adapter); 4020 igc_set_rx_mode(netdev); 4021 4022 igc_restore_vlan(adapter); 4023 4024 igc_setup_tctl(adapter); 4025 igc_setup_mrqc(adapter); 4026 igc_setup_rctl(adapter); 4027 4028 igc_set_default_mac_filter(adapter); 4029 igc_restore_nfc_rules(adapter); 4030 4031 igc_configure_tx(adapter); 4032 igc_configure_rx(adapter); 4033 4034 igc_rx_fifo_flush_base(&adapter->hw); 4035 4036 /* call igc_desc_unused which always leaves 4037 * at least 1 descriptor unused to make sure 4038 * next_to_use != next_to_clean 4039 */ 4040 for (i = 0; i < adapter->num_rx_queues; i++) { 4041 struct igc_ring *ring = adapter->rx_ring[i]; 4042 4043 if (ring->xsk_pool) 4044 igc_alloc_rx_buffers_zc(ring, igc_desc_unused(ring)); 4045 else 4046 igc_alloc_rx_buffers(ring, igc_desc_unused(ring)); 4047 } 4048 } 4049 4050 /** 4051 * igc_write_ivar - configure ivar for given MSI-X vector 4052 * @hw: pointer to the HW structure 4053 * @msix_vector: vector number we are allocating to a given ring 4054 * @index: row index of IVAR register to write within IVAR table 4055 * @offset: column offset of in IVAR, should be multiple of 8 4056 * 4057 * The IVAR table consists of 2 columns, 4058 * each containing an cause allocation for an Rx and Tx ring, and a 4059 * variable number of rows depending on the number of queues supported. 4060 */ 4061 static void igc_write_ivar(struct igc_hw *hw, int msix_vector, 4062 int index, int offset) 4063 { 4064 u32 ivar = array_rd32(IGC_IVAR0, index); 4065 4066 /* clear any bits that are currently set */ 4067 ivar &= ~((u32)0xFF << offset); 4068 4069 /* write vector and valid bit */ 4070 ivar |= (msix_vector | IGC_IVAR_VALID) << offset; 4071 4072 array_wr32(IGC_IVAR0, index, ivar); 4073 } 4074 4075 static void igc_assign_vector(struct igc_q_vector *q_vector, int msix_vector) 4076 { 4077 struct igc_adapter *adapter = q_vector->adapter; 4078 struct igc_hw *hw = &adapter->hw; 4079 int rx_queue = IGC_N0_QUEUE; 4080 int tx_queue = IGC_N0_QUEUE; 4081 4082 if (q_vector->rx.ring) 4083 rx_queue = q_vector->rx.ring->reg_idx; 4084 if (q_vector->tx.ring) 4085 tx_queue = q_vector->tx.ring->reg_idx; 4086 4087 switch (hw->mac.type) { 4088 case igc_i225: 4089 if (rx_queue > IGC_N0_QUEUE) 4090 igc_write_ivar(hw, msix_vector, 4091 rx_queue >> 1, 4092 (rx_queue & 0x1) << 4); 4093 if (tx_queue > IGC_N0_QUEUE) 4094 igc_write_ivar(hw, msix_vector, 4095 tx_queue >> 1, 4096 ((tx_queue & 0x1) << 4) + 8); 4097 q_vector->eims_value = BIT(msix_vector); 4098 break; 4099 default: 4100 WARN_ONCE(hw->mac.type != igc_i225, "Wrong MAC type\n"); 4101 break; 4102 } 4103 4104 /* add q_vector eims value to global eims_enable_mask */ 4105 adapter->eims_enable_mask |= q_vector->eims_value; 4106 4107 /* configure q_vector to set itr on first interrupt */ 4108 q_vector->set_itr = 1; 4109 } 4110 4111 /** 4112 * igc_configure_msix - Configure MSI-X hardware 4113 * @adapter: Pointer to adapter structure 4114 * 4115 * igc_configure_msix sets up the hardware to properly 4116 * generate MSI-X interrupts. 4117 */ 4118 static void igc_configure_msix(struct igc_adapter *adapter) 4119 { 4120 struct igc_hw *hw = &adapter->hw; 4121 int i, vector = 0; 4122 u32 tmp; 4123 4124 adapter->eims_enable_mask = 0; 4125 4126 /* set vector for other causes, i.e. link changes */ 4127 switch (hw->mac.type) { 4128 case igc_i225: 4129 /* Turn on MSI-X capability first, or our settings 4130 * won't stick. And it will take days to debug. 4131 */ 4132 wr32(IGC_GPIE, IGC_GPIE_MSIX_MODE | 4133 IGC_GPIE_PBA | IGC_GPIE_EIAME | 4134 IGC_GPIE_NSICR); 4135 4136 /* enable msix_other interrupt */ 4137 adapter->eims_other = BIT(vector); 4138 tmp = (vector++ | IGC_IVAR_VALID) << 8; 4139 4140 wr32(IGC_IVAR_MISC, tmp); 4141 break; 4142 default: 4143 /* do nothing, since nothing else supports MSI-X */ 4144 break; 4145 } /* switch (hw->mac.type) */ 4146 4147 adapter->eims_enable_mask |= adapter->eims_other; 4148 4149 for (i = 0; i < adapter->num_q_vectors; i++) 4150 igc_assign_vector(adapter->q_vector[i], vector++); 4151 4152 wrfl(); 4153 } 4154 4155 /** 4156 * igc_irq_enable - Enable default interrupt generation settings 4157 * @adapter: board private structure 4158 */ 4159 static void igc_irq_enable(struct igc_adapter *adapter) 4160 { 4161 struct igc_hw *hw = &adapter->hw; 4162 4163 if (adapter->msix_entries) { 4164 u32 ims = IGC_IMS_LSC | IGC_IMS_DOUTSYNC | IGC_IMS_DRSTA; 4165 u32 regval = rd32(IGC_EIAC); 4166 4167 wr32(IGC_EIAC, regval | adapter->eims_enable_mask); 4168 regval = rd32(IGC_EIAM); 4169 wr32(IGC_EIAM, regval | adapter->eims_enable_mask); 4170 wr32(IGC_EIMS, adapter->eims_enable_mask); 4171 wr32(IGC_IMS, ims); 4172 } else { 4173 wr32(IGC_IMS, IMS_ENABLE_MASK | IGC_IMS_DRSTA); 4174 wr32(IGC_IAM, IMS_ENABLE_MASK | IGC_IMS_DRSTA); 4175 } 4176 } 4177 4178 /** 4179 * igc_irq_disable - Mask off interrupt generation on the NIC 4180 * @adapter: board private structure 4181 */ 4182 static void igc_irq_disable(struct igc_adapter *adapter) 4183 { 4184 struct igc_hw *hw = &adapter->hw; 4185 4186 if (adapter->msix_entries) { 4187 u32 regval = rd32(IGC_EIAM); 4188 4189 wr32(IGC_EIAM, regval & ~adapter->eims_enable_mask); 4190 wr32(IGC_EIMC, adapter->eims_enable_mask); 4191 regval = rd32(IGC_EIAC); 4192 wr32(IGC_EIAC, regval & ~adapter->eims_enable_mask); 4193 } 4194 4195 wr32(IGC_IAM, 0); 4196 wr32(IGC_IMC, ~0); 4197 wrfl(); 4198 4199 if (adapter->msix_entries) { 4200 int vector = 0, i; 4201 4202 synchronize_irq(adapter->msix_entries[vector++].vector); 4203 4204 for (i = 0; i < adapter->num_q_vectors; i++) 4205 synchronize_irq(adapter->msix_entries[vector++].vector); 4206 } else { 4207 synchronize_irq(adapter->pdev->irq); 4208 } 4209 } 4210 4211 void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 4212 const u32 max_rss_queues) 4213 { 4214 /* Determine if we need to pair queues. */ 4215 /* If rss_queues > half of max_rss_queues, pair the queues in 4216 * order to conserve interrupts due to limited supply. 4217 */ 4218 if (adapter->rss_queues > (max_rss_queues / 2)) 4219 adapter->flags |= IGC_FLAG_QUEUE_PAIRS; 4220 else 4221 adapter->flags &= ~IGC_FLAG_QUEUE_PAIRS; 4222 } 4223 4224 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter) 4225 { 4226 return IGC_MAX_RX_QUEUES; 4227 } 4228 4229 static void igc_init_queue_configuration(struct igc_adapter *adapter) 4230 { 4231 u32 max_rss_queues; 4232 4233 max_rss_queues = igc_get_max_rss_queues(adapter); 4234 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 4235 4236 igc_set_flag_queue_pairs(adapter, max_rss_queues); 4237 } 4238 4239 /** 4240 * igc_reset_q_vector - Reset config for interrupt vector 4241 * @adapter: board private structure to initialize 4242 * @v_idx: Index of vector to be reset 4243 * 4244 * If NAPI is enabled it will delete any references to the 4245 * NAPI struct. This is preparation for igc_free_q_vector. 4246 */ 4247 static void igc_reset_q_vector(struct igc_adapter *adapter, int v_idx) 4248 { 4249 struct igc_q_vector *q_vector = adapter->q_vector[v_idx]; 4250 4251 /* if we're coming from igc_set_interrupt_capability, the vectors are 4252 * not yet allocated 4253 */ 4254 if (!q_vector) 4255 return; 4256 4257 if (q_vector->tx.ring) 4258 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 4259 4260 if (q_vector->rx.ring) 4261 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 4262 4263 netif_napi_del(&q_vector->napi); 4264 } 4265 4266 /** 4267 * igc_free_q_vector - Free memory allocated for specific interrupt vector 4268 * @adapter: board private structure to initialize 4269 * @v_idx: Index of vector to be freed 4270 * 4271 * This function frees the memory allocated to the q_vector. 4272 */ 4273 static void igc_free_q_vector(struct igc_adapter *adapter, int v_idx) 4274 { 4275 struct igc_q_vector *q_vector = adapter->q_vector[v_idx]; 4276 4277 adapter->q_vector[v_idx] = NULL; 4278 4279 /* igc_get_stats64() might access the rings on this vector, 4280 * we must wait a grace period before freeing it. 4281 */ 4282 if (q_vector) 4283 kfree_rcu(q_vector, rcu); 4284 } 4285 4286 /** 4287 * igc_free_q_vectors - Free memory allocated for interrupt vectors 4288 * @adapter: board private structure to initialize 4289 * 4290 * This function frees the memory allocated to the q_vectors. In addition if 4291 * NAPI is enabled it will delete any references to the NAPI struct prior 4292 * to freeing the q_vector. 4293 */ 4294 static void igc_free_q_vectors(struct igc_adapter *adapter) 4295 { 4296 int v_idx = adapter->num_q_vectors; 4297 4298 adapter->num_tx_queues = 0; 4299 adapter->num_rx_queues = 0; 4300 adapter->num_q_vectors = 0; 4301 4302 while (v_idx--) { 4303 igc_reset_q_vector(adapter, v_idx); 4304 igc_free_q_vector(adapter, v_idx); 4305 } 4306 } 4307 4308 /** 4309 * igc_update_itr - update the dynamic ITR value based on statistics 4310 * @q_vector: pointer to q_vector 4311 * @ring_container: ring info to update the itr for 4312 * 4313 * Stores a new ITR value based on packets and byte 4314 * counts during the last interrupt. The advantage of per interrupt 4315 * computation is faster updates and more accurate ITR for the current 4316 * traffic pattern. Constants in this function were computed 4317 * based on theoretical maximum wire speed and thresholds were set based 4318 * on testing data as well as attempting to minimize response time 4319 * while increasing bulk throughput. 4320 * NOTE: These calculations are only valid when operating in a single- 4321 * queue environment. 4322 */ 4323 static void igc_update_itr(struct igc_q_vector *q_vector, 4324 struct igc_ring_container *ring_container) 4325 { 4326 unsigned int packets = ring_container->total_packets; 4327 unsigned int bytes = ring_container->total_bytes; 4328 u8 itrval = ring_container->itr; 4329 4330 /* no packets, exit with status unchanged */ 4331 if (packets == 0) 4332 return; 4333 4334 switch (itrval) { 4335 case lowest_latency: 4336 /* handle TSO and jumbo frames */ 4337 if (bytes / packets > 8000) 4338 itrval = bulk_latency; 4339 else if ((packets < 5) && (bytes > 512)) 4340 itrval = low_latency; 4341 break; 4342 case low_latency: /* 50 usec aka 20000 ints/s */ 4343 if (bytes > 10000) { 4344 /* this if handles the TSO accounting */ 4345 if (bytes / packets > 8000) 4346 itrval = bulk_latency; 4347 else if ((packets < 10) || ((bytes / packets) > 1200)) 4348 itrval = bulk_latency; 4349 else if ((packets > 35)) 4350 itrval = lowest_latency; 4351 } else if (bytes / packets > 2000) { 4352 itrval = bulk_latency; 4353 } else if (packets <= 2 && bytes < 512) { 4354 itrval = lowest_latency; 4355 } 4356 break; 4357 case bulk_latency: /* 250 usec aka 4000 ints/s */ 4358 if (bytes > 25000) { 4359 if (packets > 35) 4360 itrval = low_latency; 4361 } else if (bytes < 1500) { 4362 itrval = low_latency; 4363 } 4364 break; 4365 } 4366 4367 /* clear work counters since we have the values we need */ 4368 ring_container->total_bytes = 0; 4369 ring_container->total_packets = 0; 4370 4371 /* write updated itr to ring container */ 4372 ring_container->itr = itrval; 4373 } 4374 4375 static void igc_set_itr(struct igc_q_vector *q_vector) 4376 { 4377 struct igc_adapter *adapter = q_vector->adapter; 4378 u32 new_itr = q_vector->itr_val; 4379 u8 current_itr = 0; 4380 4381 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 4382 switch (adapter->link_speed) { 4383 case SPEED_10: 4384 case SPEED_100: 4385 current_itr = 0; 4386 new_itr = IGC_4K_ITR; 4387 goto set_itr_now; 4388 default: 4389 break; 4390 } 4391 4392 igc_update_itr(q_vector, &q_vector->tx); 4393 igc_update_itr(q_vector, &q_vector->rx); 4394 4395 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 4396 4397 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4398 if (current_itr == lowest_latency && 4399 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4400 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4401 current_itr = low_latency; 4402 4403 switch (current_itr) { 4404 /* counts and packets in update_itr are dependent on these numbers */ 4405 case lowest_latency: 4406 new_itr = IGC_70K_ITR; /* 70,000 ints/sec */ 4407 break; 4408 case low_latency: 4409 new_itr = IGC_20K_ITR; /* 20,000 ints/sec */ 4410 break; 4411 case bulk_latency: 4412 new_itr = IGC_4K_ITR; /* 4,000 ints/sec */ 4413 break; 4414 default: 4415 break; 4416 } 4417 4418 set_itr_now: 4419 if (new_itr != q_vector->itr_val) { 4420 /* this attempts to bias the interrupt rate towards Bulk 4421 * by adding intermediate steps when interrupt rate is 4422 * increasing 4423 */ 4424 new_itr = new_itr > q_vector->itr_val ? 4425 max((new_itr * q_vector->itr_val) / 4426 (new_itr + (q_vector->itr_val >> 2)), 4427 new_itr) : new_itr; 4428 /* Don't write the value here; it resets the adapter's 4429 * internal timer, and causes us to delay far longer than 4430 * we should between interrupts. Instead, we write the ITR 4431 * value at the beginning of the next interrupt so the timing 4432 * ends up being correct. 4433 */ 4434 q_vector->itr_val = new_itr; 4435 q_vector->set_itr = 1; 4436 } 4437 } 4438 4439 static void igc_reset_interrupt_capability(struct igc_adapter *adapter) 4440 { 4441 int v_idx = adapter->num_q_vectors; 4442 4443 if (adapter->msix_entries) { 4444 pci_disable_msix(adapter->pdev); 4445 kfree(adapter->msix_entries); 4446 adapter->msix_entries = NULL; 4447 } else if (adapter->flags & IGC_FLAG_HAS_MSI) { 4448 pci_disable_msi(adapter->pdev); 4449 } 4450 4451 while (v_idx--) 4452 igc_reset_q_vector(adapter, v_idx); 4453 } 4454 4455 /** 4456 * igc_set_interrupt_capability - set MSI or MSI-X if supported 4457 * @adapter: Pointer to adapter structure 4458 * @msix: boolean value for MSI-X capability 4459 * 4460 * Attempt to configure interrupts using the best available 4461 * capabilities of the hardware and kernel. 4462 */ 4463 static void igc_set_interrupt_capability(struct igc_adapter *adapter, 4464 bool msix) 4465 { 4466 int numvecs, i; 4467 int err; 4468 4469 if (!msix) 4470 goto msi_only; 4471 adapter->flags |= IGC_FLAG_HAS_MSIX; 4472 4473 /* Number of supported queues. */ 4474 adapter->num_rx_queues = adapter->rss_queues; 4475 4476 adapter->num_tx_queues = adapter->rss_queues; 4477 4478 /* start with one vector for every Rx queue */ 4479 numvecs = adapter->num_rx_queues; 4480 4481 /* if Tx handler is separate add 1 for every Tx queue */ 4482 if (!(adapter->flags & IGC_FLAG_QUEUE_PAIRS)) 4483 numvecs += adapter->num_tx_queues; 4484 4485 /* store the number of vectors reserved for queues */ 4486 adapter->num_q_vectors = numvecs; 4487 4488 /* add 1 vector for link status interrupts */ 4489 numvecs++; 4490 4491 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), 4492 GFP_KERNEL); 4493 4494 if (!adapter->msix_entries) 4495 return; 4496 4497 /* populate entry values */ 4498 for (i = 0; i < numvecs; i++) 4499 adapter->msix_entries[i].entry = i; 4500 4501 err = pci_enable_msix_range(adapter->pdev, 4502 adapter->msix_entries, 4503 numvecs, 4504 numvecs); 4505 if (err > 0) 4506 return; 4507 4508 kfree(adapter->msix_entries); 4509 adapter->msix_entries = NULL; 4510 4511 igc_reset_interrupt_capability(adapter); 4512 4513 msi_only: 4514 adapter->flags &= ~IGC_FLAG_HAS_MSIX; 4515 4516 adapter->rss_queues = 1; 4517 adapter->flags |= IGC_FLAG_QUEUE_PAIRS; 4518 adapter->num_rx_queues = 1; 4519 adapter->num_tx_queues = 1; 4520 adapter->num_q_vectors = 1; 4521 if (!pci_enable_msi(adapter->pdev)) 4522 adapter->flags |= IGC_FLAG_HAS_MSI; 4523 } 4524 4525 /** 4526 * igc_update_ring_itr - update the dynamic ITR value based on packet size 4527 * @q_vector: pointer to q_vector 4528 * 4529 * Stores a new ITR value based on strictly on packet size. This 4530 * algorithm is less sophisticated than that used in igc_update_itr, 4531 * due to the difficulty of synchronizing statistics across multiple 4532 * receive rings. The divisors and thresholds used by this function 4533 * were determined based on theoretical maximum wire speed and testing 4534 * data, in order to minimize response time while increasing bulk 4535 * throughput. 4536 * NOTE: This function is called only when operating in a multiqueue 4537 * receive environment. 4538 */ 4539 static void igc_update_ring_itr(struct igc_q_vector *q_vector) 4540 { 4541 struct igc_adapter *adapter = q_vector->adapter; 4542 int new_val = q_vector->itr_val; 4543 int avg_wire_size = 0; 4544 unsigned int packets; 4545 4546 /* For non-gigabit speeds, just fix the interrupt rate at 4000 4547 * ints/sec - ITR timer value of 120 ticks. 4548 */ 4549 switch (adapter->link_speed) { 4550 case SPEED_10: 4551 case SPEED_100: 4552 new_val = IGC_4K_ITR; 4553 goto set_itr_val; 4554 default: 4555 break; 4556 } 4557 4558 packets = q_vector->rx.total_packets; 4559 if (packets) 4560 avg_wire_size = q_vector->rx.total_bytes / packets; 4561 4562 packets = q_vector->tx.total_packets; 4563 if (packets) 4564 avg_wire_size = max_t(u32, avg_wire_size, 4565 q_vector->tx.total_bytes / packets); 4566 4567 /* if avg_wire_size isn't set no work was done */ 4568 if (!avg_wire_size) 4569 goto clear_counts; 4570 4571 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 4572 avg_wire_size += 24; 4573 4574 /* Don't starve jumbo frames */ 4575 avg_wire_size = min(avg_wire_size, 3000); 4576 4577 /* Give a little boost to mid-size frames */ 4578 if (avg_wire_size > 300 && avg_wire_size < 1200) 4579 new_val = avg_wire_size / 3; 4580 else 4581 new_val = avg_wire_size / 2; 4582 4583 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4584 if (new_val < IGC_20K_ITR && 4585 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4586 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4587 new_val = IGC_20K_ITR; 4588 4589 set_itr_val: 4590 if (new_val != q_vector->itr_val) { 4591 q_vector->itr_val = new_val; 4592 q_vector->set_itr = 1; 4593 } 4594 clear_counts: 4595 q_vector->rx.total_bytes = 0; 4596 q_vector->rx.total_packets = 0; 4597 q_vector->tx.total_bytes = 0; 4598 q_vector->tx.total_packets = 0; 4599 } 4600 4601 static void igc_ring_irq_enable(struct igc_q_vector *q_vector) 4602 { 4603 struct igc_adapter *adapter = q_vector->adapter; 4604 struct igc_hw *hw = &adapter->hw; 4605 4606 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 4607 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 4608 if (adapter->num_q_vectors == 1) 4609 igc_set_itr(q_vector); 4610 else 4611 igc_update_ring_itr(q_vector); 4612 } 4613 4614 if (!test_bit(__IGC_DOWN, &adapter->state)) { 4615 if (adapter->msix_entries) 4616 wr32(IGC_EIMS, q_vector->eims_value); 4617 else 4618 igc_irq_enable(adapter); 4619 } 4620 } 4621 4622 static void igc_add_ring(struct igc_ring *ring, 4623 struct igc_ring_container *head) 4624 { 4625 head->ring = ring; 4626 head->count++; 4627 } 4628 4629 /** 4630 * igc_cache_ring_register - Descriptor ring to register mapping 4631 * @adapter: board private structure to initialize 4632 * 4633 * Once we know the feature-set enabled for the device, we'll cache 4634 * the register offset the descriptor ring is assigned to. 4635 */ 4636 static void igc_cache_ring_register(struct igc_adapter *adapter) 4637 { 4638 int i = 0, j = 0; 4639 4640 switch (adapter->hw.mac.type) { 4641 case igc_i225: 4642 default: 4643 for (; i < adapter->num_rx_queues; i++) 4644 adapter->rx_ring[i]->reg_idx = i; 4645 for (; j < adapter->num_tx_queues; j++) 4646 adapter->tx_ring[j]->reg_idx = j; 4647 break; 4648 } 4649 } 4650 4651 /** 4652 * igc_poll - NAPI Rx polling callback 4653 * @napi: napi polling structure 4654 * @budget: count of how many packets we should handle 4655 */ 4656 static int igc_poll(struct napi_struct *napi, int budget) 4657 { 4658 struct igc_q_vector *q_vector = container_of(napi, 4659 struct igc_q_vector, 4660 napi); 4661 struct igc_ring *rx_ring = q_vector->rx.ring; 4662 bool clean_complete = true; 4663 int work_done = 0; 4664 4665 if (q_vector->tx.ring) 4666 clean_complete = igc_clean_tx_irq(q_vector, budget); 4667 4668 if (rx_ring) { 4669 int cleaned = rx_ring->xsk_pool ? 4670 igc_clean_rx_irq_zc(q_vector, budget) : 4671 igc_clean_rx_irq(q_vector, budget); 4672 4673 work_done += cleaned; 4674 if (cleaned >= budget) 4675 clean_complete = false; 4676 } 4677 4678 /* If all work not completed, return budget and keep polling */ 4679 if (!clean_complete) 4680 return budget; 4681 4682 /* Exit the polling mode, but don't re-enable interrupts if stack might 4683 * poll us due to busy-polling 4684 */ 4685 if (likely(napi_complete_done(napi, work_done))) 4686 igc_ring_irq_enable(q_vector); 4687 4688 return min(work_done, budget - 1); 4689 } 4690 4691 /** 4692 * igc_alloc_q_vector - Allocate memory for a single interrupt vector 4693 * @adapter: board private structure to initialize 4694 * @v_count: q_vectors allocated on adapter, used for ring interleaving 4695 * @v_idx: index of vector in adapter struct 4696 * @txr_count: total number of Tx rings to allocate 4697 * @txr_idx: index of first Tx ring to allocate 4698 * @rxr_count: total number of Rx rings to allocate 4699 * @rxr_idx: index of first Rx ring to allocate 4700 * 4701 * We allocate one q_vector. If allocation fails we return -ENOMEM. 4702 */ 4703 static int igc_alloc_q_vector(struct igc_adapter *adapter, 4704 unsigned int v_count, unsigned int v_idx, 4705 unsigned int txr_count, unsigned int txr_idx, 4706 unsigned int rxr_count, unsigned int rxr_idx) 4707 { 4708 struct igc_q_vector *q_vector; 4709 struct igc_ring *ring; 4710 int ring_count; 4711 4712 /* igc only supports 1 Tx and/or 1 Rx queue per vector */ 4713 if (txr_count > 1 || rxr_count > 1) 4714 return -ENOMEM; 4715 4716 ring_count = txr_count + rxr_count; 4717 4718 /* allocate q_vector and rings */ 4719 q_vector = adapter->q_vector[v_idx]; 4720 if (!q_vector) 4721 q_vector = kzalloc(struct_size(q_vector, ring, ring_count), 4722 GFP_KERNEL); 4723 else 4724 memset(q_vector, 0, struct_size(q_vector, ring, ring_count)); 4725 if (!q_vector) 4726 return -ENOMEM; 4727 4728 /* initialize NAPI */ 4729 netif_napi_add(adapter->netdev, &q_vector->napi, igc_poll); 4730 4731 /* tie q_vector and adapter together */ 4732 adapter->q_vector[v_idx] = q_vector; 4733 q_vector->adapter = adapter; 4734 4735 /* initialize work limits */ 4736 q_vector->tx.work_limit = adapter->tx_work_limit; 4737 4738 /* initialize ITR configuration */ 4739 q_vector->itr_register = adapter->io_addr + IGC_EITR(0); 4740 q_vector->itr_val = IGC_START_ITR; 4741 4742 /* initialize pointer to rings */ 4743 ring = q_vector->ring; 4744 4745 /* initialize ITR */ 4746 if (rxr_count) { 4747 /* rx or rx/tx vector */ 4748 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 4749 q_vector->itr_val = adapter->rx_itr_setting; 4750 } else { 4751 /* tx only vector */ 4752 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 4753 q_vector->itr_val = adapter->tx_itr_setting; 4754 } 4755 4756 if (txr_count) { 4757 /* assign generic ring traits */ 4758 ring->dev = &adapter->pdev->dev; 4759 ring->netdev = adapter->netdev; 4760 4761 /* configure backlink on ring */ 4762 ring->q_vector = q_vector; 4763 4764 /* update q_vector Tx values */ 4765 igc_add_ring(ring, &q_vector->tx); 4766 4767 /* apply Tx specific ring traits */ 4768 ring->count = adapter->tx_ring_count; 4769 ring->queue_index = txr_idx; 4770 4771 /* assign ring to adapter */ 4772 adapter->tx_ring[txr_idx] = ring; 4773 4774 /* push pointer to next ring */ 4775 ring++; 4776 } 4777 4778 if (rxr_count) { 4779 /* assign generic ring traits */ 4780 ring->dev = &adapter->pdev->dev; 4781 ring->netdev = adapter->netdev; 4782 4783 /* configure backlink on ring */ 4784 ring->q_vector = q_vector; 4785 4786 /* update q_vector Rx values */ 4787 igc_add_ring(ring, &q_vector->rx); 4788 4789 /* apply Rx specific ring traits */ 4790 ring->count = adapter->rx_ring_count; 4791 ring->queue_index = rxr_idx; 4792 4793 /* assign ring to adapter */ 4794 adapter->rx_ring[rxr_idx] = ring; 4795 } 4796 4797 return 0; 4798 } 4799 4800 /** 4801 * igc_alloc_q_vectors - Allocate memory for interrupt vectors 4802 * @adapter: board private structure to initialize 4803 * 4804 * We allocate one q_vector per queue interrupt. If allocation fails we 4805 * return -ENOMEM. 4806 */ 4807 static int igc_alloc_q_vectors(struct igc_adapter *adapter) 4808 { 4809 int rxr_remaining = adapter->num_rx_queues; 4810 int txr_remaining = adapter->num_tx_queues; 4811 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 4812 int q_vectors = adapter->num_q_vectors; 4813 int err; 4814 4815 if (q_vectors >= (rxr_remaining + txr_remaining)) { 4816 for (; rxr_remaining; v_idx++) { 4817 err = igc_alloc_q_vector(adapter, q_vectors, v_idx, 4818 0, 0, 1, rxr_idx); 4819 4820 if (err) 4821 goto err_out; 4822 4823 /* update counts and index */ 4824 rxr_remaining--; 4825 rxr_idx++; 4826 } 4827 } 4828 4829 for (; v_idx < q_vectors; v_idx++) { 4830 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 4831 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 4832 4833 err = igc_alloc_q_vector(adapter, q_vectors, v_idx, 4834 tqpv, txr_idx, rqpv, rxr_idx); 4835 4836 if (err) 4837 goto err_out; 4838 4839 /* update counts and index */ 4840 rxr_remaining -= rqpv; 4841 txr_remaining -= tqpv; 4842 rxr_idx++; 4843 txr_idx++; 4844 } 4845 4846 return 0; 4847 4848 err_out: 4849 adapter->num_tx_queues = 0; 4850 adapter->num_rx_queues = 0; 4851 adapter->num_q_vectors = 0; 4852 4853 while (v_idx--) 4854 igc_free_q_vector(adapter, v_idx); 4855 4856 return -ENOMEM; 4857 } 4858 4859 /** 4860 * igc_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 4861 * @adapter: Pointer to adapter structure 4862 * @msix: boolean for MSI-X capability 4863 * 4864 * This function initializes the interrupts and allocates all of the queues. 4865 */ 4866 static int igc_init_interrupt_scheme(struct igc_adapter *adapter, bool msix) 4867 { 4868 struct net_device *dev = adapter->netdev; 4869 int err = 0; 4870 4871 igc_set_interrupt_capability(adapter, msix); 4872 4873 err = igc_alloc_q_vectors(adapter); 4874 if (err) { 4875 netdev_err(dev, "Unable to allocate memory for vectors\n"); 4876 goto err_alloc_q_vectors; 4877 } 4878 4879 igc_cache_ring_register(adapter); 4880 4881 return 0; 4882 4883 err_alloc_q_vectors: 4884 igc_reset_interrupt_capability(adapter); 4885 return err; 4886 } 4887 4888 /** 4889 * igc_sw_init - Initialize general software structures (struct igc_adapter) 4890 * @adapter: board private structure to initialize 4891 * 4892 * igc_sw_init initializes the Adapter private data structure. 4893 * Fields are initialized based on PCI device information and 4894 * OS network device settings (MTU size). 4895 */ 4896 static int igc_sw_init(struct igc_adapter *adapter) 4897 { 4898 struct net_device *netdev = adapter->netdev; 4899 struct pci_dev *pdev = adapter->pdev; 4900 struct igc_hw *hw = &adapter->hw; 4901 4902 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 4903 4904 /* set default ring sizes */ 4905 adapter->tx_ring_count = IGC_DEFAULT_TXD; 4906 adapter->rx_ring_count = IGC_DEFAULT_RXD; 4907 4908 /* set default ITR values */ 4909 adapter->rx_itr_setting = IGC_DEFAULT_ITR; 4910 adapter->tx_itr_setting = IGC_DEFAULT_ITR; 4911 4912 /* set default work limits */ 4913 adapter->tx_work_limit = IGC_DEFAULT_TX_WORK; 4914 4915 /* adjust max frame to be at least the size of a standard frame */ 4916 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 4917 VLAN_HLEN; 4918 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4919 4920 mutex_init(&adapter->nfc_rule_lock); 4921 INIT_LIST_HEAD(&adapter->nfc_rule_list); 4922 adapter->nfc_rule_count = 0; 4923 4924 spin_lock_init(&adapter->stats64_lock); 4925 spin_lock_init(&adapter->qbv_tx_lock); 4926 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 4927 adapter->flags |= IGC_FLAG_HAS_MSIX; 4928 4929 igc_init_queue_configuration(adapter); 4930 4931 /* This call may decrease the number of queues */ 4932 if (igc_init_interrupt_scheme(adapter, true)) { 4933 netdev_err(netdev, "Unable to allocate memory for queues\n"); 4934 return -ENOMEM; 4935 } 4936 4937 /* Explicitly disable IRQ since the NIC can be in any state. */ 4938 igc_irq_disable(adapter); 4939 4940 set_bit(__IGC_DOWN, &adapter->state); 4941 4942 return 0; 4943 } 4944 4945 void igc_set_queue_napi(struct igc_adapter *adapter, int vector, 4946 struct napi_struct *napi) 4947 { 4948 struct igc_q_vector *q_vector = adapter->q_vector[vector]; 4949 4950 if (q_vector->rx.ring) 4951 netif_queue_set_napi(adapter->netdev, 4952 q_vector->rx.ring->queue_index, 4953 NETDEV_QUEUE_TYPE_RX, napi); 4954 4955 if (q_vector->tx.ring) 4956 netif_queue_set_napi(adapter->netdev, 4957 q_vector->tx.ring->queue_index, 4958 NETDEV_QUEUE_TYPE_TX, napi); 4959 } 4960 4961 /** 4962 * igc_up - Open the interface and prepare it to handle traffic 4963 * @adapter: board private structure 4964 */ 4965 void igc_up(struct igc_adapter *adapter) 4966 { 4967 struct igc_hw *hw = &adapter->hw; 4968 struct napi_struct *napi; 4969 int i = 0; 4970 4971 /* hardware has been reset, we need to reload some things */ 4972 igc_configure(adapter); 4973 4974 clear_bit(__IGC_DOWN, &adapter->state); 4975 4976 for (i = 0; i < adapter->num_q_vectors; i++) { 4977 napi = &adapter->q_vector[i]->napi; 4978 napi_enable(napi); 4979 igc_set_queue_napi(adapter, i, napi); 4980 } 4981 4982 if (adapter->msix_entries) 4983 igc_configure_msix(adapter); 4984 else 4985 igc_assign_vector(adapter->q_vector[0], 0); 4986 4987 /* Clear any pending interrupts. */ 4988 rd32(IGC_ICR); 4989 igc_irq_enable(adapter); 4990 4991 netif_tx_start_all_queues(adapter->netdev); 4992 4993 /* start the watchdog. */ 4994 hw->mac.get_link_status = true; 4995 schedule_work(&adapter->watchdog_task); 4996 } 4997 4998 /** 4999 * igc_update_stats - Update the board statistics counters 5000 * @adapter: board private structure 5001 */ 5002 void igc_update_stats(struct igc_adapter *adapter) 5003 { 5004 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 5005 struct pci_dev *pdev = adapter->pdev; 5006 struct igc_hw *hw = &adapter->hw; 5007 u64 _bytes, _packets; 5008 u64 bytes, packets; 5009 unsigned int start; 5010 u32 mpc; 5011 int i; 5012 5013 /* Prevent stats update while adapter is being reset, or if the pci 5014 * connection is down. 5015 */ 5016 if (adapter->link_speed == 0) 5017 return; 5018 if (pci_channel_offline(pdev)) 5019 return; 5020 5021 packets = 0; 5022 bytes = 0; 5023 5024 rcu_read_lock(); 5025 for (i = 0; i < adapter->num_rx_queues; i++) { 5026 struct igc_ring *ring = adapter->rx_ring[i]; 5027 u32 rqdpc = rd32(IGC_RQDPC(i)); 5028 5029 if (hw->mac.type >= igc_i225) 5030 wr32(IGC_RQDPC(i), 0); 5031 5032 if (rqdpc) { 5033 ring->rx_stats.drops += rqdpc; 5034 net_stats->rx_fifo_errors += rqdpc; 5035 } 5036 5037 do { 5038 start = u64_stats_fetch_begin(&ring->rx_syncp); 5039 _bytes = ring->rx_stats.bytes; 5040 _packets = ring->rx_stats.packets; 5041 } while (u64_stats_fetch_retry(&ring->rx_syncp, start)); 5042 bytes += _bytes; 5043 packets += _packets; 5044 } 5045 5046 net_stats->rx_bytes = bytes; 5047 net_stats->rx_packets = packets; 5048 5049 packets = 0; 5050 bytes = 0; 5051 for (i = 0; i < adapter->num_tx_queues; i++) { 5052 struct igc_ring *ring = adapter->tx_ring[i]; 5053 5054 do { 5055 start = u64_stats_fetch_begin(&ring->tx_syncp); 5056 _bytes = ring->tx_stats.bytes; 5057 _packets = ring->tx_stats.packets; 5058 } while (u64_stats_fetch_retry(&ring->tx_syncp, start)); 5059 bytes += _bytes; 5060 packets += _packets; 5061 } 5062 net_stats->tx_bytes = bytes; 5063 net_stats->tx_packets = packets; 5064 rcu_read_unlock(); 5065 5066 /* read stats registers */ 5067 adapter->stats.crcerrs += rd32(IGC_CRCERRS); 5068 adapter->stats.gprc += rd32(IGC_GPRC); 5069 adapter->stats.gorc += rd32(IGC_GORCL); 5070 rd32(IGC_GORCH); /* clear GORCL */ 5071 adapter->stats.bprc += rd32(IGC_BPRC); 5072 adapter->stats.mprc += rd32(IGC_MPRC); 5073 adapter->stats.roc += rd32(IGC_ROC); 5074 5075 adapter->stats.prc64 += rd32(IGC_PRC64); 5076 adapter->stats.prc127 += rd32(IGC_PRC127); 5077 adapter->stats.prc255 += rd32(IGC_PRC255); 5078 adapter->stats.prc511 += rd32(IGC_PRC511); 5079 adapter->stats.prc1023 += rd32(IGC_PRC1023); 5080 adapter->stats.prc1522 += rd32(IGC_PRC1522); 5081 adapter->stats.tlpic += rd32(IGC_TLPIC); 5082 adapter->stats.rlpic += rd32(IGC_RLPIC); 5083 adapter->stats.hgptc += rd32(IGC_HGPTC); 5084 5085 mpc = rd32(IGC_MPC); 5086 adapter->stats.mpc += mpc; 5087 net_stats->rx_fifo_errors += mpc; 5088 adapter->stats.scc += rd32(IGC_SCC); 5089 adapter->stats.ecol += rd32(IGC_ECOL); 5090 adapter->stats.mcc += rd32(IGC_MCC); 5091 adapter->stats.latecol += rd32(IGC_LATECOL); 5092 adapter->stats.dc += rd32(IGC_DC); 5093 adapter->stats.rlec += rd32(IGC_RLEC); 5094 adapter->stats.xonrxc += rd32(IGC_XONRXC); 5095 adapter->stats.xontxc += rd32(IGC_XONTXC); 5096 adapter->stats.xoffrxc += rd32(IGC_XOFFRXC); 5097 adapter->stats.xofftxc += rd32(IGC_XOFFTXC); 5098 adapter->stats.fcruc += rd32(IGC_FCRUC); 5099 adapter->stats.gptc += rd32(IGC_GPTC); 5100 adapter->stats.gotc += rd32(IGC_GOTCL); 5101 rd32(IGC_GOTCH); /* clear GOTCL */ 5102 adapter->stats.rnbc += rd32(IGC_RNBC); 5103 adapter->stats.ruc += rd32(IGC_RUC); 5104 adapter->stats.rfc += rd32(IGC_RFC); 5105 adapter->stats.rjc += rd32(IGC_RJC); 5106 adapter->stats.tor += rd32(IGC_TORH); 5107 adapter->stats.tot += rd32(IGC_TOTH); 5108 adapter->stats.tpr += rd32(IGC_TPR); 5109 5110 adapter->stats.ptc64 += rd32(IGC_PTC64); 5111 adapter->stats.ptc127 += rd32(IGC_PTC127); 5112 adapter->stats.ptc255 += rd32(IGC_PTC255); 5113 adapter->stats.ptc511 += rd32(IGC_PTC511); 5114 adapter->stats.ptc1023 += rd32(IGC_PTC1023); 5115 adapter->stats.ptc1522 += rd32(IGC_PTC1522); 5116 5117 adapter->stats.mptc += rd32(IGC_MPTC); 5118 adapter->stats.bptc += rd32(IGC_BPTC); 5119 5120 adapter->stats.tpt += rd32(IGC_TPT); 5121 adapter->stats.colc += rd32(IGC_COLC); 5122 adapter->stats.colc += rd32(IGC_RERC); 5123 5124 adapter->stats.algnerrc += rd32(IGC_ALGNERRC); 5125 5126 adapter->stats.tsctc += rd32(IGC_TSCTC); 5127 5128 adapter->stats.iac += rd32(IGC_IAC); 5129 5130 /* Fill out the OS statistics structure */ 5131 net_stats->multicast = adapter->stats.mprc; 5132 net_stats->collisions = adapter->stats.colc; 5133 5134 /* Rx Errors */ 5135 5136 /* RLEC on some newer hardware can be incorrect so build 5137 * our own version based on RUC and ROC 5138 */ 5139 net_stats->rx_errors = adapter->stats.rxerrc + 5140 adapter->stats.crcerrs + adapter->stats.algnerrc + 5141 adapter->stats.ruc + adapter->stats.roc + 5142 adapter->stats.cexterr; 5143 net_stats->rx_length_errors = adapter->stats.ruc + 5144 adapter->stats.roc; 5145 net_stats->rx_crc_errors = adapter->stats.crcerrs; 5146 net_stats->rx_frame_errors = adapter->stats.algnerrc; 5147 net_stats->rx_missed_errors = adapter->stats.mpc; 5148 5149 /* Tx Errors */ 5150 net_stats->tx_errors = adapter->stats.ecol + 5151 adapter->stats.latecol; 5152 net_stats->tx_aborted_errors = adapter->stats.ecol; 5153 net_stats->tx_window_errors = adapter->stats.latecol; 5154 net_stats->tx_carrier_errors = adapter->stats.tncrs; 5155 5156 /* Tx Dropped */ 5157 net_stats->tx_dropped = adapter->stats.txdrop; 5158 5159 /* Management Stats */ 5160 adapter->stats.mgptc += rd32(IGC_MGTPTC); 5161 adapter->stats.mgprc += rd32(IGC_MGTPRC); 5162 adapter->stats.mgpdc += rd32(IGC_MGTPDC); 5163 } 5164 5165 /** 5166 * igc_down - Close the interface 5167 * @adapter: board private structure 5168 */ 5169 void igc_down(struct igc_adapter *adapter) 5170 { 5171 struct net_device *netdev = adapter->netdev; 5172 struct igc_hw *hw = &adapter->hw; 5173 u32 tctl, rctl; 5174 int i = 0; 5175 5176 set_bit(__IGC_DOWN, &adapter->state); 5177 5178 igc_ptp_suspend(adapter); 5179 5180 if (pci_device_is_present(adapter->pdev)) { 5181 /* disable receives in the hardware */ 5182 rctl = rd32(IGC_RCTL); 5183 wr32(IGC_RCTL, rctl & ~IGC_RCTL_EN); 5184 /* flush and sleep below */ 5185 } 5186 /* set trans_start so we don't get spurious watchdogs during reset */ 5187 netif_trans_update(netdev); 5188 5189 netif_carrier_off(netdev); 5190 netif_tx_stop_all_queues(netdev); 5191 5192 if (pci_device_is_present(adapter->pdev)) { 5193 /* disable transmits in the hardware */ 5194 tctl = rd32(IGC_TCTL); 5195 tctl &= ~IGC_TCTL_EN; 5196 wr32(IGC_TCTL, tctl); 5197 /* flush both disables and wait for them to finish */ 5198 wrfl(); 5199 usleep_range(10000, 20000); 5200 5201 igc_irq_disable(adapter); 5202 } 5203 5204 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE; 5205 5206 for (i = 0; i < adapter->num_q_vectors; i++) { 5207 if (adapter->q_vector[i]) { 5208 napi_synchronize(&adapter->q_vector[i]->napi); 5209 igc_set_queue_napi(adapter, i, NULL); 5210 napi_disable(&adapter->q_vector[i]->napi); 5211 } 5212 } 5213 5214 del_timer_sync(&adapter->watchdog_timer); 5215 del_timer_sync(&adapter->phy_info_timer); 5216 5217 /* record the stats before reset*/ 5218 spin_lock(&adapter->stats64_lock); 5219 igc_update_stats(adapter); 5220 spin_unlock(&adapter->stats64_lock); 5221 5222 adapter->link_speed = 0; 5223 adapter->link_duplex = 0; 5224 5225 if (!pci_channel_offline(adapter->pdev)) 5226 igc_reset(adapter); 5227 5228 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 5229 adapter->flags &= ~IGC_FLAG_VLAN_PROMISC; 5230 5231 igc_disable_all_tx_rings_hw(adapter); 5232 igc_clean_all_tx_rings(adapter); 5233 igc_clean_all_rx_rings(adapter); 5234 } 5235 5236 void igc_reinit_locked(struct igc_adapter *adapter) 5237 { 5238 while (test_and_set_bit(__IGC_RESETTING, &adapter->state)) 5239 usleep_range(1000, 2000); 5240 igc_down(adapter); 5241 igc_up(adapter); 5242 clear_bit(__IGC_RESETTING, &adapter->state); 5243 } 5244 5245 static void igc_reset_task(struct work_struct *work) 5246 { 5247 struct igc_adapter *adapter; 5248 5249 adapter = container_of(work, struct igc_adapter, reset_task); 5250 5251 rtnl_lock(); 5252 /* If we're already down or resetting, just bail */ 5253 if (test_bit(__IGC_DOWN, &adapter->state) || 5254 test_bit(__IGC_RESETTING, &adapter->state)) { 5255 rtnl_unlock(); 5256 return; 5257 } 5258 5259 igc_rings_dump(adapter); 5260 igc_regs_dump(adapter); 5261 netdev_err(adapter->netdev, "Reset adapter\n"); 5262 igc_reinit_locked(adapter); 5263 rtnl_unlock(); 5264 } 5265 5266 /** 5267 * igc_change_mtu - Change the Maximum Transfer Unit 5268 * @netdev: network interface device structure 5269 * @new_mtu: new value for maximum frame size 5270 * 5271 * Returns 0 on success, negative on failure 5272 */ 5273 static int igc_change_mtu(struct net_device *netdev, int new_mtu) 5274 { 5275 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 5276 struct igc_adapter *adapter = netdev_priv(netdev); 5277 5278 if (igc_xdp_is_enabled(adapter) && new_mtu > ETH_DATA_LEN) { 5279 netdev_dbg(netdev, "Jumbo frames not supported with XDP"); 5280 return -EINVAL; 5281 } 5282 5283 /* adjust max frame to be at least the size of a standard frame */ 5284 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 5285 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 5286 5287 while (test_and_set_bit(__IGC_RESETTING, &adapter->state)) 5288 usleep_range(1000, 2000); 5289 5290 /* igc_down has a dependency on max_frame_size */ 5291 adapter->max_frame_size = max_frame; 5292 5293 if (netif_running(netdev)) 5294 igc_down(adapter); 5295 5296 netdev_dbg(netdev, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); 5297 WRITE_ONCE(netdev->mtu, new_mtu); 5298 5299 if (netif_running(netdev)) 5300 igc_up(adapter); 5301 else 5302 igc_reset(adapter); 5303 5304 clear_bit(__IGC_RESETTING, &adapter->state); 5305 5306 return 0; 5307 } 5308 5309 /** 5310 * igc_tx_timeout - Respond to a Tx Hang 5311 * @netdev: network interface device structure 5312 * @txqueue: queue number that timed out 5313 **/ 5314 static void igc_tx_timeout(struct net_device *netdev, 5315 unsigned int __always_unused txqueue) 5316 { 5317 struct igc_adapter *adapter = netdev_priv(netdev); 5318 struct igc_hw *hw = &adapter->hw; 5319 5320 /* Do the reset outside of interrupt context */ 5321 adapter->tx_timeout_count++; 5322 schedule_work(&adapter->reset_task); 5323 wr32(IGC_EICS, 5324 (adapter->eims_enable_mask & ~adapter->eims_other)); 5325 } 5326 5327 /** 5328 * igc_get_stats64 - Get System Network Statistics 5329 * @netdev: network interface device structure 5330 * @stats: rtnl_link_stats64 pointer 5331 * 5332 * Returns the address of the device statistics structure. 5333 * The statistics are updated here and also from the timer callback. 5334 */ 5335 static void igc_get_stats64(struct net_device *netdev, 5336 struct rtnl_link_stats64 *stats) 5337 { 5338 struct igc_adapter *adapter = netdev_priv(netdev); 5339 5340 spin_lock(&adapter->stats64_lock); 5341 if (!test_bit(__IGC_RESETTING, &adapter->state)) 5342 igc_update_stats(adapter); 5343 memcpy(stats, &adapter->stats64, sizeof(*stats)); 5344 spin_unlock(&adapter->stats64_lock); 5345 } 5346 5347 static netdev_features_t igc_fix_features(struct net_device *netdev, 5348 netdev_features_t features) 5349 { 5350 /* Since there is no support for separate Rx/Tx vlan accel 5351 * enable/disable make sure Tx flag is always in same state as Rx. 5352 */ 5353 if (features & NETIF_F_HW_VLAN_CTAG_RX) 5354 features |= NETIF_F_HW_VLAN_CTAG_TX; 5355 else 5356 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 5357 5358 return features; 5359 } 5360 5361 static int igc_set_features(struct net_device *netdev, 5362 netdev_features_t features) 5363 { 5364 netdev_features_t changed = netdev->features ^ features; 5365 struct igc_adapter *adapter = netdev_priv(netdev); 5366 5367 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 5368 igc_vlan_mode(netdev, features); 5369 5370 /* Add VLAN support */ 5371 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 5372 return 0; 5373 5374 if (!(features & NETIF_F_NTUPLE)) 5375 igc_flush_nfc_rules(adapter); 5376 5377 netdev->features = features; 5378 5379 if (netif_running(netdev)) 5380 igc_reinit_locked(adapter); 5381 else 5382 igc_reset(adapter); 5383 5384 return 1; 5385 } 5386 5387 static netdev_features_t 5388 igc_features_check(struct sk_buff *skb, struct net_device *dev, 5389 netdev_features_t features) 5390 { 5391 unsigned int network_hdr_len, mac_hdr_len; 5392 5393 /* Make certain the headers can be described by a context descriptor */ 5394 mac_hdr_len = skb_network_offset(skb); 5395 if (unlikely(mac_hdr_len > IGC_MAX_MAC_HDR_LEN)) 5396 return features & ~(NETIF_F_HW_CSUM | 5397 NETIF_F_SCTP_CRC | 5398 NETIF_F_HW_VLAN_CTAG_TX | 5399 NETIF_F_TSO | 5400 NETIF_F_TSO6); 5401 5402 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 5403 if (unlikely(network_hdr_len > IGC_MAX_NETWORK_HDR_LEN)) 5404 return features & ~(NETIF_F_HW_CSUM | 5405 NETIF_F_SCTP_CRC | 5406 NETIF_F_TSO | 5407 NETIF_F_TSO6); 5408 5409 /* We can only support IPv4 TSO in tunnels if we can mangle the 5410 * inner IP ID field, so strip TSO if MANGLEID is not supported. 5411 */ 5412 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 5413 features &= ~NETIF_F_TSO; 5414 5415 return features; 5416 } 5417 5418 static void igc_tsync_interrupt(struct igc_adapter *adapter) 5419 { 5420 struct igc_hw *hw = &adapter->hw; 5421 u32 tsauxc, sec, nsec, tsicr; 5422 struct ptp_clock_event event; 5423 struct timespec64 ts; 5424 5425 tsicr = rd32(IGC_TSICR); 5426 5427 if (tsicr & IGC_TSICR_SYS_WRAP) { 5428 event.type = PTP_CLOCK_PPS; 5429 if (adapter->ptp_caps.pps) 5430 ptp_clock_event(adapter->ptp_clock, &event); 5431 } 5432 5433 if (tsicr & IGC_TSICR_TXTS) { 5434 /* retrieve hardware timestamp */ 5435 igc_ptp_tx_tstamp_event(adapter); 5436 } 5437 5438 if (tsicr & IGC_TSICR_TT0) { 5439 spin_lock(&adapter->tmreg_lock); 5440 ts = timespec64_add(adapter->perout[0].start, 5441 adapter->perout[0].period); 5442 wr32(IGC_TRGTTIML0, ts.tv_nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0); 5443 wr32(IGC_TRGTTIMH0, (u32)ts.tv_sec); 5444 tsauxc = rd32(IGC_TSAUXC); 5445 tsauxc |= IGC_TSAUXC_EN_TT0; 5446 wr32(IGC_TSAUXC, tsauxc); 5447 adapter->perout[0].start = ts; 5448 spin_unlock(&adapter->tmreg_lock); 5449 } 5450 5451 if (tsicr & IGC_TSICR_TT1) { 5452 spin_lock(&adapter->tmreg_lock); 5453 ts = timespec64_add(adapter->perout[1].start, 5454 adapter->perout[1].period); 5455 wr32(IGC_TRGTTIML1, ts.tv_nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0); 5456 wr32(IGC_TRGTTIMH1, (u32)ts.tv_sec); 5457 tsauxc = rd32(IGC_TSAUXC); 5458 tsauxc |= IGC_TSAUXC_EN_TT1; 5459 wr32(IGC_TSAUXC, tsauxc); 5460 adapter->perout[1].start = ts; 5461 spin_unlock(&adapter->tmreg_lock); 5462 } 5463 5464 if (tsicr & IGC_TSICR_AUTT0) { 5465 nsec = rd32(IGC_AUXSTMPL0); 5466 sec = rd32(IGC_AUXSTMPH0); 5467 event.type = PTP_CLOCK_EXTTS; 5468 event.index = 0; 5469 event.timestamp = sec * NSEC_PER_SEC + nsec; 5470 ptp_clock_event(adapter->ptp_clock, &event); 5471 } 5472 5473 if (tsicr & IGC_TSICR_AUTT1) { 5474 nsec = rd32(IGC_AUXSTMPL1); 5475 sec = rd32(IGC_AUXSTMPH1); 5476 event.type = PTP_CLOCK_EXTTS; 5477 event.index = 1; 5478 event.timestamp = sec * NSEC_PER_SEC + nsec; 5479 ptp_clock_event(adapter->ptp_clock, &event); 5480 } 5481 } 5482 5483 /** 5484 * igc_msix_other - msix other interrupt handler 5485 * @irq: interrupt number 5486 * @data: pointer to a q_vector 5487 */ 5488 static irqreturn_t igc_msix_other(int irq, void *data) 5489 { 5490 struct igc_adapter *adapter = data; 5491 struct igc_hw *hw = &adapter->hw; 5492 u32 icr = rd32(IGC_ICR); 5493 5494 /* reading ICR causes bit 31 of EICR to be cleared */ 5495 if (icr & IGC_ICR_DRSTA) 5496 schedule_work(&adapter->reset_task); 5497 5498 if (icr & IGC_ICR_DOUTSYNC) { 5499 /* HW is reporting DMA is out of sync */ 5500 adapter->stats.doosync++; 5501 } 5502 5503 if (icr & IGC_ICR_LSC) { 5504 hw->mac.get_link_status = true; 5505 /* guard against interrupt when we're going down */ 5506 if (!test_bit(__IGC_DOWN, &adapter->state)) 5507 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5508 } 5509 5510 if (icr & IGC_ICR_TS) 5511 igc_tsync_interrupt(adapter); 5512 5513 wr32(IGC_EIMS, adapter->eims_other); 5514 5515 return IRQ_HANDLED; 5516 } 5517 5518 static void igc_write_itr(struct igc_q_vector *q_vector) 5519 { 5520 u32 itr_val = q_vector->itr_val & IGC_QVECTOR_MASK; 5521 5522 if (!q_vector->set_itr) 5523 return; 5524 5525 if (!itr_val) 5526 itr_val = IGC_ITR_VAL_MASK; 5527 5528 itr_val |= IGC_EITR_CNT_IGNR; 5529 5530 writel(itr_val, q_vector->itr_register); 5531 q_vector->set_itr = 0; 5532 } 5533 5534 static irqreturn_t igc_msix_ring(int irq, void *data) 5535 { 5536 struct igc_q_vector *q_vector = data; 5537 5538 /* Write the ITR value calculated from the previous interrupt. */ 5539 igc_write_itr(q_vector); 5540 5541 napi_schedule(&q_vector->napi); 5542 5543 return IRQ_HANDLED; 5544 } 5545 5546 /** 5547 * igc_request_msix - Initialize MSI-X interrupts 5548 * @adapter: Pointer to adapter structure 5549 * 5550 * igc_request_msix allocates MSI-X vectors and requests interrupts from the 5551 * kernel. 5552 */ 5553 static int igc_request_msix(struct igc_adapter *adapter) 5554 { 5555 unsigned int num_q_vectors = adapter->num_q_vectors; 5556 int i = 0, err = 0, vector = 0, free_vector = 0; 5557 struct net_device *netdev = adapter->netdev; 5558 5559 err = request_irq(adapter->msix_entries[vector].vector, 5560 &igc_msix_other, 0, netdev->name, adapter); 5561 if (err) 5562 goto err_out; 5563 5564 if (num_q_vectors > MAX_Q_VECTORS) { 5565 num_q_vectors = MAX_Q_VECTORS; 5566 dev_warn(&adapter->pdev->dev, 5567 "The number of queue vectors (%d) is higher than max allowed (%d)\n", 5568 adapter->num_q_vectors, MAX_Q_VECTORS); 5569 } 5570 for (i = 0; i < num_q_vectors; i++) { 5571 struct igc_q_vector *q_vector = adapter->q_vector[i]; 5572 5573 vector++; 5574 5575 q_vector->itr_register = adapter->io_addr + IGC_EITR(vector); 5576 5577 if (q_vector->rx.ring && q_vector->tx.ring) 5578 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 5579 q_vector->rx.ring->queue_index); 5580 else if (q_vector->tx.ring) 5581 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 5582 q_vector->tx.ring->queue_index); 5583 else if (q_vector->rx.ring) 5584 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 5585 q_vector->rx.ring->queue_index); 5586 else 5587 sprintf(q_vector->name, "%s-unused", netdev->name); 5588 5589 err = request_irq(adapter->msix_entries[vector].vector, 5590 igc_msix_ring, 0, q_vector->name, 5591 q_vector); 5592 if (err) 5593 goto err_free; 5594 5595 netif_napi_set_irq(&q_vector->napi, 5596 adapter->msix_entries[vector].vector); 5597 } 5598 5599 igc_configure_msix(adapter); 5600 return 0; 5601 5602 err_free: 5603 /* free already assigned IRQs */ 5604 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 5605 5606 vector--; 5607 for (i = 0; i < vector; i++) { 5608 free_irq(adapter->msix_entries[free_vector++].vector, 5609 adapter->q_vector[i]); 5610 } 5611 err_out: 5612 return err; 5613 } 5614 5615 /** 5616 * igc_clear_interrupt_scheme - reset the device to a state of no interrupts 5617 * @adapter: Pointer to adapter structure 5618 * 5619 * This function resets the device so that it has 0 rx queues, tx queues, and 5620 * MSI-X interrupts allocated. 5621 */ 5622 static void igc_clear_interrupt_scheme(struct igc_adapter *adapter) 5623 { 5624 igc_free_q_vectors(adapter); 5625 igc_reset_interrupt_capability(adapter); 5626 } 5627 5628 /* Need to wait a few seconds after link up to get diagnostic information from 5629 * the phy 5630 */ 5631 static void igc_update_phy_info(struct timer_list *t) 5632 { 5633 struct igc_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5634 5635 igc_get_phy_info(&adapter->hw); 5636 } 5637 5638 /** 5639 * igc_has_link - check shared code for link and determine up/down 5640 * @adapter: pointer to driver private info 5641 */ 5642 bool igc_has_link(struct igc_adapter *adapter) 5643 { 5644 struct igc_hw *hw = &adapter->hw; 5645 bool link_active = false; 5646 5647 /* get_link_status is set on LSC (link status) interrupt or 5648 * rx sequence error interrupt. get_link_status will stay 5649 * false until the igc_check_for_link establishes link 5650 * for copper adapters ONLY 5651 */ 5652 if (!hw->mac.get_link_status) 5653 return true; 5654 hw->mac.ops.check_for_link(hw); 5655 link_active = !hw->mac.get_link_status; 5656 5657 if (hw->mac.type == igc_i225) { 5658 if (!netif_carrier_ok(adapter->netdev)) { 5659 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE; 5660 } else if (!(adapter->flags & IGC_FLAG_NEED_LINK_UPDATE)) { 5661 adapter->flags |= IGC_FLAG_NEED_LINK_UPDATE; 5662 adapter->link_check_timeout = jiffies; 5663 } 5664 } 5665 5666 return link_active; 5667 } 5668 5669 /** 5670 * igc_watchdog - Timer Call-back 5671 * @t: timer for the watchdog 5672 */ 5673 static void igc_watchdog(struct timer_list *t) 5674 { 5675 struct igc_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5676 /* Do the rest outside of interrupt context */ 5677 schedule_work(&adapter->watchdog_task); 5678 } 5679 5680 static void igc_watchdog_task(struct work_struct *work) 5681 { 5682 struct igc_adapter *adapter = container_of(work, 5683 struct igc_adapter, 5684 watchdog_task); 5685 struct net_device *netdev = adapter->netdev; 5686 struct igc_hw *hw = &adapter->hw; 5687 struct igc_phy_info *phy = &hw->phy; 5688 u16 phy_data, retry_count = 20; 5689 u32 link; 5690 int i; 5691 5692 link = igc_has_link(adapter); 5693 5694 if (adapter->flags & IGC_FLAG_NEED_LINK_UPDATE) { 5695 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5696 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE; 5697 else 5698 link = false; 5699 } 5700 5701 if (link) { 5702 /* Cancel scheduled suspend requests. */ 5703 pm_runtime_resume(netdev->dev.parent); 5704 5705 if (!netif_carrier_ok(netdev)) { 5706 u32 ctrl; 5707 5708 hw->mac.ops.get_speed_and_duplex(hw, 5709 &adapter->link_speed, 5710 &adapter->link_duplex); 5711 5712 ctrl = rd32(IGC_CTRL); 5713 /* Link status message must follow this format */ 5714 netdev_info(netdev, 5715 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5716 adapter->link_speed, 5717 adapter->link_duplex == FULL_DUPLEX ? 5718 "Full" : "Half", 5719 (ctrl & IGC_CTRL_TFCE) && 5720 (ctrl & IGC_CTRL_RFCE) ? "RX/TX" : 5721 (ctrl & IGC_CTRL_RFCE) ? "RX" : 5722 (ctrl & IGC_CTRL_TFCE) ? "TX" : "None"); 5723 5724 /* disable EEE if enabled */ 5725 if ((adapter->flags & IGC_FLAG_EEE) && 5726 adapter->link_duplex == HALF_DUPLEX) { 5727 netdev_info(netdev, 5728 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex\n"); 5729 adapter->hw.dev_spec._base.eee_enable = false; 5730 adapter->flags &= ~IGC_FLAG_EEE; 5731 } 5732 5733 /* check if SmartSpeed worked */ 5734 igc_check_downshift(hw); 5735 if (phy->speed_downgraded) 5736 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5737 5738 /* adjust timeout factor according to speed/duplex */ 5739 adapter->tx_timeout_factor = 1; 5740 switch (adapter->link_speed) { 5741 case SPEED_10: 5742 adapter->tx_timeout_factor = 14; 5743 break; 5744 case SPEED_100: 5745 case SPEED_1000: 5746 case SPEED_2500: 5747 adapter->tx_timeout_factor = 1; 5748 break; 5749 } 5750 5751 /* Once the launch time has been set on the wire, there 5752 * is a delay before the link speed can be determined 5753 * based on link-up activity. Write into the register 5754 * as soon as we know the correct link speed. 5755 */ 5756 igc_tsn_adjust_txtime_offset(adapter); 5757 5758 if (adapter->link_speed != SPEED_1000) 5759 goto no_wait; 5760 5761 /* wait for Remote receiver status OK */ 5762 retry_read_status: 5763 if (!igc_read_phy_reg(hw, PHY_1000T_STATUS, 5764 &phy_data)) { 5765 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5766 retry_count) { 5767 msleep(100); 5768 retry_count--; 5769 goto retry_read_status; 5770 } else if (!retry_count) { 5771 netdev_err(netdev, "exceed max 2 second\n"); 5772 } 5773 } else { 5774 netdev_err(netdev, "read 1000Base-T Status Reg\n"); 5775 } 5776 no_wait: 5777 netif_carrier_on(netdev); 5778 5779 /* link state has changed, schedule phy info update */ 5780 if (!test_bit(__IGC_DOWN, &adapter->state)) 5781 mod_timer(&adapter->phy_info_timer, 5782 round_jiffies(jiffies + 2 * HZ)); 5783 } 5784 } else { 5785 if (netif_carrier_ok(netdev)) { 5786 adapter->link_speed = 0; 5787 adapter->link_duplex = 0; 5788 5789 /* Links status message must follow this format */ 5790 netdev_info(netdev, "NIC Link is Down\n"); 5791 netif_carrier_off(netdev); 5792 5793 /* link state has changed, schedule phy info update */ 5794 if (!test_bit(__IGC_DOWN, &adapter->state)) 5795 mod_timer(&adapter->phy_info_timer, 5796 round_jiffies(jiffies + 2 * HZ)); 5797 5798 pm_schedule_suspend(netdev->dev.parent, 5799 MSEC_PER_SEC * 5); 5800 } 5801 } 5802 5803 spin_lock(&adapter->stats64_lock); 5804 igc_update_stats(adapter); 5805 spin_unlock(&adapter->stats64_lock); 5806 5807 for (i = 0; i < adapter->num_tx_queues; i++) { 5808 struct igc_ring *tx_ring = adapter->tx_ring[i]; 5809 5810 if (!netif_carrier_ok(netdev)) { 5811 /* We've lost link, so the controller stops DMA, 5812 * but we've got queued Tx work that's never going 5813 * to get done, so reset controller to flush Tx. 5814 * (Do the reset outside of interrupt context). 5815 */ 5816 if (igc_desc_unused(tx_ring) + 1 < tx_ring->count) { 5817 adapter->tx_timeout_count++; 5818 schedule_work(&adapter->reset_task); 5819 /* return immediately since reset is imminent */ 5820 return; 5821 } 5822 } 5823 5824 /* Force detection of hung controller every watchdog period */ 5825 set_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5826 } 5827 5828 /* Cause software interrupt to ensure Rx ring is cleaned */ 5829 if (adapter->flags & IGC_FLAG_HAS_MSIX) { 5830 u32 eics = 0; 5831 5832 for (i = 0; i < adapter->num_q_vectors; i++) { 5833 struct igc_q_vector *q_vector = adapter->q_vector[i]; 5834 struct igc_ring *rx_ring; 5835 5836 if (!q_vector->rx.ring) 5837 continue; 5838 5839 rx_ring = adapter->rx_ring[q_vector->rx.ring->queue_index]; 5840 5841 if (test_bit(IGC_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags)) { 5842 eics |= q_vector->eims_value; 5843 clear_bit(IGC_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 5844 } 5845 } 5846 if (eics) 5847 wr32(IGC_EICS, eics); 5848 } else { 5849 struct igc_ring *rx_ring = adapter->rx_ring[0]; 5850 5851 if (test_bit(IGC_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags)) { 5852 clear_bit(IGC_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 5853 wr32(IGC_ICS, IGC_ICS_RXDMT0); 5854 } 5855 } 5856 5857 igc_ptp_tx_hang(adapter); 5858 5859 /* Reset the timer */ 5860 if (!test_bit(__IGC_DOWN, &adapter->state)) { 5861 if (adapter->flags & IGC_FLAG_NEED_LINK_UPDATE) 5862 mod_timer(&adapter->watchdog_timer, 5863 round_jiffies(jiffies + HZ)); 5864 else 5865 mod_timer(&adapter->watchdog_timer, 5866 round_jiffies(jiffies + 2 * HZ)); 5867 } 5868 } 5869 5870 /** 5871 * igc_intr_msi - Interrupt Handler 5872 * @irq: interrupt number 5873 * @data: pointer to a network interface device structure 5874 */ 5875 static irqreturn_t igc_intr_msi(int irq, void *data) 5876 { 5877 struct igc_adapter *adapter = data; 5878 struct igc_q_vector *q_vector = adapter->q_vector[0]; 5879 struct igc_hw *hw = &adapter->hw; 5880 /* read ICR disables interrupts using IAM */ 5881 u32 icr = rd32(IGC_ICR); 5882 5883 igc_write_itr(q_vector); 5884 5885 if (icr & IGC_ICR_DRSTA) 5886 schedule_work(&adapter->reset_task); 5887 5888 if (icr & IGC_ICR_DOUTSYNC) { 5889 /* HW is reporting DMA is out of sync */ 5890 adapter->stats.doosync++; 5891 } 5892 5893 if (icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) { 5894 hw->mac.get_link_status = true; 5895 if (!test_bit(__IGC_DOWN, &adapter->state)) 5896 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5897 } 5898 5899 if (icr & IGC_ICR_TS) 5900 igc_tsync_interrupt(adapter); 5901 5902 napi_schedule(&q_vector->napi); 5903 5904 return IRQ_HANDLED; 5905 } 5906 5907 /** 5908 * igc_intr - Legacy Interrupt Handler 5909 * @irq: interrupt number 5910 * @data: pointer to a network interface device structure 5911 */ 5912 static irqreturn_t igc_intr(int irq, void *data) 5913 { 5914 struct igc_adapter *adapter = data; 5915 struct igc_q_vector *q_vector = adapter->q_vector[0]; 5916 struct igc_hw *hw = &adapter->hw; 5917 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 5918 * need for the IMC write 5919 */ 5920 u32 icr = rd32(IGC_ICR); 5921 5922 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 5923 * not set, then the adapter didn't send an interrupt 5924 */ 5925 if (!(icr & IGC_ICR_INT_ASSERTED)) 5926 return IRQ_NONE; 5927 5928 igc_write_itr(q_vector); 5929 5930 if (icr & IGC_ICR_DRSTA) 5931 schedule_work(&adapter->reset_task); 5932 5933 if (icr & IGC_ICR_DOUTSYNC) { 5934 /* HW is reporting DMA is out of sync */ 5935 adapter->stats.doosync++; 5936 } 5937 5938 if (icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) { 5939 hw->mac.get_link_status = true; 5940 /* guard against interrupt when we're going down */ 5941 if (!test_bit(__IGC_DOWN, &adapter->state)) 5942 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5943 } 5944 5945 if (icr & IGC_ICR_TS) 5946 igc_tsync_interrupt(adapter); 5947 5948 napi_schedule(&q_vector->napi); 5949 5950 return IRQ_HANDLED; 5951 } 5952 5953 static void igc_free_irq(struct igc_adapter *adapter) 5954 { 5955 if (adapter->msix_entries) { 5956 int vector = 0, i; 5957 5958 free_irq(adapter->msix_entries[vector++].vector, adapter); 5959 5960 for (i = 0; i < adapter->num_q_vectors; i++) 5961 free_irq(adapter->msix_entries[vector++].vector, 5962 adapter->q_vector[i]); 5963 } else { 5964 free_irq(adapter->pdev->irq, adapter); 5965 } 5966 } 5967 5968 /** 5969 * igc_request_irq - initialize interrupts 5970 * @adapter: Pointer to adapter structure 5971 * 5972 * Attempts to configure interrupts using the best available 5973 * capabilities of the hardware and kernel. 5974 */ 5975 static int igc_request_irq(struct igc_adapter *adapter) 5976 { 5977 struct net_device *netdev = adapter->netdev; 5978 struct pci_dev *pdev = adapter->pdev; 5979 int err = 0; 5980 5981 if (adapter->flags & IGC_FLAG_HAS_MSIX) { 5982 err = igc_request_msix(adapter); 5983 if (!err) 5984 goto request_done; 5985 /* fall back to MSI */ 5986 igc_free_all_tx_resources(adapter); 5987 igc_free_all_rx_resources(adapter); 5988 5989 igc_clear_interrupt_scheme(adapter); 5990 err = igc_init_interrupt_scheme(adapter, false); 5991 if (err) 5992 goto request_done; 5993 igc_setup_all_tx_resources(adapter); 5994 igc_setup_all_rx_resources(adapter); 5995 igc_configure(adapter); 5996 } 5997 5998 igc_assign_vector(adapter->q_vector[0], 0); 5999 6000 if (adapter->flags & IGC_FLAG_HAS_MSI) { 6001 err = request_irq(pdev->irq, &igc_intr_msi, 0, 6002 netdev->name, adapter); 6003 if (!err) 6004 goto request_done; 6005 6006 /* fall back to legacy interrupts */ 6007 igc_reset_interrupt_capability(adapter); 6008 adapter->flags &= ~IGC_FLAG_HAS_MSI; 6009 } 6010 6011 err = request_irq(pdev->irq, &igc_intr, IRQF_SHARED, 6012 netdev->name, adapter); 6013 6014 if (err) 6015 netdev_err(netdev, "Error %d getting interrupt\n", err); 6016 6017 request_done: 6018 return err; 6019 } 6020 6021 /** 6022 * __igc_open - Called when a network interface is made active 6023 * @netdev: network interface device structure 6024 * @resuming: boolean indicating if the device is resuming 6025 * 6026 * Returns 0 on success, negative value on failure 6027 * 6028 * The open entry point is called when a network interface is made 6029 * active by the system (IFF_UP). At this point all resources needed 6030 * for transmit and receive operations are allocated, the interrupt 6031 * handler is registered with the OS, the watchdog timer is started, 6032 * and the stack is notified that the interface is ready. 6033 */ 6034 static int __igc_open(struct net_device *netdev, bool resuming) 6035 { 6036 struct igc_adapter *adapter = netdev_priv(netdev); 6037 struct pci_dev *pdev = adapter->pdev; 6038 struct igc_hw *hw = &adapter->hw; 6039 struct napi_struct *napi; 6040 int err = 0; 6041 int i = 0; 6042 6043 /* disallow open during test */ 6044 6045 if (test_bit(__IGC_TESTING, &adapter->state)) { 6046 WARN_ON(resuming); 6047 return -EBUSY; 6048 } 6049 6050 if (!resuming) 6051 pm_runtime_get_sync(&pdev->dev); 6052 6053 netif_carrier_off(netdev); 6054 6055 /* allocate transmit descriptors */ 6056 err = igc_setup_all_tx_resources(adapter); 6057 if (err) 6058 goto err_setup_tx; 6059 6060 /* allocate receive descriptors */ 6061 err = igc_setup_all_rx_resources(adapter); 6062 if (err) 6063 goto err_setup_rx; 6064 6065 igc_power_up_link(adapter); 6066 6067 igc_configure(adapter); 6068 6069 err = igc_request_irq(adapter); 6070 if (err) 6071 goto err_req_irq; 6072 6073 clear_bit(__IGC_DOWN, &adapter->state); 6074 6075 for (i = 0; i < adapter->num_q_vectors; i++) { 6076 napi = &adapter->q_vector[i]->napi; 6077 napi_enable(napi); 6078 igc_set_queue_napi(adapter, i, napi); 6079 } 6080 6081 /* Clear any pending interrupts. */ 6082 rd32(IGC_ICR); 6083 igc_irq_enable(adapter); 6084 6085 if (!resuming) 6086 pm_runtime_put(&pdev->dev); 6087 6088 netif_tx_start_all_queues(netdev); 6089 6090 /* start the watchdog. */ 6091 hw->mac.get_link_status = true; 6092 schedule_work(&adapter->watchdog_task); 6093 6094 return IGC_SUCCESS; 6095 6096 err_req_irq: 6097 igc_release_hw_control(adapter); 6098 igc_power_down_phy_copper_base(&adapter->hw); 6099 igc_free_all_rx_resources(adapter); 6100 err_setup_rx: 6101 igc_free_all_tx_resources(adapter); 6102 err_setup_tx: 6103 igc_reset(adapter); 6104 if (!resuming) 6105 pm_runtime_put(&pdev->dev); 6106 6107 return err; 6108 } 6109 6110 int igc_open(struct net_device *netdev) 6111 { 6112 struct igc_adapter *adapter = netdev_priv(netdev); 6113 int err; 6114 6115 /* Notify the stack of the actual queue counts. */ 6116 err = netif_set_real_num_queues(netdev, adapter->num_tx_queues, 6117 adapter->num_rx_queues); 6118 if (err) { 6119 netdev_err(netdev, "error setting real queue count\n"); 6120 return err; 6121 } 6122 6123 return __igc_open(netdev, false); 6124 } 6125 6126 /** 6127 * __igc_close - Disables a network interface 6128 * @netdev: network interface device structure 6129 * @suspending: boolean indicating the device is suspending 6130 * 6131 * Returns 0, this is not allowed to fail 6132 * 6133 * The close entry point is called when an interface is de-activated 6134 * by the OS. The hardware is still under the driver's control, but 6135 * needs to be disabled. A global MAC reset is issued to stop the 6136 * hardware, and all transmit and receive resources are freed. 6137 */ 6138 static int __igc_close(struct net_device *netdev, bool suspending) 6139 { 6140 struct igc_adapter *adapter = netdev_priv(netdev); 6141 struct pci_dev *pdev = adapter->pdev; 6142 6143 WARN_ON(test_bit(__IGC_RESETTING, &adapter->state)); 6144 6145 if (!suspending) 6146 pm_runtime_get_sync(&pdev->dev); 6147 6148 igc_down(adapter); 6149 6150 igc_release_hw_control(adapter); 6151 6152 igc_free_irq(adapter); 6153 6154 igc_free_all_tx_resources(adapter); 6155 igc_free_all_rx_resources(adapter); 6156 6157 if (!suspending) 6158 pm_runtime_put_sync(&pdev->dev); 6159 6160 return 0; 6161 } 6162 6163 int igc_close(struct net_device *netdev) 6164 { 6165 if (netif_device_present(netdev) || netdev->dismantle) 6166 return __igc_close(netdev, false); 6167 return 0; 6168 } 6169 6170 /** 6171 * igc_ioctl - Access the hwtstamp interface 6172 * @netdev: network interface device structure 6173 * @ifr: interface request data 6174 * @cmd: ioctl command 6175 **/ 6176 static int igc_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6177 { 6178 switch (cmd) { 6179 case SIOCGHWTSTAMP: 6180 return igc_ptp_get_ts_config(netdev, ifr); 6181 case SIOCSHWTSTAMP: 6182 return igc_ptp_set_ts_config(netdev, ifr); 6183 default: 6184 return -EOPNOTSUPP; 6185 } 6186 } 6187 6188 static int igc_save_launchtime_params(struct igc_adapter *adapter, int queue, 6189 bool enable) 6190 { 6191 struct igc_ring *ring; 6192 6193 if (queue < 0 || queue >= adapter->num_tx_queues) 6194 return -EINVAL; 6195 6196 ring = adapter->tx_ring[queue]; 6197 ring->launchtime_enable = enable; 6198 6199 return 0; 6200 } 6201 6202 static bool is_base_time_past(ktime_t base_time, const struct timespec64 *now) 6203 { 6204 struct timespec64 b; 6205 6206 b = ktime_to_timespec64(base_time); 6207 6208 return timespec64_compare(now, &b) > 0; 6209 } 6210 6211 static bool validate_schedule(struct igc_adapter *adapter, 6212 const struct tc_taprio_qopt_offload *qopt) 6213 { 6214 int queue_uses[IGC_MAX_TX_QUEUES] = { }; 6215 struct igc_hw *hw = &adapter->hw; 6216 struct timespec64 now; 6217 size_t n; 6218 6219 if (qopt->cycle_time_extension) 6220 return false; 6221 6222 igc_ptp_read(adapter, &now); 6223 6224 /* If we program the controller's BASET registers with a time 6225 * in the future, it will hold all the packets until that 6226 * time, causing a lot of TX Hangs, so to avoid that, we 6227 * reject schedules that would start in the future. 6228 * Note: Limitation above is no longer in i226. 6229 */ 6230 if (!is_base_time_past(qopt->base_time, &now) && 6231 igc_is_device_id_i225(hw)) 6232 return false; 6233 6234 for (n = 0; n < qopt->num_entries; n++) { 6235 const struct tc_taprio_sched_entry *e, *prev; 6236 int i; 6237 6238 prev = n ? &qopt->entries[n - 1] : NULL; 6239 e = &qopt->entries[n]; 6240 6241 /* i225 only supports "global" frame preemption 6242 * settings. 6243 */ 6244 if (e->command != TC_TAPRIO_CMD_SET_GATES) 6245 return false; 6246 6247 for (i = 0; i < adapter->num_tx_queues; i++) 6248 if (e->gate_mask & BIT(i)) { 6249 queue_uses[i]++; 6250 6251 /* There are limitations: A single queue cannot 6252 * be opened and closed multiple times per cycle 6253 * unless the gate stays open. Check for it. 6254 */ 6255 if (queue_uses[i] > 1 && 6256 !(prev->gate_mask & BIT(i))) 6257 return false; 6258 } 6259 } 6260 6261 return true; 6262 } 6263 6264 static int igc_tsn_enable_launchtime(struct igc_adapter *adapter, 6265 struct tc_etf_qopt_offload *qopt) 6266 { 6267 struct igc_hw *hw = &adapter->hw; 6268 int err; 6269 6270 if (hw->mac.type != igc_i225) 6271 return -EOPNOTSUPP; 6272 6273 err = igc_save_launchtime_params(adapter, qopt->queue, qopt->enable); 6274 if (err) 6275 return err; 6276 6277 return igc_tsn_offload_apply(adapter); 6278 } 6279 6280 static int igc_qbv_clear_schedule(struct igc_adapter *adapter) 6281 { 6282 unsigned long flags; 6283 int i; 6284 6285 adapter->base_time = 0; 6286 adapter->cycle_time = NSEC_PER_SEC; 6287 adapter->taprio_offload_enable = false; 6288 adapter->qbv_config_change_errors = 0; 6289 adapter->qbv_count = 0; 6290 6291 for (i = 0; i < adapter->num_tx_queues; i++) { 6292 struct igc_ring *ring = adapter->tx_ring[i]; 6293 6294 ring->start_time = 0; 6295 ring->end_time = NSEC_PER_SEC; 6296 ring->max_sdu = 0; 6297 } 6298 6299 spin_lock_irqsave(&adapter->qbv_tx_lock, flags); 6300 6301 adapter->qbv_transition = false; 6302 6303 for (i = 0; i < adapter->num_tx_queues; i++) { 6304 struct igc_ring *ring = adapter->tx_ring[i]; 6305 6306 ring->oper_gate_closed = false; 6307 ring->admin_gate_closed = false; 6308 } 6309 6310 spin_unlock_irqrestore(&adapter->qbv_tx_lock, flags); 6311 6312 return 0; 6313 } 6314 6315 static int igc_tsn_clear_schedule(struct igc_adapter *adapter) 6316 { 6317 igc_qbv_clear_schedule(adapter); 6318 6319 return 0; 6320 } 6321 6322 static void igc_taprio_stats(struct net_device *dev, 6323 struct tc_taprio_qopt_stats *stats) 6324 { 6325 /* When Strict_End is enabled, the tx_overruns counter 6326 * will always be zero. 6327 */ 6328 stats->tx_overruns = 0; 6329 } 6330 6331 static void igc_taprio_queue_stats(struct net_device *dev, 6332 struct tc_taprio_qopt_queue_stats *queue_stats) 6333 { 6334 struct tc_taprio_qopt_stats *stats = &queue_stats->stats; 6335 6336 /* When Strict_End is enabled, the tx_overruns counter 6337 * will always be zero. 6338 */ 6339 stats->tx_overruns = 0; 6340 } 6341 6342 static int igc_save_qbv_schedule(struct igc_adapter *adapter, 6343 struct tc_taprio_qopt_offload *qopt) 6344 { 6345 bool queue_configured[IGC_MAX_TX_QUEUES] = { }; 6346 struct igc_hw *hw = &adapter->hw; 6347 u32 start_time = 0, end_time = 0; 6348 struct timespec64 now; 6349 unsigned long flags; 6350 size_t n; 6351 int i; 6352 6353 if (qopt->base_time < 0) 6354 return -ERANGE; 6355 6356 if (igc_is_device_id_i225(hw) && adapter->taprio_offload_enable) 6357 return -EALREADY; 6358 6359 if (!validate_schedule(adapter, qopt)) 6360 return -EINVAL; 6361 6362 igc_ptp_read(adapter, &now); 6363 6364 if (igc_tsn_is_taprio_activated_by_user(adapter) && 6365 is_base_time_past(qopt->base_time, &now)) 6366 adapter->qbv_config_change_errors++; 6367 6368 adapter->cycle_time = qopt->cycle_time; 6369 adapter->base_time = qopt->base_time; 6370 adapter->taprio_offload_enable = true; 6371 6372 for (n = 0; n < qopt->num_entries; n++) { 6373 struct tc_taprio_sched_entry *e = &qopt->entries[n]; 6374 6375 end_time += e->interval; 6376 6377 /* If any of the conditions below are true, we need to manually 6378 * control the end time of the cycle. 6379 * 1. Qbv users can specify a cycle time that is not equal 6380 * to the total GCL intervals. Hence, recalculation is 6381 * necessary here to exclude the time interval that 6382 * exceeds the cycle time. 6383 * 2. According to IEEE Std. 802.1Q-2018 section 8.6.9.2, 6384 * once the end of the list is reached, it will switch 6385 * to the END_OF_CYCLE state and leave the gates in the 6386 * same state until the next cycle is started. 6387 */ 6388 if (end_time > adapter->cycle_time || 6389 n + 1 == qopt->num_entries) 6390 end_time = adapter->cycle_time; 6391 6392 for (i = 0; i < adapter->num_tx_queues; i++) { 6393 struct igc_ring *ring = adapter->tx_ring[i]; 6394 6395 if (!(e->gate_mask & BIT(i))) 6396 continue; 6397 6398 /* Check whether a queue stays open for more than one 6399 * entry. If so, keep the start and advance the end 6400 * time. 6401 */ 6402 if (!queue_configured[i]) 6403 ring->start_time = start_time; 6404 ring->end_time = end_time; 6405 6406 if (ring->start_time >= adapter->cycle_time) 6407 queue_configured[i] = false; 6408 else 6409 queue_configured[i] = true; 6410 } 6411 6412 start_time += e->interval; 6413 } 6414 6415 spin_lock_irqsave(&adapter->qbv_tx_lock, flags); 6416 6417 /* Check whether a queue gets configured. 6418 * If not, set the start and end time to be end time. 6419 */ 6420 for (i = 0; i < adapter->num_tx_queues; i++) { 6421 struct igc_ring *ring = adapter->tx_ring[i]; 6422 6423 if (!is_base_time_past(qopt->base_time, &now)) { 6424 ring->admin_gate_closed = false; 6425 } else { 6426 ring->oper_gate_closed = false; 6427 ring->admin_gate_closed = false; 6428 } 6429 6430 if (!queue_configured[i]) { 6431 if (!is_base_time_past(qopt->base_time, &now)) 6432 ring->admin_gate_closed = true; 6433 else 6434 ring->oper_gate_closed = true; 6435 6436 ring->start_time = end_time; 6437 ring->end_time = end_time; 6438 } 6439 } 6440 6441 spin_unlock_irqrestore(&adapter->qbv_tx_lock, flags); 6442 6443 for (i = 0; i < adapter->num_tx_queues; i++) { 6444 struct igc_ring *ring = adapter->tx_ring[i]; 6445 struct net_device *dev = adapter->netdev; 6446 6447 if (qopt->max_sdu[i]) 6448 ring->max_sdu = qopt->max_sdu[i] + dev->hard_header_len - ETH_TLEN; 6449 else 6450 ring->max_sdu = 0; 6451 } 6452 6453 return 0; 6454 } 6455 6456 static int igc_tsn_enable_qbv_scheduling(struct igc_adapter *adapter, 6457 struct tc_taprio_qopt_offload *qopt) 6458 { 6459 struct igc_hw *hw = &adapter->hw; 6460 int err; 6461 6462 if (hw->mac.type != igc_i225) 6463 return -EOPNOTSUPP; 6464 6465 switch (qopt->cmd) { 6466 case TAPRIO_CMD_REPLACE: 6467 err = igc_save_qbv_schedule(adapter, qopt); 6468 break; 6469 case TAPRIO_CMD_DESTROY: 6470 err = igc_tsn_clear_schedule(adapter); 6471 break; 6472 case TAPRIO_CMD_STATS: 6473 igc_taprio_stats(adapter->netdev, &qopt->stats); 6474 return 0; 6475 case TAPRIO_CMD_QUEUE_STATS: 6476 igc_taprio_queue_stats(adapter->netdev, &qopt->queue_stats); 6477 return 0; 6478 default: 6479 return -EOPNOTSUPP; 6480 } 6481 6482 if (err) 6483 return err; 6484 6485 return igc_tsn_offload_apply(adapter); 6486 } 6487 6488 static int igc_save_cbs_params(struct igc_adapter *adapter, int queue, 6489 bool enable, int idleslope, int sendslope, 6490 int hicredit, int locredit) 6491 { 6492 bool cbs_status[IGC_MAX_SR_QUEUES] = { false }; 6493 struct net_device *netdev = adapter->netdev; 6494 struct igc_ring *ring; 6495 int i; 6496 6497 /* i225 has two sets of credit-based shaper logic. 6498 * Supporting it only on the top two priority queues 6499 */ 6500 if (queue < 0 || queue > 1) 6501 return -EINVAL; 6502 6503 ring = adapter->tx_ring[queue]; 6504 6505 for (i = 0; i < IGC_MAX_SR_QUEUES; i++) 6506 if (adapter->tx_ring[i]) 6507 cbs_status[i] = adapter->tx_ring[i]->cbs_enable; 6508 6509 /* CBS should be enabled on the highest priority queue first in order 6510 * for the CBS algorithm to operate as intended. 6511 */ 6512 if (enable) { 6513 if (queue == 1 && !cbs_status[0]) { 6514 netdev_err(netdev, 6515 "Enabling CBS on queue1 before queue0\n"); 6516 return -EINVAL; 6517 } 6518 } else { 6519 if (queue == 0 && cbs_status[1]) { 6520 netdev_err(netdev, 6521 "Disabling CBS on queue0 before queue1\n"); 6522 return -EINVAL; 6523 } 6524 } 6525 6526 ring->cbs_enable = enable; 6527 ring->idleslope = idleslope; 6528 ring->sendslope = sendslope; 6529 ring->hicredit = hicredit; 6530 ring->locredit = locredit; 6531 6532 return 0; 6533 } 6534 6535 static int igc_tsn_enable_cbs(struct igc_adapter *adapter, 6536 struct tc_cbs_qopt_offload *qopt) 6537 { 6538 struct igc_hw *hw = &adapter->hw; 6539 int err; 6540 6541 if (hw->mac.type != igc_i225) 6542 return -EOPNOTSUPP; 6543 6544 if (qopt->queue < 0 || qopt->queue > 1) 6545 return -EINVAL; 6546 6547 err = igc_save_cbs_params(adapter, qopt->queue, qopt->enable, 6548 qopt->idleslope, qopt->sendslope, 6549 qopt->hicredit, qopt->locredit); 6550 if (err) 6551 return err; 6552 6553 return igc_tsn_offload_apply(adapter); 6554 } 6555 6556 static int igc_tc_query_caps(struct igc_adapter *adapter, 6557 struct tc_query_caps_base *base) 6558 { 6559 struct igc_hw *hw = &adapter->hw; 6560 6561 switch (base->type) { 6562 case TC_SETUP_QDISC_MQPRIO: { 6563 struct tc_mqprio_caps *caps = base->caps; 6564 6565 caps->validate_queue_counts = true; 6566 6567 return 0; 6568 } 6569 case TC_SETUP_QDISC_TAPRIO: { 6570 struct tc_taprio_caps *caps = base->caps; 6571 6572 caps->broken_mqprio = true; 6573 6574 if (hw->mac.type == igc_i225) { 6575 caps->supports_queue_max_sdu = true; 6576 caps->gate_mask_per_txq = true; 6577 } 6578 6579 return 0; 6580 } 6581 default: 6582 return -EOPNOTSUPP; 6583 } 6584 } 6585 6586 static void igc_save_mqprio_params(struct igc_adapter *adapter, u8 num_tc, 6587 u16 *offset) 6588 { 6589 int i; 6590 6591 adapter->strict_priority_enable = true; 6592 adapter->num_tc = num_tc; 6593 6594 for (i = 0; i < num_tc; i++) 6595 adapter->queue_per_tc[i] = offset[i]; 6596 } 6597 6598 static int igc_tsn_enable_mqprio(struct igc_adapter *adapter, 6599 struct tc_mqprio_qopt_offload *mqprio) 6600 { 6601 struct igc_hw *hw = &adapter->hw; 6602 int i; 6603 6604 if (hw->mac.type != igc_i225) 6605 return -EOPNOTSUPP; 6606 6607 if (!mqprio->qopt.num_tc) { 6608 adapter->strict_priority_enable = false; 6609 goto apply; 6610 } 6611 6612 /* There are as many TCs as Tx queues. */ 6613 if (mqprio->qopt.num_tc != adapter->num_tx_queues) { 6614 NL_SET_ERR_MSG_FMT_MOD(mqprio->extack, 6615 "Only %d traffic classes supported", 6616 adapter->num_tx_queues); 6617 return -EOPNOTSUPP; 6618 } 6619 6620 /* Only one queue per TC is supported. */ 6621 for (i = 0; i < mqprio->qopt.num_tc; i++) { 6622 if (mqprio->qopt.count[i] != 1) { 6623 NL_SET_ERR_MSG_MOD(mqprio->extack, 6624 "Only one queue per TC supported"); 6625 return -EOPNOTSUPP; 6626 } 6627 } 6628 6629 /* Preemption is not supported yet. */ 6630 if (mqprio->preemptible_tcs) { 6631 NL_SET_ERR_MSG_MOD(mqprio->extack, 6632 "Preemption is not supported yet"); 6633 return -EOPNOTSUPP; 6634 } 6635 6636 igc_save_mqprio_params(adapter, mqprio->qopt.num_tc, 6637 mqprio->qopt.offset); 6638 6639 mqprio->qopt.hw = TC_MQPRIO_HW_OFFLOAD_TCS; 6640 6641 apply: 6642 return igc_tsn_offload_apply(adapter); 6643 } 6644 6645 static int igc_setup_tc(struct net_device *dev, enum tc_setup_type type, 6646 void *type_data) 6647 { 6648 struct igc_adapter *adapter = netdev_priv(dev); 6649 6650 adapter->tc_setup_type = type; 6651 6652 switch (type) { 6653 case TC_QUERY_CAPS: 6654 return igc_tc_query_caps(adapter, type_data); 6655 case TC_SETUP_QDISC_TAPRIO: 6656 return igc_tsn_enable_qbv_scheduling(adapter, type_data); 6657 6658 case TC_SETUP_QDISC_ETF: 6659 return igc_tsn_enable_launchtime(adapter, type_data); 6660 6661 case TC_SETUP_QDISC_CBS: 6662 return igc_tsn_enable_cbs(adapter, type_data); 6663 6664 case TC_SETUP_QDISC_MQPRIO: 6665 return igc_tsn_enable_mqprio(adapter, type_data); 6666 6667 default: 6668 return -EOPNOTSUPP; 6669 } 6670 } 6671 6672 static int igc_bpf(struct net_device *dev, struct netdev_bpf *bpf) 6673 { 6674 struct igc_adapter *adapter = netdev_priv(dev); 6675 6676 switch (bpf->command) { 6677 case XDP_SETUP_PROG: 6678 return igc_xdp_set_prog(adapter, bpf->prog, bpf->extack); 6679 case XDP_SETUP_XSK_POOL: 6680 return igc_xdp_setup_pool(adapter, bpf->xsk.pool, 6681 bpf->xsk.queue_id); 6682 default: 6683 return -EOPNOTSUPP; 6684 } 6685 } 6686 6687 static int igc_xdp_xmit(struct net_device *dev, int num_frames, 6688 struct xdp_frame **frames, u32 flags) 6689 { 6690 struct igc_adapter *adapter = netdev_priv(dev); 6691 int cpu = smp_processor_id(); 6692 struct netdev_queue *nq; 6693 struct igc_ring *ring; 6694 int i, nxmit; 6695 6696 if (unlikely(!netif_carrier_ok(dev))) 6697 return -ENETDOWN; 6698 6699 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 6700 return -EINVAL; 6701 6702 ring = igc_xdp_get_tx_ring(adapter, cpu); 6703 nq = txring_txq(ring); 6704 6705 __netif_tx_lock(nq, cpu); 6706 6707 /* Avoid transmit queue timeout since we share it with the slow path */ 6708 txq_trans_cond_update(nq); 6709 6710 nxmit = 0; 6711 for (i = 0; i < num_frames; i++) { 6712 int err; 6713 struct xdp_frame *xdpf = frames[i]; 6714 6715 err = igc_xdp_init_tx_descriptor(ring, xdpf); 6716 if (err) 6717 break; 6718 nxmit++; 6719 } 6720 6721 if (flags & XDP_XMIT_FLUSH) 6722 igc_flush_tx_descriptors(ring); 6723 6724 __netif_tx_unlock(nq); 6725 6726 return nxmit; 6727 } 6728 6729 static void igc_trigger_rxtxq_interrupt(struct igc_adapter *adapter, 6730 struct igc_q_vector *q_vector) 6731 { 6732 struct igc_hw *hw = &adapter->hw; 6733 u32 eics = 0; 6734 6735 eics |= q_vector->eims_value; 6736 wr32(IGC_EICS, eics); 6737 } 6738 6739 int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags) 6740 { 6741 struct igc_adapter *adapter = netdev_priv(dev); 6742 struct igc_q_vector *q_vector; 6743 struct igc_ring *ring; 6744 6745 if (test_bit(__IGC_DOWN, &adapter->state)) 6746 return -ENETDOWN; 6747 6748 if (!igc_xdp_is_enabled(adapter)) 6749 return -ENXIO; 6750 6751 if (queue_id >= adapter->num_rx_queues) 6752 return -EINVAL; 6753 6754 ring = adapter->rx_ring[queue_id]; 6755 6756 if (!ring->xsk_pool) 6757 return -ENXIO; 6758 6759 q_vector = adapter->q_vector[queue_id]; 6760 if (!napi_if_scheduled_mark_missed(&q_vector->napi)) 6761 igc_trigger_rxtxq_interrupt(adapter, q_vector); 6762 6763 return 0; 6764 } 6765 6766 static ktime_t igc_get_tstamp(struct net_device *dev, 6767 const struct skb_shared_hwtstamps *hwtstamps, 6768 bool cycles) 6769 { 6770 struct igc_adapter *adapter = netdev_priv(dev); 6771 struct igc_inline_rx_tstamps *tstamp; 6772 ktime_t timestamp; 6773 6774 tstamp = hwtstamps->netdev_data; 6775 6776 if (cycles) 6777 timestamp = igc_ptp_rx_pktstamp(adapter, tstamp->timer1); 6778 else 6779 timestamp = igc_ptp_rx_pktstamp(adapter, tstamp->timer0); 6780 6781 return timestamp; 6782 } 6783 6784 static const struct net_device_ops igc_netdev_ops = { 6785 .ndo_open = igc_open, 6786 .ndo_stop = igc_close, 6787 .ndo_start_xmit = igc_xmit_frame, 6788 .ndo_set_rx_mode = igc_set_rx_mode, 6789 .ndo_set_mac_address = igc_set_mac, 6790 .ndo_change_mtu = igc_change_mtu, 6791 .ndo_tx_timeout = igc_tx_timeout, 6792 .ndo_get_stats64 = igc_get_stats64, 6793 .ndo_fix_features = igc_fix_features, 6794 .ndo_set_features = igc_set_features, 6795 .ndo_features_check = igc_features_check, 6796 .ndo_eth_ioctl = igc_ioctl, 6797 .ndo_setup_tc = igc_setup_tc, 6798 .ndo_bpf = igc_bpf, 6799 .ndo_xdp_xmit = igc_xdp_xmit, 6800 .ndo_xsk_wakeup = igc_xsk_wakeup, 6801 .ndo_get_tstamp = igc_get_tstamp, 6802 }; 6803 6804 u32 igc_rd32(struct igc_hw *hw, u32 reg) 6805 { 6806 struct igc_adapter *igc = container_of(hw, struct igc_adapter, hw); 6807 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 6808 u32 value = 0; 6809 6810 if (IGC_REMOVED(hw_addr)) 6811 return ~value; 6812 6813 value = readl(&hw_addr[reg]); 6814 6815 /* reads should not return all F's */ 6816 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 6817 struct net_device *netdev = igc->netdev; 6818 6819 hw->hw_addr = NULL; 6820 netif_device_detach(netdev); 6821 netdev_err(netdev, "PCIe link lost, device now detached\n"); 6822 WARN(pci_device_is_present(igc->pdev), 6823 "igc: Failed to read reg 0x%x!\n", reg); 6824 } 6825 6826 return value; 6827 } 6828 6829 /* Mapping HW RSS Type to enum xdp_rss_hash_type */ 6830 static enum xdp_rss_hash_type igc_xdp_rss_type[IGC_RSS_TYPE_MAX_TABLE] = { 6831 [IGC_RSS_TYPE_NO_HASH] = XDP_RSS_TYPE_L2, 6832 [IGC_RSS_TYPE_HASH_TCP_IPV4] = XDP_RSS_TYPE_L4_IPV4_TCP, 6833 [IGC_RSS_TYPE_HASH_IPV4] = XDP_RSS_TYPE_L3_IPV4, 6834 [IGC_RSS_TYPE_HASH_TCP_IPV6] = XDP_RSS_TYPE_L4_IPV6_TCP, 6835 [IGC_RSS_TYPE_HASH_IPV6_EX] = XDP_RSS_TYPE_L3_IPV6_EX, 6836 [IGC_RSS_TYPE_HASH_IPV6] = XDP_RSS_TYPE_L3_IPV6, 6837 [IGC_RSS_TYPE_HASH_TCP_IPV6_EX] = XDP_RSS_TYPE_L4_IPV6_TCP_EX, 6838 [IGC_RSS_TYPE_HASH_UDP_IPV4] = XDP_RSS_TYPE_L4_IPV4_UDP, 6839 [IGC_RSS_TYPE_HASH_UDP_IPV6] = XDP_RSS_TYPE_L4_IPV6_UDP, 6840 [IGC_RSS_TYPE_HASH_UDP_IPV6_EX] = XDP_RSS_TYPE_L4_IPV6_UDP_EX, 6841 [10] = XDP_RSS_TYPE_NONE, /* RSS Type above 9 "Reserved" by HW */ 6842 [11] = XDP_RSS_TYPE_NONE, /* keep array sized for SW bit-mask */ 6843 [12] = XDP_RSS_TYPE_NONE, /* to handle future HW revisons */ 6844 [13] = XDP_RSS_TYPE_NONE, 6845 [14] = XDP_RSS_TYPE_NONE, 6846 [15] = XDP_RSS_TYPE_NONE, 6847 }; 6848 6849 static int igc_xdp_rx_hash(const struct xdp_md *_ctx, u32 *hash, 6850 enum xdp_rss_hash_type *rss_type) 6851 { 6852 const struct igc_xdp_buff *ctx = (void *)_ctx; 6853 6854 if (!(ctx->xdp.rxq->dev->features & NETIF_F_RXHASH)) 6855 return -ENODATA; 6856 6857 *hash = le32_to_cpu(ctx->rx_desc->wb.lower.hi_dword.rss); 6858 *rss_type = igc_xdp_rss_type[igc_rss_type(ctx->rx_desc)]; 6859 6860 return 0; 6861 } 6862 6863 static int igc_xdp_rx_timestamp(const struct xdp_md *_ctx, u64 *timestamp) 6864 { 6865 const struct igc_xdp_buff *ctx = (void *)_ctx; 6866 struct igc_adapter *adapter = netdev_priv(ctx->xdp.rxq->dev); 6867 struct igc_inline_rx_tstamps *tstamp = ctx->rx_ts; 6868 6869 if (igc_test_staterr(ctx->rx_desc, IGC_RXDADV_STAT_TSIP)) { 6870 *timestamp = igc_ptp_rx_pktstamp(adapter, tstamp->timer0); 6871 6872 return 0; 6873 } 6874 6875 return -ENODATA; 6876 } 6877 6878 static const struct xdp_metadata_ops igc_xdp_metadata_ops = { 6879 .xmo_rx_hash = igc_xdp_rx_hash, 6880 .xmo_rx_timestamp = igc_xdp_rx_timestamp, 6881 }; 6882 6883 static enum hrtimer_restart igc_qbv_scheduling_timer(struct hrtimer *timer) 6884 { 6885 struct igc_adapter *adapter = container_of(timer, struct igc_adapter, 6886 hrtimer); 6887 unsigned long flags; 6888 unsigned int i; 6889 6890 spin_lock_irqsave(&adapter->qbv_tx_lock, flags); 6891 6892 adapter->qbv_transition = true; 6893 for (i = 0; i < adapter->num_tx_queues; i++) { 6894 struct igc_ring *tx_ring = adapter->tx_ring[i]; 6895 6896 if (tx_ring->admin_gate_closed) { 6897 tx_ring->admin_gate_closed = false; 6898 tx_ring->oper_gate_closed = true; 6899 } else { 6900 tx_ring->oper_gate_closed = false; 6901 } 6902 } 6903 adapter->qbv_transition = false; 6904 6905 spin_unlock_irqrestore(&adapter->qbv_tx_lock, flags); 6906 6907 return HRTIMER_NORESTART; 6908 } 6909 6910 /** 6911 * igc_probe - Device Initialization Routine 6912 * @pdev: PCI device information struct 6913 * @ent: entry in igc_pci_tbl 6914 * 6915 * Returns 0 on success, negative on failure 6916 * 6917 * igc_probe initializes an adapter identified by a pci_dev structure. 6918 * The OS initialization, configuring the adapter private structure, 6919 * and a hardware reset occur. 6920 */ 6921 static int igc_probe(struct pci_dev *pdev, 6922 const struct pci_device_id *ent) 6923 { 6924 struct igc_adapter *adapter; 6925 struct net_device *netdev; 6926 struct igc_hw *hw; 6927 const struct igc_info *ei = igc_info_tbl[ent->driver_data]; 6928 int err; 6929 6930 err = pci_enable_device_mem(pdev); 6931 if (err) 6932 return err; 6933 6934 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 6935 if (err) { 6936 dev_err(&pdev->dev, 6937 "No usable DMA configuration, aborting\n"); 6938 goto err_dma; 6939 } 6940 6941 err = pci_request_mem_regions(pdev, igc_driver_name); 6942 if (err) 6943 goto err_pci_reg; 6944 6945 err = pci_enable_ptm(pdev, NULL); 6946 if (err < 0) 6947 dev_info(&pdev->dev, "PCIe PTM not supported by PCIe bus/controller\n"); 6948 6949 pci_set_master(pdev); 6950 6951 err = -ENOMEM; 6952 netdev = alloc_etherdev_mq(sizeof(struct igc_adapter), 6953 IGC_MAX_TX_QUEUES); 6954 6955 if (!netdev) 6956 goto err_alloc_etherdev; 6957 6958 SET_NETDEV_DEV(netdev, &pdev->dev); 6959 6960 pci_set_drvdata(pdev, netdev); 6961 adapter = netdev_priv(netdev); 6962 adapter->netdev = netdev; 6963 adapter->pdev = pdev; 6964 hw = &adapter->hw; 6965 hw->back = adapter; 6966 adapter->port_num = hw->bus.func; 6967 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 6968 6969 err = pci_save_state(pdev); 6970 if (err) 6971 goto err_ioremap; 6972 6973 err = -EIO; 6974 adapter->io_addr = ioremap(pci_resource_start(pdev, 0), 6975 pci_resource_len(pdev, 0)); 6976 if (!adapter->io_addr) 6977 goto err_ioremap; 6978 6979 /* hw->hw_addr can be zeroed, so use adapter->io_addr for unmap */ 6980 hw->hw_addr = adapter->io_addr; 6981 6982 netdev->netdev_ops = &igc_netdev_ops; 6983 netdev->xdp_metadata_ops = &igc_xdp_metadata_ops; 6984 netdev->xsk_tx_metadata_ops = &igc_xsk_tx_metadata_ops; 6985 igc_ethtool_set_ops(netdev); 6986 netdev->watchdog_timeo = 5 * HZ; 6987 6988 netdev->mem_start = pci_resource_start(pdev, 0); 6989 netdev->mem_end = pci_resource_end(pdev, 0); 6990 6991 /* PCI config space info */ 6992 hw->vendor_id = pdev->vendor; 6993 hw->device_id = pdev->device; 6994 hw->revision_id = pdev->revision; 6995 hw->subsystem_vendor_id = pdev->subsystem_vendor; 6996 hw->subsystem_device_id = pdev->subsystem_device; 6997 6998 /* Copy the default MAC and PHY function pointers */ 6999 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 7000 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 7001 7002 /* Initialize skew-specific constants */ 7003 err = ei->get_invariants(hw); 7004 if (err) 7005 goto err_sw_init; 7006 7007 /* Add supported features to the features list*/ 7008 netdev->features |= NETIF_F_SG; 7009 netdev->features |= NETIF_F_TSO; 7010 netdev->features |= NETIF_F_TSO6; 7011 netdev->features |= NETIF_F_TSO_ECN; 7012 netdev->features |= NETIF_F_RXHASH; 7013 netdev->features |= NETIF_F_RXCSUM; 7014 netdev->features |= NETIF_F_HW_CSUM; 7015 netdev->features |= NETIF_F_SCTP_CRC; 7016 netdev->features |= NETIF_F_HW_TC; 7017 7018 #define IGC_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 7019 NETIF_F_GSO_GRE_CSUM | \ 7020 NETIF_F_GSO_IPXIP4 | \ 7021 NETIF_F_GSO_IPXIP6 | \ 7022 NETIF_F_GSO_UDP_TUNNEL | \ 7023 NETIF_F_GSO_UDP_TUNNEL_CSUM) 7024 7025 netdev->gso_partial_features = IGC_GSO_PARTIAL_FEATURES; 7026 netdev->features |= NETIF_F_GSO_PARTIAL | IGC_GSO_PARTIAL_FEATURES; 7027 7028 /* setup the private structure */ 7029 err = igc_sw_init(adapter); 7030 if (err) 7031 goto err_sw_init; 7032 7033 /* copy netdev features into list of user selectable features */ 7034 netdev->hw_features |= NETIF_F_NTUPLE; 7035 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 7036 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 7037 netdev->hw_features |= netdev->features; 7038 7039 netdev->features |= NETIF_F_HIGHDMA; 7040 7041 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 7042 netdev->mpls_features |= NETIF_F_HW_CSUM; 7043 netdev->hw_enc_features |= netdev->vlan_features; 7044 7045 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | 7046 NETDEV_XDP_ACT_XSK_ZEROCOPY; 7047 7048 /* MTU range: 68 - 9216 */ 7049 netdev->min_mtu = ETH_MIN_MTU; 7050 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 7051 7052 /* before reading the NVM, reset the controller to put the device in a 7053 * known good starting state 7054 */ 7055 hw->mac.ops.reset_hw(hw); 7056 7057 if (igc_get_flash_presence_i225(hw)) { 7058 if (hw->nvm.ops.validate(hw) < 0) { 7059 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 7060 err = -EIO; 7061 goto err_eeprom; 7062 } 7063 } 7064 7065 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 7066 /* copy the MAC address out of the NVM */ 7067 if (hw->mac.ops.read_mac_addr(hw)) 7068 dev_err(&pdev->dev, "NVM Read Error\n"); 7069 } 7070 7071 eth_hw_addr_set(netdev, hw->mac.addr); 7072 7073 if (!is_valid_ether_addr(netdev->dev_addr)) { 7074 dev_err(&pdev->dev, "Invalid MAC Address\n"); 7075 err = -EIO; 7076 goto err_eeprom; 7077 } 7078 7079 /* configure RXPBSIZE and TXPBSIZE */ 7080 wr32(IGC_RXPBS, I225_RXPBSIZE_DEFAULT); 7081 wr32(IGC_TXPBS, I225_TXPBSIZE_DEFAULT); 7082 7083 timer_setup(&adapter->watchdog_timer, igc_watchdog, 0); 7084 timer_setup(&adapter->phy_info_timer, igc_update_phy_info, 0); 7085 7086 INIT_WORK(&adapter->reset_task, igc_reset_task); 7087 INIT_WORK(&adapter->watchdog_task, igc_watchdog_task); 7088 7089 hrtimer_init(&adapter->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 7090 adapter->hrtimer.function = &igc_qbv_scheduling_timer; 7091 7092 /* Initialize link properties that are user-changeable */ 7093 adapter->fc_autoneg = true; 7094 hw->phy.autoneg_advertised = 0xaf; 7095 7096 hw->fc.requested_mode = igc_fc_default; 7097 hw->fc.current_mode = igc_fc_default; 7098 7099 /* By default, support wake on port A */ 7100 adapter->flags |= IGC_FLAG_WOL_SUPPORTED; 7101 7102 /* initialize the wol settings based on the eeprom settings */ 7103 if (adapter->flags & IGC_FLAG_WOL_SUPPORTED) 7104 adapter->wol |= IGC_WUFC_MAG; 7105 7106 device_set_wakeup_enable(&adapter->pdev->dev, 7107 adapter->flags & IGC_FLAG_WOL_SUPPORTED); 7108 7109 igc_ptp_init(adapter); 7110 7111 igc_tsn_clear_schedule(adapter); 7112 7113 /* reset the hardware with the new settings */ 7114 igc_reset(adapter); 7115 7116 /* let the f/w know that the h/w is now under the control of the 7117 * driver. 7118 */ 7119 igc_get_hw_control(adapter); 7120 7121 strscpy(netdev->name, "eth%d", sizeof(netdev->name)); 7122 err = register_netdev(netdev); 7123 if (err) 7124 goto err_register; 7125 7126 /* carrier off reporting is important to ethtool even BEFORE open */ 7127 netif_carrier_off(netdev); 7128 7129 /* Check if Media Autosense is enabled */ 7130 adapter->ei = *ei; 7131 7132 /* print pcie link status and MAC address */ 7133 pcie_print_link_status(pdev); 7134 netdev_info(netdev, "MAC: %pM\n", netdev->dev_addr); 7135 7136 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 7137 /* Disable EEE for internal PHY devices */ 7138 hw->dev_spec._base.eee_enable = false; 7139 adapter->flags &= ~IGC_FLAG_EEE; 7140 igc_set_eee_i225(hw, false, false, false); 7141 7142 pm_runtime_put_noidle(&pdev->dev); 7143 7144 if (IS_ENABLED(CONFIG_IGC_LEDS)) { 7145 err = igc_led_setup(adapter); 7146 if (err) 7147 goto err_register; 7148 } 7149 7150 return 0; 7151 7152 err_register: 7153 igc_release_hw_control(adapter); 7154 err_eeprom: 7155 if (!igc_check_reset_block(hw)) 7156 igc_reset_phy(hw); 7157 err_sw_init: 7158 igc_clear_interrupt_scheme(adapter); 7159 iounmap(adapter->io_addr); 7160 err_ioremap: 7161 free_netdev(netdev); 7162 err_alloc_etherdev: 7163 pci_release_mem_regions(pdev); 7164 err_pci_reg: 7165 err_dma: 7166 pci_disable_device(pdev); 7167 return err; 7168 } 7169 7170 /** 7171 * igc_remove - Device Removal Routine 7172 * @pdev: PCI device information struct 7173 * 7174 * igc_remove is called by the PCI subsystem to alert the driver 7175 * that it should release a PCI device. This could be caused by a 7176 * Hot-Plug event, or because the driver is going to be removed from 7177 * memory. 7178 */ 7179 static void igc_remove(struct pci_dev *pdev) 7180 { 7181 struct net_device *netdev = pci_get_drvdata(pdev); 7182 struct igc_adapter *adapter = netdev_priv(netdev); 7183 7184 pm_runtime_get_noresume(&pdev->dev); 7185 7186 igc_flush_nfc_rules(adapter); 7187 7188 igc_ptp_stop(adapter); 7189 7190 pci_disable_ptm(pdev); 7191 pci_clear_master(pdev); 7192 7193 set_bit(__IGC_DOWN, &adapter->state); 7194 7195 del_timer_sync(&adapter->watchdog_timer); 7196 del_timer_sync(&adapter->phy_info_timer); 7197 7198 cancel_work_sync(&adapter->reset_task); 7199 cancel_work_sync(&adapter->watchdog_task); 7200 hrtimer_cancel(&adapter->hrtimer); 7201 7202 if (IS_ENABLED(CONFIG_IGC_LEDS)) 7203 igc_led_free(adapter); 7204 7205 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7206 * would have already happened in close and is redundant. 7207 */ 7208 igc_release_hw_control(adapter); 7209 unregister_netdev(netdev); 7210 7211 igc_clear_interrupt_scheme(adapter); 7212 pci_iounmap(pdev, adapter->io_addr); 7213 pci_release_mem_regions(pdev); 7214 7215 free_netdev(netdev); 7216 7217 pci_disable_device(pdev); 7218 } 7219 7220 static int __igc_shutdown(struct pci_dev *pdev, bool *enable_wake, 7221 bool runtime) 7222 { 7223 struct net_device *netdev = pci_get_drvdata(pdev); 7224 struct igc_adapter *adapter = netdev_priv(netdev); 7225 u32 wufc = runtime ? IGC_WUFC_LNKC : adapter->wol; 7226 struct igc_hw *hw = &adapter->hw; 7227 u32 ctrl, rctl, status; 7228 bool wake; 7229 7230 rtnl_lock(); 7231 netif_device_detach(netdev); 7232 7233 if (netif_running(netdev)) 7234 __igc_close(netdev, true); 7235 7236 igc_ptp_suspend(adapter); 7237 7238 igc_clear_interrupt_scheme(adapter); 7239 rtnl_unlock(); 7240 7241 status = rd32(IGC_STATUS); 7242 if (status & IGC_STATUS_LU) 7243 wufc &= ~IGC_WUFC_LNKC; 7244 7245 if (wufc) { 7246 igc_setup_rctl(adapter); 7247 igc_set_rx_mode(netdev); 7248 7249 /* turn on all-multi mode if wake on multicast is enabled */ 7250 if (wufc & IGC_WUFC_MC) { 7251 rctl = rd32(IGC_RCTL); 7252 rctl |= IGC_RCTL_MPE; 7253 wr32(IGC_RCTL, rctl); 7254 } 7255 7256 ctrl = rd32(IGC_CTRL); 7257 ctrl |= IGC_CTRL_ADVD3WUC; 7258 wr32(IGC_CTRL, ctrl); 7259 7260 /* Allow time for pending master requests to run */ 7261 igc_disable_pcie_master(hw); 7262 7263 wr32(IGC_WUC, IGC_WUC_PME_EN); 7264 wr32(IGC_WUFC, wufc); 7265 } else { 7266 wr32(IGC_WUC, 0); 7267 wr32(IGC_WUFC, 0); 7268 } 7269 7270 wake = wufc || adapter->en_mng_pt; 7271 if (!wake) 7272 igc_power_down_phy_copper_base(&adapter->hw); 7273 else 7274 igc_power_up_link(adapter); 7275 7276 if (enable_wake) 7277 *enable_wake = wake; 7278 7279 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7280 * would have already happened in close and is redundant. 7281 */ 7282 igc_release_hw_control(adapter); 7283 7284 pci_disable_device(pdev); 7285 7286 return 0; 7287 } 7288 7289 static int igc_runtime_suspend(struct device *dev) 7290 { 7291 return __igc_shutdown(to_pci_dev(dev), NULL, 1); 7292 } 7293 7294 static void igc_deliver_wake_packet(struct net_device *netdev) 7295 { 7296 struct igc_adapter *adapter = netdev_priv(netdev); 7297 struct igc_hw *hw = &adapter->hw; 7298 struct sk_buff *skb; 7299 u32 wupl; 7300 7301 wupl = rd32(IGC_WUPL) & IGC_WUPL_MASK; 7302 7303 /* WUPM stores only the first 128 bytes of the wake packet. 7304 * Read the packet only if we have the whole thing. 7305 */ 7306 if (wupl == 0 || wupl > IGC_WUPM_BYTES) 7307 return; 7308 7309 skb = netdev_alloc_skb_ip_align(netdev, IGC_WUPM_BYTES); 7310 if (!skb) 7311 return; 7312 7313 skb_put(skb, wupl); 7314 7315 /* Ensure reads are 32-bit aligned */ 7316 wupl = roundup(wupl, 4); 7317 7318 memcpy_fromio(skb->data, hw->hw_addr + IGC_WUPM_REG(0), wupl); 7319 7320 skb->protocol = eth_type_trans(skb, netdev); 7321 netif_rx(skb); 7322 } 7323 7324 static int __igc_resume(struct device *dev, bool rpm) 7325 { 7326 struct pci_dev *pdev = to_pci_dev(dev); 7327 struct net_device *netdev = pci_get_drvdata(pdev); 7328 struct igc_adapter *adapter = netdev_priv(netdev); 7329 struct igc_hw *hw = &adapter->hw; 7330 u32 err, val; 7331 7332 pci_set_power_state(pdev, PCI_D0); 7333 pci_restore_state(pdev); 7334 pci_save_state(pdev); 7335 7336 if (!pci_device_is_present(pdev)) 7337 return -ENODEV; 7338 err = pci_enable_device_mem(pdev); 7339 if (err) { 7340 netdev_err(netdev, "Cannot enable PCI device from suspend\n"); 7341 return err; 7342 } 7343 pci_set_master(pdev); 7344 7345 pci_enable_wake(pdev, PCI_D3hot, 0); 7346 pci_enable_wake(pdev, PCI_D3cold, 0); 7347 7348 if (igc_init_interrupt_scheme(adapter, true)) { 7349 netdev_err(netdev, "Unable to allocate memory for queues\n"); 7350 return -ENOMEM; 7351 } 7352 7353 igc_reset(adapter); 7354 7355 /* let the f/w know that the h/w is now under the control of the 7356 * driver. 7357 */ 7358 igc_get_hw_control(adapter); 7359 7360 val = rd32(IGC_WUS); 7361 if (val & WAKE_PKT_WUS) 7362 igc_deliver_wake_packet(netdev); 7363 7364 wr32(IGC_WUS, ~0); 7365 7366 if (netif_running(netdev)) { 7367 if (!rpm) 7368 rtnl_lock(); 7369 err = __igc_open(netdev, true); 7370 if (!rpm) 7371 rtnl_unlock(); 7372 if (!err) 7373 netif_device_attach(netdev); 7374 } 7375 7376 return err; 7377 } 7378 7379 static int igc_resume(struct device *dev) 7380 { 7381 return __igc_resume(dev, false); 7382 } 7383 7384 static int igc_runtime_resume(struct device *dev) 7385 { 7386 return __igc_resume(dev, true); 7387 } 7388 7389 static int igc_suspend(struct device *dev) 7390 { 7391 return __igc_shutdown(to_pci_dev(dev), NULL, 0); 7392 } 7393 7394 static int __maybe_unused igc_runtime_idle(struct device *dev) 7395 { 7396 struct net_device *netdev = dev_get_drvdata(dev); 7397 struct igc_adapter *adapter = netdev_priv(netdev); 7398 7399 if (!igc_has_link(adapter)) 7400 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 7401 7402 return -EBUSY; 7403 } 7404 7405 static void igc_shutdown(struct pci_dev *pdev) 7406 { 7407 bool wake; 7408 7409 __igc_shutdown(pdev, &wake, 0); 7410 7411 if (system_state == SYSTEM_POWER_OFF) { 7412 pci_wake_from_d3(pdev, wake); 7413 pci_set_power_state(pdev, PCI_D3hot); 7414 } 7415 } 7416 7417 /** 7418 * igc_io_error_detected - called when PCI error is detected 7419 * @pdev: Pointer to PCI device 7420 * @state: The current PCI connection state 7421 * 7422 * This function is called after a PCI bus error affecting 7423 * this device has been detected. 7424 **/ 7425 static pci_ers_result_t igc_io_error_detected(struct pci_dev *pdev, 7426 pci_channel_state_t state) 7427 { 7428 struct net_device *netdev = pci_get_drvdata(pdev); 7429 struct igc_adapter *adapter = netdev_priv(netdev); 7430 7431 rtnl_lock(); 7432 netif_device_detach(netdev); 7433 7434 if (state == pci_channel_io_perm_failure) { 7435 rtnl_unlock(); 7436 return PCI_ERS_RESULT_DISCONNECT; 7437 } 7438 7439 if (netif_running(netdev)) 7440 igc_down(adapter); 7441 pci_disable_device(pdev); 7442 rtnl_unlock(); 7443 7444 /* Request a slot reset. */ 7445 return PCI_ERS_RESULT_NEED_RESET; 7446 } 7447 7448 /** 7449 * igc_io_slot_reset - called after the PCI bus has been reset. 7450 * @pdev: Pointer to PCI device 7451 * 7452 * Restart the card from scratch, as if from a cold-boot. Implementation 7453 * resembles the first-half of the __igc_resume routine. 7454 **/ 7455 static pci_ers_result_t igc_io_slot_reset(struct pci_dev *pdev) 7456 { 7457 struct net_device *netdev = pci_get_drvdata(pdev); 7458 struct igc_adapter *adapter = netdev_priv(netdev); 7459 struct igc_hw *hw = &adapter->hw; 7460 pci_ers_result_t result; 7461 7462 if (pci_enable_device_mem(pdev)) { 7463 netdev_err(netdev, "Could not re-enable PCI device after reset\n"); 7464 result = PCI_ERS_RESULT_DISCONNECT; 7465 } else { 7466 pci_set_master(pdev); 7467 pci_restore_state(pdev); 7468 pci_save_state(pdev); 7469 7470 pci_enable_wake(pdev, PCI_D3hot, 0); 7471 pci_enable_wake(pdev, PCI_D3cold, 0); 7472 7473 /* In case of PCI error, adapter loses its HW address 7474 * so we should re-assign it here. 7475 */ 7476 hw->hw_addr = adapter->io_addr; 7477 7478 igc_reset(adapter); 7479 wr32(IGC_WUS, ~0); 7480 result = PCI_ERS_RESULT_RECOVERED; 7481 } 7482 7483 return result; 7484 } 7485 7486 /** 7487 * igc_io_resume - called when traffic can start to flow again. 7488 * @pdev: Pointer to PCI device 7489 * 7490 * This callback is called when the error recovery driver tells us that 7491 * its OK to resume normal operation. Implementation resembles the 7492 * second-half of the __igc_resume routine. 7493 */ 7494 static void igc_io_resume(struct pci_dev *pdev) 7495 { 7496 struct net_device *netdev = pci_get_drvdata(pdev); 7497 struct igc_adapter *adapter = netdev_priv(netdev); 7498 7499 rtnl_lock(); 7500 if (netif_running(netdev)) { 7501 if (igc_open(netdev)) { 7502 rtnl_unlock(); 7503 netdev_err(netdev, "igc_open failed after reset\n"); 7504 return; 7505 } 7506 } 7507 7508 netif_device_attach(netdev); 7509 7510 /* let the f/w know that the h/w is now under the control of the 7511 * driver. 7512 */ 7513 igc_get_hw_control(adapter); 7514 rtnl_unlock(); 7515 } 7516 7517 static const struct pci_error_handlers igc_err_handler = { 7518 .error_detected = igc_io_error_detected, 7519 .slot_reset = igc_io_slot_reset, 7520 .resume = igc_io_resume, 7521 }; 7522 7523 static _DEFINE_DEV_PM_OPS(igc_pm_ops, igc_suspend, igc_resume, 7524 igc_runtime_suspend, igc_runtime_resume, 7525 igc_runtime_idle); 7526 7527 static struct pci_driver igc_driver = { 7528 .name = igc_driver_name, 7529 .id_table = igc_pci_tbl, 7530 .probe = igc_probe, 7531 .remove = igc_remove, 7532 .driver.pm = pm_ptr(&igc_pm_ops), 7533 .shutdown = igc_shutdown, 7534 .err_handler = &igc_err_handler, 7535 }; 7536 7537 /** 7538 * igc_reinit_queues - return error 7539 * @adapter: pointer to adapter structure 7540 */ 7541 int igc_reinit_queues(struct igc_adapter *adapter) 7542 { 7543 struct net_device *netdev = adapter->netdev; 7544 int err = 0; 7545 7546 if (netif_running(netdev)) 7547 igc_close(netdev); 7548 7549 igc_reset_interrupt_capability(adapter); 7550 7551 if (igc_init_interrupt_scheme(adapter, true)) { 7552 netdev_err(netdev, "Unable to allocate memory for queues\n"); 7553 return -ENOMEM; 7554 } 7555 7556 if (netif_running(netdev)) 7557 err = igc_open(netdev); 7558 7559 return err; 7560 } 7561 7562 /** 7563 * igc_get_hw_dev - return device 7564 * @hw: pointer to hardware structure 7565 * 7566 * used by hardware layer to print debugging information 7567 */ 7568 struct net_device *igc_get_hw_dev(struct igc_hw *hw) 7569 { 7570 struct igc_adapter *adapter = hw->back; 7571 7572 return adapter->netdev; 7573 } 7574 7575 static void igc_disable_rx_ring_hw(struct igc_ring *ring) 7576 { 7577 struct igc_hw *hw = &ring->q_vector->adapter->hw; 7578 u8 idx = ring->reg_idx; 7579 u32 rxdctl; 7580 7581 rxdctl = rd32(IGC_RXDCTL(idx)); 7582 rxdctl &= ~IGC_RXDCTL_QUEUE_ENABLE; 7583 rxdctl |= IGC_RXDCTL_SWFLUSH; 7584 wr32(IGC_RXDCTL(idx), rxdctl); 7585 } 7586 7587 void igc_disable_rx_ring(struct igc_ring *ring) 7588 { 7589 igc_disable_rx_ring_hw(ring); 7590 igc_clean_rx_ring(ring); 7591 } 7592 7593 void igc_enable_rx_ring(struct igc_ring *ring) 7594 { 7595 struct igc_adapter *adapter = ring->q_vector->adapter; 7596 7597 igc_configure_rx_ring(adapter, ring); 7598 7599 if (ring->xsk_pool) 7600 igc_alloc_rx_buffers_zc(ring, igc_desc_unused(ring)); 7601 else 7602 igc_alloc_rx_buffers(ring, igc_desc_unused(ring)); 7603 } 7604 7605 void igc_disable_tx_ring(struct igc_ring *ring) 7606 { 7607 igc_disable_tx_ring_hw(ring); 7608 igc_clean_tx_ring(ring); 7609 } 7610 7611 void igc_enable_tx_ring(struct igc_ring *ring) 7612 { 7613 struct igc_adapter *adapter = ring->q_vector->adapter; 7614 7615 igc_configure_tx_ring(adapter, ring); 7616 } 7617 7618 /** 7619 * igc_init_module - Driver Registration Routine 7620 * 7621 * igc_init_module is the first routine called when the driver is 7622 * loaded. All it does is register with the PCI subsystem. 7623 */ 7624 static int __init igc_init_module(void) 7625 { 7626 int ret; 7627 7628 pr_info("%s\n", igc_driver_string); 7629 pr_info("%s\n", igc_copyright); 7630 7631 ret = pci_register_driver(&igc_driver); 7632 return ret; 7633 } 7634 7635 module_init(igc_init_module); 7636 7637 /** 7638 * igc_exit_module - Driver Exit Cleanup Routine 7639 * 7640 * igc_exit_module is called just before the driver is removed 7641 * from memory. 7642 */ 7643 static void __exit igc_exit_module(void) 7644 { 7645 pci_unregister_driver(&igc_driver); 7646 } 7647 7648 module_exit(igc_exit_module); 7649 /* igc_main.c */ 7650