1146740f9SSasha Neftin /* SPDX-License-Identifier: GPL-2.0 */ 2146740f9SSasha Neftin /* Copyright (c) 2018 Intel Corporation */ 3146740f9SSasha Neftin 4146740f9SSasha Neftin #ifndef _IGC_MAC_H_ 5146740f9SSasha Neftin #define _IGC_MAC_H_ 6146740f9SSasha Neftin 7c0071c7aSSasha Neftin #include "igc_hw.h" 85586838fSSasha Neftin #include "igc_phy.h" 9c0071c7aSSasha Neftin #include "igc_defines.h" 10c0071c7aSSasha Neftin 11c0071c7aSSasha Neftin /* forward declaration */ 12c0071c7aSSasha Neftin s32 igc_disable_pcie_master(struct igc_hw *hw); 13ab405612SSasha Neftin s32 igc_check_for_copper_link(struct igc_hw *hw); 144eb80801SSasha Neftin s32 igc_config_fc_after_link_up(struct igc_hw *hw); 154eb80801SSasha Neftin s32 igc_force_mac_fc(struct igc_hw *hw); 16c0071c7aSSasha Neftin void igc_init_rx_addrs(struct igc_hw *hw, u16 rar_count); 17c0071c7aSSasha Neftin s32 igc_setup_link(struct igc_hw *hw); 18c0071c7aSSasha Neftin void igc_clear_hw_cntrs_base(struct igc_hw *hw); 19c0071c7aSSasha Neftin s32 igc_get_auto_rd_done(struct igc_hw *hw); 20c0071c7aSSasha Neftin void igc_put_hw_semaphore(struct igc_hw *hw); 21ab405612SSasha Neftin void igc_rar_set(struct igc_hw *hw, u8 *addr, u32 index); 22ab405612SSasha Neftin void igc_config_collision_dist(struct igc_hw *hw); 23ab405612SSasha Neftin 24ab405612SSasha Neftin s32 igc_get_speed_and_duplex_copper(struct igc_hw *hw, u16 *speed, 25ab405612SSasha Neftin u16 *duplex); 26c0071c7aSSasha Neftin 275586838fSSasha Neftin bool igc_enable_mng_pass_thru(struct igc_hw *hw); 28*7f839684SSasha Neftin void igc_update_mc_addr_list(struct igc_hw *hw, 29*7f839684SSasha Neftin u8 *mc_addr_list, u32 mc_addr_count); 305586838fSSasha Neftin 315586838fSSasha Neftin enum igc_mng_mode { 325586838fSSasha Neftin igc_mng_mode_none = 0, 335586838fSSasha Neftin igc_mng_mode_asf, 345586838fSSasha Neftin igc_mng_mode_pt, 355586838fSSasha Neftin igc_mng_mode_ipmi, 365586838fSSasha Neftin igc_mng_mode_host_if_only 375586838fSSasha Neftin }; 385586838fSSasha Neftin 39146740f9SSasha Neftin #endif 40