1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_DEFINES_H_ 5 #define _IGC_DEFINES_H_ 6 7 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 8 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 9 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 10 11 #define IGC_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */ 12 13 /* Definitions for power management and wakeup registers */ 14 /* Wake Up Control */ 15 #define IGC_WUC_PME_EN 0x00000002 /* PME Enable */ 16 17 /* Wake Up Filter Control */ 18 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 19 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 20 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 21 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 22 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 23 24 #define IGC_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ 25 26 /* Wake Up Status */ 27 #define IGC_WUS_EX 0x00000004 /* Directed Exact */ 28 #define IGC_WUS_ARPD 0x00000020 /* Directed ARP Request */ 29 #define IGC_WUS_IPV4 0x00000040 /* Directed IPv4 */ 30 #define IGC_WUS_IPV6 0x00000080 /* Directed IPv6 */ 31 #define IGC_WUS_NSD 0x00000400 /* Directed IPv6 Neighbor Solicitation */ 32 33 /* Packet types that are enabled for wake packet delivery */ 34 #define WAKE_PKT_WUS ( \ 35 IGC_WUS_EX | \ 36 IGC_WUS_ARPD | \ 37 IGC_WUS_IPV4 | \ 38 IGC_WUS_IPV6 | \ 39 IGC_WUS_NSD) 40 41 /* Wake Up Packet Length */ 42 #define IGC_WUPL_MASK 0x00000FFF 43 44 /* Wake Up Packet Memory stores the first 128 bytes of the wake up packet */ 45 #define IGC_WUPM_BYTES 128 46 47 /* Loop limit on how long we wait for auto-negotiation to complete */ 48 #define COPPER_LINK_UP_LIMIT 10 49 #define PHY_AUTO_NEG_LIMIT 45 50 #define PHY_FORCE_LIMIT 20 51 52 /* Number of 100 microseconds we wait for PCI Express master disable */ 53 #define MASTER_DISABLE_TIMEOUT 800 54 /*Blocks new Master requests */ 55 #define IGC_CTRL_GIO_MASTER_DISABLE 0x00000004 56 /* Status of Master requests. */ 57 #define IGC_STATUS_GIO_MASTER_ENABLE 0x00080000 58 59 /* Receive Address 60 * Number of high/low register pairs in the RAR. The RAR (Receive Address 61 * Registers) holds the directed and multicast addresses that we monitor. 62 * Technically, we have 16 spots. However, we reserve one of these spots 63 * (RAR[15]) for our directed address used by controllers with 64 * manageability enabled, allowing us room for 15 multicast addresses. 65 */ 66 #define IGC_RAH_QSEL_MASK 0x000C0000 67 #define IGC_RAH_QSEL_SHIFT 18 68 #define IGC_RAH_QSEL_ENABLE BIT(28) 69 #define IGC_RAH_AV 0x80000000 /* Receive descriptor valid */ 70 71 #define IGC_RAL_MAC_ADDR_LEN 4 72 #define IGC_RAH_MAC_ADDR_LEN 2 73 74 /* Error Codes */ 75 #define IGC_SUCCESS 0 76 #define IGC_ERR_NVM 1 77 #define IGC_ERR_PHY 2 78 #define IGC_ERR_CONFIG 3 79 #define IGC_ERR_PARAM 4 80 #define IGC_ERR_MAC_INIT 5 81 #define IGC_ERR_RESET 9 82 #define IGC_ERR_MASTER_REQUESTS_PENDING 10 83 #define IGC_ERR_BLK_PHY_RESET 12 84 #define IGC_ERR_SWFW_SYNC 13 85 86 /* Device Control */ 87 #define IGC_CTRL_DEV_RST 0x20000000 /* Device reset */ 88 89 #define IGC_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 90 #define IGC_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 91 #define IGC_CTRL_FRCSPD 0x00000800 /* Force Speed */ 92 #define IGC_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 93 94 #define IGC_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 95 #define IGC_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 96 97 /* As per the EAS the maximum supported size is 9.5KB (9728 bytes) */ 98 #define MAX_JUMBO_FRAME_SIZE 0x2600 99 100 /* PBA constants */ 101 #define IGC_PBA_34K 0x0022 102 103 /* SW Semaphore Register */ 104 #define IGC_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 105 #define IGC_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 106 107 /* SWFW_SYNC Definitions */ 108 #define IGC_SWFW_EEP_SM 0x1 109 #define IGC_SWFW_PHY0_SM 0x2 110 111 /* Autoneg Advertisement Register */ 112 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 113 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 114 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 115 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 116 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 117 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 118 119 /* Link Partner Ability Register (Base Page) */ 120 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 121 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 122 123 /* 1000BASE-T Control Register */ 124 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ 125 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 126 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 127 128 /* 1000BASE-T Status Register */ 129 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 130 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 131 132 /* PHY GPY 211 registers */ 133 #define STANDARD_AN_REG_MASK 0x0007 /* MMD */ 134 #define ANEG_MULTIGBT_AN_CTRL 0x0020 /* MULTI GBT AN Control Register */ 135 #define MMD_DEVADDR_SHIFT 16 /* Shift MMD to higher bits */ 136 #define CR_2500T_FD_CAPS 0x0080 /* Advertise 2500T FD capability */ 137 138 /* NVM Control */ 139 /* Number of milliseconds for NVM auto read done after MAC reset. */ 140 #define AUTO_READ_DONE_TIMEOUT 10 141 #define IGC_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 142 #define IGC_EECD_REQ 0x00000040 /* NVM Access Request */ 143 #define IGC_EECD_GNT 0x00000080 /* NVM Access Grant */ 144 /* NVM Addressing bits based on type 0=small, 1=large */ 145 #define IGC_EECD_ADDR_BITS 0x00000400 146 #define IGC_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 147 #define IGC_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 148 #define IGC_EECD_SIZE_EX_SHIFT 11 149 #define IGC_EECD_FLUPD_I225 0x00800000 /* Update FLASH */ 150 #define IGC_EECD_FLUDONE_I225 0x04000000 /* Update FLASH done*/ 151 #define IGC_EECD_FLASH_DETECTED_I225 0x00080000 /* FLASH detected */ 152 #define IGC_FLUDONE_ATTEMPTS 20000 153 #define IGC_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ 154 155 /* Offset to data in NVM read/write registers */ 156 #define IGC_NVM_RW_REG_DATA 16 157 #define IGC_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 158 #define IGC_NVM_RW_REG_START 1 /* Start operation */ 159 #define IGC_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 160 #define IGC_NVM_POLL_READ 0 /* Flag for polling for read complete */ 161 162 /* NVM Word Offsets */ 163 #define NVM_CHECKSUM_REG 0x003F 164 165 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 166 #define NVM_SUM 0xBABA 167 168 #define NVM_PBA_OFFSET_0 8 169 #define NVM_PBA_OFFSET_1 9 170 #define NVM_RESERVED_WORD 0xFFFF 171 #define NVM_PBA_PTR_GUARD 0xFAFA 172 #define NVM_WORD_SIZE_BASE_SHIFT 6 173 174 /* Collision related configuration parameters */ 175 #define IGC_COLLISION_THRESHOLD 15 176 #define IGC_CT_SHIFT 4 177 #define IGC_COLLISION_DISTANCE 63 178 #define IGC_COLD_SHIFT 12 179 180 /* Device Status */ 181 #define IGC_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 182 #define IGC_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 183 #define IGC_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 184 #define IGC_STATUS_FUNC_SHIFT 2 185 #define IGC_STATUS_FUNC_1 0x00000004 /* Function 1 */ 186 #define IGC_STATUS_TXOFF 0x00000010 /* transmission paused */ 187 #define IGC_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 188 #define IGC_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 189 #define IGC_STATUS_SPEED_2500 0x00400000 /* Speed 2.5Gb/s */ 190 191 #define SPEED_10 10 192 #define SPEED_100 100 193 #define SPEED_1000 1000 194 #define SPEED_2500 2500 195 #define HALF_DUPLEX 1 196 #define FULL_DUPLEX 2 197 198 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */ 199 #define ADVERTISE_10_HALF 0x0001 200 #define ADVERTISE_10_FULL 0x0002 201 #define ADVERTISE_100_HALF 0x0004 202 #define ADVERTISE_100_FULL 0x0008 203 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 204 #define ADVERTISE_1000_FULL 0x0020 205 #define ADVERTISE_2500_HALF 0x0040 /* Not used, just FYI */ 206 #define ADVERTISE_2500_FULL 0x0080 207 208 #define IGC_ALL_SPEED_DUPLEX_2500 ( \ 209 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 210 ADVERTISE_100_FULL | ADVERTISE_1000_FULL | ADVERTISE_2500_FULL) 211 212 #define AUTONEG_ADVERTISE_SPEED_DEFAULT_2500 IGC_ALL_SPEED_DUPLEX_2500 213 214 /* Interrupt Cause Read */ 215 #define IGC_ICR_TXDW BIT(0) /* Transmit desc written back */ 216 #define IGC_ICR_TXQE BIT(1) /* Transmit Queue empty */ 217 #define IGC_ICR_LSC BIT(2) /* Link Status Change */ 218 #define IGC_ICR_RXSEQ BIT(3) /* Rx sequence error */ 219 #define IGC_ICR_RXDMT0 BIT(4) /* Rx desc min. threshold (0) */ 220 #define IGC_ICR_RXO BIT(6) /* Rx overrun */ 221 #define IGC_ICR_RXT0 BIT(7) /* Rx timer intr (ring 0) */ 222 #define IGC_ICR_TS BIT(19) /* Time Sync Interrupt */ 223 #define IGC_ICR_DRSTA BIT(30) /* Device Reset Asserted */ 224 225 /* If this bit asserted, the driver should claim the interrupt */ 226 #define IGC_ICR_INT_ASSERTED BIT(31) 227 228 #define IGC_ICS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */ 229 230 #define IMS_ENABLE_MASK ( \ 231 IGC_IMS_RXT0 | \ 232 IGC_IMS_TXDW | \ 233 IGC_IMS_RXDMT0 | \ 234 IGC_IMS_RXSEQ | \ 235 IGC_IMS_LSC) 236 237 /* Interrupt Mask Set */ 238 #define IGC_IMS_TXDW IGC_ICR_TXDW /* Tx desc written back */ 239 #define IGC_IMS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */ 240 #define IGC_IMS_LSC IGC_ICR_LSC /* Link Status Change */ 241 #define IGC_IMS_DOUTSYNC IGC_ICR_DOUTSYNC /* NIC DMA out of sync */ 242 #define IGC_IMS_DRSTA IGC_ICR_DRSTA /* Device Reset Asserted */ 243 #define IGC_IMS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */ 244 #define IGC_IMS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */ 245 #define IGC_IMS_TS IGC_ICR_TS /* Time Sync Interrupt */ 246 247 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */ 248 #define IGC_ITR_VAL_MASK 0x04 /* ITR value mask */ 249 250 /* Interrupt Cause Set */ 251 #define IGC_ICS_LSC IGC_ICR_LSC /* Link Status Change */ 252 #define IGC_ICS_RXDMT0 IGC_ICR_RXDMT0 /* rx desc min. threshold */ 253 #define IGC_ICS_DRSTA IGC_ICR_DRSTA /* Device Reset Aserted */ 254 255 #define IGC_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 256 #define IGC_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */ 257 #define IGC_IVAR_VALID 0x80 258 #define IGC_GPIE_NSICR 0x00000001 259 #define IGC_GPIE_MSIX_MODE 0x00000010 260 #define IGC_GPIE_EIAME 0x40000000 261 #define IGC_GPIE_PBA 0x80000000 262 263 /* Receive Descriptor bit definitions */ 264 #define IGC_RXD_STAT_DD 0x01 /* Descriptor Done */ 265 266 /* Transmit Descriptor bit definitions */ 267 #define IGC_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 268 #define IGC_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 269 #define IGC_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 270 #define IGC_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 271 #define IGC_TXD_CMD_EOP 0x01000000 /* End of Packet */ 272 #define IGC_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 273 #define IGC_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 274 #define IGC_TXD_CMD_RS 0x08000000 /* Report Status */ 275 #define IGC_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 276 #define IGC_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */ 277 #define IGC_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 278 #define IGC_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 279 #define IGC_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 280 #define IGC_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 281 #define IGC_TXD_STAT_LC 0x00000004 /* Late Collisions */ 282 #define IGC_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 283 #define IGC_TXD_CMD_TCP 0x01000000 /* TCP packet */ 284 #define IGC_TXD_CMD_IP 0x02000000 /* IP packet */ 285 #define IGC_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 286 #define IGC_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 287 #define IGC_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */ 288 289 /* IPSec Encrypt Enable */ 290 #define IGC_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 291 #define IGC_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 292 293 /* Transmit Control */ 294 #define IGC_TCTL_EN 0x00000002 /* enable Tx */ 295 #define IGC_TCTL_PSP 0x00000008 /* pad short packets */ 296 #define IGC_TCTL_CT 0x00000ff0 /* collision threshold */ 297 #define IGC_TCTL_COLD 0x003ff000 /* collision distance */ 298 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 299 #define IGC_TCTL_MULR 0x10000000 /* Multiple request support */ 300 301 /* Flow Control Constants */ 302 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 303 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 304 #define FLOW_CONTROL_TYPE 0x8808 305 /* Enable XON frame transmission */ 306 #define IGC_FCRTL_XONE 0x80000000 307 308 /* Management Control */ 309 #define IGC_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 310 #define IGC_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 311 312 /* Receive Control */ 313 #define IGC_RCTL_RST 0x00000001 /* Software reset */ 314 #define IGC_RCTL_EN 0x00000002 /* enable */ 315 #define IGC_RCTL_SBP 0x00000004 /* store bad packet */ 316 #define IGC_RCTL_UPE 0x00000008 /* unicast promisc enable */ 317 #define IGC_RCTL_MPE 0x00000010 /* multicast promisc enable */ 318 #define IGC_RCTL_LPE 0x00000020 /* long packet enable */ 319 #define IGC_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 320 #define IGC_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 321 322 #define IGC_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */ 323 #define IGC_RCTL_BAM 0x00008000 /* broadcast enable */ 324 325 /* Split Replication Receive Control */ 326 #define IGC_SRRCTL_TIMESTAMP 0x40000000 327 #define IGC_SRRCTL_TIMER1SEL(timer) (((timer) & 0x3) << 14) 328 #define IGC_SRRCTL_TIMER0SEL(timer) (((timer) & 0x3) << 17) 329 330 /* Receive Descriptor bit definitions */ 331 #define IGC_RXD_STAT_EOP 0x02 /* End of Packet */ 332 #define IGC_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 333 #define IGC_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 334 #define IGC_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 335 336 /* Advanced Receive Descriptor bit definitions */ 337 #define IGC_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */ 338 #define IGC_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */ 339 340 #define IGC_RXDEXT_STATERR_CE 0x01000000 341 #define IGC_RXDEXT_STATERR_SE 0x02000000 342 #define IGC_RXDEXT_STATERR_SEQ 0x04000000 343 #define IGC_RXDEXT_STATERR_CXE 0x10000000 344 #define IGC_RXDEXT_STATERR_TCPE 0x20000000 345 #define IGC_RXDEXT_STATERR_IPE 0x40000000 346 #define IGC_RXDEXT_STATERR_RXE 0x80000000 347 348 /* Same mask, but for extended and packet split descriptors */ 349 #define IGC_RXDEXT_ERR_FRAME_ERR_MASK ( \ 350 IGC_RXDEXT_STATERR_CE | \ 351 IGC_RXDEXT_STATERR_SE | \ 352 IGC_RXDEXT_STATERR_SEQ | \ 353 IGC_RXDEXT_STATERR_CXE | \ 354 IGC_RXDEXT_STATERR_RXE) 355 356 #define IGC_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 357 #define IGC_MRQC_RSS_FIELD_IPV4 0x00020000 358 #define IGC_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 359 #define IGC_MRQC_RSS_FIELD_IPV6 0x00100000 360 #define IGC_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 361 362 /* Header split receive */ 363 #define IGC_RFCTL_IPV6_EX_DIS 0x00010000 364 #define IGC_RFCTL_LEF 0x00040000 365 366 #define IGC_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ 367 368 #define IGC_RCTL_MO_SHIFT 12 /* multicast offset shift */ 369 #define IGC_RCTL_CFIEN 0x00080000 /* canonical form enable */ 370 #define IGC_RCTL_DPF 0x00400000 /* discard pause frames */ 371 #define IGC_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 372 #define IGC_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 373 374 #define I225_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */ 375 #define I225_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */ 376 #define IGC_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */ 377 378 #define IGC_TXPBSIZE_TSN 0x04145145 /* 5k bytes buffer for each queue */ 379 380 #define IGC_DTXMXPKTSZ_TSN 0x19 /* 1600 bytes of max TX DMA packet size */ 381 #define IGC_DTXMXPKTSZ_DEFAULT 0x98 /* 9728-byte Jumbo frames */ 382 383 /* Time Sync Interrupt Causes */ 384 #define IGC_TSICR_SYS_WRAP BIT(0) /* SYSTIM Wrap around. */ 385 #define IGC_TSICR_TXTS BIT(1) /* Transmit Timestamp. */ 386 #define IGC_TSICR_TT0 BIT(3) /* Target Time 0 Trigger. */ 387 #define IGC_TSICR_TT1 BIT(4) /* Target Time 1 Trigger. */ 388 #define IGC_TSICR_AUTT0 BIT(5) /* Auxiliary Timestamp 0 Taken. */ 389 #define IGC_TSICR_AUTT1 BIT(6) /* Auxiliary Timestamp 1 Taken. */ 390 391 #define IGC_TSICR_INTERRUPTS IGC_TSICR_TXTS 392 393 /* PTP Queue Filter */ 394 #define IGC_ETQF_1588 BIT(30) 395 396 #define IGC_FTQF_VF_BP 0x00008000 397 #define IGC_FTQF_1588_TIME_STAMP 0x08000000 398 #define IGC_FTQF_MASK 0xF0000000 399 #define IGC_FTQF_MASK_PROTO_BP 0x10000000 400 401 /* Time Sync Receive Control bit definitions */ 402 #define IGC_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 403 #define IGC_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 404 #define IGC_TSYNCRXCTL_TYPE_L2_V2 0x00 405 #define IGC_TSYNCRXCTL_TYPE_L4_V1 0x02 406 #define IGC_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 407 #define IGC_TSYNCRXCTL_TYPE_ALL 0x08 408 #define IGC_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 409 #define IGC_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ 410 #define IGC_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */ 411 #define IGC_TSYNCRXCTL_RXSYNSIG 0x00000400 /* Sample RX tstamp in PHY sop */ 412 413 /* Time Sync Receive Configuration */ 414 #define IGC_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF 415 #define IGC_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 416 #define IGC_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01 417 418 /* Immediate Interrupt Receive */ 419 #define IGC_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */ 420 #define IGC_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */ 421 #define IGC_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */ 422 #define IGC_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */ 423 424 /* Immediate Interrupt Receive Extended */ 425 #define IGC_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */ 426 #define IGC_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 427 428 /* Time Sync Transmit Control bit definitions */ 429 #define IGC_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ 430 #define IGC_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */ 431 #define IGC_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000 /* max delay */ 432 #define IGC_TSYNCTXCTL_SYNC_COMP_ERR 0x20000000 /* sync err */ 433 #define IGC_TSYNCTXCTL_SYNC_COMP 0x40000000 /* sync complete */ 434 #define IGC_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */ 435 #define IGC_TSYNCTXCTL_TXSYNSIG 0x00000020 /* Sample TX tstamp in PHY sop */ 436 437 /* Transmit Scheduling */ 438 #define IGC_TQAVCTRL_TRANSMIT_MODE_TSN 0x00000001 439 #define IGC_TQAVCTRL_ENHANCED_QAV 0x00000008 440 441 #define IGC_TXQCTL_QUEUE_MODE_LAUNCHT 0x00000001 442 #define IGC_TXQCTL_STRICT_CYCLE 0x00000002 443 #define IGC_TXQCTL_STRICT_END 0x00000004 444 445 /* Receive Checksum Control */ 446 #define IGC_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ 447 #define IGC_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 448 449 /* GPY211 - I225 defines */ 450 #define GPY_MMD_MASK 0xFFFF0000 451 #define GPY_MMD_SHIFT 16 452 #define GPY_REG_MASK 0x0000FFFF 453 454 #define IGC_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */ 455 456 /* MAC definitions */ 457 #define IGC_FACTPS_MNGCG 0x20000000 458 #define IGC_FWSM_MODE_MASK 0xE 459 #define IGC_FWSM_MODE_SHIFT 1 460 461 /* Management Control */ 462 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 463 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 464 465 /* PHY */ 466 #define PHY_REVISION_MASK 0xFFFFFFF0 467 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 468 #define IGC_GEN_POLL_TIMEOUT 1920 469 470 /* PHY Control Register */ 471 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 472 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 473 #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 474 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 475 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 476 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 477 #define MII_CR_SPEED_1000 0x0040 478 #define MII_CR_SPEED_100 0x2000 479 #define MII_CR_SPEED_10 0x0000 480 481 /* PHY Status Register */ 482 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 483 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 484 #define IGC_PHY_RST_COMP 0x0100 /* Internal PHY reset completion */ 485 486 /* PHY 1000 MII Register/Bit Definitions */ 487 /* PHY Registers defined by IEEE */ 488 #define PHY_CONTROL 0x00 /* Control Register */ 489 #define PHY_STATUS 0x01 /* Status Register */ 490 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 491 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 492 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 493 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 494 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 495 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 496 497 /* Bit definitions for valid PHY IDs. I = Integrated E = External */ 498 #define I225_I_PHY_ID 0x67C9DC00 499 500 /* MDI Control */ 501 #define IGC_MDIC_DATA_MASK 0x0000FFFF 502 #define IGC_MDIC_REG_MASK 0x001F0000 503 #define IGC_MDIC_REG_SHIFT 16 504 #define IGC_MDIC_PHY_MASK 0x03E00000 505 #define IGC_MDIC_PHY_SHIFT 21 506 #define IGC_MDIC_OP_WRITE 0x04000000 507 #define IGC_MDIC_OP_READ 0x08000000 508 #define IGC_MDIC_READY 0x10000000 509 #define IGC_MDIC_INT_EN 0x20000000 510 #define IGC_MDIC_ERROR 0x40000000 511 512 #define IGC_N0_QUEUE -1 513 514 #define IGC_MAX_MAC_HDR_LEN 127 515 #define IGC_MAX_NETWORK_HDR_LEN 511 516 517 #define IGC_VLAPQF_QUEUE_SEL(_n, q_idx) ((q_idx) << ((_n) * 4)) 518 #define IGC_VLAPQF_P_VALID(_n) (0x1 << (3 + (_n) * 4)) 519 #define IGC_VLAPQF_QUEUE_MASK 0x03 520 521 #define IGC_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 522 #define IGC_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type:1=IPv4 */ 523 #define IGC_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet Type of TCP */ 524 #define IGC_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */ 525 526 /* Maximum size of the MTA register table in all supported adapters */ 527 #define MAX_MTA_REG 128 528 529 #endif /* _IGC_DEFINES_H_ */ 530