xref: /linux/drivers/net/ethernet/intel/igc/igc_defines.h (revision 0b8061c340b643e01da431dd60c75a41bb1d31ec)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c)  2018 Intel Corporation */
3 
4 #ifndef _IGC_DEFINES_H_
5 #define _IGC_DEFINES_H_
6 
7 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
8 #define REQ_TX_DESCRIPTOR_MULTIPLE	8
9 #define REQ_RX_DESCRIPTOR_MULTIPLE	8
10 
11 #define IGC_CTRL_EXT_DRV_LOAD	0x10000000 /* Drv loaded bit for FW */
12 
13 /* Definitions for power management and wakeup registers */
14 /* Wake Up Control */
15 #define IGC_WUC_PME_EN	0x00000002 /* PME Enable */
16 
17 /* Wake Up Filter Control */
18 #define IGC_WUFC_LNKC	0x00000001 /* Link Status Change Wakeup Enable */
19 #define IGC_WUFC_MAG	0x00000002 /* Magic Packet Wakeup Enable */
20 #define IGC_WUFC_EX	0x00000004 /* Directed Exact Wakeup Enable */
21 #define IGC_WUFC_MC	0x00000008 /* Directed Multicast Wakeup Enable */
22 #define IGC_WUFC_BC	0x00000010 /* Broadcast Wakeup Enable */
23 
24 #define IGC_CTRL_ADVD3WUC	0x00100000  /* D3 WUC */
25 
26 /* Wake Up Status */
27 #define IGC_WUS_EX	0x00000004 /* Directed Exact */
28 #define IGC_WUS_ARPD	0x00000020 /* Directed ARP Request */
29 #define IGC_WUS_IPV4	0x00000040 /* Directed IPv4 */
30 #define IGC_WUS_IPV6	0x00000080 /* Directed IPv6 */
31 #define IGC_WUS_NSD	0x00000400 /* Directed IPv6 Neighbor Solicitation */
32 
33 /* Packet types that are enabled for wake packet delivery */
34 #define WAKE_PKT_WUS ( \
35 	IGC_WUS_EX   | \
36 	IGC_WUS_ARPD | \
37 	IGC_WUS_IPV4 | \
38 	IGC_WUS_IPV6 | \
39 	IGC_WUS_NSD)
40 
41 /* Wake Up Packet Length */
42 #define IGC_WUPL_MASK	0x00000FFF
43 
44 /* Wake Up Packet Memory stores the first 128 bytes of the wake up packet */
45 #define IGC_WUPM_BYTES	128
46 
47 /* Loop limit on how long we wait for auto-negotiation to complete */
48 #define COPPER_LINK_UP_LIMIT		10
49 #define PHY_AUTO_NEG_LIMIT		45
50 
51 /* Number of 100 microseconds we wait for PCI Express master disable */
52 #define MASTER_DISABLE_TIMEOUT		800
53 /*Blocks new Master requests */
54 #define IGC_CTRL_GIO_MASTER_DISABLE	0x00000004
55 /* Status of Master requests. */
56 #define IGC_STATUS_GIO_MASTER_ENABLE	0x00080000
57 
58 /* Receive Address
59  * Number of high/low register pairs in the RAR. The RAR (Receive Address
60  * Registers) holds the directed and multicast addresses that we monitor.
61  * Technically, we have 16 spots.  However, we reserve one of these spots
62  * (RAR[15]) for our directed address used by controllers with
63  * manageability enabled, allowing us room for 15 multicast addresses.
64  */
65 #define IGC_RAH_RAH_MASK	0x0000FFFF
66 #define IGC_RAH_ASEL_MASK	0x00030000
67 #define IGC_RAH_ASEL_SRC_ADDR	BIT(16)
68 #define IGC_RAH_QSEL_MASK	0x000C0000
69 #define IGC_RAH_QSEL_SHIFT	18
70 #define IGC_RAH_QSEL_ENABLE	BIT(28)
71 #define IGC_RAH_AV		0x80000000 /* Receive descriptor valid */
72 
73 #define IGC_RAL_MAC_ADDR_LEN	4
74 #define IGC_RAH_MAC_ADDR_LEN	2
75 
76 /* Error Codes */
77 #define IGC_SUCCESS			0
78 #define IGC_ERR_NVM			1
79 #define IGC_ERR_PHY			2
80 #define IGC_ERR_CONFIG			3
81 #define IGC_ERR_PARAM			4
82 #define IGC_ERR_MAC_INIT		5
83 #define IGC_ERR_RESET			9
84 #define IGC_ERR_MASTER_REQUESTS_PENDING	10
85 #define IGC_ERR_BLK_PHY_RESET		12
86 #define IGC_ERR_SWFW_SYNC		13
87 
88 /* Device Control */
89 #define IGC_CTRL_DEV_RST	0x20000000  /* Device reset */
90 
91 #define IGC_CTRL_PHY_RST	0x80000000  /* PHY Reset */
92 #define IGC_CTRL_SLU		0x00000040  /* Set link up (Force Link) */
93 #define IGC_CTRL_FRCSPD		0x00000800  /* Force Speed */
94 #define IGC_CTRL_FRCDPX		0x00001000  /* Force Duplex */
95 
96 #define IGC_CTRL_RFCE		0x08000000  /* Receive Flow Control enable */
97 #define IGC_CTRL_TFCE		0x10000000  /* Transmit flow control enable */
98 
99 /* As per the EAS the maximum supported size is 9.5KB (9728 bytes) */
100 #define MAX_JUMBO_FRAME_SIZE	0x2600
101 
102 /* PBA constants */
103 #define IGC_PBA_34K		0x0022
104 
105 /* SW Semaphore Register */
106 #define IGC_SWSM_SMBI		0x00000001 /* Driver Semaphore bit */
107 #define IGC_SWSM_SWESMBI	0x00000002 /* FW Semaphore bit */
108 
109 /* SWFW_SYNC Definitions */
110 #define IGC_SWFW_EEP_SM		0x1
111 #define IGC_SWFW_PHY0_SM	0x2
112 
113 /* Autoneg Advertisement Register */
114 #define NWAY_AR_10T_HD_CAPS	0x0020   /* 10T   Half Duplex Capable */
115 #define NWAY_AR_10T_FD_CAPS	0x0040   /* 10T   Full Duplex Capable */
116 #define NWAY_AR_100TX_HD_CAPS	0x0080   /* 100TX Half Duplex Capable */
117 #define NWAY_AR_100TX_FD_CAPS	0x0100   /* 100TX Full Duplex Capable */
118 #define NWAY_AR_PAUSE		0x0400   /* Pause operation desired */
119 #define NWAY_AR_ASM_DIR		0x0800   /* Asymmetric Pause Direction bit */
120 
121 /* Link Partner Ability Register (Base Page) */
122 #define NWAY_LPAR_PAUSE		0x0400 /* LP Pause operation desired */
123 #define NWAY_LPAR_ASM_DIR	0x0800 /* LP Asymmetric Pause Direction bit */
124 
125 /* 1000BASE-T Control Register */
126 #define CR_1000T_ASYM_PAUSE	0x0080 /* Advertise asymmetric pause bit */
127 #define CR_1000T_HD_CAPS	0x0100 /* Advertise 1000T HD capability */
128 #define CR_1000T_FD_CAPS	0x0200 /* Advertise 1000T FD capability  */
129 
130 /* 1000BASE-T Status Register */
131 #define SR_1000T_REMOTE_RX_STATUS	0x1000 /* Remote receiver OK */
132 
133 /* PHY GPY 211 registers */
134 #define STANDARD_AN_REG_MASK	0x0007 /* MMD */
135 #define ANEG_MULTIGBT_AN_CTRL	0x0020 /* MULTI GBT AN Control Register */
136 #define MMD_DEVADDR_SHIFT	16     /* Shift MMD to higher bits */
137 #define CR_2500T_FD_CAPS	0x0080 /* Advertise 2500T FD capability */
138 
139 /* NVM Control */
140 /* Number of milliseconds for NVM auto read done after MAC reset. */
141 #define AUTO_READ_DONE_TIMEOUT		10
142 #define IGC_EECD_AUTO_RD		0x00000200  /* NVM Auto Read done */
143 #define IGC_EECD_REQ		0x00000040 /* NVM Access Request */
144 #define IGC_EECD_GNT		0x00000080 /* NVM Access Grant */
145 /* NVM Addressing bits based on type 0=small, 1=large */
146 #define IGC_EECD_ADDR_BITS		0x00000400
147 #define IGC_NVM_GRANT_ATTEMPTS		1000 /* NVM # attempts to gain grant */
148 #define IGC_EECD_SIZE_EX_MASK		0x00007800  /* NVM Size */
149 #define IGC_EECD_SIZE_EX_SHIFT		11
150 #define IGC_EECD_FLUPD_I225		0x00800000 /* Update FLASH */
151 #define IGC_EECD_FLUDONE_I225		0x04000000 /* Update FLASH done*/
152 #define IGC_EECD_FLASH_DETECTED_I225	0x00080000 /* FLASH detected */
153 #define IGC_FLUDONE_ATTEMPTS		20000
154 #define IGC_EERD_EEWR_MAX_COUNT		512 /* buffered EEPROM words rw */
155 
156 /* Offset to data in NVM read/write registers */
157 #define IGC_NVM_RW_REG_DATA	16
158 #define IGC_NVM_RW_REG_DONE	2    /* Offset to READ/WRITE done bit */
159 #define IGC_NVM_RW_REG_START	1    /* Start operation */
160 #define IGC_NVM_RW_ADDR_SHIFT	2    /* Shift to the address bits */
161 #define IGC_NVM_POLL_READ	0    /* Flag for polling for read complete */
162 #define IGC_NVM_DEV_STARTER	5    /* Dev_starter Version */
163 
164 /* NVM Word Offsets */
165 #define NVM_CHECKSUM_REG		0x003F
166 
167 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
168 #define NVM_SUM				0xBABA
169 #define NVM_WORD_SIZE_BASE_SHIFT	6
170 
171 /* Collision related configuration parameters */
172 #define IGC_COLLISION_THRESHOLD		15
173 #define IGC_CT_SHIFT			4
174 #define IGC_COLLISION_DISTANCE		63
175 #define IGC_COLD_SHIFT			12
176 
177 /* Device Status */
178 #define IGC_STATUS_FD		0x00000001      /* Full duplex.0=half,1=full */
179 #define IGC_STATUS_LU		0x00000002      /* Link up.0=no,1=link */
180 #define IGC_STATUS_FUNC_MASK	0x0000000C      /* PCI Function Mask */
181 #define IGC_STATUS_FUNC_SHIFT	2
182 #define IGC_STATUS_TXOFF	0x00000010      /* transmission paused */
183 #define IGC_STATUS_SPEED_100	0x00000040      /* Speed 100Mb/s */
184 #define IGC_STATUS_SPEED_1000	0x00000080      /* Speed 1000Mb/s */
185 #define IGC_STATUS_SPEED_2500	0x00400000	/* Speed 2.5Gb/s */
186 
187 #define SPEED_10		10
188 #define SPEED_100		100
189 #define SPEED_1000		1000
190 #define SPEED_2500		2500
191 #define HALF_DUPLEX		1
192 #define FULL_DUPLEX		2
193 
194 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
195 #define ADVERTISE_10_HALF		0x0001
196 #define ADVERTISE_10_FULL		0x0002
197 #define ADVERTISE_100_HALF		0x0004
198 #define ADVERTISE_100_FULL		0x0008
199 #define ADVERTISE_1000_HALF		0x0010 /* Not used, just FYI */
200 #define ADVERTISE_1000_FULL		0x0020
201 #define ADVERTISE_2500_HALF		0x0040 /* Not used, just FYI */
202 #define ADVERTISE_2500_FULL		0x0080
203 
204 #define IGC_ALL_SPEED_DUPLEX_2500 ( \
205 	ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
206 	ADVERTISE_100_FULL | ADVERTISE_1000_FULL | ADVERTISE_2500_FULL)
207 
208 #define AUTONEG_ADVERTISE_SPEED_DEFAULT_2500	IGC_ALL_SPEED_DUPLEX_2500
209 
210 /* Interrupt Cause Read */
211 #define IGC_ICR_TXDW		BIT(0)	/* Transmit desc written back */
212 #define IGC_ICR_TXQE		BIT(1)	/* Transmit Queue empty */
213 #define IGC_ICR_LSC		BIT(2)	/* Link Status Change */
214 #define IGC_ICR_RXSEQ		BIT(3)	/* Rx sequence error */
215 #define IGC_ICR_RXDMT0		BIT(4)	/* Rx desc min. threshold (0) */
216 #define IGC_ICR_RXO		BIT(6)	/* Rx overrun */
217 #define IGC_ICR_RXT0		BIT(7)	/* Rx timer intr (ring 0) */
218 #define IGC_ICR_TS		BIT(19)	/* Time Sync Interrupt */
219 #define IGC_ICR_DRSTA		BIT(30)	/* Device Reset Asserted */
220 
221 /* If this bit asserted, the driver should claim the interrupt */
222 #define IGC_ICR_INT_ASSERTED	BIT(31)
223 
224 #define IGC_ICS_RXT0		IGC_ICR_RXT0 /* Rx timer intr */
225 
226 #define IMS_ENABLE_MASK ( \
227 	IGC_IMS_RXT0   |    \
228 	IGC_IMS_TXDW   |    \
229 	IGC_IMS_RXDMT0 |    \
230 	IGC_IMS_RXSEQ  |    \
231 	IGC_IMS_LSC)
232 
233 /* Interrupt Mask Set */
234 #define IGC_IMS_TXDW		IGC_ICR_TXDW	/* Tx desc written back */
235 #define IGC_IMS_RXSEQ		IGC_ICR_RXSEQ	/* Rx sequence error */
236 #define IGC_IMS_LSC		IGC_ICR_LSC	/* Link Status Change */
237 #define IGC_IMS_DOUTSYNC	IGC_ICR_DOUTSYNC /* NIC DMA out of sync */
238 #define IGC_IMS_DRSTA		IGC_ICR_DRSTA	/* Device Reset Asserted */
239 #define IGC_IMS_RXT0		IGC_ICR_RXT0	/* Rx timer intr */
240 #define IGC_IMS_RXDMT0		IGC_ICR_RXDMT0	/* Rx desc min. threshold */
241 #define IGC_IMS_TS		IGC_ICR_TS	/* Time Sync Interrupt */
242 
243 #define IGC_QVECTOR_MASK	0x7FFC		/* Q-vector mask */
244 #define IGC_ITR_VAL_MASK	0x04		/* ITR value mask */
245 
246 /* Interrupt Cause Set */
247 #define IGC_ICS_LSC		IGC_ICR_LSC       /* Link Status Change */
248 #define IGC_ICS_RXDMT0		IGC_ICR_RXDMT0    /* rx desc min. threshold */
249 
250 #define IGC_ICR_DOUTSYNC	0x10000000 /* NIC DMA out of sync */
251 #define IGC_EITR_CNT_IGNR	0x80000000 /* Don't reset counters on write */
252 #define IGC_IVAR_VALID		0x80
253 #define IGC_GPIE_NSICR		0x00000001
254 #define IGC_GPIE_MSIX_MODE	0x00000010
255 #define IGC_GPIE_EIAME		0x40000000
256 #define IGC_GPIE_PBA		0x80000000
257 
258 /* Receive Descriptor bit definitions */
259 #define IGC_RXD_STAT_DD		0x01    /* Descriptor Done */
260 
261 /* Transmit Descriptor bit definitions */
262 #define IGC_TXD_DTYP_D		0x00100000 /* Data Descriptor */
263 #define IGC_TXD_DTYP_C		0x00000000 /* Context Descriptor */
264 #define IGC_TXD_POPTS_IXSM	0x01       /* Insert IP checksum */
265 #define IGC_TXD_POPTS_TXSM	0x02       /* Insert TCP/UDP checksum */
266 #define IGC_TXD_CMD_EOP		0x01000000 /* End of Packet */
267 #define IGC_TXD_CMD_IC		0x04000000 /* Insert Checksum */
268 #define IGC_TXD_CMD_DEXT	0x20000000 /* Desc extension (0 = legacy) */
269 #define IGC_TXD_CMD_VLE		0x40000000 /* Add VLAN tag */
270 #define IGC_TXD_STAT_DD		0x00000001 /* Descriptor Done */
271 #define IGC_TXD_CMD_TCP		0x01000000 /* TCP packet */
272 #define IGC_TXD_CMD_IP		0x02000000 /* IP packet */
273 #define IGC_TXD_CMD_TSE		0x04000000 /* TCP Seg enable */
274 #define IGC_TXD_EXTCMD_TSTAMP	0x00000010 /* IEEE1588 Timestamp packet */
275 
276 /* IPSec Encrypt Enable */
277 #define IGC_ADVTXD_L4LEN_SHIFT	8  /* Adv ctxt L4LEN shift */
278 #define IGC_ADVTXD_MSS_SHIFT	16 /* Adv ctxt MSS shift */
279 
280 /* Transmit Control */
281 #define IGC_TCTL_EN		0x00000002 /* enable Tx */
282 #define IGC_TCTL_PSP		0x00000008 /* pad short packets */
283 #define IGC_TCTL_CT		0x00000ff0 /* collision threshold */
284 #define IGC_TCTL_COLD		0x003ff000 /* collision distance */
285 #define IGC_TCTL_RTLC		0x01000000 /* Re-transmit on late collision */
286 
287 /* Flow Control Constants */
288 #define FLOW_CONTROL_ADDRESS_LOW	0x00C28001
289 #define FLOW_CONTROL_ADDRESS_HIGH	0x00000100
290 #define FLOW_CONTROL_TYPE		0x8808
291 /* Enable XON frame transmission */
292 #define IGC_FCRTL_XONE			0x80000000
293 
294 /* Management Control */
295 #define IGC_MANC_RCV_TCO_EN	0x00020000 /* Receive TCO Packets Enabled */
296 #define IGC_MANC_BLK_PHY_RST_ON_IDE	0x00040000 /* Block phy resets */
297 
298 /* Receive Control */
299 #define IGC_RCTL_RST		0x00000001 /* Software reset */
300 #define IGC_RCTL_EN		0x00000002 /* enable */
301 #define IGC_RCTL_SBP		0x00000004 /* store bad packet */
302 #define IGC_RCTL_UPE		0x00000008 /* unicast promisc enable */
303 #define IGC_RCTL_MPE		0x00000010 /* multicast promisc enable */
304 #define IGC_RCTL_LPE		0x00000020 /* long packet enable */
305 #define IGC_RCTL_LBM_MAC	0x00000040 /* MAC loopback mode */
306 #define IGC_RCTL_LBM_TCVR	0x000000C0 /* tcvr loopback mode */
307 
308 #define IGC_RCTL_RDMTS_HALF	0x00000000 /* Rx desc min thresh size */
309 #define IGC_RCTL_BAM		0x00008000 /* broadcast enable */
310 
311 /* Split Replication Receive Control */
312 #define IGC_SRRCTL_TIMESTAMP		0x40000000
313 #define IGC_SRRCTL_TIMER1SEL(timer)	(((timer) & 0x3) << 14)
314 #define IGC_SRRCTL_TIMER0SEL(timer)	(((timer) & 0x3) << 17)
315 
316 /* Receive Descriptor bit definitions */
317 #define IGC_RXD_STAT_EOP	0x02	/* End of Packet */
318 #define IGC_RXD_STAT_IXSM	0x04	/* Ignore checksum */
319 #define IGC_RXD_STAT_UDPCS	0x10	/* UDP xsum calculated */
320 #define IGC_RXD_STAT_TCPCS	0x20	/* TCP xsum calculated */
321 
322 /* Advanced Receive Descriptor bit definitions */
323 #define IGC_RXDADV_STAT_TSIP	0x08000 /* timestamp in packet */
324 
325 #define IGC_RXDEXT_STATERR_L4E		0x20000000
326 #define IGC_RXDEXT_STATERR_IPE		0x40000000
327 #define IGC_RXDEXT_STATERR_RXE		0x80000000
328 
329 #define IGC_MRQC_RSS_FIELD_IPV4_TCP	0x00010000
330 #define IGC_MRQC_RSS_FIELD_IPV4		0x00020000
331 #define IGC_MRQC_RSS_FIELD_IPV6_TCP_EX	0x00040000
332 #define IGC_MRQC_RSS_FIELD_IPV6		0x00100000
333 #define IGC_MRQC_RSS_FIELD_IPV6_TCP	0x00200000
334 
335 /* Header split receive */
336 #define IGC_RFCTL_IPV6_EX_DIS	0x00010000
337 #define IGC_RFCTL_LEF		0x00040000
338 
339 #define IGC_RCTL_SZ_256		0x00030000 /* Rx buffer size 256 */
340 
341 #define IGC_RCTL_MO_SHIFT	12 /* multicast offset shift */
342 #define IGC_RCTL_CFIEN		0x00080000 /* canonical form enable */
343 #define IGC_RCTL_DPF		0x00400000 /* discard pause frames */
344 #define IGC_RCTL_PMCF		0x00800000 /* pass MAC control frames */
345 #define IGC_RCTL_SECRC		0x04000000 /* Strip Ethernet CRC */
346 
347 #define I225_RXPBSIZE_DEFAULT	0x000000A2 /* RXPBSIZE default */
348 #define I225_TXPBSIZE_DEFAULT	0x04000014 /* TXPBSIZE default */
349 #define IGC_RXPBS_CFG_TS_EN	0x80000000 /* Timestamp in Rx buffer */
350 
351 #define IGC_TXPBSIZE_TSN	0x04145145 /* 5k bytes buffer for each queue */
352 
353 #define IGC_DTXMXPKTSZ_TSN	0x19 /* 1600 bytes of max TX DMA packet size */
354 #define IGC_DTXMXPKTSZ_DEFAULT	0x98 /* 9728-byte Jumbo frames */
355 
356 /* Time Sync Interrupt Causes */
357 #define IGC_TSICR_SYS_WRAP	BIT(0) /* SYSTIM Wrap around. */
358 #define IGC_TSICR_TXTS		BIT(1) /* Transmit Timestamp. */
359 #define IGC_TSICR_TT0		BIT(3) /* Target Time 0 Trigger. */
360 #define IGC_TSICR_TT1		BIT(4) /* Target Time 1 Trigger. */
361 #define IGC_TSICR_AUTT0		BIT(5) /* Auxiliary Timestamp 0 Taken. */
362 #define IGC_TSICR_AUTT1		BIT(6) /* Auxiliary Timestamp 1 Taken. */
363 
364 #define IGC_TSICR_INTERRUPTS	IGC_TSICR_TXTS
365 
366 #define IGC_FTQF_VF_BP		0x00008000
367 #define IGC_FTQF_1588_TIME_STAMP	0x08000000
368 #define IGC_FTQF_MASK			0xF0000000
369 #define IGC_FTQF_MASK_PROTO_BP	0x10000000
370 
371 /* Time Sync Receive Control bit definitions */
372 #define IGC_TSYNCRXCTL_TYPE_MASK	0x0000000E  /* Rx type mask */
373 #define IGC_TSYNCRXCTL_TYPE_L2_V2	0x00
374 #define IGC_TSYNCRXCTL_TYPE_L4_V1	0x02
375 #define IGC_TSYNCRXCTL_TYPE_L2_L4_V2	0x04
376 #define IGC_TSYNCRXCTL_TYPE_ALL		0x08
377 #define IGC_TSYNCRXCTL_TYPE_EVENT_V2	0x0A
378 #define IGC_TSYNCRXCTL_ENABLED		0x00000010  /* enable Rx timestamping */
379 #define IGC_TSYNCRXCTL_SYSCFI		0x00000020  /* Sys clock frequency */
380 #define IGC_TSYNCRXCTL_RXSYNSIG		0x00000400  /* Sample RX tstamp in PHY sop */
381 
382 /* Time Sync Receive Configuration */
383 #define IGC_TSYNCRXCFG_PTP_V1_CTRLT_MASK	0x000000FF
384 #define IGC_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE	0x00
385 #define IGC_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE	0x01
386 
387 /* Immediate Interrupt Receive */
388 #define IGC_IMIR_CLEAR_MASK	0xF001FFFF /* IMIR Reg Clear Mask */
389 #define IGC_IMIR_PORT_BYPASS	0x20000 /* IMIR Port Bypass Bit */
390 #define IGC_IMIR_PRIORITY_SHIFT	29 /* IMIR Priority Shift */
391 #define IGC_IMIREXT_CLEAR_MASK	0x7FFFF /* IMIREXT Reg Clear Mask */
392 
393 /* Immediate Interrupt Receive Extended */
394 #define IGC_IMIREXT_CTRL_BP	0x00080000  /* Bypass check of ctrl bits */
395 #define IGC_IMIREXT_SIZE_BP	0x00001000  /* Packet size bypass */
396 
397 /* Time Sync Transmit Control bit definitions */
398 #define IGC_TSYNCTXCTL_TXTT_0			0x00000001  /* Tx timestamp reg 0 valid */
399 #define IGC_TSYNCTXCTL_ENABLED			0x00000010  /* enable Tx timestamping */
400 #define IGC_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK	0x0000F000  /* max delay */
401 #define IGC_TSYNCTXCTL_SYNC_COMP_ERR		0x20000000  /* sync err */
402 #define IGC_TSYNCTXCTL_SYNC_COMP		0x40000000  /* sync complete */
403 #define IGC_TSYNCTXCTL_START_SYNC		0x80000000  /* initiate sync */
404 #define IGC_TSYNCTXCTL_TXSYNSIG			0x00000020  /* Sample TX tstamp in PHY sop */
405 
406 /* Transmit Scheduling */
407 #define IGC_TQAVCTRL_TRANSMIT_MODE_TSN	0x00000001
408 #define IGC_TQAVCTRL_ENHANCED_QAV	0x00000008
409 
410 #define IGC_TXQCTL_QUEUE_MODE_LAUNCHT	0x00000001
411 #define IGC_TXQCTL_STRICT_CYCLE		0x00000002
412 #define IGC_TXQCTL_STRICT_END		0x00000004
413 
414 /* Receive Checksum Control */
415 #define IGC_RXCSUM_CRCOFL	0x00000800   /* CRC32 offload enable */
416 #define IGC_RXCSUM_PCSD		0x00002000   /* packet checksum disabled */
417 
418 /* GPY211 - I225 defines */
419 #define GPY_MMD_MASK		0xFFFF0000
420 #define GPY_MMD_SHIFT		16
421 #define GPY_REG_MASK		0x0000FFFF
422 
423 #define IGC_MMDAC_FUNC_DATA	0x4000 /* Data, no post increment */
424 
425 /* MAC definitions */
426 #define IGC_FACTPS_MNGCG	0x20000000
427 #define IGC_FWSM_MODE_MASK	0xE
428 #define IGC_FWSM_MODE_SHIFT	1
429 
430 /* Management Control */
431 #define IGC_MANC_SMBUS_EN	0x00000001 /* SMBus Enabled - RO */
432 #define IGC_MANC_ASF_EN		0x00000002 /* ASF Enabled - RO */
433 
434 /* PHY */
435 #define PHY_REVISION_MASK	0xFFFFFFF0
436 #define MAX_PHY_REG_ADDRESS	0x1F  /* 5 bit address bus (0-0x1F) */
437 #define IGC_GEN_POLL_TIMEOUT	1920
438 
439 /* PHY Control Register */
440 #define MII_CR_FULL_DUPLEX	0x0100  /* FDX =1, half duplex =0 */
441 #define MII_CR_RESTART_AUTO_NEG	0x0200  /* Restart auto negotiation */
442 #define MII_CR_POWER_DOWN	0x0800  /* Power down */
443 #define MII_CR_AUTO_NEG_EN	0x1000  /* Auto Neg Enable */
444 #define MII_CR_LOOPBACK		0x4000  /* 0 = normal, 1 = loopback */
445 #define MII_CR_RESET		0x8000  /* 0 = normal, 1 = PHY reset */
446 #define MII_CR_SPEED_1000	0x0040
447 #define MII_CR_SPEED_100	0x2000
448 #define MII_CR_SPEED_10		0x0000
449 
450 /* PHY Status Register */
451 #define MII_SR_LINK_STATUS	0x0004 /* Link Status 1 = link */
452 #define MII_SR_AUTONEG_COMPLETE	0x0020 /* Auto Neg Complete */
453 #define IGC_PHY_RST_COMP	0x0100 /* Internal PHY reset completion */
454 
455 /* PHY 1000 MII Register/Bit Definitions */
456 /* PHY Registers defined by IEEE */
457 #define PHY_CONTROL		0x00 /* Control Register */
458 #define PHY_STATUS		0x01 /* Status Register */
459 #define PHY_ID1			0x02 /* Phy Id Reg (word 1) */
460 #define PHY_ID2			0x03 /* Phy Id Reg (word 2) */
461 #define PHY_AUTONEG_ADV		0x04 /* Autoneg Advertisement */
462 #define PHY_LP_ABILITY		0x05 /* Link Partner Ability (Base Page) */
463 #define PHY_1000T_CTRL		0x09 /* 1000Base-T Control Reg */
464 #define PHY_1000T_STATUS	0x0A /* 1000Base-T Status Reg */
465 
466 /* Bit definitions for valid PHY IDs. I = Integrated E = External */
467 #define I225_I_PHY_ID		0x67C9DC00
468 
469 /* MDI Control */
470 #define IGC_MDIC_DATA_MASK	0x0000FFFF
471 #define IGC_MDIC_REG_MASK	0x001F0000
472 #define IGC_MDIC_REG_SHIFT	16
473 #define IGC_MDIC_PHY_MASK	0x03E00000
474 #define IGC_MDIC_PHY_SHIFT	21
475 #define IGC_MDIC_OP_WRITE	0x04000000
476 #define IGC_MDIC_OP_READ	0x08000000
477 #define IGC_MDIC_READY		0x10000000
478 #define IGC_MDIC_INT_EN		0x20000000
479 #define IGC_MDIC_ERROR		0x40000000
480 
481 #define IGC_N0_QUEUE		-1
482 
483 #define IGC_MAX_MAC_HDR_LEN	127
484 #define IGC_MAX_NETWORK_HDR_LEN	511
485 
486 #define IGC_VLANPQF_QSEL(_n, q_idx) ((q_idx) << ((_n) * 4))
487 #define IGC_VLANPQF_VALID(_n)	(0x1 << (3 + (_n) * 4))
488 #define IGC_VLANPQF_QUEUE_MASK	0x03
489 
490 #define IGC_ADVTXD_MACLEN_SHIFT		9  /* Adv ctxt desc mac len shift */
491 #define IGC_ADVTXD_TUCMD_IPV4		0x00000400  /* IP Packet Type:1=IPv4 */
492 #define IGC_ADVTXD_TUCMD_L4T_TCP	0x00000800  /* L4 Packet Type of TCP */
493 #define IGC_ADVTXD_TUCMD_L4T_SCTP	0x00001000 /* L4 packet TYPE of SCTP */
494 
495 /* Maximum size of the MTA register table in all supported adapters */
496 #define MAX_MTA_REG			128
497 
498 /* EEE defines */
499 #define IGC_IPCNFG_EEE_2_5G_AN		0x00000010 /* IPCNFG EEE Ena 2.5G AN */
500 #define IGC_IPCNFG_EEE_1G_AN		0x00000008 /* IPCNFG EEE Ena 1G AN */
501 #define IGC_IPCNFG_EEE_100M_AN		0x00000004 /* IPCNFG EEE Ena 100M AN */
502 #define IGC_EEER_EEE_NEG		0x20000000 /* EEE capability nego */
503 #define IGC_EEER_TX_LPI_EN		0x00010000 /* EEER Tx LPI Enable */
504 #define IGC_EEER_RX_LPI_EN		0x00020000 /* EEER Rx LPI Enable */
505 #define IGC_EEER_LPI_FC			0x00040000 /* EEER Ena on Flow Cntrl */
506 #define IGC_EEE_SU_LPI_CLK_STP		0x00800000 /* EEE LPI Clock Stop */
507 
508 /* LTR defines */
509 #define IGC_LTRC_EEEMS_EN		0x00000020 /* Enable EEE LTR max send */
510 #define IGC_RXPBS_SIZE_I225_MASK	0x0000003F /* Rx packet buffer size */
511 #define IGC_TW_SYSTEM_1000_MASK		0x000000FF
512 /* Minimum time for 100BASE-T where no data will be transmit following move out
513  * of EEE LPI Tx state
514  */
515 #define IGC_TW_SYSTEM_100_MASK		0x0000FF00
516 #define IGC_TW_SYSTEM_100_SHIFT		8
517 #define IGC_DMACR_DMAC_EN		0x80000000 /* Enable DMA Coalescing */
518 #define IGC_DMACR_DMACTHR_MASK		0x00FF0000
519 #define IGC_DMACR_DMACTHR_SHIFT		16
520 /* Reg val to set scale to 1024 nsec */
521 #define IGC_LTRMINV_SCALE_1024		2
522 /* Reg val to set scale to 32768 nsec */
523 #define IGC_LTRMINV_SCALE_32768		3
524 /* Reg val to set scale to 1024 nsec */
525 #define IGC_LTRMAXV_SCALE_1024		2
526 /* Reg val to set scale to 32768 nsec */
527 #define IGC_LTRMAXV_SCALE_32768		3
528 #define IGC_LTRMINV_LTRV_MASK		0x000003FF /* LTR minimum value */
529 #define IGC_LTRMAXV_LTRV_MASK		0x000003FF /* LTR maximum value */
530 #define IGC_LTRMINV_LSNP_REQ		0x00008000 /* LTR Snoop Requirement */
531 #define IGC_LTRMINV_SCALE_SHIFT		10
532 #define IGC_LTRMAXV_LSNP_REQ		0x00008000 /* LTR Snoop Requirement */
533 #define IGC_LTRMAXV_SCALE_SHIFT		10
534 
535 #endif /* _IGC_DEFINES_H_ */
536