1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #include <linux/delay.h> 5 6 #include "igc_hw.h" 7 #include "igc_i225.h" 8 #include "igc_mac.h" 9 #include "igc_base.h" 10 #include "igc.h" 11 12 /** 13 * igc_set_pcie_completion_timeout - set pci-e completion timeout 14 * @hw: pointer to the HW structure 15 */ 16 static s32 igc_set_pcie_completion_timeout(struct igc_hw *hw) 17 { 18 u32 gcr = rd32(IGC_GCR); 19 u16 pcie_devctl2; 20 s32 ret_val = 0; 21 22 /* only take action if timeout value is defaulted to 0 */ 23 if (gcr & IGC_GCR_CMPL_TMOUT_MASK) 24 goto out; 25 26 /* if capabilities version is type 1 we can write the 27 * timeout of 10ms to 200ms through the GCR register 28 */ 29 if (!(gcr & IGC_GCR_CAP_VER2)) { 30 gcr |= IGC_GCR_CMPL_TMOUT_10ms; 31 goto out; 32 } 33 34 /* for version 2 capabilities we need to write the config space 35 * directly in order to set the completion timeout value for 36 * 16ms to 55ms 37 */ 38 ret_val = igc_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 39 &pcie_devctl2); 40 if (ret_val) 41 goto out; 42 43 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 44 45 ret_val = igc_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 46 &pcie_devctl2); 47 out: 48 /* disable completion timeout resend */ 49 gcr &= ~IGC_GCR_CMPL_TMOUT_RESEND; 50 51 wr32(IGC_GCR, gcr); 52 53 return ret_val; 54 } 55 56 /** 57 * igc_check_for_link_base - Check for link 58 * @hw: pointer to the HW structure 59 * 60 * If sgmii is enabled, then use the pcs register to determine link, otherwise 61 * use the generic interface for determining link. 62 */ 63 static s32 igc_check_for_link_base(struct igc_hw *hw) 64 { 65 s32 ret_val = 0; 66 67 ret_val = igc_check_for_copper_link(hw); 68 69 return ret_val; 70 } 71 72 /** 73 * igc_reset_hw_base - Reset hardware 74 * @hw: pointer to the HW structure 75 * 76 * This resets the hardware into a known state. This is a 77 * function pointer entry point called by the api module. 78 */ 79 static s32 igc_reset_hw_base(struct igc_hw *hw) 80 { 81 s32 ret_val; 82 u32 ctrl; 83 84 /* Prevent the PCI-E bus from sticking if there is no TLP connection 85 * on the last TLP read/write transaction when MAC is reset. 86 */ 87 ret_val = igc_disable_pcie_master(hw); 88 if (ret_val) 89 hw_dbg("PCI-E Master disable polling has failed.\n"); 90 91 /* set the completion timeout for interface */ 92 ret_val = igc_set_pcie_completion_timeout(hw); 93 if (ret_val) 94 hw_dbg("PCI-E Set completion timeout has failed.\n"); 95 96 hw_dbg("Masking off all interrupts\n"); 97 wr32(IGC_IMC, 0xffffffff); 98 99 wr32(IGC_RCTL, 0); 100 wr32(IGC_TCTL, IGC_TCTL_PSP); 101 wrfl(); 102 103 usleep_range(10000, 20000); 104 105 ctrl = rd32(IGC_CTRL); 106 107 hw_dbg("Issuing a global reset to MAC\n"); 108 wr32(IGC_CTRL, ctrl | IGC_CTRL_RST); 109 110 ret_val = igc_get_auto_rd_done(hw); 111 if (ret_val) { 112 /* When auto config read does not complete, do not 113 * return with an error. This can happen in situations 114 * where there is no eeprom and prevents getting link. 115 */ 116 hw_dbg("Auto Read Done did not complete\n"); 117 } 118 119 /* Clear any pending interrupt events. */ 120 wr32(IGC_IMC, 0xffffffff); 121 rd32(IGC_ICR); 122 123 return ret_val; 124 } 125 126 /** 127 * igc_get_phy_id_base - Retrieve PHY addr and id 128 * @hw: pointer to the HW structure 129 * 130 * Retrieves the PHY address and ID for both PHY's which do and do not use 131 * sgmi interface. 132 */ 133 static s32 igc_get_phy_id_base(struct igc_hw *hw) 134 { 135 s32 ret_val = 0; 136 137 ret_val = igc_get_phy_id(hw); 138 139 return ret_val; 140 } 141 142 /** 143 * igc_init_nvm_params_base - Init NVM func ptrs. 144 * @hw: pointer to the HW structure 145 */ 146 static s32 igc_init_nvm_params_base(struct igc_hw *hw) 147 { 148 struct igc_nvm_info *nvm = &hw->nvm; 149 u32 eecd = rd32(IGC_EECD); 150 u16 size; 151 152 size = (u16)((eecd & IGC_EECD_SIZE_EX_MASK) >> 153 IGC_EECD_SIZE_EX_SHIFT); 154 155 /* Added to a constant, "size" becomes the left-shift value 156 * for setting word_size. 157 */ 158 size += NVM_WORD_SIZE_BASE_SHIFT; 159 160 /* Just in case size is out of range, cap it to the largest 161 * EEPROM size supported 162 */ 163 if (size > 15) 164 size = 15; 165 166 nvm->word_size = BIT(size); 167 nvm->opcode_bits = 8; 168 nvm->delay_usec = 1; 169 170 nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8; 171 nvm->address_bits = eecd & IGC_EECD_ADDR_BITS ? 172 16 : 8; 173 174 if (nvm->word_size == BIT(15)) 175 nvm->page_size = 128; 176 177 return 0; 178 } 179 180 /** 181 * igc_setup_copper_link_base - Configure copper link settings 182 * @hw: pointer to the HW structure 183 * 184 * Configures the link for auto-neg or forced speed and duplex. Then we check 185 * for link, once link is established calls to configure collision distance 186 * and flow control are called. 187 */ 188 static s32 igc_setup_copper_link_base(struct igc_hw *hw) 189 { 190 s32 ret_val = 0; 191 u32 ctrl; 192 193 ctrl = rd32(IGC_CTRL); 194 ctrl |= IGC_CTRL_SLU; 195 ctrl &= ~(IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX); 196 wr32(IGC_CTRL, ctrl); 197 198 ret_val = igc_setup_copper_link(hw); 199 200 return ret_val; 201 } 202 203 /** 204 * igc_init_mac_params_base - Init MAC func ptrs. 205 * @hw: pointer to the HW structure 206 */ 207 static s32 igc_init_mac_params_base(struct igc_hw *hw) 208 { 209 struct igc_dev_spec_base *dev_spec = &hw->dev_spec._base; 210 struct igc_mac_info *mac = &hw->mac; 211 212 /* Set mta register count */ 213 mac->mta_reg_count = 128; 214 mac->rar_entry_count = IGC_RAR_ENTRIES; 215 216 /* reset */ 217 mac->ops.reset_hw = igc_reset_hw_base; 218 219 mac->ops.acquire_swfw_sync = igc_acquire_swfw_sync_i225; 220 mac->ops.release_swfw_sync = igc_release_swfw_sync_i225; 221 222 /* Allow a single clear of the SW semaphore on I225 */ 223 if (mac->type == igc_i225) 224 dev_spec->clear_semaphore_once = true; 225 226 /* physical interface link setup */ 227 mac->ops.setup_physical_interface = igc_setup_copper_link_base; 228 229 return 0; 230 } 231 232 /** 233 * igc_init_phy_params_base - Init PHY func ptrs. 234 * @hw: pointer to the HW structure 235 */ 236 static s32 igc_init_phy_params_base(struct igc_hw *hw) 237 { 238 struct igc_phy_info *phy = &hw->phy; 239 s32 ret_val = 0; 240 241 if (hw->phy.media_type != igc_media_type_copper) { 242 phy->type = igc_phy_none; 243 goto out; 244 } 245 246 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT_2500; 247 phy->reset_delay_us = 100; 248 249 /* set lan id */ 250 hw->bus.func = (rd32(IGC_STATUS) & IGC_STATUS_FUNC_MASK) >> 251 IGC_STATUS_FUNC_SHIFT; 252 253 /* Make sure the PHY is in a good state. Several people have reported 254 * firmware leaving the PHY's page select register set to something 255 * other than the default of zero, which causes the PHY ID read to 256 * access something other than the intended register. 257 */ 258 ret_val = hw->phy.ops.reset(hw); 259 if (ret_val) { 260 hw_dbg("Error resetting the PHY.\n"); 261 goto out; 262 } 263 264 ret_val = igc_get_phy_id_base(hw); 265 if (ret_val) 266 return ret_val; 267 268 igc_check_for_link_base(hw); 269 270 /* Verify phy id and set remaining function pointers */ 271 switch (phy->id) { 272 case I225_I_PHY_ID: 273 phy->type = igc_phy_i225; 274 break; 275 default: 276 ret_val = -IGC_ERR_PHY; 277 goto out; 278 } 279 280 out: 281 return ret_val; 282 } 283 284 static s32 igc_get_invariants_base(struct igc_hw *hw) 285 { 286 struct igc_mac_info *mac = &hw->mac; 287 s32 ret_val = 0; 288 289 switch (hw->device_id) { 290 case IGC_DEV_ID_I225_LM: 291 case IGC_DEV_ID_I225_V: 292 mac->type = igc_i225; 293 break; 294 default: 295 return -IGC_ERR_MAC_INIT; 296 } 297 298 hw->phy.media_type = igc_media_type_copper; 299 300 /* mac initialization and operations */ 301 ret_val = igc_init_mac_params_base(hw); 302 if (ret_val) 303 goto out; 304 305 /* NVM initialization */ 306 ret_val = igc_init_nvm_params_base(hw); 307 switch (hw->mac.type) { 308 case igc_i225: 309 ret_val = igc_init_nvm_params_i225(hw); 310 break; 311 default: 312 break; 313 } 314 315 /* setup PHY parameters */ 316 ret_val = igc_init_phy_params_base(hw); 317 if (ret_val) 318 goto out; 319 320 out: 321 return ret_val; 322 } 323 324 /** 325 * igc_acquire_phy_base - Acquire rights to access PHY 326 * @hw: pointer to the HW structure 327 * 328 * Acquire access rights to the correct PHY. This is a 329 * function pointer entry point called by the api module. 330 */ 331 static s32 igc_acquire_phy_base(struct igc_hw *hw) 332 { 333 u16 mask = IGC_SWFW_PHY0_SM; 334 335 return hw->mac.ops.acquire_swfw_sync(hw, mask); 336 } 337 338 /** 339 * igc_release_phy_base - Release rights to access PHY 340 * @hw: pointer to the HW structure 341 * 342 * A wrapper to release access rights to the correct PHY. This is a 343 * function pointer entry point called by the api module. 344 */ 345 static void igc_release_phy_base(struct igc_hw *hw) 346 { 347 u16 mask = IGC_SWFW_PHY0_SM; 348 349 hw->mac.ops.release_swfw_sync(hw, mask); 350 } 351 352 /** 353 * igc_get_link_up_info_base - Get link speed/duplex info 354 * @hw: pointer to the HW structure 355 * @speed: stores the current speed 356 * @duplex: stores the current duplex 357 * 358 * This is a wrapper function, if using the serial gigabit media independent 359 * interface, use PCS to retrieve the link speed and duplex information. 360 * Otherwise, use the generic function to get the link speed and duplex info. 361 */ 362 static s32 igc_get_link_up_info_base(struct igc_hw *hw, u16 *speed, 363 u16 *duplex) 364 { 365 s32 ret_val; 366 367 ret_val = igc_get_speed_and_duplex_copper(hw, speed, duplex); 368 369 return ret_val; 370 } 371 372 /** 373 * igc_init_hw_base - Initialize hardware 374 * @hw: pointer to the HW structure 375 * 376 * This inits the hardware readying it for operation. 377 */ 378 static s32 igc_init_hw_base(struct igc_hw *hw) 379 { 380 struct igc_mac_info *mac = &hw->mac; 381 u16 i, rar_count = mac->rar_entry_count; 382 s32 ret_val = 0; 383 384 /* Setup the receive address */ 385 igc_init_rx_addrs(hw, rar_count); 386 387 /* Zero out the Multicast HASH table */ 388 hw_dbg("Zeroing the MTA\n"); 389 for (i = 0; i < mac->mta_reg_count; i++) 390 array_wr32(IGC_MTA, i, 0); 391 392 /* Zero out the Unicast HASH table */ 393 hw_dbg("Zeroing the UTA\n"); 394 for (i = 0; i < mac->uta_reg_count; i++) 395 array_wr32(IGC_UTA, i, 0); 396 397 /* Setup link and flow control */ 398 ret_val = igc_setup_link(hw); 399 400 /* Clear all of the statistics registers (clear on read). It is 401 * important that we do this after we have tried to establish link 402 * because the symbol error count will increment wildly if there 403 * is no link. 404 */ 405 igc_clear_hw_cntrs_base(hw); 406 407 return ret_val; 408 } 409 410 /** 411 * igc_read_mac_addr_base - Read device MAC address 412 * @hw: pointer to the HW structure 413 */ 414 static s32 igc_read_mac_addr_base(struct igc_hw *hw) 415 { 416 s32 ret_val = 0; 417 418 ret_val = igc_read_mac_addr(hw); 419 420 return ret_val; 421 } 422 423 /** 424 * igc_power_down_phy_copper_base - Remove link during PHY power down 425 * @hw: pointer to the HW structure 426 * 427 * In the case of a PHY power down to save power, or to turn off link during a 428 * driver unload, or wake on lan is not enabled, remove the link. 429 */ 430 void igc_power_down_phy_copper_base(struct igc_hw *hw) 431 { 432 /* If the management interface is not enabled, then power down */ 433 if (!(igc_enable_mng_pass_thru(hw) || igc_check_reset_block(hw))) 434 igc_power_down_phy_copper(hw); 435 } 436 437 /** 438 * igc_rx_fifo_flush_base - Clean rx fifo after Rx enable 439 * @hw: pointer to the HW structure 440 * 441 * After Rx enable, if manageability is enabled then there is likely some 442 * bad data at the start of the fifo and possibly in the DMA fifo. This 443 * function clears the fifos and flushes any packets that came in as rx was 444 * being enabled. 445 */ 446 void igc_rx_fifo_flush_base(struct igc_hw *hw) 447 { 448 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 449 int i, ms_wait; 450 451 /* disable IPv6 options as per hardware errata */ 452 rfctl = rd32(IGC_RFCTL); 453 rfctl |= IGC_RFCTL_IPV6_EX_DIS; 454 wr32(IGC_RFCTL, rfctl); 455 456 if (!(rd32(IGC_MANC) & IGC_MANC_RCV_TCO_EN)) 457 return; 458 459 /* Disable all Rx queues */ 460 for (i = 0; i < 4; i++) { 461 rxdctl[i] = rd32(IGC_RXDCTL(i)); 462 wr32(IGC_RXDCTL(i), 463 rxdctl[i] & ~IGC_RXDCTL_QUEUE_ENABLE); 464 } 465 /* Poll all queues to verify they have shut down */ 466 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 467 usleep_range(1000, 2000); 468 rx_enabled = 0; 469 for (i = 0; i < 4; i++) 470 rx_enabled |= rd32(IGC_RXDCTL(i)); 471 if (!(rx_enabled & IGC_RXDCTL_QUEUE_ENABLE)) 472 break; 473 } 474 475 if (ms_wait == 10) 476 pr_debug("Queue disable timed out after 10ms\n"); 477 478 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 479 * incoming packets are rejected. Set enable and wait 2ms so that 480 * any packet that was coming in as RCTL.EN was set is flushed 481 */ 482 wr32(IGC_RFCTL, rfctl & ~IGC_RFCTL_LEF); 483 484 rlpml = rd32(IGC_RLPML); 485 wr32(IGC_RLPML, 0); 486 487 rctl = rd32(IGC_RCTL); 488 temp_rctl = rctl & ~(IGC_RCTL_EN | IGC_RCTL_SBP); 489 temp_rctl |= IGC_RCTL_LPE; 490 491 wr32(IGC_RCTL, temp_rctl); 492 wr32(IGC_RCTL, temp_rctl | IGC_RCTL_EN); 493 wrfl(); 494 usleep_range(2000, 3000); 495 496 /* Enable Rx queues that were previously enabled and restore our 497 * previous state 498 */ 499 for (i = 0; i < 4; i++) 500 wr32(IGC_RXDCTL(i), rxdctl[i]); 501 wr32(IGC_RCTL, rctl); 502 wrfl(); 503 504 wr32(IGC_RLPML, rlpml); 505 wr32(IGC_RFCTL, rfctl); 506 507 /* Flush receive errors generated by workaround */ 508 rd32(IGC_ROC); 509 rd32(IGC_RNBC); 510 rd32(IGC_MPC); 511 } 512 513 static struct igc_mac_operations igc_mac_ops_base = { 514 .init_hw = igc_init_hw_base, 515 .check_for_link = igc_check_for_link_base, 516 .rar_set = igc_rar_set, 517 .read_mac_addr = igc_read_mac_addr_base, 518 .get_speed_and_duplex = igc_get_link_up_info_base, 519 }; 520 521 static const struct igc_phy_operations igc_phy_ops_base = { 522 .acquire = igc_acquire_phy_base, 523 .release = igc_release_phy_base, 524 .reset = igc_phy_hw_reset, 525 .read_reg = igc_read_phy_reg_gpy, 526 .write_reg = igc_write_phy_reg_gpy, 527 }; 528 529 const struct igc_info igc_base_info = { 530 .get_invariants = igc_get_invariants_base, 531 .mac_ops = &igc_mac_ops_base, 532 .phy_ops = &igc_phy_ops_base, 533 }; 534