1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #include <linux/delay.h> 5 6 #include "igc_hw.h" 7 #include "igc_i225.h" 8 #include "igc_mac.h" 9 #include "igc_base.h" 10 #include "igc.h" 11 12 /** 13 * igc_reset_hw_base - Reset hardware 14 * @hw: pointer to the HW structure 15 * 16 * This resets the hardware into a known state. This is a 17 * function pointer entry point called by the api module. 18 */ 19 static s32 igc_reset_hw_base(struct igc_hw *hw) 20 { 21 s32 ret_val; 22 u32 ctrl; 23 24 /* Prevent the PCI-E bus from sticking if there is no TLP connection 25 * on the last TLP read/write transaction when MAC is reset. 26 */ 27 ret_val = igc_disable_pcie_master(hw); 28 if (ret_val) 29 hw_dbg("PCI-E Master disable polling has failed\n"); 30 31 hw_dbg("Masking off all interrupts\n"); 32 wr32(IGC_IMC, 0xffffffff); 33 34 wr32(IGC_RCTL, 0); 35 wr32(IGC_TCTL, IGC_TCTL_PSP); 36 wrfl(); 37 38 usleep_range(10000, 20000); 39 40 ctrl = rd32(IGC_CTRL); 41 42 hw_dbg("Issuing a global reset to MAC\n"); 43 wr32(IGC_CTRL, ctrl | IGC_CTRL_RST); 44 45 ret_val = igc_get_auto_rd_done(hw); 46 if (ret_val) { 47 /* When auto config read does not complete, do not 48 * return with an error. This can happen in situations 49 * where there is no eeprom and prevents getting link. 50 */ 51 hw_dbg("Auto Read Done did not complete\n"); 52 } 53 54 /* Clear any pending interrupt events. */ 55 wr32(IGC_IMC, 0xffffffff); 56 rd32(IGC_ICR); 57 58 return ret_val; 59 } 60 61 /** 62 * igc_init_nvm_params_base - Init NVM func ptrs. 63 * @hw: pointer to the HW structure 64 */ 65 static s32 igc_init_nvm_params_base(struct igc_hw *hw) 66 { 67 struct igc_nvm_info *nvm = &hw->nvm; 68 u32 eecd = rd32(IGC_EECD); 69 u16 size; 70 71 /* failed to read reg and got all F's */ 72 if (!(~eecd)) 73 return -ENXIO; 74 75 size = FIELD_GET(IGC_EECD_SIZE_EX_MASK, eecd); 76 77 /* Added to a constant, "size" becomes the left-shift value 78 * for setting word_size. 79 */ 80 size += NVM_WORD_SIZE_BASE_SHIFT; 81 82 /* Just in case size is out of range, cap it to the largest 83 * EEPROM size supported 84 */ 85 if (size > 15) 86 size = 15; 87 88 nvm->type = igc_nvm_eeprom_spi; 89 nvm->word_size = BIT(size); 90 nvm->opcode_bits = 8; 91 nvm->delay_usec = 1; 92 93 nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8; 94 nvm->address_bits = eecd & IGC_EECD_ADDR_BITS ? 95 16 : 8; 96 97 if (nvm->word_size == BIT(15)) 98 nvm->page_size = 128; 99 100 return 0; 101 } 102 103 /** 104 * igc_setup_copper_link_base - Configure copper link settings 105 * @hw: pointer to the HW structure 106 * 107 * Configures the link for auto-neg or forced speed and duplex. Then we check 108 * for link, once link is established calls to configure collision distance 109 * and flow control are called. 110 */ 111 static s32 igc_setup_copper_link_base(struct igc_hw *hw) 112 { 113 s32 ret_val = 0; 114 u32 ctrl; 115 116 ctrl = rd32(IGC_CTRL); 117 ctrl &= ~(IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX | 118 IGC_CTRL_SPEED_MASK | IGC_CTRL_FD); 119 120 if (hw->mac.autoneg_enabled) { 121 ctrl |= IGC_CTRL_SLU; 122 wr32(IGC_CTRL, ctrl); 123 ret_val = igc_setup_copper_link(hw); 124 } else { 125 ctrl |= IGC_CTRL_SLU | IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX; 126 127 switch (hw->mac.forced_speed_duplex) { 128 case IGC_FORCED_10H: 129 ctrl |= IGC_CTRL_SPEED_10; 130 break; 131 case IGC_FORCED_10F: 132 ctrl |= IGC_CTRL_SPEED_10 | IGC_CTRL_FD; 133 break; 134 case IGC_FORCED_100H: 135 ctrl |= IGC_CTRL_SPEED_100; 136 break; 137 case IGC_FORCED_100F: 138 ctrl |= IGC_CTRL_SPEED_100 | IGC_CTRL_FD; 139 break; 140 default: 141 return -IGC_ERR_CONFIG; 142 } 143 wr32(IGC_CTRL, ctrl); 144 ret_val = igc_setup_copper_link(hw); 145 } 146 147 return ret_val; 148 } 149 150 /** 151 * igc_init_mac_params_base - Init MAC func ptrs. 152 * @hw: pointer to the HW structure 153 */ 154 static s32 igc_init_mac_params_base(struct igc_hw *hw) 155 { 156 struct igc_dev_spec_base *dev_spec = &hw->dev_spec._base; 157 struct igc_mac_info *mac = &hw->mac; 158 159 /* Set mta register count */ 160 mac->mta_reg_count = 128; 161 mac->rar_entry_count = IGC_RAR_ENTRIES; 162 163 /* reset */ 164 mac->ops.reset_hw = igc_reset_hw_base; 165 166 mac->ops.acquire_swfw_sync = igc_acquire_swfw_sync_i225; 167 mac->ops.release_swfw_sync = igc_release_swfw_sync_i225; 168 169 /* Allow a single clear of the SW semaphore on I225 */ 170 if (mac->type == igc_i225) 171 dev_spec->clear_semaphore_once = true; 172 173 /* physical interface link setup */ 174 mac->ops.setup_physical_interface = igc_setup_copper_link_base; 175 176 return 0; 177 } 178 179 /** 180 * igc_init_phy_params_base - Init PHY func ptrs. 181 * @hw: pointer to the HW structure 182 */ 183 static s32 igc_init_phy_params_base(struct igc_hw *hw) 184 { 185 struct igc_phy_info *phy = &hw->phy; 186 s32 ret_val = 0; 187 188 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT_2500; 189 phy->reset_delay_us = 100; 190 191 /* set lan id */ 192 hw->bus.func = FIELD_GET(IGC_STATUS_FUNC_MASK, rd32(IGC_STATUS)); 193 194 /* Make sure the PHY is in a good state. Several people have reported 195 * firmware leaving the PHY's page select register set to something 196 * other than the default of zero, which causes the PHY ID read to 197 * access something other than the intended register. 198 */ 199 ret_val = hw->phy.ops.reset(hw); 200 if (ret_val) { 201 hw_dbg("Error resetting the PHY\n"); 202 goto out; 203 } 204 205 ret_val = igc_get_phy_id(hw); 206 if (ret_val) 207 return ret_val; 208 209 igc_check_for_copper_link(hw); 210 211 out: 212 return ret_val; 213 } 214 215 static s32 igc_get_invariants_base(struct igc_hw *hw) 216 { 217 struct igc_mac_info *mac = &hw->mac; 218 s32 ret_val = 0; 219 220 switch (hw->device_id) { 221 case IGC_DEV_ID_I225_LM: 222 case IGC_DEV_ID_I225_V: 223 case IGC_DEV_ID_I225_I: 224 case IGC_DEV_ID_I220_V: 225 case IGC_DEV_ID_I225_K: 226 case IGC_DEV_ID_I225_K2: 227 case IGC_DEV_ID_I226_K: 228 case IGC_DEV_ID_I225_LMVP: 229 case IGC_DEV_ID_I226_LMVP: 230 case IGC_DEV_ID_I225_IT: 231 case IGC_DEV_ID_I226_LM: 232 case IGC_DEV_ID_I226_V: 233 case IGC_DEV_ID_I226_IT: 234 case IGC_DEV_ID_I221_V: 235 case IGC_DEV_ID_I226_BLANK_NVM: 236 case IGC_DEV_ID_I225_BLANK_NVM: 237 mac->type = igc_i225; 238 break; 239 default: 240 return -IGC_ERR_MAC_INIT; 241 } 242 243 hw->phy.media_type = igc_media_type_copper; 244 245 /* mac initialization and operations */ 246 ret_val = igc_init_mac_params_base(hw); 247 if (ret_val) 248 goto out; 249 250 /* NVM initialization */ 251 ret_val = igc_init_nvm_params_base(hw); 252 if (ret_val) 253 goto out; 254 switch (hw->mac.type) { 255 case igc_i225: 256 ret_val = igc_init_nvm_params_i225(hw); 257 break; 258 default: 259 break; 260 } 261 262 /* setup PHY parameters */ 263 ret_val = igc_init_phy_params_base(hw); 264 if (ret_val) 265 goto out; 266 267 out: 268 return ret_val; 269 } 270 271 /** 272 * igc_acquire_phy_base - Acquire rights to access PHY 273 * @hw: pointer to the HW structure 274 * 275 * Acquire access rights to the correct PHY. This is a 276 * function pointer entry point called by the api module. 277 */ 278 static s32 igc_acquire_phy_base(struct igc_hw *hw) 279 { 280 u16 mask = IGC_SWFW_PHY0_SM; 281 282 return hw->mac.ops.acquire_swfw_sync(hw, mask); 283 } 284 285 /** 286 * igc_release_phy_base - Release rights to access PHY 287 * @hw: pointer to the HW structure 288 * 289 * A wrapper to release access rights to the correct PHY. This is a 290 * function pointer entry point called by the api module. 291 */ 292 static void igc_release_phy_base(struct igc_hw *hw) 293 { 294 u16 mask = IGC_SWFW_PHY0_SM; 295 296 hw->mac.ops.release_swfw_sync(hw, mask); 297 } 298 299 /** 300 * igc_init_hw_base - Initialize hardware 301 * @hw: pointer to the HW structure 302 * 303 * This inits the hardware readying it for operation. 304 */ 305 static s32 igc_init_hw_base(struct igc_hw *hw) 306 { 307 struct igc_mac_info *mac = &hw->mac; 308 u16 i, rar_count = mac->rar_entry_count; 309 s32 ret_val = 0; 310 311 /* Setup the receive address */ 312 igc_init_rx_addrs(hw, rar_count); 313 314 /* Zero out the Multicast HASH table */ 315 hw_dbg("Zeroing the MTA\n"); 316 for (i = 0; i < mac->mta_reg_count; i++) 317 array_wr32(IGC_MTA, i, 0); 318 319 /* Zero out the Unicast HASH table */ 320 hw_dbg("Zeroing the UTA\n"); 321 for (i = 0; i < mac->uta_reg_count; i++) 322 array_wr32(IGC_UTA, i, 0); 323 324 /* Setup link and flow control */ 325 ret_val = igc_setup_link(hw); 326 327 /* Clear all of the statistics registers (clear on read). It is 328 * important that we do this after we have tried to establish link 329 * because the symbol error count will increment wildly if there 330 * is no link. 331 */ 332 igc_clear_hw_cntrs_base(hw); 333 334 return ret_val; 335 } 336 337 /** 338 * igc_power_down_phy_copper_base - Remove link during PHY power down 339 * @hw: pointer to the HW structure 340 * 341 * In the case of a PHY power down to save power, or to turn off link during a 342 * driver unload, or wake on lan is not enabled, remove the link. 343 */ 344 void igc_power_down_phy_copper_base(struct igc_hw *hw) 345 { 346 /* If the management interface is not enabled, then power down */ 347 if (!(igc_enable_mng_pass_thru(hw) || igc_check_reset_block(hw))) 348 igc_power_down_phy_copper(hw); 349 } 350 351 /** 352 * igc_rx_fifo_flush_base - Clean rx fifo after Rx enable 353 * @hw: pointer to the HW structure 354 * 355 * After Rx enable, if manageability is enabled then there is likely some 356 * bad data at the start of the fifo and possibly in the DMA fifo. This 357 * function clears the fifos and flushes any packets that came in as rx was 358 * being enabled. 359 */ 360 void igc_rx_fifo_flush_base(struct igc_hw *hw) 361 { 362 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 363 int i, ms_wait; 364 365 /* disable IPv6 options as per hardware errata */ 366 rfctl = rd32(IGC_RFCTL); 367 rfctl |= IGC_RFCTL_IPV6_EX_DIS; 368 wr32(IGC_RFCTL, rfctl); 369 370 if (!(rd32(IGC_MANC) & IGC_MANC_RCV_TCO_EN)) 371 return; 372 373 /* Disable all Rx queues */ 374 for (i = 0; i < 4; i++) { 375 rxdctl[i] = rd32(IGC_RXDCTL(i)); 376 wr32(IGC_RXDCTL(i), 377 rxdctl[i] & ~IGC_RXDCTL_QUEUE_ENABLE); 378 } 379 /* Poll all queues to verify they have shut down */ 380 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 381 usleep_range(1000, 2000); 382 rx_enabled = 0; 383 for (i = 0; i < 4; i++) 384 rx_enabled |= rd32(IGC_RXDCTL(i)); 385 if (!(rx_enabled & IGC_RXDCTL_QUEUE_ENABLE)) 386 break; 387 } 388 389 if (ms_wait == 10) 390 hw_dbg("Queue disable timed out after 10ms\n"); 391 392 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 393 * incoming packets are rejected. Set enable and wait 2ms so that 394 * any packet that was coming in as RCTL.EN was set is flushed 395 */ 396 wr32(IGC_RFCTL, rfctl & ~IGC_RFCTL_LEF); 397 398 rlpml = rd32(IGC_RLPML); 399 wr32(IGC_RLPML, 0); 400 401 rctl = rd32(IGC_RCTL); 402 temp_rctl = rctl & ~(IGC_RCTL_EN | IGC_RCTL_SBP); 403 temp_rctl |= IGC_RCTL_LPE; 404 405 wr32(IGC_RCTL, temp_rctl); 406 wr32(IGC_RCTL, temp_rctl | IGC_RCTL_EN); 407 wrfl(); 408 usleep_range(2000, 3000); 409 410 /* Enable Rx queues that were previously enabled and restore our 411 * previous state 412 */ 413 for (i = 0; i < 4; i++) 414 wr32(IGC_RXDCTL(i), rxdctl[i]); 415 wr32(IGC_RCTL, rctl); 416 wrfl(); 417 418 wr32(IGC_RLPML, rlpml); 419 wr32(IGC_RFCTL, rfctl); 420 421 /* Flush receive errors generated by workaround */ 422 rd32(IGC_ROC); 423 rd32(IGC_RNBC); 424 rd32(IGC_MPC); 425 } 426 427 bool igc_is_device_id_i225(struct igc_hw *hw) 428 { 429 switch (hw->device_id) { 430 case IGC_DEV_ID_I225_LM: 431 case IGC_DEV_ID_I225_V: 432 case IGC_DEV_ID_I225_I: 433 case IGC_DEV_ID_I225_K: 434 case IGC_DEV_ID_I225_K2: 435 case IGC_DEV_ID_I225_LMVP: 436 case IGC_DEV_ID_I225_IT: 437 return true; 438 default: 439 return false; 440 } 441 } 442 443 bool igc_is_device_id_i226(struct igc_hw *hw) 444 { 445 switch (hw->device_id) { 446 case IGC_DEV_ID_I226_LM: 447 case IGC_DEV_ID_I226_V: 448 case IGC_DEV_ID_I226_K: 449 case IGC_DEV_ID_I226_IT: 450 return true; 451 default: 452 return false; 453 } 454 } 455 456 static struct igc_mac_operations igc_mac_ops_base = { 457 .init_hw = igc_init_hw_base, 458 .check_for_link = igc_check_for_copper_link, 459 .rar_set = igc_rar_set, 460 .read_mac_addr = igc_read_mac_addr, 461 .get_speed_and_duplex = igc_get_speed_and_duplex_copper, 462 }; 463 464 static const struct igc_phy_operations igc_phy_ops_base = { 465 .acquire = igc_acquire_phy_base, 466 .release = igc_release_phy_base, 467 .reset = igc_phy_hw_reset, 468 .read_reg = igc_read_phy_reg_gpy, 469 .write_reg = igc_write_phy_reg_gpy, 470 .force_speed_duplex = igc_force_speed_duplex, 471 }; 472 473 const struct igc_info igc_base_info = { 474 .get_invariants = igc_get_invariants_base, 475 .mac_ops = &igc_mac_ops_base, 476 .phy_ops = &igc_phy_ops_base, 477 }; 478