1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_H_ 5 #define _IGC_H_ 6 7 #include <linux/kobject.h> 8 #include <linux/pci.h> 9 #include <linux/netdevice.h> 10 #include <linux/vmalloc.h> 11 #include <linux/ethtool.h> 12 #include <linux/sctp.h> 13 #include <linux/ptp_clock_kernel.h> 14 #include <linux/timecounter.h> 15 #include <linux/net_tstamp.h> 16 #include <linux/bitfield.h> 17 #include <linux/hrtimer.h> 18 #include <net/xdp.h> 19 20 #include "igc_hw.h" 21 22 void igc_ethtool_set_ops(struct net_device *); 23 24 /* Transmit and receive queues */ 25 #define IGC_MAX_RX_QUEUES 4 26 #define IGC_MAX_TX_QUEUES 4 27 28 #define MAX_Q_VECTORS 8 29 #define MAX_STD_JUMBO_FRAME_SIZE 9216 30 31 #define MAX_ETYPE_FILTER 8 32 #define IGC_RETA_SIZE 128 33 34 /* SDP support */ 35 #define IGC_N_EXTTS 2 36 #define IGC_N_PEROUT 2 37 #define IGC_N_SDP 4 38 39 #define MAX_FLEX_FILTER 32 40 41 #define IGC_MAX_TX_TSTAMP_REGS 4 42 43 struct igc_fpe_t { 44 struct ethtool_mmsv mmsv; 45 u32 tx_min_frag_size; 46 }; 47 48 enum igc_mac_filter_type { 49 IGC_MAC_FILTER_TYPE_DST = 0, 50 IGC_MAC_FILTER_TYPE_SRC 51 }; 52 53 struct igc_tx_queue_stats { 54 u64 packets; 55 u64 bytes; 56 u64 restart_queue; 57 u64 restart_queue2; 58 }; 59 60 struct igc_rx_queue_stats { 61 u64 packets; 62 u64 bytes; 63 u64 drops; 64 u64 csum_err; 65 u64 alloc_failed; 66 }; 67 68 struct igc_rx_packet_stats { 69 u64 ipv4_packets; /* IPv4 headers processed */ 70 u64 ipv4e_packets; /* IPv4E headers with extensions processed */ 71 u64 ipv6_packets; /* IPv6 headers processed */ 72 u64 ipv6e_packets; /* IPv6E headers with extensions processed */ 73 u64 tcp_packets; /* TCP headers processed */ 74 u64 udp_packets; /* UDP headers processed */ 75 u64 sctp_packets; /* SCTP headers processed */ 76 u64 nfs_packets; /* NFS headers processe */ 77 u64 other_packets; 78 }; 79 80 enum igc_tx_buffer_type { 81 IGC_TX_BUFFER_TYPE_SKB, 82 IGC_TX_BUFFER_TYPE_XDP, 83 IGC_TX_BUFFER_TYPE_XSK, 84 }; 85 86 /* wrapper around a pointer to a socket buffer, 87 * so a DMA handle can be stored along with the buffer 88 */ 89 struct igc_tx_buffer { 90 union igc_adv_tx_desc *next_to_watch; 91 unsigned long time_stamp; 92 enum igc_tx_buffer_type type; 93 union { 94 struct sk_buff *skb; 95 struct xdp_frame *xdpf; 96 }; 97 unsigned int bytecount; 98 u16 gso_segs; 99 __be16 protocol; 100 101 DEFINE_DMA_UNMAP_ADDR(dma); 102 DEFINE_DMA_UNMAP_LEN(len); 103 u32 tx_flags; 104 bool xsk_pending_ts; 105 }; 106 107 struct igc_tx_timestamp_request { 108 union { /* reference to the packet being timestamped */ 109 struct sk_buff *skb; 110 struct igc_tx_buffer *xsk_tx_buffer; 111 }; 112 enum igc_tx_buffer_type buffer_type; 113 unsigned long start; /* when the tstamp request started (jiffies) */ 114 u32 mask; /* _TSYNCTXCTL_TXTT_{X} bit for this request */ 115 u32 regl; /* which TXSTMPL_{X} register should be used */ 116 u32 regh; /* which TXSTMPH_{X} register should be used */ 117 u32 flags; /* flags that should be added to the tx_buffer */ 118 u8 xsk_queue_index; /* Tx queue which requesting timestamp */ 119 struct xsk_tx_metadata_compl xsk_meta; /* ref to xsk Tx metadata */ 120 }; 121 122 struct igc_inline_rx_tstamps { 123 /* Timestamps are saved in little endian at the beginning of the packet 124 * buffer following the layout: 125 * 126 * DWORD: | 0 | 1 | 2 | 3 | 127 * Field: | Timer1 SYSTIML | Timer1 SYSTIMH | Timer0 SYSTIML | Timer0 SYSTIMH | 128 * 129 * SYSTIML holds the nanoseconds part while SYSTIMH holds the seconds 130 * part of the timestamp. 131 * 132 */ 133 __le32 timer1[2]; 134 __le32 timer0[2]; 135 }; 136 137 struct igc_ring_container { 138 struct igc_ring *ring; /* pointer to linked list of rings */ 139 unsigned int total_bytes; /* total bytes processed this int */ 140 unsigned int total_packets; /* total packets processed this int */ 141 u16 work_limit; /* total work allowed per interrupt */ 142 u8 count; /* total number of rings in vector */ 143 u8 itr; /* current ITR setting for ring */ 144 }; 145 146 struct igc_ring { 147 struct igc_q_vector *q_vector; /* backlink to q_vector */ 148 struct net_device *netdev; /* back pointer to net_device */ 149 struct device *dev; /* device for dma mapping */ 150 union { /* array of buffer info structs */ 151 struct igc_tx_buffer *tx_buffer_info; 152 struct igc_rx_buffer *rx_buffer_info; 153 }; 154 void *desc; /* descriptor ring memory */ 155 unsigned long flags; /* ring specific flags */ 156 void __iomem *tail; /* pointer to ring tail register */ 157 dma_addr_t dma; /* phys address of the ring */ 158 unsigned int size; /* length of desc. ring in bytes */ 159 160 u16 count; /* number of desc. in the ring */ 161 u8 queue_index; /* logical index of the ring*/ 162 u8 reg_idx; /* physical index of the ring */ 163 bool launchtime_enable; /* true if LaunchTime is enabled */ 164 ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */ 165 ktime_t last_ff_cycle; /* Last cycle with an active first flag */ 166 167 u32 start_time; 168 u32 end_time; 169 u32 max_sdu; 170 bool oper_gate_closed; /* Operating gate. True if the TX Queue is closed */ 171 bool admin_gate_closed; /* Future gate. True if the TX Queue will be closed */ 172 173 /* CBS parameters */ 174 bool cbs_enable; /* indicates if CBS is enabled */ 175 s32 idleslope; /* idleSlope in kbps */ 176 s32 sendslope; /* sendSlope in kbps */ 177 s32 hicredit; /* hiCredit in bytes */ 178 s32 locredit; /* loCredit in bytes */ 179 180 /* everything past this point are written often */ 181 u16 next_to_clean; 182 u16 next_to_use; 183 u16 next_to_alloc; 184 185 union { 186 /* TX */ 187 struct { 188 struct igc_tx_queue_stats tx_stats; 189 struct u64_stats_sync tx_syncp; 190 struct u64_stats_sync tx_syncp2; 191 }; 192 /* RX */ 193 struct { 194 struct igc_rx_queue_stats rx_stats; 195 struct igc_rx_packet_stats pkt_stats; 196 struct u64_stats_sync rx_syncp; 197 struct sk_buff *skb; 198 }; 199 }; 200 201 struct xdp_rxq_info xdp_rxq; 202 struct xsk_buff_pool *xsk_pool; 203 } ____cacheline_internodealigned_in_smp; 204 205 /* Board specific private data structure */ 206 struct igc_adapter { 207 struct net_device *netdev; 208 209 struct ethtool_keee eee; 210 211 unsigned long state; 212 unsigned int flags; 213 unsigned int num_q_vectors; 214 215 struct msix_entry *msix_entries; 216 217 /* TX */ 218 u16 tx_work_limit; 219 u32 tx_timeout_count; 220 int num_tx_queues; 221 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; 222 223 /* RX */ 224 int num_rx_queues; 225 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES]; 226 227 struct timer_list watchdog_timer; 228 struct timer_list dma_err_timer; 229 struct timer_list phy_info_timer; 230 struct hrtimer hrtimer; 231 232 u32 wol; 233 u32 en_mng_pt; 234 u16 link_speed; 235 u16 link_duplex; 236 237 u8 port_num; 238 239 u8 __iomem *io_addr; 240 /* Interrupt Throttle Rate */ 241 u32 rx_itr_setting; 242 u32 tx_itr_setting; 243 244 struct work_struct reset_task; 245 struct work_struct watchdog_task; 246 struct work_struct dma_err_task; 247 bool fc_autoneg; 248 249 u8 tx_timeout_factor; 250 251 int msg_enable; 252 u32 max_frame_size; 253 u32 min_frame_size; 254 255 int tc_setup_type; 256 ktime_t base_time; 257 ktime_t cycle_time; 258 bool taprio_offload_enable; 259 u32 qbv_config_change_errors; 260 bool qbv_transition; 261 unsigned int qbv_count; 262 /* Access to oper_gate_closed, admin_gate_closed and qbv_transition 263 * are protected by the qbv_tx_lock. 264 */ 265 spinlock_t qbv_tx_lock; 266 267 bool strict_priority_enable; 268 u8 num_tc; 269 u16 queue_per_tc[IGC_MAX_TX_QUEUES]; 270 271 /* OS defined structs */ 272 struct pci_dev *pdev; 273 /* lock for statistics */ 274 spinlock_t stats64_lock; 275 struct rtnl_link_stats64 stats64; 276 277 /* structs defined in igc_hw.h */ 278 struct igc_hw hw; 279 struct igc_hw_stats stats; 280 281 struct igc_q_vector *q_vector[MAX_Q_VECTORS]; 282 u32 eims_enable_mask; 283 u32 eims_other; 284 285 u16 tx_ring_count; 286 u16 rx_ring_count; 287 288 u32 tx_hwtstamp_timeouts; 289 u32 tx_hwtstamp_skipped; 290 u32 rx_hwtstamp_cleared; 291 292 u32 rss_queues; 293 u32 rss_indir_tbl_init; 294 295 /* Any access to elements in nfc_rule_list is protected by the 296 * nfc_rule_lock. 297 */ 298 struct mutex nfc_rule_lock; 299 struct list_head nfc_rule_list; 300 unsigned int nfc_rule_count; 301 302 u8 rss_indir_tbl[IGC_RETA_SIZE]; 303 304 unsigned long link_check_timeout; 305 struct igc_info ei; 306 307 u32 test_icr; 308 309 struct ptp_clock *ptp_clock; 310 struct ptp_clock_info ptp_caps; 311 /* Access to ptp_tx_skb and ptp_tx_start are protected by the 312 * ptp_tx_lock. 313 */ 314 spinlock_t ptp_tx_lock; 315 struct igc_tx_timestamp_request tx_tstamp[IGC_MAX_TX_TSTAMP_REGS]; 316 struct hwtstamp_config tstamp_config; 317 unsigned int ptp_flags; 318 /* System time value lock */ 319 spinlock_t tmreg_lock; 320 /* Free-running timer lock */ 321 spinlock_t free_timer_lock; 322 struct cyclecounter cc; 323 struct timecounter tc; 324 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */ 325 ktime_t ptp_reset_start; /* Reset time in clock mono */ 326 struct system_time_snapshot snapshot; 327 struct mutex ptm_lock; /* Only allow one PTM transaction at a time */ 328 329 char fw_version[32]; 330 331 struct bpf_prog *xdp_prog; 332 333 bool pps_sys_wrap_on; 334 335 struct ptp_pin_desc sdp_config[IGC_N_SDP]; 336 struct { 337 struct timespec64 start; 338 struct timespec64 period; 339 } perout[IGC_N_PEROUT]; 340 341 struct igc_fpe_t fpe; 342 343 /* LEDs */ 344 struct mutex led_mutex; 345 struct igc_led_classdev *leds; 346 }; 347 348 void igc_up(struct igc_adapter *adapter); 349 void igc_down(struct igc_adapter *adapter); 350 int igc_open(struct net_device *netdev); 351 int igc_close(struct net_device *netdev); 352 int igc_setup_tx_resources(struct igc_ring *ring); 353 int igc_setup_rx_resources(struct igc_ring *ring); 354 void igc_free_tx_resources(struct igc_ring *ring); 355 void igc_free_rx_resources(struct igc_ring *ring); 356 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter); 357 void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 358 const u32 max_rss_queues); 359 int igc_reinit_queues(struct igc_adapter *adapter); 360 void igc_write_rss_indir_tbl(struct igc_adapter *adapter); 361 bool igc_has_link(struct igc_adapter *adapter); 362 void igc_reset(struct igc_adapter *adapter); 363 void igc_update_stats(struct igc_adapter *adapter); 364 void igc_disable_rx_ring(struct igc_ring *ring); 365 void igc_enable_rx_ring(struct igc_ring *ring); 366 void igc_disable_tx_ring(struct igc_ring *ring); 367 void igc_enable_tx_ring(struct igc_ring *ring); 368 int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags); 369 370 /* AF_XDP TX metadata operations */ 371 extern const struct xsk_tx_metadata_ops igc_xsk_tx_metadata_ops; 372 373 /* igc_dump declarations */ 374 void igc_rings_dump(struct igc_adapter *adapter); 375 void igc_regs_dump(struct igc_adapter *adapter); 376 377 extern char igc_driver_name[]; 378 379 #define IGC_REGS_LEN 740 380 381 /* flags controlling PTP/1588 function */ 382 #define IGC_PTP_ENABLED BIT(0) 383 384 /* Flags definitions */ 385 #define IGC_FLAG_HAS_MSI BIT(0) 386 #define IGC_FLAG_QUEUE_PAIRS BIT(3) 387 #define IGC_FLAG_DMAC BIT(4) 388 #define IGC_FLAG_PTP BIT(8) 389 #define IGC_FLAG_WOL_SUPPORTED BIT(8) 390 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9) 391 #define IGC_FLAG_HAS_MSIX BIT(13) 392 #define IGC_FLAG_EEE BIT(14) 393 #define IGC_FLAG_VLAN_PROMISC BIT(15) 394 #define IGC_FLAG_RX_LEGACY BIT(16) 395 #define IGC_FLAG_TSN_QBV_ENABLED BIT(17) 396 #define IGC_FLAG_TSN_QAV_ENABLED BIT(18) 397 #define IGC_FLAG_TSN_PREEMPT_ENABLED BIT(19) 398 399 #define IGC_FLAG_TSN_ANY_ENABLED \ 400 (IGC_FLAG_TSN_QBV_ENABLED | IGC_FLAG_TSN_QAV_ENABLED | \ 401 IGC_FLAG_TSN_PREEMPT_ENABLED) 402 403 #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6) 404 #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7) 405 406 #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002 407 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 408 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 409 410 /* RX-desc Write-Back format RSS Type's */ 411 enum igc_rss_type_num { 412 IGC_RSS_TYPE_NO_HASH = 0, 413 IGC_RSS_TYPE_HASH_TCP_IPV4 = 1, 414 IGC_RSS_TYPE_HASH_IPV4 = 2, 415 IGC_RSS_TYPE_HASH_TCP_IPV6 = 3, 416 IGC_RSS_TYPE_HASH_IPV6_EX = 4, 417 IGC_RSS_TYPE_HASH_IPV6 = 5, 418 IGC_RSS_TYPE_HASH_TCP_IPV6_EX = 6, 419 IGC_RSS_TYPE_HASH_UDP_IPV4 = 7, 420 IGC_RSS_TYPE_HASH_UDP_IPV6 = 8, 421 IGC_RSS_TYPE_HASH_UDP_IPV6_EX = 9, 422 IGC_RSS_TYPE_MAX = 10, 423 }; 424 #define IGC_RSS_TYPE_MAX_TABLE 16 425 #define IGC_RSS_TYPE_MASK GENMASK(3,0) /* 4-bits (3:0) = mask 0x0F */ 426 427 /* igc_rss_type - Rx descriptor RSS type field */ 428 static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc) 429 { 430 /* RSS Type 4-bits (3:0) number: 0-9 (above 9 is reserved) 431 * Accessing the same bits via u16 (wb.lower.lo_dword.hs_rss.pkt_info) 432 * is slightly slower than via u32 (wb.lower.lo_dword.data) 433 */ 434 return le32_get_bits(rx_desc->wb.lower.lo_dword.data, IGC_RSS_TYPE_MASK); 435 } 436 437 /* Interrupt defines */ 438 #define IGC_START_ITR 648 /* ~6000 ints/sec */ 439 #define IGC_4K_ITR 980 440 #define IGC_20K_ITR 196 441 #define IGC_70K_ITR 56 442 443 #define IGC_DEFAULT_ITR 3 /* dynamic */ 444 #define IGC_MAX_ITR_USECS 10000 445 #define IGC_MIN_ITR_USECS 10 446 #define NON_Q_VECTORS 1 447 #define MAX_MSIX_ENTRIES 10 448 449 /* TX/RX descriptor defines */ 450 #define IGC_DEFAULT_TXD 256 451 #define IGC_DEFAULT_TX_WORK 128 452 #define IGC_MIN_TXD 64 453 #define IGC_MAX_TXD 4096 454 455 #define IGC_DEFAULT_RXD 256 456 #define IGC_MIN_RXD 64 457 #define IGC_MAX_RXD 4096 458 459 /* Supported Rx Buffer Sizes */ 460 #define IGC_RXBUFFER_256 256 461 #define IGC_RXBUFFER_2048 2048 462 #define IGC_RXBUFFER_3072 3072 463 464 #define AUTO_ALL_MODES 0 465 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256 466 467 /* Transmit and receive latency (for PTP timestamps) */ 468 #define IGC_I225_TX_LATENCY_10 240 469 #define IGC_I225_TX_LATENCY_100 58 470 #define IGC_I225_TX_LATENCY_1000 80 471 #define IGC_I225_TX_LATENCY_2500 1325 472 #define IGC_I225_RX_LATENCY_10 6450 473 #define IGC_I225_RX_LATENCY_100 185 474 #define IGC_I225_RX_LATENCY_1000 300 475 #define IGC_I225_RX_LATENCY_2500 1485 476 477 /* RX and TX descriptor control thresholds. 478 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 479 * descriptors available in its onboard memory. 480 * Setting this to 0 disables RX descriptor prefetch. 481 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 482 * available in host memory. 483 * If PTHRESH is 0, this should also be 0. 484 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 485 * descriptors until either it has this many to write back, or the 486 * ITR timer expires. 487 */ 488 #define IGC_RX_PTHRESH 8 489 #define IGC_RX_HTHRESH 8 490 #define IGC_TX_PTHRESH 8 491 #define IGC_TX_HTHRESH 1 492 #define IGC_RX_WTHRESH 4 493 #define IGC_TX_WTHRESH 16 494 495 #define IGC_RX_DMA_ATTR \ 496 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 497 498 #define IGC_TS_HDR_LEN 16 499 500 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 501 502 #if (PAGE_SIZE < 8192) 503 #define IGC_MAX_FRAME_BUILD_SKB \ 504 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN) 505 #else 506 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN) 507 #endif 508 509 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 510 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 511 512 /* VLAN info */ 513 #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000 514 #define IGC_TX_FLAGS_VLAN_SHIFT 16 515 516 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */ 517 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, 518 const u32 stat_err_bits) 519 { 520 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 521 } 522 523 enum igc_state_t { 524 __IGC_TESTING, 525 __IGC_RESETTING, 526 __IGC_DOWN, 527 }; 528 529 enum igc_tx_flags { 530 /* cmd_type flags */ 531 IGC_TX_FLAGS_VLAN = 0x01, 532 IGC_TX_FLAGS_TSO = 0x02, 533 IGC_TX_FLAGS_TSTAMP = 0x04, 534 535 /* olinfo flags */ 536 IGC_TX_FLAGS_IPV4 = 0x10, 537 IGC_TX_FLAGS_CSUM = 0x20, 538 539 IGC_TX_FLAGS_TSTAMP_1 = 0x100, 540 IGC_TX_FLAGS_TSTAMP_2 = 0x200, 541 IGC_TX_FLAGS_TSTAMP_3 = 0x400, 542 543 IGC_TX_FLAGS_TSTAMP_TIMER_1 = 0x800, 544 }; 545 546 enum igc_boards { 547 board_base, 548 }; 549 550 /* The largest size we can write to the descriptor is 65535. In order to 551 * maintain a power of two alignment we have to limit ourselves to 32K. 552 */ 553 #define IGC_MAX_TXD_PWR 15 554 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) 555 556 /* Tx Descriptors needed, worst case */ 557 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD) 558 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 559 560 struct igc_rx_buffer { 561 union { 562 struct { 563 dma_addr_t dma; 564 struct page *page; 565 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 566 __u32 page_offset; 567 #else 568 __u16 page_offset; 569 #endif 570 __u16 pagecnt_bias; 571 }; 572 struct xdp_buff *xdp; 573 }; 574 }; 575 576 /* context wrapper around xdp_buff to provide access to descriptor metadata */ 577 struct igc_xdp_buff { 578 struct xdp_buff xdp; 579 union igc_adv_rx_desc *rx_desc; 580 struct igc_inline_rx_tstamps *rx_ts; /* data indication bit IGC_RXDADV_STAT_TSIP */ 581 }; 582 583 struct igc_metadata_request { 584 struct igc_tx_buffer *tx_buffer; 585 struct xsk_tx_metadata *meta; 586 struct igc_ring *tx_ring; 587 u32 cmd_type; 588 u16 used_desc; 589 }; 590 591 struct igc_q_vector { 592 struct igc_adapter *adapter; /* backlink */ 593 void __iomem *itr_register; 594 u32 eims_value; /* EIMS mask value */ 595 596 u16 itr_val; 597 u8 set_itr; 598 599 struct igc_ring_container rx, tx; 600 601 struct napi_struct napi; 602 603 struct rcu_head rcu; /* to avoid race with update stats on free */ 604 char name[IFNAMSIZ + 9]; 605 606 /* for dynamic allocation of rings associated with this q_vector */ 607 struct igc_ring ring[] ____cacheline_internodealigned_in_smp; 608 }; 609 610 enum igc_filter_match_flags { 611 IGC_FILTER_FLAG_ETHER_TYPE = BIT(0), 612 IGC_FILTER_FLAG_VLAN_TCI = BIT(1), 613 IGC_FILTER_FLAG_SRC_MAC_ADDR = BIT(2), 614 IGC_FILTER_FLAG_DST_MAC_ADDR = BIT(3), 615 IGC_FILTER_FLAG_USER_DATA = BIT(4), 616 IGC_FILTER_FLAG_VLAN_ETYPE = BIT(5), 617 }; 618 619 struct igc_nfc_filter { 620 u8 match_flags; 621 u16 etype; 622 u16 vlan_etype; 623 u16 vlan_tci; 624 u16 vlan_tci_mask; 625 u8 src_addr[ETH_ALEN]; 626 u8 dst_addr[ETH_ALEN]; 627 u8 user_data[8]; 628 u8 user_mask[8]; 629 u8 flex_index; 630 u8 rx_queue; 631 u8 prio; 632 u8 immediate_irq; 633 u8 drop; 634 }; 635 636 struct igc_nfc_rule { 637 struct list_head list; 638 struct igc_nfc_filter filter; 639 u32 location; 640 u16 action; 641 bool flex; 642 }; 643 644 /* IGC supports a total of 32 NFC rules: 16 MAC address based, 8 VLAN priority 645 * based, 8 ethertype based and 32 Flex filter based rules. 646 */ 647 #define IGC_MAX_RXNFC_RULES 64 648 649 struct igc_flex_filter { 650 u8 index; 651 u8 data[128]; 652 u8 mask[16]; 653 u8 length; 654 u8 rx_queue; 655 u8 prio; 656 u8 immediate_irq; 657 u8 drop; 658 }; 659 660 /* igc_desc_unused - calculate if we have unused descriptors */ 661 static inline u16 igc_desc_unused(const struct igc_ring *ring) 662 { 663 u16 ntc = ring->next_to_clean; 664 u16 ntu = ring->next_to_use; 665 666 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 667 } 668 669 static inline s32 igc_get_phy_info(struct igc_hw *hw) 670 { 671 if (hw->phy.ops.get_phy_info) 672 return hw->phy.ops.get_phy_info(hw); 673 674 return 0; 675 } 676 677 static inline s32 igc_reset_phy(struct igc_hw *hw) 678 { 679 if (hw->phy.ops.reset) 680 return hw->phy.ops.reset(hw); 681 682 return 0; 683 } 684 685 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring) 686 { 687 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 688 } 689 690 enum igc_ring_flags_t { 691 IGC_RING_FLAG_RX_3K_BUFFER, 692 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, 693 IGC_RING_FLAG_RX_SCTP_CSUM, 694 IGC_RING_FLAG_RX_LB_VLAN_BSWAP, 695 IGC_RING_FLAG_TX_CTX_IDX, 696 IGC_RING_FLAG_TX_DETECT_HANG, 697 IGC_RING_FLAG_AF_XDP_ZC, 698 IGC_RING_FLAG_TX_HWTSTAMP, 699 IGC_RING_FLAG_RX_ALLOC_FAILED, 700 }; 701 702 #define ring_uses_large_buffer(ring) \ 703 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 704 #define set_ring_uses_large_buffer(ring) \ 705 set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 706 #define clear_ring_uses_large_buffer(ring) \ 707 clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 708 709 #define ring_uses_build_skb(ring) \ 710 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 711 712 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring) 713 { 714 #if (PAGE_SIZE < 8192) 715 if (ring_uses_large_buffer(ring)) 716 return IGC_RXBUFFER_3072; 717 718 if (ring_uses_build_skb(ring)) 719 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN; 720 #endif 721 return IGC_RXBUFFER_2048; 722 } 723 724 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) 725 { 726 #if (PAGE_SIZE < 8192) 727 if (ring_uses_large_buffer(ring)) 728 return 1; 729 #endif 730 return 0; 731 } 732 733 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data) 734 { 735 if (hw->phy.ops.read_reg) 736 return hw->phy.ops.read_reg(hw, offset, data); 737 738 return -EOPNOTSUPP; 739 } 740 741 void igc_reinit_locked(struct igc_adapter *); 742 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter, 743 u32 location); 744 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 745 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 746 void igc_disable_empty_addr_recv(struct igc_adapter *adapter); 747 int igc_enable_empty_addr_recv(struct igc_adapter *adapter); 748 struct igc_ring *igc_get_tx_ring(struct igc_adapter *adapter, int cpu); 749 void igc_flush_tx_descriptors(struct igc_ring *ring); 750 void igc_ptp_init(struct igc_adapter *adapter); 751 void igc_ptp_reset(struct igc_adapter *adapter); 752 void igc_ptp_suspend(struct igc_adapter *adapter); 753 void igc_ptp_stop(struct igc_adapter *adapter); 754 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf); 755 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); 756 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); 757 void igc_ptp_tx_hang(struct igc_adapter *adapter); 758 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts); 759 void igc_ptp_tx_tstamp_event(struct igc_adapter *adapter); 760 761 int igc_led_setup(struct igc_adapter *adapter); 762 void igc_led_free(struct igc_adapter *adapter); 763 764 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring)) 765 766 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS) 767 768 #define IGC_RX_DESC(R, i) \ 769 (&(((union igc_adv_rx_desc *)((R)->desc))[i])) 770 #define IGC_TX_DESC(R, i) \ 771 (&(((union igc_adv_tx_desc *)((R)->desc))[i])) 772 #define IGC_TX_CTXTDESC(R, i) \ 773 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i])) 774 775 #endif /* _IGC_H_ */ 776