1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_H_ 5 #define _IGC_H_ 6 7 #include <linux/kobject.h> 8 #include <linux/pci.h> 9 #include <linux/netdevice.h> 10 #include <linux/vmalloc.h> 11 #include <linux/ethtool.h> 12 #include <linux/sctp.h> 13 #include <linux/ptp_clock_kernel.h> 14 #include <linux/timecounter.h> 15 #include <linux/net_tstamp.h> 16 #include <linux/bitfield.h> 17 #include <linux/hrtimer.h> 18 #include <net/xdp.h> 19 20 #include "igc_hw.h" 21 22 void igc_ethtool_set_ops(struct net_device *); 23 24 /* Transmit and receive queues */ 25 #define IGC_MAX_RX_QUEUES 4 26 #define IGC_MAX_TX_QUEUES 4 27 28 #define MAX_Q_VECTORS 8 29 #define MAX_STD_JUMBO_FRAME_SIZE 9216 30 31 #define MAX_ETYPE_FILTER 8 32 #define IGC_RETA_SIZE 128 33 #define IGC_RSS_KEY_SIZE 40 34 35 /* SDP support */ 36 #define IGC_N_EXTTS 2 37 #define IGC_N_PEROUT 2 38 #define IGC_N_SDP 4 39 40 #define MAX_FLEX_FILTER 32 41 42 #define IGC_MAX_TX_TSTAMP_REGS 4 43 44 struct igc_fpe_t { 45 struct ethtool_mmsv mmsv; 46 u32 tx_min_frag_size; 47 bool tx_enabled; 48 }; 49 50 enum igc_mac_filter_type { 51 IGC_MAC_FILTER_TYPE_DST = 0, 52 IGC_MAC_FILTER_TYPE_SRC 53 }; 54 55 struct igc_tx_queue_stats { 56 u64 packets; 57 u64 bytes; 58 u64 restart_queue; 59 u64 restart_queue2; 60 }; 61 62 struct igc_rx_queue_stats { 63 u64 packets; 64 u64 bytes; 65 u64 drops; 66 u64 csum_err; 67 u64 alloc_failed; 68 }; 69 70 struct igc_rx_packet_stats { 71 u64 ipv4_packets; /* IPv4 headers processed */ 72 u64 ipv4e_packets; /* IPv4E headers with extensions processed */ 73 u64 ipv6_packets; /* IPv6 headers processed */ 74 u64 ipv6e_packets; /* IPv6E headers with extensions processed */ 75 u64 tcp_packets; /* TCP headers processed */ 76 u64 udp_packets; /* UDP headers processed */ 77 u64 sctp_packets; /* SCTP headers processed */ 78 u64 nfs_packets; /* NFS headers processe */ 79 u64 other_packets; 80 }; 81 82 enum igc_tx_buffer_type { 83 IGC_TX_BUFFER_TYPE_SKB, 84 IGC_TX_BUFFER_TYPE_XDP, 85 IGC_TX_BUFFER_TYPE_XSK, 86 }; 87 88 /* wrapper around a pointer to a socket buffer, 89 * so a DMA handle can be stored along with the buffer 90 */ 91 struct igc_tx_buffer { 92 union igc_adv_tx_desc *next_to_watch; 93 unsigned long time_stamp; 94 enum igc_tx_buffer_type type; 95 union { 96 struct sk_buff *skb; 97 struct xdp_frame *xdpf; 98 }; 99 unsigned int bytecount; 100 u16 gso_segs; 101 __be16 protocol; 102 103 DEFINE_DMA_UNMAP_ADDR(dma); 104 DEFINE_DMA_UNMAP_LEN(len); 105 u32 tx_flags; 106 bool xsk_pending_ts; 107 }; 108 109 struct igc_tx_timestamp_request { 110 union { /* reference to the packet being timestamped */ 111 struct sk_buff *skb; 112 struct igc_tx_buffer *xsk_tx_buffer; 113 }; 114 enum igc_tx_buffer_type buffer_type; 115 unsigned long start; /* when the tstamp request started (jiffies) */ 116 u32 mask; /* _TSYNCTXCTL_TXTT_{X} bit for this request */ 117 u32 regl; /* which TXSTMPL_{X} register should be used */ 118 u32 regh; /* which TXSTMPH_{X} register should be used */ 119 u32 flags; /* flags that should be added to the tx_buffer */ 120 u8 xsk_queue_index; /* Tx queue which requesting timestamp */ 121 struct xsk_tx_metadata_compl xsk_meta; /* ref to xsk Tx metadata */ 122 }; 123 124 struct igc_inline_rx_tstamps { 125 /* Timestamps are saved in little endian at the beginning of the packet 126 * buffer following the layout: 127 * 128 * DWORD: | 0 | 1 | 2 | 3 | 129 * Field: | Timer1 SYSTIML | Timer1 SYSTIMH | Timer0 SYSTIML | Timer0 SYSTIMH | 130 * 131 * SYSTIML holds the nanoseconds part while SYSTIMH holds the seconds 132 * part of the timestamp. 133 * 134 */ 135 __le32 timer1[2]; 136 __le32 timer0[2]; 137 }; 138 139 struct igc_ring_container { 140 struct igc_ring *ring; /* pointer to linked list of rings */ 141 unsigned int total_bytes; /* total bytes processed this int */ 142 unsigned int total_packets; /* total packets processed this int */ 143 u16 work_limit; /* total work allowed per interrupt */ 144 u8 count; /* total number of rings in vector */ 145 u8 itr; /* current ITR setting for ring */ 146 }; 147 148 struct igc_ring { 149 struct igc_q_vector *q_vector; /* backlink to q_vector */ 150 struct net_device *netdev; /* back pointer to net_device */ 151 struct device *dev; /* device for dma mapping */ 152 union { /* array of buffer info structs */ 153 struct igc_tx_buffer *tx_buffer_info; 154 struct igc_rx_buffer *rx_buffer_info; 155 }; 156 void *desc; /* descriptor ring memory */ 157 unsigned long flags; /* ring specific flags */ 158 void __iomem *tail; /* pointer to ring tail register */ 159 dma_addr_t dma; /* phys address of the ring */ 160 unsigned int size; /* length of desc. ring in bytes */ 161 162 u16 count; /* number of desc. in the ring */ 163 u8 queue_index; /* logical index of the ring*/ 164 u8 reg_idx; /* physical index of the ring */ 165 bool launchtime_enable; /* true if LaunchTime is enabled */ 166 ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */ 167 ktime_t last_ff_cycle; /* Last cycle with an active first flag */ 168 bool preemptible; /* True if preemptible queue, false if express queue */ 169 170 u32 start_time; 171 u32 end_time; 172 u32 max_sdu; 173 bool oper_gate_closed; /* Operating gate. True if the TX Queue is closed */ 174 bool admin_gate_closed; /* Future gate. True if the TX Queue will be closed */ 175 176 /* CBS parameters */ 177 bool cbs_enable; /* indicates if CBS is enabled */ 178 s32 idleslope; /* idleSlope in kbps */ 179 s32 sendslope; /* sendSlope in kbps */ 180 s32 hicredit; /* hiCredit in bytes */ 181 s32 locredit; /* loCredit in bytes */ 182 183 /* everything past this point are written often */ 184 u16 next_to_clean; 185 u16 next_to_use; 186 u16 next_to_alloc; 187 188 union { 189 /* TX */ 190 struct { 191 struct igc_tx_queue_stats tx_stats; 192 struct u64_stats_sync tx_syncp; 193 struct u64_stats_sync tx_syncp2; 194 }; 195 /* RX */ 196 struct { 197 struct igc_rx_queue_stats rx_stats; 198 struct igc_rx_packet_stats pkt_stats; 199 struct u64_stats_sync rx_syncp; 200 struct sk_buff *skb; 201 }; 202 }; 203 204 struct xdp_rxq_info xdp_rxq; 205 struct xsk_buff_pool *xsk_pool; 206 } ____cacheline_internodealigned_in_smp; 207 208 /* Board specific private data structure */ 209 struct igc_adapter { 210 struct net_device *netdev; 211 212 struct ethtool_keee eee; 213 214 unsigned long state; 215 unsigned int flags; 216 unsigned int num_q_vectors; 217 218 struct msix_entry *msix_entries; 219 220 /* TX */ 221 u16 tx_work_limit; 222 u32 tx_timeout_count; 223 int num_tx_queues; 224 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; 225 226 /* RX */ 227 int num_rx_queues; 228 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES]; 229 230 struct timer_list watchdog_timer; 231 struct timer_list dma_err_timer; 232 struct timer_list phy_info_timer; 233 struct hrtimer hrtimer; 234 235 u32 wol; 236 u32 en_mng_pt; 237 u16 link_speed; 238 u16 link_duplex; 239 240 u8 port_num; 241 242 u8 __iomem *io_addr; 243 /* Interrupt Throttle Rate */ 244 u32 rx_itr_setting; 245 u32 tx_itr_setting; 246 247 struct work_struct reset_task; 248 struct work_struct watchdog_task; 249 struct work_struct dma_err_task; 250 bool fc_autoneg; 251 252 u8 tx_timeout_factor; 253 254 int msg_enable; 255 u32 max_frame_size; 256 u32 min_frame_size; 257 258 int tc_setup_type; 259 ktime_t base_time; 260 ktime_t cycle_time; 261 bool taprio_offload_enable; 262 u32 qbv_config_change_errors; 263 bool qbv_transition; 264 unsigned int qbv_count; 265 /* Access to oper_gate_closed, admin_gate_closed and qbv_transition 266 * are protected by the qbv_tx_lock. 267 */ 268 spinlock_t qbv_tx_lock; 269 270 bool strict_priority_enable; 271 u8 num_tc; 272 u16 queue_per_tc[IGC_MAX_TX_QUEUES]; 273 274 /* OS defined structs */ 275 struct pci_dev *pdev; 276 /* lock for statistics */ 277 spinlock_t stats64_lock; 278 struct rtnl_link_stats64 stats64; 279 280 /* structs defined in igc_hw.h */ 281 struct igc_hw hw; 282 struct igc_hw_stats stats; 283 284 struct igc_q_vector *q_vector[MAX_Q_VECTORS]; 285 u32 eims_enable_mask; 286 u32 eims_other; 287 288 u16 tx_ring_count; 289 u16 rx_ring_count; 290 291 u32 tx_hwtstamp_timeouts; 292 u32 tx_hwtstamp_skipped; 293 u32 rx_hwtstamp_cleared; 294 295 u32 rss_queues; 296 u32 rss_indir_tbl_init; 297 298 /* Any access to elements in nfc_rule_list is protected by the 299 * nfc_rule_lock. 300 */ 301 struct mutex nfc_rule_lock; 302 struct list_head nfc_rule_list; 303 unsigned int nfc_rule_count; 304 305 u8 rss_indir_tbl[IGC_RETA_SIZE]; 306 u8 rss_key[IGC_RSS_KEY_SIZE]; 307 308 unsigned long link_check_timeout; 309 struct igc_info ei; 310 311 u32 test_icr; 312 313 struct ptp_clock *ptp_clock; 314 struct ptp_clock_info ptp_caps; 315 /* Access to ptp_tx_skb and ptp_tx_start are protected by the 316 * ptp_tx_lock. 317 */ 318 spinlock_t ptp_tx_lock; 319 struct igc_tx_timestamp_request tx_tstamp[IGC_MAX_TX_TSTAMP_REGS]; 320 struct kernel_hwtstamp_config tstamp_config; 321 unsigned int ptp_flags; 322 /* System time value lock */ 323 spinlock_t tmreg_lock; 324 /* Free-running timer lock */ 325 spinlock_t free_timer_lock; 326 struct cyclecounter cc; 327 struct timecounter tc; 328 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */ 329 ktime_t ptp_reset_start; /* Reset time in clock mono */ 330 struct system_time_snapshot snapshot; 331 clockid_t snapshot_clock_id; 332 struct mutex ptm_lock; /* Only allow one PTM transaction at a time */ 333 334 char fw_version[32]; 335 336 struct bpf_prog *xdp_prog; 337 338 bool pps_sys_wrap_on; 339 340 struct ptp_pin_desc sdp_config[IGC_N_SDP]; 341 struct { 342 struct timespec64 start; 343 struct timespec64 period; 344 } perout[IGC_N_PEROUT]; 345 346 struct igc_fpe_t fpe; 347 348 /* LEDs */ 349 struct mutex led_mutex; 350 struct igc_led_classdev *leds; 351 bool leds_available; 352 }; 353 354 void igc_up(struct igc_adapter *adapter); 355 void igc_down(struct igc_adapter *adapter); 356 int igc_open(struct net_device *netdev); 357 int igc_close(struct net_device *netdev); 358 int igc_setup_tx_resources(struct igc_ring *ring); 359 int igc_setup_rx_resources(struct igc_ring *ring); 360 void igc_free_tx_resources(struct igc_ring *ring); 361 void igc_free_rx_resources(struct igc_ring *ring); 362 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter); 363 void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 364 const u32 max_rss_queues); 365 int igc_reinit_queues(struct igc_adapter *adapter); 366 void igc_write_rss_key(struct igc_adapter *adapter); 367 void igc_write_rss_indir_tbl(struct igc_adapter *adapter); 368 bool igc_has_link(struct igc_adapter *adapter); 369 void igc_reset(struct igc_adapter *adapter); 370 void igc_update_stats(struct igc_adapter *adapter); 371 void igc_disable_rx_ring(struct igc_ring *ring); 372 void igc_enable_rx_ring(struct igc_ring *ring); 373 void igc_disable_tx_ring(struct igc_ring *ring); 374 void igc_enable_tx_ring(struct igc_ring *ring); 375 int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags); 376 377 /* AF_XDP TX metadata operations */ 378 extern const struct xsk_tx_metadata_ops igc_xsk_tx_metadata_ops; 379 380 /* igc_dump declarations */ 381 void igc_rings_dump(struct igc_adapter *adapter); 382 void igc_regs_dump(struct igc_adapter *adapter); 383 384 extern char igc_driver_name[]; 385 386 #define IGC_REGS_LEN 740 387 388 /* flags controlling PTP/1588 function */ 389 #define IGC_PTP_ENABLED BIT(0) 390 391 /* Flags definitions */ 392 #define IGC_FLAG_HAS_MSI BIT(0) 393 #define IGC_FLAG_QUEUE_PAIRS BIT(3) 394 #define IGC_FLAG_DMAC BIT(4) 395 #define IGC_FLAG_PTP BIT(8) 396 #define IGC_FLAG_WOL_SUPPORTED BIT(8) 397 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9) 398 #define IGC_FLAG_HAS_MSIX BIT(13) 399 #define IGC_FLAG_EEE BIT(14) 400 #define IGC_FLAG_VLAN_PROMISC BIT(15) 401 #define IGC_FLAG_RX_LEGACY BIT(16) 402 #define IGC_FLAG_TSN_QBV_ENABLED BIT(17) 403 #define IGC_FLAG_TSN_QAV_ENABLED BIT(18) 404 #define IGC_FLAG_TSN_PREEMPT_ENABLED BIT(19) 405 #define IGC_FLAG_TSN_REVERSE_TXQ_PRIO BIT(20) 406 407 #define IGC_FLAG_TSN_ANY_ENABLED \ 408 (IGC_FLAG_TSN_QBV_ENABLED | IGC_FLAG_TSN_QAV_ENABLED | \ 409 IGC_FLAG_TSN_PREEMPT_ENABLED) 410 411 #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6) 412 #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7) 413 414 /* RX-desc Write-Back format RSS Type's */ 415 enum igc_rss_type_num { 416 IGC_RSS_TYPE_NO_HASH = 0, 417 IGC_RSS_TYPE_HASH_TCP_IPV4 = 1, 418 IGC_RSS_TYPE_HASH_IPV4 = 2, 419 IGC_RSS_TYPE_HASH_TCP_IPV6 = 3, 420 IGC_RSS_TYPE_HASH_IPV6_EX = 4, 421 IGC_RSS_TYPE_HASH_IPV6 = 5, 422 IGC_RSS_TYPE_HASH_TCP_IPV6_EX = 6, 423 IGC_RSS_TYPE_HASH_UDP_IPV4 = 7, 424 IGC_RSS_TYPE_HASH_UDP_IPV6 = 8, 425 IGC_RSS_TYPE_HASH_UDP_IPV6_EX = 9, 426 IGC_RSS_TYPE_MAX = 10, 427 }; 428 #define IGC_RSS_TYPE_MAX_TABLE 16 429 #define IGC_RSS_TYPE_MASK GENMASK(3,0) /* 4-bits (3:0) = mask 0x0F */ 430 431 /* igc_rss_type - Rx descriptor RSS type field */ 432 static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc) 433 { 434 /* RSS Type 4-bits (3:0) number: 0-9 (above 9 is reserved) 435 * Accessing the same bits via u16 (wb.lower.lo_dword.hs_rss.pkt_info) 436 * is slightly slower than via u32 (wb.lower.lo_dword.data) 437 */ 438 return le32_get_bits(rx_desc->wb.lower.lo_dword.data, IGC_RSS_TYPE_MASK); 439 } 440 441 /* Interrupt defines */ 442 #define IGC_START_ITR 648 /* ~6000 ints/sec */ 443 #define IGC_4K_ITR 980 444 #define IGC_20K_ITR 196 445 #define IGC_70K_ITR 56 446 447 #define IGC_DEFAULT_ITR 3 /* dynamic */ 448 #define IGC_MAX_ITR_USECS 10000 449 #define IGC_MIN_ITR_USECS 10 450 #define NON_Q_VECTORS 1 451 #define MAX_MSIX_ENTRIES 10 452 453 /* TX/RX descriptor defines */ 454 #define IGC_DEFAULT_TXD 256 455 #define IGC_DEFAULT_TX_WORK 128 456 #define IGC_MIN_TXD 64 457 #define IGC_MAX_TXD 4096 458 459 #define IGC_DEFAULT_RXD 256 460 #define IGC_MIN_RXD 64 461 #define IGC_MAX_RXD 4096 462 463 /* Supported Rx Buffer Sizes */ 464 #define IGC_RXBUFFER_256 256 465 #define IGC_RXBUFFER_2048 2048 466 #define IGC_RXBUFFER_3072 3072 467 468 #define AUTO_ALL_MODES 0 469 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256 470 471 /* Transmit and receive latency (for PTP timestamps) */ 472 #define IGC_I225_TX_LATENCY_10 240 473 #define IGC_I225_TX_LATENCY_100 58 474 #define IGC_I225_TX_LATENCY_1000 80 475 #define IGC_I225_TX_LATENCY_2500 1325 476 #define IGC_I225_RX_LATENCY_10 6450 477 #define IGC_I225_RX_LATENCY_100 185 478 #define IGC_I225_RX_LATENCY_1000 300 479 #define IGC_I225_RX_LATENCY_2500 1485 480 481 /* RX and TX descriptor control thresholds. 482 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 483 * descriptors available in its onboard memory. 484 * Setting this to 0 disables RX descriptor prefetch. 485 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 486 * available in host memory. 487 * If PTHRESH is 0, this should also be 0. 488 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 489 * descriptors until either it has this many to write back, or the 490 * ITR timer expires. 491 */ 492 #define IGC_RXDCTL_PTHRESH 8 493 #define IGC_RXDCTL_HTHRESH 8 494 #define IGC_RXDCTL_WTHRESH 4 495 /* Ena specific Rx Queue */ 496 #define IGC_RXDCTL_QUEUE_ENABLE 0x02000000 497 /* Receive Software Flush */ 498 #define IGC_RXDCTL_SWFLUSH 0x04000000 499 500 #define IGC_TXDCTL_PTHRESH_MASK GENMASK(4, 0) 501 #define IGC_TXDCTL_HTHRESH_MASK GENMASK(12, 8) 502 #define IGC_TXDCTL_WTHRESH_MASK GENMASK(20, 16) 503 #define IGC_TXDCTL_QUEUE_ENABLE_MASK GENMASK(25, 25) 504 #define IGC_TXDCTL_SWFLUSH_MASK GENMASK(26, 26) 505 #define IGC_TXDCTL_PRIORITY_MASK GENMASK(27, 27) 506 507 #define IGC_TXDCTL_PTHRESH(x) FIELD_PREP(IGC_TXDCTL_PTHRESH_MASK, (x)) 508 #define IGC_TXDCTL_HTHRESH(x) FIELD_PREP(IGC_TXDCTL_HTHRESH_MASK, (x)) 509 #define IGC_TXDCTL_WTHRESH(x) FIELD_PREP(IGC_TXDCTL_WTHRESH_MASK, (x)) 510 /* Ena specific Tx Queue */ 511 #define IGC_TXDCTL_QUEUE_ENABLE FIELD_PREP(IGC_TXDCTL_QUEUE_ENABLE_MASK, 1) 512 /* Transmit Software Flush */ 513 #define IGC_TXDCTL_SWFLUSH FIELD_PREP(IGC_TXDCTL_SWFLUSH_MASK, 1) 514 #define IGC_TXDCTL_PRIORITY(x) FIELD_PREP(IGC_TXDCTL_PRIORITY_MASK, (x)) 515 #define IGC_TXDCTL_PRIORITY_HIGH IGC_TXDCTL_PRIORITY(1) 516 517 #define IGC_RX_DMA_ATTR \ 518 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 519 520 #define IGC_TS_HDR_LEN 16 521 522 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 523 524 #if (PAGE_SIZE < 8192) 525 #define IGC_MAX_FRAME_BUILD_SKB \ 526 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN) 527 #else 528 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN) 529 #endif 530 531 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 532 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 533 534 /* VLAN info */ 535 #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000 536 #define IGC_TX_FLAGS_VLAN_SHIFT 16 537 538 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */ 539 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, 540 const u32 stat_err_bits) 541 { 542 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 543 } 544 545 enum igc_state_t { 546 __IGC_TESTING, 547 __IGC_RESETTING, 548 __IGC_DOWN, 549 }; 550 551 enum igc_tx_flags { 552 /* cmd_type flags */ 553 IGC_TX_FLAGS_VLAN = 0x01, 554 IGC_TX_FLAGS_TSO = 0x02, 555 IGC_TX_FLAGS_TSTAMP = 0x04, 556 557 /* olinfo flags */ 558 IGC_TX_FLAGS_IPV4 = 0x10, 559 IGC_TX_FLAGS_CSUM = 0x20, 560 561 IGC_TX_FLAGS_TSTAMP_1 = 0x100, 562 IGC_TX_FLAGS_TSTAMP_2 = 0x200, 563 IGC_TX_FLAGS_TSTAMP_3 = 0x400, 564 565 IGC_TX_FLAGS_TSTAMP_TIMER_1 = 0x800, 566 }; 567 568 enum igc_boards { 569 board_base, 570 }; 571 572 /* The largest size we can write to the descriptor is 65535. In order to 573 * maintain a power of two alignment we have to limit ourselves to 32K. 574 */ 575 #define IGC_MAX_TXD_PWR 15 576 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) 577 578 /* Tx Descriptors needed, worst case */ 579 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD) 580 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 581 582 struct igc_rx_buffer { 583 union { 584 struct { 585 dma_addr_t dma; 586 struct page *page; 587 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 588 __u32 page_offset; 589 #else 590 __u16 page_offset; 591 #endif 592 __u16 pagecnt_bias; 593 }; 594 struct xdp_buff *xdp; 595 }; 596 }; 597 598 /* context wrapper around xdp_buff to provide access to descriptor metadata */ 599 struct igc_xdp_buff { 600 struct xdp_buff xdp; 601 union igc_adv_rx_desc *rx_desc; 602 struct igc_inline_rx_tstamps *rx_ts; /* data indication bit IGC_RXDADV_STAT_TSIP */ 603 }; 604 605 struct igc_metadata_request { 606 struct igc_tx_buffer *tx_buffer; 607 struct xsk_tx_metadata *meta; 608 struct igc_ring *tx_ring; 609 u32 cmd_type; 610 u16 used_desc; 611 }; 612 613 struct igc_q_vector { 614 struct igc_adapter *adapter; /* backlink */ 615 void __iomem *itr_register; 616 u32 eims_value; /* EIMS mask value */ 617 618 u16 itr_val; 619 u8 set_itr; 620 621 struct igc_ring_container rx, tx; 622 623 struct napi_struct napi; 624 625 struct rcu_head rcu; /* to avoid race with update stats on free */ 626 char name[IFNAMSIZ + 9]; 627 628 /* for dynamic allocation of rings associated with this q_vector */ 629 struct igc_ring ring[] ____cacheline_internodealigned_in_smp; 630 }; 631 632 enum igc_filter_match_flags { 633 IGC_FILTER_FLAG_ETHER_TYPE = BIT(0), 634 IGC_FILTER_FLAG_VLAN_TCI = BIT(1), 635 IGC_FILTER_FLAG_SRC_MAC_ADDR = BIT(2), 636 IGC_FILTER_FLAG_DST_MAC_ADDR = BIT(3), 637 IGC_FILTER_FLAG_USER_DATA = BIT(4), 638 IGC_FILTER_FLAG_VLAN_ETYPE = BIT(5), 639 IGC_FILTER_FLAG_DEFAULT_QUEUE = BIT(6), 640 }; 641 642 struct igc_nfc_filter { 643 u8 match_flags; 644 u16 etype; 645 u16 vlan_etype; 646 u16 vlan_tci; 647 u16 vlan_tci_mask; 648 u8 src_addr[ETH_ALEN]; 649 u8 dst_addr[ETH_ALEN]; 650 u8 user_data[8]; 651 u8 user_mask[8]; 652 u8 flex_index; 653 u8 rx_queue; 654 u8 prio; 655 u8 immediate_irq; 656 u8 drop; 657 }; 658 659 struct igc_nfc_rule { 660 struct list_head list; 661 struct igc_nfc_filter filter; 662 u32 location; 663 u16 action; 664 bool flex; 665 }; 666 667 /* IGC supports a total of 65 NFC rules, listed below in order of priority: 668 * - 16 MAC address based filtering rules (highest priority) 669 * - 8 ethertype based filtering rules 670 * - 32 Flex filter based filtering rules 671 * - 8 VLAN priority based filtering rules 672 * - 1 default queue rule (lowest priority) 673 */ 674 #define IGC_MAX_RXNFC_RULES 65 675 676 struct igc_flex_filter { 677 u8 index; 678 u8 data[128]; 679 u8 mask[16]; 680 u8 length; 681 u8 rx_queue; 682 u8 prio; 683 u8 immediate_irq; 684 u8 drop; 685 }; 686 687 /* igc_desc_unused - calculate if we have unused descriptors */ 688 static inline u16 igc_desc_unused(const struct igc_ring *ring) 689 { 690 u16 ntc = ring->next_to_clean; 691 u16 ntu = ring->next_to_use; 692 693 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 694 } 695 696 static inline s32 igc_get_phy_info(struct igc_hw *hw) 697 { 698 if (hw->phy.ops.get_phy_info) 699 return hw->phy.ops.get_phy_info(hw); 700 701 return 0; 702 } 703 704 static inline s32 igc_reset_phy(struct igc_hw *hw) 705 { 706 if (hw->phy.ops.reset) 707 return hw->phy.ops.reset(hw); 708 709 return 0; 710 } 711 712 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring) 713 { 714 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 715 } 716 717 enum igc_ring_flags_t { 718 IGC_RING_FLAG_RX_3K_BUFFER, 719 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, 720 IGC_RING_FLAG_RX_SCTP_CSUM, 721 IGC_RING_FLAG_RX_LB_VLAN_BSWAP, 722 IGC_RING_FLAG_TX_CTX_IDX, 723 IGC_RING_FLAG_TX_DETECT_HANG, 724 IGC_RING_FLAG_AF_XDP_ZC, 725 IGC_RING_FLAG_TX_HWTSTAMP, 726 IGC_RING_FLAG_RX_ALLOC_FAILED, 727 }; 728 729 #define ring_uses_large_buffer(ring) \ 730 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 731 #define set_ring_uses_large_buffer(ring) \ 732 set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 733 #define clear_ring_uses_large_buffer(ring) \ 734 clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 735 736 #define ring_uses_build_skb(ring) \ 737 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 738 739 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring) 740 { 741 #if (PAGE_SIZE < 8192) 742 if (ring_uses_large_buffer(ring)) 743 return IGC_RXBUFFER_3072; 744 745 if (ring_uses_build_skb(ring)) 746 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN; 747 #endif 748 return IGC_RXBUFFER_2048; 749 } 750 751 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) 752 { 753 #if (PAGE_SIZE < 8192) 754 if (ring_uses_large_buffer(ring)) 755 return 1; 756 #endif 757 return 0; 758 } 759 760 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data) 761 { 762 if (hw->phy.ops.read_reg) 763 return hw->phy.ops.read_reg(hw, offset, data); 764 765 return -EOPNOTSUPP; 766 } 767 768 void igc_reinit_locked(struct igc_adapter *); 769 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter, 770 u32 location); 771 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 772 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 773 void igc_disable_empty_addr_recv(struct igc_adapter *adapter); 774 int igc_enable_empty_addr_recv(struct igc_adapter *adapter); 775 struct igc_ring *igc_get_tx_ring(struct igc_adapter *adapter, int cpu); 776 void igc_flush_tx_descriptors(struct igc_ring *ring); 777 void igc_ptp_init(struct igc_adapter *adapter); 778 void igc_ptp_reset(struct igc_adapter *adapter); 779 void igc_ptp_suspend(struct igc_adapter *adapter); 780 void igc_ptp_stop(struct igc_adapter *adapter); 781 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf); 782 int igc_ptp_hwtstamp_get(struct net_device *netdev, 783 struct kernel_hwtstamp_config *config); 784 int igc_ptp_hwtstamp_set(struct net_device *netdev, 785 struct kernel_hwtstamp_config *config, 786 struct netlink_ext_ack *extack); 787 void igc_ptp_tx_hang(struct igc_adapter *adapter); 788 void igc_ptp_clear_xsk_tx_tstamp_queue(struct igc_adapter *adapter, 789 u16 queue_id); 790 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts); 791 void igc_ptp_tx_tstamp_event(struct igc_adapter *adapter); 792 793 int igc_led_setup(struct igc_adapter *adapter); 794 void igc_led_free(struct igc_adapter *adapter); 795 796 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring)) 797 798 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS) 799 800 #define IGC_RX_DESC(R, i) \ 801 (&(((union igc_adv_rx_desc *)((R)->desc))[i])) 802 #define IGC_TX_DESC(R, i) \ 803 (&(((union igc_adv_tx_desc *)((R)->desc))[i])) 804 #define IGC_TX_CTXTDESC(R, i) \ 805 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i])) 806 807 #endif /* _IGC_H_ */ 808