1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_H_ 5 #define _IGC_H_ 6 7 #include <linux/kobject.h> 8 #include <linux/pci.h> 9 #include <linux/netdevice.h> 10 #include <linux/vmalloc.h> 11 #include <linux/ethtool.h> 12 #include <linux/sctp.h> 13 #include <linux/ptp_clock_kernel.h> 14 #include <linux/timecounter.h> 15 #include <linux/net_tstamp.h> 16 17 #include "igc_hw.h" 18 19 void igc_ethtool_set_ops(struct net_device *); 20 21 /* Transmit and receive queues */ 22 #define IGC_MAX_RX_QUEUES 4 23 #define IGC_MAX_TX_QUEUES 4 24 25 #define MAX_Q_VECTORS 8 26 #define MAX_STD_JUMBO_FRAME_SIZE 9216 27 28 #define MAX_ETYPE_FILTER 8 29 #define IGC_RETA_SIZE 128 30 31 /* SDP support */ 32 #define IGC_N_EXTTS 2 33 #define IGC_N_PEROUT 2 34 #define IGC_N_SDP 4 35 36 #define MAX_FLEX_FILTER 32 37 38 enum igc_mac_filter_type { 39 IGC_MAC_FILTER_TYPE_DST = 0, 40 IGC_MAC_FILTER_TYPE_SRC 41 }; 42 43 struct igc_tx_queue_stats { 44 u64 packets; 45 u64 bytes; 46 u64 restart_queue; 47 u64 restart_queue2; 48 }; 49 50 struct igc_rx_queue_stats { 51 u64 packets; 52 u64 bytes; 53 u64 drops; 54 u64 csum_err; 55 u64 alloc_failed; 56 }; 57 58 struct igc_rx_packet_stats { 59 u64 ipv4_packets; /* IPv4 headers processed */ 60 u64 ipv4e_packets; /* IPv4E headers with extensions processed */ 61 u64 ipv6_packets; /* IPv6 headers processed */ 62 u64 ipv6e_packets; /* IPv6E headers with extensions processed */ 63 u64 tcp_packets; /* TCP headers processed */ 64 u64 udp_packets; /* UDP headers processed */ 65 u64 sctp_packets; /* SCTP headers processed */ 66 u64 nfs_packets; /* NFS headers processe */ 67 u64 other_packets; 68 }; 69 70 struct igc_ring_container { 71 struct igc_ring *ring; /* pointer to linked list of rings */ 72 unsigned int total_bytes; /* total bytes processed this int */ 73 unsigned int total_packets; /* total packets processed this int */ 74 u16 work_limit; /* total work allowed per interrupt */ 75 u8 count; /* total number of rings in vector */ 76 u8 itr; /* current ITR setting for ring */ 77 }; 78 79 struct igc_ring { 80 struct igc_q_vector *q_vector; /* backlink to q_vector */ 81 struct net_device *netdev; /* back pointer to net_device */ 82 struct device *dev; /* device for dma mapping */ 83 union { /* array of buffer info structs */ 84 struct igc_tx_buffer *tx_buffer_info; 85 struct igc_rx_buffer *rx_buffer_info; 86 }; 87 void *desc; /* descriptor ring memory */ 88 unsigned long flags; /* ring specific flags */ 89 void __iomem *tail; /* pointer to ring tail register */ 90 dma_addr_t dma; /* phys address of the ring */ 91 unsigned int size; /* length of desc. ring in bytes */ 92 93 u16 count; /* number of desc. in the ring */ 94 u8 queue_index; /* logical index of the ring*/ 95 u8 reg_idx; /* physical index of the ring */ 96 bool launchtime_enable; /* true if LaunchTime is enabled */ 97 98 u32 start_time; 99 u32 end_time; 100 101 /* everything past this point are written often */ 102 u16 next_to_clean; 103 u16 next_to_use; 104 u16 next_to_alloc; 105 106 union { 107 /* TX */ 108 struct { 109 struct igc_tx_queue_stats tx_stats; 110 struct u64_stats_sync tx_syncp; 111 struct u64_stats_sync tx_syncp2; 112 }; 113 /* RX */ 114 struct { 115 struct igc_rx_queue_stats rx_stats; 116 struct igc_rx_packet_stats pkt_stats; 117 struct u64_stats_sync rx_syncp; 118 struct sk_buff *skb; 119 }; 120 }; 121 122 struct xdp_rxq_info xdp_rxq; 123 struct xsk_buff_pool *xsk_pool; 124 } ____cacheline_internodealigned_in_smp; 125 126 /* Board specific private data structure */ 127 struct igc_adapter { 128 struct net_device *netdev; 129 130 struct ethtool_eee eee; 131 u16 eee_advert; 132 133 unsigned long state; 134 unsigned int flags; 135 unsigned int num_q_vectors; 136 137 struct msix_entry *msix_entries; 138 139 /* TX */ 140 u16 tx_work_limit; 141 u32 tx_timeout_count; 142 int num_tx_queues; 143 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; 144 145 /* RX */ 146 int num_rx_queues; 147 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES]; 148 149 struct timer_list watchdog_timer; 150 struct timer_list dma_err_timer; 151 struct timer_list phy_info_timer; 152 153 u32 wol; 154 u32 en_mng_pt; 155 u16 link_speed; 156 u16 link_duplex; 157 158 u8 port_num; 159 160 u8 __iomem *io_addr; 161 /* Interrupt Throttle Rate */ 162 u32 rx_itr_setting; 163 u32 tx_itr_setting; 164 165 struct work_struct reset_task; 166 struct work_struct watchdog_task; 167 struct work_struct dma_err_task; 168 bool fc_autoneg; 169 170 u8 tx_timeout_factor; 171 172 int msg_enable; 173 u32 max_frame_size; 174 u32 min_frame_size; 175 176 ktime_t base_time; 177 ktime_t cycle_time; 178 179 /* OS defined structs */ 180 struct pci_dev *pdev; 181 /* lock for statistics */ 182 spinlock_t stats64_lock; 183 struct rtnl_link_stats64 stats64; 184 185 /* structs defined in igc_hw.h */ 186 struct igc_hw hw; 187 struct igc_hw_stats stats; 188 189 struct igc_q_vector *q_vector[MAX_Q_VECTORS]; 190 u32 eims_enable_mask; 191 u32 eims_other; 192 193 u16 tx_ring_count; 194 u16 rx_ring_count; 195 196 u32 tx_hwtstamp_timeouts; 197 u32 tx_hwtstamp_skipped; 198 u32 rx_hwtstamp_cleared; 199 200 u32 rss_queues; 201 u32 rss_indir_tbl_init; 202 203 /* Any access to elements in nfc_rule_list is protected by the 204 * nfc_rule_lock. 205 */ 206 struct mutex nfc_rule_lock; 207 struct list_head nfc_rule_list; 208 unsigned int nfc_rule_count; 209 210 u8 rss_indir_tbl[IGC_RETA_SIZE]; 211 212 unsigned long link_check_timeout; 213 struct igc_info ei; 214 215 u32 test_icr; 216 217 struct ptp_clock *ptp_clock; 218 struct ptp_clock_info ptp_caps; 219 struct work_struct ptp_tx_work; 220 struct sk_buff *ptp_tx_skb; 221 struct hwtstamp_config tstamp_config; 222 unsigned long ptp_tx_start; 223 unsigned int ptp_flags; 224 /* System time value lock */ 225 spinlock_t tmreg_lock; 226 struct cyclecounter cc; 227 struct timecounter tc; 228 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */ 229 ktime_t ptp_reset_start; /* Reset time in clock mono */ 230 231 char fw_version[32]; 232 233 struct bpf_prog *xdp_prog; 234 235 bool pps_sys_wrap_on; 236 237 struct ptp_pin_desc sdp_config[IGC_N_SDP]; 238 struct { 239 struct timespec64 start; 240 struct timespec64 period; 241 } perout[IGC_N_PEROUT]; 242 }; 243 244 void igc_up(struct igc_adapter *adapter); 245 void igc_down(struct igc_adapter *adapter); 246 int igc_open(struct net_device *netdev); 247 int igc_close(struct net_device *netdev); 248 int igc_setup_tx_resources(struct igc_ring *ring); 249 int igc_setup_rx_resources(struct igc_ring *ring); 250 void igc_free_tx_resources(struct igc_ring *ring); 251 void igc_free_rx_resources(struct igc_ring *ring); 252 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter); 253 void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 254 const u32 max_rss_queues); 255 int igc_reinit_queues(struct igc_adapter *adapter); 256 void igc_write_rss_indir_tbl(struct igc_adapter *adapter); 257 bool igc_has_link(struct igc_adapter *adapter); 258 void igc_reset(struct igc_adapter *adapter); 259 int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx); 260 void igc_update_stats(struct igc_adapter *adapter); 261 void igc_disable_rx_ring(struct igc_ring *ring); 262 void igc_enable_rx_ring(struct igc_ring *ring); 263 void igc_disable_tx_ring(struct igc_ring *ring); 264 void igc_enable_tx_ring(struct igc_ring *ring); 265 int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags); 266 267 /* igc_dump declarations */ 268 void igc_rings_dump(struct igc_adapter *adapter); 269 void igc_regs_dump(struct igc_adapter *adapter); 270 271 extern char igc_driver_name[]; 272 273 #define IGC_REGS_LEN 740 274 275 /* flags controlling PTP/1588 function */ 276 #define IGC_PTP_ENABLED BIT(0) 277 278 /* Flags definitions */ 279 #define IGC_FLAG_HAS_MSI BIT(0) 280 #define IGC_FLAG_QUEUE_PAIRS BIT(3) 281 #define IGC_FLAG_DMAC BIT(4) 282 #define IGC_FLAG_PTP BIT(8) 283 #define IGC_FLAG_WOL_SUPPORTED BIT(8) 284 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9) 285 #define IGC_FLAG_MEDIA_RESET BIT(10) 286 #define IGC_FLAG_MAS_ENABLE BIT(12) 287 #define IGC_FLAG_HAS_MSIX BIT(13) 288 #define IGC_FLAG_EEE BIT(14) 289 #define IGC_FLAG_VLAN_PROMISC BIT(15) 290 #define IGC_FLAG_RX_LEGACY BIT(16) 291 #define IGC_FLAG_TSN_QBV_ENABLED BIT(17) 292 293 #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6) 294 #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7) 295 296 #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002 297 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 298 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 299 300 /* Interrupt defines */ 301 #define IGC_START_ITR 648 /* ~6000 ints/sec */ 302 #define IGC_4K_ITR 980 303 #define IGC_20K_ITR 196 304 #define IGC_70K_ITR 56 305 306 #define IGC_DEFAULT_ITR 3 /* dynamic */ 307 #define IGC_MAX_ITR_USECS 10000 308 #define IGC_MIN_ITR_USECS 10 309 #define NON_Q_VECTORS 1 310 #define MAX_MSIX_ENTRIES 10 311 312 /* TX/RX descriptor defines */ 313 #define IGC_DEFAULT_TXD 256 314 #define IGC_DEFAULT_TX_WORK 128 315 #define IGC_MIN_TXD 80 316 #define IGC_MAX_TXD 4096 317 318 #define IGC_DEFAULT_RXD 256 319 #define IGC_MIN_RXD 80 320 #define IGC_MAX_RXD 4096 321 322 /* Supported Rx Buffer Sizes */ 323 #define IGC_RXBUFFER_256 256 324 #define IGC_RXBUFFER_2048 2048 325 #define IGC_RXBUFFER_3072 3072 326 327 #define AUTO_ALL_MODES 0 328 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256 329 330 /* Transmit and receive latency (for PTP timestamps) */ 331 #define IGC_I225_TX_LATENCY_10 240 332 #define IGC_I225_TX_LATENCY_100 58 333 #define IGC_I225_TX_LATENCY_1000 80 334 #define IGC_I225_TX_LATENCY_2500 1325 335 #define IGC_I225_RX_LATENCY_10 6450 336 #define IGC_I225_RX_LATENCY_100 185 337 #define IGC_I225_RX_LATENCY_1000 300 338 #define IGC_I225_RX_LATENCY_2500 1485 339 340 /* RX and TX descriptor control thresholds. 341 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 342 * descriptors available in its onboard memory. 343 * Setting this to 0 disables RX descriptor prefetch. 344 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 345 * available in host memory. 346 * If PTHRESH is 0, this should also be 0. 347 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 348 * descriptors until either it has this many to write back, or the 349 * ITR timer expires. 350 */ 351 #define IGC_RX_PTHRESH 8 352 #define IGC_RX_HTHRESH 8 353 #define IGC_TX_PTHRESH 8 354 #define IGC_TX_HTHRESH 1 355 #define IGC_RX_WTHRESH 4 356 #define IGC_TX_WTHRESH 16 357 358 #define IGC_RX_DMA_ATTR \ 359 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 360 361 #define IGC_TS_HDR_LEN 16 362 363 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 364 365 #if (PAGE_SIZE < 8192) 366 #define IGC_MAX_FRAME_BUILD_SKB \ 367 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN) 368 #else 369 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN) 370 #endif 371 372 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 373 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 374 375 /* VLAN info */ 376 #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000 377 #define IGC_TX_FLAGS_VLAN_SHIFT 16 378 379 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */ 380 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, 381 const u32 stat_err_bits) 382 { 383 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 384 } 385 386 enum igc_state_t { 387 __IGC_TESTING, 388 __IGC_RESETTING, 389 __IGC_DOWN, 390 __IGC_PTP_TX_IN_PROGRESS, 391 }; 392 393 enum igc_tx_flags { 394 /* cmd_type flags */ 395 IGC_TX_FLAGS_VLAN = 0x01, 396 IGC_TX_FLAGS_TSO = 0x02, 397 IGC_TX_FLAGS_TSTAMP = 0x04, 398 399 /* olinfo flags */ 400 IGC_TX_FLAGS_IPV4 = 0x10, 401 IGC_TX_FLAGS_CSUM = 0x20, 402 }; 403 404 enum igc_boards { 405 board_base, 406 }; 407 408 /* The largest size we can write to the descriptor is 65535. In order to 409 * maintain a power of two alignment we have to limit ourselves to 32K. 410 */ 411 #define IGC_MAX_TXD_PWR 15 412 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) 413 414 /* Tx Descriptors needed, worst case */ 415 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD) 416 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 417 418 enum igc_tx_buffer_type { 419 IGC_TX_BUFFER_TYPE_SKB, 420 IGC_TX_BUFFER_TYPE_XDP, 421 IGC_TX_BUFFER_TYPE_XSK, 422 }; 423 424 /* wrapper around a pointer to a socket buffer, 425 * so a DMA handle can be stored along with the buffer 426 */ 427 struct igc_tx_buffer { 428 union igc_adv_tx_desc *next_to_watch; 429 unsigned long time_stamp; 430 enum igc_tx_buffer_type type; 431 union { 432 struct sk_buff *skb; 433 struct xdp_frame *xdpf; 434 }; 435 unsigned int bytecount; 436 u16 gso_segs; 437 __be16 protocol; 438 439 DEFINE_DMA_UNMAP_ADDR(dma); 440 DEFINE_DMA_UNMAP_LEN(len); 441 u32 tx_flags; 442 }; 443 444 struct igc_rx_buffer { 445 union { 446 struct { 447 dma_addr_t dma; 448 struct page *page; 449 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 450 __u32 page_offset; 451 #else 452 __u16 page_offset; 453 #endif 454 __u16 pagecnt_bias; 455 }; 456 struct xdp_buff *xdp; 457 }; 458 }; 459 460 struct igc_q_vector { 461 struct igc_adapter *adapter; /* backlink */ 462 void __iomem *itr_register; 463 u32 eims_value; /* EIMS mask value */ 464 465 u16 itr_val; 466 u8 set_itr; 467 468 struct igc_ring_container rx, tx; 469 470 struct napi_struct napi; 471 472 struct rcu_head rcu; /* to avoid race with update stats on free */ 473 char name[IFNAMSIZ + 9]; 474 struct net_device poll_dev; 475 476 /* for dynamic allocation of rings associated with this q_vector */ 477 struct igc_ring ring[] ____cacheline_internodealigned_in_smp; 478 }; 479 480 enum igc_filter_match_flags { 481 IGC_FILTER_FLAG_ETHER_TYPE = BIT(0), 482 IGC_FILTER_FLAG_VLAN_TCI = BIT(1), 483 IGC_FILTER_FLAG_SRC_MAC_ADDR = BIT(2), 484 IGC_FILTER_FLAG_DST_MAC_ADDR = BIT(3), 485 IGC_FILTER_FLAG_USER_DATA = BIT(4), 486 IGC_FILTER_FLAG_VLAN_ETYPE = BIT(5), 487 }; 488 489 struct igc_nfc_filter { 490 u8 match_flags; 491 u16 etype; 492 __be16 vlan_etype; 493 u16 vlan_tci; 494 u8 src_addr[ETH_ALEN]; 495 u8 dst_addr[ETH_ALEN]; 496 u8 user_data[8]; 497 u8 user_mask[8]; 498 u8 flex_index; 499 u8 rx_queue; 500 u8 prio; 501 u8 immediate_irq; 502 u8 drop; 503 }; 504 505 struct igc_nfc_rule { 506 struct list_head list; 507 struct igc_nfc_filter filter; 508 u32 location; 509 u16 action; 510 bool flex; 511 }; 512 513 /* IGC supports a total of 32 NFC rules: 16 MAC address based, 8 VLAN priority 514 * based, 8 ethertype based and 32 Flex filter based rules. 515 */ 516 #define IGC_MAX_RXNFC_RULES 64 517 518 struct igc_flex_filter { 519 u8 index; 520 u8 data[128]; 521 u8 mask[16]; 522 u8 length; 523 u8 rx_queue; 524 u8 prio; 525 u8 immediate_irq; 526 u8 drop; 527 }; 528 529 /* igc_desc_unused - calculate if we have unused descriptors */ 530 static inline u16 igc_desc_unused(const struct igc_ring *ring) 531 { 532 u16 ntc = ring->next_to_clean; 533 u16 ntu = ring->next_to_use; 534 535 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 536 } 537 538 static inline s32 igc_get_phy_info(struct igc_hw *hw) 539 { 540 if (hw->phy.ops.get_phy_info) 541 return hw->phy.ops.get_phy_info(hw); 542 543 return 0; 544 } 545 546 static inline s32 igc_reset_phy(struct igc_hw *hw) 547 { 548 if (hw->phy.ops.reset) 549 return hw->phy.ops.reset(hw); 550 551 return 0; 552 } 553 554 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring) 555 { 556 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 557 } 558 559 enum igc_ring_flags_t { 560 IGC_RING_FLAG_RX_3K_BUFFER, 561 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, 562 IGC_RING_FLAG_RX_SCTP_CSUM, 563 IGC_RING_FLAG_RX_LB_VLAN_BSWAP, 564 IGC_RING_FLAG_TX_CTX_IDX, 565 IGC_RING_FLAG_TX_DETECT_HANG, 566 IGC_RING_FLAG_AF_XDP_ZC, 567 }; 568 569 #define ring_uses_large_buffer(ring) \ 570 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 571 #define set_ring_uses_large_buffer(ring) \ 572 set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 573 #define clear_ring_uses_large_buffer(ring) \ 574 clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 575 576 #define ring_uses_build_skb(ring) \ 577 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 578 579 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring) 580 { 581 #if (PAGE_SIZE < 8192) 582 if (ring_uses_large_buffer(ring)) 583 return IGC_RXBUFFER_3072; 584 585 if (ring_uses_build_skb(ring)) 586 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN; 587 #endif 588 return IGC_RXBUFFER_2048; 589 } 590 591 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) 592 { 593 #if (PAGE_SIZE < 8192) 594 if (ring_uses_large_buffer(ring)) 595 return 1; 596 #endif 597 return 0; 598 } 599 600 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data) 601 { 602 if (hw->phy.ops.read_reg) 603 return hw->phy.ops.read_reg(hw, offset, data); 604 605 return -EOPNOTSUPP; 606 } 607 608 void igc_reinit_locked(struct igc_adapter *); 609 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter, 610 u32 location); 611 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 612 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 613 614 void igc_ptp_init(struct igc_adapter *adapter); 615 void igc_ptp_reset(struct igc_adapter *adapter); 616 void igc_ptp_suspend(struct igc_adapter *adapter); 617 void igc_ptp_stop(struct igc_adapter *adapter); 618 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf); 619 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); 620 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); 621 void igc_ptp_tx_hang(struct igc_adapter *adapter); 622 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts); 623 624 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring)) 625 626 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS) 627 628 #define IGC_RX_DESC(R, i) \ 629 (&(((union igc_adv_rx_desc *)((R)->desc))[i])) 630 #define IGC_TX_DESC(R, i) \ 631 (&(((union igc_adv_tx_desc *)((R)->desc))[i])) 632 #define IGC_TX_CTXTDESC(R, i) \ 633 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i])) 634 635 #endif /* _IGC_H_ */ 636