1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_H_ 5 #define _IGC_H_ 6 7 #include <linux/kobject.h> 8 #include <linux/pci.h> 9 #include <linux/netdevice.h> 10 #include <linux/vmalloc.h> 11 #include <linux/ethtool.h> 12 #include <linux/sctp.h> 13 #include <linux/ptp_clock_kernel.h> 14 #include <linux/timecounter.h> 15 #include <linux/net_tstamp.h> 16 17 #include "igc_hw.h" 18 19 /* forward declaration */ 20 void igc_set_ethtool_ops(struct net_device *); 21 22 /* Transmit and receive queues */ 23 #define IGC_MAX_RX_QUEUES 4 24 #define IGC_MAX_TX_QUEUES 4 25 26 #define MAX_Q_VECTORS 8 27 #define MAX_STD_JUMBO_FRAME_SIZE 9216 28 29 #define MAX_ETYPE_FILTER (4 - 1) 30 #define IGC_RETA_SIZE 128 31 32 struct igc_tx_queue_stats { 33 u64 packets; 34 u64 bytes; 35 u64 restart_queue; 36 u64 restart_queue2; 37 }; 38 39 struct igc_rx_queue_stats { 40 u64 packets; 41 u64 bytes; 42 u64 drops; 43 u64 csum_err; 44 u64 alloc_failed; 45 }; 46 47 struct igc_rx_packet_stats { 48 u64 ipv4_packets; /* IPv4 headers processed */ 49 u64 ipv4e_packets; /* IPv4E headers with extensions processed */ 50 u64 ipv6_packets; /* IPv6 headers processed */ 51 u64 ipv6e_packets; /* IPv6E headers with extensions processed */ 52 u64 tcp_packets; /* TCP headers processed */ 53 u64 udp_packets; /* UDP headers processed */ 54 u64 sctp_packets; /* SCTP headers processed */ 55 u64 nfs_packets; /* NFS headers processe */ 56 u64 other_packets; 57 }; 58 59 struct igc_ring_container { 60 struct igc_ring *ring; /* pointer to linked list of rings */ 61 unsigned int total_bytes; /* total bytes processed this int */ 62 unsigned int total_packets; /* total packets processed this int */ 63 u16 work_limit; /* total work allowed per interrupt */ 64 u8 count; /* total number of rings in vector */ 65 u8 itr; /* current ITR setting for ring */ 66 }; 67 68 struct igc_ring { 69 struct igc_q_vector *q_vector; /* backlink to q_vector */ 70 struct net_device *netdev; /* back pointer to net_device */ 71 struct device *dev; /* device for dma mapping */ 72 union { /* array of buffer info structs */ 73 struct igc_tx_buffer *tx_buffer_info; 74 struct igc_rx_buffer *rx_buffer_info; 75 }; 76 void *desc; /* descriptor ring memory */ 77 unsigned long flags; /* ring specific flags */ 78 void __iomem *tail; /* pointer to ring tail register */ 79 dma_addr_t dma; /* phys address of the ring */ 80 unsigned int size; /* length of desc. ring in bytes */ 81 82 u16 count; /* number of desc. in the ring */ 83 u8 queue_index; /* logical index of the ring*/ 84 u8 reg_idx; /* physical index of the ring */ 85 bool launchtime_enable; /* true if LaunchTime is enabled */ 86 87 u32 start_time; 88 u32 end_time; 89 90 /* everything past this point are written often */ 91 u16 next_to_clean; 92 u16 next_to_use; 93 u16 next_to_alloc; 94 95 union { 96 /* TX */ 97 struct { 98 struct igc_tx_queue_stats tx_stats; 99 struct u64_stats_sync tx_syncp; 100 struct u64_stats_sync tx_syncp2; 101 }; 102 /* RX */ 103 struct { 104 struct igc_rx_queue_stats rx_stats; 105 struct igc_rx_packet_stats pkt_stats; 106 struct u64_stats_sync rx_syncp; 107 struct sk_buff *skb; 108 }; 109 }; 110 } ____cacheline_internodealigned_in_smp; 111 112 /* Board specific private data structure */ 113 struct igc_adapter { 114 struct net_device *netdev; 115 116 unsigned long state; 117 unsigned int flags; 118 unsigned int num_q_vectors; 119 120 struct msix_entry *msix_entries; 121 122 /* TX */ 123 u16 tx_work_limit; 124 u32 tx_timeout_count; 125 int num_tx_queues; 126 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; 127 128 /* RX */ 129 int num_rx_queues; 130 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES]; 131 132 struct timer_list watchdog_timer; 133 struct timer_list dma_err_timer; 134 struct timer_list phy_info_timer; 135 136 u32 wol; 137 u32 en_mng_pt; 138 u16 link_speed; 139 u16 link_duplex; 140 141 u8 port_num; 142 143 u8 __iomem *io_addr; 144 /* Interrupt Throttle Rate */ 145 u32 rx_itr_setting; 146 u32 tx_itr_setting; 147 148 struct work_struct reset_task; 149 struct work_struct watchdog_task; 150 struct work_struct dma_err_task; 151 bool fc_autoneg; 152 153 u8 tx_timeout_factor; 154 155 int msg_enable; 156 u32 max_frame_size; 157 u32 min_frame_size; 158 159 ktime_t base_time; 160 ktime_t cycle_time; 161 162 /* OS defined structs */ 163 struct pci_dev *pdev; 164 /* lock for statistics */ 165 spinlock_t stats64_lock; 166 struct rtnl_link_stats64 stats64; 167 168 /* structs defined in igc_hw.h */ 169 struct igc_hw hw; 170 struct igc_hw_stats stats; 171 172 struct igc_q_vector *q_vector[MAX_Q_VECTORS]; 173 u32 eims_enable_mask; 174 u32 eims_other; 175 176 u16 tx_ring_count; 177 u16 rx_ring_count; 178 179 u32 tx_hwtstamp_timeouts; 180 u32 tx_hwtstamp_skipped; 181 u32 rx_hwtstamp_cleared; 182 183 u32 rss_queues; 184 u32 rss_indir_tbl_init; 185 186 /* RX network flow classification support */ 187 struct hlist_head nfc_filter_list; 188 unsigned int nfc_filter_count; 189 190 /* lock for RX network flow classification filter */ 191 spinlock_t nfc_lock; 192 bool etype_bitmap[MAX_ETYPE_FILTER]; 193 194 struct igc_mac_addr *mac_table; 195 196 u8 rss_indir_tbl[IGC_RETA_SIZE]; 197 198 unsigned long link_check_timeout; 199 struct igc_info ei; 200 201 struct ptp_clock *ptp_clock; 202 struct ptp_clock_info ptp_caps; 203 struct work_struct ptp_tx_work; 204 struct sk_buff *ptp_tx_skb; 205 struct hwtstamp_config tstamp_config; 206 unsigned long ptp_tx_start; 207 unsigned long last_rx_ptp_check; 208 unsigned long last_rx_timestamp; 209 unsigned int ptp_flags; 210 /* System time value lock */ 211 spinlock_t tmreg_lock; 212 struct cyclecounter cc; 213 struct timecounter tc; 214 }; 215 216 void igc_up(struct igc_adapter *adapter); 217 void igc_down(struct igc_adapter *adapter); 218 int igc_setup_tx_resources(struct igc_ring *ring); 219 int igc_setup_rx_resources(struct igc_ring *ring); 220 void igc_free_tx_resources(struct igc_ring *ring); 221 void igc_free_rx_resources(struct igc_ring *ring); 222 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter); 223 void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 224 const u32 max_rss_queues); 225 int igc_reinit_queues(struct igc_adapter *adapter); 226 void igc_write_rss_indir_tbl(struct igc_adapter *adapter); 227 bool igc_has_link(struct igc_adapter *adapter); 228 void igc_reset(struct igc_adapter *adapter); 229 int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx); 230 int igc_add_mac_filter(struct igc_adapter *adapter, const u8 *addr, 231 const s8 queue, const u8 flags); 232 int igc_del_mac_filter(struct igc_adapter *adapter, const u8 *addr, 233 const u8 flags); 234 void igc_update_stats(struct igc_adapter *adapter); 235 236 /* igc_dump declarations */ 237 void igc_rings_dump(struct igc_adapter *adapter); 238 void igc_regs_dump(struct igc_adapter *adapter); 239 240 extern char igc_driver_name[]; 241 extern char igc_driver_version[]; 242 243 #define IGC_REGS_LEN 740 244 245 /* flags controlling PTP/1588 function */ 246 #define IGC_PTP_ENABLED BIT(0) 247 248 /* Flags definitions */ 249 #define IGC_FLAG_HAS_MSI BIT(0) 250 #define IGC_FLAG_QUEUE_PAIRS BIT(3) 251 #define IGC_FLAG_DMAC BIT(4) 252 #define IGC_FLAG_PTP BIT(8) 253 #define IGC_FLAG_WOL_SUPPORTED BIT(8) 254 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9) 255 #define IGC_FLAG_MEDIA_RESET BIT(10) 256 #define IGC_FLAG_MAS_ENABLE BIT(12) 257 #define IGC_FLAG_HAS_MSIX BIT(13) 258 #define IGC_FLAG_VLAN_PROMISC BIT(15) 259 #define IGC_FLAG_RX_LEGACY BIT(16) 260 #define IGC_FLAG_TSN_QBV_ENABLED BIT(17) 261 262 #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6) 263 #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7) 264 265 #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002 266 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 267 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 268 269 /* Interrupt defines */ 270 #define IGC_START_ITR 648 /* ~6000 ints/sec */ 271 #define IGC_4K_ITR 980 272 #define IGC_20K_ITR 196 273 #define IGC_70K_ITR 56 274 275 #define IGC_DEFAULT_ITR 3 /* dynamic */ 276 #define IGC_MAX_ITR_USECS 10000 277 #define IGC_MIN_ITR_USECS 10 278 #define NON_Q_VECTORS 1 279 #define MAX_MSIX_ENTRIES 10 280 281 /* TX/RX descriptor defines */ 282 #define IGC_DEFAULT_TXD 256 283 #define IGC_DEFAULT_TX_WORK 128 284 #define IGC_MIN_TXD 80 285 #define IGC_MAX_TXD 4096 286 287 #define IGC_DEFAULT_RXD 256 288 #define IGC_MIN_RXD 80 289 #define IGC_MAX_RXD 4096 290 291 /* Supported Rx Buffer Sizes */ 292 #define IGC_RXBUFFER_256 256 293 #define IGC_RXBUFFER_2048 2048 294 #define IGC_RXBUFFER_3072 3072 295 296 #define AUTO_ALL_MODES 0 297 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256 298 299 /* Transmit and receive latency (for PTP timestamps) */ 300 /* FIXME: These values were estimated using the ones that i225 has as 301 * basis, they seem to provide good numbers with ptp4l/phc2sys, but we 302 * need to confirm them. 303 */ 304 #define IGC_I225_TX_LATENCY_10 9542 305 #define IGC_I225_TX_LATENCY_100 1024 306 #define IGC_I225_TX_LATENCY_1000 178 307 #define IGC_I225_TX_LATENCY_2500 64 308 #define IGC_I225_RX_LATENCY_10 20662 309 #define IGC_I225_RX_LATENCY_100 2213 310 #define IGC_I225_RX_LATENCY_1000 448 311 #define IGC_I225_RX_LATENCY_2500 160 312 313 /* RX and TX descriptor control thresholds. 314 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 315 * descriptors available in its onboard memory. 316 * Setting this to 0 disables RX descriptor prefetch. 317 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 318 * available in host memory. 319 * If PTHRESH is 0, this should also be 0. 320 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 321 * descriptors until either it has this many to write back, or the 322 * ITR timer expires. 323 */ 324 #define IGC_RX_PTHRESH 8 325 #define IGC_RX_HTHRESH 8 326 #define IGC_TX_PTHRESH 8 327 #define IGC_TX_HTHRESH 1 328 #define IGC_RX_WTHRESH 4 329 #define IGC_TX_WTHRESH 16 330 331 #define IGC_RX_DMA_ATTR \ 332 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 333 334 #define IGC_TS_HDR_LEN 16 335 336 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 337 338 #if (PAGE_SIZE < 8192) 339 #define IGC_MAX_FRAME_BUILD_SKB \ 340 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN) 341 #else 342 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN) 343 #endif 344 345 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 346 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 347 348 /* VLAN info */ 349 #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000 350 351 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */ 352 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, 353 const u32 stat_err_bits) 354 { 355 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 356 } 357 358 enum igc_state_t { 359 __IGC_TESTING, 360 __IGC_RESETTING, 361 __IGC_DOWN, 362 __IGC_PTP_TX_IN_PROGRESS, 363 }; 364 365 enum igc_tx_flags { 366 /* cmd_type flags */ 367 IGC_TX_FLAGS_VLAN = 0x01, 368 IGC_TX_FLAGS_TSO = 0x02, 369 IGC_TX_FLAGS_TSTAMP = 0x04, 370 371 /* olinfo flags */ 372 IGC_TX_FLAGS_IPV4 = 0x10, 373 IGC_TX_FLAGS_CSUM = 0x20, 374 }; 375 376 enum igc_boards { 377 board_base, 378 }; 379 380 /* The largest size we can write to the descriptor is 65535. In order to 381 * maintain a power of two alignment we have to limit ourselves to 32K. 382 */ 383 #define IGC_MAX_TXD_PWR 15 384 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) 385 386 /* Tx Descriptors needed, worst case */ 387 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD) 388 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 389 390 /* wrapper around a pointer to a socket buffer, 391 * so a DMA handle can be stored along with the buffer 392 */ 393 struct igc_tx_buffer { 394 union igc_adv_tx_desc *next_to_watch; 395 unsigned long time_stamp; 396 struct sk_buff *skb; 397 unsigned int bytecount; 398 u16 gso_segs; 399 __be16 protocol; 400 401 DEFINE_DMA_UNMAP_ADDR(dma); 402 DEFINE_DMA_UNMAP_LEN(len); 403 u32 tx_flags; 404 }; 405 406 struct igc_rx_buffer { 407 dma_addr_t dma; 408 struct page *page; 409 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 410 __u32 page_offset; 411 #else 412 __u16 page_offset; 413 #endif 414 __u16 pagecnt_bias; 415 }; 416 417 struct igc_q_vector { 418 struct igc_adapter *adapter; /* backlink */ 419 void __iomem *itr_register; 420 u32 eims_value; /* EIMS mask value */ 421 422 u16 itr_val; 423 u8 set_itr; 424 425 struct igc_ring_container rx, tx; 426 427 struct napi_struct napi; 428 429 struct rcu_head rcu; /* to avoid race with update stats on free */ 430 char name[IFNAMSIZ + 9]; 431 struct net_device poll_dev; 432 433 /* for dynamic allocation of rings associated with this q_vector */ 434 struct igc_ring ring[] ____cacheline_internodealigned_in_smp; 435 }; 436 437 enum igc_filter_match_flags { 438 IGC_FILTER_FLAG_ETHER_TYPE = 0x1, 439 IGC_FILTER_FLAG_VLAN_TCI = 0x2, 440 IGC_FILTER_FLAG_SRC_MAC_ADDR = 0x4, 441 IGC_FILTER_FLAG_DST_MAC_ADDR = 0x8, 442 }; 443 444 /* RX network flow classification data structure */ 445 struct igc_nfc_input { 446 /* Byte layout in order, all values with MSB first: 447 * match_flags - 1 byte 448 * etype - 2 bytes 449 * vlan_tci - 2 bytes 450 */ 451 u8 match_flags; 452 __be16 etype; 453 __be16 vlan_tci; 454 u8 src_addr[ETH_ALEN]; 455 u8 dst_addr[ETH_ALEN]; 456 }; 457 458 struct igc_nfc_filter { 459 struct hlist_node nfc_node; 460 struct igc_nfc_input filter; 461 unsigned long cookie; 462 u16 etype_reg_index; 463 u16 sw_idx; 464 u16 action; 465 }; 466 467 struct igc_mac_addr { 468 u8 addr[ETH_ALEN]; 469 s8 queue; 470 u8 state; /* bitmask */ 471 }; 472 473 #define IGC_MAC_STATE_DEFAULT 0x1 474 #define IGC_MAC_STATE_IN_USE 0x2 475 #define IGC_MAC_STATE_SRC_ADDR 0x4 476 477 #define IGC_MAX_RXNFC_FILTERS 16 478 479 /* igc_desc_unused - calculate if we have unused descriptors */ 480 static inline u16 igc_desc_unused(const struct igc_ring *ring) 481 { 482 u16 ntc = ring->next_to_clean; 483 u16 ntu = ring->next_to_use; 484 485 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 486 } 487 488 static inline s32 igc_get_phy_info(struct igc_hw *hw) 489 { 490 if (hw->phy.ops.get_phy_info) 491 return hw->phy.ops.get_phy_info(hw); 492 493 return 0; 494 } 495 496 static inline s32 igc_reset_phy(struct igc_hw *hw) 497 { 498 if (hw->phy.ops.reset) 499 return hw->phy.ops.reset(hw); 500 501 return 0; 502 } 503 504 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring) 505 { 506 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 507 } 508 509 enum igc_ring_flags_t { 510 IGC_RING_FLAG_RX_3K_BUFFER, 511 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, 512 IGC_RING_FLAG_RX_SCTP_CSUM, 513 IGC_RING_FLAG_RX_LB_VLAN_BSWAP, 514 IGC_RING_FLAG_TX_CTX_IDX, 515 IGC_RING_FLAG_TX_DETECT_HANG 516 }; 517 518 #define ring_uses_large_buffer(ring) \ 519 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 520 521 #define ring_uses_build_skb(ring) \ 522 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 523 524 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring) 525 { 526 #if (PAGE_SIZE < 8192) 527 if (ring_uses_large_buffer(ring)) 528 return IGC_RXBUFFER_3072; 529 530 if (ring_uses_build_skb(ring)) 531 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN; 532 #endif 533 return IGC_RXBUFFER_2048; 534 } 535 536 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) 537 { 538 #if (PAGE_SIZE < 8192) 539 if (ring_uses_large_buffer(ring)) 540 return 1; 541 #endif 542 return 0; 543 } 544 545 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data) 546 { 547 if (hw->phy.ops.read_reg) 548 return hw->phy.ops.read_reg(hw, offset, data); 549 550 return 0; 551 } 552 553 /* forward declaration */ 554 void igc_reinit_locked(struct igc_adapter *); 555 int igc_add_filter(struct igc_adapter *adapter, 556 struct igc_nfc_filter *input); 557 int igc_erase_filter(struct igc_adapter *adapter, 558 struct igc_nfc_filter *input); 559 560 void igc_ptp_init(struct igc_adapter *adapter); 561 void igc_ptp_reset(struct igc_adapter *adapter); 562 void igc_ptp_suspend(struct igc_adapter *adapter); 563 void igc_ptp_stop(struct igc_adapter *adapter); 564 void igc_ptp_rx_rgtstamp(struct igc_q_vector *q_vector, struct sk_buff *skb); 565 void igc_ptp_rx_pktstamp(struct igc_q_vector *q_vector, void *va, 566 struct sk_buff *skb); 567 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); 568 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); 569 void igc_ptp_tx_hang(struct igc_adapter *adapter); 570 571 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring)) 572 573 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS) 574 575 #define IGC_RX_DESC(R, i) \ 576 (&(((union igc_adv_rx_desc *)((R)->desc))[i])) 577 #define IGC_TX_DESC(R, i) \ 578 (&(((union igc_adv_tx_desc *)((R)->desc))[i])) 579 #define IGC_TX_CTXTDESC(R, i) \ 580 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i])) 581 582 #endif /* _IGC_H_ */ 583