1 /******************************************************************************* 2 3 Intel(R) 82576 Virtual Function Linux driver 4 Copyright(c) 2009 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, see <http://www.gnu.org/licenses/>. 17 18 The full GNU General Public License is included in this distribution in 19 the file called "COPYING". 20 21 Contact Information: 22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 25 *******************************************************************************/ 26 27 #ifndef _E1000_REGS_H_ 28 #define _E1000_REGS_H_ 29 30 #define E1000_CTRL 0x00000 /* Device Control - RW */ 31 #define E1000_STATUS 0x00008 /* Device Status - RO */ 32 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 33 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ 34 #define E1000_EITR(_n) (0x01680 + (0x4 * (_n))) 35 #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */ 36 #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ 37 #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ 38 #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ 39 #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ 40 #define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */ 41 #define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */ 42 43 /* Convenience macros 44 * 45 * Note: "_n" is the queue number of the register to be written to. 46 * 47 * Example usage: 48 * E1000_RDBAL_REG(current_rx_queue) 49 */ 50 #define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \ 51 (0x0C000 + ((_n) * 0x40))) 52 #define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \ 53 (0x0C004 + ((_n) * 0x40))) 54 #define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \ 55 (0x0C008 + ((_n) * 0x40))) 56 #define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \ 57 (0x0C00C + ((_n) * 0x40))) 58 #define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \ 59 (0x0C010 + ((_n) * 0x40))) 60 #define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \ 61 (0x0C018 + ((_n) * 0x40))) 62 #define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \ 63 (0x0C028 + ((_n) * 0x40))) 64 #define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \ 65 (0x0E000 + ((_n) * 0x40))) 66 #define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \ 67 (0x0E004 + ((_n) * 0x40))) 68 #define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \ 69 (0x0E008 + ((_n) * 0x40))) 70 #define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \ 71 (0x0E010 + ((_n) * 0x40))) 72 #define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \ 73 (0x0E018 + ((_n) * 0x40))) 74 #define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \ 75 (0x0E028 + ((_n) * 0x40))) 76 #define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8)) 77 #define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8)) 78 #define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ 79 (0x054E0 + ((_i - 16) * 8))) 80 #define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ 81 (0x054E4 + ((_i - 16) * 8))) 82 83 /* Statistics registers */ 84 #define E1000_VFGPRC 0x00F10 85 #define E1000_VFGORC 0x00F18 86 #define E1000_VFMPRC 0x00F3C 87 #define E1000_VFGPTC 0x00F14 88 #define E1000_VFGOTC 0x00F34 89 #define E1000_VFGOTLBC 0x00F50 90 #define E1000_VFGPTLBC 0x00F44 91 #define E1000_VFGORLBC 0x00F48 92 #define E1000_VFGPRLBC 0x00F40 93 94 /* These act per VF so an array friendly macro is used */ 95 #define E1000_V2PMAILBOX(_n) (0x00C40 + (4 * (_n))) 96 #define E1000_VMBMEM(_n) (0x00800 + (64 * (_n))) 97 98 /* Define macros for handling registers */ 99 #define er32(reg) readl(hw->hw_addr + E1000_##reg) 100 #define ew32(reg, val) writel((val), hw->hw_addr + E1000_##reg) 101 #define array_er32(reg, offset) \ 102 readl(hw->hw_addr + E1000_##reg + (offset << 2)) 103 #define array_ew32(reg, offset, val) \ 104 writel((val), hw->hw_addr + E1000_##reg + (offset << 2)) 105 #define e1e_flush() er32(STATUS) 106 107 #endif 108