1 /******************************************************************************* 2 3 Intel(R) 82576 Virtual Function Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, see <http://www.gnu.org/licenses/>. 17 18 The full GNU General Public License is included in this distribution in 19 the file called "COPYING". 20 21 Contact Information: 22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 25 *******************************************************************************/ 26 27 #ifndef _E1000_DEFINES_H_ 28 #define _E1000_DEFINES_H_ 29 30 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 31 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 32 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 33 34 /* IVAR valid bit */ 35 #define E1000_IVAR_VALID 0x80 36 37 /* Receive Descriptor bit definitions */ 38 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 39 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 40 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 41 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 42 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 43 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 44 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 45 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 46 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 47 48 #define E1000_RXDEXT_STATERR_LB 0x00040000 49 #define E1000_RXDEXT_STATERR_CE 0x01000000 50 #define E1000_RXDEXT_STATERR_SE 0x02000000 51 #define E1000_RXDEXT_STATERR_SEQ 0x04000000 52 #define E1000_RXDEXT_STATERR_CXE 0x10000000 53 #define E1000_RXDEXT_STATERR_TCPE 0x20000000 54 #define E1000_RXDEXT_STATERR_IPE 0x40000000 55 #define E1000_RXDEXT_STATERR_RXE 0x80000000 56 57 /* Same mask, but for extended and packet split descriptors */ 58 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 59 E1000_RXDEXT_STATERR_CE | \ 60 E1000_RXDEXT_STATERR_SE | \ 61 E1000_RXDEXT_STATERR_SEQ | \ 62 E1000_RXDEXT_STATERR_CXE | \ 63 E1000_RXDEXT_STATERR_RXE) 64 65 /* Device Control */ 66 #define E1000_CTRL_RST 0x04000000 /* Global reset */ 67 68 /* Device Status */ 69 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 70 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 71 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 72 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 73 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 74 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 75 76 #define SPEED_10 10 77 #define SPEED_100 100 78 #define SPEED_1000 1000 79 #define HALF_DUPLEX 1 80 #define FULL_DUPLEX 2 81 82 /* Transmit Descriptor bit definitions */ 83 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 84 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 85 #define E1000_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */ 86 #define E1000_TXD_STAT_DD 0x00000001 /* Desc Done */ 87 88 #define MAX_JUMBO_FRAME_SIZE 0x3F00 89 90 /* 802.1q VLAN Packet Size */ 91 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ 92 93 /* Error Codes */ 94 #define E1000_SUCCESS 0 95 #define E1000_ERR_CONFIG 3 96 #define E1000_ERR_MAC_INIT 5 97 #define E1000_ERR_MBX 15 98 99 /* SRRCTL bit definitions */ 100 #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 101 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 102 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 103 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 104 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 105 #define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000 106 #define E1000_SRRCTL_DROP_EN 0x80000000 107 108 #define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F 109 #define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00 110 111 /* Additional Descriptor Control definitions */ 112 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Que */ 113 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Que */ 114 115 /* Direct Cache Access (DCA) definitions */ 116 #define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ 117 118 #define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 119 120 #endif /* _E1000_DEFINES_H_ */ 121