1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/sctp.h> 30 #include <linux/if_ether.h> 31 #include <linux/prefetch.h> 32 #include <linux/bpf.h> 33 #include <linux/bpf_trace.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/etherdevice.h> 36 #ifdef CONFIG_IGB_DCA 37 #include <linux/dca.h> 38 #endif 39 #include <linux/i2c.h> 40 #include "igb.h" 41 42 enum queue_mode { 43 QUEUE_MODE_STRICT_PRIORITY, 44 QUEUE_MODE_STREAM_RESERVATION, 45 }; 46 47 enum tx_queue_prio { 48 TX_QUEUE_PRIO_HIGH, 49 TX_QUEUE_PRIO_LOW, 50 }; 51 52 char igb_driver_name[] = "igb"; 53 static const char igb_driver_string[] = 54 "Intel(R) Gigabit Ethernet Network Driver"; 55 static const char igb_copyright[] = 56 "Copyright (c) 2007-2014 Intel Corporation."; 57 58 static const struct e1000_info *igb_info_tbl[] = { 59 [board_82575] = &e1000_82575_info, 60 }; 61 62 static const struct pci_device_id igb_pci_tbl[] = { 63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 98 /* required last entry */ 99 {0, } 100 }; 101 102 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 103 104 static int igb_setup_all_tx_resources(struct igb_adapter *); 105 static int igb_setup_all_rx_resources(struct igb_adapter *); 106 static void igb_free_all_tx_resources(struct igb_adapter *); 107 static void igb_free_all_rx_resources(struct igb_adapter *); 108 static void igb_setup_mrqc(struct igb_adapter *); 109 static void igb_init_queue_configuration(struct igb_adapter *adapter); 110 static int igb_sw_init(struct igb_adapter *); 111 int igb_open(struct net_device *); 112 int igb_close(struct net_device *); 113 static void igb_configure(struct igb_adapter *); 114 static void igb_configure_tx(struct igb_adapter *); 115 static void igb_configure_rx(struct igb_adapter *); 116 static void igb_clean_all_tx_rings(struct igb_adapter *); 117 static void igb_clean_all_rx_rings(struct igb_adapter *); 118 static void igb_set_rx_mode(struct net_device *); 119 static void igb_update_phy_info(struct timer_list *); 120 static void igb_watchdog(struct timer_list *); 121 static void igb_watchdog_task(struct work_struct *); 122 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 123 static void igb_get_stats64(struct net_device *dev, 124 struct rtnl_link_stats64 *stats); 125 static int igb_change_mtu(struct net_device *, int); 126 static int igb_set_mac(struct net_device *, void *); 127 static void igb_set_uta(struct igb_adapter *adapter, bool set); 128 static irqreturn_t igb_intr(int irq, void *); 129 static irqreturn_t igb_intr_msi(int irq, void *); 130 static irqreturn_t igb_msix_other(int irq, void *); 131 static irqreturn_t igb_msix_ring(int irq, void *); 132 #ifdef CONFIG_IGB_DCA 133 static void igb_update_dca(struct igb_q_vector *); 134 static void igb_setup_dca(struct igb_adapter *); 135 #endif /* CONFIG_IGB_DCA */ 136 static int igb_poll(struct napi_struct *, int); 137 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 138 static int igb_clean_rx_irq(struct igb_q_vector *, int); 139 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 140 static void igb_tx_timeout(struct net_device *, unsigned int txqueue); 141 static void igb_reset_task(struct work_struct *); 142 static void igb_vlan_mode(struct net_device *netdev, 143 netdev_features_t features); 144 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 145 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 146 static void igb_restore_vlan(struct igb_adapter *); 147 static void igb_rar_set_index(struct igb_adapter *, u32); 148 static void igb_ping_all_vfs(struct igb_adapter *); 149 static void igb_msg_task(struct igb_adapter *); 150 static void igb_vmm_control(struct igb_adapter *); 151 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 152 static void igb_flush_mac_table(struct igb_adapter *); 153 static int igb_available_rars(struct igb_adapter *, u8); 154 static void igb_set_default_mac_filter(struct igb_adapter *); 155 static int igb_uc_sync(struct net_device *, const unsigned char *); 156 static int igb_uc_unsync(struct net_device *, const unsigned char *); 157 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 158 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 159 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 160 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 161 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 162 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 163 bool setting); 164 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 165 bool setting); 166 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 167 struct ifla_vf_info *ivi); 168 static void igb_check_vf_rate_limit(struct igb_adapter *); 169 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 170 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 171 172 #ifdef CONFIG_PCI_IOV 173 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 174 static int igb_disable_sriov(struct pci_dev *dev, bool reinit); 175 #endif 176 177 #ifdef CONFIG_IGB_DCA 178 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 179 static struct notifier_block dca_notifier = { 180 .notifier_call = igb_notify_dca, 181 .next = NULL, 182 .priority = 0 183 }; 184 #endif 185 #ifdef CONFIG_PCI_IOV 186 static unsigned int max_vfs; 187 module_param(max_vfs, uint, 0444); 188 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 189 #endif /* CONFIG_PCI_IOV */ 190 191 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 192 pci_channel_state_t); 193 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 194 static void igb_io_resume(struct pci_dev *); 195 196 static const struct pci_error_handlers igb_err_handler = { 197 .error_detected = igb_io_error_detected, 198 .slot_reset = igb_io_slot_reset, 199 .resume = igb_io_resume, 200 }; 201 202 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 203 204 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 205 MODULE_LICENSE("GPL v2"); 206 207 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 208 static int debug = -1; 209 module_param(debug, int, 0); 210 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 211 212 struct igb_reg_info { 213 u32 ofs; 214 char *name; 215 }; 216 217 static const struct igb_reg_info igb_reg_info_tbl[] = { 218 219 /* General Registers */ 220 {E1000_CTRL, "CTRL"}, 221 {E1000_STATUS, "STATUS"}, 222 {E1000_CTRL_EXT, "CTRL_EXT"}, 223 224 /* Interrupt Registers */ 225 {E1000_ICR, "ICR"}, 226 227 /* RX Registers */ 228 {E1000_RCTL, "RCTL"}, 229 {E1000_RDLEN(0), "RDLEN"}, 230 {E1000_RDH(0), "RDH"}, 231 {E1000_RDT(0), "RDT"}, 232 {E1000_RXDCTL(0), "RXDCTL"}, 233 {E1000_RDBAL(0), "RDBAL"}, 234 {E1000_RDBAH(0), "RDBAH"}, 235 236 /* TX Registers */ 237 {E1000_TCTL, "TCTL"}, 238 {E1000_TDBAL(0), "TDBAL"}, 239 {E1000_TDBAH(0), "TDBAH"}, 240 {E1000_TDLEN(0), "TDLEN"}, 241 {E1000_TDH(0), "TDH"}, 242 {E1000_TDT(0), "TDT"}, 243 {E1000_TXDCTL(0), "TXDCTL"}, 244 {E1000_TDFH, "TDFH"}, 245 {E1000_TDFT, "TDFT"}, 246 {E1000_TDFHS, "TDFHS"}, 247 {E1000_TDFPC, "TDFPC"}, 248 249 /* List Terminator */ 250 {} 251 }; 252 253 /* igb_regdump - register printout routine */ 254 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 255 { 256 int n = 0; 257 char rname[16]; 258 u32 regs[8]; 259 260 switch (reginfo->ofs) { 261 case E1000_RDLEN(0): 262 for (n = 0; n < 4; n++) 263 regs[n] = rd32(E1000_RDLEN(n)); 264 break; 265 case E1000_RDH(0): 266 for (n = 0; n < 4; n++) 267 regs[n] = rd32(E1000_RDH(n)); 268 break; 269 case E1000_RDT(0): 270 for (n = 0; n < 4; n++) 271 regs[n] = rd32(E1000_RDT(n)); 272 break; 273 case E1000_RXDCTL(0): 274 for (n = 0; n < 4; n++) 275 regs[n] = rd32(E1000_RXDCTL(n)); 276 break; 277 case E1000_RDBAL(0): 278 for (n = 0; n < 4; n++) 279 regs[n] = rd32(E1000_RDBAL(n)); 280 break; 281 case E1000_RDBAH(0): 282 for (n = 0; n < 4; n++) 283 regs[n] = rd32(E1000_RDBAH(n)); 284 break; 285 case E1000_TDBAL(0): 286 for (n = 0; n < 4; n++) 287 regs[n] = rd32(E1000_TDBAL(n)); 288 break; 289 case E1000_TDBAH(0): 290 for (n = 0; n < 4; n++) 291 regs[n] = rd32(E1000_TDBAH(n)); 292 break; 293 case E1000_TDLEN(0): 294 for (n = 0; n < 4; n++) 295 regs[n] = rd32(E1000_TDLEN(n)); 296 break; 297 case E1000_TDH(0): 298 for (n = 0; n < 4; n++) 299 regs[n] = rd32(E1000_TDH(n)); 300 break; 301 case E1000_TDT(0): 302 for (n = 0; n < 4; n++) 303 regs[n] = rd32(E1000_TDT(n)); 304 break; 305 case E1000_TXDCTL(0): 306 for (n = 0; n < 4; n++) 307 regs[n] = rd32(E1000_TXDCTL(n)); 308 break; 309 default: 310 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 311 return; 312 } 313 314 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 315 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 316 regs[2], regs[3]); 317 } 318 319 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 320 static void igb_dump(struct igb_adapter *adapter) 321 { 322 struct net_device *netdev = adapter->netdev; 323 struct e1000_hw *hw = &adapter->hw; 324 struct igb_reg_info *reginfo; 325 struct igb_ring *tx_ring; 326 union e1000_adv_tx_desc *tx_desc; 327 struct my_u0 { __le64 a; __le64 b; } *u0; 328 struct igb_ring *rx_ring; 329 union e1000_adv_rx_desc *rx_desc; 330 u32 staterr; 331 u16 i, n; 332 333 if (!netif_msg_hw(adapter)) 334 return; 335 336 /* Print netdevice Info */ 337 if (netdev) { 338 dev_info(&adapter->pdev->dev, "Net device Info\n"); 339 pr_info("Device Name state trans_start\n"); 340 pr_info("%-15s %016lX %016lX\n", netdev->name, 341 netdev->state, dev_trans_start(netdev)); 342 } 343 344 /* Print Registers */ 345 dev_info(&adapter->pdev->dev, "Register Dump\n"); 346 pr_info(" Register Name Value\n"); 347 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 348 reginfo->name; reginfo++) { 349 igb_regdump(hw, reginfo); 350 } 351 352 /* Print TX Ring Summary */ 353 if (!netdev || !netif_running(netdev)) 354 goto exit; 355 356 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 357 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 358 for (n = 0; n < adapter->num_tx_queues; n++) { 359 struct igb_tx_buffer *buffer_info; 360 tx_ring = adapter->tx_ring[n]; 361 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 362 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 363 n, tx_ring->next_to_use, tx_ring->next_to_clean, 364 (u64)dma_unmap_addr(buffer_info, dma), 365 dma_unmap_len(buffer_info, len), 366 buffer_info->next_to_watch, 367 (u64)buffer_info->time_stamp); 368 } 369 370 /* Print TX Rings */ 371 if (!netif_msg_tx_done(adapter)) 372 goto rx_ring_summary; 373 374 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 375 376 /* Transmit Descriptor Formats 377 * 378 * Advanced Transmit Descriptor 379 * +--------------------------------------------------------------+ 380 * 0 | Buffer Address [63:0] | 381 * +--------------------------------------------------------------+ 382 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 383 * +--------------------------------------------------------------+ 384 * 63 46 45 40 39 38 36 35 32 31 24 15 0 385 */ 386 387 for (n = 0; n < adapter->num_tx_queues; n++) { 388 tx_ring = adapter->tx_ring[n]; 389 pr_info("------------------------------------\n"); 390 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 391 pr_info("------------------------------------\n"); 392 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 393 394 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 395 const char *next_desc; 396 struct igb_tx_buffer *buffer_info; 397 tx_desc = IGB_TX_DESC(tx_ring, i); 398 buffer_info = &tx_ring->tx_buffer_info[i]; 399 u0 = (struct my_u0 *)tx_desc; 400 if (i == tx_ring->next_to_use && 401 i == tx_ring->next_to_clean) 402 next_desc = " NTC/U"; 403 else if (i == tx_ring->next_to_use) 404 next_desc = " NTU"; 405 else if (i == tx_ring->next_to_clean) 406 next_desc = " NTC"; 407 else 408 next_desc = ""; 409 410 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 411 i, le64_to_cpu(u0->a), 412 le64_to_cpu(u0->b), 413 (u64)dma_unmap_addr(buffer_info, dma), 414 dma_unmap_len(buffer_info, len), 415 buffer_info->next_to_watch, 416 (u64)buffer_info->time_stamp, 417 buffer_info->skb, next_desc); 418 419 if (netif_msg_pktdata(adapter) && buffer_info->skb) 420 print_hex_dump(KERN_INFO, "", 421 DUMP_PREFIX_ADDRESS, 422 16, 1, buffer_info->skb->data, 423 dma_unmap_len(buffer_info, len), 424 true); 425 } 426 } 427 428 /* Print RX Rings Summary */ 429 rx_ring_summary: 430 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 431 pr_info("Queue [NTU] [NTC]\n"); 432 for (n = 0; n < adapter->num_rx_queues; n++) { 433 rx_ring = adapter->rx_ring[n]; 434 pr_info(" %5d %5X %5X\n", 435 n, rx_ring->next_to_use, rx_ring->next_to_clean); 436 } 437 438 /* Print RX Rings */ 439 if (!netif_msg_rx_status(adapter)) 440 goto exit; 441 442 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 443 444 /* Advanced Receive Descriptor (Read) Format 445 * 63 1 0 446 * +-----------------------------------------------------+ 447 * 0 | Packet Buffer Address [63:1] |A0/NSE| 448 * +----------------------------------------------+------+ 449 * 8 | Header Buffer Address [63:1] | DD | 450 * +-----------------------------------------------------+ 451 * 452 * 453 * Advanced Receive Descriptor (Write-Back) Format 454 * 455 * 63 48 47 32 31 30 21 20 17 16 4 3 0 456 * +------------------------------------------------------+ 457 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 458 * | Checksum Ident | | | | Type | Type | 459 * +------------------------------------------------------+ 460 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 461 * +------------------------------------------------------+ 462 * 63 48 47 32 31 20 19 0 463 */ 464 465 for (n = 0; n < adapter->num_rx_queues; n++) { 466 rx_ring = adapter->rx_ring[n]; 467 pr_info("------------------------------------\n"); 468 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 469 pr_info("------------------------------------\n"); 470 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 471 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 472 473 for (i = 0; i < rx_ring->count; i++) { 474 const char *next_desc; 475 dma_addr_t dma = (dma_addr_t)0; 476 struct igb_rx_buffer *buffer_info = NULL; 477 rx_desc = IGB_RX_DESC(rx_ring, i); 478 u0 = (struct my_u0 *)rx_desc; 479 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 480 481 if (!rx_ring->xsk_pool) { 482 buffer_info = &rx_ring->rx_buffer_info[i]; 483 dma = buffer_info->dma; 484 } 485 486 if (i == rx_ring->next_to_use) 487 next_desc = " NTU"; 488 else if (i == rx_ring->next_to_clean) 489 next_desc = " NTC"; 490 else 491 next_desc = ""; 492 493 if (staterr & E1000_RXD_STAT_DD) { 494 /* Descriptor Done */ 495 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 496 "RWB", i, 497 le64_to_cpu(u0->a), 498 le64_to_cpu(u0->b), 499 next_desc); 500 } else { 501 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 502 "R ", i, 503 le64_to_cpu(u0->a), 504 le64_to_cpu(u0->b), 505 (u64)dma, 506 next_desc); 507 508 if (netif_msg_pktdata(adapter) && 509 buffer_info && dma && buffer_info->page) { 510 print_hex_dump(KERN_INFO, "", 511 DUMP_PREFIX_ADDRESS, 512 16, 1, 513 page_address(buffer_info->page) + 514 buffer_info->page_offset, 515 igb_rx_bufsz(rx_ring), true); 516 } 517 } 518 } 519 } 520 521 exit: 522 return; 523 } 524 525 /** 526 * igb_get_i2c_data - Reads the I2C SDA data bit 527 * @data: opaque pointer to adapter struct 528 * 529 * Returns the I2C data bit value 530 **/ 531 static int igb_get_i2c_data(void *data) 532 { 533 struct igb_adapter *adapter = (struct igb_adapter *)data; 534 struct e1000_hw *hw = &adapter->hw; 535 s32 i2cctl = rd32(E1000_I2CPARAMS); 536 537 return !!(i2cctl & E1000_I2C_DATA_IN); 538 } 539 540 /** 541 * igb_set_i2c_data - Sets the I2C data bit 542 * @data: pointer to hardware structure 543 * @state: I2C data value (0 or 1) to set 544 * 545 * Sets the I2C data bit 546 **/ 547 static void igb_set_i2c_data(void *data, int state) 548 { 549 struct igb_adapter *adapter = (struct igb_adapter *)data; 550 struct e1000_hw *hw = &adapter->hw; 551 s32 i2cctl = rd32(E1000_I2CPARAMS); 552 553 if (state) { 554 i2cctl |= E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N; 555 } else { 556 i2cctl &= ~E1000_I2C_DATA_OE_N; 557 i2cctl &= ~E1000_I2C_DATA_OUT; 558 } 559 560 wr32(E1000_I2CPARAMS, i2cctl); 561 wrfl(); 562 } 563 564 /** 565 * igb_set_i2c_clk - Sets the I2C SCL clock 566 * @data: pointer to hardware structure 567 * @state: state to set clock 568 * 569 * Sets the I2C clock line to state 570 **/ 571 static void igb_set_i2c_clk(void *data, int state) 572 { 573 struct igb_adapter *adapter = (struct igb_adapter *)data; 574 struct e1000_hw *hw = &adapter->hw; 575 s32 i2cctl = rd32(E1000_I2CPARAMS); 576 577 if (state) { 578 i2cctl |= E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N; 579 } else { 580 i2cctl &= ~E1000_I2C_CLK_OUT; 581 i2cctl &= ~E1000_I2C_CLK_OE_N; 582 } 583 wr32(E1000_I2CPARAMS, i2cctl); 584 wrfl(); 585 } 586 587 /** 588 * igb_get_i2c_clk - Gets the I2C SCL clock state 589 * @data: pointer to hardware structure 590 * 591 * Gets the I2C clock state 592 **/ 593 static int igb_get_i2c_clk(void *data) 594 { 595 struct igb_adapter *adapter = (struct igb_adapter *)data; 596 struct e1000_hw *hw = &adapter->hw; 597 s32 i2cctl = rd32(E1000_I2CPARAMS); 598 599 return !!(i2cctl & E1000_I2C_CLK_IN); 600 } 601 602 static const struct i2c_algo_bit_data igb_i2c_algo = { 603 .setsda = igb_set_i2c_data, 604 .setscl = igb_set_i2c_clk, 605 .getsda = igb_get_i2c_data, 606 .getscl = igb_get_i2c_clk, 607 .udelay = 5, 608 .timeout = 20, 609 }; 610 611 /** 612 * igb_get_hw_dev - return device 613 * @hw: pointer to hardware structure 614 * 615 * used by hardware layer to print debugging information 616 **/ 617 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 618 { 619 struct igb_adapter *adapter = hw->back; 620 return adapter->netdev; 621 } 622 623 static struct pci_driver igb_driver; 624 625 /** 626 * igb_init_module - Driver Registration Routine 627 * 628 * igb_init_module is the first routine called when the driver is 629 * loaded. All it does is register with the PCI subsystem. 630 **/ 631 static int __init igb_init_module(void) 632 { 633 int ret; 634 635 pr_info("%s\n", igb_driver_string); 636 pr_info("%s\n", igb_copyright); 637 638 #ifdef CONFIG_IGB_DCA 639 dca_register_notify(&dca_notifier); 640 #endif 641 ret = pci_register_driver(&igb_driver); 642 #ifdef CONFIG_IGB_DCA 643 if (ret) 644 dca_unregister_notify(&dca_notifier); 645 #endif 646 return ret; 647 } 648 649 module_init(igb_init_module); 650 651 /** 652 * igb_exit_module - Driver Exit Cleanup Routine 653 * 654 * igb_exit_module is called just before the driver is removed 655 * from memory. 656 **/ 657 static void __exit igb_exit_module(void) 658 { 659 #ifdef CONFIG_IGB_DCA 660 dca_unregister_notify(&dca_notifier); 661 #endif 662 pci_unregister_driver(&igb_driver); 663 } 664 665 module_exit(igb_exit_module); 666 667 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 668 /** 669 * igb_cache_ring_register - Descriptor ring to register mapping 670 * @adapter: board private structure to initialize 671 * 672 * Once we know the feature-set enabled for the device, we'll cache 673 * the register offset the descriptor ring is assigned to. 674 **/ 675 static void igb_cache_ring_register(struct igb_adapter *adapter) 676 { 677 int i = 0, j = 0; 678 u32 rbase_offset = adapter->vfs_allocated_count; 679 680 switch (adapter->hw.mac.type) { 681 case e1000_82576: 682 /* The queues are allocated for virtualization such that VF 0 683 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 684 * In order to avoid collision we start at the first free queue 685 * and continue consuming queues in the same sequence 686 */ 687 if (adapter->vfs_allocated_count) { 688 for (; i < adapter->rss_queues; i++) 689 adapter->rx_ring[i]->reg_idx = rbase_offset + 690 Q_IDX_82576(i); 691 } 692 fallthrough; 693 case e1000_82575: 694 case e1000_82580: 695 case e1000_i350: 696 case e1000_i354: 697 case e1000_i210: 698 case e1000_i211: 699 default: 700 for (; i < adapter->num_rx_queues; i++) 701 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 702 for (; j < adapter->num_tx_queues; j++) 703 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 704 break; 705 } 706 } 707 708 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 709 { 710 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 711 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 712 u32 value = 0; 713 714 if (E1000_REMOVED(hw_addr)) 715 return ~value; 716 717 value = readl(&hw_addr[reg]); 718 719 /* reads should not return all F's */ 720 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 721 struct net_device *netdev = igb->netdev; 722 hw->hw_addr = NULL; 723 netdev_err(netdev, "PCIe link lost\n"); 724 WARN(pci_device_is_present(igb->pdev), 725 "igb: Failed to read reg 0x%x!\n", reg); 726 } 727 728 return value; 729 } 730 731 /** 732 * igb_write_ivar - configure ivar for given MSI-X vector 733 * @hw: pointer to the HW structure 734 * @msix_vector: vector number we are allocating to a given ring 735 * @index: row index of IVAR register to write within IVAR table 736 * @offset: column offset of in IVAR, should be multiple of 8 737 * 738 * This function is intended to handle the writing of the IVAR register 739 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 740 * each containing an cause allocation for an Rx and Tx ring, and a 741 * variable number of rows depending on the number of queues supported. 742 **/ 743 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 744 int index, int offset) 745 { 746 u32 ivar = array_rd32(E1000_IVAR0, index); 747 748 /* clear any bits that are currently set */ 749 ivar &= ~((u32)0xFF << offset); 750 751 /* write vector and valid bit */ 752 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 753 754 array_wr32(E1000_IVAR0, index, ivar); 755 } 756 757 #define IGB_N0_QUEUE -1 758 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 759 { 760 struct igb_adapter *adapter = q_vector->adapter; 761 struct e1000_hw *hw = &adapter->hw; 762 int rx_queue = IGB_N0_QUEUE; 763 int tx_queue = IGB_N0_QUEUE; 764 u32 msixbm = 0; 765 766 if (q_vector->rx.ring) 767 rx_queue = q_vector->rx.ring->reg_idx; 768 if (q_vector->tx.ring) 769 tx_queue = q_vector->tx.ring->reg_idx; 770 771 switch (hw->mac.type) { 772 case e1000_82575: 773 /* The 82575 assigns vectors using a bitmask, which matches the 774 * bitmask for the EICR/EIMS/EIMC registers. To assign one 775 * or more queues to a vector, we write the appropriate bits 776 * into the MSIXBM register for that vector. 777 */ 778 if (rx_queue > IGB_N0_QUEUE) 779 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 780 if (tx_queue > IGB_N0_QUEUE) 781 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 782 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 783 msixbm |= E1000_EIMS_OTHER; 784 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 785 q_vector->eims_value = msixbm; 786 break; 787 case e1000_82576: 788 /* 82576 uses a table that essentially consists of 2 columns 789 * with 8 rows. The ordering is column-major so we use the 790 * lower 3 bits as the row index, and the 4th bit as the 791 * column offset. 792 */ 793 if (rx_queue > IGB_N0_QUEUE) 794 igb_write_ivar(hw, msix_vector, 795 rx_queue & 0x7, 796 (rx_queue & 0x8) << 1); 797 if (tx_queue > IGB_N0_QUEUE) 798 igb_write_ivar(hw, msix_vector, 799 tx_queue & 0x7, 800 ((tx_queue & 0x8) << 1) + 8); 801 q_vector->eims_value = BIT(msix_vector); 802 break; 803 case e1000_82580: 804 case e1000_i350: 805 case e1000_i354: 806 case e1000_i210: 807 case e1000_i211: 808 /* On 82580 and newer adapters the scheme is similar to 82576 809 * however instead of ordering column-major we have things 810 * ordered row-major. So we traverse the table by using 811 * bit 0 as the column offset, and the remaining bits as the 812 * row index. 813 */ 814 if (rx_queue > IGB_N0_QUEUE) 815 igb_write_ivar(hw, msix_vector, 816 rx_queue >> 1, 817 (rx_queue & 0x1) << 4); 818 if (tx_queue > IGB_N0_QUEUE) 819 igb_write_ivar(hw, msix_vector, 820 tx_queue >> 1, 821 ((tx_queue & 0x1) << 4) + 8); 822 q_vector->eims_value = BIT(msix_vector); 823 break; 824 default: 825 BUG(); 826 break; 827 } 828 829 /* add q_vector eims value to global eims_enable_mask */ 830 adapter->eims_enable_mask |= q_vector->eims_value; 831 832 /* configure q_vector to set itr on first interrupt */ 833 q_vector->set_itr = 1; 834 } 835 836 /** 837 * igb_configure_msix - Configure MSI-X hardware 838 * @adapter: board private structure to initialize 839 * 840 * igb_configure_msix sets up the hardware to properly 841 * generate MSI-X interrupts. 842 **/ 843 static void igb_configure_msix(struct igb_adapter *adapter) 844 { 845 u32 tmp; 846 int i, vector = 0; 847 struct e1000_hw *hw = &adapter->hw; 848 849 adapter->eims_enable_mask = 0; 850 851 /* set vector for other causes, i.e. link changes */ 852 switch (hw->mac.type) { 853 case e1000_82575: 854 tmp = rd32(E1000_CTRL_EXT); 855 /* enable MSI-X PBA support*/ 856 tmp |= E1000_CTRL_EXT_PBA_CLR; 857 858 /* Auto-Mask interrupts upon ICR read. */ 859 tmp |= E1000_CTRL_EXT_EIAME; 860 tmp |= E1000_CTRL_EXT_IRCA; 861 862 wr32(E1000_CTRL_EXT, tmp); 863 864 /* enable msix_other interrupt */ 865 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 866 adapter->eims_other = E1000_EIMS_OTHER; 867 868 break; 869 870 case e1000_82576: 871 case e1000_82580: 872 case e1000_i350: 873 case e1000_i354: 874 case e1000_i210: 875 case e1000_i211: 876 /* Turn on MSI-X capability first, or our settings 877 * won't stick. And it will take days to debug. 878 */ 879 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 880 E1000_GPIE_PBA | E1000_GPIE_EIAME | 881 E1000_GPIE_NSICR); 882 883 /* enable msix_other interrupt */ 884 adapter->eims_other = BIT(vector); 885 tmp = (vector++ | E1000_IVAR_VALID) << 8; 886 887 wr32(E1000_IVAR_MISC, tmp); 888 break; 889 default: 890 /* do nothing, since nothing else supports MSI-X */ 891 break; 892 } /* switch (hw->mac.type) */ 893 894 adapter->eims_enable_mask |= adapter->eims_other; 895 896 for (i = 0; i < adapter->num_q_vectors; i++) 897 igb_assign_vector(adapter->q_vector[i], vector++); 898 899 wrfl(); 900 } 901 902 /** 903 * igb_request_msix - Initialize MSI-X interrupts 904 * @adapter: board private structure to initialize 905 * 906 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 907 * kernel. 908 **/ 909 static int igb_request_msix(struct igb_adapter *adapter) 910 { 911 unsigned int num_q_vectors = adapter->num_q_vectors; 912 struct net_device *netdev = adapter->netdev; 913 int i, err = 0, vector = 0, free_vector = 0; 914 915 err = request_irq(adapter->msix_entries[vector].vector, 916 igb_msix_other, 0, netdev->name, adapter); 917 if (err) 918 goto err_out; 919 920 if (num_q_vectors > MAX_Q_VECTORS) { 921 num_q_vectors = MAX_Q_VECTORS; 922 dev_warn(&adapter->pdev->dev, 923 "The number of queue vectors (%d) is higher than max allowed (%d)\n", 924 adapter->num_q_vectors, MAX_Q_VECTORS); 925 } 926 for (i = 0; i < num_q_vectors; i++) { 927 struct igb_q_vector *q_vector = adapter->q_vector[i]; 928 929 vector++; 930 931 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 932 933 if (q_vector->rx.ring && q_vector->tx.ring) 934 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 935 q_vector->rx.ring->queue_index); 936 else if (q_vector->tx.ring) 937 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 938 q_vector->tx.ring->queue_index); 939 else if (q_vector->rx.ring) 940 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 941 q_vector->rx.ring->queue_index); 942 else 943 sprintf(q_vector->name, "%s-unused", netdev->name); 944 945 err = request_irq(adapter->msix_entries[vector].vector, 946 igb_msix_ring, 0, q_vector->name, 947 q_vector); 948 if (err) 949 goto err_free; 950 } 951 952 igb_configure_msix(adapter); 953 return 0; 954 955 err_free: 956 /* free already assigned IRQs */ 957 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 958 959 vector--; 960 for (i = 0; i < vector; i++) { 961 free_irq(adapter->msix_entries[free_vector++].vector, 962 adapter->q_vector[i]); 963 } 964 err_out: 965 return err; 966 } 967 968 /** 969 * igb_free_q_vector - Free memory allocated for specific interrupt vector 970 * @adapter: board private structure to initialize 971 * @v_idx: Index of vector to be freed 972 * 973 * This function frees the memory allocated to the q_vector. 974 **/ 975 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 976 { 977 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 978 979 adapter->q_vector[v_idx] = NULL; 980 981 /* igb_get_stats64() might access the rings on this vector, 982 * we must wait a grace period before freeing it. 983 */ 984 if (q_vector) 985 kfree_rcu(q_vector, rcu); 986 } 987 988 /** 989 * igb_reset_q_vector - Reset config for interrupt vector 990 * @adapter: board private structure to initialize 991 * @v_idx: Index of vector to be reset 992 * 993 * If NAPI is enabled it will delete any references to the 994 * NAPI struct. This is preparation for igb_free_q_vector. 995 **/ 996 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 997 { 998 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 999 1000 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1001 * allocated. So, q_vector is NULL so we should stop here. 1002 */ 1003 if (!q_vector) 1004 return; 1005 1006 if (q_vector->tx.ring) 1007 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1008 1009 if (q_vector->rx.ring) 1010 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1011 1012 netif_napi_del(&q_vector->napi); 1013 1014 } 1015 1016 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1017 { 1018 int v_idx = adapter->num_q_vectors; 1019 1020 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1021 pci_disable_msix(adapter->pdev); 1022 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1023 pci_disable_msi(adapter->pdev); 1024 1025 while (v_idx--) 1026 igb_reset_q_vector(adapter, v_idx); 1027 } 1028 1029 /** 1030 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1031 * @adapter: board private structure to initialize 1032 * 1033 * This function frees the memory allocated to the q_vectors. In addition if 1034 * NAPI is enabled it will delete any references to the NAPI struct prior 1035 * to freeing the q_vector. 1036 **/ 1037 static void igb_free_q_vectors(struct igb_adapter *adapter) 1038 { 1039 int v_idx = adapter->num_q_vectors; 1040 1041 adapter->num_tx_queues = 0; 1042 adapter->num_rx_queues = 0; 1043 adapter->num_q_vectors = 0; 1044 1045 while (v_idx--) { 1046 igb_reset_q_vector(adapter, v_idx); 1047 igb_free_q_vector(adapter, v_idx); 1048 } 1049 } 1050 1051 /** 1052 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1053 * @adapter: board private structure to initialize 1054 * 1055 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1056 * MSI-X interrupts allocated. 1057 */ 1058 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1059 { 1060 igb_free_q_vectors(adapter); 1061 igb_reset_interrupt_capability(adapter); 1062 } 1063 1064 /** 1065 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1066 * @adapter: board private structure to initialize 1067 * @msix: boolean value of MSIX capability 1068 * 1069 * Attempt to configure interrupts using the best available 1070 * capabilities of the hardware and kernel. 1071 **/ 1072 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1073 { 1074 int err; 1075 int numvecs, i; 1076 1077 if (!msix) 1078 goto msi_only; 1079 adapter->flags |= IGB_FLAG_HAS_MSIX; 1080 1081 /* Number of supported queues. */ 1082 adapter->num_rx_queues = adapter->rss_queues; 1083 if (adapter->vfs_allocated_count) 1084 adapter->num_tx_queues = 1; 1085 else 1086 adapter->num_tx_queues = adapter->rss_queues; 1087 1088 /* start with one vector for every Rx queue */ 1089 numvecs = adapter->num_rx_queues; 1090 1091 /* if Tx handler is separate add 1 for every Tx queue */ 1092 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1093 numvecs += adapter->num_tx_queues; 1094 1095 /* store the number of vectors reserved for queues */ 1096 adapter->num_q_vectors = numvecs; 1097 1098 /* add 1 vector for link status interrupts */ 1099 numvecs++; 1100 for (i = 0; i < numvecs; i++) 1101 adapter->msix_entries[i].entry = i; 1102 1103 err = pci_enable_msix_range(adapter->pdev, 1104 adapter->msix_entries, 1105 numvecs, 1106 numvecs); 1107 if (err > 0) 1108 return; 1109 1110 igb_reset_interrupt_capability(adapter); 1111 1112 /* If we can't do MSI-X, try MSI */ 1113 msi_only: 1114 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1115 #ifdef CONFIG_PCI_IOV 1116 /* disable SR-IOV for non MSI-X configurations */ 1117 if (adapter->vf_data) { 1118 struct e1000_hw *hw = &adapter->hw; 1119 /* disable iov and allow time for transactions to clear */ 1120 pci_disable_sriov(adapter->pdev); 1121 msleep(500); 1122 1123 kfree(adapter->vf_mac_list); 1124 adapter->vf_mac_list = NULL; 1125 kfree(adapter->vf_data); 1126 adapter->vf_data = NULL; 1127 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1128 wrfl(); 1129 msleep(100); 1130 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1131 } 1132 #endif 1133 adapter->vfs_allocated_count = 0; 1134 adapter->rss_queues = 1; 1135 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1136 adapter->num_rx_queues = 1; 1137 adapter->num_tx_queues = 1; 1138 adapter->num_q_vectors = 1; 1139 if (!pci_enable_msi(adapter->pdev)) 1140 adapter->flags |= IGB_FLAG_HAS_MSI; 1141 } 1142 1143 static void igb_add_ring(struct igb_ring *ring, 1144 struct igb_ring_container *head) 1145 { 1146 head->ring = ring; 1147 head->count++; 1148 } 1149 1150 /** 1151 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1152 * @adapter: board private structure to initialize 1153 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1154 * @v_idx: index of vector in adapter struct 1155 * @txr_count: total number of Tx rings to allocate 1156 * @txr_idx: index of first Tx ring to allocate 1157 * @rxr_count: total number of Rx rings to allocate 1158 * @rxr_idx: index of first Rx ring to allocate 1159 * 1160 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1161 **/ 1162 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1163 int v_count, int v_idx, 1164 int txr_count, int txr_idx, 1165 int rxr_count, int rxr_idx) 1166 { 1167 struct igb_q_vector *q_vector; 1168 struct igb_ring *ring; 1169 int ring_count; 1170 size_t size; 1171 1172 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1173 if (txr_count > 1 || rxr_count > 1) 1174 return -ENOMEM; 1175 1176 ring_count = txr_count + rxr_count; 1177 size = kmalloc_size_roundup(struct_size(q_vector, ring, ring_count)); 1178 1179 /* allocate q_vector and rings */ 1180 q_vector = adapter->q_vector[v_idx]; 1181 if (!q_vector) { 1182 q_vector = kzalloc(size, GFP_KERNEL); 1183 } else if (size > ksize(q_vector)) { 1184 struct igb_q_vector *new_q_vector; 1185 1186 new_q_vector = kzalloc(size, GFP_KERNEL); 1187 if (new_q_vector) 1188 kfree_rcu(q_vector, rcu); 1189 q_vector = new_q_vector; 1190 } else { 1191 memset(q_vector, 0, size); 1192 } 1193 if (!q_vector) 1194 return -ENOMEM; 1195 1196 /* initialize NAPI */ 1197 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll); 1198 1199 /* tie q_vector and adapter together */ 1200 adapter->q_vector[v_idx] = q_vector; 1201 q_vector->adapter = adapter; 1202 1203 /* initialize work limits */ 1204 q_vector->tx.work_limit = adapter->tx_work_limit; 1205 1206 /* initialize ITR configuration */ 1207 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1208 q_vector->itr_val = IGB_START_ITR; 1209 1210 /* initialize pointer to rings */ 1211 ring = q_vector->ring; 1212 1213 /* initialize ITR */ 1214 if (rxr_count) { 1215 /* rx or rx/tx vector */ 1216 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1217 q_vector->itr_val = adapter->rx_itr_setting; 1218 } else { 1219 /* tx only vector */ 1220 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1221 q_vector->itr_val = adapter->tx_itr_setting; 1222 } 1223 1224 if (txr_count) { 1225 /* assign generic ring traits */ 1226 ring->dev = &adapter->pdev->dev; 1227 ring->netdev = adapter->netdev; 1228 1229 /* configure backlink on ring */ 1230 ring->q_vector = q_vector; 1231 1232 /* update q_vector Tx values */ 1233 igb_add_ring(ring, &q_vector->tx); 1234 1235 /* For 82575, context index must be unique per ring. */ 1236 if (adapter->hw.mac.type == e1000_82575) 1237 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1238 1239 /* apply Tx specific ring traits */ 1240 ring->count = adapter->tx_ring_count; 1241 ring->queue_index = txr_idx; 1242 1243 ring->cbs_enable = false; 1244 ring->idleslope = 0; 1245 ring->sendslope = 0; 1246 ring->hicredit = 0; 1247 ring->locredit = 0; 1248 1249 u64_stats_init(&ring->tx_syncp); 1250 u64_stats_init(&ring->tx_syncp2); 1251 1252 /* assign ring to adapter */ 1253 adapter->tx_ring[txr_idx] = ring; 1254 1255 /* push pointer to next ring */ 1256 ring++; 1257 } 1258 1259 if (rxr_count) { 1260 /* assign generic ring traits */ 1261 ring->dev = &adapter->pdev->dev; 1262 ring->netdev = adapter->netdev; 1263 1264 /* configure backlink on ring */ 1265 ring->q_vector = q_vector; 1266 1267 /* update q_vector Rx values */ 1268 igb_add_ring(ring, &q_vector->rx); 1269 1270 /* set flag indicating ring supports SCTP checksum offload */ 1271 if (adapter->hw.mac.type >= e1000_82576) 1272 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1273 1274 /* On i350, i354, i210, and i211, loopback VLAN packets 1275 * have the tag byte-swapped. 1276 */ 1277 if (adapter->hw.mac.type >= e1000_i350) 1278 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1279 1280 /* apply Rx specific ring traits */ 1281 ring->count = adapter->rx_ring_count; 1282 ring->queue_index = rxr_idx; 1283 1284 u64_stats_init(&ring->rx_syncp); 1285 1286 /* assign ring to adapter */ 1287 adapter->rx_ring[rxr_idx] = ring; 1288 } 1289 1290 return 0; 1291 } 1292 1293 1294 /** 1295 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1296 * @adapter: board private structure to initialize 1297 * 1298 * We allocate one q_vector per queue interrupt. If allocation fails we 1299 * return -ENOMEM. 1300 **/ 1301 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1302 { 1303 int q_vectors = adapter->num_q_vectors; 1304 int rxr_remaining = adapter->num_rx_queues; 1305 int txr_remaining = adapter->num_tx_queues; 1306 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1307 int err; 1308 1309 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1310 for (; rxr_remaining; v_idx++) { 1311 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1312 0, 0, 1, rxr_idx); 1313 1314 if (err) 1315 goto err_out; 1316 1317 /* update counts and index */ 1318 rxr_remaining--; 1319 rxr_idx++; 1320 } 1321 } 1322 1323 for (; v_idx < q_vectors; v_idx++) { 1324 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1325 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1326 1327 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1328 tqpv, txr_idx, rqpv, rxr_idx); 1329 1330 if (err) 1331 goto err_out; 1332 1333 /* update counts and index */ 1334 rxr_remaining -= rqpv; 1335 txr_remaining -= tqpv; 1336 rxr_idx++; 1337 txr_idx++; 1338 } 1339 1340 return 0; 1341 1342 err_out: 1343 adapter->num_tx_queues = 0; 1344 adapter->num_rx_queues = 0; 1345 adapter->num_q_vectors = 0; 1346 1347 while (v_idx--) 1348 igb_free_q_vector(adapter, v_idx); 1349 1350 return -ENOMEM; 1351 } 1352 1353 /** 1354 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1355 * @adapter: board private structure to initialize 1356 * @msix: boolean value of MSIX capability 1357 * 1358 * This function initializes the interrupts and allocates all of the queues. 1359 **/ 1360 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1361 { 1362 struct pci_dev *pdev = adapter->pdev; 1363 int err; 1364 1365 igb_set_interrupt_capability(adapter, msix); 1366 1367 err = igb_alloc_q_vectors(adapter); 1368 if (err) { 1369 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1370 goto err_alloc_q_vectors; 1371 } 1372 1373 igb_cache_ring_register(adapter); 1374 1375 return 0; 1376 1377 err_alloc_q_vectors: 1378 igb_reset_interrupt_capability(adapter); 1379 return err; 1380 } 1381 1382 /** 1383 * igb_request_irq - initialize interrupts 1384 * @adapter: board private structure to initialize 1385 * 1386 * Attempts to configure interrupts using the best available 1387 * capabilities of the hardware and kernel. 1388 **/ 1389 static int igb_request_irq(struct igb_adapter *adapter) 1390 { 1391 struct net_device *netdev = adapter->netdev; 1392 struct pci_dev *pdev = adapter->pdev; 1393 int err = 0; 1394 1395 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1396 err = igb_request_msix(adapter); 1397 if (!err) 1398 goto request_done; 1399 /* fall back to MSI */ 1400 igb_free_all_tx_resources(adapter); 1401 igb_free_all_rx_resources(adapter); 1402 1403 igb_clear_interrupt_scheme(adapter); 1404 err = igb_init_interrupt_scheme(adapter, false); 1405 if (err) 1406 goto request_done; 1407 1408 igb_setup_all_tx_resources(adapter); 1409 igb_setup_all_rx_resources(adapter); 1410 igb_configure(adapter); 1411 } 1412 1413 igb_assign_vector(adapter->q_vector[0], 0); 1414 1415 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1416 err = request_irq(pdev->irq, igb_intr_msi, 0, 1417 netdev->name, adapter); 1418 if (!err) 1419 goto request_done; 1420 1421 /* fall back to legacy interrupts */ 1422 igb_reset_interrupt_capability(adapter); 1423 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1424 } 1425 1426 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1427 netdev->name, adapter); 1428 1429 if (err) 1430 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1431 err); 1432 1433 request_done: 1434 return err; 1435 } 1436 1437 static void igb_free_irq(struct igb_adapter *adapter) 1438 { 1439 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1440 int vector = 0, i; 1441 1442 free_irq(adapter->msix_entries[vector++].vector, adapter); 1443 1444 for (i = 0; i < adapter->num_q_vectors; i++) 1445 free_irq(adapter->msix_entries[vector++].vector, 1446 adapter->q_vector[i]); 1447 } else { 1448 free_irq(adapter->pdev->irq, adapter); 1449 } 1450 } 1451 1452 /** 1453 * igb_irq_disable - Mask off interrupt generation on the NIC 1454 * @adapter: board private structure 1455 **/ 1456 static void igb_irq_disable(struct igb_adapter *adapter) 1457 { 1458 struct e1000_hw *hw = &adapter->hw; 1459 1460 /* we need to be careful when disabling interrupts. The VFs are also 1461 * mapped into these registers and so clearing the bits can cause 1462 * issues on the VF drivers so we only need to clear what we set 1463 */ 1464 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1465 u32 regval = rd32(E1000_EIAM); 1466 1467 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1468 wr32(E1000_EIMC, adapter->eims_enable_mask); 1469 regval = rd32(E1000_EIAC); 1470 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1471 } 1472 1473 wr32(E1000_IAM, 0); 1474 wr32(E1000_IMC, ~0); 1475 wrfl(); 1476 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1477 int i; 1478 1479 for (i = 0; i < adapter->num_q_vectors; i++) 1480 synchronize_irq(adapter->msix_entries[i].vector); 1481 } else { 1482 synchronize_irq(adapter->pdev->irq); 1483 } 1484 } 1485 1486 /** 1487 * igb_irq_enable - Enable default interrupt generation settings 1488 * @adapter: board private structure 1489 **/ 1490 static void igb_irq_enable(struct igb_adapter *adapter) 1491 { 1492 struct e1000_hw *hw = &adapter->hw; 1493 1494 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1495 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1496 u32 regval = rd32(E1000_EIAC); 1497 1498 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1499 regval = rd32(E1000_EIAM); 1500 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1501 wr32(E1000_EIMS, adapter->eims_enable_mask); 1502 if (adapter->vfs_allocated_count) { 1503 wr32(E1000_MBVFIMR, 0xFF); 1504 ims |= E1000_IMS_VMMB; 1505 } 1506 wr32(E1000_IMS, ims); 1507 } else { 1508 wr32(E1000_IMS, IMS_ENABLE_MASK | 1509 E1000_IMS_DRSTA); 1510 wr32(E1000_IAM, IMS_ENABLE_MASK | 1511 E1000_IMS_DRSTA); 1512 } 1513 } 1514 1515 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1516 { 1517 struct e1000_hw *hw = &adapter->hw; 1518 u16 pf_id = adapter->vfs_allocated_count; 1519 u16 vid = adapter->hw.mng_cookie.vlan_id; 1520 u16 old_vid = adapter->mng_vlan_id; 1521 1522 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1523 /* add VID to filter table */ 1524 igb_vfta_set(hw, vid, pf_id, true, true); 1525 adapter->mng_vlan_id = vid; 1526 } else { 1527 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1528 } 1529 1530 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1531 (vid != old_vid) && 1532 !test_bit(old_vid, adapter->active_vlans)) { 1533 /* remove VID from filter table */ 1534 igb_vfta_set(hw, vid, pf_id, false, true); 1535 } 1536 } 1537 1538 /** 1539 * igb_release_hw_control - release control of the h/w to f/w 1540 * @adapter: address of board private structure 1541 * 1542 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1543 * For ASF and Pass Through versions of f/w this means that the 1544 * driver is no longer loaded. 1545 **/ 1546 static void igb_release_hw_control(struct igb_adapter *adapter) 1547 { 1548 struct e1000_hw *hw = &adapter->hw; 1549 u32 ctrl_ext; 1550 1551 /* Let firmware take over control of h/w */ 1552 ctrl_ext = rd32(E1000_CTRL_EXT); 1553 wr32(E1000_CTRL_EXT, 1554 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1555 } 1556 1557 /** 1558 * igb_get_hw_control - get control of the h/w from f/w 1559 * @adapter: address of board private structure 1560 * 1561 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1562 * For ASF and Pass Through versions of f/w this means that 1563 * the driver is loaded. 1564 **/ 1565 static void igb_get_hw_control(struct igb_adapter *adapter) 1566 { 1567 struct e1000_hw *hw = &adapter->hw; 1568 u32 ctrl_ext; 1569 1570 /* Let firmware know the driver has taken over */ 1571 ctrl_ext = rd32(E1000_CTRL_EXT); 1572 wr32(E1000_CTRL_EXT, 1573 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1574 } 1575 1576 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1577 { 1578 struct net_device *netdev = adapter->netdev; 1579 struct e1000_hw *hw = &adapter->hw; 1580 1581 WARN_ON(hw->mac.type != e1000_i210); 1582 1583 if (enable) 1584 adapter->flags |= IGB_FLAG_FQTSS; 1585 else 1586 adapter->flags &= ~IGB_FLAG_FQTSS; 1587 1588 if (netif_running(netdev)) 1589 schedule_work(&adapter->reset_task); 1590 } 1591 1592 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1593 { 1594 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1595 } 1596 1597 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1598 enum tx_queue_prio prio) 1599 { 1600 u32 val; 1601 1602 WARN_ON(hw->mac.type != e1000_i210); 1603 WARN_ON(queue < 0 || queue > 4); 1604 1605 val = rd32(E1000_I210_TXDCTL(queue)); 1606 1607 if (prio == TX_QUEUE_PRIO_HIGH) 1608 val |= E1000_TXDCTL_PRIORITY; 1609 else 1610 val &= ~E1000_TXDCTL_PRIORITY; 1611 1612 wr32(E1000_I210_TXDCTL(queue), val); 1613 } 1614 1615 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1616 { 1617 u32 val; 1618 1619 WARN_ON(hw->mac.type != e1000_i210); 1620 WARN_ON(queue < 0 || queue > 1); 1621 1622 val = rd32(E1000_I210_TQAVCC(queue)); 1623 1624 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1625 val |= E1000_TQAVCC_QUEUEMODE; 1626 else 1627 val &= ~E1000_TQAVCC_QUEUEMODE; 1628 1629 wr32(E1000_I210_TQAVCC(queue), val); 1630 } 1631 1632 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1633 { 1634 int i; 1635 1636 for (i = 0; i < adapter->num_tx_queues; i++) { 1637 if (adapter->tx_ring[i]->cbs_enable) 1638 return true; 1639 } 1640 1641 return false; 1642 } 1643 1644 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1645 { 1646 int i; 1647 1648 for (i = 0; i < adapter->num_tx_queues; i++) { 1649 if (adapter->tx_ring[i]->launchtime_enable) 1650 return true; 1651 } 1652 1653 return false; 1654 } 1655 1656 /** 1657 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1658 * @adapter: pointer to adapter struct 1659 * @queue: queue number 1660 * 1661 * Configure CBS and Launchtime for a given hardware queue. 1662 * Parameters are retrieved from the correct Tx ring, so 1663 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1664 * for setting those correctly prior to this function being called. 1665 **/ 1666 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1667 { 1668 struct net_device *netdev = adapter->netdev; 1669 struct e1000_hw *hw = &adapter->hw; 1670 struct igb_ring *ring; 1671 u32 tqavcc, tqavctrl; 1672 u16 value; 1673 1674 WARN_ON(hw->mac.type != e1000_i210); 1675 WARN_ON(queue < 0 || queue > 1); 1676 ring = adapter->tx_ring[queue]; 1677 1678 /* If any of the Qav features is enabled, configure queues as SR and 1679 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1680 * as SP. 1681 */ 1682 if (ring->cbs_enable || ring->launchtime_enable) { 1683 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1684 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1685 } else { 1686 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1687 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1688 } 1689 1690 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1691 if (ring->cbs_enable || queue == 0) { 1692 /* i210 does not allow the queue 0 to be in the Strict 1693 * Priority mode while the Qav mode is enabled, so, 1694 * instead of disabling strict priority mode, we give 1695 * queue 0 the maximum of credits possible. 1696 * 1697 * See section 8.12.19 of the i210 datasheet, "Note: 1698 * Queue0 QueueMode must be set to 1b when 1699 * TransmitMode is set to Qav." 1700 */ 1701 if (queue == 0 && !ring->cbs_enable) { 1702 /* max "linkspeed" idleslope in kbps */ 1703 ring->idleslope = 1000000; 1704 ring->hicredit = ETH_FRAME_LEN; 1705 } 1706 1707 /* Always set data transfer arbitration to credit-based 1708 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1709 * the queues. 1710 */ 1711 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1712 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1713 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1714 1715 /* According to i210 datasheet section 7.2.7.7, we should set 1716 * the 'idleSlope' field from TQAVCC register following the 1717 * equation: 1718 * 1719 * For 100 Mbps link speed: 1720 * 1721 * value = BW * 0x7735 * 0.2 (E1) 1722 * 1723 * For 1000Mbps link speed: 1724 * 1725 * value = BW * 0x7735 * 2 (E2) 1726 * 1727 * E1 and E2 can be merged into one equation as shown below. 1728 * Note that 'link-speed' is in Mbps. 1729 * 1730 * value = BW * 0x7735 * 2 * link-speed 1731 * -------------- (E3) 1732 * 1000 1733 * 1734 * 'BW' is the percentage bandwidth out of full link speed 1735 * which can be found with the following equation. Note that 1736 * idleSlope here is the parameter from this function which 1737 * is in kbps. 1738 * 1739 * BW = idleSlope 1740 * ----------------- (E4) 1741 * link-speed * 1000 1742 * 1743 * That said, we can come up with a generic equation to 1744 * calculate the value we should set it TQAVCC register by 1745 * replacing 'BW' in E3 by E4. The resulting equation is: 1746 * 1747 * value = idleSlope * 0x7735 * 2 * link-speed 1748 * ----------------- -------------- (E5) 1749 * link-speed * 1000 1000 1750 * 1751 * 'link-speed' is present in both sides of the fraction so 1752 * it is canceled out. The final equation is the following: 1753 * 1754 * value = idleSlope * 61034 1755 * ----------------- (E6) 1756 * 1000000 1757 * 1758 * NOTE: For i210, given the above, we can see that idleslope 1759 * is represented in 16.38431 kbps units by the value at 1760 * the TQAVCC register (1Gbps / 61034), which reduces 1761 * the granularity for idleslope increments. 1762 * For instance, if you want to configure a 2576kbps 1763 * idleslope, the value to be written on the register 1764 * would have to be 157.23. If rounded down, you end 1765 * up with less bandwidth available than originally 1766 * required (~2572 kbps). If rounded up, you end up 1767 * with a higher bandwidth (~2589 kbps). Below the 1768 * approach we take is to always round up the 1769 * calculated value, so the resulting bandwidth might 1770 * be slightly higher for some configurations. 1771 */ 1772 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1773 1774 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1775 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1776 tqavcc |= value; 1777 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1778 1779 wr32(E1000_I210_TQAVHC(queue), 1780 0x80000000 + ring->hicredit * 0x7735); 1781 } else { 1782 1783 /* Set idleSlope to zero. */ 1784 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1785 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1786 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1787 1788 /* Set hiCredit to zero. */ 1789 wr32(E1000_I210_TQAVHC(queue), 0); 1790 1791 /* If CBS is not enabled for any queues anymore, then return to 1792 * the default state of Data Transmission Arbitration on 1793 * TQAVCTRL. 1794 */ 1795 if (!is_any_cbs_enabled(adapter)) { 1796 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1797 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1798 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1799 } 1800 } 1801 1802 /* If LaunchTime is enabled, set DataTranTIM. */ 1803 if (ring->launchtime_enable) { 1804 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1805 * for any of the SR queues, and configure fetchtime delta. 1806 * XXX NOTE: 1807 * - LaunchTime will be enabled for all SR queues. 1808 * - A fixed offset can be added relative to the launch 1809 * time of all packets if configured at reg LAUNCH_OS0. 1810 * We are keeping it as 0 for now (default value). 1811 */ 1812 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1813 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1814 E1000_TQAVCTRL_FETCHTIME_DELTA; 1815 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1816 } else { 1817 /* If Launchtime is not enabled for any SR queues anymore, 1818 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1819 * effectively disabling Launchtime. 1820 */ 1821 if (!is_any_txtime_enabled(adapter)) { 1822 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1823 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1824 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1825 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1826 } 1827 } 1828 1829 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1830 * CBS are not configurable by software so we don't do any 'controller 1831 * configuration' in respect to these parameters. 1832 */ 1833 1834 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1835 ring->cbs_enable ? "enabled" : "disabled", 1836 ring->launchtime_enable ? "enabled" : "disabled", 1837 queue, 1838 ring->idleslope, ring->sendslope, 1839 ring->hicredit, ring->locredit); 1840 } 1841 1842 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1843 bool enable) 1844 { 1845 struct igb_ring *ring; 1846 1847 if (queue < 0 || queue > adapter->num_tx_queues) 1848 return -EINVAL; 1849 1850 ring = adapter->tx_ring[queue]; 1851 ring->launchtime_enable = enable; 1852 1853 return 0; 1854 } 1855 1856 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1857 bool enable, int idleslope, int sendslope, 1858 int hicredit, int locredit) 1859 { 1860 struct igb_ring *ring; 1861 1862 if (queue < 0 || queue > adapter->num_tx_queues) 1863 return -EINVAL; 1864 1865 ring = adapter->tx_ring[queue]; 1866 1867 ring->cbs_enable = enable; 1868 ring->idleslope = idleslope; 1869 ring->sendslope = sendslope; 1870 ring->hicredit = hicredit; 1871 ring->locredit = locredit; 1872 1873 return 0; 1874 } 1875 1876 /** 1877 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1878 * @adapter: pointer to adapter struct 1879 * 1880 * Configure TQAVCTRL register switching the controller's Tx mode 1881 * if FQTSS mode is enabled or disabled. Additionally, will issue 1882 * a call to igb_config_tx_modes() per queue so any previously saved 1883 * Tx parameters are applied. 1884 **/ 1885 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1886 { 1887 struct net_device *netdev = adapter->netdev; 1888 struct e1000_hw *hw = &adapter->hw; 1889 u32 val; 1890 1891 /* Only i210 controller supports changing the transmission mode. */ 1892 if (hw->mac.type != e1000_i210) 1893 return; 1894 1895 if (is_fqtss_enabled(adapter)) { 1896 int i, max_queue; 1897 1898 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1899 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1900 * so SP queues wait for SR ones. 1901 */ 1902 val = rd32(E1000_I210_TQAVCTRL); 1903 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1904 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1905 wr32(E1000_I210_TQAVCTRL, val); 1906 1907 /* Configure Tx and Rx packet buffers sizes as described in 1908 * i210 datasheet section 7.2.7.7. 1909 */ 1910 val = rd32(E1000_TXPBS); 1911 val &= ~I210_TXPBSIZE_MASK; 1912 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB | 1913 I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB; 1914 wr32(E1000_TXPBS, val); 1915 1916 val = rd32(E1000_RXPBS); 1917 val &= ~I210_RXPBSIZE_MASK; 1918 val |= I210_RXPBSIZE_PB_30KB; 1919 wr32(E1000_RXPBS, val); 1920 1921 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1922 * register should not exceed the buffer size programmed in 1923 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1924 * so according to the datasheet we should set MAX_TPKT_SIZE to 1925 * 4kB / 64. 1926 * 1927 * However, when we do so, no frame from queue 2 and 3 are 1928 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1929 * or _equal_ to the buffer size programmed in TXPBS. For this 1930 * reason, we set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1931 */ 1932 val = (4096 - 1) / 64; 1933 wr32(E1000_I210_DTXMXPKTSZ, val); 1934 1935 /* Since FQTSS mode is enabled, apply any CBS configuration 1936 * previously set. If no previous CBS configuration has been 1937 * done, then the initial configuration is applied, which means 1938 * CBS is disabled. 1939 */ 1940 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1941 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1942 1943 for (i = 0; i < max_queue; i++) { 1944 igb_config_tx_modes(adapter, i); 1945 } 1946 } else { 1947 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1948 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1949 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1950 1951 val = rd32(E1000_I210_TQAVCTRL); 1952 /* According to Section 8.12.21, the other flags we've set when 1953 * enabling FQTSS are not relevant when disabling FQTSS so we 1954 * don't set they here. 1955 */ 1956 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1957 wr32(E1000_I210_TQAVCTRL, val); 1958 } 1959 1960 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1961 "enabled" : "disabled"); 1962 } 1963 1964 /** 1965 * igb_configure - configure the hardware for RX and TX 1966 * @adapter: private board structure 1967 **/ 1968 static void igb_configure(struct igb_adapter *adapter) 1969 { 1970 struct net_device *netdev = adapter->netdev; 1971 int i; 1972 1973 igb_get_hw_control(adapter); 1974 igb_set_rx_mode(netdev); 1975 igb_setup_tx_mode(adapter); 1976 1977 igb_restore_vlan(adapter); 1978 1979 igb_setup_tctl(adapter); 1980 igb_setup_mrqc(adapter); 1981 igb_setup_rctl(adapter); 1982 1983 igb_nfc_filter_restore(adapter); 1984 igb_configure_tx(adapter); 1985 igb_configure_rx(adapter); 1986 1987 igb_rx_fifo_flush_82575(&adapter->hw); 1988 1989 /* call igb_desc_unused which always leaves 1990 * at least 1 descriptor unused to make sure 1991 * next_to_use != next_to_clean 1992 */ 1993 for (i = 0; i < adapter->num_rx_queues; i++) { 1994 struct igb_ring *ring = adapter->rx_ring[i]; 1995 if (ring->xsk_pool) 1996 igb_alloc_rx_buffers_zc(ring, ring->xsk_pool, 1997 igb_desc_unused(ring)); 1998 else 1999 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 2000 } 2001 } 2002 2003 /** 2004 * igb_power_up_link - Power up the phy/serdes link 2005 * @adapter: address of board private structure 2006 **/ 2007 void igb_power_up_link(struct igb_adapter *adapter) 2008 { 2009 igb_reset_phy(&adapter->hw); 2010 2011 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2012 igb_power_up_phy_copper(&adapter->hw); 2013 else 2014 igb_power_up_serdes_link_82575(&adapter->hw); 2015 2016 igb_setup_link(&adapter->hw); 2017 } 2018 2019 /** 2020 * igb_power_down_link - Power down the phy/serdes link 2021 * @adapter: address of board private structure 2022 */ 2023 static void igb_power_down_link(struct igb_adapter *adapter) 2024 { 2025 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2026 igb_power_down_phy_copper_82575(&adapter->hw); 2027 else 2028 igb_shutdown_serdes_link_82575(&adapter->hw); 2029 } 2030 2031 /** 2032 * igb_check_swap_media - Detect and switch function for Media Auto Sense 2033 * @adapter: address of the board private structure 2034 **/ 2035 static void igb_check_swap_media(struct igb_adapter *adapter) 2036 { 2037 struct e1000_hw *hw = &adapter->hw; 2038 u32 ctrl_ext, connsw; 2039 bool swap_now = false; 2040 2041 ctrl_ext = rd32(E1000_CTRL_EXT); 2042 connsw = rd32(E1000_CONNSW); 2043 2044 /* need to live swap if current media is copper and we have fiber/serdes 2045 * to go to. 2046 */ 2047 2048 if ((hw->phy.media_type == e1000_media_type_copper) && 2049 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2050 swap_now = true; 2051 } else if ((hw->phy.media_type != e1000_media_type_copper) && 2052 !(connsw & E1000_CONNSW_SERDESD)) { 2053 /* copper signal takes time to appear */ 2054 if (adapter->copper_tries < 4) { 2055 adapter->copper_tries++; 2056 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2057 wr32(E1000_CONNSW, connsw); 2058 return; 2059 } else { 2060 adapter->copper_tries = 0; 2061 if ((connsw & E1000_CONNSW_PHYSD) && 2062 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2063 swap_now = true; 2064 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2065 wr32(E1000_CONNSW, connsw); 2066 } 2067 } 2068 } 2069 2070 if (!swap_now) 2071 return; 2072 2073 switch (hw->phy.media_type) { 2074 case e1000_media_type_copper: 2075 netdev_info(adapter->netdev, 2076 "MAS: changing media to fiber/serdes\n"); 2077 ctrl_ext |= 2078 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2079 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2080 adapter->copper_tries = 0; 2081 break; 2082 case e1000_media_type_internal_serdes: 2083 case e1000_media_type_fiber: 2084 netdev_info(adapter->netdev, 2085 "MAS: changing media to copper\n"); 2086 ctrl_ext &= 2087 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2088 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2089 break; 2090 default: 2091 /* shouldn't get here during regular operation */ 2092 netdev_err(adapter->netdev, 2093 "AMS: Invalid media type found, returning\n"); 2094 break; 2095 } 2096 wr32(E1000_CTRL_EXT, ctrl_ext); 2097 } 2098 2099 /** 2100 * igb_up - Open the interface and prepare it to handle traffic 2101 * @adapter: board private structure 2102 **/ 2103 int igb_up(struct igb_adapter *adapter) 2104 { 2105 struct e1000_hw *hw = &adapter->hw; 2106 int i; 2107 2108 /* hardware has been reset, we need to reload some things */ 2109 igb_configure(adapter); 2110 2111 clear_bit(__IGB_DOWN, &adapter->state); 2112 2113 for (i = 0; i < adapter->num_q_vectors; i++) 2114 napi_enable(&(adapter->q_vector[i]->napi)); 2115 2116 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2117 igb_configure_msix(adapter); 2118 else 2119 igb_assign_vector(adapter->q_vector[0], 0); 2120 2121 /* Clear any pending interrupts. */ 2122 rd32(E1000_TSICR); 2123 rd32(E1000_ICR); 2124 igb_irq_enable(adapter); 2125 2126 /* notify VFs that reset has been completed */ 2127 if (adapter->vfs_allocated_count) { 2128 u32 reg_data = rd32(E1000_CTRL_EXT); 2129 2130 reg_data |= E1000_CTRL_EXT_PFRSTD; 2131 wr32(E1000_CTRL_EXT, reg_data); 2132 } 2133 2134 netif_tx_start_all_queues(adapter->netdev); 2135 2136 /* start the watchdog. */ 2137 hw->mac.get_link_status = 1; 2138 schedule_work(&adapter->watchdog_task); 2139 2140 if ((adapter->flags & IGB_FLAG_EEE) && 2141 (!hw->dev_spec._82575.eee_disable)) 2142 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2143 2144 return 0; 2145 } 2146 2147 void igb_down(struct igb_adapter *adapter) 2148 { 2149 struct net_device *netdev = adapter->netdev; 2150 struct e1000_hw *hw = &adapter->hw; 2151 u32 tctl, rctl; 2152 int i; 2153 2154 /* signal that we're down so the interrupt handler does not 2155 * reschedule our watchdog timer 2156 */ 2157 set_bit(__IGB_DOWN, &adapter->state); 2158 2159 /* disable receives in the hardware */ 2160 rctl = rd32(E1000_RCTL); 2161 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2162 /* flush and sleep below */ 2163 2164 igb_nfc_filter_exit(adapter); 2165 2166 netif_carrier_off(netdev); 2167 netif_tx_stop_all_queues(netdev); 2168 2169 /* disable transmits in the hardware */ 2170 tctl = rd32(E1000_TCTL); 2171 tctl &= ~E1000_TCTL_EN; 2172 wr32(E1000_TCTL, tctl); 2173 /* flush both disables and wait for them to finish */ 2174 wrfl(); 2175 usleep_range(10000, 11000); 2176 2177 igb_irq_disable(adapter); 2178 2179 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2180 2181 for (i = 0; i < adapter->num_q_vectors; i++) { 2182 if (adapter->q_vector[i]) { 2183 napi_synchronize(&adapter->q_vector[i]->napi); 2184 napi_disable(&adapter->q_vector[i]->napi); 2185 } 2186 } 2187 2188 del_timer_sync(&adapter->watchdog_timer); 2189 del_timer_sync(&adapter->phy_info_timer); 2190 2191 /* record the stats before reset*/ 2192 spin_lock(&adapter->stats64_lock); 2193 igb_update_stats(adapter); 2194 spin_unlock(&adapter->stats64_lock); 2195 2196 adapter->link_speed = 0; 2197 adapter->link_duplex = 0; 2198 2199 if (!pci_channel_offline(adapter->pdev)) 2200 igb_reset(adapter); 2201 2202 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2203 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2204 2205 igb_clean_all_tx_rings(adapter); 2206 igb_clean_all_rx_rings(adapter); 2207 #ifdef CONFIG_IGB_DCA 2208 2209 /* since we reset the hardware DCA settings were cleared */ 2210 igb_setup_dca(adapter); 2211 #endif 2212 } 2213 2214 void igb_reinit_locked(struct igb_adapter *adapter) 2215 { 2216 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2217 usleep_range(1000, 2000); 2218 igb_down(adapter); 2219 igb_up(adapter); 2220 clear_bit(__IGB_RESETTING, &adapter->state); 2221 } 2222 2223 /** igb_enable_mas - Media Autosense re-enable after swap 2224 * 2225 * @adapter: adapter struct 2226 **/ 2227 static void igb_enable_mas(struct igb_adapter *adapter) 2228 { 2229 struct e1000_hw *hw = &adapter->hw; 2230 u32 connsw = rd32(E1000_CONNSW); 2231 2232 /* configure for SerDes media detect */ 2233 if ((hw->phy.media_type == e1000_media_type_copper) && 2234 (!(connsw & E1000_CONNSW_SERDESD))) { 2235 connsw |= E1000_CONNSW_ENRGSRC; 2236 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2237 wr32(E1000_CONNSW, connsw); 2238 wrfl(); 2239 } 2240 } 2241 2242 #ifdef CONFIG_IGB_HWMON 2243 /** 2244 * igb_set_i2c_bb - Init I2C interface 2245 * @hw: pointer to hardware structure 2246 **/ 2247 static void igb_set_i2c_bb(struct e1000_hw *hw) 2248 { 2249 u32 ctrl_ext; 2250 s32 i2cctl; 2251 2252 ctrl_ext = rd32(E1000_CTRL_EXT); 2253 ctrl_ext |= E1000_CTRL_I2C_ENA; 2254 wr32(E1000_CTRL_EXT, ctrl_ext); 2255 wrfl(); 2256 2257 i2cctl = rd32(E1000_I2CPARAMS); 2258 i2cctl |= E1000_I2CBB_EN 2259 | E1000_I2C_CLK_OE_N 2260 | E1000_I2C_DATA_OE_N; 2261 wr32(E1000_I2CPARAMS, i2cctl); 2262 wrfl(); 2263 } 2264 #endif 2265 2266 void igb_reset(struct igb_adapter *adapter) 2267 { 2268 struct pci_dev *pdev = adapter->pdev; 2269 struct e1000_hw *hw = &adapter->hw; 2270 struct e1000_mac_info *mac = &hw->mac; 2271 struct e1000_fc_info *fc = &hw->fc; 2272 u32 pba, hwm; 2273 2274 /* Repartition Pba for greater than 9k mtu 2275 * To take effect CTRL.RST is required. 2276 */ 2277 switch (mac->type) { 2278 case e1000_i350: 2279 case e1000_i354: 2280 case e1000_82580: 2281 pba = rd32(E1000_RXPBS); 2282 pba = igb_rxpbs_adjust_82580(pba); 2283 break; 2284 case e1000_82576: 2285 pba = rd32(E1000_RXPBS); 2286 pba &= E1000_RXPBS_SIZE_MASK_82576; 2287 break; 2288 case e1000_82575: 2289 case e1000_i210: 2290 case e1000_i211: 2291 default: 2292 pba = E1000_PBA_34K; 2293 break; 2294 } 2295 2296 if (mac->type == e1000_82575) { 2297 u32 min_rx_space, min_tx_space, needed_tx_space; 2298 2299 /* write Rx PBA so that hardware can report correct Tx PBA */ 2300 wr32(E1000_PBA, pba); 2301 2302 /* To maintain wire speed transmits, the Tx FIFO should be 2303 * large enough to accommodate two full transmit packets, 2304 * rounded up to the next 1KB and expressed in KB. Likewise, 2305 * the Rx FIFO should be large enough to accommodate at least 2306 * one full receive packet and is similarly rounded up and 2307 * expressed in KB. 2308 */ 2309 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2310 2311 /* The Tx FIFO also stores 16 bytes of information about the Tx 2312 * but don't include Ethernet FCS because hardware appends it. 2313 * We only need to round down to the nearest 512 byte block 2314 * count since the value we care about is 2 frames, not 1. 2315 */ 2316 min_tx_space = adapter->max_frame_size; 2317 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2318 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2319 2320 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2321 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2322 2323 /* If current Tx allocation is less than the min Tx FIFO size, 2324 * and the min Tx FIFO size is less than the current Rx FIFO 2325 * allocation, take space away from current Rx allocation. 2326 */ 2327 if (needed_tx_space < pba) { 2328 pba -= needed_tx_space; 2329 2330 /* if short on Rx space, Rx wins and must trump Tx 2331 * adjustment 2332 */ 2333 if (pba < min_rx_space) 2334 pba = min_rx_space; 2335 } 2336 2337 /* adjust PBA for jumbo frames */ 2338 wr32(E1000_PBA, pba); 2339 } 2340 2341 /* flow control settings 2342 * The high water mark must be low enough to fit one full frame 2343 * after transmitting the pause frame. As such we must have enough 2344 * space to allow for us to complete our current transmit and then 2345 * receive the frame that is in progress from the link partner. 2346 * Set it to: 2347 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2348 */ 2349 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2350 2351 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2352 fc->low_water = fc->high_water - 16; 2353 fc->pause_time = 0xFFFF; 2354 fc->send_xon = 1; 2355 fc->current_mode = fc->requested_mode; 2356 2357 /* disable receive for all VFs and wait one second */ 2358 if (adapter->vfs_allocated_count) { 2359 int i; 2360 2361 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2362 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2363 2364 /* ping all the active vfs to let them know we are going down */ 2365 igb_ping_all_vfs(adapter); 2366 2367 /* disable transmits and receives */ 2368 wr32(E1000_VFRE, 0); 2369 wr32(E1000_VFTE, 0); 2370 } 2371 2372 /* Allow time for pending master requests to run */ 2373 hw->mac.ops.reset_hw(hw); 2374 wr32(E1000_WUC, 0); 2375 2376 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2377 /* need to resetup here after media swap */ 2378 adapter->ei.get_invariants(hw); 2379 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2380 } 2381 if ((mac->type == e1000_82575 || mac->type == e1000_i350) && 2382 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2383 igb_enable_mas(adapter); 2384 } 2385 if (hw->mac.ops.init_hw(hw)) 2386 dev_err(&pdev->dev, "Hardware Error\n"); 2387 2388 /* RAR registers were cleared during init_hw, clear mac table */ 2389 igb_flush_mac_table(adapter); 2390 __dev_uc_unsync(adapter->netdev, NULL); 2391 2392 /* Recover default RAR entry */ 2393 igb_set_default_mac_filter(adapter); 2394 2395 /* Flow control settings reset on hardware reset, so guarantee flow 2396 * control is off when forcing speed. 2397 */ 2398 if (!hw->mac.autoneg) 2399 igb_force_mac_fc(hw); 2400 2401 igb_init_dmac(adapter, pba); 2402 #ifdef CONFIG_IGB_HWMON 2403 /* Re-initialize the thermal sensor on i350 devices. */ 2404 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2405 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2406 /* If present, re-initialize the external thermal sensor 2407 * interface. 2408 */ 2409 if (adapter->ets) 2410 igb_set_i2c_bb(hw); 2411 mac->ops.init_thermal_sensor_thresh(hw); 2412 } 2413 } 2414 #endif 2415 /* Re-establish EEE setting */ 2416 if (hw->phy.media_type == e1000_media_type_copper) { 2417 switch (mac->type) { 2418 case e1000_i350: 2419 case e1000_i210: 2420 case e1000_i211: 2421 igb_set_eee_i350(hw, true, true); 2422 break; 2423 case e1000_i354: 2424 igb_set_eee_i354(hw, true, true); 2425 break; 2426 default: 2427 break; 2428 } 2429 } 2430 if (!netif_running(adapter->netdev)) 2431 igb_power_down_link(adapter); 2432 2433 igb_update_mng_vlan(adapter); 2434 2435 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2436 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2437 2438 /* Re-enable PTP, where applicable. */ 2439 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2440 igb_ptp_reset(adapter); 2441 2442 igb_get_phy_info(hw); 2443 } 2444 2445 static netdev_features_t igb_fix_features(struct net_device *netdev, 2446 netdev_features_t features) 2447 { 2448 /* Since there is no support for separate Rx/Tx vlan accel 2449 * enable/disable make sure Tx flag is always in same state as Rx. 2450 */ 2451 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2452 features |= NETIF_F_HW_VLAN_CTAG_TX; 2453 else 2454 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2455 2456 return features; 2457 } 2458 2459 static int igb_set_features(struct net_device *netdev, 2460 netdev_features_t features) 2461 { 2462 netdev_features_t changed = netdev->features ^ features; 2463 struct igb_adapter *adapter = netdev_priv(netdev); 2464 2465 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2466 igb_vlan_mode(netdev, features); 2467 2468 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2469 return 0; 2470 2471 if (!(features & NETIF_F_NTUPLE)) { 2472 struct hlist_node *node2; 2473 struct igb_nfc_filter *rule; 2474 2475 spin_lock(&adapter->nfc_lock); 2476 hlist_for_each_entry_safe(rule, node2, 2477 &adapter->nfc_filter_list, nfc_node) { 2478 igb_erase_filter(adapter, rule); 2479 hlist_del(&rule->nfc_node); 2480 kfree(rule); 2481 } 2482 spin_unlock(&adapter->nfc_lock); 2483 adapter->nfc_filter_count = 0; 2484 } 2485 2486 netdev->features = features; 2487 2488 if (netif_running(netdev)) 2489 igb_reinit_locked(adapter); 2490 else 2491 igb_reset(adapter); 2492 2493 return 1; 2494 } 2495 2496 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2497 struct net_device *dev, 2498 const unsigned char *addr, u16 vid, 2499 u16 flags, bool *notified, 2500 struct netlink_ext_ack *extack) 2501 { 2502 /* guarantee we can provide a unique filter for the unicast address */ 2503 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2504 struct igb_adapter *adapter = netdev_priv(dev); 2505 int vfn = adapter->vfs_allocated_count; 2506 2507 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2508 return -ENOMEM; 2509 } 2510 2511 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2512 } 2513 2514 #define IGB_MAX_MAC_HDR_LEN 127 2515 #define IGB_MAX_NETWORK_HDR_LEN 511 2516 2517 static netdev_features_t 2518 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2519 netdev_features_t features) 2520 { 2521 unsigned int network_hdr_len, mac_hdr_len; 2522 2523 /* Make certain the headers can be described by a context descriptor */ 2524 mac_hdr_len = skb_network_offset(skb); 2525 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2526 return features & ~(NETIF_F_HW_CSUM | 2527 NETIF_F_SCTP_CRC | 2528 NETIF_F_GSO_UDP_L4 | 2529 NETIF_F_HW_VLAN_CTAG_TX | 2530 NETIF_F_TSO | 2531 NETIF_F_TSO6); 2532 2533 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2534 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2535 return features & ~(NETIF_F_HW_CSUM | 2536 NETIF_F_SCTP_CRC | 2537 NETIF_F_GSO_UDP_L4 | 2538 NETIF_F_TSO | 2539 NETIF_F_TSO6); 2540 2541 /* We can only support IPV4 TSO in tunnels if we can mangle the 2542 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2543 */ 2544 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2545 features &= ~NETIF_F_TSO; 2546 2547 return features; 2548 } 2549 2550 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2551 { 2552 if (!is_fqtss_enabled(adapter)) { 2553 enable_fqtss(adapter, true); 2554 return; 2555 } 2556 2557 igb_config_tx_modes(adapter, queue); 2558 2559 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2560 enable_fqtss(adapter, false); 2561 } 2562 2563 static int igb_offload_cbs(struct igb_adapter *adapter, 2564 struct tc_cbs_qopt_offload *qopt) 2565 { 2566 struct e1000_hw *hw = &adapter->hw; 2567 int err; 2568 2569 /* CBS offloading is only supported by i210 controller. */ 2570 if (hw->mac.type != e1000_i210) 2571 return -EOPNOTSUPP; 2572 2573 /* CBS offloading is only supported by queue 0 and queue 1. */ 2574 if (qopt->queue < 0 || qopt->queue > 1) 2575 return -EINVAL; 2576 2577 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2578 qopt->idleslope, qopt->sendslope, 2579 qopt->hicredit, qopt->locredit); 2580 if (err) 2581 return err; 2582 2583 igb_offload_apply(adapter, qopt->queue); 2584 2585 return 0; 2586 } 2587 2588 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2589 #define VLAN_PRIO_FULL_MASK (0x07) 2590 2591 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2592 struct flow_cls_offload *f, 2593 int traffic_class, 2594 struct igb_nfc_filter *input) 2595 { 2596 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2597 struct flow_dissector *dissector = rule->match.dissector; 2598 struct netlink_ext_ack *extack = f->common.extack; 2599 2600 if (dissector->used_keys & 2601 ~(BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) | 2602 BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) | 2603 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2604 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN))) { 2605 NL_SET_ERR_MSG_MOD(extack, 2606 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2607 return -EOPNOTSUPP; 2608 } 2609 2610 if (flow_rule_match_has_control_flags(rule, extack)) 2611 return -EOPNOTSUPP; 2612 2613 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2614 struct flow_match_eth_addrs match; 2615 2616 flow_rule_match_eth_addrs(rule, &match); 2617 if (!is_zero_ether_addr(match.mask->dst)) { 2618 if (!is_broadcast_ether_addr(match.mask->dst)) { 2619 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2620 return -EINVAL; 2621 } 2622 2623 input->filter.match_flags |= 2624 IGB_FILTER_FLAG_DST_MAC_ADDR; 2625 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2626 } 2627 2628 if (!is_zero_ether_addr(match.mask->src)) { 2629 if (!is_broadcast_ether_addr(match.mask->src)) { 2630 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2631 return -EINVAL; 2632 } 2633 2634 input->filter.match_flags |= 2635 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2636 ether_addr_copy(input->filter.src_addr, match.key->src); 2637 } 2638 } 2639 2640 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2641 struct flow_match_basic match; 2642 2643 flow_rule_match_basic(rule, &match); 2644 if (match.mask->n_proto) { 2645 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2646 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2647 return -EINVAL; 2648 } 2649 2650 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2651 input->filter.etype = match.key->n_proto; 2652 } 2653 } 2654 2655 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2656 struct flow_match_vlan match; 2657 2658 flow_rule_match_vlan(rule, &match); 2659 if (match.mask->vlan_priority) { 2660 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2661 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2662 return -EINVAL; 2663 } 2664 2665 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2666 input->filter.vlan_tci = 2667 (__force __be16)match.key->vlan_priority; 2668 } 2669 } 2670 2671 input->action = traffic_class; 2672 input->cookie = f->cookie; 2673 2674 return 0; 2675 } 2676 2677 static int igb_configure_clsflower(struct igb_adapter *adapter, 2678 struct flow_cls_offload *cls_flower) 2679 { 2680 struct netlink_ext_ack *extack = cls_flower->common.extack; 2681 struct igb_nfc_filter *filter, *f; 2682 int err, tc; 2683 2684 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2685 if (tc < 0) { 2686 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2687 return -EINVAL; 2688 } 2689 2690 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2691 if (!filter) 2692 return -ENOMEM; 2693 2694 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2695 if (err < 0) 2696 goto err_parse; 2697 2698 spin_lock(&adapter->nfc_lock); 2699 2700 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2701 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2702 err = -EEXIST; 2703 NL_SET_ERR_MSG_MOD(extack, 2704 "This filter is already set in ethtool"); 2705 goto err_locked; 2706 } 2707 } 2708 2709 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2710 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2711 err = -EEXIST; 2712 NL_SET_ERR_MSG_MOD(extack, 2713 "This filter is already set in cls_flower"); 2714 goto err_locked; 2715 } 2716 } 2717 2718 err = igb_add_filter(adapter, filter); 2719 if (err < 0) { 2720 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2721 goto err_locked; 2722 } 2723 2724 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2725 2726 spin_unlock(&adapter->nfc_lock); 2727 2728 return 0; 2729 2730 err_locked: 2731 spin_unlock(&adapter->nfc_lock); 2732 2733 err_parse: 2734 kfree(filter); 2735 2736 return err; 2737 } 2738 2739 static int igb_delete_clsflower(struct igb_adapter *adapter, 2740 struct flow_cls_offload *cls_flower) 2741 { 2742 struct igb_nfc_filter *filter; 2743 int err; 2744 2745 spin_lock(&adapter->nfc_lock); 2746 2747 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2748 if (filter->cookie == cls_flower->cookie) 2749 break; 2750 2751 if (!filter) { 2752 err = -ENOENT; 2753 goto out; 2754 } 2755 2756 err = igb_erase_filter(adapter, filter); 2757 if (err < 0) 2758 goto out; 2759 2760 hlist_del(&filter->nfc_node); 2761 kfree(filter); 2762 2763 out: 2764 spin_unlock(&adapter->nfc_lock); 2765 2766 return err; 2767 } 2768 2769 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2770 struct flow_cls_offload *cls_flower) 2771 { 2772 switch (cls_flower->command) { 2773 case FLOW_CLS_REPLACE: 2774 return igb_configure_clsflower(adapter, cls_flower); 2775 case FLOW_CLS_DESTROY: 2776 return igb_delete_clsflower(adapter, cls_flower); 2777 case FLOW_CLS_STATS: 2778 return -EOPNOTSUPP; 2779 default: 2780 return -EOPNOTSUPP; 2781 } 2782 } 2783 2784 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2785 void *cb_priv) 2786 { 2787 struct igb_adapter *adapter = cb_priv; 2788 2789 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2790 return -EOPNOTSUPP; 2791 2792 switch (type) { 2793 case TC_SETUP_CLSFLOWER: 2794 return igb_setup_tc_cls_flower(adapter, type_data); 2795 2796 default: 2797 return -EOPNOTSUPP; 2798 } 2799 } 2800 2801 static int igb_offload_txtime(struct igb_adapter *adapter, 2802 struct tc_etf_qopt_offload *qopt) 2803 { 2804 struct e1000_hw *hw = &adapter->hw; 2805 int err; 2806 2807 /* Launchtime offloading is only supported by i210 controller. */ 2808 if (hw->mac.type != e1000_i210) 2809 return -EOPNOTSUPP; 2810 2811 /* Launchtime offloading is only supported by queues 0 and 1. */ 2812 if (qopt->queue < 0 || qopt->queue > 1) 2813 return -EINVAL; 2814 2815 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2816 if (err) 2817 return err; 2818 2819 igb_offload_apply(adapter, qopt->queue); 2820 2821 return 0; 2822 } 2823 2824 static int igb_tc_query_caps(struct igb_adapter *adapter, 2825 struct tc_query_caps_base *base) 2826 { 2827 switch (base->type) { 2828 case TC_SETUP_QDISC_TAPRIO: { 2829 struct tc_taprio_caps *caps = base->caps; 2830 2831 caps->broken_mqprio = true; 2832 2833 return 0; 2834 } 2835 default: 2836 return -EOPNOTSUPP; 2837 } 2838 } 2839 2840 static LIST_HEAD(igb_block_cb_list); 2841 2842 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2843 void *type_data) 2844 { 2845 struct igb_adapter *adapter = netdev_priv(dev); 2846 2847 switch (type) { 2848 case TC_QUERY_CAPS: 2849 return igb_tc_query_caps(adapter, type_data); 2850 case TC_SETUP_QDISC_CBS: 2851 return igb_offload_cbs(adapter, type_data); 2852 case TC_SETUP_BLOCK: 2853 return flow_block_cb_setup_simple(type_data, 2854 &igb_block_cb_list, 2855 igb_setup_tc_block_cb, 2856 adapter, adapter, true); 2857 2858 case TC_SETUP_QDISC_ETF: 2859 return igb_offload_txtime(adapter, type_data); 2860 2861 default: 2862 return -EOPNOTSUPP; 2863 } 2864 } 2865 2866 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf) 2867 { 2868 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD; 2869 struct igb_adapter *adapter = netdev_priv(dev); 2870 struct bpf_prog *prog = bpf->prog, *old_prog; 2871 bool running = netif_running(dev); 2872 bool need_reset; 2873 2874 /* verify igb ring attributes are sufficient for XDP */ 2875 for (i = 0; i < adapter->num_rx_queues; i++) { 2876 struct igb_ring *ring = adapter->rx_ring[i]; 2877 2878 if (frame_size > igb_rx_bufsz(ring)) { 2879 NL_SET_ERR_MSG_MOD(bpf->extack, 2880 "The RX buffer size is too small for the frame size"); 2881 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n", 2882 igb_rx_bufsz(ring), frame_size); 2883 return -EINVAL; 2884 } 2885 } 2886 2887 old_prog = xchg(&adapter->xdp_prog, prog); 2888 need_reset = (!!prog != !!old_prog); 2889 2890 /* device is up and bpf is added/removed, must setup the RX queues */ 2891 if (need_reset && running) { 2892 igb_close(dev); 2893 } else { 2894 for (i = 0; i < adapter->num_rx_queues; i++) 2895 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 2896 adapter->xdp_prog); 2897 } 2898 2899 if (old_prog) 2900 bpf_prog_put(old_prog); 2901 2902 /* bpf is just replaced, RXQ and MTU are already setup */ 2903 if (!need_reset) { 2904 return 0; 2905 } else { 2906 if (prog) 2907 xdp_features_set_redirect_target(dev, true); 2908 else 2909 xdp_features_clear_redirect_target(dev); 2910 } 2911 2912 if (running) 2913 igb_open(dev); 2914 2915 return 0; 2916 } 2917 2918 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp) 2919 { 2920 struct igb_adapter *adapter = netdev_priv(dev); 2921 2922 switch (xdp->command) { 2923 case XDP_SETUP_PROG: 2924 return igb_xdp_setup(dev, xdp); 2925 case XDP_SETUP_XSK_POOL: 2926 return igb_xsk_pool_setup(adapter, xdp->xsk.pool, 2927 xdp->xsk.queue_id); 2928 default: 2929 return -EINVAL; 2930 } 2931 } 2932 2933 int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp) 2934 { 2935 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2936 int cpu = smp_processor_id(); 2937 struct igb_ring *tx_ring; 2938 struct netdev_queue *nq; 2939 u32 ret; 2940 2941 if (unlikely(!xdpf)) 2942 return IGB_XDP_CONSUMED; 2943 2944 /* During program transitions its possible adapter->xdp_prog is assigned 2945 * but ring has not been configured yet. In this case simply abort xmit. 2946 */ 2947 tx_ring = igb_xdp_is_enabled(adapter) ? 2948 igb_xdp_tx_queue_mapping(adapter) : NULL; 2949 if (unlikely(!tx_ring)) 2950 return IGB_XDP_CONSUMED; 2951 2952 nq = txring_txq(tx_ring); 2953 __netif_tx_lock(nq, cpu); 2954 /* Avoid transmit queue timeout since we share it with the slow path */ 2955 txq_trans_cond_update(nq); 2956 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2957 __netif_tx_unlock(nq); 2958 2959 return ret; 2960 } 2961 2962 static int igb_xdp_xmit(struct net_device *dev, int n, 2963 struct xdp_frame **frames, u32 flags) 2964 { 2965 struct igb_adapter *adapter = netdev_priv(dev); 2966 int cpu = smp_processor_id(); 2967 struct igb_ring *tx_ring; 2968 struct netdev_queue *nq; 2969 int nxmit = 0; 2970 int i; 2971 2972 if (unlikely(test_bit(__IGB_DOWN, &adapter->state))) 2973 return -ENETDOWN; 2974 2975 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2976 return -EINVAL; 2977 2978 /* During program transitions its possible adapter->xdp_prog is assigned 2979 * but ring has not been configured yet. In this case simply abort xmit. 2980 */ 2981 tx_ring = igb_xdp_is_enabled(adapter) ? 2982 igb_xdp_tx_queue_mapping(adapter) : NULL; 2983 if (unlikely(!tx_ring)) 2984 return -ENXIO; 2985 2986 if (unlikely(test_bit(IGB_RING_FLAG_TX_DISABLED, &tx_ring->flags))) 2987 return -ENXIO; 2988 2989 nq = txring_txq(tx_ring); 2990 __netif_tx_lock(nq, cpu); 2991 2992 /* Avoid transmit queue timeout since we share it with the slow path */ 2993 txq_trans_cond_update(nq); 2994 2995 for (i = 0; i < n; i++) { 2996 struct xdp_frame *xdpf = frames[i]; 2997 int err; 2998 2999 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 3000 if (err != IGB_XDP_TX) 3001 break; 3002 nxmit++; 3003 } 3004 3005 if (unlikely(flags & XDP_XMIT_FLUSH)) 3006 igb_xdp_ring_update_tail(tx_ring); 3007 3008 __netif_tx_unlock(nq); 3009 3010 return nxmit; 3011 } 3012 3013 static const struct net_device_ops igb_netdev_ops = { 3014 .ndo_open = igb_open, 3015 .ndo_stop = igb_close, 3016 .ndo_start_xmit = igb_xmit_frame, 3017 .ndo_get_stats64 = igb_get_stats64, 3018 .ndo_set_rx_mode = igb_set_rx_mode, 3019 .ndo_set_mac_address = igb_set_mac, 3020 .ndo_change_mtu = igb_change_mtu, 3021 .ndo_eth_ioctl = igb_ioctl, 3022 .ndo_tx_timeout = igb_tx_timeout, 3023 .ndo_validate_addr = eth_validate_addr, 3024 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 3025 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 3026 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 3027 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 3028 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 3029 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 3030 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 3031 .ndo_get_vf_config = igb_ndo_get_vf_config, 3032 .ndo_fix_features = igb_fix_features, 3033 .ndo_set_features = igb_set_features, 3034 .ndo_fdb_add = igb_ndo_fdb_add, 3035 .ndo_features_check = igb_features_check, 3036 .ndo_setup_tc = igb_setup_tc, 3037 .ndo_bpf = igb_xdp, 3038 .ndo_xdp_xmit = igb_xdp_xmit, 3039 .ndo_xsk_wakeup = igb_xsk_wakeup, 3040 }; 3041 3042 /** 3043 * igb_set_fw_version - Configure version string for ethtool 3044 * @adapter: adapter struct 3045 **/ 3046 void igb_set_fw_version(struct igb_adapter *adapter) 3047 { 3048 struct e1000_hw *hw = &adapter->hw; 3049 struct e1000_fw_version fw; 3050 3051 igb_get_fw_version(hw, &fw); 3052 3053 switch (hw->mac.type) { 3054 case e1000_i210: 3055 case e1000_i211: 3056 if (!(igb_get_flash_presence_i210(hw))) { 3057 snprintf(adapter->fw_version, 3058 sizeof(adapter->fw_version), 3059 "%2d.%2d-%d", 3060 fw.invm_major, fw.invm_minor, 3061 fw.invm_img_type); 3062 break; 3063 } 3064 fallthrough; 3065 default: 3066 /* if option rom is valid, display its version too */ 3067 if (fw.or_valid) { 3068 snprintf(adapter->fw_version, 3069 sizeof(adapter->fw_version), 3070 "%d.%d, 0x%08x, %d.%d.%d", 3071 fw.eep_major, fw.eep_minor, fw.etrack_id, 3072 fw.or_major, fw.or_build, fw.or_patch); 3073 /* no option rom */ 3074 } else if (fw.etrack_id != 0X0000) { 3075 snprintf(adapter->fw_version, 3076 sizeof(adapter->fw_version), 3077 "%d.%d, 0x%08x", 3078 fw.eep_major, fw.eep_minor, fw.etrack_id); 3079 } else { 3080 snprintf(adapter->fw_version, 3081 sizeof(adapter->fw_version), 3082 "%d.%d.%d", 3083 fw.eep_major, fw.eep_minor, fw.eep_build); 3084 } 3085 break; 3086 } 3087 } 3088 3089 /** 3090 * igb_init_mas - init Media Autosense feature if enabled in the NVM 3091 * 3092 * @adapter: adapter struct 3093 **/ 3094 static void igb_init_mas(struct igb_adapter *adapter) 3095 { 3096 struct e1000_hw *hw = &adapter->hw; 3097 u16 eeprom_data; 3098 3099 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 3100 switch (hw->bus.func) { 3101 case E1000_FUNC_0: 3102 if (eeprom_data & IGB_MAS_ENABLE_0) { 3103 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3104 netdev_info(adapter->netdev, 3105 "MAS: Enabling Media Autosense for port %d\n", 3106 hw->bus.func); 3107 } 3108 break; 3109 case E1000_FUNC_1: 3110 if (eeprom_data & IGB_MAS_ENABLE_1) { 3111 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3112 netdev_info(adapter->netdev, 3113 "MAS: Enabling Media Autosense for port %d\n", 3114 hw->bus.func); 3115 } 3116 break; 3117 case E1000_FUNC_2: 3118 if (eeprom_data & IGB_MAS_ENABLE_2) { 3119 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3120 netdev_info(adapter->netdev, 3121 "MAS: Enabling Media Autosense for port %d\n", 3122 hw->bus.func); 3123 } 3124 break; 3125 case E1000_FUNC_3: 3126 if (eeprom_data & IGB_MAS_ENABLE_3) { 3127 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3128 netdev_info(adapter->netdev, 3129 "MAS: Enabling Media Autosense for port %d\n", 3130 hw->bus.func); 3131 } 3132 break; 3133 default: 3134 /* Shouldn't get here */ 3135 netdev_err(adapter->netdev, 3136 "MAS: Invalid port configuration, returning\n"); 3137 break; 3138 } 3139 } 3140 3141 /** 3142 * igb_init_i2c - Init I2C interface 3143 * @adapter: pointer to adapter structure 3144 **/ 3145 static s32 igb_init_i2c(struct igb_adapter *adapter) 3146 { 3147 s32 status = 0; 3148 3149 /* I2C interface supported on i350 devices */ 3150 if (adapter->hw.mac.type != e1000_i350) 3151 return 0; 3152 3153 /* Initialize the i2c bus which is controlled by the registers. 3154 * This bus will use the i2c_algo_bit structure that implements 3155 * the protocol through toggling of the 4 bits in the register. 3156 */ 3157 adapter->i2c_adap.owner = THIS_MODULE; 3158 adapter->i2c_algo = igb_i2c_algo; 3159 adapter->i2c_algo.data = adapter; 3160 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 3161 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 3162 strscpy(adapter->i2c_adap.name, "igb BB", 3163 sizeof(adapter->i2c_adap.name)); 3164 status = i2c_bit_add_bus(&adapter->i2c_adap); 3165 return status; 3166 } 3167 3168 /** 3169 * igb_probe - Device Initialization Routine 3170 * @pdev: PCI device information struct 3171 * @ent: entry in igb_pci_tbl 3172 * 3173 * Returns 0 on success, negative on failure 3174 * 3175 * igb_probe initializes an adapter identified by a pci_dev structure. 3176 * The OS initialization, configuring of the adapter private structure, 3177 * and a hardware reset occur. 3178 **/ 3179 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3180 { 3181 struct net_device *netdev; 3182 struct igb_adapter *adapter; 3183 struct e1000_hw *hw; 3184 u16 eeprom_data = 0; 3185 s32 ret_val; 3186 static int global_quad_port_a; /* global quad port a indication */ 3187 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3188 u8 part_str[E1000_PBANUM_LENGTH]; 3189 int err; 3190 3191 /* Catch broken hardware that put the wrong VF device ID in 3192 * the PCIe SR-IOV capability. 3193 */ 3194 if (pdev->is_virtfn) { 3195 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n", 3196 pci_name(pdev), pdev->vendor, pdev->device); 3197 return -EINVAL; 3198 } 3199 3200 err = pci_enable_device_mem(pdev); 3201 if (err) 3202 return err; 3203 3204 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3205 if (err) { 3206 dev_err(&pdev->dev, 3207 "No usable DMA configuration, aborting\n"); 3208 goto err_dma; 3209 } 3210 3211 err = pci_request_mem_regions(pdev, igb_driver_name); 3212 if (err) 3213 goto err_pci_reg; 3214 3215 pci_set_master(pdev); 3216 pci_save_state(pdev); 3217 3218 err = -ENOMEM; 3219 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3220 IGB_MAX_TX_QUEUES); 3221 if (!netdev) 3222 goto err_alloc_etherdev; 3223 3224 SET_NETDEV_DEV(netdev, &pdev->dev); 3225 3226 pci_set_drvdata(pdev, netdev); 3227 adapter = netdev_priv(netdev); 3228 adapter->netdev = netdev; 3229 adapter->pdev = pdev; 3230 hw = &adapter->hw; 3231 hw->back = adapter; 3232 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3233 3234 err = -EIO; 3235 adapter->io_addr = pci_iomap(pdev, 0, 0); 3236 if (!adapter->io_addr) 3237 goto err_ioremap; 3238 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3239 hw->hw_addr = adapter->io_addr; 3240 3241 netdev->netdev_ops = &igb_netdev_ops; 3242 igb_set_ethtool_ops(netdev); 3243 netdev->watchdog_timeo = 5 * HZ; 3244 3245 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 3246 3247 netdev->mem_start = pci_resource_start(pdev, 0); 3248 netdev->mem_end = pci_resource_end(pdev, 0); 3249 3250 /* PCI config space info */ 3251 hw->vendor_id = pdev->vendor; 3252 hw->device_id = pdev->device; 3253 hw->revision_id = pdev->revision; 3254 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3255 hw->subsystem_device_id = pdev->subsystem_device; 3256 3257 /* Copy the default MAC, PHY and NVM function pointers */ 3258 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3259 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3260 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3261 /* Initialize skew-specific constants */ 3262 err = ei->get_invariants(hw); 3263 if (err) 3264 goto err_sw_init; 3265 3266 /* setup the private structure */ 3267 err = igb_sw_init(adapter); 3268 if (err) 3269 goto err_sw_init; 3270 3271 igb_get_bus_info_pcie(hw); 3272 3273 hw->phy.autoneg_wait_to_complete = false; 3274 3275 /* Copper options */ 3276 if (hw->phy.media_type == e1000_media_type_copper) { 3277 hw->phy.mdix = AUTO_ALL_MODES; 3278 hw->phy.disable_polarity_correction = false; 3279 hw->phy.ms_type = e1000_ms_hw_default; 3280 } 3281 3282 if (igb_check_reset_block(hw)) 3283 dev_info(&pdev->dev, 3284 "PHY reset is blocked due to SOL/IDER session.\n"); 3285 3286 /* features is initialized to 0 in allocation, it might have bits 3287 * set by igb_sw_init so we should use an or instead of an 3288 * assignment. 3289 */ 3290 netdev->features |= NETIF_F_SG | 3291 NETIF_F_TSO | 3292 NETIF_F_TSO6 | 3293 NETIF_F_RXHASH | 3294 NETIF_F_RXCSUM | 3295 NETIF_F_HW_CSUM; 3296 3297 if (hw->mac.type >= e1000_82576) 3298 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 3299 3300 if (hw->mac.type >= e1000_i350) 3301 netdev->features |= NETIF_F_HW_TC; 3302 3303 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3304 NETIF_F_GSO_GRE_CSUM | \ 3305 NETIF_F_GSO_IPXIP4 | \ 3306 NETIF_F_GSO_IPXIP6 | \ 3307 NETIF_F_GSO_UDP_TUNNEL | \ 3308 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3309 3310 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3311 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3312 3313 /* copy netdev features into list of user selectable features */ 3314 netdev->hw_features |= netdev->features | 3315 NETIF_F_HW_VLAN_CTAG_RX | 3316 NETIF_F_HW_VLAN_CTAG_TX | 3317 NETIF_F_RXALL; 3318 3319 if (hw->mac.type >= e1000_i350) 3320 netdev->hw_features |= NETIF_F_NTUPLE; 3321 3322 netdev->features |= NETIF_F_HIGHDMA; 3323 3324 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3325 netdev->mpls_features |= NETIF_F_HW_CSUM; 3326 netdev->hw_enc_features |= netdev->vlan_features; 3327 3328 /* set this bit last since it cannot be part of vlan_features */ 3329 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3330 NETIF_F_HW_VLAN_CTAG_RX | 3331 NETIF_F_HW_VLAN_CTAG_TX; 3332 3333 netdev->priv_flags |= IFF_SUPP_NOFCS; 3334 3335 netdev->priv_flags |= IFF_UNICAST_FLT; 3336 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | 3337 NETDEV_XDP_ACT_XSK_ZEROCOPY; 3338 3339 /* MTU range: 68 - 9216 */ 3340 netdev->min_mtu = ETH_MIN_MTU; 3341 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3342 3343 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3344 3345 /* before reading the NVM, reset the controller to put the device in a 3346 * known good starting state 3347 */ 3348 hw->mac.ops.reset_hw(hw); 3349 3350 /* make sure the NVM is good , i211/i210 parts can have special NVM 3351 * that doesn't contain a checksum 3352 */ 3353 switch (hw->mac.type) { 3354 case e1000_i210: 3355 case e1000_i211: 3356 if (igb_get_flash_presence_i210(hw)) { 3357 if (hw->nvm.ops.validate(hw) < 0) { 3358 dev_err(&pdev->dev, 3359 "The NVM Checksum Is Not Valid\n"); 3360 err = -EIO; 3361 goto err_eeprom; 3362 } 3363 } 3364 break; 3365 default: 3366 if (hw->nvm.ops.validate(hw) < 0) { 3367 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3368 err = -EIO; 3369 goto err_eeprom; 3370 } 3371 break; 3372 } 3373 3374 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3375 /* copy the MAC address out of the NVM */ 3376 if (hw->mac.ops.read_mac_addr(hw)) 3377 dev_err(&pdev->dev, "NVM Read Error\n"); 3378 } 3379 3380 eth_hw_addr_set(netdev, hw->mac.addr); 3381 3382 if (!is_valid_ether_addr(netdev->dev_addr)) { 3383 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3384 err = -EIO; 3385 goto err_eeprom; 3386 } 3387 3388 igb_set_default_mac_filter(adapter); 3389 3390 /* get firmware version for ethtool -i */ 3391 igb_set_fw_version(adapter); 3392 3393 /* configure RXPBSIZE and TXPBSIZE */ 3394 if (hw->mac.type == e1000_i210) { 3395 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3396 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3397 } 3398 3399 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3400 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3401 3402 INIT_WORK(&adapter->reset_task, igb_reset_task); 3403 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3404 3405 /* Initialize link properties that are user-changeable */ 3406 adapter->fc_autoneg = true; 3407 hw->mac.autoneg = true; 3408 hw->phy.autoneg_advertised = 0x2f; 3409 3410 hw->fc.requested_mode = e1000_fc_default; 3411 hw->fc.current_mode = e1000_fc_default; 3412 3413 igb_validate_mdi_setting(hw); 3414 3415 /* By default, support wake on port A */ 3416 if (hw->bus.func == 0) 3417 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3418 3419 /* Check the NVM for wake support on non-port A ports */ 3420 if (hw->mac.type >= e1000_82580) 3421 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3422 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3423 &eeprom_data); 3424 else if (hw->bus.func == 1) 3425 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3426 3427 if (eeprom_data & IGB_EEPROM_APME) 3428 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3429 3430 /* now that we have the eeprom settings, apply the special cases where 3431 * the eeprom may be wrong or the board simply won't support wake on 3432 * lan on a particular port 3433 */ 3434 switch (pdev->device) { 3435 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3436 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3437 break; 3438 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3439 case E1000_DEV_ID_82576_FIBER: 3440 case E1000_DEV_ID_82576_SERDES: 3441 /* Wake events only supported on port A for dual fiber 3442 * regardless of eeprom setting 3443 */ 3444 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3445 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3446 break; 3447 case E1000_DEV_ID_82576_QUAD_COPPER: 3448 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3449 /* if quad port adapter, disable WoL on all but port A */ 3450 if (global_quad_port_a != 0) 3451 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3452 else 3453 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3454 /* Reset for multiple quad port adapters */ 3455 if (++global_quad_port_a == 4) 3456 global_quad_port_a = 0; 3457 break; 3458 default: 3459 /* If the device can't wake, don't set software support */ 3460 if (!device_can_wakeup(&adapter->pdev->dev)) 3461 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3462 } 3463 3464 /* initialize the wol settings based on the eeprom settings */ 3465 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3466 adapter->wol |= E1000_WUFC_MAG; 3467 3468 /* Some vendors want WoL disabled by default, but still supported */ 3469 if ((hw->mac.type == e1000_i350) && 3470 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3471 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3472 adapter->wol = 0; 3473 } 3474 3475 /* Some vendors want the ability to Use the EEPROM setting as 3476 * enable/disable only, and not for capability 3477 */ 3478 if (((hw->mac.type == e1000_i350) || 3479 (hw->mac.type == e1000_i354)) && 3480 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3481 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3482 adapter->wol = 0; 3483 } 3484 if (hw->mac.type == e1000_i350) { 3485 if (((pdev->subsystem_device == 0x5001) || 3486 (pdev->subsystem_device == 0x5002)) && 3487 (hw->bus.func == 0)) { 3488 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3489 adapter->wol = 0; 3490 } 3491 if (pdev->subsystem_device == 0x1F52) 3492 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3493 } 3494 3495 device_set_wakeup_enable(&adapter->pdev->dev, 3496 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3497 3498 /* reset the hardware with the new settings */ 3499 igb_reset(adapter); 3500 3501 /* Init the I2C interface */ 3502 err = igb_init_i2c(adapter); 3503 if (err) { 3504 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3505 goto err_eeprom; 3506 } 3507 3508 /* let the f/w know that the h/w is now under the control of the 3509 * driver. 3510 */ 3511 igb_get_hw_control(adapter); 3512 3513 strcpy(netdev->name, "eth%d"); 3514 err = register_netdev(netdev); 3515 if (err) 3516 goto err_register; 3517 3518 /* carrier off reporting is important to ethtool even BEFORE open */ 3519 netif_carrier_off(netdev); 3520 3521 #ifdef CONFIG_IGB_DCA 3522 if (dca_add_requester(&pdev->dev) == 0) { 3523 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3524 dev_info(&pdev->dev, "DCA enabled\n"); 3525 igb_setup_dca(adapter); 3526 } 3527 3528 #endif 3529 #ifdef CONFIG_IGB_HWMON 3530 /* Initialize the thermal sensor on i350 devices. */ 3531 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3532 u16 ets_word; 3533 3534 /* Read the NVM to determine if this i350 device supports an 3535 * external thermal sensor. 3536 */ 3537 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3538 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3539 adapter->ets = true; 3540 else 3541 adapter->ets = false; 3542 /* Only enable I2C bit banging if an external thermal 3543 * sensor is supported. 3544 */ 3545 if (adapter->ets) 3546 igb_set_i2c_bb(hw); 3547 hw->mac.ops.init_thermal_sensor_thresh(hw); 3548 if (igb_sysfs_init(adapter)) 3549 dev_err(&pdev->dev, 3550 "failed to allocate sysfs resources\n"); 3551 } else { 3552 adapter->ets = false; 3553 } 3554 #endif 3555 /* Check if Media Autosense is enabled */ 3556 adapter->ei = *ei; 3557 if (hw->dev_spec._82575.mas_capable) 3558 igb_init_mas(adapter); 3559 3560 /* do hw tstamp init after resetting */ 3561 igb_ptp_init(adapter); 3562 3563 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3564 /* print bus type/speed/width info, not applicable to i354 */ 3565 if (hw->mac.type != e1000_i354) { 3566 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3567 netdev->name, 3568 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3569 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3570 "unknown"), 3571 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3572 "Width x4" : 3573 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3574 "Width x2" : 3575 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3576 "Width x1" : "unknown"), netdev->dev_addr); 3577 } 3578 3579 if ((hw->mac.type == e1000_82576 && 3580 rd32(E1000_EECD) & E1000_EECD_PRES) || 3581 (hw->mac.type >= e1000_i210 || 3582 igb_get_flash_presence_i210(hw))) { 3583 ret_val = igb_read_part_string(hw, part_str, 3584 E1000_PBANUM_LENGTH); 3585 } else { 3586 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3587 } 3588 3589 if (ret_val) 3590 strcpy(part_str, "Unknown"); 3591 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3592 dev_info(&pdev->dev, 3593 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3594 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3595 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3596 adapter->num_rx_queues, adapter->num_tx_queues); 3597 if (hw->phy.media_type == e1000_media_type_copper) { 3598 switch (hw->mac.type) { 3599 case e1000_i350: 3600 case e1000_i210: 3601 case e1000_i211: 3602 /* Enable EEE for internal copper PHY devices */ 3603 err = igb_set_eee_i350(hw, true, true); 3604 if ((!err) && 3605 (!hw->dev_spec._82575.eee_disable)) { 3606 adapter->eee_advert = 3607 MDIO_EEE_100TX | MDIO_EEE_1000T; 3608 adapter->flags |= IGB_FLAG_EEE; 3609 } 3610 break; 3611 case e1000_i354: 3612 if ((rd32(E1000_CTRL_EXT) & 3613 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3614 err = igb_set_eee_i354(hw, true, true); 3615 if ((!err) && 3616 (!hw->dev_spec._82575.eee_disable)) { 3617 adapter->eee_advert = 3618 MDIO_EEE_100TX | MDIO_EEE_1000T; 3619 adapter->flags |= IGB_FLAG_EEE; 3620 } 3621 } 3622 break; 3623 default: 3624 break; 3625 } 3626 } 3627 3628 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 3629 3630 pm_runtime_put_noidle(&pdev->dev); 3631 return 0; 3632 3633 err_register: 3634 igb_release_hw_control(adapter); 3635 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3636 err_eeprom: 3637 if (!igb_check_reset_block(hw)) 3638 igb_reset_phy(hw); 3639 3640 if (hw->flash_address) 3641 iounmap(hw->flash_address); 3642 err_sw_init: 3643 kfree(adapter->mac_table); 3644 kfree(adapter->shadow_vfta); 3645 igb_clear_interrupt_scheme(adapter); 3646 #ifdef CONFIG_PCI_IOV 3647 igb_disable_sriov(pdev, false); 3648 #endif 3649 pci_iounmap(pdev, adapter->io_addr); 3650 err_ioremap: 3651 free_netdev(netdev); 3652 err_alloc_etherdev: 3653 pci_release_mem_regions(pdev); 3654 err_pci_reg: 3655 err_dma: 3656 pci_disable_device(pdev); 3657 return err; 3658 } 3659 3660 #ifdef CONFIG_PCI_IOV 3661 static int igb_sriov_reinit(struct pci_dev *dev) 3662 { 3663 struct net_device *netdev = pci_get_drvdata(dev); 3664 struct igb_adapter *adapter = netdev_priv(netdev); 3665 struct pci_dev *pdev = adapter->pdev; 3666 3667 rtnl_lock(); 3668 3669 if (netif_running(netdev)) 3670 igb_close(netdev); 3671 else 3672 igb_reset(adapter); 3673 3674 igb_clear_interrupt_scheme(adapter); 3675 3676 igb_init_queue_configuration(adapter); 3677 3678 if (igb_init_interrupt_scheme(adapter, true)) { 3679 rtnl_unlock(); 3680 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3681 return -ENOMEM; 3682 } 3683 3684 if (netif_running(netdev)) 3685 igb_open(netdev); 3686 3687 rtnl_unlock(); 3688 3689 return 0; 3690 } 3691 3692 static int igb_disable_sriov(struct pci_dev *pdev, bool reinit) 3693 { 3694 struct net_device *netdev = pci_get_drvdata(pdev); 3695 struct igb_adapter *adapter = netdev_priv(netdev); 3696 struct e1000_hw *hw = &adapter->hw; 3697 unsigned long flags; 3698 3699 /* reclaim resources allocated to VFs */ 3700 if (adapter->vf_data) { 3701 /* disable iov and allow time for transactions to clear */ 3702 if (pci_vfs_assigned(pdev)) { 3703 dev_warn(&pdev->dev, 3704 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3705 return -EPERM; 3706 } else { 3707 pci_disable_sriov(pdev); 3708 msleep(500); 3709 } 3710 spin_lock_irqsave(&adapter->vfs_lock, flags); 3711 kfree(adapter->vf_mac_list); 3712 adapter->vf_mac_list = NULL; 3713 kfree(adapter->vf_data); 3714 adapter->vf_data = NULL; 3715 adapter->vfs_allocated_count = 0; 3716 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 3717 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3718 wrfl(); 3719 msleep(100); 3720 dev_info(&pdev->dev, "IOV Disabled\n"); 3721 3722 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3723 adapter->flags |= IGB_FLAG_DMAC; 3724 } 3725 3726 return reinit ? igb_sriov_reinit(pdev) : 0; 3727 } 3728 3729 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs, bool reinit) 3730 { 3731 struct net_device *netdev = pci_get_drvdata(pdev); 3732 struct igb_adapter *adapter = netdev_priv(netdev); 3733 int old_vfs = pci_num_vf(pdev); 3734 struct vf_mac_filter *mac_list; 3735 int err = 0; 3736 int num_vf_mac_filters, i; 3737 3738 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3739 err = -EPERM; 3740 goto out; 3741 } 3742 if (!num_vfs) 3743 goto out; 3744 3745 if (old_vfs) { 3746 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3747 old_vfs, max_vfs); 3748 adapter->vfs_allocated_count = old_vfs; 3749 } else 3750 adapter->vfs_allocated_count = num_vfs; 3751 3752 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3753 sizeof(struct vf_data_storage), GFP_KERNEL); 3754 3755 /* if allocation failed then we do not support SR-IOV */ 3756 if (!adapter->vf_data) { 3757 adapter->vfs_allocated_count = 0; 3758 err = -ENOMEM; 3759 goto out; 3760 } 3761 3762 /* Due to the limited number of RAR entries calculate potential 3763 * number of MAC filters available for the VFs. Reserve entries 3764 * for PF default MAC, PF MAC filters and at least one RAR entry 3765 * for each VF for VF MAC. 3766 */ 3767 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3768 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3769 adapter->vfs_allocated_count); 3770 3771 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3772 sizeof(struct vf_mac_filter), 3773 GFP_KERNEL); 3774 3775 mac_list = adapter->vf_mac_list; 3776 INIT_LIST_HEAD(&adapter->vf_macs.l); 3777 3778 if (adapter->vf_mac_list) { 3779 /* Initialize list of VF MAC filters */ 3780 for (i = 0; i < num_vf_mac_filters; i++) { 3781 mac_list->vf = -1; 3782 mac_list->free = true; 3783 list_add(&mac_list->l, &adapter->vf_macs.l); 3784 mac_list++; 3785 } 3786 } else { 3787 /* If we could not allocate memory for the VF MAC filters 3788 * we can continue without this feature but warn user. 3789 */ 3790 dev_err(&pdev->dev, 3791 "Unable to allocate memory for VF MAC filter list\n"); 3792 } 3793 3794 dev_info(&pdev->dev, "%d VFs allocated\n", 3795 adapter->vfs_allocated_count); 3796 for (i = 0; i < adapter->vfs_allocated_count; i++) 3797 igb_vf_configure(adapter, i); 3798 3799 /* DMA Coalescing is not supported in IOV mode. */ 3800 adapter->flags &= ~IGB_FLAG_DMAC; 3801 3802 if (reinit) { 3803 err = igb_sriov_reinit(pdev); 3804 if (err) 3805 goto err_out; 3806 } 3807 3808 /* only call pci_enable_sriov() if no VFs are allocated already */ 3809 if (!old_vfs) { 3810 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3811 if (err) 3812 goto err_out; 3813 } 3814 3815 goto out; 3816 3817 err_out: 3818 kfree(adapter->vf_mac_list); 3819 adapter->vf_mac_list = NULL; 3820 kfree(adapter->vf_data); 3821 adapter->vf_data = NULL; 3822 adapter->vfs_allocated_count = 0; 3823 out: 3824 return err; 3825 } 3826 3827 #endif 3828 /** 3829 * igb_remove_i2c - Cleanup I2C interface 3830 * @adapter: pointer to adapter structure 3831 **/ 3832 static void igb_remove_i2c(struct igb_adapter *adapter) 3833 { 3834 /* free the adapter bus structure */ 3835 i2c_del_adapter(&adapter->i2c_adap); 3836 } 3837 3838 /** 3839 * igb_remove - Device Removal Routine 3840 * @pdev: PCI device information struct 3841 * 3842 * igb_remove is called by the PCI subsystem to alert the driver 3843 * that it should release a PCI device. The could be caused by a 3844 * Hot-Plug event, or because the driver is going to be removed from 3845 * memory. 3846 **/ 3847 static void igb_remove(struct pci_dev *pdev) 3848 { 3849 struct net_device *netdev = pci_get_drvdata(pdev); 3850 struct igb_adapter *adapter = netdev_priv(netdev); 3851 struct e1000_hw *hw = &adapter->hw; 3852 3853 pm_runtime_get_noresume(&pdev->dev); 3854 #ifdef CONFIG_IGB_HWMON 3855 igb_sysfs_exit(adapter); 3856 #endif 3857 igb_remove_i2c(adapter); 3858 igb_ptp_stop(adapter); 3859 /* The watchdog timer may be rescheduled, so explicitly 3860 * disable watchdog from being rescheduled. 3861 */ 3862 set_bit(__IGB_DOWN, &adapter->state); 3863 del_timer_sync(&adapter->watchdog_timer); 3864 del_timer_sync(&adapter->phy_info_timer); 3865 3866 cancel_work_sync(&adapter->reset_task); 3867 cancel_work_sync(&adapter->watchdog_task); 3868 3869 #ifdef CONFIG_IGB_DCA 3870 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3871 dev_info(&pdev->dev, "DCA disabled\n"); 3872 dca_remove_requester(&pdev->dev); 3873 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3874 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3875 } 3876 #endif 3877 3878 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3879 * would have already happened in close and is redundant. 3880 */ 3881 igb_release_hw_control(adapter); 3882 3883 #ifdef CONFIG_PCI_IOV 3884 igb_disable_sriov(pdev, false); 3885 #endif 3886 3887 unregister_netdev(netdev); 3888 3889 igb_clear_interrupt_scheme(adapter); 3890 3891 pci_iounmap(pdev, adapter->io_addr); 3892 if (hw->flash_address) 3893 iounmap(hw->flash_address); 3894 pci_release_mem_regions(pdev); 3895 3896 kfree(adapter->mac_table); 3897 kfree(adapter->shadow_vfta); 3898 free_netdev(netdev); 3899 3900 pci_disable_device(pdev); 3901 } 3902 3903 /** 3904 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3905 * @adapter: board private structure to initialize 3906 * 3907 * This function initializes the vf specific data storage and then attempts to 3908 * allocate the VFs. The reason for ordering it this way is because it is much 3909 * more expensive time wise to disable SR-IOV than it is to allocate and free 3910 * the memory for the VFs. 3911 **/ 3912 static void igb_probe_vfs(struct igb_adapter *adapter) 3913 { 3914 #ifdef CONFIG_PCI_IOV 3915 struct pci_dev *pdev = adapter->pdev; 3916 struct e1000_hw *hw = &adapter->hw; 3917 3918 /* Virtualization features not supported on i210 and 82580 family. */ 3919 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211) || 3920 (hw->mac.type == e1000_82580)) 3921 return; 3922 3923 /* Of the below we really only want the effect of getting 3924 * IGB_FLAG_HAS_MSIX set (if available), without which 3925 * igb_enable_sriov() has no effect. 3926 */ 3927 igb_set_interrupt_capability(adapter, true); 3928 igb_reset_interrupt_capability(adapter); 3929 3930 pci_sriov_set_totalvfs(pdev, 7); 3931 igb_enable_sriov(pdev, max_vfs, false); 3932 3933 #endif /* CONFIG_PCI_IOV */ 3934 } 3935 3936 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3937 { 3938 struct e1000_hw *hw = &adapter->hw; 3939 unsigned int max_rss_queues; 3940 3941 /* Determine the maximum number of RSS queues supported. */ 3942 switch (hw->mac.type) { 3943 case e1000_i211: 3944 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3945 break; 3946 case e1000_82575: 3947 case e1000_i210: 3948 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3949 break; 3950 case e1000_i350: 3951 /* I350 cannot do RSS and SR-IOV at the same time */ 3952 if (!!adapter->vfs_allocated_count) { 3953 max_rss_queues = 1; 3954 break; 3955 } 3956 fallthrough; 3957 case e1000_82576: 3958 if (!!adapter->vfs_allocated_count) { 3959 max_rss_queues = 2; 3960 break; 3961 } 3962 fallthrough; 3963 case e1000_82580: 3964 case e1000_i354: 3965 default: 3966 max_rss_queues = IGB_MAX_RX_QUEUES; 3967 break; 3968 } 3969 3970 return max_rss_queues; 3971 } 3972 3973 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3974 { 3975 u32 max_rss_queues; 3976 3977 max_rss_queues = igb_get_max_rss_queues(adapter); 3978 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3979 3980 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3981 } 3982 3983 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3984 const u32 max_rss_queues) 3985 { 3986 struct e1000_hw *hw = &adapter->hw; 3987 3988 /* Determine if we need to pair queues. */ 3989 switch (hw->mac.type) { 3990 case e1000_82575: 3991 case e1000_i211: 3992 /* Device supports enough interrupts without queue pairing. */ 3993 break; 3994 case e1000_82576: 3995 case e1000_82580: 3996 case e1000_i350: 3997 case e1000_i354: 3998 case e1000_i210: 3999 default: 4000 /* If rss_queues > half of max_rss_queues, pair the queues in 4001 * order to conserve interrupts due to limited supply. 4002 */ 4003 if (adapter->rss_queues > (max_rss_queues / 2)) 4004 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 4005 else 4006 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 4007 break; 4008 } 4009 } 4010 4011 /** 4012 * igb_sw_init - Initialize general software structures (struct igb_adapter) 4013 * @adapter: board private structure to initialize 4014 * 4015 * igb_sw_init initializes the Adapter private data structure. 4016 * Fields are initialized based on PCI device information and 4017 * OS network device settings (MTU size). 4018 **/ 4019 static int igb_sw_init(struct igb_adapter *adapter) 4020 { 4021 struct e1000_hw *hw = &adapter->hw; 4022 struct net_device *netdev = adapter->netdev; 4023 struct pci_dev *pdev = adapter->pdev; 4024 4025 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 4026 4027 /* set default ring sizes */ 4028 adapter->tx_ring_count = IGB_DEFAULT_TXD; 4029 adapter->rx_ring_count = IGB_DEFAULT_RXD; 4030 4031 /* set default ITR values */ 4032 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 4033 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 4034 4035 /* set default work limits */ 4036 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 4037 4038 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD; 4039 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4040 4041 spin_lock_init(&adapter->nfc_lock); 4042 spin_lock_init(&adapter->stats64_lock); 4043 4044 /* init spinlock to avoid concurrency of VF resources */ 4045 spin_lock_init(&adapter->vfs_lock); 4046 #ifdef CONFIG_PCI_IOV 4047 switch (hw->mac.type) { 4048 case e1000_82576: 4049 case e1000_i350: 4050 if (max_vfs > 7) { 4051 dev_warn(&pdev->dev, 4052 "Maximum of 7 VFs per PF, using max\n"); 4053 max_vfs = adapter->vfs_allocated_count = 7; 4054 } else 4055 adapter->vfs_allocated_count = max_vfs; 4056 if (adapter->vfs_allocated_count) 4057 dev_warn(&pdev->dev, 4058 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 4059 break; 4060 default: 4061 break; 4062 } 4063 #endif /* CONFIG_PCI_IOV */ 4064 4065 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 4066 adapter->flags |= IGB_FLAG_HAS_MSIX; 4067 4068 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 4069 sizeof(struct igb_mac_addr), 4070 GFP_KERNEL); 4071 if (!adapter->mac_table) 4072 return -ENOMEM; 4073 4074 igb_probe_vfs(adapter); 4075 4076 igb_init_queue_configuration(adapter); 4077 4078 /* Setup and initialize a copy of the hw vlan table array */ 4079 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 4080 GFP_KERNEL); 4081 if (!adapter->shadow_vfta) 4082 return -ENOMEM; 4083 4084 /* This call may decrease the number of queues */ 4085 if (igb_init_interrupt_scheme(adapter, true)) { 4086 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4087 return -ENOMEM; 4088 } 4089 4090 /* Explicitly disable IRQ since the NIC can be in any state. */ 4091 igb_irq_disable(adapter); 4092 4093 if (hw->mac.type >= e1000_i350) 4094 adapter->flags &= ~IGB_FLAG_DMAC; 4095 4096 set_bit(__IGB_DOWN, &adapter->state); 4097 return 0; 4098 } 4099 4100 /** 4101 * __igb_open - Called when a network interface is made active 4102 * @netdev: network interface device structure 4103 * @resuming: indicates whether we are in a resume call 4104 * 4105 * Returns 0 on success, negative value on failure 4106 * 4107 * The open entry point is called when a network interface is made 4108 * active by the system (IFF_UP). At this point all resources needed 4109 * for transmit and receive operations are allocated, the interrupt 4110 * handler is registered with the OS, the watchdog timer is started, 4111 * and the stack is notified that the interface is ready. 4112 **/ 4113 static int __igb_open(struct net_device *netdev, bool resuming) 4114 { 4115 struct igb_adapter *adapter = netdev_priv(netdev); 4116 struct e1000_hw *hw = &adapter->hw; 4117 struct pci_dev *pdev = adapter->pdev; 4118 int err; 4119 int i; 4120 4121 /* disallow open during test */ 4122 if (test_bit(__IGB_TESTING, &adapter->state)) { 4123 WARN_ON(resuming); 4124 return -EBUSY; 4125 } 4126 4127 if (!resuming) 4128 pm_runtime_get_sync(&pdev->dev); 4129 4130 netif_carrier_off(netdev); 4131 4132 /* allocate transmit descriptors */ 4133 err = igb_setup_all_tx_resources(adapter); 4134 if (err) 4135 goto err_setup_tx; 4136 4137 /* allocate receive descriptors */ 4138 err = igb_setup_all_rx_resources(adapter); 4139 if (err) 4140 goto err_setup_rx; 4141 4142 igb_power_up_link(adapter); 4143 4144 /* before we allocate an interrupt, we must be ready to handle it. 4145 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4146 * as soon as we call pci_request_irq, so we have to setup our 4147 * clean_rx handler before we do so. 4148 */ 4149 igb_configure(adapter); 4150 4151 err = igb_request_irq(adapter); 4152 if (err) 4153 goto err_req_irq; 4154 4155 /* Notify the stack of the actual queue counts. */ 4156 err = netif_set_real_num_tx_queues(adapter->netdev, 4157 adapter->num_tx_queues); 4158 if (err) 4159 goto err_set_queues; 4160 4161 err = netif_set_real_num_rx_queues(adapter->netdev, 4162 adapter->num_rx_queues); 4163 if (err) 4164 goto err_set_queues; 4165 4166 /* From here on the code is the same as igb_up() */ 4167 clear_bit(__IGB_DOWN, &adapter->state); 4168 4169 for (i = 0; i < adapter->num_q_vectors; i++) 4170 napi_enable(&(adapter->q_vector[i]->napi)); 4171 4172 /* Clear any pending interrupts. */ 4173 rd32(E1000_TSICR); 4174 rd32(E1000_ICR); 4175 4176 igb_irq_enable(adapter); 4177 4178 /* notify VFs that reset has been completed */ 4179 if (adapter->vfs_allocated_count) { 4180 u32 reg_data = rd32(E1000_CTRL_EXT); 4181 4182 reg_data |= E1000_CTRL_EXT_PFRSTD; 4183 wr32(E1000_CTRL_EXT, reg_data); 4184 } 4185 4186 netif_tx_start_all_queues(netdev); 4187 4188 if (!resuming) 4189 pm_runtime_put(&pdev->dev); 4190 4191 /* start the watchdog. */ 4192 hw->mac.get_link_status = 1; 4193 schedule_work(&adapter->watchdog_task); 4194 4195 return 0; 4196 4197 err_set_queues: 4198 igb_free_irq(adapter); 4199 err_req_irq: 4200 igb_release_hw_control(adapter); 4201 igb_power_down_link(adapter); 4202 igb_free_all_rx_resources(adapter); 4203 err_setup_rx: 4204 igb_free_all_tx_resources(adapter); 4205 err_setup_tx: 4206 igb_reset(adapter); 4207 if (!resuming) 4208 pm_runtime_put(&pdev->dev); 4209 4210 return err; 4211 } 4212 4213 int igb_open(struct net_device *netdev) 4214 { 4215 return __igb_open(netdev, false); 4216 } 4217 4218 /** 4219 * __igb_close - Disables a network interface 4220 * @netdev: network interface device structure 4221 * @suspending: indicates we are in a suspend call 4222 * 4223 * Returns 0, this is not allowed to fail 4224 * 4225 * The close entry point is called when an interface is de-activated 4226 * by the OS. The hardware is still under the driver's control, but 4227 * needs to be disabled. A global MAC reset is issued to stop the 4228 * hardware, and all transmit and receive resources are freed. 4229 **/ 4230 static int __igb_close(struct net_device *netdev, bool suspending) 4231 { 4232 struct igb_adapter *adapter = netdev_priv(netdev); 4233 struct pci_dev *pdev = adapter->pdev; 4234 4235 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4236 4237 if (!suspending) 4238 pm_runtime_get_sync(&pdev->dev); 4239 4240 igb_down(adapter); 4241 igb_free_irq(adapter); 4242 4243 igb_free_all_tx_resources(adapter); 4244 igb_free_all_rx_resources(adapter); 4245 4246 if (!suspending) 4247 pm_runtime_put_sync(&pdev->dev); 4248 return 0; 4249 } 4250 4251 int igb_close(struct net_device *netdev) 4252 { 4253 if (netif_device_present(netdev) || netdev->dismantle) 4254 return __igb_close(netdev, false); 4255 return 0; 4256 } 4257 4258 /** 4259 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4260 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4261 * 4262 * Return 0 on success, negative on failure 4263 **/ 4264 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4265 { 4266 struct device *dev = tx_ring->dev; 4267 int size; 4268 4269 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4270 4271 tx_ring->tx_buffer_info = vmalloc(size); 4272 if (!tx_ring->tx_buffer_info) 4273 goto err; 4274 4275 /* round up to nearest 4K */ 4276 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4277 tx_ring->size = ALIGN(tx_ring->size, 4096); 4278 4279 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4280 &tx_ring->dma, GFP_KERNEL); 4281 if (!tx_ring->desc) 4282 goto err; 4283 4284 tx_ring->next_to_use = 0; 4285 tx_ring->next_to_clean = 0; 4286 4287 return 0; 4288 4289 err: 4290 vfree(tx_ring->tx_buffer_info); 4291 tx_ring->tx_buffer_info = NULL; 4292 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4293 return -ENOMEM; 4294 } 4295 4296 /** 4297 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4298 * (Descriptors) for all queues 4299 * @adapter: board private structure 4300 * 4301 * Return 0 on success, negative on failure 4302 **/ 4303 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4304 { 4305 struct pci_dev *pdev = adapter->pdev; 4306 int i, err = 0; 4307 4308 for (i = 0; i < adapter->num_tx_queues; i++) { 4309 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4310 if (err) { 4311 dev_err(&pdev->dev, 4312 "Allocation for Tx Queue %u failed\n", i); 4313 for (i--; i >= 0; i--) 4314 igb_free_tx_resources(adapter->tx_ring[i]); 4315 break; 4316 } 4317 } 4318 4319 return err; 4320 } 4321 4322 /** 4323 * igb_setup_tctl - configure the transmit control registers 4324 * @adapter: Board private structure 4325 **/ 4326 void igb_setup_tctl(struct igb_adapter *adapter) 4327 { 4328 struct e1000_hw *hw = &adapter->hw; 4329 u32 tctl; 4330 4331 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4332 wr32(E1000_TXDCTL(0), 0); 4333 4334 /* Program the Transmit Control Register */ 4335 tctl = rd32(E1000_TCTL); 4336 tctl &= ~E1000_TCTL_CT; 4337 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4338 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4339 4340 igb_config_collision_dist(hw); 4341 4342 /* Enable transmits */ 4343 tctl |= E1000_TCTL_EN; 4344 4345 wr32(E1000_TCTL, tctl); 4346 } 4347 4348 /** 4349 * igb_configure_tx_ring - Configure transmit ring after Reset 4350 * @adapter: board private structure 4351 * @ring: tx ring to configure 4352 * 4353 * Configure a transmit ring after a reset. 4354 **/ 4355 void igb_configure_tx_ring(struct igb_adapter *adapter, 4356 struct igb_ring *ring) 4357 { 4358 struct e1000_hw *hw = &adapter->hw; 4359 u32 txdctl = 0; 4360 u64 tdba = ring->dma; 4361 int reg_idx = ring->reg_idx; 4362 4363 WRITE_ONCE(ring->xsk_pool, igb_xsk_pool(adapter, ring)); 4364 4365 wr32(E1000_TDLEN(reg_idx), 4366 ring->count * sizeof(union e1000_adv_tx_desc)); 4367 wr32(E1000_TDBAL(reg_idx), 4368 tdba & 0x00000000ffffffffULL); 4369 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4370 4371 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4372 wr32(E1000_TDH(reg_idx), 0); 4373 writel(0, ring->tail); 4374 4375 txdctl |= IGB_TX_PTHRESH; 4376 txdctl |= IGB_TX_HTHRESH << 8; 4377 txdctl |= IGB_TX_WTHRESH << 16; 4378 4379 /* reinitialize tx_buffer_info */ 4380 memset(ring->tx_buffer_info, 0, 4381 sizeof(struct igb_tx_buffer) * ring->count); 4382 4383 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4384 wr32(E1000_TXDCTL(reg_idx), txdctl); 4385 } 4386 4387 /** 4388 * igb_configure_tx - Configure transmit Unit after Reset 4389 * @adapter: board private structure 4390 * 4391 * Configure the Tx unit of the MAC after a reset. 4392 **/ 4393 static void igb_configure_tx(struct igb_adapter *adapter) 4394 { 4395 struct e1000_hw *hw = &adapter->hw; 4396 int i; 4397 4398 /* disable the queues */ 4399 for (i = 0; i < adapter->num_tx_queues; i++) 4400 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4401 4402 wrfl(); 4403 usleep_range(10000, 20000); 4404 4405 for (i = 0; i < adapter->num_tx_queues; i++) 4406 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4407 } 4408 4409 /** 4410 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4411 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4412 * 4413 * Returns 0 on success, negative on failure 4414 **/ 4415 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4416 { 4417 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev); 4418 struct device *dev = rx_ring->dev; 4419 int size, res; 4420 4421 /* XDP RX-queue info */ 4422 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq)) 4423 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4424 res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 4425 rx_ring->queue_index, 4426 rx_ring->q_vector->napi.napi_id); 4427 if (res < 0) { 4428 dev_err(dev, "Failed to register xdp_rxq index %u\n", 4429 rx_ring->queue_index); 4430 return res; 4431 } 4432 4433 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4434 4435 rx_ring->rx_buffer_info = vmalloc(size); 4436 if (!rx_ring->rx_buffer_info) 4437 goto err; 4438 4439 /* Round up to nearest 4K */ 4440 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4441 rx_ring->size = ALIGN(rx_ring->size, 4096); 4442 4443 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4444 &rx_ring->dma, GFP_KERNEL); 4445 if (!rx_ring->desc) 4446 goto err; 4447 4448 rx_ring->next_to_alloc = 0; 4449 rx_ring->next_to_clean = 0; 4450 rx_ring->next_to_use = 0; 4451 4452 rx_ring->xdp_prog = adapter->xdp_prog; 4453 4454 return 0; 4455 4456 err: 4457 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4458 vfree(rx_ring->rx_buffer_info); 4459 rx_ring->rx_buffer_info = NULL; 4460 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4461 return -ENOMEM; 4462 } 4463 4464 /** 4465 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4466 * (Descriptors) for all queues 4467 * @adapter: board private structure 4468 * 4469 * Return 0 on success, negative on failure 4470 **/ 4471 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4472 { 4473 struct pci_dev *pdev = adapter->pdev; 4474 int i, err = 0; 4475 4476 for (i = 0; i < adapter->num_rx_queues; i++) { 4477 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4478 if (err) { 4479 dev_err(&pdev->dev, 4480 "Allocation for Rx Queue %u failed\n", i); 4481 for (i--; i >= 0; i--) 4482 igb_free_rx_resources(adapter->rx_ring[i]); 4483 break; 4484 } 4485 } 4486 4487 return err; 4488 } 4489 4490 /** 4491 * igb_setup_mrqc - configure the multiple receive queue control registers 4492 * @adapter: Board private structure 4493 **/ 4494 static void igb_setup_mrqc(struct igb_adapter *adapter) 4495 { 4496 struct e1000_hw *hw = &adapter->hw; 4497 u32 mrqc, rxcsum; 4498 u32 j, num_rx_queues; 4499 u32 rss_key[10]; 4500 4501 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4502 for (j = 0; j < 10; j++) 4503 wr32(E1000_RSSRK(j), rss_key[j]); 4504 4505 num_rx_queues = adapter->rss_queues; 4506 4507 switch (hw->mac.type) { 4508 case e1000_82576: 4509 /* 82576 supports 2 RSS queues for SR-IOV */ 4510 if (adapter->vfs_allocated_count) 4511 num_rx_queues = 2; 4512 break; 4513 default: 4514 break; 4515 } 4516 4517 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4518 for (j = 0; j < IGB_RETA_SIZE; j++) 4519 adapter->rss_indir_tbl[j] = 4520 (j * num_rx_queues) / IGB_RETA_SIZE; 4521 adapter->rss_indir_tbl_init = num_rx_queues; 4522 } 4523 igb_write_rss_indir_tbl(adapter); 4524 4525 /* Disable raw packet checksumming so that RSS hash is placed in 4526 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4527 * offloads as they are enabled by default 4528 */ 4529 rxcsum = rd32(E1000_RXCSUM); 4530 rxcsum |= E1000_RXCSUM_PCSD; 4531 4532 if (adapter->hw.mac.type >= e1000_82576) 4533 /* Enable Receive Checksum Offload for SCTP */ 4534 rxcsum |= E1000_RXCSUM_CRCOFL; 4535 4536 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4537 wr32(E1000_RXCSUM, rxcsum); 4538 4539 /* Generate RSS hash based on packet types, TCP/UDP 4540 * port numbers and/or IPv4/v6 src and dst addresses 4541 */ 4542 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4543 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4544 E1000_MRQC_RSS_FIELD_IPV6 | 4545 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4546 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4547 4548 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4549 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4550 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4551 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4552 4553 /* If VMDq is enabled then we set the appropriate mode for that, else 4554 * we default to RSS so that an RSS hash is calculated per packet even 4555 * if we are only using one queue 4556 */ 4557 if (adapter->vfs_allocated_count) { 4558 if (hw->mac.type > e1000_82575) { 4559 /* Set the default pool for the PF's first queue */ 4560 u32 vtctl = rd32(E1000_VT_CTL); 4561 4562 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4563 E1000_VT_CTL_DISABLE_DEF_POOL); 4564 vtctl |= adapter->vfs_allocated_count << 4565 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4566 wr32(E1000_VT_CTL, vtctl); 4567 } 4568 if (adapter->rss_queues > 1) 4569 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4570 else 4571 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4572 } else { 4573 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4574 } 4575 igb_vmm_control(adapter); 4576 4577 wr32(E1000_MRQC, mrqc); 4578 } 4579 4580 /** 4581 * igb_setup_rctl - configure the receive control registers 4582 * @adapter: Board private structure 4583 **/ 4584 void igb_setup_rctl(struct igb_adapter *adapter) 4585 { 4586 struct e1000_hw *hw = &adapter->hw; 4587 u32 rctl; 4588 4589 rctl = rd32(E1000_RCTL); 4590 4591 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4592 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4593 4594 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4595 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4596 4597 /* enable stripping of CRC. It's unlikely this will break BMC 4598 * redirection as it did with e1000. Newer features require 4599 * that the HW strips the CRC. 4600 */ 4601 rctl |= E1000_RCTL_SECRC; 4602 4603 /* disable store bad packets and clear size bits. */ 4604 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4605 4606 /* enable LPE to allow for reception of jumbo frames */ 4607 rctl |= E1000_RCTL_LPE; 4608 4609 /* disable queue 0 to prevent tail write w/o re-config */ 4610 wr32(E1000_RXDCTL(0), 0); 4611 4612 /* Attention!!! For SR-IOV PF driver operations you must enable 4613 * queue drop for all VF and PF queues to prevent head of line blocking 4614 * if an un-trusted VF does not provide descriptors to hardware. 4615 */ 4616 if (adapter->vfs_allocated_count) { 4617 /* set all queue drop enable bits */ 4618 wr32(E1000_QDE, ALL_QUEUES); 4619 } 4620 4621 /* This is useful for sniffing bad packets. */ 4622 if (adapter->netdev->features & NETIF_F_RXALL) { 4623 /* UPE and MPE will be handled by normal PROMISC logic 4624 * in e1000e_set_rx_mode 4625 */ 4626 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4627 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4628 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4629 4630 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4631 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4632 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4633 * and that breaks VLANs. 4634 */ 4635 } 4636 4637 wr32(E1000_RCTL, rctl); 4638 } 4639 4640 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4641 int vfn) 4642 { 4643 struct e1000_hw *hw = &adapter->hw; 4644 u32 vmolr; 4645 4646 if (size > MAX_JUMBO_FRAME_SIZE) 4647 size = MAX_JUMBO_FRAME_SIZE; 4648 4649 vmolr = rd32(E1000_VMOLR(vfn)); 4650 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4651 vmolr |= size | E1000_VMOLR_LPE; 4652 wr32(E1000_VMOLR(vfn), vmolr); 4653 4654 return 0; 4655 } 4656 4657 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4658 int vfn, bool enable) 4659 { 4660 struct e1000_hw *hw = &adapter->hw; 4661 u32 val, reg; 4662 4663 if (hw->mac.type < e1000_82576) 4664 return; 4665 4666 if (hw->mac.type == e1000_i350) 4667 reg = E1000_DVMOLR(vfn); 4668 else 4669 reg = E1000_VMOLR(vfn); 4670 4671 val = rd32(reg); 4672 if (enable) 4673 val |= E1000_VMOLR_STRVLAN; 4674 else 4675 val &= ~(E1000_VMOLR_STRVLAN); 4676 wr32(reg, val); 4677 } 4678 4679 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4680 int vfn, bool aupe) 4681 { 4682 struct e1000_hw *hw = &adapter->hw; 4683 u32 vmolr; 4684 4685 /* This register exists only on 82576 and newer so if we are older then 4686 * we should exit and do nothing 4687 */ 4688 if (hw->mac.type < e1000_82576) 4689 return; 4690 4691 vmolr = rd32(E1000_VMOLR(vfn)); 4692 if (aupe) 4693 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4694 else 4695 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4696 4697 /* clear all bits that might not be set */ 4698 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4699 4700 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4701 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4702 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4703 * multicast packets 4704 */ 4705 if (vfn <= adapter->vfs_allocated_count) 4706 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4707 4708 wr32(E1000_VMOLR(vfn), vmolr); 4709 } 4710 4711 /** 4712 * igb_setup_srrctl - configure the split and replication receive control 4713 * registers 4714 * @adapter: Board private structure 4715 * @ring: receive ring to be configured 4716 **/ 4717 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring) 4718 { 4719 struct e1000_hw *hw = &adapter->hw; 4720 int reg_idx = ring->reg_idx; 4721 u32 srrctl = 0; 4722 u32 buf_size; 4723 4724 if (ring->xsk_pool) 4725 buf_size = xsk_pool_get_rx_frame_size(ring->xsk_pool); 4726 else if (ring_uses_large_buffer(ring)) 4727 buf_size = IGB_RXBUFFER_3072; 4728 else 4729 buf_size = IGB_RXBUFFER_2048; 4730 4731 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4732 srrctl |= buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4733 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4734 if (hw->mac.type >= e1000_82580) 4735 srrctl |= E1000_SRRCTL_TIMESTAMP; 4736 /* Only set Drop Enable if VFs allocated, or we are supporting multiple 4737 * queues and rx flow control is disabled 4738 */ 4739 if (adapter->vfs_allocated_count || 4740 (!(hw->fc.current_mode & e1000_fc_rx_pause) && 4741 adapter->num_rx_queues > 1)) 4742 srrctl |= E1000_SRRCTL_DROP_EN; 4743 4744 wr32(E1000_SRRCTL(reg_idx), srrctl); 4745 } 4746 4747 /** 4748 * igb_configure_rx_ring - Configure a receive ring after Reset 4749 * @adapter: board private structure 4750 * @ring: receive ring to be configured 4751 * 4752 * Configure the Rx unit of the MAC after a reset. 4753 **/ 4754 void igb_configure_rx_ring(struct igb_adapter *adapter, 4755 struct igb_ring *ring) 4756 { 4757 struct e1000_hw *hw = &adapter->hw; 4758 union e1000_adv_rx_desc *rx_desc; 4759 u64 rdba = ring->dma; 4760 int reg_idx = ring->reg_idx; 4761 u32 rxdctl = 0; 4762 4763 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4764 WRITE_ONCE(ring->xsk_pool, igb_xsk_pool(adapter, ring)); 4765 if (ring->xsk_pool) { 4766 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4767 MEM_TYPE_XSK_BUFF_POOL, 4768 NULL)); 4769 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq); 4770 } else { 4771 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4772 MEM_TYPE_PAGE_SHARED, 4773 NULL)); 4774 } 4775 4776 /* disable the queue */ 4777 wr32(E1000_RXDCTL(reg_idx), 0); 4778 4779 /* Set DMA base address registers */ 4780 wr32(E1000_RDBAL(reg_idx), 4781 rdba & 0x00000000ffffffffULL); 4782 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4783 wr32(E1000_RDLEN(reg_idx), 4784 ring->count * sizeof(union e1000_adv_rx_desc)); 4785 4786 /* initialize head and tail */ 4787 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4788 wr32(E1000_RDH(reg_idx), 0); 4789 writel(0, ring->tail); 4790 4791 /* set descriptor configuration */ 4792 igb_setup_srrctl(adapter, ring); 4793 4794 /* set filtering for VMDQ pools */ 4795 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4796 4797 rxdctl |= IGB_RX_PTHRESH; 4798 rxdctl |= IGB_RX_HTHRESH << 8; 4799 rxdctl |= IGB_RX_WTHRESH << 16; 4800 4801 if (ring->xsk_pool) 4802 memset(ring->rx_buffer_info_zc, 0, 4803 sizeof(*ring->rx_buffer_info_zc) * ring->count); 4804 else 4805 memset(ring->rx_buffer_info, 0, 4806 sizeof(*ring->rx_buffer_info) * ring->count); 4807 4808 /* initialize Rx descriptor 0 */ 4809 rx_desc = IGB_RX_DESC(ring, 0); 4810 rx_desc->wb.upper.length = 0; 4811 4812 /* enable receive descriptor fetching */ 4813 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4814 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4815 } 4816 4817 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4818 struct igb_ring *rx_ring) 4819 { 4820 #if (PAGE_SIZE < 8192) 4821 struct e1000_hw *hw = &adapter->hw; 4822 #endif 4823 4824 /* set build_skb and buffer size flags */ 4825 clear_ring_build_skb_enabled(rx_ring); 4826 clear_ring_uses_large_buffer(rx_ring); 4827 4828 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4829 return; 4830 4831 set_ring_build_skb_enabled(rx_ring); 4832 4833 #if (PAGE_SIZE < 8192) 4834 if (adapter->max_frame_size > IGB_MAX_FRAME_BUILD_SKB || 4835 IGB_2K_TOO_SMALL_WITH_PADDING || 4836 rd32(E1000_RCTL) & E1000_RCTL_SBP) 4837 set_ring_uses_large_buffer(rx_ring); 4838 #endif 4839 } 4840 4841 /** 4842 * igb_configure_rx - Configure receive Unit after Reset 4843 * @adapter: board private structure 4844 * 4845 * Configure the Rx unit of the MAC after a reset. 4846 **/ 4847 static void igb_configure_rx(struct igb_adapter *adapter) 4848 { 4849 int i; 4850 4851 /* set the correct pool for the PF default MAC address in entry 0 */ 4852 igb_set_default_mac_filter(adapter); 4853 4854 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4855 * the Base and Length of the Rx Descriptor Ring 4856 */ 4857 for (i = 0; i < adapter->num_rx_queues; i++) { 4858 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4859 4860 igb_set_rx_buffer_len(adapter, rx_ring); 4861 igb_configure_rx_ring(adapter, rx_ring); 4862 } 4863 } 4864 4865 /** 4866 * igb_free_tx_resources - Free Tx Resources per Queue 4867 * @tx_ring: Tx descriptor ring for a specific queue 4868 * 4869 * Free all transmit software resources 4870 **/ 4871 void igb_free_tx_resources(struct igb_ring *tx_ring) 4872 { 4873 igb_clean_tx_ring(tx_ring); 4874 4875 vfree(tx_ring->tx_buffer_info); 4876 tx_ring->tx_buffer_info = NULL; 4877 4878 /* if not set, then don't free */ 4879 if (!tx_ring->desc) 4880 return; 4881 4882 dma_free_coherent(tx_ring->dev, tx_ring->size, 4883 tx_ring->desc, tx_ring->dma); 4884 4885 tx_ring->desc = NULL; 4886 } 4887 4888 /** 4889 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4890 * @adapter: board private structure 4891 * 4892 * Free all transmit software resources 4893 **/ 4894 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4895 { 4896 int i; 4897 4898 for (i = 0; i < adapter->num_tx_queues; i++) 4899 if (adapter->tx_ring[i]) 4900 igb_free_tx_resources(adapter->tx_ring[i]); 4901 } 4902 4903 /** 4904 * igb_clean_tx_ring - Free Tx Buffers 4905 * @tx_ring: ring to be cleaned 4906 **/ 4907 void igb_clean_tx_ring(struct igb_ring *tx_ring) 4908 { 4909 u16 i = tx_ring->next_to_clean; 4910 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4911 u32 xsk_frames = 0; 4912 4913 while (i != tx_ring->next_to_use) { 4914 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4915 4916 /* Free all the Tx ring sk_buffs or xdp frames */ 4917 if (tx_buffer->type == IGB_TYPE_SKB) { 4918 dev_kfree_skb_any(tx_buffer->skb); 4919 } else if (tx_buffer->type == IGB_TYPE_XDP) { 4920 xdp_return_frame(tx_buffer->xdpf); 4921 } else if (tx_buffer->type == IGB_TYPE_XSK) { 4922 xsk_frames++; 4923 goto skip_for_xsk; 4924 } 4925 4926 /* unmap skb header data */ 4927 dma_unmap_single(tx_ring->dev, 4928 dma_unmap_addr(tx_buffer, dma), 4929 dma_unmap_len(tx_buffer, len), 4930 DMA_TO_DEVICE); 4931 4932 /* check for eop_desc to determine the end of the packet */ 4933 eop_desc = tx_buffer->next_to_watch; 4934 tx_desc = IGB_TX_DESC(tx_ring, i); 4935 4936 /* unmap remaining buffers */ 4937 while (tx_desc != eop_desc) { 4938 tx_buffer++; 4939 tx_desc++; 4940 i++; 4941 if (unlikely(i == tx_ring->count)) { 4942 i = 0; 4943 tx_buffer = tx_ring->tx_buffer_info; 4944 tx_desc = IGB_TX_DESC(tx_ring, 0); 4945 } 4946 4947 /* unmap any remaining paged data */ 4948 if (dma_unmap_len(tx_buffer, len)) 4949 dma_unmap_page(tx_ring->dev, 4950 dma_unmap_addr(tx_buffer, dma), 4951 dma_unmap_len(tx_buffer, len), 4952 DMA_TO_DEVICE); 4953 } 4954 4955 skip_for_xsk: 4956 tx_buffer->next_to_watch = NULL; 4957 4958 /* move us one more past the eop_desc for start of next pkt */ 4959 tx_buffer++; 4960 i++; 4961 if (unlikely(i == tx_ring->count)) { 4962 i = 0; 4963 tx_buffer = tx_ring->tx_buffer_info; 4964 } 4965 } 4966 4967 /* reset BQL for queue */ 4968 netdev_tx_reset_queue(txring_txq(tx_ring)); 4969 4970 if (tx_ring->xsk_pool && xsk_frames) 4971 xsk_tx_completed(tx_ring->xsk_pool, xsk_frames); 4972 4973 /* reset next_to_use and next_to_clean */ 4974 tx_ring->next_to_use = 0; 4975 tx_ring->next_to_clean = 0; 4976 } 4977 4978 /** 4979 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 4980 * @adapter: board private structure 4981 **/ 4982 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 4983 { 4984 int i; 4985 4986 for (i = 0; i < adapter->num_tx_queues; i++) 4987 if (adapter->tx_ring[i]) 4988 igb_clean_tx_ring(adapter->tx_ring[i]); 4989 } 4990 4991 /** 4992 * igb_free_rx_resources - Free Rx Resources 4993 * @rx_ring: ring to clean the resources from 4994 * 4995 * Free all receive software resources 4996 **/ 4997 void igb_free_rx_resources(struct igb_ring *rx_ring) 4998 { 4999 igb_clean_rx_ring(rx_ring); 5000 5001 rx_ring->xdp_prog = NULL; 5002 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 5003 if (rx_ring->xsk_pool) { 5004 vfree(rx_ring->rx_buffer_info_zc); 5005 rx_ring->rx_buffer_info_zc = NULL; 5006 } else { 5007 vfree(rx_ring->rx_buffer_info); 5008 rx_ring->rx_buffer_info = NULL; 5009 } 5010 5011 /* if not set, then don't free */ 5012 if (!rx_ring->desc) 5013 return; 5014 5015 dma_free_coherent(rx_ring->dev, rx_ring->size, 5016 rx_ring->desc, rx_ring->dma); 5017 5018 rx_ring->desc = NULL; 5019 } 5020 5021 /** 5022 * igb_free_all_rx_resources - Free Rx Resources for All Queues 5023 * @adapter: board private structure 5024 * 5025 * Free all receive software resources 5026 **/ 5027 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 5028 { 5029 int i; 5030 5031 for (i = 0; i < adapter->num_rx_queues; i++) 5032 if (adapter->rx_ring[i]) 5033 igb_free_rx_resources(adapter->rx_ring[i]); 5034 } 5035 5036 /** 5037 * igb_clean_rx_ring - Free Rx Buffers per Queue 5038 * @rx_ring: ring to free buffers from 5039 **/ 5040 void igb_clean_rx_ring(struct igb_ring *rx_ring) 5041 { 5042 u16 i = rx_ring->next_to_clean; 5043 5044 dev_kfree_skb(rx_ring->skb); 5045 rx_ring->skb = NULL; 5046 5047 if (rx_ring->xsk_pool) { 5048 igb_clean_rx_ring_zc(rx_ring); 5049 goto skip_for_xsk; 5050 } 5051 5052 /* Free all the Rx ring sk_buffs */ 5053 while (i != rx_ring->next_to_alloc) { 5054 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 5055 5056 /* Invalidate cache lines that may have been written to by 5057 * device so that we avoid corrupting memory. 5058 */ 5059 dma_sync_single_range_for_cpu(rx_ring->dev, 5060 buffer_info->dma, 5061 buffer_info->page_offset, 5062 igb_rx_bufsz(rx_ring), 5063 DMA_FROM_DEVICE); 5064 5065 /* free resources associated with mapping */ 5066 dma_unmap_page_attrs(rx_ring->dev, 5067 buffer_info->dma, 5068 igb_rx_pg_size(rx_ring), 5069 DMA_FROM_DEVICE, 5070 IGB_RX_DMA_ATTR); 5071 __page_frag_cache_drain(buffer_info->page, 5072 buffer_info->pagecnt_bias); 5073 5074 i++; 5075 if (i == rx_ring->count) 5076 i = 0; 5077 } 5078 5079 skip_for_xsk: 5080 rx_ring->next_to_alloc = 0; 5081 rx_ring->next_to_clean = 0; 5082 rx_ring->next_to_use = 0; 5083 } 5084 5085 /** 5086 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 5087 * @adapter: board private structure 5088 **/ 5089 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 5090 { 5091 int i; 5092 5093 for (i = 0; i < adapter->num_rx_queues; i++) 5094 if (adapter->rx_ring[i]) 5095 igb_clean_rx_ring(adapter->rx_ring[i]); 5096 } 5097 5098 /** 5099 * igb_set_mac - Change the Ethernet Address of the NIC 5100 * @netdev: network interface device structure 5101 * @p: pointer to an address structure 5102 * 5103 * Returns 0 on success, negative on failure 5104 **/ 5105 static int igb_set_mac(struct net_device *netdev, void *p) 5106 { 5107 struct igb_adapter *adapter = netdev_priv(netdev); 5108 struct e1000_hw *hw = &adapter->hw; 5109 struct sockaddr *addr = p; 5110 5111 if (!is_valid_ether_addr(addr->sa_data)) 5112 return -EADDRNOTAVAIL; 5113 5114 eth_hw_addr_set(netdev, addr->sa_data); 5115 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 5116 5117 /* set the correct pool for the new PF MAC address in entry 0 */ 5118 igb_set_default_mac_filter(adapter); 5119 5120 return 0; 5121 } 5122 5123 /** 5124 * igb_write_mc_addr_list - write multicast addresses to MTA 5125 * @netdev: network interface device structure 5126 * 5127 * Writes multicast address list to the MTA hash table. 5128 * Returns: -ENOMEM on failure 5129 * 0 on no addresses written 5130 * X on writing X addresses to MTA 5131 **/ 5132 static int igb_write_mc_addr_list(struct net_device *netdev) 5133 { 5134 struct igb_adapter *adapter = netdev_priv(netdev); 5135 struct e1000_hw *hw = &adapter->hw; 5136 struct netdev_hw_addr *ha; 5137 u8 *mta_list; 5138 int i; 5139 5140 if (netdev_mc_empty(netdev)) { 5141 /* nothing to program, so clear mc list */ 5142 igb_update_mc_addr_list(hw, NULL, 0); 5143 igb_restore_vf_multicasts(adapter); 5144 return 0; 5145 } 5146 5147 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 5148 if (!mta_list) 5149 return -ENOMEM; 5150 5151 /* The shared function expects a packed array of only addresses. */ 5152 i = 0; 5153 netdev_for_each_mc_addr(ha, netdev) 5154 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 5155 5156 igb_update_mc_addr_list(hw, mta_list, i); 5157 kfree(mta_list); 5158 5159 return netdev_mc_count(netdev); 5160 } 5161 5162 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 5163 { 5164 struct e1000_hw *hw = &adapter->hw; 5165 u32 i, pf_id; 5166 5167 switch (hw->mac.type) { 5168 case e1000_i210: 5169 case e1000_i211: 5170 case e1000_i350: 5171 /* VLAN filtering needed for VLAN prio filter */ 5172 if (adapter->netdev->features & NETIF_F_NTUPLE) 5173 break; 5174 fallthrough; 5175 case e1000_82576: 5176 case e1000_82580: 5177 case e1000_i354: 5178 /* VLAN filtering needed for pool filtering */ 5179 if (adapter->vfs_allocated_count) 5180 break; 5181 fallthrough; 5182 default: 5183 return 1; 5184 } 5185 5186 /* We are already in VLAN promisc, nothing to do */ 5187 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 5188 return 0; 5189 5190 if (!adapter->vfs_allocated_count) 5191 goto set_vfta; 5192 5193 /* Add PF to all active pools */ 5194 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5195 5196 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5197 u32 vlvf = rd32(E1000_VLVF(i)); 5198 5199 vlvf |= BIT(pf_id); 5200 wr32(E1000_VLVF(i), vlvf); 5201 } 5202 5203 set_vfta: 5204 /* Set all bits in the VLAN filter table array */ 5205 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 5206 hw->mac.ops.write_vfta(hw, i, ~0U); 5207 5208 /* Set flag so we don't redo unnecessary work */ 5209 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 5210 5211 return 0; 5212 } 5213 5214 #define VFTA_BLOCK_SIZE 8 5215 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 5216 { 5217 struct e1000_hw *hw = &adapter->hw; 5218 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 5219 u32 vid_start = vfta_offset * 32; 5220 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 5221 u32 i, vid, word, bits, pf_id; 5222 5223 /* guarantee that we don't scrub out management VLAN */ 5224 vid = adapter->mng_vlan_id; 5225 if (vid >= vid_start && vid < vid_end) 5226 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5227 5228 if (!adapter->vfs_allocated_count) 5229 goto set_vfta; 5230 5231 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5232 5233 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5234 u32 vlvf = rd32(E1000_VLVF(i)); 5235 5236 /* pull VLAN ID from VLVF */ 5237 vid = vlvf & VLAN_VID_MASK; 5238 5239 /* only concern ourselves with a certain range */ 5240 if (vid < vid_start || vid >= vid_end) 5241 continue; 5242 5243 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 5244 /* record VLAN ID in VFTA */ 5245 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5246 5247 /* if PF is part of this then continue */ 5248 if (test_bit(vid, adapter->active_vlans)) 5249 continue; 5250 } 5251 5252 /* remove PF from the pool */ 5253 bits = ~BIT(pf_id); 5254 bits &= rd32(E1000_VLVF(i)); 5255 wr32(E1000_VLVF(i), bits); 5256 } 5257 5258 set_vfta: 5259 /* extract values from active_vlans and write back to VFTA */ 5260 for (i = VFTA_BLOCK_SIZE; i--;) { 5261 vid = (vfta_offset + i) * 32; 5262 word = vid / BITS_PER_LONG; 5263 bits = vid % BITS_PER_LONG; 5264 5265 vfta[i] |= adapter->active_vlans[word] >> bits; 5266 5267 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 5268 } 5269 } 5270 5271 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 5272 { 5273 u32 i; 5274 5275 /* We are not in VLAN promisc, nothing to do */ 5276 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 5277 return; 5278 5279 /* Set flag so we don't redo unnecessary work */ 5280 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 5281 5282 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 5283 igb_scrub_vfta(adapter, i); 5284 } 5285 5286 /** 5287 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 5288 * @netdev: network interface device structure 5289 * 5290 * The set_rx_mode entry point is called whenever the unicast or multicast 5291 * address lists or the network interface flags are updated. This routine is 5292 * responsible for configuring the hardware for proper unicast, multicast, 5293 * promiscuous mode, and all-multi behavior. 5294 **/ 5295 static void igb_set_rx_mode(struct net_device *netdev) 5296 { 5297 struct igb_adapter *adapter = netdev_priv(netdev); 5298 struct e1000_hw *hw = &adapter->hw; 5299 unsigned int vfn = adapter->vfs_allocated_count; 5300 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 5301 int count; 5302 5303 /* Check for Promiscuous and All Multicast modes */ 5304 if (netdev->flags & IFF_PROMISC) { 5305 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5306 vmolr |= E1000_VMOLR_MPME; 5307 5308 /* enable use of UTA filter to force packets to default pool */ 5309 if (hw->mac.type == e1000_82576) 5310 vmolr |= E1000_VMOLR_ROPE; 5311 } else { 5312 if (netdev->flags & IFF_ALLMULTI) { 5313 rctl |= E1000_RCTL_MPE; 5314 vmolr |= E1000_VMOLR_MPME; 5315 } else { 5316 /* Write addresses to the MTA, if the attempt fails 5317 * then we should just turn on promiscuous mode so 5318 * that we can at least receive multicast traffic 5319 */ 5320 count = igb_write_mc_addr_list(netdev); 5321 if (count < 0) { 5322 rctl |= E1000_RCTL_MPE; 5323 vmolr |= E1000_VMOLR_MPME; 5324 } else if (count) { 5325 vmolr |= E1000_VMOLR_ROMPE; 5326 } 5327 } 5328 } 5329 5330 /* Write addresses to available RAR registers, if there is not 5331 * sufficient space to store all the addresses then enable 5332 * unicast promiscuous mode 5333 */ 5334 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5335 rctl |= E1000_RCTL_UPE; 5336 vmolr |= E1000_VMOLR_ROPE; 5337 } 5338 5339 /* enable VLAN filtering by default */ 5340 rctl |= E1000_RCTL_VFE; 5341 5342 /* disable VLAN filtering for modes that require it */ 5343 if ((netdev->flags & IFF_PROMISC) || 5344 (netdev->features & NETIF_F_RXALL)) { 5345 /* if we fail to set all rules then just clear VFE */ 5346 if (igb_vlan_promisc_enable(adapter)) 5347 rctl &= ~E1000_RCTL_VFE; 5348 } else { 5349 igb_vlan_promisc_disable(adapter); 5350 } 5351 5352 /* update state of unicast, multicast, and VLAN filtering modes */ 5353 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5354 E1000_RCTL_VFE); 5355 wr32(E1000_RCTL, rctl); 5356 5357 #if (PAGE_SIZE < 8192) 5358 if (!adapter->vfs_allocated_count) { 5359 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5360 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5361 } 5362 #endif 5363 wr32(E1000_RLPML, rlpml); 5364 5365 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5366 * the VMOLR to enable the appropriate modes. Without this workaround 5367 * we will have issues with VLAN tag stripping not being done for frames 5368 * that are only arriving because we are the default pool 5369 */ 5370 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5371 return; 5372 5373 /* set UTA to appropriate mode */ 5374 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5375 5376 vmolr |= rd32(E1000_VMOLR(vfn)) & 5377 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5378 5379 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5380 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5381 #if (PAGE_SIZE < 8192) 5382 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5383 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5384 else 5385 #endif 5386 vmolr |= MAX_JUMBO_FRAME_SIZE; 5387 vmolr |= E1000_VMOLR_LPE; 5388 5389 wr32(E1000_VMOLR(vfn), vmolr); 5390 5391 igb_restore_vf_multicasts(adapter); 5392 } 5393 5394 static void igb_check_wvbr(struct igb_adapter *adapter) 5395 { 5396 struct e1000_hw *hw = &adapter->hw; 5397 u32 wvbr = 0; 5398 5399 switch (hw->mac.type) { 5400 case e1000_82576: 5401 case e1000_i350: 5402 wvbr = rd32(E1000_WVBR); 5403 if (!wvbr) 5404 return; 5405 break; 5406 default: 5407 break; 5408 } 5409 5410 adapter->wvbr |= wvbr; 5411 } 5412 5413 #define IGB_STAGGERED_QUEUE_OFFSET 8 5414 5415 static void igb_spoof_check(struct igb_adapter *adapter) 5416 { 5417 int j; 5418 5419 if (!adapter->wvbr) 5420 return; 5421 5422 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5423 if (adapter->wvbr & BIT(j) || 5424 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5425 dev_warn(&adapter->pdev->dev, 5426 "Spoof event(s) detected on VF %d\n", j); 5427 adapter->wvbr &= 5428 ~(BIT(j) | 5429 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5430 } 5431 } 5432 } 5433 5434 /* Need to wait a few seconds after link up to get diagnostic information from 5435 * the phy 5436 */ 5437 static void igb_update_phy_info(struct timer_list *t) 5438 { 5439 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5440 igb_get_phy_info(&adapter->hw); 5441 } 5442 5443 /** 5444 * igb_has_link - check shared code for link and determine up/down 5445 * @adapter: pointer to driver private info 5446 **/ 5447 bool igb_has_link(struct igb_adapter *adapter) 5448 { 5449 struct e1000_hw *hw = &adapter->hw; 5450 bool link_active = false; 5451 5452 /* get_link_status is set on LSC (link status) interrupt or 5453 * rx sequence error interrupt. get_link_status will stay 5454 * false until the e1000_check_for_link establishes link 5455 * for copper adapters ONLY 5456 */ 5457 switch (hw->phy.media_type) { 5458 case e1000_media_type_copper: 5459 if (!hw->mac.get_link_status) 5460 return true; 5461 fallthrough; 5462 case e1000_media_type_internal_serdes: 5463 hw->mac.ops.check_for_link(hw); 5464 link_active = !hw->mac.get_link_status; 5465 break; 5466 default: 5467 case e1000_media_type_unknown: 5468 break; 5469 } 5470 5471 if (((hw->mac.type == e1000_i210) || 5472 (hw->mac.type == e1000_i211)) && 5473 (hw->phy.id == I210_I_PHY_ID)) { 5474 if (!netif_carrier_ok(adapter->netdev)) { 5475 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5476 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5477 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5478 adapter->link_check_timeout = jiffies; 5479 } 5480 } 5481 5482 return link_active; 5483 } 5484 5485 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5486 { 5487 bool ret = false; 5488 u32 ctrl_ext, thstat; 5489 5490 /* check for thermal sensor event on i350 copper only */ 5491 if (hw->mac.type == e1000_i350) { 5492 thstat = rd32(E1000_THSTAT); 5493 ctrl_ext = rd32(E1000_CTRL_EXT); 5494 5495 if ((hw->phy.media_type == e1000_media_type_copper) && 5496 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5497 ret = !!(thstat & event); 5498 } 5499 5500 return ret; 5501 } 5502 5503 /** 5504 * igb_check_lvmmc - check for malformed packets received 5505 * and indicated in LVMMC register 5506 * @adapter: pointer to adapter 5507 **/ 5508 static void igb_check_lvmmc(struct igb_adapter *adapter) 5509 { 5510 struct e1000_hw *hw = &adapter->hw; 5511 u32 lvmmc; 5512 5513 lvmmc = rd32(E1000_LVMMC); 5514 if (lvmmc) { 5515 if (unlikely(net_ratelimit())) { 5516 netdev_warn(adapter->netdev, 5517 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5518 lvmmc); 5519 } 5520 } 5521 } 5522 5523 /** 5524 * igb_watchdog - Timer Call-back 5525 * @t: pointer to timer_list containing our private info pointer 5526 **/ 5527 static void igb_watchdog(struct timer_list *t) 5528 { 5529 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5530 /* Do the rest outside of interrupt context */ 5531 schedule_work(&adapter->watchdog_task); 5532 } 5533 5534 static void igb_watchdog_task(struct work_struct *work) 5535 { 5536 struct igb_adapter *adapter = container_of(work, 5537 struct igb_adapter, 5538 watchdog_task); 5539 struct e1000_hw *hw = &adapter->hw; 5540 struct e1000_phy_info *phy = &hw->phy; 5541 struct net_device *netdev = adapter->netdev; 5542 u32 link; 5543 int i; 5544 u32 connsw; 5545 u16 phy_data, retry_count = 20; 5546 5547 link = igb_has_link(adapter); 5548 5549 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5550 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5551 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5552 else 5553 link = false; 5554 } 5555 5556 /* Force link down if we have fiber to swap to */ 5557 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5558 if (hw->phy.media_type == e1000_media_type_copper) { 5559 connsw = rd32(E1000_CONNSW); 5560 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5561 link = 0; 5562 } 5563 } 5564 if (link) { 5565 /* Perform a reset if the media type changed. */ 5566 if (hw->dev_spec._82575.media_changed) { 5567 hw->dev_spec._82575.media_changed = false; 5568 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5569 igb_reset(adapter); 5570 } 5571 /* Cancel scheduled suspend requests. */ 5572 pm_runtime_resume(netdev->dev.parent); 5573 5574 if (!netif_carrier_ok(netdev)) { 5575 u32 ctrl; 5576 5577 hw->mac.ops.get_speed_and_duplex(hw, 5578 &adapter->link_speed, 5579 &adapter->link_duplex); 5580 5581 ctrl = rd32(E1000_CTRL); 5582 /* Links status message must follow this format */ 5583 netdev_info(netdev, 5584 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5585 netdev->name, 5586 adapter->link_speed, 5587 adapter->link_duplex == FULL_DUPLEX ? 5588 "Full" : "Half", 5589 (ctrl & E1000_CTRL_TFCE) && 5590 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5591 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5592 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5593 5594 /* disable EEE if enabled */ 5595 if ((adapter->flags & IGB_FLAG_EEE) && 5596 (adapter->link_duplex == HALF_DUPLEX)) { 5597 dev_info(&adapter->pdev->dev, 5598 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5599 adapter->hw.dev_spec._82575.eee_disable = true; 5600 adapter->flags &= ~IGB_FLAG_EEE; 5601 } 5602 5603 /* check if SmartSpeed worked */ 5604 igb_check_downshift(hw); 5605 if (phy->speed_downgraded) 5606 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5607 5608 /* check for thermal sensor event */ 5609 if (igb_thermal_sensor_event(hw, 5610 E1000_THSTAT_LINK_THROTTLE)) 5611 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5612 5613 /* adjust timeout factor according to speed/duplex */ 5614 adapter->tx_timeout_factor = 1; 5615 switch (adapter->link_speed) { 5616 case SPEED_10: 5617 adapter->tx_timeout_factor = 14; 5618 break; 5619 case SPEED_100: 5620 /* maybe add some timeout factor ? */ 5621 break; 5622 } 5623 5624 if (adapter->link_speed != SPEED_1000 || 5625 !hw->phy.ops.read_reg) 5626 goto no_wait; 5627 5628 /* wait for Remote receiver status OK */ 5629 retry_read_status: 5630 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5631 &phy_data)) { 5632 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5633 retry_count) { 5634 msleep(100); 5635 retry_count--; 5636 goto retry_read_status; 5637 } else if (!retry_count) { 5638 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5639 } 5640 } else { 5641 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5642 } 5643 no_wait: 5644 netif_carrier_on(netdev); 5645 5646 igb_ping_all_vfs(adapter); 5647 igb_check_vf_rate_limit(adapter); 5648 5649 /* link state has changed, schedule phy info update */ 5650 if (!test_bit(__IGB_DOWN, &adapter->state)) 5651 mod_timer(&adapter->phy_info_timer, 5652 round_jiffies(jiffies + 2 * HZ)); 5653 } 5654 } else { 5655 if (netif_carrier_ok(netdev)) { 5656 adapter->link_speed = 0; 5657 adapter->link_duplex = 0; 5658 5659 /* check for thermal sensor event */ 5660 if (igb_thermal_sensor_event(hw, 5661 E1000_THSTAT_PWR_DOWN)) { 5662 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5663 } 5664 5665 /* Links status message must follow this format */ 5666 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5667 netdev->name); 5668 netif_carrier_off(netdev); 5669 5670 igb_ping_all_vfs(adapter); 5671 5672 /* link state has changed, schedule phy info update */ 5673 if (!test_bit(__IGB_DOWN, &adapter->state)) 5674 mod_timer(&adapter->phy_info_timer, 5675 round_jiffies(jiffies + 2 * HZ)); 5676 5677 /* link is down, time to check for alternate media */ 5678 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5679 igb_check_swap_media(adapter); 5680 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5681 schedule_work(&adapter->reset_task); 5682 /* return immediately */ 5683 return; 5684 } 5685 } 5686 pm_schedule_suspend(netdev->dev.parent, 5687 MSEC_PER_SEC * 5); 5688 5689 /* also check for alternate media here */ 5690 } else if (!netif_carrier_ok(netdev) && 5691 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5692 igb_check_swap_media(adapter); 5693 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5694 schedule_work(&adapter->reset_task); 5695 /* return immediately */ 5696 return; 5697 } 5698 } 5699 } 5700 5701 spin_lock(&adapter->stats64_lock); 5702 igb_update_stats(adapter); 5703 spin_unlock(&adapter->stats64_lock); 5704 5705 for (i = 0; i < adapter->num_tx_queues; i++) { 5706 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5707 if (!netif_carrier_ok(netdev)) { 5708 /* We've lost link, so the controller stops DMA, 5709 * but we've got queued Tx work that's never going 5710 * to get done, so reset controller to flush Tx. 5711 * (Do the reset outside of interrupt context). 5712 */ 5713 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5714 adapter->tx_timeout_count++; 5715 schedule_work(&adapter->reset_task); 5716 /* return immediately since reset is imminent */ 5717 return; 5718 } 5719 } 5720 5721 /* Force detection of hung controller every watchdog period */ 5722 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5723 } 5724 5725 /* Cause software interrupt to ensure Rx ring is cleaned */ 5726 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5727 u32 eics = 0; 5728 5729 for (i = 0; i < adapter->num_q_vectors; i++) 5730 eics |= adapter->q_vector[i]->eims_value; 5731 wr32(E1000_EICS, eics); 5732 } else { 5733 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5734 } 5735 5736 igb_spoof_check(adapter); 5737 igb_ptp_rx_hang(adapter); 5738 igb_ptp_tx_hang(adapter); 5739 5740 /* Check LVMMC register on i350/i354 only */ 5741 if ((adapter->hw.mac.type == e1000_i350) || 5742 (adapter->hw.mac.type == e1000_i354)) 5743 igb_check_lvmmc(adapter); 5744 5745 /* Reset the timer */ 5746 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5747 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5748 mod_timer(&adapter->watchdog_timer, 5749 round_jiffies(jiffies + HZ)); 5750 else 5751 mod_timer(&adapter->watchdog_timer, 5752 round_jiffies(jiffies + 2 * HZ)); 5753 } 5754 } 5755 5756 enum latency_range { 5757 lowest_latency = 0, 5758 low_latency = 1, 5759 bulk_latency = 2, 5760 latency_invalid = 255 5761 }; 5762 5763 /** 5764 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5765 * @q_vector: pointer to q_vector 5766 * 5767 * Stores a new ITR value based on strictly on packet size. This 5768 * algorithm is less sophisticated than that used in igb_update_itr, 5769 * due to the difficulty of synchronizing statistics across multiple 5770 * receive rings. The divisors and thresholds used by this function 5771 * were determined based on theoretical maximum wire speed and testing 5772 * data, in order to minimize response time while increasing bulk 5773 * throughput. 5774 * This functionality is controlled by ethtool's coalescing settings. 5775 * NOTE: This function is called only when operating in a multiqueue 5776 * receive environment. 5777 **/ 5778 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5779 { 5780 int new_val = q_vector->itr_val; 5781 int avg_wire_size = 0; 5782 struct igb_adapter *adapter = q_vector->adapter; 5783 unsigned int packets; 5784 5785 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5786 * ints/sec - ITR timer value of 120 ticks. 5787 */ 5788 if (adapter->link_speed != SPEED_1000) { 5789 new_val = IGB_4K_ITR; 5790 goto set_itr_val; 5791 } 5792 5793 packets = q_vector->rx.total_packets; 5794 if (packets) 5795 avg_wire_size = q_vector->rx.total_bytes / packets; 5796 5797 packets = q_vector->tx.total_packets; 5798 if (packets) 5799 avg_wire_size = max_t(u32, avg_wire_size, 5800 q_vector->tx.total_bytes / packets); 5801 5802 /* if avg_wire_size isn't set no work was done */ 5803 if (!avg_wire_size) 5804 goto clear_counts; 5805 5806 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5807 avg_wire_size += 24; 5808 5809 /* Don't starve jumbo frames */ 5810 avg_wire_size = min(avg_wire_size, 3000); 5811 5812 /* Give a little boost to mid-size frames */ 5813 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5814 new_val = avg_wire_size / 3; 5815 else 5816 new_val = avg_wire_size / 2; 5817 5818 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5819 if (new_val < IGB_20K_ITR && 5820 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5821 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5822 new_val = IGB_20K_ITR; 5823 5824 set_itr_val: 5825 if (new_val != q_vector->itr_val) { 5826 q_vector->itr_val = new_val; 5827 q_vector->set_itr = 1; 5828 } 5829 clear_counts: 5830 q_vector->rx.total_bytes = 0; 5831 q_vector->rx.total_packets = 0; 5832 q_vector->tx.total_bytes = 0; 5833 q_vector->tx.total_packets = 0; 5834 } 5835 5836 /** 5837 * igb_update_itr - update the dynamic ITR value based on statistics 5838 * @q_vector: pointer to q_vector 5839 * @ring_container: ring info to update the itr for 5840 * 5841 * Stores a new ITR value based on packets and byte 5842 * counts during the last interrupt. The advantage of per interrupt 5843 * computation is faster updates and more accurate ITR for the current 5844 * traffic pattern. Constants in this function were computed 5845 * based on theoretical maximum wire speed and thresholds were set based 5846 * on testing data as well as attempting to minimize response time 5847 * while increasing bulk throughput. 5848 * This functionality is controlled by ethtool's coalescing settings. 5849 * NOTE: These calculations are only valid when operating in a single- 5850 * queue environment. 5851 **/ 5852 static void igb_update_itr(struct igb_q_vector *q_vector, 5853 struct igb_ring_container *ring_container) 5854 { 5855 unsigned int packets = ring_container->total_packets; 5856 unsigned int bytes = ring_container->total_bytes; 5857 u8 itrval = ring_container->itr; 5858 5859 /* no packets, exit with status unchanged */ 5860 if (packets == 0) 5861 return; 5862 5863 switch (itrval) { 5864 case lowest_latency: 5865 /* handle TSO and jumbo frames */ 5866 if (bytes/packets > 8000) 5867 itrval = bulk_latency; 5868 else if ((packets < 5) && (bytes > 512)) 5869 itrval = low_latency; 5870 break; 5871 case low_latency: /* 50 usec aka 20000 ints/s */ 5872 if (bytes > 10000) { 5873 /* this if handles the TSO accounting */ 5874 if (bytes/packets > 8000) 5875 itrval = bulk_latency; 5876 else if ((packets < 10) || ((bytes/packets) > 1200)) 5877 itrval = bulk_latency; 5878 else if ((packets > 35)) 5879 itrval = lowest_latency; 5880 } else if (bytes/packets > 2000) { 5881 itrval = bulk_latency; 5882 } else if (packets <= 2 && bytes < 512) { 5883 itrval = lowest_latency; 5884 } 5885 break; 5886 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5887 if (bytes > 25000) { 5888 if (packets > 35) 5889 itrval = low_latency; 5890 } else if (bytes < 1500) { 5891 itrval = low_latency; 5892 } 5893 break; 5894 } 5895 5896 /* clear work counters since we have the values we need */ 5897 ring_container->total_bytes = 0; 5898 ring_container->total_packets = 0; 5899 5900 /* write updated itr to ring container */ 5901 ring_container->itr = itrval; 5902 } 5903 5904 static void igb_set_itr(struct igb_q_vector *q_vector) 5905 { 5906 struct igb_adapter *adapter = q_vector->adapter; 5907 u32 new_itr = q_vector->itr_val; 5908 u8 current_itr = 0; 5909 5910 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5911 if (adapter->link_speed != SPEED_1000) { 5912 current_itr = 0; 5913 new_itr = IGB_4K_ITR; 5914 goto set_itr_now; 5915 } 5916 5917 igb_update_itr(q_vector, &q_vector->tx); 5918 igb_update_itr(q_vector, &q_vector->rx); 5919 5920 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5921 5922 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5923 if (current_itr == lowest_latency && 5924 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5925 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5926 current_itr = low_latency; 5927 5928 switch (current_itr) { 5929 /* counts and packets in update_itr are dependent on these numbers */ 5930 case lowest_latency: 5931 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5932 break; 5933 case low_latency: 5934 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5935 break; 5936 case bulk_latency: 5937 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5938 break; 5939 default: 5940 break; 5941 } 5942 5943 set_itr_now: 5944 if (new_itr != q_vector->itr_val) { 5945 /* this attempts to bias the interrupt rate towards Bulk 5946 * by adding intermediate steps when interrupt rate is 5947 * increasing 5948 */ 5949 new_itr = new_itr > q_vector->itr_val ? 5950 max((new_itr * q_vector->itr_val) / 5951 (new_itr + (q_vector->itr_val >> 2)), 5952 new_itr) : new_itr; 5953 /* Don't write the value here; it resets the adapter's 5954 * internal timer, and causes us to delay far longer than 5955 * we should between interrupts. Instead, we write the ITR 5956 * value at the beginning of the next interrupt so the timing 5957 * ends up being correct. 5958 */ 5959 q_vector->itr_val = new_itr; 5960 q_vector->set_itr = 1; 5961 } 5962 } 5963 5964 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 5965 struct igb_tx_buffer *first, 5966 u32 vlan_macip_lens, u32 type_tucmd, 5967 u32 mss_l4len_idx) 5968 { 5969 struct e1000_adv_tx_context_desc *context_desc; 5970 u16 i = tx_ring->next_to_use; 5971 struct timespec64 ts; 5972 5973 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5974 5975 i++; 5976 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 5977 5978 /* set bits to identify this as an advanced context descriptor */ 5979 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 5980 5981 /* For 82575, context index must be unique per ring. */ 5982 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5983 mss_l4len_idx |= tx_ring->reg_idx << 4; 5984 5985 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5986 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5987 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5988 5989 /* We assume there is always a valid tx time available. Invalid times 5990 * should have been handled by the upper layers. 5991 */ 5992 if (tx_ring->launchtime_enable) { 5993 ts = ktime_to_timespec64(first->skb->tstamp); 5994 skb_txtime_consumed(first->skb); 5995 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 5996 } else { 5997 context_desc->seqnum_seed = 0; 5998 } 5999 } 6000 6001 static int igb_tso(struct igb_ring *tx_ring, 6002 struct igb_tx_buffer *first, 6003 u8 *hdr_len) 6004 { 6005 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 6006 struct sk_buff *skb = first->skb; 6007 union { 6008 struct iphdr *v4; 6009 struct ipv6hdr *v6; 6010 unsigned char *hdr; 6011 } ip; 6012 union { 6013 struct tcphdr *tcp; 6014 struct udphdr *udp; 6015 unsigned char *hdr; 6016 } l4; 6017 u32 paylen, l4_offset; 6018 int err; 6019 6020 if (skb->ip_summed != CHECKSUM_PARTIAL) 6021 return 0; 6022 6023 if (!skb_is_gso(skb)) 6024 return 0; 6025 6026 err = skb_cow_head(skb, 0); 6027 if (err < 0) 6028 return err; 6029 6030 ip.hdr = skb_network_header(skb); 6031 l4.hdr = skb_checksum_start(skb); 6032 6033 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 6034 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 6035 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP; 6036 6037 /* initialize outer IP header fields */ 6038 if (ip.v4->version == 4) { 6039 unsigned char *csum_start = skb_checksum_start(skb); 6040 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 6041 6042 /* IP header will have to cancel out any data that 6043 * is not a part of the outer IP header 6044 */ 6045 ip.v4->check = csum_fold(csum_partial(trans_start, 6046 csum_start - trans_start, 6047 0)); 6048 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 6049 6050 ip.v4->tot_len = 0; 6051 first->tx_flags |= IGB_TX_FLAGS_TSO | 6052 IGB_TX_FLAGS_CSUM | 6053 IGB_TX_FLAGS_IPV4; 6054 } else { 6055 ip.v6->payload_len = 0; 6056 first->tx_flags |= IGB_TX_FLAGS_TSO | 6057 IGB_TX_FLAGS_CSUM; 6058 } 6059 6060 /* determine offset of inner transport header */ 6061 l4_offset = l4.hdr - skb->data; 6062 6063 /* remove payload length from inner checksum */ 6064 paylen = skb->len - l4_offset; 6065 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) { 6066 /* compute length of segmentation header */ 6067 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 6068 csum_replace_by_diff(&l4.tcp->check, 6069 (__force __wsum)htonl(paylen)); 6070 } else { 6071 /* compute length of segmentation header */ 6072 *hdr_len = sizeof(*l4.udp) + l4_offset; 6073 csum_replace_by_diff(&l4.udp->check, 6074 (__force __wsum)htonl(paylen)); 6075 } 6076 6077 /* update gso size and bytecount with header size */ 6078 first->gso_segs = skb_shinfo(skb)->gso_segs; 6079 first->bytecount += (first->gso_segs - 1) * *hdr_len; 6080 6081 /* MSS L4LEN IDX */ 6082 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 6083 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 6084 6085 /* VLAN MACLEN IPLEN */ 6086 vlan_macip_lens = l4.hdr - ip.hdr; 6087 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 6088 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6089 6090 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 6091 type_tucmd, mss_l4len_idx); 6092 6093 return 1; 6094 } 6095 6096 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 6097 { 6098 struct sk_buff *skb = first->skb; 6099 u32 vlan_macip_lens = 0; 6100 u32 type_tucmd = 0; 6101 6102 if (skb->ip_summed != CHECKSUM_PARTIAL) { 6103 csum_failed: 6104 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 6105 !tx_ring->launchtime_enable) 6106 return; 6107 goto no_csum; 6108 } 6109 6110 switch (skb->csum_offset) { 6111 case offsetof(struct tcphdr, check): 6112 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 6113 fallthrough; 6114 case offsetof(struct udphdr, check): 6115 break; 6116 case offsetof(struct sctphdr, checksum): 6117 /* validate that this is actually an SCTP request */ 6118 if (skb_csum_is_sctp(skb)) { 6119 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 6120 break; 6121 } 6122 fallthrough; 6123 default: 6124 skb_checksum_help(skb); 6125 goto csum_failed; 6126 } 6127 6128 /* update TX checksum flag */ 6129 first->tx_flags |= IGB_TX_FLAGS_CSUM; 6130 vlan_macip_lens = skb_checksum_start_offset(skb) - 6131 skb_network_offset(skb); 6132 no_csum: 6133 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 6134 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6135 6136 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 6137 } 6138 6139 #define IGB_SET_FLAG(_input, _flag, _result) \ 6140 ((_flag <= _result) ? \ 6141 ((u32)(_input & _flag) * (_result / _flag)) : \ 6142 ((u32)(_input & _flag) / (_flag / _result))) 6143 6144 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6145 { 6146 /* set type for advanced descriptor with frame checksum insertion */ 6147 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 6148 E1000_ADVTXD_DCMD_DEXT | 6149 E1000_ADVTXD_DCMD_IFCS; 6150 6151 /* set HW vlan bit if vlan is present */ 6152 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 6153 (E1000_ADVTXD_DCMD_VLE)); 6154 6155 /* set segmentation bits for TSO */ 6156 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 6157 (E1000_ADVTXD_DCMD_TSE)); 6158 6159 /* set timestamp bit if present */ 6160 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 6161 (E1000_ADVTXD_MAC_TSTAMP)); 6162 6163 /* insert frame checksum */ 6164 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 6165 6166 return cmd_type; 6167 } 6168 6169 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 6170 union e1000_adv_tx_desc *tx_desc, 6171 u32 tx_flags, unsigned int paylen) 6172 { 6173 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 6174 6175 /* 82575 requires a unique index per ring */ 6176 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6177 olinfo_status |= tx_ring->reg_idx << 4; 6178 6179 /* insert L4 checksum */ 6180 olinfo_status |= IGB_SET_FLAG(tx_flags, 6181 IGB_TX_FLAGS_CSUM, 6182 (E1000_TXD_POPTS_TXSM << 8)); 6183 6184 /* insert IPv4 checksum */ 6185 olinfo_status |= IGB_SET_FLAG(tx_flags, 6186 IGB_TX_FLAGS_IPV4, 6187 (E1000_TXD_POPTS_IXSM << 8)); 6188 6189 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6190 } 6191 6192 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6193 { 6194 struct net_device *netdev = tx_ring->netdev; 6195 6196 netif_stop_subqueue(netdev, tx_ring->queue_index); 6197 6198 /* Herbert's original patch had: 6199 * smp_mb__after_netif_stop_queue(); 6200 * but since that doesn't exist yet, just open code it. 6201 */ 6202 smp_mb(); 6203 6204 /* We need to check again in a case another CPU has just 6205 * made room available. 6206 */ 6207 if (igb_desc_unused(tx_ring) < size) 6208 return -EBUSY; 6209 6210 /* A reprieve! */ 6211 netif_wake_subqueue(netdev, tx_ring->queue_index); 6212 6213 u64_stats_update_begin(&tx_ring->tx_syncp2); 6214 tx_ring->tx_stats.restart_queue2++; 6215 u64_stats_update_end(&tx_ring->tx_syncp2); 6216 6217 return 0; 6218 } 6219 6220 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6221 { 6222 if (igb_desc_unused(tx_ring) >= size) 6223 return 0; 6224 return __igb_maybe_stop_tx(tx_ring, size); 6225 } 6226 6227 static int igb_tx_map(struct igb_ring *tx_ring, 6228 struct igb_tx_buffer *first, 6229 const u8 hdr_len) 6230 { 6231 struct sk_buff *skb = first->skb; 6232 struct igb_tx_buffer *tx_buffer; 6233 union e1000_adv_tx_desc *tx_desc; 6234 skb_frag_t *frag; 6235 dma_addr_t dma; 6236 unsigned int data_len, size; 6237 u32 tx_flags = first->tx_flags; 6238 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 6239 u16 i = tx_ring->next_to_use; 6240 6241 tx_desc = IGB_TX_DESC(tx_ring, i); 6242 6243 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 6244 6245 size = skb_headlen(skb); 6246 data_len = skb->data_len; 6247 6248 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6249 6250 tx_buffer = first; 6251 6252 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6253 if (dma_mapping_error(tx_ring->dev, dma)) 6254 goto dma_error; 6255 6256 /* record length, and DMA address */ 6257 dma_unmap_len_set(tx_buffer, len, size); 6258 dma_unmap_addr_set(tx_buffer, dma, dma); 6259 6260 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6261 6262 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 6263 tx_desc->read.cmd_type_len = 6264 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 6265 6266 i++; 6267 tx_desc++; 6268 if (i == tx_ring->count) { 6269 tx_desc = IGB_TX_DESC(tx_ring, 0); 6270 i = 0; 6271 } 6272 tx_desc->read.olinfo_status = 0; 6273 6274 dma += IGB_MAX_DATA_PER_TXD; 6275 size -= IGB_MAX_DATA_PER_TXD; 6276 6277 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6278 } 6279 6280 if (likely(!data_len)) 6281 break; 6282 6283 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6284 6285 i++; 6286 tx_desc++; 6287 if (i == tx_ring->count) { 6288 tx_desc = IGB_TX_DESC(tx_ring, 0); 6289 i = 0; 6290 } 6291 tx_desc->read.olinfo_status = 0; 6292 6293 size = skb_frag_size(frag); 6294 data_len -= size; 6295 6296 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6297 size, DMA_TO_DEVICE); 6298 6299 tx_buffer = &tx_ring->tx_buffer_info[i]; 6300 } 6301 6302 /* write last descriptor with RS and EOP bits */ 6303 cmd_type |= size | IGB_TXD_DCMD; 6304 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6305 6306 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6307 6308 /* set the timestamp */ 6309 first->time_stamp = jiffies; 6310 6311 skb_tx_timestamp(skb); 6312 6313 /* Force memory writes to complete before letting h/w know there 6314 * are new descriptors to fetch. (Only applicable for weak-ordered 6315 * memory model archs, such as IA-64). 6316 * 6317 * We also need this memory barrier to make certain all of the 6318 * status bits have been updated before next_to_watch is written. 6319 */ 6320 dma_wmb(); 6321 6322 /* set next_to_watch value indicating a packet is present */ 6323 first->next_to_watch = tx_desc; 6324 6325 i++; 6326 if (i == tx_ring->count) 6327 i = 0; 6328 6329 tx_ring->next_to_use = i; 6330 6331 /* Make sure there is space in the ring for the next send. */ 6332 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6333 6334 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6335 writel(i, tx_ring->tail); 6336 } 6337 return 0; 6338 6339 dma_error: 6340 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6341 tx_buffer = &tx_ring->tx_buffer_info[i]; 6342 6343 /* clear dma mappings for failed tx_buffer_info map */ 6344 while (tx_buffer != first) { 6345 if (dma_unmap_len(tx_buffer, len)) 6346 dma_unmap_page(tx_ring->dev, 6347 dma_unmap_addr(tx_buffer, dma), 6348 dma_unmap_len(tx_buffer, len), 6349 DMA_TO_DEVICE); 6350 dma_unmap_len_set(tx_buffer, len, 0); 6351 6352 if (i-- == 0) 6353 i += tx_ring->count; 6354 tx_buffer = &tx_ring->tx_buffer_info[i]; 6355 } 6356 6357 if (dma_unmap_len(tx_buffer, len)) 6358 dma_unmap_single(tx_ring->dev, 6359 dma_unmap_addr(tx_buffer, dma), 6360 dma_unmap_len(tx_buffer, len), 6361 DMA_TO_DEVICE); 6362 dma_unmap_len_set(tx_buffer, len, 0); 6363 6364 dev_kfree_skb_any(tx_buffer->skb); 6365 tx_buffer->skb = NULL; 6366 6367 tx_ring->next_to_use = i; 6368 6369 return -1; 6370 } 6371 6372 int igb_xmit_xdp_ring(struct igb_adapter *adapter, 6373 struct igb_ring *tx_ring, 6374 struct xdp_frame *xdpf) 6375 { 6376 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 6377 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 6378 u16 count, i, index = tx_ring->next_to_use; 6379 struct igb_tx_buffer *tx_head = &tx_ring->tx_buffer_info[index]; 6380 struct igb_tx_buffer *tx_buffer = tx_head; 6381 union e1000_adv_tx_desc *tx_desc = IGB_TX_DESC(tx_ring, index); 6382 u32 len = xdpf->len, cmd_type, olinfo_status; 6383 void *data = xdpf->data; 6384 6385 count = TXD_USE_COUNT(len); 6386 for (i = 0; i < nr_frags; i++) 6387 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i])); 6388 6389 if (igb_maybe_stop_tx(tx_ring, count + 3)) 6390 return IGB_XDP_CONSUMED; 6391 6392 i = 0; 6393 /* record the location of the first descriptor for this packet */ 6394 tx_head->bytecount = xdp_get_frame_len(xdpf); 6395 tx_head->type = IGB_TYPE_XDP; 6396 tx_head->gso_segs = 1; 6397 tx_head->xdpf = xdpf; 6398 6399 olinfo_status = tx_head->bytecount << E1000_ADVTXD_PAYLEN_SHIFT; 6400 /* 82575 requires a unique index per ring */ 6401 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6402 olinfo_status |= tx_ring->reg_idx << 4; 6403 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6404 6405 for (;;) { 6406 dma_addr_t dma; 6407 6408 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE); 6409 if (dma_mapping_error(tx_ring->dev, dma)) 6410 goto unmap; 6411 6412 /* record length, and DMA address */ 6413 dma_unmap_len_set(tx_buffer, len, len); 6414 dma_unmap_addr_set(tx_buffer, dma, dma); 6415 6416 /* put descriptor type bits */ 6417 cmd_type = E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_DEXT | 6418 E1000_ADVTXD_DCMD_IFCS | len; 6419 6420 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6421 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6422 6423 tx_buffer->protocol = 0; 6424 6425 if (++index == tx_ring->count) 6426 index = 0; 6427 6428 if (i == nr_frags) 6429 break; 6430 6431 tx_buffer = &tx_ring->tx_buffer_info[index]; 6432 tx_desc = IGB_TX_DESC(tx_ring, index); 6433 tx_desc->read.olinfo_status = 0; 6434 6435 data = skb_frag_address(&sinfo->frags[i]); 6436 len = skb_frag_size(&sinfo->frags[i]); 6437 i++; 6438 } 6439 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_TXD_DCMD); 6440 6441 netdev_tx_sent_queue(txring_txq(tx_ring), tx_head->bytecount); 6442 /* set the timestamp */ 6443 tx_head->time_stamp = jiffies; 6444 6445 /* Avoid any potential race with xdp_xmit and cleanup */ 6446 smp_wmb(); 6447 6448 /* set next_to_watch value indicating a packet is present */ 6449 tx_head->next_to_watch = tx_desc; 6450 tx_ring->next_to_use = index; 6451 6452 /* Make sure there is space in the ring for the next send. */ 6453 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6454 6455 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) 6456 writel(index, tx_ring->tail); 6457 6458 return IGB_XDP_TX; 6459 6460 unmap: 6461 for (;;) { 6462 tx_buffer = &tx_ring->tx_buffer_info[index]; 6463 if (dma_unmap_len(tx_buffer, len)) 6464 dma_unmap_page(tx_ring->dev, 6465 dma_unmap_addr(tx_buffer, dma), 6466 dma_unmap_len(tx_buffer, len), 6467 DMA_TO_DEVICE); 6468 dma_unmap_len_set(tx_buffer, len, 0); 6469 if (tx_buffer == tx_head) 6470 break; 6471 6472 if (!index) 6473 index += tx_ring->count; 6474 index--; 6475 } 6476 6477 return IGB_XDP_CONSUMED; 6478 } 6479 6480 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6481 struct igb_ring *tx_ring) 6482 { 6483 struct igb_tx_buffer *first; 6484 int tso; 6485 u32 tx_flags = 0; 6486 unsigned short f; 6487 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6488 __be16 protocol = vlan_get_protocol(skb); 6489 u8 hdr_len = 0; 6490 6491 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6492 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6493 * + 2 desc gap to keep tail from touching head, 6494 * + 1 desc for context descriptor, 6495 * otherwise try next time 6496 */ 6497 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6498 count += TXD_USE_COUNT(skb_frag_size( 6499 &skb_shinfo(skb)->frags[f])); 6500 6501 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6502 /* this is a hard error */ 6503 return NETDEV_TX_BUSY; 6504 } 6505 6506 if (unlikely(test_bit(IGB_RING_FLAG_TX_DISABLED, &tx_ring->flags))) 6507 return NETDEV_TX_BUSY; 6508 6509 /* record the location of the first descriptor for this packet */ 6510 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6511 first->type = IGB_TYPE_SKB; 6512 first->skb = skb; 6513 first->bytecount = skb->len; 6514 first->gso_segs = 1; 6515 6516 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6517 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6518 6519 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6520 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6521 &adapter->state)) { 6522 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6523 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6524 6525 adapter->ptp_tx_skb = skb_get(skb); 6526 adapter->ptp_tx_start = jiffies; 6527 if (adapter->hw.mac.type == e1000_82576) 6528 schedule_work(&adapter->ptp_tx_work); 6529 } else { 6530 adapter->tx_hwtstamp_skipped++; 6531 } 6532 } 6533 6534 if (skb_vlan_tag_present(skb)) { 6535 tx_flags |= IGB_TX_FLAGS_VLAN; 6536 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6537 } 6538 6539 /* record initial flags and protocol */ 6540 first->tx_flags = tx_flags; 6541 first->protocol = protocol; 6542 6543 tso = igb_tso(tx_ring, first, &hdr_len); 6544 if (tso < 0) 6545 goto out_drop; 6546 else if (!tso) 6547 igb_tx_csum(tx_ring, first); 6548 6549 if (igb_tx_map(tx_ring, first, hdr_len)) 6550 goto cleanup_tx_tstamp; 6551 6552 return NETDEV_TX_OK; 6553 6554 out_drop: 6555 dev_kfree_skb_any(first->skb); 6556 first->skb = NULL; 6557 cleanup_tx_tstamp: 6558 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6559 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6560 6561 dev_kfree_skb_any(adapter->ptp_tx_skb); 6562 adapter->ptp_tx_skb = NULL; 6563 if (adapter->hw.mac.type == e1000_82576) 6564 cancel_work_sync(&adapter->ptp_tx_work); 6565 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6566 } 6567 6568 return NETDEV_TX_OK; 6569 } 6570 6571 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6572 struct sk_buff *skb) 6573 { 6574 unsigned int r_idx = skb->queue_mapping; 6575 6576 if (r_idx >= adapter->num_tx_queues) 6577 r_idx = r_idx % adapter->num_tx_queues; 6578 6579 return adapter->tx_ring[r_idx]; 6580 } 6581 6582 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6583 struct net_device *netdev) 6584 { 6585 struct igb_adapter *adapter = netdev_priv(netdev); 6586 6587 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6588 * in order to meet this minimum size requirement. 6589 */ 6590 if (skb_put_padto(skb, 17)) 6591 return NETDEV_TX_OK; 6592 6593 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6594 } 6595 6596 /** 6597 * igb_tx_timeout - Respond to a Tx Hang 6598 * @netdev: network interface device structure 6599 * @txqueue: number of the Tx queue that hung (unused) 6600 **/ 6601 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6602 { 6603 struct igb_adapter *adapter = netdev_priv(netdev); 6604 struct e1000_hw *hw = &adapter->hw; 6605 6606 /* Do the reset outside of interrupt context */ 6607 adapter->tx_timeout_count++; 6608 6609 if (hw->mac.type >= e1000_82580) 6610 hw->dev_spec._82575.global_device_reset = true; 6611 6612 schedule_work(&adapter->reset_task); 6613 wr32(E1000_EICS, 6614 (adapter->eims_enable_mask & ~adapter->eims_other)); 6615 } 6616 6617 static void igb_reset_task(struct work_struct *work) 6618 { 6619 struct igb_adapter *adapter; 6620 adapter = container_of(work, struct igb_adapter, reset_task); 6621 6622 rtnl_lock(); 6623 /* If we're already down or resetting, just bail */ 6624 if (test_bit(__IGB_DOWN, &adapter->state) || 6625 test_bit(__IGB_RESETTING, &adapter->state)) { 6626 rtnl_unlock(); 6627 return; 6628 } 6629 6630 igb_dump(adapter); 6631 netdev_err(adapter->netdev, "Reset adapter\n"); 6632 igb_reinit_locked(adapter); 6633 rtnl_unlock(); 6634 } 6635 6636 /** 6637 * igb_get_stats64 - Get System Network Statistics 6638 * @netdev: network interface device structure 6639 * @stats: rtnl_link_stats64 pointer 6640 **/ 6641 static void igb_get_stats64(struct net_device *netdev, 6642 struct rtnl_link_stats64 *stats) 6643 { 6644 struct igb_adapter *adapter = netdev_priv(netdev); 6645 6646 spin_lock(&adapter->stats64_lock); 6647 igb_update_stats(adapter); 6648 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6649 spin_unlock(&adapter->stats64_lock); 6650 } 6651 6652 /** 6653 * igb_change_mtu - Change the Maximum Transfer Unit 6654 * @netdev: network interface device structure 6655 * @new_mtu: new value for maximum frame size 6656 * 6657 * Returns 0 on success, negative on failure 6658 **/ 6659 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6660 { 6661 struct igb_adapter *adapter = netdev_priv(netdev); 6662 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD; 6663 6664 if (igb_xdp_is_enabled(adapter)) { 6665 int i; 6666 6667 for (i = 0; i < adapter->num_rx_queues; i++) { 6668 struct igb_ring *ring = adapter->rx_ring[i]; 6669 6670 if (max_frame > igb_rx_bufsz(ring)) { 6671 netdev_warn(adapter->netdev, 6672 "Requested MTU size is not supported with XDP. Max frame size is %d\n", 6673 max_frame); 6674 return -EINVAL; 6675 } 6676 } 6677 } 6678 6679 /* adjust max frame to be at least the size of a standard frame */ 6680 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6681 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6682 6683 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6684 usleep_range(1000, 2000); 6685 6686 /* igb_down has a dependency on max_frame_size */ 6687 adapter->max_frame_size = max_frame; 6688 6689 if (netif_running(netdev)) 6690 igb_down(adapter); 6691 6692 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6693 netdev->mtu, new_mtu); 6694 WRITE_ONCE(netdev->mtu, new_mtu); 6695 6696 if (netif_running(netdev)) 6697 igb_up(adapter); 6698 else 6699 igb_reset(adapter); 6700 6701 clear_bit(__IGB_RESETTING, &adapter->state); 6702 6703 return 0; 6704 } 6705 6706 /** 6707 * igb_update_stats - Update the board statistics counters 6708 * @adapter: board private structure 6709 **/ 6710 void igb_update_stats(struct igb_adapter *adapter) 6711 { 6712 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6713 struct e1000_hw *hw = &adapter->hw; 6714 struct pci_dev *pdev = adapter->pdev; 6715 u32 reg, mpc; 6716 int i; 6717 u64 bytes, packets; 6718 unsigned int start; 6719 u64 _bytes, _packets; 6720 6721 /* Prevent stats update while adapter is being reset, or if the pci 6722 * connection is down. 6723 */ 6724 if (adapter->link_speed == 0) 6725 return; 6726 if (pci_channel_offline(pdev)) 6727 return; 6728 6729 bytes = 0; 6730 packets = 0; 6731 6732 rcu_read_lock(); 6733 for (i = 0; i < adapter->num_rx_queues; i++) { 6734 struct igb_ring *ring = adapter->rx_ring[i]; 6735 u32 rqdpc = rd32(E1000_RQDPC(i)); 6736 if (hw->mac.type >= e1000_i210) 6737 wr32(E1000_RQDPC(i), 0); 6738 6739 if (rqdpc) { 6740 ring->rx_stats.drops += rqdpc; 6741 net_stats->rx_fifo_errors += rqdpc; 6742 } 6743 6744 do { 6745 start = u64_stats_fetch_begin(&ring->rx_syncp); 6746 _bytes = ring->rx_stats.bytes; 6747 _packets = ring->rx_stats.packets; 6748 } while (u64_stats_fetch_retry(&ring->rx_syncp, start)); 6749 bytes += _bytes; 6750 packets += _packets; 6751 } 6752 6753 net_stats->rx_bytes = bytes; 6754 net_stats->rx_packets = packets; 6755 6756 bytes = 0; 6757 packets = 0; 6758 for (i = 0; i < adapter->num_tx_queues; i++) { 6759 struct igb_ring *ring = adapter->tx_ring[i]; 6760 do { 6761 start = u64_stats_fetch_begin(&ring->tx_syncp); 6762 _bytes = ring->tx_stats.bytes; 6763 _packets = ring->tx_stats.packets; 6764 } while (u64_stats_fetch_retry(&ring->tx_syncp, start)); 6765 bytes += _bytes; 6766 packets += _packets; 6767 } 6768 net_stats->tx_bytes = bytes; 6769 net_stats->tx_packets = packets; 6770 rcu_read_unlock(); 6771 6772 /* read stats registers */ 6773 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6774 adapter->stats.gprc += rd32(E1000_GPRC); 6775 adapter->stats.gorc += rd32(E1000_GORCL); 6776 rd32(E1000_GORCH); /* clear GORCL */ 6777 adapter->stats.bprc += rd32(E1000_BPRC); 6778 adapter->stats.mprc += rd32(E1000_MPRC); 6779 adapter->stats.roc += rd32(E1000_ROC); 6780 6781 adapter->stats.prc64 += rd32(E1000_PRC64); 6782 adapter->stats.prc127 += rd32(E1000_PRC127); 6783 adapter->stats.prc255 += rd32(E1000_PRC255); 6784 adapter->stats.prc511 += rd32(E1000_PRC511); 6785 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6786 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6787 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6788 adapter->stats.sec += rd32(E1000_SEC); 6789 6790 mpc = rd32(E1000_MPC); 6791 adapter->stats.mpc += mpc; 6792 net_stats->rx_fifo_errors += mpc; 6793 adapter->stats.scc += rd32(E1000_SCC); 6794 adapter->stats.ecol += rd32(E1000_ECOL); 6795 adapter->stats.mcc += rd32(E1000_MCC); 6796 adapter->stats.latecol += rd32(E1000_LATECOL); 6797 adapter->stats.dc += rd32(E1000_DC); 6798 adapter->stats.rlec += rd32(E1000_RLEC); 6799 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6800 adapter->stats.xontxc += rd32(E1000_XONTXC); 6801 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6802 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6803 adapter->stats.fcruc += rd32(E1000_FCRUC); 6804 adapter->stats.gptc += rd32(E1000_GPTC); 6805 adapter->stats.gotc += rd32(E1000_GOTCL); 6806 rd32(E1000_GOTCH); /* clear GOTCL */ 6807 adapter->stats.rnbc += rd32(E1000_RNBC); 6808 adapter->stats.ruc += rd32(E1000_RUC); 6809 adapter->stats.rfc += rd32(E1000_RFC); 6810 adapter->stats.rjc += rd32(E1000_RJC); 6811 adapter->stats.tor += rd32(E1000_TORH); 6812 adapter->stats.tot += rd32(E1000_TOTH); 6813 adapter->stats.tpr += rd32(E1000_TPR); 6814 6815 adapter->stats.ptc64 += rd32(E1000_PTC64); 6816 adapter->stats.ptc127 += rd32(E1000_PTC127); 6817 adapter->stats.ptc255 += rd32(E1000_PTC255); 6818 adapter->stats.ptc511 += rd32(E1000_PTC511); 6819 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6820 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6821 6822 adapter->stats.mptc += rd32(E1000_MPTC); 6823 adapter->stats.bptc += rd32(E1000_BPTC); 6824 6825 adapter->stats.tpt += rd32(E1000_TPT); 6826 adapter->stats.colc += rd32(E1000_COLC); 6827 6828 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6829 /* read internal phy specific stats */ 6830 reg = rd32(E1000_CTRL_EXT); 6831 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6832 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6833 6834 /* this stat has invalid values on i210/i211 */ 6835 if ((hw->mac.type != e1000_i210) && 6836 (hw->mac.type != e1000_i211)) 6837 adapter->stats.tncrs += rd32(E1000_TNCRS); 6838 } 6839 6840 adapter->stats.tsctc += rd32(E1000_TSCTC); 6841 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6842 6843 adapter->stats.iac += rd32(E1000_IAC); 6844 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6845 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6846 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6847 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6848 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6849 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6850 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6851 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6852 6853 /* Fill out the OS statistics structure */ 6854 net_stats->multicast = adapter->stats.mprc; 6855 net_stats->collisions = adapter->stats.colc; 6856 6857 /* Rx Errors */ 6858 6859 /* RLEC on some newer hardware can be incorrect so build 6860 * our own version based on RUC and ROC 6861 */ 6862 net_stats->rx_errors = adapter->stats.rxerrc + 6863 adapter->stats.crcerrs + adapter->stats.algnerrc + 6864 adapter->stats.ruc + adapter->stats.roc + 6865 adapter->stats.cexterr; 6866 net_stats->rx_length_errors = adapter->stats.ruc + 6867 adapter->stats.roc; 6868 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6869 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6870 net_stats->rx_missed_errors = adapter->stats.mpc; 6871 6872 /* Tx Errors */ 6873 net_stats->tx_errors = adapter->stats.ecol + 6874 adapter->stats.latecol; 6875 net_stats->tx_aborted_errors = adapter->stats.ecol; 6876 net_stats->tx_window_errors = adapter->stats.latecol; 6877 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6878 6879 /* Tx Dropped needs to be maintained elsewhere */ 6880 6881 /* Management Stats */ 6882 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6883 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6884 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6885 6886 /* OS2BMC Stats */ 6887 reg = rd32(E1000_MANC); 6888 if (reg & E1000_MANC_EN_BMC2OS) { 6889 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6890 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6891 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6892 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6893 } 6894 } 6895 6896 static void igb_perout(struct igb_adapter *adapter, int tsintr_tt) 6897 { 6898 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_PEROUT, tsintr_tt); 6899 struct e1000_hw *hw = &adapter->hw; 6900 struct timespec64 ts; 6901 u32 tsauxc; 6902 6903 if (pin < 0 || pin >= IGB_N_SDP) 6904 return; 6905 6906 spin_lock(&adapter->tmreg_lock); 6907 6908 if (hw->mac.type == e1000_82580 || 6909 hw->mac.type == e1000_i354 || 6910 hw->mac.type == e1000_i350) { 6911 s64 ns = timespec64_to_ns(&adapter->perout[tsintr_tt].period); 6912 u32 systiml, systimh, level_mask, level, rem; 6913 u64 systim, now; 6914 6915 /* read systim registers in sequence */ 6916 rd32(E1000_SYSTIMR); 6917 systiml = rd32(E1000_SYSTIML); 6918 systimh = rd32(E1000_SYSTIMH); 6919 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml); 6920 now = timecounter_cyc2time(&adapter->tc, systim); 6921 6922 if (pin < 2) { 6923 level_mask = (tsintr_tt == 1) ? 0x80000 : 0x40000; 6924 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0; 6925 } else { 6926 level_mask = (tsintr_tt == 1) ? 0x80 : 0x40; 6927 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0; 6928 } 6929 6930 div_u64_rem(now, ns, &rem); 6931 systim = systim + (ns - rem); 6932 6933 /* synchronize pin level with rising/falling edges */ 6934 div_u64_rem(now, ns << 1, &rem); 6935 if (rem < ns) { 6936 /* first half of period */ 6937 if (level == 0) { 6938 /* output is already low, skip this period */ 6939 systim += ns; 6940 pr_notice("igb: periodic output on %s missed falling edge\n", 6941 adapter->sdp_config[pin].name); 6942 } 6943 } else { 6944 /* second half of period */ 6945 if (level == 1) { 6946 /* output is already high, skip this period */ 6947 systim += ns; 6948 pr_notice("igb: periodic output on %s missed rising edge\n", 6949 adapter->sdp_config[pin].name); 6950 } 6951 } 6952 6953 /* for this chip family tv_sec is the upper part of the binary value, 6954 * so not seconds 6955 */ 6956 ts.tv_nsec = (u32)systim; 6957 ts.tv_sec = ((u32)(systim >> 32)) & 0xFF; 6958 } else { 6959 ts = timespec64_add(adapter->perout[tsintr_tt].start, 6960 adapter->perout[tsintr_tt].period); 6961 } 6962 6963 /* u32 conversion of tv_sec is safe until y2106 */ 6964 wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec); 6965 wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec); 6966 tsauxc = rd32(E1000_TSAUXC); 6967 tsauxc |= TSAUXC_EN_TT0; 6968 wr32(E1000_TSAUXC, tsauxc); 6969 adapter->perout[tsintr_tt].start = ts; 6970 6971 spin_unlock(&adapter->tmreg_lock); 6972 } 6973 6974 static void igb_extts(struct igb_adapter *adapter, int tsintr_tt) 6975 { 6976 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_EXTTS, tsintr_tt); 6977 int auxstmpl = (tsintr_tt == 1) ? E1000_AUXSTMPL1 : E1000_AUXSTMPL0; 6978 int auxstmph = (tsintr_tt == 1) ? E1000_AUXSTMPH1 : E1000_AUXSTMPH0; 6979 struct e1000_hw *hw = &adapter->hw; 6980 struct ptp_clock_event event; 6981 struct timespec64 ts; 6982 unsigned long flags; 6983 6984 if (pin < 0 || pin >= IGB_N_SDP) 6985 return; 6986 6987 if (hw->mac.type == e1000_82580 || 6988 hw->mac.type == e1000_i354 || 6989 hw->mac.type == e1000_i350) { 6990 u64 ns = rd32(auxstmpl); 6991 6992 ns += ((u64)(rd32(auxstmph) & 0xFF)) << 32; 6993 spin_lock_irqsave(&adapter->tmreg_lock, flags); 6994 ns = timecounter_cyc2time(&adapter->tc, ns); 6995 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 6996 ts = ns_to_timespec64(ns); 6997 } else { 6998 ts.tv_nsec = rd32(auxstmpl); 6999 ts.tv_sec = rd32(auxstmph); 7000 } 7001 7002 event.type = PTP_CLOCK_EXTTS; 7003 event.index = tsintr_tt; 7004 event.timestamp = ts.tv_sec * 1000000000ULL + ts.tv_nsec; 7005 ptp_clock_event(adapter->ptp_clock, &event); 7006 } 7007 7008 static void igb_tsync_interrupt(struct igb_adapter *adapter) 7009 { 7010 const u32 mask = (TSINTR_SYS_WRAP | E1000_TSICR_TXTS | 7011 TSINTR_TT0 | TSINTR_TT1 | 7012 TSINTR_AUTT0 | TSINTR_AUTT1); 7013 struct e1000_hw *hw = &adapter->hw; 7014 u32 tsicr = rd32(E1000_TSICR); 7015 struct ptp_clock_event event; 7016 7017 if (hw->mac.type == e1000_82580) { 7018 /* 82580 has a hardware bug that requires an explicit 7019 * write to clear the TimeSync interrupt cause. 7020 */ 7021 wr32(E1000_TSICR, tsicr & mask); 7022 } 7023 7024 if (tsicr & TSINTR_SYS_WRAP) { 7025 event.type = PTP_CLOCK_PPS; 7026 if (adapter->ptp_caps.pps) 7027 ptp_clock_event(adapter->ptp_clock, &event); 7028 } 7029 7030 if (tsicr & E1000_TSICR_TXTS) { 7031 /* retrieve hardware timestamp */ 7032 schedule_work(&adapter->ptp_tx_work); 7033 } 7034 7035 if (tsicr & TSINTR_TT0) 7036 igb_perout(adapter, 0); 7037 7038 if (tsicr & TSINTR_TT1) 7039 igb_perout(adapter, 1); 7040 7041 if (tsicr & TSINTR_AUTT0) 7042 igb_extts(adapter, 0); 7043 7044 if (tsicr & TSINTR_AUTT1) 7045 igb_extts(adapter, 1); 7046 } 7047 7048 static irqreturn_t igb_msix_other(int irq, void *data) 7049 { 7050 struct igb_adapter *adapter = data; 7051 struct e1000_hw *hw = &adapter->hw; 7052 u32 icr = rd32(E1000_ICR); 7053 /* reading ICR causes bit 31 of EICR to be cleared */ 7054 7055 if (icr & E1000_ICR_DRSTA) 7056 schedule_work(&adapter->reset_task); 7057 7058 if (icr & E1000_ICR_DOUTSYNC) { 7059 /* HW is reporting DMA is out of sync */ 7060 adapter->stats.doosync++; 7061 /* The DMA Out of Sync is also indication of a spoof event 7062 * in IOV mode. Check the Wrong VM Behavior register to 7063 * see if it is really a spoof event. 7064 */ 7065 igb_check_wvbr(adapter); 7066 } 7067 7068 /* Check for a mailbox event */ 7069 if (icr & E1000_ICR_VMMB) 7070 igb_msg_task(adapter); 7071 7072 if (icr & E1000_ICR_LSC) { 7073 hw->mac.get_link_status = 1; 7074 /* guard against interrupt when we're going down */ 7075 if (!test_bit(__IGB_DOWN, &adapter->state)) 7076 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7077 } 7078 7079 if (icr & E1000_ICR_TS) 7080 igb_tsync_interrupt(adapter); 7081 7082 wr32(E1000_EIMS, adapter->eims_other); 7083 7084 return IRQ_HANDLED; 7085 } 7086 7087 static void igb_write_itr(struct igb_q_vector *q_vector) 7088 { 7089 struct igb_adapter *adapter = q_vector->adapter; 7090 u32 itr_val = q_vector->itr_val & 0x7FFC; 7091 7092 if (!q_vector->set_itr) 7093 return; 7094 7095 if (!itr_val) 7096 itr_val = 0x4; 7097 7098 if (adapter->hw.mac.type == e1000_82575) 7099 itr_val |= itr_val << 16; 7100 else 7101 itr_val |= E1000_EITR_CNT_IGNR; 7102 7103 writel(itr_val, q_vector->itr_register); 7104 q_vector->set_itr = 0; 7105 } 7106 7107 static irqreturn_t igb_msix_ring(int irq, void *data) 7108 { 7109 struct igb_q_vector *q_vector = data; 7110 7111 /* Write the ITR value calculated from the previous interrupt. */ 7112 igb_write_itr(q_vector); 7113 7114 napi_schedule(&q_vector->napi); 7115 7116 return IRQ_HANDLED; 7117 } 7118 7119 #ifdef CONFIG_IGB_DCA 7120 static void igb_update_tx_dca(struct igb_adapter *adapter, 7121 struct igb_ring *tx_ring, 7122 int cpu) 7123 { 7124 struct e1000_hw *hw = &adapter->hw; 7125 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 7126 7127 if (hw->mac.type != e1000_82575) 7128 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 7129 7130 /* We can enable relaxed ordering for reads, but not writes when 7131 * DCA is enabled. This is due to a known issue in some chipsets 7132 * which will cause the DCA tag to be cleared. 7133 */ 7134 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 7135 E1000_DCA_TXCTRL_DATA_RRO_EN | 7136 E1000_DCA_TXCTRL_DESC_DCA_EN; 7137 7138 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 7139 } 7140 7141 static void igb_update_rx_dca(struct igb_adapter *adapter, 7142 struct igb_ring *rx_ring, 7143 int cpu) 7144 { 7145 struct e1000_hw *hw = &adapter->hw; 7146 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 7147 7148 if (hw->mac.type != e1000_82575) 7149 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 7150 7151 /* We can enable relaxed ordering for reads, but not writes when 7152 * DCA is enabled. This is due to a known issue in some chipsets 7153 * which will cause the DCA tag to be cleared. 7154 */ 7155 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 7156 E1000_DCA_RXCTRL_DESC_DCA_EN; 7157 7158 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 7159 } 7160 7161 static void igb_update_dca(struct igb_q_vector *q_vector) 7162 { 7163 struct igb_adapter *adapter = q_vector->adapter; 7164 int cpu = get_cpu(); 7165 7166 if (q_vector->cpu == cpu) 7167 goto out_no_update; 7168 7169 if (q_vector->tx.ring) 7170 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 7171 7172 if (q_vector->rx.ring) 7173 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 7174 7175 q_vector->cpu = cpu; 7176 out_no_update: 7177 put_cpu(); 7178 } 7179 7180 static void igb_setup_dca(struct igb_adapter *adapter) 7181 { 7182 struct e1000_hw *hw = &adapter->hw; 7183 int i; 7184 7185 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 7186 return; 7187 7188 /* Always use CB2 mode, difference is masked in the CB driver. */ 7189 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 7190 7191 for (i = 0; i < adapter->num_q_vectors; i++) { 7192 adapter->q_vector[i]->cpu = -1; 7193 igb_update_dca(adapter->q_vector[i]); 7194 } 7195 } 7196 7197 static int __igb_notify_dca(struct device *dev, void *data) 7198 { 7199 struct net_device *netdev = dev_get_drvdata(dev); 7200 struct igb_adapter *adapter = netdev_priv(netdev); 7201 struct pci_dev *pdev = adapter->pdev; 7202 struct e1000_hw *hw = &adapter->hw; 7203 unsigned long event = *(unsigned long *)data; 7204 7205 switch (event) { 7206 case DCA_PROVIDER_ADD: 7207 /* if already enabled, don't do it again */ 7208 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 7209 break; 7210 if (dca_add_requester(dev) == 0) { 7211 adapter->flags |= IGB_FLAG_DCA_ENABLED; 7212 dev_info(&pdev->dev, "DCA enabled\n"); 7213 igb_setup_dca(adapter); 7214 break; 7215 } 7216 fallthrough; /* since DCA is disabled. */ 7217 case DCA_PROVIDER_REMOVE: 7218 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 7219 /* without this a class_device is left 7220 * hanging around in the sysfs model 7221 */ 7222 dca_remove_requester(dev); 7223 dev_info(&pdev->dev, "DCA disabled\n"); 7224 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 7225 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 7226 } 7227 break; 7228 } 7229 7230 return 0; 7231 } 7232 7233 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 7234 void *p) 7235 { 7236 int ret_val; 7237 7238 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 7239 __igb_notify_dca); 7240 7241 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 7242 } 7243 #endif /* CONFIG_IGB_DCA */ 7244 7245 #ifdef CONFIG_PCI_IOV 7246 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 7247 { 7248 unsigned char mac_addr[ETH_ALEN]; 7249 7250 eth_zero_addr(mac_addr); 7251 igb_set_vf_mac(adapter, vf, mac_addr); 7252 7253 /* By default spoof check is enabled for all VFs */ 7254 adapter->vf_data[vf].spoofchk_enabled = true; 7255 7256 /* By default VFs are not trusted */ 7257 adapter->vf_data[vf].trusted = false; 7258 7259 return 0; 7260 } 7261 7262 #endif 7263 static void igb_ping_all_vfs(struct igb_adapter *adapter) 7264 { 7265 struct e1000_hw *hw = &adapter->hw; 7266 u32 ping; 7267 int i; 7268 7269 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 7270 ping = E1000_PF_CONTROL_MSG; 7271 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 7272 ping |= E1000_VT_MSGTYPE_CTS; 7273 igb_write_mbx(hw, &ping, 1, i); 7274 } 7275 } 7276 7277 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7278 { 7279 struct e1000_hw *hw = &adapter->hw; 7280 u32 vmolr = rd32(E1000_VMOLR(vf)); 7281 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7282 7283 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 7284 IGB_VF_FLAG_MULTI_PROMISC); 7285 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7286 7287 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 7288 vmolr |= E1000_VMOLR_MPME; 7289 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 7290 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 7291 } else { 7292 /* if we have hashes and we are clearing a multicast promisc 7293 * flag we need to write the hashes to the MTA as this step 7294 * was previously skipped 7295 */ 7296 if (vf_data->num_vf_mc_hashes > 30) { 7297 vmolr |= E1000_VMOLR_MPME; 7298 } else if (vf_data->num_vf_mc_hashes) { 7299 int j; 7300 7301 vmolr |= E1000_VMOLR_ROMPE; 7302 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7303 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7304 } 7305 } 7306 7307 wr32(E1000_VMOLR(vf), vmolr); 7308 7309 /* there are flags left unprocessed, likely not supported */ 7310 if (*msgbuf & E1000_VT_MSGINFO_MASK) 7311 return -EINVAL; 7312 7313 return 0; 7314 } 7315 7316 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 7317 u32 *msgbuf, u32 vf) 7318 { 7319 int n = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]); 7320 u16 *hash_list = (u16 *)&msgbuf[1]; 7321 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7322 int i; 7323 7324 /* salt away the number of multicast addresses assigned 7325 * to this VF for later use to restore when the PF multi cast 7326 * list changes 7327 */ 7328 vf_data->num_vf_mc_hashes = n; 7329 7330 /* only up to 30 hash values supported */ 7331 if (n > 30) 7332 n = 30; 7333 7334 /* store the hashes for later use */ 7335 for (i = 0; i < n; i++) 7336 vf_data->vf_mc_hashes[i] = hash_list[i]; 7337 7338 /* Flush and reset the mta with the new values */ 7339 igb_set_rx_mode(adapter->netdev); 7340 7341 return 0; 7342 } 7343 7344 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 7345 { 7346 struct e1000_hw *hw = &adapter->hw; 7347 struct vf_data_storage *vf_data; 7348 int i, j; 7349 7350 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7351 u32 vmolr = rd32(E1000_VMOLR(i)); 7352 7353 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7354 7355 vf_data = &adapter->vf_data[i]; 7356 7357 if ((vf_data->num_vf_mc_hashes > 30) || 7358 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 7359 vmolr |= E1000_VMOLR_MPME; 7360 } else if (vf_data->num_vf_mc_hashes) { 7361 vmolr |= E1000_VMOLR_ROMPE; 7362 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7363 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7364 } 7365 wr32(E1000_VMOLR(i), vmolr); 7366 } 7367 } 7368 7369 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 7370 { 7371 struct e1000_hw *hw = &adapter->hw; 7372 u32 pool_mask, vlvf_mask, i; 7373 7374 /* create mask for VF and other pools */ 7375 pool_mask = E1000_VLVF_POOLSEL_MASK; 7376 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 7377 7378 /* drop PF from pool bits */ 7379 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 7380 adapter->vfs_allocated_count); 7381 7382 /* Find the vlan filter for this id */ 7383 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 7384 u32 vlvf = rd32(E1000_VLVF(i)); 7385 u32 vfta_mask, vid, vfta; 7386 7387 /* remove the vf from the pool */ 7388 if (!(vlvf & vlvf_mask)) 7389 continue; 7390 7391 /* clear out bit from VLVF */ 7392 vlvf ^= vlvf_mask; 7393 7394 /* if other pools are present, just remove ourselves */ 7395 if (vlvf & pool_mask) 7396 goto update_vlvfb; 7397 7398 /* if PF is present, leave VFTA */ 7399 if (vlvf & E1000_VLVF_POOLSEL_MASK) 7400 goto update_vlvf; 7401 7402 vid = vlvf & E1000_VLVF_VLANID_MASK; 7403 vfta_mask = BIT(vid % 32); 7404 7405 /* clear bit from VFTA */ 7406 vfta = adapter->shadow_vfta[vid / 32]; 7407 if (vfta & vfta_mask) 7408 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 7409 update_vlvf: 7410 /* clear pool selection enable */ 7411 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7412 vlvf &= E1000_VLVF_POOLSEL_MASK; 7413 else 7414 vlvf = 0; 7415 update_vlvfb: 7416 /* clear pool bits */ 7417 wr32(E1000_VLVF(i), vlvf); 7418 } 7419 } 7420 7421 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 7422 { 7423 u32 vlvf; 7424 int idx; 7425 7426 /* short cut the special case */ 7427 if (vlan == 0) 7428 return 0; 7429 7430 /* Search for the VLAN id in the VLVF entries */ 7431 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 7432 vlvf = rd32(E1000_VLVF(idx)); 7433 if ((vlvf & VLAN_VID_MASK) == vlan) 7434 break; 7435 } 7436 7437 return idx; 7438 } 7439 7440 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 7441 { 7442 struct e1000_hw *hw = &adapter->hw; 7443 u32 bits, pf_id; 7444 int idx; 7445 7446 idx = igb_find_vlvf_entry(hw, vid); 7447 if (!idx) 7448 return; 7449 7450 /* See if any other pools are set for this VLAN filter 7451 * entry other than the PF. 7452 */ 7453 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 7454 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 7455 bits &= rd32(E1000_VLVF(idx)); 7456 7457 /* Disable the filter so this falls into the default pool. */ 7458 if (!bits) { 7459 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7460 wr32(E1000_VLVF(idx), BIT(pf_id)); 7461 else 7462 wr32(E1000_VLVF(idx), 0); 7463 } 7464 } 7465 7466 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 7467 bool add, u32 vf) 7468 { 7469 int pf_id = adapter->vfs_allocated_count; 7470 struct e1000_hw *hw = &adapter->hw; 7471 int err; 7472 7473 /* If VLAN overlaps with one the PF is currently monitoring make 7474 * sure that we are able to allocate a VLVF entry. This may be 7475 * redundant but it guarantees PF will maintain visibility to 7476 * the VLAN. 7477 */ 7478 if (add && test_bit(vid, adapter->active_vlans)) { 7479 err = igb_vfta_set(hw, vid, pf_id, true, false); 7480 if (err) 7481 return err; 7482 } 7483 7484 err = igb_vfta_set(hw, vid, vf, add, false); 7485 7486 if (add && !err) 7487 return err; 7488 7489 /* If we failed to add the VF VLAN or we are removing the VF VLAN 7490 * we may need to drop the PF pool bit in order to allow us to free 7491 * up the VLVF resources. 7492 */ 7493 if (test_bit(vid, adapter->active_vlans) || 7494 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7495 igb_update_pf_vlvf(adapter, vid); 7496 7497 return err; 7498 } 7499 7500 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 7501 { 7502 struct e1000_hw *hw = &adapter->hw; 7503 7504 if (vid) 7505 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 7506 else 7507 wr32(E1000_VMVIR(vf), 0); 7508 } 7509 7510 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7511 u16 vlan, u8 qos) 7512 { 7513 int err; 7514 7515 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7516 if (err) 7517 return err; 7518 7519 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7520 igb_set_vmolr(adapter, vf, !vlan); 7521 7522 /* revoke access to previous VLAN */ 7523 if (vlan != adapter->vf_data[vf].pf_vlan) 7524 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7525 false, vf); 7526 7527 adapter->vf_data[vf].pf_vlan = vlan; 7528 adapter->vf_data[vf].pf_qos = qos; 7529 igb_set_vf_vlan_strip(adapter, vf, true); 7530 dev_info(&adapter->pdev->dev, 7531 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7532 if (test_bit(__IGB_DOWN, &adapter->state)) { 7533 dev_warn(&adapter->pdev->dev, 7534 "The VF VLAN has been set, but the PF device is not up.\n"); 7535 dev_warn(&adapter->pdev->dev, 7536 "Bring the PF device up before attempting to use the VF device.\n"); 7537 } 7538 7539 return err; 7540 } 7541 7542 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7543 { 7544 /* Restore tagless access via VLAN 0 */ 7545 igb_set_vf_vlan(adapter, 0, true, vf); 7546 7547 igb_set_vmvir(adapter, 0, vf); 7548 igb_set_vmolr(adapter, vf, true); 7549 7550 /* Remove any PF assigned VLAN */ 7551 if (adapter->vf_data[vf].pf_vlan) 7552 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7553 false, vf); 7554 7555 adapter->vf_data[vf].pf_vlan = 0; 7556 adapter->vf_data[vf].pf_qos = 0; 7557 igb_set_vf_vlan_strip(adapter, vf, false); 7558 7559 return 0; 7560 } 7561 7562 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7563 u16 vlan, u8 qos, __be16 vlan_proto) 7564 { 7565 struct igb_adapter *adapter = netdev_priv(netdev); 7566 7567 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7568 return -EINVAL; 7569 7570 if (vlan_proto != htons(ETH_P_8021Q)) 7571 return -EPROTONOSUPPORT; 7572 7573 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7574 igb_disable_port_vlan(adapter, vf); 7575 } 7576 7577 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7578 { 7579 int add = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]); 7580 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7581 int ret; 7582 7583 if (adapter->vf_data[vf].pf_vlan) 7584 return -1; 7585 7586 /* VLAN 0 is a special case, don't allow it to be removed */ 7587 if (!vid && !add) 7588 return 0; 7589 7590 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7591 if (!ret) 7592 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7593 return ret; 7594 } 7595 7596 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7597 { 7598 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7599 7600 /* clear flags - except flag that indicates PF has set the MAC */ 7601 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7602 vf_data->last_nack = jiffies; 7603 7604 /* reset vlans for device */ 7605 igb_clear_vf_vfta(adapter, vf); 7606 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7607 igb_set_vmvir(adapter, vf_data->pf_vlan | 7608 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7609 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7610 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7611 7612 /* reset multicast table array for vf */ 7613 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7614 7615 /* Flush and reset the mta with the new values */ 7616 igb_set_rx_mode(adapter->netdev); 7617 } 7618 7619 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7620 { 7621 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7622 7623 /* clear mac address as we were hotplug removed/added */ 7624 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7625 eth_zero_addr(vf_mac); 7626 7627 /* process remaining reset events */ 7628 igb_vf_reset(adapter, vf); 7629 } 7630 7631 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7632 { 7633 struct e1000_hw *hw = &adapter->hw; 7634 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7635 u32 reg, msgbuf[3] = {}; 7636 u8 *addr = (u8 *)(&msgbuf[1]); 7637 7638 /* process all the same items cleared in a function level reset */ 7639 igb_vf_reset(adapter, vf); 7640 7641 /* set vf mac address */ 7642 igb_set_vf_mac(adapter, vf, vf_mac); 7643 7644 /* enable transmit and receive for vf */ 7645 reg = rd32(E1000_VFTE); 7646 wr32(E1000_VFTE, reg | BIT(vf)); 7647 reg = rd32(E1000_VFRE); 7648 wr32(E1000_VFRE, reg | BIT(vf)); 7649 7650 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7651 7652 /* reply to reset with ack and vf mac address */ 7653 if (!is_zero_ether_addr(vf_mac)) { 7654 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7655 memcpy(addr, vf_mac, ETH_ALEN); 7656 } else { 7657 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7658 } 7659 igb_write_mbx(hw, msgbuf, 3, vf); 7660 } 7661 7662 static void igb_flush_mac_table(struct igb_adapter *adapter) 7663 { 7664 struct e1000_hw *hw = &adapter->hw; 7665 int i; 7666 7667 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7668 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7669 eth_zero_addr(adapter->mac_table[i].addr); 7670 adapter->mac_table[i].queue = 0; 7671 igb_rar_set_index(adapter, i); 7672 } 7673 } 7674 7675 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7676 { 7677 struct e1000_hw *hw = &adapter->hw; 7678 /* do not count rar entries reserved for VFs MAC addresses */ 7679 int rar_entries = hw->mac.rar_entry_count - 7680 adapter->vfs_allocated_count; 7681 int i, count = 0; 7682 7683 for (i = 0; i < rar_entries; i++) { 7684 /* do not count default entries */ 7685 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7686 continue; 7687 7688 /* do not count "in use" entries for different queues */ 7689 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7690 (adapter->mac_table[i].queue != queue)) 7691 continue; 7692 7693 count++; 7694 } 7695 7696 return count; 7697 } 7698 7699 /* Set default MAC address for the PF in the first RAR entry */ 7700 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7701 { 7702 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7703 7704 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7705 mac_table->queue = adapter->vfs_allocated_count; 7706 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7707 7708 igb_rar_set_index(adapter, 0); 7709 } 7710 7711 /* If the filter to be added and an already existing filter express 7712 * the same address and address type, it should be possible to only 7713 * override the other configurations, for example the queue to steer 7714 * traffic. 7715 */ 7716 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7717 const u8 *addr, const u8 flags) 7718 { 7719 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7720 return true; 7721 7722 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7723 (flags & IGB_MAC_STATE_SRC_ADDR)) 7724 return false; 7725 7726 if (!ether_addr_equal(addr, entry->addr)) 7727 return false; 7728 7729 return true; 7730 } 7731 7732 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7733 * 'flags' is used to indicate what kind of match is made, match is by 7734 * default for the destination address, if matching by source address 7735 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7736 */ 7737 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7738 const u8 *addr, const u8 queue, 7739 const u8 flags) 7740 { 7741 struct e1000_hw *hw = &adapter->hw; 7742 int rar_entries = hw->mac.rar_entry_count - 7743 adapter->vfs_allocated_count; 7744 int i; 7745 7746 if (is_zero_ether_addr(addr)) 7747 return -EINVAL; 7748 7749 /* Search for the first empty entry in the MAC table. 7750 * Do not touch entries at the end of the table reserved for the VF MAC 7751 * addresses. 7752 */ 7753 for (i = 0; i < rar_entries; i++) { 7754 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7755 addr, flags)) 7756 continue; 7757 7758 ether_addr_copy(adapter->mac_table[i].addr, addr); 7759 adapter->mac_table[i].queue = queue; 7760 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7761 7762 igb_rar_set_index(adapter, i); 7763 return i; 7764 } 7765 7766 return -ENOSPC; 7767 } 7768 7769 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7770 const u8 queue) 7771 { 7772 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7773 } 7774 7775 /* Remove a MAC filter for 'addr' directing matching traffic to 7776 * 'queue', 'flags' is used to indicate what kind of match need to be 7777 * removed, match is by default for the destination address, if 7778 * matching by source address is to be removed the flag 7779 * IGB_MAC_STATE_SRC_ADDR can be used. 7780 */ 7781 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7782 const u8 *addr, const u8 queue, 7783 const u8 flags) 7784 { 7785 struct e1000_hw *hw = &adapter->hw; 7786 int rar_entries = hw->mac.rar_entry_count - 7787 adapter->vfs_allocated_count; 7788 int i; 7789 7790 if (is_zero_ether_addr(addr)) 7791 return -EINVAL; 7792 7793 /* Search for matching entry in the MAC table based on given address 7794 * and queue. Do not touch entries at the end of the table reserved 7795 * for the VF MAC addresses. 7796 */ 7797 for (i = 0; i < rar_entries; i++) { 7798 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7799 continue; 7800 if ((adapter->mac_table[i].state & flags) != flags) 7801 continue; 7802 if (adapter->mac_table[i].queue != queue) 7803 continue; 7804 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7805 continue; 7806 7807 /* When a filter for the default address is "deleted", 7808 * we return it to its initial configuration 7809 */ 7810 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7811 adapter->mac_table[i].state = 7812 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7813 adapter->mac_table[i].queue = 7814 adapter->vfs_allocated_count; 7815 } else { 7816 adapter->mac_table[i].state = 0; 7817 adapter->mac_table[i].queue = 0; 7818 eth_zero_addr(adapter->mac_table[i].addr); 7819 } 7820 7821 igb_rar_set_index(adapter, i); 7822 return 0; 7823 } 7824 7825 return -ENOENT; 7826 } 7827 7828 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7829 const u8 queue) 7830 { 7831 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7832 } 7833 7834 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7835 const u8 *addr, u8 queue, u8 flags) 7836 { 7837 struct e1000_hw *hw = &adapter->hw; 7838 7839 /* In theory, this should be supported on 82575 as well, but 7840 * that part wasn't easily accessible during development. 7841 */ 7842 if (hw->mac.type != e1000_i210) 7843 return -EOPNOTSUPP; 7844 7845 return igb_add_mac_filter_flags(adapter, addr, queue, 7846 IGB_MAC_STATE_QUEUE_STEERING | flags); 7847 } 7848 7849 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7850 const u8 *addr, u8 queue, u8 flags) 7851 { 7852 return igb_del_mac_filter_flags(adapter, addr, queue, 7853 IGB_MAC_STATE_QUEUE_STEERING | flags); 7854 } 7855 7856 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7857 { 7858 struct igb_adapter *adapter = netdev_priv(netdev); 7859 int ret; 7860 7861 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7862 7863 return min_t(int, ret, 0); 7864 } 7865 7866 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7867 { 7868 struct igb_adapter *adapter = netdev_priv(netdev); 7869 7870 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7871 7872 return 0; 7873 } 7874 7875 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7876 const u32 info, const u8 *addr) 7877 { 7878 struct pci_dev *pdev = adapter->pdev; 7879 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7880 struct vf_mac_filter *entry; 7881 bool found = false; 7882 int ret = 0; 7883 7884 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7885 !vf_data->trusted) { 7886 dev_warn(&pdev->dev, 7887 "VF %d requested MAC filter but is administratively denied\n", 7888 vf); 7889 return -EINVAL; 7890 } 7891 if (!is_valid_ether_addr(addr)) { 7892 dev_warn(&pdev->dev, 7893 "VF %d attempted to set invalid MAC filter\n", 7894 vf); 7895 return -EINVAL; 7896 } 7897 7898 switch (info) { 7899 case E1000_VF_MAC_FILTER_CLR: 7900 /* remove all unicast MAC filters related to the current VF */ 7901 list_for_each_entry(entry, &adapter->vf_macs.l, l) { 7902 if (entry->vf == vf) { 7903 entry->vf = -1; 7904 entry->free = true; 7905 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7906 } 7907 } 7908 break; 7909 case E1000_VF_MAC_FILTER_ADD: 7910 /* try to find empty slot in the list */ 7911 list_for_each_entry(entry, &adapter->vf_macs.l, l) { 7912 if (entry->free) { 7913 found = true; 7914 break; 7915 } 7916 } 7917 7918 if (found) { 7919 entry->free = false; 7920 entry->vf = vf; 7921 ether_addr_copy(entry->vf_mac, addr); 7922 7923 ret = igb_add_mac_filter(adapter, addr, vf); 7924 ret = min_t(int, ret, 0); 7925 } else { 7926 ret = -ENOSPC; 7927 } 7928 7929 if (ret == -ENOSPC) 7930 dev_warn(&pdev->dev, 7931 "VF %d has requested MAC filter but there is no space for it\n", 7932 vf); 7933 break; 7934 default: 7935 ret = -EINVAL; 7936 break; 7937 } 7938 7939 return ret; 7940 } 7941 7942 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7943 { 7944 struct pci_dev *pdev = adapter->pdev; 7945 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7946 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7947 7948 /* The VF MAC Address is stored in a packed array of bytes 7949 * starting at the second 32 bit word of the msg array 7950 */ 7951 unsigned char *addr = (unsigned char *)&msg[1]; 7952 int ret = 0; 7953 7954 if (!info) { 7955 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7956 !vf_data->trusted) { 7957 dev_warn(&pdev->dev, 7958 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 7959 vf); 7960 return -EINVAL; 7961 } 7962 7963 if (!is_valid_ether_addr(addr)) { 7964 dev_warn(&pdev->dev, 7965 "VF %d attempted to set invalid MAC\n", 7966 vf); 7967 return -EINVAL; 7968 } 7969 7970 ret = igb_set_vf_mac(adapter, vf, addr); 7971 } else { 7972 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 7973 } 7974 7975 return ret; 7976 } 7977 7978 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 7979 { 7980 struct e1000_hw *hw = &adapter->hw; 7981 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7982 u32 msg = E1000_VT_MSGTYPE_NACK; 7983 7984 /* if device isn't clear to send it shouldn't be reading either */ 7985 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 7986 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 7987 igb_write_mbx(hw, &msg, 1, vf); 7988 vf_data->last_nack = jiffies; 7989 } 7990 } 7991 7992 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 7993 { 7994 struct pci_dev *pdev = adapter->pdev; 7995 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 7996 struct e1000_hw *hw = &adapter->hw; 7997 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7998 s32 retval; 7999 8000 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 8001 8002 if (retval) { 8003 /* if receive failed revoke VF CTS stats and restart init */ 8004 dev_err(&pdev->dev, "Error receiving message from VF\n"); 8005 vf_data->flags &= ~IGB_VF_FLAG_CTS; 8006 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 8007 goto unlock; 8008 goto out; 8009 } 8010 8011 /* this is a message we already processed, do nothing */ 8012 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 8013 goto unlock; 8014 8015 /* until the vf completes a reset it should not be 8016 * allowed to start any configuration. 8017 */ 8018 if (msgbuf[0] == E1000_VF_RESET) { 8019 /* unlocks mailbox */ 8020 igb_vf_reset_msg(adapter, vf); 8021 return; 8022 } 8023 8024 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 8025 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 8026 goto unlock; 8027 retval = -1; 8028 goto out; 8029 } 8030 8031 switch ((msgbuf[0] & 0xFFFF)) { 8032 case E1000_VF_SET_MAC_ADDR: 8033 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 8034 break; 8035 case E1000_VF_SET_PROMISC: 8036 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 8037 break; 8038 case E1000_VF_SET_MULTICAST: 8039 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 8040 break; 8041 case E1000_VF_SET_LPE: 8042 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 8043 break; 8044 case E1000_VF_SET_VLAN: 8045 retval = -1; 8046 if (vf_data->pf_vlan) 8047 dev_warn(&pdev->dev, 8048 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 8049 vf); 8050 else 8051 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 8052 break; 8053 default: 8054 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 8055 retval = -1; 8056 break; 8057 } 8058 8059 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 8060 out: 8061 /* notify the VF of the results of what it sent us */ 8062 if (retval) 8063 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 8064 else 8065 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 8066 8067 /* unlocks mailbox */ 8068 igb_write_mbx(hw, msgbuf, 1, vf); 8069 return; 8070 8071 unlock: 8072 igb_unlock_mbx(hw, vf); 8073 } 8074 8075 static void igb_msg_task(struct igb_adapter *adapter) 8076 { 8077 struct e1000_hw *hw = &adapter->hw; 8078 unsigned long flags; 8079 u32 vf; 8080 8081 spin_lock_irqsave(&adapter->vfs_lock, flags); 8082 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 8083 /* process any reset requests */ 8084 if (!igb_check_for_rst(hw, vf)) 8085 igb_vf_reset_event(adapter, vf); 8086 8087 /* process any messages pending */ 8088 if (!igb_check_for_msg(hw, vf)) 8089 igb_rcv_msg_from_vf(adapter, vf); 8090 8091 /* process any acks */ 8092 if (!igb_check_for_ack(hw, vf)) 8093 igb_rcv_ack_from_vf(adapter, vf); 8094 } 8095 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 8096 } 8097 8098 /** 8099 * igb_set_uta - Set unicast filter table address 8100 * @adapter: board private structure 8101 * @set: boolean indicating if we are setting or clearing bits 8102 * 8103 * The unicast table address is a register array of 32-bit registers. 8104 * The table is meant to be used in a way similar to how the MTA is used 8105 * however due to certain limitations in the hardware it is necessary to 8106 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 8107 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 8108 **/ 8109 static void igb_set_uta(struct igb_adapter *adapter, bool set) 8110 { 8111 struct e1000_hw *hw = &adapter->hw; 8112 u32 uta = set ? ~0 : 0; 8113 int i; 8114 8115 /* we only need to do this if VMDq is enabled */ 8116 if (!adapter->vfs_allocated_count) 8117 return; 8118 8119 for (i = hw->mac.uta_reg_count; i--;) 8120 array_wr32(E1000_UTA, i, uta); 8121 } 8122 8123 /** 8124 * igb_intr_msi - Interrupt Handler 8125 * @irq: interrupt number 8126 * @data: pointer to a network interface device structure 8127 **/ 8128 static irqreturn_t igb_intr_msi(int irq, void *data) 8129 { 8130 struct igb_adapter *adapter = data; 8131 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8132 struct e1000_hw *hw = &adapter->hw; 8133 /* read ICR disables interrupts using IAM */ 8134 u32 icr = rd32(E1000_ICR); 8135 8136 igb_write_itr(q_vector); 8137 8138 if (icr & E1000_ICR_DRSTA) 8139 schedule_work(&adapter->reset_task); 8140 8141 if (icr & E1000_ICR_DOUTSYNC) { 8142 /* HW is reporting DMA is out of sync */ 8143 adapter->stats.doosync++; 8144 } 8145 8146 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8147 hw->mac.get_link_status = 1; 8148 if (!test_bit(__IGB_DOWN, &adapter->state)) 8149 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8150 } 8151 8152 if (icr & E1000_ICR_TS) 8153 igb_tsync_interrupt(adapter); 8154 8155 napi_schedule(&q_vector->napi); 8156 8157 return IRQ_HANDLED; 8158 } 8159 8160 /** 8161 * igb_intr - Legacy Interrupt Handler 8162 * @irq: interrupt number 8163 * @data: pointer to a network interface device structure 8164 **/ 8165 static irqreturn_t igb_intr(int irq, void *data) 8166 { 8167 struct igb_adapter *adapter = data; 8168 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8169 struct e1000_hw *hw = &adapter->hw; 8170 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 8171 * need for the IMC write 8172 */ 8173 u32 icr = rd32(E1000_ICR); 8174 8175 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 8176 * not set, then the adapter didn't send an interrupt 8177 */ 8178 if (!(icr & E1000_ICR_INT_ASSERTED)) 8179 return IRQ_NONE; 8180 8181 igb_write_itr(q_vector); 8182 8183 if (icr & E1000_ICR_DRSTA) 8184 schedule_work(&adapter->reset_task); 8185 8186 if (icr & E1000_ICR_DOUTSYNC) { 8187 /* HW is reporting DMA is out of sync */ 8188 adapter->stats.doosync++; 8189 } 8190 8191 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8192 hw->mac.get_link_status = 1; 8193 /* guard against interrupt when we're going down */ 8194 if (!test_bit(__IGB_DOWN, &adapter->state)) 8195 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8196 } 8197 8198 if (icr & E1000_ICR_TS) 8199 igb_tsync_interrupt(adapter); 8200 8201 napi_schedule(&q_vector->napi); 8202 8203 return IRQ_HANDLED; 8204 } 8205 8206 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 8207 { 8208 struct igb_adapter *adapter = q_vector->adapter; 8209 struct e1000_hw *hw = &adapter->hw; 8210 8211 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 8212 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 8213 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 8214 igb_set_itr(q_vector); 8215 else 8216 igb_update_ring_itr(q_vector); 8217 } 8218 8219 if (!test_bit(__IGB_DOWN, &adapter->state)) { 8220 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8221 wr32(E1000_EIMS, q_vector->eims_value); 8222 else 8223 igb_irq_enable(adapter); 8224 } 8225 } 8226 8227 /** 8228 * igb_poll - NAPI Rx polling callback 8229 * @napi: napi polling structure 8230 * @budget: count of how many packets we should handle 8231 **/ 8232 static int igb_poll(struct napi_struct *napi, int budget) 8233 { 8234 struct igb_q_vector *q_vector = container_of(napi, 8235 struct igb_q_vector, 8236 napi); 8237 struct xsk_buff_pool *xsk_pool; 8238 bool clean_complete = true; 8239 int work_done = 0; 8240 8241 #ifdef CONFIG_IGB_DCA 8242 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 8243 igb_update_dca(q_vector); 8244 #endif 8245 if (q_vector->tx.ring) 8246 clean_complete = igb_clean_tx_irq(q_vector, budget); 8247 8248 if (q_vector->rx.ring) { 8249 int cleaned; 8250 8251 xsk_pool = READ_ONCE(q_vector->rx.ring->xsk_pool); 8252 cleaned = xsk_pool ? 8253 igb_clean_rx_irq_zc(q_vector, xsk_pool, budget) : 8254 igb_clean_rx_irq(q_vector, budget); 8255 8256 work_done += cleaned; 8257 if (cleaned >= budget) 8258 clean_complete = false; 8259 } 8260 8261 /* If all work not completed, return budget and keep polling */ 8262 if (!clean_complete) 8263 return budget; 8264 8265 /* Exit the polling mode, but don't re-enable interrupts if stack might 8266 * poll us due to busy-polling 8267 */ 8268 if (likely(napi_complete_done(napi, work_done))) 8269 igb_ring_irq_enable(q_vector); 8270 8271 return work_done; 8272 } 8273 8274 /** 8275 * igb_clean_tx_irq - Reclaim resources after transmit completes 8276 * @q_vector: pointer to q_vector containing needed info 8277 * @napi_budget: Used to determine if we are in netpoll 8278 * 8279 * returns true if ring is completely cleaned 8280 **/ 8281 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 8282 { 8283 unsigned int total_bytes = 0, total_packets = 0; 8284 struct igb_adapter *adapter = q_vector->adapter; 8285 unsigned int budget = q_vector->tx.work_limit; 8286 struct igb_ring *tx_ring = q_vector->tx.ring; 8287 unsigned int i = tx_ring->next_to_clean; 8288 union e1000_adv_tx_desc *tx_desc; 8289 struct igb_tx_buffer *tx_buffer; 8290 struct xsk_buff_pool *xsk_pool; 8291 int cpu = smp_processor_id(); 8292 bool xsk_xmit_done = true; 8293 struct netdev_queue *nq; 8294 u32 xsk_frames = 0; 8295 8296 if (test_bit(__IGB_DOWN, &adapter->state)) 8297 return true; 8298 8299 tx_buffer = &tx_ring->tx_buffer_info[i]; 8300 tx_desc = IGB_TX_DESC(tx_ring, i); 8301 i -= tx_ring->count; 8302 8303 do { 8304 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 8305 8306 /* if next_to_watch is not set then there is no work pending */ 8307 if (!eop_desc) 8308 break; 8309 8310 /* prevent any other reads prior to eop_desc */ 8311 smp_rmb(); 8312 8313 /* if DD is not set pending work has not been completed */ 8314 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 8315 break; 8316 8317 /* clear next_to_watch to prevent false hangs */ 8318 tx_buffer->next_to_watch = NULL; 8319 8320 /* update the statistics for this packet */ 8321 total_bytes += tx_buffer->bytecount; 8322 total_packets += tx_buffer->gso_segs; 8323 8324 /* free the skb */ 8325 if (tx_buffer->type == IGB_TYPE_SKB) { 8326 napi_consume_skb(tx_buffer->skb, napi_budget); 8327 } else if (tx_buffer->type == IGB_TYPE_XDP) { 8328 xdp_return_frame(tx_buffer->xdpf); 8329 } else if (tx_buffer->type == IGB_TYPE_XSK) { 8330 xsk_frames++; 8331 goto skip_for_xsk; 8332 } 8333 8334 /* unmap skb header data */ 8335 dma_unmap_single(tx_ring->dev, 8336 dma_unmap_addr(tx_buffer, dma), 8337 dma_unmap_len(tx_buffer, len), 8338 DMA_TO_DEVICE); 8339 8340 /* clear tx_buffer data */ 8341 dma_unmap_len_set(tx_buffer, len, 0); 8342 8343 /* clear last DMA location and unmap remaining buffers */ 8344 while (tx_desc != eop_desc) { 8345 tx_buffer++; 8346 tx_desc++; 8347 i++; 8348 if (unlikely(!i)) { 8349 i -= tx_ring->count; 8350 tx_buffer = tx_ring->tx_buffer_info; 8351 tx_desc = IGB_TX_DESC(tx_ring, 0); 8352 } 8353 8354 /* unmap any remaining paged data */ 8355 if (dma_unmap_len(tx_buffer, len)) { 8356 dma_unmap_page(tx_ring->dev, 8357 dma_unmap_addr(tx_buffer, dma), 8358 dma_unmap_len(tx_buffer, len), 8359 DMA_TO_DEVICE); 8360 dma_unmap_len_set(tx_buffer, len, 0); 8361 } 8362 } 8363 8364 skip_for_xsk: 8365 /* move us one more past the eop_desc for start of next pkt */ 8366 tx_buffer++; 8367 tx_desc++; 8368 i++; 8369 if (unlikely(!i)) { 8370 i -= tx_ring->count; 8371 tx_buffer = tx_ring->tx_buffer_info; 8372 tx_desc = IGB_TX_DESC(tx_ring, 0); 8373 } 8374 8375 /* issue prefetch for next Tx descriptor */ 8376 prefetch(tx_desc); 8377 8378 /* update budget accounting */ 8379 budget--; 8380 } while (likely(budget)); 8381 8382 netdev_tx_completed_queue(txring_txq(tx_ring), 8383 total_packets, total_bytes); 8384 i += tx_ring->count; 8385 tx_ring->next_to_clean = i; 8386 u64_stats_update_begin(&tx_ring->tx_syncp); 8387 tx_ring->tx_stats.bytes += total_bytes; 8388 tx_ring->tx_stats.packets += total_packets; 8389 u64_stats_update_end(&tx_ring->tx_syncp); 8390 q_vector->tx.total_bytes += total_bytes; 8391 q_vector->tx.total_packets += total_packets; 8392 8393 xsk_pool = READ_ONCE(tx_ring->xsk_pool); 8394 if (xsk_pool) { 8395 if (xsk_frames) 8396 xsk_tx_completed(xsk_pool, xsk_frames); 8397 if (xsk_uses_need_wakeup(xsk_pool)) 8398 xsk_set_tx_need_wakeup(xsk_pool); 8399 8400 nq = txring_txq(tx_ring); 8401 __netif_tx_lock(nq, cpu); 8402 /* Avoid transmit queue timeout since we share it with the slow path */ 8403 txq_trans_cond_update(nq); 8404 xsk_xmit_done = igb_xmit_zc(tx_ring, xsk_pool); 8405 __netif_tx_unlock(nq); 8406 } 8407 8408 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 8409 struct e1000_hw *hw = &adapter->hw; 8410 8411 /* Detect a transmit hang in hardware, this serializes the 8412 * check with the clearing of time_stamp and movement of i 8413 */ 8414 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 8415 if (tx_buffer->next_to_watch && 8416 time_after(jiffies, tx_buffer->time_stamp + 8417 (adapter->tx_timeout_factor * HZ)) && 8418 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 8419 8420 /* detected Tx unit hang */ 8421 dev_err(tx_ring->dev, 8422 "Detected Tx Unit Hang\n" 8423 " Tx Queue <%d>\n" 8424 " TDH <%x>\n" 8425 " TDT <%x>\n" 8426 " next_to_use <%x>\n" 8427 " next_to_clean <%x>\n" 8428 "buffer_info[next_to_clean]\n" 8429 " time_stamp <%lx>\n" 8430 " next_to_watch <%p>\n" 8431 " jiffies <%lx>\n" 8432 " desc.status <%x>\n", 8433 tx_ring->queue_index, 8434 rd32(E1000_TDH(tx_ring->reg_idx)), 8435 readl(tx_ring->tail), 8436 tx_ring->next_to_use, 8437 tx_ring->next_to_clean, 8438 tx_buffer->time_stamp, 8439 tx_buffer->next_to_watch, 8440 jiffies, 8441 tx_buffer->next_to_watch->wb.status); 8442 netif_stop_subqueue(tx_ring->netdev, 8443 tx_ring->queue_index); 8444 8445 /* we are about to reset, no point in enabling stuff */ 8446 return true; 8447 } 8448 } 8449 8450 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 8451 if (unlikely(total_packets && 8452 netif_carrier_ok(tx_ring->netdev) && 8453 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 8454 /* Make sure that anybody stopping the queue after this 8455 * sees the new next_to_clean. 8456 */ 8457 smp_mb(); 8458 if (__netif_subqueue_stopped(tx_ring->netdev, 8459 tx_ring->queue_index) && 8460 !(test_bit(__IGB_DOWN, &adapter->state))) { 8461 netif_wake_subqueue(tx_ring->netdev, 8462 tx_ring->queue_index); 8463 8464 u64_stats_update_begin(&tx_ring->tx_syncp); 8465 tx_ring->tx_stats.restart_queue++; 8466 u64_stats_update_end(&tx_ring->tx_syncp); 8467 } 8468 } 8469 8470 return !!budget && xsk_xmit_done; 8471 } 8472 8473 /** 8474 * igb_reuse_rx_page - page flip buffer and store it back on the ring 8475 * @rx_ring: rx descriptor ring to store buffers on 8476 * @old_buff: donor buffer to have page reused 8477 * 8478 * Synchronizes page for reuse by the adapter 8479 **/ 8480 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 8481 struct igb_rx_buffer *old_buff) 8482 { 8483 struct igb_rx_buffer *new_buff; 8484 u16 nta = rx_ring->next_to_alloc; 8485 8486 new_buff = &rx_ring->rx_buffer_info[nta]; 8487 8488 /* update, and store next to alloc */ 8489 nta++; 8490 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 8491 8492 /* Transfer page from old buffer to new buffer. 8493 * Move each member individually to avoid possible store 8494 * forwarding stalls. 8495 */ 8496 new_buff->dma = old_buff->dma; 8497 new_buff->page = old_buff->page; 8498 new_buff->page_offset = old_buff->page_offset; 8499 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 8500 } 8501 8502 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 8503 int rx_buf_pgcnt) 8504 { 8505 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 8506 struct page *page = rx_buffer->page; 8507 8508 /* avoid re-using remote and pfmemalloc pages */ 8509 if (!dev_page_is_reusable(page)) 8510 return false; 8511 8512 #if (PAGE_SIZE < 8192) 8513 /* if we are only owner of page we can reuse it */ 8514 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1)) 8515 return false; 8516 #else 8517 #define IGB_LAST_OFFSET \ 8518 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 8519 8520 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 8521 return false; 8522 #endif 8523 8524 /* If we have drained the page fragment pool we need to update 8525 * the pagecnt_bias and page count so that we fully restock the 8526 * number of references the driver holds. 8527 */ 8528 if (unlikely(pagecnt_bias == 1)) { 8529 page_ref_add(page, USHRT_MAX - 1); 8530 rx_buffer->pagecnt_bias = USHRT_MAX; 8531 } 8532 8533 return true; 8534 } 8535 8536 /** 8537 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 8538 * @rx_ring: rx descriptor ring to transact packets on 8539 * @rx_buffer: buffer containing page to add 8540 * @skb: sk_buff to place the data into 8541 * @size: size of buffer to be added 8542 * 8543 * This function will add the data contained in rx_buffer->page to the skb. 8544 **/ 8545 static void igb_add_rx_frag(struct igb_ring *rx_ring, 8546 struct igb_rx_buffer *rx_buffer, 8547 struct sk_buff *skb, 8548 unsigned int size) 8549 { 8550 #if (PAGE_SIZE < 8192) 8551 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8552 #else 8553 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8554 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8555 SKB_DATA_ALIGN(size); 8556 #endif 8557 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8558 rx_buffer->page_offset, size, truesize); 8559 #if (PAGE_SIZE < 8192) 8560 rx_buffer->page_offset ^= truesize; 8561 #else 8562 rx_buffer->page_offset += truesize; 8563 #endif 8564 } 8565 8566 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8567 struct igb_rx_buffer *rx_buffer, 8568 struct xdp_buff *xdp, 8569 ktime_t timestamp) 8570 { 8571 #if (PAGE_SIZE < 8192) 8572 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8573 #else 8574 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 8575 xdp->data_hard_start); 8576 #endif 8577 unsigned int size = xdp->data_end - xdp->data; 8578 unsigned int headlen; 8579 struct sk_buff *skb; 8580 8581 /* prefetch first cache line of first page */ 8582 net_prefetch(xdp->data); 8583 8584 /* allocate a skb to store the frags */ 8585 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8586 if (unlikely(!skb)) 8587 return NULL; 8588 8589 if (timestamp) 8590 skb_hwtstamps(skb)->hwtstamp = timestamp; 8591 8592 /* Determine available headroom for copy */ 8593 headlen = size; 8594 if (headlen > IGB_RX_HDR_LEN) 8595 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN); 8596 8597 /* align pull length to size of long to optimize memcpy performance */ 8598 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long))); 8599 8600 /* update all of the pointers */ 8601 size -= headlen; 8602 if (size) { 8603 skb_add_rx_frag(skb, 0, rx_buffer->page, 8604 (xdp->data + headlen) - page_address(rx_buffer->page), 8605 size, truesize); 8606 #if (PAGE_SIZE < 8192) 8607 rx_buffer->page_offset ^= truesize; 8608 #else 8609 rx_buffer->page_offset += truesize; 8610 #endif 8611 } else { 8612 rx_buffer->pagecnt_bias++; 8613 } 8614 8615 return skb; 8616 } 8617 8618 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8619 struct igb_rx_buffer *rx_buffer, 8620 struct xdp_buff *xdp, 8621 ktime_t timestamp) 8622 { 8623 #if (PAGE_SIZE < 8192) 8624 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8625 #else 8626 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8627 SKB_DATA_ALIGN(xdp->data_end - 8628 xdp->data_hard_start); 8629 #endif 8630 unsigned int metasize = xdp->data - xdp->data_meta; 8631 struct sk_buff *skb; 8632 8633 /* prefetch first cache line of first page */ 8634 net_prefetch(xdp->data_meta); 8635 8636 /* build an skb around the page buffer */ 8637 skb = napi_build_skb(xdp->data_hard_start, truesize); 8638 if (unlikely(!skb)) 8639 return NULL; 8640 8641 /* update pointers within the skb to store the data */ 8642 skb_reserve(skb, xdp->data - xdp->data_hard_start); 8643 __skb_put(skb, xdp->data_end - xdp->data); 8644 8645 if (metasize) 8646 skb_metadata_set(skb, metasize); 8647 8648 if (timestamp) 8649 skb_hwtstamps(skb)->hwtstamp = timestamp; 8650 8651 /* update buffer offset */ 8652 #if (PAGE_SIZE < 8192) 8653 rx_buffer->page_offset ^= truesize; 8654 #else 8655 rx_buffer->page_offset += truesize; 8656 #endif 8657 8658 return skb; 8659 } 8660 8661 static int igb_run_xdp(struct igb_adapter *adapter, struct igb_ring *rx_ring, 8662 struct xdp_buff *xdp) 8663 { 8664 int err, result = IGB_XDP_PASS; 8665 struct bpf_prog *xdp_prog; 8666 u32 act; 8667 8668 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 8669 8670 if (!xdp_prog) 8671 goto xdp_out; 8672 8673 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 8674 8675 act = bpf_prog_run_xdp(xdp_prog, xdp); 8676 switch (act) { 8677 case XDP_PASS: 8678 break; 8679 case XDP_TX: 8680 result = igb_xdp_xmit_back(adapter, xdp); 8681 if (result == IGB_XDP_CONSUMED) 8682 goto out_failure; 8683 break; 8684 case XDP_REDIRECT: 8685 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 8686 if (err) 8687 goto out_failure; 8688 result = IGB_XDP_REDIR; 8689 break; 8690 default: 8691 bpf_warn_invalid_xdp_action(adapter->netdev, xdp_prog, act); 8692 fallthrough; 8693 case XDP_ABORTED: 8694 out_failure: 8695 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 8696 fallthrough; 8697 case XDP_DROP: 8698 result = IGB_XDP_CONSUMED; 8699 break; 8700 } 8701 xdp_out: 8702 return result; 8703 } 8704 8705 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring, 8706 unsigned int size) 8707 { 8708 unsigned int truesize; 8709 8710 #if (PAGE_SIZE < 8192) 8711 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 8712 #else 8713 truesize = ring_uses_build_skb(rx_ring) ? 8714 SKB_DATA_ALIGN(IGB_SKB_PAD + size) + 8715 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 8716 SKB_DATA_ALIGN(size); 8717 #endif 8718 return truesize; 8719 } 8720 8721 static void igb_rx_buffer_flip(struct igb_ring *rx_ring, 8722 struct igb_rx_buffer *rx_buffer, 8723 unsigned int size) 8724 { 8725 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size); 8726 #if (PAGE_SIZE < 8192) 8727 rx_buffer->page_offset ^= truesize; 8728 #else 8729 rx_buffer->page_offset += truesize; 8730 #endif 8731 } 8732 8733 static inline void igb_rx_checksum(struct igb_ring *ring, 8734 union e1000_adv_rx_desc *rx_desc, 8735 struct sk_buff *skb) 8736 { 8737 skb_checksum_none_assert(skb); 8738 8739 /* Ignore Checksum bit is set */ 8740 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8741 return; 8742 8743 /* Rx checksum disabled via ethtool */ 8744 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8745 return; 8746 8747 /* TCP/UDP checksum error bit is set */ 8748 if (igb_test_staterr(rx_desc, 8749 E1000_RXDEXT_STATERR_TCPE | 8750 E1000_RXDEXT_STATERR_IPE)) { 8751 /* work around errata with sctp packets where the TCPE aka 8752 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8753 * packets, (aka let the stack check the crc32c) 8754 */ 8755 if (!((skb->len == 60) && 8756 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8757 u64_stats_update_begin(&ring->rx_syncp); 8758 ring->rx_stats.csum_err++; 8759 u64_stats_update_end(&ring->rx_syncp); 8760 } 8761 /* let the stack verify checksum errors */ 8762 return; 8763 } 8764 /* It must be a TCP or UDP packet with a valid checksum */ 8765 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8766 E1000_RXD_STAT_UDPCS)) 8767 skb->ip_summed = CHECKSUM_UNNECESSARY; 8768 8769 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8770 le32_to_cpu(rx_desc->wb.upper.status_error)); 8771 } 8772 8773 static inline void igb_rx_hash(struct igb_ring *ring, 8774 union e1000_adv_rx_desc *rx_desc, 8775 struct sk_buff *skb) 8776 { 8777 if (ring->netdev->features & NETIF_F_RXHASH) 8778 skb_set_hash(skb, 8779 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8780 PKT_HASH_TYPE_L3); 8781 } 8782 8783 /** 8784 * igb_is_non_eop - process handling of non-EOP buffers 8785 * @rx_ring: Rx ring being processed 8786 * @rx_desc: Rx descriptor for current buffer 8787 * 8788 * This function updates next to clean. If the buffer is an EOP buffer 8789 * this function exits returning false, otherwise it will place the 8790 * sk_buff in the next buffer to be chained and return true indicating 8791 * that this is in fact a non-EOP buffer. 8792 **/ 8793 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8794 union e1000_adv_rx_desc *rx_desc) 8795 { 8796 u32 ntc = rx_ring->next_to_clean + 1; 8797 8798 /* fetch, update, and store next to clean */ 8799 ntc = (ntc < rx_ring->count) ? ntc : 0; 8800 rx_ring->next_to_clean = ntc; 8801 8802 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8803 8804 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8805 return false; 8806 8807 return true; 8808 } 8809 8810 /** 8811 * igb_cleanup_headers - Correct corrupted or empty headers 8812 * @rx_ring: rx descriptor ring packet is being transacted on 8813 * @rx_desc: pointer to the EOP Rx descriptor 8814 * @skb: pointer to current skb being fixed 8815 * 8816 * Address the case where we are pulling data in on pages only 8817 * and as such no data is present in the skb header. 8818 * 8819 * In addition if skb is not at least 60 bytes we need to pad it so that 8820 * it is large enough to qualify as a valid Ethernet frame. 8821 * 8822 * Returns true if an error was encountered and skb was freed. 8823 **/ 8824 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8825 union e1000_adv_rx_desc *rx_desc, 8826 struct sk_buff *skb) 8827 { 8828 if (unlikely((igb_test_staterr(rx_desc, 8829 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8830 struct net_device *netdev = rx_ring->netdev; 8831 if (!(netdev->features & NETIF_F_RXALL)) { 8832 dev_kfree_skb_any(skb); 8833 return true; 8834 } 8835 } 8836 8837 /* if eth_skb_pad returns an error the skb was freed */ 8838 if (eth_skb_pad(skb)) 8839 return true; 8840 8841 return false; 8842 } 8843 8844 /** 8845 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8846 * @rx_ring: rx descriptor ring packet is being transacted on 8847 * @rx_desc: pointer to the EOP Rx descriptor 8848 * @skb: pointer to current skb being populated 8849 * 8850 * This function checks the ring, descriptor, and packet information in 8851 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8852 * other fields within the skb. 8853 **/ 8854 void igb_process_skb_fields(struct igb_ring *rx_ring, 8855 union e1000_adv_rx_desc *rx_desc, 8856 struct sk_buff *skb) 8857 { 8858 struct net_device *dev = rx_ring->netdev; 8859 8860 igb_rx_hash(rx_ring, rx_desc, skb); 8861 8862 igb_rx_checksum(rx_ring, rx_desc, skb); 8863 8864 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8865 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8866 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8867 8868 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8869 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8870 u16 vid; 8871 8872 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8873 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8874 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan); 8875 else 8876 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8877 8878 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8879 } 8880 8881 skb_record_rx_queue(skb, rx_ring->queue_index); 8882 8883 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8884 } 8885 8886 static unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8887 { 8888 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8889 } 8890 8891 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8892 const unsigned int size, int *rx_buf_pgcnt) 8893 { 8894 struct igb_rx_buffer *rx_buffer; 8895 8896 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8897 *rx_buf_pgcnt = 8898 #if (PAGE_SIZE < 8192) 8899 page_count(rx_buffer->page); 8900 #else 8901 0; 8902 #endif 8903 prefetchw(rx_buffer->page); 8904 8905 /* we are reusing so sync this buffer for CPU use */ 8906 dma_sync_single_range_for_cpu(rx_ring->dev, 8907 rx_buffer->dma, 8908 rx_buffer->page_offset, 8909 size, 8910 DMA_FROM_DEVICE); 8911 8912 rx_buffer->pagecnt_bias--; 8913 8914 return rx_buffer; 8915 } 8916 8917 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8918 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt) 8919 { 8920 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) { 8921 /* hand second half of page back to the ring */ 8922 igb_reuse_rx_page(rx_ring, rx_buffer); 8923 } else { 8924 /* We are not reusing the buffer so unmap it and free 8925 * any references we are holding to it 8926 */ 8927 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8928 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8929 IGB_RX_DMA_ATTR); 8930 __page_frag_cache_drain(rx_buffer->page, 8931 rx_buffer->pagecnt_bias); 8932 } 8933 8934 /* clear contents of rx_buffer */ 8935 rx_buffer->page = NULL; 8936 } 8937 8938 void igb_finalize_xdp(struct igb_adapter *adapter, unsigned int status) 8939 { 8940 int cpu = smp_processor_id(); 8941 struct netdev_queue *nq; 8942 8943 if (status & IGB_XDP_REDIR) 8944 xdp_do_flush(); 8945 8946 if (status & IGB_XDP_TX) { 8947 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter); 8948 8949 nq = txring_txq(tx_ring); 8950 __netif_tx_lock(nq, cpu); 8951 igb_xdp_ring_update_tail(tx_ring); 8952 __netif_tx_unlock(nq); 8953 } 8954 } 8955 8956 void igb_update_rx_stats(struct igb_q_vector *q_vector, unsigned int packets, 8957 unsigned int bytes) 8958 { 8959 struct igb_ring *ring = q_vector->rx.ring; 8960 8961 u64_stats_update_begin(&ring->rx_syncp); 8962 ring->rx_stats.packets += packets; 8963 ring->rx_stats.bytes += bytes; 8964 u64_stats_update_end(&ring->rx_syncp); 8965 8966 q_vector->rx.total_packets += packets; 8967 q_vector->rx.total_bytes += bytes; 8968 } 8969 8970 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 8971 { 8972 unsigned int total_bytes = 0, total_packets = 0; 8973 struct igb_adapter *adapter = q_vector->adapter; 8974 struct igb_ring *rx_ring = q_vector->rx.ring; 8975 u16 cleaned_count = igb_desc_unused(rx_ring); 8976 struct sk_buff *skb = rx_ring->skb; 8977 unsigned int xdp_xmit = 0; 8978 struct xdp_buff xdp; 8979 u32 frame_sz = 0; 8980 int rx_buf_pgcnt; 8981 int xdp_res = 0; 8982 8983 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 8984 #if (PAGE_SIZE < 8192) 8985 frame_sz = igb_rx_frame_truesize(rx_ring, 0); 8986 #endif 8987 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 8988 8989 while (likely(total_packets < budget)) { 8990 union e1000_adv_rx_desc *rx_desc; 8991 struct igb_rx_buffer *rx_buffer; 8992 ktime_t timestamp = 0; 8993 int pkt_offset = 0; 8994 unsigned int size; 8995 void *pktbuf; 8996 8997 /* return some buffers to hardware, one at a time is too slow */ 8998 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 8999 igb_alloc_rx_buffers(rx_ring, cleaned_count); 9000 cleaned_count = 0; 9001 } 9002 9003 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 9004 size = le16_to_cpu(rx_desc->wb.upper.length); 9005 if (!size) 9006 break; 9007 9008 /* This memory barrier is needed to keep us from reading 9009 * any other fields out of the rx_desc until we know the 9010 * descriptor has been written back 9011 */ 9012 dma_rmb(); 9013 9014 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt); 9015 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset; 9016 9017 /* pull rx packet timestamp if available and valid */ 9018 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 9019 int ts_hdr_len; 9020 9021 ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector, 9022 pktbuf, ×tamp); 9023 9024 pkt_offset += ts_hdr_len; 9025 size -= ts_hdr_len; 9026 } 9027 9028 /* retrieve a buffer from the ring */ 9029 if (!skb) { 9030 unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring); 9031 unsigned int offset = pkt_offset + igb_rx_offset(rx_ring); 9032 9033 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 9034 xdp_buff_clear_frags_flag(&xdp); 9035 #if (PAGE_SIZE > 4096) 9036 /* At larger PAGE_SIZE, frame_sz depend on len size */ 9037 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size); 9038 #endif 9039 xdp_res = igb_run_xdp(adapter, rx_ring, &xdp); 9040 } 9041 9042 if (xdp_res) { 9043 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) { 9044 xdp_xmit |= xdp_res; 9045 igb_rx_buffer_flip(rx_ring, rx_buffer, size); 9046 } else { 9047 rx_buffer->pagecnt_bias++; 9048 } 9049 total_packets++; 9050 total_bytes += size; 9051 } else if (skb) 9052 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 9053 else if (ring_uses_build_skb(rx_ring)) 9054 skb = igb_build_skb(rx_ring, rx_buffer, &xdp, 9055 timestamp); 9056 else 9057 skb = igb_construct_skb(rx_ring, rx_buffer, 9058 &xdp, timestamp); 9059 9060 /* exit if we failed to retrieve a buffer */ 9061 if (!xdp_res && !skb) { 9062 rx_ring->rx_stats.alloc_failed++; 9063 rx_buffer->pagecnt_bias++; 9064 break; 9065 } 9066 9067 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt); 9068 cleaned_count++; 9069 9070 /* fetch next buffer in frame if non-eop */ 9071 if (igb_is_non_eop(rx_ring, rx_desc)) 9072 continue; 9073 9074 /* verify the packet layout is correct */ 9075 if (xdp_res || igb_cleanup_headers(rx_ring, rx_desc, skb)) { 9076 skb = NULL; 9077 continue; 9078 } 9079 9080 /* probably a little skewed due to removing CRC */ 9081 total_bytes += skb->len; 9082 9083 /* populate checksum, timestamp, VLAN, and protocol */ 9084 igb_process_skb_fields(rx_ring, rx_desc, skb); 9085 9086 napi_gro_receive(&q_vector->napi, skb); 9087 9088 /* reset skb pointer */ 9089 skb = NULL; 9090 9091 /* update budget accounting */ 9092 total_packets++; 9093 } 9094 9095 /* place incomplete frames back on ring for completion */ 9096 rx_ring->skb = skb; 9097 9098 if (xdp_xmit) 9099 igb_finalize_xdp(adapter, xdp_xmit); 9100 9101 igb_update_rx_stats(q_vector, total_packets, total_bytes); 9102 9103 if (cleaned_count) 9104 igb_alloc_rx_buffers(rx_ring, cleaned_count); 9105 9106 return total_packets; 9107 } 9108 9109 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 9110 struct igb_rx_buffer *bi) 9111 { 9112 struct page *page = bi->page; 9113 dma_addr_t dma; 9114 9115 /* since we are recycling buffers we should seldom need to alloc */ 9116 if (likely(page)) 9117 return true; 9118 9119 /* alloc new page for storage */ 9120 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 9121 if (unlikely(!page)) { 9122 rx_ring->rx_stats.alloc_failed++; 9123 return false; 9124 } 9125 9126 /* map page for use */ 9127 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 9128 igb_rx_pg_size(rx_ring), 9129 DMA_FROM_DEVICE, 9130 IGB_RX_DMA_ATTR); 9131 9132 /* if mapping failed free memory back to system since 9133 * there isn't much point in holding memory we can't use 9134 */ 9135 if (dma_mapping_error(rx_ring->dev, dma)) { 9136 __free_pages(page, igb_rx_pg_order(rx_ring)); 9137 9138 rx_ring->rx_stats.alloc_failed++; 9139 return false; 9140 } 9141 9142 bi->dma = dma; 9143 bi->page = page; 9144 bi->page_offset = igb_rx_offset(rx_ring); 9145 page_ref_add(page, USHRT_MAX - 1); 9146 bi->pagecnt_bias = USHRT_MAX; 9147 9148 return true; 9149 } 9150 9151 /** 9152 * igb_alloc_rx_buffers - Replace used receive buffers 9153 * @rx_ring: rx descriptor ring to allocate new receive buffers 9154 * @cleaned_count: count of buffers to allocate 9155 **/ 9156 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 9157 { 9158 union e1000_adv_rx_desc *rx_desc; 9159 struct igb_rx_buffer *bi; 9160 u16 i = rx_ring->next_to_use; 9161 u16 bufsz; 9162 9163 /* nothing to do */ 9164 if (!cleaned_count) 9165 return; 9166 9167 rx_desc = IGB_RX_DESC(rx_ring, i); 9168 bi = &rx_ring->rx_buffer_info[i]; 9169 i -= rx_ring->count; 9170 9171 bufsz = igb_rx_bufsz(rx_ring); 9172 9173 do { 9174 if (!igb_alloc_mapped_page(rx_ring, bi)) 9175 break; 9176 9177 /* sync the buffer for use by the device */ 9178 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 9179 bi->page_offset, bufsz, 9180 DMA_FROM_DEVICE); 9181 9182 /* Refresh the desc even if buffer_addrs didn't change 9183 * because each write-back erases this info. 9184 */ 9185 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 9186 9187 rx_desc++; 9188 bi++; 9189 i++; 9190 if (unlikely(!i)) { 9191 rx_desc = IGB_RX_DESC(rx_ring, 0); 9192 bi = rx_ring->rx_buffer_info; 9193 i -= rx_ring->count; 9194 } 9195 9196 /* clear the length for the next_to_use descriptor */ 9197 rx_desc->wb.upper.length = 0; 9198 9199 cleaned_count--; 9200 } while (cleaned_count); 9201 9202 i += rx_ring->count; 9203 9204 if (rx_ring->next_to_use != i) { 9205 /* record the next descriptor to use */ 9206 rx_ring->next_to_use = i; 9207 9208 /* update next to alloc since we have filled the ring */ 9209 rx_ring->next_to_alloc = i; 9210 9211 /* Force memory writes to complete before letting h/w 9212 * know there are new descriptors to fetch. (Only 9213 * applicable for weak-ordered memory model archs, 9214 * such as IA-64). 9215 */ 9216 dma_wmb(); 9217 writel(i, rx_ring->tail); 9218 } 9219 } 9220 9221 /** 9222 * igb_mii_ioctl - 9223 * @netdev: pointer to netdev struct 9224 * @ifr: interface structure 9225 * @cmd: ioctl command to execute 9226 **/ 9227 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9228 { 9229 struct igb_adapter *adapter = netdev_priv(netdev); 9230 struct mii_ioctl_data *data = if_mii(ifr); 9231 9232 if (adapter->hw.phy.media_type != e1000_media_type_copper) 9233 return -EOPNOTSUPP; 9234 9235 switch (cmd) { 9236 case SIOCGMIIPHY: 9237 data->phy_id = adapter->hw.phy.addr; 9238 break; 9239 case SIOCGMIIREG: 9240 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9241 &data->val_out)) 9242 return -EIO; 9243 break; 9244 case SIOCSMIIREG: 9245 if (igb_write_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9246 data->val_in)) 9247 return -EIO; 9248 break; 9249 default: 9250 return -EOPNOTSUPP; 9251 } 9252 return 0; 9253 } 9254 9255 /** 9256 * igb_ioctl - 9257 * @netdev: pointer to netdev struct 9258 * @ifr: interface structure 9259 * @cmd: ioctl command to execute 9260 **/ 9261 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9262 { 9263 switch (cmd) { 9264 case SIOCGMIIPHY: 9265 case SIOCGMIIREG: 9266 case SIOCSMIIREG: 9267 return igb_mii_ioctl(netdev, ifr, cmd); 9268 case SIOCGHWTSTAMP: 9269 return igb_ptp_get_ts_config(netdev, ifr); 9270 case SIOCSHWTSTAMP: 9271 return igb_ptp_set_ts_config(netdev, ifr); 9272 default: 9273 return -EOPNOTSUPP; 9274 } 9275 } 9276 9277 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9278 { 9279 struct igb_adapter *adapter = hw->back; 9280 9281 pci_read_config_word(adapter->pdev, reg, value); 9282 } 9283 9284 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9285 { 9286 struct igb_adapter *adapter = hw->back; 9287 9288 pci_write_config_word(adapter->pdev, reg, *value); 9289 } 9290 9291 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9292 { 9293 struct igb_adapter *adapter = hw->back; 9294 9295 if (pcie_capability_read_word(adapter->pdev, reg, value)) 9296 return -E1000_ERR_CONFIG; 9297 9298 return 0; 9299 } 9300 9301 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9302 { 9303 struct igb_adapter *adapter = hw->back; 9304 9305 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 9306 return -E1000_ERR_CONFIG; 9307 9308 return 0; 9309 } 9310 9311 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 9312 { 9313 struct igb_adapter *adapter = netdev_priv(netdev); 9314 struct e1000_hw *hw = &adapter->hw; 9315 u32 ctrl, rctl; 9316 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 9317 9318 if (enable) { 9319 /* enable VLAN tag insert/strip */ 9320 ctrl = rd32(E1000_CTRL); 9321 ctrl |= E1000_CTRL_VME; 9322 wr32(E1000_CTRL, ctrl); 9323 9324 /* Disable CFI check */ 9325 rctl = rd32(E1000_RCTL); 9326 rctl &= ~E1000_RCTL_CFIEN; 9327 wr32(E1000_RCTL, rctl); 9328 } else { 9329 /* disable VLAN tag insert/strip */ 9330 ctrl = rd32(E1000_CTRL); 9331 ctrl &= ~E1000_CTRL_VME; 9332 wr32(E1000_CTRL, ctrl); 9333 } 9334 9335 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 9336 } 9337 9338 static int igb_vlan_rx_add_vid(struct net_device *netdev, 9339 __be16 proto, u16 vid) 9340 { 9341 struct igb_adapter *adapter = netdev_priv(netdev); 9342 struct e1000_hw *hw = &adapter->hw; 9343 int pf_id = adapter->vfs_allocated_count; 9344 9345 /* add the filter since PF can receive vlans w/o entry in vlvf */ 9346 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9347 igb_vfta_set(hw, vid, pf_id, true, !!vid); 9348 9349 set_bit(vid, adapter->active_vlans); 9350 9351 return 0; 9352 } 9353 9354 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 9355 __be16 proto, u16 vid) 9356 { 9357 struct igb_adapter *adapter = netdev_priv(netdev); 9358 int pf_id = adapter->vfs_allocated_count; 9359 struct e1000_hw *hw = &adapter->hw; 9360 9361 /* remove VID from filter table */ 9362 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9363 igb_vfta_set(hw, vid, pf_id, false, true); 9364 9365 clear_bit(vid, adapter->active_vlans); 9366 9367 return 0; 9368 } 9369 9370 static void igb_restore_vlan(struct igb_adapter *adapter) 9371 { 9372 u16 vid = 1; 9373 9374 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 9375 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 9376 9377 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 9378 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 9379 } 9380 9381 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 9382 { 9383 struct pci_dev *pdev = adapter->pdev; 9384 struct e1000_mac_info *mac = &adapter->hw.mac; 9385 9386 mac->autoneg = 0; 9387 9388 /* Make sure dplx is at most 1 bit and lsb of speed is not set 9389 * for the switch() below to work 9390 */ 9391 if ((spd & 1) || (dplx & ~1)) 9392 goto err_inval; 9393 9394 /* Fiber NIC's only allow 1000 gbps Full duplex 9395 * and 100Mbps Full duplex for 100baseFx sfp 9396 */ 9397 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 9398 switch (spd + dplx) { 9399 case SPEED_10 + DUPLEX_HALF: 9400 case SPEED_10 + DUPLEX_FULL: 9401 case SPEED_100 + DUPLEX_HALF: 9402 goto err_inval; 9403 default: 9404 break; 9405 } 9406 } 9407 9408 switch (spd + dplx) { 9409 case SPEED_10 + DUPLEX_HALF: 9410 mac->forced_speed_duplex = ADVERTISE_10_HALF; 9411 break; 9412 case SPEED_10 + DUPLEX_FULL: 9413 mac->forced_speed_duplex = ADVERTISE_10_FULL; 9414 break; 9415 case SPEED_100 + DUPLEX_HALF: 9416 mac->forced_speed_duplex = ADVERTISE_100_HALF; 9417 break; 9418 case SPEED_100 + DUPLEX_FULL: 9419 mac->forced_speed_duplex = ADVERTISE_100_FULL; 9420 break; 9421 case SPEED_1000 + DUPLEX_FULL: 9422 mac->autoneg = 1; 9423 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 9424 break; 9425 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 9426 default: 9427 goto err_inval; 9428 } 9429 9430 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 9431 adapter->hw.phy.mdix = AUTO_ALL_MODES; 9432 9433 return 0; 9434 9435 err_inval: 9436 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 9437 return -EINVAL; 9438 } 9439 9440 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 9441 bool runtime) 9442 { 9443 struct net_device *netdev = pci_get_drvdata(pdev); 9444 struct igb_adapter *adapter = netdev_priv(netdev); 9445 struct e1000_hw *hw = &adapter->hw; 9446 u32 ctrl, rctl, status; 9447 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 9448 bool wake; 9449 9450 rtnl_lock(); 9451 netif_device_detach(netdev); 9452 9453 if (netif_running(netdev)) 9454 __igb_close(netdev, true); 9455 9456 igb_ptp_suspend(adapter); 9457 9458 igb_clear_interrupt_scheme(adapter); 9459 rtnl_unlock(); 9460 9461 status = rd32(E1000_STATUS); 9462 if (status & E1000_STATUS_LU) 9463 wufc &= ~E1000_WUFC_LNKC; 9464 9465 if (wufc) { 9466 igb_setup_rctl(adapter); 9467 igb_set_rx_mode(netdev); 9468 9469 /* turn on all-multi mode if wake on multicast is enabled */ 9470 if (wufc & E1000_WUFC_MC) { 9471 rctl = rd32(E1000_RCTL); 9472 rctl |= E1000_RCTL_MPE; 9473 wr32(E1000_RCTL, rctl); 9474 } 9475 9476 ctrl = rd32(E1000_CTRL); 9477 ctrl |= E1000_CTRL_ADVD3WUC; 9478 wr32(E1000_CTRL, ctrl); 9479 9480 /* Allow time for pending master requests to run */ 9481 igb_disable_pcie_master(hw); 9482 9483 wr32(E1000_WUC, E1000_WUC_PME_EN); 9484 wr32(E1000_WUFC, wufc); 9485 } else { 9486 wr32(E1000_WUC, 0); 9487 wr32(E1000_WUFC, 0); 9488 } 9489 9490 wake = wufc || adapter->en_mng_pt; 9491 if (!wake) 9492 igb_power_down_link(adapter); 9493 else 9494 igb_power_up_link(adapter); 9495 9496 if (enable_wake) 9497 *enable_wake = wake; 9498 9499 /* Release control of h/w to f/w. If f/w is AMT enabled, this 9500 * would have already happened in close and is redundant. 9501 */ 9502 igb_release_hw_control(adapter); 9503 9504 pci_disable_device(pdev); 9505 9506 return 0; 9507 } 9508 9509 static void igb_deliver_wake_packet(struct net_device *netdev) 9510 { 9511 struct igb_adapter *adapter = netdev_priv(netdev); 9512 struct e1000_hw *hw = &adapter->hw; 9513 struct sk_buff *skb; 9514 u32 wupl; 9515 9516 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 9517 9518 /* WUPM stores only the first 128 bytes of the wake packet. 9519 * Read the packet only if we have the whole thing. 9520 */ 9521 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 9522 return; 9523 9524 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 9525 if (!skb) 9526 return; 9527 9528 skb_put(skb, wupl); 9529 9530 /* Ensure reads are 32-bit aligned */ 9531 wupl = roundup(wupl, 4); 9532 9533 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 9534 9535 skb->protocol = eth_type_trans(skb, netdev); 9536 netif_rx(skb); 9537 } 9538 9539 static int igb_suspend(struct device *dev) 9540 { 9541 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 9542 } 9543 9544 static int __igb_resume(struct device *dev, bool rpm) 9545 { 9546 struct pci_dev *pdev = to_pci_dev(dev); 9547 struct net_device *netdev = pci_get_drvdata(pdev); 9548 struct igb_adapter *adapter = netdev_priv(netdev); 9549 struct e1000_hw *hw = &adapter->hw; 9550 u32 err, val; 9551 9552 pci_set_power_state(pdev, PCI_D0); 9553 pci_restore_state(pdev); 9554 pci_save_state(pdev); 9555 9556 if (!pci_device_is_present(pdev)) 9557 return -ENODEV; 9558 err = pci_enable_device_mem(pdev); 9559 if (err) { 9560 dev_err(&pdev->dev, 9561 "igb: Cannot enable PCI device from suspend\n"); 9562 return err; 9563 } 9564 pci_set_master(pdev); 9565 9566 pci_enable_wake(pdev, PCI_D3hot, 0); 9567 pci_enable_wake(pdev, PCI_D3cold, 0); 9568 9569 if (igb_init_interrupt_scheme(adapter, true)) { 9570 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9571 return -ENOMEM; 9572 } 9573 9574 igb_reset(adapter); 9575 9576 /* let the f/w know that the h/w is now under the control of the 9577 * driver. 9578 */ 9579 igb_get_hw_control(adapter); 9580 9581 val = rd32(E1000_WUS); 9582 if (val & WAKE_PKT_WUS) 9583 igb_deliver_wake_packet(netdev); 9584 9585 wr32(E1000_WUS, ~0); 9586 9587 if (!rpm) 9588 rtnl_lock(); 9589 if (!err && netif_running(netdev)) 9590 err = __igb_open(netdev, true); 9591 9592 if (!err) 9593 netif_device_attach(netdev); 9594 if (!rpm) 9595 rtnl_unlock(); 9596 9597 return err; 9598 } 9599 9600 static int igb_resume(struct device *dev) 9601 { 9602 return __igb_resume(dev, false); 9603 } 9604 9605 static int igb_runtime_idle(struct device *dev) 9606 { 9607 struct net_device *netdev = dev_get_drvdata(dev); 9608 struct igb_adapter *adapter = netdev_priv(netdev); 9609 9610 if (!igb_has_link(adapter)) 9611 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 9612 9613 return -EBUSY; 9614 } 9615 9616 static int igb_runtime_suspend(struct device *dev) 9617 { 9618 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 9619 } 9620 9621 static int igb_runtime_resume(struct device *dev) 9622 { 9623 return __igb_resume(dev, true); 9624 } 9625 9626 static void igb_shutdown(struct pci_dev *pdev) 9627 { 9628 bool wake; 9629 9630 __igb_shutdown(pdev, &wake, 0); 9631 9632 if (system_state == SYSTEM_POWER_OFF) { 9633 pci_wake_from_d3(pdev, wake); 9634 pci_set_power_state(pdev, PCI_D3hot); 9635 } 9636 } 9637 9638 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 9639 { 9640 #ifdef CONFIG_PCI_IOV 9641 int err; 9642 9643 if (num_vfs == 0) { 9644 return igb_disable_sriov(dev, true); 9645 } else { 9646 err = igb_enable_sriov(dev, num_vfs, true); 9647 return err ? err : num_vfs; 9648 } 9649 #endif 9650 return 0; 9651 } 9652 9653 /** 9654 * igb_io_error_detected - called when PCI error is detected 9655 * @pdev: Pointer to PCI device 9656 * @state: The current pci connection state 9657 * 9658 * This function is called after a PCI bus error affecting 9659 * this device has been detected. 9660 **/ 9661 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9662 pci_channel_state_t state) 9663 { 9664 struct net_device *netdev = pci_get_drvdata(pdev); 9665 struct igb_adapter *adapter = netdev_priv(netdev); 9666 9667 if (state == pci_channel_io_normal) { 9668 dev_warn(&pdev->dev, "Non-correctable non-fatal error reported.\n"); 9669 return PCI_ERS_RESULT_CAN_RECOVER; 9670 } 9671 9672 netif_device_detach(netdev); 9673 9674 if (state == pci_channel_io_perm_failure) 9675 return PCI_ERS_RESULT_DISCONNECT; 9676 9677 if (netif_running(netdev)) 9678 igb_down(adapter); 9679 pci_disable_device(pdev); 9680 9681 /* Request a slot reset. */ 9682 return PCI_ERS_RESULT_NEED_RESET; 9683 } 9684 9685 /** 9686 * igb_io_slot_reset - called after the pci bus has been reset. 9687 * @pdev: Pointer to PCI device 9688 * 9689 * Restart the card from scratch, as if from a cold-boot. Implementation 9690 * resembles the first-half of the __igb_resume routine. 9691 **/ 9692 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9693 { 9694 struct net_device *netdev = pci_get_drvdata(pdev); 9695 struct igb_adapter *adapter = netdev_priv(netdev); 9696 struct e1000_hw *hw = &adapter->hw; 9697 pci_ers_result_t result; 9698 9699 if (pci_enable_device_mem(pdev)) { 9700 dev_err(&pdev->dev, 9701 "Cannot re-enable PCI device after reset.\n"); 9702 result = PCI_ERS_RESULT_DISCONNECT; 9703 } else { 9704 pci_set_master(pdev); 9705 pci_restore_state(pdev); 9706 pci_save_state(pdev); 9707 9708 pci_enable_wake(pdev, PCI_D3hot, 0); 9709 pci_enable_wake(pdev, PCI_D3cold, 0); 9710 9711 /* In case of PCI error, adapter lose its HW address 9712 * so we should re-assign it here. 9713 */ 9714 hw->hw_addr = adapter->io_addr; 9715 9716 igb_reset(adapter); 9717 wr32(E1000_WUS, ~0); 9718 result = PCI_ERS_RESULT_RECOVERED; 9719 } 9720 9721 return result; 9722 } 9723 9724 /** 9725 * igb_io_resume - called when traffic can start flowing again. 9726 * @pdev: Pointer to PCI device 9727 * 9728 * This callback is called when the error recovery driver tells us that 9729 * its OK to resume normal operation. Implementation resembles the 9730 * second-half of the __igb_resume routine. 9731 */ 9732 static void igb_io_resume(struct pci_dev *pdev) 9733 { 9734 struct net_device *netdev = pci_get_drvdata(pdev); 9735 struct igb_adapter *adapter = netdev_priv(netdev); 9736 9737 if (netif_running(netdev)) { 9738 if (!test_bit(__IGB_DOWN, &adapter->state)) { 9739 dev_dbg(&pdev->dev, "Resuming from non-fatal error, do nothing.\n"); 9740 return; 9741 } 9742 if (igb_up(adapter)) { 9743 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9744 return; 9745 } 9746 } 9747 9748 netif_device_attach(netdev); 9749 9750 /* let the f/w know that the h/w is now under the control of the 9751 * driver. 9752 */ 9753 igb_get_hw_control(adapter); 9754 } 9755 9756 /** 9757 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9758 * @adapter: Pointer to adapter structure 9759 * @index: Index of the RAR entry which need to be synced with MAC table 9760 **/ 9761 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9762 { 9763 struct e1000_hw *hw = &adapter->hw; 9764 u32 rar_low, rar_high; 9765 u8 *addr = adapter->mac_table[index].addr; 9766 9767 /* HW expects these to be in network order when they are plugged 9768 * into the registers which are little endian. In order to guarantee 9769 * that ordering we need to do an leXX_to_cpup here in order to be 9770 * ready for the byteswap that occurs with writel 9771 */ 9772 rar_low = le32_to_cpup((__le32 *)(addr)); 9773 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9774 9775 /* Indicate to hardware the Address is Valid. */ 9776 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9777 if (is_valid_ether_addr(addr)) 9778 rar_high |= E1000_RAH_AV; 9779 9780 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9781 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9782 9783 switch (hw->mac.type) { 9784 case e1000_82575: 9785 case e1000_i210: 9786 if (adapter->mac_table[index].state & 9787 IGB_MAC_STATE_QUEUE_STEERING) 9788 rar_high |= E1000_RAH_QSEL_ENABLE; 9789 9790 rar_high |= E1000_RAH_POOL_1 * 9791 adapter->mac_table[index].queue; 9792 break; 9793 default: 9794 rar_high |= E1000_RAH_POOL_1 << 9795 adapter->mac_table[index].queue; 9796 break; 9797 } 9798 } 9799 9800 wr32(E1000_RAL(index), rar_low); 9801 wrfl(); 9802 wr32(E1000_RAH(index), rar_high); 9803 wrfl(); 9804 } 9805 9806 static int igb_set_vf_mac(struct igb_adapter *adapter, 9807 int vf, unsigned char *mac_addr) 9808 { 9809 struct e1000_hw *hw = &adapter->hw; 9810 /* VF MAC addresses start at end of receive addresses and moves 9811 * towards the first, as a result a collision should not be possible 9812 */ 9813 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9814 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9815 9816 ether_addr_copy(vf_mac_addr, mac_addr); 9817 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9818 adapter->mac_table[rar_entry].queue = vf; 9819 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9820 igb_rar_set_index(adapter, rar_entry); 9821 9822 return 0; 9823 } 9824 9825 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9826 { 9827 struct igb_adapter *adapter = netdev_priv(netdev); 9828 9829 if (vf >= adapter->vfs_allocated_count) 9830 return -EINVAL; 9831 9832 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9833 * flag and allows to overwrite the MAC via VF netdev. This 9834 * is necessary to allow libvirt a way to restore the original 9835 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9836 * down a VM. 9837 */ 9838 if (is_zero_ether_addr(mac)) { 9839 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9840 dev_info(&adapter->pdev->dev, 9841 "remove administratively set MAC on VF %d\n", 9842 vf); 9843 } else if (is_valid_ether_addr(mac)) { 9844 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9845 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9846 mac, vf); 9847 dev_info(&adapter->pdev->dev, 9848 "Reload the VF driver to make this change effective."); 9849 /* Generate additional warning if PF is down */ 9850 if (test_bit(__IGB_DOWN, &adapter->state)) { 9851 dev_warn(&adapter->pdev->dev, 9852 "The VF MAC address has been set, but the PF device is not up.\n"); 9853 dev_warn(&adapter->pdev->dev, 9854 "Bring the PF device up before attempting to use the VF device.\n"); 9855 } 9856 } else { 9857 return -EINVAL; 9858 } 9859 return igb_set_vf_mac(adapter, vf, mac); 9860 } 9861 9862 static int igb_link_mbps(int internal_link_speed) 9863 { 9864 switch (internal_link_speed) { 9865 case SPEED_100: 9866 return 100; 9867 case SPEED_1000: 9868 return 1000; 9869 default: 9870 return 0; 9871 } 9872 } 9873 9874 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9875 int link_speed) 9876 { 9877 int rf_dec, rf_int; 9878 u32 bcnrc_val; 9879 9880 if (tx_rate != 0) { 9881 /* Calculate the rate factor values to set */ 9882 rf_int = link_speed / tx_rate; 9883 rf_dec = (link_speed - (rf_int * tx_rate)); 9884 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9885 tx_rate; 9886 9887 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9888 bcnrc_val |= FIELD_PREP(E1000_RTTBCNRC_RF_INT_MASK, rf_int); 9889 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9890 } else { 9891 bcnrc_val = 0; 9892 } 9893 9894 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9895 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9896 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9897 */ 9898 wr32(E1000_RTTBCNRM, 0x14); 9899 wr32(E1000_RTTBCNRC, bcnrc_val); 9900 } 9901 9902 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9903 { 9904 int actual_link_speed, i; 9905 bool reset_rate = false; 9906 9907 /* VF TX rate limit was not set or not supported */ 9908 if ((adapter->vf_rate_link_speed == 0) || 9909 (adapter->hw.mac.type != e1000_82576)) 9910 return; 9911 9912 actual_link_speed = igb_link_mbps(adapter->link_speed); 9913 if (actual_link_speed != adapter->vf_rate_link_speed) { 9914 reset_rate = true; 9915 adapter->vf_rate_link_speed = 0; 9916 dev_info(&adapter->pdev->dev, 9917 "Link speed has been changed. VF Transmit rate is disabled\n"); 9918 } 9919 9920 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9921 if (reset_rate) 9922 adapter->vf_data[i].tx_rate = 0; 9923 9924 igb_set_vf_rate_limit(&adapter->hw, i, 9925 adapter->vf_data[i].tx_rate, 9926 actual_link_speed); 9927 } 9928 } 9929 9930 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9931 int min_tx_rate, int max_tx_rate) 9932 { 9933 struct igb_adapter *adapter = netdev_priv(netdev); 9934 struct e1000_hw *hw = &adapter->hw; 9935 int actual_link_speed; 9936 9937 if (hw->mac.type != e1000_82576) 9938 return -EOPNOTSUPP; 9939 9940 if (min_tx_rate) 9941 return -EINVAL; 9942 9943 actual_link_speed = igb_link_mbps(adapter->link_speed); 9944 if ((vf >= adapter->vfs_allocated_count) || 9945 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9946 (max_tx_rate < 0) || 9947 (max_tx_rate > actual_link_speed)) 9948 return -EINVAL; 9949 9950 adapter->vf_rate_link_speed = actual_link_speed; 9951 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 9952 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 9953 9954 return 0; 9955 } 9956 9957 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 9958 bool setting) 9959 { 9960 struct igb_adapter *adapter = netdev_priv(netdev); 9961 struct e1000_hw *hw = &adapter->hw; 9962 u32 reg_val, reg_offset; 9963 9964 if (!adapter->vfs_allocated_count) 9965 return -EOPNOTSUPP; 9966 9967 if (vf >= adapter->vfs_allocated_count) 9968 return -EINVAL; 9969 9970 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 9971 reg_val = rd32(reg_offset); 9972 if (setting) 9973 reg_val |= (BIT(vf) | 9974 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9975 else 9976 reg_val &= ~(BIT(vf) | 9977 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9978 wr32(reg_offset, reg_val); 9979 9980 adapter->vf_data[vf].spoofchk_enabled = setting; 9981 return 0; 9982 } 9983 9984 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 9985 { 9986 struct igb_adapter *adapter = netdev_priv(netdev); 9987 9988 if (vf >= adapter->vfs_allocated_count) 9989 return -EINVAL; 9990 if (adapter->vf_data[vf].trusted == setting) 9991 return 0; 9992 9993 adapter->vf_data[vf].trusted = setting; 9994 9995 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 9996 vf, setting ? "" : "not "); 9997 return 0; 9998 } 9999 10000 static int igb_ndo_get_vf_config(struct net_device *netdev, 10001 int vf, struct ifla_vf_info *ivi) 10002 { 10003 struct igb_adapter *adapter = netdev_priv(netdev); 10004 if (vf >= adapter->vfs_allocated_count) 10005 return -EINVAL; 10006 ivi->vf = vf; 10007 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 10008 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 10009 ivi->min_tx_rate = 0; 10010 ivi->vlan = adapter->vf_data[vf].pf_vlan; 10011 ivi->qos = adapter->vf_data[vf].pf_qos; 10012 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 10013 ivi->trusted = adapter->vf_data[vf].trusted; 10014 return 0; 10015 } 10016 10017 static void igb_vmm_control(struct igb_adapter *adapter) 10018 { 10019 struct e1000_hw *hw = &adapter->hw; 10020 u32 reg; 10021 10022 switch (hw->mac.type) { 10023 case e1000_82575: 10024 case e1000_i210: 10025 case e1000_i211: 10026 case e1000_i354: 10027 default: 10028 /* replication is not supported for 82575 */ 10029 return; 10030 case e1000_82576: 10031 /* notify HW that the MAC is adding vlan tags */ 10032 reg = rd32(E1000_DTXCTL); 10033 reg |= E1000_DTXCTL_VLAN_ADDED; 10034 wr32(E1000_DTXCTL, reg); 10035 fallthrough; 10036 case e1000_82580: 10037 /* enable replication vlan tag stripping */ 10038 reg = rd32(E1000_RPLOLR); 10039 reg |= E1000_RPLOLR_STRVLAN; 10040 wr32(E1000_RPLOLR, reg); 10041 fallthrough; 10042 case e1000_i350: 10043 /* none of the above registers are supported by i350 */ 10044 break; 10045 } 10046 10047 if (adapter->vfs_allocated_count) { 10048 igb_vmdq_set_loopback_pf(hw, true); 10049 igb_vmdq_set_replication_pf(hw, true); 10050 igb_vmdq_set_anti_spoofing_pf(hw, true, 10051 adapter->vfs_allocated_count); 10052 } else { 10053 igb_vmdq_set_loopback_pf(hw, false); 10054 igb_vmdq_set_replication_pf(hw, false); 10055 } 10056 } 10057 10058 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 10059 { 10060 struct e1000_hw *hw = &adapter->hw; 10061 u32 dmac_thr; 10062 u16 hwm; 10063 u32 reg; 10064 10065 if (hw->mac.type > e1000_82580) { 10066 if (adapter->flags & IGB_FLAG_DMAC) { 10067 /* force threshold to 0. */ 10068 wr32(E1000_DMCTXTH, 0); 10069 10070 /* DMA Coalescing high water mark needs to be greater 10071 * than the Rx threshold. Set hwm to PBA - max frame 10072 * size in 16B units, capping it at PBA - 6KB. 10073 */ 10074 hwm = 64 * (pba - 6); 10075 reg = rd32(E1000_FCRTC); 10076 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 10077 reg |= FIELD_PREP(E1000_FCRTC_RTH_COAL_MASK, hwm); 10078 wr32(E1000_FCRTC, reg); 10079 10080 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 10081 * frame size, capping it at PBA - 10KB. 10082 */ 10083 dmac_thr = pba - 10; 10084 reg = rd32(E1000_DMACR); 10085 reg &= ~E1000_DMACR_DMACTHR_MASK; 10086 reg |= FIELD_PREP(E1000_DMACR_DMACTHR_MASK, dmac_thr); 10087 10088 /* transition to L0x or L1 if available..*/ 10089 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 10090 10091 /* watchdog timer= +-1000 usec in 32usec intervals */ 10092 reg |= (1000 >> 5); 10093 10094 /* Disable BMC-to-OS Watchdog Enable */ 10095 if (hw->mac.type != e1000_i354) 10096 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 10097 wr32(E1000_DMACR, reg); 10098 10099 /* no lower threshold to disable 10100 * coalescing(smart fifb)-UTRESH=0 10101 */ 10102 wr32(E1000_DMCRTRH, 0); 10103 10104 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 10105 10106 wr32(E1000_DMCTLX, reg); 10107 10108 /* free space in tx packet buffer to wake from 10109 * DMA coal 10110 */ 10111 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 10112 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 10113 } 10114 10115 if (hw->mac.type >= e1000_i210 || 10116 (adapter->flags & IGB_FLAG_DMAC)) { 10117 reg = rd32(E1000_PCIEMISC); 10118 reg |= E1000_PCIEMISC_LX_DECISION; 10119 wr32(E1000_PCIEMISC, reg); 10120 } /* endif adapter->dmac is not disabled */ 10121 } else if (hw->mac.type == e1000_82580) { 10122 u32 reg = rd32(E1000_PCIEMISC); 10123 10124 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 10125 wr32(E1000_DMACR, 0); 10126 } 10127 } 10128 10129 /** 10130 * igb_read_i2c_byte - Reads 8 bit word over I2C 10131 * @hw: pointer to hardware structure 10132 * @byte_offset: byte offset to read 10133 * @dev_addr: device address 10134 * @data: value read 10135 * 10136 * Performs byte read operation over I2C interface at 10137 * a specified device address. 10138 **/ 10139 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10140 u8 dev_addr, u8 *data) 10141 { 10142 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10143 struct i2c_client *this_client = adapter->i2c_client; 10144 s32 status; 10145 u16 swfw_mask = 0; 10146 10147 if (!this_client) 10148 return E1000_ERR_I2C; 10149 10150 swfw_mask = E1000_SWFW_PHY0_SM; 10151 10152 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10153 return E1000_ERR_SWFW_SYNC; 10154 10155 status = i2c_smbus_read_byte_data(this_client, byte_offset); 10156 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10157 10158 if (status < 0) 10159 return E1000_ERR_I2C; 10160 else { 10161 *data = status; 10162 return 0; 10163 } 10164 } 10165 10166 /** 10167 * igb_write_i2c_byte - Writes 8 bit word over I2C 10168 * @hw: pointer to hardware structure 10169 * @byte_offset: byte offset to write 10170 * @dev_addr: device address 10171 * @data: value to write 10172 * 10173 * Performs byte write operation over I2C interface at 10174 * a specified device address. 10175 **/ 10176 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10177 u8 dev_addr, u8 data) 10178 { 10179 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10180 struct i2c_client *this_client = adapter->i2c_client; 10181 s32 status; 10182 u16 swfw_mask = E1000_SWFW_PHY0_SM; 10183 10184 if (!this_client) 10185 return E1000_ERR_I2C; 10186 10187 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10188 return E1000_ERR_SWFW_SYNC; 10189 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 10190 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10191 10192 if (status) 10193 return E1000_ERR_I2C; 10194 else 10195 return 0; 10196 10197 } 10198 10199 int igb_reinit_queues(struct igb_adapter *adapter) 10200 { 10201 struct net_device *netdev = adapter->netdev; 10202 struct pci_dev *pdev = adapter->pdev; 10203 int err = 0; 10204 10205 if (netif_running(netdev)) 10206 igb_close(netdev); 10207 10208 igb_reset_interrupt_capability(adapter); 10209 10210 if (igb_init_interrupt_scheme(adapter, true)) { 10211 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 10212 return -ENOMEM; 10213 } 10214 10215 if (netif_running(netdev)) 10216 err = igb_open(netdev); 10217 10218 return err; 10219 } 10220 10221 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 10222 { 10223 struct igb_nfc_filter *rule; 10224 10225 spin_lock(&adapter->nfc_lock); 10226 10227 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10228 igb_erase_filter(adapter, rule); 10229 10230 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 10231 igb_erase_filter(adapter, rule); 10232 10233 spin_unlock(&adapter->nfc_lock); 10234 } 10235 10236 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 10237 { 10238 struct igb_nfc_filter *rule; 10239 10240 spin_lock(&adapter->nfc_lock); 10241 10242 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10243 igb_add_filter(adapter, rule); 10244 10245 spin_unlock(&adapter->nfc_lock); 10246 } 10247 10248 static _DEFINE_DEV_PM_OPS(igb_pm_ops, igb_suspend, igb_resume, 10249 igb_runtime_suspend, igb_runtime_resume, 10250 igb_runtime_idle); 10251 10252 static struct pci_driver igb_driver = { 10253 .name = igb_driver_name, 10254 .id_table = igb_pci_tbl, 10255 .probe = igb_probe, 10256 .remove = igb_remove, 10257 .driver.pm = pm_ptr(&igb_pm_ops), 10258 .shutdown = igb_shutdown, 10259 .sriov_configure = igb_pci_sriov_configure, 10260 .err_handler = &igb_err_handler 10261 }; 10262 10263 /* igb_main.c */ 10264