1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/sctp.h> 30 #include <linux/if_ether.h> 31 #include <linux/prefetch.h> 32 #include <linux/bpf.h> 33 #include <linux/bpf_trace.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/etherdevice.h> 36 #ifdef CONFIG_IGB_DCA 37 #include <linux/dca.h> 38 #endif 39 #include <linux/i2c.h> 40 #include "igb.h" 41 42 enum queue_mode { 43 QUEUE_MODE_STRICT_PRIORITY, 44 QUEUE_MODE_STREAM_RESERVATION, 45 }; 46 47 enum tx_queue_prio { 48 TX_QUEUE_PRIO_HIGH, 49 TX_QUEUE_PRIO_LOW, 50 }; 51 52 char igb_driver_name[] = "igb"; 53 static const char igb_driver_string[] = 54 "Intel(R) Gigabit Ethernet Network Driver"; 55 static const char igb_copyright[] = 56 "Copyright (c) 2007-2014 Intel Corporation."; 57 58 static const struct e1000_info *igb_info_tbl[] = { 59 [board_82575] = &e1000_82575_info, 60 }; 61 62 static const struct pci_device_id igb_pci_tbl[] = { 63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 98 /* required last entry */ 99 {0, } 100 }; 101 102 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 103 104 static int igb_setup_all_tx_resources(struct igb_adapter *); 105 static int igb_setup_all_rx_resources(struct igb_adapter *); 106 static void igb_free_all_tx_resources(struct igb_adapter *); 107 static void igb_free_all_rx_resources(struct igb_adapter *); 108 static void igb_setup_mrqc(struct igb_adapter *); 109 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 110 static void igb_remove(struct pci_dev *pdev); 111 static int igb_sw_init(struct igb_adapter *); 112 int igb_open(struct net_device *); 113 int igb_close(struct net_device *); 114 static void igb_configure(struct igb_adapter *); 115 static void igb_configure_tx(struct igb_adapter *); 116 static void igb_configure_rx(struct igb_adapter *); 117 static void igb_clean_all_tx_rings(struct igb_adapter *); 118 static void igb_clean_all_rx_rings(struct igb_adapter *); 119 static void igb_clean_tx_ring(struct igb_ring *); 120 static void igb_clean_rx_ring(struct igb_ring *); 121 static void igb_set_rx_mode(struct net_device *); 122 static void igb_update_phy_info(struct timer_list *); 123 static void igb_watchdog(struct timer_list *); 124 static void igb_watchdog_task(struct work_struct *); 125 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 126 static void igb_get_stats64(struct net_device *dev, 127 struct rtnl_link_stats64 *stats); 128 static int igb_change_mtu(struct net_device *, int); 129 static int igb_set_mac(struct net_device *, void *); 130 static void igb_set_uta(struct igb_adapter *adapter, bool set); 131 static irqreturn_t igb_intr(int irq, void *); 132 static irqreturn_t igb_intr_msi(int irq, void *); 133 static irqreturn_t igb_msix_other(int irq, void *); 134 static irqreturn_t igb_msix_ring(int irq, void *); 135 #ifdef CONFIG_IGB_DCA 136 static void igb_update_dca(struct igb_q_vector *); 137 static void igb_setup_dca(struct igb_adapter *); 138 #endif /* CONFIG_IGB_DCA */ 139 static int igb_poll(struct napi_struct *, int); 140 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 141 static int igb_clean_rx_irq(struct igb_q_vector *, int); 142 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 143 static void igb_tx_timeout(struct net_device *, unsigned int txqueue); 144 static void igb_reset_task(struct work_struct *); 145 static void igb_vlan_mode(struct net_device *netdev, 146 netdev_features_t features); 147 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 148 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 149 static void igb_restore_vlan(struct igb_adapter *); 150 static void igb_rar_set_index(struct igb_adapter *, u32); 151 static void igb_ping_all_vfs(struct igb_adapter *); 152 static void igb_msg_task(struct igb_adapter *); 153 static void igb_vmm_control(struct igb_adapter *); 154 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 155 static void igb_flush_mac_table(struct igb_adapter *); 156 static int igb_available_rars(struct igb_adapter *, u8); 157 static void igb_set_default_mac_filter(struct igb_adapter *); 158 static int igb_uc_sync(struct net_device *, const unsigned char *); 159 static int igb_uc_unsync(struct net_device *, const unsigned char *); 160 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 161 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 162 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 163 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 164 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 165 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 166 bool setting); 167 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 168 bool setting); 169 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 170 struct ifla_vf_info *ivi); 171 static void igb_check_vf_rate_limit(struct igb_adapter *); 172 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 173 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 174 175 #ifdef CONFIG_PCI_IOV 176 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 177 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 178 static int igb_disable_sriov(struct pci_dev *dev); 179 static int igb_pci_disable_sriov(struct pci_dev *dev); 180 #endif 181 182 static int igb_suspend(struct device *); 183 static int igb_resume(struct device *); 184 static int igb_runtime_suspend(struct device *dev); 185 static int igb_runtime_resume(struct device *dev); 186 static int igb_runtime_idle(struct device *dev); 187 static const struct dev_pm_ops igb_pm_ops = { 188 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 189 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 190 igb_runtime_idle) 191 }; 192 static void igb_shutdown(struct pci_dev *); 193 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 194 #ifdef CONFIG_IGB_DCA 195 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 196 static struct notifier_block dca_notifier = { 197 .notifier_call = igb_notify_dca, 198 .next = NULL, 199 .priority = 0 200 }; 201 #endif 202 #ifdef CONFIG_PCI_IOV 203 static unsigned int max_vfs; 204 module_param(max_vfs, uint, 0); 205 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 206 #endif /* CONFIG_PCI_IOV */ 207 208 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 209 pci_channel_state_t); 210 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 211 static void igb_io_resume(struct pci_dev *); 212 213 static const struct pci_error_handlers igb_err_handler = { 214 .error_detected = igb_io_error_detected, 215 .slot_reset = igb_io_slot_reset, 216 .resume = igb_io_resume, 217 }; 218 219 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 220 221 static struct pci_driver igb_driver = { 222 .name = igb_driver_name, 223 .id_table = igb_pci_tbl, 224 .probe = igb_probe, 225 .remove = igb_remove, 226 #ifdef CONFIG_PM 227 .driver.pm = &igb_pm_ops, 228 #endif 229 .shutdown = igb_shutdown, 230 .sriov_configure = igb_pci_sriov_configure, 231 .err_handler = &igb_err_handler 232 }; 233 234 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 235 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 236 MODULE_LICENSE("GPL v2"); 237 238 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 239 static int debug = -1; 240 module_param(debug, int, 0); 241 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 242 243 struct igb_reg_info { 244 u32 ofs; 245 char *name; 246 }; 247 248 static const struct igb_reg_info igb_reg_info_tbl[] = { 249 250 /* General Registers */ 251 {E1000_CTRL, "CTRL"}, 252 {E1000_STATUS, "STATUS"}, 253 {E1000_CTRL_EXT, "CTRL_EXT"}, 254 255 /* Interrupt Registers */ 256 {E1000_ICR, "ICR"}, 257 258 /* RX Registers */ 259 {E1000_RCTL, "RCTL"}, 260 {E1000_RDLEN(0), "RDLEN"}, 261 {E1000_RDH(0), "RDH"}, 262 {E1000_RDT(0), "RDT"}, 263 {E1000_RXDCTL(0), "RXDCTL"}, 264 {E1000_RDBAL(0), "RDBAL"}, 265 {E1000_RDBAH(0), "RDBAH"}, 266 267 /* TX Registers */ 268 {E1000_TCTL, "TCTL"}, 269 {E1000_TDBAL(0), "TDBAL"}, 270 {E1000_TDBAH(0), "TDBAH"}, 271 {E1000_TDLEN(0), "TDLEN"}, 272 {E1000_TDH(0), "TDH"}, 273 {E1000_TDT(0), "TDT"}, 274 {E1000_TXDCTL(0), "TXDCTL"}, 275 {E1000_TDFH, "TDFH"}, 276 {E1000_TDFT, "TDFT"}, 277 {E1000_TDFHS, "TDFHS"}, 278 {E1000_TDFPC, "TDFPC"}, 279 280 /* List Terminator */ 281 {} 282 }; 283 284 /* igb_regdump - register printout routine */ 285 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 286 { 287 int n = 0; 288 char rname[16]; 289 u32 regs[8]; 290 291 switch (reginfo->ofs) { 292 case E1000_RDLEN(0): 293 for (n = 0; n < 4; n++) 294 regs[n] = rd32(E1000_RDLEN(n)); 295 break; 296 case E1000_RDH(0): 297 for (n = 0; n < 4; n++) 298 regs[n] = rd32(E1000_RDH(n)); 299 break; 300 case E1000_RDT(0): 301 for (n = 0; n < 4; n++) 302 regs[n] = rd32(E1000_RDT(n)); 303 break; 304 case E1000_RXDCTL(0): 305 for (n = 0; n < 4; n++) 306 regs[n] = rd32(E1000_RXDCTL(n)); 307 break; 308 case E1000_RDBAL(0): 309 for (n = 0; n < 4; n++) 310 regs[n] = rd32(E1000_RDBAL(n)); 311 break; 312 case E1000_RDBAH(0): 313 for (n = 0; n < 4; n++) 314 regs[n] = rd32(E1000_RDBAH(n)); 315 break; 316 case E1000_TDBAL(0): 317 for (n = 0; n < 4; n++) 318 regs[n] = rd32(E1000_TDBAL(n)); 319 break; 320 case E1000_TDBAH(0): 321 for (n = 0; n < 4; n++) 322 regs[n] = rd32(E1000_TDBAH(n)); 323 break; 324 case E1000_TDLEN(0): 325 for (n = 0; n < 4; n++) 326 regs[n] = rd32(E1000_TDLEN(n)); 327 break; 328 case E1000_TDH(0): 329 for (n = 0; n < 4; n++) 330 regs[n] = rd32(E1000_TDH(n)); 331 break; 332 case E1000_TDT(0): 333 for (n = 0; n < 4; n++) 334 regs[n] = rd32(E1000_TDT(n)); 335 break; 336 case E1000_TXDCTL(0): 337 for (n = 0; n < 4; n++) 338 regs[n] = rd32(E1000_TXDCTL(n)); 339 break; 340 default: 341 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 342 return; 343 } 344 345 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 346 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 347 regs[2], regs[3]); 348 } 349 350 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 351 static void igb_dump(struct igb_adapter *adapter) 352 { 353 struct net_device *netdev = adapter->netdev; 354 struct e1000_hw *hw = &adapter->hw; 355 struct igb_reg_info *reginfo; 356 struct igb_ring *tx_ring; 357 union e1000_adv_tx_desc *tx_desc; 358 struct my_u0 { __le64 a; __le64 b; } *u0; 359 struct igb_ring *rx_ring; 360 union e1000_adv_rx_desc *rx_desc; 361 u32 staterr; 362 u16 i, n; 363 364 if (!netif_msg_hw(adapter)) 365 return; 366 367 /* Print netdevice Info */ 368 if (netdev) { 369 dev_info(&adapter->pdev->dev, "Net device Info\n"); 370 pr_info("Device Name state trans_start\n"); 371 pr_info("%-15s %016lX %016lX\n", netdev->name, 372 netdev->state, dev_trans_start(netdev)); 373 } 374 375 /* Print Registers */ 376 dev_info(&adapter->pdev->dev, "Register Dump\n"); 377 pr_info(" Register Name Value\n"); 378 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 379 reginfo->name; reginfo++) { 380 igb_regdump(hw, reginfo); 381 } 382 383 /* Print TX Ring Summary */ 384 if (!netdev || !netif_running(netdev)) 385 goto exit; 386 387 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 388 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 389 for (n = 0; n < adapter->num_tx_queues; n++) { 390 struct igb_tx_buffer *buffer_info; 391 tx_ring = adapter->tx_ring[n]; 392 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 393 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 394 n, tx_ring->next_to_use, tx_ring->next_to_clean, 395 (u64)dma_unmap_addr(buffer_info, dma), 396 dma_unmap_len(buffer_info, len), 397 buffer_info->next_to_watch, 398 (u64)buffer_info->time_stamp); 399 } 400 401 /* Print TX Rings */ 402 if (!netif_msg_tx_done(adapter)) 403 goto rx_ring_summary; 404 405 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 406 407 /* Transmit Descriptor Formats 408 * 409 * Advanced Transmit Descriptor 410 * +--------------------------------------------------------------+ 411 * 0 | Buffer Address [63:0] | 412 * +--------------------------------------------------------------+ 413 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 414 * +--------------------------------------------------------------+ 415 * 63 46 45 40 39 38 36 35 32 31 24 15 0 416 */ 417 418 for (n = 0; n < adapter->num_tx_queues; n++) { 419 tx_ring = adapter->tx_ring[n]; 420 pr_info("------------------------------------\n"); 421 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 422 pr_info("------------------------------------\n"); 423 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 424 425 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 426 const char *next_desc; 427 struct igb_tx_buffer *buffer_info; 428 tx_desc = IGB_TX_DESC(tx_ring, i); 429 buffer_info = &tx_ring->tx_buffer_info[i]; 430 u0 = (struct my_u0 *)tx_desc; 431 if (i == tx_ring->next_to_use && 432 i == tx_ring->next_to_clean) 433 next_desc = " NTC/U"; 434 else if (i == tx_ring->next_to_use) 435 next_desc = " NTU"; 436 else if (i == tx_ring->next_to_clean) 437 next_desc = " NTC"; 438 else 439 next_desc = ""; 440 441 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 442 i, le64_to_cpu(u0->a), 443 le64_to_cpu(u0->b), 444 (u64)dma_unmap_addr(buffer_info, dma), 445 dma_unmap_len(buffer_info, len), 446 buffer_info->next_to_watch, 447 (u64)buffer_info->time_stamp, 448 buffer_info->skb, next_desc); 449 450 if (netif_msg_pktdata(adapter) && buffer_info->skb) 451 print_hex_dump(KERN_INFO, "", 452 DUMP_PREFIX_ADDRESS, 453 16, 1, buffer_info->skb->data, 454 dma_unmap_len(buffer_info, len), 455 true); 456 } 457 } 458 459 /* Print RX Rings Summary */ 460 rx_ring_summary: 461 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 462 pr_info("Queue [NTU] [NTC]\n"); 463 for (n = 0; n < adapter->num_rx_queues; n++) { 464 rx_ring = adapter->rx_ring[n]; 465 pr_info(" %5d %5X %5X\n", 466 n, rx_ring->next_to_use, rx_ring->next_to_clean); 467 } 468 469 /* Print RX Rings */ 470 if (!netif_msg_rx_status(adapter)) 471 goto exit; 472 473 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 474 475 /* Advanced Receive Descriptor (Read) Format 476 * 63 1 0 477 * +-----------------------------------------------------+ 478 * 0 | Packet Buffer Address [63:1] |A0/NSE| 479 * +----------------------------------------------+------+ 480 * 8 | Header Buffer Address [63:1] | DD | 481 * +-----------------------------------------------------+ 482 * 483 * 484 * Advanced Receive Descriptor (Write-Back) Format 485 * 486 * 63 48 47 32 31 30 21 20 17 16 4 3 0 487 * +------------------------------------------------------+ 488 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 489 * | Checksum Ident | | | | Type | Type | 490 * +------------------------------------------------------+ 491 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 492 * +------------------------------------------------------+ 493 * 63 48 47 32 31 20 19 0 494 */ 495 496 for (n = 0; n < adapter->num_rx_queues; n++) { 497 rx_ring = adapter->rx_ring[n]; 498 pr_info("------------------------------------\n"); 499 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 500 pr_info("------------------------------------\n"); 501 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 502 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 503 504 for (i = 0; i < rx_ring->count; i++) { 505 const char *next_desc; 506 struct igb_rx_buffer *buffer_info; 507 buffer_info = &rx_ring->rx_buffer_info[i]; 508 rx_desc = IGB_RX_DESC(rx_ring, i); 509 u0 = (struct my_u0 *)rx_desc; 510 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 511 512 if (i == rx_ring->next_to_use) 513 next_desc = " NTU"; 514 else if (i == rx_ring->next_to_clean) 515 next_desc = " NTC"; 516 else 517 next_desc = ""; 518 519 if (staterr & E1000_RXD_STAT_DD) { 520 /* Descriptor Done */ 521 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 522 "RWB", i, 523 le64_to_cpu(u0->a), 524 le64_to_cpu(u0->b), 525 next_desc); 526 } else { 527 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 528 "R ", i, 529 le64_to_cpu(u0->a), 530 le64_to_cpu(u0->b), 531 (u64)buffer_info->dma, 532 next_desc); 533 534 if (netif_msg_pktdata(adapter) && 535 buffer_info->dma && buffer_info->page) { 536 print_hex_dump(KERN_INFO, "", 537 DUMP_PREFIX_ADDRESS, 538 16, 1, 539 page_address(buffer_info->page) + 540 buffer_info->page_offset, 541 igb_rx_bufsz(rx_ring), true); 542 } 543 } 544 } 545 } 546 547 exit: 548 return; 549 } 550 551 /** 552 * igb_get_i2c_data - Reads the I2C SDA data bit 553 * @data: opaque pointer to adapter struct 554 * 555 * Returns the I2C data bit value 556 **/ 557 static int igb_get_i2c_data(void *data) 558 { 559 struct igb_adapter *adapter = (struct igb_adapter *)data; 560 struct e1000_hw *hw = &adapter->hw; 561 s32 i2cctl = rd32(E1000_I2CPARAMS); 562 563 return !!(i2cctl & E1000_I2C_DATA_IN); 564 } 565 566 /** 567 * igb_set_i2c_data - Sets the I2C data bit 568 * @data: pointer to hardware structure 569 * @state: I2C data value (0 or 1) to set 570 * 571 * Sets the I2C data bit 572 **/ 573 static void igb_set_i2c_data(void *data, int state) 574 { 575 struct igb_adapter *adapter = (struct igb_adapter *)data; 576 struct e1000_hw *hw = &adapter->hw; 577 s32 i2cctl = rd32(E1000_I2CPARAMS); 578 579 if (state) { 580 i2cctl |= E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N; 581 } else { 582 i2cctl &= ~E1000_I2C_DATA_OE_N; 583 i2cctl &= ~E1000_I2C_DATA_OUT; 584 } 585 586 wr32(E1000_I2CPARAMS, i2cctl); 587 wrfl(); 588 } 589 590 /** 591 * igb_set_i2c_clk - Sets the I2C SCL clock 592 * @data: pointer to hardware structure 593 * @state: state to set clock 594 * 595 * Sets the I2C clock line to state 596 **/ 597 static void igb_set_i2c_clk(void *data, int state) 598 { 599 struct igb_adapter *adapter = (struct igb_adapter *)data; 600 struct e1000_hw *hw = &adapter->hw; 601 s32 i2cctl = rd32(E1000_I2CPARAMS); 602 603 if (state) { 604 i2cctl |= E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N; 605 } else { 606 i2cctl &= ~E1000_I2C_CLK_OUT; 607 i2cctl &= ~E1000_I2C_CLK_OE_N; 608 } 609 wr32(E1000_I2CPARAMS, i2cctl); 610 wrfl(); 611 } 612 613 /** 614 * igb_get_i2c_clk - Gets the I2C SCL clock state 615 * @data: pointer to hardware structure 616 * 617 * Gets the I2C clock state 618 **/ 619 static int igb_get_i2c_clk(void *data) 620 { 621 struct igb_adapter *adapter = (struct igb_adapter *)data; 622 struct e1000_hw *hw = &adapter->hw; 623 s32 i2cctl = rd32(E1000_I2CPARAMS); 624 625 return !!(i2cctl & E1000_I2C_CLK_IN); 626 } 627 628 static const struct i2c_algo_bit_data igb_i2c_algo = { 629 .setsda = igb_set_i2c_data, 630 .setscl = igb_set_i2c_clk, 631 .getsda = igb_get_i2c_data, 632 .getscl = igb_get_i2c_clk, 633 .udelay = 5, 634 .timeout = 20, 635 }; 636 637 /** 638 * igb_get_hw_dev - return device 639 * @hw: pointer to hardware structure 640 * 641 * used by hardware layer to print debugging information 642 **/ 643 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 644 { 645 struct igb_adapter *adapter = hw->back; 646 return adapter->netdev; 647 } 648 649 /** 650 * igb_init_module - Driver Registration Routine 651 * 652 * igb_init_module is the first routine called when the driver is 653 * loaded. All it does is register with the PCI subsystem. 654 **/ 655 static int __init igb_init_module(void) 656 { 657 int ret; 658 659 pr_info("%s\n", igb_driver_string); 660 pr_info("%s\n", igb_copyright); 661 662 #ifdef CONFIG_IGB_DCA 663 dca_register_notify(&dca_notifier); 664 #endif 665 ret = pci_register_driver(&igb_driver); 666 return ret; 667 } 668 669 module_init(igb_init_module); 670 671 /** 672 * igb_exit_module - Driver Exit Cleanup Routine 673 * 674 * igb_exit_module is called just before the driver is removed 675 * from memory. 676 **/ 677 static void __exit igb_exit_module(void) 678 { 679 #ifdef CONFIG_IGB_DCA 680 dca_unregister_notify(&dca_notifier); 681 #endif 682 pci_unregister_driver(&igb_driver); 683 } 684 685 module_exit(igb_exit_module); 686 687 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 688 /** 689 * igb_cache_ring_register - Descriptor ring to register mapping 690 * @adapter: board private structure to initialize 691 * 692 * Once we know the feature-set enabled for the device, we'll cache 693 * the register offset the descriptor ring is assigned to. 694 **/ 695 static void igb_cache_ring_register(struct igb_adapter *adapter) 696 { 697 int i = 0, j = 0; 698 u32 rbase_offset = adapter->vfs_allocated_count; 699 700 switch (adapter->hw.mac.type) { 701 case e1000_82576: 702 /* The queues are allocated for virtualization such that VF 0 703 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 704 * In order to avoid collision we start at the first free queue 705 * and continue consuming queues in the same sequence 706 */ 707 if (adapter->vfs_allocated_count) { 708 for (; i < adapter->rss_queues; i++) 709 adapter->rx_ring[i]->reg_idx = rbase_offset + 710 Q_IDX_82576(i); 711 } 712 fallthrough; 713 case e1000_82575: 714 case e1000_82580: 715 case e1000_i350: 716 case e1000_i354: 717 case e1000_i210: 718 case e1000_i211: 719 default: 720 for (; i < adapter->num_rx_queues; i++) 721 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 722 for (; j < adapter->num_tx_queues; j++) 723 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 724 break; 725 } 726 } 727 728 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 729 { 730 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 731 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 732 u32 value = 0; 733 734 if (E1000_REMOVED(hw_addr)) 735 return ~value; 736 737 value = readl(&hw_addr[reg]); 738 739 /* reads should not return all F's */ 740 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 741 struct net_device *netdev = igb->netdev; 742 hw->hw_addr = NULL; 743 netdev_err(netdev, "PCIe link lost\n"); 744 WARN(pci_device_is_present(igb->pdev), 745 "igb: Failed to read reg 0x%x!\n", reg); 746 } 747 748 return value; 749 } 750 751 /** 752 * igb_write_ivar - configure ivar for given MSI-X vector 753 * @hw: pointer to the HW structure 754 * @msix_vector: vector number we are allocating to a given ring 755 * @index: row index of IVAR register to write within IVAR table 756 * @offset: column offset of in IVAR, should be multiple of 8 757 * 758 * This function is intended to handle the writing of the IVAR register 759 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 760 * each containing an cause allocation for an Rx and Tx ring, and a 761 * variable number of rows depending on the number of queues supported. 762 **/ 763 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 764 int index, int offset) 765 { 766 u32 ivar = array_rd32(E1000_IVAR0, index); 767 768 /* clear any bits that are currently set */ 769 ivar &= ~((u32)0xFF << offset); 770 771 /* write vector and valid bit */ 772 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 773 774 array_wr32(E1000_IVAR0, index, ivar); 775 } 776 777 #define IGB_N0_QUEUE -1 778 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 779 { 780 struct igb_adapter *adapter = q_vector->adapter; 781 struct e1000_hw *hw = &adapter->hw; 782 int rx_queue = IGB_N0_QUEUE; 783 int tx_queue = IGB_N0_QUEUE; 784 u32 msixbm = 0; 785 786 if (q_vector->rx.ring) 787 rx_queue = q_vector->rx.ring->reg_idx; 788 if (q_vector->tx.ring) 789 tx_queue = q_vector->tx.ring->reg_idx; 790 791 switch (hw->mac.type) { 792 case e1000_82575: 793 /* The 82575 assigns vectors using a bitmask, which matches the 794 * bitmask for the EICR/EIMS/EIMC registers. To assign one 795 * or more queues to a vector, we write the appropriate bits 796 * into the MSIXBM register for that vector. 797 */ 798 if (rx_queue > IGB_N0_QUEUE) 799 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 800 if (tx_queue > IGB_N0_QUEUE) 801 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 802 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 803 msixbm |= E1000_EIMS_OTHER; 804 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 805 q_vector->eims_value = msixbm; 806 break; 807 case e1000_82576: 808 /* 82576 uses a table that essentially consists of 2 columns 809 * with 8 rows. The ordering is column-major so we use the 810 * lower 3 bits as the row index, and the 4th bit as the 811 * column offset. 812 */ 813 if (rx_queue > IGB_N0_QUEUE) 814 igb_write_ivar(hw, msix_vector, 815 rx_queue & 0x7, 816 (rx_queue & 0x8) << 1); 817 if (tx_queue > IGB_N0_QUEUE) 818 igb_write_ivar(hw, msix_vector, 819 tx_queue & 0x7, 820 ((tx_queue & 0x8) << 1) + 8); 821 q_vector->eims_value = BIT(msix_vector); 822 break; 823 case e1000_82580: 824 case e1000_i350: 825 case e1000_i354: 826 case e1000_i210: 827 case e1000_i211: 828 /* On 82580 and newer adapters the scheme is similar to 82576 829 * however instead of ordering column-major we have things 830 * ordered row-major. So we traverse the table by using 831 * bit 0 as the column offset, and the remaining bits as the 832 * row index. 833 */ 834 if (rx_queue > IGB_N0_QUEUE) 835 igb_write_ivar(hw, msix_vector, 836 rx_queue >> 1, 837 (rx_queue & 0x1) << 4); 838 if (tx_queue > IGB_N0_QUEUE) 839 igb_write_ivar(hw, msix_vector, 840 tx_queue >> 1, 841 ((tx_queue & 0x1) << 4) + 8); 842 q_vector->eims_value = BIT(msix_vector); 843 break; 844 default: 845 BUG(); 846 break; 847 } 848 849 /* add q_vector eims value to global eims_enable_mask */ 850 adapter->eims_enable_mask |= q_vector->eims_value; 851 852 /* configure q_vector to set itr on first interrupt */ 853 q_vector->set_itr = 1; 854 } 855 856 /** 857 * igb_configure_msix - Configure MSI-X hardware 858 * @adapter: board private structure to initialize 859 * 860 * igb_configure_msix sets up the hardware to properly 861 * generate MSI-X interrupts. 862 **/ 863 static void igb_configure_msix(struct igb_adapter *adapter) 864 { 865 u32 tmp; 866 int i, vector = 0; 867 struct e1000_hw *hw = &adapter->hw; 868 869 adapter->eims_enable_mask = 0; 870 871 /* set vector for other causes, i.e. link changes */ 872 switch (hw->mac.type) { 873 case e1000_82575: 874 tmp = rd32(E1000_CTRL_EXT); 875 /* enable MSI-X PBA support*/ 876 tmp |= E1000_CTRL_EXT_PBA_CLR; 877 878 /* Auto-Mask interrupts upon ICR read. */ 879 tmp |= E1000_CTRL_EXT_EIAME; 880 tmp |= E1000_CTRL_EXT_IRCA; 881 882 wr32(E1000_CTRL_EXT, tmp); 883 884 /* enable msix_other interrupt */ 885 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 886 adapter->eims_other = E1000_EIMS_OTHER; 887 888 break; 889 890 case e1000_82576: 891 case e1000_82580: 892 case e1000_i350: 893 case e1000_i354: 894 case e1000_i210: 895 case e1000_i211: 896 /* Turn on MSI-X capability first, or our settings 897 * won't stick. And it will take days to debug. 898 */ 899 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 900 E1000_GPIE_PBA | E1000_GPIE_EIAME | 901 E1000_GPIE_NSICR); 902 903 /* enable msix_other interrupt */ 904 adapter->eims_other = BIT(vector); 905 tmp = (vector++ | E1000_IVAR_VALID) << 8; 906 907 wr32(E1000_IVAR_MISC, tmp); 908 break; 909 default: 910 /* do nothing, since nothing else supports MSI-X */ 911 break; 912 } /* switch (hw->mac.type) */ 913 914 adapter->eims_enable_mask |= adapter->eims_other; 915 916 for (i = 0; i < adapter->num_q_vectors; i++) 917 igb_assign_vector(adapter->q_vector[i], vector++); 918 919 wrfl(); 920 } 921 922 /** 923 * igb_request_msix - Initialize MSI-X interrupts 924 * @adapter: board private structure to initialize 925 * 926 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 927 * kernel. 928 **/ 929 static int igb_request_msix(struct igb_adapter *adapter) 930 { 931 unsigned int num_q_vectors = adapter->num_q_vectors; 932 struct net_device *netdev = adapter->netdev; 933 int i, err = 0, vector = 0, free_vector = 0; 934 935 err = request_irq(adapter->msix_entries[vector].vector, 936 igb_msix_other, 0, netdev->name, adapter); 937 if (err) 938 goto err_out; 939 940 if (num_q_vectors > MAX_Q_VECTORS) { 941 num_q_vectors = MAX_Q_VECTORS; 942 dev_warn(&adapter->pdev->dev, 943 "The number of queue vectors (%d) is higher than max allowed (%d)\n", 944 adapter->num_q_vectors, MAX_Q_VECTORS); 945 } 946 for (i = 0; i < num_q_vectors; i++) { 947 struct igb_q_vector *q_vector = adapter->q_vector[i]; 948 949 vector++; 950 951 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 952 953 if (q_vector->rx.ring && q_vector->tx.ring) 954 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 955 q_vector->rx.ring->queue_index); 956 else if (q_vector->tx.ring) 957 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 958 q_vector->tx.ring->queue_index); 959 else if (q_vector->rx.ring) 960 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 961 q_vector->rx.ring->queue_index); 962 else 963 sprintf(q_vector->name, "%s-unused", netdev->name); 964 965 err = request_irq(adapter->msix_entries[vector].vector, 966 igb_msix_ring, 0, q_vector->name, 967 q_vector); 968 if (err) 969 goto err_free; 970 } 971 972 igb_configure_msix(adapter); 973 return 0; 974 975 err_free: 976 /* free already assigned IRQs */ 977 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 978 979 vector--; 980 for (i = 0; i < vector; i++) { 981 free_irq(adapter->msix_entries[free_vector++].vector, 982 adapter->q_vector[i]); 983 } 984 err_out: 985 return err; 986 } 987 988 /** 989 * igb_free_q_vector - Free memory allocated for specific interrupt vector 990 * @adapter: board private structure to initialize 991 * @v_idx: Index of vector to be freed 992 * 993 * This function frees the memory allocated to the q_vector. 994 **/ 995 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 996 { 997 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 998 999 adapter->q_vector[v_idx] = NULL; 1000 1001 /* igb_get_stats64() might access the rings on this vector, 1002 * we must wait a grace period before freeing it. 1003 */ 1004 if (q_vector) 1005 kfree_rcu(q_vector, rcu); 1006 } 1007 1008 /** 1009 * igb_reset_q_vector - Reset config for interrupt vector 1010 * @adapter: board private structure to initialize 1011 * @v_idx: Index of vector to be reset 1012 * 1013 * If NAPI is enabled it will delete any references to the 1014 * NAPI struct. This is preparation for igb_free_q_vector. 1015 **/ 1016 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1017 { 1018 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1019 1020 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1021 * allocated. So, q_vector is NULL so we should stop here. 1022 */ 1023 if (!q_vector) 1024 return; 1025 1026 if (q_vector->tx.ring) 1027 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1028 1029 if (q_vector->rx.ring) 1030 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1031 1032 netif_napi_del(&q_vector->napi); 1033 1034 } 1035 1036 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1037 { 1038 int v_idx = adapter->num_q_vectors; 1039 1040 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1041 pci_disable_msix(adapter->pdev); 1042 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1043 pci_disable_msi(adapter->pdev); 1044 1045 while (v_idx--) 1046 igb_reset_q_vector(adapter, v_idx); 1047 } 1048 1049 /** 1050 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1051 * @adapter: board private structure to initialize 1052 * 1053 * This function frees the memory allocated to the q_vectors. In addition if 1054 * NAPI is enabled it will delete any references to the NAPI struct prior 1055 * to freeing the q_vector. 1056 **/ 1057 static void igb_free_q_vectors(struct igb_adapter *adapter) 1058 { 1059 int v_idx = adapter->num_q_vectors; 1060 1061 adapter->num_tx_queues = 0; 1062 adapter->num_rx_queues = 0; 1063 adapter->num_q_vectors = 0; 1064 1065 while (v_idx--) { 1066 igb_reset_q_vector(adapter, v_idx); 1067 igb_free_q_vector(adapter, v_idx); 1068 } 1069 } 1070 1071 /** 1072 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1073 * @adapter: board private structure to initialize 1074 * 1075 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1076 * MSI-X interrupts allocated. 1077 */ 1078 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1079 { 1080 igb_free_q_vectors(adapter); 1081 igb_reset_interrupt_capability(adapter); 1082 } 1083 1084 /** 1085 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1086 * @adapter: board private structure to initialize 1087 * @msix: boolean value of MSIX capability 1088 * 1089 * Attempt to configure interrupts using the best available 1090 * capabilities of the hardware and kernel. 1091 **/ 1092 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1093 { 1094 int err; 1095 int numvecs, i; 1096 1097 if (!msix) 1098 goto msi_only; 1099 adapter->flags |= IGB_FLAG_HAS_MSIX; 1100 1101 /* Number of supported queues. */ 1102 adapter->num_rx_queues = adapter->rss_queues; 1103 if (adapter->vfs_allocated_count) 1104 adapter->num_tx_queues = 1; 1105 else 1106 adapter->num_tx_queues = adapter->rss_queues; 1107 1108 /* start with one vector for every Rx queue */ 1109 numvecs = adapter->num_rx_queues; 1110 1111 /* if Tx handler is separate add 1 for every Tx queue */ 1112 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1113 numvecs += adapter->num_tx_queues; 1114 1115 /* store the number of vectors reserved for queues */ 1116 adapter->num_q_vectors = numvecs; 1117 1118 /* add 1 vector for link status interrupts */ 1119 numvecs++; 1120 for (i = 0; i < numvecs; i++) 1121 adapter->msix_entries[i].entry = i; 1122 1123 err = pci_enable_msix_range(adapter->pdev, 1124 adapter->msix_entries, 1125 numvecs, 1126 numvecs); 1127 if (err > 0) 1128 return; 1129 1130 igb_reset_interrupt_capability(adapter); 1131 1132 /* If we can't do MSI-X, try MSI */ 1133 msi_only: 1134 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1135 #ifdef CONFIG_PCI_IOV 1136 /* disable SR-IOV for non MSI-X configurations */ 1137 if (adapter->vf_data) { 1138 struct e1000_hw *hw = &adapter->hw; 1139 /* disable iov and allow time for transactions to clear */ 1140 pci_disable_sriov(adapter->pdev); 1141 msleep(500); 1142 1143 kfree(adapter->vf_mac_list); 1144 adapter->vf_mac_list = NULL; 1145 kfree(adapter->vf_data); 1146 adapter->vf_data = NULL; 1147 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1148 wrfl(); 1149 msleep(100); 1150 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1151 } 1152 #endif 1153 adapter->vfs_allocated_count = 0; 1154 adapter->rss_queues = 1; 1155 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1156 adapter->num_rx_queues = 1; 1157 adapter->num_tx_queues = 1; 1158 adapter->num_q_vectors = 1; 1159 if (!pci_enable_msi(adapter->pdev)) 1160 adapter->flags |= IGB_FLAG_HAS_MSI; 1161 } 1162 1163 static void igb_add_ring(struct igb_ring *ring, 1164 struct igb_ring_container *head) 1165 { 1166 head->ring = ring; 1167 head->count++; 1168 } 1169 1170 /** 1171 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1172 * @adapter: board private structure to initialize 1173 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1174 * @v_idx: index of vector in adapter struct 1175 * @txr_count: total number of Tx rings to allocate 1176 * @txr_idx: index of first Tx ring to allocate 1177 * @rxr_count: total number of Rx rings to allocate 1178 * @rxr_idx: index of first Rx ring to allocate 1179 * 1180 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1181 **/ 1182 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1183 int v_count, int v_idx, 1184 int txr_count, int txr_idx, 1185 int rxr_count, int rxr_idx) 1186 { 1187 struct igb_q_vector *q_vector; 1188 struct igb_ring *ring; 1189 int ring_count; 1190 size_t size; 1191 1192 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1193 if (txr_count > 1 || rxr_count > 1) 1194 return -ENOMEM; 1195 1196 ring_count = txr_count + rxr_count; 1197 size = kmalloc_size_roundup(struct_size(q_vector, ring, ring_count)); 1198 1199 /* allocate q_vector and rings */ 1200 q_vector = adapter->q_vector[v_idx]; 1201 if (!q_vector) { 1202 q_vector = kzalloc(size, GFP_KERNEL); 1203 } else if (size > ksize(q_vector)) { 1204 struct igb_q_vector *new_q_vector; 1205 1206 new_q_vector = kzalloc(size, GFP_KERNEL); 1207 if (new_q_vector) 1208 kfree_rcu(q_vector, rcu); 1209 q_vector = new_q_vector; 1210 } else { 1211 memset(q_vector, 0, size); 1212 } 1213 if (!q_vector) 1214 return -ENOMEM; 1215 1216 /* initialize NAPI */ 1217 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll); 1218 1219 /* tie q_vector and adapter together */ 1220 adapter->q_vector[v_idx] = q_vector; 1221 q_vector->adapter = adapter; 1222 1223 /* initialize work limits */ 1224 q_vector->tx.work_limit = adapter->tx_work_limit; 1225 1226 /* initialize ITR configuration */ 1227 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1228 q_vector->itr_val = IGB_START_ITR; 1229 1230 /* initialize pointer to rings */ 1231 ring = q_vector->ring; 1232 1233 /* intialize ITR */ 1234 if (rxr_count) { 1235 /* rx or rx/tx vector */ 1236 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1237 q_vector->itr_val = adapter->rx_itr_setting; 1238 } else { 1239 /* tx only vector */ 1240 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1241 q_vector->itr_val = adapter->tx_itr_setting; 1242 } 1243 1244 if (txr_count) { 1245 /* assign generic ring traits */ 1246 ring->dev = &adapter->pdev->dev; 1247 ring->netdev = adapter->netdev; 1248 1249 /* configure backlink on ring */ 1250 ring->q_vector = q_vector; 1251 1252 /* update q_vector Tx values */ 1253 igb_add_ring(ring, &q_vector->tx); 1254 1255 /* For 82575, context index must be unique per ring. */ 1256 if (adapter->hw.mac.type == e1000_82575) 1257 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1258 1259 /* apply Tx specific ring traits */ 1260 ring->count = adapter->tx_ring_count; 1261 ring->queue_index = txr_idx; 1262 1263 ring->cbs_enable = false; 1264 ring->idleslope = 0; 1265 ring->sendslope = 0; 1266 ring->hicredit = 0; 1267 ring->locredit = 0; 1268 1269 u64_stats_init(&ring->tx_syncp); 1270 u64_stats_init(&ring->tx_syncp2); 1271 1272 /* assign ring to adapter */ 1273 adapter->tx_ring[txr_idx] = ring; 1274 1275 /* push pointer to next ring */ 1276 ring++; 1277 } 1278 1279 if (rxr_count) { 1280 /* assign generic ring traits */ 1281 ring->dev = &adapter->pdev->dev; 1282 ring->netdev = adapter->netdev; 1283 1284 /* configure backlink on ring */ 1285 ring->q_vector = q_vector; 1286 1287 /* update q_vector Rx values */ 1288 igb_add_ring(ring, &q_vector->rx); 1289 1290 /* set flag indicating ring supports SCTP checksum offload */ 1291 if (adapter->hw.mac.type >= e1000_82576) 1292 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1293 1294 /* On i350, i354, i210, and i211, loopback VLAN packets 1295 * have the tag byte-swapped. 1296 */ 1297 if (adapter->hw.mac.type >= e1000_i350) 1298 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1299 1300 /* apply Rx specific ring traits */ 1301 ring->count = adapter->rx_ring_count; 1302 ring->queue_index = rxr_idx; 1303 1304 u64_stats_init(&ring->rx_syncp); 1305 1306 /* assign ring to adapter */ 1307 adapter->rx_ring[rxr_idx] = ring; 1308 } 1309 1310 return 0; 1311 } 1312 1313 1314 /** 1315 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1316 * @adapter: board private structure to initialize 1317 * 1318 * We allocate one q_vector per queue interrupt. If allocation fails we 1319 * return -ENOMEM. 1320 **/ 1321 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1322 { 1323 int q_vectors = adapter->num_q_vectors; 1324 int rxr_remaining = adapter->num_rx_queues; 1325 int txr_remaining = adapter->num_tx_queues; 1326 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1327 int err; 1328 1329 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1330 for (; rxr_remaining; v_idx++) { 1331 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1332 0, 0, 1, rxr_idx); 1333 1334 if (err) 1335 goto err_out; 1336 1337 /* update counts and index */ 1338 rxr_remaining--; 1339 rxr_idx++; 1340 } 1341 } 1342 1343 for (; v_idx < q_vectors; v_idx++) { 1344 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1345 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1346 1347 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1348 tqpv, txr_idx, rqpv, rxr_idx); 1349 1350 if (err) 1351 goto err_out; 1352 1353 /* update counts and index */ 1354 rxr_remaining -= rqpv; 1355 txr_remaining -= tqpv; 1356 rxr_idx++; 1357 txr_idx++; 1358 } 1359 1360 return 0; 1361 1362 err_out: 1363 adapter->num_tx_queues = 0; 1364 adapter->num_rx_queues = 0; 1365 adapter->num_q_vectors = 0; 1366 1367 while (v_idx--) 1368 igb_free_q_vector(adapter, v_idx); 1369 1370 return -ENOMEM; 1371 } 1372 1373 /** 1374 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1375 * @adapter: board private structure to initialize 1376 * @msix: boolean value of MSIX capability 1377 * 1378 * This function initializes the interrupts and allocates all of the queues. 1379 **/ 1380 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1381 { 1382 struct pci_dev *pdev = adapter->pdev; 1383 int err; 1384 1385 igb_set_interrupt_capability(adapter, msix); 1386 1387 err = igb_alloc_q_vectors(adapter); 1388 if (err) { 1389 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1390 goto err_alloc_q_vectors; 1391 } 1392 1393 igb_cache_ring_register(adapter); 1394 1395 return 0; 1396 1397 err_alloc_q_vectors: 1398 igb_reset_interrupt_capability(adapter); 1399 return err; 1400 } 1401 1402 /** 1403 * igb_request_irq - initialize interrupts 1404 * @adapter: board private structure to initialize 1405 * 1406 * Attempts to configure interrupts using the best available 1407 * capabilities of the hardware and kernel. 1408 **/ 1409 static int igb_request_irq(struct igb_adapter *adapter) 1410 { 1411 struct net_device *netdev = adapter->netdev; 1412 struct pci_dev *pdev = adapter->pdev; 1413 int err = 0; 1414 1415 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1416 err = igb_request_msix(adapter); 1417 if (!err) 1418 goto request_done; 1419 /* fall back to MSI */ 1420 igb_free_all_tx_resources(adapter); 1421 igb_free_all_rx_resources(adapter); 1422 1423 igb_clear_interrupt_scheme(adapter); 1424 err = igb_init_interrupt_scheme(adapter, false); 1425 if (err) 1426 goto request_done; 1427 1428 igb_setup_all_tx_resources(adapter); 1429 igb_setup_all_rx_resources(adapter); 1430 igb_configure(adapter); 1431 } 1432 1433 igb_assign_vector(adapter->q_vector[0], 0); 1434 1435 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1436 err = request_irq(pdev->irq, igb_intr_msi, 0, 1437 netdev->name, adapter); 1438 if (!err) 1439 goto request_done; 1440 1441 /* fall back to legacy interrupts */ 1442 igb_reset_interrupt_capability(adapter); 1443 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1444 } 1445 1446 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1447 netdev->name, adapter); 1448 1449 if (err) 1450 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1451 err); 1452 1453 request_done: 1454 return err; 1455 } 1456 1457 static void igb_free_irq(struct igb_adapter *adapter) 1458 { 1459 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1460 int vector = 0, i; 1461 1462 free_irq(adapter->msix_entries[vector++].vector, adapter); 1463 1464 for (i = 0; i < adapter->num_q_vectors; i++) 1465 free_irq(adapter->msix_entries[vector++].vector, 1466 adapter->q_vector[i]); 1467 } else { 1468 free_irq(adapter->pdev->irq, adapter); 1469 } 1470 } 1471 1472 /** 1473 * igb_irq_disable - Mask off interrupt generation on the NIC 1474 * @adapter: board private structure 1475 **/ 1476 static void igb_irq_disable(struct igb_adapter *adapter) 1477 { 1478 struct e1000_hw *hw = &adapter->hw; 1479 1480 /* we need to be careful when disabling interrupts. The VFs are also 1481 * mapped into these registers and so clearing the bits can cause 1482 * issues on the VF drivers so we only need to clear what we set 1483 */ 1484 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1485 u32 regval = rd32(E1000_EIAM); 1486 1487 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1488 wr32(E1000_EIMC, adapter->eims_enable_mask); 1489 regval = rd32(E1000_EIAC); 1490 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1491 } 1492 1493 wr32(E1000_IAM, 0); 1494 wr32(E1000_IMC, ~0); 1495 wrfl(); 1496 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1497 int i; 1498 1499 for (i = 0; i < adapter->num_q_vectors; i++) 1500 synchronize_irq(adapter->msix_entries[i].vector); 1501 } else { 1502 synchronize_irq(adapter->pdev->irq); 1503 } 1504 } 1505 1506 /** 1507 * igb_irq_enable - Enable default interrupt generation settings 1508 * @adapter: board private structure 1509 **/ 1510 static void igb_irq_enable(struct igb_adapter *adapter) 1511 { 1512 struct e1000_hw *hw = &adapter->hw; 1513 1514 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1515 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1516 u32 regval = rd32(E1000_EIAC); 1517 1518 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1519 regval = rd32(E1000_EIAM); 1520 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1521 wr32(E1000_EIMS, adapter->eims_enable_mask); 1522 if (adapter->vfs_allocated_count) { 1523 wr32(E1000_MBVFIMR, 0xFF); 1524 ims |= E1000_IMS_VMMB; 1525 } 1526 wr32(E1000_IMS, ims); 1527 } else { 1528 wr32(E1000_IMS, IMS_ENABLE_MASK | 1529 E1000_IMS_DRSTA); 1530 wr32(E1000_IAM, IMS_ENABLE_MASK | 1531 E1000_IMS_DRSTA); 1532 } 1533 } 1534 1535 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1536 { 1537 struct e1000_hw *hw = &adapter->hw; 1538 u16 pf_id = adapter->vfs_allocated_count; 1539 u16 vid = adapter->hw.mng_cookie.vlan_id; 1540 u16 old_vid = adapter->mng_vlan_id; 1541 1542 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1543 /* add VID to filter table */ 1544 igb_vfta_set(hw, vid, pf_id, true, true); 1545 adapter->mng_vlan_id = vid; 1546 } else { 1547 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1548 } 1549 1550 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1551 (vid != old_vid) && 1552 !test_bit(old_vid, adapter->active_vlans)) { 1553 /* remove VID from filter table */ 1554 igb_vfta_set(hw, vid, pf_id, false, true); 1555 } 1556 } 1557 1558 /** 1559 * igb_release_hw_control - release control of the h/w to f/w 1560 * @adapter: address of board private structure 1561 * 1562 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1563 * For ASF and Pass Through versions of f/w this means that the 1564 * driver is no longer loaded. 1565 **/ 1566 static void igb_release_hw_control(struct igb_adapter *adapter) 1567 { 1568 struct e1000_hw *hw = &adapter->hw; 1569 u32 ctrl_ext; 1570 1571 /* Let firmware take over control of h/w */ 1572 ctrl_ext = rd32(E1000_CTRL_EXT); 1573 wr32(E1000_CTRL_EXT, 1574 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1575 } 1576 1577 /** 1578 * igb_get_hw_control - get control of the h/w from f/w 1579 * @adapter: address of board private structure 1580 * 1581 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1582 * For ASF and Pass Through versions of f/w this means that 1583 * the driver is loaded. 1584 **/ 1585 static void igb_get_hw_control(struct igb_adapter *adapter) 1586 { 1587 struct e1000_hw *hw = &adapter->hw; 1588 u32 ctrl_ext; 1589 1590 /* Let firmware know the driver has taken over */ 1591 ctrl_ext = rd32(E1000_CTRL_EXT); 1592 wr32(E1000_CTRL_EXT, 1593 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1594 } 1595 1596 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1597 { 1598 struct net_device *netdev = adapter->netdev; 1599 struct e1000_hw *hw = &adapter->hw; 1600 1601 WARN_ON(hw->mac.type != e1000_i210); 1602 1603 if (enable) 1604 adapter->flags |= IGB_FLAG_FQTSS; 1605 else 1606 adapter->flags &= ~IGB_FLAG_FQTSS; 1607 1608 if (netif_running(netdev)) 1609 schedule_work(&adapter->reset_task); 1610 } 1611 1612 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1613 { 1614 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1615 } 1616 1617 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1618 enum tx_queue_prio prio) 1619 { 1620 u32 val; 1621 1622 WARN_ON(hw->mac.type != e1000_i210); 1623 WARN_ON(queue < 0 || queue > 4); 1624 1625 val = rd32(E1000_I210_TXDCTL(queue)); 1626 1627 if (prio == TX_QUEUE_PRIO_HIGH) 1628 val |= E1000_TXDCTL_PRIORITY; 1629 else 1630 val &= ~E1000_TXDCTL_PRIORITY; 1631 1632 wr32(E1000_I210_TXDCTL(queue), val); 1633 } 1634 1635 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1636 { 1637 u32 val; 1638 1639 WARN_ON(hw->mac.type != e1000_i210); 1640 WARN_ON(queue < 0 || queue > 1); 1641 1642 val = rd32(E1000_I210_TQAVCC(queue)); 1643 1644 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1645 val |= E1000_TQAVCC_QUEUEMODE; 1646 else 1647 val &= ~E1000_TQAVCC_QUEUEMODE; 1648 1649 wr32(E1000_I210_TQAVCC(queue), val); 1650 } 1651 1652 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1653 { 1654 int i; 1655 1656 for (i = 0; i < adapter->num_tx_queues; i++) { 1657 if (adapter->tx_ring[i]->cbs_enable) 1658 return true; 1659 } 1660 1661 return false; 1662 } 1663 1664 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1665 { 1666 int i; 1667 1668 for (i = 0; i < adapter->num_tx_queues; i++) { 1669 if (adapter->tx_ring[i]->launchtime_enable) 1670 return true; 1671 } 1672 1673 return false; 1674 } 1675 1676 /** 1677 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1678 * @adapter: pointer to adapter struct 1679 * @queue: queue number 1680 * 1681 * Configure CBS and Launchtime for a given hardware queue. 1682 * Parameters are retrieved from the correct Tx ring, so 1683 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1684 * for setting those correctly prior to this function being called. 1685 **/ 1686 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1687 { 1688 struct net_device *netdev = adapter->netdev; 1689 struct e1000_hw *hw = &adapter->hw; 1690 struct igb_ring *ring; 1691 u32 tqavcc, tqavctrl; 1692 u16 value; 1693 1694 WARN_ON(hw->mac.type != e1000_i210); 1695 WARN_ON(queue < 0 || queue > 1); 1696 ring = adapter->tx_ring[queue]; 1697 1698 /* If any of the Qav features is enabled, configure queues as SR and 1699 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1700 * as SP. 1701 */ 1702 if (ring->cbs_enable || ring->launchtime_enable) { 1703 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1704 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1705 } else { 1706 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1707 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1708 } 1709 1710 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1711 if (ring->cbs_enable || queue == 0) { 1712 /* i210 does not allow the queue 0 to be in the Strict 1713 * Priority mode while the Qav mode is enabled, so, 1714 * instead of disabling strict priority mode, we give 1715 * queue 0 the maximum of credits possible. 1716 * 1717 * See section 8.12.19 of the i210 datasheet, "Note: 1718 * Queue0 QueueMode must be set to 1b when 1719 * TransmitMode is set to Qav." 1720 */ 1721 if (queue == 0 && !ring->cbs_enable) { 1722 /* max "linkspeed" idleslope in kbps */ 1723 ring->idleslope = 1000000; 1724 ring->hicredit = ETH_FRAME_LEN; 1725 } 1726 1727 /* Always set data transfer arbitration to credit-based 1728 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1729 * the queues. 1730 */ 1731 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1732 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1733 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1734 1735 /* According to i210 datasheet section 7.2.7.7, we should set 1736 * the 'idleSlope' field from TQAVCC register following the 1737 * equation: 1738 * 1739 * For 100 Mbps link speed: 1740 * 1741 * value = BW * 0x7735 * 0.2 (E1) 1742 * 1743 * For 1000Mbps link speed: 1744 * 1745 * value = BW * 0x7735 * 2 (E2) 1746 * 1747 * E1 and E2 can be merged into one equation as shown below. 1748 * Note that 'link-speed' is in Mbps. 1749 * 1750 * value = BW * 0x7735 * 2 * link-speed 1751 * -------------- (E3) 1752 * 1000 1753 * 1754 * 'BW' is the percentage bandwidth out of full link speed 1755 * which can be found with the following equation. Note that 1756 * idleSlope here is the parameter from this function which 1757 * is in kbps. 1758 * 1759 * BW = idleSlope 1760 * ----------------- (E4) 1761 * link-speed * 1000 1762 * 1763 * That said, we can come up with a generic equation to 1764 * calculate the value we should set it TQAVCC register by 1765 * replacing 'BW' in E3 by E4. The resulting equation is: 1766 * 1767 * value = idleSlope * 0x7735 * 2 * link-speed 1768 * ----------------- -------------- (E5) 1769 * link-speed * 1000 1000 1770 * 1771 * 'link-speed' is present in both sides of the fraction so 1772 * it is canceled out. The final equation is the following: 1773 * 1774 * value = idleSlope * 61034 1775 * ----------------- (E6) 1776 * 1000000 1777 * 1778 * NOTE: For i210, given the above, we can see that idleslope 1779 * is represented in 16.38431 kbps units by the value at 1780 * the TQAVCC register (1Gbps / 61034), which reduces 1781 * the granularity for idleslope increments. 1782 * For instance, if you want to configure a 2576kbps 1783 * idleslope, the value to be written on the register 1784 * would have to be 157.23. If rounded down, you end 1785 * up with less bandwidth available than originally 1786 * required (~2572 kbps). If rounded up, you end up 1787 * with a higher bandwidth (~2589 kbps). Below the 1788 * approach we take is to always round up the 1789 * calculated value, so the resulting bandwidth might 1790 * be slightly higher for some configurations. 1791 */ 1792 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1793 1794 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1795 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1796 tqavcc |= value; 1797 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1798 1799 wr32(E1000_I210_TQAVHC(queue), 1800 0x80000000 + ring->hicredit * 0x7735); 1801 } else { 1802 1803 /* Set idleSlope to zero. */ 1804 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1805 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1806 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1807 1808 /* Set hiCredit to zero. */ 1809 wr32(E1000_I210_TQAVHC(queue), 0); 1810 1811 /* If CBS is not enabled for any queues anymore, then return to 1812 * the default state of Data Transmission Arbitration on 1813 * TQAVCTRL. 1814 */ 1815 if (!is_any_cbs_enabled(adapter)) { 1816 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1817 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1818 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1819 } 1820 } 1821 1822 /* If LaunchTime is enabled, set DataTranTIM. */ 1823 if (ring->launchtime_enable) { 1824 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1825 * for any of the SR queues, and configure fetchtime delta. 1826 * XXX NOTE: 1827 * - LaunchTime will be enabled for all SR queues. 1828 * - A fixed offset can be added relative to the launch 1829 * time of all packets if configured at reg LAUNCH_OS0. 1830 * We are keeping it as 0 for now (default value). 1831 */ 1832 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1833 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1834 E1000_TQAVCTRL_FETCHTIME_DELTA; 1835 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1836 } else { 1837 /* If Launchtime is not enabled for any SR queues anymore, 1838 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1839 * effectively disabling Launchtime. 1840 */ 1841 if (!is_any_txtime_enabled(adapter)) { 1842 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1843 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1844 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1845 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1846 } 1847 } 1848 1849 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1850 * CBS are not configurable by software so we don't do any 'controller 1851 * configuration' in respect to these parameters. 1852 */ 1853 1854 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1855 ring->cbs_enable ? "enabled" : "disabled", 1856 ring->launchtime_enable ? "enabled" : "disabled", 1857 queue, 1858 ring->idleslope, ring->sendslope, 1859 ring->hicredit, ring->locredit); 1860 } 1861 1862 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1863 bool enable) 1864 { 1865 struct igb_ring *ring; 1866 1867 if (queue < 0 || queue > adapter->num_tx_queues) 1868 return -EINVAL; 1869 1870 ring = adapter->tx_ring[queue]; 1871 ring->launchtime_enable = enable; 1872 1873 return 0; 1874 } 1875 1876 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1877 bool enable, int idleslope, int sendslope, 1878 int hicredit, int locredit) 1879 { 1880 struct igb_ring *ring; 1881 1882 if (queue < 0 || queue > adapter->num_tx_queues) 1883 return -EINVAL; 1884 1885 ring = adapter->tx_ring[queue]; 1886 1887 ring->cbs_enable = enable; 1888 ring->idleslope = idleslope; 1889 ring->sendslope = sendslope; 1890 ring->hicredit = hicredit; 1891 ring->locredit = locredit; 1892 1893 return 0; 1894 } 1895 1896 /** 1897 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1898 * @adapter: pointer to adapter struct 1899 * 1900 * Configure TQAVCTRL register switching the controller's Tx mode 1901 * if FQTSS mode is enabled or disabled. Additionally, will issue 1902 * a call to igb_config_tx_modes() per queue so any previously saved 1903 * Tx parameters are applied. 1904 **/ 1905 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1906 { 1907 struct net_device *netdev = adapter->netdev; 1908 struct e1000_hw *hw = &adapter->hw; 1909 u32 val; 1910 1911 /* Only i210 controller supports changing the transmission mode. */ 1912 if (hw->mac.type != e1000_i210) 1913 return; 1914 1915 if (is_fqtss_enabled(adapter)) { 1916 int i, max_queue; 1917 1918 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1919 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1920 * so SP queues wait for SR ones. 1921 */ 1922 val = rd32(E1000_I210_TQAVCTRL); 1923 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1924 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1925 wr32(E1000_I210_TQAVCTRL, val); 1926 1927 /* Configure Tx and Rx packet buffers sizes as described in 1928 * i210 datasheet section 7.2.7.7. 1929 */ 1930 val = rd32(E1000_TXPBS); 1931 val &= ~I210_TXPBSIZE_MASK; 1932 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB | 1933 I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB; 1934 wr32(E1000_TXPBS, val); 1935 1936 val = rd32(E1000_RXPBS); 1937 val &= ~I210_RXPBSIZE_MASK; 1938 val |= I210_RXPBSIZE_PB_30KB; 1939 wr32(E1000_RXPBS, val); 1940 1941 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1942 * register should not exceed the buffer size programmed in 1943 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1944 * so according to the datasheet we should set MAX_TPKT_SIZE to 1945 * 4kB / 64. 1946 * 1947 * However, when we do so, no frame from queue 2 and 3 are 1948 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1949 * or _equal_ to the buffer size programmed in TXPBS. For this 1950 * reason, we set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1951 */ 1952 val = (4096 - 1) / 64; 1953 wr32(E1000_I210_DTXMXPKTSZ, val); 1954 1955 /* Since FQTSS mode is enabled, apply any CBS configuration 1956 * previously set. If no previous CBS configuration has been 1957 * done, then the initial configuration is applied, which means 1958 * CBS is disabled. 1959 */ 1960 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1961 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1962 1963 for (i = 0; i < max_queue; i++) { 1964 igb_config_tx_modes(adapter, i); 1965 } 1966 } else { 1967 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1968 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1969 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1970 1971 val = rd32(E1000_I210_TQAVCTRL); 1972 /* According to Section 8.12.21, the other flags we've set when 1973 * enabling FQTSS are not relevant when disabling FQTSS so we 1974 * don't set they here. 1975 */ 1976 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1977 wr32(E1000_I210_TQAVCTRL, val); 1978 } 1979 1980 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1981 "enabled" : "disabled"); 1982 } 1983 1984 /** 1985 * igb_configure - configure the hardware for RX and TX 1986 * @adapter: private board structure 1987 **/ 1988 static void igb_configure(struct igb_adapter *adapter) 1989 { 1990 struct net_device *netdev = adapter->netdev; 1991 int i; 1992 1993 igb_get_hw_control(adapter); 1994 igb_set_rx_mode(netdev); 1995 igb_setup_tx_mode(adapter); 1996 1997 igb_restore_vlan(adapter); 1998 1999 igb_setup_tctl(adapter); 2000 igb_setup_mrqc(adapter); 2001 igb_setup_rctl(adapter); 2002 2003 igb_nfc_filter_restore(adapter); 2004 igb_configure_tx(adapter); 2005 igb_configure_rx(adapter); 2006 2007 igb_rx_fifo_flush_82575(&adapter->hw); 2008 2009 /* call igb_desc_unused which always leaves 2010 * at least 1 descriptor unused to make sure 2011 * next_to_use != next_to_clean 2012 */ 2013 for (i = 0; i < adapter->num_rx_queues; i++) { 2014 struct igb_ring *ring = adapter->rx_ring[i]; 2015 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 2016 } 2017 } 2018 2019 /** 2020 * igb_power_up_link - Power up the phy/serdes link 2021 * @adapter: address of board private structure 2022 **/ 2023 void igb_power_up_link(struct igb_adapter *adapter) 2024 { 2025 igb_reset_phy(&adapter->hw); 2026 2027 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2028 igb_power_up_phy_copper(&adapter->hw); 2029 else 2030 igb_power_up_serdes_link_82575(&adapter->hw); 2031 2032 igb_setup_link(&adapter->hw); 2033 } 2034 2035 /** 2036 * igb_power_down_link - Power down the phy/serdes link 2037 * @adapter: address of board private structure 2038 */ 2039 static void igb_power_down_link(struct igb_adapter *adapter) 2040 { 2041 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2042 igb_power_down_phy_copper_82575(&adapter->hw); 2043 else 2044 igb_shutdown_serdes_link_82575(&adapter->hw); 2045 } 2046 2047 /** 2048 * igb_check_swap_media - Detect and switch function for Media Auto Sense 2049 * @adapter: address of the board private structure 2050 **/ 2051 static void igb_check_swap_media(struct igb_adapter *adapter) 2052 { 2053 struct e1000_hw *hw = &adapter->hw; 2054 u32 ctrl_ext, connsw; 2055 bool swap_now = false; 2056 2057 ctrl_ext = rd32(E1000_CTRL_EXT); 2058 connsw = rd32(E1000_CONNSW); 2059 2060 /* need to live swap if current media is copper and we have fiber/serdes 2061 * to go to. 2062 */ 2063 2064 if ((hw->phy.media_type == e1000_media_type_copper) && 2065 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2066 swap_now = true; 2067 } else if ((hw->phy.media_type != e1000_media_type_copper) && 2068 !(connsw & E1000_CONNSW_SERDESD)) { 2069 /* copper signal takes time to appear */ 2070 if (adapter->copper_tries < 4) { 2071 adapter->copper_tries++; 2072 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2073 wr32(E1000_CONNSW, connsw); 2074 return; 2075 } else { 2076 adapter->copper_tries = 0; 2077 if ((connsw & E1000_CONNSW_PHYSD) && 2078 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2079 swap_now = true; 2080 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2081 wr32(E1000_CONNSW, connsw); 2082 } 2083 } 2084 } 2085 2086 if (!swap_now) 2087 return; 2088 2089 switch (hw->phy.media_type) { 2090 case e1000_media_type_copper: 2091 netdev_info(adapter->netdev, 2092 "MAS: changing media to fiber/serdes\n"); 2093 ctrl_ext |= 2094 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2095 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2096 adapter->copper_tries = 0; 2097 break; 2098 case e1000_media_type_internal_serdes: 2099 case e1000_media_type_fiber: 2100 netdev_info(adapter->netdev, 2101 "MAS: changing media to copper\n"); 2102 ctrl_ext &= 2103 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2104 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2105 break; 2106 default: 2107 /* shouldn't get here during regular operation */ 2108 netdev_err(adapter->netdev, 2109 "AMS: Invalid media type found, returning\n"); 2110 break; 2111 } 2112 wr32(E1000_CTRL_EXT, ctrl_ext); 2113 } 2114 2115 /** 2116 * igb_up - Open the interface and prepare it to handle traffic 2117 * @adapter: board private structure 2118 **/ 2119 int igb_up(struct igb_adapter *adapter) 2120 { 2121 struct e1000_hw *hw = &adapter->hw; 2122 int i; 2123 2124 /* hardware has been reset, we need to reload some things */ 2125 igb_configure(adapter); 2126 2127 clear_bit(__IGB_DOWN, &adapter->state); 2128 2129 for (i = 0; i < adapter->num_q_vectors; i++) 2130 napi_enable(&(adapter->q_vector[i]->napi)); 2131 2132 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2133 igb_configure_msix(adapter); 2134 else 2135 igb_assign_vector(adapter->q_vector[0], 0); 2136 2137 /* Clear any pending interrupts. */ 2138 rd32(E1000_TSICR); 2139 rd32(E1000_ICR); 2140 igb_irq_enable(adapter); 2141 2142 /* notify VFs that reset has been completed */ 2143 if (adapter->vfs_allocated_count) { 2144 u32 reg_data = rd32(E1000_CTRL_EXT); 2145 2146 reg_data |= E1000_CTRL_EXT_PFRSTD; 2147 wr32(E1000_CTRL_EXT, reg_data); 2148 } 2149 2150 netif_tx_start_all_queues(adapter->netdev); 2151 2152 /* start the watchdog. */ 2153 hw->mac.get_link_status = 1; 2154 schedule_work(&adapter->watchdog_task); 2155 2156 if ((adapter->flags & IGB_FLAG_EEE) && 2157 (!hw->dev_spec._82575.eee_disable)) 2158 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2159 2160 return 0; 2161 } 2162 2163 void igb_down(struct igb_adapter *adapter) 2164 { 2165 struct net_device *netdev = adapter->netdev; 2166 struct e1000_hw *hw = &adapter->hw; 2167 u32 tctl, rctl; 2168 int i; 2169 2170 /* signal that we're down so the interrupt handler does not 2171 * reschedule our watchdog timer 2172 */ 2173 set_bit(__IGB_DOWN, &adapter->state); 2174 2175 /* disable receives in the hardware */ 2176 rctl = rd32(E1000_RCTL); 2177 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2178 /* flush and sleep below */ 2179 2180 igb_nfc_filter_exit(adapter); 2181 2182 netif_carrier_off(netdev); 2183 netif_tx_stop_all_queues(netdev); 2184 2185 /* disable transmits in the hardware */ 2186 tctl = rd32(E1000_TCTL); 2187 tctl &= ~E1000_TCTL_EN; 2188 wr32(E1000_TCTL, tctl); 2189 /* flush both disables and wait for them to finish */ 2190 wrfl(); 2191 usleep_range(10000, 11000); 2192 2193 igb_irq_disable(adapter); 2194 2195 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2196 2197 for (i = 0; i < adapter->num_q_vectors; i++) { 2198 if (adapter->q_vector[i]) { 2199 napi_synchronize(&adapter->q_vector[i]->napi); 2200 napi_disable(&adapter->q_vector[i]->napi); 2201 } 2202 } 2203 2204 del_timer_sync(&adapter->watchdog_timer); 2205 del_timer_sync(&adapter->phy_info_timer); 2206 2207 /* record the stats before reset*/ 2208 spin_lock(&adapter->stats64_lock); 2209 igb_update_stats(adapter); 2210 spin_unlock(&adapter->stats64_lock); 2211 2212 adapter->link_speed = 0; 2213 adapter->link_duplex = 0; 2214 2215 if (!pci_channel_offline(adapter->pdev)) 2216 igb_reset(adapter); 2217 2218 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2219 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2220 2221 igb_clean_all_tx_rings(adapter); 2222 igb_clean_all_rx_rings(adapter); 2223 #ifdef CONFIG_IGB_DCA 2224 2225 /* since we reset the hardware DCA settings were cleared */ 2226 igb_setup_dca(adapter); 2227 #endif 2228 } 2229 2230 void igb_reinit_locked(struct igb_adapter *adapter) 2231 { 2232 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2233 usleep_range(1000, 2000); 2234 igb_down(adapter); 2235 igb_up(adapter); 2236 clear_bit(__IGB_RESETTING, &adapter->state); 2237 } 2238 2239 /** igb_enable_mas - Media Autosense re-enable after swap 2240 * 2241 * @adapter: adapter struct 2242 **/ 2243 static void igb_enable_mas(struct igb_adapter *adapter) 2244 { 2245 struct e1000_hw *hw = &adapter->hw; 2246 u32 connsw = rd32(E1000_CONNSW); 2247 2248 /* configure for SerDes media detect */ 2249 if ((hw->phy.media_type == e1000_media_type_copper) && 2250 (!(connsw & E1000_CONNSW_SERDESD))) { 2251 connsw |= E1000_CONNSW_ENRGSRC; 2252 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2253 wr32(E1000_CONNSW, connsw); 2254 wrfl(); 2255 } 2256 } 2257 2258 #ifdef CONFIG_IGB_HWMON 2259 /** 2260 * igb_set_i2c_bb - Init I2C interface 2261 * @hw: pointer to hardware structure 2262 **/ 2263 static void igb_set_i2c_bb(struct e1000_hw *hw) 2264 { 2265 u32 ctrl_ext; 2266 s32 i2cctl; 2267 2268 ctrl_ext = rd32(E1000_CTRL_EXT); 2269 ctrl_ext |= E1000_CTRL_I2C_ENA; 2270 wr32(E1000_CTRL_EXT, ctrl_ext); 2271 wrfl(); 2272 2273 i2cctl = rd32(E1000_I2CPARAMS); 2274 i2cctl |= E1000_I2CBB_EN 2275 | E1000_I2C_CLK_OE_N 2276 | E1000_I2C_DATA_OE_N; 2277 wr32(E1000_I2CPARAMS, i2cctl); 2278 wrfl(); 2279 } 2280 #endif 2281 2282 void igb_reset(struct igb_adapter *adapter) 2283 { 2284 struct pci_dev *pdev = adapter->pdev; 2285 struct e1000_hw *hw = &adapter->hw; 2286 struct e1000_mac_info *mac = &hw->mac; 2287 struct e1000_fc_info *fc = &hw->fc; 2288 u32 pba, hwm; 2289 2290 /* Repartition Pba for greater than 9k mtu 2291 * To take effect CTRL.RST is required. 2292 */ 2293 switch (mac->type) { 2294 case e1000_i350: 2295 case e1000_i354: 2296 case e1000_82580: 2297 pba = rd32(E1000_RXPBS); 2298 pba = igb_rxpbs_adjust_82580(pba); 2299 break; 2300 case e1000_82576: 2301 pba = rd32(E1000_RXPBS); 2302 pba &= E1000_RXPBS_SIZE_MASK_82576; 2303 break; 2304 case e1000_82575: 2305 case e1000_i210: 2306 case e1000_i211: 2307 default: 2308 pba = E1000_PBA_34K; 2309 break; 2310 } 2311 2312 if (mac->type == e1000_82575) { 2313 u32 min_rx_space, min_tx_space, needed_tx_space; 2314 2315 /* write Rx PBA so that hardware can report correct Tx PBA */ 2316 wr32(E1000_PBA, pba); 2317 2318 /* To maintain wire speed transmits, the Tx FIFO should be 2319 * large enough to accommodate two full transmit packets, 2320 * rounded up to the next 1KB and expressed in KB. Likewise, 2321 * the Rx FIFO should be large enough to accommodate at least 2322 * one full receive packet and is similarly rounded up and 2323 * expressed in KB. 2324 */ 2325 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2326 2327 /* The Tx FIFO also stores 16 bytes of information about the Tx 2328 * but don't include Ethernet FCS because hardware appends it. 2329 * We only need to round down to the nearest 512 byte block 2330 * count since the value we care about is 2 frames, not 1. 2331 */ 2332 min_tx_space = adapter->max_frame_size; 2333 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2334 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2335 2336 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2337 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2338 2339 /* If current Tx allocation is less than the min Tx FIFO size, 2340 * and the min Tx FIFO size is less than the current Rx FIFO 2341 * allocation, take space away from current Rx allocation. 2342 */ 2343 if (needed_tx_space < pba) { 2344 pba -= needed_tx_space; 2345 2346 /* if short on Rx space, Rx wins and must trump Tx 2347 * adjustment 2348 */ 2349 if (pba < min_rx_space) 2350 pba = min_rx_space; 2351 } 2352 2353 /* adjust PBA for jumbo frames */ 2354 wr32(E1000_PBA, pba); 2355 } 2356 2357 /* flow control settings 2358 * The high water mark must be low enough to fit one full frame 2359 * after transmitting the pause frame. As such we must have enough 2360 * space to allow for us to complete our current transmit and then 2361 * receive the frame that is in progress from the link partner. 2362 * Set it to: 2363 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2364 */ 2365 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2366 2367 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2368 fc->low_water = fc->high_water - 16; 2369 fc->pause_time = 0xFFFF; 2370 fc->send_xon = 1; 2371 fc->current_mode = fc->requested_mode; 2372 2373 /* disable receive for all VFs and wait one second */ 2374 if (adapter->vfs_allocated_count) { 2375 int i; 2376 2377 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2378 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2379 2380 /* ping all the active vfs to let them know we are going down */ 2381 igb_ping_all_vfs(adapter); 2382 2383 /* disable transmits and receives */ 2384 wr32(E1000_VFRE, 0); 2385 wr32(E1000_VFTE, 0); 2386 } 2387 2388 /* Allow time for pending master requests to run */ 2389 hw->mac.ops.reset_hw(hw); 2390 wr32(E1000_WUC, 0); 2391 2392 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2393 /* need to resetup here after media swap */ 2394 adapter->ei.get_invariants(hw); 2395 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2396 } 2397 if ((mac->type == e1000_82575 || mac->type == e1000_i350) && 2398 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2399 igb_enable_mas(adapter); 2400 } 2401 if (hw->mac.ops.init_hw(hw)) 2402 dev_err(&pdev->dev, "Hardware Error\n"); 2403 2404 /* RAR registers were cleared during init_hw, clear mac table */ 2405 igb_flush_mac_table(adapter); 2406 __dev_uc_unsync(adapter->netdev, NULL); 2407 2408 /* Recover default RAR entry */ 2409 igb_set_default_mac_filter(adapter); 2410 2411 /* Flow control settings reset on hardware reset, so guarantee flow 2412 * control is off when forcing speed. 2413 */ 2414 if (!hw->mac.autoneg) 2415 igb_force_mac_fc(hw); 2416 2417 igb_init_dmac(adapter, pba); 2418 #ifdef CONFIG_IGB_HWMON 2419 /* Re-initialize the thermal sensor on i350 devices. */ 2420 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2421 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2422 /* If present, re-initialize the external thermal sensor 2423 * interface. 2424 */ 2425 if (adapter->ets) 2426 igb_set_i2c_bb(hw); 2427 mac->ops.init_thermal_sensor_thresh(hw); 2428 } 2429 } 2430 #endif 2431 /* Re-establish EEE setting */ 2432 if (hw->phy.media_type == e1000_media_type_copper) { 2433 switch (mac->type) { 2434 case e1000_i350: 2435 case e1000_i210: 2436 case e1000_i211: 2437 igb_set_eee_i350(hw, true, true); 2438 break; 2439 case e1000_i354: 2440 igb_set_eee_i354(hw, true, true); 2441 break; 2442 default: 2443 break; 2444 } 2445 } 2446 if (!netif_running(adapter->netdev)) 2447 igb_power_down_link(adapter); 2448 2449 igb_update_mng_vlan(adapter); 2450 2451 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2452 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2453 2454 /* Re-enable PTP, where applicable. */ 2455 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2456 igb_ptp_reset(adapter); 2457 2458 igb_get_phy_info(hw); 2459 } 2460 2461 static netdev_features_t igb_fix_features(struct net_device *netdev, 2462 netdev_features_t features) 2463 { 2464 /* Since there is no support for separate Rx/Tx vlan accel 2465 * enable/disable make sure Tx flag is always in same state as Rx. 2466 */ 2467 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2468 features |= NETIF_F_HW_VLAN_CTAG_TX; 2469 else 2470 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2471 2472 return features; 2473 } 2474 2475 static int igb_set_features(struct net_device *netdev, 2476 netdev_features_t features) 2477 { 2478 netdev_features_t changed = netdev->features ^ features; 2479 struct igb_adapter *adapter = netdev_priv(netdev); 2480 2481 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2482 igb_vlan_mode(netdev, features); 2483 2484 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2485 return 0; 2486 2487 if (!(features & NETIF_F_NTUPLE)) { 2488 struct hlist_node *node2; 2489 struct igb_nfc_filter *rule; 2490 2491 spin_lock(&adapter->nfc_lock); 2492 hlist_for_each_entry_safe(rule, node2, 2493 &adapter->nfc_filter_list, nfc_node) { 2494 igb_erase_filter(adapter, rule); 2495 hlist_del(&rule->nfc_node); 2496 kfree(rule); 2497 } 2498 spin_unlock(&adapter->nfc_lock); 2499 adapter->nfc_filter_count = 0; 2500 } 2501 2502 netdev->features = features; 2503 2504 if (netif_running(netdev)) 2505 igb_reinit_locked(adapter); 2506 else 2507 igb_reset(adapter); 2508 2509 return 1; 2510 } 2511 2512 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2513 struct net_device *dev, 2514 const unsigned char *addr, u16 vid, 2515 u16 flags, 2516 struct netlink_ext_ack *extack) 2517 { 2518 /* guarantee we can provide a unique filter for the unicast address */ 2519 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2520 struct igb_adapter *adapter = netdev_priv(dev); 2521 int vfn = adapter->vfs_allocated_count; 2522 2523 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2524 return -ENOMEM; 2525 } 2526 2527 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2528 } 2529 2530 #define IGB_MAX_MAC_HDR_LEN 127 2531 #define IGB_MAX_NETWORK_HDR_LEN 511 2532 2533 static netdev_features_t 2534 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2535 netdev_features_t features) 2536 { 2537 unsigned int network_hdr_len, mac_hdr_len; 2538 2539 /* Make certain the headers can be described by a context descriptor */ 2540 mac_hdr_len = skb_network_header(skb) - skb->data; 2541 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2542 return features & ~(NETIF_F_HW_CSUM | 2543 NETIF_F_SCTP_CRC | 2544 NETIF_F_GSO_UDP_L4 | 2545 NETIF_F_HW_VLAN_CTAG_TX | 2546 NETIF_F_TSO | 2547 NETIF_F_TSO6); 2548 2549 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2550 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2551 return features & ~(NETIF_F_HW_CSUM | 2552 NETIF_F_SCTP_CRC | 2553 NETIF_F_GSO_UDP_L4 | 2554 NETIF_F_TSO | 2555 NETIF_F_TSO6); 2556 2557 /* We can only support IPV4 TSO in tunnels if we can mangle the 2558 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2559 */ 2560 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2561 features &= ~NETIF_F_TSO; 2562 2563 return features; 2564 } 2565 2566 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2567 { 2568 if (!is_fqtss_enabled(adapter)) { 2569 enable_fqtss(adapter, true); 2570 return; 2571 } 2572 2573 igb_config_tx_modes(adapter, queue); 2574 2575 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2576 enable_fqtss(adapter, false); 2577 } 2578 2579 static int igb_offload_cbs(struct igb_adapter *adapter, 2580 struct tc_cbs_qopt_offload *qopt) 2581 { 2582 struct e1000_hw *hw = &adapter->hw; 2583 int err; 2584 2585 /* CBS offloading is only supported by i210 controller. */ 2586 if (hw->mac.type != e1000_i210) 2587 return -EOPNOTSUPP; 2588 2589 /* CBS offloading is only supported by queue 0 and queue 1. */ 2590 if (qopt->queue < 0 || qopt->queue > 1) 2591 return -EINVAL; 2592 2593 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2594 qopt->idleslope, qopt->sendslope, 2595 qopt->hicredit, qopt->locredit); 2596 if (err) 2597 return err; 2598 2599 igb_offload_apply(adapter, qopt->queue); 2600 2601 return 0; 2602 } 2603 2604 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2605 #define VLAN_PRIO_FULL_MASK (0x07) 2606 2607 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2608 struct flow_cls_offload *f, 2609 int traffic_class, 2610 struct igb_nfc_filter *input) 2611 { 2612 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2613 struct flow_dissector *dissector = rule->match.dissector; 2614 struct netlink_ext_ack *extack = f->common.extack; 2615 2616 if (dissector->used_keys & 2617 ~(BIT(FLOW_DISSECTOR_KEY_BASIC) | 2618 BIT(FLOW_DISSECTOR_KEY_CONTROL) | 2619 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2620 BIT(FLOW_DISSECTOR_KEY_VLAN))) { 2621 NL_SET_ERR_MSG_MOD(extack, 2622 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2623 return -EOPNOTSUPP; 2624 } 2625 2626 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2627 struct flow_match_eth_addrs match; 2628 2629 flow_rule_match_eth_addrs(rule, &match); 2630 if (!is_zero_ether_addr(match.mask->dst)) { 2631 if (!is_broadcast_ether_addr(match.mask->dst)) { 2632 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2633 return -EINVAL; 2634 } 2635 2636 input->filter.match_flags |= 2637 IGB_FILTER_FLAG_DST_MAC_ADDR; 2638 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2639 } 2640 2641 if (!is_zero_ether_addr(match.mask->src)) { 2642 if (!is_broadcast_ether_addr(match.mask->src)) { 2643 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2644 return -EINVAL; 2645 } 2646 2647 input->filter.match_flags |= 2648 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2649 ether_addr_copy(input->filter.src_addr, match.key->src); 2650 } 2651 } 2652 2653 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2654 struct flow_match_basic match; 2655 2656 flow_rule_match_basic(rule, &match); 2657 if (match.mask->n_proto) { 2658 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2659 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2660 return -EINVAL; 2661 } 2662 2663 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2664 input->filter.etype = match.key->n_proto; 2665 } 2666 } 2667 2668 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2669 struct flow_match_vlan match; 2670 2671 flow_rule_match_vlan(rule, &match); 2672 if (match.mask->vlan_priority) { 2673 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2674 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2675 return -EINVAL; 2676 } 2677 2678 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2679 input->filter.vlan_tci = 2680 (__force __be16)match.key->vlan_priority; 2681 } 2682 } 2683 2684 input->action = traffic_class; 2685 input->cookie = f->cookie; 2686 2687 return 0; 2688 } 2689 2690 static int igb_configure_clsflower(struct igb_adapter *adapter, 2691 struct flow_cls_offload *cls_flower) 2692 { 2693 struct netlink_ext_ack *extack = cls_flower->common.extack; 2694 struct igb_nfc_filter *filter, *f; 2695 int err, tc; 2696 2697 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2698 if (tc < 0) { 2699 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2700 return -EINVAL; 2701 } 2702 2703 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2704 if (!filter) 2705 return -ENOMEM; 2706 2707 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2708 if (err < 0) 2709 goto err_parse; 2710 2711 spin_lock(&adapter->nfc_lock); 2712 2713 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2714 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2715 err = -EEXIST; 2716 NL_SET_ERR_MSG_MOD(extack, 2717 "This filter is already set in ethtool"); 2718 goto err_locked; 2719 } 2720 } 2721 2722 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2723 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2724 err = -EEXIST; 2725 NL_SET_ERR_MSG_MOD(extack, 2726 "This filter is already set in cls_flower"); 2727 goto err_locked; 2728 } 2729 } 2730 2731 err = igb_add_filter(adapter, filter); 2732 if (err < 0) { 2733 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2734 goto err_locked; 2735 } 2736 2737 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2738 2739 spin_unlock(&adapter->nfc_lock); 2740 2741 return 0; 2742 2743 err_locked: 2744 spin_unlock(&adapter->nfc_lock); 2745 2746 err_parse: 2747 kfree(filter); 2748 2749 return err; 2750 } 2751 2752 static int igb_delete_clsflower(struct igb_adapter *adapter, 2753 struct flow_cls_offload *cls_flower) 2754 { 2755 struct igb_nfc_filter *filter; 2756 int err; 2757 2758 spin_lock(&adapter->nfc_lock); 2759 2760 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2761 if (filter->cookie == cls_flower->cookie) 2762 break; 2763 2764 if (!filter) { 2765 err = -ENOENT; 2766 goto out; 2767 } 2768 2769 err = igb_erase_filter(adapter, filter); 2770 if (err < 0) 2771 goto out; 2772 2773 hlist_del(&filter->nfc_node); 2774 kfree(filter); 2775 2776 out: 2777 spin_unlock(&adapter->nfc_lock); 2778 2779 return err; 2780 } 2781 2782 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2783 struct flow_cls_offload *cls_flower) 2784 { 2785 switch (cls_flower->command) { 2786 case FLOW_CLS_REPLACE: 2787 return igb_configure_clsflower(adapter, cls_flower); 2788 case FLOW_CLS_DESTROY: 2789 return igb_delete_clsflower(adapter, cls_flower); 2790 case FLOW_CLS_STATS: 2791 return -EOPNOTSUPP; 2792 default: 2793 return -EOPNOTSUPP; 2794 } 2795 } 2796 2797 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2798 void *cb_priv) 2799 { 2800 struct igb_adapter *adapter = cb_priv; 2801 2802 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2803 return -EOPNOTSUPP; 2804 2805 switch (type) { 2806 case TC_SETUP_CLSFLOWER: 2807 return igb_setup_tc_cls_flower(adapter, type_data); 2808 2809 default: 2810 return -EOPNOTSUPP; 2811 } 2812 } 2813 2814 static int igb_offload_txtime(struct igb_adapter *adapter, 2815 struct tc_etf_qopt_offload *qopt) 2816 { 2817 struct e1000_hw *hw = &adapter->hw; 2818 int err; 2819 2820 /* Launchtime offloading is only supported by i210 controller. */ 2821 if (hw->mac.type != e1000_i210) 2822 return -EOPNOTSUPP; 2823 2824 /* Launchtime offloading is only supported by queues 0 and 1. */ 2825 if (qopt->queue < 0 || qopt->queue > 1) 2826 return -EINVAL; 2827 2828 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2829 if (err) 2830 return err; 2831 2832 igb_offload_apply(adapter, qopt->queue); 2833 2834 return 0; 2835 } 2836 2837 static int igb_tc_query_caps(struct igb_adapter *adapter, 2838 struct tc_query_caps_base *base) 2839 { 2840 switch (base->type) { 2841 case TC_SETUP_QDISC_TAPRIO: { 2842 struct tc_taprio_caps *caps = base->caps; 2843 2844 caps->broken_mqprio = true; 2845 2846 return 0; 2847 } 2848 default: 2849 return -EOPNOTSUPP; 2850 } 2851 } 2852 2853 static LIST_HEAD(igb_block_cb_list); 2854 2855 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2856 void *type_data) 2857 { 2858 struct igb_adapter *adapter = netdev_priv(dev); 2859 2860 switch (type) { 2861 case TC_QUERY_CAPS: 2862 return igb_tc_query_caps(adapter, type_data); 2863 case TC_SETUP_QDISC_CBS: 2864 return igb_offload_cbs(adapter, type_data); 2865 case TC_SETUP_BLOCK: 2866 return flow_block_cb_setup_simple(type_data, 2867 &igb_block_cb_list, 2868 igb_setup_tc_block_cb, 2869 adapter, adapter, true); 2870 2871 case TC_SETUP_QDISC_ETF: 2872 return igb_offload_txtime(adapter, type_data); 2873 2874 default: 2875 return -EOPNOTSUPP; 2876 } 2877 } 2878 2879 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf) 2880 { 2881 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD; 2882 struct igb_adapter *adapter = netdev_priv(dev); 2883 struct bpf_prog *prog = bpf->prog, *old_prog; 2884 bool running = netif_running(dev); 2885 bool need_reset; 2886 2887 /* verify igb ring attributes are sufficient for XDP */ 2888 for (i = 0; i < adapter->num_rx_queues; i++) { 2889 struct igb_ring *ring = adapter->rx_ring[i]; 2890 2891 if (frame_size > igb_rx_bufsz(ring)) { 2892 NL_SET_ERR_MSG_MOD(bpf->extack, 2893 "The RX buffer size is too small for the frame size"); 2894 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n", 2895 igb_rx_bufsz(ring), frame_size); 2896 return -EINVAL; 2897 } 2898 } 2899 2900 old_prog = xchg(&adapter->xdp_prog, prog); 2901 need_reset = (!!prog != !!old_prog); 2902 2903 /* device is up and bpf is added/removed, must setup the RX queues */ 2904 if (need_reset && running) { 2905 igb_close(dev); 2906 } else { 2907 for (i = 0; i < adapter->num_rx_queues; i++) 2908 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 2909 adapter->xdp_prog); 2910 } 2911 2912 if (old_prog) 2913 bpf_prog_put(old_prog); 2914 2915 /* bpf is just replaced, RXQ and MTU are already setup */ 2916 if (!need_reset) { 2917 return 0; 2918 } else { 2919 if (prog) 2920 xdp_features_set_redirect_target(dev, true); 2921 else 2922 xdp_features_clear_redirect_target(dev); 2923 } 2924 2925 if (running) 2926 igb_open(dev); 2927 2928 return 0; 2929 } 2930 2931 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp) 2932 { 2933 switch (xdp->command) { 2934 case XDP_SETUP_PROG: 2935 return igb_xdp_setup(dev, xdp); 2936 default: 2937 return -EINVAL; 2938 } 2939 } 2940 2941 static void igb_xdp_ring_update_tail(struct igb_ring *ring) 2942 { 2943 /* Force memory writes to complete before letting h/w know there 2944 * are new descriptors to fetch. 2945 */ 2946 wmb(); 2947 writel(ring->next_to_use, ring->tail); 2948 } 2949 2950 static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter) 2951 { 2952 unsigned int r_idx = smp_processor_id(); 2953 2954 if (r_idx >= adapter->num_tx_queues) 2955 r_idx = r_idx % adapter->num_tx_queues; 2956 2957 return adapter->tx_ring[r_idx]; 2958 } 2959 2960 static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp) 2961 { 2962 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2963 int cpu = smp_processor_id(); 2964 struct igb_ring *tx_ring; 2965 struct netdev_queue *nq; 2966 u32 ret; 2967 2968 if (unlikely(!xdpf)) 2969 return IGB_XDP_CONSUMED; 2970 2971 /* During program transitions its possible adapter->xdp_prog is assigned 2972 * but ring has not been configured yet. In this case simply abort xmit. 2973 */ 2974 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2975 if (unlikely(!tx_ring)) 2976 return IGB_XDP_CONSUMED; 2977 2978 nq = txring_txq(tx_ring); 2979 __netif_tx_lock(nq, cpu); 2980 /* Avoid transmit queue timeout since we share it with the slow path */ 2981 txq_trans_cond_update(nq); 2982 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2983 __netif_tx_unlock(nq); 2984 2985 return ret; 2986 } 2987 2988 static int igb_xdp_xmit(struct net_device *dev, int n, 2989 struct xdp_frame **frames, u32 flags) 2990 { 2991 struct igb_adapter *adapter = netdev_priv(dev); 2992 int cpu = smp_processor_id(); 2993 struct igb_ring *tx_ring; 2994 struct netdev_queue *nq; 2995 int nxmit = 0; 2996 int i; 2997 2998 if (unlikely(test_bit(__IGB_DOWN, &adapter->state))) 2999 return -ENETDOWN; 3000 3001 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 3002 return -EINVAL; 3003 3004 /* During program transitions its possible adapter->xdp_prog is assigned 3005 * but ring has not been configured yet. In this case simply abort xmit. 3006 */ 3007 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 3008 if (unlikely(!tx_ring)) 3009 return -ENXIO; 3010 3011 nq = txring_txq(tx_ring); 3012 __netif_tx_lock(nq, cpu); 3013 3014 /* Avoid transmit queue timeout since we share it with the slow path */ 3015 txq_trans_cond_update(nq); 3016 3017 for (i = 0; i < n; i++) { 3018 struct xdp_frame *xdpf = frames[i]; 3019 int err; 3020 3021 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 3022 if (err != IGB_XDP_TX) 3023 break; 3024 nxmit++; 3025 } 3026 3027 __netif_tx_unlock(nq); 3028 3029 if (unlikely(flags & XDP_XMIT_FLUSH)) 3030 igb_xdp_ring_update_tail(tx_ring); 3031 3032 return nxmit; 3033 } 3034 3035 static const struct net_device_ops igb_netdev_ops = { 3036 .ndo_open = igb_open, 3037 .ndo_stop = igb_close, 3038 .ndo_start_xmit = igb_xmit_frame, 3039 .ndo_get_stats64 = igb_get_stats64, 3040 .ndo_set_rx_mode = igb_set_rx_mode, 3041 .ndo_set_mac_address = igb_set_mac, 3042 .ndo_change_mtu = igb_change_mtu, 3043 .ndo_eth_ioctl = igb_ioctl, 3044 .ndo_tx_timeout = igb_tx_timeout, 3045 .ndo_validate_addr = eth_validate_addr, 3046 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 3047 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 3048 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 3049 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 3050 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 3051 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 3052 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 3053 .ndo_get_vf_config = igb_ndo_get_vf_config, 3054 .ndo_fix_features = igb_fix_features, 3055 .ndo_set_features = igb_set_features, 3056 .ndo_fdb_add = igb_ndo_fdb_add, 3057 .ndo_features_check = igb_features_check, 3058 .ndo_setup_tc = igb_setup_tc, 3059 .ndo_bpf = igb_xdp, 3060 .ndo_xdp_xmit = igb_xdp_xmit, 3061 }; 3062 3063 /** 3064 * igb_set_fw_version - Configure version string for ethtool 3065 * @adapter: adapter struct 3066 **/ 3067 void igb_set_fw_version(struct igb_adapter *adapter) 3068 { 3069 struct e1000_hw *hw = &adapter->hw; 3070 struct e1000_fw_version fw; 3071 3072 igb_get_fw_version(hw, &fw); 3073 3074 switch (hw->mac.type) { 3075 case e1000_i210: 3076 case e1000_i211: 3077 if (!(igb_get_flash_presence_i210(hw))) { 3078 snprintf(adapter->fw_version, 3079 sizeof(adapter->fw_version), 3080 "%2d.%2d-%d", 3081 fw.invm_major, fw.invm_minor, 3082 fw.invm_img_type); 3083 break; 3084 } 3085 fallthrough; 3086 default: 3087 /* if option is rom valid, display its version too */ 3088 if (fw.or_valid) { 3089 snprintf(adapter->fw_version, 3090 sizeof(adapter->fw_version), 3091 "%d.%d, 0x%08x, %d.%d.%d", 3092 fw.eep_major, fw.eep_minor, fw.etrack_id, 3093 fw.or_major, fw.or_build, fw.or_patch); 3094 /* no option rom */ 3095 } else if (fw.etrack_id != 0X0000) { 3096 snprintf(adapter->fw_version, 3097 sizeof(adapter->fw_version), 3098 "%d.%d, 0x%08x", 3099 fw.eep_major, fw.eep_minor, fw.etrack_id); 3100 } else { 3101 snprintf(adapter->fw_version, 3102 sizeof(adapter->fw_version), 3103 "%d.%d.%d", 3104 fw.eep_major, fw.eep_minor, fw.eep_build); 3105 } 3106 break; 3107 } 3108 } 3109 3110 /** 3111 * igb_init_mas - init Media Autosense feature if enabled in the NVM 3112 * 3113 * @adapter: adapter struct 3114 **/ 3115 static void igb_init_mas(struct igb_adapter *adapter) 3116 { 3117 struct e1000_hw *hw = &adapter->hw; 3118 u16 eeprom_data; 3119 3120 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 3121 switch (hw->bus.func) { 3122 case E1000_FUNC_0: 3123 if (eeprom_data & IGB_MAS_ENABLE_0) { 3124 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3125 netdev_info(adapter->netdev, 3126 "MAS: Enabling Media Autosense for port %d\n", 3127 hw->bus.func); 3128 } 3129 break; 3130 case E1000_FUNC_1: 3131 if (eeprom_data & IGB_MAS_ENABLE_1) { 3132 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3133 netdev_info(adapter->netdev, 3134 "MAS: Enabling Media Autosense for port %d\n", 3135 hw->bus.func); 3136 } 3137 break; 3138 case E1000_FUNC_2: 3139 if (eeprom_data & IGB_MAS_ENABLE_2) { 3140 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3141 netdev_info(adapter->netdev, 3142 "MAS: Enabling Media Autosense for port %d\n", 3143 hw->bus.func); 3144 } 3145 break; 3146 case E1000_FUNC_3: 3147 if (eeprom_data & IGB_MAS_ENABLE_3) { 3148 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3149 netdev_info(adapter->netdev, 3150 "MAS: Enabling Media Autosense for port %d\n", 3151 hw->bus.func); 3152 } 3153 break; 3154 default: 3155 /* Shouldn't get here */ 3156 netdev_err(adapter->netdev, 3157 "MAS: Invalid port configuration, returning\n"); 3158 break; 3159 } 3160 } 3161 3162 /** 3163 * igb_init_i2c - Init I2C interface 3164 * @adapter: pointer to adapter structure 3165 **/ 3166 static s32 igb_init_i2c(struct igb_adapter *adapter) 3167 { 3168 s32 status = 0; 3169 3170 /* I2C interface supported on i350 devices */ 3171 if (adapter->hw.mac.type != e1000_i350) 3172 return 0; 3173 3174 /* Initialize the i2c bus which is controlled by the registers. 3175 * This bus will use the i2c_algo_bit structure that implements 3176 * the protocol through toggling of the 4 bits in the register. 3177 */ 3178 adapter->i2c_adap.owner = THIS_MODULE; 3179 adapter->i2c_algo = igb_i2c_algo; 3180 adapter->i2c_algo.data = adapter; 3181 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 3182 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 3183 strscpy(adapter->i2c_adap.name, "igb BB", 3184 sizeof(adapter->i2c_adap.name)); 3185 status = i2c_bit_add_bus(&adapter->i2c_adap); 3186 return status; 3187 } 3188 3189 /** 3190 * igb_probe - Device Initialization Routine 3191 * @pdev: PCI device information struct 3192 * @ent: entry in igb_pci_tbl 3193 * 3194 * Returns 0 on success, negative on failure 3195 * 3196 * igb_probe initializes an adapter identified by a pci_dev structure. 3197 * The OS initialization, configuring of the adapter private structure, 3198 * and a hardware reset occur. 3199 **/ 3200 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3201 { 3202 struct net_device *netdev; 3203 struct igb_adapter *adapter; 3204 struct e1000_hw *hw; 3205 u16 eeprom_data = 0; 3206 s32 ret_val; 3207 static int global_quad_port_a; /* global quad port a indication */ 3208 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3209 u8 part_str[E1000_PBANUM_LENGTH]; 3210 int err; 3211 3212 /* Catch broken hardware that put the wrong VF device ID in 3213 * the PCIe SR-IOV capability. 3214 */ 3215 if (pdev->is_virtfn) { 3216 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n", 3217 pci_name(pdev), pdev->vendor, pdev->device); 3218 return -EINVAL; 3219 } 3220 3221 err = pci_enable_device_mem(pdev); 3222 if (err) 3223 return err; 3224 3225 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3226 if (err) { 3227 dev_err(&pdev->dev, 3228 "No usable DMA configuration, aborting\n"); 3229 goto err_dma; 3230 } 3231 3232 err = pci_request_mem_regions(pdev, igb_driver_name); 3233 if (err) 3234 goto err_pci_reg; 3235 3236 pci_set_master(pdev); 3237 pci_save_state(pdev); 3238 3239 err = -ENOMEM; 3240 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3241 IGB_MAX_TX_QUEUES); 3242 if (!netdev) 3243 goto err_alloc_etherdev; 3244 3245 SET_NETDEV_DEV(netdev, &pdev->dev); 3246 3247 pci_set_drvdata(pdev, netdev); 3248 adapter = netdev_priv(netdev); 3249 adapter->netdev = netdev; 3250 adapter->pdev = pdev; 3251 hw = &adapter->hw; 3252 hw->back = adapter; 3253 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3254 3255 err = -EIO; 3256 adapter->io_addr = pci_iomap(pdev, 0, 0); 3257 if (!adapter->io_addr) 3258 goto err_ioremap; 3259 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3260 hw->hw_addr = adapter->io_addr; 3261 3262 netdev->netdev_ops = &igb_netdev_ops; 3263 igb_set_ethtool_ops(netdev); 3264 netdev->watchdog_timeo = 5 * HZ; 3265 3266 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 3267 3268 netdev->mem_start = pci_resource_start(pdev, 0); 3269 netdev->mem_end = pci_resource_end(pdev, 0); 3270 3271 /* PCI config space info */ 3272 hw->vendor_id = pdev->vendor; 3273 hw->device_id = pdev->device; 3274 hw->revision_id = pdev->revision; 3275 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3276 hw->subsystem_device_id = pdev->subsystem_device; 3277 3278 /* Copy the default MAC, PHY and NVM function pointers */ 3279 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3280 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3281 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3282 /* Initialize skew-specific constants */ 3283 err = ei->get_invariants(hw); 3284 if (err) 3285 goto err_sw_init; 3286 3287 /* setup the private structure */ 3288 err = igb_sw_init(adapter); 3289 if (err) 3290 goto err_sw_init; 3291 3292 igb_get_bus_info_pcie(hw); 3293 3294 hw->phy.autoneg_wait_to_complete = false; 3295 3296 /* Copper options */ 3297 if (hw->phy.media_type == e1000_media_type_copper) { 3298 hw->phy.mdix = AUTO_ALL_MODES; 3299 hw->phy.disable_polarity_correction = false; 3300 hw->phy.ms_type = e1000_ms_hw_default; 3301 } 3302 3303 if (igb_check_reset_block(hw)) 3304 dev_info(&pdev->dev, 3305 "PHY reset is blocked due to SOL/IDER session.\n"); 3306 3307 /* features is initialized to 0 in allocation, it might have bits 3308 * set by igb_sw_init so we should use an or instead of an 3309 * assignment. 3310 */ 3311 netdev->features |= NETIF_F_SG | 3312 NETIF_F_TSO | 3313 NETIF_F_TSO6 | 3314 NETIF_F_RXHASH | 3315 NETIF_F_RXCSUM | 3316 NETIF_F_HW_CSUM; 3317 3318 if (hw->mac.type >= e1000_82576) 3319 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 3320 3321 if (hw->mac.type >= e1000_i350) 3322 netdev->features |= NETIF_F_HW_TC; 3323 3324 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3325 NETIF_F_GSO_GRE_CSUM | \ 3326 NETIF_F_GSO_IPXIP4 | \ 3327 NETIF_F_GSO_IPXIP6 | \ 3328 NETIF_F_GSO_UDP_TUNNEL | \ 3329 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3330 3331 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3332 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3333 3334 /* copy netdev features into list of user selectable features */ 3335 netdev->hw_features |= netdev->features | 3336 NETIF_F_HW_VLAN_CTAG_RX | 3337 NETIF_F_HW_VLAN_CTAG_TX | 3338 NETIF_F_RXALL; 3339 3340 if (hw->mac.type >= e1000_i350) 3341 netdev->hw_features |= NETIF_F_NTUPLE; 3342 3343 netdev->features |= NETIF_F_HIGHDMA; 3344 3345 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3346 netdev->mpls_features |= NETIF_F_HW_CSUM; 3347 netdev->hw_enc_features |= netdev->vlan_features; 3348 3349 /* set this bit last since it cannot be part of vlan_features */ 3350 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3351 NETIF_F_HW_VLAN_CTAG_RX | 3352 NETIF_F_HW_VLAN_CTAG_TX; 3353 3354 netdev->priv_flags |= IFF_SUPP_NOFCS; 3355 3356 netdev->priv_flags |= IFF_UNICAST_FLT; 3357 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT; 3358 3359 /* MTU range: 68 - 9216 */ 3360 netdev->min_mtu = ETH_MIN_MTU; 3361 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3362 3363 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3364 3365 /* before reading the NVM, reset the controller to put the device in a 3366 * known good starting state 3367 */ 3368 hw->mac.ops.reset_hw(hw); 3369 3370 /* make sure the NVM is good , i211/i210 parts can have special NVM 3371 * that doesn't contain a checksum 3372 */ 3373 switch (hw->mac.type) { 3374 case e1000_i210: 3375 case e1000_i211: 3376 if (igb_get_flash_presence_i210(hw)) { 3377 if (hw->nvm.ops.validate(hw) < 0) { 3378 dev_err(&pdev->dev, 3379 "The NVM Checksum Is Not Valid\n"); 3380 err = -EIO; 3381 goto err_eeprom; 3382 } 3383 } 3384 break; 3385 default: 3386 if (hw->nvm.ops.validate(hw) < 0) { 3387 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3388 err = -EIO; 3389 goto err_eeprom; 3390 } 3391 break; 3392 } 3393 3394 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3395 /* copy the MAC address out of the NVM */ 3396 if (hw->mac.ops.read_mac_addr(hw)) 3397 dev_err(&pdev->dev, "NVM Read Error\n"); 3398 } 3399 3400 eth_hw_addr_set(netdev, hw->mac.addr); 3401 3402 if (!is_valid_ether_addr(netdev->dev_addr)) { 3403 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3404 err = -EIO; 3405 goto err_eeprom; 3406 } 3407 3408 igb_set_default_mac_filter(adapter); 3409 3410 /* get firmware version for ethtool -i */ 3411 igb_set_fw_version(adapter); 3412 3413 /* configure RXPBSIZE and TXPBSIZE */ 3414 if (hw->mac.type == e1000_i210) { 3415 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3416 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3417 } 3418 3419 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3420 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3421 3422 INIT_WORK(&adapter->reset_task, igb_reset_task); 3423 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3424 3425 /* Initialize link properties that are user-changeable */ 3426 adapter->fc_autoneg = true; 3427 hw->mac.autoneg = true; 3428 hw->phy.autoneg_advertised = 0x2f; 3429 3430 hw->fc.requested_mode = e1000_fc_default; 3431 hw->fc.current_mode = e1000_fc_default; 3432 3433 igb_validate_mdi_setting(hw); 3434 3435 /* By default, support wake on port A */ 3436 if (hw->bus.func == 0) 3437 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3438 3439 /* Check the NVM for wake support on non-port A ports */ 3440 if (hw->mac.type >= e1000_82580) 3441 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3442 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3443 &eeprom_data); 3444 else if (hw->bus.func == 1) 3445 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3446 3447 if (eeprom_data & IGB_EEPROM_APME) 3448 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3449 3450 /* now that we have the eeprom settings, apply the special cases where 3451 * the eeprom may be wrong or the board simply won't support wake on 3452 * lan on a particular port 3453 */ 3454 switch (pdev->device) { 3455 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3456 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3457 break; 3458 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3459 case E1000_DEV_ID_82576_FIBER: 3460 case E1000_DEV_ID_82576_SERDES: 3461 /* Wake events only supported on port A for dual fiber 3462 * regardless of eeprom setting 3463 */ 3464 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3465 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3466 break; 3467 case E1000_DEV_ID_82576_QUAD_COPPER: 3468 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3469 /* if quad port adapter, disable WoL on all but port A */ 3470 if (global_quad_port_a != 0) 3471 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3472 else 3473 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3474 /* Reset for multiple quad port adapters */ 3475 if (++global_quad_port_a == 4) 3476 global_quad_port_a = 0; 3477 break; 3478 default: 3479 /* If the device can't wake, don't set software support */ 3480 if (!device_can_wakeup(&adapter->pdev->dev)) 3481 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3482 } 3483 3484 /* initialize the wol settings based on the eeprom settings */ 3485 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3486 adapter->wol |= E1000_WUFC_MAG; 3487 3488 /* Some vendors want WoL disabled by default, but still supported */ 3489 if ((hw->mac.type == e1000_i350) && 3490 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3491 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3492 adapter->wol = 0; 3493 } 3494 3495 /* Some vendors want the ability to Use the EEPROM setting as 3496 * enable/disable only, and not for capability 3497 */ 3498 if (((hw->mac.type == e1000_i350) || 3499 (hw->mac.type == e1000_i354)) && 3500 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3501 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3502 adapter->wol = 0; 3503 } 3504 if (hw->mac.type == e1000_i350) { 3505 if (((pdev->subsystem_device == 0x5001) || 3506 (pdev->subsystem_device == 0x5002)) && 3507 (hw->bus.func == 0)) { 3508 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3509 adapter->wol = 0; 3510 } 3511 if (pdev->subsystem_device == 0x1F52) 3512 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3513 } 3514 3515 device_set_wakeup_enable(&adapter->pdev->dev, 3516 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3517 3518 /* reset the hardware with the new settings */ 3519 igb_reset(adapter); 3520 3521 /* Init the I2C interface */ 3522 err = igb_init_i2c(adapter); 3523 if (err) { 3524 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3525 goto err_eeprom; 3526 } 3527 3528 /* let the f/w know that the h/w is now under the control of the 3529 * driver. 3530 */ 3531 igb_get_hw_control(adapter); 3532 3533 strcpy(netdev->name, "eth%d"); 3534 err = register_netdev(netdev); 3535 if (err) 3536 goto err_register; 3537 3538 /* carrier off reporting is important to ethtool even BEFORE open */ 3539 netif_carrier_off(netdev); 3540 3541 #ifdef CONFIG_IGB_DCA 3542 if (dca_add_requester(&pdev->dev) == 0) { 3543 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3544 dev_info(&pdev->dev, "DCA enabled\n"); 3545 igb_setup_dca(adapter); 3546 } 3547 3548 #endif 3549 #ifdef CONFIG_IGB_HWMON 3550 /* Initialize the thermal sensor on i350 devices. */ 3551 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3552 u16 ets_word; 3553 3554 /* Read the NVM to determine if this i350 device supports an 3555 * external thermal sensor. 3556 */ 3557 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3558 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3559 adapter->ets = true; 3560 else 3561 adapter->ets = false; 3562 /* Only enable I2C bit banging if an external thermal 3563 * sensor is supported. 3564 */ 3565 if (adapter->ets) 3566 igb_set_i2c_bb(hw); 3567 hw->mac.ops.init_thermal_sensor_thresh(hw); 3568 if (igb_sysfs_init(adapter)) 3569 dev_err(&pdev->dev, 3570 "failed to allocate sysfs resources\n"); 3571 } else { 3572 adapter->ets = false; 3573 } 3574 #endif 3575 /* Check if Media Autosense is enabled */ 3576 adapter->ei = *ei; 3577 if (hw->dev_spec._82575.mas_capable) 3578 igb_init_mas(adapter); 3579 3580 /* do hw tstamp init after resetting */ 3581 igb_ptp_init(adapter); 3582 3583 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3584 /* print bus type/speed/width info, not applicable to i354 */ 3585 if (hw->mac.type != e1000_i354) { 3586 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3587 netdev->name, 3588 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3589 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3590 "unknown"), 3591 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3592 "Width x4" : 3593 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3594 "Width x2" : 3595 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3596 "Width x1" : "unknown"), netdev->dev_addr); 3597 } 3598 3599 if ((hw->mac.type == e1000_82576 && 3600 rd32(E1000_EECD) & E1000_EECD_PRES) || 3601 (hw->mac.type >= e1000_i210 || 3602 igb_get_flash_presence_i210(hw))) { 3603 ret_val = igb_read_part_string(hw, part_str, 3604 E1000_PBANUM_LENGTH); 3605 } else { 3606 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3607 } 3608 3609 if (ret_val) 3610 strcpy(part_str, "Unknown"); 3611 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3612 dev_info(&pdev->dev, 3613 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3614 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3615 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3616 adapter->num_rx_queues, adapter->num_tx_queues); 3617 if (hw->phy.media_type == e1000_media_type_copper) { 3618 switch (hw->mac.type) { 3619 case e1000_i350: 3620 case e1000_i210: 3621 case e1000_i211: 3622 /* Enable EEE for internal copper PHY devices */ 3623 err = igb_set_eee_i350(hw, true, true); 3624 if ((!err) && 3625 (!hw->dev_spec._82575.eee_disable)) { 3626 adapter->eee_advert = 3627 MDIO_EEE_100TX | MDIO_EEE_1000T; 3628 adapter->flags |= IGB_FLAG_EEE; 3629 } 3630 break; 3631 case e1000_i354: 3632 if ((rd32(E1000_CTRL_EXT) & 3633 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3634 err = igb_set_eee_i354(hw, true, true); 3635 if ((!err) && 3636 (!hw->dev_spec._82575.eee_disable)) { 3637 adapter->eee_advert = 3638 MDIO_EEE_100TX | MDIO_EEE_1000T; 3639 adapter->flags |= IGB_FLAG_EEE; 3640 } 3641 } 3642 break; 3643 default: 3644 break; 3645 } 3646 } 3647 3648 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 3649 3650 pm_runtime_put_noidle(&pdev->dev); 3651 return 0; 3652 3653 err_register: 3654 igb_release_hw_control(adapter); 3655 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3656 err_eeprom: 3657 if (!igb_check_reset_block(hw)) 3658 igb_reset_phy(hw); 3659 3660 if (hw->flash_address) 3661 iounmap(hw->flash_address); 3662 err_sw_init: 3663 kfree(adapter->mac_table); 3664 kfree(adapter->shadow_vfta); 3665 igb_clear_interrupt_scheme(adapter); 3666 #ifdef CONFIG_PCI_IOV 3667 igb_disable_sriov(pdev); 3668 #endif 3669 pci_iounmap(pdev, adapter->io_addr); 3670 err_ioremap: 3671 free_netdev(netdev); 3672 err_alloc_etherdev: 3673 pci_release_mem_regions(pdev); 3674 err_pci_reg: 3675 err_dma: 3676 pci_disable_device(pdev); 3677 return err; 3678 } 3679 3680 #ifdef CONFIG_PCI_IOV 3681 static int igb_disable_sriov(struct pci_dev *pdev) 3682 { 3683 struct net_device *netdev = pci_get_drvdata(pdev); 3684 struct igb_adapter *adapter = netdev_priv(netdev); 3685 struct e1000_hw *hw = &adapter->hw; 3686 unsigned long flags; 3687 3688 /* reclaim resources allocated to VFs */ 3689 if (adapter->vf_data) { 3690 /* disable iov and allow time for transactions to clear */ 3691 if (pci_vfs_assigned(pdev)) { 3692 dev_warn(&pdev->dev, 3693 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3694 return -EPERM; 3695 } else { 3696 pci_disable_sriov(pdev); 3697 msleep(500); 3698 } 3699 spin_lock_irqsave(&adapter->vfs_lock, flags); 3700 kfree(adapter->vf_mac_list); 3701 adapter->vf_mac_list = NULL; 3702 kfree(adapter->vf_data); 3703 adapter->vf_data = NULL; 3704 adapter->vfs_allocated_count = 0; 3705 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 3706 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3707 wrfl(); 3708 msleep(100); 3709 dev_info(&pdev->dev, "IOV Disabled\n"); 3710 3711 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3712 adapter->flags |= IGB_FLAG_DMAC; 3713 } 3714 3715 return 0; 3716 } 3717 3718 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 3719 { 3720 struct net_device *netdev = pci_get_drvdata(pdev); 3721 struct igb_adapter *adapter = netdev_priv(netdev); 3722 int old_vfs = pci_num_vf(pdev); 3723 struct vf_mac_filter *mac_list; 3724 int err = 0; 3725 int num_vf_mac_filters, i; 3726 3727 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3728 err = -EPERM; 3729 goto out; 3730 } 3731 if (!num_vfs) 3732 goto out; 3733 3734 if (old_vfs) { 3735 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3736 old_vfs, max_vfs); 3737 adapter->vfs_allocated_count = old_vfs; 3738 } else 3739 adapter->vfs_allocated_count = num_vfs; 3740 3741 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3742 sizeof(struct vf_data_storage), GFP_KERNEL); 3743 3744 /* if allocation failed then we do not support SR-IOV */ 3745 if (!adapter->vf_data) { 3746 adapter->vfs_allocated_count = 0; 3747 err = -ENOMEM; 3748 goto out; 3749 } 3750 3751 /* Due to the limited number of RAR entries calculate potential 3752 * number of MAC filters available for the VFs. Reserve entries 3753 * for PF default MAC, PF MAC filters and at least one RAR entry 3754 * for each VF for VF MAC. 3755 */ 3756 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3757 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3758 adapter->vfs_allocated_count); 3759 3760 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3761 sizeof(struct vf_mac_filter), 3762 GFP_KERNEL); 3763 3764 mac_list = adapter->vf_mac_list; 3765 INIT_LIST_HEAD(&adapter->vf_macs.l); 3766 3767 if (adapter->vf_mac_list) { 3768 /* Initialize list of VF MAC filters */ 3769 for (i = 0; i < num_vf_mac_filters; i++) { 3770 mac_list->vf = -1; 3771 mac_list->free = true; 3772 list_add(&mac_list->l, &adapter->vf_macs.l); 3773 mac_list++; 3774 } 3775 } else { 3776 /* If we could not allocate memory for the VF MAC filters 3777 * we can continue without this feature but warn user. 3778 */ 3779 dev_err(&pdev->dev, 3780 "Unable to allocate memory for VF MAC filter list\n"); 3781 } 3782 3783 /* only call pci_enable_sriov() if no VFs are allocated already */ 3784 if (!old_vfs) { 3785 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3786 if (err) 3787 goto err_out; 3788 } 3789 dev_info(&pdev->dev, "%d VFs allocated\n", 3790 adapter->vfs_allocated_count); 3791 for (i = 0; i < adapter->vfs_allocated_count; i++) 3792 igb_vf_configure(adapter, i); 3793 3794 /* DMA Coalescing is not supported in IOV mode. */ 3795 adapter->flags &= ~IGB_FLAG_DMAC; 3796 goto out; 3797 3798 err_out: 3799 kfree(adapter->vf_mac_list); 3800 adapter->vf_mac_list = NULL; 3801 kfree(adapter->vf_data); 3802 adapter->vf_data = NULL; 3803 adapter->vfs_allocated_count = 0; 3804 out: 3805 return err; 3806 } 3807 3808 #endif 3809 /** 3810 * igb_remove_i2c - Cleanup I2C interface 3811 * @adapter: pointer to adapter structure 3812 **/ 3813 static void igb_remove_i2c(struct igb_adapter *adapter) 3814 { 3815 /* free the adapter bus structure */ 3816 i2c_del_adapter(&adapter->i2c_adap); 3817 } 3818 3819 /** 3820 * igb_remove - Device Removal Routine 3821 * @pdev: PCI device information struct 3822 * 3823 * igb_remove is called by the PCI subsystem to alert the driver 3824 * that it should release a PCI device. The could be caused by a 3825 * Hot-Plug event, or because the driver is going to be removed from 3826 * memory. 3827 **/ 3828 static void igb_remove(struct pci_dev *pdev) 3829 { 3830 struct net_device *netdev = pci_get_drvdata(pdev); 3831 struct igb_adapter *adapter = netdev_priv(netdev); 3832 struct e1000_hw *hw = &adapter->hw; 3833 3834 pm_runtime_get_noresume(&pdev->dev); 3835 #ifdef CONFIG_IGB_HWMON 3836 igb_sysfs_exit(adapter); 3837 #endif 3838 igb_remove_i2c(adapter); 3839 igb_ptp_stop(adapter); 3840 /* The watchdog timer may be rescheduled, so explicitly 3841 * disable watchdog from being rescheduled. 3842 */ 3843 set_bit(__IGB_DOWN, &adapter->state); 3844 del_timer_sync(&adapter->watchdog_timer); 3845 del_timer_sync(&adapter->phy_info_timer); 3846 3847 cancel_work_sync(&adapter->reset_task); 3848 cancel_work_sync(&adapter->watchdog_task); 3849 3850 #ifdef CONFIG_IGB_DCA 3851 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3852 dev_info(&pdev->dev, "DCA disabled\n"); 3853 dca_remove_requester(&pdev->dev); 3854 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3855 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3856 } 3857 #endif 3858 3859 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3860 * would have already happened in close and is redundant. 3861 */ 3862 igb_release_hw_control(adapter); 3863 3864 #ifdef CONFIG_PCI_IOV 3865 rtnl_lock(); 3866 igb_disable_sriov(pdev); 3867 rtnl_unlock(); 3868 #endif 3869 3870 unregister_netdev(netdev); 3871 3872 igb_clear_interrupt_scheme(adapter); 3873 3874 pci_iounmap(pdev, adapter->io_addr); 3875 if (hw->flash_address) 3876 iounmap(hw->flash_address); 3877 pci_release_mem_regions(pdev); 3878 3879 kfree(adapter->mac_table); 3880 kfree(adapter->shadow_vfta); 3881 free_netdev(netdev); 3882 3883 pci_disable_device(pdev); 3884 } 3885 3886 /** 3887 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3888 * @adapter: board private structure to initialize 3889 * 3890 * This function initializes the vf specific data storage and then attempts to 3891 * allocate the VFs. The reason for ordering it this way is because it is much 3892 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3893 * the memory for the VFs. 3894 **/ 3895 static void igb_probe_vfs(struct igb_adapter *adapter) 3896 { 3897 #ifdef CONFIG_PCI_IOV 3898 struct pci_dev *pdev = adapter->pdev; 3899 struct e1000_hw *hw = &adapter->hw; 3900 3901 /* Virtualization features not supported on i210 family. */ 3902 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 3903 return; 3904 3905 /* Of the below we really only want the effect of getting 3906 * IGB_FLAG_HAS_MSIX set (if available), without which 3907 * igb_enable_sriov() has no effect. 3908 */ 3909 igb_set_interrupt_capability(adapter, true); 3910 igb_reset_interrupt_capability(adapter); 3911 3912 pci_sriov_set_totalvfs(pdev, 7); 3913 igb_enable_sriov(pdev, max_vfs); 3914 3915 #endif /* CONFIG_PCI_IOV */ 3916 } 3917 3918 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3919 { 3920 struct e1000_hw *hw = &adapter->hw; 3921 unsigned int max_rss_queues; 3922 3923 /* Determine the maximum number of RSS queues supported. */ 3924 switch (hw->mac.type) { 3925 case e1000_i211: 3926 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3927 break; 3928 case e1000_82575: 3929 case e1000_i210: 3930 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3931 break; 3932 case e1000_i350: 3933 /* I350 cannot do RSS and SR-IOV at the same time */ 3934 if (!!adapter->vfs_allocated_count) { 3935 max_rss_queues = 1; 3936 break; 3937 } 3938 fallthrough; 3939 case e1000_82576: 3940 if (!!adapter->vfs_allocated_count) { 3941 max_rss_queues = 2; 3942 break; 3943 } 3944 fallthrough; 3945 case e1000_82580: 3946 case e1000_i354: 3947 default: 3948 max_rss_queues = IGB_MAX_RX_QUEUES; 3949 break; 3950 } 3951 3952 return max_rss_queues; 3953 } 3954 3955 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3956 { 3957 u32 max_rss_queues; 3958 3959 max_rss_queues = igb_get_max_rss_queues(adapter); 3960 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3961 3962 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3963 } 3964 3965 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3966 const u32 max_rss_queues) 3967 { 3968 struct e1000_hw *hw = &adapter->hw; 3969 3970 /* Determine if we need to pair queues. */ 3971 switch (hw->mac.type) { 3972 case e1000_82575: 3973 case e1000_i211: 3974 /* Device supports enough interrupts without queue pairing. */ 3975 break; 3976 case e1000_82576: 3977 case e1000_82580: 3978 case e1000_i350: 3979 case e1000_i354: 3980 case e1000_i210: 3981 default: 3982 /* If rss_queues > half of max_rss_queues, pair the queues in 3983 * order to conserve interrupts due to limited supply. 3984 */ 3985 if (adapter->rss_queues > (max_rss_queues / 2)) 3986 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3987 else 3988 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 3989 break; 3990 } 3991 } 3992 3993 /** 3994 * igb_sw_init - Initialize general software structures (struct igb_adapter) 3995 * @adapter: board private structure to initialize 3996 * 3997 * igb_sw_init initializes the Adapter private data structure. 3998 * Fields are initialized based on PCI device information and 3999 * OS network device settings (MTU size). 4000 **/ 4001 static int igb_sw_init(struct igb_adapter *adapter) 4002 { 4003 struct e1000_hw *hw = &adapter->hw; 4004 struct net_device *netdev = adapter->netdev; 4005 struct pci_dev *pdev = adapter->pdev; 4006 4007 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 4008 4009 /* set default ring sizes */ 4010 adapter->tx_ring_count = IGB_DEFAULT_TXD; 4011 adapter->rx_ring_count = IGB_DEFAULT_RXD; 4012 4013 /* set default ITR values */ 4014 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 4015 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 4016 4017 /* set default work limits */ 4018 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 4019 4020 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD; 4021 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4022 4023 spin_lock_init(&adapter->nfc_lock); 4024 spin_lock_init(&adapter->stats64_lock); 4025 4026 /* init spinlock to avoid concurrency of VF resources */ 4027 spin_lock_init(&adapter->vfs_lock); 4028 #ifdef CONFIG_PCI_IOV 4029 switch (hw->mac.type) { 4030 case e1000_82576: 4031 case e1000_i350: 4032 if (max_vfs > 7) { 4033 dev_warn(&pdev->dev, 4034 "Maximum of 7 VFs per PF, using max\n"); 4035 max_vfs = adapter->vfs_allocated_count = 7; 4036 } else 4037 adapter->vfs_allocated_count = max_vfs; 4038 if (adapter->vfs_allocated_count) 4039 dev_warn(&pdev->dev, 4040 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 4041 break; 4042 default: 4043 break; 4044 } 4045 #endif /* CONFIG_PCI_IOV */ 4046 4047 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 4048 adapter->flags |= IGB_FLAG_HAS_MSIX; 4049 4050 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 4051 sizeof(struct igb_mac_addr), 4052 GFP_KERNEL); 4053 if (!adapter->mac_table) 4054 return -ENOMEM; 4055 4056 igb_probe_vfs(adapter); 4057 4058 igb_init_queue_configuration(adapter); 4059 4060 /* Setup and initialize a copy of the hw vlan table array */ 4061 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 4062 GFP_KERNEL); 4063 if (!adapter->shadow_vfta) 4064 return -ENOMEM; 4065 4066 /* This call may decrease the number of queues */ 4067 if (igb_init_interrupt_scheme(adapter, true)) { 4068 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4069 return -ENOMEM; 4070 } 4071 4072 /* Explicitly disable IRQ since the NIC can be in any state. */ 4073 igb_irq_disable(adapter); 4074 4075 if (hw->mac.type >= e1000_i350) 4076 adapter->flags &= ~IGB_FLAG_DMAC; 4077 4078 set_bit(__IGB_DOWN, &adapter->state); 4079 return 0; 4080 } 4081 4082 /** 4083 * __igb_open - Called when a network interface is made active 4084 * @netdev: network interface device structure 4085 * @resuming: indicates whether we are in a resume call 4086 * 4087 * Returns 0 on success, negative value on failure 4088 * 4089 * The open entry point is called when a network interface is made 4090 * active by the system (IFF_UP). At this point all resources needed 4091 * for transmit and receive operations are allocated, the interrupt 4092 * handler is registered with the OS, the watchdog timer is started, 4093 * and the stack is notified that the interface is ready. 4094 **/ 4095 static int __igb_open(struct net_device *netdev, bool resuming) 4096 { 4097 struct igb_adapter *adapter = netdev_priv(netdev); 4098 struct e1000_hw *hw = &adapter->hw; 4099 struct pci_dev *pdev = adapter->pdev; 4100 int err; 4101 int i; 4102 4103 /* disallow open during test */ 4104 if (test_bit(__IGB_TESTING, &adapter->state)) { 4105 WARN_ON(resuming); 4106 return -EBUSY; 4107 } 4108 4109 if (!resuming) 4110 pm_runtime_get_sync(&pdev->dev); 4111 4112 netif_carrier_off(netdev); 4113 4114 /* allocate transmit descriptors */ 4115 err = igb_setup_all_tx_resources(adapter); 4116 if (err) 4117 goto err_setup_tx; 4118 4119 /* allocate receive descriptors */ 4120 err = igb_setup_all_rx_resources(adapter); 4121 if (err) 4122 goto err_setup_rx; 4123 4124 igb_power_up_link(adapter); 4125 4126 /* before we allocate an interrupt, we must be ready to handle it. 4127 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4128 * as soon as we call pci_request_irq, so we have to setup our 4129 * clean_rx handler before we do so. 4130 */ 4131 igb_configure(adapter); 4132 4133 err = igb_request_irq(adapter); 4134 if (err) 4135 goto err_req_irq; 4136 4137 /* Notify the stack of the actual queue counts. */ 4138 err = netif_set_real_num_tx_queues(adapter->netdev, 4139 adapter->num_tx_queues); 4140 if (err) 4141 goto err_set_queues; 4142 4143 err = netif_set_real_num_rx_queues(adapter->netdev, 4144 adapter->num_rx_queues); 4145 if (err) 4146 goto err_set_queues; 4147 4148 /* From here on the code is the same as igb_up() */ 4149 clear_bit(__IGB_DOWN, &adapter->state); 4150 4151 for (i = 0; i < adapter->num_q_vectors; i++) 4152 napi_enable(&(adapter->q_vector[i]->napi)); 4153 4154 /* Clear any pending interrupts. */ 4155 rd32(E1000_TSICR); 4156 rd32(E1000_ICR); 4157 4158 igb_irq_enable(adapter); 4159 4160 /* notify VFs that reset has been completed */ 4161 if (adapter->vfs_allocated_count) { 4162 u32 reg_data = rd32(E1000_CTRL_EXT); 4163 4164 reg_data |= E1000_CTRL_EXT_PFRSTD; 4165 wr32(E1000_CTRL_EXT, reg_data); 4166 } 4167 4168 netif_tx_start_all_queues(netdev); 4169 4170 if (!resuming) 4171 pm_runtime_put(&pdev->dev); 4172 4173 /* start the watchdog. */ 4174 hw->mac.get_link_status = 1; 4175 schedule_work(&adapter->watchdog_task); 4176 4177 return 0; 4178 4179 err_set_queues: 4180 igb_free_irq(adapter); 4181 err_req_irq: 4182 igb_release_hw_control(adapter); 4183 igb_power_down_link(adapter); 4184 igb_free_all_rx_resources(adapter); 4185 err_setup_rx: 4186 igb_free_all_tx_resources(adapter); 4187 err_setup_tx: 4188 igb_reset(adapter); 4189 if (!resuming) 4190 pm_runtime_put(&pdev->dev); 4191 4192 return err; 4193 } 4194 4195 int igb_open(struct net_device *netdev) 4196 { 4197 return __igb_open(netdev, false); 4198 } 4199 4200 /** 4201 * __igb_close - Disables a network interface 4202 * @netdev: network interface device structure 4203 * @suspending: indicates we are in a suspend call 4204 * 4205 * Returns 0, this is not allowed to fail 4206 * 4207 * The close entry point is called when an interface is de-activated 4208 * by the OS. The hardware is still under the driver's control, but 4209 * needs to be disabled. A global MAC reset is issued to stop the 4210 * hardware, and all transmit and receive resources are freed. 4211 **/ 4212 static int __igb_close(struct net_device *netdev, bool suspending) 4213 { 4214 struct igb_adapter *adapter = netdev_priv(netdev); 4215 struct pci_dev *pdev = adapter->pdev; 4216 4217 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4218 4219 if (!suspending) 4220 pm_runtime_get_sync(&pdev->dev); 4221 4222 igb_down(adapter); 4223 igb_free_irq(adapter); 4224 4225 igb_free_all_tx_resources(adapter); 4226 igb_free_all_rx_resources(adapter); 4227 4228 if (!suspending) 4229 pm_runtime_put_sync(&pdev->dev); 4230 return 0; 4231 } 4232 4233 int igb_close(struct net_device *netdev) 4234 { 4235 if (netif_device_present(netdev) || netdev->dismantle) 4236 return __igb_close(netdev, false); 4237 return 0; 4238 } 4239 4240 /** 4241 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4242 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4243 * 4244 * Return 0 on success, negative on failure 4245 **/ 4246 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4247 { 4248 struct device *dev = tx_ring->dev; 4249 int size; 4250 4251 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4252 4253 tx_ring->tx_buffer_info = vmalloc(size); 4254 if (!tx_ring->tx_buffer_info) 4255 goto err; 4256 4257 /* round up to nearest 4K */ 4258 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4259 tx_ring->size = ALIGN(tx_ring->size, 4096); 4260 4261 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4262 &tx_ring->dma, GFP_KERNEL); 4263 if (!tx_ring->desc) 4264 goto err; 4265 4266 tx_ring->next_to_use = 0; 4267 tx_ring->next_to_clean = 0; 4268 4269 return 0; 4270 4271 err: 4272 vfree(tx_ring->tx_buffer_info); 4273 tx_ring->tx_buffer_info = NULL; 4274 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4275 return -ENOMEM; 4276 } 4277 4278 /** 4279 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4280 * (Descriptors) for all queues 4281 * @adapter: board private structure 4282 * 4283 * Return 0 on success, negative on failure 4284 **/ 4285 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4286 { 4287 struct pci_dev *pdev = adapter->pdev; 4288 int i, err = 0; 4289 4290 for (i = 0; i < adapter->num_tx_queues; i++) { 4291 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4292 if (err) { 4293 dev_err(&pdev->dev, 4294 "Allocation for Tx Queue %u failed\n", i); 4295 for (i--; i >= 0; i--) 4296 igb_free_tx_resources(adapter->tx_ring[i]); 4297 break; 4298 } 4299 } 4300 4301 return err; 4302 } 4303 4304 /** 4305 * igb_setup_tctl - configure the transmit control registers 4306 * @adapter: Board private structure 4307 **/ 4308 void igb_setup_tctl(struct igb_adapter *adapter) 4309 { 4310 struct e1000_hw *hw = &adapter->hw; 4311 u32 tctl; 4312 4313 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4314 wr32(E1000_TXDCTL(0), 0); 4315 4316 /* Program the Transmit Control Register */ 4317 tctl = rd32(E1000_TCTL); 4318 tctl &= ~E1000_TCTL_CT; 4319 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4320 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4321 4322 igb_config_collision_dist(hw); 4323 4324 /* Enable transmits */ 4325 tctl |= E1000_TCTL_EN; 4326 4327 wr32(E1000_TCTL, tctl); 4328 } 4329 4330 /** 4331 * igb_configure_tx_ring - Configure transmit ring after Reset 4332 * @adapter: board private structure 4333 * @ring: tx ring to configure 4334 * 4335 * Configure a transmit ring after a reset. 4336 **/ 4337 void igb_configure_tx_ring(struct igb_adapter *adapter, 4338 struct igb_ring *ring) 4339 { 4340 struct e1000_hw *hw = &adapter->hw; 4341 u32 txdctl = 0; 4342 u64 tdba = ring->dma; 4343 int reg_idx = ring->reg_idx; 4344 4345 wr32(E1000_TDLEN(reg_idx), 4346 ring->count * sizeof(union e1000_adv_tx_desc)); 4347 wr32(E1000_TDBAL(reg_idx), 4348 tdba & 0x00000000ffffffffULL); 4349 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4350 4351 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4352 wr32(E1000_TDH(reg_idx), 0); 4353 writel(0, ring->tail); 4354 4355 txdctl |= IGB_TX_PTHRESH; 4356 txdctl |= IGB_TX_HTHRESH << 8; 4357 txdctl |= IGB_TX_WTHRESH << 16; 4358 4359 /* reinitialize tx_buffer_info */ 4360 memset(ring->tx_buffer_info, 0, 4361 sizeof(struct igb_tx_buffer) * ring->count); 4362 4363 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4364 wr32(E1000_TXDCTL(reg_idx), txdctl); 4365 } 4366 4367 /** 4368 * igb_configure_tx - Configure transmit Unit after Reset 4369 * @adapter: board private structure 4370 * 4371 * Configure the Tx unit of the MAC after a reset. 4372 **/ 4373 static void igb_configure_tx(struct igb_adapter *adapter) 4374 { 4375 struct e1000_hw *hw = &adapter->hw; 4376 int i; 4377 4378 /* disable the queues */ 4379 for (i = 0; i < adapter->num_tx_queues; i++) 4380 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4381 4382 wrfl(); 4383 usleep_range(10000, 20000); 4384 4385 for (i = 0; i < adapter->num_tx_queues; i++) 4386 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4387 } 4388 4389 /** 4390 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4391 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4392 * 4393 * Returns 0 on success, negative on failure 4394 **/ 4395 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4396 { 4397 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev); 4398 struct device *dev = rx_ring->dev; 4399 int size, res; 4400 4401 /* XDP RX-queue info */ 4402 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq)) 4403 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4404 res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 4405 rx_ring->queue_index, 0); 4406 if (res < 0) { 4407 dev_err(dev, "Failed to register xdp_rxq index %u\n", 4408 rx_ring->queue_index); 4409 return res; 4410 } 4411 4412 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4413 4414 rx_ring->rx_buffer_info = vmalloc(size); 4415 if (!rx_ring->rx_buffer_info) 4416 goto err; 4417 4418 /* Round up to nearest 4K */ 4419 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4420 rx_ring->size = ALIGN(rx_ring->size, 4096); 4421 4422 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4423 &rx_ring->dma, GFP_KERNEL); 4424 if (!rx_ring->desc) 4425 goto err; 4426 4427 rx_ring->next_to_alloc = 0; 4428 rx_ring->next_to_clean = 0; 4429 rx_ring->next_to_use = 0; 4430 4431 rx_ring->xdp_prog = adapter->xdp_prog; 4432 4433 return 0; 4434 4435 err: 4436 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4437 vfree(rx_ring->rx_buffer_info); 4438 rx_ring->rx_buffer_info = NULL; 4439 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4440 return -ENOMEM; 4441 } 4442 4443 /** 4444 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4445 * (Descriptors) for all queues 4446 * @adapter: board private structure 4447 * 4448 * Return 0 on success, negative on failure 4449 **/ 4450 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4451 { 4452 struct pci_dev *pdev = adapter->pdev; 4453 int i, err = 0; 4454 4455 for (i = 0; i < adapter->num_rx_queues; i++) { 4456 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4457 if (err) { 4458 dev_err(&pdev->dev, 4459 "Allocation for Rx Queue %u failed\n", i); 4460 for (i--; i >= 0; i--) 4461 igb_free_rx_resources(adapter->rx_ring[i]); 4462 break; 4463 } 4464 } 4465 4466 return err; 4467 } 4468 4469 /** 4470 * igb_setup_mrqc - configure the multiple receive queue control registers 4471 * @adapter: Board private structure 4472 **/ 4473 static void igb_setup_mrqc(struct igb_adapter *adapter) 4474 { 4475 struct e1000_hw *hw = &adapter->hw; 4476 u32 mrqc, rxcsum; 4477 u32 j, num_rx_queues; 4478 u32 rss_key[10]; 4479 4480 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4481 for (j = 0; j < 10; j++) 4482 wr32(E1000_RSSRK(j), rss_key[j]); 4483 4484 num_rx_queues = adapter->rss_queues; 4485 4486 switch (hw->mac.type) { 4487 case e1000_82576: 4488 /* 82576 supports 2 RSS queues for SR-IOV */ 4489 if (adapter->vfs_allocated_count) 4490 num_rx_queues = 2; 4491 break; 4492 default: 4493 break; 4494 } 4495 4496 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4497 for (j = 0; j < IGB_RETA_SIZE; j++) 4498 adapter->rss_indir_tbl[j] = 4499 (j * num_rx_queues) / IGB_RETA_SIZE; 4500 adapter->rss_indir_tbl_init = num_rx_queues; 4501 } 4502 igb_write_rss_indir_tbl(adapter); 4503 4504 /* Disable raw packet checksumming so that RSS hash is placed in 4505 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4506 * offloads as they are enabled by default 4507 */ 4508 rxcsum = rd32(E1000_RXCSUM); 4509 rxcsum |= E1000_RXCSUM_PCSD; 4510 4511 if (adapter->hw.mac.type >= e1000_82576) 4512 /* Enable Receive Checksum Offload for SCTP */ 4513 rxcsum |= E1000_RXCSUM_CRCOFL; 4514 4515 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4516 wr32(E1000_RXCSUM, rxcsum); 4517 4518 /* Generate RSS hash based on packet types, TCP/UDP 4519 * port numbers and/or IPv4/v6 src and dst addresses 4520 */ 4521 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4522 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4523 E1000_MRQC_RSS_FIELD_IPV6 | 4524 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4525 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4526 4527 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4528 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4529 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4530 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4531 4532 /* If VMDq is enabled then we set the appropriate mode for that, else 4533 * we default to RSS so that an RSS hash is calculated per packet even 4534 * if we are only using one queue 4535 */ 4536 if (adapter->vfs_allocated_count) { 4537 if (hw->mac.type > e1000_82575) { 4538 /* Set the default pool for the PF's first queue */ 4539 u32 vtctl = rd32(E1000_VT_CTL); 4540 4541 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4542 E1000_VT_CTL_DISABLE_DEF_POOL); 4543 vtctl |= adapter->vfs_allocated_count << 4544 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4545 wr32(E1000_VT_CTL, vtctl); 4546 } 4547 if (adapter->rss_queues > 1) 4548 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4549 else 4550 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4551 } else { 4552 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4553 } 4554 igb_vmm_control(adapter); 4555 4556 wr32(E1000_MRQC, mrqc); 4557 } 4558 4559 /** 4560 * igb_setup_rctl - configure the receive control registers 4561 * @adapter: Board private structure 4562 **/ 4563 void igb_setup_rctl(struct igb_adapter *adapter) 4564 { 4565 struct e1000_hw *hw = &adapter->hw; 4566 u32 rctl; 4567 4568 rctl = rd32(E1000_RCTL); 4569 4570 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4571 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4572 4573 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4574 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4575 4576 /* enable stripping of CRC. It's unlikely this will break BMC 4577 * redirection as it did with e1000. Newer features require 4578 * that the HW strips the CRC. 4579 */ 4580 rctl |= E1000_RCTL_SECRC; 4581 4582 /* disable store bad packets and clear size bits. */ 4583 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4584 4585 /* enable LPE to allow for reception of jumbo frames */ 4586 rctl |= E1000_RCTL_LPE; 4587 4588 /* disable queue 0 to prevent tail write w/o re-config */ 4589 wr32(E1000_RXDCTL(0), 0); 4590 4591 /* Attention!!! For SR-IOV PF driver operations you must enable 4592 * queue drop for all VF and PF queues to prevent head of line blocking 4593 * if an un-trusted VF does not provide descriptors to hardware. 4594 */ 4595 if (adapter->vfs_allocated_count) { 4596 /* set all queue drop enable bits */ 4597 wr32(E1000_QDE, ALL_QUEUES); 4598 } 4599 4600 /* This is useful for sniffing bad packets. */ 4601 if (adapter->netdev->features & NETIF_F_RXALL) { 4602 /* UPE and MPE will be handled by normal PROMISC logic 4603 * in e1000e_set_rx_mode 4604 */ 4605 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4606 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4607 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4608 4609 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4610 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4611 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4612 * and that breaks VLANs. 4613 */ 4614 } 4615 4616 wr32(E1000_RCTL, rctl); 4617 } 4618 4619 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4620 int vfn) 4621 { 4622 struct e1000_hw *hw = &adapter->hw; 4623 u32 vmolr; 4624 4625 if (size > MAX_JUMBO_FRAME_SIZE) 4626 size = MAX_JUMBO_FRAME_SIZE; 4627 4628 vmolr = rd32(E1000_VMOLR(vfn)); 4629 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4630 vmolr |= size | E1000_VMOLR_LPE; 4631 wr32(E1000_VMOLR(vfn), vmolr); 4632 4633 return 0; 4634 } 4635 4636 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4637 int vfn, bool enable) 4638 { 4639 struct e1000_hw *hw = &adapter->hw; 4640 u32 val, reg; 4641 4642 if (hw->mac.type < e1000_82576) 4643 return; 4644 4645 if (hw->mac.type == e1000_i350) 4646 reg = E1000_DVMOLR(vfn); 4647 else 4648 reg = E1000_VMOLR(vfn); 4649 4650 val = rd32(reg); 4651 if (enable) 4652 val |= E1000_VMOLR_STRVLAN; 4653 else 4654 val &= ~(E1000_VMOLR_STRVLAN); 4655 wr32(reg, val); 4656 } 4657 4658 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4659 int vfn, bool aupe) 4660 { 4661 struct e1000_hw *hw = &adapter->hw; 4662 u32 vmolr; 4663 4664 /* This register exists only on 82576 and newer so if we are older then 4665 * we should exit and do nothing 4666 */ 4667 if (hw->mac.type < e1000_82576) 4668 return; 4669 4670 vmolr = rd32(E1000_VMOLR(vfn)); 4671 if (aupe) 4672 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4673 else 4674 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4675 4676 /* clear all bits that might not be set */ 4677 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4678 4679 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4680 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4681 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4682 * multicast packets 4683 */ 4684 if (vfn <= adapter->vfs_allocated_count) 4685 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4686 4687 wr32(E1000_VMOLR(vfn), vmolr); 4688 } 4689 4690 /** 4691 * igb_setup_srrctl - configure the split and replication receive control 4692 * registers 4693 * @adapter: Board private structure 4694 * @ring: receive ring to be configured 4695 **/ 4696 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring) 4697 { 4698 struct e1000_hw *hw = &adapter->hw; 4699 int reg_idx = ring->reg_idx; 4700 u32 srrctl = 0; 4701 4702 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4703 if (ring_uses_large_buffer(ring)) 4704 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4705 else 4706 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4707 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4708 if (hw->mac.type >= e1000_82580) 4709 srrctl |= E1000_SRRCTL_TIMESTAMP; 4710 /* Only set Drop Enable if VFs allocated, or we are supporting multiple 4711 * queues and rx flow control is disabled 4712 */ 4713 if (adapter->vfs_allocated_count || 4714 (!(hw->fc.current_mode & e1000_fc_rx_pause) && 4715 adapter->num_rx_queues > 1)) 4716 srrctl |= E1000_SRRCTL_DROP_EN; 4717 4718 wr32(E1000_SRRCTL(reg_idx), srrctl); 4719 } 4720 4721 /** 4722 * igb_configure_rx_ring - Configure a receive ring after Reset 4723 * @adapter: board private structure 4724 * @ring: receive ring to be configured 4725 * 4726 * Configure the Rx unit of the MAC after a reset. 4727 **/ 4728 void igb_configure_rx_ring(struct igb_adapter *adapter, 4729 struct igb_ring *ring) 4730 { 4731 struct e1000_hw *hw = &adapter->hw; 4732 union e1000_adv_rx_desc *rx_desc; 4733 u64 rdba = ring->dma; 4734 int reg_idx = ring->reg_idx; 4735 u32 rxdctl = 0; 4736 4737 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4738 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4739 MEM_TYPE_PAGE_SHARED, NULL)); 4740 4741 /* disable the queue */ 4742 wr32(E1000_RXDCTL(reg_idx), 0); 4743 4744 /* Set DMA base address registers */ 4745 wr32(E1000_RDBAL(reg_idx), 4746 rdba & 0x00000000ffffffffULL); 4747 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4748 wr32(E1000_RDLEN(reg_idx), 4749 ring->count * sizeof(union e1000_adv_rx_desc)); 4750 4751 /* initialize head and tail */ 4752 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4753 wr32(E1000_RDH(reg_idx), 0); 4754 writel(0, ring->tail); 4755 4756 /* set descriptor configuration */ 4757 igb_setup_srrctl(adapter, ring); 4758 4759 /* set filtering for VMDQ pools */ 4760 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4761 4762 rxdctl |= IGB_RX_PTHRESH; 4763 rxdctl |= IGB_RX_HTHRESH << 8; 4764 rxdctl |= IGB_RX_WTHRESH << 16; 4765 4766 /* initialize rx_buffer_info */ 4767 memset(ring->rx_buffer_info, 0, 4768 sizeof(struct igb_rx_buffer) * ring->count); 4769 4770 /* initialize Rx descriptor 0 */ 4771 rx_desc = IGB_RX_DESC(ring, 0); 4772 rx_desc->wb.upper.length = 0; 4773 4774 /* enable receive descriptor fetching */ 4775 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4776 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4777 } 4778 4779 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4780 struct igb_ring *rx_ring) 4781 { 4782 /* set build_skb and buffer size flags */ 4783 clear_ring_build_skb_enabled(rx_ring); 4784 clear_ring_uses_large_buffer(rx_ring); 4785 4786 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4787 return; 4788 4789 set_ring_build_skb_enabled(rx_ring); 4790 4791 #if (PAGE_SIZE < 8192) 4792 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4793 return; 4794 4795 set_ring_uses_large_buffer(rx_ring); 4796 #endif 4797 } 4798 4799 /** 4800 * igb_configure_rx - Configure receive Unit after Reset 4801 * @adapter: board private structure 4802 * 4803 * Configure the Rx unit of the MAC after a reset. 4804 **/ 4805 static void igb_configure_rx(struct igb_adapter *adapter) 4806 { 4807 int i; 4808 4809 /* set the correct pool for the PF default MAC address in entry 0 */ 4810 igb_set_default_mac_filter(adapter); 4811 4812 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4813 * the Base and Length of the Rx Descriptor Ring 4814 */ 4815 for (i = 0; i < adapter->num_rx_queues; i++) { 4816 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4817 4818 igb_set_rx_buffer_len(adapter, rx_ring); 4819 igb_configure_rx_ring(adapter, rx_ring); 4820 } 4821 } 4822 4823 /** 4824 * igb_free_tx_resources - Free Tx Resources per Queue 4825 * @tx_ring: Tx descriptor ring for a specific queue 4826 * 4827 * Free all transmit software resources 4828 **/ 4829 void igb_free_tx_resources(struct igb_ring *tx_ring) 4830 { 4831 igb_clean_tx_ring(tx_ring); 4832 4833 vfree(tx_ring->tx_buffer_info); 4834 tx_ring->tx_buffer_info = NULL; 4835 4836 /* if not set, then don't free */ 4837 if (!tx_ring->desc) 4838 return; 4839 4840 dma_free_coherent(tx_ring->dev, tx_ring->size, 4841 tx_ring->desc, tx_ring->dma); 4842 4843 tx_ring->desc = NULL; 4844 } 4845 4846 /** 4847 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4848 * @adapter: board private structure 4849 * 4850 * Free all transmit software resources 4851 **/ 4852 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4853 { 4854 int i; 4855 4856 for (i = 0; i < adapter->num_tx_queues; i++) 4857 if (adapter->tx_ring[i]) 4858 igb_free_tx_resources(adapter->tx_ring[i]); 4859 } 4860 4861 /** 4862 * igb_clean_tx_ring - Free Tx Buffers 4863 * @tx_ring: ring to be cleaned 4864 **/ 4865 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 4866 { 4867 u16 i = tx_ring->next_to_clean; 4868 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4869 4870 while (i != tx_ring->next_to_use) { 4871 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4872 4873 /* Free all the Tx ring sk_buffs or xdp frames */ 4874 if (tx_buffer->type == IGB_TYPE_SKB) 4875 dev_kfree_skb_any(tx_buffer->skb); 4876 else 4877 xdp_return_frame(tx_buffer->xdpf); 4878 4879 /* unmap skb header data */ 4880 dma_unmap_single(tx_ring->dev, 4881 dma_unmap_addr(tx_buffer, dma), 4882 dma_unmap_len(tx_buffer, len), 4883 DMA_TO_DEVICE); 4884 4885 /* check for eop_desc to determine the end of the packet */ 4886 eop_desc = tx_buffer->next_to_watch; 4887 tx_desc = IGB_TX_DESC(tx_ring, i); 4888 4889 /* unmap remaining buffers */ 4890 while (tx_desc != eop_desc) { 4891 tx_buffer++; 4892 tx_desc++; 4893 i++; 4894 if (unlikely(i == tx_ring->count)) { 4895 i = 0; 4896 tx_buffer = tx_ring->tx_buffer_info; 4897 tx_desc = IGB_TX_DESC(tx_ring, 0); 4898 } 4899 4900 /* unmap any remaining paged data */ 4901 if (dma_unmap_len(tx_buffer, len)) 4902 dma_unmap_page(tx_ring->dev, 4903 dma_unmap_addr(tx_buffer, dma), 4904 dma_unmap_len(tx_buffer, len), 4905 DMA_TO_DEVICE); 4906 } 4907 4908 tx_buffer->next_to_watch = NULL; 4909 4910 /* move us one more past the eop_desc for start of next pkt */ 4911 tx_buffer++; 4912 i++; 4913 if (unlikely(i == tx_ring->count)) { 4914 i = 0; 4915 tx_buffer = tx_ring->tx_buffer_info; 4916 } 4917 } 4918 4919 /* reset BQL for queue */ 4920 netdev_tx_reset_queue(txring_txq(tx_ring)); 4921 4922 /* reset next_to_use and next_to_clean */ 4923 tx_ring->next_to_use = 0; 4924 tx_ring->next_to_clean = 0; 4925 } 4926 4927 /** 4928 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 4929 * @adapter: board private structure 4930 **/ 4931 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 4932 { 4933 int i; 4934 4935 for (i = 0; i < adapter->num_tx_queues; i++) 4936 if (adapter->tx_ring[i]) 4937 igb_clean_tx_ring(adapter->tx_ring[i]); 4938 } 4939 4940 /** 4941 * igb_free_rx_resources - Free Rx Resources 4942 * @rx_ring: ring to clean the resources from 4943 * 4944 * Free all receive software resources 4945 **/ 4946 void igb_free_rx_resources(struct igb_ring *rx_ring) 4947 { 4948 igb_clean_rx_ring(rx_ring); 4949 4950 rx_ring->xdp_prog = NULL; 4951 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4952 vfree(rx_ring->rx_buffer_info); 4953 rx_ring->rx_buffer_info = NULL; 4954 4955 /* if not set, then don't free */ 4956 if (!rx_ring->desc) 4957 return; 4958 4959 dma_free_coherent(rx_ring->dev, rx_ring->size, 4960 rx_ring->desc, rx_ring->dma); 4961 4962 rx_ring->desc = NULL; 4963 } 4964 4965 /** 4966 * igb_free_all_rx_resources - Free Rx Resources for All Queues 4967 * @adapter: board private structure 4968 * 4969 * Free all receive software resources 4970 **/ 4971 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 4972 { 4973 int i; 4974 4975 for (i = 0; i < adapter->num_rx_queues; i++) 4976 if (adapter->rx_ring[i]) 4977 igb_free_rx_resources(adapter->rx_ring[i]); 4978 } 4979 4980 /** 4981 * igb_clean_rx_ring - Free Rx Buffers per Queue 4982 * @rx_ring: ring to free buffers from 4983 **/ 4984 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 4985 { 4986 u16 i = rx_ring->next_to_clean; 4987 4988 dev_kfree_skb(rx_ring->skb); 4989 rx_ring->skb = NULL; 4990 4991 /* Free all the Rx ring sk_buffs */ 4992 while (i != rx_ring->next_to_alloc) { 4993 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 4994 4995 /* Invalidate cache lines that may have been written to by 4996 * device so that we avoid corrupting memory. 4997 */ 4998 dma_sync_single_range_for_cpu(rx_ring->dev, 4999 buffer_info->dma, 5000 buffer_info->page_offset, 5001 igb_rx_bufsz(rx_ring), 5002 DMA_FROM_DEVICE); 5003 5004 /* free resources associated with mapping */ 5005 dma_unmap_page_attrs(rx_ring->dev, 5006 buffer_info->dma, 5007 igb_rx_pg_size(rx_ring), 5008 DMA_FROM_DEVICE, 5009 IGB_RX_DMA_ATTR); 5010 __page_frag_cache_drain(buffer_info->page, 5011 buffer_info->pagecnt_bias); 5012 5013 i++; 5014 if (i == rx_ring->count) 5015 i = 0; 5016 } 5017 5018 rx_ring->next_to_alloc = 0; 5019 rx_ring->next_to_clean = 0; 5020 rx_ring->next_to_use = 0; 5021 } 5022 5023 /** 5024 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 5025 * @adapter: board private structure 5026 **/ 5027 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 5028 { 5029 int i; 5030 5031 for (i = 0; i < adapter->num_rx_queues; i++) 5032 if (adapter->rx_ring[i]) 5033 igb_clean_rx_ring(adapter->rx_ring[i]); 5034 } 5035 5036 /** 5037 * igb_set_mac - Change the Ethernet Address of the NIC 5038 * @netdev: network interface device structure 5039 * @p: pointer to an address structure 5040 * 5041 * Returns 0 on success, negative on failure 5042 **/ 5043 static int igb_set_mac(struct net_device *netdev, void *p) 5044 { 5045 struct igb_adapter *adapter = netdev_priv(netdev); 5046 struct e1000_hw *hw = &adapter->hw; 5047 struct sockaddr *addr = p; 5048 5049 if (!is_valid_ether_addr(addr->sa_data)) 5050 return -EADDRNOTAVAIL; 5051 5052 eth_hw_addr_set(netdev, addr->sa_data); 5053 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 5054 5055 /* set the correct pool for the new PF MAC address in entry 0 */ 5056 igb_set_default_mac_filter(adapter); 5057 5058 return 0; 5059 } 5060 5061 /** 5062 * igb_write_mc_addr_list - write multicast addresses to MTA 5063 * @netdev: network interface device structure 5064 * 5065 * Writes multicast address list to the MTA hash table. 5066 * Returns: -ENOMEM on failure 5067 * 0 on no addresses written 5068 * X on writing X addresses to MTA 5069 **/ 5070 static int igb_write_mc_addr_list(struct net_device *netdev) 5071 { 5072 struct igb_adapter *adapter = netdev_priv(netdev); 5073 struct e1000_hw *hw = &adapter->hw; 5074 struct netdev_hw_addr *ha; 5075 u8 *mta_list; 5076 int i; 5077 5078 if (netdev_mc_empty(netdev)) { 5079 /* nothing to program, so clear mc list */ 5080 igb_update_mc_addr_list(hw, NULL, 0); 5081 igb_restore_vf_multicasts(adapter); 5082 return 0; 5083 } 5084 5085 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 5086 if (!mta_list) 5087 return -ENOMEM; 5088 5089 /* The shared function expects a packed array of only addresses. */ 5090 i = 0; 5091 netdev_for_each_mc_addr(ha, netdev) 5092 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 5093 5094 igb_update_mc_addr_list(hw, mta_list, i); 5095 kfree(mta_list); 5096 5097 return netdev_mc_count(netdev); 5098 } 5099 5100 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 5101 { 5102 struct e1000_hw *hw = &adapter->hw; 5103 u32 i, pf_id; 5104 5105 switch (hw->mac.type) { 5106 case e1000_i210: 5107 case e1000_i211: 5108 case e1000_i350: 5109 /* VLAN filtering needed for VLAN prio filter */ 5110 if (adapter->netdev->features & NETIF_F_NTUPLE) 5111 break; 5112 fallthrough; 5113 case e1000_82576: 5114 case e1000_82580: 5115 case e1000_i354: 5116 /* VLAN filtering needed for pool filtering */ 5117 if (adapter->vfs_allocated_count) 5118 break; 5119 fallthrough; 5120 default: 5121 return 1; 5122 } 5123 5124 /* We are already in VLAN promisc, nothing to do */ 5125 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 5126 return 0; 5127 5128 if (!adapter->vfs_allocated_count) 5129 goto set_vfta; 5130 5131 /* Add PF to all active pools */ 5132 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5133 5134 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5135 u32 vlvf = rd32(E1000_VLVF(i)); 5136 5137 vlvf |= BIT(pf_id); 5138 wr32(E1000_VLVF(i), vlvf); 5139 } 5140 5141 set_vfta: 5142 /* Set all bits in the VLAN filter table array */ 5143 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 5144 hw->mac.ops.write_vfta(hw, i, ~0U); 5145 5146 /* Set flag so we don't redo unnecessary work */ 5147 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 5148 5149 return 0; 5150 } 5151 5152 #define VFTA_BLOCK_SIZE 8 5153 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 5154 { 5155 struct e1000_hw *hw = &adapter->hw; 5156 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 5157 u32 vid_start = vfta_offset * 32; 5158 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 5159 u32 i, vid, word, bits, pf_id; 5160 5161 /* guarantee that we don't scrub out management VLAN */ 5162 vid = adapter->mng_vlan_id; 5163 if (vid >= vid_start && vid < vid_end) 5164 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5165 5166 if (!adapter->vfs_allocated_count) 5167 goto set_vfta; 5168 5169 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5170 5171 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5172 u32 vlvf = rd32(E1000_VLVF(i)); 5173 5174 /* pull VLAN ID from VLVF */ 5175 vid = vlvf & VLAN_VID_MASK; 5176 5177 /* only concern ourselves with a certain range */ 5178 if (vid < vid_start || vid >= vid_end) 5179 continue; 5180 5181 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 5182 /* record VLAN ID in VFTA */ 5183 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5184 5185 /* if PF is part of this then continue */ 5186 if (test_bit(vid, adapter->active_vlans)) 5187 continue; 5188 } 5189 5190 /* remove PF from the pool */ 5191 bits = ~BIT(pf_id); 5192 bits &= rd32(E1000_VLVF(i)); 5193 wr32(E1000_VLVF(i), bits); 5194 } 5195 5196 set_vfta: 5197 /* extract values from active_vlans and write back to VFTA */ 5198 for (i = VFTA_BLOCK_SIZE; i--;) { 5199 vid = (vfta_offset + i) * 32; 5200 word = vid / BITS_PER_LONG; 5201 bits = vid % BITS_PER_LONG; 5202 5203 vfta[i] |= adapter->active_vlans[word] >> bits; 5204 5205 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 5206 } 5207 } 5208 5209 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 5210 { 5211 u32 i; 5212 5213 /* We are not in VLAN promisc, nothing to do */ 5214 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 5215 return; 5216 5217 /* Set flag so we don't redo unnecessary work */ 5218 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 5219 5220 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 5221 igb_scrub_vfta(adapter, i); 5222 } 5223 5224 /** 5225 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 5226 * @netdev: network interface device structure 5227 * 5228 * The set_rx_mode entry point is called whenever the unicast or multicast 5229 * address lists or the network interface flags are updated. This routine is 5230 * responsible for configuring the hardware for proper unicast, multicast, 5231 * promiscuous mode, and all-multi behavior. 5232 **/ 5233 static void igb_set_rx_mode(struct net_device *netdev) 5234 { 5235 struct igb_adapter *adapter = netdev_priv(netdev); 5236 struct e1000_hw *hw = &adapter->hw; 5237 unsigned int vfn = adapter->vfs_allocated_count; 5238 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 5239 int count; 5240 5241 /* Check for Promiscuous and All Multicast modes */ 5242 if (netdev->flags & IFF_PROMISC) { 5243 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5244 vmolr |= E1000_VMOLR_MPME; 5245 5246 /* enable use of UTA filter to force packets to default pool */ 5247 if (hw->mac.type == e1000_82576) 5248 vmolr |= E1000_VMOLR_ROPE; 5249 } else { 5250 if (netdev->flags & IFF_ALLMULTI) { 5251 rctl |= E1000_RCTL_MPE; 5252 vmolr |= E1000_VMOLR_MPME; 5253 } else { 5254 /* Write addresses to the MTA, if the attempt fails 5255 * then we should just turn on promiscuous mode so 5256 * that we can at least receive multicast traffic 5257 */ 5258 count = igb_write_mc_addr_list(netdev); 5259 if (count < 0) { 5260 rctl |= E1000_RCTL_MPE; 5261 vmolr |= E1000_VMOLR_MPME; 5262 } else if (count) { 5263 vmolr |= E1000_VMOLR_ROMPE; 5264 } 5265 } 5266 } 5267 5268 /* Write addresses to available RAR registers, if there is not 5269 * sufficient space to store all the addresses then enable 5270 * unicast promiscuous mode 5271 */ 5272 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5273 rctl |= E1000_RCTL_UPE; 5274 vmolr |= E1000_VMOLR_ROPE; 5275 } 5276 5277 /* enable VLAN filtering by default */ 5278 rctl |= E1000_RCTL_VFE; 5279 5280 /* disable VLAN filtering for modes that require it */ 5281 if ((netdev->flags & IFF_PROMISC) || 5282 (netdev->features & NETIF_F_RXALL)) { 5283 /* if we fail to set all rules then just clear VFE */ 5284 if (igb_vlan_promisc_enable(adapter)) 5285 rctl &= ~E1000_RCTL_VFE; 5286 } else { 5287 igb_vlan_promisc_disable(adapter); 5288 } 5289 5290 /* update state of unicast, multicast, and VLAN filtering modes */ 5291 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5292 E1000_RCTL_VFE); 5293 wr32(E1000_RCTL, rctl); 5294 5295 #if (PAGE_SIZE < 8192) 5296 if (!adapter->vfs_allocated_count) { 5297 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5298 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5299 } 5300 #endif 5301 wr32(E1000_RLPML, rlpml); 5302 5303 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5304 * the VMOLR to enable the appropriate modes. Without this workaround 5305 * we will have issues with VLAN tag stripping not being done for frames 5306 * that are only arriving because we are the default pool 5307 */ 5308 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5309 return; 5310 5311 /* set UTA to appropriate mode */ 5312 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5313 5314 vmolr |= rd32(E1000_VMOLR(vfn)) & 5315 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5316 5317 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5318 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5319 #if (PAGE_SIZE < 8192) 5320 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5321 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5322 else 5323 #endif 5324 vmolr |= MAX_JUMBO_FRAME_SIZE; 5325 vmolr |= E1000_VMOLR_LPE; 5326 5327 wr32(E1000_VMOLR(vfn), vmolr); 5328 5329 igb_restore_vf_multicasts(adapter); 5330 } 5331 5332 static void igb_check_wvbr(struct igb_adapter *adapter) 5333 { 5334 struct e1000_hw *hw = &adapter->hw; 5335 u32 wvbr = 0; 5336 5337 switch (hw->mac.type) { 5338 case e1000_82576: 5339 case e1000_i350: 5340 wvbr = rd32(E1000_WVBR); 5341 if (!wvbr) 5342 return; 5343 break; 5344 default: 5345 break; 5346 } 5347 5348 adapter->wvbr |= wvbr; 5349 } 5350 5351 #define IGB_STAGGERED_QUEUE_OFFSET 8 5352 5353 static void igb_spoof_check(struct igb_adapter *adapter) 5354 { 5355 int j; 5356 5357 if (!adapter->wvbr) 5358 return; 5359 5360 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5361 if (adapter->wvbr & BIT(j) || 5362 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5363 dev_warn(&adapter->pdev->dev, 5364 "Spoof event(s) detected on VF %d\n", j); 5365 adapter->wvbr &= 5366 ~(BIT(j) | 5367 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5368 } 5369 } 5370 } 5371 5372 /* Need to wait a few seconds after link up to get diagnostic information from 5373 * the phy 5374 */ 5375 static void igb_update_phy_info(struct timer_list *t) 5376 { 5377 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5378 igb_get_phy_info(&adapter->hw); 5379 } 5380 5381 /** 5382 * igb_has_link - check shared code for link and determine up/down 5383 * @adapter: pointer to driver private info 5384 **/ 5385 bool igb_has_link(struct igb_adapter *adapter) 5386 { 5387 struct e1000_hw *hw = &adapter->hw; 5388 bool link_active = false; 5389 5390 /* get_link_status is set on LSC (link status) interrupt or 5391 * rx sequence error interrupt. get_link_status will stay 5392 * false until the e1000_check_for_link establishes link 5393 * for copper adapters ONLY 5394 */ 5395 switch (hw->phy.media_type) { 5396 case e1000_media_type_copper: 5397 if (!hw->mac.get_link_status) 5398 return true; 5399 fallthrough; 5400 case e1000_media_type_internal_serdes: 5401 hw->mac.ops.check_for_link(hw); 5402 link_active = !hw->mac.get_link_status; 5403 break; 5404 default: 5405 case e1000_media_type_unknown: 5406 break; 5407 } 5408 5409 if (((hw->mac.type == e1000_i210) || 5410 (hw->mac.type == e1000_i211)) && 5411 (hw->phy.id == I210_I_PHY_ID)) { 5412 if (!netif_carrier_ok(adapter->netdev)) { 5413 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5414 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5415 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5416 adapter->link_check_timeout = jiffies; 5417 } 5418 } 5419 5420 return link_active; 5421 } 5422 5423 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5424 { 5425 bool ret = false; 5426 u32 ctrl_ext, thstat; 5427 5428 /* check for thermal sensor event on i350 copper only */ 5429 if (hw->mac.type == e1000_i350) { 5430 thstat = rd32(E1000_THSTAT); 5431 ctrl_ext = rd32(E1000_CTRL_EXT); 5432 5433 if ((hw->phy.media_type == e1000_media_type_copper) && 5434 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5435 ret = !!(thstat & event); 5436 } 5437 5438 return ret; 5439 } 5440 5441 /** 5442 * igb_check_lvmmc - check for malformed packets received 5443 * and indicated in LVMMC register 5444 * @adapter: pointer to adapter 5445 **/ 5446 static void igb_check_lvmmc(struct igb_adapter *adapter) 5447 { 5448 struct e1000_hw *hw = &adapter->hw; 5449 u32 lvmmc; 5450 5451 lvmmc = rd32(E1000_LVMMC); 5452 if (lvmmc) { 5453 if (unlikely(net_ratelimit())) { 5454 netdev_warn(adapter->netdev, 5455 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5456 lvmmc); 5457 } 5458 } 5459 } 5460 5461 /** 5462 * igb_watchdog - Timer Call-back 5463 * @t: pointer to timer_list containing our private info pointer 5464 **/ 5465 static void igb_watchdog(struct timer_list *t) 5466 { 5467 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5468 /* Do the rest outside of interrupt context */ 5469 schedule_work(&adapter->watchdog_task); 5470 } 5471 5472 static void igb_watchdog_task(struct work_struct *work) 5473 { 5474 struct igb_adapter *adapter = container_of(work, 5475 struct igb_adapter, 5476 watchdog_task); 5477 struct e1000_hw *hw = &adapter->hw; 5478 struct e1000_phy_info *phy = &hw->phy; 5479 struct net_device *netdev = adapter->netdev; 5480 u32 link; 5481 int i; 5482 u32 connsw; 5483 u16 phy_data, retry_count = 20; 5484 5485 link = igb_has_link(adapter); 5486 5487 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5488 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5489 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5490 else 5491 link = false; 5492 } 5493 5494 /* Force link down if we have fiber to swap to */ 5495 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5496 if (hw->phy.media_type == e1000_media_type_copper) { 5497 connsw = rd32(E1000_CONNSW); 5498 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5499 link = 0; 5500 } 5501 } 5502 if (link) { 5503 /* Perform a reset if the media type changed. */ 5504 if (hw->dev_spec._82575.media_changed) { 5505 hw->dev_spec._82575.media_changed = false; 5506 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5507 igb_reset(adapter); 5508 } 5509 /* Cancel scheduled suspend requests. */ 5510 pm_runtime_resume(netdev->dev.parent); 5511 5512 if (!netif_carrier_ok(netdev)) { 5513 u32 ctrl; 5514 5515 hw->mac.ops.get_speed_and_duplex(hw, 5516 &adapter->link_speed, 5517 &adapter->link_duplex); 5518 5519 ctrl = rd32(E1000_CTRL); 5520 /* Links status message must follow this format */ 5521 netdev_info(netdev, 5522 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5523 netdev->name, 5524 adapter->link_speed, 5525 adapter->link_duplex == FULL_DUPLEX ? 5526 "Full" : "Half", 5527 (ctrl & E1000_CTRL_TFCE) && 5528 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5529 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5530 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5531 5532 /* disable EEE if enabled */ 5533 if ((adapter->flags & IGB_FLAG_EEE) && 5534 (adapter->link_duplex == HALF_DUPLEX)) { 5535 dev_info(&adapter->pdev->dev, 5536 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5537 adapter->hw.dev_spec._82575.eee_disable = true; 5538 adapter->flags &= ~IGB_FLAG_EEE; 5539 } 5540 5541 /* check if SmartSpeed worked */ 5542 igb_check_downshift(hw); 5543 if (phy->speed_downgraded) 5544 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5545 5546 /* check for thermal sensor event */ 5547 if (igb_thermal_sensor_event(hw, 5548 E1000_THSTAT_LINK_THROTTLE)) 5549 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5550 5551 /* adjust timeout factor according to speed/duplex */ 5552 adapter->tx_timeout_factor = 1; 5553 switch (adapter->link_speed) { 5554 case SPEED_10: 5555 adapter->tx_timeout_factor = 14; 5556 break; 5557 case SPEED_100: 5558 /* maybe add some timeout factor ? */ 5559 break; 5560 } 5561 5562 if (adapter->link_speed != SPEED_1000 || 5563 !hw->phy.ops.read_reg) 5564 goto no_wait; 5565 5566 /* wait for Remote receiver status OK */ 5567 retry_read_status: 5568 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5569 &phy_data)) { 5570 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5571 retry_count) { 5572 msleep(100); 5573 retry_count--; 5574 goto retry_read_status; 5575 } else if (!retry_count) { 5576 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5577 } 5578 } else { 5579 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5580 } 5581 no_wait: 5582 netif_carrier_on(netdev); 5583 5584 igb_ping_all_vfs(adapter); 5585 igb_check_vf_rate_limit(adapter); 5586 5587 /* link state has changed, schedule phy info update */ 5588 if (!test_bit(__IGB_DOWN, &adapter->state)) 5589 mod_timer(&adapter->phy_info_timer, 5590 round_jiffies(jiffies + 2 * HZ)); 5591 } 5592 } else { 5593 if (netif_carrier_ok(netdev)) { 5594 adapter->link_speed = 0; 5595 adapter->link_duplex = 0; 5596 5597 /* check for thermal sensor event */ 5598 if (igb_thermal_sensor_event(hw, 5599 E1000_THSTAT_PWR_DOWN)) { 5600 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5601 } 5602 5603 /* Links status message must follow this format */ 5604 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5605 netdev->name); 5606 netif_carrier_off(netdev); 5607 5608 igb_ping_all_vfs(adapter); 5609 5610 /* link state has changed, schedule phy info update */ 5611 if (!test_bit(__IGB_DOWN, &adapter->state)) 5612 mod_timer(&adapter->phy_info_timer, 5613 round_jiffies(jiffies + 2 * HZ)); 5614 5615 /* link is down, time to check for alternate media */ 5616 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5617 igb_check_swap_media(adapter); 5618 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5619 schedule_work(&adapter->reset_task); 5620 /* return immediately */ 5621 return; 5622 } 5623 } 5624 pm_schedule_suspend(netdev->dev.parent, 5625 MSEC_PER_SEC * 5); 5626 5627 /* also check for alternate media here */ 5628 } else if (!netif_carrier_ok(netdev) && 5629 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5630 igb_check_swap_media(adapter); 5631 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5632 schedule_work(&adapter->reset_task); 5633 /* return immediately */ 5634 return; 5635 } 5636 } 5637 } 5638 5639 spin_lock(&adapter->stats64_lock); 5640 igb_update_stats(adapter); 5641 spin_unlock(&adapter->stats64_lock); 5642 5643 for (i = 0; i < adapter->num_tx_queues; i++) { 5644 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5645 if (!netif_carrier_ok(netdev)) { 5646 /* We've lost link, so the controller stops DMA, 5647 * but we've got queued Tx work that's never going 5648 * to get done, so reset controller to flush Tx. 5649 * (Do the reset outside of interrupt context). 5650 */ 5651 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5652 adapter->tx_timeout_count++; 5653 schedule_work(&adapter->reset_task); 5654 /* return immediately since reset is imminent */ 5655 return; 5656 } 5657 } 5658 5659 /* Force detection of hung controller every watchdog period */ 5660 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5661 } 5662 5663 /* Cause software interrupt to ensure Rx ring is cleaned */ 5664 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5665 u32 eics = 0; 5666 5667 for (i = 0; i < adapter->num_q_vectors; i++) 5668 eics |= adapter->q_vector[i]->eims_value; 5669 wr32(E1000_EICS, eics); 5670 } else { 5671 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5672 } 5673 5674 igb_spoof_check(adapter); 5675 igb_ptp_rx_hang(adapter); 5676 igb_ptp_tx_hang(adapter); 5677 5678 /* Check LVMMC register on i350/i354 only */ 5679 if ((adapter->hw.mac.type == e1000_i350) || 5680 (adapter->hw.mac.type == e1000_i354)) 5681 igb_check_lvmmc(adapter); 5682 5683 /* Reset the timer */ 5684 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5685 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5686 mod_timer(&adapter->watchdog_timer, 5687 round_jiffies(jiffies + HZ)); 5688 else 5689 mod_timer(&adapter->watchdog_timer, 5690 round_jiffies(jiffies + 2 * HZ)); 5691 } 5692 } 5693 5694 enum latency_range { 5695 lowest_latency = 0, 5696 low_latency = 1, 5697 bulk_latency = 2, 5698 latency_invalid = 255 5699 }; 5700 5701 /** 5702 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5703 * @q_vector: pointer to q_vector 5704 * 5705 * Stores a new ITR value based on strictly on packet size. This 5706 * algorithm is less sophisticated than that used in igb_update_itr, 5707 * due to the difficulty of synchronizing statistics across multiple 5708 * receive rings. The divisors and thresholds used by this function 5709 * were determined based on theoretical maximum wire speed and testing 5710 * data, in order to minimize response time while increasing bulk 5711 * throughput. 5712 * This functionality is controlled by ethtool's coalescing settings. 5713 * NOTE: This function is called only when operating in a multiqueue 5714 * receive environment. 5715 **/ 5716 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5717 { 5718 int new_val = q_vector->itr_val; 5719 int avg_wire_size = 0; 5720 struct igb_adapter *adapter = q_vector->adapter; 5721 unsigned int packets; 5722 5723 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5724 * ints/sec - ITR timer value of 120 ticks. 5725 */ 5726 if (adapter->link_speed != SPEED_1000) { 5727 new_val = IGB_4K_ITR; 5728 goto set_itr_val; 5729 } 5730 5731 packets = q_vector->rx.total_packets; 5732 if (packets) 5733 avg_wire_size = q_vector->rx.total_bytes / packets; 5734 5735 packets = q_vector->tx.total_packets; 5736 if (packets) 5737 avg_wire_size = max_t(u32, avg_wire_size, 5738 q_vector->tx.total_bytes / packets); 5739 5740 /* if avg_wire_size isn't set no work was done */ 5741 if (!avg_wire_size) 5742 goto clear_counts; 5743 5744 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5745 avg_wire_size += 24; 5746 5747 /* Don't starve jumbo frames */ 5748 avg_wire_size = min(avg_wire_size, 3000); 5749 5750 /* Give a little boost to mid-size frames */ 5751 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5752 new_val = avg_wire_size / 3; 5753 else 5754 new_val = avg_wire_size / 2; 5755 5756 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5757 if (new_val < IGB_20K_ITR && 5758 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5759 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5760 new_val = IGB_20K_ITR; 5761 5762 set_itr_val: 5763 if (new_val != q_vector->itr_val) { 5764 q_vector->itr_val = new_val; 5765 q_vector->set_itr = 1; 5766 } 5767 clear_counts: 5768 q_vector->rx.total_bytes = 0; 5769 q_vector->rx.total_packets = 0; 5770 q_vector->tx.total_bytes = 0; 5771 q_vector->tx.total_packets = 0; 5772 } 5773 5774 /** 5775 * igb_update_itr - update the dynamic ITR value based on statistics 5776 * @q_vector: pointer to q_vector 5777 * @ring_container: ring info to update the itr for 5778 * 5779 * Stores a new ITR value based on packets and byte 5780 * counts during the last interrupt. The advantage of per interrupt 5781 * computation is faster updates and more accurate ITR for the current 5782 * traffic pattern. Constants in this function were computed 5783 * based on theoretical maximum wire speed and thresholds were set based 5784 * on testing data as well as attempting to minimize response time 5785 * while increasing bulk throughput. 5786 * This functionality is controlled by ethtool's coalescing settings. 5787 * NOTE: These calculations are only valid when operating in a single- 5788 * queue environment. 5789 **/ 5790 static void igb_update_itr(struct igb_q_vector *q_vector, 5791 struct igb_ring_container *ring_container) 5792 { 5793 unsigned int packets = ring_container->total_packets; 5794 unsigned int bytes = ring_container->total_bytes; 5795 u8 itrval = ring_container->itr; 5796 5797 /* no packets, exit with status unchanged */ 5798 if (packets == 0) 5799 return; 5800 5801 switch (itrval) { 5802 case lowest_latency: 5803 /* handle TSO and jumbo frames */ 5804 if (bytes/packets > 8000) 5805 itrval = bulk_latency; 5806 else if ((packets < 5) && (bytes > 512)) 5807 itrval = low_latency; 5808 break; 5809 case low_latency: /* 50 usec aka 20000 ints/s */ 5810 if (bytes > 10000) { 5811 /* this if handles the TSO accounting */ 5812 if (bytes/packets > 8000) 5813 itrval = bulk_latency; 5814 else if ((packets < 10) || ((bytes/packets) > 1200)) 5815 itrval = bulk_latency; 5816 else if ((packets > 35)) 5817 itrval = lowest_latency; 5818 } else if (bytes/packets > 2000) { 5819 itrval = bulk_latency; 5820 } else if (packets <= 2 && bytes < 512) { 5821 itrval = lowest_latency; 5822 } 5823 break; 5824 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5825 if (bytes > 25000) { 5826 if (packets > 35) 5827 itrval = low_latency; 5828 } else if (bytes < 1500) { 5829 itrval = low_latency; 5830 } 5831 break; 5832 } 5833 5834 /* clear work counters since we have the values we need */ 5835 ring_container->total_bytes = 0; 5836 ring_container->total_packets = 0; 5837 5838 /* write updated itr to ring container */ 5839 ring_container->itr = itrval; 5840 } 5841 5842 static void igb_set_itr(struct igb_q_vector *q_vector) 5843 { 5844 struct igb_adapter *adapter = q_vector->adapter; 5845 u32 new_itr = q_vector->itr_val; 5846 u8 current_itr = 0; 5847 5848 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5849 if (adapter->link_speed != SPEED_1000) { 5850 current_itr = 0; 5851 new_itr = IGB_4K_ITR; 5852 goto set_itr_now; 5853 } 5854 5855 igb_update_itr(q_vector, &q_vector->tx); 5856 igb_update_itr(q_vector, &q_vector->rx); 5857 5858 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5859 5860 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5861 if (current_itr == lowest_latency && 5862 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5863 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5864 current_itr = low_latency; 5865 5866 switch (current_itr) { 5867 /* counts and packets in update_itr are dependent on these numbers */ 5868 case lowest_latency: 5869 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5870 break; 5871 case low_latency: 5872 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5873 break; 5874 case bulk_latency: 5875 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5876 break; 5877 default: 5878 break; 5879 } 5880 5881 set_itr_now: 5882 if (new_itr != q_vector->itr_val) { 5883 /* this attempts to bias the interrupt rate towards Bulk 5884 * by adding intermediate steps when interrupt rate is 5885 * increasing 5886 */ 5887 new_itr = new_itr > q_vector->itr_val ? 5888 max((new_itr * q_vector->itr_val) / 5889 (new_itr + (q_vector->itr_val >> 2)), 5890 new_itr) : new_itr; 5891 /* Don't write the value here; it resets the adapter's 5892 * internal timer, and causes us to delay far longer than 5893 * we should between interrupts. Instead, we write the ITR 5894 * value at the beginning of the next interrupt so the timing 5895 * ends up being correct. 5896 */ 5897 q_vector->itr_val = new_itr; 5898 q_vector->set_itr = 1; 5899 } 5900 } 5901 5902 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 5903 struct igb_tx_buffer *first, 5904 u32 vlan_macip_lens, u32 type_tucmd, 5905 u32 mss_l4len_idx) 5906 { 5907 struct e1000_adv_tx_context_desc *context_desc; 5908 u16 i = tx_ring->next_to_use; 5909 struct timespec64 ts; 5910 5911 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5912 5913 i++; 5914 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 5915 5916 /* set bits to identify this as an advanced context descriptor */ 5917 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 5918 5919 /* For 82575, context index must be unique per ring. */ 5920 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5921 mss_l4len_idx |= tx_ring->reg_idx << 4; 5922 5923 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5924 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5925 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5926 5927 /* We assume there is always a valid tx time available. Invalid times 5928 * should have been handled by the upper layers. 5929 */ 5930 if (tx_ring->launchtime_enable) { 5931 ts = ktime_to_timespec64(first->skb->tstamp); 5932 skb_txtime_consumed(first->skb); 5933 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 5934 } else { 5935 context_desc->seqnum_seed = 0; 5936 } 5937 } 5938 5939 static int igb_tso(struct igb_ring *tx_ring, 5940 struct igb_tx_buffer *first, 5941 u8 *hdr_len) 5942 { 5943 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 5944 struct sk_buff *skb = first->skb; 5945 union { 5946 struct iphdr *v4; 5947 struct ipv6hdr *v6; 5948 unsigned char *hdr; 5949 } ip; 5950 union { 5951 struct tcphdr *tcp; 5952 struct udphdr *udp; 5953 unsigned char *hdr; 5954 } l4; 5955 u32 paylen, l4_offset; 5956 int err; 5957 5958 if (skb->ip_summed != CHECKSUM_PARTIAL) 5959 return 0; 5960 5961 if (!skb_is_gso(skb)) 5962 return 0; 5963 5964 err = skb_cow_head(skb, 0); 5965 if (err < 0) 5966 return err; 5967 5968 ip.hdr = skb_network_header(skb); 5969 l4.hdr = skb_checksum_start(skb); 5970 5971 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 5972 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 5973 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP; 5974 5975 /* initialize outer IP header fields */ 5976 if (ip.v4->version == 4) { 5977 unsigned char *csum_start = skb_checksum_start(skb); 5978 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 5979 5980 /* IP header will have to cancel out any data that 5981 * is not a part of the outer IP header 5982 */ 5983 ip.v4->check = csum_fold(csum_partial(trans_start, 5984 csum_start - trans_start, 5985 0)); 5986 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 5987 5988 ip.v4->tot_len = 0; 5989 first->tx_flags |= IGB_TX_FLAGS_TSO | 5990 IGB_TX_FLAGS_CSUM | 5991 IGB_TX_FLAGS_IPV4; 5992 } else { 5993 ip.v6->payload_len = 0; 5994 first->tx_flags |= IGB_TX_FLAGS_TSO | 5995 IGB_TX_FLAGS_CSUM; 5996 } 5997 5998 /* determine offset of inner transport header */ 5999 l4_offset = l4.hdr - skb->data; 6000 6001 /* remove payload length from inner checksum */ 6002 paylen = skb->len - l4_offset; 6003 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) { 6004 /* compute length of segmentation header */ 6005 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 6006 csum_replace_by_diff(&l4.tcp->check, 6007 (__force __wsum)htonl(paylen)); 6008 } else { 6009 /* compute length of segmentation header */ 6010 *hdr_len = sizeof(*l4.udp) + l4_offset; 6011 csum_replace_by_diff(&l4.udp->check, 6012 (__force __wsum)htonl(paylen)); 6013 } 6014 6015 /* update gso size and bytecount with header size */ 6016 first->gso_segs = skb_shinfo(skb)->gso_segs; 6017 first->bytecount += (first->gso_segs - 1) * *hdr_len; 6018 6019 /* MSS L4LEN IDX */ 6020 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 6021 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 6022 6023 /* VLAN MACLEN IPLEN */ 6024 vlan_macip_lens = l4.hdr - ip.hdr; 6025 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 6026 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6027 6028 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 6029 type_tucmd, mss_l4len_idx); 6030 6031 return 1; 6032 } 6033 6034 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 6035 { 6036 struct sk_buff *skb = first->skb; 6037 u32 vlan_macip_lens = 0; 6038 u32 type_tucmd = 0; 6039 6040 if (skb->ip_summed != CHECKSUM_PARTIAL) { 6041 csum_failed: 6042 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 6043 !tx_ring->launchtime_enable) 6044 return; 6045 goto no_csum; 6046 } 6047 6048 switch (skb->csum_offset) { 6049 case offsetof(struct tcphdr, check): 6050 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 6051 fallthrough; 6052 case offsetof(struct udphdr, check): 6053 break; 6054 case offsetof(struct sctphdr, checksum): 6055 /* validate that this is actually an SCTP request */ 6056 if (skb_csum_is_sctp(skb)) { 6057 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 6058 break; 6059 } 6060 fallthrough; 6061 default: 6062 skb_checksum_help(skb); 6063 goto csum_failed; 6064 } 6065 6066 /* update TX checksum flag */ 6067 first->tx_flags |= IGB_TX_FLAGS_CSUM; 6068 vlan_macip_lens = skb_checksum_start_offset(skb) - 6069 skb_network_offset(skb); 6070 no_csum: 6071 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 6072 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6073 6074 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 6075 } 6076 6077 #define IGB_SET_FLAG(_input, _flag, _result) \ 6078 ((_flag <= _result) ? \ 6079 ((u32)(_input & _flag) * (_result / _flag)) : \ 6080 ((u32)(_input & _flag) / (_flag / _result))) 6081 6082 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6083 { 6084 /* set type for advanced descriptor with frame checksum insertion */ 6085 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 6086 E1000_ADVTXD_DCMD_DEXT | 6087 E1000_ADVTXD_DCMD_IFCS; 6088 6089 /* set HW vlan bit if vlan is present */ 6090 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 6091 (E1000_ADVTXD_DCMD_VLE)); 6092 6093 /* set segmentation bits for TSO */ 6094 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 6095 (E1000_ADVTXD_DCMD_TSE)); 6096 6097 /* set timestamp bit if present */ 6098 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 6099 (E1000_ADVTXD_MAC_TSTAMP)); 6100 6101 /* insert frame checksum */ 6102 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 6103 6104 return cmd_type; 6105 } 6106 6107 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 6108 union e1000_adv_tx_desc *tx_desc, 6109 u32 tx_flags, unsigned int paylen) 6110 { 6111 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 6112 6113 /* 82575 requires a unique index per ring */ 6114 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6115 olinfo_status |= tx_ring->reg_idx << 4; 6116 6117 /* insert L4 checksum */ 6118 olinfo_status |= IGB_SET_FLAG(tx_flags, 6119 IGB_TX_FLAGS_CSUM, 6120 (E1000_TXD_POPTS_TXSM << 8)); 6121 6122 /* insert IPv4 checksum */ 6123 olinfo_status |= IGB_SET_FLAG(tx_flags, 6124 IGB_TX_FLAGS_IPV4, 6125 (E1000_TXD_POPTS_IXSM << 8)); 6126 6127 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6128 } 6129 6130 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6131 { 6132 struct net_device *netdev = tx_ring->netdev; 6133 6134 netif_stop_subqueue(netdev, tx_ring->queue_index); 6135 6136 /* Herbert's original patch had: 6137 * smp_mb__after_netif_stop_queue(); 6138 * but since that doesn't exist yet, just open code it. 6139 */ 6140 smp_mb(); 6141 6142 /* We need to check again in a case another CPU has just 6143 * made room available. 6144 */ 6145 if (igb_desc_unused(tx_ring) < size) 6146 return -EBUSY; 6147 6148 /* A reprieve! */ 6149 netif_wake_subqueue(netdev, tx_ring->queue_index); 6150 6151 u64_stats_update_begin(&tx_ring->tx_syncp2); 6152 tx_ring->tx_stats.restart_queue2++; 6153 u64_stats_update_end(&tx_ring->tx_syncp2); 6154 6155 return 0; 6156 } 6157 6158 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6159 { 6160 if (igb_desc_unused(tx_ring) >= size) 6161 return 0; 6162 return __igb_maybe_stop_tx(tx_ring, size); 6163 } 6164 6165 static int igb_tx_map(struct igb_ring *tx_ring, 6166 struct igb_tx_buffer *first, 6167 const u8 hdr_len) 6168 { 6169 struct sk_buff *skb = first->skb; 6170 struct igb_tx_buffer *tx_buffer; 6171 union e1000_adv_tx_desc *tx_desc; 6172 skb_frag_t *frag; 6173 dma_addr_t dma; 6174 unsigned int data_len, size; 6175 u32 tx_flags = first->tx_flags; 6176 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 6177 u16 i = tx_ring->next_to_use; 6178 6179 tx_desc = IGB_TX_DESC(tx_ring, i); 6180 6181 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 6182 6183 size = skb_headlen(skb); 6184 data_len = skb->data_len; 6185 6186 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6187 6188 tx_buffer = first; 6189 6190 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6191 if (dma_mapping_error(tx_ring->dev, dma)) 6192 goto dma_error; 6193 6194 /* record length, and DMA address */ 6195 dma_unmap_len_set(tx_buffer, len, size); 6196 dma_unmap_addr_set(tx_buffer, dma, dma); 6197 6198 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6199 6200 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 6201 tx_desc->read.cmd_type_len = 6202 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 6203 6204 i++; 6205 tx_desc++; 6206 if (i == tx_ring->count) { 6207 tx_desc = IGB_TX_DESC(tx_ring, 0); 6208 i = 0; 6209 } 6210 tx_desc->read.olinfo_status = 0; 6211 6212 dma += IGB_MAX_DATA_PER_TXD; 6213 size -= IGB_MAX_DATA_PER_TXD; 6214 6215 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6216 } 6217 6218 if (likely(!data_len)) 6219 break; 6220 6221 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6222 6223 i++; 6224 tx_desc++; 6225 if (i == tx_ring->count) { 6226 tx_desc = IGB_TX_DESC(tx_ring, 0); 6227 i = 0; 6228 } 6229 tx_desc->read.olinfo_status = 0; 6230 6231 size = skb_frag_size(frag); 6232 data_len -= size; 6233 6234 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6235 size, DMA_TO_DEVICE); 6236 6237 tx_buffer = &tx_ring->tx_buffer_info[i]; 6238 } 6239 6240 /* write last descriptor with RS and EOP bits */ 6241 cmd_type |= size | IGB_TXD_DCMD; 6242 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6243 6244 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6245 6246 /* set the timestamp */ 6247 first->time_stamp = jiffies; 6248 6249 skb_tx_timestamp(skb); 6250 6251 /* Force memory writes to complete before letting h/w know there 6252 * are new descriptors to fetch. (Only applicable for weak-ordered 6253 * memory model archs, such as IA-64). 6254 * 6255 * We also need this memory barrier to make certain all of the 6256 * status bits have been updated before next_to_watch is written. 6257 */ 6258 dma_wmb(); 6259 6260 /* set next_to_watch value indicating a packet is present */ 6261 first->next_to_watch = tx_desc; 6262 6263 i++; 6264 if (i == tx_ring->count) 6265 i = 0; 6266 6267 tx_ring->next_to_use = i; 6268 6269 /* Make sure there is space in the ring for the next send. */ 6270 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6271 6272 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6273 writel(i, tx_ring->tail); 6274 } 6275 return 0; 6276 6277 dma_error: 6278 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6279 tx_buffer = &tx_ring->tx_buffer_info[i]; 6280 6281 /* clear dma mappings for failed tx_buffer_info map */ 6282 while (tx_buffer != first) { 6283 if (dma_unmap_len(tx_buffer, len)) 6284 dma_unmap_page(tx_ring->dev, 6285 dma_unmap_addr(tx_buffer, dma), 6286 dma_unmap_len(tx_buffer, len), 6287 DMA_TO_DEVICE); 6288 dma_unmap_len_set(tx_buffer, len, 0); 6289 6290 if (i-- == 0) 6291 i += tx_ring->count; 6292 tx_buffer = &tx_ring->tx_buffer_info[i]; 6293 } 6294 6295 if (dma_unmap_len(tx_buffer, len)) 6296 dma_unmap_single(tx_ring->dev, 6297 dma_unmap_addr(tx_buffer, dma), 6298 dma_unmap_len(tx_buffer, len), 6299 DMA_TO_DEVICE); 6300 dma_unmap_len_set(tx_buffer, len, 0); 6301 6302 dev_kfree_skb_any(tx_buffer->skb); 6303 tx_buffer->skb = NULL; 6304 6305 tx_ring->next_to_use = i; 6306 6307 return -1; 6308 } 6309 6310 int igb_xmit_xdp_ring(struct igb_adapter *adapter, 6311 struct igb_ring *tx_ring, 6312 struct xdp_frame *xdpf) 6313 { 6314 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 6315 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 6316 u16 count, i, index = tx_ring->next_to_use; 6317 struct igb_tx_buffer *tx_head = &tx_ring->tx_buffer_info[index]; 6318 struct igb_tx_buffer *tx_buffer = tx_head; 6319 union e1000_adv_tx_desc *tx_desc = IGB_TX_DESC(tx_ring, index); 6320 u32 len = xdpf->len, cmd_type, olinfo_status; 6321 void *data = xdpf->data; 6322 6323 count = TXD_USE_COUNT(len); 6324 for (i = 0; i < nr_frags; i++) 6325 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i])); 6326 6327 if (igb_maybe_stop_tx(tx_ring, count + 3)) 6328 return IGB_XDP_CONSUMED; 6329 6330 i = 0; 6331 /* record the location of the first descriptor for this packet */ 6332 tx_head->bytecount = xdp_get_frame_len(xdpf); 6333 tx_head->type = IGB_TYPE_XDP; 6334 tx_head->gso_segs = 1; 6335 tx_head->xdpf = xdpf; 6336 6337 olinfo_status = tx_head->bytecount << E1000_ADVTXD_PAYLEN_SHIFT; 6338 /* 82575 requires a unique index per ring */ 6339 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6340 olinfo_status |= tx_ring->reg_idx << 4; 6341 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6342 6343 for (;;) { 6344 dma_addr_t dma; 6345 6346 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE); 6347 if (dma_mapping_error(tx_ring->dev, dma)) 6348 goto unmap; 6349 6350 /* record length, and DMA address */ 6351 dma_unmap_len_set(tx_buffer, len, len); 6352 dma_unmap_addr_set(tx_buffer, dma, dma); 6353 6354 /* put descriptor type bits */ 6355 cmd_type = E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_DEXT | 6356 E1000_ADVTXD_DCMD_IFCS | len; 6357 6358 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6359 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6360 6361 tx_buffer->protocol = 0; 6362 6363 if (++index == tx_ring->count) 6364 index = 0; 6365 6366 if (i == nr_frags) 6367 break; 6368 6369 tx_buffer = &tx_ring->tx_buffer_info[index]; 6370 tx_desc = IGB_TX_DESC(tx_ring, index); 6371 tx_desc->read.olinfo_status = 0; 6372 6373 data = skb_frag_address(&sinfo->frags[i]); 6374 len = skb_frag_size(&sinfo->frags[i]); 6375 i++; 6376 } 6377 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_TXD_DCMD); 6378 6379 netdev_tx_sent_queue(txring_txq(tx_ring), tx_head->bytecount); 6380 /* set the timestamp */ 6381 tx_head->time_stamp = jiffies; 6382 6383 /* Avoid any potential race with xdp_xmit and cleanup */ 6384 smp_wmb(); 6385 6386 /* set next_to_watch value indicating a packet is present */ 6387 tx_head->next_to_watch = tx_desc; 6388 tx_ring->next_to_use = index; 6389 6390 /* Make sure there is space in the ring for the next send. */ 6391 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6392 6393 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) 6394 writel(index, tx_ring->tail); 6395 6396 return IGB_XDP_TX; 6397 6398 unmap: 6399 for (;;) { 6400 tx_buffer = &tx_ring->tx_buffer_info[index]; 6401 if (dma_unmap_len(tx_buffer, len)) 6402 dma_unmap_page(tx_ring->dev, 6403 dma_unmap_addr(tx_buffer, dma), 6404 dma_unmap_len(tx_buffer, len), 6405 DMA_TO_DEVICE); 6406 dma_unmap_len_set(tx_buffer, len, 0); 6407 if (tx_buffer == tx_head) 6408 break; 6409 6410 if (!index) 6411 index += tx_ring->count; 6412 index--; 6413 } 6414 6415 return IGB_XDP_CONSUMED; 6416 } 6417 6418 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6419 struct igb_ring *tx_ring) 6420 { 6421 struct igb_tx_buffer *first; 6422 int tso; 6423 u32 tx_flags = 0; 6424 unsigned short f; 6425 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6426 __be16 protocol = vlan_get_protocol(skb); 6427 u8 hdr_len = 0; 6428 6429 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6430 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6431 * + 2 desc gap to keep tail from touching head, 6432 * + 1 desc for context descriptor, 6433 * otherwise try next time 6434 */ 6435 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6436 count += TXD_USE_COUNT(skb_frag_size( 6437 &skb_shinfo(skb)->frags[f])); 6438 6439 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6440 /* this is a hard error */ 6441 return NETDEV_TX_BUSY; 6442 } 6443 6444 /* record the location of the first descriptor for this packet */ 6445 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6446 first->type = IGB_TYPE_SKB; 6447 first->skb = skb; 6448 first->bytecount = skb->len; 6449 first->gso_segs = 1; 6450 6451 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6452 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6453 6454 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6455 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6456 &adapter->state)) { 6457 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6458 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6459 6460 adapter->ptp_tx_skb = skb_get(skb); 6461 adapter->ptp_tx_start = jiffies; 6462 if (adapter->hw.mac.type == e1000_82576) 6463 schedule_work(&adapter->ptp_tx_work); 6464 } else { 6465 adapter->tx_hwtstamp_skipped++; 6466 } 6467 } 6468 6469 if (skb_vlan_tag_present(skb)) { 6470 tx_flags |= IGB_TX_FLAGS_VLAN; 6471 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6472 } 6473 6474 /* record initial flags and protocol */ 6475 first->tx_flags = tx_flags; 6476 first->protocol = protocol; 6477 6478 tso = igb_tso(tx_ring, first, &hdr_len); 6479 if (tso < 0) 6480 goto out_drop; 6481 else if (!tso) 6482 igb_tx_csum(tx_ring, first); 6483 6484 if (igb_tx_map(tx_ring, first, hdr_len)) 6485 goto cleanup_tx_tstamp; 6486 6487 return NETDEV_TX_OK; 6488 6489 out_drop: 6490 dev_kfree_skb_any(first->skb); 6491 first->skb = NULL; 6492 cleanup_tx_tstamp: 6493 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6494 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6495 6496 dev_kfree_skb_any(adapter->ptp_tx_skb); 6497 adapter->ptp_tx_skb = NULL; 6498 if (adapter->hw.mac.type == e1000_82576) 6499 cancel_work_sync(&adapter->ptp_tx_work); 6500 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6501 } 6502 6503 return NETDEV_TX_OK; 6504 } 6505 6506 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6507 struct sk_buff *skb) 6508 { 6509 unsigned int r_idx = skb->queue_mapping; 6510 6511 if (r_idx >= adapter->num_tx_queues) 6512 r_idx = r_idx % adapter->num_tx_queues; 6513 6514 return adapter->tx_ring[r_idx]; 6515 } 6516 6517 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6518 struct net_device *netdev) 6519 { 6520 struct igb_adapter *adapter = netdev_priv(netdev); 6521 6522 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6523 * in order to meet this minimum size requirement. 6524 */ 6525 if (skb_put_padto(skb, 17)) 6526 return NETDEV_TX_OK; 6527 6528 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6529 } 6530 6531 /** 6532 * igb_tx_timeout - Respond to a Tx Hang 6533 * @netdev: network interface device structure 6534 * @txqueue: number of the Tx queue that hung (unused) 6535 **/ 6536 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6537 { 6538 struct igb_adapter *adapter = netdev_priv(netdev); 6539 struct e1000_hw *hw = &adapter->hw; 6540 6541 /* Do the reset outside of interrupt context */ 6542 adapter->tx_timeout_count++; 6543 6544 if (hw->mac.type >= e1000_82580) 6545 hw->dev_spec._82575.global_device_reset = true; 6546 6547 schedule_work(&adapter->reset_task); 6548 wr32(E1000_EICS, 6549 (adapter->eims_enable_mask & ~adapter->eims_other)); 6550 } 6551 6552 static void igb_reset_task(struct work_struct *work) 6553 { 6554 struct igb_adapter *adapter; 6555 adapter = container_of(work, struct igb_adapter, reset_task); 6556 6557 rtnl_lock(); 6558 /* If we're already down or resetting, just bail */ 6559 if (test_bit(__IGB_DOWN, &adapter->state) || 6560 test_bit(__IGB_RESETTING, &adapter->state)) { 6561 rtnl_unlock(); 6562 return; 6563 } 6564 6565 igb_dump(adapter); 6566 netdev_err(adapter->netdev, "Reset adapter\n"); 6567 igb_reinit_locked(adapter); 6568 rtnl_unlock(); 6569 } 6570 6571 /** 6572 * igb_get_stats64 - Get System Network Statistics 6573 * @netdev: network interface device structure 6574 * @stats: rtnl_link_stats64 pointer 6575 **/ 6576 static void igb_get_stats64(struct net_device *netdev, 6577 struct rtnl_link_stats64 *stats) 6578 { 6579 struct igb_adapter *adapter = netdev_priv(netdev); 6580 6581 spin_lock(&adapter->stats64_lock); 6582 igb_update_stats(adapter); 6583 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6584 spin_unlock(&adapter->stats64_lock); 6585 } 6586 6587 /** 6588 * igb_change_mtu - Change the Maximum Transfer Unit 6589 * @netdev: network interface device structure 6590 * @new_mtu: new value for maximum frame size 6591 * 6592 * Returns 0 on success, negative on failure 6593 **/ 6594 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6595 { 6596 struct igb_adapter *adapter = netdev_priv(netdev); 6597 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD; 6598 6599 if (adapter->xdp_prog) { 6600 int i; 6601 6602 for (i = 0; i < adapter->num_rx_queues; i++) { 6603 struct igb_ring *ring = adapter->rx_ring[i]; 6604 6605 if (max_frame > igb_rx_bufsz(ring)) { 6606 netdev_warn(adapter->netdev, 6607 "Requested MTU size is not supported with XDP. Max frame size is %d\n", 6608 max_frame); 6609 return -EINVAL; 6610 } 6611 } 6612 } 6613 6614 /* adjust max frame to be at least the size of a standard frame */ 6615 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6616 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6617 6618 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6619 usleep_range(1000, 2000); 6620 6621 /* igb_down has a dependency on max_frame_size */ 6622 adapter->max_frame_size = max_frame; 6623 6624 if (netif_running(netdev)) 6625 igb_down(adapter); 6626 6627 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6628 netdev->mtu, new_mtu); 6629 netdev->mtu = new_mtu; 6630 6631 if (netif_running(netdev)) 6632 igb_up(adapter); 6633 else 6634 igb_reset(adapter); 6635 6636 clear_bit(__IGB_RESETTING, &adapter->state); 6637 6638 return 0; 6639 } 6640 6641 /** 6642 * igb_update_stats - Update the board statistics counters 6643 * @adapter: board private structure 6644 **/ 6645 void igb_update_stats(struct igb_adapter *adapter) 6646 { 6647 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6648 struct e1000_hw *hw = &adapter->hw; 6649 struct pci_dev *pdev = adapter->pdev; 6650 u32 reg, mpc; 6651 int i; 6652 u64 bytes, packets; 6653 unsigned int start; 6654 u64 _bytes, _packets; 6655 6656 /* Prevent stats update while adapter is being reset, or if the pci 6657 * connection is down. 6658 */ 6659 if (adapter->link_speed == 0) 6660 return; 6661 if (pci_channel_offline(pdev)) 6662 return; 6663 6664 bytes = 0; 6665 packets = 0; 6666 6667 rcu_read_lock(); 6668 for (i = 0; i < adapter->num_rx_queues; i++) { 6669 struct igb_ring *ring = adapter->rx_ring[i]; 6670 u32 rqdpc = rd32(E1000_RQDPC(i)); 6671 if (hw->mac.type >= e1000_i210) 6672 wr32(E1000_RQDPC(i), 0); 6673 6674 if (rqdpc) { 6675 ring->rx_stats.drops += rqdpc; 6676 net_stats->rx_fifo_errors += rqdpc; 6677 } 6678 6679 do { 6680 start = u64_stats_fetch_begin(&ring->rx_syncp); 6681 _bytes = ring->rx_stats.bytes; 6682 _packets = ring->rx_stats.packets; 6683 } while (u64_stats_fetch_retry(&ring->rx_syncp, start)); 6684 bytes += _bytes; 6685 packets += _packets; 6686 } 6687 6688 net_stats->rx_bytes = bytes; 6689 net_stats->rx_packets = packets; 6690 6691 bytes = 0; 6692 packets = 0; 6693 for (i = 0; i < adapter->num_tx_queues; i++) { 6694 struct igb_ring *ring = adapter->tx_ring[i]; 6695 do { 6696 start = u64_stats_fetch_begin(&ring->tx_syncp); 6697 _bytes = ring->tx_stats.bytes; 6698 _packets = ring->tx_stats.packets; 6699 } while (u64_stats_fetch_retry(&ring->tx_syncp, start)); 6700 bytes += _bytes; 6701 packets += _packets; 6702 } 6703 net_stats->tx_bytes = bytes; 6704 net_stats->tx_packets = packets; 6705 rcu_read_unlock(); 6706 6707 /* read stats registers */ 6708 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6709 adapter->stats.gprc += rd32(E1000_GPRC); 6710 adapter->stats.gorc += rd32(E1000_GORCL); 6711 rd32(E1000_GORCH); /* clear GORCL */ 6712 adapter->stats.bprc += rd32(E1000_BPRC); 6713 adapter->stats.mprc += rd32(E1000_MPRC); 6714 adapter->stats.roc += rd32(E1000_ROC); 6715 6716 adapter->stats.prc64 += rd32(E1000_PRC64); 6717 adapter->stats.prc127 += rd32(E1000_PRC127); 6718 adapter->stats.prc255 += rd32(E1000_PRC255); 6719 adapter->stats.prc511 += rd32(E1000_PRC511); 6720 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6721 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6722 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6723 adapter->stats.sec += rd32(E1000_SEC); 6724 6725 mpc = rd32(E1000_MPC); 6726 adapter->stats.mpc += mpc; 6727 net_stats->rx_fifo_errors += mpc; 6728 adapter->stats.scc += rd32(E1000_SCC); 6729 adapter->stats.ecol += rd32(E1000_ECOL); 6730 adapter->stats.mcc += rd32(E1000_MCC); 6731 adapter->stats.latecol += rd32(E1000_LATECOL); 6732 adapter->stats.dc += rd32(E1000_DC); 6733 adapter->stats.rlec += rd32(E1000_RLEC); 6734 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6735 adapter->stats.xontxc += rd32(E1000_XONTXC); 6736 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6737 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6738 adapter->stats.fcruc += rd32(E1000_FCRUC); 6739 adapter->stats.gptc += rd32(E1000_GPTC); 6740 adapter->stats.gotc += rd32(E1000_GOTCL); 6741 rd32(E1000_GOTCH); /* clear GOTCL */ 6742 adapter->stats.rnbc += rd32(E1000_RNBC); 6743 adapter->stats.ruc += rd32(E1000_RUC); 6744 adapter->stats.rfc += rd32(E1000_RFC); 6745 adapter->stats.rjc += rd32(E1000_RJC); 6746 adapter->stats.tor += rd32(E1000_TORH); 6747 adapter->stats.tot += rd32(E1000_TOTH); 6748 adapter->stats.tpr += rd32(E1000_TPR); 6749 6750 adapter->stats.ptc64 += rd32(E1000_PTC64); 6751 adapter->stats.ptc127 += rd32(E1000_PTC127); 6752 adapter->stats.ptc255 += rd32(E1000_PTC255); 6753 adapter->stats.ptc511 += rd32(E1000_PTC511); 6754 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6755 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6756 6757 adapter->stats.mptc += rd32(E1000_MPTC); 6758 adapter->stats.bptc += rd32(E1000_BPTC); 6759 6760 adapter->stats.tpt += rd32(E1000_TPT); 6761 adapter->stats.colc += rd32(E1000_COLC); 6762 6763 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6764 /* read internal phy specific stats */ 6765 reg = rd32(E1000_CTRL_EXT); 6766 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6767 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6768 6769 /* this stat has invalid values on i210/i211 */ 6770 if ((hw->mac.type != e1000_i210) && 6771 (hw->mac.type != e1000_i211)) 6772 adapter->stats.tncrs += rd32(E1000_TNCRS); 6773 } 6774 6775 adapter->stats.tsctc += rd32(E1000_TSCTC); 6776 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6777 6778 adapter->stats.iac += rd32(E1000_IAC); 6779 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6780 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6781 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6782 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6783 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6784 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6785 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6786 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6787 6788 /* Fill out the OS statistics structure */ 6789 net_stats->multicast = adapter->stats.mprc; 6790 net_stats->collisions = adapter->stats.colc; 6791 6792 /* Rx Errors */ 6793 6794 /* RLEC on some newer hardware can be incorrect so build 6795 * our own version based on RUC and ROC 6796 */ 6797 net_stats->rx_errors = adapter->stats.rxerrc + 6798 adapter->stats.crcerrs + adapter->stats.algnerrc + 6799 adapter->stats.ruc + adapter->stats.roc + 6800 adapter->stats.cexterr; 6801 net_stats->rx_length_errors = adapter->stats.ruc + 6802 adapter->stats.roc; 6803 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6804 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6805 net_stats->rx_missed_errors = adapter->stats.mpc; 6806 6807 /* Tx Errors */ 6808 net_stats->tx_errors = adapter->stats.ecol + 6809 adapter->stats.latecol; 6810 net_stats->tx_aborted_errors = adapter->stats.ecol; 6811 net_stats->tx_window_errors = adapter->stats.latecol; 6812 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6813 6814 /* Tx Dropped needs to be maintained elsewhere */ 6815 6816 /* Management Stats */ 6817 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6818 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6819 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6820 6821 /* OS2BMC Stats */ 6822 reg = rd32(E1000_MANC); 6823 if (reg & E1000_MANC_EN_BMC2OS) { 6824 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6825 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6826 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6827 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6828 } 6829 } 6830 6831 static void igb_perout(struct igb_adapter *adapter, int tsintr_tt) 6832 { 6833 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_PEROUT, tsintr_tt); 6834 struct e1000_hw *hw = &adapter->hw; 6835 struct timespec64 ts; 6836 u32 tsauxc; 6837 6838 if (pin < 0 || pin >= IGB_N_SDP) 6839 return; 6840 6841 spin_lock(&adapter->tmreg_lock); 6842 6843 if (hw->mac.type == e1000_82580 || 6844 hw->mac.type == e1000_i354 || 6845 hw->mac.type == e1000_i350) { 6846 s64 ns = timespec64_to_ns(&adapter->perout[tsintr_tt].period); 6847 u32 systiml, systimh, level_mask, level, rem; 6848 u64 systim, now; 6849 6850 /* read systim registers in sequence */ 6851 rd32(E1000_SYSTIMR); 6852 systiml = rd32(E1000_SYSTIML); 6853 systimh = rd32(E1000_SYSTIMH); 6854 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml); 6855 now = timecounter_cyc2time(&adapter->tc, systim); 6856 6857 if (pin < 2) { 6858 level_mask = (tsintr_tt == 1) ? 0x80000 : 0x40000; 6859 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0; 6860 } else { 6861 level_mask = (tsintr_tt == 1) ? 0x80 : 0x40; 6862 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0; 6863 } 6864 6865 div_u64_rem(now, ns, &rem); 6866 systim = systim + (ns - rem); 6867 6868 /* synchronize pin level with rising/falling edges */ 6869 div_u64_rem(now, ns << 1, &rem); 6870 if (rem < ns) { 6871 /* first half of period */ 6872 if (level == 0) { 6873 /* output is already low, skip this period */ 6874 systim += ns; 6875 pr_notice("igb: periodic output on %s missed falling edge\n", 6876 adapter->sdp_config[pin].name); 6877 } 6878 } else { 6879 /* second half of period */ 6880 if (level == 1) { 6881 /* output is already high, skip this period */ 6882 systim += ns; 6883 pr_notice("igb: periodic output on %s missed rising edge\n", 6884 adapter->sdp_config[pin].name); 6885 } 6886 } 6887 6888 /* for this chip family tv_sec is the upper part of the binary value, 6889 * so not seconds 6890 */ 6891 ts.tv_nsec = (u32)systim; 6892 ts.tv_sec = ((u32)(systim >> 32)) & 0xFF; 6893 } else { 6894 ts = timespec64_add(adapter->perout[tsintr_tt].start, 6895 adapter->perout[tsintr_tt].period); 6896 } 6897 6898 /* u32 conversion of tv_sec is safe until y2106 */ 6899 wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec); 6900 wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec); 6901 tsauxc = rd32(E1000_TSAUXC); 6902 tsauxc |= TSAUXC_EN_TT0; 6903 wr32(E1000_TSAUXC, tsauxc); 6904 adapter->perout[tsintr_tt].start = ts; 6905 6906 spin_unlock(&adapter->tmreg_lock); 6907 } 6908 6909 static void igb_extts(struct igb_adapter *adapter, int tsintr_tt) 6910 { 6911 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_EXTTS, tsintr_tt); 6912 int auxstmpl = (tsintr_tt == 1) ? E1000_AUXSTMPL1 : E1000_AUXSTMPL0; 6913 int auxstmph = (tsintr_tt == 1) ? E1000_AUXSTMPH1 : E1000_AUXSTMPH0; 6914 struct e1000_hw *hw = &adapter->hw; 6915 struct ptp_clock_event event; 6916 struct timespec64 ts; 6917 6918 if (pin < 0 || pin >= IGB_N_SDP) 6919 return; 6920 6921 if (hw->mac.type == e1000_82580 || 6922 hw->mac.type == e1000_i354 || 6923 hw->mac.type == e1000_i350) { 6924 s64 ns = rd32(auxstmpl); 6925 6926 ns += ((s64)(rd32(auxstmph) & 0xFF)) << 32; 6927 ts = ns_to_timespec64(ns); 6928 } else { 6929 ts.tv_nsec = rd32(auxstmpl); 6930 ts.tv_sec = rd32(auxstmph); 6931 } 6932 6933 event.type = PTP_CLOCK_EXTTS; 6934 event.index = tsintr_tt; 6935 event.timestamp = ts.tv_sec * 1000000000ULL + ts.tv_nsec; 6936 ptp_clock_event(adapter->ptp_clock, &event); 6937 } 6938 6939 static void igb_tsync_interrupt(struct igb_adapter *adapter) 6940 { 6941 struct e1000_hw *hw = &adapter->hw; 6942 u32 ack = 0, tsicr = rd32(E1000_TSICR); 6943 struct ptp_clock_event event; 6944 6945 if (tsicr & TSINTR_SYS_WRAP) { 6946 event.type = PTP_CLOCK_PPS; 6947 if (adapter->ptp_caps.pps) 6948 ptp_clock_event(adapter->ptp_clock, &event); 6949 ack |= TSINTR_SYS_WRAP; 6950 } 6951 6952 if (tsicr & E1000_TSICR_TXTS) { 6953 /* retrieve hardware timestamp */ 6954 schedule_work(&adapter->ptp_tx_work); 6955 ack |= E1000_TSICR_TXTS; 6956 } 6957 6958 if (tsicr & TSINTR_TT0) { 6959 igb_perout(adapter, 0); 6960 ack |= TSINTR_TT0; 6961 } 6962 6963 if (tsicr & TSINTR_TT1) { 6964 igb_perout(adapter, 1); 6965 ack |= TSINTR_TT1; 6966 } 6967 6968 if (tsicr & TSINTR_AUTT0) { 6969 igb_extts(adapter, 0); 6970 ack |= TSINTR_AUTT0; 6971 } 6972 6973 if (tsicr & TSINTR_AUTT1) { 6974 igb_extts(adapter, 1); 6975 ack |= TSINTR_AUTT1; 6976 } 6977 6978 /* acknowledge the interrupts */ 6979 wr32(E1000_TSICR, ack); 6980 } 6981 6982 static irqreturn_t igb_msix_other(int irq, void *data) 6983 { 6984 struct igb_adapter *adapter = data; 6985 struct e1000_hw *hw = &adapter->hw; 6986 u32 icr = rd32(E1000_ICR); 6987 /* reading ICR causes bit 31 of EICR to be cleared */ 6988 6989 if (icr & E1000_ICR_DRSTA) 6990 schedule_work(&adapter->reset_task); 6991 6992 if (icr & E1000_ICR_DOUTSYNC) { 6993 /* HW is reporting DMA is out of sync */ 6994 adapter->stats.doosync++; 6995 /* The DMA Out of Sync is also indication of a spoof event 6996 * in IOV mode. Check the Wrong VM Behavior register to 6997 * see if it is really a spoof event. 6998 */ 6999 igb_check_wvbr(adapter); 7000 } 7001 7002 /* Check for a mailbox event */ 7003 if (icr & E1000_ICR_VMMB) 7004 igb_msg_task(adapter); 7005 7006 if (icr & E1000_ICR_LSC) { 7007 hw->mac.get_link_status = 1; 7008 /* guard against interrupt when we're going down */ 7009 if (!test_bit(__IGB_DOWN, &adapter->state)) 7010 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7011 } 7012 7013 if (icr & E1000_ICR_TS) 7014 igb_tsync_interrupt(adapter); 7015 7016 wr32(E1000_EIMS, adapter->eims_other); 7017 7018 return IRQ_HANDLED; 7019 } 7020 7021 static void igb_write_itr(struct igb_q_vector *q_vector) 7022 { 7023 struct igb_adapter *adapter = q_vector->adapter; 7024 u32 itr_val = q_vector->itr_val & 0x7FFC; 7025 7026 if (!q_vector->set_itr) 7027 return; 7028 7029 if (!itr_val) 7030 itr_val = 0x4; 7031 7032 if (adapter->hw.mac.type == e1000_82575) 7033 itr_val |= itr_val << 16; 7034 else 7035 itr_val |= E1000_EITR_CNT_IGNR; 7036 7037 writel(itr_val, q_vector->itr_register); 7038 q_vector->set_itr = 0; 7039 } 7040 7041 static irqreturn_t igb_msix_ring(int irq, void *data) 7042 { 7043 struct igb_q_vector *q_vector = data; 7044 7045 /* Write the ITR value calculated from the previous interrupt. */ 7046 igb_write_itr(q_vector); 7047 7048 napi_schedule(&q_vector->napi); 7049 7050 return IRQ_HANDLED; 7051 } 7052 7053 #ifdef CONFIG_IGB_DCA 7054 static void igb_update_tx_dca(struct igb_adapter *adapter, 7055 struct igb_ring *tx_ring, 7056 int cpu) 7057 { 7058 struct e1000_hw *hw = &adapter->hw; 7059 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 7060 7061 if (hw->mac.type != e1000_82575) 7062 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 7063 7064 /* We can enable relaxed ordering for reads, but not writes when 7065 * DCA is enabled. This is due to a known issue in some chipsets 7066 * which will cause the DCA tag to be cleared. 7067 */ 7068 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 7069 E1000_DCA_TXCTRL_DATA_RRO_EN | 7070 E1000_DCA_TXCTRL_DESC_DCA_EN; 7071 7072 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 7073 } 7074 7075 static void igb_update_rx_dca(struct igb_adapter *adapter, 7076 struct igb_ring *rx_ring, 7077 int cpu) 7078 { 7079 struct e1000_hw *hw = &adapter->hw; 7080 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 7081 7082 if (hw->mac.type != e1000_82575) 7083 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 7084 7085 /* We can enable relaxed ordering for reads, but not writes when 7086 * DCA is enabled. This is due to a known issue in some chipsets 7087 * which will cause the DCA tag to be cleared. 7088 */ 7089 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 7090 E1000_DCA_RXCTRL_DESC_DCA_EN; 7091 7092 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 7093 } 7094 7095 static void igb_update_dca(struct igb_q_vector *q_vector) 7096 { 7097 struct igb_adapter *adapter = q_vector->adapter; 7098 int cpu = get_cpu(); 7099 7100 if (q_vector->cpu == cpu) 7101 goto out_no_update; 7102 7103 if (q_vector->tx.ring) 7104 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 7105 7106 if (q_vector->rx.ring) 7107 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 7108 7109 q_vector->cpu = cpu; 7110 out_no_update: 7111 put_cpu(); 7112 } 7113 7114 static void igb_setup_dca(struct igb_adapter *adapter) 7115 { 7116 struct e1000_hw *hw = &adapter->hw; 7117 int i; 7118 7119 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 7120 return; 7121 7122 /* Always use CB2 mode, difference is masked in the CB driver. */ 7123 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 7124 7125 for (i = 0; i < adapter->num_q_vectors; i++) { 7126 adapter->q_vector[i]->cpu = -1; 7127 igb_update_dca(adapter->q_vector[i]); 7128 } 7129 } 7130 7131 static int __igb_notify_dca(struct device *dev, void *data) 7132 { 7133 struct net_device *netdev = dev_get_drvdata(dev); 7134 struct igb_adapter *adapter = netdev_priv(netdev); 7135 struct pci_dev *pdev = adapter->pdev; 7136 struct e1000_hw *hw = &adapter->hw; 7137 unsigned long event = *(unsigned long *)data; 7138 7139 switch (event) { 7140 case DCA_PROVIDER_ADD: 7141 /* if already enabled, don't do it again */ 7142 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 7143 break; 7144 if (dca_add_requester(dev) == 0) { 7145 adapter->flags |= IGB_FLAG_DCA_ENABLED; 7146 dev_info(&pdev->dev, "DCA enabled\n"); 7147 igb_setup_dca(adapter); 7148 break; 7149 } 7150 fallthrough; /* since DCA is disabled. */ 7151 case DCA_PROVIDER_REMOVE: 7152 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 7153 /* without this a class_device is left 7154 * hanging around in the sysfs model 7155 */ 7156 dca_remove_requester(dev); 7157 dev_info(&pdev->dev, "DCA disabled\n"); 7158 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 7159 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 7160 } 7161 break; 7162 } 7163 7164 return 0; 7165 } 7166 7167 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 7168 void *p) 7169 { 7170 int ret_val; 7171 7172 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 7173 __igb_notify_dca); 7174 7175 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 7176 } 7177 #endif /* CONFIG_IGB_DCA */ 7178 7179 #ifdef CONFIG_PCI_IOV 7180 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 7181 { 7182 unsigned char mac_addr[ETH_ALEN]; 7183 7184 eth_zero_addr(mac_addr); 7185 igb_set_vf_mac(adapter, vf, mac_addr); 7186 7187 /* By default spoof check is enabled for all VFs */ 7188 adapter->vf_data[vf].spoofchk_enabled = true; 7189 7190 /* By default VFs are not trusted */ 7191 adapter->vf_data[vf].trusted = false; 7192 7193 return 0; 7194 } 7195 7196 #endif 7197 static void igb_ping_all_vfs(struct igb_adapter *adapter) 7198 { 7199 struct e1000_hw *hw = &adapter->hw; 7200 u32 ping; 7201 int i; 7202 7203 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 7204 ping = E1000_PF_CONTROL_MSG; 7205 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 7206 ping |= E1000_VT_MSGTYPE_CTS; 7207 igb_write_mbx(hw, &ping, 1, i); 7208 } 7209 } 7210 7211 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7212 { 7213 struct e1000_hw *hw = &adapter->hw; 7214 u32 vmolr = rd32(E1000_VMOLR(vf)); 7215 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7216 7217 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 7218 IGB_VF_FLAG_MULTI_PROMISC); 7219 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7220 7221 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 7222 vmolr |= E1000_VMOLR_MPME; 7223 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 7224 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 7225 } else { 7226 /* if we have hashes and we are clearing a multicast promisc 7227 * flag we need to write the hashes to the MTA as this step 7228 * was previously skipped 7229 */ 7230 if (vf_data->num_vf_mc_hashes > 30) { 7231 vmolr |= E1000_VMOLR_MPME; 7232 } else if (vf_data->num_vf_mc_hashes) { 7233 int j; 7234 7235 vmolr |= E1000_VMOLR_ROMPE; 7236 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7237 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7238 } 7239 } 7240 7241 wr32(E1000_VMOLR(vf), vmolr); 7242 7243 /* there are flags left unprocessed, likely not supported */ 7244 if (*msgbuf & E1000_VT_MSGINFO_MASK) 7245 return -EINVAL; 7246 7247 return 0; 7248 } 7249 7250 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 7251 u32 *msgbuf, u32 vf) 7252 { 7253 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7254 u16 *hash_list = (u16 *)&msgbuf[1]; 7255 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7256 int i; 7257 7258 /* salt away the number of multicast addresses assigned 7259 * to this VF for later use to restore when the PF multi cast 7260 * list changes 7261 */ 7262 vf_data->num_vf_mc_hashes = n; 7263 7264 /* only up to 30 hash values supported */ 7265 if (n > 30) 7266 n = 30; 7267 7268 /* store the hashes for later use */ 7269 for (i = 0; i < n; i++) 7270 vf_data->vf_mc_hashes[i] = hash_list[i]; 7271 7272 /* Flush and reset the mta with the new values */ 7273 igb_set_rx_mode(adapter->netdev); 7274 7275 return 0; 7276 } 7277 7278 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 7279 { 7280 struct e1000_hw *hw = &adapter->hw; 7281 struct vf_data_storage *vf_data; 7282 int i, j; 7283 7284 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7285 u32 vmolr = rd32(E1000_VMOLR(i)); 7286 7287 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7288 7289 vf_data = &adapter->vf_data[i]; 7290 7291 if ((vf_data->num_vf_mc_hashes > 30) || 7292 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 7293 vmolr |= E1000_VMOLR_MPME; 7294 } else if (vf_data->num_vf_mc_hashes) { 7295 vmolr |= E1000_VMOLR_ROMPE; 7296 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7297 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7298 } 7299 wr32(E1000_VMOLR(i), vmolr); 7300 } 7301 } 7302 7303 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 7304 { 7305 struct e1000_hw *hw = &adapter->hw; 7306 u32 pool_mask, vlvf_mask, i; 7307 7308 /* create mask for VF and other pools */ 7309 pool_mask = E1000_VLVF_POOLSEL_MASK; 7310 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 7311 7312 /* drop PF from pool bits */ 7313 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 7314 adapter->vfs_allocated_count); 7315 7316 /* Find the vlan filter for this id */ 7317 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 7318 u32 vlvf = rd32(E1000_VLVF(i)); 7319 u32 vfta_mask, vid, vfta; 7320 7321 /* remove the vf from the pool */ 7322 if (!(vlvf & vlvf_mask)) 7323 continue; 7324 7325 /* clear out bit from VLVF */ 7326 vlvf ^= vlvf_mask; 7327 7328 /* if other pools are present, just remove ourselves */ 7329 if (vlvf & pool_mask) 7330 goto update_vlvfb; 7331 7332 /* if PF is present, leave VFTA */ 7333 if (vlvf & E1000_VLVF_POOLSEL_MASK) 7334 goto update_vlvf; 7335 7336 vid = vlvf & E1000_VLVF_VLANID_MASK; 7337 vfta_mask = BIT(vid % 32); 7338 7339 /* clear bit from VFTA */ 7340 vfta = adapter->shadow_vfta[vid / 32]; 7341 if (vfta & vfta_mask) 7342 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 7343 update_vlvf: 7344 /* clear pool selection enable */ 7345 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7346 vlvf &= E1000_VLVF_POOLSEL_MASK; 7347 else 7348 vlvf = 0; 7349 update_vlvfb: 7350 /* clear pool bits */ 7351 wr32(E1000_VLVF(i), vlvf); 7352 } 7353 } 7354 7355 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 7356 { 7357 u32 vlvf; 7358 int idx; 7359 7360 /* short cut the special case */ 7361 if (vlan == 0) 7362 return 0; 7363 7364 /* Search for the VLAN id in the VLVF entries */ 7365 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 7366 vlvf = rd32(E1000_VLVF(idx)); 7367 if ((vlvf & VLAN_VID_MASK) == vlan) 7368 break; 7369 } 7370 7371 return idx; 7372 } 7373 7374 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 7375 { 7376 struct e1000_hw *hw = &adapter->hw; 7377 u32 bits, pf_id; 7378 int idx; 7379 7380 idx = igb_find_vlvf_entry(hw, vid); 7381 if (!idx) 7382 return; 7383 7384 /* See if any other pools are set for this VLAN filter 7385 * entry other than the PF. 7386 */ 7387 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 7388 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 7389 bits &= rd32(E1000_VLVF(idx)); 7390 7391 /* Disable the filter so this falls into the default pool. */ 7392 if (!bits) { 7393 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7394 wr32(E1000_VLVF(idx), BIT(pf_id)); 7395 else 7396 wr32(E1000_VLVF(idx), 0); 7397 } 7398 } 7399 7400 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 7401 bool add, u32 vf) 7402 { 7403 int pf_id = adapter->vfs_allocated_count; 7404 struct e1000_hw *hw = &adapter->hw; 7405 int err; 7406 7407 /* If VLAN overlaps with one the PF is currently monitoring make 7408 * sure that we are able to allocate a VLVF entry. This may be 7409 * redundant but it guarantees PF will maintain visibility to 7410 * the VLAN. 7411 */ 7412 if (add && test_bit(vid, adapter->active_vlans)) { 7413 err = igb_vfta_set(hw, vid, pf_id, true, false); 7414 if (err) 7415 return err; 7416 } 7417 7418 err = igb_vfta_set(hw, vid, vf, add, false); 7419 7420 if (add && !err) 7421 return err; 7422 7423 /* If we failed to add the VF VLAN or we are removing the VF VLAN 7424 * we may need to drop the PF pool bit in order to allow us to free 7425 * up the VLVF resources. 7426 */ 7427 if (test_bit(vid, adapter->active_vlans) || 7428 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7429 igb_update_pf_vlvf(adapter, vid); 7430 7431 return err; 7432 } 7433 7434 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 7435 { 7436 struct e1000_hw *hw = &adapter->hw; 7437 7438 if (vid) 7439 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 7440 else 7441 wr32(E1000_VMVIR(vf), 0); 7442 } 7443 7444 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7445 u16 vlan, u8 qos) 7446 { 7447 int err; 7448 7449 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7450 if (err) 7451 return err; 7452 7453 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7454 igb_set_vmolr(adapter, vf, !vlan); 7455 7456 /* revoke access to previous VLAN */ 7457 if (vlan != adapter->vf_data[vf].pf_vlan) 7458 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7459 false, vf); 7460 7461 adapter->vf_data[vf].pf_vlan = vlan; 7462 adapter->vf_data[vf].pf_qos = qos; 7463 igb_set_vf_vlan_strip(adapter, vf, true); 7464 dev_info(&adapter->pdev->dev, 7465 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7466 if (test_bit(__IGB_DOWN, &adapter->state)) { 7467 dev_warn(&adapter->pdev->dev, 7468 "The VF VLAN has been set, but the PF device is not up.\n"); 7469 dev_warn(&adapter->pdev->dev, 7470 "Bring the PF device up before attempting to use the VF device.\n"); 7471 } 7472 7473 return err; 7474 } 7475 7476 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7477 { 7478 /* Restore tagless access via VLAN 0 */ 7479 igb_set_vf_vlan(adapter, 0, true, vf); 7480 7481 igb_set_vmvir(adapter, 0, vf); 7482 igb_set_vmolr(adapter, vf, true); 7483 7484 /* Remove any PF assigned VLAN */ 7485 if (adapter->vf_data[vf].pf_vlan) 7486 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7487 false, vf); 7488 7489 adapter->vf_data[vf].pf_vlan = 0; 7490 adapter->vf_data[vf].pf_qos = 0; 7491 igb_set_vf_vlan_strip(adapter, vf, false); 7492 7493 return 0; 7494 } 7495 7496 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7497 u16 vlan, u8 qos, __be16 vlan_proto) 7498 { 7499 struct igb_adapter *adapter = netdev_priv(netdev); 7500 7501 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7502 return -EINVAL; 7503 7504 if (vlan_proto != htons(ETH_P_8021Q)) 7505 return -EPROTONOSUPPORT; 7506 7507 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7508 igb_disable_port_vlan(adapter, vf); 7509 } 7510 7511 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7512 { 7513 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7514 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7515 int ret; 7516 7517 if (adapter->vf_data[vf].pf_vlan) 7518 return -1; 7519 7520 /* VLAN 0 is a special case, don't allow it to be removed */ 7521 if (!vid && !add) 7522 return 0; 7523 7524 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7525 if (!ret) 7526 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7527 return ret; 7528 } 7529 7530 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7531 { 7532 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7533 7534 /* clear flags - except flag that indicates PF has set the MAC */ 7535 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7536 vf_data->last_nack = jiffies; 7537 7538 /* reset vlans for device */ 7539 igb_clear_vf_vfta(adapter, vf); 7540 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7541 igb_set_vmvir(adapter, vf_data->pf_vlan | 7542 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7543 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7544 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7545 7546 /* reset multicast table array for vf */ 7547 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7548 7549 /* Flush and reset the mta with the new values */ 7550 igb_set_rx_mode(adapter->netdev); 7551 } 7552 7553 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7554 { 7555 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7556 7557 /* clear mac address as we were hotplug removed/added */ 7558 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7559 eth_zero_addr(vf_mac); 7560 7561 /* process remaining reset events */ 7562 igb_vf_reset(adapter, vf); 7563 } 7564 7565 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7566 { 7567 struct e1000_hw *hw = &adapter->hw; 7568 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7569 u32 reg, msgbuf[3] = {}; 7570 u8 *addr = (u8 *)(&msgbuf[1]); 7571 7572 /* process all the same items cleared in a function level reset */ 7573 igb_vf_reset(adapter, vf); 7574 7575 /* set vf mac address */ 7576 igb_set_vf_mac(adapter, vf, vf_mac); 7577 7578 /* enable transmit and receive for vf */ 7579 reg = rd32(E1000_VFTE); 7580 wr32(E1000_VFTE, reg | BIT(vf)); 7581 reg = rd32(E1000_VFRE); 7582 wr32(E1000_VFRE, reg | BIT(vf)); 7583 7584 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7585 7586 /* reply to reset with ack and vf mac address */ 7587 if (!is_zero_ether_addr(vf_mac)) { 7588 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7589 memcpy(addr, vf_mac, ETH_ALEN); 7590 } else { 7591 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7592 } 7593 igb_write_mbx(hw, msgbuf, 3, vf); 7594 } 7595 7596 static void igb_flush_mac_table(struct igb_adapter *adapter) 7597 { 7598 struct e1000_hw *hw = &adapter->hw; 7599 int i; 7600 7601 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7602 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7603 eth_zero_addr(adapter->mac_table[i].addr); 7604 adapter->mac_table[i].queue = 0; 7605 igb_rar_set_index(adapter, i); 7606 } 7607 } 7608 7609 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7610 { 7611 struct e1000_hw *hw = &adapter->hw; 7612 /* do not count rar entries reserved for VFs MAC addresses */ 7613 int rar_entries = hw->mac.rar_entry_count - 7614 adapter->vfs_allocated_count; 7615 int i, count = 0; 7616 7617 for (i = 0; i < rar_entries; i++) { 7618 /* do not count default entries */ 7619 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7620 continue; 7621 7622 /* do not count "in use" entries for different queues */ 7623 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7624 (adapter->mac_table[i].queue != queue)) 7625 continue; 7626 7627 count++; 7628 } 7629 7630 return count; 7631 } 7632 7633 /* Set default MAC address for the PF in the first RAR entry */ 7634 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7635 { 7636 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7637 7638 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7639 mac_table->queue = adapter->vfs_allocated_count; 7640 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7641 7642 igb_rar_set_index(adapter, 0); 7643 } 7644 7645 /* If the filter to be added and an already existing filter express 7646 * the same address and address type, it should be possible to only 7647 * override the other configurations, for example the queue to steer 7648 * traffic. 7649 */ 7650 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7651 const u8 *addr, const u8 flags) 7652 { 7653 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7654 return true; 7655 7656 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7657 (flags & IGB_MAC_STATE_SRC_ADDR)) 7658 return false; 7659 7660 if (!ether_addr_equal(addr, entry->addr)) 7661 return false; 7662 7663 return true; 7664 } 7665 7666 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7667 * 'flags' is used to indicate what kind of match is made, match is by 7668 * default for the destination address, if matching by source address 7669 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7670 */ 7671 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7672 const u8 *addr, const u8 queue, 7673 const u8 flags) 7674 { 7675 struct e1000_hw *hw = &adapter->hw; 7676 int rar_entries = hw->mac.rar_entry_count - 7677 adapter->vfs_allocated_count; 7678 int i; 7679 7680 if (is_zero_ether_addr(addr)) 7681 return -EINVAL; 7682 7683 /* Search for the first empty entry in the MAC table. 7684 * Do not touch entries at the end of the table reserved for the VF MAC 7685 * addresses. 7686 */ 7687 for (i = 0; i < rar_entries; i++) { 7688 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7689 addr, flags)) 7690 continue; 7691 7692 ether_addr_copy(adapter->mac_table[i].addr, addr); 7693 adapter->mac_table[i].queue = queue; 7694 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7695 7696 igb_rar_set_index(adapter, i); 7697 return i; 7698 } 7699 7700 return -ENOSPC; 7701 } 7702 7703 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7704 const u8 queue) 7705 { 7706 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7707 } 7708 7709 /* Remove a MAC filter for 'addr' directing matching traffic to 7710 * 'queue', 'flags' is used to indicate what kind of match need to be 7711 * removed, match is by default for the destination address, if 7712 * matching by source address is to be removed the flag 7713 * IGB_MAC_STATE_SRC_ADDR can be used. 7714 */ 7715 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7716 const u8 *addr, const u8 queue, 7717 const u8 flags) 7718 { 7719 struct e1000_hw *hw = &adapter->hw; 7720 int rar_entries = hw->mac.rar_entry_count - 7721 adapter->vfs_allocated_count; 7722 int i; 7723 7724 if (is_zero_ether_addr(addr)) 7725 return -EINVAL; 7726 7727 /* Search for matching entry in the MAC table based on given address 7728 * and queue. Do not touch entries at the end of the table reserved 7729 * for the VF MAC addresses. 7730 */ 7731 for (i = 0; i < rar_entries; i++) { 7732 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7733 continue; 7734 if ((adapter->mac_table[i].state & flags) != flags) 7735 continue; 7736 if (adapter->mac_table[i].queue != queue) 7737 continue; 7738 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7739 continue; 7740 7741 /* When a filter for the default address is "deleted", 7742 * we return it to its initial configuration 7743 */ 7744 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7745 adapter->mac_table[i].state = 7746 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7747 adapter->mac_table[i].queue = 7748 adapter->vfs_allocated_count; 7749 } else { 7750 adapter->mac_table[i].state = 0; 7751 adapter->mac_table[i].queue = 0; 7752 eth_zero_addr(adapter->mac_table[i].addr); 7753 } 7754 7755 igb_rar_set_index(adapter, i); 7756 return 0; 7757 } 7758 7759 return -ENOENT; 7760 } 7761 7762 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7763 const u8 queue) 7764 { 7765 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7766 } 7767 7768 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7769 const u8 *addr, u8 queue, u8 flags) 7770 { 7771 struct e1000_hw *hw = &adapter->hw; 7772 7773 /* In theory, this should be supported on 82575 as well, but 7774 * that part wasn't easily accessible during development. 7775 */ 7776 if (hw->mac.type != e1000_i210) 7777 return -EOPNOTSUPP; 7778 7779 return igb_add_mac_filter_flags(adapter, addr, queue, 7780 IGB_MAC_STATE_QUEUE_STEERING | flags); 7781 } 7782 7783 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7784 const u8 *addr, u8 queue, u8 flags) 7785 { 7786 return igb_del_mac_filter_flags(adapter, addr, queue, 7787 IGB_MAC_STATE_QUEUE_STEERING | flags); 7788 } 7789 7790 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7791 { 7792 struct igb_adapter *adapter = netdev_priv(netdev); 7793 int ret; 7794 7795 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7796 7797 return min_t(int, ret, 0); 7798 } 7799 7800 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7801 { 7802 struct igb_adapter *adapter = netdev_priv(netdev); 7803 7804 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7805 7806 return 0; 7807 } 7808 7809 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7810 const u32 info, const u8 *addr) 7811 { 7812 struct pci_dev *pdev = adapter->pdev; 7813 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7814 struct list_head *pos; 7815 struct vf_mac_filter *entry = NULL; 7816 int ret = 0; 7817 7818 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7819 !vf_data->trusted) { 7820 dev_warn(&pdev->dev, 7821 "VF %d requested MAC filter but is administratively denied\n", 7822 vf); 7823 return -EINVAL; 7824 } 7825 if (!is_valid_ether_addr(addr)) { 7826 dev_warn(&pdev->dev, 7827 "VF %d attempted to set invalid MAC filter\n", 7828 vf); 7829 return -EINVAL; 7830 } 7831 7832 switch (info) { 7833 case E1000_VF_MAC_FILTER_CLR: 7834 /* remove all unicast MAC filters related to the current VF */ 7835 list_for_each(pos, &adapter->vf_macs.l) { 7836 entry = list_entry(pos, struct vf_mac_filter, l); 7837 if (entry->vf == vf) { 7838 entry->vf = -1; 7839 entry->free = true; 7840 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7841 } 7842 } 7843 break; 7844 case E1000_VF_MAC_FILTER_ADD: 7845 /* try to find empty slot in the list */ 7846 list_for_each(pos, &adapter->vf_macs.l) { 7847 entry = list_entry(pos, struct vf_mac_filter, l); 7848 if (entry->free) 7849 break; 7850 } 7851 7852 if (entry && entry->free) { 7853 entry->free = false; 7854 entry->vf = vf; 7855 ether_addr_copy(entry->vf_mac, addr); 7856 7857 ret = igb_add_mac_filter(adapter, addr, vf); 7858 ret = min_t(int, ret, 0); 7859 } else { 7860 ret = -ENOSPC; 7861 } 7862 7863 if (ret == -ENOSPC) 7864 dev_warn(&pdev->dev, 7865 "VF %d has requested MAC filter but there is no space for it\n", 7866 vf); 7867 break; 7868 default: 7869 ret = -EINVAL; 7870 break; 7871 } 7872 7873 return ret; 7874 } 7875 7876 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7877 { 7878 struct pci_dev *pdev = adapter->pdev; 7879 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7880 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7881 7882 /* The VF MAC Address is stored in a packed array of bytes 7883 * starting at the second 32 bit word of the msg array 7884 */ 7885 unsigned char *addr = (unsigned char *)&msg[1]; 7886 int ret = 0; 7887 7888 if (!info) { 7889 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7890 !vf_data->trusted) { 7891 dev_warn(&pdev->dev, 7892 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 7893 vf); 7894 return -EINVAL; 7895 } 7896 7897 if (!is_valid_ether_addr(addr)) { 7898 dev_warn(&pdev->dev, 7899 "VF %d attempted to set invalid MAC\n", 7900 vf); 7901 return -EINVAL; 7902 } 7903 7904 ret = igb_set_vf_mac(adapter, vf, addr); 7905 } else { 7906 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 7907 } 7908 7909 return ret; 7910 } 7911 7912 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 7913 { 7914 struct e1000_hw *hw = &adapter->hw; 7915 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7916 u32 msg = E1000_VT_MSGTYPE_NACK; 7917 7918 /* if device isn't clear to send it shouldn't be reading either */ 7919 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 7920 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 7921 igb_write_mbx(hw, &msg, 1, vf); 7922 vf_data->last_nack = jiffies; 7923 } 7924 } 7925 7926 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 7927 { 7928 struct pci_dev *pdev = adapter->pdev; 7929 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 7930 struct e1000_hw *hw = &adapter->hw; 7931 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7932 s32 retval; 7933 7934 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 7935 7936 if (retval) { 7937 /* if receive failed revoke VF CTS stats and restart init */ 7938 dev_err(&pdev->dev, "Error receiving message from VF\n"); 7939 vf_data->flags &= ~IGB_VF_FLAG_CTS; 7940 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7941 goto unlock; 7942 goto out; 7943 } 7944 7945 /* this is a message we already processed, do nothing */ 7946 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 7947 goto unlock; 7948 7949 /* until the vf completes a reset it should not be 7950 * allowed to start any configuration. 7951 */ 7952 if (msgbuf[0] == E1000_VF_RESET) { 7953 /* unlocks mailbox */ 7954 igb_vf_reset_msg(adapter, vf); 7955 return; 7956 } 7957 7958 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 7959 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7960 goto unlock; 7961 retval = -1; 7962 goto out; 7963 } 7964 7965 switch ((msgbuf[0] & 0xFFFF)) { 7966 case E1000_VF_SET_MAC_ADDR: 7967 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 7968 break; 7969 case E1000_VF_SET_PROMISC: 7970 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 7971 break; 7972 case E1000_VF_SET_MULTICAST: 7973 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 7974 break; 7975 case E1000_VF_SET_LPE: 7976 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 7977 break; 7978 case E1000_VF_SET_VLAN: 7979 retval = -1; 7980 if (vf_data->pf_vlan) 7981 dev_warn(&pdev->dev, 7982 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 7983 vf); 7984 else 7985 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 7986 break; 7987 default: 7988 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 7989 retval = -1; 7990 break; 7991 } 7992 7993 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 7994 out: 7995 /* notify the VF of the results of what it sent us */ 7996 if (retval) 7997 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 7998 else 7999 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 8000 8001 /* unlocks mailbox */ 8002 igb_write_mbx(hw, msgbuf, 1, vf); 8003 return; 8004 8005 unlock: 8006 igb_unlock_mbx(hw, vf); 8007 } 8008 8009 static void igb_msg_task(struct igb_adapter *adapter) 8010 { 8011 struct e1000_hw *hw = &adapter->hw; 8012 unsigned long flags; 8013 u32 vf; 8014 8015 spin_lock_irqsave(&adapter->vfs_lock, flags); 8016 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 8017 /* process any reset requests */ 8018 if (!igb_check_for_rst(hw, vf)) 8019 igb_vf_reset_event(adapter, vf); 8020 8021 /* process any messages pending */ 8022 if (!igb_check_for_msg(hw, vf)) 8023 igb_rcv_msg_from_vf(adapter, vf); 8024 8025 /* process any acks */ 8026 if (!igb_check_for_ack(hw, vf)) 8027 igb_rcv_ack_from_vf(adapter, vf); 8028 } 8029 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 8030 } 8031 8032 /** 8033 * igb_set_uta - Set unicast filter table address 8034 * @adapter: board private structure 8035 * @set: boolean indicating if we are setting or clearing bits 8036 * 8037 * The unicast table address is a register array of 32-bit registers. 8038 * The table is meant to be used in a way similar to how the MTA is used 8039 * however due to certain limitations in the hardware it is necessary to 8040 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 8041 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 8042 **/ 8043 static void igb_set_uta(struct igb_adapter *adapter, bool set) 8044 { 8045 struct e1000_hw *hw = &adapter->hw; 8046 u32 uta = set ? ~0 : 0; 8047 int i; 8048 8049 /* we only need to do this if VMDq is enabled */ 8050 if (!adapter->vfs_allocated_count) 8051 return; 8052 8053 for (i = hw->mac.uta_reg_count; i--;) 8054 array_wr32(E1000_UTA, i, uta); 8055 } 8056 8057 /** 8058 * igb_intr_msi - Interrupt Handler 8059 * @irq: interrupt number 8060 * @data: pointer to a network interface device structure 8061 **/ 8062 static irqreturn_t igb_intr_msi(int irq, void *data) 8063 { 8064 struct igb_adapter *adapter = data; 8065 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8066 struct e1000_hw *hw = &adapter->hw; 8067 /* read ICR disables interrupts using IAM */ 8068 u32 icr = rd32(E1000_ICR); 8069 8070 igb_write_itr(q_vector); 8071 8072 if (icr & E1000_ICR_DRSTA) 8073 schedule_work(&adapter->reset_task); 8074 8075 if (icr & E1000_ICR_DOUTSYNC) { 8076 /* HW is reporting DMA is out of sync */ 8077 adapter->stats.doosync++; 8078 } 8079 8080 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8081 hw->mac.get_link_status = 1; 8082 if (!test_bit(__IGB_DOWN, &adapter->state)) 8083 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8084 } 8085 8086 if (icr & E1000_ICR_TS) 8087 igb_tsync_interrupt(adapter); 8088 8089 napi_schedule(&q_vector->napi); 8090 8091 return IRQ_HANDLED; 8092 } 8093 8094 /** 8095 * igb_intr - Legacy Interrupt Handler 8096 * @irq: interrupt number 8097 * @data: pointer to a network interface device structure 8098 **/ 8099 static irqreturn_t igb_intr(int irq, void *data) 8100 { 8101 struct igb_adapter *adapter = data; 8102 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8103 struct e1000_hw *hw = &adapter->hw; 8104 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 8105 * need for the IMC write 8106 */ 8107 u32 icr = rd32(E1000_ICR); 8108 8109 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 8110 * not set, then the adapter didn't send an interrupt 8111 */ 8112 if (!(icr & E1000_ICR_INT_ASSERTED)) 8113 return IRQ_NONE; 8114 8115 igb_write_itr(q_vector); 8116 8117 if (icr & E1000_ICR_DRSTA) 8118 schedule_work(&adapter->reset_task); 8119 8120 if (icr & E1000_ICR_DOUTSYNC) { 8121 /* HW is reporting DMA is out of sync */ 8122 adapter->stats.doosync++; 8123 } 8124 8125 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8126 hw->mac.get_link_status = 1; 8127 /* guard against interrupt when we're going down */ 8128 if (!test_bit(__IGB_DOWN, &adapter->state)) 8129 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8130 } 8131 8132 if (icr & E1000_ICR_TS) 8133 igb_tsync_interrupt(adapter); 8134 8135 napi_schedule(&q_vector->napi); 8136 8137 return IRQ_HANDLED; 8138 } 8139 8140 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 8141 { 8142 struct igb_adapter *adapter = q_vector->adapter; 8143 struct e1000_hw *hw = &adapter->hw; 8144 8145 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 8146 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 8147 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 8148 igb_set_itr(q_vector); 8149 else 8150 igb_update_ring_itr(q_vector); 8151 } 8152 8153 if (!test_bit(__IGB_DOWN, &adapter->state)) { 8154 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8155 wr32(E1000_EIMS, q_vector->eims_value); 8156 else 8157 igb_irq_enable(adapter); 8158 } 8159 } 8160 8161 /** 8162 * igb_poll - NAPI Rx polling callback 8163 * @napi: napi polling structure 8164 * @budget: count of how many packets we should handle 8165 **/ 8166 static int igb_poll(struct napi_struct *napi, int budget) 8167 { 8168 struct igb_q_vector *q_vector = container_of(napi, 8169 struct igb_q_vector, 8170 napi); 8171 bool clean_complete = true; 8172 int work_done = 0; 8173 8174 #ifdef CONFIG_IGB_DCA 8175 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 8176 igb_update_dca(q_vector); 8177 #endif 8178 if (q_vector->tx.ring) 8179 clean_complete = igb_clean_tx_irq(q_vector, budget); 8180 8181 if (q_vector->rx.ring) { 8182 int cleaned = igb_clean_rx_irq(q_vector, budget); 8183 8184 work_done += cleaned; 8185 if (cleaned >= budget) 8186 clean_complete = false; 8187 } 8188 8189 /* If all work not completed, return budget and keep polling */ 8190 if (!clean_complete) 8191 return budget; 8192 8193 /* Exit the polling mode, but don't re-enable interrupts if stack might 8194 * poll us due to busy-polling 8195 */ 8196 if (likely(napi_complete_done(napi, work_done))) 8197 igb_ring_irq_enable(q_vector); 8198 8199 return work_done; 8200 } 8201 8202 /** 8203 * igb_clean_tx_irq - Reclaim resources after transmit completes 8204 * @q_vector: pointer to q_vector containing needed info 8205 * @napi_budget: Used to determine if we are in netpoll 8206 * 8207 * returns true if ring is completely cleaned 8208 **/ 8209 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 8210 { 8211 struct igb_adapter *adapter = q_vector->adapter; 8212 struct igb_ring *tx_ring = q_vector->tx.ring; 8213 struct igb_tx_buffer *tx_buffer; 8214 union e1000_adv_tx_desc *tx_desc; 8215 unsigned int total_bytes = 0, total_packets = 0; 8216 unsigned int budget = q_vector->tx.work_limit; 8217 unsigned int i = tx_ring->next_to_clean; 8218 8219 if (test_bit(__IGB_DOWN, &adapter->state)) 8220 return true; 8221 8222 tx_buffer = &tx_ring->tx_buffer_info[i]; 8223 tx_desc = IGB_TX_DESC(tx_ring, i); 8224 i -= tx_ring->count; 8225 8226 do { 8227 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 8228 8229 /* if next_to_watch is not set then there is no work pending */ 8230 if (!eop_desc) 8231 break; 8232 8233 /* prevent any other reads prior to eop_desc */ 8234 smp_rmb(); 8235 8236 /* if DD is not set pending work has not been completed */ 8237 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 8238 break; 8239 8240 /* clear next_to_watch to prevent false hangs */ 8241 tx_buffer->next_to_watch = NULL; 8242 8243 /* update the statistics for this packet */ 8244 total_bytes += tx_buffer->bytecount; 8245 total_packets += tx_buffer->gso_segs; 8246 8247 /* free the skb */ 8248 if (tx_buffer->type == IGB_TYPE_SKB) 8249 napi_consume_skb(tx_buffer->skb, napi_budget); 8250 else 8251 xdp_return_frame(tx_buffer->xdpf); 8252 8253 /* unmap skb header data */ 8254 dma_unmap_single(tx_ring->dev, 8255 dma_unmap_addr(tx_buffer, dma), 8256 dma_unmap_len(tx_buffer, len), 8257 DMA_TO_DEVICE); 8258 8259 /* clear tx_buffer data */ 8260 dma_unmap_len_set(tx_buffer, len, 0); 8261 8262 /* clear last DMA location and unmap remaining buffers */ 8263 while (tx_desc != eop_desc) { 8264 tx_buffer++; 8265 tx_desc++; 8266 i++; 8267 if (unlikely(!i)) { 8268 i -= tx_ring->count; 8269 tx_buffer = tx_ring->tx_buffer_info; 8270 tx_desc = IGB_TX_DESC(tx_ring, 0); 8271 } 8272 8273 /* unmap any remaining paged data */ 8274 if (dma_unmap_len(tx_buffer, len)) { 8275 dma_unmap_page(tx_ring->dev, 8276 dma_unmap_addr(tx_buffer, dma), 8277 dma_unmap_len(tx_buffer, len), 8278 DMA_TO_DEVICE); 8279 dma_unmap_len_set(tx_buffer, len, 0); 8280 } 8281 } 8282 8283 /* move us one more past the eop_desc for start of next pkt */ 8284 tx_buffer++; 8285 tx_desc++; 8286 i++; 8287 if (unlikely(!i)) { 8288 i -= tx_ring->count; 8289 tx_buffer = tx_ring->tx_buffer_info; 8290 tx_desc = IGB_TX_DESC(tx_ring, 0); 8291 } 8292 8293 /* issue prefetch for next Tx descriptor */ 8294 prefetch(tx_desc); 8295 8296 /* update budget accounting */ 8297 budget--; 8298 } while (likely(budget)); 8299 8300 netdev_tx_completed_queue(txring_txq(tx_ring), 8301 total_packets, total_bytes); 8302 i += tx_ring->count; 8303 tx_ring->next_to_clean = i; 8304 u64_stats_update_begin(&tx_ring->tx_syncp); 8305 tx_ring->tx_stats.bytes += total_bytes; 8306 tx_ring->tx_stats.packets += total_packets; 8307 u64_stats_update_end(&tx_ring->tx_syncp); 8308 q_vector->tx.total_bytes += total_bytes; 8309 q_vector->tx.total_packets += total_packets; 8310 8311 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 8312 struct e1000_hw *hw = &adapter->hw; 8313 8314 /* Detect a transmit hang in hardware, this serializes the 8315 * check with the clearing of time_stamp and movement of i 8316 */ 8317 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 8318 if (tx_buffer->next_to_watch && 8319 time_after(jiffies, tx_buffer->time_stamp + 8320 (adapter->tx_timeout_factor * HZ)) && 8321 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 8322 8323 /* detected Tx unit hang */ 8324 dev_err(tx_ring->dev, 8325 "Detected Tx Unit Hang\n" 8326 " Tx Queue <%d>\n" 8327 " TDH <%x>\n" 8328 " TDT <%x>\n" 8329 " next_to_use <%x>\n" 8330 " next_to_clean <%x>\n" 8331 "buffer_info[next_to_clean]\n" 8332 " time_stamp <%lx>\n" 8333 " next_to_watch <%p>\n" 8334 " jiffies <%lx>\n" 8335 " desc.status <%x>\n", 8336 tx_ring->queue_index, 8337 rd32(E1000_TDH(tx_ring->reg_idx)), 8338 readl(tx_ring->tail), 8339 tx_ring->next_to_use, 8340 tx_ring->next_to_clean, 8341 tx_buffer->time_stamp, 8342 tx_buffer->next_to_watch, 8343 jiffies, 8344 tx_buffer->next_to_watch->wb.status); 8345 netif_stop_subqueue(tx_ring->netdev, 8346 tx_ring->queue_index); 8347 8348 /* we are about to reset, no point in enabling stuff */ 8349 return true; 8350 } 8351 } 8352 8353 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 8354 if (unlikely(total_packets && 8355 netif_carrier_ok(tx_ring->netdev) && 8356 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 8357 /* Make sure that anybody stopping the queue after this 8358 * sees the new next_to_clean. 8359 */ 8360 smp_mb(); 8361 if (__netif_subqueue_stopped(tx_ring->netdev, 8362 tx_ring->queue_index) && 8363 !(test_bit(__IGB_DOWN, &adapter->state))) { 8364 netif_wake_subqueue(tx_ring->netdev, 8365 tx_ring->queue_index); 8366 8367 u64_stats_update_begin(&tx_ring->tx_syncp); 8368 tx_ring->tx_stats.restart_queue++; 8369 u64_stats_update_end(&tx_ring->tx_syncp); 8370 } 8371 } 8372 8373 return !!budget; 8374 } 8375 8376 /** 8377 * igb_reuse_rx_page - page flip buffer and store it back on the ring 8378 * @rx_ring: rx descriptor ring to store buffers on 8379 * @old_buff: donor buffer to have page reused 8380 * 8381 * Synchronizes page for reuse by the adapter 8382 **/ 8383 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 8384 struct igb_rx_buffer *old_buff) 8385 { 8386 struct igb_rx_buffer *new_buff; 8387 u16 nta = rx_ring->next_to_alloc; 8388 8389 new_buff = &rx_ring->rx_buffer_info[nta]; 8390 8391 /* update, and store next to alloc */ 8392 nta++; 8393 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 8394 8395 /* Transfer page from old buffer to new buffer. 8396 * Move each member individually to avoid possible store 8397 * forwarding stalls. 8398 */ 8399 new_buff->dma = old_buff->dma; 8400 new_buff->page = old_buff->page; 8401 new_buff->page_offset = old_buff->page_offset; 8402 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 8403 } 8404 8405 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 8406 int rx_buf_pgcnt) 8407 { 8408 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 8409 struct page *page = rx_buffer->page; 8410 8411 /* avoid re-using remote and pfmemalloc pages */ 8412 if (!dev_page_is_reusable(page)) 8413 return false; 8414 8415 #if (PAGE_SIZE < 8192) 8416 /* if we are only owner of page we can reuse it */ 8417 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1)) 8418 return false; 8419 #else 8420 #define IGB_LAST_OFFSET \ 8421 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 8422 8423 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 8424 return false; 8425 #endif 8426 8427 /* If we have drained the page fragment pool we need to update 8428 * the pagecnt_bias and page count so that we fully restock the 8429 * number of references the driver holds. 8430 */ 8431 if (unlikely(pagecnt_bias == 1)) { 8432 page_ref_add(page, USHRT_MAX - 1); 8433 rx_buffer->pagecnt_bias = USHRT_MAX; 8434 } 8435 8436 return true; 8437 } 8438 8439 /** 8440 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 8441 * @rx_ring: rx descriptor ring to transact packets on 8442 * @rx_buffer: buffer containing page to add 8443 * @skb: sk_buff to place the data into 8444 * @size: size of buffer to be added 8445 * 8446 * This function will add the data contained in rx_buffer->page to the skb. 8447 **/ 8448 static void igb_add_rx_frag(struct igb_ring *rx_ring, 8449 struct igb_rx_buffer *rx_buffer, 8450 struct sk_buff *skb, 8451 unsigned int size) 8452 { 8453 #if (PAGE_SIZE < 8192) 8454 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8455 #else 8456 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8457 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8458 SKB_DATA_ALIGN(size); 8459 #endif 8460 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8461 rx_buffer->page_offset, size, truesize); 8462 #if (PAGE_SIZE < 8192) 8463 rx_buffer->page_offset ^= truesize; 8464 #else 8465 rx_buffer->page_offset += truesize; 8466 #endif 8467 } 8468 8469 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8470 struct igb_rx_buffer *rx_buffer, 8471 struct xdp_buff *xdp, 8472 ktime_t timestamp) 8473 { 8474 #if (PAGE_SIZE < 8192) 8475 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8476 #else 8477 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 8478 xdp->data_hard_start); 8479 #endif 8480 unsigned int size = xdp->data_end - xdp->data; 8481 unsigned int headlen; 8482 struct sk_buff *skb; 8483 8484 /* prefetch first cache line of first page */ 8485 net_prefetch(xdp->data); 8486 8487 /* allocate a skb to store the frags */ 8488 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8489 if (unlikely(!skb)) 8490 return NULL; 8491 8492 if (timestamp) 8493 skb_hwtstamps(skb)->hwtstamp = timestamp; 8494 8495 /* Determine available headroom for copy */ 8496 headlen = size; 8497 if (headlen > IGB_RX_HDR_LEN) 8498 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN); 8499 8500 /* align pull length to size of long to optimize memcpy performance */ 8501 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long))); 8502 8503 /* update all of the pointers */ 8504 size -= headlen; 8505 if (size) { 8506 skb_add_rx_frag(skb, 0, rx_buffer->page, 8507 (xdp->data + headlen) - page_address(rx_buffer->page), 8508 size, truesize); 8509 #if (PAGE_SIZE < 8192) 8510 rx_buffer->page_offset ^= truesize; 8511 #else 8512 rx_buffer->page_offset += truesize; 8513 #endif 8514 } else { 8515 rx_buffer->pagecnt_bias++; 8516 } 8517 8518 return skb; 8519 } 8520 8521 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8522 struct igb_rx_buffer *rx_buffer, 8523 struct xdp_buff *xdp, 8524 ktime_t timestamp) 8525 { 8526 #if (PAGE_SIZE < 8192) 8527 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8528 #else 8529 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8530 SKB_DATA_ALIGN(xdp->data_end - 8531 xdp->data_hard_start); 8532 #endif 8533 unsigned int metasize = xdp->data - xdp->data_meta; 8534 struct sk_buff *skb; 8535 8536 /* prefetch first cache line of first page */ 8537 net_prefetch(xdp->data_meta); 8538 8539 /* build an skb around the page buffer */ 8540 skb = napi_build_skb(xdp->data_hard_start, truesize); 8541 if (unlikely(!skb)) 8542 return NULL; 8543 8544 /* update pointers within the skb to store the data */ 8545 skb_reserve(skb, xdp->data - xdp->data_hard_start); 8546 __skb_put(skb, xdp->data_end - xdp->data); 8547 8548 if (metasize) 8549 skb_metadata_set(skb, metasize); 8550 8551 if (timestamp) 8552 skb_hwtstamps(skb)->hwtstamp = timestamp; 8553 8554 /* update buffer offset */ 8555 #if (PAGE_SIZE < 8192) 8556 rx_buffer->page_offset ^= truesize; 8557 #else 8558 rx_buffer->page_offset += truesize; 8559 #endif 8560 8561 return skb; 8562 } 8563 8564 static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter, 8565 struct igb_ring *rx_ring, 8566 struct xdp_buff *xdp) 8567 { 8568 int err, result = IGB_XDP_PASS; 8569 struct bpf_prog *xdp_prog; 8570 u32 act; 8571 8572 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 8573 8574 if (!xdp_prog) 8575 goto xdp_out; 8576 8577 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 8578 8579 act = bpf_prog_run_xdp(xdp_prog, xdp); 8580 switch (act) { 8581 case XDP_PASS: 8582 break; 8583 case XDP_TX: 8584 result = igb_xdp_xmit_back(adapter, xdp); 8585 if (result == IGB_XDP_CONSUMED) 8586 goto out_failure; 8587 break; 8588 case XDP_REDIRECT: 8589 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 8590 if (err) 8591 goto out_failure; 8592 result = IGB_XDP_REDIR; 8593 break; 8594 default: 8595 bpf_warn_invalid_xdp_action(adapter->netdev, xdp_prog, act); 8596 fallthrough; 8597 case XDP_ABORTED: 8598 out_failure: 8599 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 8600 fallthrough; 8601 case XDP_DROP: 8602 result = IGB_XDP_CONSUMED; 8603 break; 8604 } 8605 xdp_out: 8606 return ERR_PTR(-result); 8607 } 8608 8609 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring, 8610 unsigned int size) 8611 { 8612 unsigned int truesize; 8613 8614 #if (PAGE_SIZE < 8192) 8615 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 8616 #else 8617 truesize = ring_uses_build_skb(rx_ring) ? 8618 SKB_DATA_ALIGN(IGB_SKB_PAD + size) + 8619 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 8620 SKB_DATA_ALIGN(size); 8621 #endif 8622 return truesize; 8623 } 8624 8625 static void igb_rx_buffer_flip(struct igb_ring *rx_ring, 8626 struct igb_rx_buffer *rx_buffer, 8627 unsigned int size) 8628 { 8629 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size); 8630 #if (PAGE_SIZE < 8192) 8631 rx_buffer->page_offset ^= truesize; 8632 #else 8633 rx_buffer->page_offset += truesize; 8634 #endif 8635 } 8636 8637 static inline void igb_rx_checksum(struct igb_ring *ring, 8638 union e1000_adv_rx_desc *rx_desc, 8639 struct sk_buff *skb) 8640 { 8641 skb_checksum_none_assert(skb); 8642 8643 /* Ignore Checksum bit is set */ 8644 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8645 return; 8646 8647 /* Rx checksum disabled via ethtool */ 8648 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8649 return; 8650 8651 /* TCP/UDP checksum error bit is set */ 8652 if (igb_test_staterr(rx_desc, 8653 E1000_RXDEXT_STATERR_TCPE | 8654 E1000_RXDEXT_STATERR_IPE)) { 8655 /* work around errata with sctp packets where the TCPE aka 8656 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8657 * packets, (aka let the stack check the crc32c) 8658 */ 8659 if (!((skb->len == 60) && 8660 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8661 u64_stats_update_begin(&ring->rx_syncp); 8662 ring->rx_stats.csum_err++; 8663 u64_stats_update_end(&ring->rx_syncp); 8664 } 8665 /* let the stack verify checksum errors */ 8666 return; 8667 } 8668 /* It must be a TCP or UDP packet with a valid checksum */ 8669 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8670 E1000_RXD_STAT_UDPCS)) 8671 skb->ip_summed = CHECKSUM_UNNECESSARY; 8672 8673 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8674 le32_to_cpu(rx_desc->wb.upper.status_error)); 8675 } 8676 8677 static inline void igb_rx_hash(struct igb_ring *ring, 8678 union e1000_adv_rx_desc *rx_desc, 8679 struct sk_buff *skb) 8680 { 8681 if (ring->netdev->features & NETIF_F_RXHASH) 8682 skb_set_hash(skb, 8683 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8684 PKT_HASH_TYPE_L3); 8685 } 8686 8687 /** 8688 * igb_is_non_eop - process handling of non-EOP buffers 8689 * @rx_ring: Rx ring being processed 8690 * @rx_desc: Rx descriptor for current buffer 8691 * 8692 * This function updates next to clean. If the buffer is an EOP buffer 8693 * this function exits returning false, otherwise it will place the 8694 * sk_buff in the next buffer to be chained and return true indicating 8695 * that this is in fact a non-EOP buffer. 8696 **/ 8697 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8698 union e1000_adv_rx_desc *rx_desc) 8699 { 8700 u32 ntc = rx_ring->next_to_clean + 1; 8701 8702 /* fetch, update, and store next to clean */ 8703 ntc = (ntc < rx_ring->count) ? ntc : 0; 8704 rx_ring->next_to_clean = ntc; 8705 8706 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8707 8708 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8709 return false; 8710 8711 return true; 8712 } 8713 8714 /** 8715 * igb_cleanup_headers - Correct corrupted or empty headers 8716 * @rx_ring: rx descriptor ring packet is being transacted on 8717 * @rx_desc: pointer to the EOP Rx descriptor 8718 * @skb: pointer to current skb being fixed 8719 * 8720 * Address the case where we are pulling data in on pages only 8721 * and as such no data is present in the skb header. 8722 * 8723 * In addition if skb is not at least 60 bytes we need to pad it so that 8724 * it is large enough to qualify as a valid Ethernet frame. 8725 * 8726 * Returns true if an error was encountered and skb was freed. 8727 **/ 8728 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8729 union e1000_adv_rx_desc *rx_desc, 8730 struct sk_buff *skb) 8731 { 8732 /* XDP packets use error pointer so abort at this point */ 8733 if (IS_ERR(skb)) 8734 return true; 8735 8736 if (unlikely((igb_test_staterr(rx_desc, 8737 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8738 struct net_device *netdev = rx_ring->netdev; 8739 if (!(netdev->features & NETIF_F_RXALL)) { 8740 dev_kfree_skb_any(skb); 8741 return true; 8742 } 8743 } 8744 8745 /* if eth_skb_pad returns an error the skb was freed */ 8746 if (eth_skb_pad(skb)) 8747 return true; 8748 8749 return false; 8750 } 8751 8752 /** 8753 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8754 * @rx_ring: rx descriptor ring packet is being transacted on 8755 * @rx_desc: pointer to the EOP Rx descriptor 8756 * @skb: pointer to current skb being populated 8757 * 8758 * This function checks the ring, descriptor, and packet information in 8759 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8760 * other fields within the skb. 8761 **/ 8762 static void igb_process_skb_fields(struct igb_ring *rx_ring, 8763 union e1000_adv_rx_desc *rx_desc, 8764 struct sk_buff *skb) 8765 { 8766 struct net_device *dev = rx_ring->netdev; 8767 8768 igb_rx_hash(rx_ring, rx_desc, skb); 8769 8770 igb_rx_checksum(rx_ring, rx_desc, skb); 8771 8772 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8773 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8774 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8775 8776 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8777 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8778 u16 vid; 8779 8780 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8781 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8782 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan); 8783 else 8784 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8785 8786 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8787 } 8788 8789 skb_record_rx_queue(skb, rx_ring->queue_index); 8790 8791 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8792 } 8793 8794 static unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8795 { 8796 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8797 } 8798 8799 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8800 const unsigned int size, int *rx_buf_pgcnt) 8801 { 8802 struct igb_rx_buffer *rx_buffer; 8803 8804 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8805 *rx_buf_pgcnt = 8806 #if (PAGE_SIZE < 8192) 8807 page_count(rx_buffer->page); 8808 #else 8809 0; 8810 #endif 8811 prefetchw(rx_buffer->page); 8812 8813 /* we are reusing so sync this buffer for CPU use */ 8814 dma_sync_single_range_for_cpu(rx_ring->dev, 8815 rx_buffer->dma, 8816 rx_buffer->page_offset, 8817 size, 8818 DMA_FROM_DEVICE); 8819 8820 rx_buffer->pagecnt_bias--; 8821 8822 return rx_buffer; 8823 } 8824 8825 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8826 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt) 8827 { 8828 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) { 8829 /* hand second half of page back to the ring */ 8830 igb_reuse_rx_page(rx_ring, rx_buffer); 8831 } else { 8832 /* We are not reusing the buffer so unmap it and free 8833 * any references we are holding to it 8834 */ 8835 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8836 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8837 IGB_RX_DMA_ATTR); 8838 __page_frag_cache_drain(rx_buffer->page, 8839 rx_buffer->pagecnt_bias); 8840 } 8841 8842 /* clear contents of rx_buffer */ 8843 rx_buffer->page = NULL; 8844 } 8845 8846 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 8847 { 8848 struct igb_adapter *adapter = q_vector->adapter; 8849 struct igb_ring *rx_ring = q_vector->rx.ring; 8850 struct sk_buff *skb = rx_ring->skb; 8851 unsigned int total_bytes = 0, total_packets = 0; 8852 u16 cleaned_count = igb_desc_unused(rx_ring); 8853 unsigned int xdp_xmit = 0; 8854 struct xdp_buff xdp; 8855 u32 frame_sz = 0; 8856 int rx_buf_pgcnt; 8857 8858 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 8859 #if (PAGE_SIZE < 8192) 8860 frame_sz = igb_rx_frame_truesize(rx_ring, 0); 8861 #endif 8862 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 8863 8864 while (likely(total_packets < budget)) { 8865 union e1000_adv_rx_desc *rx_desc; 8866 struct igb_rx_buffer *rx_buffer; 8867 ktime_t timestamp = 0; 8868 int pkt_offset = 0; 8869 unsigned int size; 8870 void *pktbuf; 8871 8872 /* return some buffers to hardware, one at a time is too slow */ 8873 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 8874 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8875 cleaned_count = 0; 8876 } 8877 8878 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 8879 size = le16_to_cpu(rx_desc->wb.upper.length); 8880 if (!size) 8881 break; 8882 8883 /* This memory barrier is needed to keep us from reading 8884 * any other fields out of the rx_desc until we know the 8885 * descriptor has been written back 8886 */ 8887 dma_rmb(); 8888 8889 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt); 8890 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset; 8891 8892 /* pull rx packet timestamp if available and valid */ 8893 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 8894 int ts_hdr_len; 8895 8896 ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector, 8897 pktbuf, ×tamp); 8898 8899 pkt_offset += ts_hdr_len; 8900 size -= ts_hdr_len; 8901 } 8902 8903 /* retrieve a buffer from the ring */ 8904 if (!skb) { 8905 unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring); 8906 unsigned int offset = pkt_offset + igb_rx_offset(rx_ring); 8907 8908 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 8909 xdp_buff_clear_frags_flag(&xdp); 8910 #if (PAGE_SIZE > 4096) 8911 /* At larger PAGE_SIZE, frame_sz depend on len size */ 8912 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size); 8913 #endif 8914 skb = igb_run_xdp(adapter, rx_ring, &xdp); 8915 } 8916 8917 if (IS_ERR(skb)) { 8918 unsigned int xdp_res = -PTR_ERR(skb); 8919 8920 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) { 8921 xdp_xmit |= xdp_res; 8922 igb_rx_buffer_flip(rx_ring, rx_buffer, size); 8923 } else { 8924 rx_buffer->pagecnt_bias++; 8925 } 8926 total_packets++; 8927 total_bytes += size; 8928 } else if (skb) 8929 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 8930 else if (ring_uses_build_skb(rx_ring)) 8931 skb = igb_build_skb(rx_ring, rx_buffer, &xdp, 8932 timestamp); 8933 else 8934 skb = igb_construct_skb(rx_ring, rx_buffer, 8935 &xdp, timestamp); 8936 8937 /* exit if we failed to retrieve a buffer */ 8938 if (!skb) { 8939 rx_ring->rx_stats.alloc_failed++; 8940 rx_buffer->pagecnt_bias++; 8941 break; 8942 } 8943 8944 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt); 8945 cleaned_count++; 8946 8947 /* fetch next buffer in frame if non-eop */ 8948 if (igb_is_non_eop(rx_ring, rx_desc)) 8949 continue; 8950 8951 /* verify the packet layout is correct */ 8952 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 8953 skb = NULL; 8954 continue; 8955 } 8956 8957 /* probably a little skewed due to removing CRC */ 8958 total_bytes += skb->len; 8959 8960 /* populate checksum, timestamp, VLAN, and protocol */ 8961 igb_process_skb_fields(rx_ring, rx_desc, skb); 8962 8963 napi_gro_receive(&q_vector->napi, skb); 8964 8965 /* reset skb pointer */ 8966 skb = NULL; 8967 8968 /* update budget accounting */ 8969 total_packets++; 8970 } 8971 8972 /* place incomplete frames back on ring for completion */ 8973 rx_ring->skb = skb; 8974 8975 if (xdp_xmit & IGB_XDP_REDIR) 8976 xdp_do_flush(); 8977 8978 if (xdp_xmit & IGB_XDP_TX) { 8979 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter); 8980 8981 igb_xdp_ring_update_tail(tx_ring); 8982 } 8983 8984 u64_stats_update_begin(&rx_ring->rx_syncp); 8985 rx_ring->rx_stats.packets += total_packets; 8986 rx_ring->rx_stats.bytes += total_bytes; 8987 u64_stats_update_end(&rx_ring->rx_syncp); 8988 q_vector->rx.total_packets += total_packets; 8989 q_vector->rx.total_bytes += total_bytes; 8990 8991 if (cleaned_count) 8992 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8993 8994 return total_packets; 8995 } 8996 8997 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 8998 struct igb_rx_buffer *bi) 8999 { 9000 struct page *page = bi->page; 9001 dma_addr_t dma; 9002 9003 /* since we are recycling buffers we should seldom need to alloc */ 9004 if (likely(page)) 9005 return true; 9006 9007 /* alloc new page for storage */ 9008 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 9009 if (unlikely(!page)) { 9010 rx_ring->rx_stats.alloc_failed++; 9011 return false; 9012 } 9013 9014 /* map page for use */ 9015 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 9016 igb_rx_pg_size(rx_ring), 9017 DMA_FROM_DEVICE, 9018 IGB_RX_DMA_ATTR); 9019 9020 /* if mapping failed free memory back to system since 9021 * there isn't much point in holding memory we can't use 9022 */ 9023 if (dma_mapping_error(rx_ring->dev, dma)) { 9024 __free_pages(page, igb_rx_pg_order(rx_ring)); 9025 9026 rx_ring->rx_stats.alloc_failed++; 9027 return false; 9028 } 9029 9030 bi->dma = dma; 9031 bi->page = page; 9032 bi->page_offset = igb_rx_offset(rx_ring); 9033 page_ref_add(page, USHRT_MAX - 1); 9034 bi->pagecnt_bias = USHRT_MAX; 9035 9036 return true; 9037 } 9038 9039 /** 9040 * igb_alloc_rx_buffers - Replace used receive buffers 9041 * @rx_ring: rx descriptor ring to allocate new receive buffers 9042 * @cleaned_count: count of buffers to allocate 9043 **/ 9044 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 9045 { 9046 union e1000_adv_rx_desc *rx_desc; 9047 struct igb_rx_buffer *bi; 9048 u16 i = rx_ring->next_to_use; 9049 u16 bufsz; 9050 9051 /* nothing to do */ 9052 if (!cleaned_count) 9053 return; 9054 9055 rx_desc = IGB_RX_DESC(rx_ring, i); 9056 bi = &rx_ring->rx_buffer_info[i]; 9057 i -= rx_ring->count; 9058 9059 bufsz = igb_rx_bufsz(rx_ring); 9060 9061 do { 9062 if (!igb_alloc_mapped_page(rx_ring, bi)) 9063 break; 9064 9065 /* sync the buffer for use by the device */ 9066 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 9067 bi->page_offset, bufsz, 9068 DMA_FROM_DEVICE); 9069 9070 /* Refresh the desc even if buffer_addrs didn't change 9071 * because each write-back erases this info. 9072 */ 9073 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 9074 9075 rx_desc++; 9076 bi++; 9077 i++; 9078 if (unlikely(!i)) { 9079 rx_desc = IGB_RX_DESC(rx_ring, 0); 9080 bi = rx_ring->rx_buffer_info; 9081 i -= rx_ring->count; 9082 } 9083 9084 /* clear the length for the next_to_use descriptor */ 9085 rx_desc->wb.upper.length = 0; 9086 9087 cleaned_count--; 9088 } while (cleaned_count); 9089 9090 i += rx_ring->count; 9091 9092 if (rx_ring->next_to_use != i) { 9093 /* record the next descriptor to use */ 9094 rx_ring->next_to_use = i; 9095 9096 /* update next to alloc since we have filled the ring */ 9097 rx_ring->next_to_alloc = i; 9098 9099 /* Force memory writes to complete before letting h/w 9100 * know there are new descriptors to fetch. (Only 9101 * applicable for weak-ordered memory model archs, 9102 * such as IA-64). 9103 */ 9104 dma_wmb(); 9105 writel(i, rx_ring->tail); 9106 } 9107 } 9108 9109 /** 9110 * igb_mii_ioctl - 9111 * @netdev: pointer to netdev struct 9112 * @ifr: interface structure 9113 * @cmd: ioctl command to execute 9114 **/ 9115 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9116 { 9117 struct igb_adapter *adapter = netdev_priv(netdev); 9118 struct mii_ioctl_data *data = if_mii(ifr); 9119 9120 if (adapter->hw.phy.media_type != e1000_media_type_copper) 9121 return -EOPNOTSUPP; 9122 9123 switch (cmd) { 9124 case SIOCGMIIPHY: 9125 data->phy_id = adapter->hw.phy.addr; 9126 break; 9127 case SIOCGMIIREG: 9128 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9129 &data->val_out)) 9130 return -EIO; 9131 break; 9132 case SIOCSMIIREG: 9133 default: 9134 return -EOPNOTSUPP; 9135 } 9136 return 0; 9137 } 9138 9139 /** 9140 * igb_ioctl - 9141 * @netdev: pointer to netdev struct 9142 * @ifr: interface structure 9143 * @cmd: ioctl command to execute 9144 **/ 9145 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9146 { 9147 switch (cmd) { 9148 case SIOCGMIIPHY: 9149 case SIOCGMIIREG: 9150 case SIOCSMIIREG: 9151 return igb_mii_ioctl(netdev, ifr, cmd); 9152 case SIOCGHWTSTAMP: 9153 return igb_ptp_get_ts_config(netdev, ifr); 9154 case SIOCSHWTSTAMP: 9155 return igb_ptp_set_ts_config(netdev, ifr); 9156 default: 9157 return -EOPNOTSUPP; 9158 } 9159 } 9160 9161 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9162 { 9163 struct igb_adapter *adapter = hw->back; 9164 9165 pci_read_config_word(adapter->pdev, reg, value); 9166 } 9167 9168 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9169 { 9170 struct igb_adapter *adapter = hw->back; 9171 9172 pci_write_config_word(adapter->pdev, reg, *value); 9173 } 9174 9175 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9176 { 9177 struct igb_adapter *adapter = hw->back; 9178 9179 if (pcie_capability_read_word(adapter->pdev, reg, value)) 9180 return -E1000_ERR_CONFIG; 9181 9182 return 0; 9183 } 9184 9185 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9186 { 9187 struct igb_adapter *adapter = hw->back; 9188 9189 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 9190 return -E1000_ERR_CONFIG; 9191 9192 return 0; 9193 } 9194 9195 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 9196 { 9197 struct igb_adapter *adapter = netdev_priv(netdev); 9198 struct e1000_hw *hw = &adapter->hw; 9199 u32 ctrl, rctl; 9200 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 9201 9202 if (enable) { 9203 /* enable VLAN tag insert/strip */ 9204 ctrl = rd32(E1000_CTRL); 9205 ctrl |= E1000_CTRL_VME; 9206 wr32(E1000_CTRL, ctrl); 9207 9208 /* Disable CFI check */ 9209 rctl = rd32(E1000_RCTL); 9210 rctl &= ~E1000_RCTL_CFIEN; 9211 wr32(E1000_RCTL, rctl); 9212 } else { 9213 /* disable VLAN tag insert/strip */ 9214 ctrl = rd32(E1000_CTRL); 9215 ctrl &= ~E1000_CTRL_VME; 9216 wr32(E1000_CTRL, ctrl); 9217 } 9218 9219 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 9220 } 9221 9222 static int igb_vlan_rx_add_vid(struct net_device *netdev, 9223 __be16 proto, u16 vid) 9224 { 9225 struct igb_adapter *adapter = netdev_priv(netdev); 9226 struct e1000_hw *hw = &adapter->hw; 9227 int pf_id = adapter->vfs_allocated_count; 9228 9229 /* add the filter since PF can receive vlans w/o entry in vlvf */ 9230 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9231 igb_vfta_set(hw, vid, pf_id, true, !!vid); 9232 9233 set_bit(vid, adapter->active_vlans); 9234 9235 return 0; 9236 } 9237 9238 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 9239 __be16 proto, u16 vid) 9240 { 9241 struct igb_adapter *adapter = netdev_priv(netdev); 9242 int pf_id = adapter->vfs_allocated_count; 9243 struct e1000_hw *hw = &adapter->hw; 9244 9245 /* remove VID from filter table */ 9246 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9247 igb_vfta_set(hw, vid, pf_id, false, true); 9248 9249 clear_bit(vid, adapter->active_vlans); 9250 9251 return 0; 9252 } 9253 9254 static void igb_restore_vlan(struct igb_adapter *adapter) 9255 { 9256 u16 vid = 1; 9257 9258 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 9259 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 9260 9261 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 9262 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 9263 } 9264 9265 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 9266 { 9267 struct pci_dev *pdev = adapter->pdev; 9268 struct e1000_mac_info *mac = &adapter->hw.mac; 9269 9270 mac->autoneg = 0; 9271 9272 /* Make sure dplx is at most 1 bit and lsb of speed is not set 9273 * for the switch() below to work 9274 */ 9275 if ((spd & 1) || (dplx & ~1)) 9276 goto err_inval; 9277 9278 /* Fiber NIC's only allow 1000 gbps Full duplex 9279 * and 100Mbps Full duplex for 100baseFx sfp 9280 */ 9281 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 9282 switch (spd + dplx) { 9283 case SPEED_10 + DUPLEX_HALF: 9284 case SPEED_10 + DUPLEX_FULL: 9285 case SPEED_100 + DUPLEX_HALF: 9286 goto err_inval; 9287 default: 9288 break; 9289 } 9290 } 9291 9292 switch (spd + dplx) { 9293 case SPEED_10 + DUPLEX_HALF: 9294 mac->forced_speed_duplex = ADVERTISE_10_HALF; 9295 break; 9296 case SPEED_10 + DUPLEX_FULL: 9297 mac->forced_speed_duplex = ADVERTISE_10_FULL; 9298 break; 9299 case SPEED_100 + DUPLEX_HALF: 9300 mac->forced_speed_duplex = ADVERTISE_100_HALF; 9301 break; 9302 case SPEED_100 + DUPLEX_FULL: 9303 mac->forced_speed_duplex = ADVERTISE_100_FULL; 9304 break; 9305 case SPEED_1000 + DUPLEX_FULL: 9306 mac->autoneg = 1; 9307 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 9308 break; 9309 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 9310 default: 9311 goto err_inval; 9312 } 9313 9314 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 9315 adapter->hw.phy.mdix = AUTO_ALL_MODES; 9316 9317 return 0; 9318 9319 err_inval: 9320 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 9321 return -EINVAL; 9322 } 9323 9324 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 9325 bool runtime) 9326 { 9327 struct net_device *netdev = pci_get_drvdata(pdev); 9328 struct igb_adapter *adapter = netdev_priv(netdev); 9329 struct e1000_hw *hw = &adapter->hw; 9330 u32 ctrl, rctl, status; 9331 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 9332 bool wake; 9333 9334 rtnl_lock(); 9335 netif_device_detach(netdev); 9336 9337 if (netif_running(netdev)) 9338 __igb_close(netdev, true); 9339 9340 igb_ptp_suspend(adapter); 9341 9342 igb_clear_interrupt_scheme(adapter); 9343 rtnl_unlock(); 9344 9345 status = rd32(E1000_STATUS); 9346 if (status & E1000_STATUS_LU) 9347 wufc &= ~E1000_WUFC_LNKC; 9348 9349 if (wufc) { 9350 igb_setup_rctl(adapter); 9351 igb_set_rx_mode(netdev); 9352 9353 /* turn on all-multi mode if wake on multicast is enabled */ 9354 if (wufc & E1000_WUFC_MC) { 9355 rctl = rd32(E1000_RCTL); 9356 rctl |= E1000_RCTL_MPE; 9357 wr32(E1000_RCTL, rctl); 9358 } 9359 9360 ctrl = rd32(E1000_CTRL); 9361 ctrl |= E1000_CTRL_ADVD3WUC; 9362 wr32(E1000_CTRL, ctrl); 9363 9364 /* Allow time for pending master requests to run */ 9365 igb_disable_pcie_master(hw); 9366 9367 wr32(E1000_WUC, E1000_WUC_PME_EN); 9368 wr32(E1000_WUFC, wufc); 9369 } else { 9370 wr32(E1000_WUC, 0); 9371 wr32(E1000_WUFC, 0); 9372 } 9373 9374 wake = wufc || adapter->en_mng_pt; 9375 if (!wake) 9376 igb_power_down_link(adapter); 9377 else 9378 igb_power_up_link(adapter); 9379 9380 if (enable_wake) 9381 *enable_wake = wake; 9382 9383 /* Release control of h/w to f/w. If f/w is AMT enabled, this 9384 * would have already happened in close and is redundant. 9385 */ 9386 igb_release_hw_control(adapter); 9387 9388 pci_disable_device(pdev); 9389 9390 return 0; 9391 } 9392 9393 static void igb_deliver_wake_packet(struct net_device *netdev) 9394 { 9395 struct igb_adapter *adapter = netdev_priv(netdev); 9396 struct e1000_hw *hw = &adapter->hw; 9397 struct sk_buff *skb; 9398 u32 wupl; 9399 9400 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 9401 9402 /* WUPM stores only the first 128 bytes of the wake packet. 9403 * Read the packet only if we have the whole thing. 9404 */ 9405 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 9406 return; 9407 9408 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 9409 if (!skb) 9410 return; 9411 9412 skb_put(skb, wupl); 9413 9414 /* Ensure reads are 32-bit aligned */ 9415 wupl = roundup(wupl, 4); 9416 9417 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 9418 9419 skb->protocol = eth_type_trans(skb, netdev); 9420 netif_rx(skb); 9421 } 9422 9423 static int __maybe_unused igb_suspend(struct device *dev) 9424 { 9425 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 9426 } 9427 9428 static int __maybe_unused __igb_resume(struct device *dev, bool rpm) 9429 { 9430 struct pci_dev *pdev = to_pci_dev(dev); 9431 struct net_device *netdev = pci_get_drvdata(pdev); 9432 struct igb_adapter *adapter = netdev_priv(netdev); 9433 struct e1000_hw *hw = &adapter->hw; 9434 u32 err, val; 9435 9436 pci_set_power_state(pdev, PCI_D0); 9437 pci_restore_state(pdev); 9438 pci_save_state(pdev); 9439 9440 if (!pci_device_is_present(pdev)) 9441 return -ENODEV; 9442 err = pci_enable_device_mem(pdev); 9443 if (err) { 9444 dev_err(&pdev->dev, 9445 "igb: Cannot enable PCI device from suspend\n"); 9446 return err; 9447 } 9448 pci_set_master(pdev); 9449 9450 pci_enable_wake(pdev, PCI_D3hot, 0); 9451 pci_enable_wake(pdev, PCI_D3cold, 0); 9452 9453 if (igb_init_interrupt_scheme(adapter, true)) { 9454 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9455 return -ENOMEM; 9456 } 9457 9458 igb_reset(adapter); 9459 9460 /* let the f/w know that the h/w is now under the control of the 9461 * driver. 9462 */ 9463 igb_get_hw_control(adapter); 9464 9465 val = rd32(E1000_WUS); 9466 if (val & WAKE_PKT_WUS) 9467 igb_deliver_wake_packet(netdev); 9468 9469 wr32(E1000_WUS, ~0); 9470 9471 if (!rpm) 9472 rtnl_lock(); 9473 if (!err && netif_running(netdev)) 9474 err = __igb_open(netdev, true); 9475 9476 if (!err) 9477 netif_device_attach(netdev); 9478 if (!rpm) 9479 rtnl_unlock(); 9480 9481 return err; 9482 } 9483 9484 static int __maybe_unused igb_resume(struct device *dev) 9485 { 9486 return __igb_resume(dev, false); 9487 } 9488 9489 static int __maybe_unused igb_runtime_idle(struct device *dev) 9490 { 9491 struct net_device *netdev = dev_get_drvdata(dev); 9492 struct igb_adapter *adapter = netdev_priv(netdev); 9493 9494 if (!igb_has_link(adapter)) 9495 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 9496 9497 return -EBUSY; 9498 } 9499 9500 static int __maybe_unused igb_runtime_suspend(struct device *dev) 9501 { 9502 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 9503 } 9504 9505 static int __maybe_unused igb_runtime_resume(struct device *dev) 9506 { 9507 return __igb_resume(dev, true); 9508 } 9509 9510 static void igb_shutdown(struct pci_dev *pdev) 9511 { 9512 bool wake; 9513 9514 __igb_shutdown(pdev, &wake, 0); 9515 9516 if (system_state == SYSTEM_POWER_OFF) { 9517 pci_wake_from_d3(pdev, wake); 9518 pci_set_power_state(pdev, PCI_D3hot); 9519 } 9520 } 9521 9522 #ifdef CONFIG_PCI_IOV 9523 static int igb_sriov_reinit(struct pci_dev *dev) 9524 { 9525 struct net_device *netdev = pci_get_drvdata(dev); 9526 struct igb_adapter *adapter = netdev_priv(netdev); 9527 struct pci_dev *pdev = adapter->pdev; 9528 9529 rtnl_lock(); 9530 9531 if (netif_running(netdev)) 9532 igb_close(netdev); 9533 else 9534 igb_reset(adapter); 9535 9536 igb_clear_interrupt_scheme(adapter); 9537 9538 igb_init_queue_configuration(adapter); 9539 9540 if (igb_init_interrupt_scheme(adapter, true)) { 9541 rtnl_unlock(); 9542 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9543 return -ENOMEM; 9544 } 9545 9546 if (netif_running(netdev)) 9547 igb_open(netdev); 9548 9549 rtnl_unlock(); 9550 9551 return 0; 9552 } 9553 9554 static int igb_pci_disable_sriov(struct pci_dev *dev) 9555 { 9556 int err = igb_disable_sriov(dev); 9557 9558 if (!err) 9559 err = igb_sriov_reinit(dev); 9560 9561 return err; 9562 } 9563 9564 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 9565 { 9566 int err = igb_enable_sriov(dev, num_vfs); 9567 9568 if (err) 9569 goto out; 9570 9571 err = igb_sriov_reinit(dev); 9572 if (!err) 9573 return num_vfs; 9574 9575 out: 9576 return err; 9577 } 9578 9579 #endif 9580 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 9581 { 9582 #ifdef CONFIG_PCI_IOV 9583 if (num_vfs == 0) 9584 return igb_pci_disable_sriov(dev); 9585 else 9586 return igb_pci_enable_sriov(dev, num_vfs); 9587 #endif 9588 return 0; 9589 } 9590 9591 /** 9592 * igb_io_error_detected - called when PCI error is detected 9593 * @pdev: Pointer to PCI device 9594 * @state: The current pci connection state 9595 * 9596 * This function is called after a PCI bus error affecting 9597 * this device has been detected. 9598 **/ 9599 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9600 pci_channel_state_t state) 9601 { 9602 struct net_device *netdev = pci_get_drvdata(pdev); 9603 struct igb_adapter *adapter = netdev_priv(netdev); 9604 9605 netif_device_detach(netdev); 9606 9607 if (state == pci_channel_io_perm_failure) 9608 return PCI_ERS_RESULT_DISCONNECT; 9609 9610 if (netif_running(netdev)) 9611 igb_down(adapter); 9612 pci_disable_device(pdev); 9613 9614 /* Request a slot reset. */ 9615 return PCI_ERS_RESULT_NEED_RESET; 9616 } 9617 9618 /** 9619 * igb_io_slot_reset - called after the pci bus has been reset. 9620 * @pdev: Pointer to PCI device 9621 * 9622 * Restart the card from scratch, as if from a cold-boot. Implementation 9623 * resembles the first-half of the __igb_resume routine. 9624 **/ 9625 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9626 { 9627 struct net_device *netdev = pci_get_drvdata(pdev); 9628 struct igb_adapter *adapter = netdev_priv(netdev); 9629 struct e1000_hw *hw = &adapter->hw; 9630 pci_ers_result_t result; 9631 9632 if (pci_enable_device_mem(pdev)) { 9633 dev_err(&pdev->dev, 9634 "Cannot re-enable PCI device after reset.\n"); 9635 result = PCI_ERS_RESULT_DISCONNECT; 9636 } else { 9637 pci_set_master(pdev); 9638 pci_restore_state(pdev); 9639 pci_save_state(pdev); 9640 9641 pci_enable_wake(pdev, PCI_D3hot, 0); 9642 pci_enable_wake(pdev, PCI_D3cold, 0); 9643 9644 /* In case of PCI error, adapter lose its HW address 9645 * so we should re-assign it here. 9646 */ 9647 hw->hw_addr = adapter->io_addr; 9648 9649 igb_reset(adapter); 9650 wr32(E1000_WUS, ~0); 9651 result = PCI_ERS_RESULT_RECOVERED; 9652 } 9653 9654 return result; 9655 } 9656 9657 /** 9658 * igb_io_resume - called when traffic can start flowing again. 9659 * @pdev: Pointer to PCI device 9660 * 9661 * This callback is called when the error recovery driver tells us that 9662 * its OK to resume normal operation. Implementation resembles the 9663 * second-half of the __igb_resume routine. 9664 */ 9665 static void igb_io_resume(struct pci_dev *pdev) 9666 { 9667 struct net_device *netdev = pci_get_drvdata(pdev); 9668 struct igb_adapter *adapter = netdev_priv(netdev); 9669 9670 if (netif_running(netdev)) { 9671 if (igb_up(adapter)) { 9672 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9673 return; 9674 } 9675 } 9676 9677 netif_device_attach(netdev); 9678 9679 /* let the f/w know that the h/w is now under the control of the 9680 * driver. 9681 */ 9682 igb_get_hw_control(adapter); 9683 } 9684 9685 /** 9686 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9687 * @adapter: Pointer to adapter structure 9688 * @index: Index of the RAR entry which need to be synced with MAC table 9689 **/ 9690 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9691 { 9692 struct e1000_hw *hw = &adapter->hw; 9693 u32 rar_low, rar_high; 9694 u8 *addr = adapter->mac_table[index].addr; 9695 9696 /* HW expects these to be in network order when they are plugged 9697 * into the registers which are little endian. In order to guarantee 9698 * that ordering we need to do an leXX_to_cpup here in order to be 9699 * ready for the byteswap that occurs with writel 9700 */ 9701 rar_low = le32_to_cpup((__le32 *)(addr)); 9702 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9703 9704 /* Indicate to hardware the Address is Valid. */ 9705 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9706 if (is_valid_ether_addr(addr)) 9707 rar_high |= E1000_RAH_AV; 9708 9709 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9710 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9711 9712 switch (hw->mac.type) { 9713 case e1000_82575: 9714 case e1000_i210: 9715 if (adapter->mac_table[index].state & 9716 IGB_MAC_STATE_QUEUE_STEERING) 9717 rar_high |= E1000_RAH_QSEL_ENABLE; 9718 9719 rar_high |= E1000_RAH_POOL_1 * 9720 adapter->mac_table[index].queue; 9721 break; 9722 default: 9723 rar_high |= E1000_RAH_POOL_1 << 9724 adapter->mac_table[index].queue; 9725 break; 9726 } 9727 } 9728 9729 wr32(E1000_RAL(index), rar_low); 9730 wrfl(); 9731 wr32(E1000_RAH(index), rar_high); 9732 wrfl(); 9733 } 9734 9735 static int igb_set_vf_mac(struct igb_adapter *adapter, 9736 int vf, unsigned char *mac_addr) 9737 { 9738 struct e1000_hw *hw = &adapter->hw; 9739 /* VF MAC addresses start at end of receive addresses and moves 9740 * towards the first, as a result a collision should not be possible 9741 */ 9742 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9743 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9744 9745 ether_addr_copy(vf_mac_addr, mac_addr); 9746 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9747 adapter->mac_table[rar_entry].queue = vf; 9748 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9749 igb_rar_set_index(adapter, rar_entry); 9750 9751 return 0; 9752 } 9753 9754 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9755 { 9756 struct igb_adapter *adapter = netdev_priv(netdev); 9757 9758 if (vf >= adapter->vfs_allocated_count) 9759 return -EINVAL; 9760 9761 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9762 * flag and allows to overwrite the MAC via VF netdev. This 9763 * is necessary to allow libvirt a way to restore the original 9764 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9765 * down a VM. 9766 */ 9767 if (is_zero_ether_addr(mac)) { 9768 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9769 dev_info(&adapter->pdev->dev, 9770 "remove administratively set MAC on VF %d\n", 9771 vf); 9772 } else if (is_valid_ether_addr(mac)) { 9773 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9774 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9775 mac, vf); 9776 dev_info(&adapter->pdev->dev, 9777 "Reload the VF driver to make this change effective."); 9778 /* Generate additional warning if PF is down */ 9779 if (test_bit(__IGB_DOWN, &adapter->state)) { 9780 dev_warn(&adapter->pdev->dev, 9781 "The VF MAC address has been set, but the PF device is not up.\n"); 9782 dev_warn(&adapter->pdev->dev, 9783 "Bring the PF device up before attempting to use the VF device.\n"); 9784 } 9785 } else { 9786 return -EINVAL; 9787 } 9788 return igb_set_vf_mac(adapter, vf, mac); 9789 } 9790 9791 static int igb_link_mbps(int internal_link_speed) 9792 { 9793 switch (internal_link_speed) { 9794 case SPEED_100: 9795 return 100; 9796 case SPEED_1000: 9797 return 1000; 9798 default: 9799 return 0; 9800 } 9801 } 9802 9803 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9804 int link_speed) 9805 { 9806 int rf_dec, rf_int; 9807 u32 bcnrc_val; 9808 9809 if (tx_rate != 0) { 9810 /* Calculate the rate factor values to set */ 9811 rf_int = link_speed / tx_rate; 9812 rf_dec = (link_speed - (rf_int * tx_rate)); 9813 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9814 tx_rate; 9815 9816 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9817 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 9818 E1000_RTTBCNRC_RF_INT_MASK); 9819 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9820 } else { 9821 bcnrc_val = 0; 9822 } 9823 9824 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9825 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9826 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9827 */ 9828 wr32(E1000_RTTBCNRM, 0x14); 9829 wr32(E1000_RTTBCNRC, bcnrc_val); 9830 } 9831 9832 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9833 { 9834 int actual_link_speed, i; 9835 bool reset_rate = false; 9836 9837 /* VF TX rate limit was not set or not supported */ 9838 if ((adapter->vf_rate_link_speed == 0) || 9839 (adapter->hw.mac.type != e1000_82576)) 9840 return; 9841 9842 actual_link_speed = igb_link_mbps(adapter->link_speed); 9843 if (actual_link_speed != adapter->vf_rate_link_speed) { 9844 reset_rate = true; 9845 adapter->vf_rate_link_speed = 0; 9846 dev_info(&adapter->pdev->dev, 9847 "Link speed has been changed. VF Transmit rate is disabled\n"); 9848 } 9849 9850 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9851 if (reset_rate) 9852 adapter->vf_data[i].tx_rate = 0; 9853 9854 igb_set_vf_rate_limit(&adapter->hw, i, 9855 adapter->vf_data[i].tx_rate, 9856 actual_link_speed); 9857 } 9858 } 9859 9860 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9861 int min_tx_rate, int max_tx_rate) 9862 { 9863 struct igb_adapter *adapter = netdev_priv(netdev); 9864 struct e1000_hw *hw = &adapter->hw; 9865 int actual_link_speed; 9866 9867 if (hw->mac.type != e1000_82576) 9868 return -EOPNOTSUPP; 9869 9870 if (min_tx_rate) 9871 return -EINVAL; 9872 9873 actual_link_speed = igb_link_mbps(adapter->link_speed); 9874 if ((vf >= adapter->vfs_allocated_count) || 9875 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9876 (max_tx_rate < 0) || 9877 (max_tx_rate > actual_link_speed)) 9878 return -EINVAL; 9879 9880 adapter->vf_rate_link_speed = actual_link_speed; 9881 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 9882 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 9883 9884 return 0; 9885 } 9886 9887 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 9888 bool setting) 9889 { 9890 struct igb_adapter *adapter = netdev_priv(netdev); 9891 struct e1000_hw *hw = &adapter->hw; 9892 u32 reg_val, reg_offset; 9893 9894 if (!adapter->vfs_allocated_count) 9895 return -EOPNOTSUPP; 9896 9897 if (vf >= adapter->vfs_allocated_count) 9898 return -EINVAL; 9899 9900 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 9901 reg_val = rd32(reg_offset); 9902 if (setting) 9903 reg_val |= (BIT(vf) | 9904 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9905 else 9906 reg_val &= ~(BIT(vf) | 9907 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9908 wr32(reg_offset, reg_val); 9909 9910 adapter->vf_data[vf].spoofchk_enabled = setting; 9911 return 0; 9912 } 9913 9914 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 9915 { 9916 struct igb_adapter *adapter = netdev_priv(netdev); 9917 9918 if (vf >= adapter->vfs_allocated_count) 9919 return -EINVAL; 9920 if (adapter->vf_data[vf].trusted == setting) 9921 return 0; 9922 9923 adapter->vf_data[vf].trusted = setting; 9924 9925 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 9926 vf, setting ? "" : "not "); 9927 return 0; 9928 } 9929 9930 static int igb_ndo_get_vf_config(struct net_device *netdev, 9931 int vf, struct ifla_vf_info *ivi) 9932 { 9933 struct igb_adapter *adapter = netdev_priv(netdev); 9934 if (vf >= adapter->vfs_allocated_count) 9935 return -EINVAL; 9936 ivi->vf = vf; 9937 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 9938 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 9939 ivi->min_tx_rate = 0; 9940 ivi->vlan = adapter->vf_data[vf].pf_vlan; 9941 ivi->qos = adapter->vf_data[vf].pf_qos; 9942 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 9943 ivi->trusted = adapter->vf_data[vf].trusted; 9944 return 0; 9945 } 9946 9947 static void igb_vmm_control(struct igb_adapter *adapter) 9948 { 9949 struct e1000_hw *hw = &adapter->hw; 9950 u32 reg; 9951 9952 switch (hw->mac.type) { 9953 case e1000_82575: 9954 case e1000_i210: 9955 case e1000_i211: 9956 case e1000_i354: 9957 default: 9958 /* replication is not supported for 82575 */ 9959 return; 9960 case e1000_82576: 9961 /* notify HW that the MAC is adding vlan tags */ 9962 reg = rd32(E1000_DTXCTL); 9963 reg |= E1000_DTXCTL_VLAN_ADDED; 9964 wr32(E1000_DTXCTL, reg); 9965 fallthrough; 9966 case e1000_82580: 9967 /* enable replication vlan tag stripping */ 9968 reg = rd32(E1000_RPLOLR); 9969 reg |= E1000_RPLOLR_STRVLAN; 9970 wr32(E1000_RPLOLR, reg); 9971 fallthrough; 9972 case e1000_i350: 9973 /* none of the above registers are supported by i350 */ 9974 break; 9975 } 9976 9977 if (adapter->vfs_allocated_count) { 9978 igb_vmdq_set_loopback_pf(hw, true); 9979 igb_vmdq_set_replication_pf(hw, true); 9980 igb_vmdq_set_anti_spoofing_pf(hw, true, 9981 adapter->vfs_allocated_count); 9982 } else { 9983 igb_vmdq_set_loopback_pf(hw, false); 9984 igb_vmdq_set_replication_pf(hw, false); 9985 } 9986 } 9987 9988 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 9989 { 9990 struct e1000_hw *hw = &adapter->hw; 9991 u32 dmac_thr; 9992 u16 hwm; 9993 u32 reg; 9994 9995 if (hw->mac.type > e1000_82580) { 9996 if (adapter->flags & IGB_FLAG_DMAC) { 9997 /* force threshold to 0. */ 9998 wr32(E1000_DMCTXTH, 0); 9999 10000 /* DMA Coalescing high water mark needs to be greater 10001 * than the Rx threshold. Set hwm to PBA - max frame 10002 * size in 16B units, capping it at PBA - 6KB. 10003 */ 10004 hwm = 64 * (pba - 6); 10005 reg = rd32(E1000_FCRTC); 10006 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 10007 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 10008 & E1000_FCRTC_RTH_COAL_MASK); 10009 wr32(E1000_FCRTC, reg); 10010 10011 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 10012 * frame size, capping it at PBA - 10KB. 10013 */ 10014 dmac_thr = pba - 10; 10015 reg = rd32(E1000_DMACR); 10016 reg &= ~E1000_DMACR_DMACTHR_MASK; 10017 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 10018 & E1000_DMACR_DMACTHR_MASK); 10019 10020 /* transition to L0x or L1 if available..*/ 10021 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 10022 10023 /* watchdog timer= +-1000 usec in 32usec intervals */ 10024 reg |= (1000 >> 5); 10025 10026 /* Disable BMC-to-OS Watchdog Enable */ 10027 if (hw->mac.type != e1000_i354) 10028 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 10029 wr32(E1000_DMACR, reg); 10030 10031 /* no lower threshold to disable 10032 * coalescing(smart fifb)-UTRESH=0 10033 */ 10034 wr32(E1000_DMCRTRH, 0); 10035 10036 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 10037 10038 wr32(E1000_DMCTLX, reg); 10039 10040 /* free space in tx packet buffer to wake from 10041 * DMA coal 10042 */ 10043 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 10044 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 10045 } 10046 10047 if (hw->mac.type >= e1000_i210 || 10048 (adapter->flags & IGB_FLAG_DMAC)) { 10049 reg = rd32(E1000_PCIEMISC); 10050 reg |= E1000_PCIEMISC_LX_DECISION; 10051 wr32(E1000_PCIEMISC, reg); 10052 } /* endif adapter->dmac is not disabled */ 10053 } else if (hw->mac.type == e1000_82580) { 10054 u32 reg = rd32(E1000_PCIEMISC); 10055 10056 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 10057 wr32(E1000_DMACR, 0); 10058 } 10059 } 10060 10061 /** 10062 * igb_read_i2c_byte - Reads 8 bit word over I2C 10063 * @hw: pointer to hardware structure 10064 * @byte_offset: byte offset to read 10065 * @dev_addr: device address 10066 * @data: value read 10067 * 10068 * Performs byte read operation over I2C interface at 10069 * a specified device address. 10070 **/ 10071 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10072 u8 dev_addr, u8 *data) 10073 { 10074 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10075 struct i2c_client *this_client = adapter->i2c_client; 10076 s32 status; 10077 u16 swfw_mask = 0; 10078 10079 if (!this_client) 10080 return E1000_ERR_I2C; 10081 10082 swfw_mask = E1000_SWFW_PHY0_SM; 10083 10084 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10085 return E1000_ERR_SWFW_SYNC; 10086 10087 status = i2c_smbus_read_byte_data(this_client, byte_offset); 10088 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10089 10090 if (status < 0) 10091 return E1000_ERR_I2C; 10092 else { 10093 *data = status; 10094 return 0; 10095 } 10096 } 10097 10098 /** 10099 * igb_write_i2c_byte - Writes 8 bit word over I2C 10100 * @hw: pointer to hardware structure 10101 * @byte_offset: byte offset to write 10102 * @dev_addr: device address 10103 * @data: value to write 10104 * 10105 * Performs byte write operation over I2C interface at 10106 * a specified device address. 10107 **/ 10108 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10109 u8 dev_addr, u8 data) 10110 { 10111 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10112 struct i2c_client *this_client = adapter->i2c_client; 10113 s32 status; 10114 u16 swfw_mask = E1000_SWFW_PHY0_SM; 10115 10116 if (!this_client) 10117 return E1000_ERR_I2C; 10118 10119 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10120 return E1000_ERR_SWFW_SYNC; 10121 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 10122 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10123 10124 if (status) 10125 return E1000_ERR_I2C; 10126 else 10127 return 0; 10128 10129 } 10130 10131 int igb_reinit_queues(struct igb_adapter *adapter) 10132 { 10133 struct net_device *netdev = adapter->netdev; 10134 struct pci_dev *pdev = adapter->pdev; 10135 int err = 0; 10136 10137 if (netif_running(netdev)) 10138 igb_close(netdev); 10139 10140 igb_reset_interrupt_capability(adapter); 10141 10142 if (igb_init_interrupt_scheme(adapter, true)) { 10143 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 10144 return -ENOMEM; 10145 } 10146 10147 if (netif_running(netdev)) 10148 err = igb_open(netdev); 10149 10150 return err; 10151 } 10152 10153 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 10154 { 10155 struct igb_nfc_filter *rule; 10156 10157 spin_lock(&adapter->nfc_lock); 10158 10159 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10160 igb_erase_filter(adapter, rule); 10161 10162 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 10163 igb_erase_filter(adapter, rule); 10164 10165 spin_unlock(&adapter->nfc_lock); 10166 } 10167 10168 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 10169 { 10170 struct igb_nfc_filter *rule; 10171 10172 spin_lock(&adapter->nfc_lock); 10173 10174 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10175 igb_add_filter(adapter, rule); 10176 10177 spin_unlock(&adapter->nfc_lock); 10178 } 10179 /* igb_main.c */ 10180