1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/sctp.h> 30 #include <linux/if_ether.h> 31 #include <linux/aer.h> 32 #include <linux/prefetch.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/etherdevice.h> 35 #ifdef CONFIG_IGB_DCA 36 #include <linux/dca.h> 37 #endif 38 #include <linux/i2c.h> 39 #include "igb.h" 40 41 enum queue_mode { 42 QUEUE_MODE_STRICT_PRIORITY, 43 QUEUE_MODE_STREAM_RESERVATION, 44 }; 45 46 enum tx_queue_prio { 47 TX_QUEUE_PRIO_HIGH, 48 TX_QUEUE_PRIO_LOW, 49 }; 50 51 char igb_driver_name[] = "igb"; 52 static const char igb_driver_string[] = 53 "Intel(R) Gigabit Ethernet Network Driver"; 54 static const char igb_copyright[] = 55 "Copyright (c) 2007-2014 Intel Corporation."; 56 57 static const struct e1000_info *igb_info_tbl[] = { 58 [board_82575] = &e1000_82575_info, 59 }; 60 61 static const struct pci_device_id igb_pci_tbl[] = { 62 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 97 /* required last entry */ 98 {0, } 99 }; 100 101 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 102 103 static int igb_setup_all_tx_resources(struct igb_adapter *); 104 static int igb_setup_all_rx_resources(struct igb_adapter *); 105 static void igb_free_all_tx_resources(struct igb_adapter *); 106 static void igb_free_all_rx_resources(struct igb_adapter *); 107 static void igb_setup_mrqc(struct igb_adapter *); 108 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 109 static void igb_remove(struct pci_dev *pdev); 110 static int igb_sw_init(struct igb_adapter *); 111 int igb_open(struct net_device *); 112 int igb_close(struct net_device *); 113 static void igb_configure(struct igb_adapter *); 114 static void igb_configure_tx(struct igb_adapter *); 115 static void igb_configure_rx(struct igb_adapter *); 116 static void igb_clean_all_tx_rings(struct igb_adapter *); 117 static void igb_clean_all_rx_rings(struct igb_adapter *); 118 static void igb_clean_tx_ring(struct igb_ring *); 119 static void igb_clean_rx_ring(struct igb_ring *); 120 static void igb_set_rx_mode(struct net_device *); 121 static void igb_update_phy_info(struct timer_list *); 122 static void igb_watchdog(struct timer_list *); 123 static void igb_watchdog_task(struct work_struct *); 124 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 125 static void igb_get_stats64(struct net_device *dev, 126 struct rtnl_link_stats64 *stats); 127 static int igb_change_mtu(struct net_device *, int); 128 static int igb_set_mac(struct net_device *, void *); 129 static void igb_set_uta(struct igb_adapter *adapter, bool set); 130 static irqreturn_t igb_intr(int irq, void *); 131 static irqreturn_t igb_intr_msi(int irq, void *); 132 static irqreturn_t igb_msix_other(int irq, void *); 133 static irqreturn_t igb_msix_ring(int irq, void *); 134 #ifdef CONFIG_IGB_DCA 135 static void igb_update_dca(struct igb_q_vector *); 136 static void igb_setup_dca(struct igb_adapter *); 137 #endif /* CONFIG_IGB_DCA */ 138 static int igb_poll(struct napi_struct *, int); 139 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 140 static int igb_clean_rx_irq(struct igb_q_vector *, int); 141 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 142 static void igb_tx_timeout(struct net_device *, unsigned int txqueue); 143 static void igb_reset_task(struct work_struct *); 144 static void igb_vlan_mode(struct net_device *netdev, 145 netdev_features_t features); 146 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 147 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 148 static void igb_restore_vlan(struct igb_adapter *); 149 static void igb_rar_set_index(struct igb_adapter *, u32); 150 static void igb_ping_all_vfs(struct igb_adapter *); 151 static void igb_msg_task(struct igb_adapter *); 152 static void igb_vmm_control(struct igb_adapter *); 153 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 154 static void igb_flush_mac_table(struct igb_adapter *); 155 static int igb_available_rars(struct igb_adapter *, u8); 156 static void igb_set_default_mac_filter(struct igb_adapter *); 157 static int igb_uc_sync(struct net_device *, const unsigned char *); 158 static int igb_uc_unsync(struct net_device *, const unsigned char *); 159 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 160 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 161 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 162 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 163 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 164 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 165 bool setting); 166 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 167 bool setting); 168 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 169 struct ifla_vf_info *ivi); 170 static void igb_check_vf_rate_limit(struct igb_adapter *); 171 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 172 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 173 174 #ifdef CONFIG_PCI_IOV 175 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 176 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 177 static int igb_disable_sriov(struct pci_dev *dev); 178 static int igb_pci_disable_sriov(struct pci_dev *dev); 179 #endif 180 181 static int igb_suspend(struct device *); 182 static int igb_resume(struct device *); 183 static int igb_runtime_suspend(struct device *dev); 184 static int igb_runtime_resume(struct device *dev); 185 static int igb_runtime_idle(struct device *dev); 186 static const struct dev_pm_ops igb_pm_ops = { 187 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 188 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 189 igb_runtime_idle) 190 }; 191 static void igb_shutdown(struct pci_dev *); 192 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 193 #ifdef CONFIG_IGB_DCA 194 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 195 static struct notifier_block dca_notifier = { 196 .notifier_call = igb_notify_dca, 197 .next = NULL, 198 .priority = 0 199 }; 200 #endif 201 #ifdef CONFIG_PCI_IOV 202 static unsigned int max_vfs; 203 module_param(max_vfs, uint, 0); 204 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 205 #endif /* CONFIG_PCI_IOV */ 206 207 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 208 pci_channel_state_t); 209 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 210 static void igb_io_resume(struct pci_dev *); 211 212 static const struct pci_error_handlers igb_err_handler = { 213 .error_detected = igb_io_error_detected, 214 .slot_reset = igb_io_slot_reset, 215 .resume = igb_io_resume, 216 }; 217 218 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 219 220 static struct pci_driver igb_driver = { 221 .name = igb_driver_name, 222 .id_table = igb_pci_tbl, 223 .probe = igb_probe, 224 .remove = igb_remove, 225 #ifdef CONFIG_PM 226 .driver.pm = &igb_pm_ops, 227 #endif 228 .shutdown = igb_shutdown, 229 .sriov_configure = igb_pci_sriov_configure, 230 .err_handler = &igb_err_handler 231 }; 232 233 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 234 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 235 MODULE_LICENSE("GPL v2"); 236 237 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 238 static int debug = -1; 239 module_param(debug, int, 0); 240 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 241 242 struct igb_reg_info { 243 u32 ofs; 244 char *name; 245 }; 246 247 static const struct igb_reg_info igb_reg_info_tbl[] = { 248 249 /* General Registers */ 250 {E1000_CTRL, "CTRL"}, 251 {E1000_STATUS, "STATUS"}, 252 {E1000_CTRL_EXT, "CTRL_EXT"}, 253 254 /* Interrupt Registers */ 255 {E1000_ICR, "ICR"}, 256 257 /* RX Registers */ 258 {E1000_RCTL, "RCTL"}, 259 {E1000_RDLEN(0), "RDLEN"}, 260 {E1000_RDH(0), "RDH"}, 261 {E1000_RDT(0), "RDT"}, 262 {E1000_RXDCTL(0), "RXDCTL"}, 263 {E1000_RDBAL(0), "RDBAL"}, 264 {E1000_RDBAH(0), "RDBAH"}, 265 266 /* TX Registers */ 267 {E1000_TCTL, "TCTL"}, 268 {E1000_TDBAL(0), "TDBAL"}, 269 {E1000_TDBAH(0), "TDBAH"}, 270 {E1000_TDLEN(0), "TDLEN"}, 271 {E1000_TDH(0), "TDH"}, 272 {E1000_TDT(0), "TDT"}, 273 {E1000_TXDCTL(0), "TXDCTL"}, 274 {E1000_TDFH, "TDFH"}, 275 {E1000_TDFT, "TDFT"}, 276 {E1000_TDFHS, "TDFHS"}, 277 {E1000_TDFPC, "TDFPC"}, 278 279 /* List Terminator */ 280 {} 281 }; 282 283 /* igb_regdump - register printout routine */ 284 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 285 { 286 int n = 0; 287 char rname[16]; 288 u32 regs[8]; 289 290 switch (reginfo->ofs) { 291 case E1000_RDLEN(0): 292 for (n = 0; n < 4; n++) 293 regs[n] = rd32(E1000_RDLEN(n)); 294 break; 295 case E1000_RDH(0): 296 for (n = 0; n < 4; n++) 297 regs[n] = rd32(E1000_RDH(n)); 298 break; 299 case E1000_RDT(0): 300 for (n = 0; n < 4; n++) 301 regs[n] = rd32(E1000_RDT(n)); 302 break; 303 case E1000_RXDCTL(0): 304 for (n = 0; n < 4; n++) 305 regs[n] = rd32(E1000_RXDCTL(n)); 306 break; 307 case E1000_RDBAL(0): 308 for (n = 0; n < 4; n++) 309 regs[n] = rd32(E1000_RDBAL(n)); 310 break; 311 case E1000_RDBAH(0): 312 for (n = 0; n < 4; n++) 313 regs[n] = rd32(E1000_RDBAH(n)); 314 break; 315 case E1000_TDBAL(0): 316 for (n = 0; n < 4; n++) 317 regs[n] = rd32(E1000_RDBAL(n)); 318 break; 319 case E1000_TDBAH(0): 320 for (n = 0; n < 4; n++) 321 regs[n] = rd32(E1000_TDBAH(n)); 322 break; 323 case E1000_TDLEN(0): 324 for (n = 0; n < 4; n++) 325 regs[n] = rd32(E1000_TDLEN(n)); 326 break; 327 case E1000_TDH(0): 328 for (n = 0; n < 4; n++) 329 regs[n] = rd32(E1000_TDH(n)); 330 break; 331 case E1000_TDT(0): 332 for (n = 0; n < 4; n++) 333 regs[n] = rd32(E1000_TDT(n)); 334 break; 335 case E1000_TXDCTL(0): 336 for (n = 0; n < 4; n++) 337 regs[n] = rd32(E1000_TXDCTL(n)); 338 break; 339 default: 340 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 341 return; 342 } 343 344 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 345 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 346 regs[2], regs[3]); 347 } 348 349 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 350 static void igb_dump(struct igb_adapter *adapter) 351 { 352 struct net_device *netdev = adapter->netdev; 353 struct e1000_hw *hw = &adapter->hw; 354 struct igb_reg_info *reginfo; 355 struct igb_ring *tx_ring; 356 union e1000_adv_tx_desc *tx_desc; 357 struct my_u0 { u64 a; u64 b; } *u0; 358 struct igb_ring *rx_ring; 359 union e1000_adv_rx_desc *rx_desc; 360 u32 staterr; 361 u16 i, n; 362 363 if (!netif_msg_hw(adapter)) 364 return; 365 366 /* Print netdevice Info */ 367 if (netdev) { 368 dev_info(&adapter->pdev->dev, "Net device Info\n"); 369 pr_info("Device Name state trans_start\n"); 370 pr_info("%-15s %016lX %016lX\n", netdev->name, 371 netdev->state, dev_trans_start(netdev)); 372 } 373 374 /* Print Registers */ 375 dev_info(&adapter->pdev->dev, "Register Dump\n"); 376 pr_info(" Register Name Value\n"); 377 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 378 reginfo->name; reginfo++) { 379 igb_regdump(hw, reginfo); 380 } 381 382 /* Print TX Ring Summary */ 383 if (!netdev || !netif_running(netdev)) 384 goto exit; 385 386 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 387 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 388 for (n = 0; n < adapter->num_tx_queues; n++) { 389 struct igb_tx_buffer *buffer_info; 390 tx_ring = adapter->tx_ring[n]; 391 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 392 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 393 n, tx_ring->next_to_use, tx_ring->next_to_clean, 394 (u64)dma_unmap_addr(buffer_info, dma), 395 dma_unmap_len(buffer_info, len), 396 buffer_info->next_to_watch, 397 (u64)buffer_info->time_stamp); 398 } 399 400 /* Print TX Rings */ 401 if (!netif_msg_tx_done(adapter)) 402 goto rx_ring_summary; 403 404 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 405 406 /* Transmit Descriptor Formats 407 * 408 * Advanced Transmit Descriptor 409 * +--------------------------------------------------------------+ 410 * 0 | Buffer Address [63:0] | 411 * +--------------------------------------------------------------+ 412 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 413 * +--------------------------------------------------------------+ 414 * 63 46 45 40 39 38 36 35 32 31 24 15 0 415 */ 416 417 for (n = 0; n < adapter->num_tx_queues; n++) { 418 tx_ring = adapter->tx_ring[n]; 419 pr_info("------------------------------------\n"); 420 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 421 pr_info("------------------------------------\n"); 422 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 423 424 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 425 const char *next_desc; 426 struct igb_tx_buffer *buffer_info; 427 tx_desc = IGB_TX_DESC(tx_ring, i); 428 buffer_info = &tx_ring->tx_buffer_info[i]; 429 u0 = (struct my_u0 *)tx_desc; 430 if (i == tx_ring->next_to_use && 431 i == tx_ring->next_to_clean) 432 next_desc = " NTC/U"; 433 else if (i == tx_ring->next_to_use) 434 next_desc = " NTU"; 435 else if (i == tx_ring->next_to_clean) 436 next_desc = " NTC"; 437 else 438 next_desc = ""; 439 440 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 441 i, le64_to_cpu(u0->a), 442 le64_to_cpu(u0->b), 443 (u64)dma_unmap_addr(buffer_info, dma), 444 dma_unmap_len(buffer_info, len), 445 buffer_info->next_to_watch, 446 (u64)buffer_info->time_stamp, 447 buffer_info->skb, next_desc); 448 449 if (netif_msg_pktdata(adapter) && buffer_info->skb) 450 print_hex_dump(KERN_INFO, "", 451 DUMP_PREFIX_ADDRESS, 452 16, 1, buffer_info->skb->data, 453 dma_unmap_len(buffer_info, len), 454 true); 455 } 456 } 457 458 /* Print RX Rings Summary */ 459 rx_ring_summary: 460 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 461 pr_info("Queue [NTU] [NTC]\n"); 462 for (n = 0; n < adapter->num_rx_queues; n++) { 463 rx_ring = adapter->rx_ring[n]; 464 pr_info(" %5d %5X %5X\n", 465 n, rx_ring->next_to_use, rx_ring->next_to_clean); 466 } 467 468 /* Print RX Rings */ 469 if (!netif_msg_rx_status(adapter)) 470 goto exit; 471 472 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 473 474 /* Advanced Receive Descriptor (Read) Format 475 * 63 1 0 476 * +-----------------------------------------------------+ 477 * 0 | Packet Buffer Address [63:1] |A0/NSE| 478 * +----------------------------------------------+------+ 479 * 8 | Header Buffer Address [63:1] | DD | 480 * +-----------------------------------------------------+ 481 * 482 * 483 * Advanced Receive Descriptor (Write-Back) Format 484 * 485 * 63 48 47 32 31 30 21 20 17 16 4 3 0 486 * +------------------------------------------------------+ 487 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 488 * | Checksum Ident | | | | Type | Type | 489 * +------------------------------------------------------+ 490 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 491 * +------------------------------------------------------+ 492 * 63 48 47 32 31 20 19 0 493 */ 494 495 for (n = 0; n < adapter->num_rx_queues; n++) { 496 rx_ring = adapter->rx_ring[n]; 497 pr_info("------------------------------------\n"); 498 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 499 pr_info("------------------------------------\n"); 500 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 501 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 502 503 for (i = 0; i < rx_ring->count; i++) { 504 const char *next_desc; 505 struct igb_rx_buffer *buffer_info; 506 buffer_info = &rx_ring->rx_buffer_info[i]; 507 rx_desc = IGB_RX_DESC(rx_ring, i); 508 u0 = (struct my_u0 *)rx_desc; 509 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 510 511 if (i == rx_ring->next_to_use) 512 next_desc = " NTU"; 513 else if (i == rx_ring->next_to_clean) 514 next_desc = " NTC"; 515 else 516 next_desc = ""; 517 518 if (staterr & E1000_RXD_STAT_DD) { 519 /* Descriptor Done */ 520 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 521 "RWB", i, 522 le64_to_cpu(u0->a), 523 le64_to_cpu(u0->b), 524 next_desc); 525 } else { 526 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 527 "R ", i, 528 le64_to_cpu(u0->a), 529 le64_to_cpu(u0->b), 530 (u64)buffer_info->dma, 531 next_desc); 532 533 if (netif_msg_pktdata(adapter) && 534 buffer_info->dma && buffer_info->page) { 535 print_hex_dump(KERN_INFO, "", 536 DUMP_PREFIX_ADDRESS, 537 16, 1, 538 page_address(buffer_info->page) + 539 buffer_info->page_offset, 540 igb_rx_bufsz(rx_ring), true); 541 } 542 } 543 } 544 } 545 546 exit: 547 return; 548 } 549 550 /** 551 * igb_get_i2c_data - Reads the I2C SDA data bit 552 * @hw: pointer to hardware structure 553 * @i2cctl: Current value of I2CCTL register 554 * 555 * Returns the I2C data bit value 556 **/ 557 static int igb_get_i2c_data(void *data) 558 { 559 struct igb_adapter *adapter = (struct igb_adapter *)data; 560 struct e1000_hw *hw = &adapter->hw; 561 s32 i2cctl = rd32(E1000_I2CPARAMS); 562 563 return !!(i2cctl & E1000_I2C_DATA_IN); 564 } 565 566 /** 567 * igb_set_i2c_data - Sets the I2C data bit 568 * @data: pointer to hardware structure 569 * @state: I2C data value (0 or 1) to set 570 * 571 * Sets the I2C data bit 572 **/ 573 static void igb_set_i2c_data(void *data, int state) 574 { 575 struct igb_adapter *adapter = (struct igb_adapter *)data; 576 struct e1000_hw *hw = &adapter->hw; 577 s32 i2cctl = rd32(E1000_I2CPARAMS); 578 579 if (state) 580 i2cctl |= E1000_I2C_DATA_OUT; 581 else 582 i2cctl &= ~E1000_I2C_DATA_OUT; 583 584 i2cctl &= ~E1000_I2C_DATA_OE_N; 585 i2cctl |= E1000_I2C_CLK_OE_N; 586 wr32(E1000_I2CPARAMS, i2cctl); 587 wrfl(); 588 589 } 590 591 /** 592 * igb_set_i2c_clk - Sets the I2C SCL clock 593 * @data: pointer to hardware structure 594 * @state: state to set clock 595 * 596 * Sets the I2C clock line to state 597 **/ 598 static void igb_set_i2c_clk(void *data, int state) 599 { 600 struct igb_adapter *adapter = (struct igb_adapter *)data; 601 struct e1000_hw *hw = &adapter->hw; 602 s32 i2cctl = rd32(E1000_I2CPARAMS); 603 604 if (state) { 605 i2cctl |= E1000_I2C_CLK_OUT; 606 i2cctl &= ~E1000_I2C_CLK_OE_N; 607 } else { 608 i2cctl &= ~E1000_I2C_CLK_OUT; 609 i2cctl &= ~E1000_I2C_CLK_OE_N; 610 } 611 wr32(E1000_I2CPARAMS, i2cctl); 612 wrfl(); 613 } 614 615 /** 616 * igb_get_i2c_clk - Gets the I2C SCL clock state 617 * @data: pointer to hardware structure 618 * 619 * Gets the I2C clock state 620 **/ 621 static int igb_get_i2c_clk(void *data) 622 { 623 struct igb_adapter *adapter = (struct igb_adapter *)data; 624 struct e1000_hw *hw = &adapter->hw; 625 s32 i2cctl = rd32(E1000_I2CPARAMS); 626 627 return !!(i2cctl & E1000_I2C_CLK_IN); 628 } 629 630 static const struct i2c_algo_bit_data igb_i2c_algo = { 631 .setsda = igb_set_i2c_data, 632 .setscl = igb_set_i2c_clk, 633 .getsda = igb_get_i2c_data, 634 .getscl = igb_get_i2c_clk, 635 .udelay = 5, 636 .timeout = 20, 637 }; 638 639 /** 640 * igb_get_hw_dev - return device 641 * @hw: pointer to hardware structure 642 * 643 * used by hardware layer to print debugging information 644 **/ 645 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 646 { 647 struct igb_adapter *adapter = hw->back; 648 return adapter->netdev; 649 } 650 651 /** 652 * igb_init_module - Driver Registration Routine 653 * 654 * igb_init_module is the first routine called when the driver is 655 * loaded. All it does is register with the PCI subsystem. 656 **/ 657 static int __init igb_init_module(void) 658 { 659 int ret; 660 661 pr_info("%s\n", igb_driver_string); 662 pr_info("%s\n", igb_copyright); 663 664 #ifdef CONFIG_IGB_DCA 665 dca_register_notify(&dca_notifier); 666 #endif 667 ret = pci_register_driver(&igb_driver); 668 return ret; 669 } 670 671 module_init(igb_init_module); 672 673 /** 674 * igb_exit_module - Driver Exit Cleanup Routine 675 * 676 * igb_exit_module is called just before the driver is removed 677 * from memory. 678 **/ 679 static void __exit igb_exit_module(void) 680 { 681 #ifdef CONFIG_IGB_DCA 682 dca_unregister_notify(&dca_notifier); 683 #endif 684 pci_unregister_driver(&igb_driver); 685 } 686 687 module_exit(igb_exit_module); 688 689 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 690 /** 691 * igb_cache_ring_register - Descriptor ring to register mapping 692 * @adapter: board private structure to initialize 693 * 694 * Once we know the feature-set enabled for the device, we'll cache 695 * the register offset the descriptor ring is assigned to. 696 **/ 697 static void igb_cache_ring_register(struct igb_adapter *adapter) 698 { 699 int i = 0, j = 0; 700 u32 rbase_offset = adapter->vfs_allocated_count; 701 702 switch (adapter->hw.mac.type) { 703 case e1000_82576: 704 /* The queues are allocated for virtualization such that VF 0 705 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 706 * In order to avoid collision we start at the first free queue 707 * and continue consuming queues in the same sequence 708 */ 709 if (adapter->vfs_allocated_count) { 710 for (; i < adapter->rss_queues; i++) 711 adapter->rx_ring[i]->reg_idx = rbase_offset + 712 Q_IDX_82576(i); 713 } 714 fallthrough; 715 case e1000_82575: 716 case e1000_82580: 717 case e1000_i350: 718 case e1000_i354: 719 case e1000_i210: 720 case e1000_i211: 721 fallthrough; 722 default: 723 for (; i < adapter->num_rx_queues; i++) 724 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 725 for (; j < adapter->num_tx_queues; j++) 726 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 727 break; 728 } 729 } 730 731 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 732 { 733 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 734 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 735 u32 value = 0; 736 737 if (E1000_REMOVED(hw_addr)) 738 return ~value; 739 740 value = readl(&hw_addr[reg]); 741 742 /* reads should not return all F's */ 743 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 744 struct net_device *netdev = igb->netdev; 745 hw->hw_addr = NULL; 746 netdev_err(netdev, "PCIe link lost\n"); 747 WARN(pci_device_is_present(igb->pdev), 748 "igb: Failed to read reg 0x%x!\n", reg); 749 } 750 751 return value; 752 } 753 754 /** 755 * igb_write_ivar - configure ivar for given MSI-X vector 756 * @hw: pointer to the HW structure 757 * @msix_vector: vector number we are allocating to a given ring 758 * @index: row index of IVAR register to write within IVAR table 759 * @offset: column offset of in IVAR, should be multiple of 8 760 * 761 * This function is intended to handle the writing of the IVAR register 762 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 763 * each containing an cause allocation for an Rx and Tx ring, and a 764 * variable number of rows depending on the number of queues supported. 765 **/ 766 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 767 int index, int offset) 768 { 769 u32 ivar = array_rd32(E1000_IVAR0, index); 770 771 /* clear any bits that are currently set */ 772 ivar &= ~((u32)0xFF << offset); 773 774 /* write vector and valid bit */ 775 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 776 777 array_wr32(E1000_IVAR0, index, ivar); 778 } 779 780 #define IGB_N0_QUEUE -1 781 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 782 { 783 struct igb_adapter *adapter = q_vector->adapter; 784 struct e1000_hw *hw = &adapter->hw; 785 int rx_queue = IGB_N0_QUEUE; 786 int tx_queue = IGB_N0_QUEUE; 787 u32 msixbm = 0; 788 789 if (q_vector->rx.ring) 790 rx_queue = q_vector->rx.ring->reg_idx; 791 if (q_vector->tx.ring) 792 tx_queue = q_vector->tx.ring->reg_idx; 793 794 switch (hw->mac.type) { 795 case e1000_82575: 796 /* The 82575 assigns vectors using a bitmask, which matches the 797 * bitmask for the EICR/EIMS/EIMC registers. To assign one 798 * or more queues to a vector, we write the appropriate bits 799 * into the MSIXBM register for that vector. 800 */ 801 if (rx_queue > IGB_N0_QUEUE) 802 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 803 if (tx_queue > IGB_N0_QUEUE) 804 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 805 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 806 msixbm |= E1000_EIMS_OTHER; 807 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 808 q_vector->eims_value = msixbm; 809 break; 810 case e1000_82576: 811 /* 82576 uses a table that essentially consists of 2 columns 812 * with 8 rows. The ordering is column-major so we use the 813 * lower 3 bits as the row index, and the 4th bit as the 814 * column offset. 815 */ 816 if (rx_queue > IGB_N0_QUEUE) 817 igb_write_ivar(hw, msix_vector, 818 rx_queue & 0x7, 819 (rx_queue & 0x8) << 1); 820 if (tx_queue > IGB_N0_QUEUE) 821 igb_write_ivar(hw, msix_vector, 822 tx_queue & 0x7, 823 ((tx_queue & 0x8) << 1) + 8); 824 q_vector->eims_value = BIT(msix_vector); 825 break; 826 case e1000_82580: 827 case e1000_i350: 828 case e1000_i354: 829 case e1000_i210: 830 case e1000_i211: 831 /* On 82580 and newer adapters the scheme is similar to 82576 832 * however instead of ordering column-major we have things 833 * ordered row-major. So we traverse the table by using 834 * bit 0 as the column offset, and the remaining bits as the 835 * row index. 836 */ 837 if (rx_queue > IGB_N0_QUEUE) 838 igb_write_ivar(hw, msix_vector, 839 rx_queue >> 1, 840 (rx_queue & 0x1) << 4); 841 if (tx_queue > IGB_N0_QUEUE) 842 igb_write_ivar(hw, msix_vector, 843 tx_queue >> 1, 844 ((tx_queue & 0x1) << 4) + 8); 845 q_vector->eims_value = BIT(msix_vector); 846 break; 847 default: 848 BUG(); 849 break; 850 } 851 852 /* add q_vector eims value to global eims_enable_mask */ 853 adapter->eims_enable_mask |= q_vector->eims_value; 854 855 /* configure q_vector to set itr on first interrupt */ 856 q_vector->set_itr = 1; 857 } 858 859 /** 860 * igb_configure_msix - Configure MSI-X hardware 861 * @adapter: board private structure to initialize 862 * 863 * igb_configure_msix sets up the hardware to properly 864 * generate MSI-X interrupts. 865 **/ 866 static void igb_configure_msix(struct igb_adapter *adapter) 867 { 868 u32 tmp; 869 int i, vector = 0; 870 struct e1000_hw *hw = &adapter->hw; 871 872 adapter->eims_enable_mask = 0; 873 874 /* set vector for other causes, i.e. link changes */ 875 switch (hw->mac.type) { 876 case e1000_82575: 877 tmp = rd32(E1000_CTRL_EXT); 878 /* enable MSI-X PBA support*/ 879 tmp |= E1000_CTRL_EXT_PBA_CLR; 880 881 /* Auto-Mask interrupts upon ICR read. */ 882 tmp |= E1000_CTRL_EXT_EIAME; 883 tmp |= E1000_CTRL_EXT_IRCA; 884 885 wr32(E1000_CTRL_EXT, tmp); 886 887 /* enable msix_other interrupt */ 888 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 889 adapter->eims_other = E1000_EIMS_OTHER; 890 891 break; 892 893 case e1000_82576: 894 case e1000_82580: 895 case e1000_i350: 896 case e1000_i354: 897 case e1000_i210: 898 case e1000_i211: 899 /* Turn on MSI-X capability first, or our settings 900 * won't stick. And it will take days to debug. 901 */ 902 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 903 E1000_GPIE_PBA | E1000_GPIE_EIAME | 904 E1000_GPIE_NSICR); 905 906 /* enable msix_other interrupt */ 907 adapter->eims_other = BIT(vector); 908 tmp = (vector++ | E1000_IVAR_VALID) << 8; 909 910 wr32(E1000_IVAR_MISC, tmp); 911 break; 912 default: 913 /* do nothing, since nothing else supports MSI-X */ 914 break; 915 } /* switch (hw->mac.type) */ 916 917 adapter->eims_enable_mask |= adapter->eims_other; 918 919 for (i = 0; i < adapter->num_q_vectors; i++) 920 igb_assign_vector(adapter->q_vector[i], vector++); 921 922 wrfl(); 923 } 924 925 /** 926 * igb_request_msix - Initialize MSI-X interrupts 927 * @adapter: board private structure to initialize 928 * 929 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 930 * kernel. 931 **/ 932 static int igb_request_msix(struct igb_adapter *adapter) 933 { 934 struct net_device *netdev = adapter->netdev; 935 int i, err = 0, vector = 0, free_vector = 0; 936 937 err = request_irq(adapter->msix_entries[vector].vector, 938 igb_msix_other, 0, netdev->name, adapter); 939 if (err) 940 goto err_out; 941 942 for (i = 0; i < adapter->num_q_vectors; i++) { 943 struct igb_q_vector *q_vector = adapter->q_vector[i]; 944 945 vector++; 946 947 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 948 949 if (q_vector->rx.ring && q_vector->tx.ring) 950 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 951 q_vector->rx.ring->queue_index); 952 else if (q_vector->tx.ring) 953 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 954 q_vector->tx.ring->queue_index); 955 else if (q_vector->rx.ring) 956 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 957 q_vector->rx.ring->queue_index); 958 else 959 sprintf(q_vector->name, "%s-unused", netdev->name); 960 961 err = request_irq(adapter->msix_entries[vector].vector, 962 igb_msix_ring, 0, q_vector->name, 963 q_vector); 964 if (err) 965 goto err_free; 966 } 967 968 igb_configure_msix(adapter); 969 return 0; 970 971 err_free: 972 /* free already assigned IRQs */ 973 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 974 975 vector--; 976 for (i = 0; i < vector; i++) { 977 free_irq(adapter->msix_entries[free_vector++].vector, 978 adapter->q_vector[i]); 979 } 980 err_out: 981 return err; 982 } 983 984 /** 985 * igb_free_q_vector - Free memory allocated for specific interrupt vector 986 * @adapter: board private structure to initialize 987 * @v_idx: Index of vector to be freed 988 * 989 * This function frees the memory allocated to the q_vector. 990 **/ 991 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 992 { 993 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 994 995 adapter->q_vector[v_idx] = NULL; 996 997 /* igb_get_stats64() might access the rings on this vector, 998 * we must wait a grace period before freeing it. 999 */ 1000 if (q_vector) 1001 kfree_rcu(q_vector, rcu); 1002 } 1003 1004 /** 1005 * igb_reset_q_vector - Reset config for interrupt vector 1006 * @adapter: board private structure to initialize 1007 * @v_idx: Index of vector to be reset 1008 * 1009 * If NAPI is enabled it will delete any references to the 1010 * NAPI struct. This is preparation for igb_free_q_vector. 1011 **/ 1012 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1013 { 1014 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1015 1016 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1017 * allocated. So, q_vector is NULL so we should stop here. 1018 */ 1019 if (!q_vector) 1020 return; 1021 1022 if (q_vector->tx.ring) 1023 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1024 1025 if (q_vector->rx.ring) 1026 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1027 1028 netif_napi_del(&q_vector->napi); 1029 1030 } 1031 1032 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1033 { 1034 int v_idx = adapter->num_q_vectors; 1035 1036 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1037 pci_disable_msix(adapter->pdev); 1038 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1039 pci_disable_msi(adapter->pdev); 1040 1041 while (v_idx--) 1042 igb_reset_q_vector(adapter, v_idx); 1043 } 1044 1045 /** 1046 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1047 * @adapter: board private structure to initialize 1048 * 1049 * This function frees the memory allocated to the q_vectors. In addition if 1050 * NAPI is enabled it will delete any references to the NAPI struct prior 1051 * to freeing the q_vector. 1052 **/ 1053 static void igb_free_q_vectors(struct igb_adapter *adapter) 1054 { 1055 int v_idx = adapter->num_q_vectors; 1056 1057 adapter->num_tx_queues = 0; 1058 adapter->num_rx_queues = 0; 1059 adapter->num_q_vectors = 0; 1060 1061 while (v_idx--) { 1062 igb_reset_q_vector(adapter, v_idx); 1063 igb_free_q_vector(adapter, v_idx); 1064 } 1065 } 1066 1067 /** 1068 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1069 * @adapter: board private structure to initialize 1070 * 1071 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1072 * MSI-X interrupts allocated. 1073 */ 1074 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1075 { 1076 igb_free_q_vectors(adapter); 1077 igb_reset_interrupt_capability(adapter); 1078 } 1079 1080 /** 1081 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1082 * @adapter: board private structure to initialize 1083 * @msix: boolean value of MSIX capability 1084 * 1085 * Attempt to configure interrupts using the best available 1086 * capabilities of the hardware and kernel. 1087 **/ 1088 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1089 { 1090 int err; 1091 int numvecs, i; 1092 1093 if (!msix) 1094 goto msi_only; 1095 adapter->flags |= IGB_FLAG_HAS_MSIX; 1096 1097 /* Number of supported queues. */ 1098 adapter->num_rx_queues = adapter->rss_queues; 1099 if (adapter->vfs_allocated_count) 1100 adapter->num_tx_queues = 1; 1101 else 1102 adapter->num_tx_queues = adapter->rss_queues; 1103 1104 /* start with one vector for every Rx queue */ 1105 numvecs = adapter->num_rx_queues; 1106 1107 /* if Tx handler is separate add 1 for every Tx queue */ 1108 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1109 numvecs += adapter->num_tx_queues; 1110 1111 /* store the number of vectors reserved for queues */ 1112 adapter->num_q_vectors = numvecs; 1113 1114 /* add 1 vector for link status interrupts */ 1115 numvecs++; 1116 for (i = 0; i < numvecs; i++) 1117 adapter->msix_entries[i].entry = i; 1118 1119 err = pci_enable_msix_range(adapter->pdev, 1120 adapter->msix_entries, 1121 numvecs, 1122 numvecs); 1123 if (err > 0) 1124 return; 1125 1126 igb_reset_interrupt_capability(adapter); 1127 1128 /* If we can't do MSI-X, try MSI */ 1129 msi_only: 1130 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1131 #ifdef CONFIG_PCI_IOV 1132 /* disable SR-IOV for non MSI-X configurations */ 1133 if (adapter->vf_data) { 1134 struct e1000_hw *hw = &adapter->hw; 1135 /* disable iov and allow time for transactions to clear */ 1136 pci_disable_sriov(adapter->pdev); 1137 msleep(500); 1138 1139 kfree(adapter->vf_mac_list); 1140 adapter->vf_mac_list = NULL; 1141 kfree(adapter->vf_data); 1142 adapter->vf_data = NULL; 1143 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1144 wrfl(); 1145 msleep(100); 1146 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1147 } 1148 #endif 1149 adapter->vfs_allocated_count = 0; 1150 adapter->rss_queues = 1; 1151 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1152 adapter->num_rx_queues = 1; 1153 adapter->num_tx_queues = 1; 1154 adapter->num_q_vectors = 1; 1155 if (!pci_enable_msi(adapter->pdev)) 1156 adapter->flags |= IGB_FLAG_HAS_MSI; 1157 } 1158 1159 static void igb_add_ring(struct igb_ring *ring, 1160 struct igb_ring_container *head) 1161 { 1162 head->ring = ring; 1163 head->count++; 1164 } 1165 1166 /** 1167 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1168 * @adapter: board private structure to initialize 1169 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1170 * @v_idx: index of vector in adapter struct 1171 * @txr_count: total number of Tx rings to allocate 1172 * @txr_idx: index of first Tx ring to allocate 1173 * @rxr_count: total number of Rx rings to allocate 1174 * @rxr_idx: index of first Rx ring to allocate 1175 * 1176 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1177 **/ 1178 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1179 int v_count, int v_idx, 1180 int txr_count, int txr_idx, 1181 int rxr_count, int rxr_idx) 1182 { 1183 struct igb_q_vector *q_vector; 1184 struct igb_ring *ring; 1185 int ring_count; 1186 size_t size; 1187 1188 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1189 if (txr_count > 1 || rxr_count > 1) 1190 return -ENOMEM; 1191 1192 ring_count = txr_count + rxr_count; 1193 size = struct_size(q_vector, ring, ring_count); 1194 1195 /* allocate q_vector and rings */ 1196 q_vector = adapter->q_vector[v_idx]; 1197 if (!q_vector) { 1198 q_vector = kzalloc(size, GFP_KERNEL); 1199 } else if (size > ksize(q_vector)) { 1200 kfree_rcu(q_vector, rcu); 1201 q_vector = kzalloc(size, GFP_KERNEL); 1202 } else { 1203 memset(q_vector, 0, size); 1204 } 1205 if (!q_vector) 1206 return -ENOMEM; 1207 1208 /* initialize NAPI */ 1209 netif_napi_add(adapter->netdev, &q_vector->napi, 1210 igb_poll, 64); 1211 1212 /* tie q_vector and adapter together */ 1213 adapter->q_vector[v_idx] = q_vector; 1214 q_vector->adapter = adapter; 1215 1216 /* initialize work limits */ 1217 q_vector->tx.work_limit = adapter->tx_work_limit; 1218 1219 /* initialize ITR configuration */ 1220 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1221 q_vector->itr_val = IGB_START_ITR; 1222 1223 /* initialize pointer to rings */ 1224 ring = q_vector->ring; 1225 1226 /* intialize ITR */ 1227 if (rxr_count) { 1228 /* rx or rx/tx vector */ 1229 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1230 q_vector->itr_val = adapter->rx_itr_setting; 1231 } else { 1232 /* tx only vector */ 1233 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1234 q_vector->itr_val = adapter->tx_itr_setting; 1235 } 1236 1237 if (txr_count) { 1238 /* assign generic ring traits */ 1239 ring->dev = &adapter->pdev->dev; 1240 ring->netdev = adapter->netdev; 1241 1242 /* configure backlink on ring */ 1243 ring->q_vector = q_vector; 1244 1245 /* update q_vector Tx values */ 1246 igb_add_ring(ring, &q_vector->tx); 1247 1248 /* For 82575, context index must be unique per ring. */ 1249 if (adapter->hw.mac.type == e1000_82575) 1250 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1251 1252 /* apply Tx specific ring traits */ 1253 ring->count = adapter->tx_ring_count; 1254 ring->queue_index = txr_idx; 1255 1256 ring->cbs_enable = false; 1257 ring->idleslope = 0; 1258 ring->sendslope = 0; 1259 ring->hicredit = 0; 1260 ring->locredit = 0; 1261 1262 u64_stats_init(&ring->tx_syncp); 1263 u64_stats_init(&ring->tx_syncp2); 1264 1265 /* assign ring to adapter */ 1266 adapter->tx_ring[txr_idx] = ring; 1267 1268 /* push pointer to next ring */ 1269 ring++; 1270 } 1271 1272 if (rxr_count) { 1273 /* assign generic ring traits */ 1274 ring->dev = &adapter->pdev->dev; 1275 ring->netdev = adapter->netdev; 1276 1277 /* configure backlink on ring */ 1278 ring->q_vector = q_vector; 1279 1280 /* update q_vector Rx values */ 1281 igb_add_ring(ring, &q_vector->rx); 1282 1283 /* set flag indicating ring supports SCTP checksum offload */ 1284 if (adapter->hw.mac.type >= e1000_82576) 1285 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1286 1287 /* On i350, i354, i210, and i211, loopback VLAN packets 1288 * have the tag byte-swapped. 1289 */ 1290 if (adapter->hw.mac.type >= e1000_i350) 1291 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1292 1293 /* apply Rx specific ring traits */ 1294 ring->count = adapter->rx_ring_count; 1295 ring->queue_index = rxr_idx; 1296 1297 u64_stats_init(&ring->rx_syncp); 1298 1299 /* assign ring to adapter */ 1300 adapter->rx_ring[rxr_idx] = ring; 1301 } 1302 1303 return 0; 1304 } 1305 1306 1307 /** 1308 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1309 * @adapter: board private structure to initialize 1310 * 1311 * We allocate one q_vector per queue interrupt. If allocation fails we 1312 * return -ENOMEM. 1313 **/ 1314 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1315 { 1316 int q_vectors = adapter->num_q_vectors; 1317 int rxr_remaining = adapter->num_rx_queues; 1318 int txr_remaining = adapter->num_tx_queues; 1319 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1320 int err; 1321 1322 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1323 for (; rxr_remaining; v_idx++) { 1324 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1325 0, 0, 1, rxr_idx); 1326 1327 if (err) 1328 goto err_out; 1329 1330 /* update counts and index */ 1331 rxr_remaining--; 1332 rxr_idx++; 1333 } 1334 } 1335 1336 for (; v_idx < q_vectors; v_idx++) { 1337 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1338 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1339 1340 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1341 tqpv, txr_idx, rqpv, rxr_idx); 1342 1343 if (err) 1344 goto err_out; 1345 1346 /* update counts and index */ 1347 rxr_remaining -= rqpv; 1348 txr_remaining -= tqpv; 1349 rxr_idx++; 1350 txr_idx++; 1351 } 1352 1353 return 0; 1354 1355 err_out: 1356 adapter->num_tx_queues = 0; 1357 adapter->num_rx_queues = 0; 1358 adapter->num_q_vectors = 0; 1359 1360 while (v_idx--) 1361 igb_free_q_vector(adapter, v_idx); 1362 1363 return -ENOMEM; 1364 } 1365 1366 /** 1367 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1368 * @adapter: board private structure to initialize 1369 * @msix: boolean value of MSIX capability 1370 * 1371 * This function initializes the interrupts and allocates all of the queues. 1372 **/ 1373 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1374 { 1375 struct pci_dev *pdev = adapter->pdev; 1376 int err; 1377 1378 igb_set_interrupt_capability(adapter, msix); 1379 1380 err = igb_alloc_q_vectors(adapter); 1381 if (err) { 1382 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1383 goto err_alloc_q_vectors; 1384 } 1385 1386 igb_cache_ring_register(adapter); 1387 1388 return 0; 1389 1390 err_alloc_q_vectors: 1391 igb_reset_interrupt_capability(adapter); 1392 return err; 1393 } 1394 1395 /** 1396 * igb_request_irq - initialize interrupts 1397 * @adapter: board private structure to initialize 1398 * 1399 * Attempts to configure interrupts using the best available 1400 * capabilities of the hardware and kernel. 1401 **/ 1402 static int igb_request_irq(struct igb_adapter *adapter) 1403 { 1404 struct net_device *netdev = adapter->netdev; 1405 struct pci_dev *pdev = adapter->pdev; 1406 int err = 0; 1407 1408 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1409 err = igb_request_msix(adapter); 1410 if (!err) 1411 goto request_done; 1412 /* fall back to MSI */ 1413 igb_free_all_tx_resources(adapter); 1414 igb_free_all_rx_resources(adapter); 1415 1416 igb_clear_interrupt_scheme(adapter); 1417 err = igb_init_interrupt_scheme(adapter, false); 1418 if (err) 1419 goto request_done; 1420 1421 igb_setup_all_tx_resources(adapter); 1422 igb_setup_all_rx_resources(adapter); 1423 igb_configure(adapter); 1424 } 1425 1426 igb_assign_vector(adapter->q_vector[0], 0); 1427 1428 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1429 err = request_irq(pdev->irq, igb_intr_msi, 0, 1430 netdev->name, adapter); 1431 if (!err) 1432 goto request_done; 1433 1434 /* fall back to legacy interrupts */ 1435 igb_reset_interrupt_capability(adapter); 1436 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1437 } 1438 1439 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1440 netdev->name, adapter); 1441 1442 if (err) 1443 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1444 err); 1445 1446 request_done: 1447 return err; 1448 } 1449 1450 static void igb_free_irq(struct igb_adapter *adapter) 1451 { 1452 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1453 int vector = 0, i; 1454 1455 free_irq(adapter->msix_entries[vector++].vector, adapter); 1456 1457 for (i = 0; i < adapter->num_q_vectors; i++) 1458 free_irq(adapter->msix_entries[vector++].vector, 1459 adapter->q_vector[i]); 1460 } else { 1461 free_irq(adapter->pdev->irq, adapter); 1462 } 1463 } 1464 1465 /** 1466 * igb_irq_disable - Mask off interrupt generation on the NIC 1467 * @adapter: board private structure 1468 **/ 1469 static void igb_irq_disable(struct igb_adapter *adapter) 1470 { 1471 struct e1000_hw *hw = &adapter->hw; 1472 1473 /* we need to be careful when disabling interrupts. The VFs are also 1474 * mapped into these registers and so clearing the bits can cause 1475 * issues on the VF drivers so we only need to clear what we set 1476 */ 1477 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1478 u32 regval = rd32(E1000_EIAM); 1479 1480 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1481 wr32(E1000_EIMC, adapter->eims_enable_mask); 1482 regval = rd32(E1000_EIAC); 1483 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1484 } 1485 1486 wr32(E1000_IAM, 0); 1487 wr32(E1000_IMC, ~0); 1488 wrfl(); 1489 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1490 int i; 1491 1492 for (i = 0; i < adapter->num_q_vectors; i++) 1493 synchronize_irq(adapter->msix_entries[i].vector); 1494 } else { 1495 synchronize_irq(adapter->pdev->irq); 1496 } 1497 } 1498 1499 /** 1500 * igb_irq_enable - Enable default interrupt generation settings 1501 * @adapter: board private structure 1502 **/ 1503 static void igb_irq_enable(struct igb_adapter *adapter) 1504 { 1505 struct e1000_hw *hw = &adapter->hw; 1506 1507 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1508 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1509 u32 regval = rd32(E1000_EIAC); 1510 1511 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1512 regval = rd32(E1000_EIAM); 1513 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1514 wr32(E1000_EIMS, adapter->eims_enable_mask); 1515 if (adapter->vfs_allocated_count) { 1516 wr32(E1000_MBVFIMR, 0xFF); 1517 ims |= E1000_IMS_VMMB; 1518 } 1519 wr32(E1000_IMS, ims); 1520 } else { 1521 wr32(E1000_IMS, IMS_ENABLE_MASK | 1522 E1000_IMS_DRSTA); 1523 wr32(E1000_IAM, IMS_ENABLE_MASK | 1524 E1000_IMS_DRSTA); 1525 } 1526 } 1527 1528 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1529 { 1530 struct e1000_hw *hw = &adapter->hw; 1531 u16 pf_id = adapter->vfs_allocated_count; 1532 u16 vid = adapter->hw.mng_cookie.vlan_id; 1533 u16 old_vid = adapter->mng_vlan_id; 1534 1535 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1536 /* add VID to filter table */ 1537 igb_vfta_set(hw, vid, pf_id, true, true); 1538 adapter->mng_vlan_id = vid; 1539 } else { 1540 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1541 } 1542 1543 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1544 (vid != old_vid) && 1545 !test_bit(old_vid, adapter->active_vlans)) { 1546 /* remove VID from filter table */ 1547 igb_vfta_set(hw, vid, pf_id, false, true); 1548 } 1549 } 1550 1551 /** 1552 * igb_release_hw_control - release control of the h/w to f/w 1553 * @adapter: address of board private structure 1554 * 1555 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1556 * For ASF and Pass Through versions of f/w this means that the 1557 * driver is no longer loaded. 1558 **/ 1559 static void igb_release_hw_control(struct igb_adapter *adapter) 1560 { 1561 struct e1000_hw *hw = &adapter->hw; 1562 u32 ctrl_ext; 1563 1564 /* Let firmware take over control of h/w */ 1565 ctrl_ext = rd32(E1000_CTRL_EXT); 1566 wr32(E1000_CTRL_EXT, 1567 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1568 } 1569 1570 /** 1571 * igb_get_hw_control - get control of the h/w from f/w 1572 * @adapter: address of board private structure 1573 * 1574 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1575 * For ASF and Pass Through versions of f/w this means that 1576 * the driver is loaded. 1577 **/ 1578 static void igb_get_hw_control(struct igb_adapter *adapter) 1579 { 1580 struct e1000_hw *hw = &adapter->hw; 1581 u32 ctrl_ext; 1582 1583 /* Let firmware know the driver has taken over */ 1584 ctrl_ext = rd32(E1000_CTRL_EXT); 1585 wr32(E1000_CTRL_EXT, 1586 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1587 } 1588 1589 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1590 { 1591 struct net_device *netdev = adapter->netdev; 1592 struct e1000_hw *hw = &adapter->hw; 1593 1594 WARN_ON(hw->mac.type != e1000_i210); 1595 1596 if (enable) 1597 adapter->flags |= IGB_FLAG_FQTSS; 1598 else 1599 adapter->flags &= ~IGB_FLAG_FQTSS; 1600 1601 if (netif_running(netdev)) 1602 schedule_work(&adapter->reset_task); 1603 } 1604 1605 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1606 { 1607 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1608 } 1609 1610 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1611 enum tx_queue_prio prio) 1612 { 1613 u32 val; 1614 1615 WARN_ON(hw->mac.type != e1000_i210); 1616 WARN_ON(queue < 0 || queue > 4); 1617 1618 val = rd32(E1000_I210_TXDCTL(queue)); 1619 1620 if (prio == TX_QUEUE_PRIO_HIGH) 1621 val |= E1000_TXDCTL_PRIORITY; 1622 else 1623 val &= ~E1000_TXDCTL_PRIORITY; 1624 1625 wr32(E1000_I210_TXDCTL(queue), val); 1626 } 1627 1628 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1629 { 1630 u32 val; 1631 1632 WARN_ON(hw->mac.type != e1000_i210); 1633 WARN_ON(queue < 0 || queue > 1); 1634 1635 val = rd32(E1000_I210_TQAVCC(queue)); 1636 1637 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1638 val |= E1000_TQAVCC_QUEUEMODE; 1639 else 1640 val &= ~E1000_TQAVCC_QUEUEMODE; 1641 1642 wr32(E1000_I210_TQAVCC(queue), val); 1643 } 1644 1645 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1646 { 1647 int i; 1648 1649 for (i = 0; i < adapter->num_tx_queues; i++) { 1650 if (adapter->tx_ring[i]->cbs_enable) 1651 return true; 1652 } 1653 1654 return false; 1655 } 1656 1657 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1658 { 1659 int i; 1660 1661 for (i = 0; i < adapter->num_tx_queues; i++) { 1662 if (adapter->tx_ring[i]->launchtime_enable) 1663 return true; 1664 } 1665 1666 return false; 1667 } 1668 1669 /** 1670 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1671 * @adapter: pointer to adapter struct 1672 * @queue: queue number 1673 * 1674 * Configure CBS and Launchtime for a given hardware queue. 1675 * Parameters are retrieved from the correct Tx ring, so 1676 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1677 * for setting those correctly prior to this function being called. 1678 **/ 1679 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1680 { 1681 struct igb_ring *ring = adapter->tx_ring[queue]; 1682 struct net_device *netdev = adapter->netdev; 1683 struct e1000_hw *hw = &adapter->hw; 1684 u32 tqavcc, tqavctrl; 1685 u16 value; 1686 1687 WARN_ON(hw->mac.type != e1000_i210); 1688 WARN_ON(queue < 0 || queue > 1); 1689 1690 /* If any of the Qav features is enabled, configure queues as SR and 1691 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1692 * as SP. 1693 */ 1694 if (ring->cbs_enable || ring->launchtime_enable) { 1695 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1696 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1697 } else { 1698 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1699 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1700 } 1701 1702 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1703 if (ring->cbs_enable || queue == 0) { 1704 /* i210 does not allow the queue 0 to be in the Strict 1705 * Priority mode while the Qav mode is enabled, so, 1706 * instead of disabling strict priority mode, we give 1707 * queue 0 the maximum of credits possible. 1708 * 1709 * See section 8.12.19 of the i210 datasheet, "Note: 1710 * Queue0 QueueMode must be set to 1b when 1711 * TransmitMode is set to Qav." 1712 */ 1713 if (queue == 0 && !ring->cbs_enable) { 1714 /* max "linkspeed" idleslope in kbps */ 1715 ring->idleslope = 1000000; 1716 ring->hicredit = ETH_FRAME_LEN; 1717 } 1718 1719 /* Always set data transfer arbitration to credit-based 1720 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1721 * the queues. 1722 */ 1723 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1724 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1725 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1726 1727 /* According to i210 datasheet section 7.2.7.7, we should set 1728 * the 'idleSlope' field from TQAVCC register following the 1729 * equation: 1730 * 1731 * For 100 Mbps link speed: 1732 * 1733 * value = BW * 0x7735 * 0.2 (E1) 1734 * 1735 * For 1000Mbps link speed: 1736 * 1737 * value = BW * 0x7735 * 2 (E2) 1738 * 1739 * E1 and E2 can be merged into one equation as shown below. 1740 * Note that 'link-speed' is in Mbps. 1741 * 1742 * value = BW * 0x7735 * 2 * link-speed 1743 * -------------- (E3) 1744 * 1000 1745 * 1746 * 'BW' is the percentage bandwidth out of full link speed 1747 * which can be found with the following equation. Note that 1748 * idleSlope here is the parameter from this function which 1749 * is in kbps. 1750 * 1751 * BW = idleSlope 1752 * ----------------- (E4) 1753 * link-speed * 1000 1754 * 1755 * That said, we can come up with a generic equation to 1756 * calculate the value we should set it TQAVCC register by 1757 * replacing 'BW' in E3 by E4. The resulting equation is: 1758 * 1759 * value = idleSlope * 0x7735 * 2 * link-speed 1760 * ----------------- -------------- (E5) 1761 * link-speed * 1000 1000 1762 * 1763 * 'link-speed' is present in both sides of the fraction so 1764 * it is canceled out. The final equation is the following: 1765 * 1766 * value = idleSlope * 61034 1767 * ----------------- (E6) 1768 * 1000000 1769 * 1770 * NOTE: For i210, given the above, we can see that idleslope 1771 * is represented in 16.38431 kbps units by the value at 1772 * the TQAVCC register (1Gbps / 61034), which reduces 1773 * the granularity for idleslope increments. 1774 * For instance, if you want to configure a 2576kbps 1775 * idleslope, the value to be written on the register 1776 * would have to be 157.23. If rounded down, you end 1777 * up with less bandwidth available than originally 1778 * required (~2572 kbps). If rounded up, you end up 1779 * with a higher bandwidth (~2589 kbps). Below the 1780 * approach we take is to always round up the 1781 * calculated value, so the resulting bandwidth might 1782 * be slightly higher for some configurations. 1783 */ 1784 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1785 1786 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1787 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1788 tqavcc |= value; 1789 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1790 1791 wr32(E1000_I210_TQAVHC(queue), 1792 0x80000000 + ring->hicredit * 0x7735); 1793 } else { 1794 1795 /* Set idleSlope to zero. */ 1796 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1797 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1798 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1799 1800 /* Set hiCredit to zero. */ 1801 wr32(E1000_I210_TQAVHC(queue), 0); 1802 1803 /* If CBS is not enabled for any queues anymore, then return to 1804 * the default state of Data Transmission Arbitration on 1805 * TQAVCTRL. 1806 */ 1807 if (!is_any_cbs_enabled(adapter)) { 1808 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1809 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1810 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1811 } 1812 } 1813 1814 /* If LaunchTime is enabled, set DataTranTIM. */ 1815 if (ring->launchtime_enable) { 1816 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1817 * for any of the SR queues, and configure fetchtime delta. 1818 * XXX NOTE: 1819 * - LaunchTime will be enabled for all SR queues. 1820 * - A fixed offset can be added relative to the launch 1821 * time of all packets if configured at reg LAUNCH_OS0. 1822 * We are keeping it as 0 for now (default value). 1823 */ 1824 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1825 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1826 E1000_TQAVCTRL_FETCHTIME_DELTA; 1827 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1828 } else { 1829 /* If Launchtime is not enabled for any SR queues anymore, 1830 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1831 * effectively disabling Launchtime. 1832 */ 1833 if (!is_any_txtime_enabled(adapter)) { 1834 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1835 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1836 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1837 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1838 } 1839 } 1840 1841 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1842 * CBS are not configurable by software so we don't do any 'controller 1843 * configuration' in respect to these parameters. 1844 */ 1845 1846 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1847 ring->cbs_enable ? "enabled" : "disabled", 1848 ring->launchtime_enable ? "enabled" : "disabled", 1849 queue, 1850 ring->idleslope, ring->sendslope, 1851 ring->hicredit, ring->locredit); 1852 } 1853 1854 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1855 bool enable) 1856 { 1857 struct igb_ring *ring; 1858 1859 if (queue < 0 || queue > adapter->num_tx_queues) 1860 return -EINVAL; 1861 1862 ring = adapter->tx_ring[queue]; 1863 ring->launchtime_enable = enable; 1864 1865 return 0; 1866 } 1867 1868 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1869 bool enable, int idleslope, int sendslope, 1870 int hicredit, int locredit) 1871 { 1872 struct igb_ring *ring; 1873 1874 if (queue < 0 || queue > adapter->num_tx_queues) 1875 return -EINVAL; 1876 1877 ring = adapter->tx_ring[queue]; 1878 1879 ring->cbs_enable = enable; 1880 ring->idleslope = idleslope; 1881 ring->sendslope = sendslope; 1882 ring->hicredit = hicredit; 1883 ring->locredit = locredit; 1884 1885 return 0; 1886 } 1887 1888 /** 1889 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1890 * @adapter: pointer to adapter struct 1891 * 1892 * Configure TQAVCTRL register switching the controller's Tx mode 1893 * if FQTSS mode is enabled or disabled. Additionally, will issue 1894 * a call to igb_config_tx_modes() per queue so any previously saved 1895 * Tx parameters are applied. 1896 **/ 1897 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1898 { 1899 struct net_device *netdev = adapter->netdev; 1900 struct e1000_hw *hw = &adapter->hw; 1901 u32 val; 1902 1903 /* Only i210 controller supports changing the transmission mode. */ 1904 if (hw->mac.type != e1000_i210) 1905 return; 1906 1907 if (is_fqtss_enabled(adapter)) { 1908 int i, max_queue; 1909 1910 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1911 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1912 * so SP queues wait for SR ones. 1913 */ 1914 val = rd32(E1000_I210_TQAVCTRL); 1915 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1916 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1917 wr32(E1000_I210_TQAVCTRL, val); 1918 1919 /* Configure Tx and Rx packet buffers sizes as described in 1920 * i210 datasheet section 7.2.7.7. 1921 */ 1922 val = rd32(E1000_TXPBS); 1923 val &= ~I210_TXPBSIZE_MASK; 1924 val |= I210_TXPBSIZE_PB0_8KB | I210_TXPBSIZE_PB1_8KB | 1925 I210_TXPBSIZE_PB2_4KB | I210_TXPBSIZE_PB3_4KB; 1926 wr32(E1000_TXPBS, val); 1927 1928 val = rd32(E1000_RXPBS); 1929 val &= ~I210_RXPBSIZE_MASK; 1930 val |= I210_RXPBSIZE_PB_30KB; 1931 wr32(E1000_RXPBS, val); 1932 1933 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1934 * register should not exceed the buffer size programmed in 1935 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1936 * so according to the datasheet we should set MAX_TPKT_SIZE to 1937 * 4kB / 64. 1938 * 1939 * However, when we do so, no frame from queue 2 and 3 are 1940 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1941 * or _equal_ to the buffer size programmed in TXPBS. For this 1942 * reason, we set set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1943 */ 1944 val = (4096 - 1) / 64; 1945 wr32(E1000_I210_DTXMXPKTSZ, val); 1946 1947 /* Since FQTSS mode is enabled, apply any CBS configuration 1948 * previously set. If no previous CBS configuration has been 1949 * done, then the initial configuration is applied, which means 1950 * CBS is disabled. 1951 */ 1952 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1953 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1954 1955 for (i = 0; i < max_queue; i++) { 1956 igb_config_tx_modes(adapter, i); 1957 } 1958 } else { 1959 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1960 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1961 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1962 1963 val = rd32(E1000_I210_TQAVCTRL); 1964 /* According to Section 8.12.21, the other flags we've set when 1965 * enabling FQTSS are not relevant when disabling FQTSS so we 1966 * don't set they here. 1967 */ 1968 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1969 wr32(E1000_I210_TQAVCTRL, val); 1970 } 1971 1972 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1973 "enabled" : "disabled"); 1974 } 1975 1976 /** 1977 * igb_configure - configure the hardware for RX and TX 1978 * @adapter: private board structure 1979 **/ 1980 static void igb_configure(struct igb_adapter *adapter) 1981 { 1982 struct net_device *netdev = adapter->netdev; 1983 int i; 1984 1985 igb_get_hw_control(adapter); 1986 igb_set_rx_mode(netdev); 1987 igb_setup_tx_mode(adapter); 1988 1989 igb_restore_vlan(adapter); 1990 1991 igb_setup_tctl(adapter); 1992 igb_setup_mrqc(adapter); 1993 igb_setup_rctl(adapter); 1994 1995 igb_nfc_filter_restore(adapter); 1996 igb_configure_tx(adapter); 1997 igb_configure_rx(adapter); 1998 1999 igb_rx_fifo_flush_82575(&adapter->hw); 2000 2001 /* call igb_desc_unused which always leaves 2002 * at least 1 descriptor unused to make sure 2003 * next_to_use != next_to_clean 2004 */ 2005 for (i = 0; i < adapter->num_rx_queues; i++) { 2006 struct igb_ring *ring = adapter->rx_ring[i]; 2007 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 2008 } 2009 } 2010 2011 /** 2012 * igb_power_up_link - Power up the phy/serdes link 2013 * @adapter: address of board private structure 2014 **/ 2015 void igb_power_up_link(struct igb_adapter *adapter) 2016 { 2017 igb_reset_phy(&adapter->hw); 2018 2019 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2020 igb_power_up_phy_copper(&adapter->hw); 2021 else 2022 igb_power_up_serdes_link_82575(&adapter->hw); 2023 2024 igb_setup_link(&adapter->hw); 2025 } 2026 2027 /** 2028 * igb_power_down_link - Power down the phy/serdes link 2029 * @adapter: address of board private structure 2030 */ 2031 static void igb_power_down_link(struct igb_adapter *adapter) 2032 { 2033 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2034 igb_power_down_phy_copper_82575(&adapter->hw); 2035 else 2036 igb_shutdown_serdes_link_82575(&adapter->hw); 2037 } 2038 2039 /** 2040 * Detect and switch function for Media Auto Sense 2041 * @adapter: address of the board private structure 2042 **/ 2043 static void igb_check_swap_media(struct igb_adapter *adapter) 2044 { 2045 struct e1000_hw *hw = &adapter->hw; 2046 u32 ctrl_ext, connsw; 2047 bool swap_now = false; 2048 2049 ctrl_ext = rd32(E1000_CTRL_EXT); 2050 connsw = rd32(E1000_CONNSW); 2051 2052 /* need to live swap if current media is copper and we have fiber/serdes 2053 * to go to. 2054 */ 2055 2056 if ((hw->phy.media_type == e1000_media_type_copper) && 2057 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2058 swap_now = true; 2059 } else if ((hw->phy.media_type != e1000_media_type_copper) && 2060 !(connsw & E1000_CONNSW_SERDESD)) { 2061 /* copper signal takes time to appear */ 2062 if (adapter->copper_tries < 4) { 2063 adapter->copper_tries++; 2064 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2065 wr32(E1000_CONNSW, connsw); 2066 return; 2067 } else { 2068 adapter->copper_tries = 0; 2069 if ((connsw & E1000_CONNSW_PHYSD) && 2070 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2071 swap_now = true; 2072 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2073 wr32(E1000_CONNSW, connsw); 2074 } 2075 } 2076 } 2077 2078 if (!swap_now) 2079 return; 2080 2081 switch (hw->phy.media_type) { 2082 case e1000_media_type_copper: 2083 netdev_info(adapter->netdev, 2084 "MAS: changing media to fiber/serdes\n"); 2085 ctrl_ext |= 2086 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2087 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2088 adapter->copper_tries = 0; 2089 break; 2090 case e1000_media_type_internal_serdes: 2091 case e1000_media_type_fiber: 2092 netdev_info(adapter->netdev, 2093 "MAS: changing media to copper\n"); 2094 ctrl_ext &= 2095 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2096 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2097 break; 2098 default: 2099 /* shouldn't get here during regular operation */ 2100 netdev_err(adapter->netdev, 2101 "AMS: Invalid media type found, returning\n"); 2102 break; 2103 } 2104 wr32(E1000_CTRL_EXT, ctrl_ext); 2105 } 2106 2107 /** 2108 * igb_up - Open the interface and prepare it to handle traffic 2109 * @adapter: board private structure 2110 **/ 2111 int igb_up(struct igb_adapter *adapter) 2112 { 2113 struct e1000_hw *hw = &adapter->hw; 2114 int i; 2115 2116 /* hardware has been reset, we need to reload some things */ 2117 igb_configure(adapter); 2118 2119 clear_bit(__IGB_DOWN, &adapter->state); 2120 2121 for (i = 0; i < adapter->num_q_vectors; i++) 2122 napi_enable(&(adapter->q_vector[i]->napi)); 2123 2124 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2125 igb_configure_msix(adapter); 2126 else 2127 igb_assign_vector(adapter->q_vector[0], 0); 2128 2129 /* Clear any pending interrupts. */ 2130 rd32(E1000_TSICR); 2131 rd32(E1000_ICR); 2132 igb_irq_enable(adapter); 2133 2134 /* notify VFs that reset has been completed */ 2135 if (adapter->vfs_allocated_count) { 2136 u32 reg_data = rd32(E1000_CTRL_EXT); 2137 2138 reg_data |= E1000_CTRL_EXT_PFRSTD; 2139 wr32(E1000_CTRL_EXT, reg_data); 2140 } 2141 2142 netif_tx_start_all_queues(adapter->netdev); 2143 2144 /* start the watchdog. */ 2145 hw->mac.get_link_status = 1; 2146 schedule_work(&adapter->watchdog_task); 2147 2148 if ((adapter->flags & IGB_FLAG_EEE) && 2149 (!hw->dev_spec._82575.eee_disable)) 2150 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2151 2152 return 0; 2153 } 2154 2155 void igb_down(struct igb_adapter *adapter) 2156 { 2157 struct net_device *netdev = adapter->netdev; 2158 struct e1000_hw *hw = &adapter->hw; 2159 u32 tctl, rctl; 2160 int i; 2161 2162 /* signal that we're down so the interrupt handler does not 2163 * reschedule our watchdog timer 2164 */ 2165 set_bit(__IGB_DOWN, &adapter->state); 2166 2167 /* disable receives in the hardware */ 2168 rctl = rd32(E1000_RCTL); 2169 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2170 /* flush and sleep below */ 2171 2172 igb_nfc_filter_exit(adapter); 2173 2174 netif_carrier_off(netdev); 2175 netif_tx_stop_all_queues(netdev); 2176 2177 /* disable transmits in the hardware */ 2178 tctl = rd32(E1000_TCTL); 2179 tctl &= ~E1000_TCTL_EN; 2180 wr32(E1000_TCTL, tctl); 2181 /* flush both disables and wait for them to finish */ 2182 wrfl(); 2183 usleep_range(10000, 11000); 2184 2185 igb_irq_disable(adapter); 2186 2187 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2188 2189 for (i = 0; i < adapter->num_q_vectors; i++) { 2190 if (adapter->q_vector[i]) { 2191 napi_synchronize(&adapter->q_vector[i]->napi); 2192 napi_disable(&adapter->q_vector[i]->napi); 2193 } 2194 } 2195 2196 del_timer_sync(&adapter->watchdog_timer); 2197 del_timer_sync(&adapter->phy_info_timer); 2198 2199 /* record the stats before reset*/ 2200 spin_lock(&adapter->stats64_lock); 2201 igb_update_stats(adapter); 2202 spin_unlock(&adapter->stats64_lock); 2203 2204 adapter->link_speed = 0; 2205 adapter->link_duplex = 0; 2206 2207 if (!pci_channel_offline(adapter->pdev)) 2208 igb_reset(adapter); 2209 2210 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2211 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2212 2213 igb_clean_all_tx_rings(adapter); 2214 igb_clean_all_rx_rings(adapter); 2215 #ifdef CONFIG_IGB_DCA 2216 2217 /* since we reset the hardware DCA settings were cleared */ 2218 igb_setup_dca(adapter); 2219 #endif 2220 } 2221 2222 void igb_reinit_locked(struct igb_adapter *adapter) 2223 { 2224 WARN_ON(in_interrupt()); 2225 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2226 usleep_range(1000, 2000); 2227 igb_down(adapter); 2228 igb_up(adapter); 2229 clear_bit(__IGB_RESETTING, &adapter->state); 2230 } 2231 2232 /** igb_enable_mas - Media Autosense re-enable after swap 2233 * 2234 * @adapter: adapter struct 2235 **/ 2236 static void igb_enable_mas(struct igb_adapter *adapter) 2237 { 2238 struct e1000_hw *hw = &adapter->hw; 2239 u32 connsw = rd32(E1000_CONNSW); 2240 2241 /* configure for SerDes media detect */ 2242 if ((hw->phy.media_type == e1000_media_type_copper) && 2243 (!(connsw & E1000_CONNSW_SERDESD))) { 2244 connsw |= E1000_CONNSW_ENRGSRC; 2245 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2246 wr32(E1000_CONNSW, connsw); 2247 wrfl(); 2248 } 2249 } 2250 2251 void igb_reset(struct igb_adapter *adapter) 2252 { 2253 struct pci_dev *pdev = adapter->pdev; 2254 struct e1000_hw *hw = &adapter->hw; 2255 struct e1000_mac_info *mac = &hw->mac; 2256 struct e1000_fc_info *fc = &hw->fc; 2257 u32 pba, hwm; 2258 2259 /* Repartition Pba for greater than 9k mtu 2260 * To take effect CTRL.RST is required. 2261 */ 2262 switch (mac->type) { 2263 case e1000_i350: 2264 case e1000_i354: 2265 case e1000_82580: 2266 pba = rd32(E1000_RXPBS); 2267 pba = igb_rxpbs_adjust_82580(pba); 2268 break; 2269 case e1000_82576: 2270 pba = rd32(E1000_RXPBS); 2271 pba &= E1000_RXPBS_SIZE_MASK_82576; 2272 break; 2273 case e1000_82575: 2274 case e1000_i210: 2275 case e1000_i211: 2276 default: 2277 pba = E1000_PBA_34K; 2278 break; 2279 } 2280 2281 if (mac->type == e1000_82575) { 2282 u32 min_rx_space, min_tx_space, needed_tx_space; 2283 2284 /* write Rx PBA so that hardware can report correct Tx PBA */ 2285 wr32(E1000_PBA, pba); 2286 2287 /* To maintain wire speed transmits, the Tx FIFO should be 2288 * large enough to accommodate two full transmit packets, 2289 * rounded up to the next 1KB and expressed in KB. Likewise, 2290 * the Rx FIFO should be large enough to accommodate at least 2291 * one full receive packet and is similarly rounded up and 2292 * expressed in KB. 2293 */ 2294 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2295 2296 /* The Tx FIFO also stores 16 bytes of information about the Tx 2297 * but don't include Ethernet FCS because hardware appends it. 2298 * We only need to round down to the nearest 512 byte block 2299 * count since the value we care about is 2 frames, not 1. 2300 */ 2301 min_tx_space = adapter->max_frame_size; 2302 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2303 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2304 2305 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2306 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2307 2308 /* If current Tx allocation is less than the min Tx FIFO size, 2309 * and the min Tx FIFO size is less than the current Rx FIFO 2310 * allocation, take space away from current Rx allocation. 2311 */ 2312 if (needed_tx_space < pba) { 2313 pba -= needed_tx_space; 2314 2315 /* if short on Rx space, Rx wins and must trump Tx 2316 * adjustment 2317 */ 2318 if (pba < min_rx_space) 2319 pba = min_rx_space; 2320 } 2321 2322 /* adjust PBA for jumbo frames */ 2323 wr32(E1000_PBA, pba); 2324 } 2325 2326 /* flow control settings 2327 * The high water mark must be low enough to fit one full frame 2328 * after transmitting the pause frame. As such we must have enough 2329 * space to allow for us to complete our current transmit and then 2330 * receive the frame that is in progress from the link partner. 2331 * Set it to: 2332 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2333 */ 2334 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2335 2336 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2337 fc->low_water = fc->high_water - 16; 2338 fc->pause_time = 0xFFFF; 2339 fc->send_xon = 1; 2340 fc->current_mode = fc->requested_mode; 2341 2342 /* disable receive for all VFs and wait one second */ 2343 if (adapter->vfs_allocated_count) { 2344 int i; 2345 2346 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2347 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2348 2349 /* ping all the active vfs to let them know we are going down */ 2350 igb_ping_all_vfs(adapter); 2351 2352 /* disable transmits and receives */ 2353 wr32(E1000_VFRE, 0); 2354 wr32(E1000_VFTE, 0); 2355 } 2356 2357 /* Allow time for pending master requests to run */ 2358 hw->mac.ops.reset_hw(hw); 2359 wr32(E1000_WUC, 0); 2360 2361 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2362 /* need to resetup here after media swap */ 2363 adapter->ei.get_invariants(hw); 2364 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2365 } 2366 if ((mac->type == e1000_82575 || mac->type == e1000_i350) && 2367 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2368 igb_enable_mas(adapter); 2369 } 2370 if (hw->mac.ops.init_hw(hw)) 2371 dev_err(&pdev->dev, "Hardware Error\n"); 2372 2373 /* RAR registers were cleared during init_hw, clear mac table */ 2374 igb_flush_mac_table(adapter); 2375 __dev_uc_unsync(adapter->netdev, NULL); 2376 2377 /* Recover default RAR entry */ 2378 igb_set_default_mac_filter(adapter); 2379 2380 /* Flow control settings reset on hardware reset, so guarantee flow 2381 * control is off when forcing speed. 2382 */ 2383 if (!hw->mac.autoneg) 2384 igb_force_mac_fc(hw); 2385 2386 igb_init_dmac(adapter, pba); 2387 #ifdef CONFIG_IGB_HWMON 2388 /* Re-initialize the thermal sensor on i350 devices. */ 2389 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2390 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2391 /* If present, re-initialize the external thermal sensor 2392 * interface. 2393 */ 2394 if (adapter->ets) 2395 mac->ops.init_thermal_sensor_thresh(hw); 2396 } 2397 } 2398 #endif 2399 /* Re-establish EEE setting */ 2400 if (hw->phy.media_type == e1000_media_type_copper) { 2401 switch (mac->type) { 2402 case e1000_i350: 2403 case e1000_i210: 2404 case e1000_i211: 2405 igb_set_eee_i350(hw, true, true); 2406 break; 2407 case e1000_i354: 2408 igb_set_eee_i354(hw, true, true); 2409 break; 2410 default: 2411 break; 2412 } 2413 } 2414 if (!netif_running(adapter->netdev)) 2415 igb_power_down_link(adapter); 2416 2417 igb_update_mng_vlan(adapter); 2418 2419 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2420 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2421 2422 /* Re-enable PTP, where applicable. */ 2423 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2424 igb_ptp_reset(adapter); 2425 2426 igb_get_phy_info(hw); 2427 } 2428 2429 static netdev_features_t igb_fix_features(struct net_device *netdev, 2430 netdev_features_t features) 2431 { 2432 /* Since there is no support for separate Rx/Tx vlan accel 2433 * enable/disable make sure Tx flag is always in same state as Rx. 2434 */ 2435 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2436 features |= NETIF_F_HW_VLAN_CTAG_TX; 2437 else 2438 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2439 2440 return features; 2441 } 2442 2443 static int igb_set_features(struct net_device *netdev, 2444 netdev_features_t features) 2445 { 2446 netdev_features_t changed = netdev->features ^ features; 2447 struct igb_adapter *adapter = netdev_priv(netdev); 2448 2449 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2450 igb_vlan_mode(netdev, features); 2451 2452 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2453 return 0; 2454 2455 if (!(features & NETIF_F_NTUPLE)) { 2456 struct hlist_node *node2; 2457 struct igb_nfc_filter *rule; 2458 2459 spin_lock(&adapter->nfc_lock); 2460 hlist_for_each_entry_safe(rule, node2, 2461 &adapter->nfc_filter_list, nfc_node) { 2462 igb_erase_filter(adapter, rule); 2463 hlist_del(&rule->nfc_node); 2464 kfree(rule); 2465 } 2466 spin_unlock(&adapter->nfc_lock); 2467 adapter->nfc_filter_count = 0; 2468 } 2469 2470 netdev->features = features; 2471 2472 if (netif_running(netdev)) 2473 igb_reinit_locked(adapter); 2474 else 2475 igb_reset(adapter); 2476 2477 return 1; 2478 } 2479 2480 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2481 struct net_device *dev, 2482 const unsigned char *addr, u16 vid, 2483 u16 flags, 2484 struct netlink_ext_ack *extack) 2485 { 2486 /* guarantee we can provide a unique filter for the unicast address */ 2487 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2488 struct igb_adapter *adapter = netdev_priv(dev); 2489 int vfn = adapter->vfs_allocated_count; 2490 2491 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2492 return -ENOMEM; 2493 } 2494 2495 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2496 } 2497 2498 #define IGB_MAX_MAC_HDR_LEN 127 2499 #define IGB_MAX_NETWORK_HDR_LEN 511 2500 2501 static netdev_features_t 2502 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2503 netdev_features_t features) 2504 { 2505 unsigned int network_hdr_len, mac_hdr_len; 2506 2507 /* Make certain the headers can be described by a context descriptor */ 2508 mac_hdr_len = skb_network_header(skb) - skb->data; 2509 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2510 return features & ~(NETIF_F_HW_CSUM | 2511 NETIF_F_SCTP_CRC | 2512 NETIF_F_GSO_UDP_L4 | 2513 NETIF_F_HW_VLAN_CTAG_TX | 2514 NETIF_F_TSO | 2515 NETIF_F_TSO6); 2516 2517 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2518 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2519 return features & ~(NETIF_F_HW_CSUM | 2520 NETIF_F_SCTP_CRC | 2521 NETIF_F_GSO_UDP_L4 | 2522 NETIF_F_TSO | 2523 NETIF_F_TSO6); 2524 2525 /* We can only support IPV4 TSO in tunnels if we can mangle the 2526 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2527 */ 2528 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2529 features &= ~NETIF_F_TSO; 2530 2531 return features; 2532 } 2533 2534 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2535 { 2536 if (!is_fqtss_enabled(adapter)) { 2537 enable_fqtss(adapter, true); 2538 return; 2539 } 2540 2541 igb_config_tx_modes(adapter, queue); 2542 2543 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2544 enable_fqtss(adapter, false); 2545 } 2546 2547 static int igb_offload_cbs(struct igb_adapter *adapter, 2548 struct tc_cbs_qopt_offload *qopt) 2549 { 2550 struct e1000_hw *hw = &adapter->hw; 2551 int err; 2552 2553 /* CBS offloading is only supported by i210 controller. */ 2554 if (hw->mac.type != e1000_i210) 2555 return -EOPNOTSUPP; 2556 2557 /* CBS offloading is only supported by queue 0 and queue 1. */ 2558 if (qopt->queue < 0 || qopt->queue > 1) 2559 return -EINVAL; 2560 2561 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2562 qopt->idleslope, qopt->sendslope, 2563 qopt->hicredit, qopt->locredit); 2564 if (err) 2565 return err; 2566 2567 igb_offload_apply(adapter, qopt->queue); 2568 2569 return 0; 2570 } 2571 2572 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2573 #define VLAN_PRIO_FULL_MASK (0x07) 2574 2575 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2576 struct flow_cls_offload *f, 2577 int traffic_class, 2578 struct igb_nfc_filter *input) 2579 { 2580 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2581 struct flow_dissector *dissector = rule->match.dissector; 2582 struct netlink_ext_ack *extack = f->common.extack; 2583 2584 if (dissector->used_keys & 2585 ~(BIT(FLOW_DISSECTOR_KEY_BASIC) | 2586 BIT(FLOW_DISSECTOR_KEY_CONTROL) | 2587 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2588 BIT(FLOW_DISSECTOR_KEY_VLAN))) { 2589 NL_SET_ERR_MSG_MOD(extack, 2590 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2591 return -EOPNOTSUPP; 2592 } 2593 2594 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2595 struct flow_match_eth_addrs match; 2596 2597 flow_rule_match_eth_addrs(rule, &match); 2598 if (!is_zero_ether_addr(match.mask->dst)) { 2599 if (!is_broadcast_ether_addr(match.mask->dst)) { 2600 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2601 return -EINVAL; 2602 } 2603 2604 input->filter.match_flags |= 2605 IGB_FILTER_FLAG_DST_MAC_ADDR; 2606 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2607 } 2608 2609 if (!is_zero_ether_addr(match.mask->src)) { 2610 if (!is_broadcast_ether_addr(match.mask->src)) { 2611 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2612 return -EINVAL; 2613 } 2614 2615 input->filter.match_flags |= 2616 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2617 ether_addr_copy(input->filter.src_addr, match.key->src); 2618 } 2619 } 2620 2621 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2622 struct flow_match_basic match; 2623 2624 flow_rule_match_basic(rule, &match); 2625 if (match.mask->n_proto) { 2626 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2627 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2628 return -EINVAL; 2629 } 2630 2631 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2632 input->filter.etype = match.key->n_proto; 2633 } 2634 } 2635 2636 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2637 struct flow_match_vlan match; 2638 2639 flow_rule_match_vlan(rule, &match); 2640 if (match.mask->vlan_priority) { 2641 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2642 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2643 return -EINVAL; 2644 } 2645 2646 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2647 input->filter.vlan_tci = match.key->vlan_priority; 2648 } 2649 } 2650 2651 input->action = traffic_class; 2652 input->cookie = f->cookie; 2653 2654 return 0; 2655 } 2656 2657 static int igb_configure_clsflower(struct igb_adapter *adapter, 2658 struct flow_cls_offload *cls_flower) 2659 { 2660 struct netlink_ext_ack *extack = cls_flower->common.extack; 2661 struct igb_nfc_filter *filter, *f; 2662 int err, tc; 2663 2664 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2665 if (tc < 0) { 2666 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2667 return -EINVAL; 2668 } 2669 2670 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2671 if (!filter) 2672 return -ENOMEM; 2673 2674 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2675 if (err < 0) 2676 goto err_parse; 2677 2678 spin_lock(&adapter->nfc_lock); 2679 2680 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2681 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2682 err = -EEXIST; 2683 NL_SET_ERR_MSG_MOD(extack, 2684 "This filter is already set in ethtool"); 2685 goto err_locked; 2686 } 2687 } 2688 2689 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2690 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2691 err = -EEXIST; 2692 NL_SET_ERR_MSG_MOD(extack, 2693 "This filter is already set in cls_flower"); 2694 goto err_locked; 2695 } 2696 } 2697 2698 err = igb_add_filter(adapter, filter); 2699 if (err < 0) { 2700 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2701 goto err_locked; 2702 } 2703 2704 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2705 2706 spin_unlock(&adapter->nfc_lock); 2707 2708 return 0; 2709 2710 err_locked: 2711 spin_unlock(&adapter->nfc_lock); 2712 2713 err_parse: 2714 kfree(filter); 2715 2716 return err; 2717 } 2718 2719 static int igb_delete_clsflower(struct igb_adapter *adapter, 2720 struct flow_cls_offload *cls_flower) 2721 { 2722 struct igb_nfc_filter *filter; 2723 int err; 2724 2725 spin_lock(&adapter->nfc_lock); 2726 2727 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2728 if (filter->cookie == cls_flower->cookie) 2729 break; 2730 2731 if (!filter) { 2732 err = -ENOENT; 2733 goto out; 2734 } 2735 2736 err = igb_erase_filter(adapter, filter); 2737 if (err < 0) 2738 goto out; 2739 2740 hlist_del(&filter->nfc_node); 2741 kfree(filter); 2742 2743 out: 2744 spin_unlock(&adapter->nfc_lock); 2745 2746 return err; 2747 } 2748 2749 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2750 struct flow_cls_offload *cls_flower) 2751 { 2752 switch (cls_flower->command) { 2753 case FLOW_CLS_REPLACE: 2754 return igb_configure_clsflower(adapter, cls_flower); 2755 case FLOW_CLS_DESTROY: 2756 return igb_delete_clsflower(adapter, cls_flower); 2757 case FLOW_CLS_STATS: 2758 return -EOPNOTSUPP; 2759 default: 2760 return -EOPNOTSUPP; 2761 } 2762 } 2763 2764 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2765 void *cb_priv) 2766 { 2767 struct igb_adapter *adapter = cb_priv; 2768 2769 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2770 return -EOPNOTSUPP; 2771 2772 switch (type) { 2773 case TC_SETUP_CLSFLOWER: 2774 return igb_setup_tc_cls_flower(adapter, type_data); 2775 2776 default: 2777 return -EOPNOTSUPP; 2778 } 2779 } 2780 2781 static int igb_offload_txtime(struct igb_adapter *adapter, 2782 struct tc_etf_qopt_offload *qopt) 2783 { 2784 struct e1000_hw *hw = &adapter->hw; 2785 int err; 2786 2787 /* Launchtime offloading is only supported by i210 controller. */ 2788 if (hw->mac.type != e1000_i210) 2789 return -EOPNOTSUPP; 2790 2791 /* Launchtime offloading is only supported by queues 0 and 1. */ 2792 if (qopt->queue < 0 || qopt->queue > 1) 2793 return -EINVAL; 2794 2795 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2796 if (err) 2797 return err; 2798 2799 igb_offload_apply(adapter, qopt->queue); 2800 2801 return 0; 2802 } 2803 2804 static LIST_HEAD(igb_block_cb_list); 2805 2806 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2807 void *type_data) 2808 { 2809 struct igb_adapter *adapter = netdev_priv(dev); 2810 2811 switch (type) { 2812 case TC_SETUP_QDISC_CBS: 2813 return igb_offload_cbs(adapter, type_data); 2814 case TC_SETUP_BLOCK: 2815 return flow_block_cb_setup_simple(type_data, 2816 &igb_block_cb_list, 2817 igb_setup_tc_block_cb, 2818 adapter, adapter, true); 2819 2820 case TC_SETUP_QDISC_ETF: 2821 return igb_offload_txtime(adapter, type_data); 2822 2823 default: 2824 return -EOPNOTSUPP; 2825 } 2826 } 2827 2828 static const struct net_device_ops igb_netdev_ops = { 2829 .ndo_open = igb_open, 2830 .ndo_stop = igb_close, 2831 .ndo_start_xmit = igb_xmit_frame, 2832 .ndo_get_stats64 = igb_get_stats64, 2833 .ndo_set_rx_mode = igb_set_rx_mode, 2834 .ndo_set_mac_address = igb_set_mac, 2835 .ndo_change_mtu = igb_change_mtu, 2836 .ndo_do_ioctl = igb_ioctl, 2837 .ndo_tx_timeout = igb_tx_timeout, 2838 .ndo_validate_addr = eth_validate_addr, 2839 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2840 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2841 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2842 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2843 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 2844 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2845 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 2846 .ndo_get_vf_config = igb_ndo_get_vf_config, 2847 .ndo_fix_features = igb_fix_features, 2848 .ndo_set_features = igb_set_features, 2849 .ndo_fdb_add = igb_ndo_fdb_add, 2850 .ndo_features_check = igb_features_check, 2851 .ndo_setup_tc = igb_setup_tc, 2852 }; 2853 2854 /** 2855 * igb_set_fw_version - Configure version string for ethtool 2856 * @adapter: adapter struct 2857 **/ 2858 void igb_set_fw_version(struct igb_adapter *adapter) 2859 { 2860 struct e1000_hw *hw = &adapter->hw; 2861 struct e1000_fw_version fw; 2862 2863 igb_get_fw_version(hw, &fw); 2864 2865 switch (hw->mac.type) { 2866 case e1000_i210: 2867 case e1000_i211: 2868 if (!(igb_get_flash_presence_i210(hw))) { 2869 snprintf(adapter->fw_version, 2870 sizeof(adapter->fw_version), 2871 "%2d.%2d-%d", 2872 fw.invm_major, fw.invm_minor, 2873 fw.invm_img_type); 2874 break; 2875 } 2876 fallthrough; 2877 default: 2878 /* if option is rom valid, display its version too */ 2879 if (fw.or_valid) { 2880 snprintf(adapter->fw_version, 2881 sizeof(adapter->fw_version), 2882 "%d.%d, 0x%08x, %d.%d.%d", 2883 fw.eep_major, fw.eep_minor, fw.etrack_id, 2884 fw.or_major, fw.or_build, fw.or_patch); 2885 /* no option rom */ 2886 } else if (fw.etrack_id != 0X0000) { 2887 snprintf(adapter->fw_version, 2888 sizeof(adapter->fw_version), 2889 "%d.%d, 0x%08x", 2890 fw.eep_major, fw.eep_minor, fw.etrack_id); 2891 } else { 2892 snprintf(adapter->fw_version, 2893 sizeof(adapter->fw_version), 2894 "%d.%d.%d", 2895 fw.eep_major, fw.eep_minor, fw.eep_build); 2896 } 2897 break; 2898 } 2899 } 2900 2901 /** 2902 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2903 * 2904 * @adapter: adapter struct 2905 **/ 2906 static void igb_init_mas(struct igb_adapter *adapter) 2907 { 2908 struct e1000_hw *hw = &adapter->hw; 2909 u16 eeprom_data; 2910 2911 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2912 switch (hw->bus.func) { 2913 case E1000_FUNC_0: 2914 if (eeprom_data & IGB_MAS_ENABLE_0) { 2915 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2916 netdev_info(adapter->netdev, 2917 "MAS: Enabling Media Autosense for port %d\n", 2918 hw->bus.func); 2919 } 2920 break; 2921 case E1000_FUNC_1: 2922 if (eeprom_data & IGB_MAS_ENABLE_1) { 2923 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2924 netdev_info(adapter->netdev, 2925 "MAS: Enabling Media Autosense for port %d\n", 2926 hw->bus.func); 2927 } 2928 break; 2929 case E1000_FUNC_2: 2930 if (eeprom_data & IGB_MAS_ENABLE_2) { 2931 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2932 netdev_info(adapter->netdev, 2933 "MAS: Enabling Media Autosense for port %d\n", 2934 hw->bus.func); 2935 } 2936 break; 2937 case E1000_FUNC_3: 2938 if (eeprom_data & IGB_MAS_ENABLE_3) { 2939 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2940 netdev_info(adapter->netdev, 2941 "MAS: Enabling Media Autosense for port %d\n", 2942 hw->bus.func); 2943 } 2944 break; 2945 default: 2946 /* Shouldn't get here */ 2947 netdev_err(adapter->netdev, 2948 "MAS: Invalid port configuration, returning\n"); 2949 break; 2950 } 2951 } 2952 2953 /** 2954 * igb_init_i2c - Init I2C interface 2955 * @adapter: pointer to adapter structure 2956 **/ 2957 static s32 igb_init_i2c(struct igb_adapter *adapter) 2958 { 2959 s32 status = 0; 2960 2961 /* I2C interface supported on i350 devices */ 2962 if (adapter->hw.mac.type != e1000_i350) 2963 return 0; 2964 2965 /* Initialize the i2c bus which is controlled by the registers. 2966 * This bus will use the i2c_algo_bit structue that implements 2967 * the protocol through toggling of the 4 bits in the register. 2968 */ 2969 adapter->i2c_adap.owner = THIS_MODULE; 2970 adapter->i2c_algo = igb_i2c_algo; 2971 adapter->i2c_algo.data = adapter; 2972 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 2973 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 2974 strlcpy(adapter->i2c_adap.name, "igb BB", 2975 sizeof(adapter->i2c_adap.name)); 2976 status = i2c_bit_add_bus(&adapter->i2c_adap); 2977 return status; 2978 } 2979 2980 /** 2981 * igb_probe - Device Initialization Routine 2982 * @pdev: PCI device information struct 2983 * @ent: entry in igb_pci_tbl 2984 * 2985 * Returns 0 on success, negative on failure 2986 * 2987 * igb_probe initializes an adapter identified by a pci_dev structure. 2988 * The OS initialization, configuring of the adapter private structure, 2989 * and a hardware reset occur. 2990 **/ 2991 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2992 { 2993 struct net_device *netdev; 2994 struct igb_adapter *adapter; 2995 struct e1000_hw *hw; 2996 u16 eeprom_data = 0; 2997 s32 ret_val; 2998 static int global_quad_port_a; /* global quad port a indication */ 2999 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3000 int err, pci_using_dac; 3001 u8 part_str[E1000_PBANUM_LENGTH]; 3002 3003 /* Catch broken hardware that put the wrong VF device ID in 3004 * the PCIe SR-IOV capability. 3005 */ 3006 if (pdev->is_virtfn) { 3007 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 3008 pci_name(pdev), pdev->vendor, pdev->device); 3009 return -EINVAL; 3010 } 3011 3012 err = pci_enable_device_mem(pdev); 3013 if (err) 3014 return err; 3015 3016 pci_using_dac = 0; 3017 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3018 if (!err) { 3019 pci_using_dac = 1; 3020 } else { 3021 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3022 if (err) { 3023 dev_err(&pdev->dev, 3024 "No usable DMA configuration, aborting\n"); 3025 goto err_dma; 3026 } 3027 } 3028 3029 err = pci_request_mem_regions(pdev, igb_driver_name); 3030 if (err) 3031 goto err_pci_reg; 3032 3033 pci_enable_pcie_error_reporting(pdev); 3034 3035 pci_set_master(pdev); 3036 pci_save_state(pdev); 3037 3038 err = -ENOMEM; 3039 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3040 IGB_MAX_TX_QUEUES); 3041 if (!netdev) 3042 goto err_alloc_etherdev; 3043 3044 SET_NETDEV_DEV(netdev, &pdev->dev); 3045 3046 pci_set_drvdata(pdev, netdev); 3047 adapter = netdev_priv(netdev); 3048 adapter->netdev = netdev; 3049 adapter->pdev = pdev; 3050 hw = &adapter->hw; 3051 hw->back = adapter; 3052 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3053 3054 err = -EIO; 3055 adapter->io_addr = pci_iomap(pdev, 0, 0); 3056 if (!adapter->io_addr) 3057 goto err_ioremap; 3058 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3059 hw->hw_addr = adapter->io_addr; 3060 3061 netdev->netdev_ops = &igb_netdev_ops; 3062 igb_set_ethtool_ops(netdev); 3063 netdev->watchdog_timeo = 5 * HZ; 3064 3065 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 3066 3067 netdev->mem_start = pci_resource_start(pdev, 0); 3068 netdev->mem_end = pci_resource_end(pdev, 0); 3069 3070 /* PCI config space info */ 3071 hw->vendor_id = pdev->vendor; 3072 hw->device_id = pdev->device; 3073 hw->revision_id = pdev->revision; 3074 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3075 hw->subsystem_device_id = pdev->subsystem_device; 3076 3077 /* Copy the default MAC, PHY and NVM function pointers */ 3078 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3079 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3080 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3081 /* Initialize skew-specific constants */ 3082 err = ei->get_invariants(hw); 3083 if (err) 3084 goto err_sw_init; 3085 3086 /* setup the private structure */ 3087 err = igb_sw_init(adapter); 3088 if (err) 3089 goto err_sw_init; 3090 3091 igb_get_bus_info_pcie(hw); 3092 3093 hw->phy.autoneg_wait_to_complete = false; 3094 3095 /* Copper options */ 3096 if (hw->phy.media_type == e1000_media_type_copper) { 3097 hw->phy.mdix = AUTO_ALL_MODES; 3098 hw->phy.disable_polarity_correction = false; 3099 hw->phy.ms_type = e1000_ms_hw_default; 3100 } 3101 3102 if (igb_check_reset_block(hw)) 3103 dev_info(&pdev->dev, 3104 "PHY reset is blocked due to SOL/IDER session.\n"); 3105 3106 /* features is initialized to 0 in allocation, it might have bits 3107 * set by igb_sw_init so we should use an or instead of an 3108 * assignment. 3109 */ 3110 netdev->features |= NETIF_F_SG | 3111 NETIF_F_TSO | 3112 NETIF_F_TSO6 | 3113 NETIF_F_RXHASH | 3114 NETIF_F_RXCSUM | 3115 NETIF_F_HW_CSUM; 3116 3117 if (hw->mac.type >= e1000_82576) 3118 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 3119 3120 if (hw->mac.type >= e1000_i350) 3121 netdev->features |= NETIF_F_HW_TC; 3122 3123 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3124 NETIF_F_GSO_GRE_CSUM | \ 3125 NETIF_F_GSO_IPXIP4 | \ 3126 NETIF_F_GSO_IPXIP6 | \ 3127 NETIF_F_GSO_UDP_TUNNEL | \ 3128 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3129 3130 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3131 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3132 3133 /* copy netdev features into list of user selectable features */ 3134 netdev->hw_features |= netdev->features | 3135 NETIF_F_HW_VLAN_CTAG_RX | 3136 NETIF_F_HW_VLAN_CTAG_TX | 3137 NETIF_F_RXALL; 3138 3139 if (hw->mac.type >= e1000_i350) 3140 netdev->hw_features |= NETIF_F_NTUPLE; 3141 3142 if (pci_using_dac) 3143 netdev->features |= NETIF_F_HIGHDMA; 3144 3145 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3146 netdev->mpls_features |= NETIF_F_HW_CSUM; 3147 netdev->hw_enc_features |= netdev->vlan_features; 3148 3149 /* set this bit last since it cannot be part of vlan_features */ 3150 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3151 NETIF_F_HW_VLAN_CTAG_RX | 3152 NETIF_F_HW_VLAN_CTAG_TX; 3153 3154 netdev->priv_flags |= IFF_SUPP_NOFCS; 3155 3156 netdev->priv_flags |= IFF_UNICAST_FLT; 3157 3158 /* MTU range: 68 - 9216 */ 3159 netdev->min_mtu = ETH_MIN_MTU; 3160 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3161 3162 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3163 3164 /* before reading the NVM, reset the controller to put the device in a 3165 * known good starting state 3166 */ 3167 hw->mac.ops.reset_hw(hw); 3168 3169 /* make sure the NVM is good , i211/i210 parts can have special NVM 3170 * that doesn't contain a checksum 3171 */ 3172 switch (hw->mac.type) { 3173 case e1000_i210: 3174 case e1000_i211: 3175 if (igb_get_flash_presence_i210(hw)) { 3176 if (hw->nvm.ops.validate(hw) < 0) { 3177 dev_err(&pdev->dev, 3178 "The NVM Checksum Is Not Valid\n"); 3179 err = -EIO; 3180 goto err_eeprom; 3181 } 3182 } 3183 break; 3184 default: 3185 if (hw->nvm.ops.validate(hw) < 0) { 3186 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3187 err = -EIO; 3188 goto err_eeprom; 3189 } 3190 break; 3191 } 3192 3193 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3194 /* copy the MAC address out of the NVM */ 3195 if (hw->mac.ops.read_mac_addr(hw)) 3196 dev_err(&pdev->dev, "NVM Read Error\n"); 3197 } 3198 3199 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 3200 3201 if (!is_valid_ether_addr(netdev->dev_addr)) { 3202 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3203 err = -EIO; 3204 goto err_eeprom; 3205 } 3206 3207 igb_set_default_mac_filter(adapter); 3208 3209 /* get firmware version for ethtool -i */ 3210 igb_set_fw_version(adapter); 3211 3212 /* configure RXPBSIZE and TXPBSIZE */ 3213 if (hw->mac.type == e1000_i210) { 3214 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3215 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3216 } 3217 3218 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3219 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3220 3221 INIT_WORK(&adapter->reset_task, igb_reset_task); 3222 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3223 3224 /* Initialize link properties that are user-changeable */ 3225 adapter->fc_autoneg = true; 3226 hw->mac.autoneg = true; 3227 hw->phy.autoneg_advertised = 0x2f; 3228 3229 hw->fc.requested_mode = e1000_fc_default; 3230 hw->fc.current_mode = e1000_fc_default; 3231 3232 igb_validate_mdi_setting(hw); 3233 3234 /* By default, support wake on port A */ 3235 if (hw->bus.func == 0) 3236 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3237 3238 /* Check the NVM for wake support on non-port A ports */ 3239 if (hw->mac.type >= e1000_82580) 3240 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3241 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3242 &eeprom_data); 3243 else if (hw->bus.func == 1) 3244 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3245 3246 if (eeprom_data & IGB_EEPROM_APME) 3247 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3248 3249 /* now that we have the eeprom settings, apply the special cases where 3250 * the eeprom may be wrong or the board simply won't support wake on 3251 * lan on a particular port 3252 */ 3253 switch (pdev->device) { 3254 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3255 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3256 break; 3257 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3258 case E1000_DEV_ID_82576_FIBER: 3259 case E1000_DEV_ID_82576_SERDES: 3260 /* Wake events only supported on port A for dual fiber 3261 * regardless of eeprom setting 3262 */ 3263 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3264 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3265 break; 3266 case E1000_DEV_ID_82576_QUAD_COPPER: 3267 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3268 /* if quad port adapter, disable WoL on all but port A */ 3269 if (global_quad_port_a != 0) 3270 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3271 else 3272 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3273 /* Reset for multiple quad port adapters */ 3274 if (++global_quad_port_a == 4) 3275 global_quad_port_a = 0; 3276 break; 3277 default: 3278 /* If the device can't wake, don't set software support */ 3279 if (!device_can_wakeup(&adapter->pdev->dev)) 3280 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3281 } 3282 3283 /* initialize the wol settings based on the eeprom settings */ 3284 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3285 adapter->wol |= E1000_WUFC_MAG; 3286 3287 /* Some vendors want WoL disabled by default, but still supported */ 3288 if ((hw->mac.type == e1000_i350) && 3289 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3290 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3291 adapter->wol = 0; 3292 } 3293 3294 /* Some vendors want the ability to Use the EEPROM setting as 3295 * enable/disable only, and not for capability 3296 */ 3297 if (((hw->mac.type == e1000_i350) || 3298 (hw->mac.type == e1000_i354)) && 3299 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3300 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3301 adapter->wol = 0; 3302 } 3303 if (hw->mac.type == e1000_i350) { 3304 if (((pdev->subsystem_device == 0x5001) || 3305 (pdev->subsystem_device == 0x5002)) && 3306 (hw->bus.func == 0)) { 3307 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3308 adapter->wol = 0; 3309 } 3310 if (pdev->subsystem_device == 0x1F52) 3311 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3312 } 3313 3314 device_set_wakeup_enable(&adapter->pdev->dev, 3315 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3316 3317 /* reset the hardware with the new settings */ 3318 igb_reset(adapter); 3319 3320 /* Init the I2C interface */ 3321 err = igb_init_i2c(adapter); 3322 if (err) { 3323 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3324 goto err_eeprom; 3325 } 3326 3327 /* let the f/w know that the h/w is now under the control of the 3328 * driver. 3329 */ 3330 igb_get_hw_control(adapter); 3331 3332 strcpy(netdev->name, "eth%d"); 3333 err = register_netdev(netdev); 3334 if (err) 3335 goto err_register; 3336 3337 /* carrier off reporting is important to ethtool even BEFORE open */ 3338 netif_carrier_off(netdev); 3339 3340 #ifdef CONFIG_IGB_DCA 3341 if (dca_add_requester(&pdev->dev) == 0) { 3342 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3343 dev_info(&pdev->dev, "DCA enabled\n"); 3344 igb_setup_dca(adapter); 3345 } 3346 3347 #endif 3348 #ifdef CONFIG_IGB_HWMON 3349 /* Initialize the thermal sensor on i350 devices. */ 3350 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3351 u16 ets_word; 3352 3353 /* Read the NVM to determine if this i350 device supports an 3354 * external thermal sensor. 3355 */ 3356 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3357 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3358 adapter->ets = true; 3359 else 3360 adapter->ets = false; 3361 if (igb_sysfs_init(adapter)) 3362 dev_err(&pdev->dev, 3363 "failed to allocate sysfs resources\n"); 3364 } else { 3365 adapter->ets = false; 3366 } 3367 #endif 3368 /* Check if Media Autosense is enabled */ 3369 adapter->ei = *ei; 3370 if (hw->dev_spec._82575.mas_capable) 3371 igb_init_mas(adapter); 3372 3373 /* do hw tstamp init after resetting */ 3374 igb_ptp_init(adapter); 3375 3376 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3377 /* print bus type/speed/width info, not applicable to i354 */ 3378 if (hw->mac.type != e1000_i354) { 3379 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3380 netdev->name, 3381 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3382 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3383 "unknown"), 3384 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3385 "Width x4" : 3386 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3387 "Width x2" : 3388 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3389 "Width x1" : "unknown"), netdev->dev_addr); 3390 } 3391 3392 if ((hw->mac.type >= e1000_i210 || 3393 igb_get_flash_presence_i210(hw))) { 3394 ret_val = igb_read_part_string(hw, part_str, 3395 E1000_PBANUM_LENGTH); 3396 } else { 3397 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3398 } 3399 3400 if (ret_val) 3401 strcpy(part_str, "Unknown"); 3402 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3403 dev_info(&pdev->dev, 3404 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3405 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3406 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3407 adapter->num_rx_queues, adapter->num_tx_queues); 3408 if (hw->phy.media_type == e1000_media_type_copper) { 3409 switch (hw->mac.type) { 3410 case e1000_i350: 3411 case e1000_i210: 3412 case e1000_i211: 3413 /* Enable EEE for internal copper PHY devices */ 3414 err = igb_set_eee_i350(hw, true, true); 3415 if ((!err) && 3416 (!hw->dev_spec._82575.eee_disable)) { 3417 adapter->eee_advert = 3418 MDIO_EEE_100TX | MDIO_EEE_1000T; 3419 adapter->flags |= IGB_FLAG_EEE; 3420 } 3421 break; 3422 case e1000_i354: 3423 if ((rd32(E1000_CTRL_EXT) & 3424 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3425 err = igb_set_eee_i354(hw, true, true); 3426 if ((!err) && 3427 (!hw->dev_spec._82575.eee_disable)) { 3428 adapter->eee_advert = 3429 MDIO_EEE_100TX | MDIO_EEE_1000T; 3430 adapter->flags |= IGB_FLAG_EEE; 3431 } 3432 } 3433 break; 3434 default: 3435 break; 3436 } 3437 } 3438 3439 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 3440 3441 pm_runtime_put_noidle(&pdev->dev); 3442 return 0; 3443 3444 err_register: 3445 igb_release_hw_control(adapter); 3446 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3447 err_eeprom: 3448 if (!igb_check_reset_block(hw)) 3449 igb_reset_phy(hw); 3450 3451 if (hw->flash_address) 3452 iounmap(hw->flash_address); 3453 err_sw_init: 3454 kfree(adapter->mac_table); 3455 kfree(adapter->shadow_vfta); 3456 igb_clear_interrupt_scheme(adapter); 3457 #ifdef CONFIG_PCI_IOV 3458 igb_disable_sriov(pdev); 3459 #endif 3460 pci_iounmap(pdev, adapter->io_addr); 3461 err_ioremap: 3462 free_netdev(netdev); 3463 err_alloc_etherdev: 3464 pci_release_mem_regions(pdev); 3465 err_pci_reg: 3466 err_dma: 3467 pci_disable_device(pdev); 3468 return err; 3469 } 3470 3471 #ifdef CONFIG_PCI_IOV 3472 static int igb_disable_sriov(struct pci_dev *pdev) 3473 { 3474 struct net_device *netdev = pci_get_drvdata(pdev); 3475 struct igb_adapter *adapter = netdev_priv(netdev); 3476 struct e1000_hw *hw = &adapter->hw; 3477 3478 /* reclaim resources allocated to VFs */ 3479 if (adapter->vf_data) { 3480 /* disable iov and allow time for transactions to clear */ 3481 if (pci_vfs_assigned(pdev)) { 3482 dev_warn(&pdev->dev, 3483 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3484 return -EPERM; 3485 } else { 3486 pci_disable_sriov(pdev); 3487 msleep(500); 3488 } 3489 3490 kfree(adapter->vf_mac_list); 3491 adapter->vf_mac_list = NULL; 3492 kfree(adapter->vf_data); 3493 adapter->vf_data = NULL; 3494 adapter->vfs_allocated_count = 0; 3495 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3496 wrfl(); 3497 msleep(100); 3498 dev_info(&pdev->dev, "IOV Disabled\n"); 3499 3500 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3501 adapter->flags |= IGB_FLAG_DMAC; 3502 } 3503 3504 return 0; 3505 } 3506 3507 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 3508 { 3509 struct net_device *netdev = pci_get_drvdata(pdev); 3510 struct igb_adapter *adapter = netdev_priv(netdev); 3511 int old_vfs = pci_num_vf(pdev); 3512 struct vf_mac_filter *mac_list; 3513 int err = 0; 3514 int num_vf_mac_filters, i; 3515 3516 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3517 err = -EPERM; 3518 goto out; 3519 } 3520 if (!num_vfs) 3521 goto out; 3522 3523 if (old_vfs) { 3524 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3525 old_vfs, max_vfs); 3526 adapter->vfs_allocated_count = old_vfs; 3527 } else 3528 adapter->vfs_allocated_count = num_vfs; 3529 3530 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3531 sizeof(struct vf_data_storage), GFP_KERNEL); 3532 3533 /* if allocation failed then we do not support SR-IOV */ 3534 if (!adapter->vf_data) { 3535 adapter->vfs_allocated_count = 0; 3536 err = -ENOMEM; 3537 goto out; 3538 } 3539 3540 /* Due to the limited number of RAR entries calculate potential 3541 * number of MAC filters available for the VFs. Reserve entries 3542 * for PF default MAC, PF MAC filters and at least one RAR entry 3543 * for each VF for VF MAC. 3544 */ 3545 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3546 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3547 adapter->vfs_allocated_count); 3548 3549 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3550 sizeof(struct vf_mac_filter), 3551 GFP_KERNEL); 3552 3553 mac_list = adapter->vf_mac_list; 3554 INIT_LIST_HEAD(&adapter->vf_macs.l); 3555 3556 if (adapter->vf_mac_list) { 3557 /* Initialize list of VF MAC filters */ 3558 for (i = 0; i < num_vf_mac_filters; i++) { 3559 mac_list->vf = -1; 3560 mac_list->free = true; 3561 list_add(&mac_list->l, &adapter->vf_macs.l); 3562 mac_list++; 3563 } 3564 } else { 3565 /* If we could not allocate memory for the VF MAC filters 3566 * we can continue without this feature but warn user. 3567 */ 3568 dev_err(&pdev->dev, 3569 "Unable to allocate memory for VF MAC filter list\n"); 3570 } 3571 3572 /* only call pci_enable_sriov() if no VFs are allocated already */ 3573 if (!old_vfs) { 3574 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3575 if (err) 3576 goto err_out; 3577 } 3578 dev_info(&pdev->dev, "%d VFs allocated\n", 3579 adapter->vfs_allocated_count); 3580 for (i = 0; i < adapter->vfs_allocated_count; i++) 3581 igb_vf_configure(adapter, i); 3582 3583 /* DMA Coalescing is not supported in IOV mode. */ 3584 adapter->flags &= ~IGB_FLAG_DMAC; 3585 goto out; 3586 3587 err_out: 3588 kfree(adapter->vf_mac_list); 3589 adapter->vf_mac_list = NULL; 3590 kfree(adapter->vf_data); 3591 adapter->vf_data = NULL; 3592 adapter->vfs_allocated_count = 0; 3593 out: 3594 return err; 3595 } 3596 3597 #endif 3598 /** 3599 * igb_remove_i2c - Cleanup I2C interface 3600 * @adapter: pointer to adapter structure 3601 **/ 3602 static void igb_remove_i2c(struct igb_adapter *adapter) 3603 { 3604 /* free the adapter bus structure */ 3605 i2c_del_adapter(&adapter->i2c_adap); 3606 } 3607 3608 /** 3609 * igb_remove - Device Removal Routine 3610 * @pdev: PCI device information struct 3611 * 3612 * igb_remove is called by the PCI subsystem to alert the driver 3613 * that it should release a PCI device. The could be caused by a 3614 * Hot-Plug event, or because the driver is going to be removed from 3615 * memory. 3616 **/ 3617 static void igb_remove(struct pci_dev *pdev) 3618 { 3619 struct net_device *netdev = pci_get_drvdata(pdev); 3620 struct igb_adapter *adapter = netdev_priv(netdev); 3621 struct e1000_hw *hw = &adapter->hw; 3622 3623 pm_runtime_get_noresume(&pdev->dev); 3624 #ifdef CONFIG_IGB_HWMON 3625 igb_sysfs_exit(adapter); 3626 #endif 3627 igb_remove_i2c(adapter); 3628 igb_ptp_stop(adapter); 3629 /* The watchdog timer may be rescheduled, so explicitly 3630 * disable watchdog from being rescheduled. 3631 */ 3632 set_bit(__IGB_DOWN, &adapter->state); 3633 del_timer_sync(&adapter->watchdog_timer); 3634 del_timer_sync(&adapter->phy_info_timer); 3635 3636 cancel_work_sync(&adapter->reset_task); 3637 cancel_work_sync(&adapter->watchdog_task); 3638 3639 #ifdef CONFIG_IGB_DCA 3640 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3641 dev_info(&pdev->dev, "DCA disabled\n"); 3642 dca_remove_requester(&pdev->dev); 3643 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3644 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3645 } 3646 #endif 3647 3648 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3649 * would have already happened in close and is redundant. 3650 */ 3651 igb_release_hw_control(adapter); 3652 3653 #ifdef CONFIG_PCI_IOV 3654 igb_disable_sriov(pdev); 3655 #endif 3656 3657 unregister_netdev(netdev); 3658 3659 igb_clear_interrupt_scheme(adapter); 3660 3661 pci_iounmap(pdev, adapter->io_addr); 3662 if (hw->flash_address) 3663 iounmap(hw->flash_address); 3664 pci_release_mem_regions(pdev); 3665 3666 kfree(adapter->mac_table); 3667 kfree(adapter->shadow_vfta); 3668 free_netdev(netdev); 3669 3670 pci_disable_pcie_error_reporting(pdev); 3671 3672 pci_disable_device(pdev); 3673 } 3674 3675 /** 3676 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3677 * @adapter: board private structure to initialize 3678 * 3679 * This function initializes the vf specific data storage and then attempts to 3680 * allocate the VFs. The reason for ordering it this way is because it is much 3681 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3682 * the memory for the VFs. 3683 **/ 3684 static void igb_probe_vfs(struct igb_adapter *adapter) 3685 { 3686 #ifdef CONFIG_PCI_IOV 3687 struct pci_dev *pdev = adapter->pdev; 3688 struct e1000_hw *hw = &adapter->hw; 3689 3690 /* Virtualization features not supported on i210 family. */ 3691 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 3692 return; 3693 3694 /* Of the below we really only want the effect of getting 3695 * IGB_FLAG_HAS_MSIX set (if available), without which 3696 * igb_enable_sriov() has no effect. 3697 */ 3698 igb_set_interrupt_capability(adapter, true); 3699 igb_reset_interrupt_capability(adapter); 3700 3701 pci_sriov_set_totalvfs(pdev, 7); 3702 igb_enable_sriov(pdev, max_vfs); 3703 3704 #endif /* CONFIG_PCI_IOV */ 3705 } 3706 3707 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3708 { 3709 struct e1000_hw *hw = &adapter->hw; 3710 unsigned int max_rss_queues; 3711 3712 /* Determine the maximum number of RSS queues supported. */ 3713 switch (hw->mac.type) { 3714 case e1000_i211: 3715 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3716 break; 3717 case e1000_82575: 3718 case e1000_i210: 3719 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3720 break; 3721 case e1000_i350: 3722 /* I350 cannot do RSS and SR-IOV at the same time */ 3723 if (!!adapter->vfs_allocated_count) { 3724 max_rss_queues = 1; 3725 break; 3726 } 3727 fallthrough; 3728 case e1000_82576: 3729 if (!!adapter->vfs_allocated_count) { 3730 max_rss_queues = 2; 3731 break; 3732 } 3733 fallthrough; 3734 case e1000_82580: 3735 case e1000_i354: 3736 default: 3737 max_rss_queues = IGB_MAX_RX_QUEUES; 3738 break; 3739 } 3740 3741 return max_rss_queues; 3742 } 3743 3744 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3745 { 3746 u32 max_rss_queues; 3747 3748 max_rss_queues = igb_get_max_rss_queues(adapter); 3749 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3750 3751 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3752 } 3753 3754 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3755 const u32 max_rss_queues) 3756 { 3757 struct e1000_hw *hw = &adapter->hw; 3758 3759 /* Determine if we need to pair queues. */ 3760 switch (hw->mac.type) { 3761 case e1000_82575: 3762 case e1000_i211: 3763 /* Device supports enough interrupts without queue pairing. */ 3764 break; 3765 case e1000_82576: 3766 case e1000_82580: 3767 case e1000_i350: 3768 case e1000_i354: 3769 case e1000_i210: 3770 default: 3771 /* If rss_queues > half of max_rss_queues, pair the queues in 3772 * order to conserve interrupts due to limited supply. 3773 */ 3774 if (adapter->rss_queues > (max_rss_queues / 2)) 3775 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3776 else 3777 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 3778 break; 3779 } 3780 } 3781 3782 /** 3783 * igb_sw_init - Initialize general software structures (struct igb_adapter) 3784 * @adapter: board private structure to initialize 3785 * 3786 * igb_sw_init initializes the Adapter private data structure. 3787 * Fields are initialized based on PCI device information and 3788 * OS network device settings (MTU size). 3789 **/ 3790 static int igb_sw_init(struct igb_adapter *adapter) 3791 { 3792 struct e1000_hw *hw = &adapter->hw; 3793 struct net_device *netdev = adapter->netdev; 3794 struct pci_dev *pdev = adapter->pdev; 3795 3796 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 3797 3798 /* set default ring sizes */ 3799 adapter->tx_ring_count = IGB_DEFAULT_TXD; 3800 adapter->rx_ring_count = IGB_DEFAULT_RXD; 3801 3802 /* set default ITR values */ 3803 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 3804 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 3805 3806 /* set default work limits */ 3807 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 3808 3809 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 3810 VLAN_HLEN; 3811 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 3812 3813 spin_lock_init(&adapter->nfc_lock); 3814 spin_lock_init(&adapter->stats64_lock); 3815 #ifdef CONFIG_PCI_IOV 3816 switch (hw->mac.type) { 3817 case e1000_82576: 3818 case e1000_i350: 3819 if (max_vfs > 7) { 3820 dev_warn(&pdev->dev, 3821 "Maximum of 7 VFs per PF, using max\n"); 3822 max_vfs = adapter->vfs_allocated_count = 7; 3823 } else 3824 adapter->vfs_allocated_count = max_vfs; 3825 if (adapter->vfs_allocated_count) 3826 dev_warn(&pdev->dev, 3827 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 3828 break; 3829 default: 3830 break; 3831 } 3832 #endif /* CONFIG_PCI_IOV */ 3833 3834 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 3835 adapter->flags |= IGB_FLAG_HAS_MSIX; 3836 3837 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 3838 sizeof(struct igb_mac_addr), 3839 GFP_KERNEL); 3840 if (!adapter->mac_table) 3841 return -ENOMEM; 3842 3843 igb_probe_vfs(adapter); 3844 3845 igb_init_queue_configuration(adapter); 3846 3847 /* Setup and initialize a copy of the hw vlan table array */ 3848 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 3849 GFP_KERNEL); 3850 if (!adapter->shadow_vfta) 3851 return -ENOMEM; 3852 3853 /* This call may decrease the number of queues */ 3854 if (igb_init_interrupt_scheme(adapter, true)) { 3855 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3856 return -ENOMEM; 3857 } 3858 3859 /* Explicitly disable IRQ since the NIC can be in any state. */ 3860 igb_irq_disable(adapter); 3861 3862 if (hw->mac.type >= e1000_i350) 3863 adapter->flags &= ~IGB_FLAG_DMAC; 3864 3865 set_bit(__IGB_DOWN, &adapter->state); 3866 return 0; 3867 } 3868 3869 /** 3870 * igb_open - Called when a network interface is made active 3871 * @netdev: network interface device structure 3872 * 3873 * Returns 0 on success, negative value on failure 3874 * 3875 * The open entry point is called when a network interface is made 3876 * active by the system (IFF_UP). At this point all resources needed 3877 * for transmit and receive operations are allocated, the interrupt 3878 * handler is registered with the OS, the watchdog timer is started, 3879 * and the stack is notified that the interface is ready. 3880 **/ 3881 static int __igb_open(struct net_device *netdev, bool resuming) 3882 { 3883 struct igb_adapter *adapter = netdev_priv(netdev); 3884 struct e1000_hw *hw = &adapter->hw; 3885 struct pci_dev *pdev = adapter->pdev; 3886 int err; 3887 int i; 3888 3889 /* disallow open during test */ 3890 if (test_bit(__IGB_TESTING, &adapter->state)) { 3891 WARN_ON(resuming); 3892 return -EBUSY; 3893 } 3894 3895 if (!resuming) 3896 pm_runtime_get_sync(&pdev->dev); 3897 3898 netif_carrier_off(netdev); 3899 3900 /* allocate transmit descriptors */ 3901 err = igb_setup_all_tx_resources(adapter); 3902 if (err) 3903 goto err_setup_tx; 3904 3905 /* allocate receive descriptors */ 3906 err = igb_setup_all_rx_resources(adapter); 3907 if (err) 3908 goto err_setup_rx; 3909 3910 igb_power_up_link(adapter); 3911 3912 /* before we allocate an interrupt, we must be ready to handle it. 3913 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3914 * as soon as we call pci_request_irq, so we have to setup our 3915 * clean_rx handler before we do so. 3916 */ 3917 igb_configure(adapter); 3918 3919 err = igb_request_irq(adapter); 3920 if (err) 3921 goto err_req_irq; 3922 3923 /* Notify the stack of the actual queue counts. */ 3924 err = netif_set_real_num_tx_queues(adapter->netdev, 3925 adapter->num_tx_queues); 3926 if (err) 3927 goto err_set_queues; 3928 3929 err = netif_set_real_num_rx_queues(adapter->netdev, 3930 adapter->num_rx_queues); 3931 if (err) 3932 goto err_set_queues; 3933 3934 /* From here on the code is the same as igb_up() */ 3935 clear_bit(__IGB_DOWN, &adapter->state); 3936 3937 for (i = 0; i < adapter->num_q_vectors; i++) 3938 napi_enable(&(adapter->q_vector[i]->napi)); 3939 3940 /* Clear any pending interrupts. */ 3941 rd32(E1000_TSICR); 3942 rd32(E1000_ICR); 3943 3944 igb_irq_enable(adapter); 3945 3946 /* notify VFs that reset has been completed */ 3947 if (adapter->vfs_allocated_count) { 3948 u32 reg_data = rd32(E1000_CTRL_EXT); 3949 3950 reg_data |= E1000_CTRL_EXT_PFRSTD; 3951 wr32(E1000_CTRL_EXT, reg_data); 3952 } 3953 3954 netif_tx_start_all_queues(netdev); 3955 3956 if (!resuming) 3957 pm_runtime_put(&pdev->dev); 3958 3959 /* start the watchdog. */ 3960 hw->mac.get_link_status = 1; 3961 schedule_work(&adapter->watchdog_task); 3962 3963 return 0; 3964 3965 err_set_queues: 3966 igb_free_irq(adapter); 3967 err_req_irq: 3968 igb_release_hw_control(adapter); 3969 igb_power_down_link(adapter); 3970 igb_free_all_rx_resources(adapter); 3971 err_setup_rx: 3972 igb_free_all_tx_resources(adapter); 3973 err_setup_tx: 3974 igb_reset(adapter); 3975 if (!resuming) 3976 pm_runtime_put(&pdev->dev); 3977 3978 return err; 3979 } 3980 3981 int igb_open(struct net_device *netdev) 3982 { 3983 return __igb_open(netdev, false); 3984 } 3985 3986 /** 3987 * igb_close - Disables a network interface 3988 * @netdev: network interface device structure 3989 * 3990 * Returns 0, this is not allowed to fail 3991 * 3992 * The close entry point is called when an interface is de-activated 3993 * by the OS. The hardware is still under the driver's control, but 3994 * needs to be disabled. A global MAC reset is issued to stop the 3995 * hardware, and all transmit and receive resources are freed. 3996 **/ 3997 static int __igb_close(struct net_device *netdev, bool suspending) 3998 { 3999 struct igb_adapter *adapter = netdev_priv(netdev); 4000 struct pci_dev *pdev = adapter->pdev; 4001 4002 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4003 4004 if (!suspending) 4005 pm_runtime_get_sync(&pdev->dev); 4006 4007 igb_down(adapter); 4008 igb_free_irq(adapter); 4009 4010 igb_free_all_tx_resources(adapter); 4011 igb_free_all_rx_resources(adapter); 4012 4013 if (!suspending) 4014 pm_runtime_put_sync(&pdev->dev); 4015 return 0; 4016 } 4017 4018 int igb_close(struct net_device *netdev) 4019 { 4020 if (netif_device_present(netdev) || netdev->dismantle) 4021 return __igb_close(netdev, false); 4022 return 0; 4023 } 4024 4025 /** 4026 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4027 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4028 * 4029 * Return 0 on success, negative on failure 4030 **/ 4031 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4032 { 4033 struct device *dev = tx_ring->dev; 4034 int size; 4035 4036 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4037 4038 tx_ring->tx_buffer_info = vmalloc(size); 4039 if (!tx_ring->tx_buffer_info) 4040 goto err; 4041 4042 /* round up to nearest 4K */ 4043 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4044 tx_ring->size = ALIGN(tx_ring->size, 4096); 4045 4046 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4047 &tx_ring->dma, GFP_KERNEL); 4048 if (!tx_ring->desc) 4049 goto err; 4050 4051 tx_ring->next_to_use = 0; 4052 tx_ring->next_to_clean = 0; 4053 4054 return 0; 4055 4056 err: 4057 vfree(tx_ring->tx_buffer_info); 4058 tx_ring->tx_buffer_info = NULL; 4059 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4060 return -ENOMEM; 4061 } 4062 4063 /** 4064 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4065 * (Descriptors) for all queues 4066 * @adapter: board private structure 4067 * 4068 * Return 0 on success, negative on failure 4069 **/ 4070 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4071 { 4072 struct pci_dev *pdev = adapter->pdev; 4073 int i, err = 0; 4074 4075 for (i = 0; i < adapter->num_tx_queues; i++) { 4076 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4077 if (err) { 4078 dev_err(&pdev->dev, 4079 "Allocation for Tx Queue %u failed\n", i); 4080 for (i--; i >= 0; i--) 4081 igb_free_tx_resources(adapter->tx_ring[i]); 4082 break; 4083 } 4084 } 4085 4086 return err; 4087 } 4088 4089 /** 4090 * igb_setup_tctl - configure the transmit control registers 4091 * @adapter: Board private structure 4092 **/ 4093 void igb_setup_tctl(struct igb_adapter *adapter) 4094 { 4095 struct e1000_hw *hw = &adapter->hw; 4096 u32 tctl; 4097 4098 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4099 wr32(E1000_TXDCTL(0), 0); 4100 4101 /* Program the Transmit Control Register */ 4102 tctl = rd32(E1000_TCTL); 4103 tctl &= ~E1000_TCTL_CT; 4104 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4105 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4106 4107 igb_config_collision_dist(hw); 4108 4109 /* Enable transmits */ 4110 tctl |= E1000_TCTL_EN; 4111 4112 wr32(E1000_TCTL, tctl); 4113 } 4114 4115 /** 4116 * igb_configure_tx_ring - Configure transmit ring after Reset 4117 * @adapter: board private structure 4118 * @ring: tx ring to configure 4119 * 4120 * Configure a transmit ring after a reset. 4121 **/ 4122 void igb_configure_tx_ring(struct igb_adapter *adapter, 4123 struct igb_ring *ring) 4124 { 4125 struct e1000_hw *hw = &adapter->hw; 4126 u32 txdctl = 0; 4127 u64 tdba = ring->dma; 4128 int reg_idx = ring->reg_idx; 4129 4130 wr32(E1000_TDLEN(reg_idx), 4131 ring->count * sizeof(union e1000_adv_tx_desc)); 4132 wr32(E1000_TDBAL(reg_idx), 4133 tdba & 0x00000000ffffffffULL); 4134 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4135 4136 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4137 wr32(E1000_TDH(reg_idx), 0); 4138 writel(0, ring->tail); 4139 4140 txdctl |= IGB_TX_PTHRESH; 4141 txdctl |= IGB_TX_HTHRESH << 8; 4142 txdctl |= IGB_TX_WTHRESH << 16; 4143 4144 /* reinitialize tx_buffer_info */ 4145 memset(ring->tx_buffer_info, 0, 4146 sizeof(struct igb_tx_buffer) * ring->count); 4147 4148 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4149 wr32(E1000_TXDCTL(reg_idx), txdctl); 4150 } 4151 4152 /** 4153 * igb_configure_tx - Configure transmit Unit after Reset 4154 * @adapter: board private structure 4155 * 4156 * Configure the Tx unit of the MAC after a reset. 4157 **/ 4158 static void igb_configure_tx(struct igb_adapter *adapter) 4159 { 4160 struct e1000_hw *hw = &adapter->hw; 4161 int i; 4162 4163 /* disable the queues */ 4164 for (i = 0; i < adapter->num_tx_queues; i++) 4165 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4166 4167 wrfl(); 4168 usleep_range(10000, 20000); 4169 4170 for (i = 0; i < adapter->num_tx_queues; i++) 4171 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4172 } 4173 4174 /** 4175 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4176 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4177 * 4178 * Returns 0 on success, negative on failure 4179 **/ 4180 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4181 { 4182 struct device *dev = rx_ring->dev; 4183 int size; 4184 4185 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4186 4187 rx_ring->rx_buffer_info = vmalloc(size); 4188 if (!rx_ring->rx_buffer_info) 4189 goto err; 4190 4191 /* Round up to nearest 4K */ 4192 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4193 rx_ring->size = ALIGN(rx_ring->size, 4096); 4194 4195 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4196 &rx_ring->dma, GFP_KERNEL); 4197 if (!rx_ring->desc) 4198 goto err; 4199 4200 rx_ring->next_to_alloc = 0; 4201 rx_ring->next_to_clean = 0; 4202 rx_ring->next_to_use = 0; 4203 4204 return 0; 4205 4206 err: 4207 vfree(rx_ring->rx_buffer_info); 4208 rx_ring->rx_buffer_info = NULL; 4209 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4210 return -ENOMEM; 4211 } 4212 4213 /** 4214 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4215 * (Descriptors) for all queues 4216 * @adapter: board private structure 4217 * 4218 * Return 0 on success, negative on failure 4219 **/ 4220 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4221 { 4222 struct pci_dev *pdev = adapter->pdev; 4223 int i, err = 0; 4224 4225 for (i = 0; i < adapter->num_rx_queues; i++) { 4226 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4227 if (err) { 4228 dev_err(&pdev->dev, 4229 "Allocation for Rx Queue %u failed\n", i); 4230 for (i--; i >= 0; i--) 4231 igb_free_rx_resources(adapter->rx_ring[i]); 4232 break; 4233 } 4234 } 4235 4236 return err; 4237 } 4238 4239 /** 4240 * igb_setup_mrqc - configure the multiple receive queue control registers 4241 * @adapter: Board private structure 4242 **/ 4243 static void igb_setup_mrqc(struct igb_adapter *adapter) 4244 { 4245 struct e1000_hw *hw = &adapter->hw; 4246 u32 mrqc, rxcsum; 4247 u32 j, num_rx_queues; 4248 u32 rss_key[10]; 4249 4250 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4251 for (j = 0; j < 10; j++) 4252 wr32(E1000_RSSRK(j), rss_key[j]); 4253 4254 num_rx_queues = adapter->rss_queues; 4255 4256 switch (hw->mac.type) { 4257 case e1000_82576: 4258 /* 82576 supports 2 RSS queues for SR-IOV */ 4259 if (adapter->vfs_allocated_count) 4260 num_rx_queues = 2; 4261 break; 4262 default: 4263 break; 4264 } 4265 4266 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4267 for (j = 0; j < IGB_RETA_SIZE; j++) 4268 adapter->rss_indir_tbl[j] = 4269 (j * num_rx_queues) / IGB_RETA_SIZE; 4270 adapter->rss_indir_tbl_init = num_rx_queues; 4271 } 4272 igb_write_rss_indir_tbl(adapter); 4273 4274 /* Disable raw packet checksumming so that RSS hash is placed in 4275 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4276 * offloads as they are enabled by default 4277 */ 4278 rxcsum = rd32(E1000_RXCSUM); 4279 rxcsum |= E1000_RXCSUM_PCSD; 4280 4281 if (adapter->hw.mac.type >= e1000_82576) 4282 /* Enable Receive Checksum Offload for SCTP */ 4283 rxcsum |= E1000_RXCSUM_CRCOFL; 4284 4285 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4286 wr32(E1000_RXCSUM, rxcsum); 4287 4288 /* Generate RSS hash based on packet types, TCP/UDP 4289 * port numbers and/or IPv4/v6 src and dst addresses 4290 */ 4291 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4292 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4293 E1000_MRQC_RSS_FIELD_IPV6 | 4294 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4295 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4296 4297 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4298 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4299 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4300 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4301 4302 /* If VMDq is enabled then we set the appropriate mode for that, else 4303 * we default to RSS so that an RSS hash is calculated per packet even 4304 * if we are only using one queue 4305 */ 4306 if (adapter->vfs_allocated_count) { 4307 if (hw->mac.type > e1000_82575) { 4308 /* Set the default pool for the PF's first queue */ 4309 u32 vtctl = rd32(E1000_VT_CTL); 4310 4311 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4312 E1000_VT_CTL_DISABLE_DEF_POOL); 4313 vtctl |= adapter->vfs_allocated_count << 4314 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4315 wr32(E1000_VT_CTL, vtctl); 4316 } 4317 if (adapter->rss_queues > 1) 4318 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4319 else 4320 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4321 } else { 4322 if (hw->mac.type != e1000_i211) 4323 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4324 } 4325 igb_vmm_control(adapter); 4326 4327 wr32(E1000_MRQC, mrqc); 4328 } 4329 4330 /** 4331 * igb_setup_rctl - configure the receive control registers 4332 * @adapter: Board private structure 4333 **/ 4334 void igb_setup_rctl(struct igb_adapter *adapter) 4335 { 4336 struct e1000_hw *hw = &adapter->hw; 4337 u32 rctl; 4338 4339 rctl = rd32(E1000_RCTL); 4340 4341 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4342 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4343 4344 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4345 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4346 4347 /* enable stripping of CRC. It's unlikely this will break BMC 4348 * redirection as it did with e1000. Newer features require 4349 * that the HW strips the CRC. 4350 */ 4351 rctl |= E1000_RCTL_SECRC; 4352 4353 /* disable store bad packets and clear size bits. */ 4354 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4355 4356 /* enable LPE to allow for reception of jumbo frames */ 4357 rctl |= E1000_RCTL_LPE; 4358 4359 /* disable queue 0 to prevent tail write w/o re-config */ 4360 wr32(E1000_RXDCTL(0), 0); 4361 4362 /* Attention!!! For SR-IOV PF driver operations you must enable 4363 * queue drop for all VF and PF queues to prevent head of line blocking 4364 * if an un-trusted VF does not provide descriptors to hardware. 4365 */ 4366 if (adapter->vfs_allocated_count) { 4367 /* set all queue drop enable bits */ 4368 wr32(E1000_QDE, ALL_QUEUES); 4369 } 4370 4371 /* This is useful for sniffing bad packets. */ 4372 if (adapter->netdev->features & NETIF_F_RXALL) { 4373 /* UPE and MPE will be handled by normal PROMISC logic 4374 * in e1000e_set_rx_mode 4375 */ 4376 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4377 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4378 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4379 4380 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4381 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4382 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4383 * and that breaks VLANs. 4384 */ 4385 } 4386 4387 wr32(E1000_RCTL, rctl); 4388 } 4389 4390 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4391 int vfn) 4392 { 4393 struct e1000_hw *hw = &adapter->hw; 4394 u32 vmolr; 4395 4396 if (size > MAX_JUMBO_FRAME_SIZE) 4397 size = MAX_JUMBO_FRAME_SIZE; 4398 4399 vmolr = rd32(E1000_VMOLR(vfn)); 4400 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4401 vmolr |= size | E1000_VMOLR_LPE; 4402 wr32(E1000_VMOLR(vfn), vmolr); 4403 4404 return 0; 4405 } 4406 4407 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4408 int vfn, bool enable) 4409 { 4410 struct e1000_hw *hw = &adapter->hw; 4411 u32 val, reg; 4412 4413 if (hw->mac.type < e1000_82576) 4414 return; 4415 4416 if (hw->mac.type == e1000_i350) 4417 reg = E1000_DVMOLR(vfn); 4418 else 4419 reg = E1000_VMOLR(vfn); 4420 4421 val = rd32(reg); 4422 if (enable) 4423 val |= E1000_VMOLR_STRVLAN; 4424 else 4425 val &= ~(E1000_VMOLR_STRVLAN); 4426 wr32(reg, val); 4427 } 4428 4429 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4430 int vfn, bool aupe) 4431 { 4432 struct e1000_hw *hw = &adapter->hw; 4433 u32 vmolr; 4434 4435 /* This register exists only on 82576 and newer so if we are older then 4436 * we should exit and do nothing 4437 */ 4438 if (hw->mac.type < e1000_82576) 4439 return; 4440 4441 vmolr = rd32(E1000_VMOLR(vfn)); 4442 if (aupe) 4443 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4444 else 4445 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4446 4447 /* clear all bits that might not be set */ 4448 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4449 4450 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4451 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4452 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4453 * multicast packets 4454 */ 4455 if (vfn <= adapter->vfs_allocated_count) 4456 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4457 4458 wr32(E1000_VMOLR(vfn), vmolr); 4459 } 4460 4461 /** 4462 * igb_setup_srrctl - configure the split and replication receive control 4463 * registers 4464 * @adapter: Board private structure 4465 * @ring: receive ring to be configured 4466 **/ 4467 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring) 4468 { 4469 struct e1000_hw *hw = &adapter->hw; 4470 int reg_idx = ring->reg_idx; 4471 u32 srrctl = 0; 4472 4473 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4474 if (ring_uses_large_buffer(ring)) 4475 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4476 else 4477 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4478 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4479 if (hw->mac.type >= e1000_82580) 4480 srrctl |= E1000_SRRCTL_TIMESTAMP; 4481 /* Only set Drop Enable if VFs allocated, or we are supporting multiple 4482 * queues and rx flow control is disabled 4483 */ 4484 if (adapter->vfs_allocated_count || 4485 (!(hw->fc.current_mode & e1000_fc_rx_pause) && 4486 adapter->num_rx_queues > 1)) 4487 srrctl |= E1000_SRRCTL_DROP_EN; 4488 4489 wr32(E1000_SRRCTL(reg_idx), srrctl); 4490 } 4491 4492 /** 4493 * igb_configure_rx_ring - Configure a receive ring after Reset 4494 * @adapter: board private structure 4495 * @ring: receive ring to be configured 4496 * 4497 * Configure the Rx unit of the MAC after a reset. 4498 **/ 4499 void igb_configure_rx_ring(struct igb_adapter *adapter, 4500 struct igb_ring *ring) 4501 { 4502 struct e1000_hw *hw = &adapter->hw; 4503 union e1000_adv_rx_desc *rx_desc; 4504 u64 rdba = ring->dma; 4505 int reg_idx = ring->reg_idx; 4506 u32 rxdctl = 0; 4507 4508 /* disable the queue */ 4509 wr32(E1000_RXDCTL(reg_idx), 0); 4510 4511 /* Set DMA base address registers */ 4512 wr32(E1000_RDBAL(reg_idx), 4513 rdba & 0x00000000ffffffffULL); 4514 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4515 wr32(E1000_RDLEN(reg_idx), 4516 ring->count * sizeof(union e1000_adv_rx_desc)); 4517 4518 /* initialize head and tail */ 4519 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4520 wr32(E1000_RDH(reg_idx), 0); 4521 writel(0, ring->tail); 4522 4523 /* set descriptor configuration */ 4524 igb_setup_srrctl(adapter, ring); 4525 4526 /* set filtering for VMDQ pools */ 4527 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4528 4529 rxdctl |= IGB_RX_PTHRESH; 4530 rxdctl |= IGB_RX_HTHRESH << 8; 4531 rxdctl |= IGB_RX_WTHRESH << 16; 4532 4533 /* initialize rx_buffer_info */ 4534 memset(ring->rx_buffer_info, 0, 4535 sizeof(struct igb_rx_buffer) * ring->count); 4536 4537 /* initialize Rx descriptor 0 */ 4538 rx_desc = IGB_RX_DESC(ring, 0); 4539 rx_desc->wb.upper.length = 0; 4540 4541 /* enable receive descriptor fetching */ 4542 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4543 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4544 } 4545 4546 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4547 struct igb_ring *rx_ring) 4548 { 4549 /* set build_skb and buffer size flags */ 4550 clear_ring_build_skb_enabled(rx_ring); 4551 clear_ring_uses_large_buffer(rx_ring); 4552 4553 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4554 return; 4555 4556 set_ring_build_skb_enabled(rx_ring); 4557 4558 #if (PAGE_SIZE < 8192) 4559 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4560 return; 4561 4562 set_ring_uses_large_buffer(rx_ring); 4563 #endif 4564 } 4565 4566 /** 4567 * igb_configure_rx - Configure receive Unit after Reset 4568 * @adapter: board private structure 4569 * 4570 * Configure the Rx unit of the MAC after a reset. 4571 **/ 4572 static void igb_configure_rx(struct igb_adapter *adapter) 4573 { 4574 int i; 4575 4576 /* set the correct pool for the PF default MAC address in entry 0 */ 4577 igb_set_default_mac_filter(adapter); 4578 4579 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4580 * the Base and Length of the Rx Descriptor Ring 4581 */ 4582 for (i = 0; i < adapter->num_rx_queues; i++) { 4583 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4584 4585 igb_set_rx_buffer_len(adapter, rx_ring); 4586 igb_configure_rx_ring(adapter, rx_ring); 4587 } 4588 } 4589 4590 /** 4591 * igb_free_tx_resources - Free Tx Resources per Queue 4592 * @tx_ring: Tx descriptor ring for a specific queue 4593 * 4594 * Free all transmit software resources 4595 **/ 4596 void igb_free_tx_resources(struct igb_ring *tx_ring) 4597 { 4598 igb_clean_tx_ring(tx_ring); 4599 4600 vfree(tx_ring->tx_buffer_info); 4601 tx_ring->tx_buffer_info = NULL; 4602 4603 /* if not set, then don't free */ 4604 if (!tx_ring->desc) 4605 return; 4606 4607 dma_free_coherent(tx_ring->dev, tx_ring->size, 4608 tx_ring->desc, tx_ring->dma); 4609 4610 tx_ring->desc = NULL; 4611 } 4612 4613 /** 4614 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4615 * @adapter: board private structure 4616 * 4617 * Free all transmit software resources 4618 **/ 4619 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4620 { 4621 int i; 4622 4623 for (i = 0; i < adapter->num_tx_queues; i++) 4624 if (adapter->tx_ring[i]) 4625 igb_free_tx_resources(adapter->tx_ring[i]); 4626 } 4627 4628 /** 4629 * igb_clean_tx_ring - Free Tx Buffers 4630 * @tx_ring: ring to be cleaned 4631 **/ 4632 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 4633 { 4634 u16 i = tx_ring->next_to_clean; 4635 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4636 4637 while (i != tx_ring->next_to_use) { 4638 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4639 4640 /* Free all the Tx ring sk_buffs */ 4641 dev_kfree_skb_any(tx_buffer->skb); 4642 4643 /* unmap skb header data */ 4644 dma_unmap_single(tx_ring->dev, 4645 dma_unmap_addr(tx_buffer, dma), 4646 dma_unmap_len(tx_buffer, len), 4647 DMA_TO_DEVICE); 4648 4649 /* check for eop_desc to determine the end of the packet */ 4650 eop_desc = tx_buffer->next_to_watch; 4651 tx_desc = IGB_TX_DESC(tx_ring, i); 4652 4653 /* unmap remaining buffers */ 4654 while (tx_desc != eop_desc) { 4655 tx_buffer++; 4656 tx_desc++; 4657 i++; 4658 if (unlikely(i == tx_ring->count)) { 4659 i = 0; 4660 tx_buffer = tx_ring->tx_buffer_info; 4661 tx_desc = IGB_TX_DESC(tx_ring, 0); 4662 } 4663 4664 /* unmap any remaining paged data */ 4665 if (dma_unmap_len(tx_buffer, len)) 4666 dma_unmap_page(tx_ring->dev, 4667 dma_unmap_addr(tx_buffer, dma), 4668 dma_unmap_len(tx_buffer, len), 4669 DMA_TO_DEVICE); 4670 } 4671 4672 /* move us one more past the eop_desc for start of next pkt */ 4673 tx_buffer++; 4674 i++; 4675 if (unlikely(i == tx_ring->count)) { 4676 i = 0; 4677 tx_buffer = tx_ring->tx_buffer_info; 4678 } 4679 } 4680 4681 /* reset BQL for queue */ 4682 netdev_tx_reset_queue(txring_txq(tx_ring)); 4683 4684 /* reset next_to_use and next_to_clean */ 4685 tx_ring->next_to_use = 0; 4686 tx_ring->next_to_clean = 0; 4687 } 4688 4689 /** 4690 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 4691 * @adapter: board private structure 4692 **/ 4693 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 4694 { 4695 int i; 4696 4697 for (i = 0; i < adapter->num_tx_queues; i++) 4698 if (adapter->tx_ring[i]) 4699 igb_clean_tx_ring(adapter->tx_ring[i]); 4700 } 4701 4702 /** 4703 * igb_free_rx_resources - Free Rx Resources 4704 * @rx_ring: ring to clean the resources from 4705 * 4706 * Free all receive software resources 4707 **/ 4708 void igb_free_rx_resources(struct igb_ring *rx_ring) 4709 { 4710 igb_clean_rx_ring(rx_ring); 4711 4712 vfree(rx_ring->rx_buffer_info); 4713 rx_ring->rx_buffer_info = NULL; 4714 4715 /* if not set, then don't free */ 4716 if (!rx_ring->desc) 4717 return; 4718 4719 dma_free_coherent(rx_ring->dev, rx_ring->size, 4720 rx_ring->desc, rx_ring->dma); 4721 4722 rx_ring->desc = NULL; 4723 } 4724 4725 /** 4726 * igb_free_all_rx_resources - Free Rx Resources for All Queues 4727 * @adapter: board private structure 4728 * 4729 * Free all receive software resources 4730 **/ 4731 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 4732 { 4733 int i; 4734 4735 for (i = 0; i < adapter->num_rx_queues; i++) 4736 if (adapter->rx_ring[i]) 4737 igb_free_rx_resources(adapter->rx_ring[i]); 4738 } 4739 4740 /** 4741 * igb_clean_rx_ring - Free Rx Buffers per Queue 4742 * @rx_ring: ring to free buffers from 4743 **/ 4744 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 4745 { 4746 u16 i = rx_ring->next_to_clean; 4747 4748 dev_kfree_skb(rx_ring->skb); 4749 rx_ring->skb = NULL; 4750 4751 /* Free all the Rx ring sk_buffs */ 4752 while (i != rx_ring->next_to_alloc) { 4753 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 4754 4755 /* Invalidate cache lines that may have been written to by 4756 * device so that we avoid corrupting memory. 4757 */ 4758 dma_sync_single_range_for_cpu(rx_ring->dev, 4759 buffer_info->dma, 4760 buffer_info->page_offset, 4761 igb_rx_bufsz(rx_ring), 4762 DMA_FROM_DEVICE); 4763 4764 /* free resources associated with mapping */ 4765 dma_unmap_page_attrs(rx_ring->dev, 4766 buffer_info->dma, 4767 igb_rx_pg_size(rx_ring), 4768 DMA_FROM_DEVICE, 4769 IGB_RX_DMA_ATTR); 4770 __page_frag_cache_drain(buffer_info->page, 4771 buffer_info->pagecnt_bias); 4772 4773 i++; 4774 if (i == rx_ring->count) 4775 i = 0; 4776 } 4777 4778 rx_ring->next_to_alloc = 0; 4779 rx_ring->next_to_clean = 0; 4780 rx_ring->next_to_use = 0; 4781 } 4782 4783 /** 4784 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 4785 * @adapter: board private structure 4786 **/ 4787 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 4788 { 4789 int i; 4790 4791 for (i = 0; i < adapter->num_rx_queues; i++) 4792 if (adapter->rx_ring[i]) 4793 igb_clean_rx_ring(adapter->rx_ring[i]); 4794 } 4795 4796 /** 4797 * igb_set_mac - Change the Ethernet Address of the NIC 4798 * @netdev: network interface device structure 4799 * @p: pointer to an address structure 4800 * 4801 * Returns 0 on success, negative on failure 4802 **/ 4803 static int igb_set_mac(struct net_device *netdev, void *p) 4804 { 4805 struct igb_adapter *adapter = netdev_priv(netdev); 4806 struct e1000_hw *hw = &adapter->hw; 4807 struct sockaddr *addr = p; 4808 4809 if (!is_valid_ether_addr(addr->sa_data)) 4810 return -EADDRNOTAVAIL; 4811 4812 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4813 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 4814 4815 /* set the correct pool for the new PF MAC address in entry 0 */ 4816 igb_set_default_mac_filter(adapter); 4817 4818 return 0; 4819 } 4820 4821 /** 4822 * igb_write_mc_addr_list - write multicast addresses to MTA 4823 * @netdev: network interface device structure 4824 * 4825 * Writes multicast address list to the MTA hash table. 4826 * Returns: -ENOMEM on failure 4827 * 0 on no addresses written 4828 * X on writing X addresses to MTA 4829 **/ 4830 static int igb_write_mc_addr_list(struct net_device *netdev) 4831 { 4832 struct igb_adapter *adapter = netdev_priv(netdev); 4833 struct e1000_hw *hw = &adapter->hw; 4834 struct netdev_hw_addr *ha; 4835 u8 *mta_list; 4836 int i; 4837 4838 if (netdev_mc_empty(netdev)) { 4839 /* nothing to program, so clear mc list */ 4840 igb_update_mc_addr_list(hw, NULL, 0); 4841 igb_restore_vf_multicasts(adapter); 4842 return 0; 4843 } 4844 4845 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 4846 if (!mta_list) 4847 return -ENOMEM; 4848 4849 /* The shared function expects a packed array of only addresses. */ 4850 i = 0; 4851 netdev_for_each_mc_addr(ha, netdev) 4852 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 4853 4854 igb_update_mc_addr_list(hw, mta_list, i); 4855 kfree(mta_list); 4856 4857 return netdev_mc_count(netdev); 4858 } 4859 4860 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 4861 { 4862 struct e1000_hw *hw = &adapter->hw; 4863 u32 i, pf_id; 4864 4865 switch (hw->mac.type) { 4866 case e1000_i210: 4867 case e1000_i211: 4868 case e1000_i350: 4869 /* VLAN filtering needed for VLAN prio filter */ 4870 if (adapter->netdev->features & NETIF_F_NTUPLE) 4871 break; 4872 fallthrough; 4873 case e1000_82576: 4874 case e1000_82580: 4875 case e1000_i354: 4876 /* VLAN filtering needed for pool filtering */ 4877 if (adapter->vfs_allocated_count) 4878 break; 4879 fallthrough; 4880 default: 4881 return 1; 4882 } 4883 4884 /* We are already in VLAN promisc, nothing to do */ 4885 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 4886 return 0; 4887 4888 if (!adapter->vfs_allocated_count) 4889 goto set_vfta; 4890 4891 /* Add PF to all active pools */ 4892 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4893 4894 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4895 u32 vlvf = rd32(E1000_VLVF(i)); 4896 4897 vlvf |= BIT(pf_id); 4898 wr32(E1000_VLVF(i), vlvf); 4899 } 4900 4901 set_vfta: 4902 /* Set all bits in the VLAN filter table array */ 4903 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 4904 hw->mac.ops.write_vfta(hw, i, ~0U); 4905 4906 /* Set flag so we don't redo unnecessary work */ 4907 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 4908 4909 return 0; 4910 } 4911 4912 #define VFTA_BLOCK_SIZE 8 4913 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 4914 { 4915 struct e1000_hw *hw = &adapter->hw; 4916 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4917 u32 vid_start = vfta_offset * 32; 4918 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4919 u32 i, vid, word, bits, pf_id; 4920 4921 /* guarantee that we don't scrub out management VLAN */ 4922 vid = adapter->mng_vlan_id; 4923 if (vid >= vid_start && vid < vid_end) 4924 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4925 4926 if (!adapter->vfs_allocated_count) 4927 goto set_vfta; 4928 4929 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4930 4931 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4932 u32 vlvf = rd32(E1000_VLVF(i)); 4933 4934 /* pull VLAN ID from VLVF */ 4935 vid = vlvf & VLAN_VID_MASK; 4936 4937 /* only concern ourselves with a certain range */ 4938 if (vid < vid_start || vid >= vid_end) 4939 continue; 4940 4941 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 4942 /* record VLAN ID in VFTA */ 4943 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4944 4945 /* if PF is part of this then continue */ 4946 if (test_bit(vid, adapter->active_vlans)) 4947 continue; 4948 } 4949 4950 /* remove PF from the pool */ 4951 bits = ~BIT(pf_id); 4952 bits &= rd32(E1000_VLVF(i)); 4953 wr32(E1000_VLVF(i), bits); 4954 } 4955 4956 set_vfta: 4957 /* extract values from active_vlans and write back to VFTA */ 4958 for (i = VFTA_BLOCK_SIZE; i--;) { 4959 vid = (vfta_offset + i) * 32; 4960 word = vid / BITS_PER_LONG; 4961 bits = vid % BITS_PER_LONG; 4962 4963 vfta[i] |= adapter->active_vlans[word] >> bits; 4964 4965 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 4966 } 4967 } 4968 4969 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 4970 { 4971 u32 i; 4972 4973 /* We are not in VLAN promisc, nothing to do */ 4974 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 4975 return; 4976 4977 /* Set flag so we don't redo unnecessary work */ 4978 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 4979 4980 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 4981 igb_scrub_vfta(adapter, i); 4982 } 4983 4984 /** 4985 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 4986 * @netdev: network interface device structure 4987 * 4988 * The set_rx_mode entry point is called whenever the unicast or multicast 4989 * address lists or the network interface flags are updated. This routine is 4990 * responsible for configuring the hardware for proper unicast, multicast, 4991 * promiscuous mode, and all-multi behavior. 4992 **/ 4993 static void igb_set_rx_mode(struct net_device *netdev) 4994 { 4995 struct igb_adapter *adapter = netdev_priv(netdev); 4996 struct e1000_hw *hw = &adapter->hw; 4997 unsigned int vfn = adapter->vfs_allocated_count; 4998 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 4999 int count; 5000 5001 /* Check for Promiscuous and All Multicast modes */ 5002 if (netdev->flags & IFF_PROMISC) { 5003 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5004 vmolr |= E1000_VMOLR_MPME; 5005 5006 /* enable use of UTA filter to force packets to default pool */ 5007 if (hw->mac.type == e1000_82576) 5008 vmolr |= E1000_VMOLR_ROPE; 5009 } else { 5010 if (netdev->flags & IFF_ALLMULTI) { 5011 rctl |= E1000_RCTL_MPE; 5012 vmolr |= E1000_VMOLR_MPME; 5013 } else { 5014 /* Write addresses to the MTA, if the attempt fails 5015 * then we should just turn on promiscuous mode so 5016 * that we can at least receive multicast traffic 5017 */ 5018 count = igb_write_mc_addr_list(netdev); 5019 if (count < 0) { 5020 rctl |= E1000_RCTL_MPE; 5021 vmolr |= E1000_VMOLR_MPME; 5022 } else if (count) { 5023 vmolr |= E1000_VMOLR_ROMPE; 5024 } 5025 } 5026 } 5027 5028 /* Write addresses to available RAR registers, if there is not 5029 * sufficient space to store all the addresses then enable 5030 * unicast promiscuous mode 5031 */ 5032 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5033 rctl |= E1000_RCTL_UPE; 5034 vmolr |= E1000_VMOLR_ROPE; 5035 } 5036 5037 /* enable VLAN filtering by default */ 5038 rctl |= E1000_RCTL_VFE; 5039 5040 /* disable VLAN filtering for modes that require it */ 5041 if ((netdev->flags & IFF_PROMISC) || 5042 (netdev->features & NETIF_F_RXALL)) { 5043 /* if we fail to set all rules then just clear VFE */ 5044 if (igb_vlan_promisc_enable(adapter)) 5045 rctl &= ~E1000_RCTL_VFE; 5046 } else { 5047 igb_vlan_promisc_disable(adapter); 5048 } 5049 5050 /* update state of unicast, multicast, and VLAN filtering modes */ 5051 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5052 E1000_RCTL_VFE); 5053 wr32(E1000_RCTL, rctl); 5054 5055 #if (PAGE_SIZE < 8192) 5056 if (!adapter->vfs_allocated_count) { 5057 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5058 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5059 } 5060 #endif 5061 wr32(E1000_RLPML, rlpml); 5062 5063 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5064 * the VMOLR to enable the appropriate modes. Without this workaround 5065 * we will have issues with VLAN tag stripping not being done for frames 5066 * that are only arriving because we are the default pool 5067 */ 5068 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5069 return; 5070 5071 /* set UTA to appropriate mode */ 5072 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5073 5074 vmolr |= rd32(E1000_VMOLR(vfn)) & 5075 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5076 5077 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5078 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5079 #if (PAGE_SIZE < 8192) 5080 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5081 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5082 else 5083 #endif 5084 vmolr |= MAX_JUMBO_FRAME_SIZE; 5085 vmolr |= E1000_VMOLR_LPE; 5086 5087 wr32(E1000_VMOLR(vfn), vmolr); 5088 5089 igb_restore_vf_multicasts(adapter); 5090 } 5091 5092 static void igb_check_wvbr(struct igb_adapter *adapter) 5093 { 5094 struct e1000_hw *hw = &adapter->hw; 5095 u32 wvbr = 0; 5096 5097 switch (hw->mac.type) { 5098 case e1000_82576: 5099 case e1000_i350: 5100 wvbr = rd32(E1000_WVBR); 5101 if (!wvbr) 5102 return; 5103 break; 5104 default: 5105 break; 5106 } 5107 5108 adapter->wvbr |= wvbr; 5109 } 5110 5111 #define IGB_STAGGERED_QUEUE_OFFSET 8 5112 5113 static void igb_spoof_check(struct igb_adapter *adapter) 5114 { 5115 int j; 5116 5117 if (!adapter->wvbr) 5118 return; 5119 5120 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5121 if (adapter->wvbr & BIT(j) || 5122 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5123 dev_warn(&adapter->pdev->dev, 5124 "Spoof event(s) detected on VF %d\n", j); 5125 adapter->wvbr &= 5126 ~(BIT(j) | 5127 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5128 } 5129 } 5130 } 5131 5132 /* Need to wait a few seconds after link up to get diagnostic information from 5133 * the phy 5134 */ 5135 static void igb_update_phy_info(struct timer_list *t) 5136 { 5137 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5138 igb_get_phy_info(&adapter->hw); 5139 } 5140 5141 /** 5142 * igb_has_link - check shared code for link and determine up/down 5143 * @adapter: pointer to driver private info 5144 **/ 5145 bool igb_has_link(struct igb_adapter *adapter) 5146 { 5147 struct e1000_hw *hw = &adapter->hw; 5148 bool link_active = false; 5149 5150 /* get_link_status is set on LSC (link status) interrupt or 5151 * rx sequence error interrupt. get_link_status will stay 5152 * false until the e1000_check_for_link establishes link 5153 * for copper adapters ONLY 5154 */ 5155 switch (hw->phy.media_type) { 5156 case e1000_media_type_copper: 5157 if (!hw->mac.get_link_status) 5158 return true; 5159 fallthrough; 5160 case e1000_media_type_internal_serdes: 5161 hw->mac.ops.check_for_link(hw); 5162 link_active = !hw->mac.get_link_status; 5163 break; 5164 default: 5165 case e1000_media_type_unknown: 5166 break; 5167 } 5168 5169 if (((hw->mac.type == e1000_i210) || 5170 (hw->mac.type == e1000_i211)) && 5171 (hw->phy.id == I210_I_PHY_ID)) { 5172 if (!netif_carrier_ok(adapter->netdev)) { 5173 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5174 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5175 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5176 adapter->link_check_timeout = jiffies; 5177 } 5178 } 5179 5180 return link_active; 5181 } 5182 5183 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5184 { 5185 bool ret = false; 5186 u32 ctrl_ext, thstat; 5187 5188 /* check for thermal sensor event on i350 copper only */ 5189 if (hw->mac.type == e1000_i350) { 5190 thstat = rd32(E1000_THSTAT); 5191 ctrl_ext = rd32(E1000_CTRL_EXT); 5192 5193 if ((hw->phy.media_type == e1000_media_type_copper) && 5194 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5195 ret = !!(thstat & event); 5196 } 5197 5198 return ret; 5199 } 5200 5201 /** 5202 * igb_check_lvmmc - check for malformed packets received 5203 * and indicated in LVMMC register 5204 * @adapter: pointer to adapter 5205 **/ 5206 static void igb_check_lvmmc(struct igb_adapter *adapter) 5207 { 5208 struct e1000_hw *hw = &adapter->hw; 5209 u32 lvmmc; 5210 5211 lvmmc = rd32(E1000_LVMMC); 5212 if (lvmmc) { 5213 if (unlikely(net_ratelimit())) { 5214 netdev_warn(adapter->netdev, 5215 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5216 lvmmc); 5217 } 5218 } 5219 } 5220 5221 /** 5222 * igb_watchdog - Timer Call-back 5223 * @data: pointer to adapter cast into an unsigned long 5224 **/ 5225 static void igb_watchdog(struct timer_list *t) 5226 { 5227 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5228 /* Do the rest outside of interrupt context */ 5229 schedule_work(&adapter->watchdog_task); 5230 } 5231 5232 static void igb_watchdog_task(struct work_struct *work) 5233 { 5234 struct igb_adapter *adapter = container_of(work, 5235 struct igb_adapter, 5236 watchdog_task); 5237 struct e1000_hw *hw = &adapter->hw; 5238 struct e1000_phy_info *phy = &hw->phy; 5239 struct net_device *netdev = adapter->netdev; 5240 u32 link; 5241 int i; 5242 u32 connsw; 5243 u16 phy_data, retry_count = 20; 5244 5245 link = igb_has_link(adapter); 5246 5247 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5248 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5249 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5250 else 5251 link = false; 5252 } 5253 5254 /* Force link down if we have fiber to swap to */ 5255 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5256 if (hw->phy.media_type == e1000_media_type_copper) { 5257 connsw = rd32(E1000_CONNSW); 5258 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5259 link = 0; 5260 } 5261 } 5262 if (link) { 5263 /* Perform a reset if the media type changed. */ 5264 if (hw->dev_spec._82575.media_changed) { 5265 hw->dev_spec._82575.media_changed = false; 5266 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5267 igb_reset(adapter); 5268 } 5269 /* Cancel scheduled suspend requests. */ 5270 pm_runtime_resume(netdev->dev.parent); 5271 5272 if (!netif_carrier_ok(netdev)) { 5273 u32 ctrl; 5274 5275 hw->mac.ops.get_speed_and_duplex(hw, 5276 &adapter->link_speed, 5277 &adapter->link_duplex); 5278 5279 ctrl = rd32(E1000_CTRL); 5280 /* Links status message must follow this format */ 5281 netdev_info(netdev, 5282 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5283 netdev->name, 5284 adapter->link_speed, 5285 adapter->link_duplex == FULL_DUPLEX ? 5286 "Full" : "Half", 5287 (ctrl & E1000_CTRL_TFCE) && 5288 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5289 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5290 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5291 5292 /* disable EEE if enabled */ 5293 if ((adapter->flags & IGB_FLAG_EEE) && 5294 (adapter->link_duplex == HALF_DUPLEX)) { 5295 dev_info(&adapter->pdev->dev, 5296 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5297 adapter->hw.dev_spec._82575.eee_disable = true; 5298 adapter->flags &= ~IGB_FLAG_EEE; 5299 } 5300 5301 /* check if SmartSpeed worked */ 5302 igb_check_downshift(hw); 5303 if (phy->speed_downgraded) 5304 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5305 5306 /* check for thermal sensor event */ 5307 if (igb_thermal_sensor_event(hw, 5308 E1000_THSTAT_LINK_THROTTLE)) 5309 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5310 5311 /* adjust timeout factor according to speed/duplex */ 5312 adapter->tx_timeout_factor = 1; 5313 switch (adapter->link_speed) { 5314 case SPEED_10: 5315 adapter->tx_timeout_factor = 14; 5316 break; 5317 case SPEED_100: 5318 /* maybe add some timeout factor ? */ 5319 break; 5320 } 5321 5322 if (adapter->link_speed != SPEED_1000) 5323 goto no_wait; 5324 5325 /* wait for Remote receiver status OK */ 5326 retry_read_status: 5327 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5328 &phy_data)) { 5329 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5330 retry_count) { 5331 msleep(100); 5332 retry_count--; 5333 goto retry_read_status; 5334 } else if (!retry_count) { 5335 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5336 } 5337 } else { 5338 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5339 } 5340 no_wait: 5341 netif_carrier_on(netdev); 5342 5343 igb_ping_all_vfs(adapter); 5344 igb_check_vf_rate_limit(adapter); 5345 5346 /* link state has changed, schedule phy info update */ 5347 if (!test_bit(__IGB_DOWN, &adapter->state)) 5348 mod_timer(&adapter->phy_info_timer, 5349 round_jiffies(jiffies + 2 * HZ)); 5350 } 5351 } else { 5352 if (netif_carrier_ok(netdev)) { 5353 adapter->link_speed = 0; 5354 adapter->link_duplex = 0; 5355 5356 /* check for thermal sensor event */ 5357 if (igb_thermal_sensor_event(hw, 5358 E1000_THSTAT_PWR_DOWN)) { 5359 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5360 } 5361 5362 /* Links status message must follow this format */ 5363 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5364 netdev->name); 5365 netif_carrier_off(netdev); 5366 5367 igb_ping_all_vfs(adapter); 5368 5369 /* link state has changed, schedule phy info update */ 5370 if (!test_bit(__IGB_DOWN, &adapter->state)) 5371 mod_timer(&adapter->phy_info_timer, 5372 round_jiffies(jiffies + 2 * HZ)); 5373 5374 /* link is down, time to check for alternate media */ 5375 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5376 igb_check_swap_media(adapter); 5377 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5378 schedule_work(&adapter->reset_task); 5379 /* return immediately */ 5380 return; 5381 } 5382 } 5383 pm_schedule_suspend(netdev->dev.parent, 5384 MSEC_PER_SEC * 5); 5385 5386 /* also check for alternate media here */ 5387 } else if (!netif_carrier_ok(netdev) && 5388 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5389 igb_check_swap_media(adapter); 5390 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5391 schedule_work(&adapter->reset_task); 5392 /* return immediately */ 5393 return; 5394 } 5395 } 5396 } 5397 5398 spin_lock(&adapter->stats64_lock); 5399 igb_update_stats(adapter); 5400 spin_unlock(&adapter->stats64_lock); 5401 5402 for (i = 0; i < adapter->num_tx_queues; i++) { 5403 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5404 if (!netif_carrier_ok(netdev)) { 5405 /* We've lost link, so the controller stops DMA, 5406 * but we've got queued Tx work that's never going 5407 * to get done, so reset controller to flush Tx. 5408 * (Do the reset outside of interrupt context). 5409 */ 5410 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5411 adapter->tx_timeout_count++; 5412 schedule_work(&adapter->reset_task); 5413 /* return immediately since reset is imminent */ 5414 return; 5415 } 5416 } 5417 5418 /* Force detection of hung controller every watchdog period */ 5419 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5420 } 5421 5422 /* Cause software interrupt to ensure Rx ring is cleaned */ 5423 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5424 u32 eics = 0; 5425 5426 for (i = 0; i < adapter->num_q_vectors; i++) 5427 eics |= adapter->q_vector[i]->eims_value; 5428 wr32(E1000_EICS, eics); 5429 } else { 5430 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5431 } 5432 5433 igb_spoof_check(adapter); 5434 igb_ptp_rx_hang(adapter); 5435 igb_ptp_tx_hang(adapter); 5436 5437 /* Check LVMMC register on i350/i354 only */ 5438 if ((adapter->hw.mac.type == e1000_i350) || 5439 (adapter->hw.mac.type == e1000_i354)) 5440 igb_check_lvmmc(adapter); 5441 5442 /* Reset the timer */ 5443 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5444 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5445 mod_timer(&adapter->watchdog_timer, 5446 round_jiffies(jiffies + HZ)); 5447 else 5448 mod_timer(&adapter->watchdog_timer, 5449 round_jiffies(jiffies + 2 * HZ)); 5450 } 5451 } 5452 5453 enum latency_range { 5454 lowest_latency = 0, 5455 low_latency = 1, 5456 bulk_latency = 2, 5457 latency_invalid = 255 5458 }; 5459 5460 /** 5461 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5462 * @q_vector: pointer to q_vector 5463 * 5464 * Stores a new ITR value based on strictly on packet size. This 5465 * algorithm is less sophisticated than that used in igb_update_itr, 5466 * due to the difficulty of synchronizing statistics across multiple 5467 * receive rings. The divisors and thresholds used by this function 5468 * were determined based on theoretical maximum wire speed and testing 5469 * data, in order to minimize response time while increasing bulk 5470 * throughput. 5471 * This functionality is controlled by ethtool's coalescing settings. 5472 * NOTE: This function is called only when operating in a multiqueue 5473 * receive environment. 5474 **/ 5475 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5476 { 5477 int new_val = q_vector->itr_val; 5478 int avg_wire_size = 0; 5479 struct igb_adapter *adapter = q_vector->adapter; 5480 unsigned int packets; 5481 5482 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5483 * ints/sec - ITR timer value of 120 ticks. 5484 */ 5485 if (adapter->link_speed != SPEED_1000) { 5486 new_val = IGB_4K_ITR; 5487 goto set_itr_val; 5488 } 5489 5490 packets = q_vector->rx.total_packets; 5491 if (packets) 5492 avg_wire_size = q_vector->rx.total_bytes / packets; 5493 5494 packets = q_vector->tx.total_packets; 5495 if (packets) 5496 avg_wire_size = max_t(u32, avg_wire_size, 5497 q_vector->tx.total_bytes / packets); 5498 5499 /* if avg_wire_size isn't set no work was done */ 5500 if (!avg_wire_size) 5501 goto clear_counts; 5502 5503 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5504 avg_wire_size += 24; 5505 5506 /* Don't starve jumbo frames */ 5507 avg_wire_size = min(avg_wire_size, 3000); 5508 5509 /* Give a little boost to mid-size frames */ 5510 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5511 new_val = avg_wire_size / 3; 5512 else 5513 new_val = avg_wire_size / 2; 5514 5515 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5516 if (new_val < IGB_20K_ITR && 5517 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5518 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5519 new_val = IGB_20K_ITR; 5520 5521 set_itr_val: 5522 if (new_val != q_vector->itr_val) { 5523 q_vector->itr_val = new_val; 5524 q_vector->set_itr = 1; 5525 } 5526 clear_counts: 5527 q_vector->rx.total_bytes = 0; 5528 q_vector->rx.total_packets = 0; 5529 q_vector->tx.total_bytes = 0; 5530 q_vector->tx.total_packets = 0; 5531 } 5532 5533 /** 5534 * igb_update_itr - update the dynamic ITR value based on statistics 5535 * @q_vector: pointer to q_vector 5536 * @ring_container: ring info to update the itr for 5537 * 5538 * Stores a new ITR value based on packets and byte 5539 * counts during the last interrupt. The advantage of per interrupt 5540 * computation is faster updates and more accurate ITR for the current 5541 * traffic pattern. Constants in this function were computed 5542 * based on theoretical maximum wire speed and thresholds were set based 5543 * on testing data as well as attempting to minimize response time 5544 * while increasing bulk throughput. 5545 * This functionality is controlled by ethtool's coalescing settings. 5546 * NOTE: These calculations are only valid when operating in a single- 5547 * queue environment. 5548 **/ 5549 static void igb_update_itr(struct igb_q_vector *q_vector, 5550 struct igb_ring_container *ring_container) 5551 { 5552 unsigned int packets = ring_container->total_packets; 5553 unsigned int bytes = ring_container->total_bytes; 5554 u8 itrval = ring_container->itr; 5555 5556 /* no packets, exit with status unchanged */ 5557 if (packets == 0) 5558 return; 5559 5560 switch (itrval) { 5561 case lowest_latency: 5562 /* handle TSO and jumbo frames */ 5563 if (bytes/packets > 8000) 5564 itrval = bulk_latency; 5565 else if ((packets < 5) && (bytes > 512)) 5566 itrval = low_latency; 5567 break; 5568 case low_latency: /* 50 usec aka 20000 ints/s */ 5569 if (bytes > 10000) { 5570 /* this if handles the TSO accounting */ 5571 if (bytes/packets > 8000) 5572 itrval = bulk_latency; 5573 else if ((packets < 10) || ((bytes/packets) > 1200)) 5574 itrval = bulk_latency; 5575 else if ((packets > 35)) 5576 itrval = lowest_latency; 5577 } else if (bytes/packets > 2000) { 5578 itrval = bulk_latency; 5579 } else if (packets <= 2 && bytes < 512) { 5580 itrval = lowest_latency; 5581 } 5582 break; 5583 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5584 if (bytes > 25000) { 5585 if (packets > 35) 5586 itrval = low_latency; 5587 } else if (bytes < 1500) { 5588 itrval = low_latency; 5589 } 5590 break; 5591 } 5592 5593 /* clear work counters since we have the values we need */ 5594 ring_container->total_bytes = 0; 5595 ring_container->total_packets = 0; 5596 5597 /* write updated itr to ring container */ 5598 ring_container->itr = itrval; 5599 } 5600 5601 static void igb_set_itr(struct igb_q_vector *q_vector) 5602 { 5603 struct igb_adapter *adapter = q_vector->adapter; 5604 u32 new_itr = q_vector->itr_val; 5605 u8 current_itr = 0; 5606 5607 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5608 if (adapter->link_speed != SPEED_1000) { 5609 current_itr = 0; 5610 new_itr = IGB_4K_ITR; 5611 goto set_itr_now; 5612 } 5613 5614 igb_update_itr(q_vector, &q_vector->tx); 5615 igb_update_itr(q_vector, &q_vector->rx); 5616 5617 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5618 5619 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5620 if (current_itr == lowest_latency && 5621 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5622 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5623 current_itr = low_latency; 5624 5625 switch (current_itr) { 5626 /* counts and packets in update_itr are dependent on these numbers */ 5627 case lowest_latency: 5628 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5629 break; 5630 case low_latency: 5631 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5632 break; 5633 case bulk_latency: 5634 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5635 break; 5636 default: 5637 break; 5638 } 5639 5640 set_itr_now: 5641 if (new_itr != q_vector->itr_val) { 5642 /* this attempts to bias the interrupt rate towards Bulk 5643 * by adding intermediate steps when interrupt rate is 5644 * increasing 5645 */ 5646 new_itr = new_itr > q_vector->itr_val ? 5647 max((new_itr * q_vector->itr_val) / 5648 (new_itr + (q_vector->itr_val >> 2)), 5649 new_itr) : new_itr; 5650 /* Don't write the value here; it resets the adapter's 5651 * internal timer, and causes us to delay far longer than 5652 * we should between interrupts. Instead, we write the ITR 5653 * value at the beginning of the next interrupt so the timing 5654 * ends up being correct. 5655 */ 5656 q_vector->itr_val = new_itr; 5657 q_vector->set_itr = 1; 5658 } 5659 } 5660 5661 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 5662 struct igb_tx_buffer *first, 5663 u32 vlan_macip_lens, u32 type_tucmd, 5664 u32 mss_l4len_idx) 5665 { 5666 struct e1000_adv_tx_context_desc *context_desc; 5667 u16 i = tx_ring->next_to_use; 5668 struct timespec64 ts; 5669 5670 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5671 5672 i++; 5673 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 5674 5675 /* set bits to identify this as an advanced context descriptor */ 5676 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 5677 5678 /* For 82575, context index must be unique per ring. */ 5679 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5680 mss_l4len_idx |= tx_ring->reg_idx << 4; 5681 5682 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5683 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5684 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5685 5686 /* We assume there is always a valid tx time available. Invalid times 5687 * should have been handled by the upper layers. 5688 */ 5689 if (tx_ring->launchtime_enable) { 5690 ts = ktime_to_timespec64(first->skb->tstamp); 5691 first->skb->tstamp = ktime_set(0, 0); 5692 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 5693 } else { 5694 context_desc->seqnum_seed = 0; 5695 } 5696 } 5697 5698 static int igb_tso(struct igb_ring *tx_ring, 5699 struct igb_tx_buffer *first, 5700 u8 *hdr_len) 5701 { 5702 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 5703 struct sk_buff *skb = first->skb; 5704 union { 5705 struct iphdr *v4; 5706 struct ipv6hdr *v6; 5707 unsigned char *hdr; 5708 } ip; 5709 union { 5710 struct tcphdr *tcp; 5711 struct udphdr *udp; 5712 unsigned char *hdr; 5713 } l4; 5714 u32 paylen, l4_offset; 5715 int err; 5716 5717 if (skb->ip_summed != CHECKSUM_PARTIAL) 5718 return 0; 5719 5720 if (!skb_is_gso(skb)) 5721 return 0; 5722 5723 err = skb_cow_head(skb, 0); 5724 if (err < 0) 5725 return err; 5726 5727 ip.hdr = skb_network_header(skb); 5728 l4.hdr = skb_checksum_start(skb); 5729 5730 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 5731 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 5732 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP; 5733 5734 /* initialize outer IP header fields */ 5735 if (ip.v4->version == 4) { 5736 unsigned char *csum_start = skb_checksum_start(skb); 5737 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 5738 5739 /* IP header will have to cancel out any data that 5740 * is not a part of the outer IP header 5741 */ 5742 ip.v4->check = csum_fold(csum_partial(trans_start, 5743 csum_start - trans_start, 5744 0)); 5745 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 5746 5747 ip.v4->tot_len = 0; 5748 first->tx_flags |= IGB_TX_FLAGS_TSO | 5749 IGB_TX_FLAGS_CSUM | 5750 IGB_TX_FLAGS_IPV4; 5751 } else { 5752 ip.v6->payload_len = 0; 5753 first->tx_flags |= IGB_TX_FLAGS_TSO | 5754 IGB_TX_FLAGS_CSUM; 5755 } 5756 5757 /* determine offset of inner transport header */ 5758 l4_offset = l4.hdr - skb->data; 5759 5760 /* remove payload length from inner checksum */ 5761 paylen = skb->len - l4_offset; 5762 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) { 5763 /* compute length of segmentation header */ 5764 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 5765 csum_replace_by_diff(&l4.tcp->check, 5766 (__force __wsum)htonl(paylen)); 5767 } else { 5768 /* compute length of segmentation header */ 5769 *hdr_len = sizeof(*l4.udp) + l4_offset; 5770 csum_replace_by_diff(&l4.udp->check, 5771 (__force __wsum)htonl(paylen)); 5772 } 5773 5774 /* update gso size and bytecount with header size */ 5775 first->gso_segs = skb_shinfo(skb)->gso_segs; 5776 first->bytecount += (first->gso_segs - 1) * *hdr_len; 5777 5778 /* MSS L4LEN IDX */ 5779 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 5780 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 5781 5782 /* VLAN MACLEN IPLEN */ 5783 vlan_macip_lens = l4.hdr - ip.hdr; 5784 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 5785 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5786 5787 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 5788 type_tucmd, mss_l4len_idx); 5789 5790 return 1; 5791 } 5792 5793 static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb) 5794 { 5795 unsigned int offset = 0; 5796 5797 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 5798 5799 return offset == skb_checksum_start_offset(skb); 5800 } 5801 5802 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 5803 { 5804 struct sk_buff *skb = first->skb; 5805 u32 vlan_macip_lens = 0; 5806 u32 type_tucmd = 0; 5807 5808 if (skb->ip_summed != CHECKSUM_PARTIAL) { 5809 csum_failed: 5810 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 5811 !tx_ring->launchtime_enable) 5812 return; 5813 goto no_csum; 5814 } 5815 5816 switch (skb->csum_offset) { 5817 case offsetof(struct tcphdr, check): 5818 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 5819 fallthrough; 5820 case offsetof(struct udphdr, check): 5821 break; 5822 case offsetof(struct sctphdr, checksum): 5823 /* validate that this is actually an SCTP request */ 5824 if (((first->protocol == htons(ETH_P_IP)) && 5825 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 5826 ((first->protocol == htons(ETH_P_IPV6)) && 5827 igb_ipv6_csum_is_sctp(skb))) { 5828 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 5829 break; 5830 } 5831 fallthrough; 5832 default: 5833 skb_checksum_help(skb); 5834 goto csum_failed; 5835 } 5836 5837 /* update TX checksum flag */ 5838 first->tx_flags |= IGB_TX_FLAGS_CSUM; 5839 vlan_macip_lens = skb_checksum_start_offset(skb) - 5840 skb_network_offset(skb); 5841 no_csum: 5842 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 5843 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5844 5845 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 5846 } 5847 5848 #define IGB_SET_FLAG(_input, _flag, _result) \ 5849 ((_flag <= _result) ? \ 5850 ((u32)(_input & _flag) * (_result / _flag)) : \ 5851 ((u32)(_input & _flag) / (_flag / _result))) 5852 5853 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 5854 { 5855 /* set type for advanced descriptor with frame checksum insertion */ 5856 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 5857 E1000_ADVTXD_DCMD_DEXT | 5858 E1000_ADVTXD_DCMD_IFCS; 5859 5860 /* set HW vlan bit if vlan is present */ 5861 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 5862 (E1000_ADVTXD_DCMD_VLE)); 5863 5864 /* set segmentation bits for TSO */ 5865 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 5866 (E1000_ADVTXD_DCMD_TSE)); 5867 5868 /* set timestamp bit if present */ 5869 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 5870 (E1000_ADVTXD_MAC_TSTAMP)); 5871 5872 /* insert frame checksum */ 5873 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 5874 5875 return cmd_type; 5876 } 5877 5878 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 5879 union e1000_adv_tx_desc *tx_desc, 5880 u32 tx_flags, unsigned int paylen) 5881 { 5882 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 5883 5884 /* 82575 requires a unique index per ring */ 5885 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5886 olinfo_status |= tx_ring->reg_idx << 4; 5887 5888 /* insert L4 checksum */ 5889 olinfo_status |= IGB_SET_FLAG(tx_flags, 5890 IGB_TX_FLAGS_CSUM, 5891 (E1000_TXD_POPTS_TXSM << 8)); 5892 5893 /* insert IPv4 checksum */ 5894 olinfo_status |= IGB_SET_FLAG(tx_flags, 5895 IGB_TX_FLAGS_IPV4, 5896 (E1000_TXD_POPTS_IXSM << 8)); 5897 5898 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 5899 } 5900 5901 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5902 { 5903 struct net_device *netdev = tx_ring->netdev; 5904 5905 netif_stop_subqueue(netdev, tx_ring->queue_index); 5906 5907 /* Herbert's original patch had: 5908 * smp_mb__after_netif_stop_queue(); 5909 * but since that doesn't exist yet, just open code it. 5910 */ 5911 smp_mb(); 5912 5913 /* We need to check again in a case another CPU has just 5914 * made room available. 5915 */ 5916 if (igb_desc_unused(tx_ring) < size) 5917 return -EBUSY; 5918 5919 /* A reprieve! */ 5920 netif_wake_subqueue(netdev, tx_ring->queue_index); 5921 5922 u64_stats_update_begin(&tx_ring->tx_syncp2); 5923 tx_ring->tx_stats.restart_queue2++; 5924 u64_stats_update_end(&tx_ring->tx_syncp2); 5925 5926 return 0; 5927 } 5928 5929 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5930 { 5931 if (igb_desc_unused(tx_ring) >= size) 5932 return 0; 5933 return __igb_maybe_stop_tx(tx_ring, size); 5934 } 5935 5936 static int igb_tx_map(struct igb_ring *tx_ring, 5937 struct igb_tx_buffer *first, 5938 const u8 hdr_len) 5939 { 5940 struct sk_buff *skb = first->skb; 5941 struct igb_tx_buffer *tx_buffer; 5942 union e1000_adv_tx_desc *tx_desc; 5943 skb_frag_t *frag; 5944 dma_addr_t dma; 5945 unsigned int data_len, size; 5946 u32 tx_flags = first->tx_flags; 5947 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 5948 u16 i = tx_ring->next_to_use; 5949 5950 tx_desc = IGB_TX_DESC(tx_ring, i); 5951 5952 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 5953 5954 size = skb_headlen(skb); 5955 data_len = skb->data_len; 5956 5957 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 5958 5959 tx_buffer = first; 5960 5961 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 5962 if (dma_mapping_error(tx_ring->dev, dma)) 5963 goto dma_error; 5964 5965 /* record length, and DMA address */ 5966 dma_unmap_len_set(tx_buffer, len, size); 5967 dma_unmap_addr_set(tx_buffer, dma, dma); 5968 5969 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5970 5971 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 5972 tx_desc->read.cmd_type_len = 5973 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 5974 5975 i++; 5976 tx_desc++; 5977 if (i == tx_ring->count) { 5978 tx_desc = IGB_TX_DESC(tx_ring, 0); 5979 i = 0; 5980 } 5981 tx_desc->read.olinfo_status = 0; 5982 5983 dma += IGB_MAX_DATA_PER_TXD; 5984 size -= IGB_MAX_DATA_PER_TXD; 5985 5986 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5987 } 5988 5989 if (likely(!data_len)) 5990 break; 5991 5992 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 5993 5994 i++; 5995 tx_desc++; 5996 if (i == tx_ring->count) { 5997 tx_desc = IGB_TX_DESC(tx_ring, 0); 5998 i = 0; 5999 } 6000 tx_desc->read.olinfo_status = 0; 6001 6002 size = skb_frag_size(frag); 6003 data_len -= size; 6004 6005 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6006 size, DMA_TO_DEVICE); 6007 6008 tx_buffer = &tx_ring->tx_buffer_info[i]; 6009 } 6010 6011 /* write last descriptor with RS and EOP bits */ 6012 cmd_type |= size | IGB_TXD_DCMD; 6013 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6014 6015 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6016 6017 /* set the timestamp */ 6018 first->time_stamp = jiffies; 6019 6020 skb_tx_timestamp(skb); 6021 6022 /* Force memory writes to complete before letting h/w know there 6023 * are new descriptors to fetch. (Only applicable for weak-ordered 6024 * memory model archs, such as IA-64). 6025 * 6026 * We also need this memory barrier to make certain all of the 6027 * status bits have been updated before next_to_watch is written. 6028 */ 6029 dma_wmb(); 6030 6031 /* set next_to_watch value indicating a packet is present */ 6032 first->next_to_watch = tx_desc; 6033 6034 i++; 6035 if (i == tx_ring->count) 6036 i = 0; 6037 6038 tx_ring->next_to_use = i; 6039 6040 /* Make sure there is space in the ring for the next send. */ 6041 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6042 6043 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6044 writel(i, tx_ring->tail); 6045 } 6046 return 0; 6047 6048 dma_error: 6049 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6050 tx_buffer = &tx_ring->tx_buffer_info[i]; 6051 6052 /* clear dma mappings for failed tx_buffer_info map */ 6053 while (tx_buffer != first) { 6054 if (dma_unmap_len(tx_buffer, len)) 6055 dma_unmap_page(tx_ring->dev, 6056 dma_unmap_addr(tx_buffer, dma), 6057 dma_unmap_len(tx_buffer, len), 6058 DMA_TO_DEVICE); 6059 dma_unmap_len_set(tx_buffer, len, 0); 6060 6061 if (i-- == 0) 6062 i += tx_ring->count; 6063 tx_buffer = &tx_ring->tx_buffer_info[i]; 6064 } 6065 6066 if (dma_unmap_len(tx_buffer, len)) 6067 dma_unmap_single(tx_ring->dev, 6068 dma_unmap_addr(tx_buffer, dma), 6069 dma_unmap_len(tx_buffer, len), 6070 DMA_TO_DEVICE); 6071 dma_unmap_len_set(tx_buffer, len, 0); 6072 6073 dev_kfree_skb_any(tx_buffer->skb); 6074 tx_buffer->skb = NULL; 6075 6076 tx_ring->next_to_use = i; 6077 6078 return -1; 6079 } 6080 6081 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6082 struct igb_ring *tx_ring) 6083 { 6084 struct igb_tx_buffer *first; 6085 int tso; 6086 u32 tx_flags = 0; 6087 unsigned short f; 6088 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6089 __be16 protocol = vlan_get_protocol(skb); 6090 u8 hdr_len = 0; 6091 6092 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6093 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6094 * + 2 desc gap to keep tail from touching head, 6095 * + 1 desc for context descriptor, 6096 * otherwise try next time 6097 */ 6098 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6099 count += TXD_USE_COUNT(skb_frag_size( 6100 &skb_shinfo(skb)->frags[f])); 6101 6102 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6103 /* this is a hard error */ 6104 return NETDEV_TX_BUSY; 6105 } 6106 6107 /* record the location of the first descriptor for this packet */ 6108 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6109 first->skb = skb; 6110 first->bytecount = skb->len; 6111 first->gso_segs = 1; 6112 6113 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6114 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6115 6116 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6117 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6118 &adapter->state)) { 6119 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6120 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6121 6122 adapter->ptp_tx_skb = skb_get(skb); 6123 adapter->ptp_tx_start = jiffies; 6124 if (adapter->hw.mac.type == e1000_82576) 6125 schedule_work(&adapter->ptp_tx_work); 6126 } else { 6127 adapter->tx_hwtstamp_skipped++; 6128 } 6129 } 6130 6131 if (skb_vlan_tag_present(skb)) { 6132 tx_flags |= IGB_TX_FLAGS_VLAN; 6133 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6134 } 6135 6136 /* record initial flags and protocol */ 6137 first->tx_flags = tx_flags; 6138 first->protocol = protocol; 6139 6140 tso = igb_tso(tx_ring, first, &hdr_len); 6141 if (tso < 0) 6142 goto out_drop; 6143 else if (!tso) 6144 igb_tx_csum(tx_ring, first); 6145 6146 if (igb_tx_map(tx_ring, first, hdr_len)) 6147 goto cleanup_tx_tstamp; 6148 6149 return NETDEV_TX_OK; 6150 6151 out_drop: 6152 dev_kfree_skb_any(first->skb); 6153 first->skb = NULL; 6154 cleanup_tx_tstamp: 6155 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6156 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6157 6158 dev_kfree_skb_any(adapter->ptp_tx_skb); 6159 adapter->ptp_tx_skb = NULL; 6160 if (adapter->hw.mac.type == e1000_82576) 6161 cancel_work_sync(&adapter->ptp_tx_work); 6162 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6163 } 6164 6165 return NETDEV_TX_OK; 6166 } 6167 6168 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6169 struct sk_buff *skb) 6170 { 6171 unsigned int r_idx = skb->queue_mapping; 6172 6173 if (r_idx >= adapter->num_tx_queues) 6174 r_idx = r_idx % adapter->num_tx_queues; 6175 6176 return adapter->tx_ring[r_idx]; 6177 } 6178 6179 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6180 struct net_device *netdev) 6181 { 6182 struct igb_adapter *adapter = netdev_priv(netdev); 6183 6184 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6185 * in order to meet this minimum size requirement. 6186 */ 6187 if (skb_put_padto(skb, 17)) 6188 return NETDEV_TX_OK; 6189 6190 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6191 } 6192 6193 /** 6194 * igb_tx_timeout - Respond to a Tx Hang 6195 * @netdev: network interface device structure 6196 **/ 6197 static void igb_tx_timeout(struct net_device *netdev, unsigned int txqueue) 6198 { 6199 struct igb_adapter *adapter = netdev_priv(netdev); 6200 struct e1000_hw *hw = &adapter->hw; 6201 6202 /* Do the reset outside of interrupt context */ 6203 adapter->tx_timeout_count++; 6204 6205 if (hw->mac.type >= e1000_82580) 6206 hw->dev_spec._82575.global_device_reset = true; 6207 6208 schedule_work(&adapter->reset_task); 6209 wr32(E1000_EICS, 6210 (adapter->eims_enable_mask & ~adapter->eims_other)); 6211 } 6212 6213 static void igb_reset_task(struct work_struct *work) 6214 { 6215 struct igb_adapter *adapter; 6216 adapter = container_of(work, struct igb_adapter, reset_task); 6217 6218 igb_dump(adapter); 6219 netdev_err(adapter->netdev, "Reset adapter\n"); 6220 igb_reinit_locked(adapter); 6221 } 6222 6223 /** 6224 * igb_get_stats64 - Get System Network Statistics 6225 * @netdev: network interface device structure 6226 * @stats: rtnl_link_stats64 pointer 6227 **/ 6228 static void igb_get_stats64(struct net_device *netdev, 6229 struct rtnl_link_stats64 *stats) 6230 { 6231 struct igb_adapter *adapter = netdev_priv(netdev); 6232 6233 spin_lock(&adapter->stats64_lock); 6234 igb_update_stats(adapter); 6235 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6236 spin_unlock(&adapter->stats64_lock); 6237 } 6238 6239 /** 6240 * igb_change_mtu - Change the Maximum Transfer Unit 6241 * @netdev: network interface device structure 6242 * @new_mtu: new value for maximum frame size 6243 * 6244 * Returns 0 on success, negative on failure 6245 **/ 6246 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6247 { 6248 struct igb_adapter *adapter = netdev_priv(netdev); 6249 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 6250 6251 /* adjust max frame to be at least the size of a standard frame */ 6252 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6253 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6254 6255 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6256 usleep_range(1000, 2000); 6257 6258 /* igb_down has a dependency on max_frame_size */ 6259 adapter->max_frame_size = max_frame; 6260 6261 if (netif_running(netdev)) 6262 igb_down(adapter); 6263 6264 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6265 netdev->mtu, new_mtu); 6266 netdev->mtu = new_mtu; 6267 6268 if (netif_running(netdev)) 6269 igb_up(adapter); 6270 else 6271 igb_reset(adapter); 6272 6273 clear_bit(__IGB_RESETTING, &adapter->state); 6274 6275 return 0; 6276 } 6277 6278 /** 6279 * igb_update_stats - Update the board statistics counters 6280 * @adapter: board private structure 6281 **/ 6282 void igb_update_stats(struct igb_adapter *adapter) 6283 { 6284 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6285 struct e1000_hw *hw = &adapter->hw; 6286 struct pci_dev *pdev = adapter->pdev; 6287 u32 reg, mpc; 6288 int i; 6289 u64 bytes, packets; 6290 unsigned int start; 6291 u64 _bytes, _packets; 6292 6293 /* Prevent stats update while adapter is being reset, or if the pci 6294 * connection is down. 6295 */ 6296 if (adapter->link_speed == 0) 6297 return; 6298 if (pci_channel_offline(pdev)) 6299 return; 6300 6301 bytes = 0; 6302 packets = 0; 6303 6304 rcu_read_lock(); 6305 for (i = 0; i < adapter->num_rx_queues; i++) { 6306 struct igb_ring *ring = adapter->rx_ring[i]; 6307 u32 rqdpc = rd32(E1000_RQDPC(i)); 6308 if (hw->mac.type >= e1000_i210) 6309 wr32(E1000_RQDPC(i), 0); 6310 6311 if (rqdpc) { 6312 ring->rx_stats.drops += rqdpc; 6313 net_stats->rx_fifo_errors += rqdpc; 6314 } 6315 6316 do { 6317 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 6318 _bytes = ring->rx_stats.bytes; 6319 _packets = ring->rx_stats.packets; 6320 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 6321 bytes += _bytes; 6322 packets += _packets; 6323 } 6324 6325 net_stats->rx_bytes = bytes; 6326 net_stats->rx_packets = packets; 6327 6328 bytes = 0; 6329 packets = 0; 6330 for (i = 0; i < adapter->num_tx_queues; i++) { 6331 struct igb_ring *ring = adapter->tx_ring[i]; 6332 do { 6333 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 6334 _bytes = ring->tx_stats.bytes; 6335 _packets = ring->tx_stats.packets; 6336 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 6337 bytes += _bytes; 6338 packets += _packets; 6339 } 6340 net_stats->tx_bytes = bytes; 6341 net_stats->tx_packets = packets; 6342 rcu_read_unlock(); 6343 6344 /* read stats registers */ 6345 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6346 adapter->stats.gprc += rd32(E1000_GPRC); 6347 adapter->stats.gorc += rd32(E1000_GORCL); 6348 rd32(E1000_GORCH); /* clear GORCL */ 6349 adapter->stats.bprc += rd32(E1000_BPRC); 6350 adapter->stats.mprc += rd32(E1000_MPRC); 6351 adapter->stats.roc += rd32(E1000_ROC); 6352 6353 adapter->stats.prc64 += rd32(E1000_PRC64); 6354 adapter->stats.prc127 += rd32(E1000_PRC127); 6355 adapter->stats.prc255 += rd32(E1000_PRC255); 6356 adapter->stats.prc511 += rd32(E1000_PRC511); 6357 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6358 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6359 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6360 adapter->stats.sec += rd32(E1000_SEC); 6361 6362 mpc = rd32(E1000_MPC); 6363 adapter->stats.mpc += mpc; 6364 net_stats->rx_fifo_errors += mpc; 6365 adapter->stats.scc += rd32(E1000_SCC); 6366 adapter->stats.ecol += rd32(E1000_ECOL); 6367 adapter->stats.mcc += rd32(E1000_MCC); 6368 adapter->stats.latecol += rd32(E1000_LATECOL); 6369 adapter->stats.dc += rd32(E1000_DC); 6370 adapter->stats.rlec += rd32(E1000_RLEC); 6371 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6372 adapter->stats.xontxc += rd32(E1000_XONTXC); 6373 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6374 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6375 adapter->stats.fcruc += rd32(E1000_FCRUC); 6376 adapter->stats.gptc += rd32(E1000_GPTC); 6377 adapter->stats.gotc += rd32(E1000_GOTCL); 6378 rd32(E1000_GOTCH); /* clear GOTCL */ 6379 adapter->stats.rnbc += rd32(E1000_RNBC); 6380 adapter->stats.ruc += rd32(E1000_RUC); 6381 adapter->stats.rfc += rd32(E1000_RFC); 6382 adapter->stats.rjc += rd32(E1000_RJC); 6383 adapter->stats.tor += rd32(E1000_TORH); 6384 adapter->stats.tot += rd32(E1000_TOTH); 6385 adapter->stats.tpr += rd32(E1000_TPR); 6386 6387 adapter->stats.ptc64 += rd32(E1000_PTC64); 6388 adapter->stats.ptc127 += rd32(E1000_PTC127); 6389 adapter->stats.ptc255 += rd32(E1000_PTC255); 6390 adapter->stats.ptc511 += rd32(E1000_PTC511); 6391 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6392 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6393 6394 adapter->stats.mptc += rd32(E1000_MPTC); 6395 adapter->stats.bptc += rd32(E1000_BPTC); 6396 6397 adapter->stats.tpt += rd32(E1000_TPT); 6398 adapter->stats.colc += rd32(E1000_COLC); 6399 6400 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6401 /* read internal phy specific stats */ 6402 reg = rd32(E1000_CTRL_EXT); 6403 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6404 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6405 6406 /* this stat has invalid values on i210/i211 */ 6407 if ((hw->mac.type != e1000_i210) && 6408 (hw->mac.type != e1000_i211)) 6409 adapter->stats.tncrs += rd32(E1000_TNCRS); 6410 } 6411 6412 adapter->stats.tsctc += rd32(E1000_TSCTC); 6413 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6414 6415 adapter->stats.iac += rd32(E1000_IAC); 6416 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6417 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6418 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6419 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6420 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6421 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6422 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6423 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6424 6425 /* Fill out the OS statistics structure */ 6426 net_stats->multicast = adapter->stats.mprc; 6427 net_stats->collisions = adapter->stats.colc; 6428 6429 /* Rx Errors */ 6430 6431 /* RLEC on some newer hardware can be incorrect so build 6432 * our own version based on RUC and ROC 6433 */ 6434 net_stats->rx_errors = adapter->stats.rxerrc + 6435 adapter->stats.crcerrs + adapter->stats.algnerrc + 6436 adapter->stats.ruc + adapter->stats.roc + 6437 adapter->stats.cexterr; 6438 net_stats->rx_length_errors = adapter->stats.ruc + 6439 adapter->stats.roc; 6440 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6441 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6442 net_stats->rx_missed_errors = adapter->stats.mpc; 6443 6444 /* Tx Errors */ 6445 net_stats->tx_errors = adapter->stats.ecol + 6446 adapter->stats.latecol; 6447 net_stats->tx_aborted_errors = adapter->stats.ecol; 6448 net_stats->tx_window_errors = adapter->stats.latecol; 6449 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6450 6451 /* Tx Dropped needs to be maintained elsewhere */ 6452 6453 /* Management Stats */ 6454 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6455 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6456 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6457 6458 /* OS2BMC Stats */ 6459 reg = rd32(E1000_MANC); 6460 if (reg & E1000_MANC_EN_BMC2OS) { 6461 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6462 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6463 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6464 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6465 } 6466 } 6467 6468 static void igb_tsync_interrupt(struct igb_adapter *adapter) 6469 { 6470 struct e1000_hw *hw = &adapter->hw; 6471 struct ptp_clock_event event; 6472 struct timespec64 ts; 6473 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR); 6474 6475 if (tsicr & TSINTR_SYS_WRAP) { 6476 event.type = PTP_CLOCK_PPS; 6477 if (adapter->ptp_caps.pps) 6478 ptp_clock_event(adapter->ptp_clock, &event); 6479 ack |= TSINTR_SYS_WRAP; 6480 } 6481 6482 if (tsicr & E1000_TSICR_TXTS) { 6483 /* retrieve hardware timestamp */ 6484 schedule_work(&adapter->ptp_tx_work); 6485 ack |= E1000_TSICR_TXTS; 6486 } 6487 6488 if (tsicr & TSINTR_TT0) { 6489 spin_lock(&adapter->tmreg_lock); 6490 ts = timespec64_add(adapter->perout[0].start, 6491 adapter->perout[0].period); 6492 /* u32 conversion of tv_sec is safe until y2106 */ 6493 wr32(E1000_TRGTTIML0, ts.tv_nsec); 6494 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec); 6495 tsauxc = rd32(E1000_TSAUXC); 6496 tsauxc |= TSAUXC_EN_TT0; 6497 wr32(E1000_TSAUXC, tsauxc); 6498 adapter->perout[0].start = ts; 6499 spin_unlock(&adapter->tmreg_lock); 6500 ack |= TSINTR_TT0; 6501 } 6502 6503 if (tsicr & TSINTR_TT1) { 6504 spin_lock(&adapter->tmreg_lock); 6505 ts = timespec64_add(adapter->perout[1].start, 6506 adapter->perout[1].period); 6507 wr32(E1000_TRGTTIML1, ts.tv_nsec); 6508 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec); 6509 tsauxc = rd32(E1000_TSAUXC); 6510 tsauxc |= TSAUXC_EN_TT1; 6511 wr32(E1000_TSAUXC, tsauxc); 6512 adapter->perout[1].start = ts; 6513 spin_unlock(&adapter->tmreg_lock); 6514 ack |= TSINTR_TT1; 6515 } 6516 6517 if (tsicr & TSINTR_AUTT0) { 6518 nsec = rd32(E1000_AUXSTMPL0); 6519 sec = rd32(E1000_AUXSTMPH0); 6520 event.type = PTP_CLOCK_EXTTS; 6521 event.index = 0; 6522 event.timestamp = sec * 1000000000ULL + nsec; 6523 ptp_clock_event(adapter->ptp_clock, &event); 6524 ack |= TSINTR_AUTT0; 6525 } 6526 6527 if (tsicr & TSINTR_AUTT1) { 6528 nsec = rd32(E1000_AUXSTMPL1); 6529 sec = rd32(E1000_AUXSTMPH1); 6530 event.type = PTP_CLOCK_EXTTS; 6531 event.index = 1; 6532 event.timestamp = sec * 1000000000ULL + nsec; 6533 ptp_clock_event(adapter->ptp_clock, &event); 6534 ack |= TSINTR_AUTT1; 6535 } 6536 6537 /* acknowledge the interrupts */ 6538 wr32(E1000_TSICR, ack); 6539 } 6540 6541 static irqreturn_t igb_msix_other(int irq, void *data) 6542 { 6543 struct igb_adapter *adapter = data; 6544 struct e1000_hw *hw = &adapter->hw; 6545 u32 icr = rd32(E1000_ICR); 6546 /* reading ICR causes bit 31 of EICR to be cleared */ 6547 6548 if (icr & E1000_ICR_DRSTA) 6549 schedule_work(&adapter->reset_task); 6550 6551 if (icr & E1000_ICR_DOUTSYNC) { 6552 /* HW is reporting DMA is out of sync */ 6553 adapter->stats.doosync++; 6554 /* The DMA Out of Sync is also indication of a spoof event 6555 * in IOV mode. Check the Wrong VM Behavior register to 6556 * see if it is really a spoof event. 6557 */ 6558 igb_check_wvbr(adapter); 6559 } 6560 6561 /* Check for a mailbox event */ 6562 if (icr & E1000_ICR_VMMB) 6563 igb_msg_task(adapter); 6564 6565 if (icr & E1000_ICR_LSC) { 6566 hw->mac.get_link_status = 1; 6567 /* guard against interrupt when we're going down */ 6568 if (!test_bit(__IGB_DOWN, &adapter->state)) 6569 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6570 } 6571 6572 if (icr & E1000_ICR_TS) 6573 igb_tsync_interrupt(adapter); 6574 6575 wr32(E1000_EIMS, adapter->eims_other); 6576 6577 return IRQ_HANDLED; 6578 } 6579 6580 static void igb_write_itr(struct igb_q_vector *q_vector) 6581 { 6582 struct igb_adapter *adapter = q_vector->adapter; 6583 u32 itr_val = q_vector->itr_val & 0x7FFC; 6584 6585 if (!q_vector->set_itr) 6586 return; 6587 6588 if (!itr_val) 6589 itr_val = 0x4; 6590 6591 if (adapter->hw.mac.type == e1000_82575) 6592 itr_val |= itr_val << 16; 6593 else 6594 itr_val |= E1000_EITR_CNT_IGNR; 6595 6596 writel(itr_val, q_vector->itr_register); 6597 q_vector->set_itr = 0; 6598 } 6599 6600 static irqreturn_t igb_msix_ring(int irq, void *data) 6601 { 6602 struct igb_q_vector *q_vector = data; 6603 6604 /* Write the ITR value calculated from the previous interrupt. */ 6605 igb_write_itr(q_vector); 6606 6607 napi_schedule(&q_vector->napi); 6608 6609 return IRQ_HANDLED; 6610 } 6611 6612 #ifdef CONFIG_IGB_DCA 6613 static void igb_update_tx_dca(struct igb_adapter *adapter, 6614 struct igb_ring *tx_ring, 6615 int cpu) 6616 { 6617 struct e1000_hw *hw = &adapter->hw; 6618 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 6619 6620 if (hw->mac.type != e1000_82575) 6621 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 6622 6623 /* We can enable relaxed ordering for reads, but not writes when 6624 * DCA is enabled. This is due to a known issue in some chipsets 6625 * which will cause the DCA tag to be cleared. 6626 */ 6627 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 6628 E1000_DCA_TXCTRL_DATA_RRO_EN | 6629 E1000_DCA_TXCTRL_DESC_DCA_EN; 6630 6631 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 6632 } 6633 6634 static void igb_update_rx_dca(struct igb_adapter *adapter, 6635 struct igb_ring *rx_ring, 6636 int cpu) 6637 { 6638 struct e1000_hw *hw = &adapter->hw; 6639 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 6640 6641 if (hw->mac.type != e1000_82575) 6642 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 6643 6644 /* We can enable relaxed ordering for reads, but not writes when 6645 * DCA is enabled. This is due to a known issue in some chipsets 6646 * which will cause the DCA tag to be cleared. 6647 */ 6648 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 6649 E1000_DCA_RXCTRL_DESC_DCA_EN; 6650 6651 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 6652 } 6653 6654 static void igb_update_dca(struct igb_q_vector *q_vector) 6655 { 6656 struct igb_adapter *adapter = q_vector->adapter; 6657 int cpu = get_cpu(); 6658 6659 if (q_vector->cpu == cpu) 6660 goto out_no_update; 6661 6662 if (q_vector->tx.ring) 6663 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 6664 6665 if (q_vector->rx.ring) 6666 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 6667 6668 q_vector->cpu = cpu; 6669 out_no_update: 6670 put_cpu(); 6671 } 6672 6673 static void igb_setup_dca(struct igb_adapter *adapter) 6674 { 6675 struct e1000_hw *hw = &adapter->hw; 6676 int i; 6677 6678 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 6679 return; 6680 6681 /* Always use CB2 mode, difference is masked in the CB driver. */ 6682 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 6683 6684 for (i = 0; i < adapter->num_q_vectors; i++) { 6685 adapter->q_vector[i]->cpu = -1; 6686 igb_update_dca(adapter->q_vector[i]); 6687 } 6688 } 6689 6690 static int __igb_notify_dca(struct device *dev, void *data) 6691 { 6692 struct net_device *netdev = dev_get_drvdata(dev); 6693 struct igb_adapter *adapter = netdev_priv(netdev); 6694 struct pci_dev *pdev = adapter->pdev; 6695 struct e1000_hw *hw = &adapter->hw; 6696 unsigned long event = *(unsigned long *)data; 6697 6698 switch (event) { 6699 case DCA_PROVIDER_ADD: 6700 /* if already enabled, don't do it again */ 6701 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 6702 break; 6703 if (dca_add_requester(dev) == 0) { 6704 adapter->flags |= IGB_FLAG_DCA_ENABLED; 6705 dev_info(&pdev->dev, "DCA enabled\n"); 6706 igb_setup_dca(adapter); 6707 break; 6708 } 6709 fallthrough; /* since DCA is disabled. */ 6710 case DCA_PROVIDER_REMOVE: 6711 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 6712 /* without this a class_device is left 6713 * hanging around in the sysfs model 6714 */ 6715 dca_remove_requester(dev); 6716 dev_info(&pdev->dev, "DCA disabled\n"); 6717 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 6718 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 6719 } 6720 break; 6721 } 6722 6723 return 0; 6724 } 6725 6726 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 6727 void *p) 6728 { 6729 int ret_val; 6730 6731 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 6732 __igb_notify_dca); 6733 6734 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 6735 } 6736 #endif /* CONFIG_IGB_DCA */ 6737 6738 #ifdef CONFIG_PCI_IOV 6739 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 6740 { 6741 unsigned char mac_addr[ETH_ALEN]; 6742 6743 eth_zero_addr(mac_addr); 6744 igb_set_vf_mac(adapter, vf, mac_addr); 6745 6746 /* By default spoof check is enabled for all VFs */ 6747 adapter->vf_data[vf].spoofchk_enabled = true; 6748 6749 /* By default VFs are not trusted */ 6750 adapter->vf_data[vf].trusted = false; 6751 6752 return 0; 6753 } 6754 6755 #endif 6756 static void igb_ping_all_vfs(struct igb_adapter *adapter) 6757 { 6758 struct e1000_hw *hw = &adapter->hw; 6759 u32 ping; 6760 int i; 6761 6762 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 6763 ping = E1000_PF_CONTROL_MSG; 6764 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 6765 ping |= E1000_VT_MSGTYPE_CTS; 6766 igb_write_mbx(hw, &ping, 1, i); 6767 } 6768 } 6769 6770 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 6771 { 6772 struct e1000_hw *hw = &adapter->hw; 6773 u32 vmolr = rd32(E1000_VMOLR(vf)); 6774 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6775 6776 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 6777 IGB_VF_FLAG_MULTI_PROMISC); 6778 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 6779 6780 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 6781 vmolr |= E1000_VMOLR_MPME; 6782 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 6783 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 6784 } else { 6785 /* if we have hashes and we are clearing a multicast promisc 6786 * flag we need to write the hashes to the MTA as this step 6787 * was previously skipped 6788 */ 6789 if (vf_data->num_vf_mc_hashes > 30) { 6790 vmolr |= E1000_VMOLR_MPME; 6791 } else if (vf_data->num_vf_mc_hashes) { 6792 int j; 6793 6794 vmolr |= E1000_VMOLR_ROMPE; 6795 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 6796 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 6797 } 6798 } 6799 6800 wr32(E1000_VMOLR(vf), vmolr); 6801 6802 /* there are flags left unprocessed, likely not supported */ 6803 if (*msgbuf & E1000_VT_MSGINFO_MASK) 6804 return -EINVAL; 6805 6806 return 0; 6807 } 6808 6809 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 6810 u32 *msgbuf, u32 vf) 6811 { 6812 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 6813 u16 *hash_list = (u16 *)&msgbuf[1]; 6814 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6815 int i; 6816 6817 /* salt away the number of multicast addresses assigned 6818 * to this VF for later use to restore when the PF multi cast 6819 * list changes 6820 */ 6821 vf_data->num_vf_mc_hashes = n; 6822 6823 /* only up to 30 hash values supported */ 6824 if (n > 30) 6825 n = 30; 6826 6827 /* store the hashes for later use */ 6828 for (i = 0; i < n; i++) 6829 vf_data->vf_mc_hashes[i] = hash_list[i]; 6830 6831 /* Flush and reset the mta with the new values */ 6832 igb_set_rx_mode(adapter->netdev); 6833 6834 return 0; 6835 } 6836 6837 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 6838 { 6839 struct e1000_hw *hw = &adapter->hw; 6840 struct vf_data_storage *vf_data; 6841 int i, j; 6842 6843 for (i = 0; i < adapter->vfs_allocated_count; i++) { 6844 u32 vmolr = rd32(E1000_VMOLR(i)); 6845 6846 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 6847 6848 vf_data = &adapter->vf_data[i]; 6849 6850 if ((vf_data->num_vf_mc_hashes > 30) || 6851 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 6852 vmolr |= E1000_VMOLR_MPME; 6853 } else if (vf_data->num_vf_mc_hashes) { 6854 vmolr |= E1000_VMOLR_ROMPE; 6855 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 6856 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 6857 } 6858 wr32(E1000_VMOLR(i), vmolr); 6859 } 6860 } 6861 6862 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 6863 { 6864 struct e1000_hw *hw = &adapter->hw; 6865 u32 pool_mask, vlvf_mask, i; 6866 6867 /* create mask for VF and other pools */ 6868 pool_mask = E1000_VLVF_POOLSEL_MASK; 6869 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 6870 6871 /* drop PF from pool bits */ 6872 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 6873 adapter->vfs_allocated_count); 6874 6875 /* Find the vlan filter for this id */ 6876 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 6877 u32 vlvf = rd32(E1000_VLVF(i)); 6878 u32 vfta_mask, vid, vfta; 6879 6880 /* remove the vf from the pool */ 6881 if (!(vlvf & vlvf_mask)) 6882 continue; 6883 6884 /* clear out bit from VLVF */ 6885 vlvf ^= vlvf_mask; 6886 6887 /* if other pools are present, just remove ourselves */ 6888 if (vlvf & pool_mask) 6889 goto update_vlvfb; 6890 6891 /* if PF is present, leave VFTA */ 6892 if (vlvf & E1000_VLVF_POOLSEL_MASK) 6893 goto update_vlvf; 6894 6895 vid = vlvf & E1000_VLVF_VLANID_MASK; 6896 vfta_mask = BIT(vid % 32); 6897 6898 /* clear bit from VFTA */ 6899 vfta = adapter->shadow_vfta[vid / 32]; 6900 if (vfta & vfta_mask) 6901 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 6902 update_vlvf: 6903 /* clear pool selection enable */ 6904 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6905 vlvf &= E1000_VLVF_POOLSEL_MASK; 6906 else 6907 vlvf = 0; 6908 update_vlvfb: 6909 /* clear pool bits */ 6910 wr32(E1000_VLVF(i), vlvf); 6911 } 6912 } 6913 6914 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 6915 { 6916 u32 vlvf; 6917 int idx; 6918 6919 /* short cut the special case */ 6920 if (vlan == 0) 6921 return 0; 6922 6923 /* Search for the VLAN id in the VLVF entries */ 6924 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 6925 vlvf = rd32(E1000_VLVF(idx)); 6926 if ((vlvf & VLAN_VID_MASK) == vlan) 6927 break; 6928 } 6929 6930 return idx; 6931 } 6932 6933 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 6934 { 6935 struct e1000_hw *hw = &adapter->hw; 6936 u32 bits, pf_id; 6937 int idx; 6938 6939 idx = igb_find_vlvf_entry(hw, vid); 6940 if (!idx) 6941 return; 6942 6943 /* See if any other pools are set for this VLAN filter 6944 * entry other than the PF. 6945 */ 6946 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 6947 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 6948 bits &= rd32(E1000_VLVF(idx)); 6949 6950 /* Disable the filter so this falls into the default pool. */ 6951 if (!bits) { 6952 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6953 wr32(E1000_VLVF(idx), BIT(pf_id)); 6954 else 6955 wr32(E1000_VLVF(idx), 0); 6956 } 6957 } 6958 6959 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 6960 bool add, u32 vf) 6961 { 6962 int pf_id = adapter->vfs_allocated_count; 6963 struct e1000_hw *hw = &adapter->hw; 6964 int err; 6965 6966 /* If VLAN overlaps with one the PF is currently monitoring make 6967 * sure that we are able to allocate a VLVF entry. This may be 6968 * redundant but it guarantees PF will maintain visibility to 6969 * the VLAN. 6970 */ 6971 if (add && test_bit(vid, adapter->active_vlans)) { 6972 err = igb_vfta_set(hw, vid, pf_id, true, false); 6973 if (err) 6974 return err; 6975 } 6976 6977 err = igb_vfta_set(hw, vid, vf, add, false); 6978 6979 if (add && !err) 6980 return err; 6981 6982 /* If we failed to add the VF VLAN or we are removing the VF VLAN 6983 * we may need to drop the PF pool bit in order to allow us to free 6984 * up the VLVF resources. 6985 */ 6986 if (test_bit(vid, adapter->active_vlans) || 6987 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 6988 igb_update_pf_vlvf(adapter, vid); 6989 6990 return err; 6991 } 6992 6993 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 6994 { 6995 struct e1000_hw *hw = &adapter->hw; 6996 6997 if (vid) 6998 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 6999 else 7000 wr32(E1000_VMVIR(vf), 0); 7001 } 7002 7003 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7004 u16 vlan, u8 qos) 7005 { 7006 int err; 7007 7008 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7009 if (err) 7010 return err; 7011 7012 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7013 igb_set_vmolr(adapter, vf, !vlan); 7014 7015 /* revoke access to previous VLAN */ 7016 if (vlan != adapter->vf_data[vf].pf_vlan) 7017 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7018 false, vf); 7019 7020 adapter->vf_data[vf].pf_vlan = vlan; 7021 adapter->vf_data[vf].pf_qos = qos; 7022 igb_set_vf_vlan_strip(adapter, vf, true); 7023 dev_info(&adapter->pdev->dev, 7024 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7025 if (test_bit(__IGB_DOWN, &adapter->state)) { 7026 dev_warn(&adapter->pdev->dev, 7027 "The VF VLAN has been set, but the PF device is not up.\n"); 7028 dev_warn(&adapter->pdev->dev, 7029 "Bring the PF device up before attempting to use the VF device.\n"); 7030 } 7031 7032 return err; 7033 } 7034 7035 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7036 { 7037 /* Restore tagless access via VLAN 0 */ 7038 igb_set_vf_vlan(adapter, 0, true, vf); 7039 7040 igb_set_vmvir(adapter, 0, vf); 7041 igb_set_vmolr(adapter, vf, true); 7042 7043 /* Remove any PF assigned VLAN */ 7044 if (adapter->vf_data[vf].pf_vlan) 7045 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7046 false, vf); 7047 7048 adapter->vf_data[vf].pf_vlan = 0; 7049 adapter->vf_data[vf].pf_qos = 0; 7050 igb_set_vf_vlan_strip(adapter, vf, false); 7051 7052 return 0; 7053 } 7054 7055 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7056 u16 vlan, u8 qos, __be16 vlan_proto) 7057 { 7058 struct igb_adapter *adapter = netdev_priv(netdev); 7059 7060 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7061 return -EINVAL; 7062 7063 if (vlan_proto != htons(ETH_P_8021Q)) 7064 return -EPROTONOSUPPORT; 7065 7066 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7067 igb_disable_port_vlan(adapter, vf); 7068 } 7069 7070 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7071 { 7072 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7073 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7074 int ret; 7075 7076 if (adapter->vf_data[vf].pf_vlan) 7077 return -1; 7078 7079 /* VLAN 0 is a special case, don't allow it to be removed */ 7080 if (!vid && !add) 7081 return 0; 7082 7083 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7084 if (!ret) 7085 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7086 return ret; 7087 } 7088 7089 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7090 { 7091 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7092 7093 /* clear flags - except flag that indicates PF has set the MAC */ 7094 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7095 vf_data->last_nack = jiffies; 7096 7097 /* reset vlans for device */ 7098 igb_clear_vf_vfta(adapter, vf); 7099 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7100 igb_set_vmvir(adapter, vf_data->pf_vlan | 7101 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7102 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7103 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7104 7105 /* reset multicast table array for vf */ 7106 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7107 7108 /* Flush and reset the mta with the new values */ 7109 igb_set_rx_mode(adapter->netdev); 7110 } 7111 7112 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7113 { 7114 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7115 7116 /* clear mac address as we were hotplug removed/added */ 7117 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7118 eth_zero_addr(vf_mac); 7119 7120 /* process remaining reset events */ 7121 igb_vf_reset(adapter, vf); 7122 } 7123 7124 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7125 { 7126 struct e1000_hw *hw = &adapter->hw; 7127 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7128 u32 reg, msgbuf[3]; 7129 u8 *addr = (u8 *)(&msgbuf[1]); 7130 7131 /* process all the same items cleared in a function level reset */ 7132 igb_vf_reset(adapter, vf); 7133 7134 /* set vf mac address */ 7135 igb_set_vf_mac(adapter, vf, vf_mac); 7136 7137 /* enable transmit and receive for vf */ 7138 reg = rd32(E1000_VFTE); 7139 wr32(E1000_VFTE, reg | BIT(vf)); 7140 reg = rd32(E1000_VFRE); 7141 wr32(E1000_VFRE, reg | BIT(vf)); 7142 7143 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7144 7145 /* reply to reset with ack and vf mac address */ 7146 if (!is_zero_ether_addr(vf_mac)) { 7147 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7148 memcpy(addr, vf_mac, ETH_ALEN); 7149 } else { 7150 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7151 } 7152 igb_write_mbx(hw, msgbuf, 3, vf); 7153 } 7154 7155 static void igb_flush_mac_table(struct igb_adapter *adapter) 7156 { 7157 struct e1000_hw *hw = &adapter->hw; 7158 int i; 7159 7160 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7161 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7162 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 7163 adapter->mac_table[i].queue = 0; 7164 igb_rar_set_index(adapter, i); 7165 } 7166 } 7167 7168 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7169 { 7170 struct e1000_hw *hw = &adapter->hw; 7171 /* do not count rar entries reserved for VFs MAC addresses */ 7172 int rar_entries = hw->mac.rar_entry_count - 7173 adapter->vfs_allocated_count; 7174 int i, count = 0; 7175 7176 for (i = 0; i < rar_entries; i++) { 7177 /* do not count default entries */ 7178 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7179 continue; 7180 7181 /* do not count "in use" entries for different queues */ 7182 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7183 (adapter->mac_table[i].queue != queue)) 7184 continue; 7185 7186 count++; 7187 } 7188 7189 return count; 7190 } 7191 7192 /* Set default MAC address for the PF in the first RAR entry */ 7193 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7194 { 7195 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7196 7197 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7198 mac_table->queue = adapter->vfs_allocated_count; 7199 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7200 7201 igb_rar_set_index(adapter, 0); 7202 } 7203 7204 /* If the filter to be added and an already existing filter express 7205 * the same address and address type, it should be possible to only 7206 * override the other configurations, for example the queue to steer 7207 * traffic. 7208 */ 7209 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7210 const u8 *addr, const u8 flags) 7211 { 7212 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7213 return true; 7214 7215 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7216 (flags & IGB_MAC_STATE_SRC_ADDR)) 7217 return false; 7218 7219 if (!ether_addr_equal(addr, entry->addr)) 7220 return false; 7221 7222 return true; 7223 } 7224 7225 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7226 * 'flags' is used to indicate what kind of match is made, match is by 7227 * default for the destination address, if matching by source address 7228 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7229 */ 7230 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7231 const u8 *addr, const u8 queue, 7232 const u8 flags) 7233 { 7234 struct e1000_hw *hw = &adapter->hw; 7235 int rar_entries = hw->mac.rar_entry_count - 7236 adapter->vfs_allocated_count; 7237 int i; 7238 7239 if (is_zero_ether_addr(addr)) 7240 return -EINVAL; 7241 7242 /* Search for the first empty entry in the MAC table. 7243 * Do not touch entries at the end of the table reserved for the VF MAC 7244 * addresses. 7245 */ 7246 for (i = 0; i < rar_entries; i++) { 7247 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7248 addr, flags)) 7249 continue; 7250 7251 ether_addr_copy(adapter->mac_table[i].addr, addr); 7252 adapter->mac_table[i].queue = queue; 7253 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7254 7255 igb_rar_set_index(adapter, i); 7256 return i; 7257 } 7258 7259 return -ENOSPC; 7260 } 7261 7262 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7263 const u8 queue) 7264 { 7265 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7266 } 7267 7268 /* Remove a MAC filter for 'addr' directing matching traffic to 7269 * 'queue', 'flags' is used to indicate what kind of match need to be 7270 * removed, match is by default for the destination address, if 7271 * matching by source address is to be removed the flag 7272 * IGB_MAC_STATE_SRC_ADDR can be used. 7273 */ 7274 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7275 const u8 *addr, const u8 queue, 7276 const u8 flags) 7277 { 7278 struct e1000_hw *hw = &adapter->hw; 7279 int rar_entries = hw->mac.rar_entry_count - 7280 adapter->vfs_allocated_count; 7281 int i; 7282 7283 if (is_zero_ether_addr(addr)) 7284 return -EINVAL; 7285 7286 /* Search for matching entry in the MAC table based on given address 7287 * and queue. Do not touch entries at the end of the table reserved 7288 * for the VF MAC addresses. 7289 */ 7290 for (i = 0; i < rar_entries; i++) { 7291 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7292 continue; 7293 if ((adapter->mac_table[i].state & flags) != flags) 7294 continue; 7295 if (adapter->mac_table[i].queue != queue) 7296 continue; 7297 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7298 continue; 7299 7300 /* When a filter for the default address is "deleted", 7301 * we return it to its initial configuration 7302 */ 7303 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7304 adapter->mac_table[i].state = 7305 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7306 adapter->mac_table[i].queue = 7307 adapter->vfs_allocated_count; 7308 } else { 7309 adapter->mac_table[i].state = 0; 7310 adapter->mac_table[i].queue = 0; 7311 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 7312 } 7313 7314 igb_rar_set_index(adapter, i); 7315 return 0; 7316 } 7317 7318 return -ENOENT; 7319 } 7320 7321 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7322 const u8 queue) 7323 { 7324 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7325 } 7326 7327 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7328 const u8 *addr, u8 queue, u8 flags) 7329 { 7330 struct e1000_hw *hw = &adapter->hw; 7331 7332 /* In theory, this should be supported on 82575 as well, but 7333 * that part wasn't easily accessible during development. 7334 */ 7335 if (hw->mac.type != e1000_i210) 7336 return -EOPNOTSUPP; 7337 7338 return igb_add_mac_filter_flags(adapter, addr, queue, 7339 IGB_MAC_STATE_QUEUE_STEERING | flags); 7340 } 7341 7342 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7343 const u8 *addr, u8 queue, u8 flags) 7344 { 7345 return igb_del_mac_filter_flags(adapter, addr, queue, 7346 IGB_MAC_STATE_QUEUE_STEERING | flags); 7347 } 7348 7349 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7350 { 7351 struct igb_adapter *adapter = netdev_priv(netdev); 7352 int ret; 7353 7354 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7355 7356 return min_t(int, ret, 0); 7357 } 7358 7359 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7360 { 7361 struct igb_adapter *adapter = netdev_priv(netdev); 7362 7363 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7364 7365 return 0; 7366 } 7367 7368 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7369 const u32 info, const u8 *addr) 7370 { 7371 struct pci_dev *pdev = adapter->pdev; 7372 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7373 struct list_head *pos; 7374 struct vf_mac_filter *entry = NULL; 7375 int ret = 0; 7376 7377 switch (info) { 7378 case E1000_VF_MAC_FILTER_CLR: 7379 /* remove all unicast MAC filters related to the current VF */ 7380 list_for_each(pos, &adapter->vf_macs.l) { 7381 entry = list_entry(pos, struct vf_mac_filter, l); 7382 if (entry->vf == vf) { 7383 entry->vf = -1; 7384 entry->free = true; 7385 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7386 } 7387 } 7388 break; 7389 case E1000_VF_MAC_FILTER_ADD: 7390 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7391 !vf_data->trusted) { 7392 dev_warn(&pdev->dev, 7393 "VF %d requested MAC filter but is administratively denied\n", 7394 vf); 7395 return -EINVAL; 7396 } 7397 if (!is_valid_ether_addr(addr)) { 7398 dev_warn(&pdev->dev, 7399 "VF %d attempted to set invalid MAC filter\n", 7400 vf); 7401 return -EINVAL; 7402 } 7403 7404 /* try to find empty slot in the list */ 7405 list_for_each(pos, &adapter->vf_macs.l) { 7406 entry = list_entry(pos, struct vf_mac_filter, l); 7407 if (entry->free) 7408 break; 7409 } 7410 7411 if (entry && entry->free) { 7412 entry->free = false; 7413 entry->vf = vf; 7414 ether_addr_copy(entry->vf_mac, addr); 7415 7416 ret = igb_add_mac_filter(adapter, addr, vf); 7417 ret = min_t(int, ret, 0); 7418 } else { 7419 ret = -ENOSPC; 7420 } 7421 7422 if (ret == -ENOSPC) 7423 dev_warn(&pdev->dev, 7424 "VF %d has requested MAC filter but there is no space for it\n", 7425 vf); 7426 break; 7427 default: 7428 ret = -EINVAL; 7429 break; 7430 } 7431 7432 return ret; 7433 } 7434 7435 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7436 { 7437 struct pci_dev *pdev = adapter->pdev; 7438 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7439 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7440 7441 /* The VF MAC Address is stored in a packed array of bytes 7442 * starting at the second 32 bit word of the msg array 7443 */ 7444 unsigned char *addr = (unsigned char *)&msg[1]; 7445 int ret = 0; 7446 7447 if (!info) { 7448 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7449 !vf_data->trusted) { 7450 dev_warn(&pdev->dev, 7451 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 7452 vf); 7453 return -EINVAL; 7454 } 7455 7456 if (!is_valid_ether_addr(addr)) { 7457 dev_warn(&pdev->dev, 7458 "VF %d attempted to set invalid MAC\n", 7459 vf); 7460 return -EINVAL; 7461 } 7462 7463 ret = igb_set_vf_mac(adapter, vf, addr); 7464 } else { 7465 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 7466 } 7467 7468 return ret; 7469 } 7470 7471 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 7472 { 7473 struct e1000_hw *hw = &adapter->hw; 7474 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7475 u32 msg = E1000_VT_MSGTYPE_NACK; 7476 7477 /* if device isn't clear to send it shouldn't be reading either */ 7478 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 7479 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 7480 igb_write_mbx(hw, &msg, 1, vf); 7481 vf_data->last_nack = jiffies; 7482 } 7483 } 7484 7485 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 7486 { 7487 struct pci_dev *pdev = adapter->pdev; 7488 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 7489 struct e1000_hw *hw = &adapter->hw; 7490 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7491 s32 retval; 7492 7493 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 7494 7495 if (retval) { 7496 /* if receive failed revoke VF CTS stats and restart init */ 7497 dev_err(&pdev->dev, "Error receiving message from VF\n"); 7498 vf_data->flags &= ~IGB_VF_FLAG_CTS; 7499 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7500 goto unlock; 7501 goto out; 7502 } 7503 7504 /* this is a message we already processed, do nothing */ 7505 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 7506 goto unlock; 7507 7508 /* until the vf completes a reset it should not be 7509 * allowed to start any configuration. 7510 */ 7511 if (msgbuf[0] == E1000_VF_RESET) { 7512 /* unlocks mailbox */ 7513 igb_vf_reset_msg(adapter, vf); 7514 return; 7515 } 7516 7517 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 7518 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7519 goto unlock; 7520 retval = -1; 7521 goto out; 7522 } 7523 7524 switch ((msgbuf[0] & 0xFFFF)) { 7525 case E1000_VF_SET_MAC_ADDR: 7526 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 7527 break; 7528 case E1000_VF_SET_PROMISC: 7529 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 7530 break; 7531 case E1000_VF_SET_MULTICAST: 7532 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 7533 break; 7534 case E1000_VF_SET_LPE: 7535 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 7536 break; 7537 case E1000_VF_SET_VLAN: 7538 retval = -1; 7539 if (vf_data->pf_vlan) 7540 dev_warn(&pdev->dev, 7541 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 7542 vf); 7543 else 7544 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 7545 break; 7546 default: 7547 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 7548 retval = -1; 7549 break; 7550 } 7551 7552 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 7553 out: 7554 /* notify the VF of the results of what it sent us */ 7555 if (retval) 7556 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 7557 else 7558 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 7559 7560 /* unlocks mailbox */ 7561 igb_write_mbx(hw, msgbuf, 1, vf); 7562 return; 7563 7564 unlock: 7565 igb_unlock_mbx(hw, vf); 7566 } 7567 7568 static void igb_msg_task(struct igb_adapter *adapter) 7569 { 7570 struct e1000_hw *hw = &adapter->hw; 7571 u32 vf; 7572 7573 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 7574 /* process any reset requests */ 7575 if (!igb_check_for_rst(hw, vf)) 7576 igb_vf_reset_event(adapter, vf); 7577 7578 /* process any messages pending */ 7579 if (!igb_check_for_msg(hw, vf)) 7580 igb_rcv_msg_from_vf(adapter, vf); 7581 7582 /* process any acks */ 7583 if (!igb_check_for_ack(hw, vf)) 7584 igb_rcv_ack_from_vf(adapter, vf); 7585 } 7586 } 7587 7588 /** 7589 * igb_set_uta - Set unicast filter table address 7590 * @adapter: board private structure 7591 * @set: boolean indicating if we are setting or clearing bits 7592 * 7593 * The unicast table address is a register array of 32-bit registers. 7594 * The table is meant to be used in a way similar to how the MTA is used 7595 * however due to certain limitations in the hardware it is necessary to 7596 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 7597 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 7598 **/ 7599 static void igb_set_uta(struct igb_adapter *adapter, bool set) 7600 { 7601 struct e1000_hw *hw = &adapter->hw; 7602 u32 uta = set ? ~0 : 0; 7603 int i; 7604 7605 /* we only need to do this if VMDq is enabled */ 7606 if (!adapter->vfs_allocated_count) 7607 return; 7608 7609 for (i = hw->mac.uta_reg_count; i--;) 7610 array_wr32(E1000_UTA, i, uta); 7611 } 7612 7613 /** 7614 * igb_intr_msi - Interrupt Handler 7615 * @irq: interrupt number 7616 * @data: pointer to a network interface device structure 7617 **/ 7618 static irqreturn_t igb_intr_msi(int irq, void *data) 7619 { 7620 struct igb_adapter *adapter = data; 7621 struct igb_q_vector *q_vector = adapter->q_vector[0]; 7622 struct e1000_hw *hw = &adapter->hw; 7623 /* read ICR disables interrupts using IAM */ 7624 u32 icr = rd32(E1000_ICR); 7625 7626 igb_write_itr(q_vector); 7627 7628 if (icr & E1000_ICR_DRSTA) 7629 schedule_work(&adapter->reset_task); 7630 7631 if (icr & E1000_ICR_DOUTSYNC) { 7632 /* HW is reporting DMA is out of sync */ 7633 adapter->stats.doosync++; 7634 } 7635 7636 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 7637 hw->mac.get_link_status = 1; 7638 if (!test_bit(__IGB_DOWN, &adapter->state)) 7639 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7640 } 7641 7642 if (icr & E1000_ICR_TS) 7643 igb_tsync_interrupt(adapter); 7644 7645 napi_schedule(&q_vector->napi); 7646 7647 return IRQ_HANDLED; 7648 } 7649 7650 /** 7651 * igb_intr - Legacy Interrupt Handler 7652 * @irq: interrupt number 7653 * @data: pointer to a network interface device structure 7654 **/ 7655 static irqreturn_t igb_intr(int irq, void *data) 7656 { 7657 struct igb_adapter *adapter = data; 7658 struct igb_q_vector *q_vector = adapter->q_vector[0]; 7659 struct e1000_hw *hw = &adapter->hw; 7660 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 7661 * need for the IMC write 7662 */ 7663 u32 icr = rd32(E1000_ICR); 7664 7665 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 7666 * not set, then the adapter didn't send an interrupt 7667 */ 7668 if (!(icr & E1000_ICR_INT_ASSERTED)) 7669 return IRQ_NONE; 7670 7671 igb_write_itr(q_vector); 7672 7673 if (icr & E1000_ICR_DRSTA) 7674 schedule_work(&adapter->reset_task); 7675 7676 if (icr & E1000_ICR_DOUTSYNC) { 7677 /* HW is reporting DMA is out of sync */ 7678 adapter->stats.doosync++; 7679 } 7680 7681 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 7682 hw->mac.get_link_status = 1; 7683 /* guard against interrupt when we're going down */ 7684 if (!test_bit(__IGB_DOWN, &adapter->state)) 7685 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7686 } 7687 7688 if (icr & E1000_ICR_TS) 7689 igb_tsync_interrupt(adapter); 7690 7691 napi_schedule(&q_vector->napi); 7692 7693 return IRQ_HANDLED; 7694 } 7695 7696 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 7697 { 7698 struct igb_adapter *adapter = q_vector->adapter; 7699 struct e1000_hw *hw = &adapter->hw; 7700 7701 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 7702 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 7703 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 7704 igb_set_itr(q_vector); 7705 else 7706 igb_update_ring_itr(q_vector); 7707 } 7708 7709 if (!test_bit(__IGB_DOWN, &adapter->state)) { 7710 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7711 wr32(E1000_EIMS, q_vector->eims_value); 7712 else 7713 igb_irq_enable(adapter); 7714 } 7715 } 7716 7717 /** 7718 * igb_poll - NAPI Rx polling callback 7719 * @napi: napi polling structure 7720 * @budget: count of how many packets we should handle 7721 **/ 7722 static int igb_poll(struct napi_struct *napi, int budget) 7723 { 7724 struct igb_q_vector *q_vector = container_of(napi, 7725 struct igb_q_vector, 7726 napi); 7727 bool clean_complete = true; 7728 int work_done = 0; 7729 7730 #ifdef CONFIG_IGB_DCA 7731 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 7732 igb_update_dca(q_vector); 7733 #endif 7734 if (q_vector->tx.ring) 7735 clean_complete = igb_clean_tx_irq(q_vector, budget); 7736 7737 if (q_vector->rx.ring) { 7738 int cleaned = igb_clean_rx_irq(q_vector, budget); 7739 7740 work_done += cleaned; 7741 if (cleaned >= budget) 7742 clean_complete = false; 7743 } 7744 7745 /* If all work not completed, return budget and keep polling */ 7746 if (!clean_complete) 7747 return budget; 7748 7749 /* Exit the polling mode, but don't re-enable interrupts if stack might 7750 * poll us due to busy-polling 7751 */ 7752 if (likely(napi_complete_done(napi, work_done))) 7753 igb_ring_irq_enable(q_vector); 7754 7755 return min(work_done, budget - 1); 7756 } 7757 7758 /** 7759 * igb_clean_tx_irq - Reclaim resources after transmit completes 7760 * @q_vector: pointer to q_vector containing needed info 7761 * @napi_budget: Used to determine if we are in netpoll 7762 * 7763 * returns true if ring is completely cleaned 7764 **/ 7765 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 7766 { 7767 struct igb_adapter *adapter = q_vector->adapter; 7768 struct igb_ring *tx_ring = q_vector->tx.ring; 7769 struct igb_tx_buffer *tx_buffer; 7770 union e1000_adv_tx_desc *tx_desc; 7771 unsigned int total_bytes = 0, total_packets = 0; 7772 unsigned int budget = q_vector->tx.work_limit; 7773 unsigned int i = tx_ring->next_to_clean; 7774 7775 if (test_bit(__IGB_DOWN, &adapter->state)) 7776 return true; 7777 7778 tx_buffer = &tx_ring->tx_buffer_info[i]; 7779 tx_desc = IGB_TX_DESC(tx_ring, i); 7780 i -= tx_ring->count; 7781 7782 do { 7783 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 7784 7785 /* if next_to_watch is not set then there is no work pending */ 7786 if (!eop_desc) 7787 break; 7788 7789 /* prevent any other reads prior to eop_desc */ 7790 smp_rmb(); 7791 7792 /* if DD is not set pending work has not been completed */ 7793 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 7794 break; 7795 7796 /* clear next_to_watch to prevent false hangs */ 7797 tx_buffer->next_to_watch = NULL; 7798 7799 /* update the statistics for this packet */ 7800 total_bytes += tx_buffer->bytecount; 7801 total_packets += tx_buffer->gso_segs; 7802 7803 /* free the skb */ 7804 napi_consume_skb(tx_buffer->skb, napi_budget); 7805 7806 /* unmap skb header data */ 7807 dma_unmap_single(tx_ring->dev, 7808 dma_unmap_addr(tx_buffer, dma), 7809 dma_unmap_len(tx_buffer, len), 7810 DMA_TO_DEVICE); 7811 7812 /* clear tx_buffer data */ 7813 dma_unmap_len_set(tx_buffer, len, 0); 7814 7815 /* clear last DMA location and unmap remaining buffers */ 7816 while (tx_desc != eop_desc) { 7817 tx_buffer++; 7818 tx_desc++; 7819 i++; 7820 if (unlikely(!i)) { 7821 i -= tx_ring->count; 7822 tx_buffer = tx_ring->tx_buffer_info; 7823 tx_desc = IGB_TX_DESC(tx_ring, 0); 7824 } 7825 7826 /* unmap any remaining paged data */ 7827 if (dma_unmap_len(tx_buffer, len)) { 7828 dma_unmap_page(tx_ring->dev, 7829 dma_unmap_addr(tx_buffer, dma), 7830 dma_unmap_len(tx_buffer, len), 7831 DMA_TO_DEVICE); 7832 dma_unmap_len_set(tx_buffer, len, 0); 7833 } 7834 } 7835 7836 /* move us one more past the eop_desc for start of next pkt */ 7837 tx_buffer++; 7838 tx_desc++; 7839 i++; 7840 if (unlikely(!i)) { 7841 i -= tx_ring->count; 7842 tx_buffer = tx_ring->tx_buffer_info; 7843 tx_desc = IGB_TX_DESC(tx_ring, 0); 7844 } 7845 7846 /* issue prefetch for next Tx descriptor */ 7847 prefetch(tx_desc); 7848 7849 /* update budget accounting */ 7850 budget--; 7851 } while (likely(budget)); 7852 7853 netdev_tx_completed_queue(txring_txq(tx_ring), 7854 total_packets, total_bytes); 7855 i += tx_ring->count; 7856 tx_ring->next_to_clean = i; 7857 u64_stats_update_begin(&tx_ring->tx_syncp); 7858 tx_ring->tx_stats.bytes += total_bytes; 7859 tx_ring->tx_stats.packets += total_packets; 7860 u64_stats_update_end(&tx_ring->tx_syncp); 7861 q_vector->tx.total_bytes += total_bytes; 7862 q_vector->tx.total_packets += total_packets; 7863 7864 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 7865 struct e1000_hw *hw = &adapter->hw; 7866 7867 /* Detect a transmit hang in hardware, this serializes the 7868 * check with the clearing of time_stamp and movement of i 7869 */ 7870 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 7871 if (tx_buffer->next_to_watch && 7872 time_after(jiffies, tx_buffer->time_stamp + 7873 (adapter->tx_timeout_factor * HZ)) && 7874 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 7875 7876 /* detected Tx unit hang */ 7877 dev_err(tx_ring->dev, 7878 "Detected Tx Unit Hang\n" 7879 " Tx Queue <%d>\n" 7880 " TDH <%x>\n" 7881 " TDT <%x>\n" 7882 " next_to_use <%x>\n" 7883 " next_to_clean <%x>\n" 7884 "buffer_info[next_to_clean]\n" 7885 " time_stamp <%lx>\n" 7886 " next_to_watch <%p>\n" 7887 " jiffies <%lx>\n" 7888 " desc.status <%x>\n", 7889 tx_ring->queue_index, 7890 rd32(E1000_TDH(tx_ring->reg_idx)), 7891 readl(tx_ring->tail), 7892 tx_ring->next_to_use, 7893 tx_ring->next_to_clean, 7894 tx_buffer->time_stamp, 7895 tx_buffer->next_to_watch, 7896 jiffies, 7897 tx_buffer->next_to_watch->wb.status); 7898 netif_stop_subqueue(tx_ring->netdev, 7899 tx_ring->queue_index); 7900 7901 /* we are about to reset, no point in enabling stuff */ 7902 return true; 7903 } 7904 } 7905 7906 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 7907 if (unlikely(total_packets && 7908 netif_carrier_ok(tx_ring->netdev) && 7909 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 7910 /* Make sure that anybody stopping the queue after this 7911 * sees the new next_to_clean. 7912 */ 7913 smp_mb(); 7914 if (__netif_subqueue_stopped(tx_ring->netdev, 7915 tx_ring->queue_index) && 7916 !(test_bit(__IGB_DOWN, &adapter->state))) { 7917 netif_wake_subqueue(tx_ring->netdev, 7918 tx_ring->queue_index); 7919 7920 u64_stats_update_begin(&tx_ring->tx_syncp); 7921 tx_ring->tx_stats.restart_queue++; 7922 u64_stats_update_end(&tx_ring->tx_syncp); 7923 } 7924 } 7925 7926 return !!budget; 7927 } 7928 7929 /** 7930 * igb_reuse_rx_page - page flip buffer and store it back on the ring 7931 * @rx_ring: rx descriptor ring to store buffers on 7932 * @old_buff: donor buffer to have page reused 7933 * 7934 * Synchronizes page for reuse by the adapter 7935 **/ 7936 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 7937 struct igb_rx_buffer *old_buff) 7938 { 7939 struct igb_rx_buffer *new_buff; 7940 u16 nta = rx_ring->next_to_alloc; 7941 7942 new_buff = &rx_ring->rx_buffer_info[nta]; 7943 7944 /* update, and store next to alloc */ 7945 nta++; 7946 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 7947 7948 /* Transfer page from old buffer to new buffer. 7949 * Move each member individually to avoid possible store 7950 * forwarding stalls. 7951 */ 7952 new_buff->dma = old_buff->dma; 7953 new_buff->page = old_buff->page; 7954 new_buff->page_offset = old_buff->page_offset; 7955 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 7956 } 7957 7958 static inline bool igb_page_is_reserved(struct page *page) 7959 { 7960 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 7961 } 7962 7963 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer) 7964 { 7965 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 7966 struct page *page = rx_buffer->page; 7967 7968 /* avoid re-using remote pages */ 7969 if (unlikely(igb_page_is_reserved(page))) 7970 return false; 7971 7972 #if (PAGE_SIZE < 8192) 7973 /* if we are only owner of page we can reuse it */ 7974 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 7975 return false; 7976 #else 7977 #define IGB_LAST_OFFSET \ 7978 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 7979 7980 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 7981 return false; 7982 #endif 7983 7984 /* If we have drained the page fragment pool we need to update 7985 * the pagecnt_bias and page count so that we fully restock the 7986 * number of references the driver holds. 7987 */ 7988 if (unlikely(!pagecnt_bias)) { 7989 page_ref_add(page, USHRT_MAX); 7990 rx_buffer->pagecnt_bias = USHRT_MAX; 7991 } 7992 7993 return true; 7994 } 7995 7996 /** 7997 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 7998 * @rx_ring: rx descriptor ring to transact packets on 7999 * @rx_buffer: buffer containing page to add 8000 * @skb: sk_buff to place the data into 8001 * @size: size of buffer to be added 8002 * 8003 * This function will add the data contained in rx_buffer->page to the skb. 8004 **/ 8005 static void igb_add_rx_frag(struct igb_ring *rx_ring, 8006 struct igb_rx_buffer *rx_buffer, 8007 struct sk_buff *skb, 8008 unsigned int size) 8009 { 8010 #if (PAGE_SIZE < 8192) 8011 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8012 #else 8013 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8014 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8015 SKB_DATA_ALIGN(size); 8016 #endif 8017 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8018 rx_buffer->page_offset, size, truesize); 8019 #if (PAGE_SIZE < 8192) 8020 rx_buffer->page_offset ^= truesize; 8021 #else 8022 rx_buffer->page_offset += truesize; 8023 #endif 8024 } 8025 8026 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8027 struct igb_rx_buffer *rx_buffer, 8028 union e1000_adv_rx_desc *rx_desc, 8029 unsigned int size) 8030 { 8031 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 8032 #if (PAGE_SIZE < 8192) 8033 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8034 #else 8035 unsigned int truesize = SKB_DATA_ALIGN(size); 8036 #endif 8037 unsigned int headlen; 8038 struct sk_buff *skb; 8039 8040 /* prefetch first cache line of first page */ 8041 prefetch(va); 8042 #if L1_CACHE_BYTES < 128 8043 prefetch(va + L1_CACHE_BYTES); 8044 #endif 8045 8046 /* allocate a skb to store the frags */ 8047 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8048 if (unlikely(!skb)) 8049 return NULL; 8050 8051 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) { 8052 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 8053 va += IGB_TS_HDR_LEN; 8054 size -= IGB_TS_HDR_LEN; 8055 } 8056 8057 /* Determine available headroom for copy */ 8058 headlen = size; 8059 if (headlen > IGB_RX_HDR_LEN) 8060 headlen = eth_get_headlen(skb->dev, va, IGB_RX_HDR_LEN); 8061 8062 /* align pull length to size of long to optimize memcpy performance */ 8063 memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long))); 8064 8065 /* update all of the pointers */ 8066 size -= headlen; 8067 if (size) { 8068 skb_add_rx_frag(skb, 0, rx_buffer->page, 8069 (va + headlen) - page_address(rx_buffer->page), 8070 size, truesize); 8071 #if (PAGE_SIZE < 8192) 8072 rx_buffer->page_offset ^= truesize; 8073 #else 8074 rx_buffer->page_offset += truesize; 8075 #endif 8076 } else { 8077 rx_buffer->pagecnt_bias++; 8078 } 8079 8080 return skb; 8081 } 8082 8083 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8084 struct igb_rx_buffer *rx_buffer, 8085 union e1000_adv_rx_desc *rx_desc, 8086 unsigned int size) 8087 { 8088 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 8089 #if (PAGE_SIZE < 8192) 8090 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8091 #else 8092 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8093 SKB_DATA_ALIGN(IGB_SKB_PAD + size); 8094 #endif 8095 struct sk_buff *skb; 8096 8097 /* prefetch first cache line of first page */ 8098 prefetch(va); 8099 #if L1_CACHE_BYTES < 128 8100 prefetch(va + L1_CACHE_BYTES); 8101 #endif 8102 8103 /* build an skb around the page buffer */ 8104 skb = build_skb(va - IGB_SKB_PAD, truesize); 8105 if (unlikely(!skb)) 8106 return NULL; 8107 8108 /* update pointers within the skb to store the data */ 8109 skb_reserve(skb, IGB_SKB_PAD); 8110 __skb_put(skb, size); 8111 8112 /* pull timestamp out of packet data */ 8113 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 8114 igb_ptp_rx_pktstamp(rx_ring->q_vector, skb->data, skb); 8115 __skb_pull(skb, IGB_TS_HDR_LEN); 8116 } 8117 8118 /* update buffer offset */ 8119 #if (PAGE_SIZE < 8192) 8120 rx_buffer->page_offset ^= truesize; 8121 #else 8122 rx_buffer->page_offset += truesize; 8123 #endif 8124 8125 return skb; 8126 } 8127 8128 static inline void igb_rx_checksum(struct igb_ring *ring, 8129 union e1000_adv_rx_desc *rx_desc, 8130 struct sk_buff *skb) 8131 { 8132 skb_checksum_none_assert(skb); 8133 8134 /* Ignore Checksum bit is set */ 8135 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8136 return; 8137 8138 /* Rx checksum disabled via ethtool */ 8139 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8140 return; 8141 8142 /* TCP/UDP checksum error bit is set */ 8143 if (igb_test_staterr(rx_desc, 8144 E1000_RXDEXT_STATERR_TCPE | 8145 E1000_RXDEXT_STATERR_IPE)) { 8146 /* work around errata with sctp packets where the TCPE aka 8147 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8148 * packets, (aka let the stack check the crc32c) 8149 */ 8150 if (!((skb->len == 60) && 8151 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8152 u64_stats_update_begin(&ring->rx_syncp); 8153 ring->rx_stats.csum_err++; 8154 u64_stats_update_end(&ring->rx_syncp); 8155 } 8156 /* let the stack verify checksum errors */ 8157 return; 8158 } 8159 /* It must be a TCP or UDP packet with a valid checksum */ 8160 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8161 E1000_RXD_STAT_UDPCS)) 8162 skb->ip_summed = CHECKSUM_UNNECESSARY; 8163 8164 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8165 le32_to_cpu(rx_desc->wb.upper.status_error)); 8166 } 8167 8168 static inline void igb_rx_hash(struct igb_ring *ring, 8169 union e1000_adv_rx_desc *rx_desc, 8170 struct sk_buff *skb) 8171 { 8172 if (ring->netdev->features & NETIF_F_RXHASH) 8173 skb_set_hash(skb, 8174 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8175 PKT_HASH_TYPE_L3); 8176 } 8177 8178 /** 8179 * igb_is_non_eop - process handling of non-EOP buffers 8180 * @rx_ring: Rx ring being processed 8181 * @rx_desc: Rx descriptor for current buffer 8182 * @skb: current socket buffer containing buffer in progress 8183 * 8184 * This function updates next to clean. If the buffer is an EOP buffer 8185 * this function exits returning false, otherwise it will place the 8186 * sk_buff in the next buffer to be chained and return true indicating 8187 * that this is in fact a non-EOP buffer. 8188 **/ 8189 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8190 union e1000_adv_rx_desc *rx_desc) 8191 { 8192 u32 ntc = rx_ring->next_to_clean + 1; 8193 8194 /* fetch, update, and store next to clean */ 8195 ntc = (ntc < rx_ring->count) ? ntc : 0; 8196 rx_ring->next_to_clean = ntc; 8197 8198 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8199 8200 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8201 return false; 8202 8203 return true; 8204 } 8205 8206 /** 8207 * igb_cleanup_headers - Correct corrupted or empty headers 8208 * @rx_ring: rx descriptor ring packet is being transacted on 8209 * @rx_desc: pointer to the EOP Rx descriptor 8210 * @skb: pointer to current skb being fixed 8211 * 8212 * Address the case where we are pulling data in on pages only 8213 * and as such no data is present in the skb header. 8214 * 8215 * In addition if skb is not at least 60 bytes we need to pad it so that 8216 * it is large enough to qualify as a valid Ethernet frame. 8217 * 8218 * Returns true if an error was encountered and skb was freed. 8219 **/ 8220 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8221 union e1000_adv_rx_desc *rx_desc, 8222 struct sk_buff *skb) 8223 { 8224 if (unlikely((igb_test_staterr(rx_desc, 8225 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8226 struct net_device *netdev = rx_ring->netdev; 8227 if (!(netdev->features & NETIF_F_RXALL)) { 8228 dev_kfree_skb_any(skb); 8229 return true; 8230 } 8231 } 8232 8233 /* if eth_skb_pad returns an error the skb was freed */ 8234 if (eth_skb_pad(skb)) 8235 return true; 8236 8237 return false; 8238 } 8239 8240 /** 8241 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8242 * @rx_ring: rx descriptor ring packet is being transacted on 8243 * @rx_desc: pointer to the EOP Rx descriptor 8244 * @skb: pointer to current skb being populated 8245 * 8246 * This function checks the ring, descriptor, and packet information in 8247 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8248 * other fields within the skb. 8249 **/ 8250 static void igb_process_skb_fields(struct igb_ring *rx_ring, 8251 union e1000_adv_rx_desc *rx_desc, 8252 struct sk_buff *skb) 8253 { 8254 struct net_device *dev = rx_ring->netdev; 8255 8256 igb_rx_hash(rx_ring, rx_desc, skb); 8257 8258 igb_rx_checksum(rx_ring, rx_desc, skb); 8259 8260 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8261 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8262 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8263 8264 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8265 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8266 u16 vid; 8267 8268 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8269 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8270 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 8271 else 8272 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8273 8274 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8275 } 8276 8277 skb_record_rx_queue(skb, rx_ring->queue_index); 8278 8279 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8280 } 8281 8282 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8283 const unsigned int size) 8284 { 8285 struct igb_rx_buffer *rx_buffer; 8286 8287 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8288 prefetchw(rx_buffer->page); 8289 8290 /* we are reusing so sync this buffer for CPU use */ 8291 dma_sync_single_range_for_cpu(rx_ring->dev, 8292 rx_buffer->dma, 8293 rx_buffer->page_offset, 8294 size, 8295 DMA_FROM_DEVICE); 8296 8297 rx_buffer->pagecnt_bias--; 8298 8299 return rx_buffer; 8300 } 8301 8302 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8303 struct igb_rx_buffer *rx_buffer) 8304 { 8305 if (igb_can_reuse_rx_page(rx_buffer)) { 8306 /* hand second half of page back to the ring */ 8307 igb_reuse_rx_page(rx_ring, rx_buffer); 8308 } else { 8309 /* We are not reusing the buffer so unmap it and free 8310 * any references we are holding to it 8311 */ 8312 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8313 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8314 IGB_RX_DMA_ATTR); 8315 __page_frag_cache_drain(rx_buffer->page, 8316 rx_buffer->pagecnt_bias); 8317 } 8318 8319 /* clear contents of rx_buffer */ 8320 rx_buffer->page = NULL; 8321 } 8322 8323 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 8324 { 8325 struct igb_ring *rx_ring = q_vector->rx.ring; 8326 struct sk_buff *skb = rx_ring->skb; 8327 unsigned int total_bytes = 0, total_packets = 0; 8328 u16 cleaned_count = igb_desc_unused(rx_ring); 8329 8330 while (likely(total_packets < budget)) { 8331 union e1000_adv_rx_desc *rx_desc; 8332 struct igb_rx_buffer *rx_buffer; 8333 unsigned int size; 8334 8335 /* return some buffers to hardware, one at a time is too slow */ 8336 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 8337 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8338 cleaned_count = 0; 8339 } 8340 8341 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 8342 size = le16_to_cpu(rx_desc->wb.upper.length); 8343 if (!size) 8344 break; 8345 8346 /* This memory barrier is needed to keep us from reading 8347 * any other fields out of the rx_desc until we know the 8348 * descriptor has been written back 8349 */ 8350 dma_rmb(); 8351 8352 rx_buffer = igb_get_rx_buffer(rx_ring, size); 8353 8354 /* retrieve a buffer from the ring */ 8355 if (skb) 8356 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 8357 else if (ring_uses_build_skb(rx_ring)) 8358 skb = igb_build_skb(rx_ring, rx_buffer, rx_desc, size); 8359 else 8360 skb = igb_construct_skb(rx_ring, rx_buffer, 8361 rx_desc, size); 8362 8363 /* exit if we failed to retrieve a buffer */ 8364 if (!skb) { 8365 rx_ring->rx_stats.alloc_failed++; 8366 rx_buffer->pagecnt_bias++; 8367 break; 8368 } 8369 8370 igb_put_rx_buffer(rx_ring, rx_buffer); 8371 cleaned_count++; 8372 8373 /* fetch next buffer in frame if non-eop */ 8374 if (igb_is_non_eop(rx_ring, rx_desc)) 8375 continue; 8376 8377 /* verify the packet layout is correct */ 8378 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 8379 skb = NULL; 8380 continue; 8381 } 8382 8383 /* probably a little skewed due to removing CRC */ 8384 total_bytes += skb->len; 8385 8386 /* populate checksum, timestamp, VLAN, and protocol */ 8387 igb_process_skb_fields(rx_ring, rx_desc, skb); 8388 8389 napi_gro_receive(&q_vector->napi, skb); 8390 8391 /* reset skb pointer */ 8392 skb = NULL; 8393 8394 /* update budget accounting */ 8395 total_packets++; 8396 } 8397 8398 /* place incomplete frames back on ring for completion */ 8399 rx_ring->skb = skb; 8400 8401 u64_stats_update_begin(&rx_ring->rx_syncp); 8402 rx_ring->rx_stats.packets += total_packets; 8403 rx_ring->rx_stats.bytes += total_bytes; 8404 u64_stats_update_end(&rx_ring->rx_syncp); 8405 q_vector->rx.total_packets += total_packets; 8406 q_vector->rx.total_bytes += total_bytes; 8407 8408 if (cleaned_count) 8409 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8410 8411 return total_packets; 8412 } 8413 8414 static inline unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8415 { 8416 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8417 } 8418 8419 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 8420 struct igb_rx_buffer *bi) 8421 { 8422 struct page *page = bi->page; 8423 dma_addr_t dma; 8424 8425 /* since we are recycling buffers we should seldom need to alloc */ 8426 if (likely(page)) 8427 return true; 8428 8429 /* alloc new page for storage */ 8430 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 8431 if (unlikely(!page)) { 8432 rx_ring->rx_stats.alloc_failed++; 8433 return false; 8434 } 8435 8436 /* map page for use */ 8437 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 8438 igb_rx_pg_size(rx_ring), 8439 DMA_FROM_DEVICE, 8440 IGB_RX_DMA_ATTR); 8441 8442 /* if mapping failed free memory back to system since 8443 * there isn't much point in holding memory we can't use 8444 */ 8445 if (dma_mapping_error(rx_ring->dev, dma)) { 8446 __free_pages(page, igb_rx_pg_order(rx_ring)); 8447 8448 rx_ring->rx_stats.alloc_failed++; 8449 return false; 8450 } 8451 8452 bi->dma = dma; 8453 bi->page = page; 8454 bi->page_offset = igb_rx_offset(rx_ring); 8455 bi->pagecnt_bias = 1; 8456 8457 return true; 8458 } 8459 8460 /** 8461 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 8462 * @adapter: address of board private structure 8463 **/ 8464 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 8465 { 8466 union e1000_adv_rx_desc *rx_desc; 8467 struct igb_rx_buffer *bi; 8468 u16 i = rx_ring->next_to_use; 8469 u16 bufsz; 8470 8471 /* nothing to do */ 8472 if (!cleaned_count) 8473 return; 8474 8475 rx_desc = IGB_RX_DESC(rx_ring, i); 8476 bi = &rx_ring->rx_buffer_info[i]; 8477 i -= rx_ring->count; 8478 8479 bufsz = igb_rx_bufsz(rx_ring); 8480 8481 do { 8482 if (!igb_alloc_mapped_page(rx_ring, bi)) 8483 break; 8484 8485 /* sync the buffer for use by the device */ 8486 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 8487 bi->page_offset, bufsz, 8488 DMA_FROM_DEVICE); 8489 8490 /* Refresh the desc even if buffer_addrs didn't change 8491 * because each write-back erases this info. 8492 */ 8493 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 8494 8495 rx_desc++; 8496 bi++; 8497 i++; 8498 if (unlikely(!i)) { 8499 rx_desc = IGB_RX_DESC(rx_ring, 0); 8500 bi = rx_ring->rx_buffer_info; 8501 i -= rx_ring->count; 8502 } 8503 8504 /* clear the length for the next_to_use descriptor */ 8505 rx_desc->wb.upper.length = 0; 8506 8507 cleaned_count--; 8508 } while (cleaned_count); 8509 8510 i += rx_ring->count; 8511 8512 if (rx_ring->next_to_use != i) { 8513 /* record the next descriptor to use */ 8514 rx_ring->next_to_use = i; 8515 8516 /* update next to alloc since we have filled the ring */ 8517 rx_ring->next_to_alloc = i; 8518 8519 /* Force memory writes to complete before letting h/w 8520 * know there are new descriptors to fetch. (Only 8521 * applicable for weak-ordered memory model archs, 8522 * such as IA-64). 8523 */ 8524 dma_wmb(); 8525 writel(i, rx_ring->tail); 8526 } 8527 } 8528 8529 /** 8530 * igb_mii_ioctl - 8531 * @netdev: 8532 * @ifreq: 8533 * @cmd: 8534 **/ 8535 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 8536 { 8537 struct igb_adapter *adapter = netdev_priv(netdev); 8538 struct mii_ioctl_data *data = if_mii(ifr); 8539 8540 if (adapter->hw.phy.media_type != e1000_media_type_copper) 8541 return -EOPNOTSUPP; 8542 8543 switch (cmd) { 8544 case SIOCGMIIPHY: 8545 data->phy_id = adapter->hw.phy.addr; 8546 break; 8547 case SIOCGMIIREG: 8548 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 8549 &data->val_out)) 8550 return -EIO; 8551 break; 8552 case SIOCSMIIREG: 8553 default: 8554 return -EOPNOTSUPP; 8555 } 8556 return 0; 8557 } 8558 8559 /** 8560 * igb_ioctl - 8561 * @netdev: 8562 * @ifreq: 8563 * @cmd: 8564 **/ 8565 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 8566 { 8567 switch (cmd) { 8568 case SIOCGMIIPHY: 8569 case SIOCGMIIREG: 8570 case SIOCSMIIREG: 8571 return igb_mii_ioctl(netdev, ifr, cmd); 8572 case SIOCGHWTSTAMP: 8573 return igb_ptp_get_ts_config(netdev, ifr); 8574 case SIOCSHWTSTAMP: 8575 return igb_ptp_set_ts_config(netdev, ifr); 8576 default: 8577 return -EOPNOTSUPP; 8578 } 8579 } 8580 8581 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 8582 { 8583 struct igb_adapter *adapter = hw->back; 8584 8585 pci_read_config_word(adapter->pdev, reg, value); 8586 } 8587 8588 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 8589 { 8590 struct igb_adapter *adapter = hw->back; 8591 8592 pci_write_config_word(adapter->pdev, reg, *value); 8593 } 8594 8595 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 8596 { 8597 struct igb_adapter *adapter = hw->back; 8598 8599 if (pcie_capability_read_word(adapter->pdev, reg, value)) 8600 return -E1000_ERR_CONFIG; 8601 8602 return 0; 8603 } 8604 8605 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 8606 { 8607 struct igb_adapter *adapter = hw->back; 8608 8609 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 8610 return -E1000_ERR_CONFIG; 8611 8612 return 0; 8613 } 8614 8615 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 8616 { 8617 struct igb_adapter *adapter = netdev_priv(netdev); 8618 struct e1000_hw *hw = &adapter->hw; 8619 u32 ctrl, rctl; 8620 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 8621 8622 if (enable) { 8623 /* enable VLAN tag insert/strip */ 8624 ctrl = rd32(E1000_CTRL); 8625 ctrl |= E1000_CTRL_VME; 8626 wr32(E1000_CTRL, ctrl); 8627 8628 /* Disable CFI check */ 8629 rctl = rd32(E1000_RCTL); 8630 rctl &= ~E1000_RCTL_CFIEN; 8631 wr32(E1000_RCTL, rctl); 8632 } else { 8633 /* disable VLAN tag insert/strip */ 8634 ctrl = rd32(E1000_CTRL); 8635 ctrl &= ~E1000_CTRL_VME; 8636 wr32(E1000_CTRL, ctrl); 8637 } 8638 8639 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 8640 } 8641 8642 static int igb_vlan_rx_add_vid(struct net_device *netdev, 8643 __be16 proto, u16 vid) 8644 { 8645 struct igb_adapter *adapter = netdev_priv(netdev); 8646 struct e1000_hw *hw = &adapter->hw; 8647 int pf_id = adapter->vfs_allocated_count; 8648 8649 /* add the filter since PF can receive vlans w/o entry in vlvf */ 8650 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 8651 igb_vfta_set(hw, vid, pf_id, true, !!vid); 8652 8653 set_bit(vid, adapter->active_vlans); 8654 8655 return 0; 8656 } 8657 8658 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 8659 __be16 proto, u16 vid) 8660 { 8661 struct igb_adapter *adapter = netdev_priv(netdev); 8662 int pf_id = adapter->vfs_allocated_count; 8663 struct e1000_hw *hw = &adapter->hw; 8664 8665 /* remove VID from filter table */ 8666 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 8667 igb_vfta_set(hw, vid, pf_id, false, true); 8668 8669 clear_bit(vid, adapter->active_vlans); 8670 8671 return 0; 8672 } 8673 8674 static void igb_restore_vlan(struct igb_adapter *adapter) 8675 { 8676 u16 vid = 1; 8677 8678 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 8679 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 8680 8681 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 8682 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 8683 } 8684 8685 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 8686 { 8687 struct pci_dev *pdev = adapter->pdev; 8688 struct e1000_mac_info *mac = &adapter->hw.mac; 8689 8690 mac->autoneg = 0; 8691 8692 /* Make sure dplx is at most 1 bit and lsb of speed is not set 8693 * for the switch() below to work 8694 */ 8695 if ((spd & 1) || (dplx & ~1)) 8696 goto err_inval; 8697 8698 /* Fiber NIC's only allow 1000 gbps Full duplex 8699 * and 100Mbps Full duplex for 100baseFx sfp 8700 */ 8701 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 8702 switch (spd + dplx) { 8703 case SPEED_10 + DUPLEX_HALF: 8704 case SPEED_10 + DUPLEX_FULL: 8705 case SPEED_100 + DUPLEX_HALF: 8706 goto err_inval; 8707 default: 8708 break; 8709 } 8710 } 8711 8712 switch (spd + dplx) { 8713 case SPEED_10 + DUPLEX_HALF: 8714 mac->forced_speed_duplex = ADVERTISE_10_HALF; 8715 break; 8716 case SPEED_10 + DUPLEX_FULL: 8717 mac->forced_speed_duplex = ADVERTISE_10_FULL; 8718 break; 8719 case SPEED_100 + DUPLEX_HALF: 8720 mac->forced_speed_duplex = ADVERTISE_100_HALF; 8721 break; 8722 case SPEED_100 + DUPLEX_FULL: 8723 mac->forced_speed_duplex = ADVERTISE_100_FULL; 8724 break; 8725 case SPEED_1000 + DUPLEX_FULL: 8726 mac->autoneg = 1; 8727 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 8728 break; 8729 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 8730 default: 8731 goto err_inval; 8732 } 8733 8734 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 8735 adapter->hw.phy.mdix = AUTO_ALL_MODES; 8736 8737 return 0; 8738 8739 err_inval: 8740 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 8741 return -EINVAL; 8742 } 8743 8744 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 8745 bool runtime) 8746 { 8747 struct net_device *netdev = pci_get_drvdata(pdev); 8748 struct igb_adapter *adapter = netdev_priv(netdev); 8749 struct e1000_hw *hw = &adapter->hw; 8750 u32 ctrl, rctl, status; 8751 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 8752 bool wake; 8753 8754 rtnl_lock(); 8755 netif_device_detach(netdev); 8756 8757 if (netif_running(netdev)) 8758 __igb_close(netdev, true); 8759 8760 igb_ptp_suspend(adapter); 8761 8762 igb_clear_interrupt_scheme(adapter); 8763 rtnl_unlock(); 8764 8765 status = rd32(E1000_STATUS); 8766 if (status & E1000_STATUS_LU) 8767 wufc &= ~E1000_WUFC_LNKC; 8768 8769 if (wufc) { 8770 igb_setup_rctl(adapter); 8771 igb_set_rx_mode(netdev); 8772 8773 /* turn on all-multi mode if wake on multicast is enabled */ 8774 if (wufc & E1000_WUFC_MC) { 8775 rctl = rd32(E1000_RCTL); 8776 rctl |= E1000_RCTL_MPE; 8777 wr32(E1000_RCTL, rctl); 8778 } 8779 8780 ctrl = rd32(E1000_CTRL); 8781 ctrl |= E1000_CTRL_ADVD3WUC; 8782 wr32(E1000_CTRL, ctrl); 8783 8784 /* Allow time for pending master requests to run */ 8785 igb_disable_pcie_master(hw); 8786 8787 wr32(E1000_WUC, E1000_WUC_PME_EN); 8788 wr32(E1000_WUFC, wufc); 8789 } else { 8790 wr32(E1000_WUC, 0); 8791 wr32(E1000_WUFC, 0); 8792 } 8793 8794 wake = wufc || adapter->en_mng_pt; 8795 if (!wake) 8796 igb_power_down_link(adapter); 8797 else 8798 igb_power_up_link(adapter); 8799 8800 if (enable_wake) 8801 *enable_wake = wake; 8802 8803 /* Release control of h/w to f/w. If f/w is AMT enabled, this 8804 * would have already happened in close and is redundant. 8805 */ 8806 igb_release_hw_control(adapter); 8807 8808 pci_disable_device(pdev); 8809 8810 return 0; 8811 } 8812 8813 static void igb_deliver_wake_packet(struct net_device *netdev) 8814 { 8815 struct igb_adapter *adapter = netdev_priv(netdev); 8816 struct e1000_hw *hw = &adapter->hw; 8817 struct sk_buff *skb; 8818 u32 wupl; 8819 8820 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 8821 8822 /* WUPM stores only the first 128 bytes of the wake packet. 8823 * Read the packet only if we have the whole thing. 8824 */ 8825 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 8826 return; 8827 8828 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 8829 if (!skb) 8830 return; 8831 8832 skb_put(skb, wupl); 8833 8834 /* Ensure reads are 32-bit aligned */ 8835 wupl = roundup(wupl, 4); 8836 8837 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 8838 8839 skb->protocol = eth_type_trans(skb, netdev); 8840 netif_rx(skb); 8841 } 8842 8843 static int __maybe_unused igb_suspend(struct device *dev) 8844 { 8845 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 8846 } 8847 8848 static int __maybe_unused igb_resume(struct device *dev) 8849 { 8850 struct pci_dev *pdev = to_pci_dev(dev); 8851 struct net_device *netdev = pci_get_drvdata(pdev); 8852 struct igb_adapter *adapter = netdev_priv(netdev); 8853 struct e1000_hw *hw = &adapter->hw; 8854 u32 err, val; 8855 8856 pci_set_power_state(pdev, PCI_D0); 8857 pci_restore_state(pdev); 8858 pci_save_state(pdev); 8859 8860 if (!pci_device_is_present(pdev)) 8861 return -ENODEV; 8862 err = pci_enable_device_mem(pdev); 8863 if (err) { 8864 dev_err(&pdev->dev, 8865 "igb: Cannot enable PCI device from suspend\n"); 8866 return err; 8867 } 8868 pci_set_master(pdev); 8869 8870 pci_enable_wake(pdev, PCI_D3hot, 0); 8871 pci_enable_wake(pdev, PCI_D3cold, 0); 8872 8873 if (igb_init_interrupt_scheme(adapter, true)) { 8874 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8875 return -ENOMEM; 8876 } 8877 8878 igb_reset(adapter); 8879 8880 /* let the f/w know that the h/w is now under the control of the 8881 * driver. 8882 */ 8883 igb_get_hw_control(adapter); 8884 8885 val = rd32(E1000_WUS); 8886 if (val & WAKE_PKT_WUS) 8887 igb_deliver_wake_packet(netdev); 8888 8889 wr32(E1000_WUS, ~0); 8890 8891 rtnl_lock(); 8892 if (!err && netif_running(netdev)) 8893 err = __igb_open(netdev, true); 8894 8895 if (!err) 8896 netif_device_attach(netdev); 8897 rtnl_unlock(); 8898 8899 return err; 8900 } 8901 8902 static int __maybe_unused igb_runtime_idle(struct device *dev) 8903 { 8904 struct net_device *netdev = dev_get_drvdata(dev); 8905 struct igb_adapter *adapter = netdev_priv(netdev); 8906 8907 if (!igb_has_link(adapter)) 8908 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 8909 8910 return -EBUSY; 8911 } 8912 8913 static int __maybe_unused igb_runtime_suspend(struct device *dev) 8914 { 8915 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 8916 } 8917 8918 static int __maybe_unused igb_runtime_resume(struct device *dev) 8919 { 8920 return igb_resume(dev); 8921 } 8922 8923 static void igb_shutdown(struct pci_dev *pdev) 8924 { 8925 bool wake; 8926 8927 __igb_shutdown(pdev, &wake, 0); 8928 8929 if (system_state == SYSTEM_POWER_OFF) { 8930 pci_wake_from_d3(pdev, wake); 8931 pci_set_power_state(pdev, PCI_D3hot); 8932 } 8933 } 8934 8935 #ifdef CONFIG_PCI_IOV 8936 static int igb_sriov_reinit(struct pci_dev *dev) 8937 { 8938 struct net_device *netdev = pci_get_drvdata(dev); 8939 struct igb_adapter *adapter = netdev_priv(netdev); 8940 struct pci_dev *pdev = adapter->pdev; 8941 8942 rtnl_lock(); 8943 8944 if (netif_running(netdev)) 8945 igb_close(netdev); 8946 else 8947 igb_reset(adapter); 8948 8949 igb_clear_interrupt_scheme(adapter); 8950 8951 igb_init_queue_configuration(adapter); 8952 8953 if (igb_init_interrupt_scheme(adapter, true)) { 8954 rtnl_unlock(); 8955 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8956 return -ENOMEM; 8957 } 8958 8959 if (netif_running(netdev)) 8960 igb_open(netdev); 8961 8962 rtnl_unlock(); 8963 8964 return 0; 8965 } 8966 8967 static int igb_pci_disable_sriov(struct pci_dev *dev) 8968 { 8969 int err = igb_disable_sriov(dev); 8970 8971 if (!err) 8972 err = igb_sriov_reinit(dev); 8973 8974 return err; 8975 } 8976 8977 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 8978 { 8979 int err = igb_enable_sriov(dev, num_vfs); 8980 8981 if (err) 8982 goto out; 8983 8984 err = igb_sriov_reinit(dev); 8985 if (!err) 8986 return num_vfs; 8987 8988 out: 8989 return err; 8990 } 8991 8992 #endif 8993 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 8994 { 8995 #ifdef CONFIG_PCI_IOV 8996 if (num_vfs == 0) 8997 return igb_pci_disable_sriov(dev); 8998 else 8999 return igb_pci_enable_sriov(dev, num_vfs); 9000 #endif 9001 return 0; 9002 } 9003 9004 /** 9005 * igb_io_error_detected - called when PCI error is detected 9006 * @pdev: Pointer to PCI device 9007 * @state: The current pci connection state 9008 * 9009 * This function is called after a PCI bus error affecting 9010 * this device has been detected. 9011 **/ 9012 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9013 pci_channel_state_t state) 9014 { 9015 struct net_device *netdev = pci_get_drvdata(pdev); 9016 struct igb_adapter *adapter = netdev_priv(netdev); 9017 9018 netif_device_detach(netdev); 9019 9020 if (state == pci_channel_io_perm_failure) 9021 return PCI_ERS_RESULT_DISCONNECT; 9022 9023 if (netif_running(netdev)) 9024 igb_down(adapter); 9025 pci_disable_device(pdev); 9026 9027 /* Request a slot slot reset. */ 9028 return PCI_ERS_RESULT_NEED_RESET; 9029 } 9030 9031 /** 9032 * igb_io_slot_reset - called after the pci bus has been reset. 9033 * @pdev: Pointer to PCI device 9034 * 9035 * Restart the card from scratch, as if from a cold-boot. Implementation 9036 * resembles the first-half of the igb_resume routine. 9037 **/ 9038 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9039 { 9040 struct net_device *netdev = pci_get_drvdata(pdev); 9041 struct igb_adapter *adapter = netdev_priv(netdev); 9042 struct e1000_hw *hw = &adapter->hw; 9043 pci_ers_result_t result; 9044 9045 if (pci_enable_device_mem(pdev)) { 9046 dev_err(&pdev->dev, 9047 "Cannot re-enable PCI device after reset.\n"); 9048 result = PCI_ERS_RESULT_DISCONNECT; 9049 } else { 9050 pci_set_master(pdev); 9051 pci_restore_state(pdev); 9052 pci_save_state(pdev); 9053 9054 pci_enable_wake(pdev, PCI_D3hot, 0); 9055 pci_enable_wake(pdev, PCI_D3cold, 0); 9056 9057 /* In case of PCI error, adapter lose its HW address 9058 * so we should re-assign it here. 9059 */ 9060 hw->hw_addr = adapter->io_addr; 9061 9062 igb_reset(adapter); 9063 wr32(E1000_WUS, ~0); 9064 result = PCI_ERS_RESULT_RECOVERED; 9065 } 9066 9067 return result; 9068 } 9069 9070 /** 9071 * igb_io_resume - called when traffic can start flowing again. 9072 * @pdev: Pointer to PCI device 9073 * 9074 * This callback is called when the error recovery driver tells us that 9075 * its OK to resume normal operation. Implementation resembles the 9076 * second-half of the igb_resume routine. 9077 */ 9078 static void igb_io_resume(struct pci_dev *pdev) 9079 { 9080 struct net_device *netdev = pci_get_drvdata(pdev); 9081 struct igb_adapter *adapter = netdev_priv(netdev); 9082 9083 if (netif_running(netdev)) { 9084 if (igb_up(adapter)) { 9085 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9086 return; 9087 } 9088 } 9089 9090 netif_device_attach(netdev); 9091 9092 /* let the f/w know that the h/w is now under the control of the 9093 * driver. 9094 */ 9095 igb_get_hw_control(adapter); 9096 } 9097 9098 /** 9099 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9100 * @adapter: Pointer to adapter structure 9101 * @index: Index of the RAR entry which need to be synced with MAC table 9102 **/ 9103 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9104 { 9105 struct e1000_hw *hw = &adapter->hw; 9106 u32 rar_low, rar_high; 9107 u8 *addr = adapter->mac_table[index].addr; 9108 9109 /* HW expects these to be in network order when they are plugged 9110 * into the registers which are little endian. In order to guarantee 9111 * that ordering we need to do an leXX_to_cpup here in order to be 9112 * ready for the byteswap that occurs with writel 9113 */ 9114 rar_low = le32_to_cpup((__le32 *)(addr)); 9115 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9116 9117 /* Indicate to hardware the Address is Valid. */ 9118 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9119 if (is_valid_ether_addr(addr)) 9120 rar_high |= E1000_RAH_AV; 9121 9122 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9123 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9124 9125 switch (hw->mac.type) { 9126 case e1000_82575: 9127 case e1000_i210: 9128 if (adapter->mac_table[index].state & 9129 IGB_MAC_STATE_QUEUE_STEERING) 9130 rar_high |= E1000_RAH_QSEL_ENABLE; 9131 9132 rar_high |= E1000_RAH_POOL_1 * 9133 adapter->mac_table[index].queue; 9134 break; 9135 default: 9136 rar_high |= E1000_RAH_POOL_1 << 9137 adapter->mac_table[index].queue; 9138 break; 9139 } 9140 } 9141 9142 wr32(E1000_RAL(index), rar_low); 9143 wrfl(); 9144 wr32(E1000_RAH(index), rar_high); 9145 wrfl(); 9146 } 9147 9148 static int igb_set_vf_mac(struct igb_adapter *adapter, 9149 int vf, unsigned char *mac_addr) 9150 { 9151 struct e1000_hw *hw = &adapter->hw; 9152 /* VF MAC addresses start at end of receive addresses and moves 9153 * towards the first, as a result a collision should not be possible 9154 */ 9155 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9156 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9157 9158 ether_addr_copy(vf_mac_addr, mac_addr); 9159 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9160 adapter->mac_table[rar_entry].queue = vf; 9161 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9162 igb_rar_set_index(adapter, rar_entry); 9163 9164 return 0; 9165 } 9166 9167 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9168 { 9169 struct igb_adapter *adapter = netdev_priv(netdev); 9170 9171 if (vf >= adapter->vfs_allocated_count) 9172 return -EINVAL; 9173 9174 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9175 * flag and allows to overwrite the MAC via VF netdev. This 9176 * is necessary to allow libvirt a way to restore the original 9177 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9178 * down a VM. 9179 */ 9180 if (is_zero_ether_addr(mac)) { 9181 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9182 dev_info(&adapter->pdev->dev, 9183 "remove administratively set MAC on VF %d\n", 9184 vf); 9185 } else if (is_valid_ether_addr(mac)) { 9186 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9187 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9188 mac, vf); 9189 dev_info(&adapter->pdev->dev, 9190 "Reload the VF driver to make this change effective."); 9191 /* Generate additional warning if PF is down */ 9192 if (test_bit(__IGB_DOWN, &adapter->state)) { 9193 dev_warn(&adapter->pdev->dev, 9194 "The VF MAC address has been set, but the PF device is not up.\n"); 9195 dev_warn(&adapter->pdev->dev, 9196 "Bring the PF device up before attempting to use the VF device.\n"); 9197 } 9198 } else { 9199 return -EINVAL; 9200 } 9201 return igb_set_vf_mac(adapter, vf, mac); 9202 } 9203 9204 static int igb_link_mbps(int internal_link_speed) 9205 { 9206 switch (internal_link_speed) { 9207 case SPEED_100: 9208 return 100; 9209 case SPEED_1000: 9210 return 1000; 9211 default: 9212 return 0; 9213 } 9214 } 9215 9216 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9217 int link_speed) 9218 { 9219 int rf_dec, rf_int; 9220 u32 bcnrc_val; 9221 9222 if (tx_rate != 0) { 9223 /* Calculate the rate factor values to set */ 9224 rf_int = link_speed / tx_rate; 9225 rf_dec = (link_speed - (rf_int * tx_rate)); 9226 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9227 tx_rate; 9228 9229 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9230 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 9231 E1000_RTTBCNRC_RF_INT_MASK); 9232 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9233 } else { 9234 bcnrc_val = 0; 9235 } 9236 9237 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9238 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9239 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9240 */ 9241 wr32(E1000_RTTBCNRM, 0x14); 9242 wr32(E1000_RTTBCNRC, bcnrc_val); 9243 } 9244 9245 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9246 { 9247 int actual_link_speed, i; 9248 bool reset_rate = false; 9249 9250 /* VF TX rate limit was not set or not supported */ 9251 if ((adapter->vf_rate_link_speed == 0) || 9252 (adapter->hw.mac.type != e1000_82576)) 9253 return; 9254 9255 actual_link_speed = igb_link_mbps(adapter->link_speed); 9256 if (actual_link_speed != adapter->vf_rate_link_speed) { 9257 reset_rate = true; 9258 adapter->vf_rate_link_speed = 0; 9259 dev_info(&adapter->pdev->dev, 9260 "Link speed has been changed. VF Transmit rate is disabled\n"); 9261 } 9262 9263 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9264 if (reset_rate) 9265 adapter->vf_data[i].tx_rate = 0; 9266 9267 igb_set_vf_rate_limit(&adapter->hw, i, 9268 adapter->vf_data[i].tx_rate, 9269 actual_link_speed); 9270 } 9271 } 9272 9273 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9274 int min_tx_rate, int max_tx_rate) 9275 { 9276 struct igb_adapter *adapter = netdev_priv(netdev); 9277 struct e1000_hw *hw = &adapter->hw; 9278 int actual_link_speed; 9279 9280 if (hw->mac.type != e1000_82576) 9281 return -EOPNOTSUPP; 9282 9283 if (min_tx_rate) 9284 return -EINVAL; 9285 9286 actual_link_speed = igb_link_mbps(adapter->link_speed); 9287 if ((vf >= adapter->vfs_allocated_count) || 9288 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9289 (max_tx_rate < 0) || 9290 (max_tx_rate > actual_link_speed)) 9291 return -EINVAL; 9292 9293 adapter->vf_rate_link_speed = actual_link_speed; 9294 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 9295 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 9296 9297 return 0; 9298 } 9299 9300 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 9301 bool setting) 9302 { 9303 struct igb_adapter *adapter = netdev_priv(netdev); 9304 struct e1000_hw *hw = &adapter->hw; 9305 u32 reg_val, reg_offset; 9306 9307 if (!adapter->vfs_allocated_count) 9308 return -EOPNOTSUPP; 9309 9310 if (vf >= adapter->vfs_allocated_count) 9311 return -EINVAL; 9312 9313 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 9314 reg_val = rd32(reg_offset); 9315 if (setting) 9316 reg_val |= (BIT(vf) | 9317 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9318 else 9319 reg_val &= ~(BIT(vf) | 9320 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9321 wr32(reg_offset, reg_val); 9322 9323 adapter->vf_data[vf].spoofchk_enabled = setting; 9324 return 0; 9325 } 9326 9327 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 9328 { 9329 struct igb_adapter *adapter = netdev_priv(netdev); 9330 9331 if (vf >= adapter->vfs_allocated_count) 9332 return -EINVAL; 9333 if (adapter->vf_data[vf].trusted == setting) 9334 return 0; 9335 9336 adapter->vf_data[vf].trusted = setting; 9337 9338 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 9339 vf, setting ? "" : "not "); 9340 return 0; 9341 } 9342 9343 static int igb_ndo_get_vf_config(struct net_device *netdev, 9344 int vf, struct ifla_vf_info *ivi) 9345 { 9346 struct igb_adapter *adapter = netdev_priv(netdev); 9347 if (vf >= adapter->vfs_allocated_count) 9348 return -EINVAL; 9349 ivi->vf = vf; 9350 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 9351 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 9352 ivi->min_tx_rate = 0; 9353 ivi->vlan = adapter->vf_data[vf].pf_vlan; 9354 ivi->qos = adapter->vf_data[vf].pf_qos; 9355 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 9356 ivi->trusted = adapter->vf_data[vf].trusted; 9357 return 0; 9358 } 9359 9360 static void igb_vmm_control(struct igb_adapter *adapter) 9361 { 9362 struct e1000_hw *hw = &adapter->hw; 9363 u32 reg; 9364 9365 switch (hw->mac.type) { 9366 case e1000_82575: 9367 case e1000_i210: 9368 case e1000_i211: 9369 case e1000_i354: 9370 default: 9371 /* replication is not supported for 82575 */ 9372 return; 9373 case e1000_82576: 9374 /* notify HW that the MAC is adding vlan tags */ 9375 reg = rd32(E1000_DTXCTL); 9376 reg |= E1000_DTXCTL_VLAN_ADDED; 9377 wr32(E1000_DTXCTL, reg); 9378 fallthrough; 9379 case e1000_82580: 9380 /* enable replication vlan tag stripping */ 9381 reg = rd32(E1000_RPLOLR); 9382 reg |= E1000_RPLOLR_STRVLAN; 9383 wr32(E1000_RPLOLR, reg); 9384 fallthrough; 9385 case e1000_i350: 9386 /* none of the above registers are supported by i350 */ 9387 break; 9388 } 9389 9390 if (adapter->vfs_allocated_count) { 9391 igb_vmdq_set_loopback_pf(hw, true); 9392 igb_vmdq_set_replication_pf(hw, true); 9393 igb_vmdq_set_anti_spoofing_pf(hw, true, 9394 adapter->vfs_allocated_count); 9395 } else { 9396 igb_vmdq_set_loopback_pf(hw, false); 9397 igb_vmdq_set_replication_pf(hw, false); 9398 } 9399 } 9400 9401 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 9402 { 9403 struct e1000_hw *hw = &adapter->hw; 9404 u32 dmac_thr; 9405 u16 hwm; 9406 9407 if (hw->mac.type > e1000_82580) { 9408 if (adapter->flags & IGB_FLAG_DMAC) { 9409 u32 reg; 9410 9411 /* force threshold to 0. */ 9412 wr32(E1000_DMCTXTH, 0); 9413 9414 /* DMA Coalescing high water mark needs to be greater 9415 * than the Rx threshold. Set hwm to PBA - max frame 9416 * size in 16B units, capping it at PBA - 6KB. 9417 */ 9418 hwm = 64 * (pba - 6); 9419 reg = rd32(E1000_FCRTC); 9420 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 9421 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 9422 & E1000_FCRTC_RTH_COAL_MASK); 9423 wr32(E1000_FCRTC, reg); 9424 9425 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 9426 * frame size, capping it at PBA - 10KB. 9427 */ 9428 dmac_thr = pba - 10; 9429 reg = rd32(E1000_DMACR); 9430 reg &= ~E1000_DMACR_DMACTHR_MASK; 9431 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 9432 & E1000_DMACR_DMACTHR_MASK); 9433 9434 /* transition to L0x or L1 if available..*/ 9435 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 9436 9437 /* watchdog timer= +-1000 usec in 32usec intervals */ 9438 reg |= (1000 >> 5); 9439 9440 /* Disable BMC-to-OS Watchdog Enable */ 9441 if (hw->mac.type != e1000_i354) 9442 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 9443 9444 wr32(E1000_DMACR, reg); 9445 9446 /* no lower threshold to disable 9447 * coalescing(smart fifb)-UTRESH=0 9448 */ 9449 wr32(E1000_DMCRTRH, 0); 9450 9451 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 9452 9453 wr32(E1000_DMCTLX, reg); 9454 9455 /* free space in tx packet buffer to wake from 9456 * DMA coal 9457 */ 9458 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 9459 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 9460 9461 /* make low power state decision controlled 9462 * by DMA coal 9463 */ 9464 reg = rd32(E1000_PCIEMISC); 9465 reg &= ~E1000_PCIEMISC_LX_DECISION; 9466 wr32(E1000_PCIEMISC, reg); 9467 } /* endif adapter->dmac is not disabled */ 9468 } else if (hw->mac.type == e1000_82580) { 9469 u32 reg = rd32(E1000_PCIEMISC); 9470 9471 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 9472 wr32(E1000_DMACR, 0); 9473 } 9474 } 9475 9476 /** 9477 * igb_read_i2c_byte - Reads 8 bit word over I2C 9478 * @hw: pointer to hardware structure 9479 * @byte_offset: byte offset to read 9480 * @dev_addr: device address 9481 * @data: value read 9482 * 9483 * Performs byte read operation over I2C interface at 9484 * a specified device address. 9485 **/ 9486 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 9487 u8 dev_addr, u8 *data) 9488 { 9489 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 9490 struct i2c_client *this_client = adapter->i2c_client; 9491 s32 status; 9492 u16 swfw_mask = 0; 9493 9494 if (!this_client) 9495 return E1000_ERR_I2C; 9496 9497 swfw_mask = E1000_SWFW_PHY0_SM; 9498 9499 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 9500 return E1000_ERR_SWFW_SYNC; 9501 9502 status = i2c_smbus_read_byte_data(this_client, byte_offset); 9503 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 9504 9505 if (status < 0) 9506 return E1000_ERR_I2C; 9507 else { 9508 *data = status; 9509 return 0; 9510 } 9511 } 9512 9513 /** 9514 * igb_write_i2c_byte - Writes 8 bit word over I2C 9515 * @hw: pointer to hardware structure 9516 * @byte_offset: byte offset to write 9517 * @dev_addr: device address 9518 * @data: value to write 9519 * 9520 * Performs byte write operation over I2C interface at 9521 * a specified device address. 9522 **/ 9523 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 9524 u8 dev_addr, u8 data) 9525 { 9526 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 9527 struct i2c_client *this_client = adapter->i2c_client; 9528 s32 status; 9529 u16 swfw_mask = E1000_SWFW_PHY0_SM; 9530 9531 if (!this_client) 9532 return E1000_ERR_I2C; 9533 9534 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 9535 return E1000_ERR_SWFW_SYNC; 9536 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 9537 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 9538 9539 if (status) 9540 return E1000_ERR_I2C; 9541 else 9542 return 0; 9543 9544 } 9545 9546 int igb_reinit_queues(struct igb_adapter *adapter) 9547 { 9548 struct net_device *netdev = adapter->netdev; 9549 struct pci_dev *pdev = adapter->pdev; 9550 int err = 0; 9551 9552 if (netif_running(netdev)) 9553 igb_close(netdev); 9554 9555 igb_reset_interrupt_capability(adapter); 9556 9557 if (igb_init_interrupt_scheme(adapter, true)) { 9558 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9559 return -ENOMEM; 9560 } 9561 9562 if (netif_running(netdev)) 9563 err = igb_open(netdev); 9564 9565 return err; 9566 } 9567 9568 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 9569 { 9570 struct igb_nfc_filter *rule; 9571 9572 spin_lock(&adapter->nfc_lock); 9573 9574 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 9575 igb_erase_filter(adapter, rule); 9576 9577 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 9578 igb_erase_filter(adapter, rule); 9579 9580 spin_unlock(&adapter->nfc_lock); 9581 } 9582 9583 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 9584 { 9585 struct igb_nfc_filter *rule; 9586 9587 spin_lock(&adapter->nfc_lock); 9588 9589 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 9590 igb_add_filter(adapter, rule); 9591 9592 spin_unlock(&adapter->nfc_lock); 9593 } 9594 /* igb_main.c */ 9595