1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/sctp.h> 30 #include <linux/if_ether.h> 31 #include <linux/prefetch.h> 32 #include <linux/bpf.h> 33 #include <linux/bpf_trace.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/etherdevice.h> 36 #ifdef CONFIG_IGB_DCA 37 #include <linux/dca.h> 38 #endif 39 #include <linux/i2c.h> 40 #include "igb.h" 41 42 enum queue_mode { 43 QUEUE_MODE_STRICT_PRIORITY, 44 QUEUE_MODE_STREAM_RESERVATION, 45 }; 46 47 enum tx_queue_prio { 48 TX_QUEUE_PRIO_HIGH, 49 TX_QUEUE_PRIO_LOW, 50 }; 51 52 char igb_driver_name[] = "igb"; 53 static const char igb_driver_string[] = 54 "Intel(R) Gigabit Ethernet Network Driver"; 55 static const char igb_copyright[] = 56 "Copyright (c) 2007-2014 Intel Corporation."; 57 58 static const struct e1000_info *igb_info_tbl[] = { 59 [board_82575] = &e1000_82575_info, 60 }; 61 62 static const struct pci_device_id igb_pci_tbl[] = { 63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 98 /* required last entry */ 99 {0, } 100 }; 101 102 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 103 104 static int igb_setup_all_tx_resources(struct igb_adapter *); 105 static int igb_setup_all_rx_resources(struct igb_adapter *); 106 static void igb_free_all_tx_resources(struct igb_adapter *); 107 static void igb_free_all_rx_resources(struct igb_adapter *); 108 static void igb_setup_mrqc(struct igb_adapter *); 109 static void igb_init_queue_configuration(struct igb_adapter *adapter); 110 static int igb_sw_init(struct igb_adapter *); 111 int igb_open(struct net_device *); 112 int igb_close(struct net_device *); 113 static void igb_configure(struct igb_adapter *); 114 static void igb_configure_tx(struct igb_adapter *); 115 static void igb_configure_rx(struct igb_adapter *); 116 static void igb_clean_all_tx_rings(struct igb_adapter *); 117 static void igb_clean_all_rx_rings(struct igb_adapter *); 118 static void igb_set_rx_mode(struct net_device *); 119 static void igb_update_phy_info(struct timer_list *); 120 static void igb_watchdog(struct timer_list *); 121 static void igb_watchdog_task(struct work_struct *); 122 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 123 static void igb_get_stats64(struct net_device *dev, 124 struct rtnl_link_stats64 *stats); 125 static int igb_change_mtu(struct net_device *, int); 126 static int igb_set_mac(struct net_device *, void *); 127 static void igb_set_uta(struct igb_adapter *adapter, bool set); 128 static irqreturn_t igb_intr(int irq, void *); 129 static irqreturn_t igb_intr_msi(int irq, void *); 130 static irqreturn_t igb_msix_other(int irq, void *); 131 static irqreturn_t igb_msix_ring(int irq, void *); 132 #ifdef CONFIG_IGB_DCA 133 static void igb_update_dca(struct igb_q_vector *); 134 static void igb_setup_dca(struct igb_adapter *); 135 #endif /* CONFIG_IGB_DCA */ 136 static int igb_poll(struct napi_struct *, int); 137 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 138 static int igb_clean_rx_irq(struct igb_q_vector *, int); 139 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 140 static void igb_tx_timeout(struct net_device *, unsigned int txqueue); 141 static void igb_reset_task(struct work_struct *); 142 static void igb_vlan_mode(struct net_device *netdev, 143 netdev_features_t features); 144 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 145 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 146 static void igb_restore_vlan(struct igb_adapter *); 147 static void igb_rar_set_index(struct igb_adapter *, u32); 148 static void igb_ping_all_vfs(struct igb_adapter *); 149 static void igb_msg_task(struct igb_adapter *); 150 static void igb_vmm_control(struct igb_adapter *); 151 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 152 static void igb_flush_mac_table(struct igb_adapter *); 153 static int igb_available_rars(struct igb_adapter *, u8); 154 static void igb_set_default_mac_filter(struct igb_adapter *); 155 static int igb_uc_sync(struct net_device *, const unsigned char *); 156 static int igb_uc_unsync(struct net_device *, const unsigned char *); 157 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 158 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 159 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 160 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 161 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 162 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 163 bool setting); 164 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 165 bool setting); 166 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 167 struct ifla_vf_info *ivi); 168 static void igb_check_vf_rate_limit(struct igb_adapter *); 169 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 170 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 171 172 #ifdef CONFIG_PCI_IOV 173 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 174 static int igb_disable_sriov(struct pci_dev *dev, bool reinit); 175 #endif 176 177 #ifdef CONFIG_IGB_DCA 178 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 179 static struct notifier_block dca_notifier = { 180 .notifier_call = igb_notify_dca, 181 .next = NULL, 182 .priority = 0 183 }; 184 #endif 185 #ifdef CONFIG_PCI_IOV 186 static unsigned int max_vfs; 187 module_param(max_vfs, uint, 0444); 188 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 189 #endif /* CONFIG_PCI_IOV */ 190 191 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 192 pci_channel_state_t); 193 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 194 static void igb_io_resume(struct pci_dev *); 195 196 static const struct pci_error_handlers igb_err_handler = { 197 .error_detected = igb_io_error_detected, 198 .slot_reset = igb_io_slot_reset, 199 .resume = igb_io_resume, 200 }; 201 202 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 203 204 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 205 MODULE_LICENSE("GPL v2"); 206 207 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 208 static int debug = -1; 209 module_param(debug, int, 0); 210 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 211 212 struct igb_reg_info { 213 u32 ofs; 214 char *name; 215 }; 216 217 static const struct igb_reg_info igb_reg_info_tbl[] = { 218 219 /* General Registers */ 220 {E1000_CTRL, "CTRL"}, 221 {E1000_STATUS, "STATUS"}, 222 {E1000_CTRL_EXT, "CTRL_EXT"}, 223 224 /* Interrupt Registers */ 225 {E1000_ICR, "ICR"}, 226 227 /* RX Registers */ 228 {E1000_RCTL, "RCTL"}, 229 {E1000_RDLEN(0), "RDLEN"}, 230 {E1000_RDH(0), "RDH"}, 231 {E1000_RDT(0), "RDT"}, 232 {E1000_RXDCTL(0), "RXDCTL"}, 233 {E1000_RDBAL(0), "RDBAL"}, 234 {E1000_RDBAH(0), "RDBAH"}, 235 236 /* TX Registers */ 237 {E1000_TCTL, "TCTL"}, 238 {E1000_TDBAL(0), "TDBAL"}, 239 {E1000_TDBAH(0), "TDBAH"}, 240 {E1000_TDLEN(0), "TDLEN"}, 241 {E1000_TDH(0), "TDH"}, 242 {E1000_TDT(0), "TDT"}, 243 {E1000_TXDCTL(0), "TXDCTL"}, 244 {E1000_TDFH, "TDFH"}, 245 {E1000_TDFT, "TDFT"}, 246 {E1000_TDFHS, "TDFHS"}, 247 {E1000_TDFPC, "TDFPC"}, 248 249 /* List Terminator */ 250 {} 251 }; 252 253 /* igb_regdump - register printout routine */ 254 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 255 { 256 int n = 0; 257 char rname[16]; 258 u32 regs[8]; 259 260 switch (reginfo->ofs) { 261 case E1000_RDLEN(0): 262 for (n = 0; n < 4; n++) 263 regs[n] = rd32(E1000_RDLEN(n)); 264 break; 265 case E1000_RDH(0): 266 for (n = 0; n < 4; n++) 267 regs[n] = rd32(E1000_RDH(n)); 268 break; 269 case E1000_RDT(0): 270 for (n = 0; n < 4; n++) 271 regs[n] = rd32(E1000_RDT(n)); 272 break; 273 case E1000_RXDCTL(0): 274 for (n = 0; n < 4; n++) 275 regs[n] = rd32(E1000_RXDCTL(n)); 276 break; 277 case E1000_RDBAL(0): 278 for (n = 0; n < 4; n++) 279 regs[n] = rd32(E1000_RDBAL(n)); 280 break; 281 case E1000_RDBAH(0): 282 for (n = 0; n < 4; n++) 283 regs[n] = rd32(E1000_RDBAH(n)); 284 break; 285 case E1000_TDBAL(0): 286 for (n = 0; n < 4; n++) 287 regs[n] = rd32(E1000_TDBAL(n)); 288 break; 289 case E1000_TDBAH(0): 290 for (n = 0; n < 4; n++) 291 regs[n] = rd32(E1000_TDBAH(n)); 292 break; 293 case E1000_TDLEN(0): 294 for (n = 0; n < 4; n++) 295 regs[n] = rd32(E1000_TDLEN(n)); 296 break; 297 case E1000_TDH(0): 298 for (n = 0; n < 4; n++) 299 regs[n] = rd32(E1000_TDH(n)); 300 break; 301 case E1000_TDT(0): 302 for (n = 0; n < 4; n++) 303 regs[n] = rd32(E1000_TDT(n)); 304 break; 305 case E1000_TXDCTL(0): 306 for (n = 0; n < 4; n++) 307 regs[n] = rd32(E1000_TXDCTL(n)); 308 break; 309 default: 310 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 311 return; 312 } 313 314 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 315 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 316 regs[2], regs[3]); 317 } 318 319 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 320 static void igb_dump(struct igb_adapter *adapter) 321 { 322 struct net_device *netdev = adapter->netdev; 323 struct e1000_hw *hw = &adapter->hw; 324 struct igb_reg_info *reginfo; 325 struct igb_ring *tx_ring; 326 union e1000_adv_tx_desc *tx_desc; 327 struct my_u0 { __le64 a; __le64 b; } *u0; 328 struct igb_ring *rx_ring; 329 union e1000_adv_rx_desc *rx_desc; 330 u32 staterr; 331 u16 i, n; 332 333 if (!netif_msg_hw(adapter)) 334 return; 335 336 /* Print netdevice Info */ 337 if (netdev) { 338 dev_info(&adapter->pdev->dev, "Net device Info\n"); 339 pr_info("Device Name state trans_start\n"); 340 pr_info("%-15s %016lX %016lX\n", netdev->name, 341 netdev->state, dev_trans_start(netdev)); 342 } 343 344 /* Print Registers */ 345 dev_info(&adapter->pdev->dev, "Register Dump\n"); 346 pr_info(" Register Name Value\n"); 347 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 348 reginfo->name; reginfo++) { 349 igb_regdump(hw, reginfo); 350 } 351 352 /* Print TX Ring Summary */ 353 if (!netdev || !netif_running(netdev)) 354 goto exit; 355 356 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 357 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 358 for (n = 0; n < adapter->num_tx_queues; n++) { 359 struct igb_tx_buffer *buffer_info; 360 tx_ring = adapter->tx_ring[n]; 361 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 362 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 363 n, tx_ring->next_to_use, tx_ring->next_to_clean, 364 (u64)dma_unmap_addr(buffer_info, dma), 365 dma_unmap_len(buffer_info, len), 366 buffer_info->next_to_watch, 367 (u64)buffer_info->time_stamp); 368 } 369 370 /* Print TX Rings */ 371 if (!netif_msg_tx_done(adapter)) 372 goto rx_ring_summary; 373 374 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 375 376 /* Transmit Descriptor Formats 377 * 378 * Advanced Transmit Descriptor 379 * +--------------------------------------------------------------+ 380 * 0 | Buffer Address [63:0] | 381 * +--------------------------------------------------------------+ 382 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 383 * +--------------------------------------------------------------+ 384 * 63 46 45 40 39 38 36 35 32 31 24 15 0 385 */ 386 387 for (n = 0; n < adapter->num_tx_queues; n++) { 388 tx_ring = adapter->tx_ring[n]; 389 pr_info("------------------------------------\n"); 390 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 391 pr_info("------------------------------------\n"); 392 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 393 394 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 395 const char *next_desc; 396 struct igb_tx_buffer *buffer_info; 397 tx_desc = IGB_TX_DESC(tx_ring, i); 398 buffer_info = &tx_ring->tx_buffer_info[i]; 399 u0 = (struct my_u0 *)tx_desc; 400 if (i == tx_ring->next_to_use && 401 i == tx_ring->next_to_clean) 402 next_desc = " NTC/U"; 403 else if (i == tx_ring->next_to_use) 404 next_desc = " NTU"; 405 else if (i == tx_ring->next_to_clean) 406 next_desc = " NTC"; 407 else 408 next_desc = ""; 409 410 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 411 i, le64_to_cpu(u0->a), 412 le64_to_cpu(u0->b), 413 (u64)dma_unmap_addr(buffer_info, dma), 414 dma_unmap_len(buffer_info, len), 415 buffer_info->next_to_watch, 416 (u64)buffer_info->time_stamp, 417 buffer_info->skb, next_desc); 418 419 if (netif_msg_pktdata(adapter) && buffer_info->skb) 420 print_hex_dump(KERN_INFO, "", 421 DUMP_PREFIX_ADDRESS, 422 16, 1, buffer_info->skb->data, 423 dma_unmap_len(buffer_info, len), 424 true); 425 } 426 } 427 428 /* Print RX Rings Summary */ 429 rx_ring_summary: 430 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 431 pr_info("Queue [NTU] [NTC]\n"); 432 for (n = 0; n < adapter->num_rx_queues; n++) { 433 rx_ring = adapter->rx_ring[n]; 434 pr_info(" %5d %5X %5X\n", 435 n, rx_ring->next_to_use, rx_ring->next_to_clean); 436 } 437 438 /* Print RX Rings */ 439 if (!netif_msg_rx_status(adapter)) 440 goto exit; 441 442 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 443 444 /* Advanced Receive Descriptor (Read) Format 445 * 63 1 0 446 * +-----------------------------------------------------+ 447 * 0 | Packet Buffer Address [63:1] |A0/NSE| 448 * +----------------------------------------------+------+ 449 * 8 | Header Buffer Address [63:1] | DD | 450 * +-----------------------------------------------------+ 451 * 452 * 453 * Advanced Receive Descriptor (Write-Back) Format 454 * 455 * 63 48 47 32 31 30 21 20 17 16 4 3 0 456 * +------------------------------------------------------+ 457 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 458 * | Checksum Ident | | | | Type | Type | 459 * +------------------------------------------------------+ 460 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 461 * +------------------------------------------------------+ 462 * 63 48 47 32 31 20 19 0 463 */ 464 465 for (n = 0; n < adapter->num_rx_queues; n++) { 466 rx_ring = adapter->rx_ring[n]; 467 pr_info("------------------------------------\n"); 468 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 469 pr_info("------------------------------------\n"); 470 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 471 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 472 473 for (i = 0; i < rx_ring->count; i++) { 474 const char *next_desc; 475 dma_addr_t dma = (dma_addr_t)0; 476 struct igb_rx_buffer *buffer_info = NULL; 477 rx_desc = IGB_RX_DESC(rx_ring, i); 478 u0 = (struct my_u0 *)rx_desc; 479 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 480 481 if (!rx_ring->xsk_pool) { 482 buffer_info = &rx_ring->rx_buffer_info[i]; 483 dma = buffer_info->dma; 484 } 485 486 if (i == rx_ring->next_to_use) 487 next_desc = " NTU"; 488 else if (i == rx_ring->next_to_clean) 489 next_desc = " NTC"; 490 else 491 next_desc = ""; 492 493 if (staterr & E1000_RXD_STAT_DD) { 494 /* Descriptor Done */ 495 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 496 "RWB", i, 497 le64_to_cpu(u0->a), 498 le64_to_cpu(u0->b), 499 next_desc); 500 } else { 501 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 502 "R ", i, 503 le64_to_cpu(u0->a), 504 le64_to_cpu(u0->b), 505 (u64)dma, 506 next_desc); 507 508 if (netif_msg_pktdata(adapter) && 509 buffer_info && dma && buffer_info->page) { 510 print_hex_dump(KERN_INFO, "", 511 DUMP_PREFIX_ADDRESS, 512 16, 1, 513 page_address(buffer_info->page) + 514 buffer_info->page_offset, 515 igb_rx_bufsz(rx_ring), true); 516 } 517 } 518 } 519 } 520 521 exit: 522 return; 523 } 524 525 /** 526 * igb_get_i2c_data - Reads the I2C SDA data bit 527 * @data: opaque pointer to adapter struct 528 * 529 * Returns the I2C data bit value 530 **/ 531 static int igb_get_i2c_data(void *data) 532 { 533 struct igb_adapter *adapter = (struct igb_adapter *)data; 534 struct e1000_hw *hw = &adapter->hw; 535 s32 i2cctl = rd32(E1000_I2CPARAMS); 536 537 return !!(i2cctl & E1000_I2C_DATA_IN); 538 } 539 540 /** 541 * igb_set_i2c_data - Sets the I2C data bit 542 * @data: pointer to hardware structure 543 * @state: I2C data value (0 or 1) to set 544 * 545 * Sets the I2C data bit 546 **/ 547 static void igb_set_i2c_data(void *data, int state) 548 { 549 struct igb_adapter *adapter = (struct igb_adapter *)data; 550 struct e1000_hw *hw = &adapter->hw; 551 s32 i2cctl = rd32(E1000_I2CPARAMS); 552 553 if (state) { 554 i2cctl |= E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N; 555 } else { 556 i2cctl &= ~E1000_I2C_DATA_OE_N; 557 i2cctl &= ~E1000_I2C_DATA_OUT; 558 } 559 560 wr32(E1000_I2CPARAMS, i2cctl); 561 wrfl(); 562 } 563 564 /** 565 * igb_set_i2c_clk - Sets the I2C SCL clock 566 * @data: pointer to hardware structure 567 * @state: state to set clock 568 * 569 * Sets the I2C clock line to state 570 **/ 571 static void igb_set_i2c_clk(void *data, int state) 572 { 573 struct igb_adapter *adapter = (struct igb_adapter *)data; 574 struct e1000_hw *hw = &adapter->hw; 575 s32 i2cctl = rd32(E1000_I2CPARAMS); 576 577 if (state) { 578 i2cctl |= E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N; 579 } else { 580 i2cctl &= ~E1000_I2C_CLK_OUT; 581 i2cctl &= ~E1000_I2C_CLK_OE_N; 582 } 583 wr32(E1000_I2CPARAMS, i2cctl); 584 wrfl(); 585 } 586 587 /** 588 * igb_get_i2c_clk - Gets the I2C SCL clock state 589 * @data: pointer to hardware structure 590 * 591 * Gets the I2C clock state 592 **/ 593 static int igb_get_i2c_clk(void *data) 594 { 595 struct igb_adapter *adapter = (struct igb_adapter *)data; 596 struct e1000_hw *hw = &adapter->hw; 597 s32 i2cctl = rd32(E1000_I2CPARAMS); 598 599 return !!(i2cctl & E1000_I2C_CLK_IN); 600 } 601 602 static const struct i2c_algo_bit_data igb_i2c_algo = { 603 .setsda = igb_set_i2c_data, 604 .setscl = igb_set_i2c_clk, 605 .getsda = igb_get_i2c_data, 606 .getscl = igb_get_i2c_clk, 607 .udelay = 5, 608 .timeout = 20, 609 }; 610 611 /** 612 * igb_get_hw_dev - return device 613 * @hw: pointer to hardware structure 614 * 615 * used by hardware layer to print debugging information 616 **/ 617 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 618 { 619 struct igb_adapter *adapter = hw->back; 620 return adapter->netdev; 621 } 622 623 static struct pci_driver igb_driver; 624 625 /** 626 * igb_init_module - Driver Registration Routine 627 * 628 * igb_init_module is the first routine called when the driver is 629 * loaded. All it does is register with the PCI subsystem. 630 **/ 631 static int __init igb_init_module(void) 632 { 633 int ret; 634 635 pr_info("%s\n", igb_driver_string); 636 pr_info("%s\n", igb_copyright); 637 638 #ifdef CONFIG_IGB_DCA 639 dca_register_notify(&dca_notifier); 640 #endif 641 ret = pci_register_driver(&igb_driver); 642 #ifdef CONFIG_IGB_DCA 643 if (ret) 644 dca_unregister_notify(&dca_notifier); 645 #endif 646 return ret; 647 } 648 649 module_init(igb_init_module); 650 651 /** 652 * igb_exit_module - Driver Exit Cleanup Routine 653 * 654 * igb_exit_module is called just before the driver is removed 655 * from memory. 656 **/ 657 static void __exit igb_exit_module(void) 658 { 659 #ifdef CONFIG_IGB_DCA 660 dca_unregister_notify(&dca_notifier); 661 #endif 662 pci_unregister_driver(&igb_driver); 663 } 664 665 module_exit(igb_exit_module); 666 667 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 668 /** 669 * igb_cache_ring_register - Descriptor ring to register mapping 670 * @adapter: board private structure to initialize 671 * 672 * Once we know the feature-set enabled for the device, we'll cache 673 * the register offset the descriptor ring is assigned to. 674 **/ 675 static void igb_cache_ring_register(struct igb_adapter *adapter) 676 { 677 int i = 0, j = 0; 678 u32 rbase_offset = adapter->vfs_allocated_count; 679 680 switch (adapter->hw.mac.type) { 681 case e1000_82576: 682 /* The queues are allocated for virtualization such that VF 0 683 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 684 * In order to avoid collision we start at the first free queue 685 * and continue consuming queues in the same sequence 686 */ 687 if (adapter->vfs_allocated_count) { 688 for (; i < adapter->rss_queues; i++) 689 adapter->rx_ring[i]->reg_idx = rbase_offset + 690 Q_IDX_82576(i); 691 } 692 fallthrough; 693 case e1000_82575: 694 case e1000_82580: 695 case e1000_i350: 696 case e1000_i354: 697 case e1000_i210: 698 case e1000_i211: 699 default: 700 for (; i < adapter->num_rx_queues; i++) 701 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 702 for (; j < adapter->num_tx_queues; j++) 703 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 704 break; 705 } 706 } 707 708 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 709 { 710 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 711 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 712 u32 value = 0; 713 714 if (E1000_REMOVED(hw_addr)) 715 return ~value; 716 717 value = readl(&hw_addr[reg]); 718 719 /* reads should not return all F's */ 720 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 721 struct net_device *netdev = igb->netdev; 722 hw->hw_addr = NULL; 723 netdev_err(netdev, "PCIe link lost\n"); 724 WARN(pci_device_is_present(igb->pdev), 725 "igb: Failed to read reg 0x%x!\n", reg); 726 } 727 728 return value; 729 } 730 731 /** 732 * igb_write_ivar - configure ivar for given MSI-X vector 733 * @hw: pointer to the HW structure 734 * @msix_vector: vector number we are allocating to a given ring 735 * @index: row index of IVAR register to write within IVAR table 736 * @offset: column offset of in IVAR, should be multiple of 8 737 * 738 * This function is intended to handle the writing of the IVAR register 739 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 740 * each containing an cause allocation for an Rx and Tx ring, and a 741 * variable number of rows depending on the number of queues supported. 742 **/ 743 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 744 int index, int offset) 745 { 746 u32 ivar = array_rd32(E1000_IVAR0, index); 747 748 /* clear any bits that are currently set */ 749 ivar &= ~((u32)0xFF << offset); 750 751 /* write vector and valid bit */ 752 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 753 754 array_wr32(E1000_IVAR0, index, ivar); 755 } 756 757 #define IGB_N0_QUEUE -1 758 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 759 { 760 struct igb_adapter *adapter = q_vector->adapter; 761 struct e1000_hw *hw = &adapter->hw; 762 int rx_queue = IGB_N0_QUEUE; 763 int tx_queue = IGB_N0_QUEUE; 764 u32 msixbm = 0; 765 766 if (q_vector->rx.ring) 767 rx_queue = q_vector->rx.ring->reg_idx; 768 if (q_vector->tx.ring) 769 tx_queue = q_vector->tx.ring->reg_idx; 770 771 switch (hw->mac.type) { 772 case e1000_82575: 773 /* The 82575 assigns vectors using a bitmask, which matches the 774 * bitmask for the EICR/EIMS/EIMC registers. To assign one 775 * or more queues to a vector, we write the appropriate bits 776 * into the MSIXBM register for that vector. 777 */ 778 if (rx_queue > IGB_N0_QUEUE) 779 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 780 if (tx_queue > IGB_N0_QUEUE) 781 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 782 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 783 msixbm |= E1000_EIMS_OTHER; 784 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 785 q_vector->eims_value = msixbm; 786 break; 787 case e1000_82576: 788 /* 82576 uses a table that essentially consists of 2 columns 789 * with 8 rows. The ordering is column-major so we use the 790 * lower 3 bits as the row index, and the 4th bit as the 791 * column offset. 792 */ 793 if (rx_queue > IGB_N0_QUEUE) 794 igb_write_ivar(hw, msix_vector, 795 rx_queue & 0x7, 796 (rx_queue & 0x8) << 1); 797 if (tx_queue > IGB_N0_QUEUE) 798 igb_write_ivar(hw, msix_vector, 799 tx_queue & 0x7, 800 ((tx_queue & 0x8) << 1) + 8); 801 q_vector->eims_value = BIT(msix_vector); 802 break; 803 case e1000_82580: 804 case e1000_i350: 805 case e1000_i354: 806 case e1000_i210: 807 case e1000_i211: 808 /* On 82580 and newer adapters the scheme is similar to 82576 809 * however instead of ordering column-major we have things 810 * ordered row-major. So we traverse the table by using 811 * bit 0 as the column offset, and the remaining bits as the 812 * row index. 813 */ 814 if (rx_queue > IGB_N0_QUEUE) 815 igb_write_ivar(hw, msix_vector, 816 rx_queue >> 1, 817 (rx_queue & 0x1) << 4); 818 if (tx_queue > IGB_N0_QUEUE) 819 igb_write_ivar(hw, msix_vector, 820 tx_queue >> 1, 821 ((tx_queue & 0x1) << 4) + 8); 822 q_vector->eims_value = BIT(msix_vector); 823 break; 824 default: 825 BUG(); 826 break; 827 } 828 829 /* add q_vector eims value to global eims_enable_mask */ 830 adapter->eims_enable_mask |= q_vector->eims_value; 831 832 /* configure q_vector to set itr on first interrupt */ 833 q_vector->set_itr = 1; 834 } 835 836 /** 837 * igb_configure_msix - Configure MSI-X hardware 838 * @adapter: board private structure to initialize 839 * 840 * igb_configure_msix sets up the hardware to properly 841 * generate MSI-X interrupts. 842 **/ 843 static void igb_configure_msix(struct igb_adapter *adapter) 844 { 845 u32 tmp; 846 int i, vector = 0; 847 struct e1000_hw *hw = &adapter->hw; 848 849 adapter->eims_enable_mask = 0; 850 851 /* set vector for other causes, i.e. link changes */ 852 switch (hw->mac.type) { 853 case e1000_82575: 854 tmp = rd32(E1000_CTRL_EXT); 855 /* enable MSI-X PBA support*/ 856 tmp |= E1000_CTRL_EXT_PBA_CLR; 857 858 /* Auto-Mask interrupts upon ICR read. */ 859 tmp |= E1000_CTRL_EXT_EIAME; 860 tmp |= E1000_CTRL_EXT_IRCA; 861 862 wr32(E1000_CTRL_EXT, tmp); 863 864 /* enable msix_other interrupt */ 865 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 866 adapter->eims_other = E1000_EIMS_OTHER; 867 868 break; 869 870 case e1000_82576: 871 case e1000_82580: 872 case e1000_i350: 873 case e1000_i354: 874 case e1000_i210: 875 case e1000_i211: 876 /* Turn on MSI-X capability first, or our settings 877 * won't stick. And it will take days to debug. 878 */ 879 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 880 E1000_GPIE_PBA | E1000_GPIE_EIAME | 881 E1000_GPIE_NSICR); 882 883 /* enable msix_other interrupt */ 884 adapter->eims_other = BIT(vector); 885 tmp = (vector++ | E1000_IVAR_VALID) << 8; 886 887 wr32(E1000_IVAR_MISC, tmp); 888 break; 889 default: 890 /* do nothing, since nothing else supports MSI-X */ 891 break; 892 } /* switch (hw->mac.type) */ 893 894 adapter->eims_enable_mask |= adapter->eims_other; 895 896 for (i = 0; i < adapter->num_q_vectors; i++) 897 igb_assign_vector(adapter->q_vector[i], vector++); 898 899 wrfl(); 900 } 901 902 /** 903 * igb_request_msix - Initialize MSI-X interrupts 904 * @adapter: board private structure to initialize 905 * 906 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 907 * kernel. 908 **/ 909 static int igb_request_msix(struct igb_adapter *adapter) 910 { 911 unsigned int num_q_vectors = adapter->num_q_vectors; 912 struct net_device *netdev = adapter->netdev; 913 int i, err = 0, vector = 0, free_vector = 0; 914 915 err = request_irq(adapter->msix_entries[vector].vector, 916 igb_msix_other, 0, netdev->name, adapter); 917 if (err) 918 goto err_out; 919 920 if (num_q_vectors > MAX_Q_VECTORS) { 921 num_q_vectors = MAX_Q_VECTORS; 922 dev_warn(&adapter->pdev->dev, 923 "The number of queue vectors (%d) is higher than max allowed (%d)\n", 924 adapter->num_q_vectors, MAX_Q_VECTORS); 925 } 926 for (i = 0; i < num_q_vectors; i++) { 927 struct igb_q_vector *q_vector = adapter->q_vector[i]; 928 929 vector++; 930 931 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 932 933 if (q_vector->rx.ring && q_vector->tx.ring) 934 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 935 q_vector->rx.ring->queue_index); 936 else if (q_vector->tx.ring) 937 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 938 q_vector->tx.ring->queue_index); 939 else if (q_vector->rx.ring) 940 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 941 q_vector->rx.ring->queue_index); 942 else 943 sprintf(q_vector->name, "%s-unused", netdev->name); 944 945 err = request_irq(adapter->msix_entries[vector].vector, 946 igb_msix_ring, 0, q_vector->name, 947 q_vector); 948 if (err) 949 goto err_free; 950 951 netif_napi_set_irq(&q_vector->napi, 952 adapter->msix_entries[vector].vector); 953 } 954 955 igb_configure_msix(adapter); 956 return 0; 957 958 err_free: 959 /* free already assigned IRQs */ 960 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 961 962 vector--; 963 for (i = 0; i < vector; i++) { 964 free_irq(adapter->msix_entries[free_vector++].vector, 965 adapter->q_vector[i]); 966 } 967 err_out: 968 return err; 969 } 970 971 /** 972 * igb_free_q_vector - Free memory allocated for specific interrupt vector 973 * @adapter: board private structure to initialize 974 * @v_idx: Index of vector to be freed 975 * 976 * This function frees the memory allocated to the q_vector. 977 **/ 978 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 979 { 980 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 981 982 adapter->q_vector[v_idx] = NULL; 983 984 /* igb_get_stats64() might access the rings on this vector, 985 * we must wait a grace period before freeing it. 986 */ 987 if (q_vector) 988 kfree_rcu(q_vector, rcu); 989 } 990 991 /** 992 * igb_reset_q_vector - Reset config for interrupt vector 993 * @adapter: board private structure to initialize 994 * @v_idx: Index of vector to be reset 995 * 996 * If NAPI is enabled it will delete any references to the 997 * NAPI struct. This is preparation for igb_free_q_vector. 998 **/ 999 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1000 { 1001 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1002 1003 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1004 * allocated. So, q_vector is NULL so we should stop here. 1005 */ 1006 if (!q_vector) 1007 return; 1008 1009 if (q_vector->tx.ring) 1010 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1011 1012 if (q_vector->rx.ring) 1013 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1014 1015 netif_napi_del(&q_vector->napi); 1016 1017 } 1018 1019 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1020 { 1021 int v_idx = adapter->num_q_vectors; 1022 1023 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1024 pci_disable_msix(adapter->pdev); 1025 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1026 pci_disable_msi(adapter->pdev); 1027 1028 while (v_idx--) 1029 igb_reset_q_vector(adapter, v_idx); 1030 } 1031 1032 /** 1033 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1034 * @adapter: board private structure to initialize 1035 * 1036 * This function frees the memory allocated to the q_vectors. In addition if 1037 * NAPI is enabled it will delete any references to the NAPI struct prior 1038 * to freeing the q_vector. 1039 **/ 1040 static void igb_free_q_vectors(struct igb_adapter *adapter) 1041 { 1042 int v_idx = adapter->num_q_vectors; 1043 1044 adapter->num_tx_queues = 0; 1045 adapter->num_rx_queues = 0; 1046 adapter->num_q_vectors = 0; 1047 1048 while (v_idx--) { 1049 igb_reset_q_vector(adapter, v_idx); 1050 igb_free_q_vector(adapter, v_idx); 1051 } 1052 } 1053 1054 /** 1055 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1056 * @adapter: board private structure to initialize 1057 * 1058 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1059 * MSI-X interrupts allocated. 1060 */ 1061 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1062 { 1063 igb_free_q_vectors(adapter); 1064 igb_reset_interrupt_capability(adapter); 1065 } 1066 1067 /** 1068 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1069 * @adapter: board private structure to initialize 1070 * @msix: boolean value of MSIX capability 1071 * 1072 * Attempt to configure interrupts using the best available 1073 * capabilities of the hardware and kernel. 1074 **/ 1075 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1076 { 1077 int err; 1078 int numvecs, i; 1079 1080 if (!msix) 1081 goto msi_only; 1082 adapter->flags |= IGB_FLAG_HAS_MSIX; 1083 1084 /* Number of supported queues. */ 1085 adapter->num_rx_queues = adapter->rss_queues; 1086 if (adapter->vfs_allocated_count) 1087 adapter->num_tx_queues = 1; 1088 else 1089 adapter->num_tx_queues = adapter->rss_queues; 1090 1091 /* start with one vector for every Rx queue */ 1092 numvecs = adapter->num_rx_queues; 1093 1094 /* if Tx handler is separate add 1 for every Tx queue */ 1095 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1096 numvecs += adapter->num_tx_queues; 1097 1098 /* store the number of vectors reserved for queues */ 1099 adapter->num_q_vectors = numvecs; 1100 1101 /* add 1 vector for link status interrupts */ 1102 numvecs++; 1103 for (i = 0; i < numvecs; i++) 1104 adapter->msix_entries[i].entry = i; 1105 1106 err = pci_enable_msix_range(adapter->pdev, 1107 adapter->msix_entries, 1108 numvecs, 1109 numvecs); 1110 if (err > 0) 1111 return; 1112 1113 igb_reset_interrupt_capability(adapter); 1114 1115 /* If we can't do MSI-X, try MSI */ 1116 msi_only: 1117 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1118 #ifdef CONFIG_PCI_IOV 1119 /* disable SR-IOV for non MSI-X configurations */ 1120 if (adapter->vf_data) { 1121 struct e1000_hw *hw = &adapter->hw; 1122 /* disable iov and allow time for transactions to clear */ 1123 pci_disable_sriov(adapter->pdev); 1124 msleep(500); 1125 1126 kfree(adapter->vf_mac_list); 1127 adapter->vf_mac_list = NULL; 1128 kfree(adapter->vf_data); 1129 adapter->vf_data = NULL; 1130 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1131 wrfl(); 1132 msleep(100); 1133 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1134 } 1135 #endif 1136 adapter->vfs_allocated_count = 0; 1137 adapter->rss_queues = 1; 1138 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1139 adapter->num_rx_queues = 1; 1140 adapter->num_tx_queues = 1; 1141 adapter->num_q_vectors = 1; 1142 if (!pci_enable_msi(adapter->pdev)) 1143 adapter->flags |= IGB_FLAG_HAS_MSI; 1144 } 1145 1146 static void igb_add_ring(struct igb_ring *ring, 1147 struct igb_ring_container *head) 1148 { 1149 head->ring = ring; 1150 head->count++; 1151 } 1152 1153 /** 1154 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1155 * @adapter: board private structure to initialize 1156 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1157 * @v_idx: index of vector in adapter struct 1158 * @txr_count: total number of Tx rings to allocate 1159 * @txr_idx: index of first Tx ring to allocate 1160 * @rxr_count: total number of Rx rings to allocate 1161 * @rxr_idx: index of first Rx ring to allocate 1162 * 1163 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1164 **/ 1165 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1166 int v_count, int v_idx, 1167 int txr_count, int txr_idx, 1168 int rxr_count, int rxr_idx) 1169 { 1170 struct igb_q_vector *q_vector; 1171 struct igb_ring *ring; 1172 int ring_count; 1173 size_t size; 1174 1175 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1176 if (txr_count > 1 || rxr_count > 1) 1177 return -ENOMEM; 1178 1179 ring_count = txr_count + rxr_count; 1180 size = kmalloc_size_roundup(struct_size(q_vector, ring, ring_count)); 1181 1182 /* allocate q_vector and rings */ 1183 q_vector = adapter->q_vector[v_idx]; 1184 if (!q_vector) { 1185 q_vector = kzalloc(size, GFP_KERNEL); 1186 } else if (size > ksize(q_vector)) { 1187 struct igb_q_vector *new_q_vector; 1188 1189 new_q_vector = kzalloc(size, GFP_KERNEL); 1190 if (new_q_vector) 1191 kfree_rcu(q_vector, rcu); 1192 q_vector = new_q_vector; 1193 } else { 1194 memset(q_vector, 0, size); 1195 } 1196 if (!q_vector) 1197 return -ENOMEM; 1198 1199 /* initialize NAPI */ 1200 netif_napi_add_config(adapter->netdev, &q_vector->napi, igb_poll, 1201 v_idx); 1202 1203 /* tie q_vector and adapter together */ 1204 adapter->q_vector[v_idx] = q_vector; 1205 q_vector->adapter = adapter; 1206 1207 /* initialize work limits */ 1208 q_vector->tx.work_limit = adapter->tx_work_limit; 1209 1210 /* initialize ITR configuration */ 1211 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1212 q_vector->itr_val = IGB_START_ITR; 1213 1214 /* initialize pointer to rings */ 1215 ring = q_vector->ring; 1216 1217 /* initialize ITR */ 1218 if (rxr_count) { 1219 /* rx or rx/tx vector */ 1220 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1221 q_vector->itr_val = adapter->rx_itr_setting; 1222 } else { 1223 /* tx only vector */ 1224 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1225 q_vector->itr_val = adapter->tx_itr_setting; 1226 } 1227 1228 if (txr_count) { 1229 /* assign generic ring traits */ 1230 ring->dev = &adapter->pdev->dev; 1231 ring->netdev = adapter->netdev; 1232 1233 /* configure backlink on ring */ 1234 ring->q_vector = q_vector; 1235 1236 /* update q_vector Tx values */ 1237 igb_add_ring(ring, &q_vector->tx); 1238 1239 /* For 82575, context index must be unique per ring. */ 1240 if (adapter->hw.mac.type == e1000_82575) 1241 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1242 1243 /* apply Tx specific ring traits */ 1244 ring->count = adapter->tx_ring_count; 1245 ring->queue_index = txr_idx; 1246 1247 ring->cbs_enable = false; 1248 ring->idleslope = 0; 1249 ring->sendslope = 0; 1250 ring->hicredit = 0; 1251 ring->locredit = 0; 1252 1253 u64_stats_init(&ring->tx_syncp); 1254 u64_stats_init(&ring->tx_syncp2); 1255 1256 /* assign ring to adapter */ 1257 adapter->tx_ring[txr_idx] = ring; 1258 1259 /* push pointer to next ring */ 1260 ring++; 1261 } 1262 1263 if (rxr_count) { 1264 /* assign generic ring traits */ 1265 ring->dev = &adapter->pdev->dev; 1266 ring->netdev = adapter->netdev; 1267 1268 /* configure backlink on ring */ 1269 ring->q_vector = q_vector; 1270 1271 /* update q_vector Rx values */ 1272 igb_add_ring(ring, &q_vector->rx); 1273 1274 /* set flag indicating ring supports SCTP checksum offload */ 1275 if (adapter->hw.mac.type >= e1000_82576) 1276 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1277 1278 /* On i350, i354, i210, and i211, loopback VLAN packets 1279 * have the tag byte-swapped. 1280 */ 1281 if (adapter->hw.mac.type >= e1000_i350) 1282 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1283 1284 /* apply Rx specific ring traits */ 1285 ring->count = adapter->rx_ring_count; 1286 ring->queue_index = rxr_idx; 1287 1288 u64_stats_init(&ring->rx_syncp); 1289 1290 /* assign ring to adapter */ 1291 adapter->rx_ring[rxr_idx] = ring; 1292 } 1293 1294 return 0; 1295 } 1296 1297 1298 /** 1299 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1300 * @adapter: board private structure to initialize 1301 * 1302 * We allocate one q_vector per queue interrupt. If allocation fails we 1303 * return -ENOMEM. 1304 **/ 1305 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1306 { 1307 int q_vectors = adapter->num_q_vectors; 1308 int rxr_remaining = adapter->num_rx_queues; 1309 int txr_remaining = adapter->num_tx_queues; 1310 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1311 int err; 1312 1313 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1314 for (; rxr_remaining; v_idx++) { 1315 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1316 0, 0, 1, rxr_idx); 1317 1318 if (err) 1319 goto err_out; 1320 1321 /* update counts and index */ 1322 rxr_remaining--; 1323 rxr_idx++; 1324 } 1325 } 1326 1327 for (; v_idx < q_vectors; v_idx++) { 1328 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1329 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1330 1331 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1332 tqpv, txr_idx, rqpv, rxr_idx); 1333 1334 if (err) 1335 goto err_out; 1336 1337 /* update counts and index */ 1338 rxr_remaining -= rqpv; 1339 txr_remaining -= tqpv; 1340 rxr_idx++; 1341 txr_idx++; 1342 } 1343 1344 return 0; 1345 1346 err_out: 1347 adapter->num_tx_queues = 0; 1348 adapter->num_rx_queues = 0; 1349 adapter->num_q_vectors = 0; 1350 1351 while (v_idx--) 1352 igb_free_q_vector(adapter, v_idx); 1353 1354 return -ENOMEM; 1355 } 1356 1357 /** 1358 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1359 * @adapter: board private structure to initialize 1360 * @msix: boolean value of MSIX capability 1361 * 1362 * This function initializes the interrupts and allocates all of the queues. 1363 **/ 1364 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1365 { 1366 struct pci_dev *pdev = adapter->pdev; 1367 int err; 1368 1369 igb_set_interrupt_capability(adapter, msix); 1370 1371 err = igb_alloc_q_vectors(adapter); 1372 if (err) { 1373 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1374 goto err_alloc_q_vectors; 1375 } 1376 1377 igb_cache_ring_register(adapter); 1378 1379 return 0; 1380 1381 err_alloc_q_vectors: 1382 igb_reset_interrupt_capability(adapter); 1383 return err; 1384 } 1385 1386 /** 1387 * igb_request_irq - initialize interrupts 1388 * @adapter: board private structure to initialize 1389 * 1390 * Attempts to configure interrupts using the best available 1391 * capabilities of the hardware and kernel. 1392 **/ 1393 static int igb_request_irq(struct igb_adapter *adapter) 1394 { 1395 struct net_device *netdev = adapter->netdev; 1396 struct pci_dev *pdev = adapter->pdev; 1397 int err = 0; 1398 1399 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1400 err = igb_request_msix(adapter); 1401 if (!err) 1402 goto request_done; 1403 /* fall back to MSI */ 1404 igb_free_all_tx_resources(adapter); 1405 igb_free_all_rx_resources(adapter); 1406 1407 igb_clear_interrupt_scheme(adapter); 1408 err = igb_init_interrupt_scheme(adapter, false); 1409 if (err) 1410 goto request_done; 1411 1412 igb_setup_all_tx_resources(adapter); 1413 igb_setup_all_rx_resources(adapter); 1414 igb_configure(adapter); 1415 } 1416 1417 igb_assign_vector(adapter->q_vector[0], 0); 1418 1419 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1420 err = request_irq(pdev->irq, igb_intr_msi, 0, 1421 netdev->name, adapter); 1422 if (!err) 1423 goto request_done; 1424 1425 /* fall back to legacy interrupts */ 1426 igb_reset_interrupt_capability(adapter); 1427 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1428 } 1429 1430 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1431 netdev->name, adapter); 1432 1433 if (err) 1434 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1435 err); 1436 1437 request_done: 1438 return err; 1439 } 1440 1441 static void igb_free_irq(struct igb_adapter *adapter) 1442 { 1443 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1444 int vector = 0, i; 1445 1446 free_irq(adapter->msix_entries[vector++].vector, adapter); 1447 1448 for (i = 0; i < adapter->num_q_vectors; i++) 1449 free_irq(adapter->msix_entries[vector++].vector, 1450 adapter->q_vector[i]); 1451 } else { 1452 free_irq(adapter->pdev->irq, adapter); 1453 } 1454 } 1455 1456 /** 1457 * igb_irq_disable - Mask off interrupt generation on the NIC 1458 * @adapter: board private structure 1459 **/ 1460 static void igb_irq_disable(struct igb_adapter *adapter) 1461 { 1462 struct e1000_hw *hw = &adapter->hw; 1463 1464 /* we need to be careful when disabling interrupts. The VFs are also 1465 * mapped into these registers and so clearing the bits can cause 1466 * issues on the VF drivers so we only need to clear what we set 1467 */ 1468 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1469 u32 regval = rd32(E1000_EIAM); 1470 1471 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1472 wr32(E1000_EIMC, adapter->eims_enable_mask); 1473 regval = rd32(E1000_EIAC); 1474 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1475 } 1476 1477 wr32(E1000_IAM, 0); 1478 wr32(E1000_IMC, ~0); 1479 wrfl(); 1480 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1481 int i; 1482 1483 for (i = 0; i < adapter->num_q_vectors; i++) 1484 synchronize_irq(adapter->msix_entries[i].vector); 1485 } else { 1486 synchronize_irq(adapter->pdev->irq); 1487 } 1488 } 1489 1490 /** 1491 * igb_irq_enable - Enable default interrupt generation settings 1492 * @adapter: board private structure 1493 **/ 1494 static void igb_irq_enable(struct igb_adapter *adapter) 1495 { 1496 struct e1000_hw *hw = &adapter->hw; 1497 1498 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1499 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1500 u32 regval = rd32(E1000_EIAC); 1501 1502 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1503 regval = rd32(E1000_EIAM); 1504 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1505 wr32(E1000_EIMS, adapter->eims_enable_mask); 1506 if (adapter->vfs_allocated_count) { 1507 wr32(E1000_MBVFIMR, 0xFF); 1508 ims |= E1000_IMS_VMMB; 1509 } 1510 wr32(E1000_IMS, ims); 1511 } else { 1512 wr32(E1000_IMS, IMS_ENABLE_MASK | 1513 E1000_IMS_DRSTA); 1514 wr32(E1000_IAM, IMS_ENABLE_MASK | 1515 E1000_IMS_DRSTA); 1516 } 1517 } 1518 1519 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1520 { 1521 struct e1000_hw *hw = &adapter->hw; 1522 u16 pf_id = adapter->vfs_allocated_count; 1523 u16 vid = adapter->hw.mng_cookie.vlan_id; 1524 u16 old_vid = adapter->mng_vlan_id; 1525 1526 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1527 /* add VID to filter table */ 1528 igb_vfta_set(hw, vid, pf_id, true, true); 1529 adapter->mng_vlan_id = vid; 1530 } else { 1531 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1532 } 1533 1534 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1535 (vid != old_vid) && 1536 !test_bit(old_vid, adapter->active_vlans)) { 1537 /* remove VID from filter table */ 1538 igb_vfta_set(hw, vid, pf_id, false, true); 1539 } 1540 } 1541 1542 /** 1543 * igb_release_hw_control - release control of the h/w to f/w 1544 * @adapter: address of board private structure 1545 * 1546 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1547 * For ASF and Pass Through versions of f/w this means that the 1548 * driver is no longer loaded. 1549 **/ 1550 static void igb_release_hw_control(struct igb_adapter *adapter) 1551 { 1552 struct e1000_hw *hw = &adapter->hw; 1553 u32 ctrl_ext; 1554 1555 /* Let firmware take over control of h/w */ 1556 ctrl_ext = rd32(E1000_CTRL_EXT); 1557 wr32(E1000_CTRL_EXT, 1558 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1559 } 1560 1561 /** 1562 * igb_get_hw_control - get control of the h/w from f/w 1563 * @adapter: address of board private structure 1564 * 1565 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1566 * For ASF and Pass Through versions of f/w this means that 1567 * the driver is loaded. 1568 **/ 1569 static void igb_get_hw_control(struct igb_adapter *adapter) 1570 { 1571 struct e1000_hw *hw = &adapter->hw; 1572 u32 ctrl_ext; 1573 1574 /* Let firmware know the driver has taken over */ 1575 ctrl_ext = rd32(E1000_CTRL_EXT); 1576 wr32(E1000_CTRL_EXT, 1577 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1578 } 1579 1580 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1581 { 1582 struct net_device *netdev = adapter->netdev; 1583 struct e1000_hw *hw = &adapter->hw; 1584 1585 WARN_ON(hw->mac.type != e1000_i210); 1586 1587 if (enable) 1588 adapter->flags |= IGB_FLAG_FQTSS; 1589 else 1590 adapter->flags &= ~IGB_FLAG_FQTSS; 1591 1592 if (netif_running(netdev)) 1593 schedule_work(&adapter->reset_task); 1594 } 1595 1596 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1597 { 1598 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1599 } 1600 1601 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1602 enum tx_queue_prio prio) 1603 { 1604 u32 val; 1605 1606 WARN_ON(hw->mac.type != e1000_i210); 1607 WARN_ON(queue < 0 || queue > 4); 1608 1609 val = rd32(E1000_I210_TXDCTL(queue)); 1610 1611 if (prio == TX_QUEUE_PRIO_HIGH) 1612 val |= E1000_TXDCTL_PRIORITY; 1613 else 1614 val &= ~E1000_TXDCTL_PRIORITY; 1615 1616 wr32(E1000_I210_TXDCTL(queue), val); 1617 } 1618 1619 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1620 { 1621 u32 val; 1622 1623 WARN_ON(hw->mac.type != e1000_i210); 1624 WARN_ON(queue < 0 || queue > 1); 1625 1626 val = rd32(E1000_I210_TQAVCC(queue)); 1627 1628 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1629 val |= E1000_TQAVCC_QUEUEMODE; 1630 else 1631 val &= ~E1000_TQAVCC_QUEUEMODE; 1632 1633 wr32(E1000_I210_TQAVCC(queue), val); 1634 } 1635 1636 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1637 { 1638 int i; 1639 1640 for (i = 0; i < adapter->num_tx_queues; i++) { 1641 if (adapter->tx_ring[i]->cbs_enable) 1642 return true; 1643 } 1644 1645 return false; 1646 } 1647 1648 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1649 { 1650 int i; 1651 1652 for (i = 0; i < adapter->num_tx_queues; i++) { 1653 if (adapter->tx_ring[i]->launchtime_enable) 1654 return true; 1655 } 1656 1657 return false; 1658 } 1659 1660 /** 1661 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1662 * @adapter: pointer to adapter struct 1663 * @queue: queue number 1664 * 1665 * Configure CBS and Launchtime for a given hardware queue. 1666 * Parameters are retrieved from the correct Tx ring, so 1667 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1668 * for setting those correctly prior to this function being called. 1669 **/ 1670 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1671 { 1672 struct net_device *netdev = adapter->netdev; 1673 struct e1000_hw *hw = &adapter->hw; 1674 struct igb_ring *ring; 1675 u32 tqavcc, tqavctrl; 1676 u16 value; 1677 1678 WARN_ON(hw->mac.type != e1000_i210); 1679 WARN_ON(queue < 0 || queue > 1); 1680 ring = adapter->tx_ring[queue]; 1681 1682 /* If any of the Qav features is enabled, configure queues as SR and 1683 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1684 * as SP. 1685 */ 1686 if (ring->cbs_enable || ring->launchtime_enable) { 1687 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1688 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1689 } else { 1690 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1691 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1692 } 1693 1694 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1695 if (ring->cbs_enable || queue == 0) { 1696 /* i210 does not allow the queue 0 to be in the Strict 1697 * Priority mode while the Qav mode is enabled, so, 1698 * instead of disabling strict priority mode, we give 1699 * queue 0 the maximum of credits possible. 1700 * 1701 * See section 8.12.19 of the i210 datasheet, "Note: 1702 * Queue0 QueueMode must be set to 1b when 1703 * TransmitMode is set to Qav." 1704 */ 1705 if (queue == 0 && !ring->cbs_enable) { 1706 /* max "linkspeed" idleslope in kbps */ 1707 ring->idleslope = 1000000; 1708 ring->hicredit = ETH_FRAME_LEN; 1709 } 1710 1711 /* Always set data transfer arbitration to credit-based 1712 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1713 * the queues. 1714 */ 1715 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1716 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1717 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1718 1719 /* According to i210 datasheet section 7.2.7.7, we should set 1720 * the 'idleSlope' field from TQAVCC register following the 1721 * equation: 1722 * 1723 * For 100 Mbps link speed: 1724 * 1725 * value = BW * 0x7735 * 0.2 (E1) 1726 * 1727 * For 1000Mbps link speed: 1728 * 1729 * value = BW * 0x7735 * 2 (E2) 1730 * 1731 * E1 and E2 can be merged into one equation as shown below. 1732 * Note that 'link-speed' is in Mbps. 1733 * 1734 * value = BW * 0x7735 * 2 * link-speed 1735 * -------------- (E3) 1736 * 1000 1737 * 1738 * 'BW' is the percentage bandwidth out of full link speed 1739 * which can be found with the following equation. Note that 1740 * idleSlope here is the parameter from this function which 1741 * is in kbps. 1742 * 1743 * BW = idleSlope 1744 * ----------------- (E4) 1745 * link-speed * 1000 1746 * 1747 * That said, we can come up with a generic equation to 1748 * calculate the value we should set it TQAVCC register by 1749 * replacing 'BW' in E3 by E4. The resulting equation is: 1750 * 1751 * value = idleSlope * 0x7735 * 2 * link-speed 1752 * ----------------- -------------- (E5) 1753 * link-speed * 1000 1000 1754 * 1755 * 'link-speed' is present in both sides of the fraction so 1756 * it is canceled out. The final equation is the following: 1757 * 1758 * value = idleSlope * 61034 1759 * ----------------- (E6) 1760 * 1000000 1761 * 1762 * NOTE: For i210, given the above, we can see that idleslope 1763 * is represented in 16.38431 kbps units by the value at 1764 * the TQAVCC register (1Gbps / 61034), which reduces 1765 * the granularity for idleslope increments. 1766 * For instance, if you want to configure a 2576kbps 1767 * idleslope, the value to be written on the register 1768 * would have to be 157.23. If rounded down, you end 1769 * up with less bandwidth available than originally 1770 * required (~2572 kbps). If rounded up, you end up 1771 * with a higher bandwidth (~2589 kbps). Below the 1772 * approach we take is to always round up the 1773 * calculated value, so the resulting bandwidth might 1774 * be slightly higher for some configurations. 1775 */ 1776 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1777 1778 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1779 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1780 tqavcc |= value; 1781 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1782 1783 wr32(E1000_I210_TQAVHC(queue), 1784 0x80000000 + ring->hicredit * 0x7735); 1785 } else { 1786 1787 /* Set idleSlope to zero. */ 1788 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1789 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1790 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1791 1792 /* Set hiCredit to zero. */ 1793 wr32(E1000_I210_TQAVHC(queue), 0); 1794 1795 /* If CBS is not enabled for any queues anymore, then return to 1796 * the default state of Data Transmission Arbitration on 1797 * TQAVCTRL. 1798 */ 1799 if (!is_any_cbs_enabled(adapter)) { 1800 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1801 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1802 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1803 } 1804 } 1805 1806 /* If LaunchTime is enabled, set DataTranTIM. */ 1807 if (ring->launchtime_enable) { 1808 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1809 * for any of the SR queues, and configure fetchtime delta. 1810 * XXX NOTE: 1811 * - LaunchTime will be enabled for all SR queues. 1812 * - A fixed offset can be added relative to the launch 1813 * time of all packets if configured at reg LAUNCH_OS0. 1814 * We are keeping it as 0 for now (default value). 1815 */ 1816 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1817 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1818 E1000_TQAVCTRL_FETCHTIME_DELTA; 1819 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1820 } else { 1821 /* If Launchtime is not enabled for any SR queues anymore, 1822 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1823 * effectively disabling Launchtime. 1824 */ 1825 if (!is_any_txtime_enabled(adapter)) { 1826 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1827 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1828 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1829 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1830 } 1831 } 1832 1833 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1834 * CBS are not configurable by software so we don't do any 'controller 1835 * configuration' in respect to these parameters. 1836 */ 1837 1838 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1839 ring->cbs_enable ? "enabled" : "disabled", 1840 ring->launchtime_enable ? "enabled" : "disabled", 1841 queue, 1842 ring->idleslope, ring->sendslope, 1843 ring->hicredit, ring->locredit); 1844 } 1845 1846 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1847 bool enable) 1848 { 1849 struct igb_ring *ring; 1850 1851 if (queue < 0 || queue > adapter->num_tx_queues) 1852 return -EINVAL; 1853 1854 ring = adapter->tx_ring[queue]; 1855 ring->launchtime_enable = enable; 1856 1857 return 0; 1858 } 1859 1860 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1861 bool enable, int idleslope, int sendslope, 1862 int hicredit, int locredit) 1863 { 1864 struct igb_ring *ring; 1865 1866 if (queue < 0 || queue > adapter->num_tx_queues) 1867 return -EINVAL; 1868 1869 ring = adapter->tx_ring[queue]; 1870 1871 ring->cbs_enable = enable; 1872 ring->idleslope = idleslope; 1873 ring->sendslope = sendslope; 1874 ring->hicredit = hicredit; 1875 ring->locredit = locredit; 1876 1877 return 0; 1878 } 1879 1880 /** 1881 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1882 * @adapter: pointer to adapter struct 1883 * 1884 * Configure TQAVCTRL register switching the controller's Tx mode 1885 * if FQTSS mode is enabled or disabled. Additionally, will issue 1886 * a call to igb_config_tx_modes() per queue so any previously saved 1887 * Tx parameters are applied. 1888 **/ 1889 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1890 { 1891 struct net_device *netdev = adapter->netdev; 1892 struct e1000_hw *hw = &adapter->hw; 1893 u32 val; 1894 1895 /* Only i210 controller supports changing the transmission mode. */ 1896 if (hw->mac.type != e1000_i210) 1897 return; 1898 1899 if (is_fqtss_enabled(adapter)) { 1900 int i, max_queue; 1901 1902 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1903 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1904 * so SP queues wait for SR ones. 1905 */ 1906 val = rd32(E1000_I210_TQAVCTRL); 1907 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1908 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1909 wr32(E1000_I210_TQAVCTRL, val); 1910 1911 /* Configure Tx and Rx packet buffers sizes as described in 1912 * i210 datasheet section 7.2.7.7. 1913 */ 1914 val = rd32(E1000_TXPBS); 1915 val &= ~I210_TXPBSIZE_MASK; 1916 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB | 1917 I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB; 1918 wr32(E1000_TXPBS, val); 1919 1920 val = rd32(E1000_RXPBS); 1921 val &= ~I210_RXPBSIZE_MASK; 1922 val |= I210_RXPBSIZE_PB_30KB; 1923 wr32(E1000_RXPBS, val); 1924 1925 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1926 * register should not exceed the buffer size programmed in 1927 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1928 * so according to the datasheet we should set MAX_TPKT_SIZE to 1929 * 4kB / 64. 1930 * 1931 * However, when we do so, no frame from queue 2 and 3 are 1932 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1933 * or _equal_ to the buffer size programmed in TXPBS. For this 1934 * reason, we set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1935 */ 1936 val = (4096 - 1) / 64; 1937 wr32(E1000_I210_DTXMXPKTSZ, val); 1938 1939 /* Since FQTSS mode is enabled, apply any CBS configuration 1940 * previously set. If no previous CBS configuration has been 1941 * done, then the initial configuration is applied, which means 1942 * CBS is disabled. 1943 */ 1944 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1945 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1946 1947 for (i = 0; i < max_queue; i++) { 1948 igb_config_tx_modes(adapter, i); 1949 } 1950 } else { 1951 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1952 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1953 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1954 1955 val = rd32(E1000_I210_TQAVCTRL); 1956 /* According to Section 8.12.21, the other flags we've set when 1957 * enabling FQTSS are not relevant when disabling FQTSS so we 1958 * don't set they here. 1959 */ 1960 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1961 wr32(E1000_I210_TQAVCTRL, val); 1962 } 1963 1964 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1965 "enabled" : "disabled"); 1966 } 1967 1968 /** 1969 * igb_configure - configure the hardware for RX and TX 1970 * @adapter: private board structure 1971 **/ 1972 static void igb_configure(struct igb_adapter *adapter) 1973 { 1974 struct net_device *netdev = adapter->netdev; 1975 int i; 1976 1977 igb_get_hw_control(adapter); 1978 igb_set_rx_mode(netdev); 1979 igb_setup_tx_mode(adapter); 1980 1981 igb_restore_vlan(adapter); 1982 1983 igb_setup_tctl(adapter); 1984 igb_setup_mrqc(adapter); 1985 igb_setup_rctl(adapter); 1986 1987 igb_nfc_filter_restore(adapter); 1988 igb_configure_tx(adapter); 1989 igb_configure_rx(adapter); 1990 1991 igb_rx_fifo_flush_82575(&adapter->hw); 1992 1993 /* call igb_desc_unused which always leaves 1994 * at least 1 descriptor unused to make sure 1995 * next_to_use != next_to_clean 1996 */ 1997 for (i = 0; i < adapter->num_rx_queues; i++) { 1998 struct igb_ring *ring = adapter->rx_ring[i]; 1999 if (ring->xsk_pool) 2000 igb_alloc_rx_buffers_zc(ring, ring->xsk_pool, 2001 igb_desc_unused(ring)); 2002 else 2003 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 2004 } 2005 } 2006 2007 /** 2008 * igb_power_up_link - Power up the phy/serdes link 2009 * @adapter: address of board private structure 2010 **/ 2011 void igb_power_up_link(struct igb_adapter *adapter) 2012 { 2013 igb_reset_phy(&adapter->hw); 2014 2015 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2016 igb_power_up_phy_copper(&adapter->hw); 2017 else 2018 igb_power_up_serdes_link_82575(&adapter->hw); 2019 2020 igb_setup_link(&adapter->hw); 2021 } 2022 2023 /** 2024 * igb_power_down_link - Power down the phy/serdes link 2025 * @adapter: address of board private structure 2026 */ 2027 static void igb_power_down_link(struct igb_adapter *adapter) 2028 { 2029 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2030 igb_power_down_phy_copper_82575(&adapter->hw); 2031 else 2032 igb_shutdown_serdes_link_82575(&adapter->hw); 2033 } 2034 2035 /** 2036 * igb_check_swap_media - Detect and switch function for Media Auto Sense 2037 * @adapter: address of the board private structure 2038 **/ 2039 static void igb_check_swap_media(struct igb_adapter *adapter) 2040 { 2041 struct e1000_hw *hw = &adapter->hw; 2042 u32 ctrl_ext, connsw; 2043 bool swap_now = false; 2044 2045 ctrl_ext = rd32(E1000_CTRL_EXT); 2046 connsw = rd32(E1000_CONNSW); 2047 2048 /* need to live swap if current media is copper and we have fiber/serdes 2049 * to go to. 2050 */ 2051 2052 if ((hw->phy.media_type == e1000_media_type_copper) && 2053 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2054 swap_now = true; 2055 } else if ((hw->phy.media_type != e1000_media_type_copper) && 2056 !(connsw & E1000_CONNSW_SERDESD)) { 2057 /* copper signal takes time to appear */ 2058 if (adapter->copper_tries < 4) { 2059 adapter->copper_tries++; 2060 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2061 wr32(E1000_CONNSW, connsw); 2062 return; 2063 } else { 2064 adapter->copper_tries = 0; 2065 if ((connsw & E1000_CONNSW_PHYSD) && 2066 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2067 swap_now = true; 2068 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2069 wr32(E1000_CONNSW, connsw); 2070 } 2071 } 2072 } 2073 2074 if (!swap_now) 2075 return; 2076 2077 switch (hw->phy.media_type) { 2078 case e1000_media_type_copper: 2079 netdev_info(adapter->netdev, 2080 "MAS: changing media to fiber/serdes\n"); 2081 ctrl_ext |= 2082 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2083 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2084 adapter->copper_tries = 0; 2085 break; 2086 case e1000_media_type_internal_serdes: 2087 case e1000_media_type_fiber: 2088 netdev_info(adapter->netdev, 2089 "MAS: changing media to copper\n"); 2090 ctrl_ext &= 2091 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2092 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2093 break; 2094 default: 2095 /* shouldn't get here during regular operation */ 2096 netdev_err(adapter->netdev, 2097 "AMS: Invalid media type found, returning\n"); 2098 break; 2099 } 2100 wr32(E1000_CTRL_EXT, ctrl_ext); 2101 } 2102 2103 void igb_set_queue_napi(struct igb_adapter *adapter, int vector, 2104 struct napi_struct *napi) 2105 { 2106 struct igb_q_vector *q_vector = adapter->q_vector[vector]; 2107 2108 if (q_vector->rx.ring) 2109 netif_queue_set_napi(adapter->netdev, 2110 q_vector->rx.ring->queue_index, 2111 NETDEV_QUEUE_TYPE_RX, napi); 2112 2113 if (q_vector->tx.ring) 2114 netif_queue_set_napi(adapter->netdev, 2115 q_vector->tx.ring->queue_index, 2116 NETDEV_QUEUE_TYPE_TX, napi); 2117 } 2118 2119 /** 2120 * igb_up - Open the interface and prepare it to handle traffic 2121 * @adapter: board private structure 2122 **/ 2123 int igb_up(struct igb_adapter *adapter) 2124 { 2125 struct e1000_hw *hw = &adapter->hw; 2126 struct napi_struct *napi; 2127 int i; 2128 2129 /* hardware has been reset, we need to reload some things */ 2130 igb_configure(adapter); 2131 2132 clear_bit(__IGB_DOWN, &adapter->state); 2133 2134 for (i = 0; i < adapter->num_q_vectors; i++) { 2135 napi = &adapter->q_vector[i]->napi; 2136 napi_enable(napi); 2137 igb_set_queue_napi(adapter, i, napi); 2138 } 2139 2140 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2141 igb_configure_msix(adapter); 2142 else 2143 igb_assign_vector(adapter->q_vector[0], 0); 2144 2145 /* Clear any pending interrupts. */ 2146 rd32(E1000_TSICR); 2147 rd32(E1000_ICR); 2148 igb_irq_enable(adapter); 2149 2150 /* notify VFs that reset has been completed */ 2151 if (adapter->vfs_allocated_count) { 2152 u32 reg_data = rd32(E1000_CTRL_EXT); 2153 2154 reg_data |= E1000_CTRL_EXT_PFRSTD; 2155 wr32(E1000_CTRL_EXT, reg_data); 2156 } 2157 2158 netif_tx_start_all_queues(adapter->netdev); 2159 2160 /* start the watchdog. */ 2161 hw->mac.get_link_status = 1; 2162 schedule_work(&adapter->watchdog_task); 2163 2164 if ((adapter->flags & IGB_FLAG_EEE) && 2165 (!hw->dev_spec._82575.eee_disable)) 2166 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2167 2168 return 0; 2169 } 2170 2171 void igb_down(struct igb_adapter *adapter) 2172 { 2173 struct net_device *netdev = adapter->netdev; 2174 struct e1000_hw *hw = &adapter->hw; 2175 u32 tctl, rctl; 2176 int i; 2177 2178 /* signal that we're down so the interrupt handler does not 2179 * reschedule our watchdog timer 2180 */ 2181 set_bit(__IGB_DOWN, &adapter->state); 2182 2183 /* disable receives in the hardware */ 2184 rctl = rd32(E1000_RCTL); 2185 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2186 /* flush and sleep below */ 2187 2188 igb_nfc_filter_exit(adapter); 2189 2190 netif_carrier_off(netdev); 2191 netif_tx_stop_all_queues(netdev); 2192 2193 /* disable transmits in the hardware */ 2194 tctl = rd32(E1000_TCTL); 2195 tctl &= ~E1000_TCTL_EN; 2196 wr32(E1000_TCTL, tctl); 2197 /* flush both disables and wait for them to finish */ 2198 wrfl(); 2199 usleep_range(10000, 11000); 2200 2201 igb_irq_disable(adapter); 2202 2203 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2204 2205 for (i = 0; i < adapter->num_q_vectors; i++) { 2206 if (adapter->q_vector[i]) { 2207 napi_synchronize(&adapter->q_vector[i]->napi); 2208 igb_set_queue_napi(adapter, i, NULL); 2209 napi_disable(&adapter->q_vector[i]->napi); 2210 } 2211 } 2212 2213 timer_delete_sync(&adapter->watchdog_timer); 2214 timer_delete_sync(&adapter->phy_info_timer); 2215 2216 /* record the stats before reset*/ 2217 spin_lock(&adapter->stats64_lock); 2218 igb_update_stats(adapter); 2219 spin_unlock(&adapter->stats64_lock); 2220 2221 adapter->link_speed = 0; 2222 adapter->link_duplex = 0; 2223 2224 if (!pci_channel_offline(adapter->pdev)) 2225 igb_reset(adapter); 2226 2227 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2228 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2229 2230 igb_clean_all_tx_rings(adapter); 2231 igb_clean_all_rx_rings(adapter); 2232 #ifdef CONFIG_IGB_DCA 2233 2234 /* since we reset the hardware DCA settings were cleared */ 2235 igb_setup_dca(adapter); 2236 #endif 2237 } 2238 2239 void igb_reinit_locked(struct igb_adapter *adapter) 2240 { 2241 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2242 usleep_range(1000, 2000); 2243 igb_down(adapter); 2244 igb_up(adapter); 2245 clear_bit(__IGB_RESETTING, &adapter->state); 2246 } 2247 2248 /** igb_enable_mas - Media Autosense re-enable after swap 2249 * 2250 * @adapter: adapter struct 2251 **/ 2252 static void igb_enable_mas(struct igb_adapter *adapter) 2253 { 2254 struct e1000_hw *hw = &adapter->hw; 2255 u32 connsw = rd32(E1000_CONNSW); 2256 2257 /* configure for SerDes media detect */ 2258 if ((hw->phy.media_type == e1000_media_type_copper) && 2259 (!(connsw & E1000_CONNSW_SERDESD))) { 2260 connsw |= E1000_CONNSW_ENRGSRC; 2261 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2262 wr32(E1000_CONNSW, connsw); 2263 wrfl(); 2264 } 2265 } 2266 2267 #ifdef CONFIG_IGB_HWMON 2268 /** 2269 * igb_set_i2c_bb - Init I2C interface 2270 * @hw: pointer to hardware structure 2271 **/ 2272 static void igb_set_i2c_bb(struct e1000_hw *hw) 2273 { 2274 u32 ctrl_ext; 2275 s32 i2cctl; 2276 2277 ctrl_ext = rd32(E1000_CTRL_EXT); 2278 ctrl_ext |= E1000_CTRL_I2C_ENA; 2279 wr32(E1000_CTRL_EXT, ctrl_ext); 2280 wrfl(); 2281 2282 i2cctl = rd32(E1000_I2CPARAMS); 2283 i2cctl |= E1000_I2CBB_EN 2284 | E1000_I2C_CLK_OE_N 2285 | E1000_I2C_DATA_OE_N; 2286 wr32(E1000_I2CPARAMS, i2cctl); 2287 wrfl(); 2288 } 2289 #endif 2290 2291 void igb_reset(struct igb_adapter *adapter) 2292 { 2293 struct pci_dev *pdev = adapter->pdev; 2294 struct e1000_hw *hw = &adapter->hw; 2295 struct e1000_mac_info *mac = &hw->mac; 2296 struct e1000_fc_info *fc = &hw->fc; 2297 u32 pba, hwm; 2298 2299 /* Repartition Pba for greater than 9k mtu 2300 * To take effect CTRL.RST is required. 2301 */ 2302 switch (mac->type) { 2303 case e1000_i350: 2304 case e1000_i354: 2305 case e1000_82580: 2306 pba = rd32(E1000_RXPBS); 2307 pba = igb_rxpbs_adjust_82580(pba); 2308 break; 2309 case e1000_82576: 2310 pba = rd32(E1000_RXPBS); 2311 pba &= E1000_RXPBS_SIZE_MASK_82576; 2312 break; 2313 case e1000_82575: 2314 case e1000_i210: 2315 case e1000_i211: 2316 default: 2317 pba = E1000_PBA_34K; 2318 break; 2319 } 2320 2321 if (mac->type == e1000_82575) { 2322 u32 min_rx_space, min_tx_space, needed_tx_space; 2323 2324 /* write Rx PBA so that hardware can report correct Tx PBA */ 2325 wr32(E1000_PBA, pba); 2326 2327 /* To maintain wire speed transmits, the Tx FIFO should be 2328 * large enough to accommodate two full transmit packets, 2329 * rounded up to the next 1KB and expressed in KB. Likewise, 2330 * the Rx FIFO should be large enough to accommodate at least 2331 * one full receive packet and is similarly rounded up and 2332 * expressed in KB. 2333 */ 2334 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2335 2336 /* The Tx FIFO also stores 16 bytes of information about the Tx 2337 * but don't include Ethernet FCS because hardware appends it. 2338 * We only need to round down to the nearest 512 byte block 2339 * count since the value we care about is 2 frames, not 1. 2340 */ 2341 min_tx_space = adapter->max_frame_size; 2342 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2343 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2344 2345 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2346 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2347 2348 /* If current Tx allocation is less than the min Tx FIFO size, 2349 * and the min Tx FIFO size is less than the current Rx FIFO 2350 * allocation, take space away from current Rx allocation. 2351 */ 2352 if (needed_tx_space < pba) { 2353 pba -= needed_tx_space; 2354 2355 /* if short on Rx space, Rx wins and must trump Tx 2356 * adjustment 2357 */ 2358 if (pba < min_rx_space) 2359 pba = min_rx_space; 2360 } 2361 2362 /* adjust PBA for jumbo frames */ 2363 wr32(E1000_PBA, pba); 2364 } 2365 2366 /* flow control settings 2367 * The high water mark must be low enough to fit one full frame 2368 * after transmitting the pause frame. As such we must have enough 2369 * space to allow for us to complete our current transmit and then 2370 * receive the frame that is in progress from the link partner. 2371 * Set it to: 2372 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2373 */ 2374 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2375 2376 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2377 fc->low_water = fc->high_water - 16; 2378 fc->pause_time = 0xFFFF; 2379 fc->send_xon = 1; 2380 fc->current_mode = fc->requested_mode; 2381 2382 /* disable receive for all VFs and wait one second */ 2383 if (adapter->vfs_allocated_count) { 2384 int i; 2385 2386 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2387 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2388 2389 /* ping all the active vfs to let them know we are going down */ 2390 igb_ping_all_vfs(adapter); 2391 2392 /* disable transmits and receives */ 2393 wr32(E1000_VFRE, 0); 2394 wr32(E1000_VFTE, 0); 2395 } 2396 2397 /* Allow time for pending master requests to run */ 2398 hw->mac.ops.reset_hw(hw); 2399 wr32(E1000_WUC, 0); 2400 2401 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2402 /* need to resetup here after media swap */ 2403 adapter->ei.get_invariants(hw); 2404 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2405 } 2406 if ((mac->type == e1000_82575 || mac->type == e1000_i350) && 2407 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2408 igb_enable_mas(adapter); 2409 } 2410 if (hw->mac.ops.init_hw(hw)) 2411 dev_err(&pdev->dev, "Hardware Error\n"); 2412 2413 /* RAR registers were cleared during init_hw, clear mac table */ 2414 igb_flush_mac_table(adapter); 2415 __dev_uc_unsync(adapter->netdev, NULL); 2416 2417 /* Recover default RAR entry */ 2418 igb_set_default_mac_filter(adapter); 2419 2420 /* Flow control settings reset on hardware reset, so guarantee flow 2421 * control is off when forcing speed. 2422 */ 2423 if (!hw->mac.autoneg) 2424 igb_force_mac_fc(hw); 2425 2426 igb_init_dmac(adapter, pba); 2427 #ifdef CONFIG_IGB_HWMON 2428 /* Re-initialize the thermal sensor on i350 devices. */ 2429 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2430 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2431 /* If present, re-initialize the external thermal sensor 2432 * interface. 2433 */ 2434 if (adapter->ets) 2435 igb_set_i2c_bb(hw); 2436 mac->ops.init_thermal_sensor_thresh(hw); 2437 } 2438 } 2439 #endif 2440 /* Re-establish EEE setting */ 2441 if (hw->phy.media_type == e1000_media_type_copper) { 2442 switch (mac->type) { 2443 case e1000_i350: 2444 case e1000_i210: 2445 case e1000_i211: 2446 igb_set_eee_i350(hw, true, true); 2447 break; 2448 case e1000_i354: 2449 igb_set_eee_i354(hw, true, true); 2450 break; 2451 default: 2452 break; 2453 } 2454 } 2455 if (!netif_running(adapter->netdev)) 2456 igb_power_down_link(adapter); 2457 2458 igb_update_mng_vlan(adapter); 2459 2460 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2461 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2462 2463 /* Re-enable PTP, where applicable. */ 2464 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2465 igb_ptp_reset(adapter); 2466 2467 igb_get_phy_info(hw); 2468 } 2469 2470 static netdev_features_t igb_fix_features(struct net_device *netdev, 2471 netdev_features_t features) 2472 { 2473 /* Since there is no support for separate Rx/Tx vlan accel 2474 * enable/disable make sure Tx flag is always in same state as Rx. 2475 */ 2476 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2477 features |= NETIF_F_HW_VLAN_CTAG_TX; 2478 else 2479 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2480 2481 return features; 2482 } 2483 2484 static int igb_set_features(struct net_device *netdev, 2485 netdev_features_t features) 2486 { 2487 netdev_features_t changed = netdev->features ^ features; 2488 struct igb_adapter *adapter = netdev_priv(netdev); 2489 2490 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2491 igb_vlan_mode(netdev, features); 2492 2493 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2494 return 0; 2495 2496 if (!(features & NETIF_F_NTUPLE)) { 2497 struct hlist_node *node2; 2498 struct igb_nfc_filter *rule; 2499 2500 spin_lock(&adapter->nfc_lock); 2501 hlist_for_each_entry_safe(rule, node2, 2502 &adapter->nfc_filter_list, nfc_node) { 2503 igb_erase_filter(adapter, rule); 2504 hlist_del(&rule->nfc_node); 2505 kfree(rule); 2506 } 2507 spin_unlock(&adapter->nfc_lock); 2508 adapter->nfc_filter_count = 0; 2509 } 2510 2511 netdev->features = features; 2512 2513 if (netif_running(netdev)) 2514 igb_reinit_locked(adapter); 2515 else 2516 igb_reset(adapter); 2517 2518 return 1; 2519 } 2520 2521 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2522 struct net_device *dev, 2523 const unsigned char *addr, u16 vid, 2524 u16 flags, bool *notified, 2525 struct netlink_ext_ack *extack) 2526 { 2527 /* guarantee we can provide a unique filter for the unicast address */ 2528 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2529 struct igb_adapter *adapter = netdev_priv(dev); 2530 int vfn = adapter->vfs_allocated_count; 2531 2532 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2533 return -ENOMEM; 2534 } 2535 2536 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2537 } 2538 2539 #define IGB_MAX_MAC_HDR_LEN 127 2540 #define IGB_MAX_NETWORK_HDR_LEN 511 2541 2542 static netdev_features_t 2543 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2544 netdev_features_t features) 2545 { 2546 unsigned int network_hdr_len, mac_hdr_len; 2547 2548 /* Make certain the headers can be described by a context descriptor */ 2549 mac_hdr_len = skb_network_offset(skb); 2550 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2551 return features & ~(NETIF_F_HW_CSUM | 2552 NETIF_F_SCTP_CRC | 2553 NETIF_F_GSO_UDP_L4 | 2554 NETIF_F_HW_VLAN_CTAG_TX | 2555 NETIF_F_TSO | 2556 NETIF_F_TSO6); 2557 2558 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2559 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2560 return features & ~(NETIF_F_HW_CSUM | 2561 NETIF_F_SCTP_CRC | 2562 NETIF_F_GSO_UDP_L4 | 2563 NETIF_F_TSO | 2564 NETIF_F_TSO6); 2565 2566 /* We can only support IPV4 TSO in tunnels if we can mangle the 2567 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2568 */ 2569 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2570 features &= ~NETIF_F_TSO; 2571 2572 return features; 2573 } 2574 2575 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2576 { 2577 if (!is_fqtss_enabled(adapter)) { 2578 enable_fqtss(adapter, true); 2579 return; 2580 } 2581 2582 igb_config_tx_modes(adapter, queue); 2583 2584 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2585 enable_fqtss(adapter, false); 2586 } 2587 2588 static int igb_offload_cbs(struct igb_adapter *adapter, 2589 struct tc_cbs_qopt_offload *qopt) 2590 { 2591 struct e1000_hw *hw = &adapter->hw; 2592 int err; 2593 2594 /* CBS offloading is only supported by i210 controller. */ 2595 if (hw->mac.type != e1000_i210) 2596 return -EOPNOTSUPP; 2597 2598 /* CBS offloading is only supported by queue 0 and queue 1. */ 2599 if (qopt->queue < 0 || qopt->queue > 1) 2600 return -EINVAL; 2601 2602 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2603 qopt->idleslope, qopt->sendslope, 2604 qopt->hicredit, qopt->locredit); 2605 if (err) 2606 return err; 2607 2608 igb_offload_apply(adapter, qopt->queue); 2609 2610 return 0; 2611 } 2612 2613 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2614 #define VLAN_PRIO_FULL_MASK (0x07) 2615 2616 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2617 struct flow_cls_offload *f, 2618 int traffic_class, 2619 struct igb_nfc_filter *input) 2620 { 2621 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2622 struct flow_dissector *dissector = rule->match.dissector; 2623 struct netlink_ext_ack *extack = f->common.extack; 2624 2625 if (dissector->used_keys & 2626 ~(BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) | 2627 BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) | 2628 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2629 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN))) { 2630 NL_SET_ERR_MSG_MOD(extack, 2631 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2632 return -EOPNOTSUPP; 2633 } 2634 2635 if (flow_rule_match_has_control_flags(rule, extack)) 2636 return -EOPNOTSUPP; 2637 2638 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2639 struct flow_match_eth_addrs match; 2640 2641 flow_rule_match_eth_addrs(rule, &match); 2642 if (!is_zero_ether_addr(match.mask->dst)) { 2643 if (!is_broadcast_ether_addr(match.mask->dst)) { 2644 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2645 return -EINVAL; 2646 } 2647 2648 input->filter.match_flags |= 2649 IGB_FILTER_FLAG_DST_MAC_ADDR; 2650 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2651 } 2652 2653 if (!is_zero_ether_addr(match.mask->src)) { 2654 if (!is_broadcast_ether_addr(match.mask->src)) { 2655 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2656 return -EINVAL; 2657 } 2658 2659 input->filter.match_flags |= 2660 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2661 ether_addr_copy(input->filter.src_addr, match.key->src); 2662 } 2663 } 2664 2665 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2666 struct flow_match_basic match; 2667 2668 flow_rule_match_basic(rule, &match); 2669 if (match.mask->n_proto) { 2670 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2671 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2672 return -EINVAL; 2673 } 2674 2675 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2676 input->filter.etype = match.key->n_proto; 2677 } 2678 } 2679 2680 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2681 struct flow_match_vlan match; 2682 2683 flow_rule_match_vlan(rule, &match); 2684 if (match.mask->vlan_priority) { 2685 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2686 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2687 return -EINVAL; 2688 } 2689 2690 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2691 input->filter.vlan_tci = 2692 (__force __be16)match.key->vlan_priority; 2693 } 2694 } 2695 2696 input->action = traffic_class; 2697 input->cookie = f->cookie; 2698 2699 return 0; 2700 } 2701 2702 static int igb_configure_clsflower(struct igb_adapter *adapter, 2703 struct flow_cls_offload *cls_flower) 2704 { 2705 struct netlink_ext_ack *extack = cls_flower->common.extack; 2706 struct igb_nfc_filter *filter, *f; 2707 int err, tc; 2708 2709 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2710 if (tc < 0) { 2711 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2712 return -EINVAL; 2713 } 2714 2715 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2716 if (!filter) 2717 return -ENOMEM; 2718 2719 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2720 if (err < 0) 2721 goto err_parse; 2722 2723 spin_lock(&adapter->nfc_lock); 2724 2725 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2726 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2727 err = -EEXIST; 2728 NL_SET_ERR_MSG_MOD(extack, 2729 "This filter is already set in ethtool"); 2730 goto err_locked; 2731 } 2732 } 2733 2734 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2735 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2736 err = -EEXIST; 2737 NL_SET_ERR_MSG_MOD(extack, 2738 "This filter is already set in cls_flower"); 2739 goto err_locked; 2740 } 2741 } 2742 2743 err = igb_add_filter(adapter, filter); 2744 if (err < 0) { 2745 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2746 goto err_locked; 2747 } 2748 2749 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2750 2751 spin_unlock(&adapter->nfc_lock); 2752 2753 return 0; 2754 2755 err_locked: 2756 spin_unlock(&adapter->nfc_lock); 2757 2758 err_parse: 2759 kfree(filter); 2760 2761 return err; 2762 } 2763 2764 static int igb_delete_clsflower(struct igb_adapter *adapter, 2765 struct flow_cls_offload *cls_flower) 2766 { 2767 struct igb_nfc_filter *filter; 2768 int err; 2769 2770 spin_lock(&adapter->nfc_lock); 2771 2772 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2773 if (filter->cookie == cls_flower->cookie) 2774 break; 2775 2776 if (!filter) { 2777 err = -ENOENT; 2778 goto out; 2779 } 2780 2781 err = igb_erase_filter(adapter, filter); 2782 if (err < 0) 2783 goto out; 2784 2785 hlist_del(&filter->nfc_node); 2786 kfree(filter); 2787 2788 out: 2789 spin_unlock(&adapter->nfc_lock); 2790 2791 return err; 2792 } 2793 2794 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2795 struct flow_cls_offload *cls_flower) 2796 { 2797 switch (cls_flower->command) { 2798 case FLOW_CLS_REPLACE: 2799 return igb_configure_clsflower(adapter, cls_flower); 2800 case FLOW_CLS_DESTROY: 2801 return igb_delete_clsflower(adapter, cls_flower); 2802 case FLOW_CLS_STATS: 2803 return -EOPNOTSUPP; 2804 default: 2805 return -EOPNOTSUPP; 2806 } 2807 } 2808 2809 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2810 void *cb_priv) 2811 { 2812 struct igb_adapter *adapter = cb_priv; 2813 2814 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2815 return -EOPNOTSUPP; 2816 2817 switch (type) { 2818 case TC_SETUP_CLSFLOWER: 2819 return igb_setup_tc_cls_flower(adapter, type_data); 2820 2821 default: 2822 return -EOPNOTSUPP; 2823 } 2824 } 2825 2826 static int igb_offload_txtime(struct igb_adapter *adapter, 2827 struct tc_etf_qopt_offload *qopt) 2828 { 2829 struct e1000_hw *hw = &adapter->hw; 2830 int err; 2831 2832 /* Launchtime offloading is only supported by i210 controller. */ 2833 if (hw->mac.type != e1000_i210) 2834 return -EOPNOTSUPP; 2835 2836 /* Launchtime offloading is only supported by queues 0 and 1. */ 2837 if (qopt->queue < 0 || qopt->queue > 1) 2838 return -EINVAL; 2839 2840 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2841 if (err) 2842 return err; 2843 2844 igb_offload_apply(adapter, qopt->queue); 2845 2846 return 0; 2847 } 2848 2849 static int igb_tc_query_caps(struct igb_adapter *adapter, 2850 struct tc_query_caps_base *base) 2851 { 2852 switch (base->type) { 2853 case TC_SETUP_QDISC_TAPRIO: { 2854 struct tc_taprio_caps *caps = base->caps; 2855 2856 caps->broken_mqprio = true; 2857 2858 return 0; 2859 } 2860 default: 2861 return -EOPNOTSUPP; 2862 } 2863 } 2864 2865 static LIST_HEAD(igb_block_cb_list); 2866 2867 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2868 void *type_data) 2869 { 2870 struct igb_adapter *adapter = netdev_priv(dev); 2871 2872 switch (type) { 2873 case TC_QUERY_CAPS: 2874 return igb_tc_query_caps(adapter, type_data); 2875 case TC_SETUP_QDISC_CBS: 2876 return igb_offload_cbs(adapter, type_data); 2877 case TC_SETUP_BLOCK: 2878 return flow_block_cb_setup_simple(type_data, 2879 &igb_block_cb_list, 2880 igb_setup_tc_block_cb, 2881 adapter, adapter, true); 2882 2883 case TC_SETUP_QDISC_ETF: 2884 return igb_offload_txtime(adapter, type_data); 2885 2886 default: 2887 return -EOPNOTSUPP; 2888 } 2889 } 2890 2891 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf) 2892 { 2893 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD; 2894 struct igb_adapter *adapter = netdev_priv(dev); 2895 struct bpf_prog *prog = bpf->prog, *old_prog; 2896 bool running = netif_running(dev); 2897 bool need_reset; 2898 2899 /* verify igb ring attributes are sufficient for XDP */ 2900 for (i = 0; i < adapter->num_rx_queues; i++) { 2901 struct igb_ring *ring = adapter->rx_ring[i]; 2902 2903 if (frame_size > igb_rx_bufsz(ring)) { 2904 NL_SET_ERR_MSG_MOD(bpf->extack, 2905 "The RX buffer size is too small for the frame size"); 2906 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n", 2907 igb_rx_bufsz(ring), frame_size); 2908 return -EINVAL; 2909 } 2910 } 2911 2912 old_prog = xchg(&adapter->xdp_prog, prog); 2913 need_reset = (!!prog != !!old_prog); 2914 2915 /* device is up and bpf is added/removed, must setup the RX queues */ 2916 if (need_reset && running) { 2917 igb_close(dev); 2918 } else { 2919 for (i = 0; i < adapter->num_rx_queues; i++) 2920 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 2921 adapter->xdp_prog); 2922 } 2923 2924 if (old_prog) 2925 bpf_prog_put(old_prog); 2926 2927 /* bpf is just replaced, RXQ and MTU are already setup */ 2928 if (!need_reset) { 2929 return 0; 2930 } else { 2931 if (prog) 2932 xdp_features_set_redirect_target(dev, true); 2933 else 2934 xdp_features_clear_redirect_target(dev); 2935 } 2936 2937 if (running) 2938 igb_open(dev); 2939 2940 return 0; 2941 } 2942 2943 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp) 2944 { 2945 struct igb_adapter *adapter = netdev_priv(dev); 2946 2947 switch (xdp->command) { 2948 case XDP_SETUP_PROG: 2949 return igb_xdp_setup(dev, xdp); 2950 case XDP_SETUP_XSK_POOL: 2951 return igb_xsk_pool_setup(adapter, xdp->xsk.pool, 2952 xdp->xsk.queue_id); 2953 default: 2954 return -EINVAL; 2955 } 2956 } 2957 2958 int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp) 2959 { 2960 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2961 int cpu = smp_processor_id(); 2962 struct igb_ring *tx_ring; 2963 struct netdev_queue *nq; 2964 u32 ret; 2965 2966 if (unlikely(!xdpf)) 2967 return IGB_XDP_CONSUMED; 2968 2969 /* During program transitions its possible adapter->xdp_prog is assigned 2970 * but ring has not been configured yet. In this case simply abort xmit. 2971 */ 2972 tx_ring = igb_xdp_is_enabled(adapter) ? 2973 igb_xdp_tx_queue_mapping(adapter) : NULL; 2974 if (unlikely(!tx_ring)) 2975 return IGB_XDP_CONSUMED; 2976 2977 nq = txring_txq(tx_ring); 2978 __netif_tx_lock(nq, cpu); 2979 /* Avoid transmit queue timeout since we share it with the slow path */ 2980 txq_trans_cond_update(nq); 2981 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2982 __netif_tx_unlock(nq); 2983 2984 return ret; 2985 } 2986 2987 static int igb_xdp_xmit(struct net_device *dev, int n, 2988 struct xdp_frame **frames, u32 flags) 2989 { 2990 struct igb_adapter *adapter = netdev_priv(dev); 2991 int cpu = smp_processor_id(); 2992 struct igb_ring *tx_ring; 2993 struct netdev_queue *nq; 2994 int nxmit = 0; 2995 int i; 2996 2997 if (unlikely(test_bit(__IGB_DOWN, &adapter->state))) 2998 return -ENETDOWN; 2999 3000 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 3001 return -EINVAL; 3002 3003 /* During program transitions its possible adapter->xdp_prog is assigned 3004 * but ring has not been configured yet. In this case simply abort xmit. 3005 */ 3006 tx_ring = igb_xdp_is_enabled(adapter) ? 3007 igb_xdp_tx_queue_mapping(adapter) : NULL; 3008 if (unlikely(!tx_ring)) 3009 return -ENXIO; 3010 3011 if (unlikely(test_bit(IGB_RING_FLAG_TX_DISABLED, &tx_ring->flags))) 3012 return -ENXIO; 3013 3014 nq = txring_txq(tx_ring); 3015 __netif_tx_lock(nq, cpu); 3016 3017 /* Avoid transmit queue timeout since we share it with the slow path */ 3018 txq_trans_cond_update(nq); 3019 3020 for (i = 0; i < n; i++) { 3021 struct xdp_frame *xdpf = frames[i]; 3022 int err; 3023 3024 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 3025 if (err != IGB_XDP_TX) 3026 break; 3027 nxmit++; 3028 } 3029 3030 if (unlikely(flags & XDP_XMIT_FLUSH)) 3031 igb_xdp_ring_update_tail(tx_ring); 3032 3033 __netif_tx_unlock(nq); 3034 3035 return nxmit; 3036 } 3037 3038 static const struct net_device_ops igb_netdev_ops = { 3039 .ndo_open = igb_open, 3040 .ndo_stop = igb_close, 3041 .ndo_start_xmit = igb_xmit_frame, 3042 .ndo_get_stats64 = igb_get_stats64, 3043 .ndo_set_rx_mode = igb_set_rx_mode, 3044 .ndo_set_mac_address = igb_set_mac, 3045 .ndo_change_mtu = igb_change_mtu, 3046 .ndo_eth_ioctl = igb_ioctl, 3047 .ndo_tx_timeout = igb_tx_timeout, 3048 .ndo_validate_addr = eth_validate_addr, 3049 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 3050 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 3051 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 3052 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 3053 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 3054 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 3055 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 3056 .ndo_get_vf_config = igb_ndo_get_vf_config, 3057 .ndo_fix_features = igb_fix_features, 3058 .ndo_set_features = igb_set_features, 3059 .ndo_fdb_add = igb_ndo_fdb_add, 3060 .ndo_features_check = igb_features_check, 3061 .ndo_setup_tc = igb_setup_tc, 3062 .ndo_bpf = igb_xdp, 3063 .ndo_xdp_xmit = igb_xdp_xmit, 3064 .ndo_xsk_wakeup = igb_xsk_wakeup, 3065 .ndo_hwtstamp_get = igb_ptp_hwtstamp_get, 3066 .ndo_hwtstamp_set = igb_ptp_hwtstamp_set, 3067 }; 3068 3069 /** 3070 * igb_set_fw_version - Configure version string for ethtool 3071 * @adapter: adapter struct 3072 **/ 3073 void igb_set_fw_version(struct igb_adapter *adapter) 3074 { 3075 struct e1000_hw *hw = &adapter->hw; 3076 struct e1000_fw_version fw; 3077 3078 igb_get_fw_version(hw, &fw); 3079 3080 switch (hw->mac.type) { 3081 case e1000_i210: 3082 case e1000_i211: 3083 if (!(igb_get_flash_presence_i210(hw))) { 3084 snprintf(adapter->fw_version, 3085 sizeof(adapter->fw_version), 3086 "%2d.%2d-%d", 3087 fw.invm_major, fw.invm_minor, 3088 fw.invm_img_type); 3089 break; 3090 } 3091 fallthrough; 3092 default: 3093 /* if option rom is valid, display its version too */ 3094 if (fw.or_valid) { 3095 snprintf(adapter->fw_version, 3096 sizeof(adapter->fw_version), 3097 "%d.%d, 0x%08x, %d.%d.%d", 3098 fw.eep_major, fw.eep_minor, fw.etrack_id, 3099 fw.or_major, fw.or_build, fw.or_patch); 3100 /* no option rom */ 3101 } else if (fw.etrack_id != 0X0000) { 3102 snprintf(adapter->fw_version, 3103 sizeof(adapter->fw_version), 3104 "%d.%d, 0x%08x", 3105 fw.eep_major, fw.eep_minor, fw.etrack_id); 3106 } else { 3107 snprintf(adapter->fw_version, 3108 sizeof(adapter->fw_version), 3109 "%d.%d.%d", 3110 fw.eep_major, fw.eep_minor, fw.eep_build); 3111 } 3112 break; 3113 } 3114 } 3115 3116 /** 3117 * igb_init_mas - init Media Autosense feature if enabled in the NVM 3118 * 3119 * @adapter: adapter struct 3120 **/ 3121 static void igb_init_mas(struct igb_adapter *adapter) 3122 { 3123 struct e1000_hw *hw = &adapter->hw; 3124 u16 eeprom_data; 3125 3126 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 3127 switch (hw->bus.func) { 3128 case E1000_FUNC_0: 3129 if (eeprom_data & IGB_MAS_ENABLE_0) { 3130 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3131 netdev_info(adapter->netdev, 3132 "MAS: Enabling Media Autosense for port %d\n", 3133 hw->bus.func); 3134 } 3135 break; 3136 case E1000_FUNC_1: 3137 if (eeprom_data & IGB_MAS_ENABLE_1) { 3138 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3139 netdev_info(adapter->netdev, 3140 "MAS: Enabling Media Autosense for port %d\n", 3141 hw->bus.func); 3142 } 3143 break; 3144 case E1000_FUNC_2: 3145 if (eeprom_data & IGB_MAS_ENABLE_2) { 3146 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3147 netdev_info(adapter->netdev, 3148 "MAS: Enabling Media Autosense for port %d\n", 3149 hw->bus.func); 3150 } 3151 break; 3152 case E1000_FUNC_3: 3153 if (eeprom_data & IGB_MAS_ENABLE_3) { 3154 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3155 netdev_info(adapter->netdev, 3156 "MAS: Enabling Media Autosense for port %d\n", 3157 hw->bus.func); 3158 } 3159 break; 3160 default: 3161 /* Shouldn't get here */ 3162 netdev_err(adapter->netdev, 3163 "MAS: Invalid port configuration, returning\n"); 3164 break; 3165 } 3166 } 3167 3168 /** 3169 * igb_init_i2c - Init I2C interface 3170 * @adapter: pointer to adapter structure 3171 **/ 3172 static s32 igb_init_i2c(struct igb_adapter *adapter) 3173 { 3174 s32 status = 0; 3175 3176 /* I2C interface supported on i350 devices */ 3177 if (adapter->hw.mac.type != e1000_i350) 3178 return 0; 3179 3180 /* Initialize the i2c bus which is controlled by the registers. 3181 * This bus will use the i2c_algo_bit structure that implements 3182 * the protocol through toggling of the 4 bits in the register. 3183 */ 3184 adapter->i2c_adap.owner = THIS_MODULE; 3185 adapter->i2c_algo = igb_i2c_algo; 3186 adapter->i2c_algo.data = adapter; 3187 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 3188 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 3189 strscpy(adapter->i2c_adap.name, "igb BB", 3190 sizeof(adapter->i2c_adap.name)); 3191 status = i2c_bit_add_bus(&adapter->i2c_adap); 3192 return status; 3193 } 3194 3195 /** 3196 * igb_probe - Device Initialization Routine 3197 * @pdev: PCI device information struct 3198 * @ent: entry in igb_pci_tbl 3199 * 3200 * Returns 0 on success, negative on failure 3201 * 3202 * igb_probe initializes an adapter identified by a pci_dev structure. 3203 * The OS initialization, configuring of the adapter private structure, 3204 * and a hardware reset occur. 3205 **/ 3206 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3207 { 3208 struct net_device *netdev; 3209 struct igb_adapter *adapter; 3210 struct e1000_hw *hw; 3211 u16 eeprom_data = 0; 3212 s32 ret_val; 3213 static int global_quad_port_a; /* global quad port a indication */ 3214 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3215 u8 part_str[E1000_PBANUM_LENGTH]; 3216 int err; 3217 3218 /* Catch broken hardware that put the wrong VF device ID in 3219 * the PCIe SR-IOV capability. 3220 */ 3221 if (pdev->is_virtfn) { 3222 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n", 3223 pci_name(pdev), pdev->vendor, pdev->device); 3224 return -EINVAL; 3225 } 3226 3227 err = pci_enable_device_mem(pdev); 3228 if (err) 3229 return err; 3230 3231 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3232 if (err) { 3233 dev_err(&pdev->dev, 3234 "No usable DMA configuration, aborting\n"); 3235 goto err_dma; 3236 } 3237 3238 err = pci_request_mem_regions(pdev, igb_driver_name); 3239 if (err) 3240 goto err_pci_reg; 3241 3242 pci_set_master(pdev); 3243 pci_save_state(pdev); 3244 3245 err = -ENOMEM; 3246 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3247 IGB_MAX_TX_QUEUES); 3248 if (!netdev) 3249 goto err_alloc_etherdev; 3250 3251 SET_NETDEV_DEV(netdev, &pdev->dev); 3252 3253 pci_set_drvdata(pdev, netdev); 3254 adapter = netdev_priv(netdev); 3255 adapter->netdev = netdev; 3256 adapter->pdev = pdev; 3257 hw = &adapter->hw; 3258 hw->back = adapter; 3259 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3260 3261 err = -EIO; 3262 adapter->io_addr = pci_iomap(pdev, 0, 0); 3263 if (!adapter->io_addr) 3264 goto err_ioremap; 3265 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3266 hw->hw_addr = adapter->io_addr; 3267 3268 netdev->netdev_ops = &igb_netdev_ops; 3269 igb_set_ethtool_ops(netdev); 3270 netdev->watchdog_timeo = 5 * HZ; 3271 3272 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 3273 3274 netdev->mem_start = pci_resource_start(pdev, 0); 3275 netdev->mem_end = pci_resource_end(pdev, 0); 3276 3277 /* PCI config space info */ 3278 hw->vendor_id = pdev->vendor; 3279 hw->device_id = pdev->device; 3280 hw->revision_id = pdev->revision; 3281 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3282 hw->subsystem_device_id = pdev->subsystem_device; 3283 3284 /* Copy the default MAC, PHY and NVM function pointers */ 3285 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3286 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3287 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3288 /* Initialize skew-specific constants */ 3289 err = ei->get_invariants(hw); 3290 if (err) 3291 goto err_sw_init; 3292 3293 /* setup the private structure */ 3294 err = igb_sw_init(adapter); 3295 if (err) 3296 goto err_sw_init; 3297 3298 igb_get_bus_info_pcie(hw); 3299 3300 hw->phy.autoneg_wait_to_complete = false; 3301 3302 /* Copper options */ 3303 if (hw->phy.media_type == e1000_media_type_copper) { 3304 hw->phy.mdix = AUTO_ALL_MODES; 3305 hw->phy.disable_polarity_correction = false; 3306 hw->phy.ms_type = e1000_ms_hw_default; 3307 } 3308 3309 if (igb_check_reset_block(hw)) 3310 dev_info(&pdev->dev, 3311 "PHY reset is blocked due to SOL/IDER session.\n"); 3312 3313 /* features is initialized to 0 in allocation, it might have bits 3314 * set by igb_sw_init so we should use an or instead of an 3315 * assignment. 3316 */ 3317 netdev->features |= NETIF_F_SG | 3318 NETIF_F_TSO | 3319 NETIF_F_TSO6 | 3320 NETIF_F_RXHASH | 3321 NETIF_F_RXCSUM | 3322 NETIF_F_HW_CSUM; 3323 3324 if (hw->mac.type >= e1000_82576) 3325 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 3326 3327 if (hw->mac.type >= e1000_i350) 3328 netdev->features |= NETIF_F_HW_TC; 3329 3330 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3331 NETIF_F_GSO_GRE_CSUM | \ 3332 NETIF_F_GSO_IPXIP4 | \ 3333 NETIF_F_GSO_IPXIP6 | \ 3334 NETIF_F_GSO_UDP_TUNNEL | \ 3335 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3336 3337 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3338 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3339 3340 /* copy netdev features into list of user selectable features */ 3341 netdev->hw_features |= netdev->features | 3342 NETIF_F_HW_VLAN_CTAG_RX | 3343 NETIF_F_HW_VLAN_CTAG_TX | 3344 NETIF_F_RXALL; 3345 3346 if (hw->mac.type >= e1000_i350) 3347 netdev->hw_features |= NETIF_F_NTUPLE; 3348 3349 netdev->features |= NETIF_F_HIGHDMA; 3350 3351 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3352 netdev->mpls_features |= NETIF_F_HW_CSUM; 3353 netdev->hw_enc_features |= netdev->vlan_features; 3354 3355 /* set this bit last since it cannot be part of vlan_features */ 3356 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3357 NETIF_F_HW_VLAN_CTAG_RX | 3358 NETIF_F_HW_VLAN_CTAG_TX; 3359 3360 netdev->priv_flags |= IFF_SUPP_NOFCS; 3361 3362 netdev->priv_flags |= IFF_UNICAST_FLT; 3363 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | 3364 NETDEV_XDP_ACT_XSK_ZEROCOPY; 3365 3366 /* MTU range: 68 - 9216 */ 3367 netdev->min_mtu = ETH_MIN_MTU; 3368 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3369 3370 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3371 3372 /* before reading the NVM, reset the controller to put the device in a 3373 * known good starting state 3374 */ 3375 hw->mac.ops.reset_hw(hw); 3376 3377 /* make sure the NVM is good , i211/i210 parts can have special NVM 3378 * that doesn't contain a checksum 3379 */ 3380 switch (hw->mac.type) { 3381 case e1000_i210: 3382 case e1000_i211: 3383 if (igb_get_flash_presence_i210(hw)) { 3384 if (hw->nvm.ops.validate(hw) < 0) { 3385 dev_err(&pdev->dev, 3386 "The NVM Checksum Is Not Valid\n"); 3387 err = -EIO; 3388 goto err_eeprom; 3389 } 3390 } 3391 break; 3392 default: 3393 if (hw->nvm.ops.validate(hw) < 0) { 3394 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3395 err = -EIO; 3396 goto err_eeprom; 3397 } 3398 break; 3399 } 3400 3401 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3402 /* copy the MAC address out of the NVM */ 3403 if (hw->mac.ops.read_mac_addr(hw)) 3404 dev_err(&pdev->dev, "NVM Read Error\n"); 3405 } 3406 3407 eth_hw_addr_set(netdev, hw->mac.addr); 3408 3409 if (!is_valid_ether_addr(netdev->dev_addr)) { 3410 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3411 err = -EIO; 3412 goto err_eeprom; 3413 } 3414 3415 igb_set_default_mac_filter(adapter); 3416 3417 /* get firmware version for ethtool -i */ 3418 igb_set_fw_version(adapter); 3419 3420 /* configure RXPBSIZE and TXPBSIZE */ 3421 if (hw->mac.type == e1000_i210) { 3422 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3423 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3424 } 3425 3426 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3427 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3428 3429 INIT_WORK(&adapter->reset_task, igb_reset_task); 3430 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3431 3432 /* Initialize link properties that are user-changeable */ 3433 adapter->fc_autoneg = true; 3434 hw->mac.autoneg = true; 3435 hw->phy.autoneg_advertised = 0x2f; 3436 3437 hw->fc.requested_mode = e1000_fc_default; 3438 hw->fc.current_mode = e1000_fc_default; 3439 3440 igb_validate_mdi_setting(hw); 3441 3442 /* By default, support wake on port A */ 3443 if (hw->bus.func == 0) 3444 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3445 3446 /* Check the NVM for wake support on non-port A ports */ 3447 if (hw->mac.type >= e1000_82580) 3448 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3449 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3450 &eeprom_data); 3451 else if (hw->bus.func == 1) 3452 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3453 3454 if (eeprom_data & IGB_EEPROM_APME) 3455 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3456 3457 /* now that we have the eeprom settings, apply the special cases where 3458 * the eeprom may be wrong or the board simply won't support wake on 3459 * lan on a particular port 3460 */ 3461 switch (pdev->device) { 3462 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3463 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3464 break; 3465 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3466 case E1000_DEV_ID_82576_FIBER: 3467 case E1000_DEV_ID_82576_SERDES: 3468 /* Wake events only supported on port A for dual fiber 3469 * regardless of eeprom setting 3470 */ 3471 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3472 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3473 break; 3474 case E1000_DEV_ID_82576_QUAD_COPPER: 3475 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3476 /* if quad port adapter, disable WoL on all but port A */ 3477 if (global_quad_port_a != 0) 3478 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3479 else 3480 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3481 /* Reset for multiple quad port adapters */ 3482 if (++global_quad_port_a == 4) 3483 global_quad_port_a = 0; 3484 break; 3485 default: 3486 /* If the device can't wake, don't set software support */ 3487 if (!device_can_wakeup(&adapter->pdev->dev)) 3488 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3489 } 3490 3491 /* initialize the wol settings based on the eeprom settings */ 3492 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3493 adapter->wol |= E1000_WUFC_MAG; 3494 3495 /* Some vendors want WoL disabled by default, but still supported */ 3496 if ((hw->mac.type == e1000_i350) && 3497 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3498 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3499 adapter->wol = 0; 3500 } 3501 3502 /* Some vendors want the ability to Use the EEPROM setting as 3503 * enable/disable only, and not for capability 3504 */ 3505 if (((hw->mac.type == e1000_i350) || 3506 (hw->mac.type == e1000_i354)) && 3507 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3508 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3509 adapter->wol = 0; 3510 } 3511 if (hw->mac.type == e1000_i350) { 3512 if (((pdev->subsystem_device == 0x5001) || 3513 (pdev->subsystem_device == 0x5002)) && 3514 (hw->bus.func == 0)) { 3515 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3516 adapter->wol = 0; 3517 } 3518 if (pdev->subsystem_device == 0x1F52) 3519 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3520 } 3521 3522 device_set_wakeup_enable(&adapter->pdev->dev, 3523 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3524 3525 /* reset the hardware with the new settings */ 3526 igb_reset(adapter); 3527 3528 /* Init the I2C interface */ 3529 err = igb_init_i2c(adapter); 3530 if (err) { 3531 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3532 goto err_eeprom; 3533 } 3534 3535 /* let the f/w know that the h/w is now under the control of the 3536 * driver. 3537 */ 3538 igb_get_hw_control(adapter); 3539 3540 strcpy(netdev->name, "eth%d"); 3541 err = register_netdev(netdev); 3542 if (err) 3543 goto err_register; 3544 3545 /* carrier off reporting is important to ethtool even BEFORE open */ 3546 netif_carrier_off(netdev); 3547 3548 #ifdef CONFIG_IGB_DCA 3549 if (dca_add_requester(&pdev->dev) == 0) { 3550 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3551 dev_info(&pdev->dev, "DCA enabled\n"); 3552 igb_setup_dca(adapter); 3553 } 3554 3555 #endif 3556 #ifdef CONFIG_IGB_HWMON 3557 /* Initialize the thermal sensor on i350 devices. */ 3558 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3559 u16 ets_word; 3560 3561 /* Read the NVM to determine if this i350 device supports an 3562 * external thermal sensor. 3563 */ 3564 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3565 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3566 adapter->ets = true; 3567 else 3568 adapter->ets = false; 3569 /* Only enable I2C bit banging if an external thermal 3570 * sensor is supported. 3571 */ 3572 if (adapter->ets) 3573 igb_set_i2c_bb(hw); 3574 hw->mac.ops.init_thermal_sensor_thresh(hw); 3575 if (igb_sysfs_init(adapter)) 3576 dev_err(&pdev->dev, 3577 "failed to allocate sysfs resources\n"); 3578 } else { 3579 adapter->ets = false; 3580 } 3581 #endif 3582 /* Check if Media Autosense is enabled */ 3583 adapter->ei = *ei; 3584 if (hw->dev_spec._82575.mas_capable) 3585 igb_init_mas(adapter); 3586 3587 /* do hw tstamp init after resetting */ 3588 igb_ptp_init(adapter); 3589 3590 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3591 /* print bus type/speed/width info, not applicable to i354 */ 3592 if (hw->mac.type != e1000_i354) { 3593 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3594 netdev->name, 3595 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3596 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3597 "unknown"), 3598 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3599 "Width x4" : 3600 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3601 "Width x2" : 3602 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3603 "Width x1" : "unknown"), netdev->dev_addr); 3604 } 3605 3606 if ((hw->mac.type == e1000_82576 && 3607 rd32(E1000_EECD) & E1000_EECD_PRES) || 3608 (hw->mac.type >= e1000_i210 || 3609 igb_get_flash_presence_i210(hw))) { 3610 ret_val = igb_read_part_string(hw, part_str, 3611 E1000_PBANUM_LENGTH); 3612 } else { 3613 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3614 } 3615 3616 if (ret_val) 3617 strcpy(part_str, "Unknown"); 3618 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3619 dev_info(&pdev->dev, 3620 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3621 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3622 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3623 adapter->num_rx_queues, adapter->num_tx_queues); 3624 if (hw->phy.media_type == e1000_media_type_copper) { 3625 switch (hw->mac.type) { 3626 case e1000_i350: 3627 case e1000_i210: 3628 case e1000_i211: 3629 /* Enable EEE for internal copper PHY devices */ 3630 err = igb_set_eee_i350(hw, true, true); 3631 if ((!err) && 3632 (!hw->dev_spec._82575.eee_disable)) { 3633 adapter->eee_advert = 3634 MDIO_EEE_100TX | MDIO_EEE_1000T; 3635 adapter->flags |= IGB_FLAG_EEE; 3636 } 3637 break; 3638 case e1000_i354: 3639 if ((rd32(E1000_CTRL_EXT) & 3640 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3641 err = igb_set_eee_i354(hw, true, true); 3642 if ((!err) && 3643 (!hw->dev_spec._82575.eee_disable)) { 3644 adapter->eee_advert = 3645 MDIO_EEE_100TX | MDIO_EEE_1000T; 3646 adapter->flags |= IGB_FLAG_EEE; 3647 } 3648 } 3649 break; 3650 default: 3651 break; 3652 } 3653 } 3654 3655 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 3656 3657 pm_runtime_put_noidle(&pdev->dev); 3658 return 0; 3659 3660 err_register: 3661 igb_release_hw_control(adapter); 3662 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3663 err_eeprom: 3664 if (!igb_check_reset_block(hw)) 3665 igb_reset_phy(hw); 3666 3667 if (hw->flash_address) 3668 iounmap(hw->flash_address); 3669 err_sw_init: 3670 kfree(adapter->mac_table); 3671 kfree(adapter->shadow_vfta); 3672 igb_clear_interrupt_scheme(adapter); 3673 #ifdef CONFIG_PCI_IOV 3674 igb_disable_sriov(pdev, false); 3675 #endif 3676 pci_iounmap(pdev, adapter->io_addr); 3677 err_ioremap: 3678 free_netdev(netdev); 3679 err_alloc_etherdev: 3680 pci_release_mem_regions(pdev); 3681 err_pci_reg: 3682 err_dma: 3683 pci_disable_device(pdev); 3684 return err; 3685 } 3686 3687 #ifdef CONFIG_PCI_IOV 3688 static int igb_sriov_reinit(struct pci_dev *dev) 3689 { 3690 struct net_device *netdev = pci_get_drvdata(dev); 3691 struct igb_adapter *adapter = netdev_priv(netdev); 3692 struct pci_dev *pdev = adapter->pdev; 3693 3694 rtnl_lock(); 3695 3696 if (netif_running(netdev)) 3697 igb_close(netdev); 3698 else 3699 igb_reset(adapter); 3700 3701 igb_clear_interrupt_scheme(adapter); 3702 3703 igb_init_queue_configuration(adapter); 3704 3705 if (igb_init_interrupt_scheme(adapter, true)) { 3706 rtnl_unlock(); 3707 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3708 return -ENOMEM; 3709 } 3710 3711 if (netif_running(netdev)) 3712 igb_open(netdev); 3713 3714 rtnl_unlock(); 3715 3716 return 0; 3717 } 3718 3719 static int igb_disable_sriov(struct pci_dev *pdev, bool reinit) 3720 { 3721 struct net_device *netdev = pci_get_drvdata(pdev); 3722 struct igb_adapter *adapter = netdev_priv(netdev); 3723 struct e1000_hw *hw = &adapter->hw; 3724 unsigned long flags; 3725 3726 /* reclaim resources allocated to VFs */ 3727 if (adapter->vf_data) { 3728 /* disable iov and allow time for transactions to clear */ 3729 if (pci_vfs_assigned(pdev)) { 3730 dev_warn(&pdev->dev, 3731 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3732 return -EPERM; 3733 } else { 3734 pci_disable_sriov(pdev); 3735 msleep(500); 3736 } 3737 spin_lock_irqsave(&adapter->vfs_lock, flags); 3738 kfree(adapter->vf_mac_list); 3739 adapter->vf_mac_list = NULL; 3740 kfree(adapter->vf_data); 3741 adapter->vf_data = NULL; 3742 adapter->vfs_allocated_count = 0; 3743 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 3744 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3745 wrfl(); 3746 msleep(100); 3747 dev_info(&pdev->dev, "IOV Disabled\n"); 3748 3749 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3750 adapter->flags |= IGB_FLAG_DMAC; 3751 } 3752 3753 return reinit ? igb_sriov_reinit(pdev) : 0; 3754 } 3755 3756 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs, bool reinit) 3757 { 3758 struct net_device *netdev = pci_get_drvdata(pdev); 3759 struct igb_adapter *adapter = netdev_priv(netdev); 3760 int old_vfs = pci_num_vf(pdev); 3761 struct vf_mac_filter *mac_list; 3762 int err = 0; 3763 int num_vf_mac_filters, i; 3764 3765 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3766 err = -EPERM; 3767 goto out; 3768 } 3769 if (!num_vfs) 3770 goto out; 3771 3772 if (old_vfs) { 3773 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3774 old_vfs, max_vfs); 3775 adapter->vfs_allocated_count = old_vfs; 3776 } else 3777 adapter->vfs_allocated_count = num_vfs; 3778 3779 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3780 sizeof(struct vf_data_storage), GFP_KERNEL); 3781 3782 /* if allocation failed then we do not support SR-IOV */ 3783 if (!adapter->vf_data) { 3784 adapter->vfs_allocated_count = 0; 3785 err = -ENOMEM; 3786 goto out; 3787 } 3788 3789 /* Due to the limited number of RAR entries calculate potential 3790 * number of MAC filters available for the VFs. Reserve entries 3791 * for PF default MAC, PF MAC filters and at least one RAR entry 3792 * for each VF for VF MAC. 3793 */ 3794 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3795 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3796 adapter->vfs_allocated_count); 3797 3798 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3799 sizeof(struct vf_mac_filter), 3800 GFP_KERNEL); 3801 3802 mac_list = adapter->vf_mac_list; 3803 INIT_LIST_HEAD(&adapter->vf_macs.l); 3804 3805 if (adapter->vf_mac_list) { 3806 /* Initialize list of VF MAC filters */ 3807 for (i = 0; i < num_vf_mac_filters; i++) { 3808 mac_list->vf = -1; 3809 mac_list->free = true; 3810 list_add(&mac_list->l, &adapter->vf_macs.l); 3811 mac_list++; 3812 } 3813 } else { 3814 /* If we could not allocate memory for the VF MAC filters 3815 * we can continue without this feature but warn user. 3816 */ 3817 dev_err(&pdev->dev, 3818 "Unable to allocate memory for VF MAC filter list\n"); 3819 } 3820 3821 dev_info(&pdev->dev, "%d VFs allocated\n", 3822 adapter->vfs_allocated_count); 3823 for (i = 0; i < adapter->vfs_allocated_count; i++) 3824 igb_vf_configure(adapter, i); 3825 3826 /* DMA Coalescing is not supported in IOV mode. */ 3827 adapter->flags &= ~IGB_FLAG_DMAC; 3828 3829 if (reinit) { 3830 err = igb_sriov_reinit(pdev); 3831 if (err) 3832 goto err_out; 3833 } 3834 3835 /* only call pci_enable_sriov() if no VFs are allocated already */ 3836 if (!old_vfs) { 3837 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3838 if (err) 3839 goto err_out; 3840 } 3841 3842 goto out; 3843 3844 err_out: 3845 kfree(adapter->vf_mac_list); 3846 adapter->vf_mac_list = NULL; 3847 kfree(adapter->vf_data); 3848 adapter->vf_data = NULL; 3849 adapter->vfs_allocated_count = 0; 3850 out: 3851 return err; 3852 } 3853 3854 #endif 3855 /** 3856 * igb_remove_i2c - Cleanup I2C interface 3857 * @adapter: pointer to adapter structure 3858 **/ 3859 static void igb_remove_i2c(struct igb_adapter *adapter) 3860 { 3861 /* free the adapter bus structure */ 3862 i2c_del_adapter(&adapter->i2c_adap); 3863 } 3864 3865 /** 3866 * igb_remove - Device Removal Routine 3867 * @pdev: PCI device information struct 3868 * 3869 * igb_remove is called by the PCI subsystem to alert the driver 3870 * that it should release a PCI device. The could be caused by a 3871 * Hot-Plug event, or because the driver is going to be removed from 3872 * memory. 3873 **/ 3874 static void igb_remove(struct pci_dev *pdev) 3875 { 3876 struct net_device *netdev = pci_get_drvdata(pdev); 3877 struct igb_adapter *adapter = netdev_priv(netdev); 3878 struct e1000_hw *hw = &adapter->hw; 3879 3880 pm_runtime_get_noresume(&pdev->dev); 3881 #ifdef CONFIG_IGB_HWMON 3882 igb_sysfs_exit(adapter); 3883 #endif 3884 igb_remove_i2c(adapter); 3885 igb_ptp_stop(adapter); 3886 /* The watchdog timer may be rescheduled, so explicitly 3887 * disable watchdog from being rescheduled. 3888 */ 3889 set_bit(__IGB_DOWN, &adapter->state); 3890 timer_delete_sync(&adapter->watchdog_timer); 3891 timer_delete_sync(&adapter->phy_info_timer); 3892 3893 cancel_work_sync(&adapter->reset_task); 3894 cancel_work_sync(&adapter->watchdog_task); 3895 3896 #ifdef CONFIG_IGB_DCA 3897 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3898 dev_info(&pdev->dev, "DCA disabled\n"); 3899 dca_remove_requester(&pdev->dev); 3900 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3901 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3902 } 3903 #endif 3904 3905 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3906 * would have already happened in close and is redundant. 3907 */ 3908 igb_release_hw_control(adapter); 3909 3910 #ifdef CONFIG_PCI_IOV 3911 igb_disable_sriov(pdev, false); 3912 #endif 3913 3914 unregister_netdev(netdev); 3915 3916 igb_clear_interrupt_scheme(adapter); 3917 3918 pci_iounmap(pdev, adapter->io_addr); 3919 if (hw->flash_address) 3920 iounmap(hw->flash_address); 3921 pci_release_mem_regions(pdev); 3922 3923 kfree(adapter->mac_table); 3924 kfree(adapter->shadow_vfta); 3925 free_netdev(netdev); 3926 3927 pci_disable_device(pdev); 3928 } 3929 3930 /** 3931 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3932 * @adapter: board private structure to initialize 3933 * 3934 * This function initializes the vf specific data storage and then attempts to 3935 * allocate the VFs. The reason for ordering it this way is because it is much 3936 * more expensive time wise to disable SR-IOV than it is to allocate and free 3937 * the memory for the VFs. 3938 **/ 3939 static void igb_probe_vfs(struct igb_adapter *adapter) 3940 { 3941 #ifdef CONFIG_PCI_IOV 3942 struct pci_dev *pdev = adapter->pdev; 3943 struct e1000_hw *hw = &adapter->hw; 3944 3945 /* Virtualization features not supported on i210 and 82580 family. */ 3946 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211) || 3947 (hw->mac.type == e1000_82580)) 3948 return; 3949 3950 /* Of the below we really only want the effect of getting 3951 * IGB_FLAG_HAS_MSIX set (if available), without which 3952 * igb_enable_sriov() has no effect. 3953 */ 3954 igb_set_interrupt_capability(adapter, true); 3955 igb_reset_interrupt_capability(adapter); 3956 3957 pci_sriov_set_totalvfs(pdev, 7); 3958 igb_enable_sriov(pdev, max_vfs, false); 3959 3960 #endif /* CONFIG_PCI_IOV */ 3961 } 3962 3963 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3964 { 3965 struct e1000_hw *hw = &adapter->hw; 3966 unsigned int max_rss_queues; 3967 3968 /* Determine the maximum number of RSS queues supported. */ 3969 switch (hw->mac.type) { 3970 case e1000_i211: 3971 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3972 break; 3973 case e1000_82575: 3974 case e1000_i210: 3975 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3976 break; 3977 case e1000_i350: 3978 /* I350 cannot do RSS and SR-IOV at the same time */ 3979 if (!!adapter->vfs_allocated_count) { 3980 max_rss_queues = 1; 3981 break; 3982 } 3983 fallthrough; 3984 case e1000_82576: 3985 if (!!adapter->vfs_allocated_count) { 3986 max_rss_queues = 2; 3987 break; 3988 } 3989 fallthrough; 3990 case e1000_82580: 3991 case e1000_i354: 3992 default: 3993 max_rss_queues = IGB_MAX_RX_QUEUES; 3994 break; 3995 } 3996 3997 return max_rss_queues; 3998 } 3999 4000 static void igb_init_queue_configuration(struct igb_adapter *adapter) 4001 { 4002 u32 max_rss_queues; 4003 4004 max_rss_queues = igb_get_max_rss_queues(adapter); 4005 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 4006 4007 igb_set_flag_queue_pairs(adapter, max_rss_queues); 4008 } 4009 4010 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 4011 const u32 max_rss_queues) 4012 { 4013 struct e1000_hw *hw = &adapter->hw; 4014 4015 /* Determine if we need to pair queues. */ 4016 switch (hw->mac.type) { 4017 case e1000_82575: 4018 case e1000_i211: 4019 /* Device supports enough interrupts without queue pairing. */ 4020 break; 4021 case e1000_82576: 4022 case e1000_82580: 4023 case e1000_i350: 4024 case e1000_i354: 4025 case e1000_i210: 4026 default: 4027 /* If rss_queues > half of max_rss_queues, pair the queues in 4028 * order to conserve interrupts due to limited supply. 4029 */ 4030 if (adapter->rss_queues > (max_rss_queues / 2)) 4031 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 4032 else 4033 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 4034 break; 4035 } 4036 } 4037 4038 /** 4039 * igb_sw_init - Initialize general software structures (struct igb_adapter) 4040 * @adapter: board private structure to initialize 4041 * 4042 * igb_sw_init initializes the Adapter private data structure. 4043 * Fields are initialized based on PCI device information and 4044 * OS network device settings (MTU size). 4045 **/ 4046 static int igb_sw_init(struct igb_adapter *adapter) 4047 { 4048 struct e1000_hw *hw = &adapter->hw; 4049 struct net_device *netdev = adapter->netdev; 4050 struct pci_dev *pdev = adapter->pdev; 4051 4052 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 4053 4054 /* set default ring sizes */ 4055 adapter->tx_ring_count = IGB_DEFAULT_TXD; 4056 adapter->rx_ring_count = IGB_DEFAULT_RXD; 4057 4058 /* set default ITR values */ 4059 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 4060 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 4061 4062 /* set default work limits */ 4063 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 4064 4065 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD; 4066 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4067 4068 spin_lock_init(&adapter->nfc_lock); 4069 spin_lock_init(&adapter->stats64_lock); 4070 4071 /* init spinlock to avoid concurrency of VF resources */ 4072 spin_lock_init(&adapter->vfs_lock); 4073 #ifdef CONFIG_PCI_IOV 4074 switch (hw->mac.type) { 4075 case e1000_82576: 4076 case e1000_i350: 4077 if (max_vfs > 7) { 4078 dev_warn(&pdev->dev, 4079 "Maximum of 7 VFs per PF, using max\n"); 4080 max_vfs = adapter->vfs_allocated_count = 7; 4081 } else 4082 adapter->vfs_allocated_count = max_vfs; 4083 if (adapter->vfs_allocated_count) 4084 dev_warn(&pdev->dev, 4085 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 4086 break; 4087 default: 4088 break; 4089 } 4090 #endif /* CONFIG_PCI_IOV */ 4091 4092 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 4093 adapter->flags |= IGB_FLAG_HAS_MSIX; 4094 4095 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 4096 sizeof(struct igb_mac_addr), 4097 GFP_KERNEL); 4098 if (!adapter->mac_table) 4099 return -ENOMEM; 4100 4101 igb_probe_vfs(adapter); 4102 4103 igb_init_queue_configuration(adapter); 4104 4105 /* Setup and initialize a copy of the hw vlan table array */ 4106 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 4107 GFP_KERNEL); 4108 if (!adapter->shadow_vfta) 4109 return -ENOMEM; 4110 4111 /* This call may decrease the number of queues */ 4112 if (igb_init_interrupt_scheme(adapter, true)) { 4113 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4114 return -ENOMEM; 4115 } 4116 4117 /* Explicitly disable IRQ since the NIC can be in any state. */ 4118 igb_irq_disable(adapter); 4119 4120 if (hw->mac.type >= e1000_i350) 4121 adapter->flags &= ~IGB_FLAG_DMAC; 4122 4123 set_bit(__IGB_DOWN, &adapter->state); 4124 return 0; 4125 } 4126 4127 /** 4128 * __igb_open - Called when a network interface is made active 4129 * @netdev: network interface device structure 4130 * @resuming: indicates whether we are in a resume call 4131 * 4132 * Returns 0 on success, negative value on failure 4133 * 4134 * The open entry point is called when a network interface is made 4135 * active by the system (IFF_UP). At this point all resources needed 4136 * for transmit and receive operations are allocated, the interrupt 4137 * handler is registered with the OS, the watchdog timer is started, 4138 * and the stack is notified that the interface is ready. 4139 **/ 4140 static int __igb_open(struct net_device *netdev, bool resuming) 4141 { 4142 struct igb_adapter *adapter = netdev_priv(netdev); 4143 struct pci_dev *pdev = adapter->pdev; 4144 struct e1000_hw *hw = &adapter->hw; 4145 struct napi_struct *napi; 4146 int err; 4147 int i; 4148 4149 /* disallow open during test */ 4150 if (test_bit(__IGB_TESTING, &adapter->state)) { 4151 WARN_ON(resuming); 4152 return -EBUSY; 4153 } 4154 4155 if (!resuming) 4156 pm_runtime_get_sync(&pdev->dev); 4157 4158 netif_carrier_off(netdev); 4159 4160 /* allocate transmit descriptors */ 4161 err = igb_setup_all_tx_resources(adapter); 4162 if (err) 4163 goto err_setup_tx; 4164 4165 /* allocate receive descriptors */ 4166 err = igb_setup_all_rx_resources(adapter); 4167 if (err) 4168 goto err_setup_rx; 4169 4170 igb_power_up_link(adapter); 4171 4172 /* before we allocate an interrupt, we must be ready to handle it. 4173 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4174 * as soon as we call pci_request_irq, so we have to setup our 4175 * clean_rx handler before we do so. 4176 */ 4177 igb_configure(adapter); 4178 4179 err = igb_request_irq(adapter); 4180 if (err) 4181 goto err_req_irq; 4182 4183 /* Notify the stack of the actual queue counts. */ 4184 err = netif_set_real_num_tx_queues(adapter->netdev, 4185 adapter->num_tx_queues); 4186 if (err) 4187 goto err_set_queues; 4188 4189 err = netif_set_real_num_rx_queues(adapter->netdev, 4190 adapter->num_rx_queues); 4191 if (err) 4192 goto err_set_queues; 4193 4194 /* From here on the code is the same as igb_up() */ 4195 clear_bit(__IGB_DOWN, &adapter->state); 4196 4197 for (i = 0; i < adapter->num_q_vectors; i++) { 4198 napi = &adapter->q_vector[i]->napi; 4199 napi_enable(napi); 4200 igb_set_queue_napi(adapter, i, napi); 4201 } 4202 4203 /* Clear any pending interrupts. */ 4204 rd32(E1000_TSICR); 4205 rd32(E1000_ICR); 4206 4207 igb_irq_enable(adapter); 4208 4209 /* notify VFs that reset has been completed */ 4210 if (adapter->vfs_allocated_count) { 4211 u32 reg_data = rd32(E1000_CTRL_EXT); 4212 4213 reg_data |= E1000_CTRL_EXT_PFRSTD; 4214 wr32(E1000_CTRL_EXT, reg_data); 4215 } 4216 4217 netif_tx_start_all_queues(netdev); 4218 4219 if (!resuming) 4220 pm_runtime_put(&pdev->dev); 4221 4222 /* start the watchdog. */ 4223 hw->mac.get_link_status = 1; 4224 schedule_work(&adapter->watchdog_task); 4225 4226 return 0; 4227 4228 err_set_queues: 4229 igb_free_irq(adapter); 4230 err_req_irq: 4231 igb_release_hw_control(adapter); 4232 igb_power_down_link(adapter); 4233 igb_free_all_rx_resources(adapter); 4234 err_setup_rx: 4235 igb_free_all_tx_resources(adapter); 4236 err_setup_tx: 4237 igb_reset(adapter); 4238 if (!resuming) 4239 pm_runtime_put(&pdev->dev); 4240 4241 return err; 4242 } 4243 4244 int igb_open(struct net_device *netdev) 4245 { 4246 return __igb_open(netdev, false); 4247 } 4248 4249 /** 4250 * __igb_close - Disables a network interface 4251 * @netdev: network interface device structure 4252 * @suspending: indicates we are in a suspend call 4253 * 4254 * Returns 0, this is not allowed to fail 4255 * 4256 * The close entry point is called when an interface is de-activated 4257 * by the OS. The hardware is still under the driver's control, but 4258 * needs to be disabled. A global MAC reset is issued to stop the 4259 * hardware, and all transmit and receive resources are freed. 4260 **/ 4261 static int __igb_close(struct net_device *netdev, bool suspending) 4262 { 4263 struct igb_adapter *adapter = netdev_priv(netdev); 4264 struct pci_dev *pdev = adapter->pdev; 4265 4266 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4267 4268 if (!suspending) 4269 pm_runtime_get_sync(&pdev->dev); 4270 4271 igb_down(adapter); 4272 igb_free_irq(adapter); 4273 4274 igb_free_all_tx_resources(adapter); 4275 igb_free_all_rx_resources(adapter); 4276 4277 if (!suspending) 4278 pm_runtime_put_sync(&pdev->dev); 4279 return 0; 4280 } 4281 4282 int igb_close(struct net_device *netdev) 4283 { 4284 if (netif_device_present(netdev) || netdev->dismantle) 4285 return __igb_close(netdev, false); 4286 return 0; 4287 } 4288 4289 /** 4290 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4291 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4292 * 4293 * Return 0 on success, negative on failure 4294 **/ 4295 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4296 { 4297 struct device *dev = tx_ring->dev; 4298 int size; 4299 4300 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4301 4302 tx_ring->tx_buffer_info = vmalloc(size); 4303 if (!tx_ring->tx_buffer_info) 4304 goto err; 4305 4306 /* round up to nearest 4K */ 4307 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4308 tx_ring->size = ALIGN(tx_ring->size, 4096); 4309 4310 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4311 &tx_ring->dma, GFP_KERNEL); 4312 if (!tx_ring->desc) 4313 goto err; 4314 4315 tx_ring->next_to_use = 0; 4316 tx_ring->next_to_clean = 0; 4317 4318 return 0; 4319 4320 err: 4321 vfree(tx_ring->tx_buffer_info); 4322 tx_ring->tx_buffer_info = NULL; 4323 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4324 return -ENOMEM; 4325 } 4326 4327 /** 4328 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4329 * (Descriptors) for all queues 4330 * @adapter: board private structure 4331 * 4332 * Return 0 on success, negative on failure 4333 **/ 4334 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4335 { 4336 struct pci_dev *pdev = adapter->pdev; 4337 int i, err = 0; 4338 4339 for (i = 0; i < adapter->num_tx_queues; i++) { 4340 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4341 if (err) { 4342 dev_err(&pdev->dev, 4343 "Allocation for Tx Queue %u failed\n", i); 4344 for (i--; i >= 0; i--) 4345 igb_free_tx_resources(adapter->tx_ring[i]); 4346 break; 4347 } 4348 } 4349 4350 return err; 4351 } 4352 4353 /** 4354 * igb_setup_tctl - configure the transmit control registers 4355 * @adapter: Board private structure 4356 **/ 4357 void igb_setup_tctl(struct igb_adapter *adapter) 4358 { 4359 struct e1000_hw *hw = &adapter->hw; 4360 u32 tctl; 4361 4362 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4363 wr32(E1000_TXDCTL(0), 0); 4364 4365 /* Program the Transmit Control Register */ 4366 tctl = rd32(E1000_TCTL); 4367 tctl &= ~E1000_TCTL_CT; 4368 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4369 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4370 4371 igb_config_collision_dist(hw); 4372 4373 /* Enable transmits */ 4374 tctl |= E1000_TCTL_EN; 4375 4376 wr32(E1000_TCTL, tctl); 4377 } 4378 4379 /** 4380 * igb_configure_tx_ring - Configure transmit ring after Reset 4381 * @adapter: board private structure 4382 * @ring: tx ring to configure 4383 * 4384 * Configure a transmit ring after a reset. 4385 **/ 4386 void igb_configure_tx_ring(struct igb_adapter *adapter, 4387 struct igb_ring *ring) 4388 { 4389 struct e1000_hw *hw = &adapter->hw; 4390 u32 txdctl = 0; 4391 u64 tdba = ring->dma; 4392 int reg_idx = ring->reg_idx; 4393 4394 WRITE_ONCE(ring->xsk_pool, igb_xsk_pool(adapter, ring)); 4395 4396 wr32(E1000_TDLEN(reg_idx), 4397 ring->count * sizeof(union e1000_adv_tx_desc)); 4398 wr32(E1000_TDBAL(reg_idx), 4399 tdba & 0x00000000ffffffffULL); 4400 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4401 4402 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4403 wr32(E1000_TDH(reg_idx), 0); 4404 writel(0, ring->tail); 4405 4406 txdctl |= IGB_TX_PTHRESH; 4407 txdctl |= IGB_TX_HTHRESH << 8; 4408 txdctl |= IGB_TX_WTHRESH << 16; 4409 4410 /* reinitialize tx_buffer_info */ 4411 memset(ring->tx_buffer_info, 0, 4412 sizeof(struct igb_tx_buffer) * ring->count); 4413 4414 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4415 wr32(E1000_TXDCTL(reg_idx), txdctl); 4416 } 4417 4418 /** 4419 * igb_configure_tx - Configure transmit Unit after Reset 4420 * @adapter: board private structure 4421 * 4422 * Configure the Tx unit of the MAC after a reset. 4423 **/ 4424 static void igb_configure_tx(struct igb_adapter *adapter) 4425 { 4426 struct e1000_hw *hw = &adapter->hw; 4427 int i; 4428 4429 /* disable the queues */ 4430 for (i = 0; i < adapter->num_tx_queues; i++) 4431 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4432 4433 wrfl(); 4434 usleep_range(10000, 20000); 4435 4436 for (i = 0; i < adapter->num_tx_queues; i++) 4437 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4438 } 4439 4440 /** 4441 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4442 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4443 * 4444 * Returns 0 on success, negative on failure 4445 **/ 4446 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4447 { 4448 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev); 4449 struct device *dev = rx_ring->dev; 4450 int size, res; 4451 4452 /* XDP RX-queue info */ 4453 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq)) 4454 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4455 res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 4456 rx_ring->queue_index, 0); 4457 if (res < 0) { 4458 dev_err(dev, "Failed to register xdp_rxq index %u\n", 4459 rx_ring->queue_index); 4460 return res; 4461 } 4462 4463 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4464 4465 rx_ring->rx_buffer_info = vmalloc(size); 4466 if (!rx_ring->rx_buffer_info) 4467 goto err; 4468 4469 /* Round up to nearest 4K */ 4470 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4471 rx_ring->size = ALIGN(rx_ring->size, 4096); 4472 4473 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4474 &rx_ring->dma, GFP_KERNEL); 4475 if (!rx_ring->desc) 4476 goto err; 4477 4478 rx_ring->next_to_alloc = 0; 4479 rx_ring->next_to_clean = 0; 4480 rx_ring->next_to_use = 0; 4481 4482 rx_ring->xdp_prog = adapter->xdp_prog; 4483 4484 return 0; 4485 4486 err: 4487 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4488 vfree(rx_ring->rx_buffer_info); 4489 rx_ring->rx_buffer_info = NULL; 4490 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4491 return -ENOMEM; 4492 } 4493 4494 /** 4495 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4496 * (Descriptors) for all queues 4497 * @adapter: board private structure 4498 * 4499 * Return 0 on success, negative on failure 4500 **/ 4501 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4502 { 4503 struct pci_dev *pdev = adapter->pdev; 4504 int i, err = 0; 4505 4506 for (i = 0; i < adapter->num_rx_queues; i++) { 4507 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4508 if (err) { 4509 dev_err(&pdev->dev, 4510 "Allocation for Rx Queue %u failed\n", i); 4511 for (i--; i >= 0; i--) 4512 igb_free_rx_resources(adapter->rx_ring[i]); 4513 break; 4514 } 4515 } 4516 4517 return err; 4518 } 4519 4520 /** 4521 * igb_setup_mrqc - configure the multiple receive queue control registers 4522 * @adapter: Board private structure 4523 **/ 4524 static void igb_setup_mrqc(struct igb_adapter *adapter) 4525 { 4526 struct e1000_hw *hw = &adapter->hw; 4527 u32 mrqc, rxcsum; 4528 u32 j, num_rx_queues; 4529 u32 rss_key[10]; 4530 4531 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4532 for (j = 0; j < 10; j++) 4533 wr32(E1000_RSSRK(j), rss_key[j]); 4534 4535 num_rx_queues = adapter->rss_queues; 4536 4537 switch (hw->mac.type) { 4538 case e1000_82576: 4539 /* 82576 supports 2 RSS queues for SR-IOV */ 4540 if (adapter->vfs_allocated_count) 4541 num_rx_queues = 2; 4542 break; 4543 default: 4544 break; 4545 } 4546 4547 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4548 for (j = 0; j < IGB_RETA_SIZE; j++) 4549 adapter->rss_indir_tbl[j] = 4550 (j * num_rx_queues) / IGB_RETA_SIZE; 4551 adapter->rss_indir_tbl_init = num_rx_queues; 4552 } 4553 igb_write_rss_indir_tbl(adapter); 4554 4555 /* Disable raw packet checksumming so that RSS hash is placed in 4556 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4557 * offloads as they are enabled by default 4558 */ 4559 rxcsum = rd32(E1000_RXCSUM); 4560 rxcsum |= E1000_RXCSUM_PCSD; 4561 4562 if (adapter->hw.mac.type >= e1000_82576) 4563 /* Enable Receive Checksum Offload for SCTP */ 4564 rxcsum |= E1000_RXCSUM_CRCOFL; 4565 4566 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4567 wr32(E1000_RXCSUM, rxcsum); 4568 4569 /* Generate RSS hash based on packet types, TCP/UDP 4570 * port numbers and/or IPv4/v6 src and dst addresses 4571 */ 4572 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4573 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4574 E1000_MRQC_RSS_FIELD_IPV6 | 4575 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4576 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4577 4578 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4579 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4580 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4581 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4582 4583 /* If VMDq is enabled then we set the appropriate mode for that, else 4584 * we default to RSS so that an RSS hash is calculated per packet even 4585 * if we are only using one queue 4586 */ 4587 if (adapter->vfs_allocated_count) { 4588 if (hw->mac.type > e1000_82575) { 4589 /* Set the default pool for the PF's first queue */ 4590 u32 vtctl = rd32(E1000_VT_CTL); 4591 4592 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4593 E1000_VT_CTL_DISABLE_DEF_POOL); 4594 vtctl |= adapter->vfs_allocated_count << 4595 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4596 wr32(E1000_VT_CTL, vtctl); 4597 } 4598 if (adapter->rss_queues > 1) 4599 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4600 else 4601 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4602 } else { 4603 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4604 } 4605 igb_vmm_control(adapter); 4606 4607 wr32(E1000_MRQC, mrqc); 4608 } 4609 4610 /** 4611 * igb_setup_rctl - configure the receive control registers 4612 * @adapter: Board private structure 4613 **/ 4614 void igb_setup_rctl(struct igb_adapter *adapter) 4615 { 4616 struct e1000_hw *hw = &adapter->hw; 4617 u32 rctl; 4618 4619 rctl = rd32(E1000_RCTL); 4620 4621 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4622 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4623 4624 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4625 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4626 4627 /* enable stripping of CRC. It's unlikely this will break BMC 4628 * redirection as it did with e1000. Newer features require 4629 * that the HW strips the CRC. 4630 */ 4631 rctl |= E1000_RCTL_SECRC; 4632 4633 /* disable store bad packets and clear size bits. */ 4634 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4635 4636 /* enable LPE to allow for reception of jumbo frames */ 4637 rctl |= E1000_RCTL_LPE; 4638 4639 /* disable queue 0 to prevent tail write w/o re-config */ 4640 wr32(E1000_RXDCTL(0), 0); 4641 4642 /* Attention!!! For SR-IOV PF driver operations you must enable 4643 * queue drop for all VF and PF queues to prevent head of line blocking 4644 * if an un-trusted VF does not provide descriptors to hardware. 4645 */ 4646 if (adapter->vfs_allocated_count) { 4647 /* set all queue drop enable bits */ 4648 wr32(E1000_QDE, ALL_QUEUES); 4649 } 4650 4651 /* This is useful for sniffing bad packets. */ 4652 if (adapter->netdev->features & NETIF_F_RXALL) { 4653 /* UPE and MPE will be handled by normal PROMISC logic 4654 * in e1000e_set_rx_mode 4655 */ 4656 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4657 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4658 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4659 4660 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4661 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4662 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4663 * and that breaks VLANs. 4664 */ 4665 } 4666 4667 wr32(E1000_RCTL, rctl); 4668 } 4669 4670 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4671 int vfn) 4672 { 4673 struct e1000_hw *hw = &adapter->hw; 4674 u32 vmolr; 4675 4676 if (size > MAX_JUMBO_FRAME_SIZE) 4677 size = MAX_JUMBO_FRAME_SIZE; 4678 4679 vmolr = rd32(E1000_VMOLR(vfn)); 4680 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4681 vmolr |= size | E1000_VMOLR_LPE; 4682 wr32(E1000_VMOLR(vfn), vmolr); 4683 4684 return 0; 4685 } 4686 4687 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4688 int vfn, bool enable) 4689 { 4690 struct e1000_hw *hw = &adapter->hw; 4691 u32 val, reg; 4692 4693 if (hw->mac.type < e1000_82576) 4694 return; 4695 4696 if (hw->mac.type == e1000_i350) 4697 reg = E1000_DVMOLR(vfn); 4698 else 4699 reg = E1000_VMOLR(vfn); 4700 4701 val = rd32(reg); 4702 if (enable) 4703 val |= E1000_VMOLR_STRVLAN; 4704 else 4705 val &= ~(E1000_VMOLR_STRVLAN); 4706 wr32(reg, val); 4707 } 4708 4709 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4710 int vfn, bool aupe) 4711 { 4712 struct e1000_hw *hw = &adapter->hw; 4713 u32 vmolr; 4714 4715 /* This register exists only on 82576 and newer so if we are older then 4716 * we should exit and do nothing 4717 */ 4718 if (hw->mac.type < e1000_82576) 4719 return; 4720 4721 vmolr = rd32(E1000_VMOLR(vfn)); 4722 if (aupe) 4723 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4724 else 4725 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4726 4727 /* clear all bits that might not be set */ 4728 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4729 4730 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4731 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4732 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4733 * multicast packets 4734 */ 4735 if (vfn <= adapter->vfs_allocated_count) 4736 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4737 4738 wr32(E1000_VMOLR(vfn), vmolr); 4739 } 4740 4741 /** 4742 * igb_setup_srrctl - configure the split and replication receive control 4743 * registers 4744 * @adapter: Board private structure 4745 * @ring: receive ring to be configured 4746 **/ 4747 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring) 4748 { 4749 struct e1000_hw *hw = &adapter->hw; 4750 int reg_idx = ring->reg_idx; 4751 u32 srrctl = 0; 4752 u32 buf_size; 4753 4754 if (ring->xsk_pool) 4755 buf_size = xsk_pool_get_rx_frame_size(ring->xsk_pool); 4756 else if (ring_uses_large_buffer(ring)) 4757 buf_size = IGB_RXBUFFER_3072; 4758 else 4759 buf_size = IGB_RXBUFFER_2048; 4760 4761 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4762 srrctl |= buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4763 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4764 if (hw->mac.type >= e1000_82580) 4765 srrctl |= E1000_SRRCTL_TIMESTAMP; 4766 /* Only set Drop Enable if VFs allocated, or we are supporting multiple 4767 * queues and rx flow control is disabled 4768 */ 4769 if (adapter->vfs_allocated_count || 4770 (!(hw->fc.current_mode & e1000_fc_rx_pause) && 4771 adapter->num_rx_queues > 1)) 4772 srrctl |= E1000_SRRCTL_DROP_EN; 4773 4774 wr32(E1000_SRRCTL(reg_idx), srrctl); 4775 } 4776 4777 /** 4778 * igb_configure_rx_ring - Configure a receive ring after Reset 4779 * @adapter: board private structure 4780 * @ring: receive ring to be configured 4781 * 4782 * Configure the Rx unit of the MAC after a reset. 4783 **/ 4784 void igb_configure_rx_ring(struct igb_adapter *adapter, 4785 struct igb_ring *ring) 4786 { 4787 struct e1000_hw *hw = &adapter->hw; 4788 union e1000_adv_rx_desc *rx_desc; 4789 u64 rdba = ring->dma; 4790 int reg_idx = ring->reg_idx; 4791 u32 rxdctl = 0; 4792 4793 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4794 WRITE_ONCE(ring->xsk_pool, igb_xsk_pool(adapter, ring)); 4795 if (ring->xsk_pool) { 4796 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4797 MEM_TYPE_XSK_BUFF_POOL, 4798 NULL)); 4799 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq); 4800 } else { 4801 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4802 MEM_TYPE_PAGE_SHARED, 4803 NULL)); 4804 } 4805 4806 /* disable the queue */ 4807 wr32(E1000_RXDCTL(reg_idx), 0); 4808 4809 /* Set DMA base address registers */ 4810 wr32(E1000_RDBAL(reg_idx), 4811 rdba & 0x00000000ffffffffULL); 4812 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4813 wr32(E1000_RDLEN(reg_idx), 4814 ring->count * sizeof(union e1000_adv_rx_desc)); 4815 4816 /* initialize head and tail */ 4817 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4818 wr32(E1000_RDH(reg_idx), 0); 4819 writel(0, ring->tail); 4820 4821 /* set descriptor configuration */ 4822 igb_setup_srrctl(adapter, ring); 4823 4824 /* set filtering for VMDQ pools */ 4825 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4826 4827 rxdctl |= IGB_RX_PTHRESH; 4828 rxdctl |= IGB_RX_HTHRESH << 8; 4829 rxdctl |= IGB_RX_WTHRESH << 16; 4830 4831 if (ring->xsk_pool) 4832 memset(ring->rx_buffer_info_zc, 0, 4833 sizeof(*ring->rx_buffer_info_zc) * ring->count); 4834 else 4835 memset(ring->rx_buffer_info, 0, 4836 sizeof(*ring->rx_buffer_info) * ring->count); 4837 4838 /* initialize Rx descriptor 0 */ 4839 rx_desc = IGB_RX_DESC(ring, 0); 4840 rx_desc->wb.upper.length = 0; 4841 4842 /* enable receive descriptor fetching */ 4843 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4844 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4845 } 4846 4847 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4848 struct igb_ring *rx_ring) 4849 { 4850 #if (PAGE_SIZE < 8192) 4851 struct e1000_hw *hw = &adapter->hw; 4852 #endif 4853 4854 /* set build_skb and buffer size flags */ 4855 clear_ring_build_skb_enabled(rx_ring); 4856 clear_ring_uses_large_buffer(rx_ring); 4857 4858 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4859 return; 4860 4861 set_ring_build_skb_enabled(rx_ring); 4862 4863 #if (PAGE_SIZE < 8192) 4864 if (adapter->max_frame_size > IGB_MAX_FRAME_BUILD_SKB || 4865 IGB_2K_TOO_SMALL_WITH_PADDING || 4866 rd32(E1000_RCTL) & E1000_RCTL_SBP) 4867 set_ring_uses_large_buffer(rx_ring); 4868 #endif 4869 } 4870 4871 /** 4872 * igb_configure_rx - Configure receive Unit after Reset 4873 * @adapter: board private structure 4874 * 4875 * Configure the Rx unit of the MAC after a reset. 4876 **/ 4877 static void igb_configure_rx(struct igb_adapter *adapter) 4878 { 4879 int i; 4880 4881 /* set the correct pool for the PF default MAC address in entry 0 */ 4882 igb_set_default_mac_filter(adapter); 4883 4884 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4885 * the Base and Length of the Rx Descriptor Ring 4886 */ 4887 for (i = 0; i < adapter->num_rx_queues; i++) { 4888 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4889 4890 igb_set_rx_buffer_len(adapter, rx_ring); 4891 igb_configure_rx_ring(adapter, rx_ring); 4892 } 4893 } 4894 4895 /** 4896 * igb_free_tx_resources - Free Tx Resources per Queue 4897 * @tx_ring: Tx descriptor ring for a specific queue 4898 * 4899 * Free all transmit software resources 4900 **/ 4901 void igb_free_tx_resources(struct igb_ring *tx_ring) 4902 { 4903 igb_clean_tx_ring(tx_ring); 4904 4905 vfree(tx_ring->tx_buffer_info); 4906 tx_ring->tx_buffer_info = NULL; 4907 4908 /* if not set, then don't free */ 4909 if (!tx_ring->desc) 4910 return; 4911 4912 dma_free_coherent(tx_ring->dev, tx_ring->size, 4913 tx_ring->desc, tx_ring->dma); 4914 4915 tx_ring->desc = NULL; 4916 } 4917 4918 /** 4919 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4920 * @adapter: board private structure 4921 * 4922 * Free all transmit software resources 4923 **/ 4924 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4925 { 4926 int i; 4927 4928 for (i = 0; i < adapter->num_tx_queues; i++) 4929 if (adapter->tx_ring[i]) 4930 igb_free_tx_resources(adapter->tx_ring[i]); 4931 } 4932 4933 /** 4934 * igb_clean_tx_ring - Free Tx Buffers 4935 * @tx_ring: ring to be cleaned 4936 **/ 4937 void igb_clean_tx_ring(struct igb_ring *tx_ring) 4938 { 4939 u16 i = tx_ring->next_to_clean; 4940 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4941 u32 xsk_frames = 0; 4942 4943 while (i != tx_ring->next_to_use) { 4944 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4945 4946 /* Free all the Tx ring sk_buffs or xdp frames */ 4947 if (tx_buffer->type == IGB_TYPE_SKB) { 4948 dev_kfree_skb_any(tx_buffer->skb); 4949 } else if (tx_buffer->type == IGB_TYPE_XDP) { 4950 xdp_return_frame(tx_buffer->xdpf); 4951 } else if (tx_buffer->type == IGB_TYPE_XSK) { 4952 xsk_frames++; 4953 goto skip_for_xsk; 4954 } 4955 4956 /* unmap skb header data */ 4957 dma_unmap_single(tx_ring->dev, 4958 dma_unmap_addr(tx_buffer, dma), 4959 dma_unmap_len(tx_buffer, len), 4960 DMA_TO_DEVICE); 4961 4962 /* check for eop_desc to determine the end of the packet */ 4963 eop_desc = tx_buffer->next_to_watch; 4964 tx_desc = IGB_TX_DESC(tx_ring, i); 4965 4966 /* unmap remaining buffers */ 4967 while (tx_desc != eop_desc) { 4968 tx_buffer++; 4969 tx_desc++; 4970 i++; 4971 if (unlikely(i == tx_ring->count)) { 4972 i = 0; 4973 tx_buffer = tx_ring->tx_buffer_info; 4974 tx_desc = IGB_TX_DESC(tx_ring, 0); 4975 } 4976 4977 /* unmap any remaining paged data */ 4978 if (dma_unmap_len(tx_buffer, len)) 4979 dma_unmap_page(tx_ring->dev, 4980 dma_unmap_addr(tx_buffer, dma), 4981 dma_unmap_len(tx_buffer, len), 4982 DMA_TO_DEVICE); 4983 } 4984 4985 skip_for_xsk: 4986 tx_buffer->next_to_watch = NULL; 4987 4988 /* move us one more past the eop_desc for start of next pkt */ 4989 tx_buffer++; 4990 i++; 4991 if (unlikely(i == tx_ring->count)) { 4992 i = 0; 4993 tx_buffer = tx_ring->tx_buffer_info; 4994 } 4995 } 4996 4997 /* reset BQL for queue */ 4998 netdev_tx_reset_queue(txring_txq(tx_ring)); 4999 5000 if (tx_ring->xsk_pool && xsk_frames) 5001 xsk_tx_completed(tx_ring->xsk_pool, xsk_frames); 5002 5003 /* reset next_to_use and next_to_clean */ 5004 tx_ring->next_to_use = 0; 5005 tx_ring->next_to_clean = 0; 5006 } 5007 5008 /** 5009 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 5010 * @adapter: board private structure 5011 **/ 5012 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 5013 { 5014 int i; 5015 5016 for (i = 0; i < adapter->num_tx_queues; i++) 5017 if (adapter->tx_ring[i]) 5018 igb_clean_tx_ring(adapter->tx_ring[i]); 5019 } 5020 5021 /** 5022 * igb_free_rx_resources - Free Rx Resources 5023 * @rx_ring: ring to clean the resources from 5024 * 5025 * Free all receive software resources 5026 **/ 5027 void igb_free_rx_resources(struct igb_ring *rx_ring) 5028 { 5029 igb_clean_rx_ring(rx_ring); 5030 5031 rx_ring->xdp_prog = NULL; 5032 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 5033 if (rx_ring->xsk_pool) { 5034 vfree(rx_ring->rx_buffer_info_zc); 5035 rx_ring->rx_buffer_info_zc = NULL; 5036 } else { 5037 vfree(rx_ring->rx_buffer_info); 5038 rx_ring->rx_buffer_info = NULL; 5039 } 5040 5041 /* if not set, then don't free */ 5042 if (!rx_ring->desc) 5043 return; 5044 5045 dma_free_coherent(rx_ring->dev, rx_ring->size, 5046 rx_ring->desc, rx_ring->dma); 5047 5048 rx_ring->desc = NULL; 5049 } 5050 5051 /** 5052 * igb_free_all_rx_resources - Free Rx Resources for All Queues 5053 * @adapter: board private structure 5054 * 5055 * Free all receive software resources 5056 **/ 5057 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 5058 { 5059 int i; 5060 5061 for (i = 0; i < adapter->num_rx_queues; i++) 5062 if (adapter->rx_ring[i]) 5063 igb_free_rx_resources(adapter->rx_ring[i]); 5064 } 5065 5066 /** 5067 * igb_clean_rx_ring - Free Rx Buffers per Queue 5068 * @rx_ring: ring to free buffers from 5069 **/ 5070 void igb_clean_rx_ring(struct igb_ring *rx_ring) 5071 { 5072 u16 i = rx_ring->next_to_clean; 5073 5074 dev_kfree_skb(rx_ring->skb); 5075 rx_ring->skb = NULL; 5076 5077 if (rx_ring->xsk_pool) { 5078 igb_clean_rx_ring_zc(rx_ring); 5079 goto skip_for_xsk; 5080 } 5081 5082 /* Free all the Rx ring sk_buffs */ 5083 while (i != rx_ring->next_to_alloc) { 5084 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 5085 5086 /* Invalidate cache lines that may have been written to by 5087 * device so that we avoid corrupting memory. 5088 */ 5089 dma_sync_single_range_for_cpu(rx_ring->dev, 5090 buffer_info->dma, 5091 buffer_info->page_offset, 5092 igb_rx_bufsz(rx_ring), 5093 DMA_FROM_DEVICE); 5094 5095 /* free resources associated with mapping */ 5096 dma_unmap_page_attrs(rx_ring->dev, 5097 buffer_info->dma, 5098 igb_rx_pg_size(rx_ring), 5099 DMA_FROM_DEVICE, 5100 IGB_RX_DMA_ATTR); 5101 __page_frag_cache_drain(buffer_info->page, 5102 buffer_info->pagecnt_bias); 5103 5104 i++; 5105 if (i == rx_ring->count) 5106 i = 0; 5107 } 5108 5109 skip_for_xsk: 5110 rx_ring->next_to_alloc = 0; 5111 rx_ring->next_to_clean = 0; 5112 rx_ring->next_to_use = 0; 5113 } 5114 5115 /** 5116 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 5117 * @adapter: board private structure 5118 **/ 5119 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 5120 { 5121 int i; 5122 5123 for (i = 0; i < adapter->num_rx_queues; i++) 5124 if (adapter->rx_ring[i]) 5125 igb_clean_rx_ring(adapter->rx_ring[i]); 5126 } 5127 5128 /** 5129 * igb_set_mac - Change the Ethernet Address of the NIC 5130 * @netdev: network interface device structure 5131 * @p: pointer to an address structure 5132 * 5133 * Returns 0 on success, negative on failure 5134 **/ 5135 static int igb_set_mac(struct net_device *netdev, void *p) 5136 { 5137 struct igb_adapter *adapter = netdev_priv(netdev); 5138 struct e1000_hw *hw = &adapter->hw; 5139 struct sockaddr *addr = p; 5140 5141 if (!is_valid_ether_addr(addr->sa_data)) 5142 return -EADDRNOTAVAIL; 5143 5144 eth_hw_addr_set(netdev, addr->sa_data); 5145 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 5146 5147 /* set the correct pool for the new PF MAC address in entry 0 */ 5148 igb_set_default_mac_filter(adapter); 5149 5150 return 0; 5151 } 5152 5153 /** 5154 * igb_write_mc_addr_list - write multicast addresses to MTA 5155 * @netdev: network interface device structure 5156 * 5157 * Writes multicast address list to the MTA hash table. 5158 * Returns: -ENOMEM on failure 5159 * 0 on no addresses written 5160 * X on writing X addresses to MTA 5161 **/ 5162 static int igb_write_mc_addr_list(struct net_device *netdev) 5163 { 5164 struct igb_adapter *adapter = netdev_priv(netdev); 5165 struct e1000_hw *hw = &adapter->hw; 5166 struct netdev_hw_addr *ha; 5167 u8 *mta_list; 5168 int i; 5169 5170 if (netdev_mc_empty(netdev)) { 5171 /* nothing to program, so clear mc list */ 5172 igb_update_mc_addr_list(hw, NULL, 0); 5173 igb_restore_vf_multicasts(adapter); 5174 return 0; 5175 } 5176 5177 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 5178 if (!mta_list) 5179 return -ENOMEM; 5180 5181 /* The shared function expects a packed array of only addresses. */ 5182 i = 0; 5183 netdev_for_each_mc_addr(ha, netdev) 5184 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 5185 5186 igb_update_mc_addr_list(hw, mta_list, i); 5187 kfree(mta_list); 5188 5189 return netdev_mc_count(netdev); 5190 } 5191 5192 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 5193 { 5194 struct e1000_hw *hw = &adapter->hw; 5195 u32 i, pf_id; 5196 5197 switch (hw->mac.type) { 5198 case e1000_i210: 5199 case e1000_i211: 5200 case e1000_i350: 5201 /* VLAN filtering needed for VLAN prio filter */ 5202 if (adapter->netdev->features & NETIF_F_NTUPLE) 5203 break; 5204 fallthrough; 5205 case e1000_82576: 5206 case e1000_82580: 5207 case e1000_i354: 5208 /* VLAN filtering needed for pool filtering */ 5209 if (adapter->vfs_allocated_count) 5210 break; 5211 fallthrough; 5212 default: 5213 return 1; 5214 } 5215 5216 /* We are already in VLAN promisc, nothing to do */ 5217 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 5218 return 0; 5219 5220 if (!adapter->vfs_allocated_count) 5221 goto set_vfta; 5222 5223 /* Add PF to all active pools */ 5224 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5225 5226 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5227 u32 vlvf = rd32(E1000_VLVF(i)); 5228 5229 vlvf |= BIT(pf_id); 5230 wr32(E1000_VLVF(i), vlvf); 5231 } 5232 5233 set_vfta: 5234 /* Set all bits in the VLAN filter table array */ 5235 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 5236 hw->mac.ops.write_vfta(hw, i, ~0U); 5237 5238 /* Set flag so we don't redo unnecessary work */ 5239 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 5240 5241 return 0; 5242 } 5243 5244 #define VFTA_BLOCK_SIZE 8 5245 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 5246 { 5247 struct e1000_hw *hw = &adapter->hw; 5248 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 5249 u32 vid_start = vfta_offset * 32; 5250 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 5251 u32 i, vid, word, bits, pf_id; 5252 5253 /* guarantee that we don't scrub out management VLAN */ 5254 vid = adapter->mng_vlan_id; 5255 if (vid >= vid_start && vid < vid_end) 5256 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5257 5258 if (!adapter->vfs_allocated_count) 5259 goto set_vfta; 5260 5261 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5262 5263 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5264 u32 vlvf = rd32(E1000_VLVF(i)); 5265 5266 /* pull VLAN ID from VLVF */ 5267 vid = vlvf & VLAN_VID_MASK; 5268 5269 /* only concern ourselves with a certain range */ 5270 if (vid < vid_start || vid >= vid_end) 5271 continue; 5272 5273 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 5274 /* record VLAN ID in VFTA */ 5275 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5276 5277 /* if PF is part of this then continue */ 5278 if (test_bit(vid, adapter->active_vlans)) 5279 continue; 5280 } 5281 5282 /* remove PF from the pool */ 5283 bits = ~BIT(pf_id); 5284 bits &= rd32(E1000_VLVF(i)); 5285 wr32(E1000_VLVF(i), bits); 5286 } 5287 5288 set_vfta: 5289 /* extract values from active_vlans and write back to VFTA */ 5290 for (i = VFTA_BLOCK_SIZE; i--;) { 5291 vid = (vfta_offset + i) * 32; 5292 word = vid / BITS_PER_LONG; 5293 bits = vid % BITS_PER_LONG; 5294 5295 vfta[i] |= adapter->active_vlans[word] >> bits; 5296 5297 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 5298 } 5299 } 5300 5301 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 5302 { 5303 u32 i; 5304 5305 /* We are not in VLAN promisc, nothing to do */ 5306 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 5307 return; 5308 5309 /* Set flag so we don't redo unnecessary work */ 5310 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 5311 5312 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 5313 igb_scrub_vfta(adapter, i); 5314 } 5315 5316 /** 5317 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 5318 * @netdev: network interface device structure 5319 * 5320 * The set_rx_mode entry point is called whenever the unicast or multicast 5321 * address lists or the network interface flags are updated. This routine is 5322 * responsible for configuring the hardware for proper unicast, multicast, 5323 * promiscuous mode, and all-multi behavior. 5324 **/ 5325 static void igb_set_rx_mode(struct net_device *netdev) 5326 { 5327 struct igb_adapter *adapter = netdev_priv(netdev); 5328 struct e1000_hw *hw = &adapter->hw; 5329 unsigned int vfn = adapter->vfs_allocated_count; 5330 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 5331 int count; 5332 5333 /* Check for Promiscuous and All Multicast modes */ 5334 if (netdev->flags & IFF_PROMISC) { 5335 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5336 vmolr |= E1000_VMOLR_MPME; 5337 5338 /* enable use of UTA filter to force packets to default pool */ 5339 if (hw->mac.type == e1000_82576) 5340 vmolr |= E1000_VMOLR_ROPE; 5341 } else { 5342 if (netdev->flags & IFF_ALLMULTI) { 5343 rctl |= E1000_RCTL_MPE; 5344 vmolr |= E1000_VMOLR_MPME; 5345 } else { 5346 /* Write addresses to the MTA, if the attempt fails 5347 * then we should just turn on promiscuous mode so 5348 * that we can at least receive multicast traffic 5349 */ 5350 count = igb_write_mc_addr_list(netdev); 5351 if (count < 0) { 5352 rctl |= E1000_RCTL_MPE; 5353 vmolr |= E1000_VMOLR_MPME; 5354 } else if (count) { 5355 vmolr |= E1000_VMOLR_ROMPE; 5356 } 5357 } 5358 } 5359 5360 /* Write addresses to available RAR registers, if there is not 5361 * sufficient space to store all the addresses then enable 5362 * unicast promiscuous mode 5363 */ 5364 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5365 rctl |= E1000_RCTL_UPE; 5366 vmolr |= E1000_VMOLR_ROPE; 5367 } 5368 5369 /* enable VLAN filtering by default */ 5370 rctl |= E1000_RCTL_VFE; 5371 5372 /* disable VLAN filtering for modes that require it */ 5373 if ((netdev->flags & IFF_PROMISC) || 5374 (netdev->features & NETIF_F_RXALL)) { 5375 /* if we fail to set all rules then just clear VFE */ 5376 if (igb_vlan_promisc_enable(adapter)) 5377 rctl &= ~E1000_RCTL_VFE; 5378 } else { 5379 igb_vlan_promisc_disable(adapter); 5380 } 5381 5382 /* update state of unicast, multicast, and VLAN filtering modes */ 5383 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5384 E1000_RCTL_VFE); 5385 wr32(E1000_RCTL, rctl); 5386 5387 #if (PAGE_SIZE < 8192) 5388 if (!adapter->vfs_allocated_count) { 5389 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5390 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5391 } 5392 #endif 5393 wr32(E1000_RLPML, rlpml); 5394 5395 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5396 * the VMOLR to enable the appropriate modes. Without this workaround 5397 * we will have issues with VLAN tag stripping not being done for frames 5398 * that are only arriving because we are the default pool 5399 */ 5400 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5401 return; 5402 5403 /* set UTA to appropriate mode */ 5404 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5405 5406 vmolr |= rd32(E1000_VMOLR(vfn)) & 5407 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5408 5409 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5410 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5411 #if (PAGE_SIZE < 8192) 5412 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5413 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5414 else 5415 #endif 5416 vmolr |= MAX_JUMBO_FRAME_SIZE; 5417 vmolr |= E1000_VMOLR_LPE; 5418 5419 wr32(E1000_VMOLR(vfn), vmolr); 5420 5421 igb_restore_vf_multicasts(adapter); 5422 } 5423 5424 static void igb_check_wvbr(struct igb_adapter *adapter) 5425 { 5426 struct e1000_hw *hw = &adapter->hw; 5427 u32 wvbr = 0; 5428 5429 switch (hw->mac.type) { 5430 case e1000_82576: 5431 case e1000_i350: 5432 wvbr = rd32(E1000_WVBR); 5433 if (!wvbr) 5434 return; 5435 break; 5436 default: 5437 break; 5438 } 5439 5440 adapter->wvbr |= wvbr; 5441 } 5442 5443 #define IGB_STAGGERED_QUEUE_OFFSET 8 5444 5445 static void igb_spoof_check(struct igb_adapter *adapter) 5446 { 5447 int j; 5448 5449 if (!adapter->wvbr) 5450 return; 5451 5452 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5453 if (adapter->wvbr & BIT(j) || 5454 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5455 dev_warn(&adapter->pdev->dev, 5456 "Spoof event(s) detected on VF %d\n", j); 5457 adapter->wvbr &= 5458 ~(BIT(j) | 5459 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5460 } 5461 } 5462 } 5463 5464 /* Need to wait a few seconds after link up to get diagnostic information from 5465 * the phy 5466 */ 5467 static void igb_update_phy_info(struct timer_list *t) 5468 { 5469 struct igb_adapter *adapter = timer_container_of(adapter, t, 5470 phy_info_timer); 5471 igb_get_phy_info(&adapter->hw); 5472 } 5473 5474 /** 5475 * igb_has_link - check shared code for link and determine up/down 5476 * @adapter: pointer to driver private info 5477 **/ 5478 bool igb_has_link(struct igb_adapter *adapter) 5479 { 5480 struct e1000_hw *hw = &adapter->hw; 5481 bool link_active = false; 5482 5483 /* get_link_status is set on LSC (link status) interrupt or 5484 * rx sequence error interrupt. get_link_status will stay 5485 * false until the e1000_check_for_link establishes link 5486 * for copper adapters ONLY 5487 */ 5488 switch (hw->phy.media_type) { 5489 case e1000_media_type_copper: 5490 if (!hw->mac.get_link_status) 5491 return true; 5492 fallthrough; 5493 case e1000_media_type_internal_serdes: 5494 hw->mac.ops.check_for_link(hw); 5495 link_active = !hw->mac.get_link_status; 5496 break; 5497 default: 5498 case e1000_media_type_unknown: 5499 break; 5500 } 5501 5502 if (((hw->mac.type == e1000_i210) || 5503 (hw->mac.type == e1000_i211)) && 5504 (hw->phy.id == I210_I_PHY_ID)) { 5505 if (!netif_carrier_ok(adapter->netdev)) { 5506 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5507 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5508 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5509 adapter->link_check_timeout = jiffies; 5510 } 5511 } 5512 5513 return link_active; 5514 } 5515 5516 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5517 { 5518 bool ret = false; 5519 u32 ctrl_ext, thstat; 5520 5521 /* check for thermal sensor event on i350 copper only */ 5522 if (hw->mac.type == e1000_i350) { 5523 thstat = rd32(E1000_THSTAT); 5524 ctrl_ext = rd32(E1000_CTRL_EXT); 5525 5526 if ((hw->phy.media_type == e1000_media_type_copper) && 5527 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5528 ret = !!(thstat & event); 5529 } 5530 5531 return ret; 5532 } 5533 5534 /** 5535 * igb_check_lvmmc - check for malformed packets received 5536 * and indicated in LVMMC register 5537 * @adapter: pointer to adapter 5538 **/ 5539 static void igb_check_lvmmc(struct igb_adapter *adapter) 5540 { 5541 struct e1000_hw *hw = &adapter->hw; 5542 u32 lvmmc; 5543 5544 lvmmc = rd32(E1000_LVMMC); 5545 if (lvmmc) { 5546 if (unlikely(net_ratelimit())) { 5547 netdev_warn(adapter->netdev, 5548 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5549 lvmmc); 5550 } 5551 } 5552 } 5553 5554 /** 5555 * igb_watchdog - Timer Call-back 5556 * @t: pointer to timer_list containing our private info pointer 5557 **/ 5558 static void igb_watchdog(struct timer_list *t) 5559 { 5560 struct igb_adapter *adapter = timer_container_of(adapter, t, 5561 watchdog_timer); 5562 /* Do the rest outside of interrupt context */ 5563 schedule_work(&adapter->watchdog_task); 5564 } 5565 5566 static void igb_watchdog_task(struct work_struct *work) 5567 { 5568 struct igb_adapter *adapter = container_of(work, 5569 struct igb_adapter, 5570 watchdog_task); 5571 struct e1000_hw *hw = &adapter->hw; 5572 struct e1000_phy_info *phy = &hw->phy; 5573 struct net_device *netdev = adapter->netdev; 5574 u32 link; 5575 int i; 5576 u32 connsw; 5577 u16 phy_data, retry_count = 20; 5578 5579 link = igb_has_link(adapter); 5580 5581 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5582 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5583 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5584 else 5585 link = false; 5586 } 5587 5588 /* Force link down if we have fiber to swap to */ 5589 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5590 if (hw->phy.media_type == e1000_media_type_copper) { 5591 connsw = rd32(E1000_CONNSW); 5592 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5593 link = 0; 5594 } 5595 } 5596 if (link) { 5597 /* Perform a reset if the media type changed. */ 5598 if (hw->dev_spec._82575.media_changed) { 5599 hw->dev_spec._82575.media_changed = false; 5600 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5601 igb_reset(adapter); 5602 } 5603 /* Cancel scheduled suspend requests. */ 5604 pm_runtime_resume(netdev->dev.parent); 5605 5606 if (!netif_carrier_ok(netdev)) { 5607 u32 ctrl; 5608 5609 hw->mac.ops.get_speed_and_duplex(hw, 5610 &adapter->link_speed, 5611 &adapter->link_duplex); 5612 5613 ctrl = rd32(E1000_CTRL); 5614 /* Links status message must follow this format */ 5615 netdev_info(netdev, 5616 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5617 netdev->name, 5618 adapter->link_speed, 5619 adapter->link_duplex == FULL_DUPLEX ? 5620 "Full" : "Half", 5621 (ctrl & E1000_CTRL_TFCE) && 5622 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5623 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5624 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5625 5626 /* disable EEE if enabled */ 5627 if ((adapter->flags & IGB_FLAG_EEE) && 5628 (adapter->link_duplex == HALF_DUPLEX)) { 5629 dev_info(&adapter->pdev->dev, 5630 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5631 adapter->hw.dev_spec._82575.eee_disable = true; 5632 adapter->flags &= ~IGB_FLAG_EEE; 5633 } 5634 5635 /* check if SmartSpeed worked */ 5636 igb_check_downshift(hw); 5637 if (phy->speed_downgraded) 5638 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5639 5640 /* check for thermal sensor event */ 5641 if (igb_thermal_sensor_event(hw, 5642 E1000_THSTAT_LINK_THROTTLE)) 5643 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5644 5645 /* adjust timeout factor according to speed/duplex */ 5646 adapter->tx_timeout_factor = 1; 5647 switch (adapter->link_speed) { 5648 case SPEED_10: 5649 adapter->tx_timeout_factor = 14; 5650 break; 5651 case SPEED_100: 5652 /* maybe add some timeout factor ? */ 5653 break; 5654 } 5655 5656 if (adapter->link_speed != SPEED_1000 || 5657 !hw->phy.ops.read_reg) 5658 goto no_wait; 5659 5660 /* wait for Remote receiver status OK */ 5661 retry_read_status: 5662 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5663 &phy_data)) { 5664 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5665 retry_count) { 5666 msleep(100); 5667 retry_count--; 5668 goto retry_read_status; 5669 } else if (!retry_count) { 5670 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5671 } 5672 } else { 5673 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5674 } 5675 no_wait: 5676 netif_carrier_on(netdev); 5677 5678 igb_ping_all_vfs(adapter); 5679 igb_check_vf_rate_limit(adapter); 5680 5681 /* link state has changed, schedule phy info update */ 5682 if (!test_bit(__IGB_DOWN, &adapter->state)) 5683 mod_timer(&adapter->phy_info_timer, 5684 round_jiffies(jiffies + 2 * HZ)); 5685 } 5686 } else { 5687 if (netif_carrier_ok(netdev)) { 5688 adapter->link_speed = 0; 5689 adapter->link_duplex = 0; 5690 5691 /* check for thermal sensor event */ 5692 if (igb_thermal_sensor_event(hw, 5693 E1000_THSTAT_PWR_DOWN)) { 5694 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5695 } 5696 5697 /* Links status message must follow this format */ 5698 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5699 netdev->name); 5700 netif_carrier_off(netdev); 5701 5702 igb_ping_all_vfs(adapter); 5703 5704 /* link state has changed, schedule phy info update */ 5705 if (!test_bit(__IGB_DOWN, &adapter->state)) 5706 mod_timer(&adapter->phy_info_timer, 5707 round_jiffies(jiffies + 2 * HZ)); 5708 5709 /* link is down, time to check for alternate media */ 5710 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5711 igb_check_swap_media(adapter); 5712 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5713 schedule_work(&adapter->reset_task); 5714 /* return immediately */ 5715 return; 5716 } 5717 } 5718 pm_schedule_suspend(netdev->dev.parent, 5719 MSEC_PER_SEC * 5); 5720 5721 /* also check for alternate media here */ 5722 } else if (!netif_carrier_ok(netdev) && 5723 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5724 igb_check_swap_media(adapter); 5725 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5726 schedule_work(&adapter->reset_task); 5727 /* return immediately */ 5728 return; 5729 } 5730 } 5731 } 5732 5733 spin_lock(&adapter->stats64_lock); 5734 igb_update_stats(adapter); 5735 spin_unlock(&adapter->stats64_lock); 5736 5737 for (i = 0; i < adapter->num_tx_queues; i++) { 5738 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5739 if (!netif_carrier_ok(netdev)) { 5740 /* We've lost link, so the controller stops DMA, 5741 * but we've got queued Tx work that's never going 5742 * to get done, so reset controller to flush Tx. 5743 * (Do the reset outside of interrupt context). 5744 */ 5745 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5746 adapter->tx_timeout_count++; 5747 schedule_work(&adapter->reset_task); 5748 /* return immediately since reset is imminent */ 5749 return; 5750 } 5751 } 5752 5753 /* Force detection of hung controller every watchdog period */ 5754 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5755 } 5756 5757 /* Cause software interrupt to ensure Rx ring is cleaned */ 5758 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5759 u32 eics = 0; 5760 5761 for (i = 0; i < adapter->num_q_vectors; i++) { 5762 struct igb_q_vector *q_vector = adapter->q_vector[i]; 5763 struct igb_ring *rx_ring; 5764 5765 if (!q_vector->rx.ring) 5766 continue; 5767 5768 rx_ring = adapter->rx_ring[q_vector->rx.ring->queue_index]; 5769 5770 if (test_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags)) { 5771 eics |= q_vector->eims_value; 5772 clear_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 5773 } 5774 } 5775 if (eics) 5776 wr32(E1000_EICS, eics); 5777 } else { 5778 struct igb_ring *rx_ring = adapter->rx_ring[0]; 5779 5780 if (test_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags)) { 5781 clear_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 5782 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5783 } 5784 } 5785 5786 igb_spoof_check(adapter); 5787 igb_ptp_rx_hang(adapter); 5788 igb_ptp_tx_hang(adapter); 5789 5790 /* Check LVMMC register on i350/i354 only */ 5791 if ((adapter->hw.mac.type == e1000_i350) || 5792 (adapter->hw.mac.type == e1000_i354)) 5793 igb_check_lvmmc(adapter); 5794 5795 /* Reset the timer */ 5796 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5797 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5798 mod_timer(&adapter->watchdog_timer, 5799 round_jiffies(jiffies + HZ)); 5800 else 5801 mod_timer(&adapter->watchdog_timer, 5802 round_jiffies(jiffies + 2 * HZ)); 5803 } 5804 } 5805 5806 enum latency_range { 5807 lowest_latency = 0, 5808 low_latency = 1, 5809 bulk_latency = 2, 5810 latency_invalid = 255 5811 }; 5812 5813 /** 5814 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5815 * @q_vector: pointer to q_vector 5816 * 5817 * Stores a new ITR value based on strictly on packet size. This 5818 * algorithm is less sophisticated than that used in igb_update_itr, 5819 * due to the difficulty of synchronizing statistics across multiple 5820 * receive rings. The divisors and thresholds used by this function 5821 * were determined based on theoretical maximum wire speed and testing 5822 * data, in order to minimize response time while increasing bulk 5823 * throughput. 5824 * This functionality is controlled by ethtool's coalescing settings. 5825 * NOTE: This function is called only when operating in a multiqueue 5826 * receive environment. 5827 **/ 5828 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5829 { 5830 int new_val = q_vector->itr_val; 5831 int avg_wire_size = 0; 5832 struct igb_adapter *adapter = q_vector->adapter; 5833 unsigned int packets; 5834 5835 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5836 * ints/sec - ITR timer value of 120 ticks. 5837 */ 5838 if (adapter->link_speed != SPEED_1000) { 5839 new_val = IGB_4K_ITR; 5840 goto set_itr_val; 5841 } 5842 5843 packets = q_vector->rx.total_packets; 5844 if (packets) 5845 avg_wire_size = q_vector->rx.total_bytes / packets; 5846 5847 packets = q_vector->tx.total_packets; 5848 if (packets) 5849 avg_wire_size = max_t(u32, avg_wire_size, 5850 q_vector->tx.total_bytes / packets); 5851 5852 /* if avg_wire_size isn't set no work was done */ 5853 if (!avg_wire_size) 5854 goto clear_counts; 5855 5856 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5857 avg_wire_size += 24; 5858 5859 /* Don't starve jumbo frames */ 5860 avg_wire_size = min(avg_wire_size, 3000); 5861 5862 /* Give a little boost to mid-size frames */ 5863 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5864 new_val = avg_wire_size / 3; 5865 else 5866 new_val = avg_wire_size / 2; 5867 5868 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5869 if (new_val < IGB_20K_ITR && 5870 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5871 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5872 new_val = IGB_20K_ITR; 5873 5874 set_itr_val: 5875 if (new_val != q_vector->itr_val) { 5876 q_vector->itr_val = new_val; 5877 q_vector->set_itr = 1; 5878 } 5879 clear_counts: 5880 q_vector->rx.total_bytes = 0; 5881 q_vector->rx.total_packets = 0; 5882 q_vector->tx.total_bytes = 0; 5883 q_vector->tx.total_packets = 0; 5884 } 5885 5886 /** 5887 * igb_update_itr - update the dynamic ITR value based on statistics 5888 * @q_vector: pointer to q_vector 5889 * @ring_container: ring info to update the itr for 5890 * 5891 * Stores a new ITR value based on packets and byte 5892 * counts during the last interrupt. The advantage of per interrupt 5893 * computation is faster updates and more accurate ITR for the current 5894 * traffic pattern. Constants in this function were computed 5895 * based on theoretical maximum wire speed and thresholds were set based 5896 * on testing data as well as attempting to minimize response time 5897 * while increasing bulk throughput. 5898 * This functionality is controlled by ethtool's coalescing settings. 5899 * NOTE: These calculations are only valid when operating in a single- 5900 * queue environment. 5901 **/ 5902 static void igb_update_itr(struct igb_q_vector *q_vector, 5903 struct igb_ring_container *ring_container) 5904 { 5905 unsigned int packets = ring_container->total_packets; 5906 unsigned int bytes = ring_container->total_bytes; 5907 u8 itrval = ring_container->itr; 5908 5909 /* no packets, exit with status unchanged */ 5910 if (packets == 0) 5911 return; 5912 5913 switch (itrval) { 5914 case lowest_latency: 5915 /* handle TSO and jumbo frames */ 5916 if (bytes/packets > 8000) 5917 itrval = bulk_latency; 5918 else if ((packets < 5) && (bytes > 512)) 5919 itrval = low_latency; 5920 break; 5921 case low_latency: /* 50 usec aka 20000 ints/s */ 5922 if (bytes > 10000) { 5923 /* this if handles the TSO accounting */ 5924 if (bytes/packets > 8000) 5925 itrval = bulk_latency; 5926 else if ((packets < 10) || ((bytes/packets) > 1200)) 5927 itrval = bulk_latency; 5928 else if ((packets > 35)) 5929 itrval = lowest_latency; 5930 } else if (bytes/packets > 2000) { 5931 itrval = bulk_latency; 5932 } else if (packets <= 2 && bytes < 512) { 5933 itrval = lowest_latency; 5934 } 5935 break; 5936 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5937 if (bytes > 25000) { 5938 if (packets > 35) 5939 itrval = low_latency; 5940 } else if (bytes < 1500) { 5941 itrval = low_latency; 5942 } 5943 break; 5944 } 5945 5946 /* clear work counters since we have the values we need */ 5947 ring_container->total_bytes = 0; 5948 ring_container->total_packets = 0; 5949 5950 /* write updated itr to ring container */ 5951 ring_container->itr = itrval; 5952 } 5953 5954 static void igb_set_itr(struct igb_q_vector *q_vector) 5955 { 5956 struct igb_adapter *adapter = q_vector->adapter; 5957 u32 new_itr = q_vector->itr_val; 5958 u8 current_itr = 0; 5959 5960 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5961 if (adapter->link_speed != SPEED_1000) { 5962 current_itr = 0; 5963 new_itr = IGB_4K_ITR; 5964 goto set_itr_now; 5965 } 5966 5967 igb_update_itr(q_vector, &q_vector->tx); 5968 igb_update_itr(q_vector, &q_vector->rx); 5969 5970 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5971 5972 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5973 if (current_itr == lowest_latency && 5974 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5975 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5976 current_itr = low_latency; 5977 5978 switch (current_itr) { 5979 /* counts and packets in update_itr are dependent on these numbers */ 5980 case lowest_latency: 5981 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5982 break; 5983 case low_latency: 5984 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5985 break; 5986 case bulk_latency: 5987 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5988 break; 5989 default: 5990 break; 5991 } 5992 5993 set_itr_now: 5994 if (new_itr != q_vector->itr_val) { 5995 /* this attempts to bias the interrupt rate towards Bulk 5996 * by adding intermediate steps when interrupt rate is 5997 * increasing 5998 */ 5999 new_itr = new_itr > q_vector->itr_val ? 6000 max((new_itr * q_vector->itr_val) / 6001 (new_itr + (q_vector->itr_val >> 2)), 6002 new_itr) : new_itr; 6003 /* Don't write the value here; it resets the adapter's 6004 * internal timer, and causes us to delay far longer than 6005 * we should between interrupts. Instead, we write the ITR 6006 * value at the beginning of the next interrupt so the timing 6007 * ends up being correct. 6008 */ 6009 q_vector->itr_val = new_itr; 6010 q_vector->set_itr = 1; 6011 } 6012 } 6013 6014 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 6015 struct igb_tx_buffer *first, 6016 u32 vlan_macip_lens, u32 type_tucmd, 6017 u32 mss_l4len_idx) 6018 { 6019 struct e1000_adv_tx_context_desc *context_desc; 6020 u16 i = tx_ring->next_to_use; 6021 struct timespec64 ts; 6022 6023 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 6024 6025 i++; 6026 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 6027 6028 /* set bits to identify this as an advanced context descriptor */ 6029 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 6030 6031 /* For 82575, context index must be unique per ring. */ 6032 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6033 mss_l4len_idx |= tx_ring->reg_idx << 4; 6034 6035 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 6036 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 6037 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 6038 6039 /* We assume there is always a valid tx time available. Invalid times 6040 * should have been handled by the upper layers. 6041 */ 6042 if (tx_ring->launchtime_enable) { 6043 ts = ktime_to_timespec64(first->skb->tstamp); 6044 skb_txtime_consumed(first->skb); 6045 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 6046 } else { 6047 context_desc->seqnum_seed = 0; 6048 } 6049 } 6050 6051 static int igb_tso(struct igb_ring *tx_ring, 6052 struct igb_tx_buffer *first, 6053 u8 *hdr_len) 6054 { 6055 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 6056 struct sk_buff *skb = first->skb; 6057 union { 6058 struct iphdr *v4; 6059 struct ipv6hdr *v6; 6060 unsigned char *hdr; 6061 } ip; 6062 union { 6063 struct tcphdr *tcp; 6064 struct udphdr *udp; 6065 unsigned char *hdr; 6066 } l4; 6067 u32 paylen, l4_offset; 6068 int err; 6069 6070 if (skb->ip_summed != CHECKSUM_PARTIAL) 6071 return 0; 6072 6073 if (!skb_is_gso(skb)) 6074 return 0; 6075 6076 err = skb_cow_head(skb, 0); 6077 if (err < 0) 6078 return err; 6079 6080 ip.hdr = skb_network_header(skb); 6081 l4.hdr = skb_checksum_start(skb); 6082 6083 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 6084 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 6085 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP; 6086 6087 /* initialize outer IP header fields */ 6088 if (ip.v4->version == 4) { 6089 unsigned char *csum_start = skb_checksum_start(skb); 6090 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 6091 6092 /* IP header will have to cancel out any data that 6093 * is not a part of the outer IP header 6094 */ 6095 ip.v4->check = csum_fold(csum_partial(trans_start, 6096 csum_start - trans_start, 6097 0)); 6098 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 6099 6100 ip.v4->tot_len = 0; 6101 first->tx_flags |= IGB_TX_FLAGS_TSO | 6102 IGB_TX_FLAGS_CSUM | 6103 IGB_TX_FLAGS_IPV4; 6104 } else { 6105 ip.v6->payload_len = 0; 6106 first->tx_flags |= IGB_TX_FLAGS_TSO | 6107 IGB_TX_FLAGS_CSUM; 6108 } 6109 6110 /* determine offset of inner transport header */ 6111 l4_offset = l4.hdr - skb->data; 6112 6113 /* remove payload length from inner checksum */ 6114 paylen = skb->len - l4_offset; 6115 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) { 6116 /* compute length of segmentation header */ 6117 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 6118 csum_replace_by_diff(&l4.tcp->check, 6119 (__force __wsum)htonl(paylen)); 6120 } else { 6121 /* compute length of segmentation header */ 6122 *hdr_len = sizeof(*l4.udp) + l4_offset; 6123 csum_replace_by_diff(&l4.udp->check, 6124 (__force __wsum)htonl(paylen)); 6125 } 6126 6127 /* update gso size and bytecount with header size */ 6128 first->gso_segs = skb_shinfo(skb)->gso_segs; 6129 first->bytecount += (first->gso_segs - 1) * *hdr_len; 6130 6131 /* MSS L4LEN IDX */ 6132 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 6133 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 6134 6135 /* VLAN MACLEN IPLEN */ 6136 vlan_macip_lens = l4.hdr - ip.hdr; 6137 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 6138 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6139 6140 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 6141 type_tucmd, mss_l4len_idx); 6142 6143 return 1; 6144 } 6145 6146 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 6147 { 6148 struct sk_buff *skb = first->skb; 6149 u32 vlan_macip_lens = 0; 6150 u32 type_tucmd = 0; 6151 6152 if (skb->ip_summed != CHECKSUM_PARTIAL) { 6153 csum_failed: 6154 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 6155 !tx_ring->launchtime_enable) 6156 return; 6157 goto no_csum; 6158 } 6159 6160 switch (skb->csum_offset) { 6161 case offsetof(struct tcphdr, check): 6162 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 6163 fallthrough; 6164 case offsetof(struct udphdr, check): 6165 break; 6166 case offsetof(struct sctphdr, checksum): 6167 /* validate that this is actually an SCTP request */ 6168 if (skb_csum_is_sctp(skb)) { 6169 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 6170 break; 6171 } 6172 fallthrough; 6173 default: 6174 skb_checksum_help(skb); 6175 goto csum_failed; 6176 } 6177 6178 /* update TX checksum flag */ 6179 first->tx_flags |= IGB_TX_FLAGS_CSUM; 6180 vlan_macip_lens = skb_checksum_start_offset(skb) - 6181 skb_network_offset(skb); 6182 no_csum: 6183 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 6184 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6185 6186 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 6187 } 6188 6189 #define IGB_SET_FLAG(_input, _flag, _result) \ 6190 ((_flag <= _result) ? \ 6191 ((u32)(_input & _flag) * (_result / _flag)) : \ 6192 ((u32)(_input & _flag) / (_flag / _result))) 6193 6194 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6195 { 6196 /* set type for advanced descriptor with frame checksum insertion */ 6197 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 6198 E1000_ADVTXD_DCMD_DEXT | 6199 E1000_ADVTXD_DCMD_IFCS; 6200 6201 /* set HW vlan bit if vlan is present */ 6202 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 6203 (E1000_ADVTXD_DCMD_VLE)); 6204 6205 /* set segmentation bits for TSO */ 6206 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 6207 (E1000_ADVTXD_DCMD_TSE)); 6208 6209 /* set timestamp bit if present */ 6210 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 6211 (E1000_ADVTXD_MAC_TSTAMP)); 6212 6213 /* insert frame checksum */ 6214 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 6215 6216 return cmd_type; 6217 } 6218 6219 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 6220 union e1000_adv_tx_desc *tx_desc, 6221 u32 tx_flags, unsigned int paylen) 6222 { 6223 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 6224 6225 /* 82575 requires a unique index per ring */ 6226 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6227 olinfo_status |= tx_ring->reg_idx << 4; 6228 6229 /* insert L4 checksum */ 6230 olinfo_status |= IGB_SET_FLAG(tx_flags, 6231 IGB_TX_FLAGS_CSUM, 6232 (E1000_TXD_POPTS_TXSM << 8)); 6233 6234 /* insert IPv4 checksum */ 6235 olinfo_status |= IGB_SET_FLAG(tx_flags, 6236 IGB_TX_FLAGS_IPV4, 6237 (E1000_TXD_POPTS_IXSM << 8)); 6238 6239 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6240 } 6241 6242 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6243 { 6244 struct net_device *netdev = tx_ring->netdev; 6245 6246 netif_stop_subqueue(netdev, tx_ring->queue_index); 6247 6248 /* Herbert's original patch had: 6249 * smp_mb__after_netif_stop_queue(); 6250 * but since that doesn't exist yet, just open code it. 6251 */ 6252 smp_mb(); 6253 6254 /* We need to check again in a case another CPU has just 6255 * made room available. 6256 */ 6257 if (igb_desc_unused(tx_ring) < size) 6258 return -EBUSY; 6259 6260 /* A reprieve! */ 6261 netif_wake_subqueue(netdev, tx_ring->queue_index); 6262 6263 u64_stats_update_begin(&tx_ring->tx_syncp2); 6264 tx_ring->tx_stats.restart_queue2++; 6265 u64_stats_update_end(&tx_ring->tx_syncp2); 6266 6267 return 0; 6268 } 6269 6270 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6271 { 6272 if (igb_desc_unused(tx_ring) >= size) 6273 return 0; 6274 return __igb_maybe_stop_tx(tx_ring, size); 6275 } 6276 6277 static int igb_tx_map(struct igb_ring *tx_ring, 6278 struct igb_tx_buffer *first, 6279 const u8 hdr_len) 6280 { 6281 struct sk_buff *skb = first->skb; 6282 struct igb_tx_buffer *tx_buffer; 6283 union e1000_adv_tx_desc *tx_desc; 6284 skb_frag_t *frag; 6285 dma_addr_t dma; 6286 unsigned int data_len, size; 6287 u32 tx_flags = first->tx_flags; 6288 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 6289 u16 i = tx_ring->next_to_use; 6290 6291 tx_desc = IGB_TX_DESC(tx_ring, i); 6292 6293 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 6294 6295 size = skb_headlen(skb); 6296 data_len = skb->data_len; 6297 6298 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6299 6300 tx_buffer = first; 6301 6302 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6303 if (dma_mapping_error(tx_ring->dev, dma)) 6304 goto dma_error; 6305 6306 /* record length, and DMA address */ 6307 dma_unmap_len_set(tx_buffer, len, size); 6308 dma_unmap_addr_set(tx_buffer, dma, dma); 6309 6310 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6311 6312 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 6313 tx_desc->read.cmd_type_len = 6314 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 6315 6316 i++; 6317 tx_desc++; 6318 if (i == tx_ring->count) { 6319 tx_desc = IGB_TX_DESC(tx_ring, 0); 6320 i = 0; 6321 } 6322 tx_desc->read.olinfo_status = 0; 6323 6324 dma += IGB_MAX_DATA_PER_TXD; 6325 size -= IGB_MAX_DATA_PER_TXD; 6326 6327 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6328 } 6329 6330 if (likely(!data_len)) 6331 break; 6332 6333 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6334 6335 i++; 6336 tx_desc++; 6337 if (i == tx_ring->count) { 6338 tx_desc = IGB_TX_DESC(tx_ring, 0); 6339 i = 0; 6340 } 6341 tx_desc->read.olinfo_status = 0; 6342 6343 size = skb_frag_size(frag); 6344 data_len -= size; 6345 6346 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6347 size, DMA_TO_DEVICE); 6348 6349 tx_buffer = &tx_ring->tx_buffer_info[i]; 6350 } 6351 6352 /* write last descriptor with RS and EOP bits */ 6353 cmd_type |= size | IGB_TXD_DCMD; 6354 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6355 6356 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6357 6358 /* set the timestamp */ 6359 first->time_stamp = jiffies; 6360 6361 skb_tx_timestamp(skb); 6362 6363 /* Force memory writes to complete before letting h/w know there 6364 * are new descriptors to fetch. (Only applicable for weak-ordered 6365 * memory model archs, such as IA-64). 6366 * 6367 * We also need this memory barrier to make certain all of the 6368 * status bits have been updated before next_to_watch is written. 6369 */ 6370 dma_wmb(); 6371 6372 /* set next_to_watch value indicating a packet is present */ 6373 first->next_to_watch = tx_desc; 6374 6375 i++; 6376 if (i == tx_ring->count) 6377 i = 0; 6378 6379 tx_ring->next_to_use = i; 6380 6381 /* Make sure there is space in the ring for the next send. */ 6382 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6383 6384 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6385 writel(i, tx_ring->tail); 6386 } 6387 return 0; 6388 6389 dma_error: 6390 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6391 tx_buffer = &tx_ring->tx_buffer_info[i]; 6392 6393 /* clear dma mappings for failed tx_buffer_info map */ 6394 while (tx_buffer != first) { 6395 if (dma_unmap_len(tx_buffer, len)) 6396 dma_unmap_page(tx_ring->dev, 6397 dma_unmap_addr(tx_buffer, dma), 6398 dma_unmap_len(tx_buffer, len), 6399 DMA_TO_DEVICE); 6400 dma_unmap_len_set(tx_buffer, len, 0); 6401 6402 if (i-- == 0) 6403 i += tx_ring->count; 6404 tx_buffer = &tx_ring->tx_buffer_info[i]; 6405 } 6406 6407 if (dma_unmap_len(tx_buffer, len)) 6408 dma_unmap_single(tx_ring->dev, 6409 dma_unmap_addr(tx_buffer, dma), 6410 dma_unmap_len(tx_buffer, len), 6411 DMA_TO_DEVICE); 6412 dma_unmap_len_set(tx_buffer, len, 0); 6413 6414 dev_kfree_skb_any(tx_buffer->skb); 6415 tx_buffer->skb = NULL; 6416 6417 tx_ring->next_to_use = i; 6418 6419 return -1; 6420 } 6421 6422 int igb_xmit_xdp_ring(struct igb_adapter *adapter, 6423 struct igb_ring *tx_ring, 6424 struct xdp_frame *xdpf) 6425 { 6426 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 6427 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 6428 u16 count, i, index = tx_ring->next_to_use; 6429 struct igb_tx_buffer *tx_head = &tx_ring->tx_buffer_info[index]; 6430 struct igb_tx_buffer *tx_buffer = tx_head; 6431 union e1000_adv_tx_desc *tx_desc = IGB_TX_DESC(tx_ring, index); 6432 u32 len = xdpf->len, cmd_type, olinfo_status; 6433 void *data = xdpf->data; 6434 6435 count = TXD_USE_COUNT(len); 6436 for (i = 0; i < nr_frags; i++) 6437 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i])); 6438 6439 if (igb_maybe_stop_tx(tx_ring, count + 3)) 6440 return IGB_XDP_CONSUMED; 6441 6442 i = 0; 6443 /* record the location of the first descriptor for this packet */ 6444 tx_head->bytecount = xdp_get_frame_len(xdpf); 6445 tx_head->type = IGB_TYPE_XDP; 6446 tx_head->gso_segs = 1; 6447 tx_head->xdpf = xdpf; 6448 6449 olinfo_status = tx_head->bytecount << E1000_ADVTXD_PAYLEN_SHIFT; 6450 /* 82575 requires a unique index per ring */ 6451 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6452 olinfo_status |= tx_ring->reg_idx << 4; 6453 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6454 6455 for (;;) { 6456 dma_addr_t dma; 6457 6458 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE); 6459 if (dma_mapping_error(tx_ring->dev, dma)) 6460 goto unmap; 6461 6462 /* record length, and DMA address */ 6463 dma_unmap_len_set(tx_buffer, len, len); 6464 dma_unmap_addr_set(tx_buffer, dma, dma); 6465 6466 /* put descriptor type bits */ 6467 cmd_type = E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_DEXT | 6468 E1000_ADVTXD_DCMD_IFCS | len; 6469 6470 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6471 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6472 6473 tx_buffer->protocol = 0; 6474 6475 if (++index == tx_ring->count) 6476 index = 0; 6477 6478 if (i == nr_frags) 6479 break; 6480 6481 tx_buffer = &tx_ring->tx_buffer_info[index]; 6482 tx_desc = IGB_TX_DESC(tx_ring, index); 6483 tx_desc->read.olinfo_status = 0; 6484 6485 data = skb_frag_address(&sinfo->frags[i]); 6486 len = skb_frag_size(&sinfo->frags[i]); 6487 i++; 6488 } 6489 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_TXD_DCMD); 6490 6491 netdev_tx_sent_queue(txring_txq(tx_ring), tx_head->bytecount); 6492 /* set the timestamp */ 6493 tx_head->time_stamp = jiffies; 6494 6495 /* Avoid any potential race with xdp_xmit and cleanup */ 6496 smp_wmb(); 6497 6498 /* set next_to_watch value indicating a packet is present */ 6499 tx_head->next_to_watch = tx_desc; 6500 tx_ring->next_to_use = index; 6501 6502 /* Make sure there is space in the ring for the next send. */ 6503 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6504 6505 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) 6506 writel(index, tx_ring->tail); 6507 6508 return IGB_XDP_TX; 6509 6510 unmap: 6511 for (;;) { 6512 tx_buffer = &tx_ring->tx_buffer_info[index]; 6513 if (dma_unmap_len(tx_buffer, len)) 6514 dma_unmap_page(tx_ring->dev, 6515 dma_unmap_addr(tx_buffer, dma), 6516 dma_unmap_len(tx_buffer, len), 6517 DMA_TO_DEVICE); 6518 dma_unmap_len_set(tx_buffer, len, 0); 6519 if (tx_buffer == tx_head) 6520 break; 6521 6522 if (!index) 6523 index += tx_ring->count; 6524 index--; 6525 } 6526 6527 return IGB_XDP_CONSUMED; 6528 } 6529 6530 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6531 struct igb_ring *tx_ring) 6532 { 6533 struct igb_tx_buffer *first; 6534 int tso; 6535 u32 tx_flags = 0; 6536 unsigned short f; 6537 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6538 __be16 protocol = vlan_get_protocol(skb); 6539 u8 hdr_len = 0; 6540 6541 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6542 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6543 * + 2 desc gap to keep tail from touching head, 6544 * + 1 desc for context descriptor, 6545 * otherwise try next time 6546 */ 6547 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6548 count += TXD_USE_COUNT(skb_frag_size( 6549 &skb_shinfo(skb)->frags[f])); 6550 6551 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6552 /* this is a hard error */ 6553 return NETDEV_TX_BUSY; 6554 } 6555 6556 if (unlikely(test_bit(IGB_RING_FLAG_TX_DISABLED, &tx_ring->flags))) 6557 return NETDEV_TX_BUSY; 6558 6559 /* record the location of the first descriptor for this packet */ 6560 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6561 first->type = IGB_TYPE_SKB; 6562 first->skb = skb; 6563 first->bytecount = skb->len; 6564 first->gso_segs = 1; 6565 6566 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6567 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6568 6569 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6570 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6571 &adapter->state)) { 6572 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6573 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6574 6575 adapter->ptp_tx_skb = skb_get(skb); 6576 adapter->ptp_tx_start = jiffies; 6577 if (adapter->hw.mac.type == e1000_82576) 6578 schedule_work(&adapter->ptp_tx_work); 6579 } else { 6580 adapter->tx_hwtstamp_skipped++; 6581 } 6582 } 6583 6584 if (skb_vlan_tag_present(skb)) { 6585 tx_flags |= IGB_TX_FLAGS_VLAN; 6586 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6587 } 6588 6589 /* record initial flags and protocol */ 6590 first->tx_flags = tx_flags; 6591 first->protocol = protocol; 6592 6593 tso = igb_tso(tx_ring, first, &hdr_len); 6594 if (tso < 0) 6595 goto out_drop; 6596 else if (!tso) 6597 igb_tx_csum(tx_ring, first); 6598 6599 if (igb_tx_map(tx_ring, first, hdr_len)) 6600 goto cleanup_tx_tstamp; 6601 6602 return NETDEV_TX_OK; 6603 6604 out_drop: 6605 dev_kfree_skb_any(first->skb); 6606 first->skb = NULL; 6607 cleanup_tx_tstamp: 6608 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6609 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6610 6611 dev_kfree_skb_any(adapter->ptp_tx_skb); 6612 adapter->ptp_tx_skb = NULL; 6613 if (adapter->hw.mac.type == e1000_82576) 6614 cancel_work_sync(&adapter->ptp_tx_work); 6615 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6616 } 6617 6618 return NETDEV_TX_OK; 6619 } 6620 6621 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6622 struct sk_buff *skb) 6623 { 6624 unsigned int r_idx = skb->queue_mapping; 6625 6626 if (r_idx >= adapter->num_tx_queues) 6627 r_idx = r_idx % adapter->num_tx_queues; 6628 6629 return adapter->tx_ring[r_idx]; 6630 } 6631 6632 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6633 struct net_device *netdev) 6634 { 6635 struct igb_adapter *adapter = netdev_priv(netdev); 6636 6637 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6638 * in order to meet this minimum size requirement. 6639 */ 6640 if (skb_put_padto(skb, 17)) 6641 return NETDEV_TX_OK; 6642 6643 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6644 } 6645 6646 /** 6647 * igb_tx_timeout - Respond to a Tx Hang 6648 * @netdev: network interface device structure 6649 * @txqueue: number of the Tx queue that hung (unused) 6650 **/ 6651 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6652 { 6653 struct igb_adapter *adapter = netdev_priv(netdev); 6654 struct e1000_hw *hw = &adapter->hw; 6655 6656 /* Do the reset outside of interrupt context */ 6657 adapter->tx_timeout_count++; 6658 6659 if (hw->mac.type >= e1000_82580) 6660 hw->dev_spec._82575.global_device_reset = true; 6661 6662 schedule_work(&adapter->reset_task); 6663 wr32(E1000_EICS, 6664 (adapter->eims_enable_mask & ~adapter->eims_other)); 6665 } 6666 6667 static void igb_reset_task(struct work_struct *work) 6668 { 6669 struct igb_adapter *adapter; 6670 adapter = container_of(work, struct igb_adapter, reset_task); 6671 6672 rtnl_lock(); 6673 /* If we're already down or resetting, just bail */ 6674 if (test_bit(__IGB_DOWN, &adapter->state) || 6675 test_bit(__IGB_RESETTING, &adapter->state)) { 6676 rtnl_unlock(); 6677 return; 6678 } 6679 6680 igb_dump(adapter); 6681 netdev_err(adapter->netdev, "Reset adapter\n"); 6682 igb_reinit_locked(adapter); 6683 rtnl_unlock(); 6684 } 6685 6686 /** 6687 * igb_get_stats64 - Get System Network Statistics 6688 * @netdev: network interface device structure 6689 * @stats: rtnl_link_stats64 pointer 6690 **/ 6691 static void igb_get_stats64(struct net_device *netdev, 6692 struct rtnl_link_stats64 *stats) 6693 { 6694 struct igb_adapter *adapter = netdev_priv(netdev); 6695 6696 spin_lock(&adapter->stats64_lock); 6697 igb_update_stats(adapter); 6698 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6699 spin_unlock(&adapter->stats64_lock); 6700 } 6701 6702 /** 6703 * igb_change_mtu - Change the Maximum Transfer Unit 6704 * @netdev: network interface device structure 6705 * @new_mtu: new value for maximum frame size 6706 * 6707 * Returns 0 on success, negative on failure 6708 **/ 6709 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6710 { 6711 struct igb_adapter *adapter = netdev_priv(netdev); 6712 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD; 6713 6714 if (igb_xdp_is_enabled(adapter)) { 6715 int i; 6716 6717 for (i = 0; i < adapter->num_rx_queues; i++) { 6718 struct igb_ring *ring = adapter->rx_ring[i]; 6719 6720 if (max_frame > igb_rx_bufsz(ring)) { 6721 netdev_warn(adapter->netdev, 6722 "Requested MTU size is not supported with XDP. Max frame size is %d\n", 6723 max_frame); 6724 return -EINVAL; 6725 } 6726 } 6727 } 6728 6729 /* adjust max frame to be at least the size of a standard frame */ 6730 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6731 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6732 6733 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6734 usleep_range(1000, 2000); 6735 6736 /* igb_down has a dependency on max_frame_size */ 6737 adapter->max_frame_size = max_frame; 6738 6739 if (netif_running(netdev)) 6740 igb_down(adapter); 6741 6742 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6743 netdev->mtu, new_mtu); 6744 WRITE_ONCE(netdev->mtu, new_mtu); 6745 6746 if (netif_running(netdev)) 6747 igb_up(adapter); 6748 else 6749 igb_reset(adapter); 6750 6751 clear_bit(__IGB_RESETTING, &adapter->state); 6752 6753 return 0; 6754 } 6755 6756 /** 6757 * igb_update_stats - Update the board statistics counters 6758 * @adapter: board private structure 6759 **/ 6760 void igb_update_stats(struct igb_adapter *adapter) 6761 { 6762 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6763 struct e1000_hw *hw = &adapter->hw; 6764 struct pci_dev *pdev = adapter->pdev; 6765 u32 reg, mpc; 6766 int i; 6767 u64 bytes, packets; 6768 unsigned int start; 6769 u64 _bytes, _packets; 6770 6771 /* Prevent stats update while adapter is being reset, or if the pci 6772 * connection is down. 6773 */ 6774 if (adapter->link_speed == 0) 6775 return; 6776 if (pci_channel_offline(pdev)) 6777 return; 6778 6779 bytes = 0; 6780 packets = 0; 6781 6782 rcu_read_lock(); 6783 for (i = 0; i < adapter->num_rx_queues; i++) { 6784 struct igb_ring *ring = adapter->rx_ring[i]; 6785 u32 rqdpc = rd32(E1000_RQDPC(i)); 6786 if (hw->mac.type >= e1000_i210) 6787 wr32(E1000_RQDPC(i), 0); 6788 6789 if (rqdpc) { 6790 ring->rx_stats.drops += rqdpc; 6791 net_stats->rx_fifo_errors += rqdpc; 6792 } 6793 6794 do { 6795 start = u64_stats_fetch_begin(&ring->rx_syncp); 6796 _bytes = ring->rx_stats.bytes; 6797 _packets = ring->rx_stats.packets; 6798 } while (u64_stats_fetch_retry(&ring->rx_syncp, start)); 6799 bytes += _bytes; 6800 packets += _packets; 6801 } 6802 6803 net_stats->rx_bytes = bytes; 6804 net_stats->rx_packets = packets; 6805 6806 bytes = 0; 6807 packets = 0; 6808 for (i = 0; i < adapter->num_tx_queues; i++) { 6809 struct igb_ring *ring = adapter->tx_ring[i]; 6810 do { 6811 start = u64_stats_fetch_begin(&ring->tx_syncp); 6812 _bytes = ring->tx_stats.bytes; 6813 _packets = ring->tx_stats.packets; 6814 } while (u64_stats_fetch_retry(&ring->tx_syncp, start)); 6815 bytes += _bytes; 6816 packets += _packets; 6817 } 6818 net_stats->tx_bytes = bytes; 6819 net_stats->tx_packets = packets; 6820 rcu_read_unlock(); 6821 6822 /* read stats registers */ 6823 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6824 adapter->stats.gprc += rd32(E1000_GPRC); 6825 adapter->stats.gorc += rd32(E1000_GORCL); 6826 rd32(E1000_GORCH); /* clear GORCL */ 6827 adapter->stats.bprc += rd32(E1000_BPRC); 6828 adapter->stats.mprc += rd32(E1000_MPRC); 6829 adapter->stats.roc += rd32(E1000_ROC); 6830 6831 adapter->stats.prc64 += rd32(E1000_PRC64); 6832 adapter->stats.prc127 += rd32(E1000_PRC127); 6833 adapter->stats.prc255 += rd32(E1000_PRC255); 6834 adapter->stats.prc511 += rd32(E1000_PRC511); 6835 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6836 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6837 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6838 adapter->stats.sec += rd32(E1000_SEC); 6839 6840 mpc = rd32(E1000_MPC); 6841 adapter->stats.mpc += mpc; 6842 net_stats->rx_fifo_errors += mpc; 6843 adapter->stats.scc += rd32(E1000_SCC); 6844 adapter->stats.ecol += rd32(E1000_ECOL); 6845 adapter->stats.mcc += rd32(E1000_MCC); 6846 adapter->stats.latecol += rd32(E1000_LATECOL); 6847 adapter->stats.dc += rd32(E1000_DC); 6848 adapter->stats.rlec += rd32(E1000_RLEC); 6849 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6850 adapter->stats.xontxc += rd32(E1000_XONTXC); 6851 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6852 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6853 adapter->stats.fcruc += rd32(E1000_FCRUC); 6854 adapter->stats.gptc += rd32(E1000_GPTC); 6855 adapter->stats.gotc += rd32(E1000_GOTCL); 6856 rd32(E1000_GOTCH); /* clear GOTCL */ 6857 adapter->stats.rnbc += rd32(E1000_RNBC); 6858 adapter->stats.ruc += rd32(E1000_RUC); 6859 adapter->stats.rfc += rd32(E1000_RFC); 6860 adapter->stats.rjc += rd32(E1000_RJC); 6861 adapter->stats.tor += rd32(E1000_TORH); 6862 adapter->stats.tot += rd32(E1000_TOTH); 6863 adapter->stats.tpr += rd32(E1000_TPR); 6864 6865 adapter->stats.ptc64 += rd32(E1000_PTC64); 6866 adapter->stats.ptc127 += rd32(E1000_PTC127); 6867 adapter->stats.ptc255 += rd32(E1000_PTC255); 6868 adapter->stats.ptc511 += rd32(E1000_PTC511); 6869 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6870 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6871 6872 adapter->stats.mptc += rd32(E1000_MPTC); 6873 adapter->stats.bptc += rd32(E1000_BPTC); 6874 6875 adapter->stats.tpt += rd32(E1000_TPT); 6876 adapter->stats.colc += rd32(E1000_COLC); 6877 6878 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6879 /* read internal phy specific stats */ 6880 reg = rd32(E1000_CTRL_EXT); 6881 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6882 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6883 6884 /* this stat has invalid values on i210/i211 */ 6885 if ((hw->mac.type != e1000_i210) && 6886 (hw->mac.type != e1000_i211)) 6887 adapter->stats.tncrs += rd32(E1000_TNCRS); 6888 } 6889 6890 adapter->stats.tsctc += rd32(E1000_TSCTC); 6891 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6892 6893 adapter->stats.iac += rd32(E1000_IAC); 6894 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6895 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6896 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6897 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6898 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6899 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6900 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6901 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6902 6903 /* Fill out the OS statistics structure */ 6904 net_stats->multicast = adapter->stats.mprc; 6905 net_stats->collisions = adapter->stats.colc; 6906 6907 /* Rx Errors */ 6908 6909 /* RLEC on some newer hardware can be incorrect so build 6910 * our own version based on RUC and ROC 6911 */ 6912 net_stats->rx_errors = adapter->stats.rxerrc + 6913 adapter->stats.crcerrs + adapter->stats.algnerrc + 6914 adapter->stats.ruc + adapter->stats.roc + 6915 adapter->stats.cexterr; 6916 net_stats->rx_length_errors = adapter->stats.ruc + 6917 adapter->stats.roc; 6918 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6919 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6920 net_stats->rx_missed_errors = adapter->stats.mpc; 6921 6922 /* Tx Errors */ 6923 net_stats->tx_errors = adapter->stats.ecol + 6924 adapter->stats.latecol; 6925 net_stats->tx_aborted_errors = adapter->stats.ecol; 6926 net_stats->tx_window_errors = adapter->stats.latecol; 6927 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6928 6929 /* Tx Dropped needs to be maintained elsewhere */ 6930 6931 /* Management Stats */ 6932 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6933 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6934 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6935 6936 /* OS2BMC Stats */ 6937 reg = rd32(E1000_MANC); 6938 if (reg & E1000_MANC_EN_BMC2OS) { 6939 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6940 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6941 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6942 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6943 } 6944 } 6945 6946 static void igb_perout(struct igb_adapter *adapter, int tsintr_tt) 6947 { 6948 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_PEROUT, tsintr_tt); 6949 struct e1000_hw *hw = &adapter->hw; 6950 struct timespec64 ts; 6951 u32 tsauxc; 6952 6953 if (pin < 0 || pin >= IGB_N_SDP) 6954 return; 6955 6956 spin_lock(&adapter->tmreg_lock); 6957 6958 if (hw->mac.type == e1000_82580 || 6959 hw->mac.type == e1000_i354 || 6960 hw->mac.type == e1000_i350) { 6961 s64 ns = timespec64_to_ns(&adapter->perout[tsintr_tt].period); 6962 u32 systiml, systimh, level_mask, level, rem; 6963 u64 systim, now; 6964 6965 /* read systim registers in sequence */ 6966 rd32(E1000_SYSTIMR); 6967 systiml = rd32(E1000_SYSTIML); 6968 systimh = rd32(E1000_SYSTIMH); 6969 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml); 6970 now = timecounter_cyc2time(&adapter->tc, systim); 6971 6972 if (pin < 2) { 6973 level_mask = (tsintr_tt == 1) ? 0x80000 : 0x40000; 6974 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0; 6975 } else { 6976 level_mask = (tsintr_tt == 1) ? 0x80 : 0x40; 6977 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0; 6978 } 6979 6980 div_u64_rem(now, ns, &rem); 6981 systim = systim + (ns - rem); 6982 6983 /* synchronize pin level with rising/falling edges */ 6984 div_u64_rem(now, ns << 1, &rem); 6985 if (rem < ns) { 6986 /* first half of period */ 6987 if (level == 0) { 6988 /* output is already low, skip this period */ 6989 systim += ns; 6990 pr_notice("igb: periodic output on %s missed falling edge\n", 6991 adapter->sdp_config[pin].name); 6992 } 6993 } else { 6994 /* second half of period */ 6995 if (level == 1) { 6996 /* output is already high, skip this period */ 6997 systim += ns; 6998 pr_notice("igb: periodic output on %s missed rising edge\n", 6999 adapter->sdp_config[pin].name); 7000 } 7001 } 7002 7003 /* for this chip family tv_sec is the upper part of the binary value, 7004 * so not seconds 7005 */ 7006 ts.tv_nsec = (u32)systim; 7007 ts.tv_sec = ((u32)(systim >> 32)) & 0xFF; 7008 } else { 7009 ts = timespec64_add(adapter->perout[tsintr_tt].start, 7010 adapter->perout[tsintr_tt].period); 7011 } 7012 7013 /* u32 conversion of tv_sec is safe until y2106 */ 7014 wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec); 7015 wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec); 7016 tsauxc = rd32(E1000_TSAUXC); 7017 tsauxc |= TSAUXC_EN_TT0; 7018 wr32(E1000_TSAUXC, tsauxc); 7019 adapter->perout[tsintr_tt].start = ts; 7020 7021 spin_unlock(&adapter->tmreg_lock); 7022 } 7023 7024 static void igb_extts(struct igb_adapter *adapter, int tsintr_tt) 7025 { 7026 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_EXTTS, tsintr_tt); 7027 int auxstmpl = (tsintr_tt == 1) ? E1000_AUXSTMPL1 : E1000_AUXSTMPL0; 7028 int auxstmph = (tsintr_tt == 1) ? E1000_AUXSTMPH1 : E1000_AUXSTMPH0; 7029 struct e1000_hw *hw = &adapter->hw; 7030 struct ptp_clock_event event; 7031 struct timespec64 ts; 7032 unsigned long flags; 7033 7034 if (pin < 0 || pin >= IGB_N_SDP) 7035 return; 7036 7037 if (hw->mac.type == e1000_82580 || 7038 hw->mac.type == e1000_i354 || 7039 hw->mac.type == e1000_i350) { 7040 u64 ns = rd32(auxstmpl); 7041 7042 ns += ((u64)(rd32(auxstmph) & 0xFF)) << 32; 7043 spin_lock_irqsave(&adapter->tmreg_lock, flags); 7044 ns = timecounter_cyc2time(&adapter->tc, ns); 7045 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 7046 ts = ns_to_timespec64(ns); 7047 } else { 7048 ts.tv_nsec = rd32(auxstmpl); 7049 ts.tv_sec = rd32(auxstmph); 7050 } 7051 7052 event.type = PTP_CLOCK_EXTTS; 7053 event.index = tsintr_tt; 7054 event.timestamp = ts.tv_sec * 1000000000ULL + ts.tv_nsec; 7055 ptp_clock_event(adapter->ptp_clock, &event); 7056 } 7057 7058 static void igb_tsync_interrupt(struct igb_adapter *adapter) 7059 { 7060 const u32 mask = (TSINTR_SYS_WRAP | E1000_TSICR_TXTS | 7061 TSINTR_TT0 | TSINTR_TT1 | 7062 TSINTR_AUTT0 | TSINTR_AUTT1); 7063 struct e1000_hw *hw = &adapter->hw; 7064 u32 tsicr = rd32(E1000_TSICR); 7065 struct ptp_clock_event event; 7066 7067 if (hw->mac.type == e1000_82580) { 7068 /* 82580 has a hardware bug that requires an explicit 7069 * write to clear the TimeSync interrupt cause. 7070 */ 7071 wr32(E1000_TSICR, tsicr & mask); 7072 } 7073 7074 if (tsicr & TSINTR_SYS_WRAP) { 7075 event.type = PTP_CLOCK_PPS; 7076 if (adapter->ptp_caps.pps) 7077 ptp_clock_event(adapter->ptp_clock, &event); 7078 } 7079 7080 if (tsicr & E1000_TSICR_TXTS) { 7081 /* retrieve hardware timestamp */ 7082 schedule_work(&adapter->ptp_tx_work); 7083 } 7084 7085 if (tsicr & TSINTR_TT0) 7086 igb_perout(adapter, 0); 7087 7088 if (tsicr & TSINTR_TT1) 7089 igb_perout(adapter, 1); 7090 7091 if (tsicr & TSINTR_AUTT0) 7092 igb_extts(adapter, 0); 7093 7094 if (tsicr & TSINTR_AUTT1) 7095 igb_extts(adapter, 1); 7096 } 7097 7098 static irqreturn_t igb_msix_other(int irq, void *data) 7099 { 7100 struct igb_adapter *adapter = data; 7101 struct e1000_hw *hw = &adapter->hw; 7102 u32 icr = rd32(E1000_ICR); 7103 /* reading ICR causes bit 31 of EICR to be cleared */ 7104 7105 if (icr & E1000_ICR_DRSTA) 7106 schedule_work(&adapter->reset_task); 7107 7108 if (icr & E1000_ICR_DOUTSYNC) { 7109 /* HW is reporting DMA is out of sync */ 7110 adapter->stats.doosync++; 7111 /* The DMA Out of Sync is also indication of a spoof event 7112 * in IOV mode. Check the Wrong VM Behavior register to 7113 * see if it is really a spoof event. 7114 */ 7115 igb_check_wvbr(adapter); 7116 } 7117 7118 /* Check for a mailbox event */ 7119 if (icr & E1000_ICR_VMMB) 7120 igb_msg_task(adapter); 7121 7122 if (icr & E1000_ICR_LSC) { 7123 hw->mac.get_link_status = 1; 7124 /* guard against interrupt when we're going down */ 7125 if (!test_bit(__IGB_DOWN, &adapter->state)) 7126 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7127 } 7128 7129 if (icr & E1000_ICR_TS) 7130 igb_tsync_interrupt(adapter); 7131 7132 wr32(E1000_EIMS, adapter->eims_other); 7133 7134 return IRQ_HANDLED; 7135 } 7136 7137 static void igb_write_itr(struct igb_q_vector *q_vector) 7138 { 7139 struct igb_adapter *adapter = q_vector->adapter; 7140 u32 itr_val = q_vector->itr_val & 0x7FFC; 7141 7142 if (!q_vector->set_itr) 7143 return; 7144 7145 if (!itr_val) 7146 itr_val = 0x4; 7147 7148 if (adapter->hw.mac.type == e1000_82575) 7149 itr_val |= itr_val << 16; 7150 else 7151 itr_val |= E1000_EITR_CNT_IGNR; 7152 7153 writel(itr_val, q_vector->itr_register); 7154 q_vector->set_itr = 0; 7155 } 7156 7157 static irqreturn_t igb_msix_ring(int irq, void *data) 7158 { 7159 struct igb_q_vector *q_vector = data; 7160 7161 /* Write the ITR value calculated from the previous interrupt. */ 7162 igb_write_itr(q_vector); 7163 7164 napi_schedule(&q_vector->napi); 7165 7166 return IRQ_HANDLED; 7167 } 7168 7169 #ifdef CONFIG_IGB_DCA 7170 static void igb_update_tx_dca(struct igb_adapter *adapter, 7171 struct igb_ring *tx_ring, 7172 int cpu) 7173 { 7174 struct e1000_hw *hw = &adapter->hw; 7175 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 7176 7177 if (hw->mac.type != e1000_82575) 7178 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 7179 7180 /* We can enable relaxed ordering for reads, but not writes when 7181 * DCA is enabled. This is due to a known issue in some chipsets 7182 * which will cause the DCA tag to be cleared. 7183 */ 7184 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 7185 E1000_DCA_TXCTRL_DATA_RRO_EN | 7186 E1000_DCA_TXCTRL_DESC_DCA_EN; 7187 7188 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 7189 } 7190 7191 static void igb_update_rx_dca(struct igb_adapter *adapter, 7192 struct igb_ring *rx_ring, 7193 int cpu) 7194 { 7195 struct e1000_hw *hw = &adapter->hw; 7196 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 7197 7198 if (hw->mac.type != e1000_82575) 7199 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 7200 7201 /* We can enable relaxed ordering for reads, but not writes when 7202 * DCA is enabled. This is due to a known issue in some chipsets 7203 * which will cause the DCA tag to be cleared. 7204 */ 7205 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 7206 E1000_DCA_RXCTRL_DESC_DCA_EN; 7207 7208 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 7209 } 7210 7211 static void igb_update_dca(struct igb_q_vector *q_vector) 7212 { 7213 struct igb_adapter *adapter = q_vector->adapter; 7214 int cpu = get_cpu(); 7215 7216 if (q_vector->cpu == cpu) 7217 goto out_no_update; 7218 7219 if (q_vector->tx.ring) 7220 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 7221 7222 if (q_vector->rx.ring) 7223 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 7224 7225 q_vector->cpu = cpu; 7226 out_no_update: 7227 put_cpu(); 7228 } 7229 7230 static void igb_setup_dca(struct igb_adapter *adapter) 7231 { 7232 struct e1000_hw *hw = &adapter->hw; 7233 int i; 7234 7235 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 7236 return; 7237 7238 /* Always use CB2 mode, difference is masked in the CB driver. */ 7239 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 7240 7241 for (i = 0; i < adapter->num_q_vectors; i++) { 7242 adapter->q_vector[i]->cpu = -1; 7243 igb_update_dca(adapter->q_vector[i]); 7244 } 7245 } 7246 7247 static int __igb_notify_dca(struct device *dev, void *data) 7248 { 7249 struct net_device *netdev = dev_get_drvdata(dev); 7250 struct igb_adapter *adapter = netdev_priv(netdev); 7251 struct pci_dev *pdev = adapter->pdev; 7252 struct e1000_hw *hw = &adapter->hw; 7253 unsigned long event = *(unsigned long *)data; 7254 7255 switch (event) { 7256 case DCA_PROVIDER_ADD: 7257 /* if already enabled, don't do it again */ 7258 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 7259 break; 7260 if (dca_add_requester(dev) == 0) { 7261 adapter->flags |= IGB_FLAG_DCA_ENABLED; 7262 dev_info(&pdev->dev, "DCA enabled\n"); 7263 igb_setup_dca(adapter); 7264 break; 7265 } 7266 fallthrough; /* since DCA is disabled. */ 7267 case DCA_PROVIDER_REMOVE: 7268 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 7269 /* without this a class_device is left 7270 * hanging around in the sysfs model 7271 */ 7272 dca_remove_requester(dev); 7273 dev_info(&pdev->dev, "DCA disabled\n"); 7274 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 7275 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 7276 } 7277 break; 7278 } 7279 7280 return 0; 7281 } 7282 7283 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 7284 void *p) 7285 { 7286 int ret_val; 7287 7288 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 7289 __igb_notify_dca); 7290 7291 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 7292 } 7293 #endif /* CONFIG_IGB_DCA */ 7294 7295 #ifdef CONFIG_PCI_IOV 7296 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 7297 { 7298 unsigned char mac_addr[ETH_ALEN]; 7299 7300 eth_zero_addr(mac_addr); 7301 igb_set_vf_mac(adapter, vf, mac_addr); 7302 7303 /* By default spoof check is enabled for all VFs */ 7304 adapter->vf_data[vf].spoofchk_enabled = true; 7305 7306 /* By default VFs are not trusted */ 7307 adapter->vf_data[vf].trusted = false; 7308 7309 return 0; 7310 } 7311 7312 #endif 7313 static void igb_ping_all_vfs(struct igb_adapter *adapter) 7314 { 7315 struct e1000_hw *hw = &adapter->hw; 7316 u32 ping; 7317 int i; 7318 7319 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 7320 ping = E1000_PF_CONTROL_MSG; 7321 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 7322 ping |= E1000_VT_MSGTYPE_CTS; 7323 igb_write_mbx(hw, &ping, 1, i); 7324 } 7325 } 7326 7327 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7328 { 7329 struct e1000_hw *hw = &adapter->hw; 7330 u32 vmolr = rd32(E1000_VMOLR(vf)); 7331 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7332 7333 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 7334 IGB_VF_FLAG_MULTI_PROMISC); 7335 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7336 7337 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 7338 vmolr |= E1000_VMOLR_MPME; 7339 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 7340 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 7341 } else { 7342 /* if we have hashes and we are clearing a multicast promisc 7343 * flag we need to write the hashes to the MTA as this step 7344 * was previously skipped 7345 */ 7346 if (vf_data->num_vf_mc_hashes > 30) { 7347 vmolr |= E1000_VMOLR_MPME; 7348 } else if (vf_data->num_vf_mc_hashes) { 7349 int j; 7350 7351 vmolr |= E1000_VMOLR_ROMPE; 7352 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7353 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7354 } 7355 } 7356 7357 wr32(E1000_VMOLR(vf), vmolr); 7358 7359 /* there are flags left unprocessed, likely not supported */ 7360 if (*msgbuf & E1000_VT_MSGINFO_MASK) 7361 return -EINVAL; 7362 7363 return 0; 7364 } 7365 7366 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 7367 u32 *msgbuf, u32 vf) 7368 { 7369 int n = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]); 7370 u16 *hash_list = (u16 *)&msgbuf[1]; 7371 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7372 int i; 7373 7374 /* salt away the number of multicast addresses assigned 7375 * to this VF for later use to restore when the PF multi cast 7376 * list changes 7377 */ 7378 vf_data->num_vf_mc_hashes = n; 7379 7380 /* only up to 30 hash values supported */ 7381 if (n > 30) 7382 n = 30; 7383 7384 /* store the hashes for later use */ 7385 for (i = 0; i < n; i++) 7386 vf_data->vf_mc_hashes[i] = hash_list[i]; 7387 7388 /* Flush and reset the mta with the new values */ 7389 igb_set_rx_mode(adapter->netdev); 7390 7391 return 0; 7392 } 7393 7394 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 7395 { 7396 struct e1000_hw *hw = &adapter->hw; 7397 struct vf_data_storage *vf_data; 7398 int i, j; 7399 7400 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7401 u32 vmolr = rd32(E1000_VMOLR(i)); 7402 7403 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7404 7405 vf_data = &adapter->vf_data[i]; 7406 7407 if ((vf_data->num_vf_mc_hashes > 30) || 7408 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 7409 vmolr |= E1000_VMOLR_MPME; 7410 } else if (vf_data->num_vf_mc_hashes) { 7411 vmolr |= E1000_VMOLR_ROMPE; 7412 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7413 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7414 } 7415 wr32(E1000_VMOLR(i), vmolr); 7416 } 7417 } 7418 7419 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 7420 { 7421 struct e1000_hw *hw = &adapter->hw; 7422 u32 pool_mask, vlvf_mask, i; 7423 7424 /* create mask for VF and other pools */ 7425 pool_mask = E1000_VLVF_POOLSEL_MASK; 7426 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 7427 7428 /* drop PF from pool bits */ 7429 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 7430 adapter->vfs_allocated_count); 7431 7432 /* Find the vlan filter for this id */ 7433 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 7434 u32 vlvf = rd32(E1000_VLVF(i)); 7435 u32 vfta_mask, vid, vfta; 7436 7437 /* remove the vf from the pool */ 7438 if (!(vlvf & vlvf_mask)) 7439 continue; 7440 7441 /* clear out bit from VLVF */ 7442 vlvf ^= vlvf_mask; 7443 7444 /* if other pools are present, just remove ourselves */ 7445 if (vlvf & pool_mask) 7446 goto update_vlvfb; 7447 7448 /* if PF is present, leave VFTA */ 7449 if (vlvf & E1000_VLVF_POOLSEL_MASK) 7450 goto update_vlvf; 7451 7452 vid = vlvf & E1000_VLVF_VLANID_MASK; 7453 vfta_mask = BIT(vid % 32); 7454 7455 /* clear bit from VFTA */ 7456 vfta = adapter->shadow_vfta[vid / 32]; 7457 if (vfta & vfta_mask) 7458 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 7459 update_vlvf: 7460 /* clear pool selection enable */ 7461 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7462 vlvf &= E1000_VLVF_POOLSEL_MASK; 7463 else 7464 vlvf = 0; 7465 update_vlvfb: 7466 /* clear pool bits */ 7467 wr32(E1000_VLVF(i), vlvf); 7468 } 7469 } 7470 7471 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 7472 { 7473 u32 vlvf; 7474 int idx; 7475 7476 /* short cut the special case */ 7477 if (vlan == 0) 7478 return 0; 7479 7480 /* Search for the VLAN id in the VLVF entries */ 7481 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 7482 vlvf = rd32(E1000_VLVF(idx)); 7483 if ((vlvf & VLAN_VID_MASK) == vlan) 7484 break; 7485 } 7486 7487 return idx; 7488 } 7489 7490 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 7491 { 7492 struct e1000_hw *hw = &adapter->hw; 7493 u32 bits, pf_id; 7494 int idx; 7495 7496 idx = igb_find_vlvf_entry(hw, vid); 7497 if (!idx) 7498 return; 7499 7500 /* See if any other pools are set for this VLAN filter 7501 * entry other than the PF. 7502 */ 7503 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 7504 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 7505 bits &= rd32(E1000_VLVF(idx)); 7506 7507 /* Disable the filter so this falls into the default pool. */ 7508 if (!bits) { 7509 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7510 wr32(E1000_VLVF(idx), BIT(pf_id)); 7511 else 7512 wr32(E1000_VLVF(idx), 0); 7513 } 7514 } 7515 7516 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 7517 bool add, u32 vf) 7518 { 7519 int pf_id = adapter->vfs_allocated_count; 7520 struct e1000_hw *hw = &adapter->hw; 7521 int err; 7522 7523 /* If VLAN overlaps with one the PF is currently monitoring make 7524 * sure that we are able to allocate a VLVF entry. This may be 7525 * redundant but it guarantees PF will maintain visibility to 7526 * the VLAN. 7527 */ 7528 if (add && test_bit(vid, adapter->active_vlans)) { 7529 err = igb_vfta_set(hw, vid, pf_id, true, false); 7530 if (err) 7531 return err; 7532 } 7533 7534 err = igb_vfta_set(hw, vid, vf, add, false); 7535 7536 if (add && !err) 7537 return err; 7538 7539 /* If we failed to add the VF VLAN or we are removing the VF VLAN 7540 * we may need to drop the PF pool bit in order to allow us to free 7541 * up the VLVF resources. 7542 */ 7543 if (test_bit(vid, adapter->active_vlans) || 7544 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7545 igb_update_pf_vlvf(adapter, vid); 7546 7547 return err; 7548 } 7549 7550 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 7551 { 7552 struct e1000_hw *hw = &adapter->hw; 7553 7554 if (vid) 7555 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 7556 else 7557 wr32(E1000_VMVIR(vf), 0); 7558 } 7559 7560 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7561 u16 vlan, u8 qos) 7562 { 7563 int err; 7564 7565 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7566 if (err) 7567 return err; 7568 7569 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7570 igb_set_vmolr(adapter, vf, !vlan); 7571 7572 /* revoke access to previous VLAN */ 7573 if (vlan != adapter->vf_data[vf].pf_vlan) 7574 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7575 false, vf); 7576 7577 adapter->vf_data[vf].pf_vlan = vlan; 7578 adapter->vf_data[vf].pf_qos = qos; 7579 igb_set_vf_vlan_strip(adapter, vf, true); 7580 dev_info(&adapter->pdev->dev, 7581 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7582 if (test_bit(__IGB_DOWN, &adapter->state)) { 7583 dev_warn(&adapter->pdev->dev, 7584 "The VF VLAN has been set, but the PF device is not up.\n"); 7585 dev_warn(&adapter->pdev->dev, 7586 "Bring the PF device up before attempting to use the VF device.\n"); 7587 } 7588 7589 return err; 7590 } 7591 7592 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7593 { 7594 /* Restore tagless access via VLAN 0 */ 7595 igb_set_vf_vlan(adapter, 0, true, vf); 7596 7597 igb_set_vmvir(adapter, 0, vf); 7598 igb_set_vmolr(adapter, vf, true); 7599 7600 /* Remove any PF assigned VLAN */ 7601 if (adapter->vf_data[vf].pf_vlan) 7602 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7603 false, vf); 7604 7605 adapter->vf_data[vf].pf_vlan = 0; 7606 adapter->vf_data[vf].pf_qos = 0; 7607 igb_set_vf_vlan_strip(adapter, vf, false); 7608 7609 return 0; 7610 } 7611 7612 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7613 u16 vlan, u8 qos, __be16 vlan_proto) 7614 { 7615 struct igb_adapter *adapter = netdev_priv(netdev); 7616 7617 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7618 return -EINVAL; 7619 7620 if (vlan_proto != htons(ETH_P_8021Q)) 7621 return -EPROTONOSUPPORT; 7622 7623 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7624 igb_disable_port_vlan(adapter, vf); 7625 } 7626 7627 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7628 { 7629 int add = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]); 7630 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7631 int ret; 7632 7633 if (adapter->vf_data[vf].pf_vlan) 7634 return -1; 7635 7636 /* VLAN 0 is a special case, don't allow it to be removed */ 7637 if (!vid && !add) 7638 return 0; 7639 7640 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7641 if (!ret) 7642 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7643 return ret; 7644 } 7645 7646 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7647 { 7648 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7649 7650 /* clear flags - except flag that indicates PF has set the MAC */ 7651 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7652 vf_data->last_nack = jiffies; 7653 7654 /* reset vlans for device */ 7655 igb_clear_vf_vfta(adapter, vf); 7656 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7657 igb_set_vmvir(adapter, vf_data->pf_vlan | 7658 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7659 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7660 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7661 7662 /* reset multicast table array for vf */ 7663 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7664 7665 /* Flush and reset the mta with the new values */ 7666 igb_set_rx_mode(adapter->netdev); 7667 } 7668 7669 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7670 { 7671 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7672 7673 /* clear mac address as we were hotplug removed/added */ 7674 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7675 eth_zero_addr(vf_mac); 7676 7677 /* process remaining reset events */ 7678 igb_vf_reset(adapter, vf); 7679 } 7680 7681 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7682 { 7683 struct e1000_hw *hw = &adapter->hw; 7684 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7685 u32 reg, msgbuf[3] = {}; 7686 u8 *addr = (u8 *)(&msgbuf[1]); 7687 7688 /* process all the same items cleared in a function level reset */ 7689 igb_vf_reset(adapter, vf); 7690 7691 /* set vf mac address */ 7692 igb_set_vf_mac(adapter, vf, vf_mac); 7693 7694 /* enable transmit and receive for vf */ 7695 reg = rd32(E1000_VFTE); 7696 wr32(E1000_VFTE, reg | BIT(vf)); 7697 reg = rd32(E1000_VFRE); 7698 wr32(E1000_VFRE, reg | BIT(vf)); 7699 7700 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7701 7702 /* reply to reset with ack and vf mac address */ 7703 if (!is_zero_ether_addr(vf_mac)) { 7704 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7705 memcpy(addr, vf_mac, ETH_ALEN); 7706 } else { 7707 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7708 } 7709 igb_write_mbx(hw, msgbuf, 3, vf); 7710 } 7711 7712 static void igb_flush_mac_table(struct igb_adapter *adapter) 7713 { 7714 struct e1000_hw *hw = &adapter->hw; 7715 int i; 7716 7717 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7718 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7719 eth_zero_addr(adapter->mac_table[i].addr); 7720 adapter->mac_table[i].queue = 0; 7721 igb_rar_set_index(adapter, i); 7722 } 7723 } 7724 7725 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7726 { 7727 struct e1000_hw *hw = &adapter->hw; 7728 /* do not count rar entries reserved for VFs MAC addresses */ 7729 int rar_entries = hw->mac.rar_entry_count - 7730 adapter->vfs_allocated_count; 7731 int i, count = 0; 7732 7733 for (i = 0; i < rar_entries; i++) { 7734 /* do not count default entries */ 7735 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7736 continue; 7737 7738 /* do not count "in use" entries for different queues */ 7739 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7740 (adapter->mac_table[i].queue != queue)) 7741 continue; 7742 7743 count++; 7744 } 7745 7746 return count; 7747 } 7748 7749 /* Set default MAC address for the PF in the first RAR entry */ 7750 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7751 { 7752 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7753 7754 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7755 mac_table->queue = adapter->vfs_allocated_count; 7756 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7757 7758 igb_rar_set_index(adapter, 0); 7759 } 7760 7761 /* If the filter to be added and an already existing filter express 7762 * the same address and address type, it should be possible to only 7763 * override the other configurations, for example the queue to steer 7764 * traffic. 7765 */ 7766 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7767 const u8 *addr, const u8 flags) 7768 { 7769 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7770 return true; 7771 7772 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7773 (flags & IGB_MAC_STATE_SRC_ADDR)) 7774 return false; 7775 7776 if (!ether_addr_equal(addr, entry->addr)) 7777 return false; 7778 7779 return true; 7780 } 7781 7782 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7783 * 'flags' is used to indicate what kind of match is made, match is by 7784 * default for the destination address, if matching by source address 7785 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7786 */ 7787 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7788 const u8 *addr, const u8 queue, 7789 const u8 flags) 7790 { 7791 struct e1000_hw *hw = &adapter->hw; 7792 int rar_entries = hw->mac.rar_entry_count - 7793 adapter->vfs_allocated_count; 7794 int i; 7795 7796 if (is_zero_ether_addr(addr)) 7797 return -EINVAL; 7798 7799 /* Search for the first empty entry in the MAC table. 7800 * Do not touch entries at the end of the table reserved for the VF MAC 7801 * addresses. 7802 */ 7803 for (i = 0; i < rar_entries; i++) { 7804 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7805 addr, flags)) 7806 continue; 7807 7808 ether_addr_copy(adapter->mac_table[i].addr, addr); 7809 adapter->mac_table[i].queue = queue; 7810 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7811 7812 igb_rar_set_index(adapter, i); 7813 return i; 7814 } 7815 7816 return -ENOSPC; 7817 } 7818 7819 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7820 const u8 queue) 7821 { 7822 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7823 } 7824 7825 /* Remove a MAC filter for 'addr' directing matching traffic to 7826 * 'queue', 'flags' is used to indicate what kind of match need to be 7827 * removed, match is by default for the destination address, if 7828 * matching by source address is to be removed the flag 7829 * IGB_MAC_STATE_SRC_ADDR can be used. 7830 */ 7831 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7832 const u8 *addr, const u8 queue, 7833 const u8 flags) 7834 { 7835 struct e1000_hw *hw = &adapter->hw; 7836 int rar_entries = hw->mac.rar_entry_count - 7837 adapter->vfs_allocated_count; 7838 int i; 7839 7840 if (is_zero_ether_addr(addr)) 7841 return -EINVAL; 7842 7843 /* Search for matching entry in the MAC table based on given address 7844 * and queue. Do not touch entries at the end of the table reserved 7845 * for the VF MAC addresses. 7846 */ 7847 for (i = 0; i < rar_entries; i++) { 7848 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7849 continue; 7850 if ((adapter->mac_table[i].state & flags) != flags) 7851 continue; 7852 if (adapter->mac_table[i].queue != queue) 7853 continue; 7854 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7855 continue; 7856 7857 /* When a filter for the default address is "deleted", 7858 * we return it to its initial configuration 7859 */ 7860 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7861 adapter->mac_table[i].state = 7862 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7863 adapter->mac_table[i].queue = 7864 adapter->vfs_allocated_count; 7865 } else { 7866 adapter->mac_table[i].state = 0; 7867 adapter->mac_table[i].queue = 0; 7868 eth_zero_addr(adapter->mac_table[i].addr); 7869 } 7870 7871 igb_rar_set_index(adapter, i); 7872 return 0; 7873 } 7874 7875 return -ENOENT; 7876 } 7877 7878 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7879 const u8 queue) 7880 { 7881 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7882 } 7883 7884 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7885 const u8 *addr, u8 queue, u8 flags) 7886 { 7887 struct e1000_hw *hw = &adapter->hw; 7888 7889 /* In theory, this should be supported on 82575 as well, but 7890 * that part wasn't easily accessible during development. 7891 */ 7892 if (hw->mac.type != e1000_i210) 7893 return -EOPNOTSUPP; 7894 7895 return igb_add_mac_filter_flags(adapter, addr, queue, 7896 IGB_MAC_STATE_QUEUE_STEERING | flags); 7897 } 7898 7899 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7900 const u8 *addr, u8 queue, u8 flags) 7901 { 7902 return igb_del_mac_filter_flags(adapter, addr, queue, 7903 IGB_MAC_STATE_QUEUE_STEERING | flags); 7904 } 7905 7906 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7907 { 7908 struct igb_adapter *adapter = netdev_priv(netdev); 7909 int ret; 7910 7911 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7912 7913 return min_t(int, ret, 0); 7914 } 7915 7916 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7917 { 7918 struct igb_adapter *adapter = netdev_priv(netdev); 7919 7920 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7921 7922 return 0; 7923 } 7924 7925 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7926 const u32 info, const u8 *addr) 7927 { 7928 struct pci_dev *pdev = adapter->pdev; 7929 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7930 struct vf_mac_filter *entry; 7931 bool found = false; 7932 int ret = 0; 7933 7934 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7935 !vf_data->trusted) { 7936 dev_warn(&pdev->dev, 7937 "VF %d requested MAC filter but is administratively denied\n", 7938 vf); 7939 return -EINVAL; 7940 } 7941 if (!is_valid_ether_addr(addr)) { 7942 dev_warn(&pdev->dev, 7943 "VF %d attempted to set invalid MAC filter\n", 7944 vf); 7945 return -EINVAL; 7946 } 7947 7948 switch (info) { 7949 case E1000_VF_MAC_FILTER_CLR: 7950 /* remove all unicast MAC filters related to the current VF */ 7951 list_for_each_entry(entry, &adapter->vf_macs.l, l) { 7952 if (entry->vf == vf) { 7953 entry->vf = -1; 7954 entry->free = true; 7955 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7956 } 7957 } 7958 break; 7959 case E1000_VF_MAC_FILTER_ADD: 7960 /* try to find empty slot in the list */ 7961 list_for_each_entry(entry, &adapter->vf_macs.l, l) { 7962 if (entry->free) { 7963 found = true; 7964 break; 7965 } 7966 } 7967 7968 if (found) { 7969 entry->free = false; 7970 entry->vf = vf; 7971 ether_addr_copy(entry->vf_mac, addr); 7972 7973 ret = igb_add_mac_filter(adapter, addr, vf); 7974 ret = min_t(int, ret, 0); 7975 } else { 7976 ret = -ENOSPC; 7977 } 7978 7979 if (ret == -ENOSPC) 7980 dev_warn(&pdev->dev, 7981 "VF %d has requested MAC filter but there is no space for it\n", 7982 vf); 7983 break; 7984 default: 7985 ret = -EINVAL; 7986 break; 7987 } 7988 7989 return ret; 7990 } 7991 7992 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7993 { 7994 struct pci_dev *pdev = adapter->pdev; 7995 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7996 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7997 7998 /* The VF MAC Address is stored in a packed array of bytes 7999 * starting at the second 32 bit word of the msg array 8000 */ 8001 unsigned char *addr = (unsigned char *)&msg[1]; 8002 int ret = 0; 8003 8004 if (!info) { 8005 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 8006 !vf_data->trusted) { 8007 dev_warn(&pdev->dev, 8008 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 8009 vf); 8010 return -EINVAL; 8011 } 8012 8013 if (!is_valid_ether_addr(addr)) { 8014 dev_warn(&pdev->dev, 8015 "VF %d attempted to set invalid MAC\n", 8016 vf); 8017 return -EINVAL; 8018 } 8019 8020 ret = igb_set_vf_mac(adapter, vf, addr); 8021 } else { 8022 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 8023 } 8024 8025 return ret; 8026 } 8027 8028 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 8029 { 8030 struct e1000_hw *hw = &adapter->hw; 8031 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 8032 u32 msg = E1000_VT_MSGTYPE_NACK; 8033 8034 /* if device isn't clear to send it shouldn't be reading either */ 8035 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 8036 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 8037 igb_write_mbx(hw, &msg, 1, vf); 8038 vf_data->last_nack = jiffies; 8039 } 8040 } 8041 8042 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 8043 { 8044 struct pci_dev *pdev = adapter->pdev; 8045 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 8046 struct e1000_hw *hw = &adapter->hw; 8047 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 8048 s32 retval; 8049 8050 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 8051 8052 if (retval) { 8053 /* if receive failed revoke VF CTS stats and restart init */ 8054 dev_err(&pdev->dev, "Error receiving message from VF\n"); 8055 vf_data->flags &= ~IGB_VF_FLAG_CTS; 8056 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 8057 goto unlock; 8058 goto out; 8059 } 8060 8061 /* this is a message we already processed, do nothing */ 8062 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 8063 goto unlock; 8064 8065 /* until the vf completes a reset it should not be 8066 * allowed to start any configuration. 8067 */ 8068 if (msgbuf[0] == E1000_VF_RESET) { 8069 /* unlocks mailbox */ 8070 igb_vf_reset_msg(adapter, vf); 8071 return; 8072 } 8073 8074 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 8075 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 8076 goto unlock; 8077 retval = -1; 8078 goto out; 8079 } 8080 8081 switch ((msgbuf[0] & 0xFFFF)) { 8082 case E1000_VF_SET_MAC_ADDR: 8083 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 8084 break; 8085 case E1000_VF_SET_PROMISC: 8086 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 8087 break; 8088 case E1000_VF_SET_MULTICAST: 8089 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 8090 break; 8091 case E1000_VF_SET_LPE: 8092 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 8093 break; 8094 case E1000_VF_SET_VLAN: 8095 retval = -1; 8096 if (vf_data->pf_vlan) 8097 dev_warn(&pdev->dev, 8098 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 8099 vf); 8100 else 8101 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 8102 break; 8103 default: 8104 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 8105 retval = -1; 8106 break; 8107 } 8108 8109 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 8110 out: 8111 /* notify the VF of the results of what it sent us */ 8112 if (retval) 8113 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 8114 else 8115 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 8116 8117 /* unlocks mailbox */ 8118 igb_write_mbx(hw, msgbuf, 1, vf); 8119 return; 8120 8121 unlock: 8122 igb_unlock_mbx(hw, vf); 8123 } 8124 8125 static void igb_msg_task(struct igb_adapter *adapter) 8126 { 8127 struct e1000_hw *hw = &adapter->hw; 8128 unsigned long flags; 8129 u32 vf; 8130 8131 spin_lock_irqsave(&adapter->vfs_lock, flags); 8132 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 8133 /* process any reset requests */ 8134 if (!igb_check_for_rst(hw, vf)) 8135 igb_vf_reset_event(adapter, vf); 8136 8137 /* process any messages pending */ 8138 if (!igb_check_for_msg(hw, vf)) 8139 igb_rcv_msg_from_vf(adapter, vf); 8140 8141 /* process any acks */ 8142 if (!igb_check_for_ack(hw, vf)) 8143 igb_rcv_ack_from_vf(adapter, vf); 8144 } 8145 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 8146 } 8147 8148 /** 8149 * igb_set_uta - Set unicast filter table address 8150 * @adapter: board private structure 8151 * @set: boolean indicating if we are setting or clearing bits 8152 * 8153 * The unicast table address is a register array of 32-bit registers. 8154 * The table is meant to be used in a way similar to how the MTA is used 8155 * however due to certain limitations in the hardware it is necessary to 8156 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 8157 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 8158 **/ 8159 static void igb_set_uta(struct igb_adapter *adapter, bool set) 8160 { 8161 struct e1000_hw *hw = &adapter->hw; 8162 u32 uta = set ? ~0 : 0; 8163 int i; 8164 8165 /* we only need to do this if VMDq is enabled */ 8166 if (!adapter->vfs_allocated_count) 8167 return; 8168 8169 for (i = hw->mac.uta_reg_count; i--;) 8170 array_wr32(E1000_UTA, i, uta); 8171 } 8172 8173 /** 8174 * igb_intr_msi - Interrupt Handler 8175 * @irq: interrupt number 8176 * @data: pointer to a network interface device structure 8177 **/ 8178 static irqreturn_t igb_intr_msi(int irq, void *data) 8179 { 8180 struct igb_adapter *adapter = data; 8181 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8182 struct e1000_hw *hw = &adapter->hw; 8183 /* read ICR disables interrupts using IAM */ 8184 u32 icr = rd32(E1000_ICR); 8185 8186 igb_write_itr(q_vector); 8187 8188 if (icr & E1000_ICR_DRSTA) 8189 schedule_work(&adapter->reset_task); 8190 8191 if (icr & E1000_ICR_DOUTSYNC) { 8192 /* HW is reporting DMA is out of sync */ 8193 adapter->stats.doosync++; 8194 } 8195 8196 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8197 hw->mac.get_link_status = 1; 8198 if (!test_bit(__IGB_DOWN, &adapter->state)) 8199 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8200 } 8201 8202 if (icr & E1000_ICR_TS) 8203 igb_tsync_interrupt(adapter); 8204 8205 napi_schedule(&q_vector->napi); 8206 8207 return IRQ_HANDLED; 8208 } 8209 8210 /** 8211 * igb_intr - Legacy Interrupt Handler 8212 * @irq: interrupt number 8213 * @data: pointer to a network interface device structure 8214 **/ 8215 static irqreturn_t igb_intr(int irq, void *data) 8216 { 8217 struct igb_adapter *adapter = data; 8218 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8219 struct e1000_hw *hw = &adapter->hw; 8220 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 8221 * need for the IMC write 8222 */ 8223 u32 icr = rd32(E1000_ICR); 8224 8225 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 8226 * not set, then the adapter didn't send an interrupt 8227 */ 8228 if (!(icr & E1000_ICR_INT_ASSERTED)) 8229 return IRQ_NONE; 8230 8231 igb_write_itr(q_vector); 8232 8233 if (icr & E1000_ICR_DRSTA) 8234 schedule_work(&adapter->reset_task); 8235 8236 if (icr & E1000_ICR_DOUTSYNC) { 8237 /* HW is reporting DMA is out of sync */ 8238 adapter->stats.doosync++; 8239 } 8240 8241 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8242 hw->mac.get_link_status = 1; 8243 /* guard against interrupt when we're going down */ 8244 if (!test_bit(__IGB_DOWN, &adapter->state)) 8245 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8246 } 8247 8248 if (icr & E1000_ICR_TS) 8249 igb_tsync_interrupt(adapter); 8250 8251 napi_schedule(&q_vector->napi); 8252 8253 return IRQ_HANDLED; 8254 } 8255 8256 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 8257 { 8258 struct igb_adapter *adapter = q_vector->adapter; 8259 struct e1000_hw *hw = &adapter->hw; 8260 8261 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 8262 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 8263 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 8264 igb_set_itr(q_vector); 8265 else 8266 igb_update_ring_itr(q_vector); 8267 } 8268 8269 if (!test_bit(__IGB_DOWN, &adapter->state)) { 8270 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8271 wr32(E1000_EIMS, q_vector->eims_value); 8272 else 8273 igb_irq_enable(adapter); 8274 } 8275 } 8276 8277 /** 8278 * igb_poll - NAPI Rx polling callback 8279 * @napi: napi polling structure 8280 * @budget: count of how many packets we should handle 8281 **/ 8282 static int igb_poll(struct napi_struct *napi, int budget) 8283 { 8284 struct igb_q_vector *q_vector = container_of(napi, 8285 struct igb_q_vector, 8286 napi); 8287 struct xsk_buff_pool *xsk_pool; 8288 bool clean_complete = true; 8289 int work_done = 0; 8290 8291 #ifdef CONFIG_IGB_DCA 8292 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 8293 igb_update_dca(q_vector); 8294 #endif 8295 if (q_vector->tx.ring) 8296 clean_complete = igb_clean_tx_irq(q_vector, budget); 8297 8298 if (q_vector->rx.ring) { 8299 int cleaned; 8300 8301 xsk_pool = READ_ONCE(q_vector->rx.ring->xsk_pool); 8302 cleaned = xsk_pool ? 8303 igb_clean_rx_irq_zc(q_vector, xsk_pool, budget) : 8304 igb_clean_rx_irq(q_vector, budget); 8305 8306 work_done += cleaned; 8307 if (cleaned >= budget) 8308 clean_complete = false; 8309 } 8310 8311 /* If all work not completed, return budget and keep polling */ 8312 if (!clean_complete) 8313 return budget; 8314 8315 /* Exit the polling mode, but don't re-enable interrupts if stack might 8316 * poll us due to busy-polling 8317 */ 8318 if (likely(napi_complete_done(napi, work_done))) 8319 igb_ring_irq_enable(q_vector); 8320 8321 return work_done; 8322 } 8323 8324 /** 8325 * igb_clean_tx_irq - Reclaim resources after transmit completes 8326 * @q_vector: pointer to q_vector containing needed info 8327 * @napi_budget: Used to determine if we are in netpoll 8328 * 8329 * returns true if ring is completely cleaned 8330 **/ 8331 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 8332 { 8333 unsigned int total_bytes = 0, total_packets = 0; 8334 struct igb_adapter *adapter = q_vector->adapter; 8335 unsigned int budget = q_vector->tx.work_limit; 8336 struct igb_ring *tx_ring = q_vector->tx.ring; 8337 unsigned int i = tx_ring->next_to_clean; 8338 union e1000_adv_tx_desc *tx_desc; 8339 struct igb_tx_buffer *tx_buffer; 8340 struct xsk_buff_pool *xsk_pool; 8341 int cpu = smp_processor_id(); 8342 bool xsk_xmit_done = true; 8343 struct netdev_queue *nq; 8344 u32 xsk_frames = 0; 8345 8346 if (test_bit(__IGB_DOWN, &adapter->state)) 8347 return true; 8348 8349 tx_buffer = &tx_ring->tx_buffer_info[i]; 8350 tx_desc = IGB_TX_DESC(tx_ring, i); 8351 i -= tx_ring->count; 8352 8353 do { 8354 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 8355 8356 /* if next_to_watch is not set then there is no work pending */ 8357 if (!eop_desc) 8358 break; 8359 8360 /* prevent any other reads prior to eop_desc */ 8361 smp_rmb(); 8362 8363 /* if DD is not set pending work has not been completed */ 8364 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 8365 break; 8366 8367 /* clear next_to_watch to prevent false hangs */ 8368 tx_buffer->next_to_watch = NULL; 8369 8370 /* update the statistics for this packet */ 8371 total_bytes += tx_buffer->bytecount; 8372 total_packets += tx_buffer->gso_segs; 8373 8374 /* free the skb */ 8375 if (tx_buffer->type == IGB_TYPE_SKB) { 8376 napi_consume_skb(tx_buffer->skb, napi_budget); 8377 } else if (tx_buffer->type == IGB_TYPE_XDP) { 8378 xdp_return_frame(tx_buffer->xdpf); 8379 } else if (tx_buffer->type == IGB_TYPE_XSK) { 8380 xsk_frames++; 8381 goto skip_for_xsk; 8382 } 8383 8384 /* unmap skb header data */ 8385 dma_unmap_single(tx_ring->dev, 8386 dma_unmap_addr(tx_buffer, dma), 8387 dma_unmap_len(tx_buffer, len), 8388 DMA_TO_DEVICE); 8389 8390 /* clear tx_buffer data */ 8391 dma_unmap_len_set(tx_buffer, len, 0); 8392 8393 /* clear last DMA location and unmap remaining buffers */ 8394 while (tx_desc != eop_desc) { 8395 tx_buffer++; 8396 tx_desc++; 8397 i++; 8398 if (unlikely(!i)) { 8399 i -= tx_ring->count; 8400 tx_buffer = tx_ring->tx_buffer_info; 8401 tx_desc = IGB_TX_DESC(tx_ring, 0); 8402 } 8403 8404 /* unmap any remaining paged data */ 8405 if (dma_unmap_len(tx_buffer, len)) { 8406 dma_unmap_page(tx_ring->dev, 8407 dma_unmap_addr(tx_buffer, dma), 8408 dma_unmap_len(tx_buffer, len), 8409 DMA_TO_DEVICE); 8410 dma_unmap_len_set(tx_buffer, len, 0); 8411 } 8412 } 8413 8414 skip_for_xsk: 8415 /* move us one more past the eop_desc for start of next pkt */ 8416 tx_buffer++; 8417 tx_desc++; 8418 i++; 8419 if (unlikely(!i)) { 8420 i -= tx_ring->count; 8421 tx_buffer = tx_ring->tx_buffer_info; 8422 tx_desc = IGB_TX_DESC(tx_ring, 0); 8423 } 8424 8425 /* issue prefetch for next Tx descriptor */ 8426 prefetch(tx_desc); 8427 8428 /* update budget accounting */ 8429 budget--; 8430 } while (likely(budget)); 8431 8432 netdev_tx_completed_queue(txring_txq(tx_ring), 8433 total_packets, total_bytes); 8434 i += tx_ring->count; 8435 tx_ring->next_to_clean = i; 8436 u64_stats_update_begin(&tx_ring->tx_syncp); 8437 tx_ring->tx_stats.bytes += total_bytes; 8438 tx_ring->tx_stats.packets += total_packets; 8439 u64_stats_update_end(&tx_ring->tx_syncp); 8440 q_vector->tx.total_bytes += total_bytes; 8441 q_vector->tx.total_packets += total_packets; 8442 8443 xsk_pool = READ_ONCE(tx_ring->xsk_pool); 8444 if (xsk_pool) { 8445 if (xsk_frames) 8446 xsk_tx_completed(xsk_pool, xsk_frames); 8447 if (xsk_uses_need_wakeup(xsk_pool)) 8448 xsk_set_tx_need_wakeup(xsk_pool); 8449 8450 nq = txring_txq(tx_ring); 8451 __netif_tx_lock(nq, cpu); 8452 /* Avoid transmit queue timeout since we share it with the slow path */ 8453 txq_trans_cond_update(nq); 8454 xsk_xmit_done = igb_xmit_zc(tx_ring, xsk_pool); 8455 __netif_tx_unlock(nq); 8456 } 8457 8458 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 8459 struct e1000_hw *hw = &adapter->hw; 8460 8461 /* Detect a transmit hang in hardware, this serializes the 8462 * check with the clearing of time_stamp and movement of i 8463 */ 8464 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 8465 if (tx_buffer->next_to_watch && 8466 time_after(jiffies, tx_buffer->time_stamp + 8467 (adapter->tx_timeout_factor * HZ)) && 8468 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 8469 8470 /* detected Tx unit hang */ 8471 dev_err(tx_ring->dev, 8472 "Detected Tx Unit Hang\n" 8473 " Tx Queue <%d>\n" 8474 " TDH <%x>\n" 8475 " TDT <%x>\n" 8476 " next_to_use <%x>\n" 8477 " next_to_clean <%x>\n" 8478 "buffer_info[next_to_clean]\n" 8479 " time_stamp <%lx>\n" 8480 " next_to_watch <%p>\n" 8481 " jiffies <%lx>\n" 8482 " desc.status <%x>\n", 8483 tx_ring->queue_index, 8484 rd32(E1000_TDH(tx_ring->reg_idx)), 8485 readl(tx_ring->tail), 8486 tx_ring->next_to_use, 8487 tx_ring->next_to_clean, 8488 tx_buffer->time_stamp, 8489 tx_buffer->next_to_watch, 8490 jiffies, 8491 tx_buffer->next_to_watch->wb.status); 8492 netif_stop_subqueue(tx_ring->netdev, 8493 tx_ring->queue_index); 8494 8495 /* we are about to reset, no point in enabling stuff */ 8496 return true; 8497 } 8498 } 8499 8500 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 8501 if (unlikely(total_packets && 8502 netif_carrier_ok(tx_ring->netdev) && 8503 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 8504 /* Make sure that anybody stopping the queue after this 8505 * sees the new next_to_clean. 8506 */ 8507 smp_mb(); 8508 if (__netif_subqueue_stopped(tx_ring->netdev, 8509 tx_ring->queue_index) && 8510 !(test_bit(__IGB_DOWN, &adapter->state))) { 8511 netif_wake_subqueue(tx_ring->netdev, 8512 tx_ring->queue_index); 8513 8514 u64_stats_update_begin(&tx_ring->tx_syncp); 8515 tx_ring->tx_stats.restart_queue++; 8516 u64_stats_update_end(&tx_ring->tx_syncp); 8517 } 8518 } 8519 8520 return !!budget && xsk_xmit_done; 8521 } 8522 8523 /** 8524 * igb_reuse_rx_page - page flip buffer and store it back on the ring 8525 * @rx_ring: rx descriptor ring to store buffers on 8526 * @old_buff: donor buffer to have page reused 8527 * 8528 * Synchronizes page for reuse by the adapter 8529 **/ 8530 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 8531 struct igb_rx_buffer *old_buff) 8532 { 8533 struct igb_rx_buffer *new_buff; 8534 u16 nta = rx_ring->next_to_alloc; 8535 8536 new_buff = &rx_ring->rx_buffer_info[nta]; 8537 8538 /* update, and store next to alloc */ 8539 nta++; 8540 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 8541 8542 /* Transfer page from old buffer to new buffer. 8543 * Move each member individually to avoid possible store 8544 * forwarding stalls. 8545 */ 8546 new_buff->dma = old_buff->dma; 8547 new_buff->page = old_buff->page; 8548 new_buff->page_offset = old_buff->page_offset; 8549 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 8550 } 8551 8552 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 8553 int rx_buf_pgcnt) 8554 { 8555 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 8556 struct page *page = rx_buffer->page; 8557 8558 /* avoid re-using remote and pfmemalloc pages */ 8559 if (!dev_page_is_reusable(page)) 8560 return false; 8561 8562 #if (PAGE_SIZE < 8192) 8563 /* if we are only owner of page we can reuse it */ 8564 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1)) 8565 return false; 8566 #else 8567 #define IGB_LAST_OFFSET \ 8568 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 8569 8570 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 8571 return false; 8572 #endif 8573 8574 /* If we have drained the page fragment pool we need to update 8575 * the pagecnt_bias and page count so that we fully restock the 8576 * number of references the driver holds. 8577 */ 8578 if (unlikely(pagecnt_bias == 1)) { 8579 page_ref_add(page, USHRT_MAX - 1); 8580 rx_buffer->pagecnt_bias = USHRT_MAX; 8581 } 8582 8583 return true; 8584 } 8585 8586 /** 8587 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 8588 * @rx_ring: rx descriptor ring to transact packets on 8589 * @rx_buffer: buffer containing page to add 8590 * @skb: sk_buff to place the data into 8591 * @size: size of buffer to be added 8592 * 8593 * This function will add the data contained in rx_buffer->page to the skb. 8594 **/ 8595 static void igb_add_rx_frag(struct igb_ring *rx_ring, 8596 struct igb_rx_buffer *rx_buffer, 8597 struct sk_buff *skb, 8598 unsigned int size) 8599 { 8600 #if (PAGE_SIZE < 8192) 8601 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8602 #else 8603 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8604 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8605 SKB_DATA_ALIGN(size); 8606 #endif 8607 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8608 rx_buffer->page_offset, size, truesize); 8609 #if (PAGE_SIZE < 8192) 8610 rx_buffer->page_offset ^= truesize; 8611 #else 8612 rx_buffer->page_offset += truesize; 8613 #endif 8614 } 8615 8616 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8617 struct igb_rx_buffer *rx_buffer, 8618 struct xdp_buff *xdp, 8619 ktime_t timestamp) 8620 { 8621 #if (PAGE_SIZE < 8192) 8622 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8623 #else 8624 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 8625 xdp->data_hard_start); 8626 #endif 8627 unsigned int size = xdp->data_end - xdp->data; 8628 unsigned int headlen; 8629 struct sk_buff *skb; 8630 8631 /* prefetch first cache line of first page */ 8632 net_prefetch(xdp->data); 8633 8634 /* allocate a skb to store the frags */ 8635 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8636 if (unlikely(!skb)) 8637 return NULL; 8638 8639 if (timestamp) 8640 skb_hwtstamps(skb)->hwtstamp = timestamp; 8641 8642 /* Determine available headroom for copy */ 8643 headlen = size; 8644 if (headlen > IGB_RX_HDR_LEN) 8645 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN); 8646 8647 /* align pull length to size of long to optimize memcpy performance */ 8648 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long))); 8649 8650 /* update all of the pointers */ 8651 size -= headlen; 8652 if (size) { 8653 skb_add_rx_frag(skb, 0, rx_buffer->page, 8654 (xdp->data + headlen) - page_address(rx_buffer->page), 8655 size, truesize); 8656 #if (PAGE_SIZE < 8192) 8657 rx_buffer->page_offset ^= truesize; 8658 #else 8659 rx_buffer->page_offset += truesize; 8660 #endif 8661 } else { 8662 rx_buffer->pagecnt_bias++; 8663 } 8664 8665 return skb; 8666 } 8667 8668 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8669 struct igb_rx_buffer *rx_buffer, 8670 struct xdp_buff *xdp, 8671 ktime_t timestamp) 8672 { 8673 #if (PAGE_SIZE < 8192) 8674 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8675 #else 8676 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8677 SKB_DATA_ALIGN(xdp->data_end - 8678 xdp->data_hard_start); 8679 #endif 8680 unsigned int metasize = xdp->data - xdp->data_meta; 8681 struct sk_buff *skb; 8682 8683 /* prefetch first cache line of first page */ 8684 net_prefetch(xdp->data_meta); 8685 8686 /* build an skb around the page buffer */ 8687 skb = napi_build_skb(xdp->data_hard_start, truesize); 8688 if (unlikely(!skb)) 8689 return NULL; 8690 8691 /* update pointers within the skb to store the data */ 8692 skb_reserve(skb, xdp->data - xdp->data_hard_start); 8693 __skb_put(skb, xdp->data_end - xdp->data); 8694 8695 if (metasize) 8696 skb_metadata_set(skb, metasize); 8697 8698 if (timestamp) 8699 skb_hwtstamps(skb)->hwtstamp = timestamp; 8700 8701 /* update buffer offset */ 8702 #if (PAGE_SIZE < 8192) 8703 rx_buffer->page_offset ^= truesize; 8704 #else 8705 rx_buffer->page_offset += truesize; 8706 #endif 8707 8708 return skb; 8709 } 8710 8711 static int igb_run_xdp(struct igb_adapter *adapter, struct igb_ring *rx_ring, 8712 struct xdp_buff *xdp) 8713 { 8714 int err, result = IGB_XDP_PASS; 8715 struct bpf_prog *xdp_prog; 8716 u32 act; 8717 8718 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 8719 8720 if (!xdp_prog) 8721 goto xdp_out; 8722 8723 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 8724 8725 act = bpf_prog_run_xdp(xdp_prog, xdp); 8726 switch (act) { 8727 case XDP_PASS: 8728 break; 8729 case XDP_TX: 8730 result = igb_xdp_xmit_back(adapter, xdp); 8731 if (result == IGB_XDP_CONSUMED) 8732 goto out_failure; 8733 break; 8734 case XDP_REDIRECT: 8735 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 8736 if (err) 8737 goto out_failure; 8738 result = IGB_XDP_REDIR; 8739 break; 8740 default: 8741 bpf_warn_invalid_xdp_action(adapter->netdev, xdp_prog, act); 8742 fallthrough; 8743 case XDP_ABORTED: 8744 out_failure: 8745 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 8746 fallthrough; 8747 case XDP_DROP: 8748 result = IGB_XDP_CONSUMED; 8749 break; 8750 } 8751 xdp_out: 8752 return result; 8753 } 8754 8755 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring, 8756 unsigned int size) 8757 { 8758 unsigned int truesize; 8759 8760 #if (PAGE_SIZE < 8192) 8761 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 8762 #else 8763 truesize = ring_uses_build_skb(rx_ring) ? 8764 SKB_DATA_ALIGN(IGB_SKB_PAD + size) + 8765 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 8766 SKB_DATA_ALIGN(size); 8767 #endif 8768 return truesize; 8769 } 8770 8771 static void igb_rx_buffer_flip(struct igb_ring *rx_ring, 8772 struct igb_rx_buffer *rx_buffer, 8773 unsigned int size) 8774 { 8775 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size); 8776 #if (PAGE_SIZE < 8192) 8777 rx_buffer->page_offset ^= truesize; 8778 #else 8779 rx_buffer->page_offset += truesize; 8780 #endif 8781 } 8782 8783 static inline void igb_rx_checksum(struct igb_ring *ring, 8784 union e1000_adv_rx_desc *rx_desc, 8785 struct sk_buff *skb) 8786 { 8787 skb_checksum_none_assert(skb); 8788 8789 /* Ignore Checksum bit is set */ 8790 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8791 return; 8792 8793 /* Rx checksum disabled via ethtool */ 8794 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8795 return; 8796 8797 /* TCP/UDP checksum error bit is set */ 8798 if (igb_test_staterr(rx_desc, 8799 E1000_RXDEXT_STATERR_TCPE | 8800 E1000_RXDEXT_STATERR_IPE)) { 8801 /* work around errata with sctp packets where the TCPE aka 8802 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8803 * packets, (aka let the stack check the crc32c) 8804 */ 8805 if (!((skb->len == 60) && 8806 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8807 u64_stats_update_begin(&ring->rx_syncp); 8808 ring->rx_stats.csum_err++; 8809 u64_stats_update_end(&ring->rx_syncp); 8810 } 8811 /* let the stack verify checksum errors */ 8812 return; 8813 } 8814 /* It must be a TCP or UDP packet with a valid checksum */ 8815 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8816 E1000_RXD_STAT_UDPCS)) 8817 skb->ip_summed = CHECKSUM_UNNECESSARY; 8818 8819 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8820 le32_to_cpu(rx_desc->wb.upper.status_error)); 8821 } 8822 8823 static inline void igb_rx_hash(struct igb_ring *ring, 8824 union e1000_adv_rx_desc *rx_desc, 8825 struct sk_buff *skb) 8826 { 8827 if (ring->netdev->features & NETIF_F_RXHASH) 8828 skb_set_hash(skb, 8829 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8830 PKT_HASH_TYPE_L3); 8831 } 8832 8833 /** 8834 * igb_is_non_eop - process handling of non-EOP buffers 8835 * @rx_ring: Rx ring being processed 8836 * @rx_desc: Rx descriptor for current buffer 8837 * 8838 * This function updates next to clean. If the buffer is an EOP buffer 8839 * this function exits returning false, otherwise it will place the 8840 * sk_buff in the next buffer to be chained and return true indicating 8841 * that this is in fact a non-EOP buffer. 8842 **/ 8843 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8844 union e1000_adv_rx_desc *rx_desc) 8845 { 8846 u32 ntc = rx_ring->next_to_clean + 1; 8847 8848 /* fetch, update, and store next to clean */ 8849 ntc = (ntc < rx_ring->count) ? ntc : 0; 8850 rx_ring->next_to_clean = ntc; 8851 8852 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8853 8854 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8855 return false; 8856 8857 return true; 8858 } 8859 8860 /** 8861 * igb_cleanup_headers - Correct corrupted or empty headers 8862 * @rx_ring: rx descriptor ring packet is being transacted on 8863 * @rx_desc: pointer to the EOP Rx descriptor 8864 * @skb: pointer to current skb being fixed 8865 * 8866 * Address the case where we are pulling data in on pages only 8867 * and as such no data is present in the skb header. 8868 * 8869 * In addition if skb is not at least 60 bytes we need to pad it so that 8870 * it is large enough to qualify as a valid Ethernet frame. 8871 * 8872 * Returns true if an error was encountered and skb was freed. 8873 **/ 8874 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8875 union e1000_adv_rx_desc *rx_desc, 8876 struct sk_buff *skb) 8877 { 8878 if (unlikely((igb_test_staterr(rx_desc, 8879 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8880 struct net_device *netdev = rx_ring->netdev; 8881 if (!(netdev->features & NETIF_F_RXALL)) { 8882 dev_kfree_skb_any(skb); 8883 return true; 8884 } 8885 } 8886 8887 /* if eth_skb_pad returns an error the skb was freed */ 8888 if (eth_skb_pad(skb)) 8889 return true; 8890 8891 return false; 8892 } 8893 8894 /** 8895 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8896 * @rx_ring: rx descriptor ring packet is being transacted on 8897 * @rx_desc: pointer to the EOP Rx descriptor 8898 * @skb: pointer to current skb being populated 8899 * 8900 * This function checks the ring, descriptor, and packet information in 8901 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8902 * other fields within the skb. 8903 **/ 8904 void igb_process_skb_fields(struct igb_ring *rx_ring, 8905 union e1000_adv_rx_desc *rx_desc, 8906 struct sk_buff *skb) 8907 { 8908 struct net_device *dev = rx_ring->netdev; 8909 8910 igb_rx_hash(rx_ring, rx_desc, skb); 8911 8912 igb_rx_checksum(rx_ring, rx_desc, skb); 8913 8914 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8915 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8916 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8917 8918 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8919 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8920 u16 vid; 8921 8922 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8923 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8924 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan); 8925 else 8926 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8927 8928 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8929 } 8930 8931 skb_record_rx_queue(skb, rx_ring->queue_index); 8932 8933 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8934 } 8935 8936 static unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8937 { 8938 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8939 } 8940 8941 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8942 const unsigned int size, int *rx_buf_pgcnt) 8943 { 8944 struct igb_rx_buffer *rx_buffer; 8945 8946 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8947 *rx_buf_pgcnt = 8948 #if (PAGE_SIZE < 8192) 8949 page_count(rx_buffer->page); 8950 #else 8951 0; 8952 #endif 8953 prefetchw(rx_buffer->page); 8954 8955 /* we are reusing so sync this buffer for CPU use */ 8956 dma_sync_single_range_for_cpu(rx_ring->dev, 8957 rx_buffer->dma, 8958 rx_buffer->page_offset, 8959 size, 8960 DMA_FROM_DEVICE); 8961 8962 rx_buffer->pagecnt_bias--; 8963 8964 return rx_buffer; 8965 } 8966 8967 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8968 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt) 8969 { 8970 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) { 8971 /* hand second half of page back to the ring */ 8972 igb_reuse_rx_page(rx_ring, rx_buffer); 8973 } else { 8974 /* We are not reusing the buffer so unmap it and free 8975 * any references we are holding to it 8976 */ 8977 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8978 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8979 IGB_RX_DMA_ATTR); 8980 __page_frag_cache_drain(rx_buffer->page, 8981 rx_buffer->pagecnt_bias); 8982 } 8983 8984 /* clear contents of rx_buffer */ 8985 rx_buffer->page = NULL; 8986 } 8987 8988 void igb_finalize_xdp(struct igb_adapter *adapter, unsigned int status) 8989 { 8990 int cpu = smp_processor_id(); 8991 struct netdev_queue *nq; 8992 8993 if (status & IGB_XDP_REDIR) 8994 xdp_do_flush(); 8995 8996 if (status & IGB_XDP_TX) { 8997 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter); 8998 8999 nq = txring_txq(tx_ring); 9000 __netif_tx_lock(nq, cpu); 9001 igb_xdp_ring_update_tail(tx_ring); 9002 __netif_tx_unlock(nq); 9003 } 9004 } 9005 9006 void igb_update_rx_stats(struct igb_q_vector *q_vector, unsigned int packets, 9007 unsigned int bytes) 9008 { 9009 struct igb_ring *ring = q_vector->rx.ring; 9010 9011 u64_stats_update_begin(&ring->rx_syncp); 9012 ring->rx_stats.packets += packets; 9013 ring->rx_stats.bytes += bytes; 9014 u64_stats_update_end(&ring->rx_syncp); 9015 9016 q_vector->rx.total_packets += packets; 9017 q_vector->rx.total_bytes += bytes; 9018 } 9019 9020 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 9021 { 9022 unsigned int total_bytes = 0, total_packets = 0; 9023 struct igb_adapter *adapter = q_vector->adapter; 9024 struct igb_ring *rx_ring = q_vector->rx.ring; 9025 u16 cleaned_count = igb_desc_unused(rx_ring); 9026 struct sk_buff *skb = rx_ring->skb; 9027 unsigned int xdp_xmit = 0; 9028 struct xdp_buff xdp; 9029 u32 frame_sz = 0; 9030 int rx_buf_pgcnt; 9031 int xdp_res = 0; 9032 9033 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 9034 #if (PAGE_SIZE < 8192) 9035 frame_sz = igb_rx_frame_truesize(rx_ring, 0); 9036 #endif 9037 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 9038 9039 while (likely(total_packets < budget)) { 9040 union e1000_adv_rx_desc *rx_desc; 9041 struct igb_rx_buffer *rx_buffer; 9042 ktime_t timestamp = 0; 9043 int pkt_offset = 0; 9044 unsigned int size; 9045 void *pktbuf; 9046 9047 /* return some buffers to hardware, one at a time is too slow */ 9048 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 9049 igb_alloc_rx_buffers(rx_ring, cleaned_count); 9050 cleaned_count = 0; 9051 } 9052 9053 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 9054 size = le16_to_cpu(rx_desc->wb.upper.length); 9055 if (!size) 9056 break; 9057 9058 /* This memory barrier is needed to keep us from reading 9059 * any other fields out of the rx_desc until we know the 9060 * descriptor has been written back 9061 */ 9062 dma_rmb(); 9063 9064 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt); 9065 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset; 9066 9067 /* pull rx packet timestamp if available and valid */ 9068 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 9069 int ts_hdr_len; 9070 9071 ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector, 9072 pktbuf, ×tamp); 9073 9074 pkt_offset += ts_hdr_len; 9075 size -= ts_hdr_len; 9076 } 9077 9078 /* retrieve a buffer from the ring */ 9079 if (!skb) { 9080 unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring); 9081 unsigned int offset = pkt_offset + igb_rx_offset(rx_ring); 9082 9083 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 9084 xdp_buff_clear_frags_flag(&xdp); 9085 #if (PAGE_SIZE > 4096) 9086 /* At larger PAGE_SIZE, frame_sz depend on len size */ 9087 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size); 9088 #endif 9089 xdp_res = igb_run_xdp(adapter, rx_ring, &xdp); 9090 } 9091 9092 if (xdp_res) { 9093 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) { 9094 xdp_xmit |= xdp_res; 9095 igb_rx_buffer_flip(rx_ring, rx_buffer, size); 9096 } else { 9097 rx_buffer->pagecnt_bias++; 9098 } 9099 total_packets++; 9100 total_bytes += size; 9101 } else if (skb) 9102 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 9103 else if (ring_uses_build_skb(rx_ring)) 9104 skb = igb_build_skb(rx_ring, rx_buffer, &xdp, 9105 timestamp); 9106 else 9107 skb = igb_construct_skb(rx_ring, rx_buffer, 9108 &xdp, timestamp); 9109 9110 /* exit if we failed to retrieve a buffer */ 9111 if (!xdp_res && !skb) { 9112 rx_ring->rx_stats.alloc_failed++; 9113 rx_buffer->pagecnt_bias++; 9114 set_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 9115 break; 9116 } 9117 9118 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt); 9119 cleaned_count++; 9120 9121 /* fetch next buffer in frame if non-eop */ 9122 if (igb_is_non_eop(rx_ring, rx_desc)) 9123 continue; 9124 9125 /* verify the packet layout is correct */ 9126 if (xdp_res || igb_cleanup_headers(rx_ring, rx_desc, skb)) { 9127 skb = NULL; 9128 continue; 9129 } 9130 9131 /* probably a little skewed due to removing CRC */ 9132 total_bytes += skb->len; 9133 9134 /* populate checksum, timestamp, VLAN, and protocol */ 9135 igb_process_skb_fields(rx_ring, rx_desc, skb); 9136 9137 napi_gro_receive(&q_vector->napi, skb); 9138 9139 /* reset skb pointer */ 9140 skb = NULL; 9141 9142 /* update budget accounting */ 9143 total_packets++; 9144 } 9145 9146 /* place incomplete frames back on ring for completion */ 9147 rx_ring->skb = skb; 9148 9149 if (xdp_xmit) 9150 igb_finalize_xdp(adapter, xdp_xmit); 9151 9152 igb_update_rx_stats(q_vector, total_packets, total_bytes); 9153 9154 if (cleaned_count) 9155 igb_alloc_rx_buffers(rx_ring, cleaned_count); 9156 9157 return total_packets; 9158 } 9159 9160 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 9161 struct igb_rx_buffer *bi) 9162 { 9163 struct page *page = bi->page; 9164 dma_addr_t dma; 9165 9166 /* since we are recycling buffers we should seldom need to alloc */ 9167 if (likely(page)) 9168 return true; 9169 9170 /* alloc new page for storage */ 9171 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 9172 if (unlikely(!page)) { 9173 rx_ring->rx_stats.alloc_failed++; 9174 set_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 9175 return false; 9176 } 9177 9178 /* map page for use */ 9179 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 9180 igb_rx_pg_size(rx_ring), 9181 DMA_FROM_DEVICE, 9182 IGB_RX_DMA_ATTR); 9183 9184 /* if mapping failed free memory back to system since 9185 * there isn't much point in holding memory we can't use 9186 */ 9187 if (dma_mapping_error(rx_ring->dev, dma)) { 9188 __free_pages(page, igb_rx_pg_order(rx_ring)); 9189 9190 rx_ring->rx_stats.alloc_failed++; 9191 set_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 9192 return false; 9193 } 9194 9195 bi->dma = dma; 9196 bi->page = page; 9197 bi->page_offset = igb_rx_offset(rx_ring); 9198 page_ref_add(page, USHRT_MAX - 1); 9199 bi->pagecnt_bias = USHRT_MAX; 9200 9201 return true; 9202 } 9203 9204 /** 9205 * igb_alloc_rx_buffers - Replace used receive buffers 9206 * @rx_ring: rx descriptor ring to allocate new receive buffers 9207 * @cleaned_count: count of buffers to allocate 9208 **/ 9209 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 9210 { 9211 union e1000_adv_rx_desc *rx_desc; 9212 struct igb_rx_buffer *bi; 9213 u16 i = rx_ring->next_to_use; 9214 u16 bufsz; 9215 9216 /* nothing to do */ 9217 if (!cleaned_count) 9218 return; 9219 9220 rx_desc = IGB_RX_DESC(rx_ring, i); 9221 bi = &rx_ring->rx_buffer_info[i]; 9222 i -= rx_ring->count; 9223 9224 bufsz = igb_rx_bufsz(rx_ring); 9225 9226 do { 9227 if (!igb_alloc_mapped_page(rx_ring, bi)) 9228 break; 9229 9230 /* sync the buffer for use by the device */ 9231 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 9232 bi->page_offset, bufsz, 9233 DMA_FROM_DEVICE); 9234 9235 /* Refresh the desc even if buffer_addrs didn't change 9236 * because each write-back erases this info. 9237 */ 9238 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 9239 9240 rx_desc++; 9241 bi++; 9242 i++; 9243 if (unlikely(!i)) { 9244 rx_desc = IGB_RX_DESC(rx_ring, 0); 9245 bi = rx_ring->rx_buffer_info; 9246 i -= rx_ring->count; 9247 } 9248 9249 /* clear the length for the next_to_use descriptor */ 9250 rx_desc->wb.upper.length = 0; 9251 9252 cleaned_count--; 9253 } while (cleaned_count); 9254 9255 i += rx_ring->count; 9256 9257 if (rx_ring->next_to_use != i) { 9258 /* record the next descriptor to use */ 9259 rx_ring->next_to_use = i; 9260 9261 /* update next to alloc since we have filled the ring */ 9262 rx_ring->next_to_alloc = i; 9263 9264 /* Force memory writes to complete before letting h/w 9265 * know there are new descriptors to fetch. (Only 9266 * applicable for weak-ordered memory model archs, 9267 * such as IA-64). 9268 */ 9269 dma_wmb(); 9270 writel(i, rx_ring->tail); 9271 } 9272 } 9273 9274 /** 9275 * igb_mii_ioctl - 9276 * @netdev: pointer to netdev struct 9277 * @ifr: interface structure 9278 * @cmd: ioctl command to execute 9279 **/ 9280 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9281 { 9282 struct igb_adapter *adapter = netdev_priv(netdev); 9283 struct mii_ioctl_data *data = if_mii(ifr); 9284 9285 if (adapter->hw.phy.media_type != e1000_media_type_copper) 9286 return -EOPNOTSUPP; 9287 9288 switch (cmd) { 9289 case SIOCGMIIPHY: 9290 data->phy_id = adapter->hw.phy.addr; 9291 break; 9292 case SIOCGMIIREG: 9293 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9294 &data->val_out)) 9295 return -EIO; 9296 break; 9297 case SIOCSMIIREG: 9298 if (igb_write_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9299 data->val_in)) 9300 return -EIO; 9301 break; 9302 default: 9303 return -EOPNOTSUPP; 9304 } 9305 return 0; 9306 } 9307 9308 /** 9309 * igb_ioctl - 9310 * @netdev: pointer to netdev struct 9311 * @ifr: interface structure 9312 * @cmd: ioctl command to execute 9313 **/ 9314 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9315 { 9316 switch (cmd) { 9317 case SIOCGMIIPHY: 9318 case SIOCGMIIREG: 9319 case SIOCSMIIREG: 9320 return igb_mii_ioctl(netdev, ifr, cmd); 9321 default: 9322 return -EOPNOTSUPP; 9323 } 9324 } 9325 9326 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9327 { 9328 struct igb_adapter *adapter = hw->back; 9329 9330 pci_read_config_word(adapter->pdev, reg, value); 9331 } 9332 9333 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9334 { 9335 struct igb_adapter *adapter = hw->back; 9336 9337 pci_write_config_word(adapter->pdev, reg, *value); 9338 } 9339 9340 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9341 { 9342 struct igb_adapter *adapter = hw->back; 9343 9344 if (pcie_capability_read_word(adapter->pdev, reg, value)) 9345 return -E1000_ERR_CONFIG; 9346 9347 return 0; 9348 } 9349 9350 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9351 { 9352 struct igb_adapter *adapter = hw->back; 9353 9354 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 9355 return -E1000_ERR_CONFIG; 9356 9357 return 0; 9358 } 9359 9360 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 9361 { 9362 struct igb_adapter *adapter = netdev_priv(netdev); 9363 struct e1000_hw *hw = &adapter->hw; 9364 u32 ctrl, rctl; 9365 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 9366 9367 if (enable) { 9368 /* enable VLAN tag insert/strip */ 9369 ctrl = rd32(E1000_CTRL); 9370 ctrl |= E1000_CTRL_VME; 9371 wr32(E1000_CTRL, ctrl); 9372 9373 /* Disable CFI check */ 9374 rctl = rd32(E1000_RCTL); 9375 rctl &= ~E1000_RCTL_CFIEN; 9376 wr32(E1000_RCTL, rctl); 9377 } else { 9378 /* disable VLAN tag insert/strip */ 9379 ctrl = rd32(E1000_CTRL); 9380 ctrl &= ~E1000_CTRL_VME; 9381 wr32(E1000_CTRL, ctrl); 9382 } 9383 9384 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 9385 } 9386 9387 static int igb_vlan_rx_add_vid(struct net_device *netdev, 9388 __be16 proto, u16 vid) 9389 { 9390 struct igb_adapter *adapter = netdev_priv(netdev); 9391 struct e1000_hw *hw = &adapter->hw; 9392 int pf_id = adapter->vfs_allocated_count; 9393 9394 /* add the filter since PF can receive vlans w/o entry in vlvf */ 9395 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9396 igb_vfta_set(hw, vid, pf_id, true, !!vid); 9397 9398 set_bit(vid, adapter->active_vlans); 9399 9400 return 0; 9401 } 9402 9403 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 9404 __be16 proto, u16 vid) 9405 { 9406 struct igb_adapter *adapter = netdev_priv(netdev); 9407 int pf_id = adapter->vfs_allocated_count; 9408 struct e1000_hw *hw = &adapter->hw; 9409 9410 /* remove VID from filter table */ 9411 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9412 igb_vfta_set(hw, vid, pf_id, false, true); 9413 9414 clear_bit(vid, adapter->active_vlans); 9415 9416 return 0; 9417 } 9418 9419 static void igb_restore_vlan(struct igb_adapter *adapter) 9420 { 9421 u16 vid = 1; 9422 9423 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 9424 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 9425 9426 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 9427 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 9428 } 9429 9430 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 9431 { 9432 struct pci_dev *pdev = adapter->pdev; 9433 struct e1000_mac_info *mac = &adapter->hw.mac; 9434 9435 mac->autoneg = 0; 9436 9437 /* Make sure dplx is at most 1 bit and lsb of speed is not set 9438 * for the switch() below to work 9439 */ 9440 if ((spd & 1) || (dplx & ~1)) 9441 goto err_inval; 9442 9443 /* Fiber NIC's only allow 1000 gbps Full duplex 9444 * and 100Mbps Full duplex for 100baseFx sfp 9445 */ 9446 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 9447 switch (spd + dplx) { 9448 case SPEED_10 + DUPLEX_HALF: 9449 case SPEED_10 + DUPLEX_FULL: 9450 case SPEED_100 + DUPLEX_HALF: 9451 goto err_inval; 9452 default: 9453 break; 9454 } 9455 } 9456 9457 switch (spd + dplx) { 9458 case SPEED_10 + DUPLEX_HALF: 9459 mac->forced_speed_duplex = ADVERTISE_10_HALF; 9460 break; 9461 case SPEED_10 + DUPLEX_FULL: 9462 mac->forced_speed_duplex = ADVERTISE_10_FULL; 9463 break; 9464 case SPEED_100 + DUPLEX_HALF: 9465 mac->forced_speed_duplex = ADVERTISE_100_HALF; 9466 break; 9467 case SPEED_100 + DUPLEX_FULL: 9468 mac->forced_speed_duplex = ADVERTISE_100_FULL; 9469 break; 9470 case SPEED_1000 + DUPLEX_FULL: 9471 mac->autoneg = 1; 9472 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 9473 break; 9474 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 9475 default: 9476 goto err_inval; 9477 } 9478 9479 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 9480 adapter->hw.phy.mdix = AUTO_ALL_MODES; 9481 9482 return 0; 9483 9484 err_inval: 9485 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 9486 return -EINVAL; 9487 } 9488 9489 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 9490 bool runtime) 9491 { 9492 struct net_device *netdev = pci_get_drvdata(pdev); 9493 struct igb_adapter *adapter = netdev_priv(netdev); 9494 struct e1000_hw *hw = &adapter->hw; 9495 u32 ctrl, rctl, status; 9496 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 9497 bool wake; 9498 9499 rtnl_lock(); 9500 netif_device_detach(netdev); 9501 9502 if (netif_running(netdev)) 9503 __igb_close(netdev, true); 9504 9505 igb_ptp_suspend(adapter); 9506 9507 igb_clear_interrupt_scheme(adapter); 9508 rtnl_unlock(); 9509 9510 status = rd32(E1000_STATUS); 9511 if (status & E1000_STATUS_LU) 9512 wufc &= ~E1000_WUFC_LNKC; 9513 9514 if (wufc) { 9515 igb_setup_rctl(adapter); 9516 igb_set_rx_mode(netdev); 9517 9518 /* turn on all-multi mode if wake on multicast is enabled */ 9519 if (wufc & E1000_WUFC_MC) { 9520 rctl = rd32(E1000_RCTL); 9521 rctl |= E1000_RCTL_MPE; 9522 wr32(E1000_RCTL, rctl); 9523 } 9524 9525 ctrl = rd32(E1000_CTRL); 9526 ctrl |= E1000_CTRL_ADVD3WUC; 9527 wr32(E1000_CTRL, ctrl); 9528 9529 /* Allow time for pending master requests to run */ 9530 igb_disable_pcie_master(hw); 9531 9532 wr32(E1000_WUC, E1000_WUC_PME_EN); 9533 wr32(E1000_WUFC, wufc); 9534 } else { 9535 wr32(E1000_WUC, 0); 9536 wr32(E1000_WUFC, 0); 9537 } 9538 9539 wake = wufc || adapter->en_mng_pt; 9540 if (!wake) 9541 igb_power_down_link(adapter); 9542 else 9543 igb_power_up_link(adapter); 9544 9545 if (enable_wake) 9546 *enable_wake = wake; 9547 9548 /* Release control of h/w to f/w. If f/w is AMT enabled, this 9549 * would have already happened in close and is redundant. 9550 */ 9551 igb_release_hw_control(adapter); 9552 9553 pci_disable_device(pdev); 9554 9555 return 0; 9556 } 9557 9558 static void igb_deliver_wake_packet(struct net_device *netdev) 9559 { 9560 struct igb_adapter *adapter = netdev_priv(netdev); 9561 struct e1000_hw *hw = &adapter->hw; 9562 struct sk_buff *skb; 9563 u32 wupl; 9564 9565 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 9566 9567 /* WUPM stores only the first 128 bytes of the wake packet. 9568 * Read the packet only if we have the whole thing. 9569 */ 9570 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 9571 return; 9572 9573 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 9574 if (!skb) 9575 return; 9576 9577 skb_put(skb, wupl); 9578 9579 /* Ensure reads are 32-bit aligned */ 9580 wupl = roundup(wupl, 4); 9581 9582 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 9583 9584 skb->protocol = eth_type_trans(skb, netdev); 9585 netif_rx(skb); 9586 } 9587 9588 static int igb_suspend(struct device *dev) 9589 { 9590 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 9591 } 9592 9593 static int __igb_resume(struct device *dev, bool rpm) 9594 { 9595 struct pci_dev *pdev = to_pci_dev(dev); 9596 struct net_device *netdev = pci_get_drvdata(pdev); 9597 struct igb_adapter *adapter = netdev_priv(netdev); 9598 struct e1000_hw *hw = &adapter->hw; 9599 u32 err, val; 9600 9601 pci_set_power_state(pdev, PCI_D0); 9602 pci_restore_state(pdev); 9603 pci_save_state(pdev); 9604 9605 if (!pci_device_is_present(pdev)) 9606 return -ENODEV; 9607 err = pci_enable_device_mem(pdev); 9608 if (err) { 9609 dev_err(&pdev->dev, 9610 "igb: Cannot enable PCI device from suspend\n"); 9611 return err; 9612 } 9613 pci_set_master(pdev); 9614 9615 pci_enable_wake(pdev, PCI_D3hot, 0); 9616 pci_enable_wake(pdev, PCI_D3cold, 0); 9617 9618 if (igb_init_interrupt_scheme(adapter, true)) { 9619 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9620 return -ENOMEM; 9621 } 9622 9623 igb_reset(adapter); 9624 9625 /* let the f/w know that the h/w is now under the control of the 9626 * driver. 9627 */ 9628 igb_get_hw_control(adapter); 9629 9630 val = rd32(E1000_WUS); 9631 if (val & WAKE_PKT_WUS) 9632 igb_deliver_wake_packet(netdev); 9633 9634 wr32(E1000_WUS, ~0); 9635 9636 if (!rpm) 9637 rtnl_lock(); 9638 if (!err && netif_running(netdev)) 9639 err = __igb_open(netdev, true); 9640 9641 if (!err) 9642 netif_device_attach(netdev); 9643 if (!rpm) 9644 rtnl_unlock(); 9645 9646 return err; 9647 } 9648 9649 static int igb_resume(struct device *dev) 9650 { 9651 return __igb_resume(dev, false); 9652 } 9653 9654 static int igb_runtime_idle(struct device *dev) 9655 { 9656 struct net_device *netdev = dev_get_drvdata(dev); 9657 struct igb_adapter *adapter = netdev_priv(netdev); 9658 9659 if (!igb_has_link(adapter)) 9660 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 9661 9662 return -EBUSY; 9663 } 9664 9665 static int igb_runtime_suspend(struct device *dev) 9666 { 9667 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 9668 } 9669 9670 static int igb_runtime_resume(struct device *dev) 9671 { 9672 return __igb_resume(dev, true); 9673 } 9674 9675 static void igb_shutdown(struct pci_dev *pdev) 9676 { 9677 bool wake; 9678 9679 __igb_shutdown(pdev, &wake, 0); 9680 9681 if (system_state == SYSTEM_POWER_OFF) { 9682 pci_wake_from_d3(pdev, wake); 9683 pci_set_power_state(pdev, PCI_D3hot); 9684 } 9685 } 9686 9687 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 9688 { 9689 #ifdef CONFIG_PCI_IOV 9690 int err; 9691 9692 if (num_vfs == 0) { 9693 return igb_disable_sriov(dev, true); 9694 } else { 9695 err = igb_enable_sriov(dev, num_vfs, true); 9696 return err ? err : num_vfs; 9697 } 9698 #endif 9699 return 0; 9700 } 9701 9702 /** 9703 * igb_io_error_detected - called when PCI error is detected 9704 * @pdev: Pointer to PCI device 9705 * @state: The current pci connection state 9706 * 9707 * This function is called after a PCI bus error affecting 9708 * this device has been detected. 9709 **/ 9710 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9711 pci_channel_state_t state) 9712 { 9713 struct net_device *netdev = pci_get_drvdata(pdev); 9714 struct igb_adapter *adapter = netdev_priv(netdev); 9715 9716 if (state == pci_channel_io_normal) { 9717 dev_warn(&pdev->dev, "Non-correctable non-fatal error reported.\n"); 9718 return PCI_ERS_RESULT_CAN_RECOVER; 9719 } 9720 9721 netif_device_detach(netdev); 9722 9723 if (state == pci_channel_io_perm_failure) 9724 return PCI_ERS_RESULT_DISCONNECT; 9725 9726 rtnl_lock(); 9727 if (netif_running(netdev)) 9728 igb_down(adapter); 9729 rtnl_unlock(); 9730 9731 pci_disable_device(pdev); 9732 9733 /* Request a slot reset. */ 9734 return PCI_ERS_RESULT_NEED_RESET; 9735 } 9736 9737 /** 9738 * igb_io_slot_reset - called after the pci bus has been reset. 9739 * @pdev: Pointer to PCI device 9740 * 9741 * Restart the card from scratch, as if from a cold-boot. Implementation 9742 * resembles the first-half of the __igb_resume routine. 9743 **/ 9744 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9745 { 9746 struct net_device *netdev = pci_get_drvdata(pdev); 9747 struct igb_adapter *adapter = netdev_priv(netdev); 9748 struct e1000_hw *hw = &adapter->hw; 9749 pci_ers_result_t result; 9750 9751 if (pci_enable_device_mem(pdev)) { 9752 dev_err(&pdev->dev, 9753 "Cannot re-enable PCI device after reset.\n"); 9754 result = PCI_ERS_RESULT_DISCONNECT; 9755 } else { 9756 pci_set_master(pdev); 9757 pci_restore_state(pdev); 9758 pci_save_state(pdev); 9759 9760 pci_enable_wake(pdev, PCI_D3hot, 0); 9761 pci_enable_wake(pdev, PCI_D3cold, 0); 9762 9763 /* In case of PCI error, adapter lose its HW address 9764 * so we should re-assign it here. 9765 */ 9766 hw->hw_addr = adapter->io_addr; 9767 9768 igb_reset(adapter); 9769 wr32(E1000_WUS, ~0); 9770 result = PCI_ERS_RESULT_RECOVERED; 9771 } 9772 9773 return result; 9774 } 9775 9776 /** 9777 * igb_io_resume - called when traffic can start flowing again. 9778 * @pdev: Pointer to PCI device 9779 * 9780 * This callback is called when the error recovery driver tells us that 9781 * its OK to resume normal operation. Implementation resembles the 9782 * second-half of the __igb_resume routine. 9783 */ 9784 static void igb_io_resume(struct pci_dev *pdev) 9785 { 9786 struct net_device *netdev = pci_get_drvdata(pdev); 9787 struct igb_adapter *adapter = netdev_priv(netdev); 9788 9789 rtnl_lock(); 9790 if (netif_running(netdev)) { 9791 if (!test_bit(__IGB_DOWN, &adapter->state)) { 9792 dev_dbg(&pdev->dev, "Resuming from non-fatal error, do nothing.\n"); 9793 rtnl_unlock(); 9794 return; 9795 } 9796 9797 if (igb_up(adapter)) { 9798 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9799 rtnl_unlock(); 9800 return; 9801 } 9802 } 9803 rtnl_unlock(); 9804 9805 netif_device_attach(netdev); 9806 9807 /* let the f/w know that the h/w is now under the control of the 9808 * driver. 9809 */ 9810 igb_get_hw_control(adapter); 9811 } 9812 9813 /** 9814 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9815 * @adapter: Pointer to adapter structure 9816 * @index: Index of the RAR entry which need to be synced with MAC table 9817 **/ 9818 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9819 { 9820 struct e1000_hw *hw = &adapter->hw; 9821 u32 rar_low, rar_high; 9822 u8 *addr = adapter->mac_table[index].addr; 9823 9824 /* HW expects these to be in network order when they are plugged 9825 * into the registers which are little endian. In order to guarantee 9826 * that ordering we need to do an leXX_to_cpup here in order to be 9827 * ready for the byteswap that occurs with writel 9828 */ 9829 rar_low = le32_to_cpup((__le32 *)(addr)); 9830 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9831 9832 /* Indicate to hardware the Address is Valid. */ 9833 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9834 if (is_valid_ether_addr(addr)) 9835 rar_high |= E1000_RAH_AV; 9836 9837 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9838 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9839 9840 switch (hw->mac.type) { 9841 case e1000_82575: 9842 case e1000_i210: 9843 if (adapter->mac_table[index].state & 9844 IGB_MAC_STATE_QUEUE_STEERING) 9845 rar_high |= E1000_RAH_QSEL_ENABLE; 9846 9847 rar_high |= E1000_RAH_POOL_1 * 9848 adapter->mac_table[index].queue; 9849 break; 9850 default: 9851 rar_high |= E1000_RAH_POOL_1 << 9852 adapter->mac_table[index].queue; 9853 break; 9854 } 9855 } 9856 9857 wr32(E1000_RAL(index), rar_low); 9858 wrfl(); 9859 wr32(E1000_RAH(index), rar_high); 9860 wrfl(); 9861 } 9862 9863 static int igb_set_vf_mac(struct igb_adapter *adapter, 9864 int vf, unsigned char *mac_addr) 9865 { 9866 struct e1000_hw *hw = &adapter->hw; 9867 /* VF MAC addresses start at end of receive addresses and moves 9868 * towards the first, as a result a collision should not be possible 9869 */ 9870 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9871 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9872 9873 ether_addr_copy(vf_mac_addr, mac_addr); 9874 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9875 adapter->mac_table[rar_entry].queue = vf; 9876 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9877 igb_rar_set_index(adapter, rar_entry); 9878 9879 return 0; 9880 } 9881 9882 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9883 { 9884 struct igb_adapter *adapter = netdev_priv(netdev); 9885 9886 if (vf >= adapter->vfs_allocated_count) 9887 return -EINVAL; 9888 9889 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9890 * flag and allows to overwrite the MAC via VF netdev. This 9891 * is necessary to allow libvirt a way to restore the original 9892 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9893 * down a VM. 9894 */ 9895 if (is_zero_ether_addr(mac)) { 9896 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9897 dev_info(&adapter->pdev->dev, 9898 "remove administratively set MAC on VF %d\n", 9899 vf); 9900 } else if (is_valid_ether_addr(mac)) { 9901 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9902 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9903 mac, vf); 9904 dev_info(&adapter->pdev->dev, 9905 "Reload the VF driver to make this change effective."); 9906 /* Generate additional warning if PF is down */ 9907 if (test_bit(__IGB_DOWN, &adapter->state)) { 9908 dev_warn(&adapter->pdev->dev, 9909 "The VF MAC address has been set, but the PF device is not up.\n"); 9910 dev_warn(&adapter->pdev->dev, 9911 "Bring the PF device up before attempting to use the VF device.\n"); 9912 } 9913 } else { 9914 return -EINVAL; 9915 } 9916 return igb_set_vf_mac(adapter, vf, mac); 9917 } 9918 9919 static int igb_link_mbps(int internal_link_speed) 9920 { 9921 switch (internal_link_speed) { 9922 case SPEED_100: 9923 return 100; 9924 case SPEED_1000: 9925 return 1000; 9926 default: 9927 return 0; 9928 } 9929 } 9930 9931 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9932 int link_speed) 9933 { 9934 int rf_dec, rf_int; 9935 u32 bcnrc_val; 9936 9937 if (tx_rate != 0) { 9938 /* Calculate the rate factor values to set */ 9939 rf_int = link_speed / tx_rate; 9940 rf_dec = (link_speed - (rf_int * tx_rate)); 9941 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9942 tx_rate; 9943 9944 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9945 bcnrc_val |= FIELD_PREP(E1000_RTTBCNRC_RF_INT_MASK, rf_int); 9946 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9947 } else { 9948 bcnrc_val = 0; 9949 } 9950 9951 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9952 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9953 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9954 */ 9955 wr32(E1000_RTTBCNRM, 0x14); 9956 wr32(E1000_RTTBCNRC, bcnrc_val); 9957 } 9958 9959 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9960 { 9961 int actual_link_speed, i; 9962 bool reset_rate = false; 9963 9964 /* VF TX rate limit was not set or not supported */ 9965 if ((adapter->vf_rate_link_speed == 0) || 9966 (adapter->hw.mac.type != e1000_82576)) 9967 return; 9968 9969 actual_link_speed = igb_link_mbps(adapter->link_speed); 9970 if (actual_link_speed != adapter->vf_rate_link_speed) { 9971 reset_rate = true; 9972 adapter->vf_rate_link_speed = 0; 9973 dev_info(&adapter->pdev->dev, 9974 "Link speed has been changed. VF Transmit rate is disabled\n"); 9975 } 9976 9977 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9978 if (reset_rate) 9979 adapter->vf_data[i].tx_rate = 0; 9980 9981 igb_set_vf_rate_limit(&adapter->hw, i, 9982 adapter->vf_data[i].tx_rate, 9983 actual_link_speed); 9984 } 9985 } 9986 9987 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9988 int min_tx_rate, int max_tx_rate) 9989 { 9990 struct igb_adapter *adapter = netdev_priv(netdev); 9991 struct e1000_hw *hw = &adapter->hw; 9992 int actual_link_speed; 9993 9994 if (hw->mac.type != e1000_82576) 9995 return -EOPNOTSUPP; 9996 9997 if (min_tx_rate) 9998 return -EINVAL; 9999 10000 actual_link_speed = igb_link_mbps(adapter->link_speed); 10001 if ((vf >= adapter->vfs_allocated_count) || 10002 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 10003 (max_tx_rate < 0) || 10004 (max_tx_rate > actual_link_speed)) 10005 return -EINVAL; 10006 10007 adapter->vf_rate_link_speed = actual_link_speed; 10008 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 10009 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 10010 10011 return 0; 10012 } 10013 10014 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 10015 bool setting) 10016 { 10017 struct igb_adapter *adapter = netdev_priv(netdev); 10018 struct e1000_hw *hw = &adapter->hw; 10019 u32 reg_val, reg_offset; 10020 10021 if (!adapter->vfs_allocated_count) 10022 return -EOPNOTSUPP; 10023 10024 if (vf >= adapter->vfs_allocated_count) 10025 return -EINVAL; 10026 10027 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 10028 reg_val = rd32(reg_offset); 10029 if (setting) 10030 reg_val |= (BIT(vf) | 10031 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 10032 else 10033 reg_val &= ~(BIT(vf) | 10034 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 10035 wr32(reg_offset, reg_val); 10036 10037 adapter->vf_data[vf].spoofchk_enabled = setting; 10038 return 0; 10039 } 10040 10041 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 10042 { 10043 struct igb_adapter *adapter = netdev_priv(netdev); 10044 10045 if (vf >= adapter->vfs_allocated_count) 10046 return -EINVAL; 10047 if (adapter->vf_data[vf].trusted == setting) 10048 return 0; 10049 10050 adapter->vf_data[vf].trusted = setting; 10051 10052 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 10053 vf, setting ? "" : "not "); 10054 return 0; 10055 } 10056 10057 static int igb_ndo_get_vf_config(struct net_device *netdev, 10058 int vf, struct ifla_vf_info *ivi) 10059 { 10060 struct igb_adapter *adapter = netdev_priv(netdev); 10061 if (vf >= adapter->vfs_allocated_count) 10062 return -EINVAL; 10063 ivi->vf = vf; 10064 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 10065 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 10066 ivi->min_tx_rate = 0; 10067 ivi->vlan = adapter->vf_data[vf].pf_vlan; 10068 ivi->qos = adapter->vf_data[vf].pf_qos; 10069 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 10070 ivi->trusted = adapter->vf_data[vf].trusted; 10071 return 0; 10072 } 10073 10074 static void igb_vmm_control(struct igb_adapter *adapter) 10075 { 10076 struct e1000_hw *hw = &adapter->hw; 10077 u32 reg; 10078 10079 switch (hw->mac.type) { 10080 case e1000_82575: 10081 case e1000_i210: 10082 case e1000_i211: 10083 case e1000_i354: 10084 default: 10085 /* replication is not supported for 82575 */ 10086 return; 10087 case e1000_82576: 10088 /* notify HW that the MAC is adding vlan tags */ 10089 reg = rd32(E1000_DTXCTL); 10090 reg |= E1000_DTXCTL_VLAN_ADDED; 10091 wr32(E1000_DTXCTL, reg); 10092 fallthrough; 10093 case e1000_82580: 10094 /* enable replication vlan tag stripping */ 10095 reg = rd32(E1000_RPLOLR); 10096 reg |= E1000_RPLOLR_STRVLAN; 10097 wr32(E1000_RPLOLR, reg); 10098 fallthrough; 10099 case e1000_i350: 10100 /* none of the above registers are supported by i350 */ 10101 break; 10102 } 10103 10104 if (adapter->vfs_allocated_count) { 10105 igb_vmdq_set_loopback_pf(hw, true); 10106 igb_vmdq_set_replication_pf(hw, true); 10107 igb_vmdq_set_anti_spoofing_pf(hw, true, 10108 adapter->vfs_allocated_count); 10109 } else { 10110 igb_vmdq_set_loopback_pf(hw, false); 10111 igb_vmdq_set_replication_pf(hw, false); 10112 } 10113 } 10114 10115 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 10116 { 10117 struct e1000_hw *hw = &adapter->hw; 10118 u32 dmac_thr; 10119 u16 hwm; 10120 u32 reg; 10121 10122 if (hw->mac.type > e1000_82580) { 10123 if (adapter->flags & IGB_FLAG_DMAC) { 10124 /* force threshold to 0. */ 10125 wr32(E1000_DMCTXTH, 0); 10126 10127 /* DMA Coalescing high water mark needs to be greater 10128 * than the Rx threshold. Set hwm to PBA - max frame 10129 * size in 16B units, capping it at PBA - 6KB. 10130 */ 10131 hwm = 64 * (pba - 6); 10132 reg = rd32(E1000_FCRTC); 10133 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 10134 reg |= FIELD_PREP(E1000_FCRTC_RTH_COAL_MASK, hwm); 10135 wr32(E1000_FCRTC, reg); 10136 10137 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 10138 * frame size, capping it at PBA - 10KB. 10139 */ 10140 dmac_thr = pba - 10; 10141 reg = rd32(E1000_DMACR); 10142 reg &= ~E1000_DMACR_DMACTHR_MASK; 10143 reg |= FIELD_PREP(E1000_DMACR_DMACTHR_MASK, dmac_thr); 10144 10145 /* transition to L0x or L1 if available..*/ 10146 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 10147 10148 /* watchdog timer= +-1000 usec in 32usec intervals */ 10149 reg |= (1000 >> 5); 10150 10151 /* Disable BMC-to-OS Watchdog Enable */ 10152 if (hw->mac.type != e1000_i354) 10153 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 10154 wr32(E1000_DMACR, reg); 10155 10156 /* no lower threshold to disable 10157 * coalescing(smart fifb)-UTRESH=0 10158 */ 10159 wr32(E1000_DMCRTRH, 0); 10160 10161 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 10162 10163 wr32(E1000_DMCTLX, reg); 10164 10165 /* free space in tx packet buffer to wake from 10166 * DMA coal 10167 */ 10168 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 10169 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 10170 } 10171 10172 if (hw->mac.type >= e1000_i210 || 10173 (adapter->flags & IGB_FLAG_DMAC)) { 10174 reg = rd32(E1000_PCIEMISC); 10175 reg |= E1000_PCIEMISC_LX_DECISION; 10176 wr32(E1000_PCIEMISC, reg); 10177 } /* endif adapter->dmac is not disabled */ 10178 } else if (hw->mac.type == e1000_82580) { 10179 u32 reg = rd32(E1000_PCIEMISC); 10180 10181 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 10182 wr32(E1000_DMACR, 0); 10183 } 10184 } 10185 10186 /** 10187 * igb_read_i2c_byte - Reads 8 bit word over I2C 10188 * @hw: pointer to hardware structure 10189 * @byte_offset: byte offset to read 10190 * @dev_addr: device address 10191 * @data: value read 10192 * 10193 * Performs byte read operation over I2C interface at 10194 * a specified device address. 10195 **/ 10196 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10197 u8 dev_addr, u8 *data) 10198 { 10199 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10200 struct i2c_client *this_client = adapter->i2c_client; 10201 s32 status; 10202 u16 swfw_mask = 0; 10203 10204 if (!this_client) 10205 return E1000_ERR_I2C; 10206 10207 swfw_mask = E1000_SWFW_PHY0_SM; 10208 10209 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10210 return E1000_ERR_SWFW_SYNC; 10211 10212 status = i2c_smbus_read_byte_data(this_client, byte_offset); 10213 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10214 10215 if (status < 0) 10216 return E1000_ERR_I2C; 10217 else { 10218 *data = status; 10219 return 0; 10220 } 10221 } 10222 10223 /** 10224 * igb_write_i2c_byte - Writes 8 bit word over I2C 10225 * @hw: pointer to hardware structure 10226 * @byte_offset: byte offset to write 10227 * @dev_addr: device address 10228 * @data: value to write 10229 * 10230 * Performs byte write operation over I2C interface at 10231 * a specified device address. 10232 **/ 10233 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10234 u8 dev_addr, u8 data) 10235 { 10236 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10237 struct i2c_client *this_client = adapter->i2c_client; 10238 s32 status; 10239 u16 swfw_mask = E1000_SWFW_PHY0_SM; 10240 10241 if (!this_client) 10242 return E1000_ERR_I2C; 10243 10244 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10245 return E1000_ERR_SWFW_SYNC; 10246 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 10247 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10248 10249 if (status) 10250 return E1000_ERR_I2C; 10251 else 10252 return 0; 10253 10254 } 10255 10256 int igb_reinit_queues(struct igb_adapter *adapter) 10257 { 10258 struct net_device *netdev = adapter->netdev; 10259 struct pci_dev *pdev = adapter->pdev; 10260 int err = 0; 10261 10262 if (netif_running(netdev)) 10263 igb_close(netdev); 10264 10265 igb_reset_interrupt_capability(adapter); 10266 10267 if (igb_init_interrupt_scheme(adapter, true)) { 10268 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 10269 return -ENOMEM; 10270 } 10271 10272 if (netif_running(netdev)) 10273 err = igb_open(netdev); 10274 10275 return err; 10276 } 10277 10278 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 10279 { 10280 struct igb_nfc_filter *rule; 10281 10282 spin_lock(&adapter->nfc_lock); 10283 10284 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10285 igb_erase_filter(adapter, rule); 10286 10287 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 10288 igb_erase_filter(adapter, rule); 10289 10290 spin_unlock(&adapter->nfc_lock); 10291 } 10292 10293 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 10294 { 10295 struct igb_nfc_filter *rule; 10296 10297 spin_lock(&adapter->nfc_lock); 10298 10299 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10300 igb_add_filter(adapter, rule); 10301 10302 spin_unlock(&adapter->nfc_lock); 10303 } 10304 10305 static _DEFINE_DEV_PM_OPS(igb_pm_ops, igb_suspend, igb_resume, 10306 igb_runtime_suspend, igb_runtime_resume, 10307 igb_runtime_idle); 10308 10309 static struct pci_driver igb_driver = { 10310 .name = igb_driver_name, 10311 .id_table = igb_pci_tbl, 10312 .probe = igb_probe, 10313 .remove = igb_remove, 10314 .driver.pm = pm_ptr(&igb_pm_ops), 10315 .shutdown = igb_shutdown, 10316 .sriov_configure = igb_pci_sriov_configure, 10317 .err_handler = &igb_err_handler 10318 }; 10319 10320 /* igb_main.c */ 10321