1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/sctp.h> 30 #include <linux/if_ether.h> 31 #include <linux/prefetch.h> 32 #include <linux/bpf.h> 33 #include <linux/bpf_trace.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/etherdevice.h> 36 #ifdef CONFIG_IGB_DCA 37 #include <linux/dca.h> 38 #endif 39 #include <linux/i2c.h> 40 #include "igb.h" 41 42 enum queue_mode { 43 QUEUE_MODE_STRICT_PRIORITY, 44 QUEUE_MODE_STREAM_RESERVATION, 45 }; 46 47 enum tx_queue_prio { 48 TX_QUEUE_PRIO_HIGH, 49 TX_QUEUE_PRIO_LOW, 50 }; 51 52 char igb_driver_name[] = "igb"; 53 static const char igb_driver_string[] = 54 "Intel(R) Gigabit Ethernet Network Driver"; 55 static const char igb_copyright[] = 56 "Copyright (c) 2007-2014 Intel Corporation."; 57 58 static const struct e1000_info *igb_info_tbl[] = { 59 [board_82575] = &e1000_82575_info, 60 }; 61 62 static const struct pci_device_id igb_pci_tbl[] = { 63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 98 /* required last entry */ 99 {0, } 100 }; 101 102 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 103 104 static int igb_setup_all_tx_resources(struct igb_adapter *); 105 static int igb_setup_all_rx_resources(struct igb_adapter *); 106 static void igb_free_all_tx_resources(struct igb_adapter *); 107 static void igb_free_all_rx_resources(struct igb_adapter *); 108 static void igb_setup_mrqc(struct igb_adapter *); 109 static void igb_init_queue_configuration(struct igb_adapter *adapter); 110 static int igb_sw_init(struct igb_adapter *); 111 int igb_open(struct net_device *); 112 int igb_close(struct net_device *); 113 static void igb_configure(struct igb_adapter *); 114 static void igb_configure_tx(struct igb_adapter *); 115 static void igb_configure_rx(struct igb_adapter *); 116 static void igb_clean_all_tx_rings(struct igb_adapter *); 117 static void igb_clean_all_rx_rings(struct igb_adapter *); 118 static void igb_set_rx_mode(struct net_device *); 119 static void igb_update_phy_info(struct timer_list *); 120 static void igb_watchdog(struct timer_list *); 121 static void igb_watchdog_task(struct work_struct *); 122 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 123 static void igb_get_stats64(struct net_device *dev, 124 struct rtnl_link_stats64 *stats); 125 static int igb_change_mtu(struct net_device *, int); 126 static int igb_set_mac(struct net_device *, void *); 127 static void igb_set_uta(struct igb_adapter *adapter, bool set); 128 static irqreturn_t igb_intr(int irq, void *); 129 static irqreturn_t igb_intr_msi(int irq, void *); 130 static irqreturn_t igb_msix_other(int irq, void *); 131 static irqreturn_t igb_msix_ring(int irq, void *); 132 #ifdef CONFIG_IGB_DCA 133 static void igb_update_dca(struct igb_q_vector *); 134 static void igb_setup_dca(struct igb_adapter *); 135 #endif /* CONFIG_IGB_DCA */ 136 static int igb_poll(struct napi_struct *, int); 137 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 138 static int igb_clean_rx_irq(struct igb_q_vector *, int); 139 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 140 static void igb_tx_timeout(struct net_device *, unsigned int txqueue); 141 static void igb_reset_task(struct work_struct *); 142 static void igb_vlan_mode(struct net_device *netdev, 143 netdev_features_t features); 144 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 145 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 146 static void igb_restore_vlan(struct igb_adapter *); 147 static void igb_rar_set_index(struct igb_adapter *, u32); 148 static void igb_ping_all_vfs(struct igb_adapter *); 149 static void igb_msg_task(struct igb_adapter *); 150 static void igb_vmm_control(struct igb_adapter *); 151 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 152 static void igb_flush_mac_table(struct igb_adapter *); 153 static int igb_available_rars(struct igb_adapter *, u8); 154 static void igb_set_default_mac_filter(struct igb_adapter *); 155 static int igb_uc_sync(struct net_device *, const unsigned char *); 156 static int igb_uc_unsync(struct net_device *, const unsigned char *); 157 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 158 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 159 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 160 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 161 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 162 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 163 bool setting); 164 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 165 bool setting); 166 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 167 struct ifla_vf_info *ivi); 168 static void igb_check_vf_rate_limit(struct igb_adapter *); 169 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 170 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 171 172 #ifdef CONFIG_PCI_IOV 173 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 174 static int igb_disable_sriov(struct pci_dev *dev, bool reinit); 175 #endif 176 177 #ifdef CONFIG_IGB_DCA 178 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 179 static struct notifier_block dca_notifier = { 180 .notifier_call = igb_notify_dca, 181 .next = NULL, 182 .priority = 0 183 }; 184 #endif 185 #ifdef CONFIG_PCI_IOV 186 static unsigned int max_vfs; 187 module_param(max_vfs, uint, 0444); 188 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 189 #endif /* CONFIG_PCI_IOV */ 190 191 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 192 pci_channel_state_t); 193 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 194 static void igb_io_resume(struct pci_dev *); 195 196 static const struct pci_error_handlers igb_err_handler = { 197 .error_detected = igb_io_error_detected, 198 .slot_reset = igb_io_slot_reset, 199 .resume = igb_io_resume, 200 }; 201 202 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 203 204 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 205 MODULE_LICENSE("GPL v2"); 206 207 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 208 static int debug = -1; 209 module_param(debug, int, 0); 210 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 211 212 struct igb_reg_info { 213 u32 ofs; 214 char *name; 215 }; 216 217 static const struct igb_reg_info igb_reg_info_tbl[] = { 218 219 /* General Registers */ 220 {E1000_CTRL, "CTRL"}, 221 {E1000_STATUS, "STATUS"}, 222 {E1000_CTRL_EXT, "CTRL_EXT"}, 223 224 /* Interrupt Registers */ 225 {E1000_ICR, "ICR"}, 226 227 /* RX Registers */ 228 {E1000_RCTL, "RCTL"}, 229 {E1000_RDLEN(0), "RDLEN"}, 230 {E1000_RDH(0), "RDH"}, 231 {E1000_RDT(0), "RDT"}, 232 {E1000_RXDCTL(0), "RXDCTL"}, 233 {E1000_RDBAL(0), "RDBAL"}, 234 {E1000_RDBAH(0), "RDBAH"}, 235 236 /* TX Registers */ 237 {E1000_TCTL, "TCTL"}, 238 {E1000_TDBAL(0), "TDBAL"}, 239 {E1000_TDBAH(0), "TDBAH"}, 240 {E1000_TDLEN(0), "TDLEN"}, 241 {E1000_TDH(0), "TDH"}, 242 {E1000_TDT(0), "TDT"}, 243 {E1000_TXDCTL(0), "TXDCTL"}, 244 {E1000_TDFH, "TDFH"}, 245 {E1000_TDFT, "TDFT"}, 246 {E1000_TDFHS, "TDFHS"}, 247 {E1000_TDFPC, "TDFPC"}, 248 249 /* List Terminator */ 250 {} 251 }; 252 253 /* igb_regdump - register printout routine */ 254 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 255 { 256 int n = 0; 257 char rname[16]; 258 u32 regs[8]; 259 260 switch (reginfo->ofs) { 261 case E1000_RDLEN(0): 262 for (n = 0; n < 4; n++) 263 regs[n] = rd32(E1000_RDLEN(n)); 264 break; 265 case E1000_RDH(0): 266 for (n = 0; n < 4; n++) 267 regs[n] = rd32(E1000_RDH(n)); 268 break; 269 case E1000_RDT(0): 270 for (n = 0; n < 4; n++) 271 regs[n] = rd32(E1000_RDT(n)); 272 break; 273 case E1000_RXDCTL(0): 274 for (n = 0; n < 4; n++) 275 regs[n] = rd32(E1000_RXDCTL(n)); 276 break; 277 case E1000_RDBAL(0): 278 for (n = 0; n < 4; n++) 279 regs[n] = rd32(E1000_RDBAL(n)); 280 break; 281 case E1000_RDBAH(0): 282 for (n = 0; n < 4; n++) 283 regs[n] = rd32(E1000_RDBAH(n)); 284 break; 285 case E1000_TDBAL(0): 286 for (n = 0; n < 4; n++) 287 regs[n] = rd32(E1000_TDBAL(n)); 288 break; 289 case E1000_TDBAH(0): 290 for (n = 0; n < 4; n++) 291 regs[n] = rd32(E1000_TDBAH(n)); 292 break; 293 case E1000_TDLEN(0): 294 for (n = 0; n < 4; n++) 295 regs[n] = rd32(E1000_TDLEN(n)); 296 break; 297 case E1000_TDH(0): 298 for (n = 0; n < 4; n++) 299 regs[n] = rd32(E1000_TDH(n)); 300 break; 301 case E1000_TDT(0): 302 for (n = 0; n < 4; n++) 303 regs[n] = rd32(E1000_TDT(n)); 304 break; 305 case E1000_TXDCTL(0): 306 for (n = 0; n < 4; n++) 307 regs[n] = rd32(E1000_TXDCTL(n)); 308 break; 309 default: 310 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 311 return; 312 } 313 314 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 315 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 316 regs[2], regs[3]); 317 } 318 319 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 320 static void igb_dump(struct igb_adapter *adapter) 321 { 322 struct net_device *netdev = adapter->netdev; 323 struct e1000_hw *hw = &adapter->hw; 324 struct igb_reg_info *reginfo; 325 struct igb_ring *tx_ring; 326 union e1000_adv_tx_desc *tx_desc; 327 struct my_u0 { __le64 a; __le64 b; } *u0; 328 struct igb_ring *rx_ring; 329 union e1000_adv_rx_desc *rx_desc; 330 u32 staterr; 331 u16 i, n; 332 333 if (!netif_msg_hw(adapter)) 334 return; 335 336 /* Print netdevice Info */ 337 if (netdev) { 338 dev_info(&adapter->pdev->dev, "Net device Info\n"); 339 pr_info("Device Name state trans_start\n"); 340 pr_info("%-15s %016lX %016lX\n", netdev->name, 341 netdev->state, dev_trans_start(netdev)); 342 } 343 344 /* Print Registers */ 345 dev_info(&adapter->pdev->dev, "Register Dump\n"); 346 pr_info(" Register Name Value\n"); 347 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 348 reginfo->name; reginfo++) { 349 igb_regdump(hw, reginfo); 350 } 351 352 /* Print TX Ring Summary */ 353 if (!netdev || !netif_running(netdev)) 354 goto exit; 355 356 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 357 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 358 for (n = 0; n < adapter->num_tx_queues; n++) { 359 struct igb_tx_buffer *buffer_info; 360 tx_ring = adapter->tx_ring[n]; 361 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 362 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 363 n, tx_ring->next_to_use, tx_ring->next_to_clean, 364 (u64)dma_unmap_addr(buffer_info, dma), 365 dma_unmap_len(buffer_info, len), 366 buffer_info->next_to_watch, 367 (u64)buffer_info->time_stamp); 368 } 369 370 /* Print TX Rings */ 371 if (!netif_msg_tx_done(adapter)) 372 goto rx_ring_summary; 373 374 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 375 376 /* Transmit Descriptor Formats 377 * 378 * Advanced Transmit Descriptor 379 * +--------------------------------------------------------------+ 380 * 0 | Buffer Address [63:0] | 381 * +--------------------------------------------------------------+ 382 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 383 * +--------------------------------------------------------------+ 384 * 63 46 45 40 39 38 36 35 32 31 24 15 0 385 */ 386 387 for (n = 0; n < adapter->num_tx_queues; n++) { 388 tx_ring = adapter->tx_ring[n]; 389 pr_info("------------------------------------\n"); 390 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 391 pr_info("------------------------------------\n"); 392 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 393 394 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 395 const char *next_desc; 396 struct igb_tx_buffer *buffer_info; 397 tx_desc = IGB_TX_DESC(tx_ring, i); 398 buffer_info = &tx_ring->tx_buffer_info[i]; 399 u0 = (struct my_u0 *)tx_desc; 400 if (i == tx_ring->next_to_use && 401 i == tx_ring->next_to_clean) 402 next_desc = " NTC/U"; 403 else if (i == tx_ring->next_to_use) 404 next_desc = " NTU"; 405 else if (i == tx_ring->next_to_clean) 406 next_desc = " NTC"; 407 else 408 next_desc = ""; 409 410 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 411 i, le64_to_cpu(u0->a), 412 le64_to_cpu(u0->b), 413 (u64)dma_unmap_addr(buffer_info, dma), 414 dma_unmap_len(buffer_info, len), 415 buffer_info->next_to_watch, 416 (u64)buffer_info->time_stamp, 417 buffer_info->skb, next_desc); 418 419 if (netif_msg_pktdata(adapter) && buffer_info->skb) 420 print_hex_dump(KERN_INFO, "", 421 DUMP_PREFIX_ADDRESS, 422 16, 1, buffer_info->skb->data, 423 dma_unmap_len(buffer_info, len), 424 true); 425 } 426 } 427 428 /* Print RX Rings Summary */ 429 rx_ring_summary: 430 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 431 pr_info("Queue [NTU] [NTC]\n"); 432 for (n = 0; n < adapter->num_rx_queues; n++) { 433 rx_ring = adapter->rx_ring[n]; 434 pr_info(" %5d %5X %5X\n", 435 n, rx_ring->next_to_use, rx_ring->next_to_clean); 436 } 437 438 /* Print RX Rings */ 439 if (!netif_msg_rx_status(adapter)) 440 goto exit; 441 442 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 443 444 /* Advanced Receive Descriptor (Read) Format 445 * 63 1 0 446 * +-----------------------------------------------------+ 447 * 0 | Packet Buffer Address [63:1] |A0/NSE| 448 * +----------------------------------------------+------+ 449 * 8 | Header Buffer Address [63:1] | DD | 450 * +-----------------------------------------------------+ 451 * 452 * 453 * Advanced Receive Descriptor (Write-Back) Format 454 * 455 * 63 48 47 32 31 30 21 20 17 16 4 3 0 456 * +------------------------------------------------------+ 457 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 458 * | Checksum Ident | | | | Type | Type | 459 * +------------------------------------------------------+ 460 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 461 * +------------------------------------------------------+ 462 * 63 48 47 32 31 20 19 0 463 */ 464 465 for (n = 0; n < adapter->num_rx_queues; n++) { 466 rx_ring = adapter->rx_ring[n]; 467 pr_info("------------------------------------\n"); 468 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 469 pr_info("------------------------------------\n"); 470 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 471 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 472 473 for (i = 0; i < rx_ring->count; i++) { 474 const char *next_desc; 475 dma_addr_t dma = (dma_addr_t)0; 476 struct igb_rx_buffer *buffer_info = NULL; 477 rx_desc = IGB_RX_DESC(rx_ring, i); 478 u0 = (struct my_u0 *)rx_desc; 479 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 480 481 if (!rx_ring->xsk_pool) { 482 buffer_info = &rx_ring->rx_buffer_info[i]; 483 dma = buffer_info->dma; 484 } 485 486 if (i == rx_ring->next_to_use) 487 next_desc = " NTU"; 488 else if (i == rx_ring->next_to_clean) 489 next_desc = " NTC"; 490 else 491 next_desc = ""; 492 493 if (staterr & E1000_RXD_STAT_DD) { 494 /* Descriptor Done */ 495 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 496 "RWB", i, 497 le64_to_cpu(u0->a), 498 le64_to_cpu(u0->b), 499 next_desc); 500 } else { 501 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 502 "R ", i, 503 le64_to_cpu(u0->a), 504 le64_to_cpu(u0->b), 505 (u64)dma, 506 next_desc); 507 508 if (netif_msg_pktdata(adapter) && 509 buffer_info && dma && buffer_info->page) { 510 print_hex_dump(KERN_INFO, "", 511 DUMP_PREFIX_ADDRESS, 512 16, 1, 513 page_address(buffer_info->page) + 514 buffer_info->page_offset, 515 igb_rx_bufsz(rx_ring), true); 516 } 517 } 518 } 519 } 520 521 exit: 522 return; 523 } 524 525 /** 526 * igb_get_i2c_data - Reads the I2C SDA data bit 527 * @data: opaque pointer to adapter struct 528 * 529 * Returns the I2C data bit value 530 **/ 531 static int igb_get_i2c_data(void *data) 532 { 533 struct igb_adapter *adapter = (struct igb_adapter *)data; 534 struct e1000_hw *hw = &adapter->hw; 535 s32 i2cctl = rd32(E1000_I2CPARAMS); 536 537 return !!(i2cctl & E1000_I2C_DATA_IN); 538 } 539 540 /** 541 * igb_set_i2c_data - Sets the I2C data bit 542 * @data: pointer to hardware structure 543 * @state: I2C data value (0 or 1) to set 544 * 545 * Sets the I2C data bit 546 **/ 547 static void igb_set_i2c_data(void *data, int state) 548 { 549 struct igb_adapter *adapter = (struct igb_adapter *)data; 550 struct e1000_hw *hw = &adapter->hw; 551 s32 i2cctl = rd32(E1000_I2CPARAMS); 552 553 if (state) { 554 i2cctl |= E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N; 555 } else { 556 i2cctl &= ~E1000_I2C_DATA_OE_N; 557 i2cctl &= ~E1000_I2C_DATA_OUT; 558 } 559 560 wr32(E1000_I2CPARAMS, i2cctl); 561 wrfl(); 562 } 563 564 /** 565 * igb_set_i2c_clk - Sets the I2C SCL clock 566 * @data: pointer to hardware structure 567 * @state: state to set clock 568 * 569 * Sets the I2C clock line to state 570 **/ 571 static void igb_set_i2c_clk(void *data, int state) 572 { 573 struct igb_adapter *adapter = (struct igb_adapter *)data; 574 struct e1000_hw *hw = &adapter->hw; 575 s32 i2cctl = rd32(E1000_I2CPARAMS); 576 577 if (state) { 578 i2cctl |= E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N; 579 } else { 580 i2cctl &= ~E1000_I2C_CLK_OUT; 581 i2cctl &= ~E1000_I2C_CLK_OE_N; 582 } 583 wr32(E1000_I2CPARAMS, i2cctl); 584 wrfl(); 585 } 586 587 /** 588 * igb_get_i2c_clk - Gets the I2C SCL clock state 589 * @data: pointer to hardware structure 590 * 591 * Gets the I2C clock state 592 **/ 593 static int igb_get_i2c_clk(void *data) 594 { 595 struct igb_adapter *adapter = (struct igb_adapter *)data; 596 struct e1000_hw *hw = &adapter->hw; 597 s32 i2cctl = rd32(E1000_I2CPARAMS); 598 599 return !!(i2cctl & E1000_I2C_CLK_IN); 600 } 601 602 static const struct i2c_algo_bit_data igb_i2c_algo = { 603 .setsda = igb_set_i2c_data, 604 .setscl = igb_set_i2c_clk, 605 .getsda = igb_get_i2c_data, 606 .getscl = igb_get_i2c_clk, 607 .udelay = 5, 608 .timeout = 20, 609 }; 610 611 /** 612 * igb_get_hw_dev - return device 613 * @hw: pointer to hardware structure 614 * 615 * used by hardware layer to print debugging information 616 **/ 617 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 618 { 619 struct igb_adapter *adapter = hw->back; 620 return adapter->netdev; 621 } 622 623 static struct pci_driver igb_driver; 624 625 /** 626 * igb_init_module - Driver Registration Routine 627 * 628 * igb_init_module is the first routine called when the driver is 629 * loaded. All it does is register with the PCI subsystem. 630 **/ 631 static int __init igb_init_module(void) 632 { 633 int ret; 634 635 pr_info("%s\n", igb_driver_string); 636 pr_info("%s\n", igb_copyright); 637 638 #ifdef CONFIG_IGB_DCA 639 dca_register_notify(&dca_notifier); 640 #endif 641 ret = pci_register_driver(&igb_driver); 642 #ifdef CONFIG_IGB_DCA 643 if (ret) 644 dca_unregister_notify(&dca_notifier); 645 #endif 646 return ret; 647 } 648 649 module_init(igb_init_module); 650 651 /** 652 * igb_exit_module - Driver Exit Cleanup Routine 653 * 654 * igb_exit_module is called just before the driver is removed 655 * from memory. 656 **/ 657 static void __exit igb_exit_module(void) 658 { 659 #ifdef CONFIG_IGB_DCA 660 dca_unregister_notify(&dca_notifier); 661 #endif 662 pci_unregister_driver(&igb_driver); 663 } 664 665 module_exit(igb_exit_module); 666 667 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 668 /** 669 * igb_cache_ring_register - Descriptor ring to register mapping 670 * @adapter: board private structure to initialize 671 * 672 * Once we know the feature-set enabled for the device, we'll cache 673 * the register offset the descriptor ring is assigned to. 674 **/ 675 static void igb_cache_ring_register(struct igb_adapter *adapter) 676 { 677 int i = 0, j = 0; 678 u32 rbase_offset = adapter->vfs_allocated_count; 679 680 switch (adapter->hw.mac.type) { 681 case e1000_82576: 682 /* The queues are allocated for virtualization such that VF 0 683 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 684 * In order to avoid collision we start at the first free queue 685 * and continue consuming queues in the same sequence 686 */ 687 if (adapter->vfs_allocated_count) { 688 for (; i < adapter->rss_queues; i++) 689 adapter->rx_ring[i]->reg_idx = rbase_offset + 690 Q_IDX_82576(i); 691 } 692 fallthrough; 693 case e1000_82575: 694 case e1000_82580: 695 case e1000_i350: 696 case e1000_i354: 697 case e1000_i210: 698 case e1000_i211: 699 default: 700 for (; i < adapter->num_rx_queues; i++) 701 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 702 for (; j < adapter->num_tx_queues; j++) 703 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 704 break; 705 } 706 } 707 708 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 709 { 710 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 711 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 712 u32 value = 0; 713 714 if (E1000_REMOVED(hw_addr)) 715 return ~value; 716 717 value = readl(&hw_addr[reg]); 718 719 /* reads should not return all F's */ 720 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 721 struct net_device *netdev = igb->netdev; 722 hw->hw_addr = NULL; 723 netdev_err(netdev, "PCIe link lost\n"); 724 WARN(pci_device_is_present(igb->pdev), 725 "igb: Failed to read reg 0x%x!\n", reg); 726 } 727 728 return value; 729 } 730 731 /** 732 * igb_write_ivar - configure ivar for given MSI-X vector 733 * @hw: pointer to the HW structure 734 * @msix_vector: vector number we are allocating to a given ring 735 * @index: row index of IVAR register to write within IVAR table 736 * @offset: column offset of in IVAR, should be multiple of 8 737 * 738 * This function is intended to handle the writing of the IVAR register 739 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 740 * each containing an cause allocation for an Rx and Tx ring, and a 741 * variable number of rows depending on the number of queues supported. 742 **/ 743 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 744 int index, int offset) 745 { 746 u32 ivar = array_rd32(E1000_IVAR0, index); 747 748 /* clear any bits that are currently set */ 749 ivar &= ~((u32)0xFF << offset); 750 751 /* write vector and valid bit */ 752 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 753 754 array_wr32(E1000_IVAR0, index, ivar); 755 } 756 757 #define IGB_N0_QUEUE -1 758 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 759 { 760 struct igb_adapter *adapter = q_vector->adapter; 761 struct e1000_hw *hw = &adapter->hw; 762 int rx_queue = IGB_N0_QUEUE; 763 int tx_queue = IGB_N0_QUEUE; 764 u32 msixbm = 0; 765 766 if (q_vector->rx.ring) 767 rx_queue = q_vector->rx.ring->reg_idx; 768 if (q_vector->tx.ring) 769 tx_queue = q_vector->tx.ring->reg_idx; 770 771 switch (hw->mac.type) { 772 case e1000_82575: 773 /* The 82575 assigns vectors using a bitmask, which matches the 774 * bitmask for the EICR/EIMS/EIMC registers. To assign one 775 * or more queues to a vector, we write the appropriate bits 776 * into the MSIXBM register for that vector. 777 */ 778 if (rx_queue > IGB_N0_QUEUE) 779 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 780 if (tx_queue > IGB_N0_QUEUE) 781 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 782 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 783 msixbm |= E1000_EIMS_OTHER; 784 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 785 q_vector->eims_value = msixbm; 786 break; 787 case e1000_82576: 788 /* 82576 uses a table that essentially consists of 2 columns 789 * with 8 rows. The ordering is column-major so we use the 790 * lower 3 bits as the row index, and the 4th bit as the 791 * column offset. 792 */ 793 if (rx_queue > IGB_N0_QUEUE) 794 igb_write_ivar(hw, msix_vector, 795 rx_queue & 0x7, 796 (rx_queue & 0x8) << 1); 797 if (tx_queue > IGB_N0_QUEUE) 798 igb_write_ivar(hw, msix_vector, 799 tx_queue & 0x7, 800 ((tx_queue & 0x8) << 1) + 8); 801 q_vector->eims_value = BIT(msix_vector); 802 break; 803 case e1000_82580: 804 case e1000_i350: 805 case e1000_i354: 806 case e1000_i210: 807 case e1000_i211: 808 /* On 82580 and newer adapters the scheme is similar to 82576 809 * however instead of ordering column-major we have things 810 * ordered row-major. So we traverse the table by using 811 * bit 0 as the column offset, and the remaining bits as the 812 * row index. 813 */ 814 if (rx_queue > IGB_N0_QUEUE) 815 igb_write_ivar(hw, msix_vector, 816 rx_queue >> 1, 817 (rx_queue & 0x1) << 4); 818 if (tx_queue > IGB_N0_QUEUE) 819 igb_write_ivar(hw, msix_vector, 820 tx_queue >> 1, 821 ((tx_queue & 0x1) << 4) + 8); 822 q_vector->eims_value = BIT(msix_vector); 823 break; 824 default: 825 BUG(); 826 break; 827 } 828 829 /* add q_vector eims value to global eims_enable_mask */ 830 adapter->eims_enable_mask |= q_vector->eims_value; 831 832 /* configure q_vector to set itr on first interrupt */ 833 q_vector->set_itr = 1; 834 } 835 836 /** 837 * igb_configure_msix - Configure MSI-X hardware 838 * @adapter: board private structure to initialize 839 * 840 * igb_configure_msix sets up the hardware to properly 841 * generate MSI-X interrupts. 842 **/ 843 static void igb_configure_msix(struct igb_adapter *adapter) 844 { 845 u32 tmp; 846 int i, vector = 0; 847 struct e1000_hw *hw = &adapter->hw; 848 849 adapter->eims_enable_mask = 0; 850 851 /* set vector for other causes, i.e. link changes */ 852 switch (hw->mac.type) { 853 case e1000_82575: 854 tmp = rd32(E1000_CTRL_EXT); 855 /* enable MSI-X PBA support*/ 856 tmp |= E1000_CTRL_EXT_PBA_CLR; 857 858 /* Auto-Mask interrupts upon ICR read. */ 859 tmp |= E1000_CTRL_EXT_EIAME; 860 tmp |= E1000_CTRL_EXT_IRCA; 861 862 wr32(E1000_CTRL_EXT, tmp); 863 864 /* enable msix_other interrupt */ 865 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 866 adapter->eims_other = E1000_EIMS_OTHER; 867 868 break; 869 870 case e1000_82576: 871 case e1000_82580: 872 case e1000_i350: 873 case e1000_i354: 874 case e1000_i210: 875 case e1000_i211: 876 /* Turn on MSI-X capability first, or our settings 877 * won't stick. And it will take days to debug. 878 */ 879 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 880 E1000_GPIE_PBA | E1000_GPIE_EIAME | 881 E1000_GPIE_NSICR); 882 883 /* enable msix_other interrupt */ 884 adapter->eims_other = BIT(vector); 885 tmp = (vector++ | E1000_IVAR_VALID) << 8; 886 887 wr32(E1000_IVAR_MISC, tmp); 888 break; 889 default: 890 /* do nothing, since nothing else supports MSI-X */ 891 break; 892 } /* switch (hw->mac.type) */ 893 894 adapter->eims_enable_mask |= adapter->eims_other; 895 896 for (i = 0; i < adapter->num_q_vectors; i++) 897 igb_assign_vector(adapter->q_vector[i], vector++); 898 899 wrfl(); 900 } 901 902 /** 903 * igb_request_msix - Initialize MSI-X interrupts 904 * @adapter: board private structure to initialize 905 * 906 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 907 * kernel. 908 **/ 909 static int igb_request_msix(struct igb_adapter *adapter) 910 { 911 unsigned int num_q_vectors = adapter->num_q_vectors; 912 struct net_device *netdev = adapter->netdev; 913 int i, err = 0, vector = 0, free_vector = 0; 914 915 err = request_irq(adapter->msix_entries[vector].vector, 916 igb_msix_other, 0, netdev->name, adapter); 917 if (err) 918 goto err_out; 919 920 if (num_q_vectors > MAX_Q_VECTORS) { 921 num_q_vectors = MAX_Q_VECTORS; 922 dev_warn(&adapter->pdev->dev, 923 "The number of queue vectors (%d) is higher than max allowed (%d)\n", 924 adapter->num_q_vectors, MAX_Q_VECTORS); 925 } 926 for (i = 0; i < num_q_vectors; i++) { 927 struct igb_q_vector *q_vector = adapter->q_vector[i]; 928 929 vector++; 930 931 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 932 933 if (q_vector->rx.ring && q_vector->tx.ring) 934 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 935 q_vector->rx.ring->queue_index); 936 else if (q_vector->tx.ring) 937 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 938 q_vector->tx.ring->queue_index); 939 else if (q_vector->rx.ring) 940 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 941 q_vector->rx.ring->queue_index); 942 else 943 sprintf(q_vector->name, "%s-unused", netdev->name); 944 945 err = request_irq(adapter->msix_entries[vector].vector, 946 igb_msix_ring, 0, q_vector->name, 947 q_vector); 948 if (err) 949 goto err_free; 950 951 netif_napi_set_irq(&q_vector->napi, 952 adapter->msix_entries[vector].vector); 953 } 954 955 igb_configure_msix(adapter); 956 return 0; 957 958 err_free: 959 /* free already assigned IRQs */ 960 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 961 962 vector--; 963 for (i = 0; i < vector; i++) { 964 free_irq(adapter->msix_entries[free_vector++].vector, 965 adapter->q_vector[i]); 966 } 967 err_out: 968 return err; 969 } 970 971 /** 972 * igb_free_q_vector - Free memory allocated for specific interrupt vector 973 * @adapter: board private structure to initialize 974 * @v_idx: Index of vector to be freed 975 * 976 * This function frees the memory allocated to the q_vector. 977 **/ 978 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 979 { 980 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 981 982 adapter->q_vector[v_idx] = NULL; 983 984 /* igb_get_stats64() might access the rings on this vector, 985 * we must wait a grace period before freeing it. 986 */ 987 if (q_vector) 988 kfree_rcu(q_vector, rcu); 989 } 990 991 /** 992 * igb_reset_q_vector - Reset config for interrupt vector 993 * @adapter: board private structure to initialize 994 * @v_idx: Index of vector to be reset 995 * 996 * If NAPI is enabled it will delete any references to the 997 * NAPI struct. This is preparation for igb_free_q_vector. 998 **/ 999 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1000 { 1001 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1002 1003 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1004 * allocated. So, q_vector is NULL so we should stop here. 1005 */ 1006 if (!q_vector) 1007 return; 1008 1009 if (q_vector->tx.ring) 1010 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1011 1012 if (q_vector->rx.ring) 1013 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1014 1015 netif_napi_del(&q_vector->napi); 1016 1017 } 1018 1019 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1020 { 1021 int v_idx = adapter->num_q_vectors; 1022 1023 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1024 pci_disable_msix(adapter->pdev); 1025 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1026 pci_disable_msi(adapter->pdev); 1027 1028 while (v_idx--) 1029 igb_reset_q_vector(adapter, v_idx); 1030 } 1031 1032 /** 1033 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1034 * @adapter: board private structure to initialize 1035 * 1036 * This function frees the memory allocated to the q_vectors. In addition if 1037 * NAPI is enabled it will delete any references to the NAPI struct prior 1038 * to freeing the q_vector. 1039 **/ 1040 static void igb_free_q_vectors(struct igb_adapter *adapter) 1041 { 1042 int v_idx = adapter->num_q_vectors; 1043 1044 adapter->num_tx_queues = 0; 1045 adapter->num_rx_queues = 0; 1046 adapter->num_q_vectors = 0; 1047 1048 while (v_idx--) { 1049 igb_reset_q_vector(adapter, v_idx); 1050 igb_free_q_vector(adapter, v_idx); 1051 } 1052 } 1053 1054 /** 1055 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1056 * @adapter: board private structure to initialize 1057 * 1058 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1059 * MSI-X interrupts allocated. 1060 */ 1061 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1062 { 1063 igb_free_q_vectors(adapter); 1064 igb_reset_interrupt_capability(adapter); 1065 } 1066 1067 /** 1068 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1069 * @adapter: board private structure to initialize 1070 * @msix: boolean value of MSIX capability 1071 * 1072 * Attempt to configure interrupts using the best available 1073 * capabilities of the hardware and kernel. 1074 **/ 1075 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1076 { 1077 int err; 1078 int numvecs, i; 1079 1080 if (!msix) 1081 goto msi_only; 1082 adapter->flags |= IGB_FLAG_HAS_MSIX; 1083 1084 /* Number of supported queues. */ 1085 adapter->num_rx_queues = adapter->rss_queues; 1086 if (adapter->vfs_allocated_count) 1087 adapter->num_tx_queues = 1; 1088 else 1089 adapter->num_tx_queues = adapter->rss_queues; 1090 1091 /* start with one vector for every Rx queue */ 1092 numvecs = adapter->num_rx_queues; 1093 1094 /* if Tx handler is separate add 1 for every Tx queue */ 1095 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1096 numvecs += adapter->num_tx_queues; 1097 1098 /* store the number of vectors reserved for queues */ 1099 adapter->num_q_vectors = numvecs; 1100 1101 /* add 1 vector for link status interrupts */ 1102 numvecs++; 1103 for (i = 0; i < numvecs; i++) 1104 adapter->msix_entries[i].entry = i; 1105 1106 err = pci_enable_msix_range(adapter->pdev, 1107 adapter->msix_entries, 1108 numvecs, 1109 numvecs); 1110 if (err > 0) 1111 return; 1112 1113 igb_reset_interrupt_capability(adapter); 1114 1115 /* If we can't do MSI-X, try MSI */ 1116 msi_only: 1117 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1118 #ifdef CONFIG_PCI_IOV 1119 /* disable SR-IOV for non MSI-X configurations */ 1120 if (adapter->vf_data) { 1121 struct e1000_hw *hw = &adapter->hw; 1122 /* disable iov and allow time for transactions to clear */ 1123 pci_disable_sriov(adapter->pdev); 1124 msleep(500); 1125 1126 kfree(adapter->vf_mac_list); 1127 adapter->vf_mac_list = NULL; 1128 kfree(adapter->vf_data); 1129 adapter->vf_data = NULL; 1130 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1131 wrfl(); 1132 msleep(100); 1133 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1134 } 1135 #endif 1136 adapter->vfs_allocated_count = 0; 1137 adapter->rss_queues = 1; 1138 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1139 adapter->num_rx_queues = 1; 1140 adapter->num_tx_queues = 1; 1141 adapter->num_q_vectors = 1; 1142 if (!pci_enable_msi(adapter->pdev)) 1143 adapter->flags |= IGB_FLAG_HAS_MSI; 1144 } 1145 1146 static void igb_add_ring(struct igb_ring *ring, 1147 struct igb_ring_container *head) 1148 { 1149 head->ring = ring; 1150 head->count++; 1151 } 1152 1153 /** 1154 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1155 * @adapter: board private structure to initialize 1156 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1157 * @v_idx: index of vector in adapter struct 1158 * @txr_count: total number of Tx rings to allocate 1159 * @txr_idx: index of first Tx ring to allocate 1160 * @rxr_count: total number of Rx rings to allocate 1161 * @rxr_idx: index of first Rx ring to allocate 1162 * 1163 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1164 **/ 1165 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1166 int v_count, int v_idx, 1167 int txr_count, int txr_idx, 1168 int rxr_count, int rxr_idx) 1169 { 1170 struct igb_q_vector *q_vector; 1171 struct igb_ring *ring; 1172 int ring_count; 1173 size_t size; 1174 1175 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1176 if (txr_count > 1 || rxr_count > 1) 1177 return -ENOMEM; 1178 1179 ring_count = txr_count + rxr_count; 1180 size = kmalloc_size_roundup(struct_size(q_vector, ring, ring_count)); 1181 1182 /* allocate q_vector and rings */ 1183 q_vector = adapter->q_vector[v_idx]; 1184 if (!q_vector) { 1185 q_vector = kzalloc(size, GFP_KERNEL); 1186 } else if (size > ksize(q_vector)) { 1187 struct igb_q_vector *new_q_vector; 1188 1189 new_q_vector = kzalloc(size, GFP_KERNEL); 1190 if (new_q_vector) 1191 kfree_rcu(q_vector, rcu); 1192 q_vector = new_q_vector; 1193 } else { 1194 memset(q_vector, 0, size); 1195 } 1196 if (!q_vector) 1197 return -ENOMEM; 1198 1199 /* initialize NAPI */ 1200 netif_napi_add_config(adapter->netdev, &q_vector->napi, igb_poll, 1201 v_idx); 1202 1203 /* tie q_vector and adapter together */ 1204 adapter->q_vector[v_idx] = q_vector; 1205 q_vector->adapter = adapter; 1206 1207 /* initialize work limits */ 1208 q_vector->tx.work_limit = adapter->tx_work_limit; 1209 1210 /* initialize ITR configuration */ 1211 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1212 q_vector->itr_val = IGB_START_ITR; 1213 1214 /* initialize pointer to rings */ 1215 ring = q_vector->ring; 1216 1217 /* initialize ITR */ 1218 if (rxr_count) { 1219 /* rx or rx/tx vector */ 1220 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1221 q_vector->itr_val = adapter->rx_itr_setting; 1222 } else { 1223 /* tx only vector */ 1224 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1225 q_vector->itr_val = adapter->tx_itr_setting; 1226 } 1227 1228 if (txr_count) { 1229 /* assign generic ring traits */ 1230 ring->dev = &adapter->pdev->dev; 1231 ring->netdev = adapter->netdev; 1232 1233 /* configure backlink on ring */ 1234 ring->q_vector = q_vector; 1235 1236 /* update q_vector Tx values */ 1237 igb_add_ring(ring, &q_vector->tx); 1238 1239 /* For 82575, context index must be unique per ring. */ 1240 if (adapter->hw.mac.type == e1000_82575) 1241 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1242 1243 /* apply Tx specific ring traits */ 1244 ring->count = adapter->tx_ring_count; 1245 ring->queue_index = txr_idx; 1246 1247 ring->cbs_enable = false; 1248 ring->idleslope = 0; 1249 ring->sendslope = 0; 1250 ring->hicredit = 0; 1251 ring->locredit = 0; 1252 1253 u64_stats_init(&ring->tx_syncp); 1254 u64_stats_init(&ring->tx_syncp2); 1255 1256 /* assign ring to adapter */ 1257 adapter->tx_ring[txr_idx] = ring; 1258 1259 /* push pointer to next ring */ 1260 ring++; 1261 } 1262 1263 if (rxr_count) { 1264 /* assign generic ring traits */ 1265 ring->dev = &adapter->pdev->dev; 1266 ring->netdev = adapter->netdev; 1267 1268 /* configure backlink on ring */ 1269 ring->q_vector = q_vector; 1270 1271 /* update q_vector Rx values */ 1272 igb_add_ring(ring, &q_vector->rx); 1273 1274 /* set flag indicating ring supports SCTP checksum offload */ 1275 if (adapter->hw.mac.type >= e1000_82576) 1276 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1277 1278 /* On i350, i354, i210, and i211, loopback VLAN packets 1279 * have the tag byte-swapped. 1280 */ 1281 if (adapter->hw.mac.type >= e1000_i350) 1282 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1283 1284 /* apply Rx specific ring traits */ 1285 ring->count = adapter->rx_ring_count; 1286 ring->queue_index = rxr_idx; 1287 1288 u64_stats_init(&ring->rx_syncp); 1289 1290 /* assign ring to adapter */ 1291 adapter->rx_ring[rxr_idx] = ring; 1292 } 1293 1294 return 0; 1295 } 1296 1297 1298 /** 1299 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1300 * @adapter: board private structure to initialize 1301 * 1302 * We allocate one q_vector per queue interrupt. If allocation fails we 1303 * return -ENOMEM. 1304 **/ 1305 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1306 { 1307 int q_vectors = adapter->num_q_vectors; 1308 int rxr_remaining = adapter->num_rx_queues; 1309 int txr_remaining = adapter->num_tx_queues; 1310 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1311 int err; 1312 1313 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1314 for (; rxr_remaining; v_idx++) { 1315 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1316 0, 0, 1, rxr_idx); 1317 1318 if (err) 1319 goto err_out; 1320 1321 /* update counts and index */ 1322 rxr_remaining--; 1323 rxr_idx++; 1324 } 1325 } 1326 1327 for (; v_idx < q_vectors; v_idx++) { 1328 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1329 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1330 1331 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1332 tqpv, txr_idx, rqpv, rxr_idx); 1333 1334 if (err) 1335 goto err_out; 1336 1337 /* update counts and index */ 1338 rxr_remaining -= rqpv; 1339 txr_remaining -= tqpv; 1340 rxr_idx++; 1341 txr_idx++; 1342 } 1343 1344 return 0; 1345 1346 err_out: 1347 adapter->num_tx_queues = 0; 1348 adapter->num_rx_queues = 0; 1349 adapter->num_q_vectors = 0; 1350 1351 while (v_idx--) 1352 igb_free_q_vector(adapter, v_idx); 1353 1354 return -ENOMEM; 1355 } 1356 1357 /** 1358 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1359 * @adapter: board private structure to initialize 1360 * @msix: boolean value of MSIX capability 1361 * 1362 * This function initializes the interrupts and allocates all of the queues. 1363 **/ 1364 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1365 { 1366 struct pci_dev *pdev = adapter->pdev; 1367 int err; 1368 1369 igb_set_interrupt_capability(adapter, msix); 1370 1371 err = igb_alloc_q_vectors(adapter); 1372 if (err) { 1373 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1374 goto err_alloc_q_vectors; 1375 } 1376 1377 igb_cache_ring_register(adapter); 1378 1379 return 0; 1380 1381 err_alloc_q_vectors: 1382 igb_reset_interrupt_capability(adapter); 1383 return err; 1384 } 1385 1386 /** 1387 * igb_request_irq - initialize interrupts 1388 * @adapter: board private structure to initialize 1389 * 1390 * Attempts to configure interrupts using the best available 1391 * capabilities of the hardware and kernel. 1392 **/ 1393 static int igb_request_irq(struct igb_adapter *adapter) 1394 { 1395 struct net_device *netdev = adapter->netdev; 1396 struct pci_dev *pdev = adapter->pdev; 1397 int err = 0; 1398 1399 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1400 err = igb_request_msix(adapter); 1401 if (!err) 1402 goto request_done; 1403 /* fall back to MSI */ 1404 igb_free_all_tx_resources(adapter); 1405 igb_free_all_rx_resources(adapter); 1406 1407 igb_clear_interrupt_scheme(adapter); 1408 err = igb_init_interrupt_scheme(adapter, false); 1409 if (err) 1410 goto request_done; 1411 1412 igb_setup_all_tx_resources(adapter); 1413 igb_setup_all_rx_resources(adapter); 1414 igb_configure(adapter); 1415 } 1416 1417 igb_assign_vector(adapter->q_vector[0], 0); 1418 1419 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1420 err = request_irq(pdev->irq, igb_intr_msi, 0, 1421 netdev->name, adapter); 1422 if (!err) 1423 goto request_done; 1424 1425 /* fall back to legacy interrupts */ 1426 igb_reset_interrupt_capability(adapter); 1427 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1428 } 1429 1430 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1431 netdev->name, adapter); 1432 1433 if (err) 1434 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1435 err); 1436 1437 request_done: 1438 return err; 1439 } 1440 1441 static void igb_free_irq(struct igb_adapter *adapter) 1442 { 1443 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1444 int vector = 0, i; 1445 1446 free_irq(adapter->msix_entries[vector++].vector, adapter); 1447 1448 for (i = 0; i < adapter->num_q_vectors; i++) 1449 free_irq(adapter->msix_entries[vector++].vector, 1450 adapter->q_vector[i]); 1451 } else { 1452 free_irq(adapter->pdev->irq, adapter); 1453 } 1454 } 1455 1456 /** 1457 * igb_irq_disable - Mask off interrupt generation on the NIC 1458 * @adapter: board private structure 1459 **/ 1460 static void igb_irq_disable(struct igb_adapter *adapter) 1461 { 1462 struct e1000_hw *hw = &adapter->hw; 1463 1464 /* we need to be careful when disabling interrupts. The VFs are also 1465 * mapped into these registers and so clearing the bits can cause 1466 * issues on the VF drivers so we only need to clear what we set 1467 */ 1468 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1469 u32 regval = rd32(E1000_EIAM); 1470 1471 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1472 wr32(E1000_EIMC, adapter->eims_enable_mask); 1473 regval = rd32(E1000_EIAC); 1474 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1475 } 1476 1477 wr32(E1000_IAM, 0); 1478 wr32(E1000_IMC, ~0); 1479 wrfl(); 1480 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1481 int i; 1482 1483 for (i = 0; i < adapter->num_q_vectors; i++) 1484 synchronize_irq(adapter->msix_entries[i].vector); 1485 } else { 1486 synchronize_irq(adapter->pdev->irq); 1487 } 1488 } 1489 1490 /** 1491 * igb_irq_enable - Enable default interrupt generation settings 1492 * @adapter: board private structure 1493 **/ 1494 static void igb_irq_enable(struct igb_adapter *adapter) 1495 { 1496 struct e1000_hw *hw = &adapter->hw; 1497 1498 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1499 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1500 u32 regval = rd32(E1000_EIAC); 1501 1502 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1503 regval = rd32(E1000_EIAM); 1504 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1505 wr32(E1000_EIMS, adapter->eims_enable_mask); 1506 if (adapter->vfs_allocated_count) { 1507 wr32(E1000_MBVFIMR, 0xFF); 1508 ims |= E1000_IMS_VMMB; 1509 } 1510 wr32(E1000_IMS, ims); 1511 } else { 1512 wr32(E1000_IMS, IMS_ENABLE_MASK | 1513 E1000_IMS_DRSTA); 1514 wr32(E1000_IAM, IMS_ENABLE_MASK | 1515 E1000_IMS_DRSTA); 1516 } 1517 } 1518 1519 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1520 { 1521 struct e1000_hw *hw = &adapter->hw; 1522 u16 pf_id = adapter->vfs_allocated_count; 1523 u16 vid = adapter->hw.mng_cookie.vlan_id; 1524 u16 old_vid = adapter->mng_vlan_id; 1525 1526 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1527 /* add VID to filter table */ 1528 igb_vfta_set(hw, vid, pf_id, true, true); 1529 adapter->mng_vlan_id = vid; 1530 } else { 1531 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1532 } 1533 1534 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1535 (vid != old_vid) && 1536 !test_bit(old_vid, adapter->active_vlans)) { 1537 /* remove VID from filter table */ 1538 igb_vfta_set(hw, vid, pf_id, false, true); 1539 } 1540 } 1541 1542 /** 1543 * igb_release_hw_control - release control of the h/w to f/w 1544 * @adapter: address of board private structure 1545 * 1546 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1547 * For ASF and Pass Through versions of f/w this means that the 1548 * driver is no longer loaded. 1549 **/ 1550 static void igb_release_hw_control(struct igb_adapter *adapter) 1551 { 1552 struct e1000_hw *hw = &adapter->hw; 1553 u32 ctrl_ext; 1554 1555 /* Let firmware take over control of h/w */ 1556 ctrl_ext = rd32(E1000_CTRL_EXT); 1557 wr32(E1000_CTRL_EXT, 1558 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1559 } 1560 1561 /** 1562 * igb_get_hw_control - get control of the h/w from f/w 1563 * @adapter: address of board private structure 1564 * 1565 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1566 * For ASF and Pass Through versions of f/w this means that 1567 * the driver is loaded. 1568 **/ 1569 static void igb_get_hw_control(struct igb_adapter *adapter) 1570 { 1571 struct e1000_hw *hw = &adapter->hw; 1572 u32 ctrl_ext; 1573 1574 /* Let firmware know the driver has taken over */ 1575 ctrl_ext = rd32(E1000_CTRL_EXT); 1576 wr32(E1000_CTRL_EXT, 1577 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1578 } 1579 1580 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1581 { 1582 struct net_device *netdev = adapter->netdev; 1583 struct e1000_hw *hw = &adapter->hw; 1584 1585 WARN_ON(hw->mac.type != e1000_i210); 1586 1587 if (enable) 1588 adapter->flags |= IGB_FLAG_FQTSS; 1589 else 1590 adapter->flags &= ~IGB_FLAG_FQTSS; 1591 1592 if (netif_running(netdev)) 1593 schedule_work(&adapter->reset_task); 1594 } 1595 1596 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1597 { 1598 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1599 } 1600 1601 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1602 enum tx_queue_prio prio) 1603 { 1604 u32 val; 1605 1606 WARN_ON(hw->mac.type != e1000_i210); 1607 WARN_ON(queue < 0 || queue > 4); 1608 1609 val = rd32(E1000_I210_TXDCTL(queue)); 1610 1611 if (prio == TX_QUEUE_PRIO_HIGH) 1612 val |= E1000_TXDCTL_PRIORITY; 1613 else 1614 val &= ~E1000_TXDCTL_PRIORITY; 1615 1616 wr32(E1000_I210_TXDCTL(queue), val); 1617 } 1618 1619 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1620 { 1621 u32 val; 1622 1623 WARN_ON(hw->mac.type != e1000_i210); 1624 WARN_ON(queue < 0 || queue > 1); 1625 1626 val = rd32(E1000_I210_TQAVCC(queue)); 1627 1628 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1629 val |= E1000_TQAVCC_QUEUEMODE; 1630 else 1631 val &= ~E1000_TQAVCC_QUEUEMODE; 1632 1633 wr32(E1000_I210_TQAVCC(queue), val); 1634 } 1635 1636 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1637 { 1638 int i; 1639 1640 for (i = 0; i < adapter->num_tx_queues; i++) { 1641 if (adapter->tx_ring[i]->cbs_enable) 1642 return true; 1643 } 1644 1645 return false; 1646 } 1647 1648 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1649 { 1650 int i; 1651 1652 for (i = 0; i < adapter->num_tx_queues; i++) { 1653 if (adapter->tx_ring[i]->launchtime_enable) 1654 return true; 1655 } 1656 1657 return false; 1658 } 1659 1660 /** 1661 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1662 * @adapter: pointer to adapter struct 1663 * @queue: queue number 1664 * 1665 * Configure CBS and Launchtime for a given hardware queue. 1666 * Parameters are retrieved from the correct Tx ring, so 1667 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1668 * for setting those correctly prior to this function being called. 1669 **/ 1670 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1671 { 1672 struct net_device *netdev = adapter->netdev; 1673 struct e1000_hw *hw = &adapter->hw; 1674 struct igb_ring *ring; 1675 u32 tqavcc, tqavctrl; 1676 u16 value; 1677 1678 WARN_ON(hw->mac.type != e1000_i210); 1679 WARN_ON(queue < 0 || queue > 1); 1680 ring = adapter->tx_ring[queue]; 1681 1682 /* If any of the Qav features is enabled, configure queues as SR and 1683 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1684 * as SP. 1685 */ 1686 if (ring->cbs_enable || ring->launchtime_enable) { 1687 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1688 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1689 } else { 1690 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1691 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1692 } 1693 1694 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1695 if (ring->cbs_enable || queue == 0) { 1696 /* i210 does not allow the queue 0 to be in the Strict 1697 * Priority mode while the Qav mode is enabled, so, 1698 * instead of disabling strict priority mode, we give 1699 * queue 0 the maximum of credits possible. 1700 * 1701 * See section 8.12.19 of the i210 datasheet, "Note: 1702 * Queue0 QueueMode must be set to 1b when 1703 * TransmitMode is set to Qav." 1704 */ 1705 if (queue == 0 && !ring->cbs_enable) { 1706 /* max "linkspeed" idleslope in kbps */ 1707 ring->idleslope = 1000000; 1708 ring->hicredit = ETH_FRAME_LEN; 1709 } 1710 1711 /* Always set data transfer arbitration to credit-based 1712 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1713 * the queues. 1714 */ 1715 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1716 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1717 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1718 1719 /* According to i210 datasheet section 7.2.7.7, we should set 1720 * the 'idleSlope' field from TQAVCC register following the 1721 * equation: 1722 * 1723 * For 100 Mbps link speed: 1724 * 1725 * value = BW * 0x7735 * 0.2 (E1) 1726 * 1727 * For 1000Mbps link speed: 1728 * 1729 * value = BW * 0x7735 * 2 (E2) 1730 * 1731 * E1 and E2 can be merged into one equation as shown below. 1732 * Note that 'link-speed' is in Mbps. 1733 * 1734 * value = BW * 0x7735 * 2 * link-speed 1735 * -------------- (E3) 1736 * 1000 1737 * 1738 * 'BW' is the percentage bandwidth out of full link speed 1739 * which can be found with the following equation. Note that 1740 * idleSlope here is the parameter from this function which 1741 * is in kbps. 1742 * 1743 * BW = idleSlope 1744 * ----------------- (E4) 1745 * link-speed * 1000 1746 * 1747 * That said, we can come up with a generic equation to 1748 * calculate the value we should set it TQAVCC register by 1749 * replacing 'BW' in E3 by E4. The resulting equation is: 1750 * 1751 * value = idleSlope * 0x7735 * 2 * link-speed 1752 * ----------------- -------------- (E5) 1753 * link-speed * 1000 1000 1754 * 1755 * 'link-speed' is present in both sides of the fraction so 1756 * it is canceled out. The final equation is the following: 1757 * 1758 * value = idleSlope * 61034 1759 * ----------------- (E6) 1760 * 1000000 1761 * 1762 * NOTE: For i210, given the above, we can see that idleslope 1763 * is represented in 16.38431 kbps units by the value at 1764 * the TQAVCC register (1Gbps / 61034), which reduces 1765 * the granularity for idleslope increments. 1766 * For instance, if you want to configure a 2576kbps 1767 * idleslope, the value to be written on the register 1768 * would have to be 157.23. If rounded down, you end 1769 * up with less bandwidth available than originally 1770 * required (~2572 kbps). If rounded up, you end up 1771 * with a higher bandwidth (~2589 kbps). Below the 1772 * approach we take is to always round up the 1773 * calculated value, so the resulting bandwidth might 1774 * be slightly higher for some configurations. 1775 */ 1776 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1777 1778 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1779 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1780 tqavcc |= value; 1781 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1782 1783 wr32(E1000_I210_TQAVHC(queue), 1784 0x80000000 + ring->hicredit * 0x7735); 1785 } else { 1786 1787 /* Set idleSlope to zero. */ 1788 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1789 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1790 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1791 1792 /* Set hiCredit to zero. */ 1793 wr32(E1000_I210_TQAVHC(queue), 0); 1794 1795 /* If CBS is not enabled for any queues anymore, then return to 1796 * the default state of Data Transmission Arbitration on 1797 * TQAVCTRL. 1798 */ 1799 if (!is_any_cbs_enabled(adapter)) { 1800 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1801 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1802 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1803 } 1804 } 1805 1806 /* If LaunchTime is enabled, set DataTranTIM. */ 1807 if (ring->launchtime_enable) { 1808 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1809 * for any of the SR queues, and configure fetchtime delta. 1810 * XXX NOTE: 1811 * - LaunchTime will be enabled for all SR queues. 1812 * - A fixed offset can be added relative to the launch 1813 * time of all packets if configured at reg LAUNCH_OS0. 1814 * We are keeping it as 0 for now (default value). 1815 */ 1816 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1817 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1818 E1000_TQAVCTRL_FETCHTIME_DELTA; 1819 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1820 } else { 1821 /* If Launchtime is not enabled for any SR queues anymore, 1822 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1823 * effectively disabling Launchtime. 1824 */ 1825 if (!is_any_txtime_enabled(adapter)) { 1826 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1827 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1828 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1829 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1830 } 1831 } 1832 1833 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1834 * CBS are not configurable by software so we don't do any 'controller 1835 * configuration' in respect to these parameters. 1836 */ 1837 1838 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1839 ring->cbs_enable ? "enabled" : "disabled", 1840 ring->launchtime_enable ? "enabled" : "disabled", 1841 queue, 1842 ring->idleslope, ring->sendslope, 1843 ring->hicredit, ring->locredit); 1844 } 1845 1846 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1847 bool enable) 1848 { 1849 struct igb_ring *ring; 1850 1851 if (queue < 0 || queue > adapter->num_tx_queues) 1852 return -EINVAL; 1853 1854 ring = adapter->tx_ring[queue]; 1855 ring->launchtime_enable = enable; 1856 1857 return 0; 1858 } 1859 1860 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1861 bool enable, int idleslope, int sendslope, 1862 int hicredit, int locredit) 1863 { 1864 struct igb_ring *ring; 1865 1866 if (queue < 0 || queue > adapter->num_tx_queues) 1867 return -EINVAL; 1868 1869 ring = adapter->tx_ring[queue]; 1870 1871 ring->cbs_enable = enable; 1872 ring->idleslope = idleslope; 1873 ring->sendslope = sendslope; 1874 ring->hicredit = hicredit; 1875 ring->locredit = locredit; 1876 1877 return 0; 1878 } 1879 1880 /** 1881 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1882 * @adapter: pointer to adapter struct 1883 * 1884 * Configure TQAVCTRL register switching the controller's Tx mode 1885 * if FQTSS mode is enabled or disabled. Additionally, will issue 1886 * a call to igb_config_tx_modes() per queue so any previously saved 1887 * Tx parameters are applied. 1888 **/ 1889 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1890 { 1891 struct net_device *netdev = adapter->netdev; 1892 struct e1000_hw *hw = &adapter->hw; 1893 u32 val; 1894 1895 /* Only i210 controller supports changing the transmission mode. */ 1896 if (hw->mac.type != e1000_i210) 1897 return; 1898 1899 if (is_fqtss_enabled(adapter)) { 1900 int i, max_queue; 1901 1902 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1903 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1904 * so SP queues wait for SR ones. 1905 */ 1906 val = rd32(E1000_I210_TQAVCTRL); 1907 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1908 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1909 wr32(E1000_I210_TQAVCTRL, val); 1910 1911 /* Configure Tx and Rx packet buffers sizes as described in 1912 * i210 datasheet section 7.2.7.7. 1913 */ 1914 val = rd32(E1000_TXPBS); 1915 val &= ~I210_TXPBSIZE_MASK; 1916 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB | 1917 I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB; 1918 wr32(E1000_TXPBS, val); 1919 1920 val = rd32(E1000_RXPBS); 1921 val &= ~I210_RXPBSIZE_MASK; 1922 val |= I210_RXPBSIZE_PB_30KB; 1923 wr32(E1000_RXPBS, val); 1924 1925 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1926 * register should not exceed the buffer size programmed in 1927 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1928 * so according to the datasheet we should set MAX_TPKT_SIZE to 1929 * 4kB / 64. 1930 * 1931 * However, when we do so, no frame from queue 2 and 3 are 1932 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1933 * or _equal_ to the buffer size programmed in TXPBS. For this 1934 * reason, we set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1935 */ 1936 val = (4096 - 1) / 64; 1937 wr32(E1000_I210_DTXMXPKTSZ, val); 1938 1939 /* Since FQTSS mode is enabled, apply any CBS configuration 1940 * previously set. If no previous CBS configuration has been 1941 * done, then the initial configuration is applied, which means 1942 * CBS is disabled. 1943 */ 1944 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1945 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1946 1947 for (i = 0; i < max_queue; i++) { 1948 igb_config_tx_modes(adapter, i); 1949 } 1950 } else { 1951 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1952 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1953 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1954 1955 val = rd32(E1000_I210_TQAVCTRL); 1956 /* According to Section 8.12.21, the other flags we've set when 1957 * enabling FQTSS are not relevant when disabling FQTSS so we 1958 * don't set they here. 1959 */ 1960 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1961 wr32(E1000_I210_TQAVCTRL, val); 1962 } 1963 1964 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1965 "enabled" : "disabled"); 1966 } 1967 1968 /** 1969 * igb_configure - configure the hardware for RX and TX 1970 * @adapter: private board structure 1971 **/ 1972 static void igb_configure(struct igb_adapter *adapter) 1973 { 1974 struct net_device *netdev = adapter->netdev; 1975 int i; 1976 1977 igb_get_hw_control(adapter); 1978 igb_set_rx_mode(netdev); 1979 igb_setup_tx_mode(adapter); 1980 1981 igb_restore_vlan(adapter); 1982 1983 igb_setup_tctl(adapter); 1984 igb_setup_mrqc(adapter); 1985 igb_setup_rctl(adapter); 1986 1987 igb_nfc_filter_restore(adapter); 1988 igb_configure_tx(adapter); 1989 igb_configure_rx(adapter); 1990 1991 igb_rx_fifo_flush_82575(&adapter->hw); 1992 1993 /* call igb_desc_unused which always leaves 1994 * at least 1 descriptor unused to make sure 1995 * next_to_use != next_to_clean 1996 */ 1997 for (i = 0; i < adapter->num_rx_queues; i++) { 1998 struct igb_ring *ring = adapter->rx_ring[i]; 1999 if (ring->xsk_pool) 2000 igb_alloc_rx_buffers_zc(ring, ring->xsk_pool, 2001 igb_desc_unused(ring)); 2002 else 2003 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 2004 } 2005 } 2006 2007 /** 2008 * igb_power_up_link - Power up the phy/serdes link 2009 * @adapter: address of board private structure 2010 **/ 2011 void igb_power_up_link(struct igb_adapter *adapter) 2012 { 2013 igb_reset_phy(&adapter->hw); 2014 2015 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2016 igb_power_up_phy_copper(&adapter->hw); 2017 else 2018 igb_power_up_serdes_link_82575(&adapter->hw); 2019 2020 igb_setup_link(&adapter->hw); 2021 } 2022 2023 /** 2024 * igb_power_down_link - Power down the phy/serdes link 2025 * @adapter: address of board private structure 2026 */ 2027 static void igb_power_down_link(struct igb_adapter *adapter) 2028 { 2029 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2030 igb_power_down_phy_copper_82575(&adapter->hw); 2031 else 2032 igb_shutdown_serdes_link_82575(&adapter->hw); 2033 } 2034 2035 /** 2036 * igb_check_swap_media - Detect and switch function for Media Auto Sense 2037 * @adapter: address of the board private structure 2038 **/ 2039 static void igb_check_swap_media(struct igb_adapter *adapter) 2040 { 2041 struct e1000_hw *hw = &adapter->hw; 2042 u32 ctrl_ext, connsw; 2043 bool swap_now = false; 2044 2045 ctrl_ext = rd32(E1000_CTRL_EXT); 2046 connsw = rd32(E1000_CONNSW); 2047 2048 /* need to live swap if current media is copper and we have fiber/serdes 2049 * to go to. 2050 */ 2051 2052 if ((hw->phy.media_type == e1000_media_type_copper) && 2053 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2054 swap_now = true; 2055 } else if ((hw->phy.media_type != e1000_media_type_copper) && 2056 !(connsw & E1000_CONNSW_SERDESD)) { 2057 /* copper signal takes time to appear */ 2058 if (adapter->copper_tries < 4) { 2059 adapter->copper_tries++; 2060 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2061 wr32(E1000_CONNSW, connsw); 2062 return; 2063 } else { 2064 adapter->copper_tries = 0; 2065 if ((connsw & E1000_CONNSW_PHYSD) && 2066 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2067 swap_now = true; 2068 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2069 wr32(E1000_CONNSW, connsw); 2070 } 2071 } 2072 } 2073 2074 if (!swap_now) 2075 return; 2076 2077 switch (hw->phy.media_type) { 2078 case e1000_media_type_copper: 2079 netdev_info(adapter->netdev, 2080 "MAS: changing media to fiber/serdes\n"); 2081 ctrl_ext |= 2082 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2083 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2084 adapter->copper_tries = 0; 2085 break; 2086 case e1000_media_type_internal_serdes: 2087 case e1000_media_type_fiber: 2088 netdev_info(adapter->netdev, 2089 "MAS: changing media to copper\n"); 2090 ctrl_ext &= 2091 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2092 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2093 break; 2094 default: 2095 /* shouldn't get here during regular operation */ 2096 netdev_err(adapter->netdev, 2097 "AMS: Invalid media type found, returning\n"); 2098 break; 2099 } 2100 wr32(E1000_CTRL_EXT, ctrl_ext); 2101 } 2102 2103 void igb_set_queue_napi(struct igb_adapter *adapter, int vector, 2104 struct napi_struct *napi) 2105 { 2106 struct igb_q_vector *q_vector = adapter->q_vector[vector]; 2107 2108 if (q_vector->rx.ring) 2109 netif_queue_set_napi(adapter->netdev, 2110 q_vector->rx.ring->queue_index, 2111 NETDEV_QUEUE_TYPE_RX, napi); 2112 2113 if (q_vector->tx.ring) 2114 netif_queue_set_napi(adapter->netdev, 2115 q_vector->tx.ring->queue_index, 2116 NETDEV_QUEUE_TYPE_TX, napi); 2117 } 2118 2119 /** 2120 * igb_up - Open the interface and prepare it to handle traffic 2121 * @adapter: board private structure 2122 **/ 2123 int igb_up(struct igb_adapter *adapter) 2124 { 2125 struct e1000_hw *hw = &adapter->hw; 2126 struct napi_struct *napi; 2127 int i; 2128 2129 /* hardware has been reset, we need to reload some things */ 2130 igb_configure(adapter); 2131 2132 clear_bit(__IGB_DOWN, &adapter->state); 2133 2134 for (i = 0; i < adapter->num_q_vectors; i++) { 2135 napi = &adapter->q_vector[i]->napi; 2136 napi_enable(napi); 2137 igb_set_queue_napi(adapter, i, napi); 2138 } 2139 2140 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2141 igb_configure_msix(adapter); 2142 else 2143 igb_assign_vector(adapter->q_vector[0], 0); 2144 2145 /* Clear any pending interrupts. */ 2146 rd32(E1000_TSICR); 2147 rd32(E1000_ICR); 2148 igb_irq_enable(adapter); 2149 2150 /* notify VFs that reset has been completed */ 2151 if (adapter->vfs_allocated_count) { 2152 u32 reg_data = rd32(E1000_CTRL_EXT); 2153 2154 reg_data |= E1000_CTRL_EXT_PFRSTD; 2155 wr32(E1000_CTRL_EXT, reg_data); 2156 } 2157 2158 netif_tx_start_all_queues(adapter->netdev); 2159 2160 /* start the watchdog. */ 2161 hw->mac.get_link_status = 1; 2162 schedule_work(&adapter->watchdog_task); 2163 2164 if ((adapter->flags & IGB_FLAG_EEE) && 2165 (!hw->dev_spec._82575.eee_disable)) 2166 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2167 2168 return 0; 2169 } 2170 2171 void igb_down(struct igb_adapter *adapter) 2172 { 2173 struct net_device *netdev = adapter->netdev; 2174 struct e1000_hw *hw = &adapter->hw; 2175 u32 tctl, rctl; 2176 int i; 2177 2178 /* signal that we're down so the interrupt handler does not 2179 * reschedule our watchdog timer 2180 */ 2181 set_bit(__IGB_DOWN, &adapter->state); 2182 2183 /* disable receives in the hardware */ 2184 rctl = rd32(E1000_RCTL); 2185 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2186 /* flush and sleep below */ 2187 2188 igb_nfc_filter_exit(adapter); 2189 2190 netif_carrier_off(netdev); 2191 netif_tx_stop_all_queues(netdev); 2192 2193 /* disable transmits in the hardware */ 2194 tctl = rd32(E1000_TCTL); 2195 tctl &= ~E1000_TCTL_EN; 2196 wr32(E1000_TCTL, tctl); 2197 /* flush both disables and wait for them to finish */ 2198 wrfl(); 2199 usleep_range(10000, 11000); 2200 2201 igb_irq_disable(adapter); 2202 2203 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2204 2205 for (i = 0; i < adapter->num_q_vectors; i++) { 2206 if (adapter->q_vector[i]) { 2207 napi_synchronize(&adapter->q_vector[i]->napi); 2208 igb_set_queue_napi(adapter, i, NULL); 2209 napi_disable(&adapter->q_vector[i]->napi); 2210 } 2211 } 2212 2213 timer_delete_sync(&adapter->watchdog_timer); 2214 timer_delete_sync(&adapter->phy_info_timer); 2215 2216 /* record the stats before reset*/ 2217 spin_lock(&adapter->stats64_lock); 2218 igb_update_stats(adapter); 2219 spin_unlock(&adapter->stats64_lock); 2220 2221 adapter->link_speed = 0; 2222 adapter->link_duplex = 0; 2223 2224 if (!pci_channel_offline(adapter->pdev)) 2225 igb_reset(adapter); 2226 2227 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2228 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2229 2230 igb_clean_all_tx_rings(adapter); 2231 igb_clean_all_rx_rings(adapter); 2232 #ifdef CONFIG_IGB_DCA 2233 2234 /* since we reset the hardware DCA settings were cleared */ 2235 igb_setup_dca(adapter); 2236 #endif 2237 } 2238 2239 void igb_reinit_locked(struct igb_adapter *adapter) 2240 { 2241 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2242 usleep_range(1000, 2000); 2243 igb_down(adapter); 2244 igb_up(adapter); 2245 clear_bit(__IGB_RESETTING, &adapter->state); 2246 } 2247 2248 /** igb_enable_mas - Media Autosense re-enable after swap 2249 * 2250 * @adapter: adapter struct 2251 **/ 2252 static void igb_enable_mas(struct igb_adapter *adapter) 2253 { 2254 struct e1000_hw *hw = &adapter->hw; 2255 u32 connsw = rd32(E1000_CONNSW); 2256 2257 /* configure for SerDes media detect */ 2258 if ((hw->phy.media_type == e1000_media_type_copper) && 2259 (!(connsw & E1000_CONNSW_SERDESD))) { 2260 connsw |= E1000_CONNSW_ENRGSRC; 2261 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2262 wr32(E1000_CONNSW, connsw); 2263 wrfl(); 2264 } 2265 } 2266 2267 #ifdef CONFIG_IGB_HWMON 2268 /** 2269 * igb_set_i2c_bb - Init I2C interface 2270 * @hw: pointer to hardware structure 2271 **/ 2272 static void igb_set_i2c_bb(struct e1000_hw *hw) 2273 { 2274 u32 ctrl_ext; 2275 s32 i2cctl; 2276 2277 ctrl_ext = rd32(E1000_CTRL_EXT); 2278 ctrl_ext |= E1000_CTRL_I2C_ENA; 2279 wr32(E1000_CTRL_EXT, ctrl_ext); 2280 wrfl(); 2281 2282 i2cctl = rd32(E1000_I2CPARAMS); 2283 i2cctl |= E1000_I2CBB_EN 2284 | E1000_I2C_CLK_OE_N 2285 | E1000_I2C_DATA_OE_N; 2286 wr32(E1000_I2CPARAMS, i2cctl); 2287 wrfl(); 2288 } 2289 #endif 2290 2291 void igb_reset(struct igb_adapter *adapter) 2292 { 2293 struct pci_dev *pdev = adapter->pdev; 2294 struct e1000_hw *hw = &adapter->hw; 2295 struct e1000_mac_info *mac = &hw->mac; 2296 struct e1000_fc_info *fc = &hw->fc; 2297 u32 pba, hwm; 2298 2299 /* Repartition Pba for greater than 9k mtu 2300 * To take effect CTRL.RST is required. 2301 */ 2302 switch (mac->type) { 2303 case e1000_i350: 2304 case e1000_i354: 2305 case e1000_82580: 2306 pba = rd32(E1000_RXPBS); 2307 pba = igb_rxpbs_adjust_82580(pba); 2308 break; 2309 case e1000_82576: 2310 pba = rd32(E1000_RXPBS); 2311 pba &= E1000_RXPBS_SIZE_MASK_82576; 2312 break; 2313 case e1000_82575: 2314 case e1000_i210: 2315 case e1000_i211: 2316 default: 2317 pba = E1000_PBA_34K; 2318 break; 2319 } 2320 2321 if (mac->type == e1000_82575) { 2322 u32 min_rx_space, min_tx_space, needed_tx_space; 2323 2324 /* write Rx PBA so that hardware can report correct Tx PBA */ 2325 wr32(E1000_PBA, pba); 2326 2327 /* To maintain wire speed transmits, the Tx FIFO should be 2328 * large enough to accommodate two full transmit packets, 2329 * rounded up to the next 1KB and expressed in KB. Likewise, 2330 * the Rx FIFO should be large enough to accommodate at least 2331 * one full receive packet and is similarly rounded up and 2332 * expressed in KB. 2333 */ 2334 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2335 2336 /* The Tx FIFO also stores 16 bytes of information about the Tx 2337 * but don't include Ethernet FCS because hardware appends it. 2338 * We only need to round down to the nearest 512 byte block 2339 * count since the value we care about is 2 frames, not 1. 2340 */ 2341 min_tx_space = adapter->max_frame_size; 2342 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2343 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2344 2345 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2346 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2347 2348 /* If current Tx allocation is less than the min Tx FIFO size, 2349 * and the min Tx FIFO size is less than the current Rx FIFO 2350 * allocation, take space away from current Rx allocation. 2351 */ 2352 if (needed_tx_space < pba) { 2353 pba -= needed_tx_space; 2354 2355 /* if short on Rx space, Rx wins and must trump Tx 2356 * adjustment 2357 */ 2358 if (pba < min_rx_space) 2359 pba = min_rx_space; 2360 } 2361 2362 /* adjust PBA for jumbo frames */ 2363 wr32(E1000_PBA, pba); 2364 } 2365 2366 /* flow control settings 2367 * The high water mark must be low enough to fit one full frame 2368 * after transmitting the pause frame. As such we must have enough 2369 * space to allow for us to complete our current transmit and then 2370 * receive the frame that is in progress from the link partner. 2371 * Set it to: 2372 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2373 */ 2374 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2375 2376 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2377 fc->low_water = fc->high_water - 16; 2378 fc->pause_time = 0xFFFF; 2379 fc->send_xon = 1; 2380 fc->current_mode = fc->requested_mode; 2381 2382 /* disable receive for all VFs and wait one second */ 2383 if (adapter->vfs_allocated_count) { 2384 int i; 2385 2386 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2387 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2388 2389 /* ping all the active vfs to let them know we are going down */ 2390 igb_ping_all_vfs(adapter); 2391 2392 /* disable transmits and receives */ 2393 wr32(E1000_VFRE, 0); 2394 wr32(E1000_VFTE, 0); 2395 } 2396 2397 /* Allow time for pending master requests to run */ 2398 hw->mac.ops.reset_hw(hw); 2399 wr32(E1000_WUC, 0); 2400 2401 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2402 /* need to resetup here after media swap */ 2403 adapter->ei.get_invariants(hw); 2404 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2405 } 2406 if ((mac->type == e1000_82575 || mac->type == e1000_i350) && 2407 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2408 igb_enable_mas(adapter); 2409 } 2410 if (hw->mac.ops.init_hw(hw)) 2411 dev_err(&pdev->dev, "Hardware Error\n"); 2412 2413 /* RAR registers were cleared during init_hw, clear mac table */ 2414 igb_flush_mac_table(adapter); 2415 __dev_uc_unsync(adapter->netdev, NULL); 2416 2417 /* Recover default RAR entry */ 2418 igb_set_default_mac_filter(adapter); 2419 2420 /* Flow control settings reset on hardware reset, so guarantee flow 2421 * control is off when forcing speed. 2422 */ 2423 if (!hw->mac.autoneg) 2424 igb_force_mac_fc(hw); 2425 2426 igb_init_dmac(adapter, pba); 2427 #ifdef CONFIG_IGB_HWMON 2428 /* Re-initialize the thermal sensor on i350 devices. */ 2429 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2430 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2431 /* If present, re-initialize the external thermal sensor 2432 * interface. 2433 */ 2434 if (adapter->ets) 2435 igb_set_i2c_bb(hw); 2436 mac->ops.init_thermal_sensor_thresh(hw); 2437 } 2438 } 2439 #endif 2440 /* Re-establish EEE setting */ 2441 if (hw->phy.media_type == e1000_media_type_copper) { 2442 switch (mac->type) { 2443 case e1000_i350: 2444 case e1000_i210: 2445 case e1000_i211: 2446 igb_set_eee_i350(hw, true, true); 2447 break; 2448 case e1000_i354: 2449 igb_set_eee_i354(hw, true, true); 2450 break; 2451 default: 2452 break; 2453 } 2454 } 2455 if (!netif_running(adapter->netdev)) 2456 igb_power_down_link(adapter); 2457 2458 igb_update_mng_vlan(adapter); 2459 2460 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2461 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2462 2463 /* Re-enable PTP, where applicable. */ 2464 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2465 igb_ptp_reset(adapter); 2466 2467 igb_get_phy_info(hw); 2468 } 2469 2470 static netdev_features_t igb_fix_features(struct net_device *netdev, 2471 netdev_features_t features) 2472 { 2473 /* Since there is no support for separate Rx/Tx vlan accel 2474 * enable/disable make sure Tx flag is always in same state as Rx. 2475 */ 2476 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2477 features |= NETIF_F_HW_VLAN_CTAG_TX; 2478 else 2479 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2480 2481 return features; 2482 } 2483 2484 static int igb_set_features(struct net_device *netdev, 2485 netdev_features_t features) 2486 { 2487 netdev_features_t changed = netdev->features ^ features; 2488 struct igb_adapter *adapter = netdev_priv(netdev); 2489 2490 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2491 igb_vlan_mode(netdev, features); 2492 2493 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2494 return 0; 2495 2496 if (!(features & NETIF_F_NTUPLE)) { 2497 struct hlist_node *node2; 2498 struct igb_nfc_filter *rule; 2499 2500 spin_lock(&adapter->nfc_lock); 2501 hlist_for_each_entry_safe(rule, node2, 2502 &adapter->nfc_filter_list, nfc_node) { 2503 igb_erase_filter(adapter, rule); 2504 hlist_del(&rule->nfc_node); 2505 kfree(rule); 2506 } 2507 spin_unlock(&adapter->nfc_lock); 2508 adapter->nfc_filter_count = 0; 2509 } 2510 2511 netdev->features = features; 2512 2513 if (netif_running(netdev)) 2514 igb_reinit_locked(adapter); 2515 else 2516 igb_reset(adapter); 2517 2518 return 1; 2519 } 2520 2521 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2522 struct net_device *dev, 2523 const unsigned char *addr, u16 vid, 2524 u16 flags, bool *notified, 2525 struct netlink_ext_ack *extack) 2526 { 2527 /* guarantee we can provide a unique filter for the unicast address */ 2528 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2529 struct igb_adapter *adapter = netdev_priv(dev); 2530 int vfn = adapter->vfs_allocated_count; 2531 2532 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2533 return -ENOMEM; 2534 } 2535 2536 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2537 } 2538 2539 #define IGB_MAX_MAC_HDR_LEN 127 2540 #define IGB_MAX_NETWORK_HDR_LEN 511 2541 2542 static netdev_features_t 2543 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2544 netdev_features_t features) 2545 { 2546 unsigned int network_hdr_len, mac_hdr_len; 2547 2548 /* Make certain the headers can be described by a context descriptor */ 2549 mac_hdr_len = skb_network_offset(skb); 2550 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2551 return features & ~(NETIF_F_HW_CSUM | 2552 NETIF_F_SCTP_CRC | 2553 NETIF_F_GSO_UDP_L4 | 2554 NETIF_F_HW_VLAN_CTAG_TX | 2555 NETIF_F_TSO | 2556 NETIF_F_TSO6); 2557 2558 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2559 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2560 return features & ~(NETIF_F_HW_CSUM | 2561 NETIF_F_SCTP_CRC | 2562 NETIF_F_GSO_UDP_L4 | 2563 NETIF_F_TSO | 2564 NETIF_F_TSO6); 2565 2566 /* We can only support IPV4 TSO in tunnels if we can mangle the 2567 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2568 */ 2569 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2570 features &= ~NETIF_F_TSO; 2571 2572 return features; 2573 } 2574 2575 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2576 { 2577 if (!is_fqtss_enabled(adapter)) { 2578 enable_fqtss(adapter, true); 2579 return; 2580 } 2581 2582 igb_config_tx_modes(adapter, queue); 2583 2584 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2585 enable_fqtss(adapter, false); 2586 } 2587 2588 static int igb_offload_cbs(struct igb_adapter *adapter, 2589 struct tc_cbs_qopt_offload *qopt) 2590 { 2591 struct e1000_hw *hw = &adapter->hw; 2592 int err; 2593 2594 /* CBS offloading is only supported by i210 controller. */ 2595 if (hw->mac.type != e1000_i210) 2596 return -EOPNOTSUPP; 2597 2598 /* CBS offloading is only supported by queue 0 and queue 1. */ 2599 if (qopt->queue < 0 || qopt->queue > 1) 2600 return -EINVAL; 2601 2602 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2603 qopt->idleslope, qopt->sendslope, 2604 qopt->hicredit, qopt->locredit); 2605 if (err) 2606 return err; 2607 2608 igb_offload_apply(adapter, qopt->queue); 2609 2610 return 0; 2611 } 2612 2613 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2614 #define VLAN_PRIO_FULL_MASK (0x07) 2615 2616 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2617 struct flow_cls_offload *f, 2618 int traffic_class, 2619 struct igb_nfc_filter *input) 2620 { 2621 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2622 struct flow_dissector *dissector = rule->match.dissector; 2623 struct netlink_ext_ack *extack = f->common.extack; 2624 2625 if (dissector->used_keys & 2626 ~(BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) | 2627 BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) | 2628 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2629 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN))) { 2630 NL_SET_ERR_MSG_MOD(extack, 2631 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2632 return -EOPNOTSUPP; 2633 } 2634 2635 if (flow_rule_match_has_control_flags(rule, extack)) 2636 return -EOPNOTSUPP; 2637 2638 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2639 struct flow_match_eth_addrs match; 2640 2641 flow_rule_match_eth_addrs(rule, &match); 2642 if (!is_zero_ether_addr(match.mask->dst)) { 2643 if (!is_broadcast_ether_addr(match.mask->dst)) { 2644 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2645 return -EINVAL; 2646 } 2647 2648 input->filter.match_flags |= 2649 IGB_FILTER_FLAG_DST_MAC_ADDR; 2650 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2651 } 2652 2653 if (!is_zero_ether_addr(match.mask->src)) { 2654 if (!is_broadcast_ether_addr(match.mask->src)) { 2655 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2656 return -EINVAL; 2657 } 2658 2659 input->filter.match_flags |= 2660 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2661 ether_addr_copy(input->filter.src_addr, match.key->src); 2662 } 2663 } 2664 2665 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2666 struct flow_match_basic match; 2667 2668 flow_rule_match_basic(rule, &match); 2669 if (match.mask->n_proto) { 2670 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2671 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2672 return -EINVAL; 2673 } 2674 2675 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2676 input->filter.etype = match.key->n_proto; 2677 } 2678 } 2679 2680 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2681 struct flow_match_vlan match; 2682 2683 flow_rule_match_vlan(rule, &match); 2684 if (match.mask->vlan_priority) { 2685 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2686 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2687 return -EINVAL; 2688 } 2689 2690 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2691 input->filter.vlan_tci = 2692 (__force __be16)match.key->vlan_priority; 2693 } 2694 } 2695 2696 input->action = traffic_class; 2697 input->cookie = f->cookie; 2698 2699 return 0; 2700 } 2701 2702 static int igb_configure_clsflower(struct igb_adapter *adapter, 2703 struct flow_cls_offload *cls_flower) 2704 { 2705 struct netlink_ext_ack *extack = cls_flower->common.extack; 2706 struct igb_nfc_filter *filter, *f; 2707 int err, tc; 2708 2709 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2710 if (tc < 0) { 2711 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2712 return -EINVAL; 2713 } 2714 2715 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2716 if (!filter) 2717 return -ENOMEM; 2718 2719 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2720 if (err < 0) 2721 goto err_parse; 2722 2723 spin_lock(&adapter->nfc_lock); 2724 2725 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2726 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2727 err = -EEXIST; 2728 NL_SET_ERR_MSG_MOD(extack, 2729 "This filter is already set in ethtool"); 2730 goto err_locked; 2731 } 2732 } 2733 2734 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2735 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2736 err = -EEXIST; 2737 NL_SET_ERR_MSG_MOD(extack, 2738 "This filter is already set in cls_flower"); 2739 goto err_locked; 2740 } 2741 } 2742 2743 err = igb_add_filter(adapter, filter); 2744 if (err < 0) { 2745 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2746 goto err_locked; 2747 } 2748 2749 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2750 2751 spin_unlock(&adapter->nfc_lock); 2752 2753 return 0; 2754 2755 err_locked: 2756 spin_unlock(&adapter->nfc_lock); 2757 2758 err_parse: 2759 kfree(filter); 2760 2761 return err; 2762 } 2763 2764 static int igb_delete_clsflower(struct igb_adapter *adapter, 2765 struct flow_cls_offload *cls_flower) 2766 { 2767 struct igb_nfc_filter *filter; 2768 int err; 2769 2770 spin_lock(&adapter->nfc_lock); 2771 2772 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2773 if (filter->cookie == cls_flower->cookie) 2774 break; 2775 2776 if (!filter) { 2777 err = -ENOENT; 2778 goto out; 2779 } 2780 2781 err = igb_erase_filter(adapter, filter); 2782 if (err < 0) 2783 goto out; 2784 2785 hlist_del(&filter->nfc_node); 2786 kfree(filter); 2787 2788 out: 2789 spin_unlock(&adapter->nfc_lock); 2790 2791 return err; 2792 } 2793 2794 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2795 struct flow_cls_offload *cls_flower) 2796 { 2797 switch (cls_flower->command) { 2798 case FLOW_CLS_REPLACE: 2799 return igb_configure_clsflower(adapter, cls_flower); 2800 case FLOW_CLS_DESTROY: 2801 return igb_delete_clsflower(adapter, cls_flower); 2802 case FLOW_CLS_STATS: 2803 return -EOPNOTSUPP; 2804 default: 2805 return -EOPNOTSUPP; 2806 } 2807 } 2808 2809 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2810 void *cb_priv) 2811 { 2812 struct igb_adapter *adapter = cb_priv; 2813 2814 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2815 return -EOPNOTSUPP; 2816 2817 switch (type) { 2818 case TC_SETUP_CLSFLOWER: 2819 return igb_setup_tc_cls_flower(adapter, type_data); 2820 2821 default: 2822 return -EOPNOTSUPP; 2823 } 2824 } 2825 2826 static int igb_offload_txtime(struct igb_adapter *adapter, 2827 struct tc_etf_qopt_offload *qopt) 2828 { 2829 struct e1000_hw *hw = &adapter->hw; 2830 int err; 2831 2832 /* Launchtime offloading is only supported by i210 controller. */ 2833 if (hw->mac.type != e1000_i210) 2834 return -EOPNOTSUPP; 2835 2836 /* Launchtime offloading is only supported by queues 0 and 1. */ 2837 if (qopt->queue < 0 || qopt->queue > 1) 2838 return -EINVAL; 2839 2840 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2841 if (err) 2842 return err; 2843 2844 igb_offload_apply(adapter, qopt->queue); 2845 2846 return 0; 2847 } 2848 2849 static int igb_tc_query_caps(struct igb_adapter *adapter, 2850 struct tc_query_caps_base *base) 2851 { 2852 switch (base->type) { 2853 case TC_SETUP_QDISC_TAPRIO: { 2854 struct tc_taprio_caps *caps = base->caps; 2855 2856 caps->broken_mqprio = true; 2857 2858 return 0; 2859 } 2860 default: 2861 return -EOPNOTSUPP; 2862 } 2863 } 2864 2865 static LIST_HEAD(igb_block_cb_list); 2866 2867 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2868 void *type_data) 2869 { 2870 struct igb_adapter *adapter = netdev_priv(dev); 2871 2872 switch (type) { 2873 case TC_QUERY_CAPS: 2874 return igb_tc_query_caps(adapter, type_data); 2875 case TC_SETUP_QDISC_CBS: 2876 return igb_offload_cbs(adapter, type_data); 2877 case TC_SETUP_BLOCK: 2878 return flow_block_cb_setup_simple(type_data, 2879 &igb_block_cb_list, 2880 igb_setup_tc_block_cb, 2881 adapter, adapter, true); 2882 2883 case TC_SETUP_QDISC_ETF: 2884 return igb_offload_txtime(adapter, type_data); 2885 2886 default: 2887 return -EOPNOTSUPP; 2888 } 2889 } 2890 2891 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf) 2892 { 2893 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD; 2894 struct igb_adapter *adapter = netdev_priv(dev); 2895 struct bpf_prog *prog = bpf->prog, *old_prog; 2896 bool running = netif_running(dev); 2897 bool need_reset; 2898 2899 /* verify igb ring attributes are sufficient for XDP */ 2900 for (i = 0; i < adapter->num_rx_queues; i++) { 2901 struct igb_ring *ring = adapter->rx_ring[i]; 2902 2903 if (frame_size > igb_rx_bufsz(ring)) { 2904 NL_SET_ERR_MSG_MOD(bpf->extack, 2905 "The RX buffer size is too small for the frame size"); 2906 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n", 2907 igb_rx_bufsz(ring), frame_size); 2908 return -EINVAL; 2909 } 2910 } 2911 2912 old_prog = xchg(&adapter->xdp_prog, prog); 2913 need_reset = (!!prog != !!old_prog); 2914 2915 /* device is up and bpf is added/removed, must setup the RX queues */ 2916 if (need_reset && running) { 2917 igb_close(dev); 2918 } else { 2919 for (i = 0; i < adapter->num_rx_queues; i++) 2920 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 2921 adapter->xdp_prog); 2922 } 2923 2924 if (old_prog) 2925 bpf_prog_put(old_prog); 2926 2927 /* bpf is just replaced, RXQ and MTU are already setup */ 2928 if (!need_reset) { 2929 return 0; 2930 } else { 2931 if (prog) 2932 xdp_features_set_redirect_target(dev, true); 2933 else 2934 xdp_features_clear_redirect_target(dev); 2935 } 2936 2937 if (running) 2938 igb_open(dev); 2939 2940 return 0; 2941 } 2942 2943 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp) 2944 { 2945 struct igb_adapter *adapter = netdev_priv(dev); 2946 2947 switch (xdp->command) { 2948 case XDP_SETUP_PROG: 2949 return igb_xdp_setup(dev, xdp); 2950 case XDP_SETUP_XSK_POOL: 2951 return igb_xsk_pool_setup(adapter, xdp->xsk.pool, 2952 xdp->xsk.queue_id); 2953 default: 2954 return -EINVAL; 2955 } 2956 } 2957 2958 int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp) 2959 { 2960 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2961 int cpu = smp_processor_id(); 2962 struct igb_ring *tx_ring; 2963 struct netdev_queue *nq; 2964 u32 ret; 2965 2966 if (unlikely(!xdpf)) 2967 return IGB_XDP_CONSUMED; 2968 2969 /* During program transitions its possible adapter->xdp_prog is assigned 2970 * but ring has not been configured yet. In this case simply abort xmit. 2971 */ 2972 tx_ring = igb_xdp_is_enabled(adapter) ? 2973 igb_xdp_tx_queue_mapping(adapter) : NULL; 2974 if (unlikely(!tx_ring)) 2975 return IGB_XDP_CONSUMED; 2976 2977 nq = txring_txq(tx_ring); 2978 __netif_tx_lock(nq, cpu); 2979 /* Avoid transmit queue timeout since we share it with the slow path */ 2980 txq_trans_cond_update(nq); 2981 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2982 __netif_tx_unlock(nq); 2983 2984 return ret; 2985 } 2986 2987 static int igb_xdp_xmit(struct net_device *dev, int n, 2988 struct xdp_frame **frames, u32 flags) 2989 { 2990 struct igb_adapter *adapter = netdev_priv(dev); 2991 int cpu = smp_processor_id(); 2992 struct igb_ring *tx_ring; 2993 struct netdev_queue *nq; 2994 int nxmit = 0; 2995 int i; 2996 2997 if (unlikely(test_bit(__IGB_DOWN, &adapter->state))) 2998 return -ENETDOWN; 2999 3000 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 3001 return -EINVAL; 3002 3003 /* During program transitions its possible adapter->xdp_prog is assigned 3004 * but ring has not been configured yet. In this case simply abort xmit. 3005 */ 3006 tx_ring = igb_xdp_is_enabled(adapter) ? 3007 igb_xdp_tx_queue_mapping(adapter) : NULL; 3008 if (unlikely(!tx_ring)) 3009 return -ENXIO; 3010 3011 if (unlikely(test_bit(IGB_RING_FLAG_TX_DISABLED, &tx_ring->flags))) 3012 return -ENXIO; 3013 3014 nq = txring_txq(tx_ring); 3015 __netif_tx_lock(nq, cpu); 3016 3017 /* Avoid transmit queue timeout since we share it with the slow path */ 3018 txq_trans_cond_update(nq); 3019 3020 for (i = 0; i < n; i++) { 3021 struct xdp_frame *xdpf = frames[i]; 3022 int err; 3023 3024 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 3025 if (err != IGB_XDP_TX) 3026 break; 3027 nxmit++; 3028 } 3029 3030 if (unlikely(flags & XDP_XMIT_FLUSH)) 3031 igb_xdp_ring_update_tail(tx_ring); 3032 3033 __netif_tx_unlock(nq); 3034 3035 return nxmit; 3036 } 3037 3038 static const struct net_device_ops igb_netdev_ops = { 3039 .ndo_open = igb_open, 3040 .ndo_stop = igb_close, 3041 .ndo_start_xmit = igb_xmit_frame, 3042 .ndo_get_stats64 = igb_get_stats64, 3043 .ndo_set_rx_mode = igb_set_rx_mode, 3044 .ndo_set_mac_address = igb_set_mac, 3045 .ndo_change_mtu = igb_change_mtu, 3046 .ndo_eth_ioctl = igb_ioctl, 3047 .ndo_tx_timeout = igb_tx_timeout, 3048 .ndo_validate_addr = eth_validate_addr, 3049 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 3050 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 3051 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 3052 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 3053 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 3054 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 3055 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 3056 .ndo_get_vf_config = igb_ndo_get_vf_config, 3057 .ndo_fix_features = igb_fix_features, 3058 .ndo_set_features = igb_set_features, 3059 .ndo_fdb_add = igb_ndo_fdb_add, 3060 .ndo_features_check = igb_features_check, 3061 .ndo_setup_tc = igb_setup_tc, 3062 .ndo_bpf = igb_xdp, 3063 .ndo_xdp_xmit = igb_xdp_xmit, 3064 .ndo_xsk_wakeup = igb_xsk_wakeup, 3065 .ndo_hwtstamp_get = igb_ptp_hwtstamp_get, 3066 .ndo_hwtstamp_set = igb_ptp_hwtstamp_set, 3067 }; 3068 3069 /** 3070 * igb_set_fw_version - Configure version string for ethtool 3071 * @adapter: adapter struct 3072 **/ 3073 void igb_set_fw_version(struct igb_adapter *adapter) 3074 { 3075 struct e1000_hw *hw = &adapter->hw; 3076 struct e1000_fw_version fw; 3077 3078 igb_get_fw_version(hw, &fw); 3079 3080 switch (hw->mac.type) { 3081 case e1000_i210: 3082 case e1000_i211: 3083 if (!(igb_get_flash_presence_i210(hw))) { 3084 snprintf(adapter->fw_version, 3085 sizeof(adapter->fw_version), 3086 "%2d.%2d-%d", 3087 fw.invm_major, fw.invm_minor, 3088 fw.invm_img_type); 3089 break; 3090 } 3091 fallthrough; 3092 default: 3093 /* if option rom is valid, display its version too */ 3094 if (fw.or_valid) { 3095 snprintf(adapter->fw_version, 3096 sizeof(adapter->fw_version), 3097 "%d.%d, 0x%08x, %d.%d.%d", 3098 fw.eep_major, fw.eep_minor, fw.etrack_id, 3099 fw.or_major, fw.or_build, fw.or_patch); 3100 /* no option rom */ 3101 } else if (fw.etrack_id != 0X0000) { 3102 snprintf(adapter->fw_version, 3103 sizeof(adapter->fw_version), 3104 "%d.%d, 0x%08x", 3105 fw.eep_major, fw.eep_minor, fw.etrack_id); 3106 } else { 3107 snprintf(adapter->fw_version, 3108 sizeof(adapter->fw_version), 3109 "%d.%d.%d", 3110 fw.eep_major, fw.eep_minor, fw.eep_build); 3111 } 3112 break; 3113 } 3114 } 3115 3116 /** 3117 * igb_init_mas - init Media Autosense feature if enabled in the NVM 3118 * 3119 * @adapter: adapter struct 3120 **/ 3121 static void igb_init_mas(struct igb_adapter *adapter) 3122 { 3123 struct e1000_hw *hw = &adapter->hw; 3124 u16 eeprom_data; 3125 3126 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 3127 switch (hw->bus.func) { 3128 case E1000_FUNC_0: 3129 if (eeprom_data & IGB_MAS_ENABLE_0) { 3130 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3131 netdev_info(adapter->netdev, 3132 "MAS: Enabling Media Autosense for port %d\n", 3133 hw->bus.func); 3134 } 3135 break; 3136 case E1000_FUNC_1: 3137 if (eeprom_data & IGB_MAS_ENABLE_1) { 3138 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3139 netdev_info(adapter->netdev, 3140 "MAS: Enabling Media Autosense for port %d\n", 3141 hw->bus.func); 3142 } 3143 break; 3144 case E1000_FUNC_2: 3145 if (eeprom_data & IGB_MAS_ENABLE_2) { 3146 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3147 netdev_info(adapter->netdev, 3148 "MAS: Enabling Media Autosense for port %d\n", 3149 hw->bus.func); 3150 } 3151 break; 3152 case E1000_FUNC_3: 3153 if (eeprom_data & IGB_MAS_ENABLE_3) { 3154 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3155 netdev_info(adapter->netdev, 3156 "MAS: Enabling Media Autosense for port %d\n", 3157 hw->bus.func); 3158 } 3159 break; 3160 default: 3161 /* Shouldn't get here */ 3162 netdev_err(adapter->netdev, 3163 "MAS: Invalid port configuration, returning\n"); 3164 break; 3165 } 3166 } 3167 3168 /** 3169 * igb_init_i2c - Init I2C interface 3170 * @adapter: pointer to adapter structure 3171 **/ 3172 static s32 igb_init_i2c(struct igb_adapter *adapter) 3173 { 3174 s32 status = 0; 3175 3176 /* I2C interface supported on i350 devices */ 3177 if (adapter->hw.mac.type != e1000_i350) 3178 return 0; 3179 3180 /* Initialize the i2c bus which is controlled by the registers. 3181 * This bus will use the i2c_algo_bit structure that implements 3182 * the protocol through toggling of the 4 bits in the register. 3183 */ 3184 adapter->i2c_adap.owner = THIS_MODULE; 3185 adapter->i2c_algo = igb_i2c_algo; 3186 adapter->i2c_algo.data = adapter; 3187 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 3188 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 3189 strscpy(adapter->i2c_adap.name, "igb BB", 3190 sizeof(adapter->i2c_adap.name)); 3191 status = i2c_bit_add_bus(&adapter->i2c_adap); 3192 return status; 3193 } 3194 3195 /** 3196 * igb_probe - Device Initialization Routine 3197 * @pdev: PCI device information struct 3198 * @ent: entry in igb_pci_tbl 3199 * 3200 * Returns 0 on success, negative on failure 3201 * 3202 * igb_probe initializes an adapter identified by a pci_dev structure. 3203 * The OS initialization, configuring of the adapter private structure, 3204 * and a hardware reset occur. 3205 **/ 3206 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3207 { 3208 struct net_device *netdev; 3209 struct igb_adapter *adapter; 3210 struct e1000_hw *hw; 3211 u16 eeprom_data = 0; 3212 s32 ret_val; 3213 static int global_quad_port_a; /* global quad port a indication */ 3214 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3215 u8 part_str[E1000_PBANUM_LENGTH]; 3216 int err; 3217 3218 /* Catch broken hardware that put the wrong VF device ID in 3219 * the PCIe SR-IOV capability. 3220 */ 3221 if (pdev->is_virtfn) { 3222 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n", 3223 pci_name(pdev), pdev->vendor, pdev->device); 3224 return -EINVAL; 3225 } 3226 3227 err = pci_enable_device_mem(pdev); 3228 if (err) 3229 return err; 3230 3231 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3232 if (err) { 3233 dev_err(&pdev->dev, 3234 "No usable DMA configuration, aborting\n"); 3235 goto err_dma; 3236 } 3237 3238 err = pci_request_mem_regions(pdev, igb_driver_name); 3239 if (err) 3240 goto err_pci_reg; 3241 3242 pci_set_master(pdev); 3243 pci_save_state(pdev); 3244 3245 err = -ENOMEM; 3246 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3247 IGB_MAX_TX_QUEUES); 3248 if (!netdev) 3249 goto err_alloc_etherdev; 3250 3251 SET_NETDEV_DEV(netdev, &pdev->dev); 3252 3253 pci_set_drvdata(pdev, netdev); 3254 adapter = netdev_priv(netdev); 3255 adapter->netdev = netdev; 3256 adapter->pdev = pdev; 3257 hw = &adapter->hw; 3258 hw->back = adapter; 3259 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3260 3261 err = -EIO; 3262 adapter->io_addr = pci_iomap(pdev, 0, 0); 3263 if (!adapter->io_addr) 3264 goto err_ioremap; 3265 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3266 hw->hw_addr = adapter->io_addr; 3267 3268 netdev->netdev_ops = &igb_netdev_ops; 3269 igb_set_ethtool_ops(netdev); 3270 netdev->watchdog_timeo = 5 * HZ; 3271 3272 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 3273 3274 netdev->mem_start = pci_resource_start(pdev, 0); 3275 netdev->mem_end = pci_resource_end(pdev, 0); 3276 3277 /* PCI config space info */ 3278 hw->vendor_id = pdev->vendor; 3279 hw->device_id = pdev->device; 3280 hw->revision_id = pdev->revision; 3281 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3282 hw->subsystem_device_id = pdev->subsystem_device; 3283 3284 /* Copy the default MAC, PHY and NVM function pointers */ 3285 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3286 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3287 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3288 /* Initialize skew-specific constants */ 3289 err = ei->get_invariants(hw); 3290 if (err) 3291 goto err_sw_init; 3292 3293 /* setup the private structure */ 3294 err = igb_sw_init(adapter); 3295 if (err) 3296 goto err_sw_init; 3297 3298 igb_get_bus_info_pcie(hw); 3299 3300 hw->phy.autoneg_wait_to_complete = false; 3301 3302 /* Copper options */ 3303 if (hw->phy.media_type == e1000_media_type_copper) { 3304 hw->phy.mdix = AUTO_ALL_MODES; 3305 hw->phy.disable_polarity_correction = false; 3306 hw->phy.ms_type = e1000_ms_hw_default; 3307 } 3308 3309 if (igb_check_reset_block(hw)) 3310 dev_info(&pdev->dev, 3311 "PHY reset is blocked due to SOL/IDER session.\n"); 3312 3313 /* features is initialized to 0 in allocation, it might have bits 3314 * set by igb_sw_init so we should use an or instead of an 3315 * assignment. 3316 */ 3317 netdev->features |= NETIF_F_SG | 3318 NETIF_F_TSO | 3319 NETIF_F_TSO6 | 3320 NETIF_F_RXHASH | 3321 NETIF_F_RXCSUM | 3322 NETIF_F_HW_CSUM; 3323 3324 if (hw->mac.type >= e1000_82576) 3325 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 3326 3327 if (hw->mac.type >= e1000_i350) 3328 netdev->features |= NETIF_F_HW_TC; 3329 3330 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3331 NETIF_F_GSO_GRE_CSUM | \ 3332 NETIF_F_GSO_IPXIP4 | \ 3333 NETIF_F_GSO_IPXIP6 | \ 3334 NETIF_F_GSO_UDP_TUNNEL | \ 3335 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3336 3337 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3338 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3339 3340 /* copy netdev features into list of user selectable features */ 3341 netdev->hw_features |= netdev->features | 3342 NETIF_F_HW_VLAN_CTAG_RX | 3343 NETIF_F_HW_VLAN_CTAG_TX | 3344 NETIF_F_RXALL; 3345 3346 if (hw->mac.type >= e1000_i350) 3347 netdev->hw_features |= NETIF_F_NTUPLE; 3348 3349 netdev->features |= NETIF_F_HIGHDMA; 3350 3351 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3352 netdev->mpls_features |= NETIF_F_HW_CSUM; 3353 netdev->hw_enc_features |= netdev->vlan_features; 3354 3355 /* set this bit last since it cannot be part of vlan_features */ 3356 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3357 NETIF_F_HW_VLAN_CTAG_RX | 3358 NETIF_F_HW_VLAN_CTAG_TX; 3359 3360 netdev->priv_flags |= IFF_SUPP_NOFCS; 3361 3362 netdev->priv_flags |= IFF_UNICAST_FLT; 3363 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | 3364 NETDEV_XDP_ACT_XSK_ZEROCOPY; 3365 3366 /* MTU range: 68 - 9216 */ 3367 netdev->min_mtu = ETH_MIN_MTU; 3368 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3369 3370 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3371 3372 /* before reading the NVM, reset the controller to put the device in a 3373 * known good starting state 3374 */ 3375 hw->mac.ops.reset_hw(hw); 3376 3377 /* make sure the NVM is good , i211/i210 parts can have special NVM 3378 * that doesn't contain a checksum 3379 */ 3380 switch (hw->mac.type) { 3381 case e1000_i210: 3382 case e1000_i211: 3383 if (igb_get_flash_presence_i210(hw)) { 3384 if (hw->nvm.ops.validate(hw) < 0) { 3385 dev_err(&pdev->dev, 3386 "The NVM Checksum Is Not Valid\n"); 3387 err = -EIO; 3388 goto err_eeprom; 3389 } 3390 } 3391 break; 3392 default: 3393 if (hw->nvm.ops.validate(hw) < 0) { 3394 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3395 err = -EIO; 3396 goto err_eeprom; 3397 } 3398 break; 3399 } 3400 3401 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3402 /* copy the MAC address out of the NVM */ 3403 if (hw->mac.ops.read_mac_addr(hw)) 3404 dev_err(&pdev->dev, "NVM Read Error\n"); 3405 } 3406 3407 eth_hw_addr_set(netdev, hw->mac.addr); 3408 3409 if (!is_valid_ether_addr(netdev->dev_addr)) { 3410 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3411 err = -EIO; 3412 goto err_eeprom; 3413 } 3414 3415 igb_set_default_mac_filter(adapter); 3416 3417 /* get firmware version for ethtool -i */ 3418 igb_set_fw_version(adapter); 3419 3420 /* configure RXPBSIZE and TXPBSIZE */ 3421 if (hw->mac.type == e1000_i210) { 3422 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3423 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3424 } 3425 3426 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3427 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3428 3429 INIT_WORK(&adapter->reset_task, igb_reset_task); 3430 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3431 3432 /* Initialize link properties that are user-changeable */ 3433 adapter->fc_autoneg = true; 3434 hw->mac.autoneg = true; 3435 hw->phy.autoneg_advertised = 0x2f; 3436 3437 hw->fc.requested_mode = e1000_fc_default; 3438 hw->fc.current_mode = e1000_fc_default; 3439 3440 igb_validate_mdi_setting(hw); 3441 3442 /* By default, support wake on port A */ 3443 if (hw->bus.func == 0) 3444 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3445 3446 /* Check the NVM for wake support on non-port A ports */ 3447 if (hw->mac.type >= e1000_82580) 3448 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3449 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3450 &eeprom_data); 3451 else if (hw->bus.func == 1) 3452 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3453 3454 if (eeprom_data & IGB_EEPROM_APME) 3455 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3456 3457 /* now that we have the eeprom settings, apply the special cases where 3458 * the eeprom may be wrong or the board simply won't support wake on 3459 * lan on a particular port 3460 */ 3461 switch (pdev->device) { 3462 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3463 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3464 break; 3465 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3466 case E1000_DEV_ID_82576_FIBER: 3467 case E1000_DEV_ID_82576_SERDES: 3468 /* Wake events only supported on port A for dual fiber 3469 * regardless of eeprom setting 3470 */ 3471 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3472 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3473 break; 3474 case E1000_DEV_ID_82576_QUAD_COPPER: 3475 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3476 /* if quad port adapter, disable WoL on all but port A */ 3477 if (global_quad_port_a != 0) 3478 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3479 else 3480 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3481 /* Reset for multiple quad port adapters */ 3482 if (++global_quad_port_a == 4) 3483 global_quad_port_a = 0; 3484 break; 3485 default: 3486 /* If the device can't wake, don't set software support */ 3487 if (!device_can_wakeup(&adapter->pdev->dev)) 3488 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3489 } 3490 3491 /* initialize the wol settings based on the eeprom settings */ 3492 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3493 adapter->wol |= E1000_WUFC_MAG; 3494 3495 /* Some vendors want WoL disabled by default, but still supported */ 3496 if ((hw->mac.type == e1000_i350) && 3497 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3498 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3499 adapter->wol = 0; 3500 } 3501 3502 /* Some vendors want the ability to Use the EEPROM setting as 3503 * enable/disable only, and not for capability 3504 */ 3505 if (((hw->mac.type == e1000_i350) || 3506 (hw->mac.type == e1000_i354)) && 3507 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3508 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3509 adapter->wol = 0; 3510 } 3511 if (hw->mac.type == e1000_i350) { 3512 if (((pdev->subsystem_device == 0x5001) || 3513 (pdev->subsystem_device == 0x5002)) && 3514 (hw->bus.func == 0)) { 3515 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3516 adapter->wol = 0; 3517 } 3518 if (pdev->subsystem_device == 0x1F52) 3519 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3520 } 3521 3522 device_set_wakeup_enable(&adapter->pdev->dev, 3523 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3524 3525 /* reset the hardware with the new settings */ 3526 igb_reset(adapter); 3527 3528 /* Init the I2C interface */ 3529 err = igb_init_i2c(adapter); 3530 if (err) { 3531 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3532 goto err_eeprom; 3533 } 3534 3535 /* let the f/w know that the h/w is now under the control of the 3536 * driver. 3537 */ 3538 igb_get_hw_control(adapter); 3539 3540 strcpy(netdev->name, "eth%d"); 3541 err = register_netdev(netdev); 3542 if (err) 3543 goto err_register; 3544 3545 /* carrier off reporting is important to ethtool even BEFORE open */ 3546 netif_carrier_off(netdev); 3547 3548 #ifdef CONFIG_IGB_DCA 3549 if (dca_add_requester(&pdev->dev) == 0) { 3550 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3551 dev_info(&pdev->dev, "DCA enabled\n"); 3552 igb_setup_dca(adapter); 3553 } 3554 3555 #endif 3556 #ifdef CONFIG_IGB_HWMON 3557 /* Initialize the thermal sensor on i350 devices. */ 3558 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3559 u16 ets_word; 3560 3561 /* Read the NVM to determine if this i350 device supports an 3562 * external thermal sensor. 3563 */ 3564 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3565 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3566 adapter->ets = true; 3567 else 3568 adapter->ets = false; 3569 /* Only enable I2C bit banging if an external thermal 3570 * sensor is supported. 3571 */ 3572 if (adapter->ets) 3573 igb_set_i2c_bb(hw); 3574 hw->mac.ops.init_thermal_sensor_thresh(hw); 3575 if (igb_sysfs_init(adapter)) 3576 dev_err(&pdev->dev, 3577 "failed to allocate sysfs resources\n"); 3578 } else { 3579 adapter->ets = false; 3580 } 3581 #endif 3582 /* Check if Media Autosense is enabled */ 3583 adapter->ei = *ei; 3584 if (hw->dev_spec._82575.mas_capable) 3585 igb_init_mas(adapter); 3586 3587 /* do hw tstamp init after resetting */ 3588 igb_ptp_init(adapter); 3589 3590 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3591 /* print bus type/speed/width info, not applicable to i354 */ 3592 if (hw->mac.type != e1000_i354) { 3593 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3594 netdev->name, 3595 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3596 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3597 "unknown"), 3598 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3599 "Width x4" : 3600 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3601 "Width x2" : 3602 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3603 "Width x1" : "unknown"), netdev->dev_addr); 3604 } 3605 3606 if ((hw->mac.type == e1000_82576 && 3607 rd32(E1000_EECD) & E1000_EECD_PRES) || 3608 (hw->mac.type >= e1000_i210 || 3609 igb_get_flash_presence_i210(hw))) { 3610 ret_val = igb_read_part_string(hw, part_str, 3611 E1000_PBANUM_LENGTH); 3612 } else { 3613 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3614 } 3615 3616 if (ret_val) 3617 strcpy(part_str, "Unknown"); 3618 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3619 dev_info(&pdev->dev, 3620 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3621 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3622 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3623 adapter->num_rx_queues, adapter->num_tx_queues); 3624 if (hw->phy.media_type == e1000_media_type_copper) { 3625 switch (hw->mac.type) { 3626 case e1000_i350: 3627 case e1000_i210: 3628 case e1000_i211: 3629 /* Enable EEE for internal copper PHY devices */ 3630 err = igb_set_eee_i350(hw, true, true); 3631 if ((!err) && 3632 (!hw->dev_spec._82575.eee_disable)) { 3633 adapter->eee_advert = 3634 MDIO_EEE_100TX | MDIO_EEE_1000T; 3635 adapter->flags |= IGB_FLAG_EEE; 3636 } 3637 break; 3638 case e1000_i354: 3639 if ((rd32(E1000_CTRL_EXT) & 3640 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3641 err = igb_set_eee_i354(hw, true, true); 3642 if ((!err) && 3643 (!hw->dev_spec._82575.eee_disable)) { 3644 adapter->eee_advert = 3645 MDIO_EEE_100TX | MDIO_EEE_1000T; 3646 adapter->flags |= IGB_FLAG_EEE; 3647 } 3648 } 3649 break; 3650 default: 3651 break; 3652 } 3653 } 3654 3655 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 3656 3657 pm_runtime_put_noidle(&pdev->dev); 3658 return 0; 3659 3660 err_register: 3661 igb_release_hw_control(adapter); 3662 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3663 err_eeprom: 3664 if (!igb_check_reset_block(hw)) 3665 igb_reset_phy(hw); 3666 3667 if (hw->flash_address) 3668 iounmap(hw->flash_address); 3669 err_sw_init: 3670 kfree(adapter->mac_table); 3671 kfree(adapter->shadow_vfta); 3672 igb_clear_interrupt_scheme(adapter); 3673 #ifdef CONFIG_PCI_IOV 3674 igb_disable_sriov(pdev, false); 3675 #endif 3676 pci_iounmap(pdev, adapter->io_addr); 3677 err_ioremap: 3678 free_netdev(netdev); 3679 err_alloc_etherdev: 3680 pci_release_mem_regions(pdev); 3681 err_pci_reg: 3682 err_dma: 3683 pci_disable_device(pdev); 3684 return err; 3685 } 3686 3687 #ifdef CONFIG_PCI_IOV 3688 static int igb_sriov_reinit(struct pci_dev *dev) 3689 { 3690 struct net_device *netdev = pci_get_drvdata(dev); 3691 struct igb_adapter *adapter = netdev_priv(netdev); 3692 struct pci_dev *pdev = adapter->pdev; 3693 3694 rtnl_lock(); 3695 3696 if (netif_running(netdev)) 3697 igb_close(netdev); 3698 else 3699 igb_reset(adapter); 3700 3701 igb_clear_interrupt_scheme(adapter); 3702 3703 igb_init_queue_configuration(adapter); 3704 3705 if (igb_init_interrupt_scheme(adapter, true)) { 3706 rtnl_unlock(); 3707 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3708 return -ENOMEM; 3709 } 3710 3711 if (netif_running(netdev)) 3712 igb_open(netdev); 3713 3714 rtnl_unlock(); 3715 3716 return 0; 3717 } 3718 3719 static int igb_disable_sriov(struct pci_dev *pdev, bool reinit) 3720 { 3721 struct net_device *netdev = pci_get_drvdata(pdev); 3722 struct igb_adapter *adapter = netdev_priv(netdev); 3723 struct e1000_hw *hw = &adapter->hw; 3724 unsigned long flags; 3725 3726 /* reclaim resources allocated to VFs */ 3727 if (adapter->vf_data) { 3728 /* disable iov and allow time for transactions to clear */ 3729 if (pci_vfs_assigned(pdev)) { 3730 dev_warn(&pdev->dev, 3731 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3732 return -EPERM; 3733 } else { 3734 pci_disable_sriov(pdev); 3735 msleep(500); 3736 } 3737 spin_lock_irqsave(&adapter->vfs_lock, flags); 3738 kfree(adapter->vf_mac_list); 3739 adapter->vf_mac_list = NULL; 3740 kfree(adapter->vf_data); 3741 adapter->vf_data = NULL; 3742 adapter->vfs_allocated_count = 0; 3743 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 3744 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3745 wrfl(); 3746 msleep(100); 3747 dev_info(&pdev->dev, "IOV Disabled\n"); 3748 3749 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3750 adapter->flags |= IGB_FLAG_DMAC; 3751 } 3752 3753 return reinit ? igb_sriov_reinit(pdev) : 0; 3754 } 3755 3756 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs, bool reinit) 3757 { 3758 struct net_device *netdev = pci_get_drvdata(pdev); 3759 struct igb_adapter *adapter = netdev_priv(netdev); 3760 int old_vfs = pci_num_vf(pdev); 3761 struct vf_mac_filter *mac_list; 3762 int err = 0; 3763 int num_vf_mac_filters, i; 3764 3765 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3766 err = -EPERM; 3767 goto out; 3768 } 3769 if (!num_vfs) 3770 goto out; 3771 3772 if (old_vfs) { 3773 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3774 old_vfs, max_vfs); 3775 adapter->vfs_allocated_count = old_vfs; 3776 } else 3777 adapter->vfs_allocated_count = num_vfs; 3778 3779 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3780 sizeof(struct vf_data_storage), GFP_KERNEL); 3781 3782 /* if allocation failed then we do not support SR-IOV */ 3783 if (!adapter->vf_data) { 3784 adapter->vfs_allocated_count = 0; 3785 err = -ENOMEM; 3786 goto out; 3787 } 3788 3789 /* Due to the limited number of RAR entries calculate potential 3790 * number of MAC filters available for the VFs. Reserve entries 3791 * for PF default MAC, PF MAC filters and at least one RAR entry 3792 * for each VF for VF MAC. 3793 */ 3794 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3795 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3796 adapter->vfs_allocated_count); 3797 3798 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3799 sizeof(struct vf_mac_filter), 3800 GFP_KERNEL); 3801 3802 mac_list = adapter->vf_mac_list; 3803 INIT_LIST_HEAD(&adapter->vf_macs.l); 3804 3805 if (adapter->vf_mac_list) { 3806 /* Initialize list of VF MAC filters */ 3807 for (i = 0; i < num_vf_mac_filters; i++) { 3808 mac_list->vf = -1; 3809 mac_list->free = true; 3810 list_add(&mac_list->l, &adapter->vf_macs.l); 3811 mac_list++; 3812 } 3813 } else { 3814 /* If we could not allocate memory for the VF MAC filters 3815 * we can continue without this feature but warn user. 3816 */ 3817 dev_err(&pdev->dev, 3818 "Unable to allocate memory for VF MAC filter list\n"); 3819 } 3820 3821 dev_info(&pdev->dev, "%d VFs allocated\n", 3822 adapter->vfs_allocated_count); 3823 for (i = 0; i < adapter->vfs_allocated_count; i++) 3824 igb_vf_configure(adapter, i); 3825 3826 /* DMA Coalescing is not supported in IOV mode. */ 3827 adapter->flags &= ~IGB_FLAG_DMAC; 3828 3829 if (reinit) { 3830 err = igb_sriov_reinit(pdev); 3831 if (err) 3832 goto err_out; 3833 } 3834 3835 /* only call pci_enable_sriov() if no VFs are allocated already */ 3836 if (!old_vfs) { 3837 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3838 if (err) 3839 goto err_out; 3840 } 3841 3842 goto out; 3843 3844 err_out: 3845 kfree(adapter->vf_mac_list); 3846 adapter->vf_mac_list = NULL; 3847 kfree(adapter->vf_data); 3848 adapter->vf_data = NULL; 3849 adapter->vfs_allocated_count = 0; 3850 out: 3851 return err; 3852 } 3853 3854 #endif 3855 /** 3856 * igb_remove_i2c - Cleanup I2C interface 3857 * @adapter: pointer to adapter structure 3858 **/ 3859 static void igb_remove_i2c(struct igb_adapter *adapter) 3860 { 3861 /* free the adapter bus structure */ 3862 i2c_del_adapter(&adapter->i2c_adap); 3863 } 3864 3865 /** 3866 * igb_remove - Device Removal Routine 3867 * @pdev: PCI device information struct 3868 * 3869 * igb_remove is called by the PCI subsystem to alert the driver 3870 * that it should release a PCI device. The could be caused by a 3871 * Hot-Plug event, or because the driver is going to be removed from 3872 * memory. 3873 **/ 3874 static void igb_remove(struct pci_dev *pdev) 3875 { 3876 struct net_device *netdev = pci_get_drvdata(pdev); 3877 struct igb_adapter *adapter = netdev_priv(netdev); 3878 struct e1000_hw *hw = &adapter->hw; 3879 3880 pm_runtime_get_noresume(&pdev->dev); 3881 #ifdef CONFIG_IGB_HWMON 3882 igb_sysfs_exit(adapter); 3883 #endif 3884 igb_remove_i2c(adapter); 3885 igb_ptp_stop(adapter); 3886 /* The watchdog timer may be rescheduled, so explicitly 3887 * disable watchdog from being rescheduled. 3888 */ 3889 set_bit(__IGB_DOWN, &adapter->state); 3890 timer_delete_sync(&adapter->watchdog_timer); 3891 timer_delete_sync(&adapter->phy_info_timer); 3892 3893 cancel_work_sync(&adapter->reset_task); 3894 cancel_work_sync(&adapter->watchdog_task); 3895 3896 #ifdef CONFIG_IGB_DCA 3897 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3898 dev_info(&pdev->dev, "DCA disabled\n"); 3899 dca_remove_requester(&pdev->dev); 3900 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3901 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3902 } 3903 #endif 3904 3905 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3906 * would have already happened in close and is redundant. 3907 */ 3908 igb_release_hw_control(adapter); 3909 3910 #ifdef CONFIG_PCI_IOV 3911 igb_disable_sriov(pdev, false); 3912 #endif 3913 3914 unregister_netdev(netdev); 3915 3916 igb_clear_interrupt_scheme(adapter); 3917 3918 pci_iounmap(pdev, adapter->io_addr); 3919 if (hw->flash_address) 3920 iounmap(hw->flash_address); 3921 pci_release_mem_regions(pdev); 3922 3923 kfree(adapter->mac_table); 3924 kfree(adapter->shadow_vfta); 3925 free_netdev(netdev); 3926 3927 pci_disable_device(pdev); 3928 } 3929 3930 /** 3931 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3932 * @adapter: board private structure to initialize 3933 * 3934 * This function initializes the vf specific data storage and then attempts to 3935 * allocate the VFs. The reason for ordering it this way is because it is much 3936 * more expensive time wise to disable SR-IOV than it is to allocate and free 3937 * the memory for the VFs. 3938 **/ 3939 static void igb_probe_vfs(struct igb_adapter *adapter) 3940 { 3941 #ifdef CONFIG_PCI_IOV 3942 struct pci_dev *pdev = adapter->pdev; 3943 struct e1000_hw *hw = &adapter->hw; 3944 3945 /* Virtualization features not supported on i210 and 82580 family. */ 3946 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211) || 3947 (hw->mac.type == e1000_82580)) 3948 return; 3949 3950 /* Of the below we really only want the effect of getting 3951 * IGB_FLAG_HAS_MSIX set (if available), without which 3952 * igb_enable_sriov() has no effect. 3953 */ 3954 igb_set_interrupt_capability(adapter, true); 3955 igb_reset_interrupt_capability(adapter); 3956 3957 pci_sriov_set_totalvfs(pdev, 7); 3958 igb_enable_sriov(pdev, max_vfs, false); 3959 3960 #endif /* CONFIG_PCI_IOV */ 3961 } 3962 3963 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3964 { 3965 struct e1000_hw *hw = &adapter->hw; 3966 unsigned int max_rss_queues; 3967 3968 /* Determine the maximum number of RSS queues supported. */ 3969 switch (hw->mac.type) { 3970 case e1000_i211: 3971 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3972 break; 3973 case e1000_82575: 3974 case e1000_i210: 3975 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3976 break; 3977 case e1000_i350: 3978 /* I350 cannot do RSS and SR-IOV at the same time */ 3979 if (!!adapter->vfs_allocated_count) { 3980 max_rss_queues = 1; 3981 break; 3982 } 3983 fallthrough; 3984 case e1000_82576: 3985 if (!!adapter->vfs_allocated_count) { 3986 max_rss_queues = 2; 3987 break; 3988 } 3989 fallthrough; 3990 case e1000_82580: 3991 case e1000_i354: 3992 default: 3993 max_rss_queues = IGB_MAX_RX_QUEUES; 3994 break; 3995 } 3996 3997 return max_rss_queues; 3998 } 3999 4000 static void igb_init_queue_configuration(struct igb_adapter *adapter) 4001 { 4002 u32 max_rss_queues; 4003 4004 max_rss_queues = igb_get_max_rss_queues(adapter); 4005 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 4006 4007 igb_set_flag_queue_pairs(adapter, max_rss_queues); 4008 } 4009 4010 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 4011 const u32 max_rss_queues) 4012 { 4013 struct e1000_hw *hw = &adapter->hw; 4014 4015 /* Determine if we need to pair queues. */ 4016 switch (hw->mac.type) { 4017 case e1000_82575: 4018 case e1000_i211: 4019 /* Device supports enough interrupts without queue pairing. */ 4020 break; 4021 case e1000_82576: 4022 case e1000_82580: 4023 case e1000_i350: 4024 case e1000_i354: 4025 case e1000_i210: 4026 default: 4027 /* If rss_queues > half of max_rss_queues, pair the queues in 4028 * order to conserve interrupts due to limited supply. 4029 */ 4030 if (adapter->rss_queues > (max_rss_queues / 2)) 4031 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 4032 else 4033 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 4034 break; 4035 } 4036 } 4037 4038 /** 4039 * igb_sw_init - Initialize general software structures (struct igb_adapter) 4040 * @adapter: board private structure to initialize 4041 * 4042 * igb_sw_init initializes the Adapter private data structure. 4043 * Fields are initialized based on PCI device information and 4044 * OS network device settings (MTU size). 4045 **/ 4046 static int igb_sw_init(struct igb_adapter *adapter) 4047 { 4048 struct e1000_hw *hw = &adapter->hw; 4049 struct net_device *netdev = adapter->netdev; 4050 struct pci_dev *pdev = adapter->pdev; 4051 4052 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 4053 4054 /* set default ring sizes */ 4055 adapter->tx_ring_count = IGB_DEFAULT_TXD; 4056 adapter->rx_ring_count = IGB_DEFAULT_RXD; 4057 4058 /* set default ITR values */ 4059 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 4060 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 4061 4062 /* set default work limits */ 4063 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 4064 4065 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD; 4066 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4067 4068 spin_lock_init(&adapter->nfc_lock); 4069 spin_lock_init(&adapter->stats64_lock); 4070 4071 /* init spinlock to avoid concurrency of VF resources */ 4072 spin_lock_init(&adapter->vfs_lock); 4073 #ifdef CONFIG_PCI_IOV 4074 switch (hw->mac.type) { 4075 case e1000_82576: 4076 case e1000_i350: 4077 if (max_vfs > 7) { 4078 dev_warn(&pdev->dev, 4079 "Maximum of 7 VFs per PF, using max\n"); 4080 max_vfs = adapter->vfs_allocated_count = 7; 4081 } else 4082 adapter->vfs_allocated_count = max_vfs; 4083 if (adapter->vfs_allocated_count) 4084 dev_warn(&pdev->dev, 4085 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 4086 break; 4087 default: 4088 break; 4089 } 4090 #endif /* CONFIG_PCI_IOV */ 4091 4092 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 4093 adapter->flags |= IGB_FLAG_HAS_MSIX; 4094 4095 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 4096 sizeof(struct igb_mac_addr), 4097 GFP_KERNEL); 4098 if (!adapter->mac_table) 4099 return -ENOMEM; 4100 4101 igb_probe_vfs(adapter); 4102 4103 igb_init_queue_configuration(adapter); 4104 4105 /* Setup and initialize a copy of the hw vlan table array */ 4106 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 4107 GFP_KERNEL); 4108 if (!adapter->shadow_vfta) 4109 return -ENOMEM; 4110 4111 /* This call may decrease the number of queues */ 4112 if (igb_init_interrupt_scheme(adapter, true)) { 4113 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4114 return -ENOMEM; 4115 } 4116 4117 /* Explicitly disable IRQ since the NIC can be in any state. */ 4118 igb_irq_disable(adapter); 4119 4120 if (hw->mac.type >= e1000_i350) 4121 adapter->flags &= ~IGB_FLAG_DMAC; 4122 4123 set_bit(__IGB_DOWN, &adapter->state); 4124 return 0; 4125 } 4126 4127 /** 4128 * __igb_open - Called when a network interface is made active 4129 * @netdev: network interface device structure 4130 * @resuming: indicates whether we are in a resume call 4131 * 4132 * Returns 0 on success, negative value on failure 4133 * 4134 * The open entry point is called when a network interface is made 4135 * active by the system (IFF_UP). At this point all resources needed 4136 * for transmit and receive operations are allocated, the interrupt 4137 * handler is registered with the OS, the watchdog timer is started, 4138 * and the stack is notified that the interface is ready. 4139 **/ 4140 static int __igb_open(struct net_device *netdev, bool resuming) 4141 { 4142 struct igb_adapter *adapter = netdev_priv(netdev); 4143 struct pci_dev *pdev = adapter->pdev; 4144 struct e1000_hw *hw = &adapter->hw; 4145 struct napi_struct *napi; 4146 int err; 4147 int i; 4148 4149 /* disallow open during test */ 4150 if (test_bit(__IGB_TESTING, &adapter->state)) { 4151 WARN_ON(resuming); 4152 return -EBUSY; 4153 } 4154 4155 if (!resuming) 4156 pm_runtime_get_sync(&pdev->dev); 4157 4158 netif_carrier_off(netdev); 4159 4160 /* allocate transmit descriptors */ 4161 err = igb_setup_all_tx_resources(adapter); 4162 if (err) 4163 goto err_setup_tx; 4164 4165 /* allocate receive descriptors */ 4166 err = igb_setup_all_rx_resources(adapter); 4167 if (err) 4168 goto err_setup_rx; 4169 4170 igb_power_up_link(adapter); 4171 4172 /* before we allocate an interrupt, we must be ready to handle it. 4173 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4174 * as soon as we call pci_request_irq, so we have to setup our 4175 * clean_rx handler before we do so. 4176 */ 4177 igb_configure(adapter); 4178 4179 err = igb_request_irq(adapter); 4180 if (err) 4181 goto err_req_irq; 4182 4183 /* Notify the stack of the actual queue counts. */ 4184 err = netif_set_real_num_tx_queues(adapter->netdev, 4185 adapter->num_tx_queues); 4186 if (err) 4187 goto err_set_queues; 4188 4189 err = netif_set_real_num_rx_queues(adapter->netdev, 4190 adapter->num_rx_queues); 4191 if (err) 4192 goto err_set_queues; 4193 4194 /* From here on the code is the same as igb_up() */ 4195 clear_bit(__IGB_DOWN, &adapter->state); 4196 4197 for (i = 0; i < adapter->num_q_vectors; i++) { 4198 napi = &adapter->q_vector[i]->napi; 4199 napi_enable(napi); 4200 igb_set_queue_napi(adapter, i, napi); 4201 } 4202 4203 /* Clear any pending interrupts. */ 4204 rd32(E1000_TSICR); 4205 rd32(E1000_ICR); 4206 4207 igb_irq_enable(adapter); 4208 4209 /* notify VFs that reset has been completed */ 4210 if (adapter->vfs_allocated_count) { 4211 u32 reg_data = rd32(E1000_CTRL_EXT); 4212 4213 reg_data |= E1000_CTRL_EXT_PFRSTD; 4214 wr32(E1000_CTRL_EXT, reg_data); 4215 } 4216 4217 netif_tx_start_all_queues(netdev); 4218 4219 if (!resuming) 4220 pm_runtime_put(&pdev->dev); 4221 4222 /* start the watchdog. */ 4223 hw->mac.get_link_status = 1; 4224 schedule_work(&adapter->watchdog_task); 4225 4226 return 0; 4227 4228 err_set_queues: 4229 igb_free_irq(adapter); 4230 err_req_irq: 4231 igb_release_hw_control(adapter); 4232 igb_power_down_link(adapter); 4233 igb_free_all_rx_resources(adapter); 4234 err_setup_rx: 4235 igb_free_all_tx_resources(adapter); 4236 err_setup_tx: 4237 igb_reset(adapter); 4238 if (!resuming) 4239 pm_runtime_put(&pdev->dev); 4240 4241 return err; 4242 } 4243 4244 int igb_open(struct net_device *netdev) 4245 { 4246 return __igb_open(netdev, false); 4247 } 4248 4249 /** 4250 * __igb_close - Disables a network interface 4251 * @netdev: network interface device structure 4252 * @suspending: indicates we are in a suspend call 4253 * 4254 * Returns 0, this is not allowed to fail 4255 * 4256 * The close entry point is called when an interface is de-activated 4257 * by the OS. The hardware is still under the driver's control, but 4258 * needs to be disabled. A global MAC reset is issued to stop the 4259 * hardware, and all transmit and receive resources are freed. 4260 **/ 4261 static int __igb_close(struct net_device *netdev, bool suspending) 4262 { 4263 struct igb_adapter *adapter = netdev_priv(netdev); 4264 struct pci_dev *pdev = adapter->pdev; 4265 4266 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4267 4268 if (!suspending) 4269 pm_runtime_get_sync(&pdev->dev); 4270 4271 igb_down(adapter); 4272 igb_free_irq(adapter); 4273 4274 igb_free_all_tx_resources(adapter); 4275 igb_free_all_rx_resources(adapter); 4276 4277 if (!suspending) 4278 pm_runtime_put_sync(&pdev->dev); 4279 return 0; 4280 } 4281 4282 int igb_close(struct net_device *netdev) 4283 { 4284 if (netif_device_present(netdev) || netdev->dismantle) 4285 return __igb_close(netdev, false); 4286 return 0; 4287 } 4288 4289 /** 4290 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4291 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4292 * 4293 * Return 0 on success, negative on failure 4294 **/ 4295 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4296 { 4297 struct device *dev = tx_ring->dev; 4298 int size; 4299 4300 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4301 4302 tx_ring->tx_buffer_info = vmalloc(size); 4303 if (!tx_ring->tx_buffer_info) 4304 goto err; 4305 4306 /* round up to nearest 4K */ 4307 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4308 tx_ring->size = ALIGN(tx_ring->size, 4096); 4309 4310 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4311 &tx_ring->dma, GFP_KERNEL); 4312 if (!tx_ring->desc) 4313 goto err; 4314 4315 tx_ring->next_to_use = 0; 4316 tx_ring->next_to_clean = 0; 4317 4318 return 0; 4319 4320 err: 4321 vfree(tx_ring->tx_buffer_info); 4322 tx_ring->tx_buffer_info = NULL; 4323 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4324 return -ENOMEM; 4325 } 4326 4327 /** 4328 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4329 * (Descriptors) for all queues 4330 * @adapter: board private structure 4331 * 4332 * Return 0 on success, negative on failure 4333 **/ 4334 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4335 { 4336 struct pci_dev *pdev = adapter->pdev; 4337 int i, err = 0; 4338 4339 for (i = 0; i < adapter->num_tx_queues; i++) { 4340 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4341 if (err) { 4342 dev_err(&pdev->dev, 4343 "Allocation for Tx Queue %u failed\n", i); 4344 for (i--; i >= 0; i--) 4345 igb_free_tx_resources(adapter->tx_ring[i]); 4346 break; 4347 } 4348 } 4349 4350 return err; 4351 } 4352 4353 /** 4354 * igb_setup_tctl - configure the transmit control registers 4355 * @adapter: Board private structure 4356 **/ 4357 void igb_setup_tctl(struct igb_adapter *adapter) 4358 { 4359 struct e1000_hw *hw = &adapter->hw; 4360 u32 tctl; 4361 4362 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4363 wr32(E1000_TXDCTL(0), 0); 4364 4365 /* Program the Transmit Control Register */ 4366 tctl = rd32(E1000_TCTL); 4367 tctl &= ~E1000_TCTL_CT; 4368 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4369 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4370 4371 igb_config_collision_dist(hw); 4372 4373 /* Enable transmits */ 4374 tctl |= E1000_TCTL_EN; 4375 4376 wr32(E1000_TCTL, tctl); 4377 } 4378 4379 /** 4380 * igb_configure_tx_ring - Configure transmit ring after Reset 4381 * @adapter: board private structure 4382 * @ring: tx ring to configure 4383 * 4384 * Configure a transmit ring after a reset. 4385 **/ 4386 void igb_configure_tx_ring(struct igb_adapter *adapter, 4387 struct igb_ring *ring) 4388 { 4389 struct e1000_hw *hw = &adapter->hw; 4390 u32 txdctl = 0; 4391 u64 tdba = ring->dma; 4392 int reg_idx = ring->reg_idx; 4393 4394 WRITE_ONCE(ring->xsk_pool, igb_xsk_pool(adapter, ring)); 4395 4396 wr32(E1000_TDLEN(reg_idx), 4397 ring->count * sizeof(union e1000_adv_tx_desc)); 4398 wr32(E1000_TDBAL(reg_idx), 4399 tdba & 0x00000000ffffffffULL); 4400 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4401 4402 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4403 wr32(E1000_TDH(reg_idx), 0); 4404 writel(0, ring->tail); 4405 4406 txdctl |= IGB_TX_PTHRESH; 4407 txdctl |= IGB_TX_HTHRESH << 8; 4408 txdctl |= IGB_TX_WTHRESH << 16; 4409 4410 /* reinitialize tx_buffer_info */ 4411 memset(ring->tx_buffer_info, 0, 4412 sizeof(struct igb_tx_buffer) * ring->count); 4413 4414 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4415 wr32(E1000_TXDCTL(reg_idx), txdctl); 4416 } 4417 4418 /** 4419 * igb_configure_tx - Configure transmit Unit after Reset 4420 * @adapter: board private structure 4421 * 4422 * Configure the Tx unit of the MAC after a reset. 4423 **/ 4424 static void igb_configure_tx(struct igb_adapter *adapter) 4425 { 4426 struct e1000_hw *hw = &adapter->hw; 4427 int i; 4428 4429 /* disable the queues */ 4430 for (i = 0; i < adapter->num_tx_queues; i++) 4431 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4432 4433 wrfl(); 4434 usleep_range(10000, 20000); 4435 4436 for (i = 0; i < adapter->num_tx_queues; i++) 4437 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4438 } 4439 4440 /** 4441 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4442 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4443 * 4444 * Returns 0 on success, negative on failure 4445 **/ 4446 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4447 { 4448 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev); 4449 struct device *dev = rx_ring->dev; 4450 int size, res; 4451 4452 /* XDP RX-queue info */ 4453 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq)) 4454 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4455 res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 4456 rx_ring->queue_index, 4457 rx_ring->q_vector->napi.napi_id); 4458 if (res < 0) { 4459 dev_err(dev, "Failed to register xdp_rxq index %u\n", 4460 rx_ring->queue_index); 4461 return res; 4462 } 4463 4464 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4465 4466 rx_ring->rx_buffer_info = vmalloc(size); 4467 if (!rx_ring->rx_buffer_info) 4468 goto err; 4469 4470 /* Round up to nearest 4K */ 4471 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4472 rx_ring->size = ALIGN(rx_ring->size, 4096); 4473 4474 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4475 &rx_ring->dma, GFP_KERNEL); 4476 if (!rx_ring->desc) 4477 goto err; 4478 4479 rx_ring->next_to_alloc = 0; 4480 rx_ring->next_to_clean = 0; 4481 rx_ring->next_to_use = 0; 4482 4483 rx_ring->xdp_prog = adapter->xdp_prog; 4484 4485 return 0; 4486 4487 err: 4488 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4489 vfree(rx_ring->rx_buffer_info); 4490 rx_ring->rx_buffer_info = NULL; 4491 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4492 return -ENOMEM; 4493 } 4494 4495 /** 4496 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4497 * (Descriptors) for all queues 4498 * @adapter: board private structure 4499 * 4500 * Return 0 on success, negative on failure 4501 **/ 4502 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4503 { 4504 struct pci_dev *pdev = adapter->pdev; 4505 int i, err = 0; 4506 4507 for (i = 0; i < adapter->num_rx_queues; i++) { 4508 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4509 if (err) { 4510 dev_err(&pdev->dev, 4511 "Allocation for Rx Queue %u failed\n", i); 4512 for (i--; i >= 0; i--) 4513 igb_free_rx_resources(adapter->rx_ring[i]); 4514 break; 4515 } 4516 } 4517 4518 return err; 4519 } 4520 4521 /** 4522 * igb_setup_mrqc - configure the multiple receive queue control registers 4523 * @adapter: Board private structure 4524 **/ 4525 static void igb_setup_mrqc(struct igb_adapter *adapter) 4526 { 4527 struct e1000_hw *hw = &adapter->hw; 4528 u32 mrqc, rxcsum; 4529 u32 j, num_rx_queues; 4530 u32 rss_key[10]; 4531 4532 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4533 for (j = 0; j < 10; j++) 4534 wr32(E1000_RSSRK(j), rss_key[j]); 4535 4536 num_rx_queues = adapter->rss_queues; 4537 4538 switch (hw->mac.type) { 4539 case e1000_82576: 4540 /* 82576 supports 2 RSS queues for SR-IOV */ 4541 if (adapter->vfs_allocated_count) 4542 num_rx_queues = 2; 4543 break; 4544 default: 4545 break; 4546 } 4547 4548 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4549 for (j = 0; j < IGB_RETA_SIZE; j++) 4550 adapter->rss_indir_tbl[j] = 4551 (j * num_rx_queues) / IGB_RETA_SIZE; 4552 adapter->rss_indir_tbl_init = num_rx_queues; 4553 } 4554 igb_write_rss_indir_tbl(adapter); 4555 4556 /* Disable raw packet checksumming so that RSS hash is placed in 4557 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4558 * offloads as they are enabled by default 4559 */ 4560 rxcsum = rd32(E1000_RXCSUM); 4561 rxcsum |= E1000_RXCSUM_PCSD; 4562 4563 if (adapter->hw.mac.type >= e1000_82576) 4564 /* Enable Receive Checksum Offload for SCTP */ 4565 rxcsum |= E1000_RXCSUM_CRCOFL; 4566 4567 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4568 wr32(E1000_RXCSUM, rxcsum); 4569 4570 /* Generate RSS hash based on packet types, TCP/UDP 4571 * port numbers and/or IPv4/v6 src and dst addresses 4572 */ 4573 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4574 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4575 E1000_MRQC_RSS_FIELD_IPV6 | 4576 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4577 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4578 4579 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4580 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4581 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4582 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4583 4584 /* If VMDq is enabled then we set the appropriate mode for that, else 4585 * we default to RSS so that an RSS hash is calculated per packet even 4586 * if we are only using one queue 4587 */ 4588 if (adapter->vfs_allocated_count) { 4589 if (hw->mac.type > e1000_82575) { 4590 /* Set the default pool for the PF's first queue */ 4591 u32 vtctl = rd32(E1000_VT_CTL); 4592 4593 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4594 E1000_VT_CTL_DISABLE_DEF_POOL); 4595 vtctl |= adapter->vfs_allocated_count << 4596 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4597 wr32(E1000_VT_CTL, vtctl); 4598 } 4599 if (adapter->rss_queues > 1) 4600 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4601 else 4602 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4603 } else { 4604 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4605 } 4606 igb_vmm_control(adapter); 4607 4608 wr32(E1000_MRQC, mrqc); 4609 } 4610 4611 /** 4612 * igb_setup_rctl - configure the receive control registers 4613 * @adapter: Board private structure 4614 **/ 4615 void igb_setup_rctl(struct igb_adapter *adapter) 4616 { 4617 struct e1000_hw *hw = &adapter->hw; 4618 u32 rctl; 4619 4620 rctl = rd32(E1000_RCTL); 4621 4622 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4623 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4624 4625 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4626 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4627 4628 /* enable stripping of CRC. It's unlikely this will break BMC 4629 * redirection as it did with e1000. Newer features require 4630 * that the HW strips the CRC. 4631 */ 4632 rctl |= E1000_RCTL_SECRC; 4633 4634 /* disable store bad packets and clear size bits. */ 4635 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4636 4637 /* enable LPE to allow for reception of jumbo frames */ 4638 rctl |= E1000_RCTL_LPE; 4639 4640 /* disable queue 0 to prevent tail write w/o re-config */ 4641 wr32(E1000_RXDCTL(0), 0); 4642 4643 /* Attention!!! For SR-IOV PF driver operations you must enable 4644 * queue drop for all VF and PF queues to prevent head of line blocking 4645 * if an un-trusted VF does not provide descriptors to hardware. 4646 */ 4647 if (adapter->vfs_allocated_count) { 4648 /* set all queue drop enable bits */ 4649 wr32(E1000_QDE, ALL_QUEUES); 4650 } 4651 4652 /* This is useful for sniffing bad packets. */ 4653 if (adapter->netdev->features & NETIF_F_RXALL) { 4654 /* UPE and MPE will be handled by normal PROMISC logic 4655 * in e1000e_set_rx_mode 4656 */ 4657 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4658 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4659 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4660 4661 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4662 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4663 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4664 * and that breaks VLANs. 4665 */ 4666 } 4667 4668 wr32(E1000_RCTL, rctl); 4669 } 4670 4671 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4672 int vfn) 4673 { 4674 struct e1000_hw *hw = &adapter->hw; 4675 u32 vmolr; 4676 4677 if (size > MAX_JUMBO_FRAME_SIZE) 4678 size = MAX_JUMBO_FRAME_SIZE; 4679 4680 vmolr = rd32(E1000_VMOLR(vfn)); 4681 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4682 vmolr |= size | E1000_VMOLR_LPE; 4683 wr32(E1000_VMOLR(vfn), vmolr); 4684 4685 return 0; 4686 } 4687 4688 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4689 int vfn, bool enable) 4690 { 4691 struct e1000_hw *hw = &adapter->hw; 4692 u32 val, reg; 4693 4694 if (hw->mac.type < e1000_82576) 4695 return; 4696 4697 if (hw->mac.type == e1000_i350) 4698 reg = E1000_DVMOLR(vfn); 4699 else 4700 reg = E1000_VMOLR(vfn); 4701 4702 val = rd32(reg); 4703 if (enable) 4704 val |= E1000_VMOLR_STRVLAN; 4705 else 4706 val &= ~(E1000_VMOLR_STRVLAN); 4707 wr32(reg, val); 4708 } 4709 4710 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4711 int vfn, bool aupe) 4712 { 4713 struct e1000_hw *hw = &adapter->hw; 4714 u32 vmolr; 4715 4716 /* This register exists only on 82576 and newer so if we are older then 4717 * we should exit and do nothing 4718 */ 4719 if (hw->mac.type < e1000_82576) 4720 return; 4721 4722 vmolr = rd32(E1000_VMOLR(vfn)); 4723 if (aupe) 4724 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4725 else 4726 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4727 4728 /* clear all bits that might not be set */ 4729 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4730 4731 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4732 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4733 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4734 * multicast packets 4735 */ 4736 if (vfn <= adapter->vfs_allocated_count) 4737 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4738 4739 wr32(E1000_VMOLR(vfn), vmolr); 4740 } 4741 4742 /** 4743 * igb_setup_srrctl - configure the split and replication receive control 4744 * registers 4745 * @adapter: Board private structure 4746 * @ring: receive ring to be configured 4747 **/ 4748 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring) 4749 { 4750 struct e1000_hw *hw = &adapter->hw; 4751 int reg_idx = ring->reg_idx; 4752 u32 srrctl = 0; 4753 u32 buf_size; 4754 4755 if (ring->xsk_pool) 4756 buf_size = xsk_pool_get_rx_frame_size(ring->xsk_pool); 4757 else if (ring_uses_large_buffer(ring)) 4758 buf_size = IGB_RXBUFFER_3072; 4759 else 4760 buf_size = IGB_RXBUFFER_2048; 4761 4762 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4763 srrctl |= buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4764 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4765 if (hw->mac.type >= e1000_82580) 4766 srrctl |= E1000_SRRCTL_TIMESTAMP; 4767 /* Only set Drop Enable if VFs allocated, or we are supporting multiple 4768 * queues and rx flow control is disabled 4769 */ 4770 if (adapter->vfs_allocated_count || 4771 (!(hw->fc.current_mode & e1000_fc_rx_pause) && 4772 adapter->num_rx_queues > 1)) 4773 srrctl |= E1000_SRRCTL_DROP_EN; 4774 4775 wr32(E1000_SRRCTL(reg_idx), srrctl); 4776 } 4777 4778 /** 4779 * igb_configure_rx_ring - Configure a receive ring after Reset 4780 * @adapter: board private structure 4781 * @ring: receive ring to be configured 4782 * 4783 * Configure the Rx unit of the MAC after a reset. 4784 **/ 4785 void igb_configure_rx_ring(struct igb_adapter *adapter, 4786 struct igb_ring *ring) 4787 { 4788 struct e1000_hw *hw = &adapter->hw; 4789 union e1000_adv_rx_desc *rx_desc; 4790 u64 rdba = ring->dma; 4791 int reg_idx = ring->reg_idx; 4792 u32 rxdctl = 0; 4793 4794 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4795 WRITE_ONCE(ring->xsk_pool, igb_xsk_pool(adapter, ring)); 4796 if (ring->xsk_pool) { 4797 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4798 MEM_TYPE_XSK_BUFF_POOL, 4799 NULL)); 4800 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq); 4801 } else { 4802 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4803 MEM_TYPE_PAGE_SHARED, 4804 NULL)); 4805 } 4806 4807 /* disable the queue */ 4808 wr32(E1000_RXDCTL(reg_idx), 0); 4809 4810 /* Set DMA base address registers */ 4811 wr32(E1000_RDBAL(reg_idx), 4812 rdba & 0x00000000ffffffffULL); 4813 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4814 wr32(E1000_RDLEN(reg_idx), 4815 ring->count * sizeof(union e1000_adv_rx_desc)); 4816 4817 /* initialize head and tail */ 4818 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4819 wr32(E1000_RDH(reg_idx), 0); 4820 writel(0, ring->tail); 4821 4822 /* set descriptor configuration */ 4823 igb_setup_srrctl(adapter, ring); 4824 4825 /* set filtering for VMDQ pools */ 4826 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4827 4828 rxdctl |= IGB_RX_PTHRESH; 4829 rxdctl |= IGB_RX_HTHRESH << 8; 4830 rxdctl |= IGB_RX_WTHRESH << 16; 4831 4832 if (ring->xsk_pool) 4833 memset(ring->rx_buffer_info_zc, 0, 4834 sizeof(*ring->rx_buffer_info_zc) * ring->count); 4835 else 4836 memset(ring->rx_buffer_info, 0, 4837 sizeof(*ring->rx_buffer_info) * ring->count); 4838 4839 /* initialize Rx descriptor 0 */ 4840 rx_desc = IGB_RX_DESC(ring, 0); 4841 rx_desc->wb.upper.length = 0; 4842 4843 /* enable receive descriptor fetching */ 4844 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4845 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4846 } 4847 4848 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4849 struct igb_ring *rx_ring) 4850 { 4851 #if (PAGE_SIZE < 8192) 4852 struct e1000_hw *hw = &adapter->hw; 4853 #endif 4854 4855 /* set build_skb and buffer size flags */ 4856 clear_ring_build_skb_enabled(rx_ring); 4857 clear_ring_uses_large_buffer(rx_ring); 4858 4859 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4860 return; 4861 4862 set_ring_build_skb_enabled(rx_ring); 4863 4864 #if (PAGE_SIZE < 8192) 4865 if (adapter->max_frame_size > IGB_MAX_FRAME_BUILD_SKB || 4866 IGB_2K_TOO_SMALL_WITH_PADDING || 4867 rd32(E1000_RCTL) & E1000_RCTL_SBP) 4868 set_ring_uses_large_buffer(rx_ring); 4869 #endif 4870 } 4871 4872 /** 4873 * igb_configure_rx - Configure receive Unit after Reset 4874 * @adapter: board private structure 4875 * 4876 * Configure the Rx unit of the MAC after a reset. 4877 **/ 4878 static void igb_configure_rx(struct igb_adapter *adapter) 4879 { 4880 int i; 4881 4882 /* set the correct pool for the PF default MAC address in entry 0 */ 4883 igb_set_default_mac_filter(adapter); 4884 4885 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4886 * the Base and Length of the Rx Descriptor Ring 4887 */ 4888 for (i = 0; i < adapter->num_rx_queues; i++) { 4889 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4890 4891 igb_set_rx_buffer_len(adapter, rx_ring); 4892 igb_configure_rx_ring(adapter, rx_ring); 4893 } 4894 } 4895 4896 /** 4897 * igb_free_tx_resources - Free Tx Resources per Queue 4898 * @tx_ring: Tx descriptor ring for a specific queue 4899 * 4900 * Free all transmit software resources 4901 **/ 4902 void igb_free_tx_resources(struct igb_ring *tx_ring) 4903 { 4904 igb_clean_tx_ring(tx_ring); 4905 4906 vfree(tx_ring->tx_buffer_info); 4907 tx_ring->tx_buffer_info = NULL; 4908 4909 /* if not set, then don't free */ 4910 if (!tx_ring->desc) 4911 return; 4912 4913 dma_free_coherent(tx_ring->dev, tx_ring->size, 4914 tx_ring->desc, tx_ring->dma); 4915 4916 tx_ring->desc = NULL; 4917 } 4918 4919 /** 4920 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4921 * @adapter: board private structure 4922 * 4923 * Free all transmit software resources 4924 **/ 4925 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4926 { 4927 int i; 4928 4929 for (i = 0; i < adapter->num_tx_queues; i++) 4930 if (adapter->tx_ring[i]) 4931 igb_free_tx_resources(adapter->tx_ring[i]); 4932 } 4933 4934 /** 4935 * igb_clean_tx_ring - Free Tx Buffers 4936 * @tx_ring: ring to be cleaned 4937 **/ 4938 void igb_clean_tx_ring(struct igb_ring *tx_ring) 4939 { 4940 u16 i = tx_ring->next_to_clean; 4941 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4942 u32 xsk_frames = 0; 4943 4944 while (i != tx_ring->next_to_use) { 4945 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4946 4947 /* Free all the Tx ring sk_buffs or xdp frames */ 4948 if (tx_buffer->type == IGB_TYPE_SKB) { 4949 dev_kfree_skb_any(tx_buffer->skb); 4950 } else if (tx_buffer->type == IGB_TYPE_XDP) { 4951 xdp_return_frame(tx_buffer->xdpf); 4952 } else if (tx_buffer->type == IGB_TYPE_XSK) { 4953 xsk_frames++; 4954 goto skip_for_xsk; 4955 } 4956 4957 /* unmap skb header data */ 4958 dma_unmap_single(tx_ring->dev, 4959 dma_unmap_addr(tx_buffer, dma), 4960 dma_unmap_len(tx_buffer, len), 4961 DMA_TO_DEVICE); 4962 4963 /* check for eop_desc to determine the end of the packet */ 4964 eop_desc = tx_buffer->next_to_watch; 4965 tx_desc = IGB_TX_DESC(tx_ring, i); 4966 4967 /* unmap remaining buffers */ 4968 while (tx_desc != eop_desc) { 4969 tx_buffer++; 4970 tx_desc++; 4971 i++; 4972 if (unlikely(i == tx_ring->count)) { 4973 i = 0; 4974 tx_buffer = tx_ring->tx_buffer_info; 4975 tx_desc = IGB_TX_DESC(tx_ring, 0); 4976 } 4977 4978 /* unmap any remaining paged data */ 4979 if (dma_unmap_len(tx_buffer, len)) 4980 dma_unmap_page(tx_ring->dev, 4981 dma_unmap_addr(tx_buffer, dma), 4982 dma_unmap_len(tx_buffer, len), 4983 DMA_TO_DEVICE); 4984 } 4985 4986 skip_for_xsk: 4987 tx_buffer->next_to_watch = NULL; 4988 4989 /* move us one more past the eop_desc for start of next pkt */ 4990 tx_buffer++; 4991 i++; 4992 if (unlikely(i == tx_ring->count)) { 4993 i = 0; 4994 tx_buffer = tx_ring->tx_buffer_info; 4995 } 4996 } 4997 4998 /* reset BQL for queue */ 4999 netdev_tx_reset_queue(txring_txq(tx_ring)); 5000 5001 if (tx_ring->xsk_pool && xsk_frames) 5002 xsk_tx_completed(tx_ring->xsk_pool, xsk_frames); 5003 5004 /* reset next_to_use and next_to_clean */ 5005 tx_ring->next_to_use = 0; 5006 tx_ring->next_to_clean = 0; 5007 } 5008 5009 /** 5010 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 5011 * @adapter: board private structure 5012 **/ 5013 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 5014 { 5015 int i; 5016 5017 for (i = 0; i < adapter->num_tx_queues; i++) 5018 if (adapter->tx_ring[i]) 5019 igb_clean_tx_ring(adapter->tx_ring[i]); 5020 } 5021 5022 /** 5023 * igb_free_rx_resources - Free Rx Resources 5024 * @rx_ring: ring to clean the resources from 5025 * 5026 * Free all receive software resources 5027 **/ 5028 void igb_free_rx_resources(struct igb_ring *rx_ring) 5029 { 5030 igb_clean_rx_ring(rx_ring); 5031 5032 rx_ring->xdp_prog = NULL; 5033 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 5034 if (rx_ring->xsk_pool) { 5035 vfree(rx_ring->rx_buffer_info_zc); 5036 rx_ring->rx_buffer_info_zc = NULL; 5037 } else { 5038 vfree(rx_ring->rx_buffer_info); 5039 rx_ring->rx_buffer_info = NULL; 5040 } 5041 5042 /* if not set, then don't free */ 5043 if (!rx_ring->desc) 5044 return; 5045 5046 dma_free_coherent(rx_ring->dev, rx_ring->size, 5047 rx_ring->desc, rx_ring->dma); 5048 5049 rx_ring->desc = NULL; 5050 } 5051 5052 /** 5053 * igb_free_all_rx_resources - Free Rx Resources for All Queues 5054 * @adapter: board private structure 5055 * 5056 * Free all receive software resources 5057 **/ 5058 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 5059 { 5060 int i; 5061 5062 for (i = 0; i < adapter->num_rx_queues; i++) 5063 if (adapter->rx_ring[i]) 5064 igb_free_rx_resources(adapter->rx_ring[i]); 5065 } 5066 5067 /** 5068 * igb_clean_rx_ring - Free Rx Buffers per Queue 5069 * @rx_ring: ring to free buffers from 5070 **/ 5071 void igb_clean_rx_ring(struct igb_ring *rx_ring) 5072 { 5073 u16 i = rx_ring->next_to_clean; 5074 5075 dev_kfree_skb(rx_ring->skb); 5076 rx_ring->skb = NULL; 5077 5078 if (rx_ring->xsk_pool) { 5079 igb_clean_rx_ring_zc(rx_ring); 5080 goto skip_for_xsk; 5081 } 5082 5083 /* Free all the Rx ring sk_buffs */ 5084 while (i != rx_ring->next_to_alloc) { 5085 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 5086 5087 /* Invalidate cache lines that may have been written to by 5088 * device so that we avoid corrupting memory. 5089 */ 5090 dma_sync_single_range_for_cpu(rx_ring->dev, 5091 buffer_info->dma, 5092 buffer_info->page_offset, 5093 igb_rx_bufsz(rx_ring), 5094 DMA_FROM_DEVICE); 5095 5096 /* free resources associated with mapping */ 5097 dma_unmap_page_attrs(rx_ring->dev, 5098 buffer_info->dma, 5099 igb_rx_pg_size(rx_ring), 5100 DMA_FROM_DEVICE, 5101 IGB_RX_DMA_ATTR); 5102 __page_frag_cache_drain(buffer_info->page, 5103 buffer_info->pagecnt_bias); 5104 5105 i++; 5106 if (i == rx_ring->count) 5107 i = 0; 5108 } 5109 5110 skip_for_xsk: 5111 rx_ring->next_to_alloc = 0; 5112 rx_ring->next_to_clean = 0; 5113 rx_ring->next_to_use = 0; 5114 } 5115 5116 /** 5117 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 5118 * @adapter: board private structure 5119 **/ 5120 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 5121 { 5122 int i; 5123 5124 for (i = 0; i < adapter->num_rx_queues; i++) 5125 if (adapter->rx_ring[i]) 5126 igb_clean_rx_ring(adapter->rx_ring[i]); 5127 } 5128 5129 /** 5130 * igb_set_mac - Change the Ethernet Address of the NIC 5131 * @netdev: network interface device structure 5132 * @p: pointer to an address structure 5133 * 5134 * Returns 0 on success, negative on failure 5135 **/ 5136 static int igb_set_mac(struct net_device *netdev, void *p) 5137 { 5138 struct igb_adapter *adapter = netdev_priv(netdev); 5139 struct e1000_hw *hw = &adapter->hw; 5140 struct sockaddr *addr = p; 5141 5142 if (!is_valid_ether_addr(addr->sa_data)) 5143 return -EADDRNOTAVAIL; 5144 5145 eth_hw_addr_set(netdev, addr->sa_data); 5146 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 5147 5148 /* set the correct pool for the new PF MAC address in entry 0 */ 5149 igb_set_default_mac_filter(adapter); 5150 5151 return 0; 5152 } 5153 5154 /** 5155 * igb_write_mc_addr_list - write multicast addresses to MTA 5156 * @netdev: network interface device structure 5157 * 5158 * Writes multicast address list to the MTA hash table. 5159 * Returns: -ENOMEM on failure 5160 * 0 on no addresses written 5161 * X on writing X addresses to MTA 5162 **/ 5163 static int igb_write_mc_addr_list(struct net_device *netdev) 5164 { 5165 struct igb_adapter *adapter = netdev_priv(netdev); 5166 struct e1000_hw *hw = &adapter->hw; 5167 struct netdev_hw_addr *ha; 5168 u8 *mta_list; 5169 int i; 5170 5171 if (netdev_mc_empty(netdev)) { 5172 /* nothing to program, so clear mc list */ 5173 igb_update_mc_addr_list(hw, NULL, 0); 5174 igb_restore_vf_multicasts(adapter); 5175 return 0; 5176 } 5177 5178 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 5179 if (!mta_list) 5180 return -ENOMEM; 5181 5182 /* The shared function expects a packed array of only addresses. */ 5183 i = 0; 5184 netdev_for_each_mc_addr(ha, netdev) 5185 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 5186 5187 igb_update_mc_addr_list(hw, mta_list, i); 5188 kfree(mta_list); 5189 5190 return netdev_mc_count(netdev); 5191 } 5192 5193 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 5194 { 5195 struct e1000_hw *hw = &adapter->hw; 5196 u32 i, pf_id; 5197 5198 switch (hw->mac.type) { 5199 case e1000_i210: 5200 case e1000_i211: 5201 case e1000_i350: 5202 /* VLAN filtering needed for VLAN prio filter */ 5203 if (adapter->netdev->features & NETIF_F_NTUPLE) 5204 break; 5205 fallthrough; 5206 case e1000_82576: 5207 case e1000_82580: 5208 case e1000_i354: 5209 /* VLAN filtering needed for pool filtering */ 5210 if (adapter->vfs_allocated_count) 5211 break; 5212 fallthrough; 5213 default: 5214 return 1; 5215 } 5216 5217 /* We are already in VLAN promisc, nothing to do */ 5218 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 5219 return 0; 5220 5221 if (!adapter->vfs_allocated_count) 5222 goto set_vfta; 5223 5224 /* Add PF to all active pools */ 5225 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5226 5227 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5228 u32 vlvf = rd32(E1000_VLVF(i)); 5229 5230 vlvf |= BIT(pf_id); 5231 wr32(E1000_VLVF(i), vlvf); 5232 } 5233 5234 set_vfta: 5235 /* Set all bits in the VLAN filter table array */ 5236 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 5237 hw->mac.ops.write_vfta(hw, i, ~0U); 5238 5239 /* Set flag so we don't redo unnecessary work */ 5240 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 5241 5242 return 0; 5243 } 5244 5245 #define VFTA_BLOCK_SIZE 8 5246 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 5247 { 5248 struct e1000_hw *hw = &adapter->hw; 5249 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 5250 u32 vid_start = vfta_offset * 32; 5251 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 5252 u32 i, vid, word, bits, pf_id; 5253 5254 /* guarantee that we don't scrub out management VLAN */ 5255 vid = adapter->mng_vlan_id; 5256 if (vid >= vid_start && vid < vid_end) 5257 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5258 5259 if (!adapter->vfs_allocated_count) 5260 goto set_vfta; 5261 5262 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5263 5264 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5265 u32 vlvf = rd32(E1000_VLVF(i)); 5266 5267 /* pull VLAN ID from VLVF */ 5268 vid = vlvf & VLAN_VID_MASK; 5269 5270 /* only concern ourselves with a certain range */ 5271 if (vid < vid_start || vid >= vid_end) 5272 continue; 5273 5274 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 5275 /* record VLAN ID in VFTA */ 5276 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5277 5278 /* if PF is part of this then continue */ 5279 if (test_bit(vid, adapter->active_vlans)) 5280 continue; 5281 } 5282 5283 /* remove PF from the pool */ 5284 bits = ~BIT(pf_id); 5285 bits &= rd32(E1000_VLVF(i)); 5286 wr32(E1000_VLVF(i), bits); 5287 } 5288 5289 set_vfta: 5290 /* extract values from active_vlans and write back to VFTA */ 5291 for (i = VFTA_BLOCK_SIZE; i--;) { 5292 vid = (vfta_offset + i) * 32; 5293 word = vid / BITS_PER_LONG; 5294 bits = vid % BITS_PER_LONG; 5295 5296 vfta[i] |= adapter->active_vlans[word] >> bits; 5297 5298 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 5299 } 5300 } 5301 5302 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 5303 { 5304 u32 i; 5305 5306 /* We are not in VLAN promisc, nothing to do */ 5307 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 5308 return; 5309 5310 /* Set flag so we don't redo unnecessary work */ 5311 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 5312 5313 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 5314 igb_scrub_vfta(adapter, i); 5315 } 5316 5317 /** 5318 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 5319 * @netdev: network interface device structure 5320 * 5321 * The set_rx_mode entry point is called whenever the unicast or multicast 5322 * address lists or the network interface flags are updated. This routine is 5323 * responsible for configuring the hardware for proper unicast, multicast, 5324 * promiscuous mode, and all-multi behavior. 5325 **/ 5326 static void igb_set_rx_mode(struct net_device *netdev) 5327 { 5328 struct igb_adapter *adapter = netdev_priv(netdev); 5329 struct e1000_hw *hw = &adapter->hw; 5330 unsigned int vfn = adapter->vfs_allocated_count; 5331 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 5332 int count; 5333 5334 /* Check for Promiscuous and All Multicast modes */ 5335 if (netdev->flags & IFF_PROMISC) { 5336 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5337 vmolr |= E1000_VMOLR_MPME; 5338 5339 /* enable use of UTA filter to force packets to default pool */ 5340 if (hw->mac.type == e1000_82576) 5341 vmolr |= E1000_VMOLR_ROPE; 5342 } else { 5343 if (netdev->flags & IFF_ALLMULTI) { 5344 rctl |= E1000_RCTL_MPE; 5345 vmolr |= E1000_VMOLR_MPME; 5346 } else { 5347 /* Write addresses to the MTA, if the attempt fails 5348 * then we should just turn on promiscuous mode so 5349 * that we can at least receive multicast traffic 5350 */ 5351 count = igb_write_mc_addr_list(netdev); 5352 if (count < 0) { 5353 rctl |= E1000_RCTL_MPE; 5354 vmolr |= E1000_VMOLR_MPME; 5355 } else if (count) { 5356 vmolr |= E1000_VMOLR_ROMPE; 5357 } 5358 } 5359 } 5360 5361 /* Write addresses to available RAR registers, if there is not 5362 * sufficient space to store all the addresses then enable 5363 * unicast promiscuous mode 5364 */ 5365 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5366 rctl |= E1000_RCTL_UPE; 5367 vmolr |= E1000_VMOLR_ROPE; 5368 } 5369 5370 /* enable VLAN filtering by default */ 5371 rctl |= E1000_RCTL_VFE; 5372 5373 /* disable VLAN filtering for modes that require it */ 5374 if ((netdev->flags & IFF_PROMISC) || 5375 (netdev->features & NETIF_F_RXALL)) { 5376 /* if we fail to set all rules then just clear VFE */ 5377 if (igb_vlan_promisc_enable(adapter)) 5378 rctl &= ~E1000_RCTL_VFE; 5379 } else { 5380 igb_vlan_promisc_disable(adapter); 5381 } 5382 5383 /* update state of unicast, multicast, and VLAN filtering modes */ 5384 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5385 E1000_RCTL_VFE); 5386 wr32(E1000_RCTL, rctl); 5387 5388 #if (PAGE_SIZE < 8192) 5389 if (!adapter->vfs_allocated_count) { 5390 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5391 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5392 } 5393 #endif 5394 wr32(E1000_RLPML, rlpml); 5395 5396 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5397 * the VMOLR to enable the appropriate modes. Without this workaround 5398 * we will have issues with VLAN tag stripping not being done for frames 5399 * that are only arriving because we are the default pool 5400 */ 5401 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5402 return; 5403 5404 /* set UTA to appropriate mode */ 5405 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5406 5407 vmolr |= rd32(E1000_VMOLR(vfn)) & 5408 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5409 5410 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5411 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5412 #if (PAGE_SIZE < 8192) 5413 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5414 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5415 else 5416 #endif 5417 vmolr |= MAX_JUMBO_FRAME_SIZE; 5418 vmolr |= E1000_VMOLR_LPE; 5419 5420 wr32(E1000_VMOLR(vfn), vmolr); 5421 5422 igb_restore_vf_multicasts(adapter); 5423 } 5424 5425 static void igb_check_wvbr(struct igb_adapter *adapter) 5426 { 5427 struct e1000_hw *hw = &adapter->hw; 5428 u32 wvbr = 0; 5429 5430 switch (hw->mac.type) { 5431 case e1000_82576: 5432 case e1000_i350: 5433 wvbr = rd32(E1000_WVBR); 5434 if (!wvbr) 5435 return; 5436 break; 5437 default: 5438 break; 5439 } 5440 5441 adapter->wvbr |= wvbr; 5442 } 5443 5444 #define IGB_STAGGERED_QUEUE_OFFSET 8 5445 5446 static void igb_spoof_check(struct igb_adapter *adapter) 5447 { 5448 int j; 5449 5450 if (!adapter->wvbr) 5451 return; 5452 5453 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5454 if (adapter->wvbr & BIT(j) || 5455 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5456 dev_warn(&adapter->pdev->dev, 5457 "Spoof event(s) detected on VF %d\n", j); 5458 adapter->wvbr &= 5459 ~(BIT(j) | 5460 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5461 } 5462 } 5463 } 5464 5465 /* Need to wait a few seconds after link up to get diagnostic information from 5466 * the phy 5467 */ 5468 static void igb_update_phy_info(struct timer_list *t) 5469 { 5470 struct igb_adapter *adapter = timer_container_of(adapter, t, 5471 phy_info_timer); 5472 igb_get_phy_info(&adapter->hw); 5473 } 5474 5475 /** 5476 * igb_has_link - check shared code for link and determine up/down 5477 * @adapter: pointer to driver private info 5478 **/ 5479 bool igb_has_link(struct igb_adapter *adapter) 5480 { 5481 struct e1000_hw *hw = &adapter->hw; 5482 bool link_active = false; 5483 5484 /* get_link_status is set on LSC (link status) interrupt or 5485 * rx sequence error interrupt. get_link_status will stay 5486 * false until the e1000_check_for_link establishes link 5487 * for copper adapters ONLY 5488 */ 5489 switch (hw->phy.media_type) { 5490 case e1000_media_type_copper: 5491 if (!hw->mac.get_link_status) 5492 return true; 5493 fallthrough; 5494 case e1000_media_type_internal_serdes: 5495 hw->mac.ops.check_for_link(hw); 5496 link_active = !hw->mac.get_link_status; 5497 break; 5498 default: 5499 case e1000_media_type_unknown: 5500 break; 5501 } 5502 5503 if (((hw->mac.type == e1000_i210) || 5504 (hw->mac.type == e1000_i211)) && 5505 (hw->phy.id == I210_I_PHY_ID)) { 5506 if (!netif_carrier_ok(adapter->netdev)) { 5507 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5508 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5509 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5510 adapter->link_check_timeout = jiffies; 5511 } 5512 } 5513 5514 return link_active; 5515 } 5516 5517 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5518 { 5519 bool ret = false; 5520 u32 ctrl_ext, thstat; 5521 5522 /* check for thermal sensor event on i350 copper only */ 5523 if (hw->mac.type == e1000_i350) { 5524 thstat = rd32(E1000_THSTAT); 5525 ctrl_ext = rd32(E1000_CTRL_EXT); 5526 5527 if ((hw->phy.media_type == e1000_media_type_copper) && 5528 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5529 ret = !!(thstat & event); 5530 } 5531 5532 return ret; 5533 } 5534 5535 /** 5536 * igb_check_lvmmc - check for malformed packets received 5537 * and indicated in LVMMC register 5538 * @adapter: pointer to adapter 5539 **/ 5540 static void igb_check_lvmmc(struct igb_adapter *adapter) 5541 { 5542 struct e1000_hw *hw = &adapter->hw; 5543 u32 lvmmc; 5544 5545 lvmmc = rd32(E1000_LVMMC); 5546 if (lvmmc) { 5547 if (unlikely(net_ratelimit())) { 5548 netdev_warn(adapter->netdev, 5549 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5550 lvmmc); 5551 } 5552 } 5553 } 5554 5555 /** 5556 * igb_watchdog - Timer Call-back 5557 * @t: pointer to timer_list containing our private info pointer 5558 **/ 5559 static void igb_watchdog(struct timer_list *t) 5560 { 5561 struct igb_adapter *adapter = timer_container_of(adapter, t, 5562 watchdog_timer); 5563 /* Do the rest outside of interrupt context */ 5564 schedule_work(&adapter->watchdog_task); 5565 } 5566 5567 static void igb_watchdog_task(struct work_struct *work) 5568 { 5569 struct igb_adapter *adapter = container_of(work, 5570 struct igb_adapter, 5571 watchdog_task); 5572 struct e1000_hw *hw = &adapter->hw; 5573 struct e1000_phy_info *phy = &hw->phy; 5574 struct net_device *netdev = adapter->netdev; 5575 u32 link; 5576 int i; 5577 u32 connsw; 5578 u16 phy_data, retry_count = 20; 5579 5580 link = igb_has_link(adapter); 5581 5582 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5583 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5584 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5585 else 5586 link = false; 5587 } 5588 5589 /* Force link down if we have fiber to swap to */ 5590 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5591 if (hw->phy.media_type == e1000_media_type_copper) { 5592 connsw = rd32(E1000_CONNSW); 5593 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5594 link = 0; 5595 } 5596 } 5597 if (link) { 5598 /* Perform a reset if the media type changed. */ 5599 if (hw->dev_spec._82575.media_changed) { 5600 hw->dev_spec._82575.media_changed = false; 5601 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5602 igb_reset(adapter); 5603 } 5604 /* Cancel scheduled suspend requests. */ 5605 pm_runtime_resume(netdev->dev.parent); 5606 5607 if (!netif_carrier_ok(netdev)) { 5608 u32 ctrl; 5609 5610 hw->mac.ops.get_speed_and_duplex(hw, 5611 &adapter->link_speed, 5612 &adapter->link_duplex); 5613 5614 ctrl = rd32(E1000_CTRL); 5615 /* Links status message must follow this format */ 5616 netdev_info(netdev, 5617 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5618 netdev->name, 5619 adapter->link_speed, 5620 adapter->link_duplex == FULL_DUPLEX ? 5621 "Full" : "Half", 5622 (ctrl & E1000_CTRL_TFCE) && 5623 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5624 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5625 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5626 5627 /* disable EEE if enabled */ 5628 if ((adapter->flags & IGB_FLAG_EEE) && 5629 (adapter->link_duplex == HALF_DUPLEX)) { 5630 dev_info(&adapter->pdev->dev, 5631 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5632 adapter->hw.dev_spec._82575.eee_disable = true; 5633 adapter->flags &= ~IGB_FLAG_EEE; 5634 } 5635 5636 /* check if SmartSpeed worked */ 5637 igb_check_downshift(hw); 5638 if (phy->speed_downgraded) 5639 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5640 5641 /* check for thermal sensor event */ 5642 if (igb_thermal_sensor_event(hw, 5643 E1000_THSTAT_LINK_THROTTLE)) 5644 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5645 5646 /* adjust timeout factor according to speed/duplex */ 5647 adapter->tx_timeout_factor = 1; 5648 switch (adapter->link_speed) { 5649 case SPEED_10: 5650 adapter->tx_timeout_factor = 14; 5651 break; 5652 case SPEED_100: 5653 /* maybe add some timeout factor ? */ 5654 break; 5655 } 5656 5657 if (adapter->link_speed != SPEED_1000 || 5658 !hw->phy.ops.read_reg) 5659 goto no_wait; 5660 5661 /* wait for Remote receiver status OK */ 5662 retry_read_status: 5663 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5664 &phy_data)) { 5665 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5666 retry_count) { 5667 msleep(100); 5668 retry_count--; 5669 goto retry_read_status; 5670 } else if (!retry_count) { 5671 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5672 } 5673 } else { 5674 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5675 } 5676 no_wait: 5677 netif_carrier_on(netdev); 5678 5679 igb_ping_all_vfs(adapter); 5680 igb_check_vf_rate_limit(adapter); 5681 5682 /* link state has changed, schedule phy info update */ 5683 if (!test_bit(__IGB_DOWN, &adapter->state)) 5684 mod_timer(&adapter->phy_info_timer, 5685 round_jiffies(jiffies + 2 * HZ)); 5686 } 5687 } else { 5688 if (netif_carrier_ok(netdev)) { 5689 adapter->link_speed = 0; 5690 adapter->link_duplex = 0; 5691 5692 /* check for thermal sensor event */ 5693 if (igb_thermal_sensor_event(hw, 5694 E1000_THSTAT_PWR_DOWN)) { 5695 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5696 } 5697 5698 /* Links status message must follow this format */ 5699 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5700 netdev->name); 5701 netif_carrier_off(netdev); 5702 5703 igb_ping_all_vfs(adapter); 5704 5705 /* link state has changed, schedule phy info update */ 5706 if (!test_bit(__IGB_DOWN, &adapter->state)) 5707 mod_timer(&adapter->phy_info_timer, 5708 round_jiffies(jiffies + 2 * HZ)); 5709 5710 /* link is down, time to check for alternate media */ 5711 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5712 igb_check_swap_media(adapter); 5713 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5714 schedule_work(&adapter->reset_task); 5715 /* return immediately */ 5716 return; 5717 } 5718 } 5719 pm_schedule_suspend(netdev->dev.parent, 5720 MSEC_PER_SEC * 5); 5721 5722 /* also check for alternate media here */ 5723 } else if (!netif_carrier_ok(netdev) && 5724 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5725 igb_check_swap_media(adapter); 5726 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5727 schedule_work(&adapter->reset_task); 5728 /* return immediately */ 5729 return; 5730 } 5731 } 5732 } 5733 5734 spin_lock(&adapter->stats64_lock); 5735 igb_update_stats(adapter); 5736 spin_unlock(&adapter->stats64_lock); 5737 5738 for (i = 0; i < adapter->num_tx_queues; i++) { 5739 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5740 if (!netif_carrier_ok(netdev)) { 5741 /* We've lost link, so the controller stops DMA, 5742 * but we've got queued Tx work that's never going 5743 * to get done, so reset controller to flush Tx. 5744 * (Do the reset outside of interrupt context). 5745 */ 5746 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5747 adapter->tx_timeout_count++; 5748 schedule_work(&adapter->reset_task); 5749 /* return immediately since reset is imminent */ 5750 return; 5751 } 5752 } 5753 5754 /* Force detection of hung controller every watchdog period */ 5755 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5756 } 5757 5758 /* Cause software interrupt to ensure Rx ring is cleaned */ 5759 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5760 u32 eics = 0; 5761 5762 for (i = 0; i < adapter->num_q_vectors; i++) { 5763 struct igb_q_vector *q_vector = adapter->q_vector[i]; 5764 struct igb_ring *rx_ring; 5765 5766 if (!q_vector->rx.ring) 5767 continue; 5768 5769 rx_ring = adapter->rx_ring[q_vector->rx.ring->queue_index]; 5770 5771 if (test_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags)) { 5772 eics |= q_vector->eims_value; 5773 clear_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 5774 } 5775 } 5776 if (eics) 5777 wr32(E1000_EICS, eics); 5778 } else { 5779 struct igb_ring *rx_ring = adapter->rx_ring[0]; 5780 5781 if (test_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags)) { 5782 clear_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 5783 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5784 } 5785 } 5786 5787 igb_spoof_check(adapter); 5788 igb_ptp_rx_hang(adapter); 5789 igb_ptp_tx_hang(adapter); 5790 5791 /* Check LVMMC register on i350/i354 only */ 5792 if ((adapter->hw.mac.type == e1000_i350) || 5793 (adapter->hw.mac.type == e1000_i354)) 5794 igb_check_lvmmc(adapter); 5795 5796 /* Reset the timer */ 5797 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5798 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5799 mod_timer(&adapter->watchdog_timer, 5800 round_jiffies(jiffies + HZ)); 5801 else 5802 mod_timer(&adapter->watchdog_timer, 5803 round_jiffies(jiffies + 2 * HZ)); 5804 } 5805 } 5806 5807 enum latency_range { 5808 lowest_latency = 0, 5809 low_latency = 1, 5810 bulk_latency = 2, 5811 latency_invalid = 255 5812 }; 5813 5814 /** 5815 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5816 * @q_vector: pointer to q_vector 5817 * 5818 * Stores a new ITR value based on strictly on packet size. This 5819 * algorithm is less sophisticated than that used in igb_update_itr, 5820 * due to the difficulty of synchronizing statistics across multiple 5821 * receive rings. The divisors and thresholds used by this function 5822 * were determined based on theoretical maximum wire speed and testing 5823 * data, in order to minimize response time while increasing bulk 5824 * throughput. 5825 * This functionality is controlled by ethtool's coalescing settings. 5826 * NOTE: This function is called only when operating in a multiqueue 5827 * receive environment. 5828 **/ 5829 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5830 { 5831 int new_val = q_vector->itr_val; 5832 int avg_wire_size = 0; 5833 struct igb_adapter *adapter = q_vector->adapter; 5834 unsigned int packets; 5835 5836 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5837 * ints/sec - ITR timer value of 120 ticks. 5838 */ 5839 if (adapter->link_speed != SPEED_1000) { 5840 new_val = IGB_4K_ITR; 5841 goto set_itr_val; 5842 } 5843 5844 packets = q_vector->rx.total_packets; 5845 if (packets) 5846 avg_wire_size = q_vector->rx.total_bytes / packets; 5847 5848 packets = q_vector->tx.total_packets; 5849 if (packets) 5850 avg_wire_size = max_t(u32, avg_wire_size, 5851 q_vector->tx.total_bytes / packets); 5852 5853 /* if avg_wire_size isn't set no work was done */ 5854 if (!avg_wire_size) 5855 goto clear_counts; 5856 5857 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5858 avg_wire_size += 24; 5859 5860 /* Don't starve jumbo frames */ 5861 avg_wire_size = min(avg_wire_size, 3000); 5862 5863 /* Give a little boost to mid-size frames */ 5864 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5865 new_val = avg_wire_size / 3; 5866 else 5867 new_val = avg_wire_size / 2; 5868 5869 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5870 if (new_val < IGB_20K_ITR && 5871 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5872 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5873 new_val = IGB_20K_ITR; 5874 5875 set_itr_val: 5876 if (new_val != q_vector->itr_val) { 5877 q_vector->itr_val = new_val; 5878 q_vector->set_itr = 1; 5879 } 5880 clear_counts: 5881 q_vector->rx.total_bytes = 0; 5882 q_vector->rx.total_packets = 0; 5883 q_vector->tx.total_bytes = 0; 5884 q_vector->tx.total_packets = 0; 5885 } 5886 5887 /** 5888 * igb_update_itr - update the dynamic ITR value based on statistics 5889 * @q_vector: pointer to q_vector 5890 * @ring_container: ring info to update the itr for 5891 * 5892 * Stores a new ITR value based on packets and byte 5893 * counts during the last interrupt. The advantage of per interrupt 5894 * computation is faster updates and more accurate ITR for the current 5895 * traffic pattern. Constants in this function were computed 5896 * based on theoretical maximum wire speed and thresholds were set based 5897 * on testing data as well as attempting to minimize response time 5898 * while increasing bulk throughput. 5899 * This functionality is controlled by ethtool's coalescing settings. 5900 * NOTE: These calculations are only valid when operating in a single- 5901 * queue environment. 5902 **/ 5903 static void igb_update_itr(struct igb_q_vector *q_vector, 5904 struct igb_ring_container *ring_container) 5905 { 5906 unsigned int packets = ring_container->total_packets; 5907 unsigned int bytes = ring_container->total_bytes; 5908 u8 itrval = ring_container->itr; 5909 5910 /* no packets, exit with status unchanged */ 5911 if (packets == 0) 5912 return; 5913 5914 switch (itrval) { 5915 case lowest_latency: 5916 /* handle TSO and jumbo frames */ 5917 if (bytes/packets > 8000) 5918 itrval = bulk_latency; 5919 else if ((packets < 5) && (bytes > 512)) 5920 itrval = low_latency; 5921 break; 5922 case low_latency: /* 50 usec aka 20000 ints/s */ 5923 if (bytes > 10000) { 5924 /* this if handles the TSO accounting */ 5925 if (bytes/packets > 8000) 5926 itrval = bulk_latency; 5927 else if ((packets < 10) || ((bytes/packets) > 1200)) 5928 itrval = bulk_latency; 5929 else if ((packets > 35)) 5930 itrval = lowest_latency; 5931 } else if (bytes/packets > 2000) { 5932 itrval = bulk_latency; 5933 } else if (packets <= 2 && bytes < 512) { 5934 itrval = lowest_latency; 5935 } 5936 break; 5937 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5938 if (bytes > 25000) { 5939 if (packets > 35) 5940 itrval = low_latency; 5941 } else if (bytes < 1500) { 5942 itrval = low_latency; 5943 } 5944 break; 5945 } 5946 5947 /* clear work counters since we have the values we need */ 5948 ring_container->total_bytes = 0; 5949 ring_container->total_packets = 0; 5950 5951 /* write updated itr to ring container */ 5952 ring_container->itr = itrval; 5953 } 5954 5955 static void igb_set_itr(struct igb_q_vector *q_vector) 5956 { 5957 struct igb_adapter *adapter = q_vector->adapter; 5958 u32 new_itr = q_vector->itr_val; 5959 u8 current_itr = 0; 5960 5961 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5962 if (adapter->link_speed != SPEED_1000) { 5963 current_itr = 0; 5964 new_itr = IGB_4K_ITR; 5965 goto set_itr_now; 5966 } 5967 5968 igb_update_itr(q_vector, &q_vector->tx); 5969 igb_update_itr(q_vector, &q_vector->rx); 5970 5971 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5972 5973 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5974 if (current_itr == lowest_latency && 5975 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5976 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5977 current_itr = low_latency; 5978 5979 switch (current_itr) { 5980 /* counts and packets in update_itr are dependent on these numbers */ 5981 case lowest_latency: 5982 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5983 break; 5984 case low_latency: 5985 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5986 break; 5987 case bulk_latency: 5988 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5989 break; 5990 default: 5991 break; 5992 } 5993 5994 set_itr_now: 5995 if (new_itr != q_vector->itr_val) { 5996 /* this attempts to bias the interrupt rate towards Bulk 5997 * by adding intermediate steps when interrupt rate is 5998 * increasing 5999 */ 6000 new_itr = new_itr > q_vector->itr_val ? 6001 max((new_itr * q_vector->itr_val) / 6002 (new_itr + (q_vector->itr_val >> 2)), 6003 new_itr) : new_itr; 6004 /* Don't write the value here; it resets the adapter's 6005 * internal timer, and causes us to delay far longer than 6006 * we should between interrupts. Instead, we write the ITR 6007 * value at the beginning of the next interrupt so the timing 6008 * ends up being correct. 6009 */ 6010 q_vector->itr_val = new_itr; 6011 q_vector->set_itr = 1; 6012 } 6013 } 6014 6015 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 6016 struct igb_tx_buffer *first, 6017 u32 vlan_macip_lens, u32 type_tucmd, 6018 u32 mss_l4len_idx) 6019 { 6020 struct e1000_adv_tx_context_desc *context_desc; 6021 u16 i = tx_ring->next_to_use; 6022 struct timespec64 ts; 6023 6024 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 6025 6026 i++; 6027 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 6028 6029 /* set bits to identify this as an advanced context descriptor */ 6030 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 6031 6032 /* For 82575, context index must be unique per ring. */ 6033 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6034 mss_l4len_idx |= tx_ring->reg_idx << 4; 6035 6036 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 6037 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 6038 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 6039 6040 /* We assume there is always a valid tx time available. Invalid times 6041 * should have been handled by the upper layers. 6042 */ 6043 if (tx_ring->launchtime_enable) { 6044 ts = ktime_to_timespec64(first->skb->tstamp); 6045 skb_txtime_consumed(first->skb); 6046 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 6047 } else { 6048 context_desc->seqnum_seed = 0; 6049 } 6050 } 6051 6052 static int igb_tso(struct igb_ring *tx_ring, 6053 struct igb_tx_buffer *first, 6054 u8 *hdr_len) 6055 { 6056 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 6057 struct sk_buff *skb = first->skb; 6058 union { 6059 struct iphdr *v4; 6060 struct ipv6hdr *v6; 6061 unsigned char *hdr; 6062 } ip; 6063 union { 6064 struct tcphdr *tcp; 6065 struct udphdr *udp; 6066 unsigned char *hdr; 6067 } l4; 6068 u32 paylen, l4_offset; 6069 int err; 6070 6071 if (skb->ip_summed != CHECKSUM_PARTIAL) 6072 return 0; 6073 6074 if (!skb_is_gso(skb)) 6075 return 0; 6076 6077 err = skb_cow_head(skb, 0); 6078 if (err < 0) 6079 return err; 6080 6081 ip.hdr = skb_network_header(skb); 6082 l4.hdr = skb_checksum_start(skb); 6083 6084 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 6085 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 6086 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP; 6087 6088 /* initialize outer IP header fields */ 6089 if (ip.v4->version == 4) { 6090 unsigned char *csum_start = skb_checksum_start(skb); 6091 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 6092 6093 /* IP header will have to cancel out any data that 6094 * is not a part of the outer IP header 6095 */ 6096 ip.v4->check = csum_fold(csum_partial(trans_start, 6097 csum_start - trans_start, 6098 0)); 6099 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 6100 6101 ip.v4->tot_len = 0; 6102 first->tx_flags |= IGB_TX_FLAGS_TSO | 6103 IGB_TX_FLAGS_CSUM | 6104 IGB_TX_FLAGS_IPV4; 6105 } else { 6106 ip.v6->payload_len = 0; 6107 first->tx_flags |= IGB_TX_FLAGS_TSO | 6108 IGB_TX_FLAGS_CSUM; 6109 } 6110 6111 /* determine offset of inner transport header */ 6112 l4_offset = l4.hdr - skb->data; 6113 6114 /* remove payload length from inner checksum */ 6115 paylen = skb->len - l4_offset; 6116 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) { 6117 /* compute length of segmentation header */ 6118 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 6119 csum_replace_by_diff(&l4.tcp->check, 6120 (__force __wsum)htonl(paylen)); 6121 } else { 6122 /* compute length of segmentation header */ 6123 *hdr_len = sizeof(*l4.udp) + l4_offset; 6124 csum_replace_by_diff(&l4.udp->check, 6125 (__force __wsum)htonl(paylen)); 6126 } 6127 6128 /* update gso size and bytecount with header size */ 6129 first->gso_segs = skb_shinfo(skb)->gso_segs; 6130 first->bytecount += (first->gso_segs - 1) * *hdr_len; 6131 6132 /* MSS L4LEN IDX */ 6133 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 6134 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 6135 6136 /* VLAN MACLEN IPLEN */ 6137 vlan_macip_lens = l4.hdr - ip.hdr; 6138 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 6139 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6140 6141 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 6142 type_tucmd, mss_l4len_idx); 6143 6144 return 1; 6145 } 6146 6147 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 6148 { 6149 struct sk_buff *skb = first->skb; 6150 u32 vlan_macip_lens = 0; 6151 u32 type_tucmd = 0; 6152 6153 if (skb->ip_summed != CHECKSUM_PARTIAL) { 6154 csum_failed: 6155 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 6156 !tx_ring->launchtime_enable) 6157 return; 6158 goto no_csum; 6159 } 6160 6161 switch (skb->csum_offset) { 6162 case offsetof(struct tcphdr, check): 6163 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 6164 fallthrough; 6165 case offsetof(struct udphdr, check): 6166 break; 6167 case offsetof(struct sctphdr, checksum): 6168 /* validate that this is actually an SCTP request */ 6169 if (skb_csum_is_sctp(skb)) { 6170 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 6171 break; 6172 } 6173 fallthrough; 6174 default: 6175 skb_checksum_help(skb); 6176 goto csum_failed; 6177 } 6178 6179 /* update TX checksum flag */ 6180 first->tx_flags |= IGB_TX_FLAGS_CSUM; 6181 vlan_macip_lens = skb_checksum_start_offset(skb) - 6182 skb_network_offset(skb); 6183 no_csum: 6184 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 6185 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6186 6187 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 6188 } 6189 6190 #define IGB_SET_FLAG(_input, _flag, _result) \ 6191 ((_flag <= _result) ? \ 6192 ((u32)(_input & _flag) * (_result / _flag)) : \ 6193 ((u32)(_input & _flag) / (_flag / _result))) 6194 6195 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6196 { 6197 /* set type for advanced descriptor with frame checksum insertion */ 6198 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 6199 E1000_ADVTXD_DCMD_DEXT | 6200 E1000_ADVTXD_DCMD_IFCS; 6201 6202 /* set HW vlan bit if vlan is present */ 6203 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 6204 (E1000_ADVTXD_DCMD_VLE)); 6205 6206 /* set segmentation bits for TSO */ 6207 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 6208 (E1000_ADVTXD_DCMD_TSE)); 6209 6210 /* set timestamp bit if present */ 6211 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 6212 (E1000_ADVTXD_MAC_TSTAMP)); 6213 6214 /* insert frame checksum */ 6215 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 6216 6217 return cmd_type; 6218 } 6219 6220 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 6221 union e1000_adv_tx_desc *tx_desc, 6222 u32 tx_flags, unsigned int paylen) 6223 { 6224 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 6225 6226 /* 82575 requires a unique index per ring */ 6227 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6228 olinfo_status |= tx_ring->reg_idx << 4; 6229 6230 /* insert L4 checksum */ 6231 olinfo_status |= IGB_SET_FLAG(tx_flags, 6232 IGB_TX_FLAGS_CSUM, 6233 (E1000_TXD_POPTS_TXSM << 8)); 6234 6235 /* insert IPv4 checksum */ 6236 olinfo_status |= IGB_SET_FLAG(tx_flags, 6237 IGB_TX_FLAGS_IPV4, 6238 (E1000_TXD_POPTS_IXSM << 8)); 6239 6240 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6241 } 6242 6243 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6244 { 6245 struct net_device *netdev = tx_ring->netdev; 6246 6247 netif_stop_subqueue(netdev, tx_ring->queue_index); 6248 6249 /* Herbert's original patch had: 6250 * smp_mb__after_netif_stop_queue(); 6251 * but since that doesn't exist yet, just open code it. 6252 */ 6253 smp_mb(); 6254 6255 /* We need to check again in a case another CPU has just 6256 * made room available. 6257 */ 6258 if (igb_desc_unused(tx_ring) < size) 6259 return -EBUSY; 6260 6261 /* A reprieve! */ 6262 netif_wake_subqueue(netdev, tx_ring->queue_index); 6263 6264 u64_stats_update_begin(&tx_ring->tx_syncp2); 6265 tx_ring->tx_stats.restart_queue2++; 6266 u64_stats_update_end(&tx_ring->tx_syncp2); 6267 6268 return 0; 6269 } 6270 6271 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6272 { 6273 if (igb_desc_unused(tx_ring) >= size) 6274 return 0; 6275 return __igb_maybe_stop_tx(tx_ring, size); 6276 } 6277 6278 static int igb_tx_map(struct igb_ring *tx_ring, 6279 struct igb_tx_buffer *first, 6280 const u8 hdr_len) 6281 { 6282 struct sk_buff *skb = first->skb; 6283 struct igb_tx_buffer *tx_buffer; 6284 union e1000_adv_tx_desc *tx_desc; 6285 skb_frag_t *frag; 6286 dma_addr_t dma; 6287 unsigned int data_len, size; 6288 u32 tx_flags = first->tx_flags; 6289 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 6290 u16 i = tx_ring->next_to_use; 6291 6292 tx_desc = IGB_TX_DESC(tx_ring, i); 6293 6294 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 6295 6296 size = skb_headlen(skb); 6297 data_len = skb->data_len; 6298 6299 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6300 6301 tx_buffer = first; 6302 6303 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6304 if (dma_mapping_error(tx_ring->dev, dma)) 6305 goto dma_error; 6306 6307 /* record length, and DMA address */ 6308 dma_unmap_len_set(tx_buffer, len, size); 6309 dma_unmap_addr_set(tx_buffer, dma, dma); 6310 6311 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6312 6313 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 6314 tx_desc->read.cmd_type_len = 6315 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 6316 6317 i++; 6318 tx_desc++; 6319 if (i == tx_ring->count) { 6320 tx_desc = IGB_TX_DESC(tx_ring, 0); 6321 i = 0; 6322 } 6323 tx_desc->read.olinfo_status = 0; 6324 6325 dma += IGB_MAX_DATA_PER_TXD; 6326 size -= IGB_MAX_DATA_PER_TXD; 6327 6328 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6329 } 6330 6331 if (likely(!data_len)) 6332 break; 6333 6334 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6335 6336 i++; 6337 tx_desc++; 6338 if (i == tx_ring->count) { 6339 tx_desc = IGB_TX_DESC(tx_ring, 0); 6340 i = 0; 6341 } 6342 tx_desc->read.olinfo_status = 0; 6343 6344 size = skb_frag_size(frag); 6345 data_len -= size; 6346 6347 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6348 size, DMA_TO_DEVICE); 6349 6350 tx_buffer = &tx_ring->tx_buffer_info[i]; 6351 } 6352 6353 /* write last descriptor with RS and EOP bits */ 6354 cmd_type |= size | IGB_TXD_DCMD; 6355 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6356 6357 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6358 6359 /* set the timestamp */ 6360 first->time_stamp = jiffies; 6361 6362 skb_tx_timestamp(skb); 6363 6364 /* Force memory writes to complete before letting h/w know there 6365 * are new descriptors to fetch. (Only applicable for weak-ordered 6366 * memory model archs, such as IA-64). 6367 * 6368 * We also need this memory barrier to make certain all of the 6369 * status bits have been updated before next_to_watch is written. 6370 */ 6371 dma_wmb(); 6372 6373 /* set next_to_watch value indicating a packet is present */ 6374 first->next_to_watch = tx_desc; 6375 6376 i++; 6377 if (i == tx_ring->count) 6378 i = 0; 6379 6380 tx_ring->next_to_use = i; 6381 6382 /* Make sure there is space in the ring for the next send. */ 6383 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6384 6385 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6386 writel(i, tx_ring->tail); 6387 } 6388 return 0; 6389 6390 dma_error: 6391 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6392 tx_buffer = &tx_ring->tx_buffer_info[i]; 6393 6394 /* clear dma mappings for failed tx_buffer_info map */ 6395 while (tx_buffer != first) { 6396 if (dma_unmap_len(tx_buffer, len)) 6397 dma_unmap_page(tx_ring->dev, 6398 dma_unmap_addr(tx_buffer, dma), 6399 dma_unmap_len(tx_buffer, len), 6400 DMA_TO_DEVICE); 6401 dma_unmap_len_set(tx_buffer, len, 0); 6402 6403 if (i-- == 0) 6404 i += tx_ring->count; 6405 tx_buffer = &tx_ring->tx_buffer_info[i]; 6406 } 6407 6408 if (dma_unmap_len(tx_buffer, len)) 6409 dma_unmap_single(tx_ring->dev, 6410 dma_unmap_addr(tx_buffer, dma), 6411 dma_unmap_len(tx_buffer, len), 6412 DMA_TO_DEVICE); 6413 dma_unmap_len_set(tx_buffer, len, 0); 6414 6415 dev_kfree_skb_any(tx_buffer->skb); 6416 tx_buffer->skb = NULL; 6417 6418 tx_ring->next_to_use = i; 6419 6420 return -1; 6421 } 6422 6423 int igb_xmit_xdp_ring(struct igb_adapter *adapter, 6424 struct igb_ring *tx_ring, 6425 struct xdp_frame *xdpf) 6426 { 6427 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 6428 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 6429 u16 count, i, index = tx_ring->next_to_use; 6430 struct igb_tx_buffer *tx_head = &tx_ring->tx_buffer_info[index]; 6431 struct igb_tx_buffer *tx_buffer = tx_head; 6432 union e1000_adv_tx_desc *tx_desc = IGB_TX_DESC(tx_ring, index); 6433 u32 len = xdpf->len, cmd_type, olinfo_status; 6434 void *data = xdpf->data; 6435 6436 count = TXD_USE_COUNT(len); 6437 for (i = 0; i < nr_frags; i++) 6438 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i])); 6439 6440 if (igb_maybe_stop_tx(tx_ring, count + 3)) 6441 return IGB_XDP_CONSUMED; 6442 6443 i = 0; 6444 /* record the location of the first descriptor for this packet */ 6445 tx_head->bytecount = xdp_get_frame_len(xdpf); 6446 tx_head->type = IGB_TYPE_XDP; 6447 tx_head->gso_segs = 1; 6448 tx_head->xdpf = xdpf; 6449 6450 olinfo_status = tx_head->bytecount << E1000_ADVTXD_PAYLEN_SHIFT; 6451 /* 82575 requires a unique index per ring */ 6452 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6453 olinfo_status |= tx_ring->reg_idx << 4; 6454 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6455 6456 for (;;) { 6457 dma_addr_t dma; 6458 6459 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE); 6460 if (dma_mapping_error(tx_ring->dev, dma)) 6461 goto unmap; 6462 6463 /* record length, and DMA address */ 6464 dma_unmap_len_set(tx_buffer, len, len); 6465 dma_unmap_addr_set(tx_buffer, dma, dma); 6466 6467 /* put descriptor type bits */ 6468 cmd_type = E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_DEXT | 6469 E1000_ADVTXD_DCMD_IFCS | len; 6470 6471 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6472 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6473 6474 tx_buffer->protocol = 0; 6475 6476 if (++index == tx_ring->count) 6477 index = 0; 6478 6479 if (i == nr_frags) 6480 break; 6481 6482 tx_buffer = &tx_ring->tx_buffer_info[index]; 6483 tx_desc = IGB_TX_DESC(tx_ring, index); 6484 tx_desc->read.olinfo_status = 0; 6485 6486 data = skb_frag_address(&sinfo->frags[i]); 6487 len = skb_frag_size(&sinfo->frags[i]); 6488 i++; 6489 } 6490 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_TXD_DCMD); 6491 6492 netdev_tx_sent_queue(txring_txq(tx_ring), tx_head->bytecount); 6493 /* set the timestamp */ 6494 tx_head->time_stamp = jiffies; 6495 6496 /* Avoid any potential race with xdp_xmit and cleanup */ 6497 smp_wmb(); 6498 6499 /* set next_to_watch value indicating a packet is present */ 6500 tx_head->next_to_watch = tx_desc; 6501 tx_ring->next_to_use = index; 6502 6503 /* Make sure there is space in the ring for the next send. */ 6504 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6505 6506 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) 6507 writel(index, tx_ring->tail); 6508 6509 return IGB_XDP_TX; 6510 6511 unmap: 6512 for (;;) { 6513 tx_buffer = &tx_ring->tx_buffer_info[index]; 6514 if (dma_unmap_len(tx_buffer, len)) 6515 dma_unmap_page(tx_ring->dev, 6516 dma_unmap_addr(tx_buffer, dma), 6517 dma_unmap_len(tx_buffer, len), 6518 DMA_TO_DEVICE); 6519 dma_unmap_len_set(tx_buffer, len, 0); 6520 if (tx_buffer == tx_head) 6521 break; 6522 6523 if (!index) 6524 index += tx_ring->count; 6525 index--; 6526 } 6527 6528 return IGB_XDP_CONSUMED; 6529 } 6530 6531 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6532 struct igb_ring *tx_ring) 6533 { 6534 struct igb_tx_buffer *first; 6535 int tso; 6536 u32 tx_flags = 0; 6537 unsigned short f; 6538 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6539 __be16 protocol = vlan_get_protocol(skb); 6540 u8 hdr_len = 0; 6541 6542 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6543 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6544 * + 2 desc gap to keep tail from touching head, 6545 * + 1 desc for context descriptor, 6546 * otherwise try next time 6547 */ 6548 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6549 count += TXD_USE_COUNT(skb_frag_size( 6550 &skb_shinfo(skb)->frags[f])); 6551 6552 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6553 /* this is a hard error */ 6554 return NETDEV_TX_BUSY; 6555 } 6556 6557 if (unlikely(test_bit(IGB_RING_FLAG_TX_DISABLED, &tx_ring->flags))) 6558 return NETDEV_TX_BUSY; 6559 6560 /* record the location of the first descriptor for this packet */ 6561 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6562 first->type = IGB_TYPE_SKB; 6563 first->skb = skb; 6564 first->bytecount = skb->len; 6565 first->gso_segs = 1; 6566 6567 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6568 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6569 6570 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6571 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6572 &adapter->state)) { 6573 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6574 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6575 6576 adapter->ptp_tx_skb = skb_get(skb); 6577 adapter->ptp_tx_start = jiffies; 6578 if (adapter->hw.mac.type == e1000_82576) 6579 schedule_work(&adapter->ptp_tx_work); 6580 } else { 6581 adapter->tx_hwtstamp_skipped++; 6582 } 6583 } 6584 6585 if (skb_vlan_tag_present(skb)) { 6586 tx_flags |= IGB_TX_FLAGS_VLAN; 6587 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6588 } 6589 6590 /* record initial flags and protocol */ 6591 first->tx_flags = tx_flags; 6592 first->protocol = protocol; 6593 6594 tso = igb_tso(tx_ring, first, &hdr_len); 6595 if (tso < 0) 6596 goto out_drop; 6597 else if (!tso) 6598 igb_tx_csum(tx_ring, first); 6599 6600 if (igb_tx_map(tx_ring, first, hdr_len)) 6601 goto cleanup_tx_tstamp; 6602 6603 return NETDEV_TX_OK; 6604 6605 out_drop: 6606 dev_kfree_skb_any(first->skb); 6607 first->skb = NULL; 6608 cleanup_tx_tstamp: 6609 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6610 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6611 6612 dev_kfree_skb_any(adapter->ptp_tx_skb); 6613 adapter->ptp_tx_skb = NULL; 6614 if (adapter->hw.mac.type == e1000_82576) 6615 cancel_work_sync(&adapter->ptp_tx_work); 6616 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6617 } 6618 6619 return NETDEV_TX_OK; 6620 } 6621 6622 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6623 struct sk_buff *skb) 6624 { 6625 unsigned int r_idx = skb->queue_mapping; 6626 6627 if (r_idx >= adapter->num_tx_queues) 6628 r_idx = r_idx % adapter->num_tx_queues; 6629 6630 return adapter->tx_ring[r_idx]; 6631 } 6632 6633 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6634 struct net_device *netdev) 6635 { 6636 struct igb_adapter *adapter = netdev_priv(netdev); 6637 6638 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6639 * in order to meet this minimum size requirement. 6640 */ 6641 if (skb_put_padto(skb, 17)) 6642 return NETDEV_TX_OK; 6643 6644 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6645 } 6646 6647 /** 6648 * igb_tx_timeout - Respond to a Tx Hang 6649 * @netdev: network interface device structure 6650 * @txqueue: number of the Tx queue that hung (unused) 6651 **/ 6652 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6653 { 6654 struct igb_adapter *adapter = netdev_priv(netdev); 6655 struct e1000_hw *hw = &adapter->hw; 6656 6657 /* Do the reset outside of interrupt context */ 6658 adapter->tx_timeout_count++; 6659 6660 if (hw->mac.type >= e1000_82580) 6661 hw->dev_spec._82575.global_device_reset = true; 6662 6663 schedule_work(&adapter->reset_task); 6664 wr32(E1000_EICS, 6665 (adapter->eims_enable_mask & ~adapter->eims_other)); 6666 } 6667 6668 static void igb_reset_task(struct work_struct *work) 6669 { 6670 struct igb_adapter *adapter; 6671 adapter = container_of(work, struct igb_adapter, reset_task); 6672 6673 rtnl_lock(); 6674 /* If we're already down or resetting, just bail */ 6675 if (test_bit(__IGB_DOWN, &adapter->state) || 6676 test_bit(__IGB_RESETTING, &adapter->state)) { 6677 rtnl_unlock(); 6678 return; 6679 } 6680 6681 igb_dump(adapter); 6682 netdev_err(adapter->netdev, "Reset adapter\n"); 6683 igb_reinit_locked(adapter); 6684 rtnl_unlock(); 6685 } 6686 6687 /** 6688 * igb_get_stats64 - Get System Network Statistics 6689 * @netdev: network interface device structure 6690 * @stats: rtnl_link_stats64 pointer 6691 **/ 6692 static void igb_get_stats64(struct net_device *netdev, 6693 struct rtnl_link_stats64 *stats) 6694 { 6695 struct igb_adapter *adapter = netdev_priv(netdev); 6696 6697 spin_lock(&adapter->stats64_lock); 6698 igb_update_stats(adapter); 6699 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6700 spin_unlock(&adapter->stats64_lock); 6701 } 6702 6703 /** 6704 * igb_change_mtu - Change the Maximum Transfer Unit 6705 * @netdev: network interface device structure 6706 * @new_mtu: new value for maximum frame size 6707 * 6708 * Returns 0 on success, negative on failure 6709 **/ 6710 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6711 { 6712 struct igb_adapter *adapter = netdev_priv(netdev); 6713 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD; 6714 6715 if (igb_xdp_is_enabled(adapter)) { 6716 int i; 6717 6718 for (i = 0; i < adapter->num_rx_queues; i++) { 6719 struct igb_ring *ring = adapter->rx_ring[i]; 6720 6721 if (max_frame > igb_rx_bufsz(ring)) { 6722 netdev_warn(adapter->netdev, 6723 "Requested MTU size is not supported with XDP. Max frame size is %d\n", 6724 max_frame); 6725 return -EINVAL; 6726 } 6727 } 6728 } 6729 6730 /* adjust max frame to be at least the size of a standard frame */ 6731 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6732 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6733 6734 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6735 usleep_range(1000, 2000); 6736 6737 /* igb_down has a dependency on max_frame_size */ 6738 adapter->max_frame_size = max_frame; 6739 6740 if (netif_running(netdev)) 6741 igb_down(adapter); 6742 6743 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6744 netdev->mtu, new_mtu); 6745 WRITE_ONCE(netdev->mtu, new_mtu); 6746 6747 if (netif_running(netdev)) 6748 igb_up(adapter); 6749 else 6750 igb_reset(adapter); 6751 6752 clear_bit(__IGB_RESETTING, &adapter->state); 6753 6754 return 0; 6755 } 6756 6757 /** 6758 * igb_update_stats - Update the board statistics counters 6759 * @adapter: board private structure 6760 **/ 6761 void igb_update_stats(struct igb_adapter *adapter) 6762 { 6763 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6764 struct e1000_hw *hw = &adapter->hw; 6765 struct pci_dev *pdev = adapter->pdev; 6766 u32 reg, mpc; 6767 int i; 6768 u64 bytes, packets; 6769 unsigned int start; 6770 u64 _bytes, _packets; 6771 6772 /* Prevent stats update while adapter is being reset, or if the pci 6773 * connection is down. 6774 */ 6775 if (adapter->link_speed == 0) 6776 return; 6777 if (pci_channel_offline(pdev)) 6778 return; 6779 6780 bytes = 0; 6781 packets = 0; 6782 6783 rcu_read_lock(); 6784 for (i = 0; i < adapter->num_rx_queues; i++) { 6785 struct igb_ring *ring = adapter->rx_ring[i]; 6786 u32 rqdpc = rd32(E1000_RQDPC(i)); 6787 if (hw->mac.type >= e1000_i210) 6788 wr32(E1000_RQDPC(i), 0); 6789 6790 if (rqdpc) { 6791 ring->rx_stats.drops += rqdpc; 6792 net_stats->rx_fifo_errors += rqdpc; 6793 } 6794 6795 do { 6796 start = u64_stats_fetch_begin(&ring->rx_syncp); 6797 _bytes = ring->rx_stats.bytes; 6798 _packets = ring->rx_stats.packets; 6799 } while (u64_stats_fetch_retry(&ring->rx_syncp, start)); 6800 bytes += _bytes; 6801 packets += _packets; 6802 } 6803 6804 net_stats->rx_bytes = bytes; 6805 net_stats->rx_packets = packets; 6806 6807 bytes = 0; 6808 packets = 0; 6809 for (i = 0; i < adapter->num_tx_queues; i++) { 6810 struct igb_ring *ring = adapter->tx_ring[i]; 6811 do { 6812 start = u64_stats_fetch_begin(&ring->tx_syncp); 6813 _bytes = ring->tx_stats.bytes; 6814 _packets = ring->tx_stats.packets; 6815 } while (u64_stats_fetch_retry(&ring->tx_syncp, start)); 6816 bytes += _bytes; 6817 packets += _packets; 6818 } 6819 net_stats->tx_bytes = bytes; 6820 net_stats->tx_packets = packets; 6821 rcu_read_unlock(); 6822 6823 /* read stats registers */ 6824 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6825 adapter->stats.gprc += rd32(E1000_GPRC); 6826 adapter->stats.gorc += rd32(E1000_GORCL); 6827 rd32(E1000_GORCH); /* clear GORCL */ 6828 adapter->stats.bprc += rd32(E1000_BPRC); 6829 adapter->stats.mprc += rd32(E1000_MPRC); 6830 adapter->stats.roc += rd32(E1000_ROC); 6831 6832 adapter->stats.prc64 += rd32(E1000_PRC64); 6833 adapter->stats.prc127 += rd32(E1000_PRC127); 6834 adapter->stats.prc255 += rd32(E1000_PRC255); 6835 adapter->stats.prc511 += rd32(E1000_PRC511); 6836 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6837 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6838 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6839 adapter->stats.sec += rd32(E1000_SEC); 6840 6841 mpc = rd32(E1000_MPC); 6842 adapter->stats.mpc += mpc; 6843 net_stats->rx_fifo_errors += mpc; 6844 adapter->stats.scc += rd32(E1000_SCC); 6845 adapter->stats.ecol += rd32(E1000_ECOL); 6846 adapter->stats.mcc += rd32(E1000_MCC); 6847 adapter->stats.latecol += rd32(E1000_LATECOL); 6848 adapter->stats.dc += rd32(E1000_DC); 6849 adapter->stats.rlec += rd32(E1000_RLEC); 6850 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6851 adapter->stats.xontxc += rd32(E1000_XONTXC); 6852 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6853 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6854 adapter->stats.fcruc += rd32(E1000_FCRUC); 6855 adapter->stats.gptc += rd32(E1000_GPTC); 6856 adapter->stats.gotc += rd32(E1000_GOTCL); 6857 rd32(E1000_GOTCH); /* clear GOTCL */ 6858 adapter->stats.rnbc += rd32(E1000_RNBC); 6859 adapter->stats.ruc += rd32(E1000_RUC); 6860 adapter->stats.rfc += rd32(E1000_RFC); 6861 adapter->stats.rjc += rd32(E1000_RJC); 6862 adapter->stats.tor += rd32(E1000_TORH); 6863 adapter->stats.tot += rd32(E1000_TOTH); 6864 adapter->stats.tpr += rd32(E1000_TPR); 6865 6866 adapter->stats.ptc64 += rd32(E1000_PTC64); 6867 adapter->stats.ptc127 += rd32(E1000_PTC127); 6868 adapter->stats.ptc255 += rd32(E1000_PTC255); 6869 adapter->stats.ptc511 += rd32(E1000_PTC511); 6870 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6871 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6872 6873 adapter->stats.mptc += rd32(E1000_MPTC); 6874 adapter->stats.bptc += rd32(E1000_BPTC); 6875 6876 adapter->stats.tpt += rd32(E1000_TPT); 6877 adapter->stats.colc += rd32(E1000_COLC); 6878 6879 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6880 /* read internal phy specific stats */ 6881 reg = rd32(E1000_CTRL_EXT); 6882 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6883 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6884 6885 /* this stat has invalid values on i210/i211 */ 6886 if ((hw->mac.type != e1000_i210) && 6887 (hw->mac.type != e1000_i211)) 6888 adapter->stats.tncrs += rd32(E1000_TNCRS); 6889 } 6890 6891 adapter->stats.tsctc += rd32(E1000_TSCTC); 6892 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6893 6894 adapter->stats.iac += rd32(E1000_IAC); 6895 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6896 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6897 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6898 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6899 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6900 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6901 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6902 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6903 6904 /* Fill out the OS statistics structure */ 6905 net_stats->multicast = adapter->stats.mprc; 6906 net_stats->collisions = adapter->stats.colc; 6907 6908 /* Rx Errors */ 6909 6910 /* RLEC on some newer hardware can be incorrect so build 6911 * our own version based on RUC and ROC 6912 */ 6913 net_stats->rx_errors = adapter->stats.rxerrc + 6914 adapter->stats.crcerrs + adapter->stats.algnerrc + 6915 adapter->stats.ruc + adapter->stats.roc + 6916 adapter->stats.cexterr; 6917 net_stats->rx_length_errors = adapter->stats.ruc + 6918 adapter->stats.roc; 6919 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6920 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6921 net_stats->rx_missed_errors = adapter->stats.mpc; 6922 6923 /* Tx Errors */ 6924 net_stats->tx_errors = adapter->stats.ecol + 6925 adapter->stats.latecol; 6926 net_stats->tx_aborted_errors = adapter->stats.ecol; 6927 net_stats->tx_window_errors = adapter->stats.latecol; 6928 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6929 6930 /* Tx Dropped needs to be maintained elsewhere */ 6931 6932 /* Management Stats */ 6933 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6934 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6935 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6936 6937 /* OS2BMC Stats */ 6938 reg = rd32(E1000_MANC); 6939 if (reg & E1000_MANC_EN_BMC2OS) { 6940 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6941 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6942 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6943 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6944 } 6945 } 6946 6947 static void igb_perout(struct igb_adapter *adapter, int tsintr_tt) 6948 { 6949 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_PEROUT, tsintr_tt); 6950 struct e1000_hw *hw = &adapter->hw; 6951 struct timespec64 ts; 6952 u32 tsauxc; 6953 6954 if (pin < 0 || pin >= IGB_N_SDP) 6955 return; 6956 6957 spin_lock(&adapter->tmreg_lock); 6958 6959 if (hw->mac.type == e1000_82580 || 6960 hw->mac.type == e1000_i354 || 6961 hw->mac.type == e1000_i350) { 6962 s64 ns = timespec64_to_ns(&adapter->perout[tsintr_tt].period); 6963 u32 systiml, systimh, level_mask, level, rem; 6964 u64 systim, now; 6965 6966 /* read systim registers in sequence */ 6967 rd32(E1000_SYSTIMR); 6968 systiml = rd32(E1000_SYSTIML); 6969 systimh = rd32(E1000_SYSTIMH); 6970 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml); 6971 now = timecounter_cyc2time(&adapter->tc, systim); 6972 6973 if (pin < 2) { 6974 level_mask = (tsintr_tt == 1) ? 0x80000 : 0x40000; 6975 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0; 6976 } else { 6977 level_mask = (tsintr_tt == 1) ? 0x80 : 0x40; 6978 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0; 6979 } 6980 6981 div_u64_rem(now, ns, &rem); 6982 systim = systim + (ns - rem); 6983 6984 /* synchronize pin level with rising/falling edges */ 6985 div_u64_rem(now, ns << 1, &rem); 6986 if (rem < ns) { 6987 /* first half of period */ 6988 if (level == 0) { 6989 /* output is already low, skip this period */ 6990 systim += ns; 6991 pr_notice("igb: periodic output on %s missed falling edge\n", 6992 adapter->sdp_config[pin].name); 6993 } 6994 } else { 6995 /* second half of period */ 6996 if (level == 1) { 6997 /* output is already high, skip this period */ 6998 systim += ns; 6999 pr_notice("igb: periodic output on %s missed rising edge\n", 7000 adapter->sdp_config[pin].name); 7001 } 7002 } 7003 7004 /* for this chip family tv_sec is the upper part of the binary value, 7005 * so not seconds 7006 */ 7007 ts.tv_nsec = (u32)systim; 7008 ts.tv_sec = ((u32)(systim >> 32)) & 0xFF; 7009 } else { 7010 ts = timespec64_add(adapter->perout[tsintr_tt].start, 7011 adapter->perout[tsintr_tt].period); 7012 } 7013 7014 /* u32 conversion of tv_sec is safe until y2106 */ 7015 wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec); 7016 wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec); 7017 tsauxc = rd32(E1000_TSAUXC); 7018 tsauxc |= TSAUXC_EN_TT0; 7019 wr32(E1000_TSAUXC, tsauxc); 7020 adapter->perout[tsintr_tt].start = ts; 7021 7022 spin_unlock(&adapter->tmreg_lock); 7023 } 7024 7025 static void igb_extts(struct igb_adapter *adapter, int tsintr_tt) 7026 { 7027 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_EXTTS, tsintr_tt); 7028 int auxstmpl = (tsintr_tt == 1) ? E1000_AUXSTMPL1 : E1000_AUXSTMPL0; 7029 int auxstmph = (tsintr_tt == 1) ? E1000_AUXSTMPH1 : E1000_AUXSTMPH0; 7030 struct e1000_hw *hw = &adapter->hw; 7031 struct ptp_clock_event event; 7032 struct timespec64 ts; 7033 unsigned long flags; 7034 7035 if (pin < 0 || pin >= IGB_N_SDP) 7036 return; 7037 7038 if (hw->mac.type == e1000_82580 || 7039 hw->mac.type == e1000_i354 || 7040 hw->mac.type == e1000_i350) { 7041 u64 ns = rd32(auxstmpl); 7042 7043 ns += ((u64)(rd32(auxstmph) & 0xFF)) << 32; 7044 spin_lock_irqsave(&adapter->tmreg_lock, flags); 7045 ns = timecounter_cyc2time(&adapter->tc, ns); 7046 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 7047 ts = ns_to_timespec64(ns); 7048 } else { 7049 ts.tv_nsec = rd32(auxstmpl); 7050 ts.tv_sec = rd32(auxstmph); 7051 } 7052 7053 event.type = PTP_CLOCK_EXTTS; 7054 event.index = tsintr_tt; 7055 event.timestamp = ts.tv_sec * 1000000000ULL + ts.tv_nsec; 7056 ptp_clock_event(adapter->ptp_clock, &event); 7057 } 7058 7059 static void igb_tsync_interrupt(struct igb_adapter *adapter) 7060 { 7061 const u32 mask = (TSINTR_SYS_WRAP | E1000_TSICR_TXTS | 7062 TSINTR_TT0 | TSINTR_TT1 | 7063 TSINTR_AUTT0 | TSINTR_AUTT1); 7064 struct e1000_hw *hw = &adapter->hw; 7065 u32 tsicr = rd32(E1000_TSICR); 7066 struct ptp_clock_event event; 7067 7068 if (hw->mac.type == e1000_82580) { 7069 /* 82580 has a hardware bug that requires an explicit 7070 * write to clear the TimeSync interrupt cause. 7071 */ 7072 wr32(E1000_TSICR, tsicr & mask); 7073 } 7074 7075 if (tsicr & TSINTR_SYS_WRAP) { 7076 event.type = PTP_CLOCK_PPS; 7077 if (adapter->ptp_caps.pps) 7078 ptp_clock_event(adapter->ptp_clock, &event); 7079 } 7080 7081 if (tsicr & E1000_TSICR_TXTS) { 7082 /* retrieve hardware timestamp */ 7083 schedule_work(&adapter->ptp_tx_work); 7084 } 7085 7086 if (tsicr & TSINTR_TT0) 7087 igb_perout(adapter, 0); 7088 7089 if (tsicr & TSINTR_TT1) 7090 igb_perout(adapter, 1); 7091 7092 if (tsicr & TSINTR_AUTT0) 7093 igb_extts(adapter, 0); 7094 7095 if (tsicr & TSINTR_AUTT1) 7096 igb_extts(adapter, 1); 7097 } 7098 7099 static irqreturn_t igb_msix_other(int irq, void *data) 7100 { 7101 struct igb_adapter *adapter = data; 7102 struct e1000_hw *hw = &adapter->hw; 7103 u32 icr = rd32(E1000_ICR); 7104 /* reading ICR causes bit 31 of EICR to be cleared */ 7105 7106 if (icr & E1000_ICR_DRSTA) 7107 schedule_work(&adapter->reset_task); 7108 7109 if (icr & E1000_ICR_DOUTSYNC) { 7110 /* HW is reporting DMA is out of sync */ 7111 adapter->stats.doosync++; 7112 /* The DMA Out of Sync is also indication of a spoof event 7113 * in IOV mode. Check the Wrong VM Behavior register to 7114 * see if it is really a spoof event. 7115 */ 7116 igb_check_wvbr(adapter); 7117 } 7118 7119 /* Check for a mailbox event */ 7120 if (icr & E1000_ICR_VMMB) 7121 igb_msg_task(adapter); 7122 7123 if (icr & E1000_ICR_LSC) { 7124 hw->mac.get_link_status = 1; 7125 /* guard against interrupt when we're going down */ 7126 if (!test_bit(__IGB_DOWN, &adapter->state)) 7127 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7128 } 7129 7130 if (icr & E1000_ICR_TS) 7131 igb_tsync_interrupt(adapter); 7132 7133 wr32(E1000_EIMS, adapter->eims_other); 7134 7135 return IRQ_HANDLED; 7136 } 7137 7138 static void igb_write_itr(struct igb_q_vector *q_vector) 7139 { 7140 struct igb_adapter *adapter = q_vector->adapter; 7141 u32 itr_val = q_vector->itr_val & 0x7FFC; 7142 7143 if (!q_vector->set_itr) 7144 return; 7145 7146 if (!itr_val) 7147 itr_val = 0x4; 7148 7149 if (adapter->hw.mac.type == e1000_82575) 7150 itr_val |= itr_val << 16; 7151 else 7152 itr_val |= E1000_EITR_CNT_IGNR; 7153 7154 writel(itr_val, q_vector->itr_register); 7155 q_vector->set_itr = 0; 7156 } 7157 7158 static irqreturn_t igb_msix_ring(int irq, void *data) 7159 { 7160 struct igb_q_vector *q_vector = data; 7161 7162 /* Write the ITR value calculated from the previous interrupt. */ 7163 igb_write_itr(q_vector); 7164 7165 napi_schedule(&q_vector->napi); 7166 7167 return IRQ_HANDLED; 7168 } 7169 7170 #ifdef CONFIG_IGB_DCA 7171 static void igb_update_tx_dca(struct igb_adapter *adapter, 7172 struct igb_ring *tx_ring, 7173 int cpu) 7174 { 7175 struct e1000_hw *hw = &adapter->hw; 7176 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 7177 7178 if (hw->mac.type != e1000_82575) 7179 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 7180 7181 /* We can enable relaxed ordering for reads, but not writes when 7182 * DCA is enabled. This is due to a known issue in some chipsets 7183 * which will cause the DCA tag to be cleared. 7184 */ 7185 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 7186 E1000_DCA_TXCTRL_DATA_RRO_EN | 7187 E1000_DCA_TXCTRL_DESC_DCA_EN; 7188 7189 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 7190 } 7191 7192 static void igb_update_rx_dca(struct igb_adapter *adapter, 7193 struct igb_ring *rx_ring, 7194 int cpu) 7195 { 7196 struct e1000_hw *hw = &adapter->hw; 7197 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 7198 7199 if (hw->mac.type != e1000_82575) 7200 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 7201 7202 /* We can enable relaxed ordering for reads, but not writes when 7203 * DCA is enabled. This is due to a known issue in some chipsets 7204 * which will cause the DCA tag to be cleared. 7205 */ 7206 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 7207 E1000_DCA_RXCTRL_DESC_DCA_EN; 7208 7209 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 7210 } 7211 7212 static void igb_update_dca(struct igb_q_vector *q_vector) 7213 { 7214 struct igb_adapter *adapter = q_vector->adapter; 7215 int cpu = get_cpu(); 7216 7217 if (q_vector->cpu == cpu) 7218 goto out_no_update; 7219 7220 if (q_vector->tx.ring) 7221 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 7222 7223 if (q_vector->rx.ring) 7224 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 7225 7226 q_vector->cpu = cpu; 7227 out_no_update: 7228 put_cpu(); 7229 } 7230 7231 static void igb_setup_dca(struct igb_adapter *adapter) 7232 { 7233 struct e1000_hw *hw = &adapter->hw; 7234 int i; 7235 7236 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 7237 return; 7238 7239 /* Always use CB2 mode, difference is masked in the CB driver. */ 7240 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 7241 7242 for (i = 0; i < adapter->num_q_vectors; i++) { 7243 adapter->q_vector[i]->cpu = -1; 7244 igb_update_dca(adapter->q_vector[i]); 7245 } 7246 } 7247 7248 static int __igb_notify_dca(struct device *dev, void *data) 7249 { 7250 struct net_device *netdev = dev_get_drvdata(dev); 7251 struct igb_adapter *adapter = netdev_priv(netdev); 7252 struct pci_dev *pdev = adapter->pdev; 7253 struct e1000_hw *hw = &adapter->hw; 7254 unsigned long event = *(unsigned long *)data; 7255 7256 switch (event) { 7257 case DCA_PROVIDER_ADD: 7258 /* if already enabled, don't do it again */ 7259 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 7260 break; 7261 if (dca_add_requester(dev) == 0) { 7262 adapter->flags |= IGB_FLAG_DCA_ENABLED; 7263 dev_info(&pdev->dev, "DCA enabled\n"); 7264 igb_setup_dca(adapter); 7265 break; 7266 } 7267 fallthrough; /* since DCA is disabled. */ 7268 case DCA_PROVIDER_REMOVE: 7269 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 7270 /* without this a class_device is left 7271 * hanging around in the sysfs model 7272 */ 7273 dca_remove_requester(dev); 7274 dev_info(&pdev->dev, "DCA disabled\n"); 7275 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 7276 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 7277 } 7278 break; 7279 } 7280 7281 return 0; 7282 } 7283 7284 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 7285 void *p) 7286 { 7287 int ret_val; 7288 7289 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 7290 __igb_notify_dca); 7291 7292 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 7293 } 7294 #endif /* CONFIG_IGB_DCA */ 7295 7296 #ifdef CONFIG_PCI_IOV 7297 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 7298 { 7299 unsigned char mac_addr[ETH_ALEN]; 7300 7301 eth_zero_addr(mac_addr); 7302 igb_set_vf_mac(adapter, vf, mac_addr); 7303 7304 /* By default spoof check is enabled for all VFs */ 7305 adapter->vf_data[vf].spoofchk_enabled = true; 7306 7307 /* By default VFs are not trusted */ 7308 adapter->vf_data[vf].trusted = false; 7309 7310 return 0; 7311 } 7312 7313 #endif 7314 static void igb_ping_all_vfs(struct igb_adapter *adapter) 7315 { 7316 struct e1000_hw *hw = &adapter->hw; 7317 u32 ping; 7318 int i; 7319 7320 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 7321 ping = E1000_PF_CONTROL_MSG; 7322 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 7323 ping |= E1000_VT_MSGTYPE_CTS; 7324 igb_write_mbx(hw, &ping, 1, i); 7325 } 7326 } 7327 7328 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7329 { 7330 struct e1000_hw *hw = &adapter->hw; 7331 u32 vmolr = rd32(E1000_VMOLR(vf)); 7332 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7333 7334 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 7335 IGB_VF_FLAG_MULTI_PROMISC); 7336 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7337 7338 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 7339 vmolr |= E1000_VMOLR_MPME; 7340 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 7341 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 7342 } else { 7343 /* if we have hashes and we are clearing a multicast promisc 7344 * flag we need to write the hashes to the MTA as this step 7345 * was previously skipped 7346 */ 7347 if (vf_data->num_vf_mc_hashes > 30) { 7348 vmolr |= E1000_VMOLR_MPME; 7349 } else if (vf_data->num_vf_mc_hashes) { 7350 int j; 7351 7352 vmolr |= E1000_VMOLR_ROMPE; 7353 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7354 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7355 } 7356 } 7357 7358 wr32(E1000_VMOLR(vf), vmolr); 7359 7360 /* there are flags left unprocessed, likely not supported */ 7361 if (*msgbuf & E1000_VT_MSGINFO_MASK) 7362 return -EINVAL; 7363 7364 return 0; 7365 } 7366 7367 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 7368 u32 *msgbuf, u32 vf) 7369 { 7370 int n = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]); 7371 u16 *hash_list = (u16 *)&msgbuf[1]; 7372 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7373 int i; 7374 7375 /* salt away the number of multicast addresses assigned 7376 * to this VF for later use to restore when the PF multi cast 7377 * list changes 7378 */ 7379 vf_data->num_vf_mc_hashes = n; 7380 7381 /* only up to 30 hash values supported */ 7382 if (n > 30) 7383 n = 30; 7384 7385 /* store the hashes for later use */ 7386 for (i = 0; i < n; i++) 7387 vf_data->vf_mc_hashes[i] = hash_list[i]; 7388 7389 /* Flush and reset the mta with the new values */ 7390 igb_set_rx_mode(adapter->netdev); 7391 7392 return 0; 7393 } 7394 7395 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 7396 { 7397 struct e1000_hw *hw = &adapter->hw; 7398 struct vf_data_storage *vf_data; 7399 int i, j; 7400 7401 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7402 u32 vmolr = rd32(E1000_VMOLR(i)); 7403 7404 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7405 7406 vf_data = &adapter->vf_data[i]; 7407 7408 if ((vf_data->num_vf_mc_hashes > 30) || 7409 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 7410 vmolr |= E1000_VMOLR_MPME; 7411 } else if (vf_data->num_vf_mc_hashes) { 7412 vmolr |= E1000_VMOLR_ROMPE; 7413 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7414 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7415 } 7416 wr32(E1000_VMOLR(i), vmolr); 7417 } 7418 } 7419 7420 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 7421 { 7422 struct e1000_hw *hw = &adapter->hw; 7423 u32 pool_mask, vlvf_mask, i; 7424 7425 /* create mask for VF and other pools */ 7426 pool_mask = E1000_VLVF_POOLSEL_MASK; 7427 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 7428 7429 /* drop PF from pool bits */ 7430 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 7431 adapter->vfs_allocated_count); 7432 7433 /* Find the vlan filter for this id */ 7434 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 7435 u32 vlvf = rd32(E1000_VLVF(i)); 7436 u32 vfta_mask, vid, vfta; 7437 7438 /* remove the vf from the pool */ 7439 if (!(vlvf & vlvf_mask)) 7440 continue; 7441 7442 /* clear out bit from VLVF */ 7443 vlvf ^= vlvf_mask; 7444 7445 /* if other pools are present, just remove ourselves */ 7446 if (vlvf & pool_mask) 7447 goto update_vlvfb; 7448 7449 /* if PF is present, leave VFTA */ 7450 if (vlvf & E1000_VLVF_POOLSEL_MASK) 7451 goto update_vlvf; 7452 7453 vid = vlvf & E1000_VLVF_VLANID_MASK; 7454 vfta_mask = BIT(vid % 32); 7455 7456 /* clear bit from VFTA */ 7457 vfta = adapter->shadow_vfta[vid / 32]; 7458 if (vfta & vfta_mask) 7459 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 7460 update_vlvf: 7461 /* clear pool selection enable */ 7462 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7463 vlvf &= E1000_VLVF_POOLSEL_MASK; 7464 else 7465 vlvf = 0; 7466 update_vlvfb: 7467 /* clear pool bits */ 7468 wr32(E1000_VLVF(i), vlvf); 7469 } 7470 } 7471 7472 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 7473 { 7474 u32 vlvf; 7475 int idx; 7476 7477 /* short cut the special case */ 7478 if (vlan == 0) 7479 return 0; 7480 7481 /* Search for the VLAN id in the VLVF entries */ 7482 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 7483 vlvf = rd32(E1000_VLVF(idx)); 7484 if ((vlvf & VLAN_VID_MASK) == vlan) 7485 break; 7486 } 7487 7488 return idx; 7489 } 7490 7491 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 7492 { 7493 struct e1000_hw *hw = &adapter->hw; 7494 u32 bits, pf_id; 7495 int idx; 7496 7497 idx = igb_find_vlvf_entry(hw, vid); 7498 if (!idx) 7499 return; 7500 7501 /* See if any other pools are set for this VLAN filter 7502 * entry other than the PF. 7503 */ 7504 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 7505 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 7506 bits &= rd32(E1000_VLVF(idx)); 7507 7508 /* Disable the filter so this falls into the default pool. */ 7509 if (!bits) { 7510 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7511 wr32(E1000_VLVF(idx), BIT(pf_id)); 7512 else 7513 wr32(E1000_VLVF(idx), 0); 7514 } 7515 } 7516 7517 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 7518 bool add, u32 vf) 7519 { 7520 int pf_id = adapter->vfs_allocated_count; 7521 struct e1000_hw *hw = &adapter->hw; 7522 int err; 7523 7524 /* If VLAN overlaps with one the PF is currently monitoring make 7525 * sure that we are able to allocate a VLVF entry. This may be 7526 * redundant but it guarantees PF will maintain visibility to 7527 * the VLAN. 7528 */ 7529 if (add && test_bit(vid, adapter->active_vlans)) { 7530 err = igb_vfta_set(hw, vid, pf_id, true, false); 7531 if (err) 7532 return err; 7533 } 7534 7535 err = igb_vfta_set(hw, vid, vf, add, false); 7536 7537 if (add && !err) 7538 return err; 7539 7540 /* If we failed to add the VF VLAN or we are removing the VF VLAN 7541 * we may need to drop the PF pool bit in order to allow us to free 7542 * up the VLVF resources. 7543 */ 7544 if (test_bit(vid, adapter->active_vlans) || 7545 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7546 igb_update_pf_vlvf(adapter, vid); 7547 7548 return err; 7549 } 7550 7551 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 7552 { 7553 struct e1000_hw *hw = &adapter->hw; 7554 7555 if (vid) 7556 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 7557 else 7558 wr32(E1000_VMVIR(vf), 0); 7559 } 7560 7561 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7562 u16 vlan, u8 qos) 7563 { 7564 int err; 7565 7566 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7567 if (err) 7568 return err; 7569 7570 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7571 igb_set_vmolr(adapter, vf, !vlan); 7572 7573 /* revoke access to previous VLAN */ 7574 if (vlan != adapter->vf_data[vf].pf_vlan) 7575 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7576 false, vf); 7577 7578 adapter->vf_data[vf].pf_vlan = vlan; 7579 adapter->vf_data[vf].pf_qos = qos; 7580 igb_set_vf_vlan_strip(adapter, vf, true); 7581 dev_info(&adapter->pdev->dev, 7582 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7583 if (test_bit(__IGB_DOWN, &adapter->state)) { 7584 dev_warn(&adapter->pdev->dev, 7585 "The VF VLAN has been set, but the PF device is not up.\n"); 7586 dev_warn(&adapter->pdev->dev, 7587 "Bring the PF device up before attempting to use the VF device.\n"); 7588 } 7589 7590 return err; 7591 } 7592 7593 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7594 { 7595 /* Restore tagless access via VLAN 0 */ 7596 igb_set_vf_vlan(adapter, 0, true, vf); 7597 7598 igb_set_vmvir(adapter, 0, vf); 7599 igb_set_vmolr(adapter, vf, true); 7600 7601 /* Remove any PF assigned VLAN */ 7602 if (adapter->vf_data[vf].pf_vlan) 7603 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7604 false, vf); 7605 7606 adapter->vf_data[vf].pf_vlan = 0; 7607 adapter->vf_data[vf].pf_qos = 0; 7608 igb_set_vf_vlan_strip(adapter, vf, false); 7609 7610 return 0; 7611 } 7612 7613 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7614 u16 vlan, u8 qos, __be16 vlan_proto) 7615 { 7616 struct igb_adapter *adapter = netdev_priv(netdev); 7617 7618 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7619 return -EINVAL; 7620 7621 if (vlan_proto != htons(ETH_P_8021Q)) 7622 return -EPROTONOSUPPORT; 7623 7624 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7625 igb_disable_port_vlan(adapter, vf); 7626 } 7627 7628 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7629 { 7630 int add = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]); 7631 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7632 int ret; 7633 7634 if (adapter->vf_data[vf].pf_vlan) 7635 return -1; 7636 7637 /* VLAN 0 is a special case, don't allow it to be removed */ 7638 if (!vid && !add) 7639 return 0; 7640 7641 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7642 if (!ret) 7643 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7644 return ret; 7645 } 7646 7647 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7648 { 7649 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7650 7651 /* clear flags - except flag that indicates PF has set the MAC */ 7652 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7653 vf_data->last_nack = jiffies; 7654 7655 /* reset vlans for device */ 7656 igb_clear_vf_vfta(adapter, vf); 7657 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7658 igb_set_vmvir(adapter, vf_data->pf_vlan | 7659 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7660 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7661 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7662 7663 /* reset multicast table array for vf */ 7664 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7665 7666 /* Flush and reset the mta with the new values */ 7667 igb_set_rx_mode(adapter->netdev); 7668 } 7669 7670 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7671 { 7672 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7673 7674 /* clear mac address as we were hotplug removed/added */ 7675 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7676 eth_zero_addr(vf_mac); 7677 7678 /* process remaining reset events */ 7679 igb_vf_reset(adapter, vf); 7680 } 7681 7682 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7683 { 7684 struct e1000_hw *hw = &adapter->hw; 7685 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7686 u32 reg, msgbuf[3] = {}; 7687 u8 *addr = (u8 *)(&msgbuf[1]); 7688 7689 /* process all the same items cleared in a function level reset */ 7690 igb_vf_reset(adapter, vf); 7691 7692 /* set vf mac address */ 7693 igb_set_vf_mac(adapter, vf, vf_mac); 7694 7695 /* enable transmit and receive for vf */ 7696 reg = rd32(E1000_VFTE); 7697 wr32(E1000_VFTE, reg | BIT(vf)); 7698 reg = rd32(E1000_VFRE); 7699 wr32(E1000_VFRE, reg | BIT(vf)); 7700 7701 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7702 7703 /* reply to reset with ack and vf mac address */ 7704 if (!is_zero_ether_addr(vf_mac)) { 7705 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7706 memcpy(addr, vf_mac, ETH_ALEN); 7707 } else { 7708 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7709 } 7710 igb_write_mbx(hw, msgbuf, 3, vf); 7711 } 7712 7713 static void igb_flush_mac_table(struct igb_adapter *adapter) 7714 { 7715 struct e1000_hw *hw = &adapter->hw; 7716 int i; 7717 7718 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7719 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7720 eth_zero_addr(adapter->mac_table[i].addr); 7721 adapter->mac_table[i].queue = 0; 7722 igb_rar_set_index(adapter, i); 7723 } 7724 } 7725 7726 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7727 { 7728 struct e1000_hw *hw = &adapter->hw; 7729 /* do not count rar entries reserved for VFs MAC addresses */ 7730 int rar_entries = hw->mac.rar_entry_count - 7731 adapter->vfs_allocated_count; 7732 int i, count = 0; 7733 7734 for (i = 0; i < rar_entries; i++) { 7735 /* do not count default entries */ 7736 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7737 continue; 7738 7739 /* do not count "in use" entries for different queues */ 7740 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7741 (adapter->mac_table[i].queue != queue)) 7742 continue; 7743 7744 count++; 7745 } 7746 7747 return count; 7748 } 7749 7750 /* Set default MAC address for the PF in the first RAR entry */ 7751 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7752 { 7753 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7754 7755 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7756 mac_table->queue = adapter->vfs_allocated_count; 7757 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7758 7759 igb_rar_set_index(adapter, 0); 7760 } 7761 7762 /* If the filter to be added and an already existing filter express 7763 * the same address and address type, it should be possible to only 7764 * override the other configurations, for example the queue to steer 7765 * traffic. 7766 */ 7767 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7768 const u8 *addr, const u8 flags) 7769 { 7770 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7771 return true; 7772 7773 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7774 (flags & IGB_MAC_STATE_SRC_ADDR)) 7775 return false; 7776 7777 if (!ether_addr_equal(addr, entry->addr)) 7778 return false; 7779 7780 return true; 7781 } 7782 7783 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7784 * 'flags' is used to indicate what kind of match is made, match is by 7785 * default for the destination address, if matching by source address 7786 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7787 */ 7788 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7789 const u8 *addr, const u8 queue, 7790 const u8 flags) 7791 { 7792 struct e1000_hw *hw = &adapter->hw; 7793 int rar_entries = hw->mac.rar_entry_count - 7794 adapter->vfs_allocated_count; 7795 int i; 7796 7797 if (is_zero_ether_addr(addr)) 7798 return -EINVAL; 7799 7800 /* Search for the first empty entry in the MAC table. 7801 * Do not touch entries at the end of the table reserved for the VF MAC 7802 * addresses. 7803 */ 7804 for (i = 0; i < rar_entries; i++) { 7805 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7806 addr, flags)) 7807 continue; 7808 7809 ether_addr_copy(adapter->mac_table[i].addr, addr); 7810 adapter->mac_table[i].queue = queue; 7811 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7812 7813 igb_rar_set_index(adapter, i); 7814 return i; 7815 } 7816 7817 return -ENOSPC; 7818 } 7819 7820 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7821 const u8 queue) 7822 { 7823 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7824 } 7825 7826 /* Remove a MAC filter for 'addr' directing matching traffic to 7827 * 'queue', 'flags' is used to indicate what kind of match need to be 7828 * removed, match is by default for the destination address, if 7829 * matching by source address is to be removed the flag 7830 * IGB_MAC_STATE_SRC_ADDR can be used. 7831 */ 7832 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7833 const u8 *addr, const u8 queue, 7834 const u8 flags) 7835 { 7836 struct e1000_hw *hw = &adapter->hw; 7837 int rar_entries = hw->mac.rar_entry_count - 7838 adapter->vfs_allocated_count; 7839 int i; 7840 7841 if (is_zero_ether_addr(addr)) 7842 return -EINVAL; 7843 7844 /* Search for matching entry in the MAC table based on given address 7845 * and queue. Do not touch entries at the end of the table reserved 7846 * for the VF MAC addresses. 7847 */ 7848 for (i = 0; i < rar_entries; i++) { 7849 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7850 continue; 7851 if ((adapter->mac_table[i].state & flags) != flags) 7852 continue; 7853 if (adapter->mac_table[i].queue != queue) 7854 continue; 7855 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7856 continue; 7857 7858 /* When a filter for the default address is "deleted", 7859 * we return it to its initial configuration 7860 */ 7861 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7862 adapter->mac_table[i].state = 7863 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7864 adapter->mac_table[i].queue = 7865 adapter->vfs_allocated_count; 7866 } else { 7867 adapter->mac_table[i].state = 0; 7868 adapter->mac_table[i].queue = 0; 7869 eth_zero_addr(adapter->mac_table[i].addr); 7870 } 7871 7872 igb_rar_set_index(adapter, i); 7873 return 0; 7874 } 7875 7876 return -ENOENT; 7877 } 7878 7879 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7880 const u8 queue) 7881 { 7882 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7883 } 7884 7885 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7886 const u8 *addr, u8 queue, u8 flags) 7887 { 7888 struct e1000_hw *hw = &adapter->hw; 7889 7890 /* In theory, this should be supported on 82575 as well, but 7891 * that part wasn't easily accessible during development. 7892 */ 7893 if (hw->mac.type != e1000_i210) 7894 return -EOPNOTSUPP; 7895 7896 return igb_add_mac_filter_flags(adapter, addr, queue, 7897 IGB_MAC_STATE_QUEUE_STEERING | flags); 7898 } 7899 7900 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7901 const u8 *addr, u8 queue, u8 flags) 7902 { 7903 return igb_del_mac_filter_flags(adapter, addr, queue, 7904 IGB_MAC_STATE_QUEUE_STEERING | flags); 7905 } 7906 7907 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7908 { 7909 struct igb_adapter *adapter = netdev_priv(netdev); 7910 int ret; 7911 7912 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7913 7914 return min_t(int, ret, 0); 7915 } 7916 7917 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7918 { 7919 struct igb_adapter *adapter = netdev_priv(netdev); 7920 7921 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7922 7923 return 0; 7924 } 7925 7926 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7927 const u32 info, const u8 *addr) 7928 { 7929 struct pci_dev *pdev = adapter->pdev; 7930 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7931 struct vf_mac_filter *entry; 7932 bool found = false; 7933 int ret = 0; 7934 7935 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7936 !vf_data->trusted) { 7937 dev_warn(&pdev->dev, 7938 "VF %d requested MAC filter but is administratively denied\n", 7939 vf); 7940 return -EINVAL; 7941 } 7942 if (!is_valid_ether_addr(addr)) { 7943 dev_warn(&pdev->dev, 7944 "VF %d attempted to set invalid MAC filter\n", 7945 vf); 7946 return -EINVAL; 7947 } 7948 7949 switch (info) { 7950 case E1000_VF_MAC_FILTER_CLR: 7951 /* remove all unicast MAC filters related to the current VF */ 7952 list_for_each_entry(entry, &adapter->vf_macs.l, l) { 7953 if (entry->vf == vf) { 7954 entry->vf = -1; 7955 entry->free = true; 7956 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7957 } 7958 } 7959 break; 7960 case E1000_VF_MAC_FILTER_ADD: 7961 /* try to find empty slot in the list */ 7962 list_for_each_entry(entry, &adapter->vf_macs.l, l) { 7963 if (entry->free) { 7964 found = true; 7965 break; 7966 } 7967 } 7968 7969 if (found) { 7970 entry->free = false; 7971 entry->vf = vf; 7972 ether_addr_copy(entry->vf_mac, addr); 7973 7974 ret = igb_add_mac_filter(adapter, addr, vf); 7975 ret = min_t(int, ret, 0); 7976 } else { 7977 ret = -ENOSPC; 7978 } 7979 7980 if (ret == -ENOSPC) 7981 dev_warn(&pdev->dev, 7982 "VF %d has requested MAC filter but there is no space for it\n", 7983 vf); 7984 break; 7985 default: 7986 ret = -EINVAL; 7987 break; 7988 } 7989 7990 return ret; 7991 } 7992 7993 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7994 { 7995 struct pci_dev *pdev = adapter->pdev; 7996 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7997 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7998 7999 /* The VF MAC Address is stored in a packed array of bytes 8000 * starting at the second 32 bit word of the msg array 8001 */ 8002 unsigned char *addr = (unsigned char *)&msg[1]; 8003 int ret = 0; 8004 8005 if (!info) { 8006 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 8007 !vf_data->trusted) { 8008 dev_warn(&pdev->dev, 8009 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 8010 vf); 8011 return -EINVAL; 8012 } 8013 8014 if (!is_valid_ether_addr(addr)) { 8015 dev_warn(&pdev->dev, 8016 "VF %d attempted to set invalid MAC\n", 8017 vf); 8018 return -EINVAL; 8019 } 8020 8021 ret = igb_set_vf_mac(adapter, vf, addr); 8022 } else { 8023 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 8024 } 8025 8026 return ret; 8027 } 8028 8029 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 8030 { 8031 struct e1000_hw *hw = &adapter->hw; 8032 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 8033 u32 msg = E1000_VT_MSGTYPE_NACK; 8034 8035 /* if device isn't clear to send it shouldn't be reading either */ 8036 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 8037 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 8038 igb_write_mbx(hw, &msg, 1, vf); 8039 vf_data->last_nack = jiffies; 8040 } 8041 } 8042 8043 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 8044 { 8045 struct pci_dev *pdev = adapter->pdev; 8046 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 8047 struct e1000_hw *hw = &adapter->hw; 8048 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 8049 s32 retval; 8050 8051 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 8052 8053 if (retval) { 8054 /* if receive failed revoke VF CTS stats and restart init */ 8055 dev_err(&pdev->dev, "Error receiving message from VF\n"); 8056 vf_data->flags &= ~IGB_VF_FLAG_CTS; 8057 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 8058 goto unlock; 8059 goto out; 8060 } 8061 8062 /* this is a message we already processed, do nothing */ 8063 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 8064 goto unlock; 8065 8066 /* until the vf completes a reset it should not be 8067 * allowed to start any configuration. 8068 */ 8069 if (msgbuf[0] == E1000_VF_RESET) { 8070 /* unlocks mailbox */ 8071 igb_vf_reset_msg(adapter, vf); 8072 return; 8073 } 8074 8075 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 8076 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 8077 goto unlock; 8078 retval = -1; 8079 goto out; 8080 } 8081 8082 switch ((msgbuf[0] & 0xFFFF)) { 8083 case E1000_VF_SET_MAC_ADDR: 8084 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 8085 break; 8086 case E1000_VF_SET_PROMISC: 8087 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 8088 break; 8089 case E1000_VF_SET_MULTICAST: 8090 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 8091 break; 8092 case E1000_VF_SET_LPE: 8093 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 8094 break; 8095 case E1000_VF_SET_VLAN: 8096 retval = -1; 8097 if (vf_data->pf_vlan) 8098 dev_warn(&pdev->dev, 8099 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 8100 vf); 8101 else 8102 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 8103 break; 8104 default: 8105 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 8106 retval = -1; 8107 break; 8108 } 8109 8110 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 8111 out: 8112 /* notify the VF of the results of what it sent us */ 8113 if (retval) 8114 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 8115 else 8116 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 8117 8118 /* unlocks mailbox */ 8119 igb_write_mbx(hw, msgbuf, 1, vf); 8120 return; 8121 8122 unlock: 8123 igb_unlock_mbx(hw, vf); 8124 } 8125 8126 static void igb_msg_task(struct igb_adapter *adapter) 8127 { 8128 struct e1000_hw *hw = &adapter->hw; 8129 unsigned long flags; 8130 u32 vf; 8131 8132 spin_lock_irqsave(&adapter->vfs_lock, flags); 8133 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 8134 /* process any reset requests */ 8135 if (!igb_check_for_rst(hw, vf)) 8136 igb_vf_reset_event(adapter, vf); 8137 8138 /* process any messages pending */ 8139 if (!igb_check_for_msg(hw, vf)) 8140 igb_rcv_msg_from_vf(adapter, vf); 8141 8142 /* process any acks */ 8143 if (!igb_check_for_ack(hw, vf)) 8144 igb_rcv_ack_from_vf(adapter, vf); 8145 } 8146 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 8147 } 8148 8149 /** 8150 * igb_set_uta - Set unicast filter table address 8151 * @adapter: board private structure 8152 * @set: boolean indicating if we are setting or clearing bits 8153 * 8154 * The unicast table address is a register array of 32-bit registers. 8155 * The table is meant to be used in a way similar to how the MTA is used 8156 * however due to certain limitations in the hardware it is necessary to 8157 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 8158 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 8159 **/ 8160 static void igb_set_uta(struct igb_adapter *adapter, bool set) 8161 { 8162 struct e1000_hw *hw = &adapter->hw; 8163 u32 uta = set ? ~0 : 0; 8164 int i; 8165 8166 /* we only need to do this if VMDq is enabled */ 8167 if (!adapter->vfs_allocated_count) 8168 return; 8169 8170 for (i = hw->mac.uta_reg_count; i--;) 8171 array_wr32(E1000_UTA, i, uta); 8172 } 8173 8174 /** 8175 * igb_intr_msi - Interrupt Handler 8176 * @irq: interrupt number 8177 * @data: pointer to a network interface device structure 8178 **/ 8179 static irqreturn_t igb_intr_msi(int irq, void *data) 8180 { 8181 struct igb_adapter *adapter = data; 8182 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8183 struct e1000_hw *hw = &adapter->hw; 8184 /* read ICR disables interrupts using IAM */ 8185 u32 icr = rd32(E1000_ICR); 8186 8187 igb_write_itr(q_vector); 8188 8189 if (icr & E1000_ICR_DRSTA) 8190 schedule_work(&adapter->reset_task); 8191 8192 if (icr & E1000_ICR_DOUTSYNC) { 8193 /* HW is reporting DMA is out of sync */ 8194 adapter->stats.doosync++; 8195 } 8196 8197 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8198 hw->mac.get_link_status = 1; 8199 if (!test_bit(__IGB_DOWN, &adapter->state)) 8200 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8201 } 8202 8203 if (icr & E1000_ICR_TS) 8204 igb_tsync_interrupt(adapter); 8205 8206 napi_schedule(&q_vector->napi); 8207 8208 return IRQ_HANDLED; 8209 } 8210 8211 /** 8212 * igb_intr - Legacy Interrupt Handler 8213 * @irq: interrupt number 8214 * @data: pointer to a network interface device structure 8215 **/ 8216 static irqreturn_t igb_intr(int irq, void *data) 8217 { 8218 struct igb_adapter *adapter = data; 8219 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8220 struct e1000_hw *hw = &adapter->hw; 8221 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 8222 * need for the IMC write 8223 */ 8224 u32 icr = rd32(E1000_ICR); 8225 8226 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 8227 * not set, then the adapter didn't send an interrupt 8228 */ 8229 if (!(icr & E1000_ICR_INT_ASSERTED)) 8230 return IRQ_NONE; 8231 8232 igb_write_itr(q_vector); 8233 8234 if (icr & E1000_ICR_DRSTA) 8235 schedule_work(&adapter->reset_task); 8236 8237 if (icr & E1000_ICR_DOUTSYNC) { 8238 /* HW is reporting DMA is out of sync */ 8239 adapter->stats.doosync++; 8240 } 8241 8242 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8243 hw->mac.get_link_status = 1; 8244 /* guard against interrupt when we're going down */ 8245 if (!test_bit(__IGB_DOWN, &adapter->state)) 8246 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8247 } 8248 8249 if (icr & E1000_ICR_TS) 8250 igb_tsync_interrupt(adapter); 8251 8252 napi_schedule(&q_vector->napi); 8253 8254 return IRQ_HANDLED; 8255 } 8256 8257 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 8258 { 8259 struct igb_adapter *adapter = q_vector->adapter; 8260 struct e1000_hw *hw = &adapter->hw; 8261 8262 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 8263 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 8264 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 8265 igb_set_itr(q_vector); 8266 else 8267 igb_update_ring_itr(q_vector); 8268 } 8269 8270 if (!test_bit(__IGB_DOWN, &adapter->state)) { 8271 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8272 wr32(E1000_EIMS, q_vector->eims_value); 8273 else 8274 igb_irq_enable(adapter); 8275 } 8276 } 8277 8278 /** 8279 * igb_poll - NAPI Rx polling callback 8280 * @napi: napi polling structure 8281 * @budget: count of how many packets we should handle 8282 **/ 8283 static int igb_poll(struct napi_struct *napi, int budget) 8284 { 8285 struct igb_q_vector *q_vector = container_of(napi, 8286 struct igb_q_vector, 8287 napi); 8288 struct xsk_buff_pool *xsk_pool; 8289 bool clean_complete = true; 8290 int work_done = 0; 8291 8292 #ifdef CONFIG_IGB_DCA 8293 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 8294 igb_update_dca(q_vector); 8295 #endif 8296 if (q_vector->tx.ring) 8297 clean_complete = igb_clean_tx_irq(q_vector, budget); 8298 8299 if (q_vector->rx.ring) { 8300 int cleaned; 8301 8302 xsk_pool = READ_ONCE(q_vector->rx.ring->xsk_pool); 8303 cleaned = xsk_pool ? 8304 igb_clean_rx_irq_zc(q_vector, xsk_pool, budget) : 8305 igb_clean_rx_irq(q_vector, budget); 8306 8307 work_done += cleaned; 8308 if (cleaned >= budget) 8309 clean_complete = false; 8310 } 8311 8312 /* If all work not completed, return budget and keep polling */ 8313 if (!clean_complete) 8314 return budget; 8315 8316 /* Exit the polling mode, but don't re-enable interrupts if stack might 8317 * poll us due to busy-polling 8318 */ 8319 if (likely(napi_complete_done(napi, work_done))) 8320 igb_ring_irq_enable(q_vector); 8321 8322 return work_done; 8323 } 8324 8325 /** 8326 * igb_clean_tx_irq - Reclaim resources after transmit completes 8327 * @q_vector: pointer to q_vector containing needed info 8328 * @napi_budget: Used to determine if we are in netpoll 8329 * 8330 * returns true if ring is completely cleaned 8331 **/ 8332 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 8333 { 8334 unsigned int total_bytes = 0, total_packets = 0; 8335 struct igb_adapter *adapter = q_vector->adapter; 8336 unsigned int budget = q_vector->tx.work_limit; 8337 struct igb_ring *tx_ring = q_vector->tx.ring; 8338 unsigned int i = tx_ring->next_to_clean; 8339 union e1000_adv_tx_desc *tx_desc; 8340 struct igb_tx_buffer *tx_buffer; 8341 struct xsk_buff_pool *xsk_pool; 8342 int cpu = smp_processor_id(); 8343 bool xsk_xmit_done = true; 8344 struct netdev_queue *nq; 8345 u32 xsk_frames = 0; 8346 8347 if (test_bit(__IGB_DOWN, &adapter->state)) 8348 return true; 8349 8350 tx_buffer = &tx_ring->tx_buffer_info[i]; 8351 tx_desc = IGB_TX_DESC(tx_ring, i); 8352 i -= tx_ring->count; 8353 8354 do { 8355 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 8356 8357 /* if next_to_watch is not set then there is no work pending */ 8358 if (!eop_desc) 8359 break; 8360 8361 /* prevent any other reads prior to eop_desc */ 8362 smp_rmb(); 8363 8364 /* if DD is not set pending work has not been completed */ 8365 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 8366 break; 8367 8368 /* clear next_to_watch to prevent false hangs */ 8369 tx_buffer->next_to_watch = NULL; 8370 8371 /* update the statistics for this packet */ 8372 total_bytes += tx_buffer->bytecount; 8373 total_packets += tx_buffer->gso_segs; 8374 8375 /* free the skb */ 8376 if (tx_buffer->type == IGB_TYPE_SKB) { 8377 napi_consume_skb(tx_buffer->skb, napi_budget); 8378 } else if (tx_buffer->type == IGB_TYPE_XDP) { 8379 xdp_return_frame(tx_buffer->xdpf); 8380 } else if (tx_buffer->type == IGB_TYPE_XSK) { 8381 xsk_frames++; 8382 goto skip_for_xsk; 8383 } 8384 8385 /* unmap skb header data */ 8386 dma_unmap_single(tx_ring->dev, 8387 dma_unmap_addr(tx_buffer, dma), 8388 dma_unmap_len(tx_buffer, len), 8389 DMA_TO_DEVICE); 8390 8391 /* clear tx_buffer data */ 8392 dma_unmap_len_set(tx_buffer, len, 0); 8393 8394 /* clear last DMA location and unmap remaining buffers */ 8395 while (tx_desc != eop_desc) { 8396 tx_buffer++; 8397 tx_desc++; 8398 i++; 8399 if (unlikely(!i)) { 8400 i -= tx_ring->count; 8401 tx_buffer = tx_ring->tx_buffer_info; 8402 tx_desc = IGB_TX_DESC(tx_ring, 0); 8403 } 8404 8405 /* unmap any remaining paged data */ 8406 if (dma_unmap_len(tx_buffer, len)) { 8407 dma_unmap_page(tx_ring->dev, 8408 dma_unmap_addr(tx_buffer, dma), 8409 dma_unmap_len(tx_buffer, len), 8410 DMA_TO_DEVICE); 8411 dma_unmap_len_set(tx_buffer, len, 0); 8412 } 8413 } 8414 8415 skip_for_xsk: 8416 /* move us one more past the eop_desc for start of next pkt */ 8417 tx_buffer++; 8418 tx_desc++; 8419 i++; 8420 if (unlikely(!i)) { 8421 i -= tx_ring->count; 8422 tx_buffer = tx_ring->tx_buffer_info; 8423 tx_desc = IGB_TX_DESC(tx_ring, 0); 8424 } 8425 8426 /* issue prefetch for next Tx descriptor */ 8427 prefetch(tx_desc); 8428 8429 /* update budget accounting */ 8430 budget--; 8431 } while (likely(budget)); 8432 8433 netdev_tx_completed_queue(txring_txq(tx_ring), 8434 total_packets, total_bytes); 8435 i += tx_ring->count; 8436 tx_ring->next_to_clean = i; 8437 u64_stats_update_begin(&tx_ring->tx_syncp); 8438 tx_ring->tx_stats.bytes += total_bytes; 8439 tx_ring->tx_stats.packets += total_packets; 8440 u64_stats_update_end(&tx_ring->tx_syncp); 8441 q_vector->tx.total_bytes += total_bytes; 8442 q_vector->tx.total_packets += total_packets; 8443 8444 xsk_pool = READ_ONCE(tx_ring->xsk_pool); 8445 if (xsk_pool) { 8446 if (xsk_frames) 8447 xsk_tx_completed(xsk_pool, xsk_frames); 8448 if (xsk_uses_need_wakeup(xsk_pool)) 8449 xsk_set_tx_need_wakeup(xsk_pool); 8450 8451 nq = txring_txq(tx_ring); 8452 __netif_tx_lock(nq, cpu); 8453 /* Avoid transmit queue timeout since we share it with the slow path */ 8454 txq_trans_cond_update(nq); 8455 xsk_xmit_done = igb_xmit_zc(tx_ring, xsk_pool); 8456 __netif_tx_unlock(nq); 8457 } 8458 8459 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 8460 struct e1000_hw *hw = &adapter->hw; 8461 8462 /* Detect a transmit hang in hardware, this serializes the 8463 * check with the clearing of time_stamp and movement of i 8464 */ 8465 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 8466 if (tx_buffer->next_to_watch && 8467 time_after(jiffies, tx_buffer->time_stamp + 8468 (adapter->tx_timeout_factor * HZ)) && 8469 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 8470 8471 /* detected Tx unit hang */ 8472 dev_err(tx_ring->dev, 8473 "Detected Tx Unit Hang\n" 8474 " Tx Queue <%d>\n" 8475 " TDH <%x>\n" 8476 " TDT <%x>\n" 8477 " next_to_use <%x>\n" 8478 " next_to_clean <%x>\n" 8479 "buffer_info[next_to_clean]\n" 8480 " time_stamp <%lx>\n" 8481 " next_to_watch <%p>\n" 8482 " jiffies <%lx>\n" 8483 " desc.status <%x>\n", 8484 tx_ring->queue_index, 8485 rd32(E1000_TDH(tx_ring->reg_idx)), 8486 readl(tx_ring->tail), 8487 tx_ring->next_to_use, 8488 tx_ring->next_to_clean, 8489 tx_buffer->time_stamp, 8490 tx_buffer->next_to_watch, 8491 jiffies, 8492 tx_buffer->next_to_watch->wb.status); 8493 netif_stop_subqueue(tx_ring->netdev, 8494 tx_ring->queue_index); 8495 8496 /* we are about to reset, no point in enabling stuff */ 8497 return true; 8498 } 8499 } 8500 8501 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 8502 if (unlikely(total_packets && 8503 netif_carrier_ok(tx_ring->netdev) && 8504 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 8505 /* Make sure that anybody stopping the queue after this 8506 * sees the new next_to_clean. 8507 */ 8508 smp_mb(); 8509 if (__netif_subqueue_stopped(tx_ring->netdev, 8510 tx_ring->queue_index) && 8511 !(test_bit(__IGB_DOWN, &adapter->state))) { 8512 netif_wake_subqueue(tx_ring->netdev, 8513 tx_ring->queue_index); 8514 8515 u64_stats_update_begin(&tx_ring->tx_syncp); 8516 tx_ring->tx_stats.restart_queue++; 8517 u64_stats_update_end(&tx_ring->tx_syncp); 8518 } 8519 } 8520 8521 return !!budget && xsk_xmit_done; 8522 } 8523 8524 /** 8525 * igb_reuse_rx_page - page flip buffer and store it back on the ring 8526 * @rx_ring: rx descriptor ring to store buffers on 8527 * @old_buff: donor buffer to have page reused 8528 * 8529 * Synchronizes page for reuse by the adapter 8530 **/ 8531 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 8532 struct igb_rx_buffer *old_buff) 8533 { 8534 struct igb_rx_buffer *new_buff; 8535 u16 nta = rx_ring->next_to_alloc; 8536 8537 new_buff = &rx_ring->rx_buffer_info[nta]; 8538 8539 /* update, and store next to alloc */ 8540 nta++; 8541 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 8542 8543 /* Transfer page from old buffer to new buffer. 8544 * Move each member individually to avoid possible store 8545 * forwarding stalls. 8546 */ 8547 new_buff->dma = old_buff->dma; 8548 new_buff->page = old_buff->page; 8549 new_buff->page_offset = old_buff->page_offset; 8550 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 8551 } 8552 8553 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 8554 int rx_buf_pgcnt) 8555 { 8556 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 8557 struct page *page = rx_buffer->page; 8558 8559 /* avoid re-using remote and pfmemalloc pages */ 8560 if (!dev_page_is_reusable(page)) 8561 return false; 8562 8563 #if (PAGE_SIZE < 8192) 8564 /* if we are only owner of page we can reuse it */ 8565 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1)) 8566 return false; 8567 #else 8568 #define IGB_LAST_OFFSET \ 8569 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 8570 8571 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 8572 return false; 8573 #endif 8574 8575 /* If we have drained the page fragment pool we need to update 8576 * the pagecnt_bias and page count so that we fully restock the 8577 * number of references the driver holds. 8578 */ 8579 if (unlikely(pagecnt_bias == 1)) { 8580 page_ref_add(page, USHRT_MAX - 1); 8581 rx_buffer->pagecnt_bias = USHRT_MAX; 8582 } 8583 8584 return true; 8585 } 8586 8587 /** 8588 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 8589 * @rx_ring: rx descriptor ring to transact packets on 8590 * @rx_buffer: buffer containing page to add 8591 * @skb: sk_buff to place the data into 8592 * @size: size of buffer to be added 8593 * 8594 * This function will add the data contained in rx_buffer->page to the skb. 8595 **/ 8596 static void igb_add_rx_frag(struct igb_ring *rx_ring, 8597 struct igb_rx_buffer *rx_buffer, 8598 struct sk_buff *skb, 8599 unsigned int size) 8600 { 8601 #if (PAGE_SIZE < 8192) 8602 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8603 #else 8604 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8605 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8606 SKB_DATA_ALIGN(size); 8607 #endif 8608 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8609 rx_buffer->page_offset, size, truesize); 8610 #if (PAGE_SIZE < 8192) 8611 rx_buffer->page_offset ^= truesize; 8612 #else 8613 rx_buffer->page_offset += truesize; 8614 #endif 8615 } 8616 8617 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8618 struct igb_rx_buffer *rx_buffer, 8619 struct xdp_buff *xdp, 8620 ktime_t timestamp) 8621 { 8622 #if (PAGE_SIZE < 8192) 8623 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8624 #else 8625 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 8626 xdp->data_hard_start); 8627 #endif 8628 unsigned int size = xdp->data_end - xdp->data; 8629 unsigned int headlen; 8630 struct sk_buff *skb; 8631 8632 /* prefetch first cache line of first page */ 8633 net_prefetch(xdp->data); 8634 8635 /* allocate a skb to store the frags */ 8636 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8637 if (unlikely(!skb)) 8638 return NULL; 8639 8640 if (timestamp) 8641 skb_hwtstamps(skb)->hwtstamp = timestamp; 8642 8643 /* Determine available headroom for copy */ 8644 headlen = size; 8645 if (headlen > IGB_RX_HDR_LEN) 8646 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN); 8647 8648 /* align pull length to size of long to optimize memcpy performance */ 8649 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long))); 8650 8651 /* update all of the pointers */ 8652 size -= headlen; 8653 if (size) { 8654 skb_add_rx_frag(skb, 0, rx_buffer->page, 8655 (xdp->data + headlen) - page_address(rx_buffer->page), 8656 size, truesize); 8657 #if (PAGE_SIZE < 8192) 8658 rx_buffer->page_offset ^= truesize; 8659 #else 8660 rx_buffer->page_offset += truesize; 8661 #endif 8662 } else { 8663 rx_buffer->pagecnt_bias++; 8664 } 8665 8666 return skb; 8667 } 8668 8669 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8670 struct igb_rx_buffer *rx_buffer, 8671 struct xdp_buff *xdp, 8672 ktime_t timestamp) 8673 { 8674 #if (PAGE_SIZE < 8192) 8675 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8676 #else 8677 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8678 SKB_DATA_ALIGN(xdp->data_end - 8679 xdp->data_hard_start); 8680 #endif 8681 unsigned int metasize = xdp->data - xdp->data_meta; 8682 struct sk_buff *skb; 8683 8684 /* prefetch first cache line of first page */ 8685 net_prefetch(xdp->data_meta); 8686 8687 /* build an skb around the page buffer */ 8688 skb = napi_build_skb(xdp->data_hard_start, truesize); 8689 if (unlikely(!skb)) 8690 return NULL; 8691 8692 /* update pointers within the skb to store the data */ 8693 skb_reserve(skb, xdp->data - xdp->data_hard_start); 8694 __skb_put(skb, xdp->data_end - xdp->data); 8695 8696 if (metasize) 8697 skb_metadata_set(skb, metasize); 8698 8699 if (timestamp) 8700 skb_hwtstamps(skb)->hwtstamp = timestamp; 8701 8702 /* update buffer offset */ 8703 #if (PAGE_SIZE < 8192) 8704 rx_buffer->page_offset ^= truesize; 8705 #else 8706 rx_buffer->page_offset += truesize; 8707 #endif 8708 8709 return skb; 8710 } 8711 8712 static int igb_run_xdp(struct igb_adapter *adapter, struct igb_ring *rx_ring, 8713 struct xdp_buff *xdp) 8714 { 8715 int err, result = IGB_XDP_PASS; 8716 struct bpf_prog *xdp_prog; 8717 u32 act; 8718 8719 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 8720 8721 if (!xdp_prog) 8722 goto xdp_out; 8723 8724 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 8725 8726 act = bpf_prog_run_xdp(xdp_prog, xdp); 8727 switch (act) { 8728 case XDP_PASS: 8729 break; 8730 case XDP_TX: 8731 result = igb_xdp_xmit_back(adapter, xdp); 8732 if (result == IGB_XDP_CONSUMED) 8733 goto out_failure; 8734 break; 8735 case XDP_REDIRECT: 8736 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 8737 if (err) 8738 goto out_failure; 8739 result = IGB_XDP_REDIR; 8740 break; 8741 default: 8742 bpf_warn_invalid_xdp_action(adapter->netdev, xdp_prog, act); 8743 fallthrough; 8744 case XDP_ABORTED: 8745 out_failure: 8746 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 8747 fallthrough; 8748 case XDP_DROP: 8749 result = IGB_XDP_CONSUMED; 8750 break; 8751 } 8752 xdp_out: 8753 return result; 8754 } 8755 8756 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring, 8757 unsigned int size) 8758 { 8759 unsigned int truesize; 8760 8761 #if (PAGE_SIZE < 8192) 8762 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 8763 #else 8764 truesize = ring_uses_build_skb(rx_ring) ? 8765 SKB_DATA_ALIGN(IGB_SKB_PAD + size) + 8766 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 8767 SKB_DATA_ALIGN(size); 8768 #endif 8769 return truesize; 8770 } 8771 8772 static void igb_rx_buffer_flip(struct igb_ring *rx_ring, 8773 struct igb_rx_buffer *rx_buffer, 8774 unsigned int size) 8775 { 8776 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size); 8777 #if (PAGE_SIZE < 8192) 8778 rx_buffer->page_offset ^= truesize; 8779 #else 8780 rx_buffer->page_offset += truesize; 8781 #endif 8782 } 8783 8784 static inline void igb_rx_checksum(struct igb_ring *ring, 8785 union e1000_adv_rx_desc *rx_desc, 8786 struct sk_buff *skb) 8787 { 8788 skb_checksum_none_assert(skb); 8789 8790 /* Ignore Checksum bit is set */ 8791 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8792 return; 8793 8794 /* Rx checksum disabled via ethtool */ 8795 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8796 return; 8797 8798 /* TCP/UDP checksum error bit is set */ 8799 if (igb_test_staterr(rx_desc, 8800 E1000_RXDEXT_STATERR_TCPE | 8801 E1000_RXDEXT_STATERR_IPE)) { 8802 /* work around errata with sctp packets where the TCPE aka 8803 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8804 * packets, (aka let the stack check the crc32c) 8805 */ 8806 if (!((skb->len == 60) && 8807 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8808 u64_stats_update_begin(&ring->rx_syncp); 8809 ring->rx_stats.csum_err++; 8810 u64_stats_update_end(&ring->rx_syncp); 8811 } 8812 /* let the stack verify checksum errors */ 8813 return; 8814 } 8815 /* It must be a TCP or UDP packet with a valid checksum */ 8816 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8817 E1000_RXD_STAT_UDPCS)) 8818 skb->ip_summed = CHECKSUM_UNNECESSARY; 8819 8820 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8821 le32_to_cpu(rx_desc->wb.upper.status_error)); 8822 } 8823 8824 static inline void igb_rx_hash(struct igb_ring *ring, 8825 union e1000_adv_rx_desc *rx_desc, 8826 struct sk_buff *skb) 8827 { 8828 if (ring->netdev->features & NETIF_F_RXHASH) 8829 skb_set_hash(skb, 8830 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8831 PKT_HASH_TYPE_L3); 8832 } 8833 8834 /** 8835 * igb_is_non_eop - process handling of non-EOP buffers 8836 * @rx_ring: Rx ring being processed 8837 * @rx_desc: Rx descriptor for current buffer 8838 * 8839 * This function updates next to clean. If the buffer is an EOP buffer 8840 * this function exits returning false, otherwise it will place the 8841 * sk_buff in the next buffer to be chained and return true indicating 8842 * that this is in fact a non-EOP buffer. 8843 **/ 8844 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8845 union e1000_adv_rx_desc *rx_desc) 8846 { 8847 u32 ntc = rx_ring->next_to_clean + 1; 8848 8849 /* fetch, update, and store next to clean */ 8850 ntc = (ntc < rx_ring->count) ? ntc : 0; 8851 rx_ring->next_to_clean = ntc; 8852 8853 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8854 8855 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8856 return false; 8857 8858 return true; 8859 } 8860 8861 /** 8862 * igb_cleanup_headers - Correct corrupted or empty headers 8863 * @rx_ring: rx descriptor ring packet is being transacted on 8864 * @rx_desc: pointer to the EOP Rx descriptor 8865 * @skb: pointer to current skb being fixed 8866 * 8867 * Address the case where we are pulling data in on pages only 8868 * and as such no data is present in the skb header. 8869 * 8870 * In addition if skb is not at least 60 bytes we need to pad it so that 8871 * it is large enough to qualify as a valid Ethernet frame. 8872 * 8873 * Returns true if an error was encountered and skb was freed. 8874 **/ 8875 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8876 union e1000_adv_rx_desc *rx_desc, 8877 struct sk_buff *skb) 8878 { 8879 if (unlikely((igb_test_staterr(rx_desc, 8880 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8881 struct net_device *netdev = rx_ring->netdev; 8882 if (!(netdev->features & NETIF_F_RXALL)) { 8883 dev_kfree_skb_any(skb); 8884 return true; 8885 } 8886 } 8887 8888 /* if eth_skb_pad returns an error the skb was freed */ 8889 if (eth_skb_pad(skb)) 8890 return true; 8891 8892 return false; 8893 } 8894 8895 /** 8896 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8897 * @rx_ring: rx descriptor ring packet is being transacted on 8898 * @rx_desc: pointer to the EOP Rx descriptor 8899 * @skb: pointer to current skb being populated 8900 * 8901 * This function checks the ring, descriptor, and packet information in 8902 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8903 * other fields within the skb. 8904 **/ 8905 void igb_process_skb_fields(struct igb_ring *rx_ring, 8906 union e1000_adv_rx_desc *rx_desc, 8907 struct sk_buff *skb) 8908 { 8909 struct net_device *dev = rx_ring->netdev; 8910 8911 igb_rx_hash(rx_ring, rx_desc, skb); 8912 8913 igb_rx_checksum(rx_ring, rx_desc, skb); 8914 8915 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8916 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8917 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8918 8919 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8920 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8921 u16 vid; 8922 8923 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8924 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8925 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan); 8926 else 8927 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8928 8929 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8930 } 8931 8932 skb_record_rx_queue(skb, rx_ring->queue_index); 8933 8934 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8935 } 8936 8937 static unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8938 { 8939 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8940 } 8941 8942 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8943 const unsigned int size, int *rx_buf_pgcnt) 8944 { 8945 struct igb_rx_buffer *rx_buffer; 8946 8947 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8948 *rx_buf_pgcnt = 8949 #if (PAGE_SIZE < 8192) 8950 page_count(rx_buffer->page); 8951 #else 8952 0; 8953 #endif 8954 prefetchw(rx_buffer->page); 8955 8956 /* we are reusing so sync this buffer for CPU use */ 8957 dma_sync_single_range_for_cpu(rx_ring->dev, 8958 rx_buffer->dma, 8959 rx_buffer->page_offset, 8960 size, 8961 DMA_FROM_DEVICE); 8962 8963 rx_buffer->pagecnt_bias--; 8964 8965 return rx_buffer; 8966 } 8967 8968 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8969 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt) 8970 { 8971 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) { 8972 /* hand second half of page back to the ring */ 8973 igb_reuse_rx_page(rx_ring, rx_buffer); 8974 } else { 8975 /* We are not reusing the buffer so unmap it and free 8976 * any references we are holding to it 8977 */ 8978 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8979 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8980 IGB_RX_DMA_ATTR); 8981 __page_frag_cache_drain(rx_buffer->page, 8982 rx_buffer->pagecnt_bias); 8983 } 8984 8985 /* clear contents of rx_buffer */ 8986 rx_buffer->page = NULL; 8987 } 8988 8989 void igb_finalize_xdp(struct igb_adapter *adapter, unsigned int status) 8990 { 8991 int cpu = smp_processor_id(); 8992 struct netdev_queue *nq; 8993 8994 if (status & IGB_XDP_REDIR) 8995 xdp_do_flush(); 8996 8997 if (status & IGB_XDP_TX) { 8998 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter); 8999 9000 nq = txring_txq(tx_ring); 9001 __netif_tx_lock(nq, cpu); 9002 igb_xdp_ring_update_tail(tx_ring); 9003 __netif_tx_unlock(nq); 9004 } 9005 } 9006 9007 void igb_update_rx_stats(struct igb_q_vector *q_vector, unsigned int packets, 9008 unsigned int bytes) 9009 { 9010 struct igb_ring *ring = q_vector->rx.ring; 9011 9012 u64_stats_update_begin(&ring->rx_syncp); 9013 ring->rx_stats.packets += packets; 9014 ring->rx_stats.bytes += bytes; 9015 u64_stats_update_end(&ring->rx_syncp); 9016 9017 q_vector->rx.total_packets += packets; 9018 q_vector->rx.total_bytes += bytes; 9019 } 9020 9021 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 9022 { 9023 unsigned int total_bytes = 0, total_packets = 0; 9024 struct igb_adapter *adapter = q_vector->adapter; 9025 struct igb_ring *rx_ring = q_vector->rx.ring; 9026 u16 cleaned_count = igb_desc_unused(rx_ring); 9027 struct sk_buff *skb = rx_ring->skb; 9028 unsigned int xdp_xmit = 0; 9029 struct xdp_buff xdp; 9030 u32 frame_sz = 0; 9031 int rx_buf_pgcnt; 9032 int xdp_res = 0; 9033 9034 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 9035 #if (PAGE_SIZE < 8192) 9036 frame_sz = igb_rx_frame_truesize(rx_ring, 0); 9037 #endif 9038 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 9039 9040 while (likely(total_packets < budget)) { 9041 union e1000_adv_rx_desc *rx_desc; 9042 struct igb_rx_buffer *rx_buffer; 9043 ktime_t timestamp = 0; 9044 int pkt_offset = 0; 9045 unsigned int size; 9046 void *pktbuf; 9047 9048 /* return some buffers to hardware, one at a time is too slow */ 9049 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 9050 igb_alloc_rx_buffers(rx_ring, cleaned_count); 9051 cleaned_count = 0; 9052 } 9053 9054 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 9055 size = le16_to_cpu(rx_desc->wb.upper.length); 9056 if (!size) 9057 break; 9058 9059 /* This memory barrier is needed to keep us from reading 9060 * any other fields out of the rx_desc until we know the 9061 * descriptor has been written back 9062 */ 9063 dma_rmb(); 9064 9065 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt); 9066 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset; 9067 9068 /* pull rx packet timestamp if available and valid */ 9069 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 9070 int ts_hdr_len; 9071 9072 ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector, 9073 pktbuf, ×tamp); 9074 9075 pkt_offset += ts_hdr_len; 9076 size -= ts_hdr_len; 9077 } 9078 9079 /* retrieve a buffer from the ring */ 9080 if (!skb) { 9081 unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring); 9082 unsigned int offset = pkt_offset + igb_rx_offset(rx_ring); 9083 9084 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 9085 xdp_buff_clear_frags_flag(&xdp); 9086 #if (PAGE_SIZE > 4096) 9087 /* At larger PAGE_SIZE, frame_sz depend on len size */ 9088 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size); 9089 #endif 9090 xdp_res = igb_run_xdp(adapter, rx_ring, &xdp); 9091 } 9092 9093 if (xdp_res) { 9094 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) { 9095 xdp_xmit |= xdp_res; 9096 igb_rx_buffer_flip(rx_ring, rx_buffer, size); 9097 } else { 9098 rx_buffer->pagecnt_bias++; 9099 } 9100 total_packets++; 9101 total_bytes += size; 9102 } else if (skb) 9103 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 9104 else if (ring_uses_build_skb(rx_ring)) 9105 skb = igb_build_skb(rx_ring, rx_buffer, &xdp, 9106 timestamp); 9107 else 9108 skb = igb_construct_skb(rx_ring, rx_buffer, 9109 &xdp, timestamp); 9110 9111 /* exit if we failed to retrieve a buffer */ 9112 if (!xdp_res && !skb) { 9113 rx_ring->rx_stats.alloc_failed++; 9114 rx_buffer->pagecnt_bias++; 9115 set_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 9116 break; 9117 } 9118 9119 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt); 9120 cleaned_count++; 9121 9122 /* fetch next buffer in frame if non-eop */ 9123 if (igb_is_non_eop(rx_ring, rx_desc)) 9124 continue; 9125 9126 /* verify the packet layout is correct */ 9127 if (xdp_res || igb_cleanup_headers(rx_ring, rx_desc, skb)) { 9128 skb = NULL; 9129 continue; 9130 } 9131 9132 /* probably a little skewed due to removing CRC */ 9133 total_bytes += skb->len; 9134 9135 /* populate checksum, timestamp, VLAN, and protocol */ 9136 igb_process_skb_fields(rx_ring, rx_desc, skb); 9137 9138 napi_gro_receive(&q_vector->napi, skb); 9139 9140 /* reset skb pointer */ 9141 skb = NULL; 9142 9143 /* update budget accounting */ 9144 total_packets++; 9145 } 9146 9147 /* place incomplete frames back on ring for completion */ 9148 rx_ring->skb = skb; 9149 9150 if (xdp_xmit) 9151 igb_finalize_xdp(adapter, xdp_xmit); 9152 9153 igb_update_rx_stats(q_vector, total_packets, total_bytes); 9154 9155 if (cleaned_count) 9156 igb_alloc_rx_buffers(rx_ring, cleaned_count); 9157 9158 return total_packets; 9159 } 9160 9161 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 9162 struct igb_rx_buffer *bi) 9163 { 9164 struct page *page = bi->page; 9165 dma_addr_t dma; 9166 9167 /* since we are recycling buffers we should seldom need to alloc */ 9168 if (likely(page)) 9169 return true; 9170 9171 /* alloc new page for storage */ 9172 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 9173 if (unlikely(!page)) { 9174 rx_ring->rx_stats.alloc_failed++; 9175 set_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 9176 return false; 9177 } 9178 9179 /* map page for use */ 9180 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 9181 igb_rx_pg_size(rx_ring), 9182 DMA_FROM_DEVICE, 9183 IGB_RX_DMA_ATTR); 9184 9185 /* if mapping failed free memory back to system since 9186 * there isn't much point in holding memory we can't use 9187 */ 9188 if (dma_mapping_error(rx_ring->dev, dma)) { 9189 __free_pages(page, igb_rx_pg_order(rx_ring)); 9190 9191 rx_ring->rx_stats.alloc_failed++; 9192 set_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 9193 return false; 9194 } 9195 9196 bi->dma = dma; 9197 bi->page = page; 9198 bi->page_offset = igb_rx_offset(rx_ring); 9199 page_ref_add(page, USHRT_MAX - 1); 9200 bi->pagecnt_bias = USHRT_MAX; 9201 9202 return true; 9203 } 9204 9205 /** 9206 * igb_alloc_rx_buffers - Replace used receive buffers 9207 * @rx_ring: rx descriptor ring to allocate new receive buffers 9208 * @cleaned_count: count of buffers to allocate 9209 **/ 9210 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 9211 { 9212 union e1000_adv_rx_desc *rx_desc; 9213 struct igb_rx_buffer *bi; 9214 u16 i = rx_ring->next_to_use; 9215 u16 bufsz; 9216 9217 /* nothing to do */ 9218 if (!cleaned_count) 9219 return; 9220 9221 rx_desc = IGB_RX_DESC(rx_ring, i); 9222 bi = &rx_ring->rx_buffer_info[i]; 9223 i -= rx_ring->count; 9224 9225 bufsz = igb_rx_bufsz(rx_ring); 9226 9227 do { 9228 if (!igb_alloc_mapped_page(rx_ring, bi)) 9229 break; 9230 9231 /* sync the buffer for use by the device */ 9232 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 9233 bi->page_offset, bufsz, 9234 DMA_FROM_DEVICE); 9235 9236 /* Refresh the desc even if buffer_addrs didn't change 9237 * because each write-back erases this info. 9238 */ 9239 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 9240 9241 rx_desc++; 9242 bi++; 9243 i++; 9244 if (unlikely(!i)) { 9245 rx_desc = IGB_RX_DESC(rx_ring, 0); 9246 bi = rx_ring->rx_buffer_info; 9247 i -= rx_ring->count; 9248 } 9249 9250 /* clear the length for the next_to_use descriptor */ 9251 rx_desc->wb.upper.length = 0; 9252 9253 cleaned_count--; 9254 } while (cleaned_count); 9255 9256 i += rx_ring->count; 9257 9258 if (rx_ring->next_to_use != i) { 9259 /* record the next descriptor to use */ 9260 rx_ring->next_to_use = i; 9261 9262 /* update next to alloc since we have filled the ring */ 9263 rx_ring->next_to_alloc = i; 9264 9265 /* Force memory writes to complete before letting h/w 9266 * know there are new descriptors to fetch. (Only 9267 * applicable for weak-ordered memory model archs, 9268 * such as IA-64). 9269 */ 9270 dma_wmb(); 9271 writel(i, rx_ring->tail); 9272 } 9273 } 9274 9275 /** 9276 * igb_mii_ioctl - 9277 * @netdev: pointer to netdev struct 9278 * @ifr: interface structure 9279 * @cmd: ioctl command to execute 9280 **/ 9281 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9282 { 9283 struct igb_adapter *adapter = netdev_priv(netdev); 9284 struct mii_ioctl_data *data = if_mii(ifr); 9285 9286 if (adapter->hw.phy.media_type != e1000_media_type_copper) 9287 return -EOPNOTSUPP; 9288 9289 switch (cmd) { 9290 case SIOCGMIIPHY: 9291 data->phy_id = adapter->hw.phy.addr; 9292 break; 9293 case SIOCGMIIREG: 9294 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9295 &data->val_out)) 9296 return -EIO; 9297 break; 9298 case SIOCSMIIREG: 9299 if (igb_write_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9300 data->val_in)) 9301 return -EIO; 9302 break; 9303 default: 9304 return -EOPNOTSUPP; 9305 } 9306 return 0; 9307 } 9308 9309 /** 9310 * igb_ioctl - 9311 * @netdev: pointer to netdev struct 9312 * @ifr: interface structure 9313 * @cmd: ioctl command to execute 9314 **/ 9315 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9316 { 9317 switch (cmd) { 9318 case SIOCGMIIPHY: 9319 case SIOCGMIIREG: 9320 case SIOCSMIIREG: 9321 return igb_mii_ioctl(netdev, ifr, cmd); 9322 default: 9323 return -EOPNOTSUPP; 9324 } 9325 } 9326 9327 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9328 { 9329 struct igb_adapter *adapter = hw->back; 9330 9331 pci_read_config_word(adapter->pdev, reg, value); 9332 } 9333 9334 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9335 { 9336 struct igb_adapter *adapter = hw->back; 9337 9338 pci_write_config_word(adapter->pdev, reg, *value); 9339 } 9340 9341 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9342 { 9343 struct igb_adapter *adapter = hw->back; 9344 9345 if (pcie_capability_read_word(adapter->pdev, reg, value)) 9346 return -E1000_ERR_CONFIG; 9347 9348 return 0; 9349 } 9350 9351 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9352 { 9353 struct igb_adapter *adapter = hw->back; 9354 9355 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 9356 return -E1000_ERR_CONFIG; 9357 9358 return 0; 9359 } 9360 9361 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 9362 { 9363 struct igb_adapter *adapter = netdev_priv(netdev); 9364 struct e1000_hw *hw = &adapter->hw; 9365 u32 ctrl, rctl; 9366 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 9367 9368 if (enable) { 9369 /* enable VLAN tag insert/strip */ 9370 ctrl = rd32(E1000_CTRL); 9371 ctrl |= E1000_CTRL_VME; 9372 wr32(E1000_CTRL, ctrl); 9373 9374 /* Disable CFI check */ 9375 rctl = rd32(E1000_RCTL); 9376 rctl &= ~E1000_RCTL_CFIEN; 9377 wr32(E1000_RCTL, rctl); 9378 } else { 9379 /* disable VLAN tag insert/strip */ 9380 ctrl = rd32(E1000_CTRL); 9381 ctrl &= ~E1000_CTRL_VME; 9382 wr32(E1000_CTRL, ctrl); 9383 } 9384 9385 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 9386 } 9387 9388 static int igb_vlan_rx_add_vid(struct net_device *netdev, 9389 __be16 proto, u16 vid) 9390 { 9391 struct igb_adapter *adapter = netdev_priv(netdev); 9392 struct e1000_hw *hw = &adapter->hw; 9393 int pf_id = adapter->vfs_allocated_count; 9394 9395 /* add the filter since PF can receive vlans w/o entry in vlvf */ 9396 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9397 igb_vfta_set(hw, vid, pf_id, true, !!vid); 9398 9399 set_bit(vid, adapter->active_vlans); 9400 9401 return 0; 9402 } 9403 9404 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 9405 __be16 proto, u16 vid) 9406 { 9407 struct igb_adapter *adapter = netdev_priv(netdev); 9408 int pf_id = adapter->vfs_allocated_count; 9409 struct e1000_hw *hw = &adapter->hw; 9410 9411 /* remove VID from filter table */ 9412 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9413 igb_vfta_set(hw, vid, pf_id, false, true); 9414 9415 clear_bit(vid, adapter->active_vlans); 9416 9417 return 0; 9418 } 9419 9420 static void igb_restore_vlan(struct igb_adapter *adapter) 9421 { 9422 u16 vid = 1; 9423 9424 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 9425 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 9426 9427 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 9428 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 9429 } 9430 9431 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 9432 { 9433 struct pci_dev *pdev = adapter->pdev; 9434 struct e1000_mac_info *mac = &adapter->hw.mac; 9435 9436 mac->autoneg = 0; 9437 9438 /* Make sure dplx is at most 1 bit and lsb of speed is not set 9439 * for the switch() below to work 9440 */ 9441 if ((spd & 1) || (dplx & ~1)) 9442 goto err_inval; 9443 9444 /* Fiber NIC's only allow 1000 gbps Full duplex 9445 * and 100Mbps Full duplex for 100baseFx sfp 9446 */ 9447 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 9448 switch (spd + dplx) { 9449 case SPEED_10 + DUPLEX_HALF: 9450 case SPEED_10 + DUPLEX_FULL: 9451 case SPEED_100 + DUPLEX_HALF: 9452 goto err_inval; 9453 default: 9454 break; 9455 } 9456 } 9457 9458 switch (spd + dplx) { 9459 case SPEED_10 + DUPLEX_HALF: 9460 mac->forced_speed_duplex = ADVERTISE_10_HALF; 9461 break; 9462 case SPEED_10 + DUPLEX_FULL: 9463 mac->forced_speed_duplex = ADVERTISE_10_FULL; 9464 break; 9465 case SPEED_100 + DUPLEX_HALF: 9466 mac->forced_speed_duplex = ADVERTISE_100_HALF; 9467 break; 9468 case SPEED_100 + DUPLEX_FULL: 9469 mac->forced_speed_duplex = ADVERTISE_100_FULL; 9470 break; 9471 case SPEED_1000 + DUPLEX_FULL: 9472 mac->autoneg = 1; 9473 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 9474 break; 9475 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 9476 default: 9477 goto err_inval; 9478 } 9479 9480 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 9481 adapter->hw.phy.mdix = AUTO_ALL_MODES; 9482 9483 return 0; 9484 9485 err_inval: 9486 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 9487 return -EINVAL; 9488 } 9489 9490 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 9491 bool runtime) 9492 { 9493 struct net_device *netdev = pci_get_drvdata(pdev); 9494 struct igb_adapter *adapter = netdev_priv(netdev); 9495 struct e1000_hw *hw = &adapter->hw; 9496 u32 ctrl, rctl, status; 9497 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 9498 bool wake; 9499 9500 rtnl_lock(); 9501 netif_device_detach(netdev); 9502 9503 if (netif_running(netdev)) 9504 __igb_close(netdev, true); 9505 9506 igb_ptp_suspend(adapter); 9507 9508 igb_clear_interrupt_scheme(adapter); 9509 rtnl_unlock(); 9510 9511 status = rd32(E1000_STATUS); 9512 if (status & E1000_STATUS_LU) 9513 wufc &= ~E1000_WUFC_LNKC; 9514 9515 if (wufc) { 9516 igb_setup_rctl(adapter); 9517 igb_set_rx_mode(netdev); 9518 9519 /* turn on all-multi mode if wake on multicast is enabled */ 9520 if (wufc & E1000_WUFC_MC) { 9521 rctl = rd32(E1000_RCTL); 9522 rctl |= E1000_RCTL_MPE; 9523 wr32(E1000_RCTL, rctl); 9524 } 9525 9526 ctrl = rd32(E1000_CTRL); 9527 ctrl |= E1000_CTRL_ADVD3WUC; 9528 wr32(E1000_CTRL, ctrl); 9529 9530 /* Allow time for pending master requests to run */ 9531 igb_disable_pcie_master(hw); 9532 9533 wr32(E1000_WUC, E1000_WUC_PME_EN); 9534 wr32(E1000_WUFC, wufc); 9535 } else { 9536 wr32(E1000_WUC, 0); 9537 wr32(E1000_WUFC, 0); 9538 } 9539 9540 wake = wufc || adapter->en_mng_pt; 9541 if (!wake) 9542 igb_power_down_link(adapter); 9543 else 9544 igb_power_up_link(adapter); 9545 9546 if (enable_wake) 9547 *enable_wake = wake; 9548 9549 /* Release control of h/w to f/w. If f/w is AMT enabled, this 9550 * would have already happened in close and is redundant. 9551 */ 9552 igb_release_hw_control(adapter); 9553 9554 pci_disable_device(pdev); 9555 9556 return 0; 9557 } 9558 9559 static void igb_deliver_wake_packet(struct net_device *netdev) 9560 { 9561 struct igb_adapter *adapter = netdev_priv(netdev); 9562 struct e1000_hw *hw = &adapter->hw; 9563 struct sk_buff *skb; 9564 u32 wupl; 9565 9566 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 9567 9568 /* WUPM stores only the first 128 bytes of the wake packet. 9569 * Read the packet only if we have the whole thing. 9570 */ 9571 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 9572 return; 9573 9574 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 9575 if (!skb) 9576 return; 9577 9578 skb_put(skb, wupl); 9579 9580 /* Ensure reads are 32-bit aligned */ 9581 wupl = roundup(wupl, 4); 9582 9583 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 9584 9585 skb->protocol = eth_type_trans(skb, netdev); 9586 netif_rx(skb); 9587 } 9588 9589 static int igb_suspend(struct device *dev) 9590 { 9591 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 9592 } 9593 9594 static int __igb_resume(struct device *dev, bool rpm) 9595 { 9596 struct pci_dev *pdev = to_pci_dev(dev); 9597 struct net_device *netdev = pci_get_drvdata(pdev); 9598 struct igb_adapter *adapter = netdev_priv(netdev); 9599 struct e1000_hw *hw = &adapter->hw; 9600 u32 err, val; 9601 9602 pci_set_power_state(pdev, PCI_D0); 9603 pci_restore_state(pdev); 9604 pci_save_state(pdev); 9605 9606 if (!pci_device_is_present(pdev)) 9607 return -ENODEV; 9608 err = pci_enable_device_mem(pdev); 9609 if (err) { 9610 dev_err(&pdev->dev, 9611 "igb: Cannot enable PCI device from suspend\n"); 9612 return err; 9613 } 9614 pci_set_master(pdev); 9615 9616 pci_enable_wake(pdev, PCI_D3hot, 0); 9617 pci_enable_wake(pdev, PCI_D3cold, 0); 9618 9619 if (igb_init_interrupt_scheme(adapter, true)) { 9620 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9621 return -ENOMEM; 9622 } 9623 9624 igb_reset(adapter); 9625 9626 /* let the f/w know that the h/w is now under the control of the 9627 * driver. 9628 */ 9629 igb_get_hw_control(adapter); 9630 9631 val = rd32(E1000_WUS); 9632 if (val & WAKE_PKT_WUS) 9633 igb_deliver_wake_packet(netdev); 9634 9635 wr32(E1000_WUS, ~0); 9636 9637 if (!rpm) 9638 rtnl_lock(); 9639 if (!err && netif_running(netdev)) 9640 err = __igb_open(netdev, true); 9641 9642 if (!err) 9643 netif_device_attach(netdev); 9644 if (!rpm) 9645 rtnl_unlock(); 9646 9647 return err; 9648 } 9649 9650 static int igb_resume(struct device *dev) 9651 { 9652 return __igb_resume(dev, false); 9653 } 9654 9655 static int igb_runtime_idle(struct device *dev) 9656 { 9657 struct net_device *netdev = dev_get_drvdata(dev); 9658 struct igb_adapter *adapter = netdev_priv(netdev); 9659 9660 if (!igb_has_link(adapter)) 9661 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 9662 9663 return -EBUSY; 9664 } 9665 9666 static int igb_runtime_suspend(struct device *dev) 9667 { 9668 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 9669 } 9670 9671 static int igb_runtime_resume(struct device *dev) 9672 { 9673 return __igb_resume(dev, true); 9674 } 9675 9676 static void igb_shutdown(struct pci_dev *pdev) 9677 { 9678 bool wake; 9679 9680 __igb_shutdown(pdev, &wake, 0); 9681 9682 if (system_state == SYSTEM_POWER_OFF) { 9683 pci_wake_from_d3(pdev, wake); 9684 pci_set_power_state(pdev, PCI_D3hot); 9685 } 9686 } 9687 9688 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 9689 { 9690 #ifdef CONFIG_PCI_IOV 9691 int err; 9692 9693 if (num_vfs == 0) { 9694 return igb_disable_sriov(dev, true); 9695 } else { 9696 err = igb_enable_sriov(dev, num_vfs, true); 9697 return err ? err : num_vfs; 9698 } 9699 #endif 9700 return 0; 9701 } 9702 9703 /** 9704 * igb_io_error_detected - called when PCI error is detected 9705 * @pdev: Pointer to PCI device 9706 * @state: The current pci connection state 9707 * 9708 * This function is called after a PCI bus error affecting 9709 * this device has been detected. 9710 **/ 9711 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9712 pci_channel_state_t state) 9713 { 9714 struct net_device *netdev = pci_get_drvdata(pdev); 9715 struct igb_adapter *adapter = netdev_priv(netdev); 9716 9717 if (state == pci_channel_io_normal) { 9718 dev_warn(&pdev->dev, "Non-correctable non-fatal error reported.\n"); 9719 return PCI_ERS_RESULT_CAN_RECOVER; 9720 } 9721 9722 netif_device_detach(netdev); 9723 9724 if (state == pci_channel_io_perm_failure) 9725 return PCI_ERS_RESULT_DISCONNECT; 9726 9727 rtnl_lock(); 9728 if (netif_running(netdev)) 9729 igb_down(adapter); 9730 rtnl_unlock(); 9731 9732 pci_disable_device(pdev); 9733 9734 /* Request a slot reset. */ 9735 return PCI_ERS_RESULT_NEED_RESET; 9736 } 9737 9738 /** 9739 * igb_io_slot_reset - called after the pci bus has been reset. 9740 * @pdev: Pointer to PCI device 9741 * 9742 * Restart the card from scratch, as if from a cold-boot. Implementation 9743 * resembles the first-half of the __igb_resume routine. 9744 **/ 9745 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9746 { 9747 struct net_device *netdev = pci_get_drvdata(pdev); 9748 struct igb_adapter *adapter = netdev_priv(netdev); 9749 struct e1000_hw *hw = &adapter->hw; 9750 pci_ers_result_t result; 9751 9752 if (pci_enable_device_mem(pdev)) { 9753 dev_err(&pdev->dev, 9754 "Cannot re-enable PCI device after reset.\n"); 9755 result = PCI_ERS_RESULT_DISCONNECT; 9756 } else { 9757 pci_set_master(pdev); 9758 pci_restore_state(pdev); 9759 pci_save_state(pdev); 9760 9761 pci_enable_wake(pdev, PCI_D3hot, 0); 9762 pci_enable_wake(pdev, PCI_D3cold, 0); 9763 9764 /* In case of PCI error, adapter lose its HW address 9765 * so we should re-assign it here. 9766 */ 9767 hw->hw_addr = adapter->io_addr; 9768 9769 igb_reset(adapter); 9770 wr32(E1000_WUS, ~0); 9771 result = PCI_ERS_RESULT_RECOVERED; 9772 } 9773 9774 return result; 9775 } 9776 9777 /** 9778 * igb_io_resume - called when traffic can start flowing again. 9779 * @pdev: Pointer to PCI device 9780 * 9781 * This callback is called when the error recovery driver tells us that 9782 * its OK to resume normal operation. Implementation resembles the 9783 * second-half of the __igb_resume routine. 9784 */ 9785 static void igb_io_resume(struct pci_dev *pdev) 9786 { 9787 struct net_device *netdev = pci_get_drvdata(pdev); 9788 struct igb_adapter *adapter = netdev_priv(netdev); 9789 9790 rtnl_lock(); 9791 if (netif_running(netdev)) { 9792 if (!test_bit(__IGB_DOWN, &adapter->state)) { 9793 dev_dbg(&pdev->dev, "Resuming from non-fatal error, do nothing.\n"); 9794 rtnl_unlock(); 9795 return; 9796 } 9797 9798 if (igb_up(adapter)) { 9799 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9800 rtnl_unlock(); 9801 return; 9802 } 9803 } 9804 rtnl_unlock(); 9805 9806 netif_device_attach(netdev); 9807 9808 /* let the f/w know that the h/w is now under the control of the 9809 * driver. 9810 */ 9811 igb_get_hw_control(adapter); 9812 } 9813 9814 /** 9815 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9816 * @adapter: Pointer to adapter structure 9817 * @index: Index of the RAR entry which need to be synced with MAC table 9818 **/ 9819 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9820 { 9821 struct e1000_hw *hw = &adapter->hw; 9822 u32 rar_low, rar_high; 9823 u8 *addr = adapter->mac_table[index].addr; 9824 9825 /* HW expects these to be in network order when they are plugged 9826 * into the registers which are little endian. In order to guarantee 9827 * that ordering we need to do an leXX_to_cpup here in order to be 9828 * ready for the byteswap that occurs with writel 9829 */ 9830 rar_low = le32_to_cpup((__le32 *)(addr)); 9831 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9832 9833 /* Indicate to hardware the Address is Valid. */ 9834 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9835 if (is_valid_ether_addr(addr)) 9836 rar_high |= E1000_RAH_AV; 9837 9838 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9839 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9840 9841 switch (hw->mac.type) { 9842 case e1000_82575: 9843 case e1000_i210: 9844 if (adapter->mac_table[index].state & 9845 IGB_MAC_STATE_QUEUE_STEERING) 9846 rar_high |= E1000_RAH_QSEL_ENABLE; 9847 9848 rar_high |= E1000_RAH_POOL_1 * 9849 adapter->mac_table[index].queue; 9850 break; 9851 default: 9852 rar_high |= E1000_RAH_POOL_1 << 9853 adapter->mac_table[index].queue; 9854 break; 9855 } 9856 } 9857 9858 wr32(E1000_RAL(index), rar_low); 9859 wrfl(); 9860 wr32(E1000_RAH(index), rar_high); 9861 wrfl(); 9862 } 9863 9864 static int igb_set_vf_mac(struct igb_adapter *adapter, 9865 int vf, unsigned char *mac_addr) 9866 { 9867 struct e1000_hw *hw = &adapter->hw; 9868 /* VF MAC addresses start at end of receive addresses and moves 9869 * towards the first, as a result a collision should not be possible 9870 */ 9871 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9872 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9873 9874 ether_addr_copy(vf_mac_addr, mac_addr); 9875 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9876 adapter->mac_table[rar_entry].queue = vf; 9877 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9878 igb_rar_set_index(adapter, rar_entry); 9879 9880 return 0; 9881 } 9882 9883 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9884 { 9885 struct igb_adapter *adapter = netdev_priv(netdev); 9886 9887 if (vf >= adapter->vfs_allocated_count) 9888 return -EINVAL; 9889 9890 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9891 * flag and allows to overwrite the MAC via VF netdev. This 9892 * is necessary to allow libvirt a way to restore the original 9893 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9894 * down a VM. 9895 */ 9896 if (is_zero_ether_addr(mac)) { 9897 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9898 dev_info(&adapter->pdev->dev, 9899 "remove administratively set MAC on VF %d\n", 9900 vf); 9901 } else if (is_valid_ether_addr(mac)) { 9902 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9903 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9904 mac, vf); 9905 dev_info(&adapter->pdev->dev, 9906 "Reload the VF driver to make this change effective."); 9907 /* Generate additional warning if PF is down */ 9908 if (test_bit(__IGB_DOWN, &adapter->state)) { 9909 dev_warn(&adapter->pdev->dev, 9910 "The VF MAC address has been set, but the PF device is not up.\n"); 9911 dev_warn(&adapter->pdev->dev, 9912 "Bring the PF device up before attempting to use the VF device.\n"); 9913 } 9914 } else { 9915 return -EINVAL; 9916 } 9917 return igb_set_vf_mac(adapter, vf, mac); 9918 } 9919 9920 static int igb_link_mbps(int internal_link_speed) 9921 { 9922 switch (internal_link_speed) { 9923 case SPEED_100: 9924 return 100; 9925 case SPEED_1000: 9926 return 1000; 9927 default: 9928 return 0; 9929 } 9930 } 9931 9932 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9933 int link_speed) 9934 { 9935 int rf_dec, rf_int; 9936 u32 bcnrc_val; 9937 9938 if (tx_rate != 0) { 9939 /* Calculate the rate factor values to set */ 9940 rf_int = link_speed / tx_rate; 9941 rf_dec = (link_speed - (rf_int * tx_rate)); 9942 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9943 tx_rate; 9944 9945 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9946 bcnrc_val |= FIELD_PREP(E1000_RTTBCNRC_RF_INT_MASK, rf_int); 9947 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9948 } else { 9949 bcnrc_val = 0; 9950 } 9951 9952 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9953 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9954 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9955 */ 9956 wr32(E1000_RTTBCNRM, 0x14); 9957 wr32(E1000_RTTBCNRC, bcnrc_val); 9958 } 9959 9960 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9961 { 9962 int actual_link_speed, i; 9963 bool reset_rate = false; 9964 9965 /* VF TX rate limit was not set or not supported */ 9966 if ((adapter->vf_rate_link_speed == 0) || 9967 (adapter->hw.mac.type != e1000_82576)) 9968 return; 9969 9970 actual_link_speed = igb_link_mbps(adapter->link_speed); 9971 if (actual_link_speed != adapter->vf_rate_link_speed) { 9972 reset_rate = true; 9973 adapter->vf_rate_link_speed = 0; 9974 dev_info(&adapter->pdev->dev, 9975 "Link speed has been changed. VF Transmit rate is disabled\n"); 9976 } 9977 9978 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9979 if (reset_rate) 9980 adapter->vf_data[i].tx_rate = 0; 9981 9982 igb_set_vf_rate_limit(&adapter->hw, i, 9983 adapter->vf_data[i].tx_rate, 9984 actual_link_speed); 9985 } 9986 } 9987 9988 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9989 int min_tx_rate, int max_tx_rate) 9990 { 9991 struct igb_adapter *adapter = netdev_priv(netdev); 9992 struct e1000_hw *hw = &adapter->hw; 9993 int actual_link_speed; 9994 9995 if (hw->mac.type != e1000_82576) 9996 return -EOPNOTSUPP; 9997 9998 if (min_tx_rate) 9999 return -EINVAL; 10000 10001 actual_link_speed = igb_link_mbps(adapter->link_speed); 10002 if ((vf >= adapter->vfs_allocated_count) || 10003 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 10004 (max_tx_rate < 0) || 10005 (max_tx_rate > actual_link_speed)) 10006 return -EINVAL; 10007 10008 adapter->vf_rate_link_speed = actual_link_speed; 10009 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 10010 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 10011 10012 return 0; 10013 } 10014 10015 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 10016 bool setting) 10017 { 10018 struct igb_adapter *adapter = netdev_priv(netdev); 10019 struct e1000_hw *hw = &adapter->hw; 10020 u32 reg_val, reg_offset; 10021 10022 if (!adapter->vfs_allocated_count) 10023 return -EOPNOTSUPP; 10024 10025 if (vf >= adapter->vfs_allocated_count) 10026 return -EINVAL; 10027 10028 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 10029 reg_val = rd32(reg_offset); 10030 if (setting) 10031 reg_val |= (BIT(vf) | 10032 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 10033 else 10034 reg_val &= ~(BIT(vf) | 10035 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 10036 wr32(reg_offset, reg_val); 10037 10038 adapter->vf_data[vf].spoofchk_enabled = setting; 10039 return 0; 10040 } 10041 10042 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 10043 { 10044 struct igb_adapter *adapter = netdev_priv(netdev); 10045 10046 if (vf >= adapter->vfs_allocated_count) 10047 return -EINVAL; 10048 if (adapter->vf_data[vf].trusted == setting) 10049 return 0; 10050 10051 adapter->vf_data[vf].trusted = setting; 10052 10053 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 10054 vf, setting ? "" : "not "); 10055 return 0; 10056 } 10057 10058 static int igb_ndo_get_vf_config(struct net_device *netdev, 10059 int vf, struct ifla_vf_info *ivi) 10060 { 10061 struct igb_adapter *adapter = netdev_priv(netdev); 10062 if (vf >= adapter->vfs_allocated_count) 10063 return -EINVAL; 10064 ivi->vf = vf; 10065 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 10066 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 10067 ivi->min_tx_rate = 0; 10068 ivi->vlan = adapter->vf_data[vf].pf_vlan; 10069 ivi->qos = adapter->vf_data[vf].pf_qos; 10070 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 10071 ivi->trusted = adapter->vf_data[vf].trusted; 10072 return 0; 10073 } 10074 10075 static void igb_vmm_control(struct igb_adapter *adapter) 10076 { 10077 struct e1000_hw *hw = &adapter->hw; 10078 u32 reg; 10079 10080 switch (hw->mac.type) { 10081 case e1000_82575: 10082 case e1000_i210: 10083 case e1000_i211: 10084 case e1000_i354: 10085 default: 10086 /* replication is not supported for 82575 */ 10087 return; 10088 case e1000_82576: 10089 /* notify HW that the MAC is adding vlan tags */ 10090 reg = rd32(E1000_DTXCTL); 10091 reg |= E1000_DTXCTL_VLAN_ADDED; 10092 wr32(E1000_DTXCTL, reg); 10093 fallthrough; 10094 case e1000_82580: 10095 /* enable replication vlan tag stripping */ 10096 reg = rd32(E1000_RPLOLR); 10097 reg |= E1000_RPLOLR_STRVLAN; 10098 wr32(E1000_RPLOLR, reg); 10099 fallthrough; 10100 case e1000_i350: 10101 /* none of the above registers are supported by i350 */ 10102 break; 10103 } 10104 10105 if (adapter->vfs_allocated_count) { 10106 igb_vmdq_set_loopback_pf(hw, true); 10107 igb_vmdq_set_replication_pf(hw, true); 10108 igb_vmdq_set_anti_spoofing_pf(hw, true, 10109 adapter->vfs_allocated_count); 10110 } else { 10111 igb_vmdq_set_loopback_pf(hw, false); 10112 igb_vmdq_set_replication_pf(hw, false); 10113 } 10114 } 10115 10116 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 10117 { 10118 struct e1000_hw *hw = &adapter->hw; 10119 u32 dmac_thr; 10120 u16 hwm; 10121 u32 reg; 10122 10123 if (hw->mac.type > e1000_82580) { 10124 if (adapter->flags & IGB_FLAG_DMAC) { 10125 /* force threshold to 0. */ 10126 wr32(E1000_DMCTXTH, 0); 10127 10128 /* DMA Coalescing high water mark needs to be greater 10129 * than the Rx threshold. Set hwm to PBA - max frame 10130 * size in 16B units, capping it at PBA - 6KB. 10131 */ 10132 hwm = 64 * (pba - 6); 10133 reg = rd32(E1000_FCRTC); 10134 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 10135 reg |= FIELD_PREP(E1000_FCRTC_RTH_COAL_MASK, hwm); 10136 wr32(E1000_FCRTC, reg); 10137 10138 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 10139 * frame size, capping it at PBA - 10KB. 10140 */ 10141 dmac_thr = pba - 10; 10142 reg = rd32(E1000_DMACR); 10143 reg &= ~E1000_DMACR_DMACTHR_MASK; 10144 reg |= FIELD_PREP(E1000_DMACR_DMACTHR_MASK, dmac_thr); 10145 10146 /* transition to L0x or L1 if available..*/ 10147 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 10148 10149 /* watchdog timer= +-1000 usec in 32usec intervals */ 10150 reg |= (1000 >> 5); 10151 10152 /* Disable BMC-to-OS Watchdog Enable */ 10153 if (hw->mac.type != e1000_i354) 10154 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 10155 wr32(E1000_DMACR, reg); 10156 10157 /* no lower threshold to disable 10158 * coalescing(smart fifb)-UTRESH=0 10159 */ 10160 wr32(E1000_DMCRTRH, 0); 10161 10162 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 10163 10164 wr32(E1000_DMCTLX, reg); 10165 10166 /* free space in tx packet buffer to wake from 10167 * DMA coal 10168 */ 10169 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 10170 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 10171 } 10172 10173 if (hw->mac.type >= e1000_i210 || 10174 (adapter->flags & IGB_FLAG_DMAC)) { 10175 reg = rd32(E1000_PCIEMISC); 10176 reg |= E1000_PCIEMISC_LX_DECISION; 10177 wr32(E1000_PCIEMISC, reg); 10178 } /* endif adapter->dmac is not disabled */ 10179 } else if (hw->mac.type == e1000_82580) { 10180 u32 reg = rd32(E1000_PCIEMISC); 10181 10182 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 10183 wr32(E1000_DMACR, 0); 10184 } 10185 } 10186 10187 /** 10188 * igb_read_i2c_byte - Reads 8 bit word over I2C 10189 * @hw: pointer to hardware structure 10190 * @byte_offset: byte offset to read 10191 * @dev_addr: device address 10192 * @data: value read 10193 * 10194 * Performs byte read operation over I2C interface at 10195 * a specified device address. 10196 **/ 10197 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10198 u8 dev_addr, u8 *data) 10199 { 10200 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10201 struct i2c_client *this_client = adapter->i2c_client; 10202 s32 status; 10203 u16 swfw_mask = 0; 10204 10205 if (!this_client) 10206 return E1000_ERR_I2C; 10207 10208 swfw_mask = E1000_SWFW_PHY0_SM; 10209 10210 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10211 return E1000_ERR_SWFW_SYNC; 10212 10213 status = i2c_smbus_read_byte_data(this_client, byte_offset); 10214 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10215 10216 if (status < 0) 10217 return E1000_ERR_I2C; 10218 else { 10219 *data = status; 10220 return 0; 10221 } 10222 } 10223 10224 /** 10225 * igb_write_i2c_byte - Writes 8 bit word over I2C 10226 * @hw: pointer to hardware structure 10227 * @byte_offset: byte offset to write 10228 * @dev_addr: device address 10229 * @data: value to write 10230 * 10231 * Performs byte write operation over I2C interface at 10232 * a specified device address. 10233 **/ 10234 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10235 u8 dev_addr, u8 data) 10236 { 10237 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10238 struct i2c_client *this_client = adapter->i2c_client; 10239 s32 status; 10240 u16 swfw_mask = E1000_SWFW_PHY0_SM; 10241 10242 if (!this_client) 10243 return E1000_ERR_I2C; 10244 10245 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10246 return E1000_ERR_SWFW_SYNC; 10247 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 10248 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10249 10250 if (status) 10251 return E1000_ERR_I2C; 10252 else 10253 return 0; 10254 10255 } 10256 10257 int igb_reinit_queues(struct igb_adapter *adapter) 10258 { 10259 struct net_device *netdev = adapter->netdev; 10260 struct pci_dev *pdev = adapter->pdev; 10261 int err = 0; 10262 10263 if (netif_running(netdev)) 10264 igb_close(netdev); 10265 10266 igb_reset_interrupt_capability(adapter); 10267 10268 if (igb_init_interrupt_scheme(adapter, true)) { 10269 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 10270 return -ENOMEM; 10271 } 10272 10273 if (netif_running(netdev)) 10274 err = igb_open(netdev); 10275 10276 return err; 10277 } 10278 10279 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 10280 { 10281 struct igb_nfc_filter *rule; 10282 10283 spin_lock(&adapter->nfc_lock); 10284 10285 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10286 igb_erase_filter(adapter, rule); 10287 10288 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 10289 igb_erase_filter(adapter, rule); 10290 10291 spin_unlock(&adapter->nfc_lock); 10292 } 10293 10294 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 10295 { 10296 struct igb_nfc_filter *rule; 10297 10298 spin_lock(&adapter->nfc_lock); 10299 10300 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10301 igb_add_filter(adapter, rule); 10302 10303 spin_unlock(&adapter->nfc_lock); 10304 } 10305 10306 static _DEFINE_DEV_PM_OPS(igb_pm_ops, igb_suspend, igb_resume, 10307 igb_runtime_suspend, igb_runtime_resume, 10308 igb_runtime_idle); 10309 10310 static struct pci_driver igb_driver = { 10311 .name = igb_driver_name, 10312 .id_table = igb_pci_tbl, 10313 .probe = igb_probe, 10314 .remove = igb_remove, 10315 .driver.pm = pm_ptr(&igb_pm_ops), 10316 .shutdown = igb_shutdown, 10317 .sriov_configure = igb_pci_sriov_configure, 10318 .err_handler = &igb_err_handler 10319 }; 10320 10321 /* igb_main.c */ 10322