1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/sctp.h> 30 #include <linux/if_ether.h> 31 #include <linux/aer.h> 32 #include <linux/prefetch.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/etherdevice.h> 35 #ifdef CONFIG_IGB_DCA 36 #include <linux/dca.h> 37 #endif 38 #include <linux/i2c.h> 39 #include "igb.h" 40 41 #define MAJ 5 42 #define MIN 6 43 #define BUILD 0 44 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 45 __stringify(BUILD) "-k" 46 47 enum queue_mode { 48 QUEUE_MODE_STRICT_PRIORITY, 49 QUEUE_MODE_STREAM_RESERVATION, 50 }; 51 52 enum tx_queue_prio { 53 TX_QUEUE_PRIO_HIGH, 54 TX_QUEUE_PRIO_LOW, 55 }; 56 57 char igb_driver_name[] = "igb"; 58 char igb_driver_version[] = DRV_VERSION; 59 static const char igb_driver_string[] = 60 "Intel(R) Gigabit Ethernet Network Driver"; 61 static const char igb_copyright[] = 62 "Copyright (c) 2007-2014 Intel Corporation."; 63 64 static const struct e1000_info *igb_info_tbl[] = { 65 [board_82575] = &e1000_82575_info, 66 }; 67 68 static const struct pci_device_id igb_pci_tbl[] = { 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 104 /* required last entry */ 105 {0, } 106 }; 107 108 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 109 110 static int igb_setup_all_tx_resources(struct igb_adapter *); 111 static int igb_setup_all_rx_resources(struct igb_adapter *); 112 static void igb_free_all_tx_resources(struct igb_adapter *); 113 static void igb_free_all_rx_resources(struct igb_adapter *); 114 static void igb_setup_mrqc(struct igb_adapter *); 115 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 116 static void igb_remove(struct pci_dev *pdev); 117 static int igb_sw_init(struct igb_adapter *); 118 int igb_open(struct net_device *); 119 int igb_close(struct net_device *); 120 static void igb_configure(struct igb_adapter *); 121 static void igb_configure_tx(struct igb_adapter *); 122 static void igb_configure_rx(struct igb_adapter *); 123 static void igb_clean_all_tx_rings(struct igb_adapter *); 124 static void igb_clean_all_rx_rings(struct igb_adapter *); 125 static void igb_clean_tx_ring(struct igb_ring *); 126 static void igb_clean_rx_ring(struct igb_ring *); 127 static void igb_set_rx_mode(struct net_device *); 128 static void igb_update_phy_info(struct timer_list *); 129 static void igb_watchdog(struct timer_list *); 130 static void igb_watchdog_task(struct work_struct *); 131 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 132 static void igb_get_stats64(struct net_device *dev, 133 struct rtnl_link_stats64 *stats); 134 static int igb_change_mtu(struct net_device *, int); 135 static int igb_set_mac(struct net_device *, void *); 136 static void igb_set_uta(struct igb_adapter *adapter, bool set); 137 static irqreturn_t igb_intr(int irq, void *); 138 static irqreturn_t igb_intr_msi(int irq, void *); 139 static irqreturn_t igb_msix_other(int irq, void *); 140 static irqreturn_t igb_msix_ring(int irq, void *); 141 #ifdef CONFIG_IGB_DCA 142 static void igb_update_dca(struct igb_q_vector *); 143 static void igb_setup_dca(struct igb_adapter *); 144 #endif /* CONFIG_IGB_DCA */ 145 static int igb_poll(struct napi_struct *, int); 146 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 147 static int igb_clean_rx_irq(struct igb_q_vector *, int); 148 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 149 static void igb_tx_timeout(struct net_device *); 150 static void igb_reset_task(struct work_struct *); 151 static void igb_vlan_mode(struct net_device *netdev, 152 netdev_features_t features); 153 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 154 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 155 static void igb_restore_vlan(struct igb_adapter *); 156 static void igb_rar_set_index(struct igb_adapter *, u32); 157 static void igb_ping_all_vfs(struct igb_adapter *); 158 static void igb_msg_task(struct igb_adapter *); 159 static void igb_vmm_control(struct igb_adapter *); 160 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 161 static void igb_flush_mac_table(struct igb_adapter *); 162 static int igb_available_rars(struct igb_adapter *, u8); 163 static void igb_set_default_mac_filter(struct igb_adapter *); 164 static int igb_uc_sync(struct net_device *, const unsigned char *); 165 static int igb_uc_unsync(struct net_device *, const unsigned char *); 166 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 167 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 168 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 169 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 170 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 171 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 172 bool setting); 173 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 174 bool setting); 175 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 176 struct ifla_vf_info *ivi); 177 static void igb_check_vf_rate_limit(struct igb_adapter *); 178 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 179 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 180 181 #ifdef CONFIG_PCI_IOV 182 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 183 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 184 static int igb_disable_sriov(struct pci_dev *dev); 185 static int igb_pci_disable_sriov(struct pci_dev *dev); 186 #endif 187 188 static int igb_suspend(struct device *); 189 static int igb_resume(struct device *); 190 static int igb_runtime_suspend(struct device *dev); 191 static int igb_runtime_resume(struct device *dev); 192 static int igb_runtime_idle(struct device *dev); 193 static const struct dev_pm_ops igb_pm_ops = { 194 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 195 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 196 igb_runtime_idle) 197 }; 198 static void igb_shutdown(struct pci_dev *); 199 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 200 #ifdef CONFIG_IGB_DCA 201 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 202 static struct notifier_block dca_notifier = { 203 .notifier_call = igb_notify_dca, 204 .next = NULL, 205 .priority = 0 206 }; 207 #endif 208 #ifdef CONFIG_PCI_IOV 209 static unsigned int max_vfs; 210 module_param(max_vfs, uint, 0); 211 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 212 #endif /* CONFIG_PCI_IOV */ 213 214 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 215 pci_channel_state_t); 216 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 217 static void igb_io_resume(struct pci_dev *); 218 219 static const struct pci_error_handlers igb_err_handler = { 220 .error_detected = igb_io_error_detected, 221 .slot_reset = igb_io_slot_reset, 222 .resume = igb_io_resume, 223 }; 224 225 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 226 227 static struct pci_driver igb_driver = { 228 .name = igb_driver_name, 229 .id_table = igb_pci_tbl, 230 .probe = igb_probe, 231 .remove = igb_remove, 232 #ifdef CONFIG_PM 233 .driver.pm = &igb_pm_ops, 234 #endif 235 .shutdown = igb_shutdown, 236 .sriov_configure = igb_pci_sriov_configure, 237 .err_handler = &igb_err_handler 238 }; 239 240 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 241 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 242 MODULE_LICENSE("GPL v2"); 243 MODULE_VERSION(DRV_VERSION); 244 245 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 246 static int debug = -1; 247 module_param(debug, int, 0); 248 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 249 250 struct igb_reg_info { 251 u32 ofs; 252 char *name; 253 }; 254 255 static const struct igb_reg_info igb_reg_info_tbl[] = { 256 257 /* General Registers */ 258 {E1000_CTRL, "CTRL"}, 259 {E1000_STATUS, "STATUS"}, 260 {E1000_CTRL_EXT, "CTRL_EXT"}, 261 262 /* Interrupt Registers */ 263 {E1000_ICR, "ICR"}, 264 265 /* RX Registers */ 266 {E1000_RCTL, "RCTL"}, 267 {E1000_RDLEN(0), "RDLEN"}, 268 {E1000_RDH(0), "RDH"}, 269 {E1000_RDT(0), "RDT"}, 270 {E1000_RXDCTL(0), "RXDCTL"}, 271 {E1000_RDBAL(0), "RDBAL"}, 272 {E1000_RDBAH(0), "RDBAH"}, 273 274 /* TX Registers */ 275 {E1000_TCTL, "TCTL"}, 276 {E1000_TDBAL(0), "TDBAL"}, 277 {E1000_TDBAH(0), "TDBAH"}, 278 {E1000_TDLEN(0), "TDLEN"}, 279 {E1000_TDH(0), "TDH"}, 280 {E1000_TDT(0), "TDT"}, 281 {E1000_TXDCTL(0), "TXDCTL"}, 282 {E1000_TDFH, "TDFH"}, 283 {E1000_TDFT, "TDFT"}, 284 {E1000_TDFHS, "TDFHS"}, 285 {E1000_TDFPC, "TDFPC"}, 286 287 /* List Terminator */ 288 {} 289 }; 290 291 /* igb_regdump - register printout routine */ 292 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 293 { 294 int n = 0; 295 char rname[16]; 296 u32 regs[8]; 297 298 switch (reginfo->ofs) { 299 case E1000_RDLEN(0): 300 for (n = 0; n < 4; n++) 301 regs[n] = rd32(E1000_RDLEN(n)); 302 break; 303 case E1000_RDH(0): 304 for (n = 0; n < 4; n++) 305 regs[n] = rd32(E1000_RDH(n)); 306 break; 307 case E1000_RDT(0): 308 for (n = 0; n < 4; n++) 309 regs[n] = rd32(E1000_RDT(n)); 310 break; 311 case E1000_RXDCTL(0): 312 for (n = 0; n < 4; n++) 313 regs[n] = rd32(E1000_RXDCTL(n)); 314 break; 315 case E1000_RDBAL(0): 316 for (n = 0; n < 4; n++) 317 regs[n] = rd32(E1000_RDBAL(n)); 318 break; 319 case E1000_RDBAH(0): 320 for (n = 0; n < 4; n++) 321 regs[n] = rd32(E1000_RDBAH(n)); 322 break; 323 case E1000_TDBAL(0): 324 for (n = 0; n < 4; n++) 325 regs[n] = rd32(E1000_RDBAL(n)); 326 break; 327 case E1000_TDBAH(0): 328 for (n = 0; n < 4; n++) 329 regs[n] = rd32(E1000_TDBAH(n)); 330 break; 331 case E1000_TDLEN(0): 332 for (n = 0; n < 4; n++) 333 regs[n] = rd32(E1000_TDLEN(n)); 334 break; 335 case E1000_TDH(0): 336 for (n = 0; n < 4; n++) 337 regs[n] = rd32(E1000_TDH(n)); 338 break; 339 case E1000_TDT(0): 340 for (n = 0; n < 4; n++) 341 regs[n] = rd32(E1000_TDT(n)); 342 break; 343 case E1000_TXDCTL(0): 344 for (n = 0; n < 4; n++) 345 regs[n] = rd32(E1000_TXDCTL(n)); 346 break; 347 default: 348 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 349 return; 350 } 351 352 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 353 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 354 regs[2], regs[3]); 355 } 356 357 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 358 static void igb_dump(struct igb_adapter *adapter) 359 { 360 struct net_device *netdev = adapter->netdev; 361 struct e1000_hw *hw = &adapter->hw; 362 struct igb_reg_info *reginfo; 363 struct igb_ring *tx_ring; 364 union e1000_adv_tx_desc *tx_desc; 365 struct my_u0 { u64 a; u64 b; } *u0; 366 struct igb_ring *rx_ring; 367 union e1000_adv_rx_desc *rx_desc; 368 u32 staterr; 369 u16 i, n; 370 371 if (!netif_msg_hw(adapter)) 372 return; 373 374 /* Print netdevice Info */ 375 if (netdev) { 376 dev_info(&adapter->pdev->dev, "Net device Info\n"); 377 pr_info("Device Name state trans_start\n"); 378 pr_info("%-15s %016lX %016lX\n", netdev->name, 379 netdev->state, dev_trans_start(netdev)); 380 } 381 382 /* Print Registers */ 383 dev_info(&adapter->pdev->dev, "Register Dump\n"); 384 pr_info(" Register Name Value\n"); 385 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 386 reginfo->name; reginfo++) { 387 igb_regdump(hw, reginfo); 388 } 389 390 /* Print TX Ring Summary */ 391 if (!netdev || !netif_running(netdev)) 392 goto exit; 393 394 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 395 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 396 for (n = 0; n < adapter->num_tx_queues; n++) { 397 struct igb_tx_buffer *buffer_info; 398 tx_ring = adapter->tx_ring[n]; 399 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 400 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 401 n, tx_ring->next_to_use, tx_ring->next_to_clean, 402 (u64)dma_unmap_addr(buffer_info, dma), 403 dma_unmap_len(buffer_info, len), 404 buffer_info->next_to_watch, 405 (u64)buffer_info->time_stamp); 406 } 407 408 /* Print TX Rings */ 409 if (!netif_msg_tx_done(adapter)) 410 goto rx_ring_summary; 411 412 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 413 414 /* Transmit Descriptor Formats 415 * 416 * Advanced Transmit Descriptor 417 * +--------------------------------------------------------------+ 418 * 0 | Buffer Address [63:0] | 419 * +--------------------------------------------------------------+ 420 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 421 * +--------------------------------------------------------------+ 422 * 63 46 45 40 39 38 36 35 32 31 24 15 0 423 */ 424 425 for (n = 0; n < adapter->num_tx_queues; n++) { 426 tx_ring = adapter->tx_ring[n]; 427 pr_info("------------------------------------\n"); 428 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 429 pr_info("------------------------------------\n"); 430 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 431 432 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 433 const char *next_desc; 434 struct igb_tx_buffer *buffer_info; 435 tx_desc = IGB_TX_DESC(tx_ring, i); 436 buffer_info = &tx_ring->tx_buffer_info[i]; 437 u0 = (struct my_u0 *)tx_desc; 438 if (i == tx_ring->next_to_use && 439 i == tx_ring->next_to_clean) 440 next_desc = " NTC/U"; 441 else if (i == tx_ring->next_to_use) 442 next_desc = " NTU"; 443 else if (i == tx_ring->next_to_clean) 444 next_desc = " NTC"; 445 else 446 next_desc = ""; 447 448 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 449 i, le64_to_cpu(u0->a), 450 le64_to_cpu(u0->b), 451 (u64)dma_unmap_addr(buffer_info, dma), 452 dma_unmap_len(buffer_info, len), 453 buffer_info->next_to_watch, 454 (u64)buffer_info->time_stamp, 455 buffer_info->skb, next_desc); 456 457 if (netif_msg_pktdata(adapter) && buffer_info->skb) 458 print_hex_dump(KERN_INFO, "", 459 DUMP_PREFIX_ADDRESS, 460 16, 1, buffer_info->skb->data, 461 dma_unmap_len(buffer_info, len), 462 true); 463 } 464 } 465 466 /* Print RX Rings Summary */ 467 rx_ring_summary: 468 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 469 pr_info("Queue [NTU] [NTC]\n"); 470 for (n = 0; n < adapter->num_rx_queues; n++) { 471 rx_ring = adapter->rx_ring[n]; 472 pr_info(" %5d %5X %5X\n", 473 n, rx_ring->next_to_use, rx_ring->next_to_clean); 474 } 475 476 /* Print RX Rings */ 477 if (!netif_msg_rx_status(adapter)) 478 goto exit; 479 480 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 481 482 /* Advanced Receive Descriptor (Read) Format 483 * 63 1 0 484 * +-----------------------------------------------------+ 485 * 0 | Packet Buffer Address [63:1] |A0/NSE| 486 * +----------------------------------------------+------+ 487 * 8 | Header Buffer Address [63:1] | DD | 488 * +-----------------------------------------------------+ 489 * 490 * 491 * Advanced Receive Descriptor (Write-Back) Format 492 * 493 * 63 48 47 32 31 30 21 20 17 16 4 3 0 494 * +------------------------------------------------------+ 495 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 496 * | Checksum Ident | | | | Type | Type | 497 * +------------------------------------------------------+ 498 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 499 * +------------------------------------------------------+ 500 * 63 48 47 32 31 20 19 0 501 */ 502 503 for (n = 0; n < adapter->num_rx_queues; n++) { 504 rx_ring = adapter->rx_ring[n]; 505 pr_info("------------------------------------\n"); 506 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 507 pr_info("------------------------------------\n"); 508 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 509 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 510 511 for (i = 0; i < rx_ring->count; i++) { 512 const char *next_desc; 513 struct igb_rx_buffer *buffer_info; 514 buffer_info = &rx_ring->rx_buffer_info[i]; 515 rx_desc = IGB_RX_DESC(rx_ring, i); 516 u0 = (struct my_u0 *)rx_desc; 517 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 518 519 if (i == rx_ring->next_to_use) 520 next_desc = " NTU"; 521 else if (i == rx_ring->next_to_clean) 522 next_desc = " NTC"; 523 else 524 next_desc = ""; 525 526 if (staterr & E1000_RXD_STAT_DD) { 527 /* Descriptor Done */ 528 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 529 "RWB", i, 530 le64_to_cpu(u0->a), 531 le64_to_cpu(u0->b), 532 next_desc); 533 } else { 534 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 535 "R ", i, 536 le64_to_cpu(u0->a), 537 le64_to_cpu(u0->b), 538 (u64)buffer_info->dma, 539 next_desc); 540 541 if (netif_msg_pktdata(adapter) && 542 buffer_info->dma && buffer_info->page) { 543 print_hex_dump(KERN_INFO, "", 544 DUMP_PREFIX_ADDRESS, 545 16, 1, 546 page_address(buffer_info->page) + 547 buffer_info->page_offset, 548 igb_rx_bufsz(rx_ring), true); 549 } 550 } 551 } 552 } 553 554 exit: 555 return; 556 } 557 558 /** 559 * igb_get_i2c_data - Reads the I2C SDA data bit 560 * @hw: pointer to hardware structure 561 * @i2cctl: Current value of I2CCTL register 562 * 563 * Returns the I2C data bit value 564 **/ 565 static int igb_get_i2c_data(void *data) 566 { 567 struct igb_adapter *adapter = (struct igb_adapter *)data; 568 struct e1000_hw *hw = &adapter->hw; 569 s32 i2cctl = rd32(E1000_I2CPARAMS); 570 571 return !!(i2cctl & E1000_I2C_DATA_IN); 572 } 573 574 /** 575 * igb_set_i2c_data - Sets the I2C data bit 576 * @data: pointer to hardware structure 577 * @state: I2C data value (0 or 1) to set 578 * 579 * Sets the I2C data bit 580 **/ 581 static void igb_set_i2c_data(void *data, int state) 582 { 583 struct igb_adapter *adapter = (struct igb_adapter *)data; 584 struct e1000_hw *hw = &adapter->hw; 585 s32 i2cctl = rd32(E1000_I2CPARAMS); 586 587 if (state) 588 i2cctl |= E1000_I2C_DATA_OUT; 589 else 590 i2cctl &= ~E1000_I2C_DATA_OUT; 591 592 i2cctl &= ~E1000_I2C_DATA_OE_N; 593 i2cctl |= E1000_I2C_CLK_OE_N; 594 wr32(E1000_I2CPARAMS, i2cctl); 595 wrfl(); 596 597 } 598 599 /** 600 * igb_set_i2c_clk - Sets the I2C SCL clock 601 * @data: pointer to hardware structure 602 * @state: state to set clock 603 * 604 * Sets the I2C clock line to state 605 **/ 606 static void igb_set_i2c_clk(void *data, int state) 607 { 608 struct igb_adapter *adapter = (struct igb_adapter *)data; 609 struct e1000_hw *hw = &adapter->hw; 610 s32 i2cctl = rd32(E1000_I2CPARAMS); 611 612 if (state) { 613 i2cctl |= E1000_I2C_CLK_OUT; 614 i2cctl &= ~E1000_I2C_CLK_OE_N; 615 } else { 616 i2cctl &= ~E1000_I2C_CLK_OUT; 617 i2cctl &= ~E1000_I2C_CLK_OE_N; 618 } 619 wr32(E1000_I2CPARAMS, i2cctl); 620 wrfl(); 621 } 622 623 /** 624 * igb_get_i2c_clk - Gets the I2C SCL clock state 625 * @data: pointer to hardware structure 626 * 627 * Gets the I2C clock state 628 **/ 629 static int igb_get_i2c_clk(void *data) 630 { 631 struct igb_adapter *adapter = (struct igb_adapter *)data; 632 struct e1000_hw *hw = &adapter->hw; 633 s32 i2cctl = rd32(E1000_I2CPARAMS); 634 635 return !!(i2cctl & E1000_I2C_CLK_IN); 636 } 637 638 static const struct i2c_algo_bit_data igb_i2c_algo = { 639 .setsda = igb_set_i2c_data, 640 .setscl = igb_set_i2c_clk, 641 .getsda = igb_get_i2c_data, 642 .getscl = igb_get_i2c_clk, 643 .udelay = 5, 644 .timeout = 20, 645 }; 646 647 /** 648 * igb_get_hw_dev - return device 649 * @hw: pointer to hardware structure 650 * 651 * used by hardware layer to print debugging information 652 **/ 653 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 654 { 655 struct igb_adapter *adapter = hw->back; 656 return adapter->netdev; 657 } 658 659 /** 660 * igb_init_module - Driver Registration Routine 661 * 662 * igb_init_module is the first routine called when the driver is 663 * loaded. All it does is register with the PCI subsystem. 664 **/ 665 static int __init igb_init_module(void) 666 { 667 int ret; 668 669 pr_info("%s - version %s\n", 670 igb_driver_string, igb_driver_version); 671 pr_info("%s\n", igb_copyright); 672 673 #ifdef CONFIG_IGB_DCA 674 dca_register_notify(&dca_notifier); 675 #endif 676 ret = pci_register_driver(&igb_driver); 677 return ret; 678 } 679 680 module_init(igb_init_module); 681 682 /** 683 * igb_exit_module - Driver Exit Cleanup Routine 684 * 685 * igb_exit_module is called just before the driver is removed 686 * from memory. 687 **/ 688 static void __exit igb_exit_module(void) 689 { 690 #ifdef CONFIG_IGB_DCA 691 dca_unregister_notify(&dca_notifier); 692 #endif 693 pci_unregister_driver(&igb_driver); 694 } 695 696 module_exit(igb_exit_module); 697 698 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 699 /** 700 * igb_cache_ring_register - Descriptor ring to register mapping 701 * @adapter: board private structure to initialize 702 * 703 * Once we know the feature-set enabled for the device, we'll cache 704 * the register offset the descriptor ring is assigned to. 705 **/ 706 static void igb_cache_ring_register(struct igb_adapter *adapter) 707 { 708 int i = 0, j = 0; 709 u32 rbase_offset = adapter->vfs_allocated_count; 710 711 switch (adapter->hw.mac.type) { 712 case e1000_82576: 713 /* The queues are allocated for virtualization such that VF 0 714 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 715 * In order to avoid collision we start at the first free queue 716 * and continue consuming queues in the same sequence 717 */ 718 if (adapter->vfs_allocated_count) { 719 for (; i < adapter->rss_queues; i++) 720 adapter->rx_ring[i]->reg_idx = rbase_offset + 721 Q_IDX_82576(i); 722 } 723 /* Fall through */ 724 case e1000_82575: 725 case e1000_82580: 726 case e1000_i350: 727 case e1000_i354: 728 case e1000_i210: 729 case e1000_i211: 730 /* Fall through */ 731 default: 732 for (; i < adapter->num_rx_queues; i++) 733 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 734 for (; j < adapter->num_tx_queues; j++) 735 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 736 break; 737 } 738 } 739 740 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 741 { 742 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 743 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 744 u32 value = 0; 745 746 if (E1000_REMOVED(hw_addr)) 747 return ~value; 748 749 value = readl(&hw_addr[reg]); 750 751 /* reads should not return all F's */ 752 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 753 struct net_device *netdev = igb->netdev; 754 hw->hw_addr = NULL; 755 netdev_err(netdev, "PCIe link lost\n"); 756 WARN(1, "igb: Failed to read reg 0x%x!\n", reg); 757 } 758 759 return value; 760 } 761 762 /** 763 * igb_write_ivar - configure ivar for given MSI-X vector 764 * @hw: pointer to the HW structure 765 * @msix_vector: vector number we are allocating to a given ring 766 * @index: row index of IVAR register to write within IVAR table 767 * @offset: column offset of in IVAR, should be multiple of 8 768 * 769 * This function is intended to handle the writing of the IVAR register 770 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 771 * each containing an cause allocation for an Rx and Tx ring, and a 772 * variable number of rows depending on the number of queues supported. 773 **/ 774 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 775 int index, int offset) 776 { 777 u32 ivar = array_rd32(E1000_IVAR0, index); 778 779 /* clear any bits that are currently set */ 780 ivar &= ~((u32)0xFF << offset); 781 782 /* write vector and valid bit */ 783 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 784 785 array_wr32(E1000_IVAR0, index, ivar); 786 } 787 788 #define IGB_N0_QUEUE -1 789 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 790 { 791 struct igb_adapter *adapter = q_vector->adapter; 792 struct e1000_hw *hw = &adapter->hw; 793 int rx_queue = IGB_N0_QUEUE; 794 int tx_queue = IGB_N0_QUEUE; 795 u32 msixbm = 0; 796 797 if (q_vector->rx.ring) 798 rx_queue = q_vector->rx.ring->reg_idx; 799 if (q_vector->tx.ring) 800 tx_queue = q_vector->tx.ring->reg_idx; 801 802 switch (hw->mac.type) { 803 case e1000_82575: 804 /* The 82575 assigns vectors using a bitmask, which matches the 805 * bitmask for the EICR/EIMS/EIMC registers. To assign one 806 * or more queues to a vector, we write the appropriate bits 807 * into the MSIXBM register for that vector. 808 */ 809 if (rx_queue > IGB_N0_QUEUE) 810 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 811 if (tx_queue > IGB_N0_QUEUE) 812 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 813 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 814 msixbm |= E1000_EIMS_OTHER; 815 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 816 q_vector->eims_value = msixbm; 817 break; 818 case e1000_82576: 819 /* 82576 uses a table that essentially consists of 2 columns 820 * with 8 rows. The ordering is column-major so we use the 821 * lower 3 bits as the row index, and the 4th bit as the 822 * column offset. 823 */ 824 if (rx_queue > IGB_N0_QUEUE) 825 igb_write_ivar(hw, msix_vector, 826 rx_queue & 0x7, 827 (rx_queue & 0x8) << 1); 828 if (tx_queue > IGB_N0_QUEUE) 829 igb_write_ivar(hw, msix_vector, 830 tx_queue & 0x7, 831 ((tx_queue & 0x8) << 1) + 8); 832 q_vector->eims_value = BIT(msix_vector); 833 break; 834 case e1000_82580: 835 case e1000_i350: 836 case e1000_i354: 837 case e1000_i210: 838 case e1000_i211: 839 /* On 82580 and newer adapters the scheme is similar to 82576 840 * however instead of ordering column-major we have things 841 * ordered row-major. So we traverse the table by using 842 * bit 0 as the column offset, and the remaining bits as the 843 * row index. 844 */ 845 if (rx_queue > IGB_N0_QUEUE) 846 igb_write_ivar(hw, msix_vector, 847 rx_queue >> 1, 848 (rx_queue & 0x1) << 4); 849 if (tx_queue > IGB_N0_QUEUE) 850 igb_write_ivar(hw, msix_vector, 851 tx_queue >> 1, 852 ((tx_queue & 0x1) << 4) + 8); 853 q_vector->eims_value = BIT(msix_vector); 854 break; 855 default: 856 BUG(); 857 break; 858 } 859 860 /* add q_vector eims value to global eims_enable_mask */ 861 adapter->eims_enable_mask |= q_vector->eims_value; 862 863 /* configure q_vector to set itr on first interrupt */ 864 q_vector->set_itr = 1; 865 } 866 867 /** 868 * igb_configure_msix - Configure MSI-X hardware 869 * @adapter: board private structure to initialize 870 * 871 * igb_configure_msix sets up the hardware to properly 872 * generate MSI-X interrupts. 873 **/ 874 static void igb_configure_msix(struct igb_adapter *adapter) 875 { 876 u32 tmp; 877 int i, vector = 0; 878 struct e1000_hw *hw = &adapter->hw; 879 880 adapter->eims_enable_mask = 0; 881 882 /* set vector for other causes, i.e. link changes */ 883 switch (hw->mac.type) { 884 case e1000_82575: 885 tmp = rd32(E1000_CTRL_EXT); 886 /* enable MSI-X PBA support*/ 887 tmp |= E1000_CTRL_EXT_PBA_CLR; 888 889 /* Auto-Mask interrupts upon ICR read. */ 890 tmp |= E1000_CTRL_EXT_EIAME; 891 tmp |= E1000_CTRL_EXT_IRCA; 892 893 wr32(E1000_CTRL_EXT, tmp); 894 895 /* enable msix_other interrupt */ 896 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 897 adapter->eims_other = E1000_EIMS_OTHER; 898 899 break; 900 901 case e1000_82576: 902 case e1000_82580: 903 case e1000_i350: 904 case e1000_i354: 905 case e1000_i210: 906 case e1000_i211: 907 /* Turn on MSI-X capability first, or our settings 908 * won't stick. And it will take days to debug. 909 */ 910 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 911 E1000_GPIE_PBA | E1000_GPIE_EIAME | 912 E1000_GPIE_NSICR); 913 914 /* enable msix_other interrupt */ 915 adapter->eims_other = BIT(vector); 916 tmp = (vector++ | E1000_IVAR_VALID) << 8; 917 918 wr32(E1000_IVAR_MISC, tmp); 919 break; 920 default: 921 /* do nothing, since nothing else supports MSI-X */ 922 break; 923 } /* switch (hw->mac.type) */ 924 925 adapter->eims_enable_mask |= adapter->eims_other; 926 927 for (i = 0; i < adapter->num_q_vectors; i++) 928 igb_assign_vector(adapter->q_vector[i], vector++); 929 930 wrfl(); 931 } 932 933 /** 934 * igb_request_msix - Initialize MSI-X interrupts 935 * @adapter: board private structure to initialize 936 * 937 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 938 * kernel. 939 **/ 940 static int igb_request_msix(struct igb_adapter *adapter) 941 { 942 struct net_device *netdev = adapter->netdev; 943 int i, err = 0, vector = 0, free_vector = 0; 944 945 err = request_irq(adapter->msix_entries[vector].vector, 946 igb_msix_other, 0, netdev->name, adapter); 947 if (err) 948 goto err_out; 949 950 for (i = 0; i < adapter->num_q_vectors; i++) { 951 struct igb_q_vector *q_vector = adapter->q_vector[i]; 952 953 vector++; 954 955 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 956 957 if (q_vector->rx.ring && q_vector->tx.ring) 958 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 959 q_vector->rx.ring->queue_index); 960 else if (q_vector->tx.ring) 961 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 962 q_vector->tx.ring->queue_index); 963 else if (q_vector->rx.ring) 964 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 965 q_vector->rx.ring->queue_index); 966 else 967 sprintf(q_vector->name, "%s-unused", netdev->name); 968 969 err = request_irq(adapter->msix_entries[vector].vector, 970 igb_msix_ring, 0, q_vector->name, 971 q_vector); 972 if (err) 973 goto err_free; 974 } 975 976 igb_configure_msix(adapter); 977 return 0; 978 979 err_free: 980 /* free already assigned IRQs */ 981 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 982 983 vector--; 984 for (i = 0; i < vector; i++) { 985 free_irq(adapter->msix_entries[free_vector++].vector, 986 adapter->q_vector[i]); 987 } 988 err_out: 989 return err; 990 } 991 992 /** 993 * igb_free_q_vector - Free memory allocated for specific interrupt vector 994 * @adapter: board private structure to initialize 995 * @v_idx: Index of vector to be freed 996 * 997 * This function frees the memory allocated to the q_vector. 998 **/ 999 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 1000 { 1001 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1002 1003 adapter->q_vector[v_idx] = NULL; 1004 1005 /* igb_get_stats64() might access the rings on this vector, 1006 * we must wait a grace period before freeing it. 1007 */ 1008 if (q_vector) 1009 kfree_rcu(q_vector, rcu); 1010 } 1011 1012 /** 1013 * igb_reset_q_vector - Reset config for interrupt vector 1014 * @adapter: board private structure to initialize 1015 * @v_idx: Index of vector to be reset 1016 * 1017 * If NAPI is enabled it will delete any references to the 1018 * NAPI struct. This is preparation for igb_free_q_vector. 1019 **/ 1020 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1021 { 1022 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1023 1024 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1025 * allocated. So, q_vector is NULL so we should stop here. 1026 */ 1027 if (!q_vector) 1028 return; 1029 1030 if (q_vector->tx.ring) 1031 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1032 1033 if (q_vector->rx.ring) 1034 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1035 1036 netif_napi_del(&q_vector->napi); 1037 1038 } 1039 1040 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1041 { 1042 int v_idx = adapter->num_q_vectors; 1043 1044 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1045 pci_disable_msix(adapter->pdev); 1046 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1047 pci_disable_msi(adapter->pdev); 1048 1049 while (v_idx--) 1050 igb_reset_q_vector(adapter, v_idx); 1051 } 1052 1053 /** 1054 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1055 * @adapter: board private structure to initialize 1056 * 1057 * This function frees the memory allocated to the q_vectors. In addition if 1058 * NAPI is enabled it will delete any references to the NAPI struct prior 1059 * to freeing the q_vector. 1060 **/ 1061 static void igb_free_q_vectors(struct igb_adapter *adapter) 1062 { 1063 int v_idx = adapter->num_q_vectors; 1064 1065 adapter->num_tx_queues = 0; 1066 adapter->num_rx_queues = 0; 1067 adapter->num_q_vectors = 0; 1068 1069 while (v_idx--) { 1070 igb_reset_q_vector(adapter, v_idx); 1071 igb_free_q_vector(adapter, v_idx); 1072 } 1073 } 1074 1075 /** 1076 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1077 * @adapter: board private structure to initialize 1078 * 1079 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1080 * MSI-X interrupts allocated. 1081 */ 1082 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1083 { 1084 igb_free_q_vectors(adapter); 1085 igb_reset_interrupt_capability(adapter); 1086 } 1087 1088 /** 1089 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1090 * @adapter: board private structure to initialize 1091 * @msix: boolean value of MSIX capability 1092 * 1093 * Attempt to configure interrupts using the best available 1094 * capabilities of the hardware and kernel. 1095 **/ 1096 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1097 { 1098 int err; 1099 int numvecs, i; 1100 1101 if (!msix) 1102 goto msi_only; 1103 adapter->flags |= IGB_FLAG_HAS_MSIX; 1104 1105 /* Number of supported queues. */ 1106 adapter->num_rx_queues = adapter->rss_queues; 1107 if (adapter->vfs_allocated_count) 1108 adapter->num_tx_queues = 1; 1109 else 1110 adapter->num_tx_queues = adapter->rss_queues; 1111 1112 /* start with one vector for every Rx queue */ 1113 numvecs = adapter->num_rx_queues; 1114 1115 /* if Tx handler is separate add 1 for every Tx queue */ 1116 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1117 numvecs += adapter->num_tx_queues; 1118 1119 /* store the number of vectors reserved for queues */ 1120 adapter->num_q_vectors = numvecs; 1121 1122 /* add 1 vector for link status interrupts */ 1123 numvecs++; 1124 for (i = 0; i < numvecs; i++) 1125 adapter->msix_entries[i].entry = i; 1126 1127 err = pci_enable_msix_range(adapter->pdev, 1128 adapter->msix_entries, 1129 numvecs, 1130 numvecs); 1131 if (err > 0) 1132 return; 1133 1134 igb_reset_interrupt_capability(adapter); 1135 1136 /* If we can't do MSI-X, try MSI */ 1137 msi_only: 1138 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1139 #ifdef CONFIG_PCI_IOV 1140 /* disable SR-IOV for non MSI-X configurations */ 1141 if (adapter->vf_data) { 1142 struct e1000_hw *hw = &adapter->hw; 1143 /* disable iov and allow time for transactions to clear */ 1144 pci_disable_sriov(adapter->pdev); 1145 msleep(500); 1146 1147 kfree(adapter->vf_mac_list); 1148 adapter->vf_mac_list = NULL; 1149 kfree(adapter->vf_data); 1150 adapter->vf_data = NULL; 1151 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1152 wrfl(); 1153 msleep(100); 1154 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1155 } 1156 #endif 1157 adapter->vfs_allocated_count = 0; 1158 adapter->rss_queues = 1; 1159 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1160 adapter->num_rx_queues = 1; 1161 adapter->num_tx_queues = 1; 1162 adapter->num_q_vectors = 1; 1163 if (!pci_enable_msi(adapter->pdev)) 1164 adapter->flags |= IGB_FLAG_HAS_MSI; 1165 } 1166 1167 static void igb_add_ring(struct igb_ring *ring, 1168 struct igb_ring_container *head) 1169 { 1170 head->ring = ring; 1171 head->count++; 1172 } 1173 1174 /** 1175 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1176 * @adapter: board private structure to initialize 1177 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1178 * @v_idx: index of vector in adapter struct 1179 * @txr_count: total number of Tx rings to allocate 1180 * @txr_idx: index of first Tx ring to allocate 1181 * @rxr_count: total number of Rx rings to allocate 1182 * @rxr_idx: index of first Rx ring to allocate 1183 * 1184 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1185 **/ 1186 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1187 int v_count, int v_idx, 1188 int txr_count, int txr_idx, 1189 int rxr_count, int rxr_idx) 1190 { 1191 struct igb_q_vector *q_vector; 1192 struct igb_ring *ring; 1193 int ring_count; 1194 size_t size; 1195 1196 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1197 if (txr_count > 1 || rxr_count > 1) 1198 return -ENOMEM; 1199 1200 ring_count = txr_count + rxr_count; 1201 size = struct_size(q_vector, ring, ring_count); 1202 1203 /* allocate q_vector and rings */ 1204 q_vector = adapter->q_vector[v_idx]; 1205 if (!q_vector) { 1206 q_vector = kzalloc(size, GFP_KERNEL); 1207 } else if (size > ksize(q_vector)) { 1208 kfree_rcu(q_vector, rcu); 1209 q_vector = kzalloc(size, GFP_KERNEL); 1210 } else { 1211 memset(q_vector, 0, size); 1212 } 1213 if (!q_vector) 1214 return -ENOMEM; 1215 1216 /* initialize NAPI */ 1217 netif_napi_add(adapter->netdev, &q_vector->napi, 1218 igb_poll, 64); 1219 1220 /* tie q_vector and adapter together */ 1221 adapter->q_vector[v_idx] = q_vector; 1222 q_vector->adapter = adapter; 1223 1224 /* initialize work limits */ 1225 q_vector->tx.work_limit = adapter->tx_work_limit; 1226 1227 /* initialize ITR configuration */ 1228 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1229 q_vector->itr_val = IGB_START_ITR; 1230 1231 /* initialize pointer to rings */ 1232 ring = q_vector->ring; 1233 1234 /* intialize ITR */ 1235 if (rxr_count) { 1236 /* rx or rx/tx vector */ 1237 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1238 q_vector->itr_val = adapter->rx_itr_setting; 1239 } else { 1240 /* tx only vector */ 1241 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1242 q_vector->itr_val = adapter->tx_itr_setting; 1243 } 1244 1245 if (txr_count) { 1246 /* assign generic ring traits */ 1247 ring->dev = &adapter->pdev->dev; 1248 ring->netdev = adapter->netdev; 1249 1250 /* configure backlink on ring */ 1251 ring->q_vector = q_vector; 1252 1253 /* update q_vector Tx values */ 1254 igb_add_ring(ring, &q_vector->tx); 1255 1256 /* For 82575, context index must be unique per ring. */ 1257 if (adapter->hw.mac.type == e1000_82575) 1258 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1259 1260 /* apply Tx specific ring traits */ 1261 ring->count = adapter->tx_ring_count; 1262 ring->queue_index = txr_idx; 1263 1264 ring->cbs_enable = false; 1265 ring->idleslope = 0; 1266 ring->sendslope = 0; 1267 ring->hicredit = 0; 1268 ring->locredit = 0; 1269 1270 u64_stats_init(&ring->tx_syncp); 1271 u64_stats_init(&ring->tx_syncp2); 1272 1273 /* assign ring to adapter */ 1274 adapter->tx_ring[txr_idx] = ring; 1275 1276 /* push pointer to next ring */ 1277 ring++; 1278 } 1279 1280 if (rxr_count) { 1281 /* assign generic ring traits */ 1282 ring->dev = &adapter->pdev->dev; 1283 ring->netdev = adapter->netdev; 1284 1285 /* configure backlink on ring */ 1286 ring->q_vector = q_vector; 1287 1288 /* update q_vector Rx values */ 1289 igb_add_ring(ring, &q_vector->rx); 1290 1291 /* set flag indicating ring supports SCTP checksum offload */ 1292 if (adapter->hw.mac.type >= e1000_82576) 1293 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1294 1295 /* On i350, i354, i210, and i211, loopback VLAN packets 1296 * have the tag byte-swapped. 1297 */ 1298 if (adapter->hw.mac.type >= e1000_i350) 1299 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1300 1301 /* apply Rx specific ring traits */ 1302 ring->count = adapter->rx_ring_count; 1303 ring->queue_index = rxr_idx; 1304 1305 u64_stats_init(&ring->rx_syncp); 1306 1307 /* assign ring to adapter */ 1308 adapter->rx_ring[rxr_idx] = ring; 1309 } 1310 1311 return 0; 1312 } 1313 1314 1315 /** 1316 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1317 * @adapter: board private structure to initialize 1318 * 1319 * We allocate one q_vector per queue interrupt. If allocation fails we 1320 * return -ENOMEM. 1321 **/ 1322 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1323 { 1324 int q_vectors = adapter->num_q_vectors; 1325 int rxr_remaining = adapter->num_rx_queues; 1326 int txr_remaining = adapter->num_tx_queues; 1327 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1328 int err; 1329 1330 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1331 for (; rxr_remaining; v_idx++) { 1332 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1333 0, 0, 1, rxr_idx); 1334 1335 if (err) 1336 goto err_out; 1337 1338 /* update counts and index */ 1339 rxr_remaining--; 1340 rxr_idx++; 1341 } 1342 } 1343 1344 for (; v_idx < q_vectors; v_idx++) { 1345 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1346 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1347 1348 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1349 tqpv, txr_idx, rqpv, rxr_idx); 1350 1351 if (err) 1352 goto err_out; 1353 1354 /* update counts and index */ 1355 rxr_remaining -= rqpv; 1356 txr_remaining -= tqpv; 1357 rxr_idx++; 1358 txr_idx++; 1359 } 1360 1361 return 0; 1362 1363 err_out: 1364 adapter->num_tx_queues = 0; 1365 adapter->num_rx_queues = 0; 1366 adapter->num_q_vectors = 0; 1367 1368 while (v_idx--) 1369 igb_free_q_vector(adapter, v_idx); 1370 1371 return -ENOMEM; 1372 } 1373 1374 /** 1375 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1376 * @adapter: board private structure to initialize 1377 * @msix: boolean value of MSIX capability 1378 * 1379 * This function initializes the interrupts and allocates all of the queues. 1380 **/ 1381 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1382 { 1383 struct pci_dev *pdev = adapter->pdev; 1384 int err; 1385 1386 igb_set_interrupt_capability(adapter, msix); 1387 1388 err = igb_alloc_q_vectors(adapter); 1389 if (err) { 1390 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1391 goto err_alloc_q_vectors; 1392 } 1393 1394 igb_cache_ring_register(adapter); 1395 1396 return 0; 1397 1398 err_alloc_q_vectors: 1399 igb_reset_interrupt_capability(adapter); 1400 return err; 1401 } 1402 1403 /** 1404 * igb_request_irq - initialize interrupts 1405 * @adapter: board private structure to initialize 1406 * 1407 * Attempts to configure interrupts using the best available 1408 * capabilities of the hardware and kernel. 1409 **/ 1410 static int igb_request_irq(struct igb_adapter *adapter) 1411 { 1412 struct net_device *netdev = adapter->netdev; 1413 struct pci_dev *pdev = adapter->pdev; 1414 int err = 0; 1415 1416 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1417 err = igb_request_msix(adapter); 1418 if (!err) 1419 goto request_done; 1420 /* fall back to MSI */ 1421 igb_free_all_tx_resources(adapter); 1422 igb_free_all_rx_resources(adapter); 1423 1424 igb_clear_interrupt_scheme(adapter); 1425 err = igb_init_interrupt_scheme(adapter, false); 1426 if (err) 1427 goto request_done; 1428 1429 igb_setup_all_tx_resources(adapter); 1430 igb_setup_all_rx_resources(adapter); 1431 igb_configure(adapter); 1432 } 1433 1434 igb_assign_vector(adapter->q_vector[0], 0); 1435 1436 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1437 err = request_irq(pdev->irq, igb_intr_msi, 0, 1438 netdev->name, adapter); 1439 if (!err) 1440 goto request_done; 1441 1442 /* fall back to legacy interrupts */ 1443 igb_reset_interrupt_capability(adapter); 1444 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1445 } 1446 1447 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1448 netdev->name, adapter); 1449 1450 if (err) 1451 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1452 err); 1453 1454 request_done: 1455 return err; 1456 } 1457 1458 static void igb_free_irq(struct igb_adapter *adapter) 1459 { 1460 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1461 int vector = 0, i; 1462 1463 free_irq(adapter->msix_entries[vector++].vector, adapter); 1464 1465 for (i = 0; i < adapter->num_q_vectors; i++) 1466 free_irq(adapter->msix_entries[vector++].vector, 1467 adapter->q_vector[i]); 1468 } else { 1469 free_irq(adapter->pdev->irq, adapter); 1470 } 1471 } 1472 1473 /** 1474 * igb_irq_disable - Mask off interrupt generation on the NIC 1475 * @adapter: board private structure 1476 **/ 1477 static void igb_irq_disable(struct igb_adapter *adapter) 1478 { 1479 struct e1000_hw *hw = &adapter->hw; 1480 1481 /* we need to be careful when disabling interrupts. The VFs are also 1482 * mapped into these registers and so clearing the bits can cause 1483 * issues on the VF drivers so we only need to clear what we set 1484 */ 1485 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1486 u32 regval = rd32(E1000_EIAM); 1487 1488 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1489 wr32(E1000_EIMC, adapter->eims_enable_mask); 1490 regval = rd32(E1000_EIAC); 1491 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1492 } 1493 1494 wr32(E1000_IAM, 0); 1495 wr32(E1000_IMC, ~0); 1496 wrfl(); 1497 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1498 int i; 1499 1500 for (i = 0; i < adapter->num_q_vectors; i++) 1501 synchronize_irq(adapter->msix_entries[i].vector); 1502 } else { 1503 synchronize_irq(adapter->pdev->irq); 1504 } 1505 } 1506 1507 /** 1508 * igb_irq_enable - Enable default interrupt generation settings 1509 * @adapter: board private structure 1510 **/ 1511 static void igb_irq_enable(struct igb_adapter *adapter) 1512 { 1513 struct e1000_hw *hw = &adapter->hw; 1514 1515 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1516 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1517 u32 regval = rd32(E1000_EIAC); 1518 1519 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1520 regval = rd32(E1000_EIAM); 1521 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1522 wr32(E1000_EIMS, adapter->eims_enable_mask); 1523 if (adapter->vfs_allocated_count) { 1524 wr32(E1000_MBVFIMR, 0xFF); 1525 ims |= E1000_IMS_VMMB; 1526 } 1527 wr32(E1000_IMS, ims); 1528 } else { 1529 wr32(E1000_IMS, IMS_ENABLE_MASK | 1530 E1000_IMS_DRSTA); 1531 wr32(E1000_IAM, IMS_ENABLE_MASK | 1532 E1000_IMS_DRSTA); 1533 } 1534 } 1535 1536 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1537 { 1538 struct e1000_hw *hw = &adapter->hw; 1539 u16 pf_id = adapter->vfs_allocated_count; 1540 u16 vid = adapter->hw.mng_cookie.vlan_id; 1541 u16 old_vid = adapter->mng_vlan_id; 1542 1543 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1544 /* add VID to filter table */ 1545 igb_vfta_set(hw, vid, pf_id, true, true); 1546 adapter->mng_vlan_id = vid; 1547 } else { 1548 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1549 } 1550 1551 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1552 (vid != old_vid) && 1553 !test_bit(old_vid, adapter->active_vlans)) { 1554 /* remove VID from filter table */ 1555 igb_vfta_set(hw, vid, pf_id, false, true); 1556 } 1557 } 1558 1559 /** 1560 * igb_release_hw_control - release control of the h/w to f/w 1561 * @adapter: address of board private structure 1562 * 1563 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1564 * For ASF and Pass Through versions of f/w this means that the 1565 * driver is no longer loaded. 1566 **/ 1567 static void igb_release_hw_control(struct igb_adapter *adapter) 1568 { 1569 struct e1000_hw *hw = &adapter->hw; 1570 u32 ctrl_ext; 1571 1572 /* Let firmware take over control of h/w */ 1573 ctrl_ext = rd32(E1000_CTRL_EXT); 1574 wr32(E1000_CTRL_EXT, 1575 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1576 } 1577 1578 /** 1579 * igb_get_hw_control - get control of the h/w from f/w 1580 * @adapter: address of board private structure 1581 * 1582 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1583 * For ASF and Pass Through versions of f/w this means that 1584 * the driver is loaded. 1585 **/ 1586 static void igb_get_hw_control(struct igb_adapter *adapter) 1587 { 1588 struct e1000_hw *hw = &adapter->hw; 1589 u32 ctrl_ext; 1590 1591 /* Let firmware know the driver has taken over */ 1592 ctrl_ext = rd32(E1000_CTRL_EXT); 1593 wr32(E1000_CTRL_EXT, 1594 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1595 } 1596 1597 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1598 { 1599 struct net_device *netdev = adapter->netdev; 1600 struct e1000_hw *hw = &adapter->hw; 1601 1602 WARN_ON(hw->mac.type != e1000_i210); 1603 1604 if (enable) 1605 adapter->flags |= IGB_FLAG_FQTSS; 1606 else 1607 adapter->flags &= ~IGB_FLAG_FQTSS; 1608 1609 if (netif_running(netdev)) 1610 schedule_work(&adapter->reset_task); 1611 } 1612 1613 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1614 { 1615 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1616 } 1617 1618 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1619 enum tx_queue_prio prio) 1620 { 1621 u32 val; 1622 1623 WARN_ON(hw->mac.type != e1000_i210); 1624 WARN_ON(queue < 0 || queue > 4); 1625 1626 val = rd32(E1000_I210_TXDCTL(queue)); 1627 1628 if (prio == TX_QUEUE_PRIO_HIGH) 1629 val |= E1000_TXDCTL_PRIORITY; 1630 else 1631 val &= ~E1000_TXDCTL_PRIORITY; 1632 1633 wr32(E1000_I210_TXDCTL(queue), val); 1634 } 1635 1636 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1637 { 1638 u32 val; 1639 1640 WARN_ON(hw->mac.type != e1000_i210); 1641 WARN_ON(queue < 0 || queue > 1); 1642 1643 val = rd32(E1000_I210_TQAVCC(queue)); 1644 1645 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1646 val |= E1000_TQAVCC_QUEUEMODE; 1647 else 1648 val &= ~E1000_TQAVCC_QUEUEMODE; 1649 1650 wr32(E1000_I210_TQAVCC(queue), val); 1651 } 1652 1653 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1654 { 1655 int i; 1656 1657 for (i = 0; i < adapter->num_tx_queues; i++) { 1658 if (adapter->tx_ring[i]->cbs_enable) 1659 return true; 1660 } 1661 1662 return false; 1663 } 1664 1665 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1666 { 1667 int i; 1668 1669 for (i = 0; i < adapter->num_tx_queues; i++) { 1670 if (adapter->tx_ring[i]->launchtime_enable) 1671 return true; 1672 } 1673 1674 return false; 1675 } 1676 1677 /** 1678 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1679 * @adapter: pointer to adapter struct 1680 * @queue: queue number 1681 * 1682 * Configure CBS and Launchtime for a given hardware queue. 1683 * Parameters are retrieved from the correct Tx ring, so 1684 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1685 * for setting those correctly prior to this function being called. 1686 **/ 1687 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1688 { 1689 struct igb_ring *ring = adapter->tx_ring[queue]; 1690 struct net_device *netdev = adapter->netdev; 1691 struct e1000_hw *hw = &adapter->hw; 1692 u32 tqavcc, tqavctrl; 1693 u16 value; 1694 1695 WARN_ON(hw->mac.type != e1000_i210); 1696 WARN_ON(queue < 0 || queue > 1); 1697 1698 /* If any of the Qav features is enabled, configure queues as SR and 1699 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1700 * as SP. 1701 */ 1702 if (ring->cbs_enable || ring->launchtime_enable) { 1703 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1704 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1705 } else { 1706 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1707 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1708 } 1709 1710 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1711 if (ring->cbs_enable || queue == 0) { 1712 /* i210 does not allow the queue 0 to be in the Strict 1713 * Priority mode while the Qav mode is enabled, so, 1714 * instead of disabling strict priority mode, we give 1715 * queue 0 the maximum of credits possible. 1716 * 1717 * See section 8.12.19 of the i210 datasheet, "Note: 1718 * Queue0 QueueMode must be set to 1b when 1719 * TransmitMode is set to Qav." 1720 */ 1721 if (queue == 0 && !ring->cbs_enable) { 1722 /* max "linkspeed" idleslope in kbps */ 1723 ring->idleslope = 1000000; 1724 ring->hicredit = ETH_FRAME_LEN; 1725 } 1726 1727 /* Always set data transfer arbitration to credit-based 1728 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1729 * the queues. 1730 */ 1731 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1732 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1733 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1734 1735 /* According to i210 datasheet section 7.2.7.7, we should set 1736 * the 'idleSlope' field from TQAVCC register following the 1737 * equation: 1738 * 1739 * For 100 Mbps link speed: 1740 * 1741 * value = BW * 0x7735 * 0.2 (E1) 1742 * 1743 * For 1000Mbps link speed: 1744 * 1745 * value = BW * 0x7735 * 2 (E2) 1746 * 1747 * E1 and E2 can be merged into one equation as shown below. 1748 * Note that 'link-speed' is in Mbps. 1749 * 1750 * value = BW * 0x7735 * 2 * link-speed 1751 * -------------- (E3) 1752 * 1000 1753 * 1754 * 'BW' is the percentage bandwidth out of full link speed 1755 * which can be found with the following equation. Note that 1756 * idleSlope here is the parameter from this function which 1757 * is in kbps. 1758 * 1759 * BW = idleSlope 1760 * ----------------- (E4) 1761 * link-speed * 1000 1762 * 1763 * That said, we can come up with a generic equation to 1764 * calculate the value we should set it TQAVCC register by 1765 * replacing 'BW' in E3 by E4. The resulting equation is: 1766 * 1767 * value = idleSlope * 0x7735 * 2 * link-speed 1768 * ----------------- -------------- (E5) 1769 * link-speed * 1000 1000 1770 * 1771 * 'link-speed' is present in both sides of the fraction so 1772 * it is canceled out. The final equation is the following: 1773 * 1774 * value = idleSlope * 61034 1775 * ----------------- (E6) 1776 * 1000000 1777 * 1778 * NOTE: For i210, given the above, we can see that idleslope 1779 * is represented in 16.38431 kbps units by the value at 1780 * the TQAVCC register (1Gbps / 61034), which reduces 1781 * the granularity for idleslope increments. 1782 * For instance, if you want to configure a 2576kbps 1783 * idleslope, the value to be written on the register 1784 * would have to be 157.23. If rounded down, you end 1785 * up with less bandwidth available than originally 1786 * required (~2572 kbps). If rounded up, you end up 1787 * with a higher bandwidth (~2589 kbps). Below the 1788 * approach we take is to always round up the 1789 * calculated value, so the resulting bandwidth might 1790 * be slightly higher for some configurations. 1791 */ 1792 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1793 1794 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1795 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1796 tqavcc |= value; 1797 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1798 1799 wr32(E1000_I210_TQAVHC(queue), 1800 0x80000000 + ring->hicredit * 0x7735); 1801 } else { 1802 1803 /* Set idleSlope to zero. */ 1804 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1805 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1806 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1807 1808 /* Set hiCredit to zero. */ 1809 wr32(E1000_I210_TQAVHC(queue), 0); 1810 1811 /* If CBS is not enabled for any queues anymore, then return to 1812 * the default state of Data Transmission Arbitration on 1813 * TQAVCTRL. 1814 */ 1815 if (!is_any_cbs_enabled(adapter)) { 1816 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1817 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1818 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1819 } 1820 } 1821 1822 /* If LaunchTime is enabled, set DataTranTIM. */ 1823 if (ring->launchtime_enable) { 1824 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1825 * for any of the SR queues, and configure fetchtime delta. 1826 * XXX NOTE: 1827 * - LaunchTime will be enabled for all SR queues. 1828 * - A fixed offset can be added relative to the launch 1829 * time of all packets if configured at reg LAUNCH_OS0. 1830 * We are keeping it as 0 for now (default value). 1831 */ 1832 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1833 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1834 E1000_TQAVCTRL_FETCHTIME_DELTA; 1835 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1836 } else { 1837 /* If Launchtime is not enabled for any SR queues anymore, 1838 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1839 * effectively disabling Launchtime. 1840 */ 1841 if (!is_any_txtime_enabled(adapter)) { 1842 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1843 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1844 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1845 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1846 } 1847 } 1848 1849 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1850 * CBS are not configurable by software so we don't do any 'controller 1851 * configuration' in respect to these parameters. 1852 */ 1853 1854 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1855 ring->cbs_enable ? "enabled" : "disabled", 1856 ring->launchtime_enable ? "enabled" : "disabled", 1857 queue, 1858 ring->idleslope, ring->sendslope, 1859 ring->hicredit, ring->locredit); 1860 } 1861 1862 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1863 bool enable) 1864 { 1865 struct igb_ring *ring; 1866 1867 if (queue < 0 || queue > adapter->num_tx_queues) 1868 return -EINVAL; 1869 1870 ring = adapter->tx_ring[queue]; 1871 ring->launchtime_enable = enable; 1872 1873 return 0; 1874 } 1875 1876 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1877 bool enable, int idleslope, int sendslope, 1878 int hicredit, int locredit) 1879 { 1880 struct igb_ring *ring; 1881 1882 if (queue < 0 || queue > adapter->num_tx_queues) 1883 return -EINVAL; 1884 1885 ring = adapter->tx_ring[queue]; 1886 1887 ring->cbs_enable = enable; 1888 ring->idleslope = idleslope; 1889 ring->sendslope = sendslope; 1890 ring->hicredit = hicredit; 1891 ring->locredit = locredit; 1892 1893 return 0; 1894 } 1895 1896 /** 1897 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1898 * @adapter: pointer to adapter struct 1899 * 1900 * Configure TQAVCTRL register switching the controller's Tx mode 1901 * if FQTSS mode is enabled or disabled. Additionally, will issue 1902 * a call to igb_config_tx_modes() per queue so any previously saved 1903 * Tx parameters are applied. 1904 **/ 1905 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1906 { 1907 struct net_device *netdev = adapter->netdev; 1908 struct e1000_hw *hw = &adapter->hw; 1909 u32 val; 1910 1911 /* Only i210 controller supports changing the transmission mode. */ 1912 if (hw->mac.type != e1000_i210) 1913 return; 1914 1915 if (is_fqtss_enabled(adapter)) { 1916 int i, max_queue; 1917 1918 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1919 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1920 * so SP queues wait for SR ones. 1921 */ 1922 val = rd32(E1000_I210_TQAVCTRL); 1923 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1924 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1925 wr32(E1000_I210_TQAVCTRL, val); 1926 1927 /* Configure Tx and Rx packet buffers sizes as described in 1928 * i210 datasheet section 7.2.7.7. 1929 */ 1930 val = rd32(E1000_TXPBS); 1931 val &= ~I210_TXPBSIZE_MASK; 1932 val |= I210_TXPBSIZE_PB0_8KB | I210_TXPBSIZE_PB1_8KB | 1933 I210_TXPBSIZE_PB2_4KB | I210_TXPBSIZE_PB3_4KB; 1934 wr32(E1000_TXPBS, val); 1935 1936 val = rd32(E1000_RXPBS); 1937 val &= ~I210_RXPBSIZE_MASK; 1938 val |= I210_RXPBSIZE_PB_30KB; 1939 wr32(E1000_RXPBS, val); 1940 1941 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1942 * register should not exceed the buffer size programmed in 1943 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1944 * so according to the datasheet we should set MAX_TPKT_SIZE to 1945 * 4kB / 64. 1946 * 1947 * However, when we do so, no frame from queue 2 and 3 are 1948 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1949 * or _equal_ to the buffer size programmed in TXPBS. For this 1950 * reason, we set set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1951 */ 1952 val = (4096 - 1) / 64; 1953 wr32(E1000_I210_DTXMXPKTSZ, val); 1954 1955 /* Since FQTSS mode is enabled, apply any CBS configuration 1956 * previously set. If no previous CBS configuration has been 1957 * done, then the initial configuration is applied, which means 1958 * CBS is disabled. 1959 */ 1960 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1961 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1962 1963 for (i = 0; i < max_queue; i++) { 1964 igb_config_tx_modes(adapter, i); 1965 } 1966 } else { 1967 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1968 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1969 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1970 1971 val = rd32(E1000_I210_TQAVCTRL); 1972 /* According to Section 8.12.21, the other flags we've set when 1973 * enabling FQTSS are not relevant when disabling FQTSS so we 1974 * don't set they here. 1975 */ 1976 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1977 wr32(E1000_I210_TQAVCTRL, val); 1978 } 1979 1980 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1981 "enabled" : "disabled"); 1982 } 1983 1984 /** 1985 * igb_configure - configure the hardware for RX and TX 1986 * @adapter: private board structure 1987 **/ 1988 static void igb_configure(struct igb_adapter *adapter) 1989 { 1990 struct net_device *netdev = adapter->netdev; 1991 int i; 1992 1993 igb_get_hw_control(adapter); 1994 igb_set_rx_mode(netdev); 1995 igb_setup_tx_mode(adapter); 1996 1997 igb_restore_vlan(adapter); 1998 1999 igb_setup_tctl(adapter); 2000 igb_setup_mrqc(adapter); 2001 igb_setup_rctl(adapter); 2002 2003 igb_nfc_filter_restore(adapter); 2004 igb_configure_tx(adapter); 2005 igb_configure_rx(adapter); 2006 2007 igb_rx_fifo_flush_82575(&adapter->hw); 2008 2009 /* call igb_desc_unused which always leaves 2010 * at least 1 descriptor unused to make sure 2011 * next_to_use != next_to_clean 2012 */ 2013 for (i = 0; i < adapter->num_rx_queues; i++) { 2014 struct igb_ring *ring = adapter->rx_ring[i]; 2015 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 2016 } 2017 } 2018 2019 /** 2020 * igb_power_up_link - Power up the phy/serdes link 2021 * @adapter: address of board private structure 2022 **/ 2023 void igb_power_up_link(struct igb_adapter *adapter) 2024 { 2025 igb_reset_phy(&adapter->hw); 2026 2027 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2028 igb_power_up_phy_copper(&adapter->hw); 2029 else 2030 igb_power_up_serdes_link_82575(&adapter->hw); 2031 2032 igb_setup_link(&adapter->hw); 2033 } 2034 2035 /** 2036 * igb_power_down_link - Power down the phy/serdes link 2037 * @adapter: address of board private structure 2038 */ 2039 static void igb_power_down_link(struct igb_adapter *adapter) 2040 { 2041 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2042 igb_power_down_phy_copper_82575(&adapter->hw); 2043 else 2044 igb_shutdown_serdes_link_82575(&adapter->hw); 2045 } 2046 2047 /** 2048 * Detect and switch function for Media Auto Sense 2049 * @adapter: address of the board private structure 2050 **/ 2051 static void igb_check_swap_media(struct igb_adapter *adapter) 2052 { 2053 struct e1000_hw *hw = &adapter->hw; 2054 u32 ctrl_ext, connsw; 2055 bool swap_now = false; 2056 2057 ctrl_ext = rd32(E1000_CTRL_EXT); 2058 connsw = rd32(E1000_CONNSW); 2059 2060 /* need to live swap if current media is copper and we have fiber/serdes 2061 * to go to. 2062 */ 2063 2064 if ((hw->phy.media_type == e1000_media_type_copper) && 2065 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2066 swap_now = true; 2067 } else if (!(connsw & E1000_CONNSW_SERDESD)) { 2068 /* copper signal takes time to appear */ 2069 if (adapter->copper_tries < 4) { 2070 adapter->copper_tries++; 2071 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2072 wr32(E1000_CONNSW, connsw); 2073 return; 2074 } else { 2075 adapter->copper_tries = 0; 2076 if ((connsw & E1000_CONNSW_PHYSD) && 2077 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2078 swap_now = true; 2079 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2080 wr32(E1000_CONNSW, connsw); 2081 } 2082 } 2083 } 2084 2085 if (!swap_now) 2086 return; 2087 2088 switch (hw->phy.media_type) { 2089 case e1000_media_type_copper: 2090 netdev_info(adapter->netdev, 2091 "MAS: changing media to fiber/serdes\n"); 2092 ctrl_ext |= 2093 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2094 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2095 adapter->copper_tries = 0; 2096 break; 2097 case e1000_media_type_internal_serdes: 2098 case e1000_media_type_fiber: 2099 netdev_info(adapter->netdev, 2100 "MAS: changing media to copper\n"); 2101 ctrl_ext &= 2102 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2103 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2104 break; 2105 default: 2106 /* shouldn't get here during regular operation */ 2107 netdev_err(adapter->netdev, 2108 "AMS: Invalid media type found, returning\n"); 2109 break; 2110 } 2111 wr32(E1000_CTRL_EXT, ctrl_ext); 2112 } 2113 2114 /** 2115 * igb_up - Open the interface and prepare it to handle traffic 2116 * @adapter: board private structure 2117 **/ 2118 int igb_up(struct igb_adapter *adapter) 2119 { 2120 struct e1000_hw *hw = &adapter->hw; 2121 int i; 2122 2123 /* hardware has been reset, we need to reload some things */ 2124 igb_configure(adapter); 2125 2126 clear_bit(__IGB_DOWN, &adapter->state); 2127 2128 for (i = 0; i < adapter->num_q_vectors; i++) 2129 napi_enable(&(adapter->q_vector[i]->napi)); 2130 2131 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2132 igb_configure_msix(adapter); 2133 else 2134 igb_assign_vector(adapter->q_vector[0], 0); 2135 2136 /* Clear any pending interrupts. */ 2137 rd32(E1000_TSICR); 2138 rd32(E1000_ICR); 2139 igb_irq_enable(adapter); 2140 2141 /* notify VFs that reset has been completed */ 2142 if (adapter->vfs_allocated_count) { 2143 u32 reg_data = rd32(E1000_CTRL_EXT); 2144 2145 reg_data |= E1000_CTRL_EXT_PFRSTD; 2146 wr32(E1000_CTRL_EXT, reg_data); 2147 } 2148 2149 netif_tx_start_all_queues(adapter->netdev); 2150 2151 /* start the watchdog. */ 2152 hw->mac.get_link_status = 1; 2153 schedule_work(&adapter->watchdog_task); 2154 2155 if ((adapter->flags & IGB_FLAG_EEE) && 2156 (!hw->dev_spec._82575.eee_disable)) 2157 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2158 2159 return 0; 2160 } 2161 2162 void igb_down(struct igb_adapter *adapter) 2163 { 2164 struct net_device *netdev = adapter->netdev; 2165 struct e1000_hw *hw = &adapter->hw; 2166 u32 tctl, rctl; 2167 int i; 2168 2169 /* signal that we're down so the interrupt handler does not 2170 * reschedule our watchdog timer 2171 */ 2172 set_bit(__IGB_DOWN, &adapter->state); 2173 2174 /* disable receives in the hardware */ 2175 rctl = rd32(E1000_RCTL); 2176 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2177 /* flush and sleep below */ 2178 2179 igb_nfc_filter_exit(adapter); 2180 2181 netif_carrier_off(netdev); 2182 netif_tx_stop_all_queues(netdev); 2183 2184 /* disable transmits in the hardware */ 2185 tctl = rd32(E1000_TCTL); 2186 tctl &= ~E1000_TCTL_EN; 2187 wr32(E1000_TCTL, tctl); 2188 /* flush both disables and wait for them to finish */ 2189 wrfl(); 2190 usleep_range(10000, 11000); 2191 2192 igb_irq_disable(adapter); 2193 2194 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2195 2196 for (i = 0; i < adapter->num_q_vectors; i++) { 2197 if (adapter->q_vector[i]) { 2198 napi_synchronize(&adapter->q_vector[i]->napi); 2199 napi_disable(&adapter->q_vector[i]->napi); 2200 } 2201 } 2202 2203 del_timer_sync(&adapter->watchdog_timer); 2204 del_timer_sync(&adapter->phy_info_timer); 2205 2206 /* record the stats before reset*/ 2207 spin_lock(&adapter->stats64_lock); 2208 igb_update_stats(adapter); 2209 spin_unlock(&adapter->stats64_lock); 2210 2211 adapter->link_speed = 0; 2212 adapter->link_duplex = 0; 2213 2214 if (!pci_channel_offline(adapter->pdev)) 2215 igb_reset(adapter); 2216 2217 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2218 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2219 2220 igb_clean_all_tx_rings(adapter); 2221 igb_clean_all_rx_rings(adapter); 2222 #ifdef CONFIG_IGB_DCA 2223 2224 /* since we reset the hardware DCA settings were cleared */ 2225 igb_setup_dca(adapter); 2226 #endif 2227 } 2228 2229 void igb_reinit_locked(struct igb_adapter *adapter) 2230 { 2231 WARN_ON(in_interrupt()); 2232 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2233 usleep_range(1000, 2000); 2234 igb_down(adapter); 2235 igb_up(adapter); 2236 clear_bit(__IGB_RESETTING, &adapter->state); 2237 } 2238 2239 /** igb_enable_mas - Media Autosense re-enable after swap 2240 * 2241 * @adapter: adapter struct 2242 **/ 2243 static void igb_enable_mas(struct igb_adapter *adapter) 2244 { 2245 struct e1000_hw *hw = &adapter->hw; 2246 u32 connsw = rd32(E1000_CONNSW); 2247 2248 /* configure for SerDes media detect */ 2249 if ((hw->phy.media_type == e1000_media_type_copper) && 2250 (!(connsw & E1000_CONNSW_SERDESD))) { 2251 connsw |= E1000_CONNSW_ENRGSRC; 2252 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2253 wr32(E1000_CONNSW, connsw); 2254 wrfl(); 2255 } 2256 } 2257 2258 void igb_reset(struct igb_adapter *adapter) 2259 { 2260 struct pci_dev *pdev = adapter->pdev; 2261 struct e1000_hw *hw = &adapter->hw; 2262 struct e1000_mac_info *mac = &hw->mac; 2263 struct e1000_fc_info *fc = &hw->fc; 2264 u32 pba, hwm; 2265 2266 /* Repartition Pba for greater than 9k mtu 2267 * To take effect CTRL.RST is required. 2268 */ 2269 switch (mac->type) { 2270 case e1000_i350: 2271 case e1000_i354: 2272 case e1000_82580: 2273 pba = rd32(E1000_RXPBS); 2274 pba = igb_rxpbs_adjust_82580(pba); 2275 break; 2276 case e1000_82576: 2277 pba = rd32(E1000_RXPBS); 2278 pba &= E1000_RXPBS_SIZE_MASK_82576; 2279 break; 2280 case e1000_82575: 2281 case e1000_i210: 2282 case e1000_i211: 2283 default: 2284 pba = E1000_PBA_34K; 2285 break; 2286 } 2287 2288 if (mac->type == e1000_82575) { 2289 u32 min_rx_space, min_tx_space, needed_tx_space; 2290 2291 /* write Rx PBA so that hardware can report correct Tx PBA */ 2292 wr32(E1000_PBA, pba); 2293 2294 /* To maintain wire speed transmits, the Tx FIFO should be 2295 * large enough to accommodate two full transmit packets, 2296 * rounded up to the next 1KB and expressed in KB. Likewise, 2297 * the Rx FIFO should be large enough to accommodate at least 2298 * one full receive packet and is similarly rounded up and 2299 * expressed in KB. 2300 */ 2301 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2302 2303 /* The Tx FIFO also stores 16 bytes of information about the Tx 2304 * but don't include Ethernet FCS because hardware appends it. 2305 * We only need to round down to the nearest 512 byte block 2306 * count since the value we care about is 2 frames, not 1. 2307 */ 2308 min_tx_space = adapter->max_frame_size; 2309 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2310 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2311 2312 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2313 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2314 2315 /* If current Tx allocation is less than the min Tx FIFO size, 2316 * and the min Tx FIFO size is less than the current Rx FIFO 2317 * allocation, take space away from current Rx allocation. 2318 */ 2319 if (needed_tx_space < pba) { 2320 pba -= needed_tx_space; 2321 2322 /* if short on Rx space, Rx wins and must trump Tx 2323 * adjustment 2324 */ 2325 if (pba < min_rx_space) 2326 pba = min_rx_space; 2327 } 2328 2329 /* adjust PBA for jumbo frames */ 2330 wr32(E1000_PBA, pba); 2331 } 2332 2333 /* flow control settings 2334 * The high water mark must be low enough to fit one full frame 2335 * after transmitting the pause frame. As such we must have enough 2336 * space to allow for us to complete our current transmit and then 2337 * receive the frame that is in progress from the link partner. 2338 * Set it to: 2339 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2340 */ 2341 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2342 2343 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2344 fc->low_water = fc->high_water - 16; 2345 fc->pause_time = 0xFFFF; 2346 fc->send_xon = 1; 2347 fc->current_mode = fc->requested_mode; 2348 2349 /* disable receive for all VFs and wait one second */ 2350 if (adapter->vfs_allocated_count) { 2351 int i; 2352 2353 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2354 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2355 2356 /* ping all the active vfs to let them know we are going down */ 2357 igb_ping_all_vfs(adapter); 2358 2359 /* disable transmits and receives */ 2360 wr32(E1000_VFRE, 0); 2361 wr32(E1000_VFTE, 0); 2362 } 2363 2364 /* Allow time for pending master requests to run */ 2365 hw->mac.ops.reset_hw(hw); 2366 wr32(E1000_WUC, 0); 2367 2368 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2369 /* need to resetup here after media swap */ 2370 adapter->ei.get_invariants(hw); 2371 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2372 } 2373 if ((mac->type == e1000_82575) && 2374 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2375 igb_enable_mas(adapter); 2376 } 2377 if (hw->mac.ops.init_hw(hw)) 2378 dev_err(&pdev->dev, "Hardware Error\n"); 2379 2380 /* RAR registers were cleared during init_hw, clear mac table */ 2381 igb_flush_mac_table(adapter); 2382 __dev_uc_unsync(adapter->netdev, NULL); 2383 2384 /* Recover default RAR entry */ 2385 igb_set_default_mac_filter(adapter); 2386 2387 /* Flow control settings reset on hardware reset, so guarantee flow 2388 * control is off when forcing speed. 2389 */ 2390 if (!hw->mac.autoneg) 2391 igb_force_mac_fc(hw); 2392 2393 igb_init_dmac(adapter, pba); 2394 #ifdef CONFIG_IGB_HWMON 2395 /* Re-initialize the thermal sensor on i350 devices. */ 2396 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2397 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2398 /* If present, re-initialize the external thermal sensor 2399 * interface. 2400 */ 2401 if (adapter->ets) 2402 mac->ops.init_thermal_sensor_thresh(hw); 2403 } 2404 } 2405 #endif 2406 /* Re-establish EEE setting */ 2407 if (hw->phy.media_type == e1000_media_type_copper) { 2408 switch (mac->type) { 2409 case e1000_i350: 2410 case e1000_i210: 2411 case e1000_i211: 2412 igb_set_eee_i350(hw, true, true); 2413 break; 2414 case e1000_i354: 2415 igb_set_eee_i354(hw, true, true); 2416 break; 2417 default: 2418 break; 2419 } 2420 } 2421 if (!netif_running(adapter->netdev)) 2422 igb_power_down_link(adapter); 2423 2424 igb_update_mng_vlan(adapter); 2425 2426 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2427 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2428 2429 /* Re-enable PTP, where applicable. */ 2430 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2431 igb_ptp_reset(adapter); 2432 2433 igb_get_phy_info(hw); 2434 } 2435 2436 static netdev_features_t igb_fix_features(struct net_device *netdev, 2437 netdev_features_t features) 2438 { 2439 /* Since there is no support for separate Rx/Tx vlan accel 2440 * enable/disable make sure Tx flag is always in same state as Rx. 2441 */ 2442 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2443 features |= NETIF_F_HW_VLAN_CTAG_TX; 2444 else 2445 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2446 2447 return features; 2448 } 2449 2450 static int igb_set_features(struct net_device *netdev, 2451 netdev_features_t features) 2452 { 2453 netdev_features_t changed = netdev->features ^ features; 2454 struct igb_adapter *adapter = netdev_priv(netdev); 2455 2456 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2457 igb_vlan_mode(netdev, features); 2458 2459 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2460 return 0; 2461 2462 if (!(features & NETIF_F_NTUPLE)) { 2463 struct hlist_node *node2; 2464 struct igb_nfc_filter *rule; 2465 2466 spin_lock(&adapter->nfc_lock); 2467 hlist_for_each_entry_safe(rule, node2, 2468 &adapter->nfc_filter_list, nfc_node) { 2469 igb_erase_filter(adapter, rule); 2470 hlist_del(&rule->nfc_node); 2471 kfree(rule); 2472 } 2473 spin_unlock(&adapter->nfc_lock); 2474 adapter->nfc_filter_count = 0; 2475 } 2476 2477 netdev->features = features; 2478 2479 if (netif_running(netdev)) 2480 igb_reinit_locked(adapter); 2481 else 2482 igb_reset(adapter); 2483 2484 return 1; 2485 } 2486 2487 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2488 struct net_device *dev, 2489 const unsigned char *addr, u16 vid, 2490 u16 flags, 2491 struct netlink_ext_ack *extack) 2492 { 2493 /* guarantee we can provide a unique filter for the unicast address */ 2494 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2495 struct igb_adapter *adapter = netdev_priv(dev); 2496 int vfn = adapter->vfs_allocated_count; 2497 2498 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2499 return -ENOMEM; 2500 } 2501 2502 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2503 } 2504 2505 #define IGB_MAX_MAC_HDR_LEN 127 2506 #define IGB_MAX_NETWORK_HDR_LEN 511 2507 2508 static netdev_features_t 2509 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2510 netdev_features_t features) 2511 { 2512 unsigned int network_hdr_len, mac_hdr_len; 2513 2514 /* Make certain the headers can be described by a context descriptor */ 2515 mac_hdr_len = skb_network_header(skb) - skb->data; 2516 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2517 return features & ~(NETIF_F_HW_CSUM | 2518 NETIF_F_SCTP_CRC | 2519 NETIF_F_HW_VLAN_CTAG_TX | 2520 NETIF_F_TSO | 2521 NETIF_F_TSO6); 2522 2523 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2524 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2525 return features & ~(NETIF_F_HW_CSUM | 2526 NETIF_F_SCTP_CRC | 2527 NETIF_F_TSO | 2528 NETIF_F_TSO6); 2529 2530 /* We can only support IPV4 TSO in tunnels if we can mangle the 2531 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2532 */ 2533 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2534 features &= ~NETIF_F_TSO; 2535 2536 return features; 2537 } 2538 2539 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2540 { 2541 if (!is_fqtss_enabled(adapter)) { 2542 enable_fqtss(adapter, true); 2543 return; 2544 } 2545 2546 igb_config_tx_modes(adapter, queue); 2547 2548 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2549 enable_fqtss(adapter, false); 2550 } 2551 2552 static int igb_offload_cbs(struct igb_adapter *adapter, 2553 struct tc_cbs_qopt_offload *qopt) 2554 { 2555 struct e1000_hw *hw = &adapter->hw; 2556 int err; 2557 2558 /* CBS offloading is only supported by i210 controller. */ 2559 if (hw->mac.type != e1000_i210) 2560 return -EOPNOTSUPP; 2561 2562 /* CBS offloading is only supported by queue 0 and queue 1. */ 2563 if (qopt->queue < 0 || qopt->queue > 1) 2564 return -EINVAL; 2565 2566 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2567 qopt->idleslope, qopt->sendslope, 2568 qopt->hicredit, qopt->locredit); 2569 if (err) 2570 return err; 2571 2572 igb_offload_apply(adapter, qopt->queue); 2573 2574 return 0; 2575 } 2576 2577 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2578 #define VLAN_PRIO_FULL_MASK (0x07) 2579 2580 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2581 struct tc_cls_flower_offload *f, 2582 int traffic_class, 2583 struct igb_nfc_filter *input) 2584 { 2585 struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f); 2586 struct flow_dissector *dissector = rule->match.dissector; 2587 struct netlink_ext_ack *extack = f->common.extack; 2588 2589 if (dissector->used_keys & 2590 ~(BIT(FLOW_DISSECTOR_KEY_BASIC) | 2591 BIT(FLOW_DISSECTOR_KEY_CONTROL) | 2592 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2593 BIT(FLOW_DISSECTOR_KEY_VLAN))) { 2594 NL_SET_ERR_MSG_MOD(extack, 2595 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2596 return -EOPNOTSUPP; 2597 } 2598 2599 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2600 struct flow_match_eth_addrs match; 2601 2602 flow_rule_match_eth_addrs(rule, &match); 2603 if (!is_zero_ether_addr(match.mask->dst)) { 2604 if (!is_broadcast_ether_addr(match.mask->dst)) { 2605 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2606 return -EINVAL; 2607 } 2608 2609 input->filter.match_flags |= 2610 IGB_FILTER_FLAG_DST_MAC_ADDR; 2611 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2612 } 2613 2614 if (!is_zero_ether_addr(match.mask->src)) { 2615 if (!is_broadcast_ether_addr(match.mask->src)) { 2616 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2617 return -EINVAL; 2618 } 2619 2620 input->filter.match_flags |= 2621 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2622 ether_addr_copy(input->filter.src_addr, match.key->src); 2623 } 2624 } 2625 2626 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2627 struct flow_match_basic match; 2628 2629 flow_rule_match_basic(rule, &match); 2630 if (match.mask->n_proto) { 2631 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2632 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2633 return -EINVAL; 2634 } 2635 2636 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2637 input->filter.etype = match.key->n_proto; 2638 } 2639 } 2640 2641 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2642 struct flow_match_vlan match; 2643 2644 flow_rule_match_vlan(rule, &match); 2645 if (match.mask->vlan_priority) { 2646 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2647 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2648 return -EINVAL; 2649 } 2650 2651 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2652 input->filter.vlan_tci = match.key->vlan_priority; 2653 } 2654 } 2655 2656 input->action = traffic_class; 2657 input->cookie = f->cookie; 2658 2659 return 0; 2660 } 2661 2662 static int igb_configure_clsflower(struct igb_adapter *adapter, 2663 struct tc_cls_flower_offload *cls_flower) 2664 { 2665 struct netlink_ext_ack *extack = cls_flower->common.extack; 2666 struct igb_nfc_filter *filter, *f; 2667 int err, tc; 2668 2669 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2670 if (tc < 0) { 2671 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2672 return -EINVAL; 2673 } 2674 2675 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2676 if (!filter) 2677 return -ENOMEM; 2678 2679 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2680 if (err < 0) 2681 goto err_parse; 2682 2683 spin_lock(&adapter->nfc_lock); 2684 2685 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2686 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2687 err = -EEXIST; 2688 NL_SET_ERR_MSG_MOD(extack, 2689 "This filter is already set in ethtool"); 2690 goto err_locked; 2691 } 2692 } 2693 2694 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2695 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2696 err = -EEXIST; 2697 NL_SET_ERR_MSG_MOD(extack, 2698 "This filter is already set in cls_flower"); 2699 goto err_locked; 2700 } 2701 } 2702 2703 err = igb_add_filter(adapter, filter); 2704 if (err < 0) { 2705 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2706 goto err_locked; 2707 } 2708 2709 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2710 2711 spin_unlock(&adapter->nfc_lock); 2712 2713 return 0; 2714 2715 err_locked: 2716 spin_unlock(&adapter->nfc_lock); 2717 2718 err_parse: 2719 kfree(filter); 2720 2721 return err; 2722 } 2723 2724 static int igb_delete_clsflower(struct igb_adapter *adapter, 2725 struct tc_cls_flower_offload *cls_flower) 2726 { 2727 struct igb_nfc_filter *filter; 2728 int err; 2729 2730 spin_lock(&adapter->nfc_lock); 2731 2732 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2733 if (filter->cookie == cls_flower->cookie) 2734 break; 2735 2736 if (!filter) { 2737 err = -ENOENT; 2738 goto out; 2739 } 2740 2741 err = igb_erase_filter(adapter, filter); 2742 if (err < 0) 2743 goto out; 2744 2745 hlist_del(&filter->nfc_node); 2746 kfree(filter); 2747 2748 out: 2749 spin_unlock(&adapter->nfc_lock); 2750 2751 return err; 2752 } 2753 2754 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2755 struct tc_cls_flower_offload *cls_flower) 2756 { 2757 switch (cls_flower->command) { 2758 case TC_CLSFLOWER_REPLACE: 2759 return igb_configure_clsflower(adapter, cls_flower); 2760 case TC_CLSFLOWER_DESTROY: 2761 return igb_delete_clsflower(adapter, cls_flower); 2762 case TC_CLSFLOWER_STATS: 2763 return -EOPNOTSUPP; 2764 default: 2765 return -EOPNOTSUPP; 2766 } 2767 } 2768 2769 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2770 void *cb_priv) 2771 { 2772 struct igb_adapter *adapter = cb_priv; 2773 2774 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2775 return -EOPNOTSUPP; 2776 2777 switch (type) { 2778 case TC_SETUP_CLSFLOWER: 2779 return igb_setup_tc_cls_flower(adapter, type_data); 2780 2781 default: 2782 return -EOPNOTSUPP; 2783 } 2784 } 2785 2786 static int igb_setup_tc_block(struct igb_adapter *adapter, 2787 struct tc_block_offload *f) 2788 { 2789 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 2790 return -EOPNOTSUPP; 2791 2792 switch (f->command) { 2793 case TC_BLOCK_BIND: 2794 return tcf_block_cb_register(f->block, igb_setup_tc_block_cb, 2795 adapter, adapter, f->extack); 2796 case TC_BLOCK_UNBIND: 2797 tcf_block_cb_unregister(f->block, igb_setup_tc_block_cb, 2798 adapter); 2799 return 0; 2800 default: 2801 return -EOPNOTSUPP; 2802 } 2803 } 2804 2805 static int igb_offload_txtime(struct igb_adapter *adapter, 2806 struct tc_etf_qopt_offload *qopt) 2807 { 2808 struct e1000_hw *hw = &adapter->hw; 2809 int err; 2810 2811 /* Launchtime offloading is only supported by i210 controller. */ 2812 if (hw->mac.type != e1000_i210) 2813 return -EOPNOTSUPP; 2814 2815 /* Launchtime offloading is only supported by queues 0 and 1. */ 2816 if (qopt->queue < 0 || qopt->queue > 1) 2817 return -EINVAL; 2818 2819 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2820 if (err) 2821 return err; 2822 2823 igb_offload_apply(adapter, qopt->queue); 2824 2825 return 0; 2826 } 2827 2828 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2829 void *type_data) 2830 { 2831 struct igb_adapter *adapter = netdev_priv(dev); 2832 2833 switch (type) { 2834 case TC_SETUP_QDISC_CBS: 2835 return igb_offload_cbs(adapter, type_data); 2836 case TC_SETUP_BLOCK: 2837 return igb_setup_tc_block(adapter, type_data); 2838 case TC_SETUP_QDISC_ETF: 2839 return igb_offload_txtime(adapter, type_data); 2840 2841 default: 2842 return -EOPNOTSUPP; 2843 } 2844 } 2845 2846 static const struct net_device_ops igb_netdev_ops = { 2847 .ndo_open = igb_open, 2848 .ndo_stop = igb_close, 2849 .ndo_start_xmit = igb_xmit_frame, 2850 .ndo_get_stats64 = igb_get_stats64, 2851 .ndo_set_rx_mode = igb_set_rx_mode, 2852 .ndo_set_mac_address = igb_set_mac, 2853 .ndo_change_mtu = igb_change_mtu, 2854 .ndo_do_ioctl = igb_ioctl, 2855 .ndo_tx_timeout = igb_tx_timeout, 2856 .ndo_validate_addr = eth_validate_addr, 2857 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2858 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2859 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2860 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2861 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 2862 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2863 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 2864 .ndo_get_vf_config = igb_ndo_get_vf_config, 2865 .ndo_fix_features = igb_fix_features, 2866 .ndo_set_features = igb_set_features, 2867 .ndo_fdb_add = igb_ndo_fdb_add, 2868 .ndo_features_check = igb_features_check, 2869 .ndo_setup_tc = igb_setup_tc, 2870 }; 2871 2872 /** 2873 * igb_set_fw_version - Configure version string for ethtool 2874 * @adapter: adapter struct 2875 **/ 2876 void igb_set_fw_version(struct igb_adapter *adapter) 2877 { 2878 struct e1000_hw *hw = &adapter->hw; 2879 struct e1000_fw_version fw; 2880 2881 igb_get_fw_version(hw, &fw); 2882 2883 switch (hw->mac.type) { 2884 case e1000_i210: 2885 case e1000_i211: 2886 if (!(igb_get_flash_presence_i210(hw))) { 2887 snprintf(adapter->fw_version, 2888 sizeof(adapter->fw_version), 2889 "%2d.%2d-%d", 2890 fw.invm_major, fw.invm_minor, 2891 fw.invm_img_type); 2892 break; 2893 } 2894 /* fall through */ 2895 default: 2896 /* if option is rom valid, display its version too */ 2897 if (fw.or_valid) { 2898 snprintf(adapter->fw_version, 2899 sizeof(adapter->fw_version), 2900 "%d.%d, 0x%08x, %d.%d.%d", 2901 fw.eep_major, fw.eep_minor, fw.etrack_id, 2902 fw.or_major, fw.or_build, fw.or_patch); 2903 /* no option rom */ 2904 } else if (fw.etrack_id != 0X0000) { 2905 snprintf(adapter->fw_version, 2906 sizeof(adapter->fw_version), 2907 "%d.%d, 0x%08x", 2908 fw.eep_major, fw.eep_minor, fw.etrack_id); 2909 } else { 2910 snprintf(adapter->fw_version, 2911 sizeof(adapter->fw_version), 2912 "%d.%d.%d", 2913 fw.eep_major, fw.eep_minor, fw.eep_build); 2914 } 2915 break; 2916 } 2917 } 2918 2919 /** 2920 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2921 * 2922 * @adapter: adapter struct 2923 **/ 2924 static void igb_init_mas(struct igb_adapter *adapter) 2925 { 2926 struct e1000_hw *hw = &adapter->hw; 2927 u16 eeprom_data; 2928 2929 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2930 switch (hw->bus.func) { 2931 case E1000_FUNC_0: 2932 if (eeprom_data & IGB_MAS_ENABLE_0) { 2933 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2934 netdev_info(adapter->netdev, 2935 "MAS: Enabling Media Autosense for port %d\n", 2936 hw->bus.func); 2937 } 2938 break; 2939 case E1000_FUNC_1: 2940 if (eeprom_data & IGB_MAS_ENABLE_1) { 2941 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2942 netdev_info(adapter->netdev, 2943 "MAS: Enabling Media Autosense for port %d\n", 2944 hw->bus.func); 2945 } 2946 break; 2947 case E1000_FUNC_2: 2948 if (eeprom_data & IGB_MAS_ENABLE_2) { 2949 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2950 netdev_info(adapter->netdev, 2951 "MAS: Enabling Media Autosense for port %d\n", 2952 hw->bus.func); 2953 } 2954 break; 2955 case E1000_FUNC_3: 2956 if (eeprom_data & IGB_MAS_ENABLE_3) { 2957 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2958 netdev_info(adapter->netdev, 2959 "MAS: Enabling Media Autosense for port %d\n", 2960 hw->bus.func); 2961 } 2962 break; 2963 default: 2964 /* Shouldn't get here */ 2965 netdev_err(adapter->netdev, 2966 "MAS: Invalid port configuration, returning\n"); 2967 break; 2968 } 2969 } 2970 2971 /** 2972 * igb_init_i2c - Init I2C interface 2973 * @adapter: pointer to adapter structure 2974 **/ 2975 static s32 igb_init_i2c(struct igb_adapter *adapter) 2976 { 2977 s32 status = 0; 2978 2979 /* I2C interface supported on i350 devices */ 2980 if (adapter->hw.mac.type != e1000_i350) 2981 return 0; 2982 2983 /* Initialize the i2c bus which is controlled by the registers. 2984 * This bus will use the i2c_algo_bit structue that implements 2985 * the protocol through toggling of the 4 bits in the register. 2986 */ 2987 adapter->i2c_adap.owner = THIS_MODULE; 2988 adapter->i2c_algo = igb_i2c_algo; 2989 adapter->i2c_algo.data = adapter; 2990 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 2991 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 2992 strlcpy(adapter->i2c_adap.name, "igb BB", 2993 sizeof(adapter->i2c_adap.name)); 2994 status = i2c_bit_add_bus(&adapter->i2c_adap); 2995 return status; 2996 } 2997 2998 /** 2999 * igb_probe - Device Initialization Routine 3000 * @pdev: PCI device information struct 3001 * @ent: entry in igb_pci_tbl 3002 * 3003 * Returns 0 on success, negative on failure 3004 * 3005 * igb_probe initializes an adapter identified by a pci_dev structure. 3006 * The OS initialization, configuring of the adapter private structure, 3007 * and a hardware reset occur. 3008 **/ 3009 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3010 { 3011 struct net_device *netdev; 3012 struct igb_adapter *adapter; 3013 struct e1000_hw *hw; 3014 u16 eeprom_data = 0; 3015 s32 ret_val; 3016 static int global_quad_port_a; /* global quad port a indication */ 3017 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3018 int err, pci_using_dac; 3019 u8 part_str[E1000_PBANUM_LENGTH]; 3020 3021 /* Catch broken hardware that put the wrong VF device ID in 3022 * the PCIe SR-IOV capability. 3023 */ 3024 if (pdev->is_virtfn) { 3025 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 3026 pci_name(pdev), pdev->vendor, pdev->device); 3027 return -EINVAL; 3028 } 3029 3030 err = pci_enable_device_mem(pdev); 3031 if (err) 3032 return err; 3033 3034 pci_using_dac = 0; 3035 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3036 if (!err) { 3037 pci_using_dac = 1; 3038 } else { 3039 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3040 if (err) { 3041 dev_err(&pdev->dev, 3042 "No usable DMA configuration, aborting\n"); 3043 goto err_dma; 3044 } 3045 } 3046 3047 err = pci_request_mem_regions(pdev, igb_driver_name); 3048 if (err) 3049 goto err_pci_reg; 3050 3051 pci_enable_pcie_error_reporting(pdev); 3052 3053 pci_set_master(pdev); 3054 pci_save_state(pdev); 3055 3056 err = -ENOMEM; 3057 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3058 IGB_MAX_TX_QUEUES); 3059 if (!netdev) 3060 goto err_alloc_etherdev; 3061 3062 SET_NETDEV_DEV(netdev, &pdev->dev); 3063 3064 pci_set_drvdata(pdev, netdev); 3065 adapter = netdev_priv(netdev); 3066 adapter->netdev = netdev; 3067 adapter->pdev = pdev; 3068 hw = &adapter->hw; 3069 hw->back = adapter; 3070 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3071 3072 err = -EIO; 3073 adapter->io_addr = pci_iomap(pdev, 0, 0); 3074 if (!adapter->io_addr) 3075 goto err_ioremap; 3076 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3077 hw->hw_addr = adapter->io_addr; 3078 3079 netdev->netdev_ops = &igb_netdev_ops; 3080 igb_set_ethtool_ops(netdev); 3081 netdev->watchdog_timeo = 5 * HZ; 3082 3083 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 3084 3085 netdev->mem_start = pci_resource_start(pdev, 0); 3086 netdev->mem_end = pci_resource_end(pdev, 0); 3087 3088 /* PCI config space info */ 3089 hw->vendor_id = pdev->vendor; 3090 hw->device_id = pdev->device; 3091 hw->revision_id = pdev->revision; 3092 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3093 hw->subsystem_device_id = pdev->subsystem_device; 3094 3095 /* Copy the default MAC, PHY and NVM function pointers */ 3096 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3097 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3098 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3099 /* Initialize skew-specific constants */ 3100 err = ei->get_invariants(hw); 3101 if (err) 3102 goto err_sw_init; 3103 3104 /* setup the private structure */ 3105 err = igb_sw_init(adapter); 3106 if (err) 3107 goto err_sw_init; 3108 3109 igb_get_bus_info_pcie(hw); 3110 3111 hw->phy.autoneg_wait_to_complete = false; 3112 3113 /* Copper options */ 3114 if (hw->phy.media_type == e1000_media_type_copper) { 3115 hw->phy.mdix = AUTO_ALL_MODES; 3116 hw->phy.disable_polarity_correction = false; 3117 hw->phy.ms_type = e1000_ms_hw_default; 3118 } 3119 3120 if (igb_check_reset_block(hw)) 3121 dev_info(&pdev->dev, 3122 "PHY reset is blocked due to SOL/IDER session.\n"); 3123 3124 /* features is initialized to 0 in allocation, it might have bits 3125 * set by igb_sw_init so we should use an or instead of an 3126 * assignment. 3127 */ 3128 netdev->features |= NETIF_F_SG | 3129 NETIF_F_TSO | 3130 NETIF_F_TSO6 | 3131 NETIF_F_RXHASH | 3132 NETIF_F_RXCSUM | 3133 NETIF_F_HW_CSUM; 3134 3135 if (hw->mac.type >= e1000_82576) 3136 netdev->features |= NETIF_F_SCTP_CRC; 3137 3138 if (hw->mac.type >= e1000_i350) 3139 netdev->features |= NETIF_F_HW_TC; 3140 3141 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3142 NETIF_F_GSO_GRE_CSUM | \ 3143 NETIF_F_GSO_IPXIP4 | \ 3144 NETIF_F_GSO_IPXIP6 | \ 3145 NETIF_F_GSO_UDP_TUNNEL | \ 3146 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3147 3148 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3149 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3150 3151 /* copy netdev features into list of user selectable features */ 3152 netdev->hw_features |= netdev->features | 3153 NETIF_F_HW_VLAN_CTAG_RX | 3154 NETIF_F_HW_VLAN_CTAG_TX | 3155 NETIF_F_RXALL; 3156 3157 if (hw->mac.type >= e1000_i350) 3158 netdev->hw_features |= NETIF_F_NTUPLE; 3159 3160 if (pci_using_dac) 3161 netdev->features |= NETIF_F_HIGHDMA; 3162 3163 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3164 netdev->mpls_features |= NETIF_F_HW_CSUM; 3165 netdev->hw_enc_features |= netdev->vlan_features; 3166 3167 /* set this bit last since it cannot be part of vlan_features */ 3168 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3169 NETIF_F_HW_VLAN_CTAG_RX | 3170 NETIF_F_HW_VLAN_CTAG_TX; 3171 3172 netdev->priv_flags |= IFF_SUPP_NOFCS; 3173 3174 netdev->priv_flags |= IFF_UNICAST_FLT; 3175 3176 /* MTU range: 68 - 9216 */ 3177 netdev->min_mtu = ETH_MIN_MTU; 3178 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3179 3180 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3181 3182 /* before reading the NVM, reset the controller to put the device in a 3183 * known good starting state 3184 */ 3185 hw->mac.ops.reset_hw(hw); 3186 3187 /* make sure the NVM is good , i211/i210 parts can have special NVM 3188 * that doesn't contain a checksum 3189 */ 3190 switch (hw->mac.type) { 3191 case e1000_i210: 3192 case e1000_i211: 3193 if (igb_get_flash_presence_i210(hw)) { 3194 if (hw->nvm.ops.validate(hw) < 0) { 3195 dev_err(&pdev->dev, 3196 "The NVM Checksum Is Not Valid\n"); 3197 err = -EIO; 3198 goto err_eeprom; 3199 } 3200 } 3201 break; 3202 default: 3203 if (hw->nvm.ops.validate(hw) < 0) { 3204 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3205 err = -EIO; 3206 goto err_eeprom; 3207 } 3208 break; 3209 } 3210 3211 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3212 /* copy the MAC address out of the NVM */ 3213 if (hw->mac.ops.read_mac_addr(hw)) 3214 dev_err(&pdev->dev, "NVM Read Error\n"); 3215 } 3216 3217 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 3218 3219 if (!is_valid_ether_addr(netdev->dev_addr)) { 3220 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3221 err = -EIO; 3222 goto err_eeprom; 3223 } 3224 3225 igb_set_default_mac_filter(adapter); 3226 3227 /* get firmware version for ethtool -i */ 3228 igb_set_fw_version(adapter); 3229 3230 /* configure RXPBSIZE and TXPBSIZE */ 3231 if (hw->mac.type == e1000_i210) { 3232 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3233 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3234 } 3235 3236 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3237 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3238 3239 INIT_WORK(&adapter->reset_task, igb_reset_task); 3240 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3241 3242 /* Initialize link properties that are user-changeable */ 3243 adapter->fc_autoneg = true; 3244 hw->mac.autoneg = true; 3245 hw->phy.autoneg_advertised = 0x2f; 3246 3247 hw->fc.requested_mode = e1000_fc_default; 3248 hw->fc.current_mode = e1000_fc_default; 3249 3250 igb_validate_mdi_setting(hw); 3251 3252 /* By default, support wake on port A */ 3253 if (hw->bus.func == 0) 3254 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3255 3256 /* Check the NVM for wake support on non-port A ports */ 3257 if (hw->mac.type >= e1000_82580) 3258 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3259 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3260 &eeprom_data); 3261 else if (hw->bus.func == 1) 3262 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3263 3264 if (eeprom_data & IGB_EEPROM_APME) 3265 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3266 3267 /* now that we have the eeprom settings, apply the special cases where 3268 * the eeprom may be wrong or the board simply won't support wake on 3269 * lan on a particular port 3270 */ 3271 switch (pdev->device) { 3272 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3273 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3274 break; 3275 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3276 case E1000_DEV_ID_82576_FIBER: 3277 case E1000_DEV_ID_82576_SERDES: 3278 /* Wake events only supported on port A for dual fiber 3279 * regardless of eeprom setting 3280 */ 3281 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3282 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3283 break; 3284 case E1000_DEV_ID_82576_QUAD_COPPER: 3285 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3286 /* if quad port adapter, disable WoL on all but port A */ 3287 if (global_quad_port_a != 0) 3288 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3289 else 3290 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3291 /* Reset for multiple quad port adapters */ 3292 if (++global_quad_port_a == 4) 3293 global_quad_port_a = 0; 3294 break; 3295 default: 3296 /* If the device can't wake, don't set software support */ 3297 if (!device_can_wakeup(&adapter->pdev->dev)) 3298 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3299 } 3300 3301 /* initialize the wol settings based on the eeprom settings */ 3302 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3303 adapter->wol |= E1000_WUFC_MAG; 3304 3305 /* Some vendors want WoL disabled by default, but still supported */ 3306 if ((hw->mac.type == e1000_i350) && 3307 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3308 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3309 adapter->wol = 0; 3310 } 3311 3312 /* Some vendors want the ability to Use the EEPROM setting as 3313 * enable/disable only, and not for capability 3314 */ 3315 if (((hw->mac.type == e1000_i350) || 3316 (hw->mac.type == e1000_i354)) && 3317 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3318 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3319 adapter->wol = 0; 3320 } 3321 if (hw->mac.type == e1000_i350) { 3322 if (((pdev->subsystem_device == 0x5001) || 3323 (pdev->subsystem_device == 0x5002)) && 3324 (hw->bus.func == 0)) { 3325 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3326 adapter->wol = 0; 3327 } 3328 if (pdev->subsystem_device == 0x1F52) 3329 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3330 } 3331 3332 device_set_wakeup_enable(&adapter->pdev->dev, 3333 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3334 3335 /* reset the hardware with the new settings */ 3336 igb_reset(adapter); 3337 3338 /* Init the I2C interface */ 3339 err = igb_init_i2c(adapter); 3340 if (err) { 3341 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3342 goto err_eeprom; 3343 } 3344 3345 /* let the f/w know that the h/w is now under the control of the 3346 * driver. 3347 */ 3348 igb_get_hw_control(adapter); 3349 3350 strcpy(netdev->name, "eth%d"); 3351 err = register_netdev(netdev); 3352 if (err) 3353 goto err_register; 3354 3355 /* carrier off reporting is important to ethtool even BEFORE open */ 3356 netif_carrier_off(netdev); 3357 3358 #ifdef CONFIG_IGB_DCA 3359 if (dca_add_requester(&pdev->dev) == 0) { 3360 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3361 dev_info(&pdev->dev, "DCA enabled\n"); 3362 igb_setup_dca(adapter); 3363 } 3364 3365 #endif 3366 #ifdef CONFIG_IGB_HWMON 3367 /* Initialize the thermal sensor on i350 devices. */ 3368 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3369 u16 ets_word; 3370 3371 /* Read the NVM to determine if this i350 device supports an 3372 * external thermal sensor. 3373 */ 3374 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3375 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3376 adapter->ets = true; 3377 else 3378 adapter->ets = false; 3379 if (igb_sysfs_init(adapter)) 3380 dev_err(&pdev->dev, 3381 "failed to allocate sysfs resources\n"); 3382 } else { 3383 adapter->ets = false; 3384 } 3385 #endif 3386 /* Check if Media Autosense is enabled */ 3387 adapter->ei = *ei; 3388 if (hw->dev_spec._82575.mas_capable) 3389 igb_init_mas(adapter); 3390 3391 /* do hw tstamp init after resetting */ 3392 igb_ptp_init(adapter); 3393 3394 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3395 /* print bus type/speed/width info, not applicable to i354 */ 3396 if (hw->mac.type != e1000_i354) { 3397 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3398 netdev->name, 3399 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3400 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3401 "unknown"), 3402 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3403 "Width x4" : 3404 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3405 "Width x2" : 3406 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3407 "Width x1" : "unknown"), netdev->dev_addr); 3408 } 3409 3410 if ((hw->mac.type >= e1000_i210 || 3411 igb_get_flash_presence_i210(hw))) { 3412 ret_val = igb_read_part_string(hw, part_str, 3413 E1000_PBANUM_LENGTH); 3414 } else { 3415 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3416 } 3417 3418 if (ret_val) 3419 strcpy(part_str, "Unknown"); 3420 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3421 dev_info(&pdev->dev, 3422 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3423 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3424 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3425 adapter->num_rx_queues, adapter->num_tx_queues); 3426 if (hw->phy.media_type == e1000_media_type_copper) { 3427 switch (hw->mac.type) { 3428 case e1000_i350: 3429 case e1000_i210: 3430 case e1000_i211: 3431 /* Enable EEE for internal copper PHY devices */ 3432 err = igb_set_eee_i350(hw, true, true); 3433 if ((!err) && 3434 (!hw->dev_spec._82575.eee_disable)) { 3435 adapter->eee_advert = 3436 MDIO_EEE_100TX | MDIO_EEE_1000T; 3437 adapter->flags |= IGB_FLAG_EEE; 3438 } 3439 break; 3440 case e1000_i354: 3441 if ((rd32(E1000_CTRL_EXT) & 3442 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3443 err = igb_set_eee_i354(hw, true, true); 3444 if ((!err) && 3445 (!hw->dev_spec._82575.eee_disable)) { 3446 adapter->eee_advert = 3447 MDIO_EEE_100TX | MDIO_EEE_1000T; 3448 adapter->flags |= IGB_FLAG_EEE; 3449 } 3450 } 3451 break; 3452 default: 3453 break; 3454 } 3455 } 3456 3457 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP); 3458 3459 pm_runtime_put_noidle(&pdev->dev); 3460 return 0; 3461 3462 err_register: 3463 igb_release_hw_control(adapter); 3464 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3465 err_eeprom: 3466 if (!igb_check_reset_block(hw)) 3467 igb_reset_phy(hw); 3468 3469 if (hw->flash_address) 3470 iounmap(hw->flash_address); 3471 err_sw_init: 3472 kfree(adapter->mac_table); 3473 kfree(adapter->shadow_vfta); 3474 igb_clear_interrupt_scheme(adapter); 3475 #ifdef CONFIG_PCI_IOV 3476 igb_disable_sriov(pdev); 3477 #endif 3478 pci_iounmap(pdev, adapter->io_addr); 3479 err_ioremap: 3480 free_netdev(netdev); 3481 err_alloc_etherdev: 3482 pci_release_mem_regions(pdev); 3483 err_pci_reg: 3484 err_dma: 3485 pci_disable_device(pdev); 3486 return err; 3487 } 3488 3489 #ifdef CONFIG_PCI_IOV 3490 static int igb_disable_sriov(struct pci_dev *pdev) 3491 { 3492 struct net_device *netdev = pci_get_drvdata(pdev); 3493 struct igb_adapter *adapter = netdev_priv(netdev); 3494 struct e1000_hw *hw = &adapter->hw; 3495 3496 /* reclaim resources allocated to VFs */ 3497 if (adapter->vf_data) { 3498 /* disable iov and allow time for transactions to clear */ 3499 if (pci_vfs_assigned(pdev)) { 3500 dev_warn(&pdev->dev, 3501 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3502 return -EPERM; 3503 } else { 3504 pci_disable_sriov(pdev); 3505 msleep(500); 3506 } 3507 3508 kfree(adapter->vf_mac_list); 3509 adapter->vf_mac_list = NULL; 3510 kfree(adapter->vf_data); 3511 adapter->vf_data = NULL; 3512 adapter->vfs_allocated_count = 0; 3513 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3514 wrfl(); 3515 msleep(100); 3516 dev_info(&pdev->dev, "IOV Disabled\n"); 3517 3518 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3519 adapter->flags |= IGB_FLAG_DMAC; 3520 } 3521 3522 return 0; 3523 } 3524 3525 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 3526 { 3527 struct net_device *netdev = pci_get_drvdata(pdev); 3528 struct igb_adapter *adapter = netdev_priv(netdev); 3529 int old_vfs = pci_num_vf(pdev); 3530 struct vf_mac_filter *mac_list; 3531 int err = 0; 3532 int num_vf_mac_filters, i; 3533 3534 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3535 err = -EPERM; 3536 goto out; 3537 } 3538 if (!num_vfs) 3539 goto out; 3540 3541 if (old_vfs) { 3542 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3543 old_vfs, max_vfs); 3544 adapter->vfs_allocated_count = old_vfs; 3545 } else 3546 adapter->vfs_allocated_count = num_vfs; 3547 3548 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3549 sizeof(struct vf_data_storage), GFP_KERNEL); 3550 3551 /* if allocation failed then we do not support SR-IOV */ 3552 if (!adapter->vf_data) { 3553 adapter->vfs_allocated_count = 0; 3554 err = -ENOMEM; 3555 goto out; 3556 } 3557 3558 /* Due to the limited number of RAR entries calculate potential 3559 * number of MAC filters available for the VFs. Reserve entries 3560 * for PF default MAC, PF MAC filters and at least one RAR entry 3561 * for each VF for VF MAC. 3562 */ 3563 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3564 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3565 adapter->vfs_allocated_count); 3566 3567 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3568 sizeof(struct vf_mac_filter), 3569 GFP_KERNEL); 3570 3571 mac_list = adapter->vf_mac_list; 3572 INIT_LIST_HEAD(&adapter->vf_macs.l); 3573 3574 if (adapter->vf_mac_list) { 3575 /* Initialize list of VF MAC filters */ 3576 for (i = 0; i < num_vf_mac_filters; i++) { 3577 mac_list->vf = -1; 3578 mac_list->free = true; 3579 list_add(&mac_list->l, &adapter->vf_macs.l); 3580 mac_list++; 3581 } 3582 } else { 3583 /* If we could not allocate memory for the VF MAC filters 3584 * we can continue without this feature but warn user. 3585 */ 3586 dev_err(&pdev->dev, 3587 "Unable to allocate memory for VF MAC filter list\n"); 3588 } 3589 3590 /* only call pci_enable_sriov() if no VFs are allocated already */ 3591 if (!old_vfs) { 3592 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3593 if (err) 3594 goto err_out; 3595 } 3596 dev_info(&pdev->dev, "%d VFs allocated\n", 3597 adapter->vfs_allocated_count); 3598 for (i = 0; i < adapter->vfs_allocated_count; i++) 3599 igb_vf_configure(adapter, i); 3600 3601 /* DMA Coalescing is not supported in IOV mode. */ 3602 adapter->flags &= ~IGB_FLAG_DMAC; 3603 goto out; 3604 3605 err_out: 3606 kfree(adapter->vf_mac_list); 3607 adapter->vf_mac_list = NULL; 3608 kfree(adapter->vf_data); 3609 adapter->vf_data = NULL; 3610 adapter->vfs_allocated_count = 0; 3611 out: 3612 return err; 3613 } 3614 3615 #endif 3616 /** 3617 * igb_remove_i2c - Cleanup I2C interface 3618 * @adapter: pointer to adapter structure 3619 **/ 3620 static void igb_remove_i2c(struct igb_adapter *adapter) 3621 { 3622 /* free the adapter bus structure */ 3623 i2c_del_adapter(&adapter->i2c_adap); 3624 } 3625 3626 /** 3627 * igb_remove - Device Removal Routine 3628 * @pdev: PCI device information struct 3629 * 3630 * igb_remove is called by the PCI subsystem to alert the driver 3631 * that it should release a PCI device. The could be caused by a 3632 * Hot-Plug event, or because the driver is going to be removed from 3633 * memory. 3634 **/ 3635 static void igb_remove(struct pci_dev *pdev) 3636 { 3637 struct net_device *netdev = pci_get_drvdata(pdev); 3638 struct igb_adapter *adapter = netdev_priv(netdev); 3639 struct e1000_hw *hw = &adapter->hw; 3640 3641 pm_runtime_get_noresume(&pdev->dev); 3642 #ifdef CONFIG_IGB_HWMON 3643 igb_sysfs_exit(adapter); 3644 #endif 3645 igb_remove_i2c(adapter); 3646 igb_ptp_stop(adapter); 3647 /* The watchdog timer may be rescheduled, so explicitly 3648 * disable watchdog from being rescheduled. 3649 */ 3650 set_bit(__IGB_DOWN, &adapter->state); 3651 del_timer_sync(&adapter->watchdog_timer); 3652 del_timer_sync(&adapter->phy_info_timer); 3653 3654 cancel_work_sync(&adapter->reset_task); 3655 cancel_work_sync(&adapter->watchdog_task); 3656 3657 #ifdef CONFIG_IGB_DCA 3658 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3659 dev_info(&pdev->dev, "DCA disabled\n"); 3660 dca_remove_requester(&pdev->dev); 3661 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3662 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3663 } 3664 #endif 3665 3666 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3667 * would have already happened in close and is redundant. 3668 */ 3669 igb_release_hw_control(adapter); 3670 3671 #ifdef CONFIG_PCI_IOV 3672 igb_disable_sriov(pdev); 3673 #endif 3674 3675 unregister_netdev(netdev); 3676 3677 igb_clear_interrupt_scheme(adapter); 3678 3679 pci_iounmap(pdev, adapter->io_addr); 3680 if (hw->flash_address) 3681 iounmap(hw->flash_address); 3682 pci_release_mem_regions(pdev); 3683 3684 kfree(adapter->mac_table); 3685 kfree(adapter->shadow_vfta); 3686 free_netdev(netdev); 3687 3688 pci_disable_pcie_error_reporting(pdev); 3689 3690 pci_disable_device(pdev); 3691 } 3692 3693 /** 3694 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3695 * @adapter: board private structure to initialize 3696 * 3697 * This function initializes the vf specific data storage and then attempts to 3698 * allocate the VFs. The reason for ordering it this way is because it is much 3699 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3700 * the memory for the VFs. 3701 **/ 3702 static void igb_probe_vfs(struct igb_adapter *adapter) 3703 { 3704 #ifdef CONFIG_PCI_IOV 3705 struct pci_dev *pdev = adapter->pdev; 3706 struct e1000_hw *hw = &adapter->hw; 3707 3708 /* Virtualization features not supported on i210 family. */ 3709 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 3710 return; 3711 3712 /* Of the below we really only want the effect of getting 3713 * IGB_FLAG_HAS_MSIX set (if available), without which 3714 * igb_enable_sriov() has no effect. 3715 */ 3716 igb_set_interrupt_capability(adapter, true); 3717 igb_reset_interrupt_capability(adapter); 3718 3719 pci_sriov_set_totalvfs(pdev, 7); 3720 igb_enable_sriov(pdev, max_vfs); 3721 3722 #endif /* CONFIG_PCI_IOV */ 3723 } 3724 3725 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3726 { 3727 struct e1000_hw *hw = &adapter->hw; 3728 unsigned int max_rss_queues; 3729 3730 /* Determine the maximum number of RSS queues supported. */ 3731 switch (hw->mac.type) { 3732 case e1000_i211: 3733 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3734 break; 3735 case e1000_82575: 3736 case e1000_i210: 3737 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3738 break; 3739 case e1000_i350: 3740 /* I350 cannot do RSS and SR-IOV at the same time */ 3741 if (!!adapter->vfs_allocated_count) { 3742 max_rss_queues = 1; 3743 break; 3744 } 3745 /* fall through */ 3746 case e1000_82576: 3747 if (!!adapter->vfs_allocated_count) { 3748 max_rss_queues = 2; 3749 break; 3750 } 3751 /* fall through */ 3752 case e1000_82580: 3753 case e1000_i354: 3754 default: 3755 max_rss_queues = IGB_MAX_RX_QUEUES; 3756 break; 3757 } 3758 3759 return max_rss_queues; 3760 } 3761 3762 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3763 { 3764 u32 max_rss_queues; 3765 3766 max_rss_queues = igb_get_max_rss_queues(adapter); 3767 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3768 3769 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3770 } 3771 3772 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3773 const u32 max_rss_queues) 3774 { 3775 struct e1000_hw *hw = &adapter->hw; 3776 3777 /* Determine if we need to pair queues. */ 3778 switch (hw->mac.type) { 3779 case e1000_82575: 3780 case e1000_i211: 3781 /* Device supports enough interrupts without queue pairing. */ 3782 break; 3783 case e1000_82576: 3784 case e1000_82580: 3785 case e1000_i350: 3786 case e1000_i354: 3787 case e1000_i210: 3788 default: 3789 /* If rss_queues > half of max_rss_queues, pair the queues in 3790 * order to conserve interrupts due to limited supply. 3791 */ 3792 if (adapter->rss_queues > (max_rss_queues / 2)) 3793 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3794 else 3795 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 3796 break; 3797 } 3798 } 3799 3800 /** 3801 * igb_sw_init - Initialize general software structures (struct igb_adapter) 3802 * @adapter: board private structure to initialize 3803 * 3804 * igb_sw_init initializes the Adapter private data structure. 3805 * Fields are initialized based on PCI device information and 3806 * OS network device settings (MTU size). 3807 **/ 3808 static int igb_sw_init(struct igb_adapter *adapter) 3809 { 3810 struct e1000_hw *hw = &adapter->hw; 3811 struct net_device *netdev = adapter->netdev; 3812 struct pci_dev *pdev = adapter->pdev; 3813 3814 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 3815 3816 /* set default ring sizes */ 3817 adapter->tx_ring_count = IGB_DEFAULT_TXD; 3818 adapter->rx_ring_count = IGB_DEFAULT_RXD; 3819 3820 /* set default ITR values */ 3821 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 3822 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 3823 3824 /* set default work limits */ 3825 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 3826 3827 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 3828 VLAN_HLEN; 3829 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 3830 3831 spin_lock_init(&adapter->nfc_lock); 3832 spin_lock_init(&adapter->stats64_lock); 3833 #ifdef CONFIG_PCI_IOV 3834 switch (hw->mac.type) { 3835 case e1000_82576: 3836 case e1000_i350: 3837 if (max_vfs > 7) { 3838 dev_warn(&pdev->dev, 3839 "Maximum of 7 VFs per PF, using max\n"); 3840 max_vfs = adapter->vfs_allocated_count = 7; 3841 } else 3842 adapter->vfs_allocated_count = max_vfs; 3843 if (adapter->vfs_allocated_count) 3844 dev_warn(&pdev->dev, 3845 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 3846 break; 3847 default: 3848 break; 3849 } 3850 #endif /* CONFIG_PCI_IOV */ 3851 3852 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 3853 adapter->flags |= IGB_FLAG_HAS_MSIX; 3854 3855 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 3856 sizeof(struct igb_mac_addr), 3857 GFP_KERNEL); 3858 if (!adapter->mac_table) 3859 return -ENOMEM; 3860 3861 igb_probe_vfs(adapter); 3862 3863 igb_init_queue_configuration(adapter); 3864 3865 /* Setup and initialize a copy of the hw vlan table array */ 3866 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 3867 GFP_KERNEL); 3868 if (!adapter->shadow_vfta) 3869 return -ENOMEM; 3870 3871 /* This call may decrease the number of queues */ 3872 if (igb_init_interrupt_scheme(adapter, true)) { 3873 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3874 return -ENOMEM; 3875 } 3876 3877 /* Explicitly disable IRQ since the NIC can be in any state. */ 3878 igb_irq_disable(adapter); 3879 3880 if (hw->mac.type >= e1000_i350) 3881 adapter->flags &= ~IGB_FLAG_DMAC; 3882 3883 set_bit(__IGB_DOWN, &adapter->state); 3884 return 0; 3885 } 3886 3887 /** 3888 * igb_open - Called when a network interface is made active 3889 * @netdev: network interface device structure 3890 * 3891 * Returns 0 on success, negative value on failure 3892 * 3893 * The open entry point is called when a network interface is made 3894 * active by the system (IFF_UP). At this point all resources needed 3895 * for transmit and receive operations are allocated, the interrupt 3896 * handler is registered with the OS, the watchdog timer is started, 3897 * and the stack is notified that the interface is ready. 3898 **/ 3899 static int __igb_open(struct net_device *netdev, bool resuming) 3900 { 3901 struct igb_adapter *adapter = netdev_priv(netdev); 3902 struct e1000_hw *hw = &adapter->hw; 3903 struct pci_dev *pdev = adapter->pdev; 3904 int err; 3905 int i; 3906 3907 /* disallow open during test */ 3908 if (test_bit(__IGB_TESTING, &adapter->state)) { 3909 WARN_ON(resuming); 3910 return -EBUSY; 3911 } 3912 3913 if (!resuming) 3914 pm_runtime_get_sync(&pdev->dev); 3915 3916 netif_carrier_off(netdev); 3917 3918 /* allocate transmit descriptors */ 3919 err = igb_setup_all_tx_resources(adapter); 3920 if (err) 3921 goto err_setup_tx; 3922 3923 /* allocate receive descriptors */ 3924 err = igb_setup_all_rx_resources(adapter); 3925 if (err) 3926 goto err_setup_rx; 3927 3928 igb_power_up_link(adapter); 3929 3930 /* before we allocate an interrupt, we must be ready to handle it. 3931 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3932 * as soon as we call pci_request_irq, so we have to setup our 3933 * clean_rx handler before we do so. 3934 */ 3935 igb_configure(adapter); 3936 3937 err = igb_request_irq(adapter); 3938 if (err) 3939 goto err_req_irq; 3940 3941 /* Notify the stack of the actual queue counts. */ 3942 err = netif_set_real_num_tx_queues(adapter->netdev, 3943 adapter->num_tx_queues); 3944 if (err) 3945 goto err_set_queues; 3946 3947 err = netif_set_real_num_rx_queues(adapter->netdev, 3948 adapter->num_rx_queues); 3949 if (err) 3950 goto err_set_queues; 3951 3952 /* From here on the code is the same as igb_up() */ 3953 clear_bit(__IGB_DOWN, &adapter->state); 3954 3955 for (i = 0; i < adapter->num_q_vectors; i++) 3956 napi_enable(&(adapter->q_vector[i]->napi)); 3957 3958 /* Clear any pending interrupts. */ 3959 rd32(E1000_TSICR); 3960 rd32(E1000_ICR); 3961 3962 igb_irq_enable(adapter); 3963 3964 /* notify VFs that reset has been completed */ 3965 if (adapter->vfs_allocated_count) { 3966 u32 reg_data = rd32(E1000_CTRL_EXT); 3967 3968 reg_data |= E1000_CTRL_EXT_PFRSTD; 3969 wr32(E1000_CTRL_EXT, reg_data); 3970 } 3971 3972 netif_tx_start_all_queues(netdev); 3973 3974 if (!resuming) 3975 pm_runtime_put(&pdev->dev); 3976 3977 /* start the watchdog. */ 3978 hw->mac.get_link_status = 1; 3979 schedule_work(&adapter->watchdog_task); 3980 3981 return 0; 3982 3983 err_set_queues: 3984 igb_free_irq(adapter); 3985 err_req_irq: 3986 igb_release_hw_control(adapter); 3987 igb_power_down_link(adapter); 3988 igb_free_all_rx_resources(adapter); 3989 err_setup_rx: 3990 igb_free_all_tx_resources(adapter); 3991 err_setup_tx: 3992 igb_reset(adapter); 3993 if (!resuming) 3994 pm_runtime_put(&pdev->dev); 3995 3996 return err; 3997 } 3998 3999 int igb_open(struct net_device *netdev) 4000 { 4001 return __igb_open(netdev, false); 4002 } 4003 4004 /** 4005 * igb_close - Disables a network interface 4006 * @netdev: network interface device structure 4007 * 4008 * Returns 0, this is not allowed to fail 4009 * 4010 * The close entry point is called when an interface is de-activated 4011 * by the OS. The hardware is still under the driver's control, but 4012 * needs to be disabled. A global MAC reset is issued to stop the 4013 * hardware, and all transmit and receive resources are freed. 4014 **/ 4015 static int __igb_close(struct net_device *netdev, bool suspending) 4016 { 4017 struct igb_adapter *adapter = netdev_priv(netdev); 4018 struct pci_dev *pdev = adapter->pdev; 4019 4020 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4021 4022 if (!suspending) 4023 pm_runtime_get_sync(&pdev->dev); 4024 4025 igb_down(adapter); 4026 igb_free_irq(adapter); 4027 4028 igb_free_all_tx_resources(adapter); 4029 igb_free_all_rx_resources(adapter); 4030 4031 if (!suspending) 4032 pm_runtime_put_sync(&pdev->dev); 4033 return 0; 4034 } 4035 4036 int igb_close(struct net_device *netdev) 4037 { 4038 if (netif_device_present(netdev) || netdev->dismantle) 4039 return __igb_close(netdev, false); 4040 return 0; 4041 } 4042 4043 /** 4044 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4045 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4046 * 4047 * Return 0 on success, negative on failure 4048 **/ 4049 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4050 { 4051 struct device *dev = tx_ring->dev; 4052 int size; 4053 4054 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4055 4056 tx_ring->tx_buffer_info = vmalloc(size); 4057 if (!tx_ring->tx_buffer_info) 4058 goto err; 4059 4060 /* round up to nearest 4K */ 4061 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4062 tx_ring->size = ALIGN(tx_ring->size, 4096); 4063 4064 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4065 &tx_ring->dma, GFP_KERNEL); 4066 if (!tx_ring->desc) 4067 goto err; 4068 4069 tx_ring->next_to_use = 0; 4070 tx_ring->next_to_clean = 0; 4071 4072 return 0; 4073 4074 err: 4075 vfree(tx_ring->tx_buffer_info); 4076 tx_ring->tx_buffer_info = NULL; 4077 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4078 return -ENOMEM; 4079 } 4080 4081 /** 4082 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4083 * (Descriptors) for all queues 4084 * @adapter: board private structure 4085 * 4086 * Return 0 on success, negative on failure 4087 **/ 4088 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4089 { 4090 struct pci_dev *pdev = adapter->pdev; 4091 int i, err = 0; 4092 4093 for (i = 0; i < adapter->num_tx_queues; i++) { 4094 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4095 if (err) { 4096 dev_err(&pdev->dev, 4097 "Allocation for Tx Queue %u failed\n", i); 4098 for (i--; i >= 0; i--) 4099 igb_free_tx_resources(adapter->tx_ring[i]); 4100 break; 4101 } 4102 } 4103 4104 return err; 4105 } 4106 4107 /** 4108 * igb_setup_tctl - configure the transmit control registers 4109 * @adapter: Board private structure 4110 **/ 4111 void igb_setup_tctl(struct igb_adapter *adapter) 4112 { 4113 struct e1000_hw *hw = &adapter->hw; 4114 u32 tctl; 4115 4116 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4117 wr32(E1000_TXDCTL(0), 0); 4118 4119 /* Program the Transmit Control Register */ 4120 tctl = rd32(E1000_TCTL); 4121 tctl &= ~E1000_TCTL_CT; 4122 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4123 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4124 4125 igb_config_collision_dist(hw); 4126 4127 /* Enable transmits */ 4128 tctl |= E1000_TCTL_EN; 4129 4130 wr32(E1000_TCTL, tctl); 4131 } 4132 4133 /** 4134 * igb_configure_tx_ring - Configure transmit ring after Reset 4135 * @adapter: board private structure 4136 * @ring: tx ring to configure 4137 * 4138 * Configure a transmit ring after a reset. 4139 **/ 4140 void igb_configure_tx_ring(struct igb_adapter *adapter, 4141 struct igb_ring *ring) 4142 { 4143 struct e1000_hw *hw = &adapter->hw; 4144 u32 txdctl = 0; 4145 u64 tdba = ring->dma; 4146 int reg_idx = ring->reg_idx; 4147 4148 wr32(E1000_TDLEN(reg_idx), 4149 ring->count * sizeof(union e1000_adv_tx_desc)); 4150 wr32(E1000_TDBAL(reg_idx), 4151 tdba & 0x00000000ffffffffULL); 4152 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4153 4154 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4155 wr32(E1000_TDH(reg_idx), 0); 4156 writel(0, ring->tail); 4157 4158 txdctl |= IGB_TX_PTHRESH; 4159 txdctl |= IGB_TX_HTHRESH << 8; 4160 txdctl |= IGB_TX_WTHRESH << 16; 4161 4162 /* reinitialize tx_buffer_info */ 4163 memset(ring->tx_buffer_info, 0, 4164 sizeof(struct igb_tx_buffer) * ring->count); 4165 4166 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4167 wr32(E1000_TXDCTL(reg_idx), txdctl); 4168 } 4169 4170 /** 4171 * igb_configure_tx - Configure transmit Unit after Reset 4172 * @adapter: board private structure 4173 * 4174 * Configure the Tx unit of the MAC after a reset. 4175 **/ 4176 static void igb_configure_tx(struct igb_adapter *adapter) 4177 { 4178 struct e1000_hw *hw = &adapter->hw; 4179 int i; 4180 4181 /* disable the queues */ 4182 for (i = 0; i < adapter->num_tx_queues; i++) 4183 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4184 4185 wrfl(); 4186 usleep_range(10000, 20000); 4187 4188 for (i = 0; i < adapter->num_tx_queues; i++) 4189 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4190 } 4191 4192 /** 4193 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4194 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4195 * 4196 * Returns 0 on success, negative on failure 4197 **/ 4198 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4199 { 4200 struct device *dev = rx_ring->dev; 4201 int size; 4202 4203 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4204 4205 rx_ring->rx_buffer_info = vmalloc(size); 4206 if (!rx_ring->rx_buffer_info) 4207 goto err; 4208 4209 /* Round up to nearest 4K */ 4210 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4211 rx_ring->size = ALIGN(rx_ring->size, 4096); 4212 4213 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4214 &rx_ring->dma, GFP_KERNEL); 4215 if (!rx_ring->desc) 4216 goto err; 4217 4218 rx_ring->next_to_alloc = 0; 4219 rx_ring->next_to_clean = 0; 4220 rx_ring->next_to_use = 0; 4221 4222 return 0; 4223 4224 err: 4225 vfree(rx_ring->rx_buffer_info); 4226 rx_ring->rx_buffer_info = NULL; 4227 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4228 return -ENOMEM; 4229 } 4230 4231 /** 4232 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4233 * (Descriptors) for all queues 4234 * @adapter: board private structure 4235 * 4236 * Return 0 on success, negative on failure 4237 **/ 4238 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4239 { 4240 struct pci_dev *pdev = adapter->pdev; 4241 int i, err = 0; 4242 4243 for (i = 0; i < adapter->num_rx_queues; i++) { 4244 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4245 if (err) { 4246 dev_err(&pdev->dev, 4247 "Allocation for Rx Queue %u failed\n", i); 4248 for (i--; i >= 0; i--) 4249 igb_free_rx_resources(adapter->rx_ring[i]); 4250 break; 4251 } 4252 } 4253 4254 return err; 4255 } 4256 4257 /** 4258 * igb_setup_mrqc - configure the multiple receive queue control registers 4259 * @adapter: Board private structure 4260 **/ 4261 static void igb_setup_mrqc(struct igb_adapter *adapter) 4262 { 4263 struct e1000_hw *hw = &adapter->hw; 4264 u32 mrqc, rxcsum; 4265 u32 j, num_rx_queues; 4266 u32 rss_key[10]; 4267 4268 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4269 for (j = 0; j < 10; j++) 4270 wr32(E1000_RSSRK(j), rss_key[j]); 4271 4272 num_rx_queues = adapter->rss_queues; 4273 4274 switch (hw->mac.type) { 4275 case e1000_82576: 4276 /* 82576 supports 2 RSS queues for SR-IOV */ 4277 if (adapter->vfs_allocated_count) 4278 num_rx_queues = 2; 4279 break; 4280 default: 4281 break; 4282 } 4283 4284 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4285 for (j = 0; j < IGB_RETA_SIZE; j++) 4286 adapter->rss_indir_tbl[j] = 4287 (j * num_rx_queues) / IGB_RETA_SIZE; 4288 adapter->rss_indir_tbl_init = num_rx_queues; 4289 } 4290 igb_write_rss_indir_tbl(adapter); 4291 4292 /* Disable raw packet checksumming so that RSS hash is placed in 4293 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4294 * offloads as they are enabled by default 4295 */ 4296 rxcsum = rd32(E1000_RXCSUM); 4297 rxcsum |= E1000_RXCSUM_PCSD; 4298 4299 if (adapter->hw.mac.type >= e1000_82576) 4300 /* Enable Receive Checksum Offload for SCTP */ 4301 rxcsum |= E1000_RXCSUM_CRCOFL; 4302 4303 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4304 wr32(E1000_RXCSUM, rxcsum); 4305 4306 /* Generate RSS hash based on packet types, TCP/UDP 4307 * port numbers and/or IPv4/v6 src and dst addresses 4308 */ 4309 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4310 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4311 E1000_MRQC_RSS_FIELD_IPV6 | 4312 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4313 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4314 4315 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4316 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4317 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4318 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4319 4320 /* If VMDq is enabled then we set the appropriate mode for that, else 4321 * we default to RSS so that an RSS hash is calculated per packet even 4322 * if we are only using one queue 4323 */ 4324 if (adapter->vfs_allocated_count) { 4325 if (hw->mac.type > e1000_82575) { 4326 /* Set the default pool for the PF's first queue */ 4327 u32 vtctl = rd32(E1000_VT_CTL); 4328 4329 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4330 E1000_VT_CTL_DISABLE_DEF_POOL); 4331 vtctl |= adapter->vfs_allocated_count << 4332 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4333 wr32(E1000_VT_CTL, vtctl); 4334 } 4335 if (adapter->rss_queues > 1) 4336 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4337 else 4338 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4339 } else { 4340 if (hw->mac.type != e1000_i211) 4341 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4342 } 4343 igb_vmm_control(adapter); 4344 4345 wr32(E1000_MRQC, mrqc); 4346 } 4347 4348 /** 4349 * igb_setup_rctl - configure the receive control registers 4350 * @adapter: Board private structure 4351 **/ 4352 void igb_setup_rctl(struct igb_adapter *adapter) 4353 { 4354 struct e1000_hw *hw = &adapter->hw; 4355 u32 rctl; 4356 4357 rctl = rd32(E1000_RCTL); 4358 4359 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4360 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4361 4362 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4363 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4364 4365 /* enable stripping of CRC. It's unlikely this will break BMC 4366 * redirection as it did with e1000. Newer features require 4367 * that the HW strips the CRC. 4368 */ 4369 rctl |= E1000_RCTL_SECRC; 4370 4371 /* disable store bad packets and clear size bits. */ 4372 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4373 4374 /* enable LPE to allow for reception of jumbo frames */ 4375 rctl |= E1000_RCTL_LPE; 4376 4377 /* disable queue 0 to prevent tail write w/o re-config */ 4378 wr32(E1000_RXDCTL(0), 0); 4379 4380 /* Attention!!! For SR-IOV PF driver operations you must enable 4381 * queue drop for all VF and PF queues to prevent head of line blocking 4382 * if an un-trusted VF does not provide descriptors to hardware. 4383 */ 4384 if (adapter->vfs_allocated_count) { 4385 /* set all queue drop enable bits */ 4386 wr32(E1000_QDE, ALL_QUEUES); 4387 } 4388 4389 /* This is useful for sniffing bad packets. */ 4390 if (adapter->netdev->features & NETIF_F_RXALL) { 4391 /* UPE and MPE will be handled by normal PROMISC logic 4392 * in e1000e_set_rx_mode 4393 */ 4394 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4395 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4396 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4397 4398 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4399 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4400 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4401 * and that breaks VLANs. 4402 */ 4403 } 4404 4405 wr32(E1000_RCTL, rctl); 4406 } 4407 4408 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4409 int vfn) 4410 { 4411 struct e1000_hw *hw = &adapter->hw; 4412 u32 vmolr; 4413 4414 if (size > MAX_JUMBO_FRAME_SIZE) 4415 size = MAX_JUMBO_FRAME_SIZE; 4416 4417 vmolr = rd32(E1000_VMOLR(vfn)); 4418 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4419 vmolr |= size | E1000_VMOLR_LPE; 4420 wr32(E1000_VMOLR(vfn), vmolr); 4421 4422 return 0; 4423 } 4424 4425 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4426 int vfn, bool enable) 4427 { 4428 struct e1000_hw *hw = &adapter->hw; 4429 u32 val, reg; 4430 4431 if (hw->mac.type < e1000_82576) 4432 return; 4433 4434 if (hw->mac.type == e1000_i350) 4435 reg = E1000_DVMOLR(vfn); 4436 else 4437 reg = E1000_VMOLR(vfn); 4438 4439 val = rd32(reg); 4440 if (enable) 4441 val |= E1000_VMOLR_STRVLAN; 4442 else 4443 val &= ~(E1000_VMOLR_STRVLAN); 4444 wr32(reg, val); 4445 } 4446 4447 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4448 int vfn, bool aupe) 4449 { 4450 struct e1000_hw *hw = &adapter->hw; 4451 u32 vmolr; 4452 4453 /* This register exists only on 82576 and newer so if we are older then 4454 * we should exit and do nothing 4455 */ 4456 if (hw->mac.type < e1000_82576) 4457 return; 4458 4459 vmolr = rd32(E1000_VMOLR(vfn)); 4460 if (aupe) 4461 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4462 else 4463 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4464 4465 /* clear all bits that might not be set */ 4466 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4467 4468 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4469 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4470 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4471 * multicast packets 4472 */ 4473 if (vfn <= adapter->vfs_allocated_count) 4474 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4475 4476 wr32(E1000_VMOLR(vfn), vmolr); 4477 } 4478 4479 /** 4480 * igb_configure_rx_ring - Configure a receive ring after Reset 4481 * @adapter: board private structure 4482 * @ring: receive ring to be configured 4483 * 4484 * Configure the Rx unit of the MAC after a reset. 4485 **/ 4486 void igb_configure_rx_ring(struct igb_adapter *adapter, 4487 struct igb_ring *ring) 4488 { 4489 struct e1000_hw *hw = &adapter->hw; 4490 union e1000_adv_rx_desc *rx_desc; 4491 u64 rdba = ring->dma; 4492 int reg_idx = ring->reg_idx; 4493 u32 srrctl = 0, rxdctl = 0; 4494 4495 /* disable the queue */ 4496 wr32(E1000_RXDCTL(reg_idx), 0); 4497 4498 /* Set DMA base address registers */ 4499 wr32(E1000_RDBAL(reg_idx), 4500 rdba & 0x00000000ffffffffULL); 4501 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4502 wr32(E1000_RDLEN(reg_idx), 4503 ring->count * sizeof(union e1000_adv_rx_desc)); 4504 4505 /* initialize head and tail */ 4506 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4507 wr32(E1000_RDH(reg_idx), 0); 4508 writel(0, ring->tail); 4509 4510 /* set descriptor configuration */ 4511 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4512 if (ring_uses_large_buffer(ring)) 4513 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4514 else 4515 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4516 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4517 if (hw->mac.type >= e1000_82580) 4518 srrctl |= E1000_SRRCTL_TIMESTAMP; 4519 /* Only set Drop Enable if we are supporting multiple queues */ 4520 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 4521 srrctl |= E1000_SRRCTL_DROP_EN; 4522 4523 wr32(E1000_SRRCTL(reg_idx), srrctl); 4524 4525 /* set filtering for VMDQ pools */ 4526 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4527 4528 rxdctl |= IGB_RX_PTHRESH; 4529 rxdctl |= IGB_RX_HTHRESH << 8; 4530 rxdctl |= IGB_RX_WTHRESH << 16; 4531 4532 /* initialize rx_buffer_info */ 4533 memset(ring->rx_buffer_info, 0, 4534 sizeof(struct igb_rx_buffer) * ring->count); 4535 4536 /* initialize Rx descriptor 0 */ 4537 rx_desc = IGB_RX_DESC(ring, 0); 4538 rx_desc->wb.upper.length = 0; 4539 4540 /* enable receive descriptor fetching */ 4541 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4542 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4543 } 4544 4545 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4546 struct igb_ring *rx_ring) 4547 { 4548 /* set build_skb and buffer size flags */ 4549 clear_ring_build_skb_enabled(rx_ring); 4550 clear_ring_uses_large_buffer(rx_ring); 4551 4552 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4553 return; 4554 4555 set_ring_build_skb_enabled(rx_ring); 4556 4557 #if (PAGE_SIZE < 8192) 4558 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4559 return; 4560 4561 set_ring_uses_large_buffer(rx_ring); 4562 #endif 4563 } 4564 4565 /** 4566 * igb_configure_rx - Configure receive Unit after Reset 4567 * @adapter: board private structure 4568 * 4569 * Configure the Rx unit of the MAC after a reset. 4570 **/ 4571 static void igb_configure_rx(struct igb_adapter *adapter) 4572 { 4573 int i; 4574 4575 /* set the correct pool for the PF default MAC address in entry 0 */ 4576 igb_set_default_mac_filter(adapter); 4577 4578 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4579 * the Base and Length of the Rx Descriptor Ring 4580 */ 4581 for (i = 0; i < adapter->num_rx_queues; i++) { 4582 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4583 4584 igb_set_rx_buffer_len(adapter, rx_ring); 4585 igb_configure_rx_ring(adapter, rx_ring); 4586 } 4587 } 4588 4589 /** 4590 * igb_free_tx_resources - Free Tx Resources per Queue 4591 * @tx_ring: Tx descriptor ring for a specific queue 4592 * 4593 * Free all transmit software resources 4594 **/ 4595 void igb_free_tx_resources(struct igb_ring *tx_ring) 4596 { 4597 igb_clean_tx_ring(tx_ring); 4598 4599 vfree(tx_ring->tx_buffer_info); 4600 tx_ring->tx_buffer_info = NULL; 4601 4602 /* if not set, then don't free */ 4603 if (!tx_ring->desc) 4604 return; 4605 4606 dma_free_coherent(tx_ring->dev, tx_ring->size, 4607 tx_ring->desc, tx_ring->dma); 4608 4609 tx_ring->desc = NULL; 4610 } 4611 4612 /** 4613 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4614 * @adapter: board private structure 4615 * 4616 * Free all transmit software resources 4617 **/ 4618 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4619 { 4620 int i; 4621 4622 for (i = 0; i < adapter->num_tx_queues; i++) 4623 if (adapter->tx_ring[i]) 4624 igb_free_tx_resources(adapter->tx_ring[i]); 4625 } 4626 4627 /** 4628 * igb_clean_tx_ring - Free Tx Buffers 4629 * @tx_ring: ring to be cleaned 4630 **/ 4631 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 4632 { 4633 u16 i = tx_ring->next_to_clean; 4634 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4635 4636 while (i != tx_ring->next_to_use) { 4637 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4638 4639 /* Free all the Tx ring sk_buffs */ 4640 dev_kfree_skb_any(tx_buffer->skb); 4641 4642 /* unmap skb header data */ 4643 dma_unmap_single(tx_ring->dev, 4644 dma_unmap_addr(tx_buffer, dma), 4645 dma_unmap_len(tx_buffer, len), 4646 DMA_TO_DEVICE); 4647 4648 /* check for eop_desc to determine the end of the packet */ 4649 eop_desc = tx_buffer->next_to_watch; 4650 tx_desc = IGB_TX_DESC(tx_ring, i); 4651 4652 /* unmap remaining buffers */ 4653 while (tx_desc != eop_desc) { 4654 tx_buffer++; 4655 tx_desc++; 4656 i++; 4657 if (unlikely(i == tx_ring->count)) { 4658 i = 0; 4659 tx_buffer = tx_ring->tx_buffer_info; 4660 tx_desc = IGB_TX_DESC(tx_ring, 0); 4661 } 4662 4663 /* unmap any remaining paged data */ 4664 if (dma_unmap_len(tx_buffer, len)) 4665 dma_unmap_page(tx_ring->dev, 4666 dma_unmap_addr(tx_buffer, dma), 4667 dma_unmap_len(tx_buffer, len), 4668 DMA_TO_DEVICE); 4669 } 4670 4671 /* move us one more past the eop_desc for start of next pkt */ 4672 tx_buffer++; 4673 i++; 4674 if (unlikely(i == tx_ring->count)) { 4675 i = 0; 4676 tx_buffer = tx_ring->tx_buffer_info; 4677 } 4678 } 4679 4680 /* reset BQL for queue */ 4681 netdev_tx_reset_queue(txring_txq(tx_ring)); 4682 4683 /* reset next_to_use and next_to_clean */ 4684 tx_ring->next_to_use = 0; 4685 tx_ring->next_to_clean = 0; 4686 } 4687 4688 /** 4689 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 4690 * @adapter: board private structure 4691 **/ 4692 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 4693 { 4694 int i; 4695 4696 for (i = 0; i < adapter->num_tx_queues; i++) 4697 if (adapter->tx_ring[i]) 4698 igb_clean_tx_ring(adapter->tx_ring[i]); 4699 } 4700 4701 /** 4702 * igb_free_rx_resources - Free Rx Resources 4703 * @rx_ring: ring to clean the resources from 4704 * 4705 * Free all receive software resources 4706 **/ 4707 void igb_free_rx_resources(struct igb_ring *rx_ring) 4708 { 4709 igb_clean_rx_ring(rx_ring); 4710 4711 vfree(rx_ring->rx_buffer_info); 4712 rx_ring->rx_buffer_info = NULL; 4713 4714 /* if not set, then don't free */ 4715 if (!rx_ring->desc) 4716 return; 4717 4718 dma_free_coherent(rx_ring->dev, rx_ring->size, 4719 rx_ring->desc, rx_ring->dma); 4720 4721 rx_ring->desc = NULL; 4722 } 4723 4724 /** 4725 * igb_free_all_rx_resources - Free Rx Resources for All Queues 4726 * @adapter: board private structure 4727 * 4728 * Free all receive software resources 4729 **/ 4730 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 4731 { 4732 int i; 4733 4734 for (i = 0; i < adapter->num_rx_queues; i++) 4735 if (adapter->rx_ring[i]) 4736 igb_free_rx_resources(adapter->rx_ring[i]); 4737 } 4738 4739 /** 4740 * igb_clean_rx_ring - Free Rx Buffers per Queue 4741 * @rx_ring: ring to free buffers from 4742 **/ 4743 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 4744 { 4745 u16 i = rx_ring->next_to_clean; 4746 4747 if (rx_ring->skb) 4748 dev_kfree_skb(rx_ring->skb); 4749 rx_ring->skb = NULL; 4750 4751 /* Free all the Rx ring sk_buffs */ 4752 while (i != rx_ring->next_to_alloc) { 4753 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 4754 4755 /* Invalidate cache lines that may have been written to by 4756 * device so that we avoid corrupting memory. 4757 */ 4758 dma_sync_single_range_for_cpu(rx_ring->dev, 4759 buffer_info->dma, 4760 buffer_info->page_offset, 4761 igb_rx_bufsz(rx_ring), 4762 DMA_FROM_DEVICE); 4763 4764 /* free resources associated with mapping */ 4765 dma_unmap_page_attrs(rx_ring->dev, 4766 buffer_info->dma, 4767 igb_rx_pg_size(rx_ring), 4768 DMA_FROM_DEVICE, 4769 IGB_RX_DMA_ATTR); 4770 __page_frag_cache_drain(buffer_info->page, 4771 buffer_info->pagecnt_bias); 4772 4773 i++; 4774 if (i == rx_ring->count) 4775 i = 0; 4776 } 4777 4778 rx_ring->next_to_alloc = 0; 4779 rx_ring->next_to_clean = 0; 4780 rx_ring->next_to_use = 0; 4781 } 4782 4783 /** 4784 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 4785 * @adapter: board private structure 4786 **/ 4787 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 4788 { 4789 int i; 4790 4791 for (i = 0; i < adapter->num_rx_queues; i++) 4792 if (adapter->rx_ring[i]) 4793 igb_clean_rx_ring(adapter->rx_ring[i]); 4794 } 4795 4796 /** 4797 * igb_set_mac - Change the Ethernet Address of the NIC 4798 * @netdev: network interface device structure 4799 * @p: pointer to an address structure 4800 * 4801 * Returns 0 on success, negative on failure 4802 **/ 4803 static int igb_set_mac(struct net_device *netdev, void *p) 4804 { 4805 struct igb_adapter *adapter = netdev_priv(netdev); 4806 struct e1000_hw *hw = &adapter->hw; 4807 struct sockaddr *addr = p; 4808 4809 if (!is_valid_ether_addr(addr->sa_data)) 4810 return -EADDRNOTAVAIL; 4811 4812 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4813 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 4814 4815 /* set the correct pool for the new PF MAC address in entry 0 */ 4816 igb_set_default_mac_filter(adapter); 4817 4818 return 0; 4819 } 4820 4821 /** 4822 * igb_write_mc_addr_list - write multicast addresses to MTA 4823 * @netdev: network interface device structure 4824 * 4825 * Writes multicast address list to the MTA hash table. 4826 * Returns: -ENOMEM on failure 4827 * 0 on no addresses written 4828 * X on writing X addresses to MTA 4829 **/ 4830 static int igb_write_mc_addr_list(struct net_device *netdev) 4831 { 4832 struct igb_adapter *adapter = netdev_priv(netdev); 4833 struct e1000_hw *hw = &adapter->hw; 4834 struct netdev_hw_addr *ha; 4835 u8 *mta_list; 4836 int i; 4837 4838 if (netdev_mc_empty(netdev)) { 4839 /* nothing to program, so clear mc list */ 4840 igb_update_mc_addr_list(hw, NULL, 0); 4841 igb_restore_vf_multicasts(adapter); 4842 return 0; 4843 } 4844 4845 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 4846 if (!mta_list) 4847 return -ENOMEM; 4848 4849 /* The shared function expects a packed array of only addresses. */ 4850 i = 0; 4851 netdev_for_each_mc_addr(ha, netdev) 4852 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 4853 4854 igb_update_mc_addr_list(hw, mta_list, i); 4855 kfree(mta_list); 4856 4857 return netdev_mc_count(netdev); 4858 } 4859 4860 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 4861 { 4862 struct e1000_hw *hw = &adapter->hw; 4863 u32 i, pf_id; 4864 4865 switch (hw->mac.type) { 4866 case e1000_i210: 4867 case e1000_i211: 4868 case e1000_i350: 4869 /* VLAN filtering needed for VLAN prio filter */ 4870 if (adapter->netdev->features & NETIF_F_NTUPLE) 4871 break; 4872 /* fall through */ 4873 case e1000_82576: 4874 case e1000_82580: 4875 case e1000_i354: 4876 /* VLAN filtering needed for pool filtering */ 4877 if (adapter->vfs_allocated_count) 4878 break; 4879 /* fall through */ 4880 default: 4881 return 1; 4882 } 4883 4884 /* We are already in VLAN promisc, nothing to do */ 4885 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 4886 return 0; 4887 4888 if (!adapter->vfs_allocated_count) 4889 goto set_vfta; 4890 4891 /* Add PF to all active pools */ 4892 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4893 4894 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4895 u32 vlvf = rd32(E1000_VLVF(i)); 4896 4897 vlvf |= BIT(pf_id); 4898 wr32(E1000_VLVF(i), vlvf); 4899 } 4900 4901 set_vfta: 4902 /* Set all bits in the VLAN filter table array */ 4903 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 4904 hw->mac.ops.write_vfta(hw, i, ~0U); 4905 4906 /* Set flag so we don't redo unnecessary work */ 4907 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 4908 4909 return 0; 4910 } 4911 4912 #define VFTA_BLOCK_SIZE 8 4913 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 4914 { 4915 struct e1000_hw *hw = &adapter->hw; 4916 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4917 u32 vid_start = vfta_offset * 32; 4918 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4919 u32 i, vid, word, bits, pf_id; 4920 4921 /* guarantee that we don't scrub out management VLAN */ 4922 vid = adapter->mng_vlan_id; 4923 if (vid >= vid_start && vid < vid_end) 4924 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4925 4926 if (!adapter->vfs_allocated_count) 4927 goto set_vfta; 4928 4929 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4930 4931 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4932 u32 vlvf = rd32(E1000_VLVF(i)); 4933 4934 /* pull VLAN ID from VLVF */ 4935 vid = vlvf & VLAN_VID_MASK; 4936 4937 /* only concern ourselves with a certain range */ 4938 if (vid < vid_start || vid >= vid_end) 4939 continue; 4940 4941 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 4942 /* record VLAN ID in VFTA */ 4943 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4944 4945 /* if PF is part of this then continue */ 4946 if (test_bit(vid, adapter->active_vlans)) 4947 continue; 4948 } 4949 4950 /* remove PF from the pool */ 4951 bits = ~BIT(pf_id); 4952 bits &= rd32(E1000_VLVF(i)); 4953 wr32(E1000_VLVF(i), bits); 4954 } 4955 4956 set_vfta: 4957 /* extract values from active_vlans and write back to VFTA */ 4958 for (i = VFTA_BLOCK_SIZE; i--;) { 4959 vid = (vfta_offset + i) * 32; 4960 word = vid / BITS_PER_LONG; 4961 bits = vid % BITS_PER_LONG; 4962 4963 vfta[i] |= adapter->active_vlans[word] >> bits; 4964 4965 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 4966 } 4967 } 4968 4969 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 4970 { 4971 u32 i; 4972 4973 /* We are not in VLAN promisc, nothing to do */ 4974 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 4975 return; 4976 4977 /* Set flag so we don't redo unnecessary work */ 4978 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 4979 4980 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 4981 igb_scrub_vfta(adapter, i); 4982 } 4983 4984 /** 4985 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 4986 * @netdev: network interface device structure 4987 * 4988 * The set_rx_mode entry point is called whenever the unicast or multicast 4989 * address lists or the network interface flags are updated. This routine is 4990 * responsible for configuring the hardware for proper unicast, multicast, 4991 * promiscuous mode, and all-multi behavior. 4992 **/ 4993 static void igb_set_rx_mode(struct net_device *netdev) 4994 { 4995 struct igb_adapter *adapter = netdev_priv(netdev); 4996 struct e1000_hw *hw = &adapter->hw; 4997 unsigned int vfn = adapter->vfs_allocated_count; 4998 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 4999 int count; 5000 5001 /* Check for Promiscuous and All Multicast modes */ 5002 if (netdev->flags & IFF_PROMISC) { 5003 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5004 vmolr |= E1000_VMOLR_MPME; 5005 5006 /* enable use of UTA filter to force packets to default pool */ 5007 if (hw->mac.type == e1000_82576) 5008 vmolr |= E1000_VMOLR_ROPE; 5009 } else { 5010 if (netdev->flags & IFF_ALLMULTI) { 5011 rctl |= E1000_RCTL_MPE; 5012 vmolr |= E1000_VMOLR_MPME; 5013 } else { 5014 /* Write addresses to the MTA, if the attempt fails 5015 * then we should just turn on promiscuous mode so 5016 * that we can at least receive multicast traffic 5017 */ 5018 count = igb_write_mc_addr_list(netdev); 5019 if (count < 0) { 5020 rctl |= E1000_RCTL_MPE; 5021 vmolr |= E1000_VMOLR_MPME; 5022 } else if (count) { 5023 vmolr |= E1000_VMOLR_ROMPE; 5024 } 5025 } 5026 } 5027 5028 /* Write addresses to available RAR registers, if there is not 5029 * sufficient space to store all the addresses then enable 5030 * unicast promiscuous mode 5031 */ 5032 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5033 rctl |= E1000_RCTL_UPE; 5034 vmolr |= E1000_VMOLR_ROPE; 5035 } 5036 5037 /* enable VLAN filtering by default */ 5038 rctl |= E1000_RCTL_VFE; 5039 5040 /* disable VLAN filtering for modes that require it */ 5041 if ((netdev->flags & IFF_PROMISC) || 5042 (netdev->features & NETIF_F_RXALL)) { 5043 /* if we fail to set all rules then just clear VFE */ 5044 if (igb_vlan_promisc_enable(adapter)) 5045 rctl &= ~E1000_RCTL_VFE; 5046 } else { 5047 igb_vlan_promisc_disable(adapter); 5048 } 5049 5050 /* update state of unicast, multicast, and VLAN filtering modes */ 5051 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5052 E1000_RCTL_VFE); 5053 wr32(E1000_RCTL, rctl); 5054 5055 #if (PAGE_SIZE < 8192) 5056 if (!adapter->vfs_allocated_count) { 5057 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5058 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5059 } 5060 #endif 5061 wr32(E1000_RLPML, rlpml); 5062 5063 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5064 * the VMOLR to enable the appropriate modes. Without this workaround 5065 * we will have issues with VLAN tag stripping not being done for frames 5066 * that are only arriving because we are the default pool 5067 */ 5068 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5069 return; 5070 5071 /* set UTA to appropriate mode */ 5072 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5073 5074 vmolr |= rd32(E1000_VMOLR(vfn)) & 5075 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5076 5077 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5078 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5079 #if (PAGE_SIZE < 8192) 5080 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5081 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5082 else 5083 #endif 5084 vmolr |= MAX_JUMBO_FRAME_SIZE; 5085 vmolr |= E1000_VMOLR_LPE; 5086 5087 wr32(E1000_VMOLR(vfn), vmolr); 5088 5089 igb_restore_vf_multicasts(adapter); 5090 } 5091 5092 static void igb_check_wvbr(struct igb_adapter *adapter) 5093 { 5094 struct e1000_hw *hw = &adapter->hw; 5095 u32 wvbr = 0; 5096 5097 switch (hw->mac.type) { 5098 case e1000_82576: 5099 case e1000_i350: 5100 wvbr = rd32(E1000_WVBR); 5101 if (!wvbr) 5102 return; 5103 break; 5104 default: 5105 break; 5106 } 5107 5108 adapter->wvbr |= wvbr; 5109 } 5110 5111 #define IGB_STAGGERED_QUEUE_OFFSET 8 5112 5113 static void igb_spoof_check(struct igb_adapter *adapter) 5114 { 5115 int j; 5116 5117 if (!adapter->wvbr) 5118 return; 5119 5120 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5121 if (adapter->wvbr & BIT(j) || 5122 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5123 dev_warn(&adapter->pdev->dev, 5124 "Spoof event(s) detected on VF %d\n", j); 5125 adapter->wvbr &= 5126 ~(BIT(j) | 5127 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5128 } 5129 } 5130 } 5131 5132 /* Need to wait a few seconds after link up to get diagnostic information from 5133 * the phy 5134 */ 5135 static void igb_update_phy_info(struct timer_list *t) 5136 { 5137 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5138 igb_get_phy_info(&adapter->hw); 5139 } 5140 5141 /** 5142 * igb_has_link - check shared code for link and determine up/down 5143 * @adapter: pointer to driver private info 5144 **/ 5145 bool igb_has_link(struct igb_adapter *adapter) 5146 { 5147 struct e1000_hw *hw = &adapter->hw; 5148 bool link_active = false; 5149 5150 /* get_link_status is set on LSC (link status) interrupt or 5151 * rx sequence error interrupt. get_link_status will stay 5152 * false until the e1000_check_for_link establishes link 5153 * for copper adapters ONLY 5154 */ 5155 switch (hw->phy.media_type) { 5156 case e1000_media_type_copper: 5157 if (!hw->mac.get_link_status) 5158 return true; 5159 /* fall through */ 5160 case e1000_media_type_internal_serdes: 5161 hw->mac.ops.check_for_link(hw); 5162 link_active = !hw->mac.get_link_status; 5163 break; 5164 default: 5165 case e1000_media_type_unknown: 5166 break; 5167 } 5168 5169 if (((hw->mac.type == e1000_i210) || 5170 (hw->mac.type == e1000_i211)) && 5171 (hw->phy.id == I210_I_PHY_ID)) { 5172 if (!netif_carrier_ok(adapter->netdev)) { 5173 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5174 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5175 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5176 adapter->link_check_timeout = jiffies; 5177 } 5178 } 5179 5180 return link_active; 5181 } 5182 5183 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5184 { 5185 bool ret = false; 5186 u32 ctrl_ext, thstat; 5187 5188 /* check for thermal sensor event on i350 copper only */ 5189 if (hw->mac.type == e1000_i350) { 5190 thstat = rd32(E1000_THSTAT); 5191 ctrl_ext = rd32(E1000_CTRL_EXT); 5192 5193 if ((hw->phy.media_type == e1000_media_type_copper) && 5194 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5195 ret = !!(thstat & event); 5196 } 5197 5198 return ret; 5199 } 5200 5201 /** 5202 * igb_check_lvmmc - check for malformed packets received 5203 * and indicated in LVMMC register 5204 * @adapter: pointer to adapter 5205 **/ 5206 static void igb_check_lvmmc(struct igb_adapter *adapter) 5207 { 5208 struct e1000_hw *hw = &adapter->hw; 5209 u32 lvmmc; 5210 5211 lvmmc = rd32(E1000_LVMMC); 5212 if (lvmmc) { 5213 if (unlikely(net_ratelimit())) { 5214 netdev_warn(adapter->netdev, 5215 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5216 lvmmc); 5217 } 5218 } 5219 } 5220 5221 /** 5222 * igb_watchdog - Timer Call-back 5223 * @data: pointer to adapter cast into an unsigned long 5224 **/ 5225 static void igb_watchdog(struct timer_list *t) 5226 { 5227 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5228 /* Do the rest outside of interrupt context */ 5229 schedule_work(&adapter->watchdog_task); 5230 } 5231 5232 static void igb_watchdog_task(struct work_struct *work) 5233 { 5234 struct igb_adapter *adapter = container_of(work, 5235 struct igb_adapter, 5236 watchdog_task); 5237 struct e1000_hw *hw = &adapter->hw; 5238 struct e1000_phy_info *phy = &hw->phy; 5239 struct net_device *netdev = adapter->netdev; 5240 u32 link; 5241 int i; 5242 u32 connsw; 5243 u16 phy_data, retry_count = 20; 5244 5245 link = igb_has_link(adapter); 5246 5247 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5248 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5249 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5250 else 5251 link = false; 5252 } 5253 5254 /* Force link down if we have fiber to swap to */ 5255 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5256 if (hw->phy.media_type == e1000_media_type_copper) { 5257 connsw = rd32(E1000_CONNSW); 5258 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5259 link = 0; 5260 } 5261 } 5262 if (link) { 5263 /* Perform a reset if the media type changed. */ 5264 if (hw->dev_spec._82575.media_changed) { 5265 hw->dev_spec._82575.media_changed = false; 5266 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5267 igb_reset(adapter); 5268 } 5269 /* Cancel scheduled suspend requests. */ 5270 pm_runtime_resume(netdev->dev.parent); 5271 5272 if (!netif_carrier_ok(netdev)) { 5273 u32 ctrl; 5274 5275 hw->mac.ops.get_speed_and_duplex(hw, 5276 &adapter->link_speed, 5277 &adapter->link_duplex); 5278 5279 ctrl = rd32(E1000_CTRL); 5280 /* Links status message must follow this format */ 5281 netdev_info(netdev, 5282 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5283 netdev->name, 5284 adapter->link_speed, 5285 adapter->link_duplex == FULL_DUPLEX ? 5286 "Full" : "Half", 5287 (ctrl & E1000_CTRL_TFCE) && 5288 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5289 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5290 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5291 5292 /* disable EEE if enabled */ 5293 if ((adapter->flags & IGB_FLAG_EEE) && 5294 (adapter->link_duplex == HALF_DUPLEX)) { 5295 dev_info(&adapter->pdev->dev, 5296 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5297 adapter->hw.dev_spec._82575.eee_disable = true; 5298 adapter->flags &= ~IGB_FLAG_EEE; 5299 } 5300 5301 /* check if SmartSpeed worked */ 5302 igb_check_downshift(hw); 5303 if (phy->speed_downgraded) 5304 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5305 5306 /* check for thermal sensor event */ 5307 if (igb_thermal_sensor_event(hw, 5308 E1000_THSTAT_LINK_THROTTLE)) 5309 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5310 5311 /* adjust timeout factor according to speed/duplex */ 5312 adapter->tx_timeout_factor = 1; 5313 switch (adapter->link_speed) { 5314 case SPEED_10: 5315 adapter->tx_timeout_factor = 14; 5316 break; 5317 case SPEED_100: 5318 /* maybe add some timeout factor ? */ 5319 break; 5320 } 5321 5322 if (adapter->link_speed != SPEED_1000) 5323 goto no_wait; 5324 5325 /* wait for Remote receiver status OK */ 5326 retry_read_status: 5327 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5328 &phy_data)) { 5329 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5330 retry_count) { 5331 msleep(100); 5332 retry_count--; 5333 goto retry_read_status; 5334 } else if (!retry_count) { 5335 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5336 } 5337 } else { 5338 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5339 } 5340 no_wait: 5341 netif_carrier_on(netdev); 5342 5343 igb_ping_all_vfs(adapter); 5344 igb_check_vf_rate_limit(adapter); 5345 5346 /* link state has changed, schedule phy info update */ 5347 if (!test_bit(__IGB_DOWN, &adapter->state)) 5348 mod_timer(&adapter->phy_info_timer, 5349 round_jiffies(jiffies + 2 * HZ)); 5350 } 5351 } else { 5352 if (netif_carrier_ok(netdev)) { 5353 adapter->link_speed = 0; 5354 adapter->link_duplex = 0; 5355 5356 /* check for thermal sensor event */ 5357 if (igb_thermal_sensor_event(hw, 5358 E1000_THSTAT_PWR_DOWN)) { 5359 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5360 } 5361 5362 /* Links status message must follow this format */ 5363 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5364 netdev->name); 5365 netif_carrier_off(netdev); 5366 5367 igb_ping_all_vfs(adapter); 5368 5369 /* link state has changed, schedule phy info update */ 5370 if (!test_bit(__IGB_DOWN, &adapter->state)) 5371 mod_timer(&adapter->phy_info_timer, 5372 round_jiffies(jiffies + 2 * HZ)); 5373 5374 /* link is down, time to check for alternate media */ 5375 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5376 igb_check_swap_media(adapter); 5377 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5378 schedule_work(&adapter->reset_task); 5379 /* return immediately */ 5380 return; 5381 } 5382 } 5383 pm_schedule_suspend(netdev->dev.parent, 5384 MSEC_PER_SEC * 5); 5385 5386 /* also check for alternate media here */ 5387 } else if (!netif_carrier_ok(netdev) && 5388 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5389 igb_check_swap_media(adapter); 5390 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5391 schedule_work(&adapter->reset_task); 5392 /* return immediately */ 5393 return; 5394 } 5395 } 5396 } 5397 5398 spin_lock(&adapter->stats64_lock); 5399 igb_update_stats(adapter); 5400 spin_unlock(&adapter->stats64_lock); 5401 5402 for (i = 0; i < adapter->num_tx_queues; i++) { 5403 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5404 if (!netif_carrier_ok(netdev)) { 5405 /* We've lost link, so the controller stops DMA, 5406 * but we've got queued Tx work that's never going 5407 * to get done, so reset controller to flush Tx. 5408 * (Do the reset outside of interrupt context). 5409 */ 5410 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5411 adapter->tx_timeout_count++; 5412 schedule_work(&adapter->reset_task); 5413 /* return immediately since reset is imminent */ 5414 return; 5415 } 5416 } 5417 5418 /* Force detection of hung controller every watchdog period */ 5419 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5420 } 5421 5422 /* Cause software interrupt to ensure Rx ring is cleaned */ 5423 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5424 u32 eics = 0; 5425 5426 for (i = 0; i < adapter->num_q_vectors; i++) 5427 eics |= adapter->q_vector[i]->eims_value; 5428 wr32(E1000_EICS, eics); 5429 } else { 5430 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5431 } 5432 5433 igb_spoof_check(adapter); 5434 igb_ptp_rx_hang(adapter); 5435 igb_ptp_tx_hang(adapter); 5436 5437 /* Check LVMMC register on i350/i354 only */ 5438 if ((adapter->hw.mac.type == e1000_i350) || 5439 (adapter->hw.mac.type == e1000_i354)) 5440 igb_check_lvmmc(adapter); 5441 5442 /* Reset the timer */ 5443 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5444 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5445 mod_timer(&adapter->watchdog_timer, 5446 round_jiffies(jiffies + HZ)); 5447 else 5448 mod_timer(&adapter->watchdog_timer, 5449 round_jiffies(jiffies + 2 * HZ)); 5450 } 5451 } 5452 5453 enum latency_range { 5454 lowest_latency = 0, 5455 low_latency = 1, 5456 bulk_latency = 2, 5457 latency_invalid = 255 5458 }; 5459 5460 /** 5461 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5462 * @q_vector: pointer to q_vector 5463 * 5464 * Stores a new ITR value based on strictly on packet size. This 5465 * algorithm is less sophisticated than that used in igb_update_itr, 5466 * due to the difficulty of synchronizing statistics across multiple 5467 * receive rings. The divisors and thresholds used by this function 5468 * were determined based on theoretical maximum wire speed and testing 5469 * data, in order to minimize response time while increasing bulk 5470 * throughput. 5471 * This functionality is controlled by ethtool's coalescing settings. 5472 * NOTE: This function is called only when operating in a multiqueue 5473 * receive environment. 5474 **/ 5475 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5476 { 5477 int new_val = q_vector->itr_val; 5478 int avg_wire_size = 0; 5479 struct igb_adapter *adapter = q_vector->adapter; 5480 unsigned int packets; 5481 5482 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5483 * ints/sec - ITR timer value of 120 ticks. 5484 */ 5485 if (adapter->link_speed != SPEED_1000) { 5486 new_val = IGB_4K_ITR; 5487 goto set_itr_val; 5488 } 5489 5490 packets = q_vector->rx.total_packets; 5491 if (packets) 5492 avg_wire_size = q_vector->rx.total_bytes / packets; 5493 5494 packets = q_vector->tx.total_packets; 5495 if (packets) 5496 avg_wire_size = max_t(u32, avg_wire_size, 5497 q_vector->tx.total_bytes / packets); 5498 5499 /* if avg_wire_size isn't set no work was done */ 5500 if (!avg_wire_size) 5501 goto clear_counts; 5502 5503 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5504 avg_wire_size += 24; 5505 5506 /* Don't starve jumbo frames */ 5507 avg_wire_size = min(avg_wire_size, 3000); 5508 5509 /* Give a little boost to mid-size frames */ 5510 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5511 new_val = avg_wire_size / 3; 5512 else 5513 new_val = avg_wire_size / 2; 5514 5515 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5516 if (new_val < IGB_20K_ITR && 5517 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5518 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5519 new_val = IGB_20K_ITR; 5520 5521 set_itr_val: 5522 if (new_val != q_vector->itr_val) { 5523 q_vector->itr_val = new_val; 5524 q_vector->set_itr = 1; 5525 } 5526 clear_counts: 5527 q_vector->rx.total_bytes = 0; 5528 q_vector->rx.total_packets = 0; 5529 q_vector->tx.total_bytes = 0; 5530 q_vector->tx.total_packets = 0; 5531 } 5532 5533 /** 5534 * igb_update_itr - update the dynamic ITR value based on statistics 5535 * @q_vector: pointer to q_vector 5536 * @ring_container: ring info to update the itr for 5537 * 5538 * Stores a new ITR value based on packets and byte 5539 * counts during the last interrupt. The advantage of per interrupt 5540 * computation is faster updates and more accurate ITR for the current 5541 * traffic pattern. Constants in this function were computed 5542 * based on theoretical maximum wire speed and thresholds were set based 5543 * on testing data as well as attempting to minimize response time 5544 * while increasing bulk throughput. 5545 * This functionality is controlled by ethtool's coalescing settings. 5546 * NOTE: These calculations are only valid when operating in a single- 5547 * queue environment. 5548 **/ 5549 static void igb_update_itr(struct igb_q_vector *q_vector, 5550 struct igb_ring_container *ring_container) 5551 { 5552 unsigned int packets = ring_container->total_packets; 5553 unsigned int bytes = ring_container->total_bytes; 5554 u8 itrval = ring_container->itr; 5555 5556 /* no packets, exit with status unchanged */ 5557 if (packets == 0) 5558 return; 5559 5560 switch (itrval) { 5561 case lowest_latency: 5562 /* handle TSO and jumbo frames */ 5563 if (bytes/packets > 8000) 5564 itrval = bulk_latency; 5565 else if ((packets < 5) && (bytes > 512)) 5566 itrval = low_latency; 5567 break; 5568 case low_latency: /* 50 usec aka 20000 ints/s */ 5569 if (bytes > 10000) { 5570 /* this if handles the TSO accounting */ 5571 if (bytes/packets > 8000) 5572 itrval = bulk_latency; 5573 else if ((packets < 10) || ((bytes/packets) > 1200)) 5574 itrval = bulk_latency; 5575 else if ((packets > 35)) 5576 itrval = lowest_latency; 5577 } else if (bytes/packets > 2000) { 5578 itrval = bulk_latency; 5579 } else if (packets <= 2 && bytes < 512) { 5580 itrval = lowest_latency; 5581 } 5582 break; 5583 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5584 if (bytes > 25000) { 5585 if (packets > 35) 5586 itrval = low_latency; 5587 } else if (bytes < 1500) { 5588 itrval = low_latency; 5589 } 5590 break; 5591 } 5592 5593 /* clear work counters since we have the values we need */ 5594 ring_container->total_bytes = 0; 5595 ring_container->total_packets = 0; 5596 5597 /* write updated itr to ring container */ 5598 ring_container->itr = itrval; 5599 } 5600 5601 static void igb_set_itr(struct igb_q_vector *q_vector) 5602 { 5603 struct igb_adapter *adapter = q_vector->adapter; 5604 u32 new_itr = q_vector->itr_val; 5605 u8 current_itr = 0; 5606 5607 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5608 if (adapter->link_speed != SPEED_1000) { 5609 current_itr = 0; 5610 new_itr = IGB_4K_ITR; 5611 goto set_itr_now; 5612 } 5613 5614 igb_update_itr(q_vector, &q_vector->tx); 5615 igb_update_itr(q_vector, &q_vector->rx); 5616 5617 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5618 5619 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5620 if (current_itr == lowest_latency && 5621 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5622 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5623 current_itr = low_latency; 5624 5625 switch (current_itr) { 5626 /* counts and packets in update_itr are dependent on these numbers */ 5627 case lowest_latency: 5628 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5629 break; 5630 case low_latency: 5631 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5632 break; 5633 case bulk_latency: 5634 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5635 break; 5636 default: 5637 break; 5638 } 5639 5640 set_itr_now: 5641 if (new_itr != q_vector->itr_val) { 5642 /* this attempts to bias the interrupt rate towards Bulk 5643 * by adding intermediate steps when interrupt rate is 5644 * increasing 5645 */ 5646 new_itr = new_itr > q_vector->itr_val ? 5647 max((new_itr * q_vector->itr_val) / 5648 (new_itr + (q_vector->itr_val >> 2)), 5649 new_itr) : new_itr; 5650 /* Don't write the value here; it resets the adapter's 5651 * internal timer, and causes us to delay far longer than 5652 * we should between interrupts. Instead, we write the ITR 5653 * value at the beginning of the next interrupt so the timing 5654 * ends up being correct. 5655 */ 5656 q_vector->itr_val = new_itr; 5657 q_vector->set_itr = 1; 5658 } 5659 } 5660 5661 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 5662 struct igb_tx_buffer *first, 5663 u32 vlan_macip_lens, u32 type_tucmd, 5664 u32 mss_l4len_idx) 5665 { 5666 struct e1000_adv_tx_context_desc *context_desc; 5667 u16 i = tx_ring->next_to_use; 5668 struct timespec64 ts; 5669 5670 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5671 5672 i++; 5673 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 5674 5675 /* set bits to identify this as an advanced context descriptor */ 5676 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 5677 5678 /* For 82575, context index must be unique per ring. */ 5679 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5680 mss_l4len_idx |= tx_ring->reg_idx << 4; 5681 5682 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5683 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5684 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5685 5686 /* We assume there is always a valid tx time available. Invalid times 5687 * should have been handled by the upper layers. 5688 */ 5689 if (tx_ring->launchtime_enable) { 5690 ts = ns_to_timespec64(first->skb->tstamp); 5691 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 5692 } else { 5693 context_desc->seqnum_seed = 0; 5694 } 5695 } 5696 5697 static int igb_tso(struct igb_ring *tx_ring, 5698 struct igb_tx_buffer *first, 5699 u8 *hdr_len) 5700 { 5701 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 5702 struct sk_buff *skb = first->skb; 5703 union { 5704 struct iphdr *v4; 5705 struct ipv6hdr *v6; 5706 unsigned char *hdr; 5707 } ip; 5708 union { 5709 struct tcphdr *tcp; 5710 unsigned char *hdr; 5711 } l4; 5712 u32 paylen, l4_offset; 5713 int err; 5714 5715 if (skb->ip_summed != CHECKSUM_PARTIAL) 5716 return 0; 5717 5718 if (!skb_is_gso(skb)) 5719 return 0; 5720 5721 err = skb_cow_head(skb, 0); 5722 if (err < 0) 5723 return err; 5724 5725 ip.hdr = skb_network_header(skb); 5726 l4.hdr = skb_checksum_start(skb); 5727 5728 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 5729 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 5730 5731 /* initialize outer IP header fields */ 5732 if (ip.v4->version == 4) { 5733 unsigned char *csum_start = skb_checksum_start(skb); 5734 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 5735 5736 /* IP header will have to cancel out any data that 5737 * is not a part of the outer IP header 5738 */ 5739 ip.v4->check = csum_fold(csum_partial(trans_start, 5740 csum_start - trans_start, 5741 0)); 5742 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 5743 5744 ip.v4->tot_len = 0; 5745 first->tx_flags |= IGB_TX_FLAGS_TSO | 5746 IGB_TX_FLAGS_CSUM | 5747 IGB_TX_FLAGS_IPV4; 5748 } else { 5749 ip.v6->payload_len = 0; 5750 first->tx_flags |= IGB_TX_FLAGS_TSO | 5751 IGB_TX_FLAGS_CSUM; 5752 } 5753 5754 /* determine offset of inner transport header */ 5755 l4_offset = l4.hdr - skb->data; 5756 5757 /* compute length of segmentation header */ 5758 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 5759 5760 /* remove payload length from inner checksum */ 5761 paylen = skb->len - l4_offset; 5762 csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); 5763 5764 /* update gso size and bytecount with header size */ 5765 first->gso_segs = skb_shinfo(skb)->gso_segs; 5766 first->bytecount += (first->gso_segs - 1) * *hdr_len; 5767 5768 /* MSS L4LEN IDX */ 5769 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 5770 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 5771 5772 /* VLAN MACLEN IPLEN */ 5773 vlan_macip_lens = l4.hdr - ip.hdr; 5774 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 5775 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5776 5777 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 5778 type_tucmd, mss_l4len_idx); 5779 5780 return 1; 5781 } 5782 5783 static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb) 5784 { 5785 unsigned int offset = 0; 5786 5787 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 5788 5789 return offset == skb_checksum_start_offset(skb); 5790 } 5791 5792 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 5793 { 5794 struct sk_buff *skb = first->skb; 5795 u32 vlan_macip_lens = 0; 5796 u32 type_tucmd = 0; 5797 5798 if (skb->ip_summed != CHECKSUM_PARTIAL) { 5799 csum_failed: 5800 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 5801 !tx_ring->launchtime_enable) 5802 return; 5803 goto no_csum; 5804 } 5805 5806 switch (skb->csum_offset) { 5807 case offsetof(struct tcphdr, check): 5808 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 5809 /* fall through */ 5810 case offsetof(struct udphdr, check): 5811 break; 5812 case offsetof(struct sctphdr, checksum): 5813 /* validate that this is actually an SCTP request */ 5814 if (((first->protocol == htons(ETH_P_IP)) && 5815 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 5816 ((first->protocol == htons(ETH_P_IPV6)) && 5817 igb_ipv6_csum_is_sctp(skb))) { 5818 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 5819 break; 5820 } 5821 /* fall through */ 5822 default: 5823 skb_checksum_help(skb); 5824 goto csum_failed; 5825 } 5826 5827 /* update TX checksum flag */ 5828 first->tx_flags |= IGB_TX_FLAGS_CSUM; 5829 vlan_macip_lens = skb_checksum_start_offset(skb) - 5830 skb_network_offset(skb); 5831 no_csum: 5832 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 5833 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5834 5835 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 5836 } 5837 5838 #define IGB_SET_FLAG(_input, _flag, _result) \ 5839 ((_flag <= _result) ? \ 5840 ((u32)(_input & _flag) * (_result / _flag)) : \ 5841 ((u32)(_input & _flag) / (_flag / _result))) 5842 5843 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 5844 { 5845 /* set type for advanced descriptor with frame checksum insertion */ 5846 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 5847 E1000_ADVTXD_DCMD_DEXT | 5848 E1000_ADVTXD_DCMD_IFCS; 5849 5850 /* set HW vlan bit if vlan is present */ 5851 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 5852 (E1000_ADVTXD_DCMD_VLE)); 5853 5854 /* set segmentation bits for TSO */ 5855 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 5856 (E1000_ADVTXD_DCMD_TSE)); 5857 5858 /* set timestamp bit if present */ 5859 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 5860 (E1000_ADVTXD_MAC_TSTAMP)); 5861 5862 /* insert frame checksum */ 5863 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 5864 5865 return cmd_type; 5866 } 5867 5868 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 5869 union e1000_adv_tx_desc *tx_desc, 5870 u32 tx_flags, unsigned int paylen) 5871 { 5872 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 5873 5874 /* 82575 requires a unique index per ring */ 5875 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5876 olinfo_status |= tx_ring->reg_idx << 4; 5877 5878 /* insert L4 checksum */ 5879 olinfo_status |= IGB_SET_FLAG(tx_flags, 5880 IGB_TX_FLAGS_CSUM, 5881 (E1000_TXD_POPTS_TXSM << 8)); 5882 5883 /* insert IPv4 checksum */ 5884 olinfo_status |= IGB_SET_FLAG(tx_flags, 5885 IGB_TX_FLAGS_IPV4, 5886 (E1000_TXD_POPTS_IXSM << 8)); 5887 5888 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 5889 } 5890 5891 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5892 { 5893 struct net_device *netdev = tx_ring->netdev; 5894 5895 netif_stop_subqueue(netdev, tx_ring->queue_index); 5896 5897 /* Herbert's original patch had: 5898 * smp_mb__after_netif_stop_queue(); 5899 * but since that doesn't exist yet, just open code it. 5900 */ 5901 smp_mb(); 5902 5903 /* We need to check again in a case another CPU has just 5904 * made room available. 5905 */ 5906 if (igb_desc_unused(tx_ring) < size) 5907 return -EBUSY; 5908 5909 /* A reprieve! */ 5910 netif_wake_subqueue(netdev, tx_ring->queue_index); 5911 5912 u64_stats_update_begin(&tx_ring->tx_syncp2); 5913 tx_ring->tx_stats.restart_queue2++; 5914 u64_stats_update_end(&tx_ring->tx_syncp2); 5915 5916 return 0; 5917 } 5918 5919 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5920 { 5921 if (igb_desc_unused(tx_ring) >= size) 5922 return 0; 5923 return __igb_maybe_stop_tx(tx_ring, size); 5924 } 5925 5926 static int igb_tx_map(struct igb_ring *tx_ring, 5927 struct igb_tx_buffer *first, 5928 const u8 hdr_len) 5929 { 5930 struct sk_buff *skb = first->skb; 5931 struct igb_tx_buffer *tx_buffer; 5932 union e1000_adv_tx_desc *tx_desc; 5933 struct skb_frag_struct *frag; 5934 dma_addr_t dma; 5935 unsigned int data_len, size; 5936 u32 tx_flags = first->tx_flags; 5937 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 5938 u16 i = tx_ring->next_to_use; 5939 5940 tx_desc = IGB_TX_DESC(tx_ring, i); 5941 5942 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 5943 5944 size = skb_headlen(skb); 5945 data_len = skb->data_len; 5946 5947 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 5948 5949 tx_buffer = first; 5950 5951 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 5952 if (dma_mapping_error(tx_ring->dev, dma)) 5953 goto dma_error; 5954 5955 /* record length, and DMA address */ 5956 dma_unmap_len_set(tx_buffer, len, size); 5957 dma_unmap_addr_set(tx_buffer, dma, dma); 5958 5959 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5960 5961 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 5962 tx_desc->read.cmd_type_len = 5963 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 5964 5965 i++; 5966 tx_desc++; 5967 if (i == tx_ring->count) { 5968 tx_desc = IGB_TX_DESC(tx_ring, 0); 5969 i = 0; 5970 } 5971 tx_desc->read.olinfo_status = 0; 5972 5973 dma += IGB_MAX_DATA_PER_TXD; 5974 size -= IGB_MAX_DATA_PER_TXD; 5975 5976 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5977 } 5978 5979 if (likely(!data_len)) 5980 break; 5981 5982 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 5983 5984 i++; 5985 tx_desc++; 5986 if (i == tx_ring->count) { 5987 tx_desc = IGB_TX_DESC(tx_ring, 0); 5988 i = 0; 5989 } 5990 tx_desc->read.olinfo_status = 0; 5991 5992 size = skb_frag_size(frag); 5993 data_len -= size; 5994 5995 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 5996 size, DMA_TO_DEVICE); 5997 5998 tx_buffer = &tx_ring->tx_buffer_info[i]; 5999 } 6000 6001 /* write last descriptor with RS and EOP bits */ 6002 cmd_type |= size | IGB_TXD_DCMD; 6003 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6004 6005 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6006 6007 /* set the timestamp */ 6008 first->time_stamp = jiffies; 6009 6010 skb_tx_timestamp(skb); 6011 6012 /* Force memory writes to complete before letting h/w know there 6013 * are new descriptors to fetch. (Only applicable for weak-ordered 6014 * memory model archs, such as IA-64). 6015 * 6016 * We also need this memory barrier to make certain all of the 6017 * status bits have been updated before next_to_watch is written. 6018 */ 6019 dma_wmb(); 6020 6021 /* set next_to_watch value indicating a packet is present */ 6022 first->next_to_watch = tx_desc; 6023 6024 i++; 6025 if (i == tx_ring->count) 6026 i = 0; 6027 6028 tx_ring->next_to_use = i; 6029 6030 /* Make sure there is space in the ring for the next send. */ 6031 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6032 6033 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6034 writel(i, tx_ring->tail); 6035 } 6036 return 0; 6037 6038 dma_error: 6039 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6040 tx_buffer = &tx_ring->tx_buffer_info[i]; 6041 6042 /* clear dma mappings for failed tx_buffer_info map */ 6043 while (tx_buffer != first) { 6044 if (dma_unmap_len(tx_buffer, len)) 6045 dma_unmap_page(tx_ring->dev, 6046 dma_unmap_addr(tx_buffer, dma), 6047 dma_unmap_len(tx_buffer, len), 6048 DMA_TO_DEVICE); 6049 dma_unmap_len_set(tx_buffer, len, 0); 6050 6051 if (i-- == 0) 6052 i += tx_ring->count; 6053 tx_buffer = &tx_ring->tx_buffer_info[i]; 6054 } 6055 6056 if (dma_unmap_len(tx_buffer, len)) 6057 dma_unmap_single(tx_ring->dev, 6058 dma_unmap_addr(tx_buffer, dma), 6059 dma_unmap_len(tx_buffer, len), 6060 DMA_TO_DEVICE); 6061 dma_unmap_len_set(tx_buffer, len, 0); 6062 6063 dev_kfree_skb_any(tx_buffer->skb); 6064 tx_buffer->skb = NULL; 6065 6066 tx_ring->next_to_use = i; 6067 6068 return -1; 6069 } 6070 6071 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6072 struct igb_ring *tx_ring) 6073 { 6074 struct igb_tx_buffer *first; 6075 int tso; 6076 u32 tx_flags = 0; 6077 unsigned short f; 6078 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6079 __be16 protocol = vlan_get_protocol(skb); 6080 u8 hdr_len = 0; 6081 6082 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6083 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6084 * + 2 desc gap to keep tail from touching head, 6085 * + 1 desc for context descriptor, 6086 * otherwise try next time 6087 */ 6088 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6089 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 6090 6091 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6092 /* this is a hard error */ 6093 return NETDEV_TX_BUSY; 6094 } 6095 6096 /* record the location of the first descriptor for this packet */ 6097 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6098 first->skb = skb; 6099 first->bytecount = skb->len; 6100 first->gso_segs = 1; 6101 6102 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6103 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6104 6105 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6106 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6107 &adapter->state)) { 6108 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6109 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6110 6111 adapter->ptp_tx_skb = skb_get(skb); 6112 adapter->ptp_tx_start = jiffies; 6113 if (adapter->hw.mac.type == e1000_82576) 6114 schedule_work(&adapter->ptp_tx_work); 6115 } else { 6116 adapter->tx_hwtstamp_skipped++; 6117 } 6118 } 6119 6120 if (skb_vlan_tag_present(skb)) { 6121 tx_flags |= IGB_TX_FLAGS_VLAN; 6122 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6123 } 6124 6125 /* record initial flags and protocol */ 6126 first->tx_flags = tx_flags; 6127 first->protocol = protocol; 6128 6129 tso = igb_tso(tx_ring, first, &hdr_len); 6130 if (tso < 0) 6131 goto out_drop; 6132 else if (!tso) 6133 igb_tx_csum(tx_ring, first); 6134 6135 if (igb_tx_map(tx_ring, first, hdr_len)) 6136 goto cleanup_tx_tstamp; 6137 6138 return NETDEV_TX_OK; 6139 6140 out_drop: 6141 dev_kfree_skb_any(first->skb); 6142 first->skb = NULL; 6143 cleanup_tx_tstamp: 6144 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6145 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6146 6147 dev_kfree_skb_any(adapter->ptp_tx_skb); 6148 adapter->ptp_tx_skb = NULL; 6149 if (adapter->hw.mac.type == e1000_82576) 6150 cancel_work_sync(&adapter->ptp_tx_work); 6151 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6152 } 6153 6154 return NETDEV_TX_OK; 6155 } 6156 6157 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6158 struct sk_buff *skb) 6159 { 6160 unsigned int r_idx = skb->queue_mapping; 6161 6162 if (r_idx >= adapter->num_tx_queues) 6163 r_idx = r_idx % adapter->num_tx_queues; 6164 6165 return adapter->tx_ring[r_idx]; 6166 } 6167 6168 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6169 struct net_device *netdev) 6170 { 6171 struct igb_adapter *adapter = netdev_priv(netdev); 6172 6173 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6174 * in order to meet this minimum size requirement. 6175 */ 6176 if (skb_put_padto(skb, 17)) 6177 return NETDEV_TX_OK; 6178 6179 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6180 } 6181 6182 /** 6183 * igb_tx_timeout - Respond to a Tx Hang 6184 * @netdev: network interface device structure 6185 **/ 6186 static void igb_tx_timeout(struct net_device *netdev) 6187 { 6188 struct igb_adapter *adapter = netdev_priv(netdev); 6189 struct e1000_hw *hw = &adapter->hw; 6190 6191 /* Do the reset outside of interrupt context */ 6192 adapter->tx_timeout_count++; 6193 6194 if (hw->mac.type >= e1000_82580) 6195 hw->dev_spec._82575.global_device_reset = true; 6196 6197 schedule_work(&adapter->reset_task); 6198 wr32(E1000_EICS, 6199 (adapter->eims_enable_mask & ~adapter->eims_other)); 6200 } 6201 6202 static void igb_reset_task(struct work_struct *work) 6203 { 6204 struct igb_adapter *adapter; 6205 adapter = container_of(work, struct igb_adapter, reset_task); 6206 6207 igb_dump(adapter); 6208 netdev_err(adapter->netdev, "Reset adapter\n"); 6209 igb_reinit_locked(adapter); 6210 } 6211 6212 /** 6213 * igb_get_stats64 - Get System Network Statistics 6214 * @netdev: network interface device structure 6215 * @stats: rtnl_link_stats64 pointer 6216 **/ 6217 static void igb_get_stats64(struct net_device *netdev, 6218 struct rtnl_link_stats64 *stats) 6219 { 6220 struct igb_adapter *adapter = netdev_priv(netdev); 6221 6222 spin_lock(&adapter->stats64_lock); 6223 igb_update_stats(adapter); 6224 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6225 spin_unlock(&adapter->stats64_lock); 6226 } 6227 6228 /** 6229 * igb_change_mtu - Change the Maximum Transfer Unit 6230 * @netdev: network interface device structure 6231 * @new_mtu: new value for maximum frame size 6232 * 6233 * Returns 0 on success, negative on failure 6234 **/ 6235 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6236 { 6237 struct igb_adapter *adapter = netdev_priv(netdev); 6238 struct pci_dev *pdev = adapter->pdev; 6239 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 6240 6241 /* adjust max frame to be at least the size of a standard frame */ 6242 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6243 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6244 6245 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6246 usleep_range(1000, 2000); 6247 6248 /* igb_down has a dependency on max_frame_size */ 6249 adapter->max_frame_size = max_frame; 6250 6251 if (netif_running(netdev)) 6252 igb_down(adapter); 6253 6254 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 6255 netdev->mtu, new_mtu); 6256 netdev->mtu = new_mtu; 6257 6258 if (netif_running(netdev)) 6259 igb_up(adapter); 6260 else 6261 igb_reset(adapter); 6262 6263 clear_bit(__IGB_RESETTING, &adapter->state); 6264 6265 return 0; 6266 } 6267 6268 /** 6269 * igb_update_stats - Update the board statistics counters 6270 * @adapter: board private structure 6271 **/ 6272 void igb_update_stats(struct igb_adapter *adapter) 6273 { 6274 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6275 struct e1000_hw *hw = &adapter->hw; 6276 struct pci_dev *pdev = adapter->pdev; 6277 u32 reg, mpc; 6278 int i; 6279 u64 bytes, packets; 6280 unsigned int start; 6281 u64 _bytes, _packets; 6282 6283 /* Prevent stats update while adapter is being reset, or if the pci 6284 * connection is down. 6285 */ 6286 if (adapter->link_speed == 0) 6287 return; 6288 if (pci_channel_offline(pdev)) 6289 return; 6290 6291 bytes = 0; 6292 packets = 0; 6293 6294 rcu_read_lock(); 6295 for (i = 0; i < adapter->num_rx_queues; i++) { 6296 struct igb_ring *ring = adapter->rx_ring[i]; 6297 u32 rqdpc = rd32(E1000_RQDPC(i)); 6298 if (hw->mac.type >= e1000_i210) 6299 wr32(E1000_RQDPC(i), 0); 6300 6301 if (rqdpc) { 6302 ring->rx_stats.drops += rqdpc; 6303 net_stats->rx_fifo_errors += rqdpc; 6304 } 6305 6306 do { 6307 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 6308 _bytes = ring->rx_stats.bytes; 6309 _packets = ring->rx_stats.packets; 6310 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 6311 bytes += _bytes; 6312 packets += _packets; 6313 } 6314 6315 net_stats->rx_bytes = bytes; 6316 net_stats->rx_packets = packets; 6317 6318 bytes = 0; 6319 packets = 0; 6320 for (i = 0; i < adapter->num_tx_queues; i++) { 6321 struct igb_ring *ring = adapter->tx_ring[i]; 6322 do { 6323 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 6324 _bytes = ring->tx_stats.bytes; 6325 _packets = ring->tx_stats.packets; 6326 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 6327 bytes += _bytes; 6328 packets += _packets; 6329 } 6330 net_stats->tx_bytes = bytes; 6331 net_stats->tx_packets = packets; 6332 rcu_read_unlock(); 6333 6334 /* read stats registers */ 6335 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6336 adapter->stats.gprc += rd32(E1000_GPRC); 6337 adapter->stats.gorc += rd32(E1000_GORCL); 6338 rd32(E1000_GORCH); /* clear GORCL */ 6339 adapter->stats.bprc += rd32(E1000_BPRC); 6340 adapter->stats.mprc += rd32(E1000_MPRC); 6341 adapter->stats.roc += rd32(E1000_ROC); 6342 6343 adapter->stats.prc64 += rd32(E1000_PRC64); 6344 adapter->stats.prc127 += rd32(E1000_PRC127); 6345 adapter->stats.prc255 += rd32(E1000_PRC255); 6346 adapter->stats.prc511 += rd32(E1000_PRC511); 6347 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6348 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6349 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6350 adapter->stats.sec += rd32(E1000_SEC); 6351 6352 mpc = rd32(E1000_MPC); 6353 adapter->stats.mpc += mpc; 6354 net_stats->rx_fifo_errors += mpc; 6355 adapter->stats.scc += rd32(E1000_SCC); 6356 adapter->stats.ecol += rd32(E1000_ECOL); 6357 adapter->stats.mcc += rd32(E1000_MCC); 6358 adapter->stats.latecol += rd32(E1000_LATECOL); 6359 adapter->stats.dc += rd32(E1000_DC); 6360 adapter->stats.rlec += rd32(E1000_RLEC); 6361 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6362 adapter->stats.xontxc += rd32(E1000_XONTXC); 6363 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6364 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6365 adapter->stats.fcruc += rd32(E1000_FCRUC); 6366 adapter->stats.gptc += rd32(E1000_GPTC); 6367 adapter->stats.gotc += rd32(E1000_GOTCL); 6368 rd32(E1000_GOTCH); /* clear GOTCL */ 6369 adapter->stats.rnbc += rd32(E1000_RNBC); 6370 adapter->stats.ruc += rd32(E1000_RUC); 6371 adapter->stats.rfc += rd32(E1000_RFC); 6372 adapter->stats.rjc += rd32(E1000_RJC); 6373 adapter->stats.tor += rd32(E1000_TORH); 6374 adapter->stats.tot += rd32(E1000_TOTH); 6375 adapter->stats.tpr += rd32(E1000_TPR); 6376 6377 adapter->stats.ptc64 += rd32(E1000_PTC64); 6378 adapter->stats.ptc127 += rd32(E1000_PTC127); 6379 adapter->stats.ptc255 += rd32(E1000_PTC255); 6380 adapter->stats.ptc511 += rd32(E1000_PTC511); 6381 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6382 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6383 6384 adapter->stats.mptc += rd32(E1000_MPTC); 6385 adapter->stats.bptc += rd32(E1000_BPTC); 6386 6387 adapter->stats.tpt += rd32(E1000_TPT); 6388 adapter->stats.colc += rd32(E1000_COLC); 6389 6390 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6391 /* read internal phy specific stats */ 6392 reg = rd32(E1000_CTRL_EXT); 6393 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6394 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6395 6396 /* this stat has invalid values on i210/i211 */ 6397 if ((hw->mac.type != e1000_i210) && 6398 (hw->mac.type != e1000_i211)) 6399 adapter->stats.tncrs += rd32(E1000_TNCRS); 6400 } 6401 6402 adapter->stats.tsctc += rd32(E1000_TSCTC); 6403 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6404 6405 adapter->stats.iac += rd32(E1000_IAC); 6406 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6407 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6408 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6409 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6410 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6411 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6412 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6413 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6414 6415 /* Fill out the OS statistics structure */ 6416 net_stats->multicast = adapter->stats.mprc; 6417 net_stats->collisions = adapter->stats.colc; 6418 6419 /* Rx Errors */ 6420 6421 /* RLEC on some newer hardware can be incorrect so build 6422 * our own version based on RUC and ROC 6423 */ 6424 net_stats->rx_errors = adapter->stats.rxerrc + 6425 adapter->stats.crcerrs + adapter->stats.algnerrc + 6426 adapter->stats.ruc + adapter->stats.roc + 6427 adapter->stats.cexterr; 6428 net_stats->rx_length_errors = adapter->stats.ruc + 6429 adapter->stats.roc; 6430 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6431 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6432 net_stats->rx_missed_errors = adapter->stats.mpc; 6433 6434 /* Tx Errors */ 6435 net_stats->tx_errors = adapter->stats.ecol + 6436 adapter->stats.latecol; 6437 net_stats->tx_aborted_errors = adapter->stats.ecol; 6438 net_stats->tx_window_errors = adapter->stats.latecol; 6439 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6440 6441 /* Tx Dropped needs to be maintained elsewhere */ 6442 6443 /* Management Stats */ 6444 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6445 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6446 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6447 6448 /* OS2BMC Stats */ 6449 reg = rd32(E1000_MANC); 6450 if (reg & E1000_MANC_EN_BMC2OS) { 6451 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6452 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6453 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6454 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6455 } 6456 } 6457 6458 static void igb_tsync_interrupt(struct igb_adapter *adapter) 6459 { 6460 struct e1000_hw *hw = &adapter->hw; 6461 struct ptp_clock_event event; 6462 struct timespec64 ts; 6463 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR); 6464 6465 if (tsicr & TSINTR_SYS_WRAP) { 6466 event.type = PTP_CLOCK_PPS; 6467 if (adapter->ptp_caps.pps) 6468 ptp_clock_event(adapter->ptp_clock, &event); 6469 ack |= TSINTR_SYS_WRAP; 6470 } 6471 6472 if (tsicr & E1000_TSICR_TXTS) { 6473 /* retrieve hardware timestamp */ 6474 schedule_work(&adapter->ptp_tx_work); 6475 ack |= E1000_TSICR_TXTS; 6476 } 6477 6478 if (tsicr & TSINTR_TT0) { 6479 spin_lock(&adapter->tmreg_lock); 6480 ts = timespec64_add(adapter->perout[0].start, 6481 adapter->perout[0].period); 6482 /* u32 conversion of tv_sec is safe until y2106 */ 6483 wr32(E1000_TRGTTIML0, ts.tv_nsec); 6484 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec); 6485 tsauxc = rd32(E1000_TSAUXC); 6486 tsauxc |= TSAUXC_EN_TT0; 6487 wr32(E1000_TSAUXC, tsauxc); 6488 adapter->perout[0].start = ts; 6489 spin_unlock(&adapter->tmreg_lock); 6490 ack |= TSINTR_TT0; 6491 } 6492 6493 if (tsicr & TSINTR_TT1) { 6494 spin_lock(&adapter->tmreg_lock); 6495 ts = timespec64_add(adapter->perout[1].start, 6496 adapter->perout[1].period); 6497 wr32(E1000_TRGTTIML1, ts.tv_nsec); 6498 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec); 6499 tsauxc = rd32(E1000_TSAUXC); 6500 tsauxc |= TSAUXC_EN_TT1; 6501 wr32(E1000_TSAUXC, tsauxc); 6502 adapter->perout[1].start = ts; 6503 spin_unlock(&adapter->tmreg_lock); 6504 ack |= TSINTR_TT1; 6505 } 6506 6507 if (tsicr & TSINTR_AUTT0) { 6508 nsec = rd32(E1000_AUXSTMPL0); 6509 sec = rd32(E1000_AUXSTMPH0); 6510 event.type = PTP_CLOCK_EXTTS; 6511 event.index = 0; 6512 event.timestamp = sec * 1000000000ULL + nsec; 6513 ptp_clock_event(adapter->ptp_clock, &event); 6514 ack |= TSINTR_AUTT0; 6515 } 6516 6517 if (tsicr & TSINTR_AUTT1) { 6518 nsec = rd32(E1000_AUXSTMPL1); 6519 sec = rd32(E1000_AUXSTMPH1); 6520 event.type = PTP_CLOCK_EXTTS; 6521 event.index = 1; 6522 event.timestamp = sec * 1000000000ULL + nsec; 6523 ptp_clock_event(adapter->ptp_clock, &event); 6524 ack |= TSINTR_AUTT1; 6525 } 6526 6527 /* acknowledge the interrupts */ 6528 wr32(E1000_TSICR, ack); 6529 } 6530 6531 static irqreturn_t igb_msix_other(int irq, void *data) 6532 { 6533 struct igb_adapter *adapter = data; 6534 struct e1000_hw *hw = &adapter->hw; 6535 u32 icr = rd32(E1000_ICR); 6536 /* reading ICR causes bit 31 of EICR to be cleared */ 6537 6538 if (icr & E1000_ICR_DRSTA) 6539 schedule_work(&adapter->reset_task); 6540 6541 if (icr & E1000_ICR_DOUTSYNC) { 6542 /* HW is reporting DMA is out of sync */ 6543 adapter->stats.doosync++; 6544 /* The DMA Out of Sync is also indication of a spoof event 6545 * in IOV mode. Check the Wrong VM Behavior register to 6546 * see if it is really a spoof event. 6547 */ 6548 igb_check_wvbr(adapter); 6549 } 6550 6551 /* Check for a mailbox event */ 6552 if (icr & E1000_ICR_VMMB) 6553 igb_msg_task(adapter); 6554 6555 if (icr & E1000_ICR_LSC) { 6556 hw->mac.get_link_status = 1; 6557 /* guard against interrupt when we're going down */ 6558 if (!test_bit(__IGB_DOWN, &adapter->state)) 6559 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6560 } 6561 6562 if (icr & E1000_ICR_TS) 6563 igb_tsync_interrupt(adapter); 6564 6565 wr32(E1000_EIMS, adapter->eims_other); 6566 6567 return IRQ_HANDLED; 6568 } 6569 6570 static void igb_write_itr(struct igb_q_vector *q_vector) 6571 { 6572 struct igb_adapter *adapter = q_vector->adapter; 6573 u32 itr_val = q_vector->itr_val & 0x7FFC; 6574 6575 if (!q_vector->set_itr) 6576 return; 6577 6578 if (!itr_val) 6579 itr_val = 0x4; 6580 6581 if (adapter->hw.mac.type == e1000_82575) 6582 itr_val |= itr_val << 16; 6583 else 6584 itr_val |= E1000_EITR_CNT_IGNR; 6585 6586 writel(itr_val, q_vector->itr_register); 6587 q_vector->set_itr = 0; 6588 } 6589 6590 static irqreturn_t igb_msix_ring(int irq, void *data) 6591 { 6592 struct igb_q_vector *q_vector = data; 6593 6594 /* Write the ITR value calculated from the previous interrupt. */ 6595 igb_write_itr(q_vector); 6596 6597 napi_schedule(&q_vector->napi); 6598 6599 return IRQ_HANDLED; 6600 } 6601 6602 #ifdef CONFIG_IGB_DCA 6603 static void igb_update_tx_dca(struct igb_adapter *adapter, 6604 struct igb_ring *tx_ring, 6605 int cpu) 6606 { 6607 struct e1000_hw *hw = &adapter->hw; 6608 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 6609 6610 if (hw->mac.type != e1000_82575) 6611 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 6612 6613 /* We can enable relaxed ordering for reads, but not writes when 6614 * DCA is enabled. This is due to a known issue in some chipsets 6615 * which will cause the DCA tag to be cleared. 6616 */ 6617 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 6618 E1000_DCA_TXCTRL_DATA_RRO_EN | 6619 E1000_DCA_TXCTRL_DESC_DCA_EN; 6620 6621 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 6622 } 6623 6624 static void igb_update_rx_dca(struct igb_adapter *adapter, 6625 struct igb_ring *rx_ring, 6626 int cpu) 6627 { 6628 struct e1000_hw *hw = &adapter->hw; 6629 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 6630 6631 if (hw->mac.type != e1000_82575) 6632 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 6633 6634 /* We can enable relaxed ordering for reads, but not writes when 6635 * DCA is enabled. This is due to a known issue in some chipsets 6636 * which will cause the DCA tag to be cleared. 6637 */ 6638 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 6639 E1000_DCA_RXCTRL_DESC_DCA_EN; 6640 6641 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 6642 } 6643 6644 static void igb_update_dca(struct igb_q_vector *q_vector) 6645 { 6646 struct igb_adapter *adapter = q_vector->adapter; 6647 int cpu = get_cpu(); 6648 6649 if (q_vector->cpu == cpu) 6650 goto out_no_update; 6651 6652 if (q_vector->tx.ring) 6653 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 6654 6655 if (q_vector->rx.ring) 6656 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 6657 6658 q_vector->cpu = cpu; 6659 out_no_update: 6660 put_cpu(); 6661 } 6662 6663 static void igb_setup_dca(struct igb_adapter *adapter) 6664 { 6665 struct e1000_hw *hw = &adapter->hw; 6666 int i; 6667 6668 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 6669 return; 6670 6671 /* Always use CB2 mode, difference is masked in the CB driver. */ 6672 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 6673 6674 for (i = 0; i < adapter->num_q_vectors; i++) { 6675 adapter->q_vector[i]->cpu = -1; 6676 igb_update_dca(adapter->q_vector[i]); 6677 } 6678 } 6679 6680 static int __igb_notify_dca(struct device *dev, void *data) 6681 { 6682 struct net_device *netdev = dev_get_drvdata(dev); 6683 struct igb_adapter *adapter = netdev_priv(netdev); 6684 struct pci_dev *pdev = adapter->pdev; 6685 struct e1000_hw *hw = &adapter->hw; 6686 unsigned long event = *(unsigned long *)data; 6687 6688 switch (event) { 6689 case DCA_PROVIDER_ADD: 6690 /* if already enabled, don't do it again */ 6691 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 6692 break; 6693 if (dca_add_requester(dev) == 0) { 6694 adapter->flags |= IGB_FLAG_DCA_ENABLED; 6695 dev_info(&pdev->dev, "DCA enabled\n"); 6696 igb_setup_dca(adapter); 6697 break; 6698 } 6699 /* Fall Through - since DCA is disabled. */ 6700 case DCA_PROVIDER_REMOVE: 6701 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 6702 /* without this a class_device is left 6703 * hanging around in the sysfs model 6704 */ 6705 dca_remove_requester(dev); 6706 dev_info(&pdev->dev, "DCA disabled\n"); 6707 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 6708 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 6709 } 6710 break; 6711 } 6712 6713 return 0; 6714 } 6715 6716 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 6717 void *p) 6718 { 6719 int ret_val; 6720 6721 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 6722 __igb_notify_dca); 6723 6724 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 6725 } 6726 #endif /* CONFIG_IGB_DCA */ 6727 6728 #ifdef CONFIG_PCI_IOV 6729 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 6730 { 6731 unsigned char mac_addr[ETH_ALEN]; 6732 6733 eth_zero_addr(mac_addr); 6734 igb_set_vf_mac(adapter, vf, mac_addr); 6735 6736 /* By default spoof check is enabled for all VFs */ 6737 adapter->vf_data[vf].spoofchk_enabled = true; 6738 6739 /* By default VFs are not trusted */ 6740 adapter->vf_data[vf].trusted = false; 6741 6742 return 0; 6743 } 6744 6745 #endif 6746 static void igb_ping_all_vfs(struct igb_adapter *adapter) 6747 { 6748 struct e1000_hw *hw = &adapter->hw; 6749 u32 ping; 6750 int i; 6751 6752 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 6753 ping = E1000_PF_CONTROL_MSG; 6754 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 6755 ping |= E1000_VT_MSGTYPE_CTS; 6756 igb_write_mbx(hw, &ping, 1, i); 6757 } 6758 } 6759 6760 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 6761 { 6762 struct e1000_hw *hw = &adapter->hw; 6763 u32 vmolr = rd32(E1000_VMOLR(vf)); 6764 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6765 6766 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 6767 IGB_VF_FLAG_MULTI_PROMISC); 6768 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 6769 6770 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 6771 vmolr |= E1000_VMOLR_MPME; 6772 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 6773 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 6774 } else { 6775 /* if we have hashes and we are clearing a multicast promisc 6776 * flag we need to write the hashes to the MTA as this step 6777 * was previously skipped 6778 */ 6779 if (vf_data->num_vf_mc_hashes > 30) { 6780 vmolr |= E1000_VMOLR_MPME; 6781 } else if (vf_data->num_vf_mc_hashes) { 6782 int j; 6783 6784 vmolr |= E1000_VMOLR_ROMPE; 6785 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 6786 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 6787 } 6788 } 6789 6790 wr32(E1000_VMOLR(vf), vmolr); 6791 6792 /* there are flags left unprocessed, likely not supported */ 6793 if (*msgbuf & E1000_VT_MSGINFO_MASK) 6794 return -EINVAL; 6795 6796 return 0; 6797 } 6798 6799 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 6800 u32 *msgbuf, u32 vf) 6801 { 6802 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 6803 u16 *hash_list = (u16 *)&msgbuf[1]; 6804 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6805 int i; 6806 6807 /* salt away the number of multicast addresses assigned 6808 * to this VF for later use to restore when the PF multi cast 6809 * list changes 6810 */ 6811 vf_data->num_vf_mc_hashes = n; 6812 6813 /* only up to 30 hash values supported */ 6814 if (n > 30) 6815 n = 30; 6816 6817 /* store the hashes for later use */ 6818 for (i = 0; i < n; i++) 6819 vf_data->vf_mc_hashes[i] = hash_list[i]; 6820 6821 /* Flush and reset the mta with the new values */ 6822 igb_set_rx_mode(adapter->netdev); 6823 6824 return 0; 6825 } 6826 6827 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 6828 { 6829 struct e1000_hw *hw = &adapter->hw; 6830 struct vf_data_storage *vf_data; 6831 int i, j; 6832 6833 for (i = 0; i < adapter->vfs_allocated_count; i++) { 6834 u32 vmolr = rd32(E1000_VMOLR(i)); 6835 6836 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 6837 6838 vf_data = &adapter->vf_data[i]; 6839 6840 if ((vf_data->num_vf_mc_hashes > 30) || 6841 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 6842 vmolr |= E1000_VMOLR_MPME; 6843 } else if (vf_data->num_vf_mc_hashes) { 6844 vmolr |= E1000_VMOLR_ROMPE; 6845 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 6846 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 6847 } 6848 wr32(E1000_VMOLR(i), vmolr); 6849 } 6850 } 6851 6852 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 6853 { 6854 struct e1000_hw *hw = &adapter->hw; 6855 u32 pool_mask, vlvf_mask, i; 6856 6857 /* create mask for VF and other pools */ 6858 pool_mask = E1000_VLVF_POOLSEL_MASK; 6859 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 6860 6861 /* drop PF from pool bits */ 6862 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 6863 adapter->vfs_allocated_count); 6864 6865 /* Find the vlan filter for this id */ 6866 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 6867 u32 vlvf = rd32(E1000_VLVF(i)); 6868 u32 vfta_mask, vid, vfta; 6869 6870 /* remove the vf from the pool */ 6871 if (!(vlvf & vlvf_mask)) 6872 continue; 6873 6874 /* clear out bit from VLVF */ 6875 vlvf ^= vlvf_mask; 6876 6877 /* if other pools are present, just remove ourselves */ 6878 if (vlvf & pool_mask) 6879 goto update_vlvfb; 6880 6881 /* if PF is present, leave VFTA */ 6882 if (vlvf & E1000_VLVF_POOLSEL_MASK) 6883 goto update_vlvf; 6884 6885 vid = vlvf & E1000_VLVF_VLANID_MASK; 6886 vfta_mask = BIT(vid % 32); 6887 6888 /* clear bit from VFTA */ 6889 vfta = adapter->shadow_vfta[vid / 32]; 6890 if (vfta & vfta_mask) 6891 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 6892 update_vlvf: 6893 /* clear pool selection enable */ 6894 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6895 vlvf &= E1000_VLVF_POOLSEL_MASK; 6896 else 6897 vlvf = 0; 6898 update_vlvfb: 6899 /* clear pool bits */ 6900 wr32(E1000_VLVF(i), vlvf); 6901 } 6902 } 6903 6904 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 6905 { 6906 u32 vlvf; 6907 int idx; 6908 6909 /* short cut the special case */ 6910 if (vlan == 0) 6911 return 0; 6912 6913 /* Search for the VLAN id in the VLVF entries */ 6914 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 6915 vlvf = rd32(E1000_VLVF(idx)); 6916 if ((vlvf & VLAN_VID_MASK) == vlan) 6917 break; 6918 } 6919 6920 return idx; 6921 } 6922 6923 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 6924 { 6925 struct e1000_hw *hw = &adapter->hw; 6926 u32 bits, pf_id; 6927 int idx; 6928 6929 idx = igb_find_vlvf_entry(hw, vid); 6930 if (!idx) 6931 return; 6932 6933 /* See if any other pools are set for this VLAN filter 6934 * entry other than the PF. 6935 */ 6936 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 6937 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 6938 bits &= rd32(E1000_VLVF(idx)); 6939 6940 /* Disable the filter so this falls into the default pool. */ 6941 if (!bits) { 6942 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6943 wr32(E1000_VLVF(idx), BIT(pf_id)); 6944 else 6945 wr32(E1000_VLVF(idx), 0); 6946 } 6947 } 6948 6949 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 6950 bool add, u32 vf) 6951 { 6952 int pf_id = adapter->vfs_allocated_count; 6953 struct e1000_hw *hw = &adapter->hw; 6954 int err; 6955 6956 /* If VLAN overlaps with one the PF is currently monitoring make 6957 * sure that we are able to allocate a VLVF entry. This may be 6958 * redundant but it guarantees PF will maintain visibility to 6959 * the VLAN. 6960 */ 6961 if (add && test_bit(vid, adapter->active_vlans)) { 6962 err = igb_vfta_set(hw, vid, pf_id, true, false); 6963 if (err) 6964 return err; 6965 } 6966 6967 err = igb_vfta_set(hw, vid, vf, add, false); 6968 6969 if (add && !err) 6970 return err; 6971 6972 /* If we failed to add the VF VLAN or we are removing the VF VLAN 6973 * we may need to drop the PF pool bit in order to allow us to free 6974 * up the VLVF resources. 6975 */ 6976 if (test_bit(vid, adapter->active_vlans) || 6977 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 6978 igb_update_pf_vlvf(adapter, vid); 6979 6980 return err; 6981 } 6982 6983 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 6984 { 6985 struct e1000_hw *hw = &adapter->hw; 6986 6987 if (vid) 6988 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 6989 else 6990 wr32(E1000_VMVIR(vf), 0); 6991 } 6992 6993 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 6994 u16 vlan, u8 qos) 6995 { 6996 int err; 6997 6998 err = igb_set_vf_vlan(adapter, vlan, true, vf); 6999 if (err) 7000 return err; 7001 7002 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7003 igb_set_vmolr(adapter, vf, !vlan); 7004 7005 /* revoke access to previous VLAN */ 7006 if (vlan != adapter->vf_data[vf].pf_vlan) 7007 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7008 false, vf); 7009 7010 adapter->vf_data[vf].pf_vlan = vlan; 7011 adapter->vf_data[vf].pf_qos = qos; 7012 igb_set_vf_vlan_strip(adapter, vf, true); 7013 dev_info(&adapter->pdev->dev, 7014 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7015 if (test_bit(__IGB_DOWN, &adapter->state)) { 7016 dev_warn(&adapter->pdev->dev, 7017 "The VF VLAN has been set, but the PF device is not up.\n"); 7018 dev_warn(&adapter->pdev->dev, 7019 "Bring the PF device up before attempting to use the VF device.\n"); 7020 } 7021 7022 return err; 7023 } 7024 7025 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7026 { 7027 /* Restore tagless access via VLAN 0 */ 7028 igb_set_vf_vlan(adapter, 0, true, vf); 7029 7030 igb_set_vmvir(adapter, 0, vf); 7031 igb_set_vmolr(adapter, vf, true); 7032 7033 /* Remove any PF assigned VLAN */ 7034 if (adapter->vf_data[vf].pf_vlan) 7035 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7036 false, vf); 7037 7038 adapter->vf_data[vf].pf_vlan = 0; 7039 adapter->vf_data[vf].pf_qos = 0; 7040 igb_set_vf_vlan_strip(adapter, vf, false); 7041 7042 return 0; 7043 } 7044 7045 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7046 u16 vlan, u8 qos, __be16 vlan_proto) 7047 { 7048 struct igb_adapter *adapter = netdev_priv(netdev); 7049 7050 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7051 return -EINVAL; 7052 7053 if (vlan_proto != htons(ETH_P_8021Q)) 7054 return -EPROTONOSUPPORT; 7055 7056 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7057 igb_disable_port_vlan(adapter, vf); 7058 } 7059 7060 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7061 { 7062 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7063 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7064 int ret; 7065 7066 if (adapter->vf_data[vf].pf_vlan) 7067 return -1; 7068 7069 /* VLAN 0 is a special case, don't allow it to be removed */ 7070 if (!vid && !add) 7071 return 0; 7072 7073 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7074 if (!ret) 7075 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7076 return ret; 7077 } 7078 7079 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7080 { 7081 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7082 7083 /* clear flags - except flag that indicates PF has set the MAC */ 7084 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7085 vf_data->last_nack = jiffies; 7086 7087 /* reset vlans for device */ 7088 igb_clear_vf_vfta(adapter, vf); 7089 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7090 igb_set_vmvir(adapter, vf_data->pf_vlan | 7091 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7092 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7093 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7094 7095 /* reset multicast table array for vf */ 7096 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7097 7098 /* Flush and reset the mta with the new values */ 7099 igb_set_rx_mode(adapter->netdev); 7100 } 7101 7102 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7103 { 7104 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7105 7106 /* clear mac address as we were hotplug removed/added */ 7107 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7108 eth_zero_addr(vf_mac); 7109 7110 /* process remaining reset events */ 7111 igb_vf_reset(adapter, vf); 7112 } 7113 7114 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7115 { 7116 struct e1000_hw *hw = &adapter->hw; 7117 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7118 u32 reg, msgbuf[3]; 7119 u8 *addr = (u8 *)(&msgbuf[1]); 7120 7121 /* process all the same items cleared in a function level reset */ 7122 igb_vf_reset(adapter, vf); 7123 7124 /* set vf mac address */ 7125 igb_set_vf_mac(adapter, vf, vf_mac); 7126 7127 /* enable transmit and receive for vf */ 7128 reg = rd32(E1000_VFTE); 7129 wr32(E1000_VFTE, reg | BIT(vf)); 7130 reg = rd32(E1000_VFRE); 7131 wr32(E1000_VFRE, reg | BIT(vf)); 7132 7133 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7134 7135 /* reply to reset with ack and vf mac address */ 7136 if (!is_zero_ether_addr(vf_mac)) { 7137 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7138 memcpy(addr, vf_mac, ETH_ALEN); 7139 } else { 7140 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7141 } 7142 igb_write_mbx(hw, msgbuf, 3, vf); 7143 } 7144 7145 static void igb_flush_mac_table(struct igb_adapter *adapter) 7146 { 7147 struct e1000_hw *hw = &adapter->hw; 7148 int i; 7149 7150 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7151 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7152 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 7153 adapter->mac_table[i].queue = 0; 7154 igb_rar_set_index(adapter, i); 7155 } 7156 } 7157 7158 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7159 { 7160 struct e1000_hw *hw = &adapter->hw; 7161 /* do not count rar entries reserved for VFs MAC addresses */ 7162 int rar_entries = hw->mac.rar_entry_count - 7163 adapter->vfs_allocated_count; 7164 int i, count = 0; 7165 7166 for (i = 0; i < rar_entries; i++) { 7167 /* do not count default entries */ 7168 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7169 continue; 7170 7171 /* do not count "in use" entries for different queues */ 7172 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7173 (adapter->mac_table[i].queue != queue)) 7174 continue; 7175 7176 count++; 7177 } 7178 7179 return count; 7180 } 7181 7182 /* Set default MAC address for the PF in the first RAR entry */ 7183 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7184 { 7185 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7186 7187 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7188 mac_table->queue = adapter->vfs_allocated_count; 7189 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7190 7191 igb_rar_set_index(adapter, 0); 7192 } 7193 7194 /* If the filter to be added and an already existing filter express 7195 * the same address and address type, it should be possible to only 7196 * override the other configurations, for example the queue to steer 7197 * traffic. 7198 */ 7199 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7200 const u8 *addr, const u8 flags) 7201 { 7202 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7203 return true; 7204 7205 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7206 (flags & IGB_MAC_STATE_SRC_ADDR)) 7207 return false; 7208 7209 if (!ether_addr_equal(addr, entry->addr)) 7210 return false; 7211 7212 return true; 7213 } 7214 7215 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7216 * 'flags' is used to indicate what kind of match is made, match is by 7217 * default for the destination address, if matching by source address 7218 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7219 */ 7220 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7221 const u8 *addr, const u8 queue, 7222 const u8 flags) 7223 { 7224 struct e1000_hw *hw = &adapter->hw; 7225 int rar_entries = hw->mac.rar_entry_count - 7226 adapter->vfs_allocated_count; 7227 int i; 7228 7229 if (is_zero_ether_addr(addr)) 7230 return -EINVAL; 7231 7232 /* Search for the first empty entry in the MAC table. 7233 * Do not touch entries at the end of the table reserved for the VF MAC 7234 * addresses. 7235 */ 7236 for (i = 0; i < rar_entries; i++) { 7237 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7238 addr, flags)) 7239 continue; 7240 7241 ether_addr_copy(adapter->mac_table[i].addr, addr); 7242 adapter->mac_table[i].queue = queue; 7243 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7244 7245 igb_rar_set_index(adapter, i); 7246 return i; 7247 } 7248 7249 return -ENOSPC; 7250 } 7251 7252 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7253 const u8 queue) 7254 { 7255 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7256 } 7257 7258 /* Remove a MAC filter for 'addr' directing matching traffic to 7259 * 'queue', 'flags' is used to indicate what kind of match need to be 7260 * removed, match is by default for the destination address, if 7261 * matching by source address is to be removed the flag 7262 * IGB_MAC_STATE_SRC_ADDR can be used. 7263 */ 7264 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7265 const u8 *addr, const u8 queue, 7266 const u8 flags) 7267 { 7268 struct e1000_hw *hw = &adapter->hw; 7269 int rar_entries = hw->mac.rar_entry_count - 7270 adapter->vfs_allocated_count; 7271 int i; 7272 7273 if (is_zero_ether_addr(addr)) 7274 return -EINVAL; 7275 7276 /* Search for matching entry in the MAC table based on given address 7277 * and queue. Do not touch entries at the end of the table reserved 7278 * for the VF MAC addresses. 7279 */ 7280 for (i = 0; i < rar_entries; i++) { 7281 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7282 continue; 7283 if ((adapter->mac_table[i].state & flags) != flags) 7284 continue; 7285 if (adapter->mac_table[i].queue != queue) 7286 continue; 7287 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7288 continue; 7289 7290 /* When a filter for the default address is "deleted", 7291 * we return it to its initial configuration 7292 */ 7293 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7294 adapter->mac_table[i].state = 7295 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7296 adapter->mac_table[i].queue = 7297 adapter->vfs_allocated_count; 7298 } else { 7299 adapter->mac_table[i].state = 0; 7300 adapter->mac_table[i].queue = 0; 7301 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 7302 } 7303 7304 igb_rar_set_index(adapter, i); 7305 return 0; 7306 } 7307 7308 return -ENOENT; 7309 } 7310 7311 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7312 const u8 queue) 7313 { 7314 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7315 } 7316 7317 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7318 const u8 *addr, u8 queue, u8 flags) 7319 { 7320 struct e1000_hw *hw = &adapter->hw; 7321 7322 /* In theory, this should be supported on 82575 as well, but 7323 * that part wasn't easily accessible during development. 7324 */ 7325 if (hw->mac.type != e1000_i210) 7326 return -EOPNOTSUPP; 7327 7328 return igb_add_mac_filter_flags(adapter, addr, queue, 7329 IGB_MAC_STATE_QUEUE_STEERING | flags); 7330 } 7331 7332 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7333 const u8 *addr, u8 queue, u8 flags) 7334 { 7335 return igb_del_mac_filter_flags(adapter, addr, queue, 7336 IGB_MAC_STATE_QUEUE_STEERING | flags); 7337 } 7338 7339 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7340 { 7341 struct igb_adapter *adapter = netdev_priv(netdev); 7342 int ret; 7343 7344 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7345 7346 return min_t(int, ret, 0); 7347 } 7348 7349 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7350 { 7351 struct igb_adapter *adapter = netdev_priv(netdev); 7352 7353 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7354 7355 return 0; 7356 } 7357 7358 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7359 const u32 info, const u8 *addr) 7360 { 7361 struct pci_dev *pdev = adapter->pdev; 7362 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7363 struct list_head *pos; 7364 struct vf_mac_filter *entry = NULL; 7365 int ret = 0; 7366 7367 switch (info) { 7368 case E1000_VF_MAC_FILTER_CLR: 7369 /* remove all unicast MAC filters related to the current VF */ 7370 list_for_each(pos, &adapter->vf_macs.l) { 7371 entry = list_entry(pos, struct vf_mac_filter, l); 7372 if (entry->vf == vf) { 7373 entry->vf = -1; 7374 entry->free = true; 7375 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7376 } 7377 } 7378 break; 7379 case E1000_VF_MAC_FILTER_ADD: 7380 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7381 !vf_data->trusted) { 7382 dev_warn(&pdev->dev, 7383 "VF %d requested MAC filter but is administratively denied\n", 7384 vf); 7385 return -EINVAL; 7386 } 7387 if (!is_valid_ether_addr(addr)) { 7388 dev_warn(&pdev->dev, 7389 "VF %d attempted to set invalid MAC filter\n", 7390 vf); 7391 return -EINVAL; 7392 } 7393 7394 /* try to find empty slot in the list */ 7395 list_for_each(pos, &adapter->vf_macs.l) { 7396 entry = list_entry(pos, struct vf_mac_filter, l); 7397 if (entry->free) 7398 break; 7399 } 7400 7401 if (entry && entry->free) { 7402 entry->free = false; 7403 entry->vf = vf; 7404 ether_addr_copy(entry->vf_mac, addr); 7405 7406 ret = igb_add_mac_filter(adapter, addr, vf); 7407 ret = min_t(int, ret, 0); 7408 } else { 7409 ret = -ENOSPC; 7410 } 7411 7412 if (ret == -ENOSPC) 7413 dev_warn(&pdev->dev, 7414 "VF %d has requested MAC filter but there is no space for it\n", 7415 vf); 7416 break; 7417 default: 7418 ret = -EINVAL; 7419 break; 7420 } 7421 7422 return ret; 7423 } 7424 7425 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7426 { 7427 struct pci_dev *pdev = adapter->pdev; 7428 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7429 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7430 7431 /* The VF MAC Address is stored in a packed array of bytes 7432 * starting at the second 32 bit word of the msg array 7433 */ 7434 unsigned char *addr = (unsigned char *)&msg[1]; 7435 int ret = 0; 7436 7437 if (!info) { 7438 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7439 !vf_data->trusted) { 7440 dev_warn(&pdev->dev, 7441 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 7442 vf); 7443 return -EINVAL; 7444 } 7445 7446 if (!is_valid_ether_addr(addr)) { 7447 dev_warn(&pdev->dev, 7448 "VF %d attempted to set invalid MAC\n", 7449 vf); 7450 return -EINVAL; 7451 } 7452 7453 ret = igb_set_vf_mac(adapter, vf, addr); 7454 } else { 7455 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 7456 } 7457 7458 return ret; 7459 } 7460 7461 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 7462 { 7463 struct e1000_hw *hw = &adapter->hw; 7464 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7465 u32 msg = E1000_VT_MSGTYPE_NACK; 7466 7467 /* if device isn't clear to send it shouldn't be reading either */ 7468 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 7469 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 7470 igb_write_mbx(hw, &msg, 1, vf); 7471 vf_data->last_nack = jiffies; 7472 } 7473 } 7474 7475 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 7476 { 7477 struct pci_dev *pdev = adapter->pdev; 7478 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 7479 struct e1000_hw *hw = &adapter->hw; 7480 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7481 s32 retval; 7482 7483 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 7484 7485 if (retval) { 7486 /* if receive failed revoke VF CTS stats and restart init */ 7487 dev_err(&pdev->dev, "Error receiving message from VF\n"); 7488 vf_data->flags &= ~IGB_VF_FLAG_CTS; 7489 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7490 goto unlock; 7491 goto out; 7492 } 7493 7494 /* this is a message we already processed, do nothing */ 7495 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 7496 goto unlock; 7497 7498 /* until the vf completes a reset it should not be 7499 * allowed to start any configuration. 7500 */ 7501 if (msgbuf[0] == E1000_VF_RESET) { 7502 /* unlocks mailbox */ 7503 igb_vf_reset_msg(adapter, vf); 7504 return; 7505 } 7506 7507 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 7508 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7509 goto unlock; 7510 retval = -1; 7511 goto out; 7512 } 7513 7514 switch ((msgbuf[0] & 0xFFFF)) { 7515 case E1000_VF_SET_MAC_ADDR: 7516 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 7517 break; 7518 case E1000_VF_SET_PROMISC: 7519 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 7520 break; 7521 case E1000_VF_SET_MULTICAST: 7522 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 7523 break; 7524 case E1000_VF_SET_LPE: 7525 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 7526 break; 7527 case E1000_VF_SET_VLAN: 7528 retval = -1; 7529 if (vf_data->pf_vlan) 7530 dev_warn(&pdev->dev, 7531 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 7532 vf); 7533 else 7534 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 7535 break; 7536 default: 7537 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 7538 retval = -1; 7539 break; 7540 } 7541 7542 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 7543 out: 7544 /* notify the VF of the results of what it sent us */ 7545 if (retval) 7546 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 7547 else 7548 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 7549 7550 /* unlocks mailbox */ 7551 igb_write_mbx(hw, msgbuf, 1, vf); 7552 return; 7553 7554 unlock: 7555 igb_unlock_mbx(hw, vf); 7556 } 7557 7558 static void igb_msg_task(struct igb_adapter *adapter) 7559 { 7560 struct e1000_hw *hw = &adapter->hw; 7561 u32 vf; 7562 7563 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 7564 /* process any reset requests */ 7565 if (!igb_check_for_rst(hw, vf)) 7566 igb_vf_reset_event(adapter, vf); 7567 7568 /* process any messages pending */ 7569 if (!igb_check_for_msg(hw, vf)) 7570 igb_rcv_msg_from_vf(adapter, vf); 7571 7572 /* process any acks */ 7573 if (!igb_check_for_ack(hw, vf)) 7574 igb_rcv_ack_from_vf(adapter, vf); 7575 } 7576 } 7577 7578 /** 7579 * igb_set_uta - Set unicast filter table address 7580 * @adapter: board private structure 7581 * @set: boolean indicating if we are setting or clearing bits 7582 * 7583 * The unicast table address is a register array of 32-bit registers. 7584 * The table is meant to be used in a way similar to how the MTA is used 7585 * however due to certain limitations in the hardware it is necessary to 7586 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 7587 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 7588 **/ 7589 static void igb_set_uta(struct igb_adapter *adapter, bool set) 7590 { 7591 struct e1000_hw *hw = &adapter->hw; 7592 u32 uta = set ? ~0 : 0; 7593 int i; 7594 7595 /* we only need to do this if VMDq is enabled */ 7596 if (!adapter->vfs_allocated_count) 7597 return; 7598 7599 for (i = hw->mac.uta_reg_count; i--;) 7600 array_wr32(E1000_UTA, i, uta); 7601 } 7602 7603 /** 7604 * igb_intr_msi - Interrupt Handler 7605 * @irq: interrupt number 7606 * @data: pointer to a network interface device structure 7607 **/ 7608 static irqreturn_t igb_intr_msi(int irq, void *data) 7609 { 7610 struct igb_adapter *adapter = data; 7611 struct igb_q_vector *q_vector = adapter->q_vector[0]; 7612 struct e1000_hw *hw = &adapter->hw; 7613 /* read ICR disables interrupts using IAM */ 7614 u32 icr = rd32(E1000_ICR); 7615 7616 igb_write_itr(q_vector); 7617 7618 if (icr & E1000_ICR_DRSTA) 7619 schedule_work(&adapter->reset_task); 7620 7621 if (icr & E1000_ICR_DOUTSYNC) { 7622 /* HW is reporting DMA is out of sync */ 7623 adapter->stats.doosync++; 7624 } 7625 7626 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 7627 hw->mac.get_link_status = 1; 7628 if (!test_bit(__IGB_DOWN, &adapter->state)) 7629 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7630 } 7631 7632 if (icr & E1000_ICR_TS) 7633 igb_tsync_interrupt(adapter); 7634 7635 napi_schedule(&q_vector->napi); 7636 7637 return IRQ_HANDLED; 7638 } 7639 7640 /** 7641 * igb_intr - Legacy Interrupt Handler 7642 * @irq: interrupt number 7643 * @data: pointer to a network interface device structure 7644 **/ 7645 static irqreturn_t igb_intr(int irq, void *data) 7646 { 7647 struct igb_adapter *adapter = data; 7648 struct igb_q_vector *q_vector = adapter->q_vector[0]; 7649 struct e1000_hw *hw = &adapter->hw; 7650 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 7651 * need for the IMC write 7652 */ 7653 u32 icr = rd32(E1000_ICR); 7654 7655 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 7656 * not set, then the adapter didn't send an interrupt 7657 */ 7658 if (!(icr & E1000_ICR_INT_ASSERTED)) 7659 return IRQ_NONE; 7660 7661 igb_write_itr(q_vector); 7662 7663 if (icr & E1000_ICR_DRSTA) 7664 schedule_work(&adapter->reset_task); 7665 7666 if (icr & E1000_ICR_DOUTSYNC) { 7667 /* HW is reporting DMA is out of sync */ 7668 adapter->stats.doosync++; 7669 } 7670 7671 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 7672 hw->mac.get_link_status = 1; 7673 /* guard against interrupt when we're going down */ 7674 if (!test_bit(__IGB_DOWN, &adapter->state)) 7675 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7676 } 7677 7678 if (icr & E1000_ICR_TS) 7679 igb_tsync_interrupt(adapter); 7680 7681 napi_schedule(&q_vector->napi); 7682 7683 return IRQ_HANDLED; 7684 } 7685 7686 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 7687 { 7688 struct igb_adapter *adapter = q_vector->adapter; 7689 struct e1000_hw *hw = &adapter->hw; 7690 7691 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 7692 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 7693 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 7694 igb_set_itr(q_vector); 7695 else 7696 igb_update_ring_itr(q_vector); 7697 } 7698 7699 if (!test_bit(__IGB_DOWN, &adapter->state)) { 7700 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7701 wr32(E1000_EIMS, q_vector->eims_value); 7702 else 7703 igb_irq_enable(adapter); 7704 } 7705 } 7706 7707 /** 7708 * igb_poll - NAPI Rx polling callback 7709 * @napi: napi polling structure 7710 * @budget: count of how many packets we should handle 7711 **/ 7712 static int igb_poll(struct napi_struct *napi, int budget) 7713 { 7714 struct igb_q_vector *q_vector = container_of(napi, 7715 struct igb_q_vector, 7716 napi); 7717 bool clean_complete = true; 7718 int work_done = 0; 7719 7720 #ifdef CONFIG_IGB_DCA 7721 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 7722 igb_update_dca(q_vector); 7723 #endif 7724 if (q_vector->tx.ring) 7725 clean_complete = igb_clean_tx_irq(q_vector, budget); 7726 7727 if (q_vector->rx.ring) { 7728 int cleaned = igb_clean_rx_irq(q_vector, budget); 7729 7730 work_done += cleaned; 7731 if (cleaned >= budget) 7732 clean_complete = false; 7733 } 7734 7735 /* If all work not completed, return budget and keep polling */ 7736 if (!clean_complete) 7737 return budget; 7738 7739 /* Exit the polling mode, but don't re-enable interrupts if stack might 7740 * poll us due to busy-polling 7741 */ 7742 if (likely(napi_complete_done(napi, work_done))) 7743 igb_ring_irq_enable(q_vector); 7744 7745 return min(work_done, budget - 1); 7746 } 7747 7748 /** 7749 * igb_clean_tx_irq - Reclaim resources after transmit completes 7750 * @q_vector: pointer to q_vector containing needed info 7751 * @napi_budget: Used to determine if we are in netpoll 7752 * 7753 * returns true if ring is completely cleaned 7754 **/ 7755 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 7756 { 7757 struct igb_adapter *adapter = q_vector->adapter; 7758 struct igb_ring *tx_ring = q_vector->tx.ring; 7759 struct igb_tx_buffer *tx_buffer; 7760 union e1000_adv_tx_desc *tx_desc; 7761 unsigned int total_bytes = 0, total_packets = 0; 7762 unsigned int budget = q_vector->tx.work_limit; 7763 unsigned int i = tx_ring->next_to_clean; 7764 7765 if (test_bit(__IGB_DOWN, &adapter->state)) 7766 return true; 7767 7768 tx_buffer = &tx_ring->tx_buffer_info[i]; 7769 tx_desc = IGB_TX_DESC(tx_ring, i); 7770 i -= tx_ring->count; 7771 7772 do { 7773 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 7774 7775 /* if next_to_watch is not set then there is no work pending */ 7776 if (!eop_desc) 7777 break; 7778 7779 /* prevent any other reads prior to eop_desc */ 7780 smp_rmb(); 7781 7782 /* if DD is not set pending work has not been completed */ 7783 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 7784 break; 7785 7786 /* clear next_to_watch to prevent false hangs */ 7787 tx_buffer->next_to_watch = NULL; 7788 7789 /* update the statistics for this packet */ 7790 total_bytes += tx_buffer->bytecount; 7791 total_packets += tx_buffer->gso_segs; 7792 7793 /* free the skb */ 7794 napi_consume_skb(tx_buffer->skb, napi_budget); 7795 7796 /* unmap skb header data */ 7797 dma_unmap_single(tx_ring->dev, 7798 dma_unmap_addr(tx_buffer, dma), 7799 dma_unmap_len(tx_buffer, len), 7800 DMA_TO_DEVICE); 7801 7802 /* clear tx_buffer data */ 7803 dma_unmap_len_set(tx_buffer, len, 0); 7804 7805 /* clear last DMA location and unmap remaining buffers */ 7806 while (tx_desc != eop_desc) { 7807 tx_buffer++; 7808 tx_desc++; 7809 i++; 7810 if (unlikely(!i)) { 7811 i -= tx_ring->count; 7812 tx_buffer = tx_ring->tx_buffer_info; 7813 tx_desc = IGB_TX_DESC(tx_ring, 0); 7814 } 7815 7816 /* unmap any remaining paged data */ 7817 if (dma_unmap_len(tx_buffer, len)) { 7818 dma_unmap_page(tx_ring->dev, 7819 dma_unmap_addr(tx_buffer, dma), 7820 dma_unmap_len(tx_buffer, len), 7821 DMA_TO_DEVICE); 7822 dma_unmap_len_set(tx_buffer, len, 0); 7823 } 7824 } 7825 7826 /* move us one more past the eop_desc for start of next pkt */ 7827 tx_buffer++; 7828 tx_desc++; 7829 i++; 7830 if (unlikely(!i)) { 7831 i -= tx_ring->count; 7832 tx_buffer = tx_ring->tx_buffer_info; 7833 tx_desc = IGB_TX_DESC(tx_ring, 0); 7834 } 7835 7836 /* issue prefetch for next Tx descriptor */ 7837 prefetch(tx_desc); 7838 7839 /* update budget accounting */ 7840 budget--; 7841 } while (likely(budget)); 7842 7843 netdev_tx_completed_queue(txring_txq(tx_ring), 7844 total_packets, total_bytes); 7845 i += tx_ring->count; 7846 tx_ring->next_to_clean = i; 7847 u64_stats_update_begin(&tx_ring->tx_syncp); 7848 tx_ring->tx_stats.bytes += total_bytes; 7849 tx_ring->tx_stats.packets += total_packets; 7850 u64_stats_update_end(&tx_ring->tx_syncp); 7851 q_vector->tx.total_bytes += total_bytes; 7852 q_vector->tx.total_packets += total_packets; 7853 7854 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 7855 struct e1000_hw *hw = &adapter->hw; 7856 7857 /* Detect a transmit hang in hardware, this serializes the 7858 * check with the clearing of time_stamp and movement of i 7859 */ 7860 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 7861 if (tx_buffer->next_to_watch && 7862 time_after(jiffies, tx_buffer->time_stamp + 7863 (adapter->tx_timeout_factor * HZ)) && 7864 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 7865 7866 /* detected Tx unit hang */ 7867 dev_err(tx_ring->dev, 7868 "Detected Tx Unit Hang\n" 7869 " Tx Queue <%d>\n" 7870 " TDH <%x>\n" 7871 " TDT <%x>\n" 7872 " next_to_use <%x>\n" 7873 " next_to_clean <%x>\n" 7874 "buffer_info[next_to_clean]\n" 7875 " time_stamp <%lx>\n" 7876 " next_to_watch <%p>\n" 7877 " jiffies <%lx>\n" 7878 " desc.status <%x>\n", 7879 tx_ring->queue_index, 7880 rd32(E1000_TDH(tx_ring->reg_idx)), 7881 readl(tx_ring->tail), 7882 tx_ring->next_to_use, 7883 tx_ring->next_to_clean, 7884 tx_buffer->time_stamp, 7885 tx_buffer->next_to_watch, 7886 jiffies, 7887 tx_buffer->next_to_watch->wb.status); 7888 netif_stop_subqueue(tx_ring->netdev, 7889 tx_ring->queue_index); 7890 7891 /* we are about to reset, no point in enabling stuff */ 7892 return true; 7893 } 7894 } 7895 7896 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 7897 if (unlikely(total_packets && 7898 netif_carrier_ok(tx_ring->netdev) && 7899 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 7900 /* Make sure that anybody stopping the queue after this 7901 * sees the new next_to_clean. 7902 */ 7903 smp_mb(); 7904 if (__netif_subqueue_stopped(tx_ring->netdev, 7905 tx_ring->queue_index) && 7906 !(test_bit(__IGB_DOWN, &adapter->state))) { 7907 netif_wake_subqueue(tx_ring->netdev, 7908 tx_ring->queue_index); 7909 7910 u64_stats_update_begin(&tx_ring->tx_syncp); 7911 tx_ring->tx_stats.restart_queue++; 7912 u64_stats_update_end(&tx_ring->tx_syncp); 7913 } 7914 } 7915 7916 return !!budget; 7917 } 7918 7919 /** 7920 * igb_reuse_rx_page - page flip buffer and store it back on the ring 7921 * @rx_ring: rx descriptor ring to store buffers on 7922 * @old_buff: donor buffer to have page reused 7923 * 7924 * Synchronizes page for reuse by the adapter 7925 **/ 7926 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 7927 struct igb_rx_buffer *old_buff) 7928 { 7929 struct igb_rx_buffer *new_buff; 7930 u16 nta = rx_ring->next_to_alloc; 7931 7932 new_buff = &rx_ring->rx_buffer_info[nta]; 7933 7934 /* update, and store next to alloc */ 7935 nta++; 7936 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 7937 7938 /* Transfer page from old buffer to new buffer. 7939 * Move each member individually to avoid possible store 7940 * forwarding stalls. 7941 */ 7942 new_buff->dma = old_buff->dma; 7943 new_buff->page = old_buff->page; 7944 new_buff->page_offset = old_buff->page_offset; 7945 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 7946 } 7947 7948 static inline bool igb_page_is_reserved(struct page *page) 7949 { 7950 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 7951 } 7952 7953 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer) 7954 { 7955 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 7956 struct page *page = rx_buffer->page; 7957 7958 /* avoid re-using remote pages */ 7959 if (unlikely(igb_page_is_reserved(page))) 7960 return false; 7961 7962 #if (PAGE_SIZE < 8192) 7963 /* if we are only owner of page we can reuse it */ 7964 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 7965 return false; 7966 #else 7967 #define IGB_LAST_OFFSET \ 7968 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 7969 7970 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 7971 return false; 7972 #endif 7973 7974 /* If we have drained the page fragment pool we need to update 7975 * the pagecnt_bias and page count so that we fully restock the 7976 * number of references the driver holds. 7977 */ 7978 if (unlikely(!pagecnt_bias)) { 7979 page_ref_add(page, USHRT_MAX); 7980 rx_buffer->pagecnt_bias = USHRT_MAX; 7981 } 7982 7983 return true; 7984 } 7985 7986 /** 7987 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 7988 * @rx_ring: rx descriptor ring to transact packets on 7989 * @rx_buffer: buffer containing page to add 7990 * @skb: sk_buff to place the data into 7991 * @size: size of buffer to be added 7992 * 7993 * This function will add the data contained in rx_buffer->page to the skb. 7994 **/ 7995 static void igb_add_rx_frag(struct igb_ring *rx_ring, 7996 struct igb_rx_buffer *rx_buffer, 7997 struct sk_buff *skb, 7998 unsigned int size) 7999 { 8000 #if (PAGE_SIZE < 8192) 8001 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8002 #else 8003 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8004 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8005 SKB_DATA_ALIGN(size); 8006 #endif 8007 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8008 rx_buffer->page_offset, size, truesize); 8009 #if (PAGE_SIZE < 8192) 8010 rx_buffer->page_offset ^= truesize; 8011 #else 8012 rx_buffer->page_offset += truesize; 8013 #endif 8014 } 8015 8016 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8017 struct igb_rx_buffer *rx_buffer, 8018 union e1000_adv_rx_desc *rx_desc, 8019 unsigned int size) 8020 { 8021 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 8022 #if (PAGE_SIZE < 8192) 8023 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8024 #else 8025 unsigned int truesize = SKB_DATA_ALIGN(size); 8026 #endif 8027 unsigned int headlen; 8028 struct sk_buff *skb; 8029 8030 /* prefetch first cache line of first page */ 8031 prefetch(va); 8032 #if L1_CACHE_BYTES < 128 8033 prefetch(va + L1_CACHE_BYTES); 8034 #endif 8035 8036 /* allocate a skb to store the frags */ 8037 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8038 if (unlikely(!skb)) 8039 return NULL; 8040 8041 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) { 8042 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 8043 va += IGB_TS_HDR_LEN; 8044 size -= IGB_TS_HDR_LEN; 8045 } 8046 8047 /* Determine available headroom for copy */ 8048 headlen = size; 8049 if (headlen > IGB_RX_HDR_LEN) 8050 headlen = eth_get_headlen(skb->dev, va, IGB_RX_HDR_LEN); 8051 8052 /* align pull length to size of long to optimize memcpy performance */ 8053 memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long))); 8054 8055 /* update all of the pointers */ 8056 size -= headlen; 8057 if (size) { 8058 skb_add_rx_frag(skb, 0, rx_buffer->page, 8059 (va + headlen) - page_address(rx_buffer->page), 8060 size, truesize); 8061 #if (PAGE_SIZE < 8192) 8062 rx_buffer->page_offset ^= truesize; 8063 #else 8064 rx_buffer->page_offset += truesize; 8065 #endif 8066 } else { 8067 rx_buffer->pagecnt_bias++; 8068 } 8069 8070 return skb; 8071 } 8072 8073 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8074 struct igb_rx_buffer *rx_buffer, 8075 union e1000_adv_rx_desc *rx_desc, 8076 unsigned int size) 8077 { 8078 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 8079 #if (PAGE_SIZE < 8192) 8080 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8081 #else 8082 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8083 SKB_DATA_ALIGN(IGB_SKB_PAD + size); 8084 #endif 8085 struct sk_buff *skb; 8086 8087 /* prefetch first cache line of first page */ 8088 prefetch(va); 8089 #if L1_CACHE_BYTES < 128 8090 prefetch(va + L1_CACHE_BYTES); 8091 #endif 8092 8093 /* build an skb around the page buffer */ 8094 skb = build_skb(va - IGB_SKB_PAD, truesize); 8095 if (unlikely(!skb)) 8096 return NULL; 8097 8098 /* update pointers within the skb to store the data */ 8099 skb_reserve(skb, IGB_SKB_PAD); 8100 __skb_put(skb, size); 8101 8102 /* pull timestamp out of packet data */ 8103 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 8104 igb_ptp_rx_pktstamp(rx_ring->q_vector, skb->data, skb); 8105 __skb_pull(skb, IGB_TS_HDR_LEN); 8106 } 8107 8108 /* update buffer offset */ 8109 #if (PAGE_SIZE < 8192) 8110 rx_buffer->page_offset ^= truesize; 8111 #else 8112 rx_buffer->page_offset += truesize; 8113 #endif 8114 8115 return skb; 8116 } 8117 8118 static inline void igb_rx_checksum(struct igb_ring *ring, 8119 union e1000_adv_rx_desc *rx_desc, 8120 struct sk_buff *skb) 8121 { 8122 skb_checksum_none_assert(skb); 8123 8124 /* Ignore Checksum bit is set */ 8125 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8126 return; 8127 8128 /* Rx checksum disabled via ethtool */ 8129 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8130 return; 8131 8132 /* TCP/UDP checksum error bit is set */ 8133 if (igb_test_staterr(rx_desc, 8134 E1000_RXDEXT_STATERR_TCPE | 8135 E1000_RXDEXT_STATERR_IPE)) { 8136 /* work around errata with sctp packets where the TCPE aka 8137 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8138 * packets, (aka let the stack check the crc32c) 8139 */ 8140 if (!((skb->len == 60) && 8141 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8142 u64_stats_update_begin(&ring->rx_syncp); 8143 ring->rx_stats.csum_err++; 8144 u64_stats_update_end(&ring->rx_syncp); 8145 } 8146 /* let the stack verify checksum errors */ 8147 return; 8148 } 8149 /* It must be a TCP or UDP packet with a valid checksum */ 8150 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8151 E1000_RXD_STAT_UDPCS)) 8152 skb->ip_summed = CHECKSUM_UNNECESSARY; 8153 8154 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8155 le32_to_cpu(rx_desc->wb.upper.status_error)); 8156 } 8157 8158 static inline void igb_rx_hash(struct igb_ring *ring, 8159 union e1000_adv_rx_desc *rx_desc, 8160 struct sk_buff *skb) 8161 { 8162 if (ring->netdev->features & NETIF_F_RXHASH) 8163 skb_set_hash(skb, 8164 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8165 PKT_HASH_TYPE_L3); 8166 } 8167 8168 /** 8169 * igb_is_non_eop - process handling of non-EOP buffers 8170 * @rx_ring: Rx ring being processed 8171 * @rx_desc: Rx descriptor for current buffer 8172 * @skb: current socket buffer containing buffer in progress 8173 * 8174 * This function updates next to clean. If the buffer is an EOP buffer 8175 * this function exits returning false, otherwise it will place the 8176 * sk_buff in the next buffer to be chained and return true indicating 8177 * that this is in fact a non-EOP buffer. 8178 **/ 8179 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8180 union e1000_adv_rx_desc *rx_desc) 8181 { 8182 u32 ntc = rx_ring->next_to_clean + 1; 8183 8184 /* fetch, update, and store next to clean */ 8185 ntc = (ntc < rx_ring->count) ? ntc : 0; 8186 rx_ring->next_to_clean = ntc; 8187 8188 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8189 8190 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8191 return false; 8192 8193 return true; 8194 } 8195 8196 /** 8197 * igb_cleanup_headers - Correct corrupted or empty headers 8198 * @rx_ring: rx descriptor ring packet is being transacted on 8199 * @rx_desc: pointer to the EOP Rx descriptor 8200 * @skb: pointer to current skb being fixed 8201 * 8202 * Address the case where we are pulling data in on pages only 8203 * and as such no data is present in the skb header. 8204 * 8205 * In addition if skb is not at least 60 bytes we need to pad it so that 8206 * it is large enough to qualify as a valid Ethernet frame. 8207 * 8208 * Returns true if an error was encountered and skb was freed. 8209 **/ 8210 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8211 union e1000_adv_rx_desc *rx_desc, 8212 struct sk_buff *skb) 8213 { 8214 if (unlikely((igb_test_staterr(rx_desc, 8215 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8216 struct net_device *netdev = rx_ring->netdev; 8217 if (!(netdev->features & NETIF_F_RXALL)) { 8218 dev_kfree_skb_any(skb); 8219 return true; 8220 } 8221 } 8222 8223 /* if eth_skb_pad returns an error the skb was freed */ 8224 if (eth_skb_pad(skb)) 8225 return true; 8226 8227 return false; 8228 } 8229 8230 /** 8231 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8232 * @rx_ring: rx descriptor ring packet is being transacted on 8233 * @rx_desc: pointer to the EOP Rx descriptor 8234 * @skb: pointer to current skb being populated 8235 * 8236 * This function checks the ring, descriptor, and packet information in 8237 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8238 * other fields within the skb. 8239 **/ 8240 static void igb_process_skb_fields(struct igb_ring *rx_ring, 8241 union e1000_adv_rx_desc *rx_desc, 8242 struct sk_buff *skb) 8243 { 8244 struct net_device *dev = rx_ring->netdev; 8245 8246 igb_rx_hash(rx_ring, rx_desc, skb); 8247 8248 igb_rx_checksum(rx_ring, rx_desc, skb); 8249 8250 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8251 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8252 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8253 8254 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8255 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8256 u16 vid; 8257 8258 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8259 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8260 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 8261 else 8262 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8263 8264 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8265 } 8266 8267 skb_record_rx_queue(skb, rx_ring->queue_index); 8268 8269 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8270 } 8271 8272 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8273 const unsigned int size) 8274 { 8275 struct igb_rx_buffer *rx_buffer; 8276 8277 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8278 prefetchw(rx_buffer->page); 8279 8280 /* we are reusing so sync this buffer for CPU use */ 8281 dma_sync_single_range_for_cpu(rx_ring->dev, 8282 rx_buffer->dma, 8283 rx_buffer->page_offset, 8284 size, 8285 DMA_FROM_DEVICE); 8286 8287 rx_buffer->pagecnt_bias--; 8288 8289 return rx_buffer; 8290 } 8291 8292 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8293 struct igb_rx_buffer *rx_buffer) 8294 { 8295 if (igb_can_reuse_rx_page(rx_buffer)) { 8296 /* hand second half of page back to the ring */ 8297 igb_reuse_rx_page(rx_ring, rx_buffer); 8298 } else { 8299 /* We are not reusing the buffer so unmap it and free 8300 * any references we are holding to it 8301 */ 8302 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8303 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8304 IGB_RX_DMA_ATTR); 8305 __page_frag_cache_drain(rx_buffer->page, 8306 rx_buffer->pagecnt_bias); 8307 } 8308 8309 /* clear contents of rx_buffer */ 8310 rx_buffer->page = NULL; 8311 } 8312 8313 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 8314 { 8315 struct igb_ring *rx_ring = q_vector->rx.ring; 8316 struct sk_buff *skb = rx_ring->skb; 8317 unsigned int total_bytes = 0, total_packets = 0; 8318 u16 cleaned_count = igb_desc_unused(rx_ring); 8319 8320 while (likely(total_packets < budget)) { 8321 union e1000_adv_rx_desc *rx_desc; 8322 struct igb_rx_buffer *rx_buffer; 8323 unsigned int size; 8324 8325 /* return some buffers to hardware, one at a time is too slow */ 8326 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 8327 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8328 cleaned_count = 0; 8329 } 8330 8331 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 8332 size = le16_to_cpu(rx_desc->wb.upper.length); 8333 if (!size) 8334 break; 8335 8336 /* This memory barrier is needed to keep us from reading 8337 * any other fields out of the rx_desc until we know the 8338 * descriptor has been written back 8339 */ 8340 dma_rmb(); 8341 8342 rx_buffer = igb_get_rx_buffer(rx_ring, size); 8343 8344 /* retrieve a buffer from the ring */ 8345 if (skb) 8346 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 8347 else if (ring_uses_build_skb(rx_ring)) 8348 skb = igb_build_skb(rx_ring, rx_buffer, rx_desc, size); 8349 else 8350 skb = igb_construct_skb(rx_ring, rx_buffer, 8351 rx_desc, size); 8352 8353 /* exit if we failed to retrieve a buffer */ 8354 if (!skb) { 8355 rx_ring->rx_stats.alloc_failed++; 8356 rx_buffer->pagecnt_bias++; 8357 break; 8358 } 8359 8360 igb_put_rx_buffer(rx_ring, rx_buffer); 8361 cleaned_count++; 8362 8363 /* fetch next buffer in frame if non-eop */ 8364 if (igb_is_non_eop(rx_ring, rx_desc)) 8365 continue; 8366 8367 /* verify the packet layout is correct */ 8368 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 8369 skb = NULL; 8370 continue; 8371 } 8372 8373 /* probably a little skewed due to removing CRC */ 8374 total_bytes += skb->len; 8375 8376 /* populate checksum, timestamp, VLAN, and protocol */ 8377 igb_process_skb_fields(rx_ring, rx_desc, skb); 8378 8379 napi_gro_receive(&q_vector->napi, skb); 8380 8381 /* reset skb pointer */ 8382 skb = NULL; 8383 8384 /* update budget accounting */ 8385 total_packets++; 8386 } 8387 8388 /* place incomplete frames back on ring for completion */ 8389 rx_ring->skb = skb; 8390 8391 u64_stats_update_begin(&rx_ring->rx_syncp); 8392 rx_ring->rx_stats.packets += total_packets; 8393 rx_ring->rx_stats.bytes += total_bytes; 8394 u64_stats_update_end(&rx_ring->rx_syncp); 8395 q_vector->rx.total_packets += total_packets; 8396 q_vector->rx.total_bytes += total_bytes; 8397 8398 if (cleaned_count) 8399 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8400 8401 return total_packets; 8402 } 8403 8404 static inline unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8405 { 8406 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8407 } 8408 8409 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 8410 struct igb_rx_buffer *bi) 8411 { 8412 struct page *page = bi->page; 8413 dma_addr_t dma; 8414 8415 /* since we are recycling buffers we should seldom need to alloc */ 8416 if (likely(page)) 8417 return true; 8418 8419 /* alloc new page for storage */ 8420 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 8421 if (unlikely(!page)) { 8422 rx_ring->rx_stats.alloc_failed++; 8423 return false; 8424 } 8425 8426 /* map page for use */ 8427 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 8428 igb_rx_pg_size(rx_ring), 8429 DMA_FROM_DEVICE, 8430 IGB_RX_DMA_ATTR); 8431 8432 /* if mapping failed free memory back to system since 8433 * there isn't much point in holding memory we can't use 8434 */ 8435 if (dma_mapping_error(rx_ring->dev, dma)) { 8436 __free_pages(page, igb_rx_pg_order(rx_ring)); 8437 8438 rx_ring->rx_stats.alloc_failed++; 8439 return false; 8440 } 8441 8442 bi->dma = dma; 8443 bi->page = page; 8444 bi->page_offset = igb_rx_offset(rx_ring); 8445 bi->pagecnt_bias = 1; 8446 8447 return true; 8448 } 8449 8450 /** 8451 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 8452 * @adapter: address of board private structure 8453 **/ 8454 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 8455 { 8456 union e1000_adv_rx_desc *rx_desc; 8457 struct igb_rx_buffer *bi; 8458 u16 i = rx_ring->next_to_use; 8459 u16 bufsz; 8460 8461 /* nothing to do */ 8462 if (!cleaned_count) 8463 return; 8464 8465 rx_desc = IGB_RX_DESC(rx_ring, i); 8466 bi = &rx_ring->rx_buffer_info[i]; 8467 i -= rx_ring->count; 8468 8469 bufsz = igb_rx_bufsz(rx_ring); 8470 8471 do { 8472 if (!igb_alloc_mapped_page(rx_ring, bi)) 8473 break; 8474 8475 /* sync the buffer for use by the device */ 8476 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 8477 bi->page_offset, bufsz, 8478 DMA_FROM_DEVICE); 8479 8480 /* Refresh the desc even if buffer_addrs didn't change 8481 * because each write-back erases this info. 8482 */ 8483 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 8484 8485 rx_desc++; 8486 bi++; 8487 i++; 8488 if (unlikely(!i)) { 8489 rx_desc = IGB_RX_DESC(rx_ring, 0); 8490 bi = rx_ring->rx_buffer_info; 8491 i -= rx_ring->count; 8492 } 8493 8494 /* clear the length for the next_to_use descriptor */ 8495 rx_desc->wb.upper.length = 0; 8496 8497 cleaned_count--; 8498 } while (cleaned_count); 8499 8500 i += rx_ring->count; 8501 8502 if (rx_ring->next_to_use != i) { 8503 /* record the next descriptor to use */ 8504 rx_ring->next_to_use = i; 8505 8506 /* update next to alloc since we have filled the ring */ 8507 rx_ring->next_to_alloc = i; 8508 8509 /* Force memory writes to complete before letting h/w 8510 * know there are new descriptors to fetch. (Only 8511 * applicable for weak-ordered memory model archs, 8512 * such as IA-64). 8513 */ 8514 dma_wmb(); 8515 writel(i, rx_ring->tail); 8516 } 8517 } 8518 8519 /** 8520 * igb_mii_ioctl - 8521 * @netdev: 8522 * @ifreq: 8523 * @cmd: 8524 **/ 8525 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 8526 { 8527 struct igb_adapter *adapter = netdev_priv(netdev); 8528 struct mii_ioctl_data *data = if_mii(ifr); 8529 8530 if (adapter->hw.phy.media_type != e1000_media_type_copper) 8531 return -EOPNOTSUPP; 8532 8533 switch (cmd) { 8534 case SIOCGMIIPHY: 8535 data->phy_id = adapter->hw.phy.addr; 8536 break; 8537 case SIOCGMIIREG: 8538 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 8539 &data->val_out)) 8540 return -EIO; 8541 break; 8542 case SIOCSMIIREG: 8543 default: 8544 return -EOPNOTSUPP; 8545 } 8546 return 0; 8547 } 8548 8549 /** 8550 * igb_ioctl - 8551 * @netdev: 8552 * @ifreq: 8553 * @cmd: 8554 **/ 8555 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 8556 { 8557 switch (cmd) { 8558 case SIOCGMIIPHY: 8559 case SIOCGMIIREG: 8560 case SIOCSMIIREG: 8561 return igb_mii_ioctl(netdev, ifr, cmd); 8562 case SIOCGHWTSTAMP: 8563 return igb_ptp_get_ts_config(netdev, ifr); 8564 case SIOCSHWTSTAMP: 8565 return igb_ptp_set_ts_config(netdev, ifr); 8566 default: 8567 return -EOPNOTSUPP; 8568 } 8569 } 8570 8571 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 8572 { 8573 struct igb_adapter *adapter = hw->back; 8574 8575 pci_read_config_word(adapter->pdev, reg, value); 8576 } 8577 8578 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 8579 { 8580 struct igb_adapter *adapter = hw->back; 8581 8582 pci_write_config_word(adapter->pdev, reg, *value); 8583 } 8584 8585 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 8586 { 8587 struct igb_adapter *adapter = hw->back; 8588 8589 if (pcie_capability_read_word(adapter->pdev, reg, value)) 8590 return -E1000_ERR_CONFIG; 8591 8592 return 0; 8593 } 8594 8595 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 8596 { 8597 struct igb_adapter *adapter = hw->back; 8598 8599 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 8600 return -E1000_ERR_CONFIG; 8601 8602 return 0; 8603 } 8604 8605 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 8606 { 8607 struct igb_adapter *adapter = netdev_priv(netdev); 8608 struct e1000_hw *hw = &adapter->hw; 8609 u32 ctrl, rctl; 8610 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 8611 8612 if (enable) { 8613 /* enable VLAN tag insert/strip */ 8614 ctrl = rd32(E1000_CTRL); 8615 ctrl |= E1000_CTRL_VME; 8616 wr32(E1000_CTRL, ctrl); 8617 8618 /* Disable CFI check */ 8619 rctl = rd32(E1000_RCTL); 8620 rctl &= ~E1000_RCTL_CFIEN; 8621 wr32(E1000_RCTL, rctl); 8622 } else { 8623 /* disable VLAN tag insert/strip */ 8624 ctrl = rd32(E1000_CTRL); 8625 ctrl &= ~E1000_CTRL_VME; 8626 wr32(E1000_CTRL, ctrl); 8627 } 8628 8629 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 8630 } 8631 8632 static int igb_vlan_rx_add_vid(struct net_device *netdev, 8633 __be16 proto, u16 vid) 8634 { 8635 struct igb_adapter *adapter = netdev_priv(netdev); 8636 struct e1000_hw *hw = &adapter->hw; 8637 int pf_id = adapter->vfs_allocated_count; 8638 8639 /* add the filter since PF can receive vlans w/o entry in vlvf */ 8640 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 8641 igb_vfta_set(hw, vid, pf_id, true, !!vid); 8642 8643 set_bit(vid, adapter->active_vlans); 8644 8645 return 0; 8646 } 8647 8648 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 8649 __be16 proto, u16 vid) 8650 { 8651 struct igb_adapter *adapter = netdev_priv(netdev); 8652 int pf_id = adapter->vfs_allocated_count; 8653 struct e1000_hw *hw = &adapter->hw; 8654 8655 /* remove VID from filter table */ 8656 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 8657 igb_vfta_set(hw, vid, pf_id, false, true); 8658 8659 clear_bit(vid, adapter->active_vlans); 8660 8661 return 0; 8662 } 8663 8664 static void igb_restore_vlan(struct igb_adapter *adapter) 8665 { 8666 u16 vid = 1; 8667 8668 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 8669 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 8670 8671 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 8672 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 8673 } 8674 8675 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 8676 { 8677 struct pci_dev *pdev = adapter->pdev; 8678 struct e1000_mac_info *mac = &adapter->hw.mac; 8679 8680 mac->autoneg = 0; 8681 8682 /* Make sure dplx is at most 1 bit and lsb of speed is not set 8683 * for the switch() below to work 8684 */ 8685 if ((spd & 1) || (dplx & ~1)) 8686 goto err_inval; 8687 8688 /* Fiber NIC's only allow 1000 gbps Full duplex 8689 * and 100Mbps Full duplex for 100baseFx sfp 8690 */ 8691 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 8692 switch (spd + dplx) { 8693 case SPEED_10 + DUPLEX_HALF: 8694 case SPEED_10 + DUPLEX_FULL: 8695 case SPEED_100 + DUPLEX_HALF: 8696 goto err_inval; 8697 default: 8698 break; 8699 } 8700 } 8701 8702 switch (spd + dplx) { 8703 case SPEED_10 + DUPLEX_HALF: 8704 mac->forced_speed_duplex = ADVERTISE_10_HALF; 8705 break; 8706 case SPEED_10 + DUPLEX_FULL: 8707 mac->forced_speed_duplex = ADVERTISE_10_FULL; 8708 break; 8709 case SPEED_100 + DUPLEX_HALF: 8710 mac->forced_speed_duplex = ADVERTISE_100_HALF; 8711 break; 8712 case SPEED_100 + DUPLEX_FULL: 8713 mac->forced_speed_duplex = ADVERTISE_100_FULL; 8714 break; 8715 case SPEED_1000 + DUPLEX_FULL: 8716 mac->autoneg = 1; 8717 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 8718 break; 8719 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 8720 default: 8721 goto err_inval; 8722 } 8723 8724 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 8725 adapter->hw.phy.mdix = AUTO_ALL_MODES; 8726 8727 return 0; 8728 8729 err_inval: 8730 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 8731 return -EINVAL; 8732 } 8733 8734 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 8735 bool runtime) 8736 { 8737 struct net_device *netdev = pci_get_drvdata(pdev); 8738 struct igb_adapter *adapter = netdev_priv(netdev); 8739 struct e1000_hw *hw = &adapter->hw; 8740 u32 ctrl, rctl, status; 8741 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 8742 bool wake; 8743 8744 rtnl_lock(); 8745 netif_device_detach(netdev); 8746 8747 if (netif_running(netdev)) 8748 __igb_close(netdev, true); 8749 8750 igb_ptp_suspend(adapter); 8751 8752 igb_clear_interrupt_scheme(adapter); 8753 rtnl_unlock(); 8754 8755 status = rd32(E1000_STATUS); 8756 if (status & E1000_STATUS_LU) 8757 wufc &= ~E1000_WUFC_LNKC; 8758 8759 if (wufc) { 8760 igb_setup_rctl(adapter); 8761 igb_set_rx_mode(netdev); 8762 8763 /* turn on all-multi mode if wake on multicast is enabled */ 8764 if (wufc & E1000_WUFC_MC) { 8765 rctl = rd32(E1000_RCTL); 8766 rctl |= E1000_RCTL_MPE; 8767 wr32(E1000_RCTL, rctl); 8768 } 8769 8770 ctrl = rd32(E1000_CTRL); 8771 ctrl |= E1000_CTRL_ADVD3WUC; 8772 wr32(E1000_CTRL, ctrl); 8773 8774 /* Allow time for pending master requests to run */ 8775 igb_disable_pcie_master(hw); 8776 8777 wr32(E1000_WUC, E1000_WUC_PME_EN); 8778 wr32(E1000_WUFC, wufc); 8779 } else { 8780 wr32(E1000_WUC, 0); 8781 wr32(E1000_WUFC, 0); 8782 } 8783 8784 wake = wufc || adapter->en_mng_pt; 8785 if (!wake) 8786 igb_power_down_link(adapter); 8787 else 8788 igb_power_up_link(adapter); 8789 8790 if (enable_wake) 8791 *enable_wake = wake; 8792 8793 /* Release control of h/w to f/w. If f/w is AMT enabled, this 8794 * would have already happened in close and is redundant. 8795 */ 8796 igb_release_hw_control(adapter); 8797 8798 pci_disable_device(pdev); 8799 8800 return 0; 8801 } 8802 8803 static void igb_deliver_wake_packet(struct net_device *netdev) 8804 { 8805 struct igb_adapter *adapter = netdev_priv(netdev); 8806 struct e1000_hw *hw = &adapter->hw; 8807 struct sk_buff *skb; 8808 u32 wupl; 8809 8810 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 8811 8812 /* WUPM stores only the first 128 bytes of the wake packet. 8813 * Read the packet only if we have the whole thing. 8814 */ 8815 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 8816 return; 8817 8818 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 8819 if (!skb) 8820 return; 8821 8822 skb_put(skb, wupl); 8823 8824 /* Ensure reads are 32-bit aligned */ 8825 wupl = roundup(wupl, 4); 8826 8827 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 8828 8829 skb->protocol = eth_type_trans(skb, netdev); 8830 netif_rx(skb); 8831 } 8832 8833 static int __maybe_unused igb_suspend(struct device *dev) 8834 { 8835 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 8836 } 8837 8838 static int __maybe_unused igb_resume(struct device *dev) 8839 { 8840 struct pci_dev *pdev = to_pci_dev(dev); 8841 struct net_device *netdev = pci_get_drvdata(pdev); 8842 struct igb_adapter *adapter = netdev_priv(netdev); 8843 struct e1000_hw *hw = &adapter->hw; 8844 u32 err, val; 8845 8846 pci_set_power_state(pdev, PCI_D0); 8847 pci_restore_state(pdev); 8848 pci_save_state(pdev); 8849 8850 if (!pci_device_is_present(pdev)) 8851 return -ENODEV; 8852 err = pci_enable_device_mem(pdev); 8853 if (err) { 8854 dev_err(&pdev->dev, 8855 "igb: Cannot enable PCI device from suspend\n"); 8856 return err; 8857 } 8858 pci_set_master(pdev); 8859 8860 pci_enable_wake(pdev, PCI_D3hot, 0); 8861 pci_enable_wake(pdev, PCI_D3cold, 0); 8862 8863 if (igb_init_interrupt_scheme(adapter, true)) { 8864 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8865 return -ENOMEM; 8866 } 8867 8868 igb_reset(adapter); 8869 8870 /* let the f/w know that the h/w is now under the control of the 8871 * driver. 8872 */ 8873 igb_get_hw_control(adapter); 8874 8875 val = rd32(E1000_WUS); 8876 if (val & WAKE_PKT_WUS) 8877 igb_deliver_wake_packet(netdev); 8878 8879 wr32(E1000_WUS, ~0); 8880 8881 rtnl_lock(); 8882 if (!err && netif_running(netdev)) 8883 err = __igb_open(netdev, true); 8884 8885 if (!err) 8886 netif_device_attach(netdev); 8887 rtnl_unlock(); 8888 8889 return err; 8890 } 8891 8892 static int __maybe_unused igb_runtime_idle(struct device *dev) 8893 { 8894 struct pci_dev *pdev = to_pci_dev(dev); 8895 struct net_device *netdev = pci_get_drvdata(pdev); 8896 struct igb_adapter *adapter = netdev_priv(netdev); 8897 8898 if (!igb_has_link(adapter)) 8899 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 8900 8901 return -EBUSY; 8902 } 8903 8904 static int __maybe_unused igb_runtime_suspend(struct device *dev) 8905 { 8906 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 8907 } 8908 8909 static int __maybe_unused igb_runtime_resume(struct device *dev) 8910 { 8911 return igb_resume(dev); 8912 } 8913 8914 static void igb_shutdown(struct pci_dev *pdev) 8915 { 8916 bool wake; 8917 8918 __igb_shutdown(pdev, &wake, 0); 8919 8920 if (system_state == SYSTEM_POWER_OFF) { 8921 pci_wake_from_d3(pdev, wake); 8922 pci_set_power_state(pdev, PCI_D3hot); 8923 } 8924 } 8925 8926 #ifdef CONFIG_PCI_IOV 8927 static int igb_sriov_reinit(struct pci_dev *dev) 8928 { 8929 struct net_device *netdev = pci_get_drvdata(dev); 8930 struct igb_adapter *adapter = netdev_priv(netdev); 8931 struct pci_dev *pdev = adapter->pdev; 8932 8933 rtnl_lock(); 8934 8935 if (netif_running(netdev)) 8936 igb_close(netdev); 8937 else 8938 igb_reset(adapter); 8939 8940 igb_clear_interrupt_scheme(adapter); 8941 8942 igb_init_queue_configuration(adapter); 8943 8944 if (igb_init_interrupt_scheme(adapter, true)) { 8945 rtnl_unlock(); 8946 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8947 return -ENOMEM; 8948 } 8949 8950 if (netif_running(netdev)) 8951 igb_open(netdev); 8952 8953 rtnl_unlock(); 8954 8955 return 0; 8956 } 8957 8958 static int igb_pci_disable_sriov(struct pci_dev *dev) 8959 { 8960 int err = igb_disable_sriov(dev); 8961 8962 if (!err) 8963 err = igb_sriov_reinit(dev); 8964 8965 return err; 8966 } 8967 8968 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 8969 { 8970 int err = igb_enable_sriov(dev, num_vfs); 8971 8972 if (err) 8973 goto out; 8974 8975 err = igb_sriov_reinit(dev); 8976 if (!err) 8977 return num_vfs; 8978 8979 out: 8980 return err; 8981 } 8982 8983 #endif 8984 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 8985 { 8986 #ifdef CONFIG_PCI_IOV 8987 if (num_vfs == 0) 8988 return igb_pci_disable_sriov(dev); 8989 else 8990 return igb_pci_enable_sriov(dev, num_vfs); 8991 #endif 8992 return 0; 8993 } 8994 8995 /** 8996 * igb_io_error_detected - called when PCI error is detected 8997 * @pdev: Pointer to PCI device 8998 * @state: The current pci connection state 8999 * 9000 * This function is called after a PCI bus error affecting 9001 * this device has been detected. 9002 **/ 9003 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9004 pci_channel_state_t state) 9005 { 9006 struct net_device *netdev = pci_get_drvdata(pdev); 9007 struct igb_adapter *adapter = netdev_priv(netdev); 9008 9009 netif_device_detach(netdev); 9010 9011 if (state == pci_channel_io_perm_failure) 9012 return PCI_ERS_RESULT_DISCONNECT; 9013 9014 if (netif_running(netdev)) 9015 igb_down(adapter); 9016 pci_disable_device(pdev); 9017 9018 /* Request a slot slot reset. */ 9019 return PCI_ERS_RESULT_NEED_RESET; 9020 } 9021 9022 /** 9023 * igb_io_slot_reset - called after the pci bus has been reset. 9024 * @pdev: Pointer to PCI device 9025 * 9026 * Restart the card from scratch, as if from a cold-boot. Implementation 9027 * resembles the first-half of the igb_resume routine. 9028 **/ 9029 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9030 { 9031 struct net_device *netdev = pci_get_drvdata(pdev); 9032 struct igb_adapter *adapter = netdev_priv(netdev); 9033 struct e1000_hw *hw = &adapter->hw; 9034 pci_ers_result_t result; 9035 9036 if (pci_enable_device_mem(pdev)) { 9037 dev_err(&pdev->dev, 9038 "Cannot re-enable PCI device after reset.\n"); 9039 result = PCI_ERS_RESULT_DISCONNECT; 9040 } else { 9041 pci_set_master(pdev); 9042 pci_restore_state(pdev); 9043 pci_save_state(pdev); 9044 9045 pci_enable_wake(pdev, PCI_D3hot, 0); 9046 pci_enable_wake(pdev, PCI_D3cold, 0); 9047 9048 /* In case of PCI error, adapter lose its HW address 9049 * so we should re-assign it here. 9050 */ 9051 hw->hw_addr = adapter->io_addr; 9052 9053 igb_reset(adapter); 9054 wr32(E1000_WUS, ~0); 9055 result = PCI_ERS_RESULT_RECOVERED; 9056 } 9057 9058 return result; 9059 } 9060 9061 /** 9062 * igb_io_resume - called when traffic can start flowing again. 9063 * @pdev: Pointer to PCI device 9064 * 9065 * This callback is called when the error recovery driver tells us that 9066 * its OK to resume normal operation. Implementation resembles the 9067 * second-half of the igb_resume routine. 9068 */ 9069 static void igb_io_resume(struct pci_dev *pdev) 9070 { 9071 struct net_device *netdev = pci_get_drvdata(pdev); 9072 struct igb_adapter *adapter = netdev_priv(netdev); 9073 9074 if (netif_running(netdev)) { 9075 if (igb_up(adapter)) { 9076 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9077 return; 9078 } 9079 } 9080 9081 netif_device_attach(netdev); 9082 9083 /* let the f/w know that the h/w is now under the control of the 9084 * driver. 9085 */ 9086 igb_get_hw_control(adapter); 9087 } 9088 9089 /** 9090 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9091 * @adapter: Pointer to adapter structure 9092 * @index: Index of the RAR entry which need to be synced with MAC table 9093 **/ 9094 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9095 { 9096 struct e1000_hw *hw = &adapter->hw; 9097 u32 rar_low, rar_high; 9098 u8 *addr = adapter->mac_table[index].addr; 9099 9100 /* HW expects these to be in network order when they are plugged 9101 * into the registers which are little endian. In order to guarantee 9102 * that ordering we need to do an leXX_to_cpup here in order to be 9103 * ready for the byteswap that occurs with writel 9104 */ 9105 rar_low = le32_to_cpup((__le32 *)(addr)); 9106 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9107 9108 /* Indicate to hardware the Address is Valid. */ 9109 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9110 if (is_valid_ether_addr(addr)) 9111 rar_high |= E1000_RAH_AV; 9112 9113 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9114 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9115 9116 switch (hw->mac.type) { 9117 case e1000_82575: 9118 case e1000_i210: 9119 if (adapter->mac_table[index].state & 9120 IGB_MAC_STATE_QUEUE_STEERING) 9121 rar_high |= E1000_RAH_QSEL_ENABLE; 9122 9123 rar_high |= E1000_RAH_POOL_1 * 9124 adapter->mac_table[index].queue; 9125 break; 9126 default: 9127 rar_high |= E1000_RAH_POOL_1 << 9128 adapter->mac_table[index].queue; 9129 break; 9130 } 9131 } 9132 9133 wr32(E1000_RAL(index), rar_low); 9134 wrfl(); 9135 wr32(E1000_RAH(index), rar_high); 9136 wrfl(); 9137 } 9138 9139 static int igb_set_vf_mac(struct igb_adapter *adapter, 9140 int vf, unsigned char *mac_addr) 9141 { 9142 struct e1000_hw *hw = &adapter->hw; 9143 /* VF MAC addresses start at end of receive addresses and moves 9144 * towards the first, as a result a collision should not be possible 9145 */ 9146 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9147 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9148 9149 ether_addr_copy(vf_mac_addr, mac_addr); 9150 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9151 adapter->mac_table[rar_entry].queue = vf; 9152 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9153 igb_rar_set_index(adapter, rar_entry); 9154 9155 return 0; 9156 } 9157 9158 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9159 { 9160 struct igb_adapter *adapter = netdev_priv(netdev); 9161 9162 if (vf >= adapter->vfs_allocated_count) 9163 return -EINVAL; 9164 9165 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9166 * flag and allows to overwrite the MAC via VF netdev. This 9167 * is necessary to allow libvirt a way to restore the original 9168 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9169 * down a VM. 9170 */ 9171 if (is_zero_ether_addr(mac)) { 9172 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9173 dev_info(&adapter->pdev->dev, 9174 "remove administratively set MAC on VF %d\n", 9175 vf); 9176 } else if (is_valid_ether_addr(mac)) { 9177 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9178 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9179 mac, vf); 9180 dev_info(&adapter->pdev->dev, 9181 "Reload the VF driver to make this change effective."); 9182 /* Generate additional warning if PF is down */ 9183 if (test_bit(__IGB_DOWN, &adapter->state)) { 9184 dev_warn(&adapter->pdev->dev, 9185 "The VF MAC address has been set, but the PF device is not up.\n"); 9186 dev_warn(&adapter->pdev->dev, 9187 "Bring the PF device up before attempting to use the VF device.\n"); 9188 } 9189 } else { 9190 return -EINVAL; 9191 } 9192 return igb_set_vf_mac(adapter, vf, mac); 9193 } 9194 9195 static int igb_link_mbps(int internal_link_speed) 9196 { 9197 switch (internal_link_speed) { 9198 case SPEED_100: 9199 return 100; 9200 case SPEED_1000: 9201 return 1000; 9202 default: 9203 return 0; 9204 } 9205 } 9206 9207 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9208 int link_speed) 9209 { 9210 int rf_dec, rf_int; 9211 u32 bcnrc_val; 9212 9213 if (tx_rate != 0) { 9214 /* Calculate the rate factor values to set */ 9215 rf_int = link_speed / tx_rate; 9216 rf_dec = (link_speed - (rf_int * tx_rate)); 9217 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9218 tx_rate; 9219 9220 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9221 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 9222 E1000_RTTBCNRC_RF_INT_MASK); 9223 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9224 } else { 9225 bcnrc_val = 0; 9226 } 9227 9228 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9229 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9230 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9231 */ 9232 wr32(E1000_RTTBCNRM, 0x14); 9233 wr32(E1000_RTTBCNRC, bcnrc_val); 9234 } 9235 9236 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9237 { 9238 int actual_link_speed, i; 9239 bool reset_rate = false; 9240 9241 /* VF TX rate limit was not set or not supported */ 9242 if ((adapter->vf_rate_link_speed == 0) || 9243 (adapter->hw.mac.type != e1000_82576)) 9244 return; 9245 9246 actual_link_speed = igb_link_mbps(adapter->link_speed); 9247 if (actual_link_speed != adapter->vf_rate_link_speed) { 9248 reset_rate = true; 9249 adapter->vf_rate_link_speed = 0; 9250 dev_info(&adapter->pdev->dev, 9251 "Link speed has been changed. VF Transmit rate is disabled\n"); 9252 } 9253 9254 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9255 if (reset_rate) 9256 adapter->vf_data[i].tx_rate = 0; 9257 9258 igb_set_vf_rate_limit(&adapter->hw, i, 9259 adapter->vf_data[i].tx_rate, 9260 actual_link_speed); 9261 } 9262 } 9263 9264 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9265 int min_tx_rate, int max_tx_rate) 9266 { 9267 struct igb_adapter *adapter = netdev_priv(netdev); 9268 struct e1000_hw *hw = &adapter->hw; 9269 int actual_link_speed; 9270 9271 if (hw->mac.type != e1000_82576) 9272 return -EOPNOTSUPP; 9273 9274 if (min_tx_rate) 9275 return -EINVAL; 9276 9277 actual_link_speed = igb_link_mbps(adapter->link_speed); 9278 if ((vf >= adapter->vfs_allocated_count) || 9279 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9280 (max_tx_rate < 0) || 9281 (max_tx_rate > actual_link_speed)) 9282 return -EINVAL; 9283 9284 adapter->vf_rate_link_speed = actual_link_speed; 9285 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 9286 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 9287 9288 return 0; 9289 } 9290 9291 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 9292 bool setting) 9293 { 9294 struct igb_adapter *adapter = netdev_priv(netdev); 9295 struct e1000_hw *hw = &adapter->hw; 9296 u32 reg_val, reg_offset; 9297 9298 if (!adapter->vfs_allocated_count) 9299 return -EOPNOTSUPP; 9300 9301 if (vf >= adapter->vfs_allocated_count) 9302 return -EINVAL; 9303 9304 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 9305 reg_val = rd32(reg_offset); 9306 if (setting) 9307 reg_val |= (BIT(vf) | 9308 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9309 else 9310 reg_val &= ~(BIT(vf) | 9311 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9312 wr32(reg_offset, reg_val); 9313 9314 adapter->vf_data[vf].spoofchk_enabled = setting; 9315 return 0; 9316 } 9317 9318 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 9319 { 9320 struct igb_adapter *adapter = netdev_priv(netdev); 9321 9322 if (vf >= adapter->vfs_allocated_count) 9323 return -EINVAL; 9324 if (adapter->vf_data[vf].trusted == setting) 9325 return 0; 9326 9327 adapter->vf_data[vf].trusted = setting; 9328 9329 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 9330 vf, setting ? "" : "not "); 9331 return 0; 9332 } 9333 9334 static int igb_ndo_get_vf_config(struct net_device *netdev, 9335 int vf, struct ifla_vf_info *ivi) 9336 { 9337 struct igb_adapter *adapter = netdev_priv(netdev); 9338 if (vf >= adapter->vfs_allocated_count) 9339 return -EINVAL; 9340 ivi->vf = vf; 9341 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 9342 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 9343 ivi->min_tx_rate = 0; 9344 ivi->vlan = adapter->vf_data[vf].pf_vlan; 9345 ivi->qos = adapter->vf_data[vf].pf_qos; 9346 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 9347 ivi->trusted = adapter->vf_data[vf].trusted; 9348 return 0; 9349 } 9350 9351 static void igb_vmm_control(struct igb_adapter *adapter) 9352 { 9353 struct e1000_hw *hw = &adapter->hw; 9354 u32 reg; 9355 9356 switch (hw->mac.type) { 9357 case e1000_82575: 9358 case e1000_i210: 9359 case e1000_i211: 9360 case e1000_i354: 9361 default: 9362 /* replication is not supported for 82575 */ 9363 return; 9364 case e1000_82576: 9365 /* notify HW that the MAC is adding vlan tags */ 9366 reg = rd32(E1000_DTXCTL); 9367 reg |= E1000_DTXCTL_VLAN_ADDED; 9368 wr32(E1000_DTXCTL, reg); 9369 /* Fall through */ 9370 case e1000_82580: 9371 /* enable replication vlan tag stripping */ 9372 reg = rd32(E1000_RPLOLR); 9373 reg |= E1000_RPLOLR_STRVLAN; 9374 wr32(E1000_RPLOLR, reg); 9375 /* Fall through */ 9376 case e1000_i350: 9377 /* none of the above registers are supported by i350 */ 9378 break; 9379 } 9380 9381 if (adapter->vfs_allocated_count) { 9382 igb_vmdq_set_loopback_pf(hw, true); 9383 igb_vmdq_set_replication_pf(hw, true); 9384 igb_vmdq_set_anti_spoofing_pf(hw, true, 9385 adapter->vfs_allocated_count); 9386 } else { 9387 igb_vmdq_set_loopback_pf(hw, false); 9388 igb_vmdq_set_replication_pf(hw, false); 9389 } 9390 } 9391 9392 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 9393 { 9394 struct e1000_hw *hw = &adapter->hw; 9395 u32 dmac_thr; 9396 u16 hwm; 9397 9398 if (hw->mac.type > e1000_82580) { 9399 if (adapter->flags & IGB_FLAG_DMAC) { 9400 u32 reg; 9401 9402 /* force threshold to 0. */ 9403 wr32(E1000_DMCTXTH, 0); 9404 9405 /* DMA Coalescing high water mark needs to be greater 9406 * than the Rx threshold. Set hwm to PBA - max frame 9407 * size in 16B units, capping it at PBA - 6KB. 9408 */ 9409 hwm = 64 * (pba - 6); 9410 reg = rd32(E1000_FCRTC); 9411 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 9412 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 9413 & E1000_FCRTC_RTH_COAL_MASK); 9414 wr32(E1000_FCRTC, reg); 9415 9416 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 9417 * frame size, capping it at PBA - 10KB. 9418 */ 9419 dmac_thr = pba - 10; 9420 reg = rd32(E1000_DMACR); 9421 reg &= ~E1000_DMACR_DMACTHR_MASK; 9422 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 9423 & E1000_DMACR_DMACTHR_MASK); 9424 9425 /* transition to L0x or L1 if available..*/ 9426 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 9427 9428 /* watchdog timer= +-1000 usec in 32usec intervals */ 9429 reg |= (1000 >> 5); 9430 9431 /* Disable BMC-to-OS Watchdog Enable */ 9432 if (hw->mac.type != e1000_i354) 9433 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 9434 9435 wr32(E1000_DMACR, reg); 9436 9437 /* no lower threshold to disable 9438 * coalescing(smart fifb)-UTRESH=0 9439 */ 9440 wr32(E1000_DMCRTRH, 0); 9441 9442 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 9443 9444 wr32(E1000_DMCTLX, reg); 9445 9446 /* free space in tx packet buffer to wake from 9447 * DMA coal 9448 */ 9449 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 9450 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 9451 9452 /* make low power state decision controlled 9453 * by DMA coal 9454 */ 9455 reg = rd32(E1000_PCIEMISC); 9456 reg &= ~E1000_PCIEMISC_LX_DECISION; 9457 wr32(E1000_PCIEMISC, reg); 9458 } /* endif adapter->dmac is not disabled */ 9459 } else if (hw->mac.type == e1000_82580) { 9460 u32 reg = rd32(E1000_PCIEMISC); 9461 9462 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 9463 wr32(E1000_DMACR, 0); 9464 } 9465 } 9466 9467 /** 9468 * igb_read_i2c_byte - Reads 8 bit word over I2C 9469 * @hw: pointer to hardware structure 9470 * @byte_offset: byte offset to read 9471 * @dev_addr: device address 9472 * @data: value read 9473 * 9474 * Performs byte read operation over I2C interface at 9475 * a specified device address. 9476 **/ 9477 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 9478 u8 dev_addr, u8 *data) 9479 { 9480 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 9481 struct i2c_client *this_client = adapter->i2c_client; 9482 s32 status; 9483 u16 swfw_mask = 0; 9484 9485 if (!this_client) 9486 return E1000_ERR_I2C; 9487 9488 swfw_mask = E1000_SWFW_PHY0_SM; 9489 9490 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 9491 return E1000_ERR_SWFW_SYNC; 9492 9493 status = i2c_smbus_read_byte_data(this_client, byte_offset); 9494 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 9495 9496 if (status < 0) 9497 return E1000_ERR_I2C; 9498 else { 9499 *data = status; 9500 return 0; 9501 } 9502 } 9503 9504 /** 9505 * igb_write_i2c_byte - Writes 8 bit word over I2C 9506 * @hw: pointer to hardware structure 9507 * @byte_offset: byte offset to write 9508 * @dev_addr: device address 9509 * @data: value to write 9510 * 9511 * Performs byte write operation over I2C interface at 9512 * a specified device address. 9513 **/ 9514 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 9515 u8 dev_addr, u8 data) 9516 { 9517 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 9518 struct i2c_client *this_client = adapter->i2c_client; 9519 s32 status; 9520 u16 swfw_mask = E1000_SWFW_PHY0_SM; 9521 9522 if (!this_client) 9523 return E1000_ERR_I2C; 9524 9525 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 9526 return E1000_ERR_SWFW_SYNC; 9527 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 9528 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 9529 9530 if (status) 9531 return E1000_ERR_I2C; 9532 else 9533 return 0; 9534 9535 } 9536 9537 int igb_reinit_queues(struct igb_adapter *adapter) 9538 { 9539 struct net_device *netdev = adapter->netdev; 9540 struct pci_dev *pdev = adapter->pdev; 9541 int err = 0; 9542 9543 if (netif_running(netdev)) 9544 igb_close(netdev); 9545 9546 igb_reset_interrupt_capability(adapter); 9547 9548 if (igb_init_interrupt_scheme(adapter, true)) { 9549 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9550 return -ENOMEM; 9551 } 9552 9553 if (netif_running(netdev)) 9554 err = igb_open(netdev); 9555 9556 return err; 9557 } 9558 9559 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 9560 { 9561 struct igb_nfc_filter *rule; 9562 9563 spin_lock(&adapter->nfc_lock); 9564 9565 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 9566 igb_erase_filter(adapter, rule); 9567 9568 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 9569 igb_erase_filter(adapter, rule); 9570 9571 spin_unlock(&adapter->nfc_lock); 9572 } 9573 9574 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 9575 { 9576 struct igb_nfc_filter *rule; 9577 9578 spin_lock(&adapter->nfc_lock); 9579 9580 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 9581 igb_add_filter(adapter, rule); 9582 9583 spin_unlock(&adapter->nfc_lock); 9584 } 9585 /* igb_main.c */ 9586