1 /* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 25 26 #include <linux/module.h> 27 #include <linux/types.h> 28 #include <linux/init.h> 29 #include <linux/bitops.h> 30 #include <linux/vmalloc.h> 31 #include <linux/pagemap.h> 32 #include <linux/netdevice.h> 33 #include <linux/ipv6.h> 34 #include <linux/slab.h> 35 #include <net/checksum.h> 36 #include <net/ip6_checksum.h> 37 #include <linux/net_tstamp.h> 38 #include <linux/mii.h> 39 #include <linux/ethtool.h> 40 #include <linux/if.h> 41 #include <linux/if_vlan.h> 42 #include <linux/pci.h> 43 #include <linux/pci-aspm.h> 44 #include <linux/delay.h> 45 #include <linux/interrupt.h> 46 #include <linux/ip.h> 47 #include <linux/tcp.h> 48 #include <linux/sctp.h> 49 #include <linux/if_ether.h> 50 #include <linux/aer.h> 51 #include <linux/prefetch.h> 52 #include <linux/pm_runtime.h> 53 #ifdef CONFIG_IGB_DCA 54 #include <linux/dca.h> 55 #endif 56 #include <linux/i2c.h> 57 #include "igb.h" 58 59 #define MAJ 5 60 #define MIN 2 61 #define BUILD 18 62 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 63 __stringify(BUILD) "-k" 64 char igb_driver_name[] = "igb"; 65 char igb_driver_version[] = DRV_VERSION; 66 static const char igb_driver_string[] = 67 "Intel(R) Gigabit Ethernet Network Driver"; 68 static const char igb_copyright[] = 69 "Copyright (c) 2007-2014 Intel Corporation."; 70 71 static const struct e1000_info *igb_info_tbl[] = { 72 [board_82575] = &e1000_82575_info, 73 }; 74 75 static const struct pci_device_id igb_pci_tbl[] = { 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 111 /* required last entry */ 112 {0, } 113 }; 114 115 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 116 117 static int igb_setup_all_tx_resources(struct igb_adapter *); 118 static int igb_setup_all_rx_resources(struct igb_adapter *); 119 static void igb_free_all_tx_resources(struct igb_adapter *); 120 static void igb_free_all_rx_resources(struct igb_adapter *); 121 static void igb_setup_mrqc(struct igb_adapter *); 122 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 123 static void igb_remove(struct pci_dev *pdev); 124 static int igb_sw_init(struct igb_adapter *); 125 static int igb_open(struct net_device *); 126 static int igb_close(struct net_device *); 127 static void igb_configure(struct igb_adapter *); 128 static void igb_configure_tx(struct igb_adapter *); 129 static void igb_configure_rx(struct igb_adapter *); 130 static void igb_clean_all_tx_rings(struct igb_adapter *); 131 static void igb_clean_all_rx_rings(struct igb_adapter *); 132 static void igb_clean_tx_ring(struct igb_ring *); 133 static void igb_clean_rx_ring(struct igb_ring *); 134 static void igb_set_rx_mode(struct net_device *); 135 static void igb_update_phy_info(unsigned long); 136 static void igb_watchdog(unsigned long); 137 static void igb_watchdog_task(struct work_struct *); 138 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 139 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, 140 struct rtnl_link_stats64 *stats); 141 static int igb_change_mtu(struct net_device *, int); 142 static int igb_set_mac(struct net_device *, void *); 143 static void igb_set_uta(struct igb_adapter *adapter); 144 static irqreturn_t igb_intr(int irq, void *); 145 static irqreturn_t igb_intr_msi(int irq, void *); 146 static irqreturn_t igb_msix_other(int irq, void *); 147 static irqreturn_t igb_msix_ring(int irq, void *); 148 #ifdef CONFIG_IGB_DCA 149 static void igb_update_dca(struct igb_q_vector *); 150 static void igb_setup_dca(struct igb_adapter *); 151 #endif /* CONFIG_IGB_DCA */ 152 static int igb_poll(struct napi_struct *, int); 153 static bool igb_clean_tx_irq(struct igb_q_vector *); 154 static bool igb_clean_rx_irq(struct igb_q_vector *, int); 155 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 156 static void igb_tx_timeout(struct net_device *); 157 static void igb_reset_task(struct work_struct *); 158 static void igb_vlan_mode(struct net_device *netdev, 159 netdev_features_t features); 160 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 161 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 162 static void igb_restore_vlan(struct igb_adapter *); 163 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); 164 static void igb_ping_all_vfs(struct igb_adapter *); 165 static void igb_msg_task(struct igb_adapter *); 166 static void igb_vmm_control(struct igb_adapter *); 167 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 168 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 169 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 170 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 171 int vf, u16 vlan, u8 qos); 172 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 173 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 174 bool setting); 175 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 176 struct ifla_vf_info *ivi); 177 static void igb_check_vf_rate_limit(struct igb_adapter *); 178 179 #ifdef CONFIG_PCI_IOV 180 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 181 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 182 #endif 183 184 #ifdef CONFIG_PM 185 #ifdef CONFIG_PM_SLEEP 186 static int igb_suspend(struct device *); 187 #endif 188 static int igb_resume(struct device *); 189 static int igb_runtime_suspend(struct device *dev); 190 static int igb_runtime_resume(struct device *dev); 191 static int igb_runtime_idle(struct device *dev); 192 static const struct dev_pm_ops igb_pm_ops = { 193 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 194 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 195 igb_runtime_idle) 196 }; 197 #endif 198 static void igb_shutdown(struct pci_dev *); 199 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 200 #ifdef CONFIG_IGB_DCA 201 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 202 static struct notifier_block dca_notifier = { 203 .notifier_call = igb_notify_dca, 204 .next = NULL, 205 .priority = 0 206 }; 207 #endif 208 #ifdef CONFIG_NET_POLL_CONTROLLER 209 /* for netdump / net console */ 210 static void igb_netpoll(struct net_device *); 211 #endif 212 #ifdef CONFIG_PCI_IOV 213 static unsigned int max_vfs; 214 module_param(max_vfs, uint, 0); 215 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 216 #endif /* CONFIG_PCI_IOV */ 217 218 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 219 pci_channel_state_t); 220 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 221 static void igb_io_resume(struct pci_dev *); 222 223 static const struct pci_error_handlers igb_err_handler = { 224 .error_detected = igb_io_error_detected, 225 .slot_reset = igb_io_slot_reset, 226 .resume = igb_io_resume, 227 }; 228 229 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 230 231 static struct pci_driver igb_driver = { 232 .name = igb_driver_name, 233 .id_table = igb_pci_tbl, 234 .probe = igb_probe, 235 .remove = igb_remove, 236 #ifdef CONFIG_PM 237 .driver.pm = &igb_pm_ops, 238 #endif 239 .shutdown = igb_shutdown, 240 .sriov_configure = igb_pci_sriov_configure, 241 .err_handler = &igb_err_handler 242 }; 243 244 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 245 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 246 MODULE_LICENSE("GPL"); 247 MODULE_VERSION(DRV_VERSION); 248 249 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 250 static int debug = -1; 251 module_param(debug, int, 0); 252 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 253 254 struct igb_reg_info { 255 u32 ofs; 256 char *name; 257 }; 258 259 static const struct igb_reg_info igb_reg_info_tbl[] = { 260 261 /* General Registers */ 262 {E1000_CTRL, "CTRL"}, 263 {E1000_STATUS, "STATUS"}, 264 {E1000_CTRL_EXT, "CTRL_EXT"}, 265 266 /* Interrupt Registers */ 267 {E1000_ICR, "ICR"}, 268 269 /* RX Registers */ 270 {E1000_RCTL, "RCTL"}, 271 {E1000_RDLEN(0), "RDLEN"}, 272 {E1000_RDH(0), "RDH"}, 273 {E1000_RDT(0), "RDT"}, 274 {E1000_RXDCTL(0), "RXDCTL"}, 275 {E1000_RDBAL(0), "RDBAL"}, 276 {E1000_RDBAH(0), "RDBAH"}, 277 278 /* TX Registers */ 279 {E1000_TCTL, "TCTL"}, 280 {E1000_TDBAL(0), "TDBAL"}, 281 {E1000_TDBAH(0), "TDBAH"}, 282 {E1000_TDLEN(0), "TDLEN"}, 283 {E1000_TDH(0), "TDH"}, 284 {E1000_TDT(0), "TDT"}, 285 {E1000_TXDCTL(0), "TXDCTL"}, 286 {E1000_TDFH, "TDFH"}, 287 {E1000_TDFT, "TDFT"}, 288 {E1000_TDFHS, "TDFHS"}, 289 {E1000_TDFPC, "TDFPC"}, 290 291 /* List Terminator */ 292 {} 293 }; 294 295 /* igb_regdump - register printout routine */ 296 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 297 { 298 int n = 0; 299 char rname[16]; 300 u32 regs[8]; 301 302 switch (reginfo->ofs) { 303 case E1000_RDLEN(0): 304 for (n = 0; n < 4; n++) 305 regs[n] = rd32(E1000_RDLEN(n)); 306 break; 307 case E1000_RDH(0): 308 for (n = 0; n < 4; n++) 309 regs[n] = rd32(E1000_RDH(n)); 310 break; 311 case E1000_RDT(0): 312 for (n = 0; n < 4; n++) 313 regs[n] = rd32(E1000_RDT(n)); 314 break; 315 case E1000_RXDCTL(0): 316 for (n = 0; n < 4; n++) 317 regs[n] = rd32(E1000_RXDCTL(n)); 318 break; 319 case E1000_RDBAL(0): 320 for (n = 0; n < 4; n++) 321 regs[n] = rd32(E1000_RDBAL(n)); 322 break; 323 case E1000_RDBAH(0): 324 for (n = 0; n < 4; n++) 325 regs[n] = rd32(E1000_RDBAH(n)); 326 break; 327 case E1000_TDBAL(0): 328 for (n = 0; n < 4; n++) 329 regs[n] = rd32(E1000_RDBAL(n)); 330 break; 331 case E1000_TDBAH(0): 332 for (n = 0; n < 4; n++) 333 regs[n] = rd32(E1000_TDBAH(n)); 334 break; 335 case E1000_TDLEN(0): 336 for (n = 0; n < 4; n++) 337 regs[n] = rd32(E1000_TDLEN(n)); 338 break; 339 case E1000_TDH(0): 340 for (n = 0; n < 4; n++) 341 regs[n] = rd32(E1000_TDH(n)); 342 break; 343 case E1000_TDT(0): 344 for (n = 0; n < 4; n++) 345 regs[n] = rd32(E1000_TDT(n)); 346 break; 347 case E1000_TXDCTL(0): 348 for (n = 0; n < 4; n++) 349 regs[n] = rd32(E1000_TXDCTL(n)); 350 break; 351 default: 352 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 353 return; 354 } 355 356 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 357 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 358 regs[2], regs[3]); 359 } 360 361 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 362 static void igb_dump(struct igb_adapter *adapter) 363 { 364 struct net_device *netdev = adapter->netdev; 365 struct e1000_hw *hw = &adapter->hw; 366 struct igb_reg_info *reginfo; 367 struct igb_ring *tx_ring; 368 union e1000_adv_tx_desc *tx_desc; 369 struct my_u0 { u64 a; u64 b; } *u0; 370 struct igb_ring *rx_ring; 371 union e1000_adv_rx_desc *rx_desc; 372 u32 staterr; 373 u16 i, n; 374 375 if (!netif_msg_hw(adapter)) 376 return; 377 378 /* Print netdevice Info */ 379 if (netdev) { 380 dev_info(&adapter->pdev->dev, "Net device Info\n"); 381 pr_info("Device Name state trans_start last_rx\n"); 382 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, 383 netdev->state, netdev->trans_start, netdev->last_rx); 384 } 385 386 /* Print Registers */ 387 dev_info(&adapter->pdev->dev, "Register Dump\n"); 388 pr_info(" Register Name Value\n"); 389 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 390 reginfo->name; reginfo++) { 391 igb_regdump(hw, reginfo); 392 } 393 394 /* Print TX Ring Summary */ 395 if (!netdev || !netif_running(netdev)) 396 goto exit; 397 398 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 399 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 400 for (n = 0; n < adapter->num_tx_queues; n++) { 401 struct igb_tx_buffer *buffer_info; 402 tx_ring = adapter->tx_ring[n]; 403 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 404 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 405 n, tx_ring->next_to_use, tx_ring->next_to_clean, 406 (u64)dma_unmap_addr(buffer_info, dma), 407 dma_unmap_len(buffer_info, len), 408 buffer_info->next_to_watch, 409 (u64)buffer_info->time_stamp); 410 } 411 412 /* Print TX Rings */ 413 if (!netif_msg_tx_done(adapter)) 414 goto rx_ring_summary; 415 416 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 417 418 /* Transmit Descriptor Formats 419 * 420 * Advanced Transmit Descriptor 421 * +--------------------------------------------------------------+ 422 * 0 | Buffer Address [63:0] | 423 * +--------------------------------------------------------------+ 424 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 425 * +--------------------------------------------------------------+ 426 * 63 46 45 40 39 38 36 35 32 31 24 15 0 427 */ 428 429 for (n = 0; n < adapter->num_tx_queues; n++) { 430 tx_ring = adapter->tx_ring[n]; 431 pr_info("------------------------------------\n"); 432 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 433 pr_info("------------------------------------\n"); 434 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 435 436 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 437 const char *next_desc; 438 struct igb_tx_buffer *buffer_info; 439 tx_desc = IGB_TX_DESC(tx_ring, i); 440 buffer_info = &tx_ring->tx_buffer_info[i]; 441 u0 = (struct my_u0 *)tx_desc; 442 if (i == tx_ring->next_to_use && 443 i == tx_ring->next_to_clean) 444 next_desc = " NTC/U"; 445 else if (i == tx_ring->next_to_use) 446 next_desc = " NTU"; 447 else if (i == tx_ring->next_to_clean) 448 next_desc = " NTC"; 449 else 450 next_desc = ""; 451 452 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 453 i, le64_to_cpu(u0->a), 454 le64_to_cpu(u0->b), 455 (u64)dma_unmap_addr(buffer_info, dma), 456 dma_unmap_len(buffer_info, len), 457 buffer_info->next_to_watch, 458 (u64)buffer_info->time_stamp, 459 buffer_info->skb, next_desc); 460 461 if (netif_msg_pktdata(adapter) && buffer_info->skb) 462 print_hex_dump(KERN_INFO, "", 463 DUMP_PREFIX_ADDRESS, 464 16, 1, buffer_info->skb->data, 465 dma_unmap_len(buffer_info, len), 466 true); 467 } 468 } 469 470 /* Print RX Rings Summary */ 471 rx_ring_summary: 472 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 473 pr_info("Queue [NTU] [NTC]\n"); 474 for (n = 0; n < adapter->num_rx_queues; n++) { 475 rx_ring = adapter->rx_ring[n]; 476 pr_info(" %5d %5X %5X\n", 477 n, rx_ring->next_to_use, rx_ring->next_to_clean); 478 } 479 480 /* Print RX Rings */ 481 if (!netif_msg_rx_status(adapter)) 482 goto exit; 483 484 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 485 486 /* Advanced Receive Descriptor (Read) Format 487 * 63 1 0 488 * +-----------------------------------------------------+ 489 * 0 | Packet Buffer Address [63:1] |A0/NSE| 490 * +----------------------------------------------+------+ 491 * 8 | Header Buffer Address [63:1] | DD | 492 * +-----------------------------------------------------+ 493 * 494 * 495 * Advanced Receive Descriptor (Write-Back) Format 496 * 497 * 63 48 47 32 31 30 21 20 17 16 4 3 0 498 * +------------------------------------------------------+ 499 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 500 * | Checksum Ident | | | | Type | Type | 501 * +------------------------------------------------------+ 502 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 503 * +------------------------------------------------------+ 504 * 63 48 47 32 31 20 19 0 505 */ 506 507 for (n = 0; n < adapter->num_rx_queues; n++) { 508 rx_ring = adapter->rx_ring[n]; 509 pr_info("------------------------------------\n"); 510 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 511 pr_info("------------------------------------\n"); 512 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 513 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 514 515 for (i = 0; i < rx_ring->count; i++) { 516 const char *next_desc; 517 struct igb_rx_buffer *buffer_info; 518 buffer_info = &rx_ring->rx_buffer_info[i]; 519 rx_desc = IGB_RX_DESC(rx_ring, i); 520 u0 = (struct my_u0 *)rx_desc; 521 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 522 523 if (i == rx_ring->next_to_use) 524 next_desc = " NTU"; 525 else if (i == rx_ring->next_to_clean) 526 next_desc = " NTC"; 527 else 528 next_desc = ""; 529 530 if (staterr & E1000_RXD_STAT_DD) { 531 /* Descriptor Done */ 532 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 533 "RWB", i, 534 le64_to_cpu(u0->a), 535 le64_to_cpu(u0->b), 536 next_desc); 537 } else { 538 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 539 "R ", i, 540 le64_to_cpu(u0->a), 541 le64_to_cpu(u0->b), 542 (u64)buffer_info->dma, 543 next_desc); 544 545 if (netif_msg_pktdata(adapter) && 546 buffer_info->dma && buffer_info->page) { 547 print_hex_dump(KERN_INFO, "", 548 DUMP_PREFIX_ADDRESS, 549 16, 1, 550 page_address(buffer_info->page) + 551 buffer_info->page_offset, 552 IGB_RX_BUFSZ, true); 553 } 554 } 555 } 556 } 557 558 exit: 559 return; 560 } 561 562 /** 563 * igb_get_i2c_data - Reads the I2C SDA data bit 564 * @hw: pointer to hardware structure 565 * @i2cctl: Current value of I2CCTL register 566 * 567 * Returns the I2C data bit value 568 **/ 569 static int igb_get_i2c_data(void *data) 570 { 571 struct igb_adapter *adapter = (struct igb_adapter *)data; 572 struct e1000_hw *hw = &adapter->hw; 573 s32 i2cctl = rd32(E1000_I2CPARAMS); 574 575 return !!(i2cctl & E1000_I2C_DATA_IN); 576 } 577 578 /** 579 * igb_set_i2c_data - Sets the I2C data bit 580 * @data: pointer to hardware structure 581 * @state: I2C data value (0 or 1) to set 582 * 583 * Sets the I2C data bit 584 **/ 585 static void igb_set_i2c_data(void *data, int state) 586 { 587 struct igb_adapter *adapter = (struct igb_adapter *)data; 588 struct e1000_hw *hw = &adapter->hw; 589 s32 i2cctl = rd32(E1000_I2CPARAMS); 590 591 if (state) 592 i2cctl |= E1000_I2C_DATA_OUT; 593 else 594 i2cctl &= ~E1000_I2C_DATA_OUT; 595 596 i2cctl &= ~E1000_I2C_DATA_OE_N; 597 i2cctl |= E1000_I2C_CLK_OE_N; 598 wr32(E1000_I2CPARAMS, i2cctl); 599 wrfl(); 600 601 } 602 603 /** 604 * igb_set_i2c_clk - Sets the I2C SCL clock 605 * @data: pointer to hardware structure 606 * @state: state to set clock 607 * 608 * Sets the I2C clock line to state 609 **/ 610 static void igb_set_i2c_clk(void *data, int state) 611 { 612 struct igb_adapter *adapter = (struct igb_adapter *)data; 613 struct e1000_hw *hw = &adapter->hw; 614 s32 i2cctl = rd32(E1000_I2CPARAMS); 615 616 if (state) { 617 i2cctl |= E1000_I2C_CLK_OUT; 618 i2cctl &= ~E1000_I2C_CLK_OE_N; 619 } else { 620 i2cctl &= ~E1000_I2C_CLK_OUT; 621 i2cctl &= ~E1000_I2C_CLK_OE_N; 622 } 623 wr32(E1000_I2CPARAMS, i2cctl); 624 wrfl(); 625 } 626 627 /** 628 * igb_get_i2c_clk - Gets the I2C SCL clock state 629 * @data: pointer to hardware structure 630 * 631 * Gets the I2C clock state 632 **/ 633 static int igb_get_i2c_clk(void *data) 634 { 635 struct igb_adapter *adapter = (struct igb_adapter *)data; 636 struct e1000_hw *hw = &adapter->hw; 637 s32 i2cctl = rd32(E1000_I2CPARAMS); 638 639 return !!(i2cctl & E1000_I2C_CLK_IN); 640 } 641 642 static const struct i2c_algo_bit_data igb_i2c_algo = { 643 .setsda = igb_set_i2c_data, 644 .setscl = igb_set_i2c_clk, 645 .getsda = igb_get_i2c_data, 646 .getscl = igb_get_i2c_clk, 647 .udelay = 5, 648 .timeout = 20, 649 }; 650 651 /** 652 * igb_get_hw_dev - return device 653 * @hw: pointer to hardware structure 654 * 655 * used by hardware layer to print debugging information 656 **/ 657 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 658 { 659 struct igb_adapter *adapter = hw->back; 660 return adapter->netdev; 661 } 662 663 /** 664 * igb_init_module - Driver Registration Routine 665 * 666 * igb_init_module is the first routine called when the driver is 667 * loaded. All it does is register with the PCI subsystem. 668 **/ 669 static int __init igb_init_module(void) 670 { 671 int ret; 672 673 pr_info("%s - version %s\n", 674 igb_driver_string, igb_driver_version); 675 pr_info("%s\n", igb_copyright); 676 677 #ifdef CONFIG_IGB_DCA 678 dca_register_notify(&dca_notifier); 679 #endif 680 ret = pci_register_driver(&igb_driver); 681 return ret; 682 } 683 684 module_init(igb_init_module); 685 686 /** 687 * igb_exit_module - Driver Exit Cleanup Routine 688 * 689 * igb_exit_module is called just before the driver is removed 690 * from memory. 691 **/ 692 static void __exit igb_exit_module(void) 693 { 694 #ifdef CONFIG_IGB_DCA 695 dca_unregister_notify(&dca_notifier); 696 #endif 697 pci_unregister_driver(&igb_driver); 698 } 699 700 module_exit(igb_exit_module); 701 702 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 703 /** 704 * igb_cache_ring_register - Descriptor ring to register mapping 705 * @adapter: board private structure to initialize 706 * 707 * Once we know the feature-set enabled for the device, we'll cache 708 * the register offset the descriptor ring is assigned to. 709 **/ 710 static void igb_cache_ring_register(struct igb_adapter *adapter) 711 { 712 int i = 0, j = 0; 713 u32 rbase_offset = adapter->vfs_allocated_count; 714 715 switch (adapter->hw.mac.type) { 716 case e1000_82576: 717 /* The queues are allocated for virtualization such that VF 0 718 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 719 * In order to avoid collision we start at the first free queue 720 * and continue consuming queues in the same sequence 721 */ 722 if (adapter->vfs_allocated_count) { 723 for (; i < adapter->rss_queues; i++) 724 adapter->rx_ring[i]->reg_idx = rbase_offset + 725 Q_IDX_82576(i); 726 } 727 /* Fall through */ 728 case e1000_82575: 729 case e1000_82580: 730 case e1000_i350: 731 case e1000_i354: 732 case e1000_i210: 733 case e1000_i211: 734 /* Fall through */ 735 default: 736 for (; i < adapter->num_rx_queues; i++) 737 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 738 for (; j < adapter->num_tx_queues; j++) 739 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 740 break; 741 } 742 } 743 744 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 745 { 746 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 747 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr); 748 u32 value = 0; 749 750 if (E1000_REMOVED(hw_addr)) 751 return ~value; 752 753 value = readl(&hw_addr[reg]); 754 755 /* reads should not return all F's */ 756 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 757 struct net_device *netdev = igb->netdev; 758 hw->hw_addr = NULL; 759 netif_device_detach(netdev); 760 netdev_err(netdev, "PCIe link lost, device now detached\n"); 761 } 762 763 return value; 764 } 765 766 /** 767 * igb_write_ivar - configure ivar for given MSI-X vector 768 * @hw: pointer to the HW structure 769 * @msix_vector: vector number we are allocating to a given ring 770 * @index: row index of IVAR register to write within IVAR table 771 * @offset: column offset of in IVAR, should be multiple of 8 772 * 773 * This function is intended to handle the writing of the IVAR register 774 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 775 * each containing an cause allocation for an Rx and Tx ring, and a 776 * variable number of rows depending on the number of queues supported. 777 **/ 778 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 779 int index, int offset) 780 { 781 u32 ivar = array_rd32(E1000_IVAR0, index); 782 783 /* clear any bits that are currently set */ 784 ivar &= ~((u32)0xFF << offset); 785 786 /* write vector and valid bit */ 787 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 788 789 array_wr32(E1000_IVAR0, index, ivar); 790 } 791 792 #define IGB_N0_QUEUE -1 793 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 794 { 795 struct igb_adapter *adapter = q_vector->adapter; 796 struct e1000_hw *hw = &adapter->hw; 797 int rx_queue = IGB_N0_QUEUE; 798 int tx_queue = IGB_N0_QUEUE; 799 u32 msixbm = 0; 800 801 if (q_vector->rx.ring) 802 rx_queue = q_vector->rx.ring->reg_idx; 803 if (q_vector->tx.ring) 804 tx_queue = q_vector->tx.ring->reg_idx; 805 806 switch (hw->mac.type) { 807 case e1000_82575: 808 /* The 82575 assigns vectors using a bitmask, which matches the 809 * bitmask for the EICR/EIMS/EIMC registers. To assign one 810 * or more queues to a vector, we write the appropriate bits 811 * into the MSIXBM register for that vector. 812 */ 813 if (rx_queue > IGB_N0_QUEUE) 814 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 815 if (tx_queue > IGB_N0_QUEUE) 816 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 817 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 818 msixbm |= E1000_EIMS_OTHER; 819 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 820 q_vector->eims_value = msixbm; 821 break; 822 case e1000_82576: 823 /* 82576 uses a table that essentially consists of 2 columns 824 * with 8 rows. The ordering is column-major so we use the 825 * lower 3 bits as the row index, and the 4th bit as the 826 * column offset. 827 */ 828 if (rx_queue > IGB_N0_QUEUE) 829 igb_write_ivar(hw, msix_vector, 830 rx_queue & 0x7, 831 (rx_queue & 0x8) << 1); 832 if (tx_queue > IGB_N0_QUEUE) 833 igb_write_ivar(hw, msix_vector, 834 tx_queue & 0x7, 835 ((tx_queue & 0x8) << 1) + 8); 836 q_vector->eims_value = 1 << msix_vector; 837 break; 838 case e1000_82580: 839 case e1000_i350: 840 case e1000_i354: 841 case e1000_i210: 842 case e1000_i211: 843 /* On 82580 and newer adapters the scheme is similar to 82576 844 * however instead of ordering column-major we have things 845 * ordered row-major. So we traverse the table by using 846 * bit 0 as the column offset, and the remaining bits as the 847 * row index. 848 */ 849 if (rx_queue > IGB_N0_QUEUE) 850 igb_write_ivar(hw, msix_vector, 851 rx_queue >> 1, 852 (rx_queue & 0x1) << 4); 853 if (tx_queue > IGB_N0_QUEUE) 854 igb_write_ivar(hw, msix_vector, 855 tx_queue >> 1, 856 ((tx_queue & 0x1) << 4) + 8); 857 q_vector->eims_value = 1 << msix_vector; 858 break; 859 default: 860 BUG(); 861 break; 862 } 863 864 /* add q_vector eims value to global eims_enable_mask */ 865 adapter->eims_enable_mask |= q_vector->eims_value; 866 867 /* configure q_vector to set itr on first interrupt */ 868 q_vector->set_itr = 1; 869 } 870 871 /** 872 * igb_configure_msix - Configure MSI-X hardware 873 * @adapter: board private structure to initialize 874 * 875 * igb_configure_msix sets up the hardware to properly 876 * generate MSI-X interrupts. 877 **/ 878 static void igb_configure_msix(struct igb_adapter *adapter) 879 { 880 u32 tmp; 881 int i, vector = 0; 882 struct e1000_hw *hw = &adapter->hw; 883 884 adapter->eims_enable_mask = 0; 885 886 /* set vector for other causes, i.e. link changes */ 887 switch (hw->mac.type) { 888 case e1000_82575: 889 tmp = rd32(E1000_CTRL_EXT); 890 /* enable MSI-X PBA support*/ 891 tmp |= E1000_CTRL_EXT_PBA_CLR; 892 893 /* Auto-Mask interrupts upon ICR read. */ 894 tmp |= E1000_CTRL_EXT_EIAME; 895 tmp |= E1000_CTRL_EXT_IRCA; 896 897 wr32(E1000_CTRL_EXT, tmp); 898 899 /* enable msix_other interrupt */ 900 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 901 adapter->eims_other = E1000_EIMS_OTHER; 902 903 break; 904 905 case e1000_82576: 906 case e1000_82580: 907 case e1000_i350: 908 case e1000_i354: 909 case e1000_i210: 910 case e1000_i211: 911 /* Turn on MSI-X capability first, or our settings 912 * won't stick. And it will take days to debug. 913 */ 914 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 915 E1000_GPIE_PBA | E1000_GPIE_EIAME | 916 E1000_GPIE_NSICR); 917 918 /* enable msix_other interrupt */ 919 adapter->eims_other = 1 << vector; 920 tmp = (vector++ | E1000_IVAR_VALID) << 8; 921 922 wr32(E1000_IVAR_MISC, tmp); 923 break; 924 default: 925 /* do nothing, since nothing else supports MSI-X */ 926 break; 927 } /* switch (hw->mac.type) */ 928 929 adapter->eims_enable_mask |= adapter->eims_other; 930 931 for (i = 0; i < adapter->num_q_vectors; i++) 932 igb_assign_vector(adapter->q_vector[i], vector++); 933 934 wrfl(); 935 } 936 937 /** 938 * igb_request_msix - Initialize MSI-X interrupts 939 * @adapter: board private structure to initialize 940 * 941 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 942 * kernel. 943 **/ 944 static int igb_request_msix(struct igb_adapter *adapter) 945 { 946 struct net_device *netdev = adapter->netdev; 947 struct e1000_hw *hw = &adapter->hw; 948 int i, err = 0, vector = 0, free_vector = 0; 949 950 err = request_irq(adapter->msix_entries[vector].vector, 951 igb_msix_other, 0, netdev->name, adapter); 952 if (err) 953 goto err_out; 954 955 for (i = 0; i < adapter->num_q_vectors; i++) { 956 struct igb_q_vector *q_vector = adapter->q_vector[i]; 957 958 vector++; 959 960 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); 961 962 if (q_vector->rx.ring && q_vector->tx.ring) 963 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 964 q_vector->rx.ring->queue_index); 965 else if (q_vector->tx.ring) 966 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 967 q_vector->tx.ring->queue_index); 968 else if (q_vector->rx.ring) 969 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 970 q_vector->rx.ring->queue_index); 971 else 972 sprintf(q_vector->name, "%s-unused", netdev->name); 973 974 err = request_irq(adapter->msix_entries[vector].vector, 975 igb_msix_ring, 0, q_vector->name, 976 q_vector); 977 if (err) 978 goto err_free; 979 } 980 981 igb_configure_msix(adapter); 982 return 0; 983 984 err_free: 985 /* free already assigned IRQs */ 986 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 987 988 vector--; 989 for (i = 0; i < vector; i++) { 990 free_irq(adapter->msix_entries[free_vector++].vector, 991 adapter->q_vector[i]); 992 } 993 err_out: 994 return err; 995 } 996 997 /** 998 * igb_free_q_vector - Free memory allocated for specific interrupt vector 999 * @adapter: board private structure to initialize 1000 * @v_idx: Index of vector to be freed 1001 * 1002 * This function frees the memory allocated to the q_vector. 1003 **/ 1004 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 1005 { 1006 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1007 1008 adapter->q_vector[v_idx] = NULL; 1009 1010 /* igb_get_stats64() might access the rings on this vector, 1011 * we must wait a grace period before freeing it. 1012 */ 1013 if (q_vector) 1014 kfree_rcu(q_vector, rcu); 1015 } 1016 1017 /** 1018 * igb_reset_q_vector - Reset config for interrupt vector 1019 * @adapter: board private structure to initialize 1020 * @v_idx: Index of vector to be reset 1021 * 1022 * If NAPI is enabled it will delete any references to the 1023 * NAPI struct. This is preparation for igb_free_q_vector. 1024 **/ 1025 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1026 { 1027 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1028 1029 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1030 * allocated. So, q_vector is NULL so we should stop here. 1031 */ 1032 if (!q_vector) 1033 return; 1034 1035 if (q_vector->tx.ring) 1036 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1037 1038 if (q_vector->rx.ring) 1039 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1040 1041 netif_napi_del(&q_vector->napi); 1042 1043 } 1044 1045 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1046 { 1047 int v_idx = adapter->num_q_vectors; 1048 1049 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1050 pci_disable_msix(adapter->pdev); 1051 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1052 pci_disable_msi(adapter->pdev); 1053 1054 while (v_idx--) 1055 igb_reset_q_vector(adapter, v_idx); 1056 } 1057 1058 /** 1059 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1060 * @adapter: board private structure to initialize 1061 * 1062 * This function frees the memory allocated to the q_vectors. In addition if 1063 * NAPI is enabled it will delete any references to the NAPI struct prior 1064 * to freeing the q_vector. 1065 **/ 1066 static void igb_free_q_vectors(struct igb_adapter *adapter) 1067 { 1068 int v_idx = adapter->num_q_vectors; 1069 1070 adapter->num_tx_queues = 0; 1071 adapter->num_rx_queues = 0; 1072 adapter->num_q_vectors = 0; 1073 1074 while (v_idx--) { 1075 igb_reset_q_vector(adapter, v_idx); 1076 igb_free_q_vector(adapter, v_idx); 1077 } 1078 } 1079 1080 /** 1081 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1082 * @adapter: board private structure to initialize 1083 * 1084 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1085 * MSI-X interrupts allocated. 1086 */ 1087 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1088 { 1089 igb_free_q_vectors(adapter); 1090 igb_reset_interrupt_capability(adapter); 1091 } 1092 1093 /** 1094 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1095 * @adapter: board private structure to initialize 1096 * @msix: boolean value of MSIX capability 1097 * 1098 * Attempt to configure interrupts using the best available 1099 * capabilities of the hardware and kernel. 1100 **/ 1101 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1102 { 1103 int err; 1104 int numvecs, i; 1105 1106 if (!msix) 1107 goto msi_only; 1108 adapter->flags |= IGB_FLAG_HAS_MSIX; 1109 1110 /* Number of supported queues. */ 1111 adapter->num_rx_queues = adapter->rss_queues; 1112 if (adapter->vfs_allocated_count) 1113 adapter->num_tx_queues = 1; 1114 else 1115 adapter->num_tx_queues = adapter->rss_queues; 1116 1117 /* start with one vector for every Rx queue */ 1118 numvecs = adapter->num_rx_queues; 1119 1120 /* if Tx handler is separate add 1 for every Tx queue */ 1121 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1122 numvecs += adapter->num_tx_queues; 1123 1124 /* store the number of vectors reserved for queues */ 1125 adapter->num_q_vectors = numvecs; 1126 1127 /* add 1 vector for link status interrupts */ 1128 numvecs++; 1129 for (i = 0; i < numvecs; i++) 1130 adapter->msix_entries[i].entry = i; 1131 1132 err = pci_enable_msix_range(adapter->pdev, 1133 adapter->msix_entries, 1134 numvecs, 1135 numvecs); 1136 if (err > 0) 1137 return; 1138 1139 igb_reset_interrupt_capability(adapter); 1140 1141 /* If we can't do MSI-X, try MSI */ 1142 msi_only: 1143 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1144 #ifdef CONFIG_PCI_IOV 1145 /* disable SR-IOV for non MSI-X configurations */ 1146 if (adapter->vf_data) { 1147 struct e1000_hw *hw = &adapter->hw; 1148 /* disable iov and allow time for transactions to clear */ 1149 pci_disable_sriov(adapter->pdev); 1150 msleep(500); 1151 1152 kfree(adapter->vf_data); 1153 adapter->vf_data = NULL; 1154 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1155 wrfl(); 1156 msleep(100); 1157 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1158 } 1159 #endif 1160 adapter->vfs_allocated_count = 0; 1161 adapter->rss_queues = 1; 1162 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1163 adapter->num_rx_queues = 1; 1164 adapter->num_tx_queues = 1; 1165 adapter->num_q_vectors = 1; 1166 if (!pci_enable_msi(adapter->pdev)) 1167 adapter->flags |= IGB_FLAG_HAS_MSI; 1168 } 1169 1170 static void igb_add_ring(struct igb_ring *ring, 1171 struct igb_ring_container *head) 1172 { 1173 head->ring = ring; 1174 head->count++; 1175 } 1176 1177 /** 1178 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1179 * @adapter: board private structure to initialize 1180 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1181 * @v_idx: index of vector in adapter struct 1182 * @txr_count: total number of Tx rings to allocate 1183 * @txr_idx: index of first Tx ring to allocate 1184 * @rxr_count: total number of Rx rings to allocate 1185 * @rxr_idx: index of first Rx ring to allocate 1186 * 1187 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1188 **/ 1189 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1190 int v_count, int v_idx, 1191 int txr_count, int txr_idx, 1192 int rxr_count, int rxr_idx) 1193 { 1194 struct igb_q_vector *q_vector; 1195 struct igb_ring *ring; 1196 int ring_count, size; 1197 1198 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1199 if (txr_count > 1 || rxr_count > 1) 1200 return -ENOMEM; 1201 1202 ring_count = txr_count + rxr_count; 1203 size = sizeof(struct igb_q_vector) + 1204 (sizeof(struct igb_ring) * ring_count); 1205 1206 /* allocate q_vector and rings */ 1207 q_vector = adapter->q_vector[v_idx]; 1208 if (!q_vector) 1209 q_vector = kzalloc(size, GFP_KERNEL); 1210 else 1211 memset(q_vector, 0, size); 1212 if (!q_vector) 1213 return -ENOMEM; 1214 1215 /* initialize NAPI */ 1216 netif_napi_add(adapter->netdev, &q_vector->napi, 1217 igb_poll, 64); 1218 1219 /* tie q_vector and adapter together */ 1220 adapter->q_vector[v_idx] = q_vector; 1221 q_vector->adapter = adapter; 1222 1223 /* initialize work limits */ 1224 q_vector->tx.work_limit = adapter->tx_work_limit; 1225 1226 /* initialize ITR configuration */ 1227 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0); 1228 q_vector->itr_val = IGB_START_ITR; 1229 1230 /* initialize pointer to rings */ 1231 ring = q_vector->ring; 1232 1233 /* intialize ITR */ 1234 if (rxr_count) { 1235 /* rx or rx/tx vector */ 1236 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1237 q_vector->itr_val = adapter->rx_itr_setting; 1238 } else { 1239 /* tx only vector */ 1240 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1241 q_vector->itr_val = adapter->tx_itr_setting; 1242 } 1243 1244 if (txr_count) { 1245 /* assign generic ring traits */ 1246 ring->dev = &adapter->pdev->dev; 1247 ring->netdev = adapter->netdev; 1248 1249 /* configure backlink on ring */ 1250 ring->q_vector = q_vector; 1251 1252 /* update q_vector Tx values */ 1253 igb_add_ring(ring, &q_vector->tx); 1254 1255 /* For 82575, context index must be unique per ring. */ 1256 if (adapter->hw.mac.type == e1000_82575) 1257 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1258 1259 /* apply Tx specific ring traits */ 1260 ring->count = adapter->tx_ring_count; 1261 ring->queue_index = txr_idx; 1262 1263 u64_stats_init(&ring->tx_syncp); 1264 u64_stats_init(&ring->tx_syncp2); 1265 1266 /* assign ring to adapter */ 1267 adapter->tx_ring[txr_idx] = ring; 1268 1269 /* push pointer to next ring */ 1270 ring++; 1271 } 1272 1273 if (rxr_count) { 1274 /* assign generic ring traits */ 1275 ring->dev = &adapter->pdev->dev; 1276 ring->netdev = adapter->netdev; 1277 1278 /* configure backlink on ring */ 1279 ring->q_vector = q_vector; 1280 1281 /* update q_vector Rx values */ 1282 igb_add_ring(ring, &q_vector->rx); 1283 1284 /* set flag indicating ring supports SCTP checksum offload */ 1285 if (adapter->hw.mac.type >= e1000_82576) 1286 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1287 1288 /* On i350, i354, i210, and i211, loopback VLAN packets 1289 * have the tag byte-swapped. 1290 */ 1291 if (adapter->hw.mac.type >= e1000_i350) 1292 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1293 1294 /* apply Rx specific ring traits */ 1295 ring->count = adapter->rx_ring_count; 1296 ring->queue_index = rxr_idx; 1297 1298 u64_stats_init(&ring->rx_syncp); 1299 1300 /* assign ring to adapter */ 1301 adapter->rx_ring[rxr_idx] = ring; 1302 } 1303 1304 return 0; 1305 } 1306 1307 1308 /** 1309 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1310 * @adapter: board private structure to initialize 1311 * 1312 * We allocate one q_vector per queue interrupt. If allocation fails we 1313 * return -ENOMEM. 1314 **/ 1315 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1316 { 1317 int q_vectors = adapter->num_q_vectors; 1318 int rxr_remaining = adapter->num_rx_queues; 1319 int txr_remaining = adapter->num_tx_queues; 1320 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1321 int err; 1322 1323 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1324 for (; rxr_remaining; v_idx++) { 1325 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1326 0, 0, 1, rxr_idx); 1327 1328 if (err) 1329 goto err_out; 1330 1331 /* update counts and index */ 1332 rxr_remaining--; 1333 rxr_idx++; 1334 } 1335 } 1336 1337 for (; v_idx < q_vectors; v_idx++) { 1338 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1339 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1340 1341 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1342 tqpv, txr_idx, rqpv, rxr_idx); 1343 1344 if (err) 1345 goto err_out; 1346 1347 /* update counts and index */ 1348 rxr_remaining -= rqpv; 1349 txr_remaining -= tqpv; 1350 rxr_idx++; 1351 txr_idx++; 1352 } 1353 1354 return 0; 1355 1356 err_out: 1357 adapter->num_tx_queues = 0; 1358 adapter->num_rx_queues = 0; 1359 adapter->num_q_vectors = 0; 1360 1361 while (v_idx--) 1362 igb_free_q_vector(adapter, v_idx); 1363 1364 return -ENOMEM; 1365 } 1366 1367 /** 1368 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1369 * @adapter: board private structure to initialize 1370 * @msix: boolean value of MSIX capability 1371 * 1372 * This function initializes the interrupts and allocates all of the queues. 1373 **/ 1374 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1375 { 1376 struct pci_dev *pdev = adapter->pdev; 1377 int err; 1378 1379 igb_set_interrupt_capability(adapter, msix); 1380 1381 err = igb_alloc_q_vectors(adapter); 1382 if (err) { 1383 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1384 goto err_alloc_q_vectors; 1385 } 1386 1387 igb_cache_ring_register(adapter); 1388 1389 return 0; 1390 1391 err_alloc_q_vectors: 1392 igb_reset_interrupt_capability(adapter); 1393 return err; 1394 } 1395 1396 /** 1397 * igb_request_irq - initialize interrupts 1398 * @adapter: board private structure to initialize 1399 * 1400 * Attempts to configure interrupts using the best available 1401 * capabilities of the hardware and kernel. 1402 **/ 1403 static int igb_request_irq(struct igb_adapter *adapter) 1404 { 1405 struct net_device *netdev = adapter->netdev; 1406 struct pci_dev *pdev = adapter->pdev; 1407 int err = 0; 1408 1409 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1410 err = igb_request_msix(adapter); 1411 if (!err) 1412 goto request_done; 1413 /* fall back to MSI */ 1414 igb_free_all_tx_resources(adapter); 1415 igb_free_all_rx_resources(adapter); 1416 1417 igb_clear_interrupt_scheme(adapter); 1418 err = igb_init_interrupt_scheme(adapter, false); 1419 if (err) 1420 goto request_done; 1421 1422 igb_setup_all_tx_resources(adapter); 1423 igb_setup_all_rx_resources(adapter); 1424 igb_configure(adapter); 1425 } 1426 1427 igb_assign_vector(adapter->q_vector[0], 0); 1428 1429 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1430 err = request_irq(pdev->irq, igb_intr_msi, 0, 1431 netdev->name, adapter); 1432 if (!err) 1433 goto request_done; 1434 1435 /* fall back to legacy interrupts */ 1436 igb_reset_interrupt_capability(adapter); 1437 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1438 } 1439 1440 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1441 netdev->name, adapter); 1442 1443 if (err) 1444 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1445 err); 1446 1447 request_done: 1448 return err; 1449 } 1450 1451 static void igb_free_irq(struct igb_adapter *adapter) 1452 { 1453 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1454 int vector = 0, i; 1455 1456 free_irq(adapter->msix_entries[vector++].vector, adapter); 1457 1458 for (i = 0; i < adapter->num_q_vectors; i++) 1459 free_irq(adapter->msix_entries[vector++].vector, 1460 adapter->q_vector[i]); 1461 } else { 1462 free_irq(adapter->pdev->irq, adapter); 1463 } 1464 } 1465 1466 /** 1467 * igb_irq_disable - Mask off interrupt generation on the NIC 1468 * @adapter: board private structure 1469 **/ 1470 static void igb_irq_disable(struct igb_adapter *adapter) 1471 { 1472 struct e1000_hw *hw = &adapter->hw; 1473 1474 /* we need to be careful when disabling interrupts. The VFs are also 1475 * mapped into these registers and so clearing the bits can cause 1476 * issues on the VF drivers so we only need to clear what we set 1477 */ 1478 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1479 u32 regval = rd32(E1000_EIAM); 1480 1481 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1482 wr32(E1000_EIMC, adapter->eims_enable_mask); 1483 regval = rd32(E1000_EIAC); 1484 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1485 } 1486 1487 wr32(E1000_IAM, 0); 1488 wr32(E1000_IMC, ~0); 1489 wrfl(); 1490 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1491 int i; 1492 1493 for (i = 0; i < adapter->num_q_vectors; i++) 1494 synchronize_irq(adapter->msix_entries[i].vector); 1495 } else { 1496 synchronize_irq(adapter->pdev->irq); 1497 } 1498 } 1499 1500 /** 1501 * igb_irq_enable - Enable default interrupt generation settings 1502 * @adapter: board private structure 1503 **/ 1504 static void igb_irq_enable(struct igb_adapter *adapter) 1505 { 1506 struct e1000_hw *hw = &adapter->hw; 1507 1508 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1509 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1510 u32 regval = rd32(E1000_EIAC); 1511 1512 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1513 regval = rd32(E1000_EIAM); 1514 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1515 wr32(E1000_EIMS, adapter->eims_enable_mask); 1516 if (adapter->vfs_allocated_count) { 1517 wr32(E1000_MBVFIMR, 0xFF); 1518 ims |= E1000_IMS_VMMB; 1519 } 1520 wr32(E1000_IMS, ims); 1521 } else { 1522 wr32(E1000_IMS, IMS_ENABLE_MASK | 1523 E1000_IMS_DRSTA); 1524 wr32(E1000_IAM, IMS_ENABLE_MASK | 1525 E1000_IMS_DRSTA); 1526 } 1527 } 1528 1529 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1530 { 1531 struct e1000_hw *hw = &adapter->hw; 1532 u16 vid = adapter->hw.mng_cookie.vlan_id; 1533 u16 old_vid = adapter->mng_vlan_id; 1534 1535 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1536 /* add VID to filter table */ 1537 igb_vfta_set(hw, vid, true); 1538 adapter->mng_vlan_id = vid; 1539 } else { 1540 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1541 } 1542 1543 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1544 (vid != old_vid) && 1545 !test_bit(old_vid, adapter->active_vlans)) { 1546 /* remove VID from filter table */ 1547 igb_vfta_set(hw, old_vid, false); 1548 } 1549 } 1550 1551 /** 1552 * igb_release_hw_control - release control of the h/w to f/w 1553 * @adapter: address of board private structure 1554 * 1555 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1556 * For ASF and Pass Through versions of f/w this means that the 1557 * driver is no longer loaded. 1558 **/ 1559 static void igb_release_hw_control(struct igb_adapter *adapter) 1560 { 1561 struct e1000_hw *hw = &adapter->hw; 1562 u32 ctrl_ext; 1563 1564 /* Let firmware take over control of h/w */ 1565 ctrl_ext = rd32(E1000_CTRL_EXT); 1566 wr32(E1000_CTRL_EXT, 1567 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1568 } 1569 1570 /** 1571 * igb_get_hw_control - get control of the h/w from f/w 1572 * @adapter: address of board private structure 1573 * 1574 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1575 * For ASF and Pass Through versions of f/w this means that 1576 * the driver is loaded. 1577 **/ 1578 static void igb_get_hw_control(struct igb_adapter *adapter) 1579 { 1580 struct e1000_hw *hw = &adapter->hw; 1581 u32 ctrl_ext; 1582 1583 /* Let firmware know the driver has taken over */ 1584 ctrl_ext = rd32(E1000_CTRL_EXT); 1585 wr32(E1000_CTRL_EXT, 1586 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1587 } 1588 1589 /** 1590 * igb_configure - configure the hardware for RX and TX 1591 * @adapter: private board structure 1592 **/ 1593 static void igb_configure(struct igb_adapter *adapter) 1594 { 1595 struct net_device *netdev = adapter->netdev; 1596 int i; 1597 1598 igb_get_hw_control(adapter); 1599 igb_set_rx_mode(netdev); 1600 1601 igb_restore_vlan(adapter); 1602 1603 igb_setup_tctl(adapter); 1604 igb_setup_mrqc(adapter); 1605 igb_setup_rctl(adapter); 1606 1607 igb_configure_tx(adapter); 1608 igb_configure_rx(adapter); 1609 1610 igb_rx_fifo_flush_82575(&adapter->hw); 1611 1612 /* call igb_desc_unused which always leaves 1613 * at least 1 descriptor unused to make sure 1614 * next_to_use != next_to_clean 1615 */ 1616 for (i = 0; i < adapter->num_rx_queues; i++) { 1617 struct igb_ring *ring = adapter->rx_ring[i]; 1618 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1619 } 1620 } 1621 1622 /** 1623 * igb_power_up_link - Power up the phy/serdes link 1624 * @adapter: address of board private structure 1625 **/ 1626 void igb_power_up_link(struct igb_adapter *adapter) 1627 { 1628 igb_reset_phy(&adapter->hw); 1629 1630 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1631 igb_power_up_phy_copper(&adapter->hw); 1632 else 1633 igb_power_up_serdes_link_82575(&adapter->hw); 1634 1635 igb_setup_link(&adapter->hw); 1636 } 1637 1638 /** 1639 * igb_power_down_link - Power down the phy/serdes link 1640 * @adapter: address of board private structure 1641 */ 1642 static void igb_power_down_link(struct igb_adapter *adapter) 1643 { 1644 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1645 igb_power_down_phy_copper_82575(&adapter->hw); 1646 else 1647 igb_shutdown_serdes_link_82575(&adapter->hw); 1648 } 1649 1650 /** 1651 * Detect and switch function for Media Auto Sense 1652 * @adapter: address of the board private structure 1653 **/ 1654 static void igb_check_swap_media(struct igb_adapter *adapter) 1655 { 1656 struct e1000_hw *hw = &adapter->hw; 1657 u32 ctrl_ext, connsw; 1658 bool swap_now = false; 1659 1660 ctrl_ext = rd32(E1000_CTRL_EXT); 1661 connsw = rd32(E1000_CONNSW); 1662 1663 /* need to live swap if current media is copper and we have fiber/serdes 1664 * to go to. 1665 */ 1666 1667 if ((hw->phy.media_type == e1000_media_type_copper) && 1668 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 1669 swap_now = true; 1670 } else if (!(connsw & E1000_CONNSW_SERDESD)) { 1671 /* copper signal takes time to appear */ 1672 if (adapter->copper_tries < 4) { 1673 adapter->copper_tries++; 1674 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 1675 wr32(E1000_CONNSW, connsw); 1676 return; 1677 } else { 1678 adapter->copper_tries = 0; 1679 if ((connsw & E1000_CONNSW_PHYSD) && 1680 (!(connsw & E1000_CONNSW_PHY_PDN))) { 1681 swap_now = true; 1682 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 1683 wr32(E1000_CONNSW, connsw); 1684 } 1685 } 1686 } 1687 1688 if (!swap_now) 1689 return; 1690 1691 switch (hw->phy.media_type) { 1692 case e1000_media_type_copper: 1693 netdev_info(adapter->netdev, 1694 "MAS: changing media to fiber/serdes\n"); 1695 ctrl_ext |= 1696 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1697 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1698 adapter->copper_tries = 0; 1699 break; 1700 case e1000_media_type_internal_serdes: 1701 case e1000_media_type_fiber: 1702 netdev_info(adapter->netdev, 1703 "MAS: changing media to copper\n"); 1704 ctrl_ext &= 1705 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1706 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1707 break; 1708 default: 1709 /* shouldn't get here during regular operation */ 1710 netdev_err(adapter->netdev, 1711 "AMS: Invalid media type found, returning\n"); 1712 break; 1713 } 1714 wr32(E1000_CTRL_EXT, ctrl_ext); 1715 } 1716 1717 /** 1718 * igb_up - Open the interface and prepare it to handle traffic 1719 * @adapter: board private structure 1720 **/ 1721 int igb_up(struct igb_adapter *adapter) 1722 { 1723 struct e1000_hw *hw = &adapter->hw; 1724 int i; 1725 1726 /* hardware has been reset, we need to reload some things */ 1727 igb_configure(adapter); 1728 1729 clear_bit(__IGB_DOWN, &adapter->state); 1730 1731 for (i = 0; i < adapter->num_q_vectors; i++) 1732 napi_enable(&(adapter->q_vector[i]->napi)); 1733 1734 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1735 igb_configure_msix(adapter); 1736 else 1737 igb_assign_vector(adapter->q_vector[0], 0); 1738 1739 /* Clear any pending interrupts. */ 1740 rd32(E1000_ICR); 1741 igb_irq_enable(adapter); 1742 1743 /* notify VFs that reset has been completed */ 1744 if (adapter->vfs_allocated_count) { 1745 u32 reg_data = rd32(E1000_CTRL_EXT); 1746 1747 reg_data |= E1000_CTRL_EXT_PFRSTD; 1748 wr32(E1000_CTRL_EXT, reg_data); 1749 } 1750 1751 netif_tx_start_all_queues(adapter->netdev); 1752 1753 /* start the watchdog. */ 1754 hw->mac.get_link_status = 1; 1755 schedule_work(&adapter->watchdog_task); 1756 1757 if ((adapter->flags & IGB_FLAG_EEE) && 1758 (!hw->dev_spec._82575.eee_disable)) 1759 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 1760 1761 return 0; 1762 } 1763 1764 void igb_down(struct igb_adapter *adapter) 1765 { 1766 struct net_device *netdev = adapter->netdev; 1767 struct e1000_hw *hw = &adapter->hw; 1768 u32 tctl, rctl; 1769 int i; 1770 1771 /* signal that we're down so the interrupt handler does not 1772 * reschedule our watchdog timer 1773 */ 1774 set_bit(__IGB_DOWN, &adapter->state); 1775 1776 /* disable receives in the hardware */ 1777 rctl = rd32(E1000_RCTL); 1778 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 1779 /* flush and sleep below */ 1780 1781 netif_carrier_off(netdev); 1782 netif_tx_stop_all_queues(netdev); 1783 1784 /* disable transmits in the hardware */ 1785 tctl = rd32(E1000_TCTL); 1786 tctl &= ~E1000_TCTL_EN; 1787 wr32(E1000_TCTL, tctl); 1788 /* flush both disables and wait for them to finish */ 1789 wrfl(); 1790 usleep_range(10000, 11000); 1791 1792 igb_irq_disable(adapter); 1793 1794 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 1795 1796 for (i = 0; i < adapter->num_q_vectors; i++) { 1797 if (adapter->q_vector[i]) { 1798 napi_synchronize(&adapter->q_vector[i]->napi); 1799 napi_disable(&adapter->q_vector[i]->napi); 1800 } 1801 } 1802 1803 del_timer_sync(&adapter->watchdog_timer); 1804 del_timer_sync(&adapter->phy_info_timer); 1805 1806 /* record the stats before reset*/ 1807 spin_lock(&adapter->stats64_lock); 1808 igb_update_stats(adapter, &adapter->stats64); 1809 spin_unlock(&adapter->stats64_lock); 1810 1811 adapter->link_speed = 0; 1812 adapter->link_duplex = 0; 1813 1814 if (!pci_channel_offline(adapter->pdev)) 1815 igb_reset(adapter); 1816 igb_clean_all_tx_rings(adapter); 1817 igb_clean_all_rx_rings(adapter); 1818 #ifdef CONFIG_IGB_DCA 1819 1820 /* since we reset the hardware DCA settings were cleared */ 1821 igb_setup_dca(adapter); 1822 #endif 1823 } 1824 1825 void igb_reinit_locked(struct igb_adapter *adapter) 1826 { 1827 WARN_ON(in_interrupt()); 1828 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 1829 usleep_range(1000, 2000); 1830 igb_down(adapter); 1831 igb_up(adapter); 1832 clear_bit(__IGB_RESETTING, &adapter->state); 1833 } 1834 1835 /** igb_enable_mas - Media Autosense re-enable after swap 1836 * 1837 * @adapter: adapter struct 1838 **/ 1839 static void igb_enable_mas(struct igb_adapter *adapter) 1840 { 1841 struct e1000_hw *hw = &adapter->hw; 1842 u32 connsw = rd32(E1000_CONNSW); 1843 1844 /* configure for SerDes media detect */ 1845 if ((hw->phy.media_type == e1000_media_type_copper) && 1846 (!(connsw & E1000_CONNSW_SERDESD))) { 1847 connsw |= E1000_CONNSW_ENRGSRC; 1848 connsw |= E1000_CONNSW_AUTOSENSE_EN; 1849 wr32(E1000_CONNSW, connsw); 1850 wrfl(); 1851 } 1852 } 1853 1854 void igb_reset(struct igb_adapter *adapter) 1855 { 1856 struct pci_dev *pdev = adapter->pdev; 1857 struct e1000_hw *hw = &adapter->hw; 1858 struct e1000_mac_info *mac = &hw->mac; 1859 struct e1000_fc_info *fc = &hw->fc; 1860 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm; 1861 1862 /* Repartition Pba for greater than 9k mtu 1863 * To take effect CTRL.RST is required. 1864 */ 1865 switch (mac->type) { 1866 case e1000_i350: 1867 case e1000_i354: 1868 case e1000_82580: 1869 pba = rd32(E1000_RXPBS); 1870 pba = igb_rxpbs_adjust_82580(pba); 1871 break; 1872 case e1000_82576: 1873 pba = rd32(E1000_RXPBS); 1874 pba &= E1000_RXPBS_SIZE_MASK_82576; 1875 break; 1876 case e1000_82575: 1877 case e1000_i210: 1878 case e1000_i211: 1879 default: 1880 pba = E1000_PBA_34K; 1881 break; 1882 } 1883 1884 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && 1885 (mac->type < e1000_82576)) { 1886 /* adjust PBA for jumbo frames */ 1887 wr32(E1000_PBA, pba); 1888 1889 /* To maintain wire speed transmits, the Tx FIFO should be 1890 * large enough to accommodate two full transmit packets, 1891 * rounded up to the next 1KB and expressed in KB. Likewise, 1892 * the Rx FIFO should be large enough to accommodate at least 1893 * one full receive packet and is similarly rounded up and 1894 * expressed in KB. 1895 */ 1896 pba = rd32(E1000_PBA); 1897 /* upper 16 bits has Tx packet buffer allocation size in KB */ 1898 tx_space = pba >> 16; 1899 /* lower 16 bits has Rx packet buffer allocation size in KB */ 1900 pba &= 0xffff; 1901 /* the Tx fifo also stores 16 bytes of information about the Tx 1902 * but don't include ethernet FCS because hardware appends it 1903 */ 1904 min_tx_space = (adapter->max_frame_size + 1905 sizeof(union e1000_adv_tx_desc) - 1906 ETH_FCS_LEN) * 2; 1907 min_tx_space = ALIGN(min_tx_space, 1024); 1908 min_tx_space >>= 10; 1909 /* software strips receive CRC, so leave room for it */ 1910 min_rx_space = adapter->max_frame_size; 1911 min_rx_space = ALIGN(min_rx_space, 1024); 1912 min_rx_space >>= 10; 1913 1914 /* If current Tx allocation is less than the min Tx FIFO size, 1915 * and the min Tx FIFO size is less than the current Rx FIFO 1916 * allocation, take space away from current Rx allocation 1917 */ 1918 if (tx_space < min_tx_space && 1919 ((min_tx_space - tx_space) < pba)) { 1920 pba = pba - (min_tx_space - tx_space); 1921 1922 /* if short on Rx space, Rx wins and must trump Tx 1923 * adjustment 1924 */ 1925 if (pba < min_rx_space) 1926 pba = min_rx_space; 1927 } 1928 wr32(E1000_PBA, pba); 1929 } 1930 1931 /* flow control settings */ 1932 /* The high water mark must be low enough to fit one full frame 1933 * (or the size used for early receive) above it in the Rx FIFO. 1934 * Set it to the lower of: 1935 * - 90% of the Rx FIFO size, or 1936 * - the full Rx FIFO size minus one full frame 1937 */ 1938 hwm = min(((pba << 10) * 9 / 10), 1939 ((pba << 10) - 2 * adapter->max_frame_size)); 1940 1941 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 1942 fc->low_water = fc->high_water - 16; 1943 fc->pause_time = 0xFFFF; 1944 fc->send_xon = 1; 1945 fc->current_mode = fc->requested_mode; 1946 1947 /* disable receive for all VFs and wait one second */ 1948 if (adapter->vfs_allocated_count) { 1949 int i; 1950 1951 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 1952 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 1953 1954 /* ping all the active vfs to let them know we are going down */ 1955 igb_ping_all_vfs(adapter); 1956 1957 /* disable transmits and receives */ 1958 wr32(E1000_VFRE, 0); 1959 wr32(E1000_VFTE, 0); 1960 } 1961 1962 /* Allow time for pending master requests to run */ 1963 hw->mac.ops.reset_hw(hw); 1964 wr32(E1000_WUC, 0); 1965 1966 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 1967 /* need to resetup here after media swap */ 1968 adapter->ei.get_invariants(hw); 1969 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 1970 } 1971 if ((mac->type == e1000_82575) && 1972 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 1973 igb_enable_mas(adapter); 1974 } 1975 if (hw->mac.ops.init_hw(hw)) 1976 dev_err(&pdev->dev, "Hardware Error\n"); 1977 1978 /* Flow control settings reset on hardware reset, so guarantee flow 1979 * control is off when forcing speed. 1980 */ 1981 if (!hw->mac.autoneg) 1982 igb_force_mac_fc(hw); 1983 1984 igb_init_dmac(adapter, pba); 1985 #ifdef CONFIG_IGB_HWMON 1986 /* Re-initialize the thermal sensor on i350 devices. */ 1987 if (!test_bit(__IGB_DOWN, &adapter->state)) { 1988 if (mac->type == e1000_i350 && hw->bus.func == 0) { 1989 /* If present, re-initialize the external thermal sensor 1990 * interface. 1991 */ 1992 if (adapter->ets) 1993 mac->ops.init_thermal_sensor_thresh(hw); 1994 } 1995 } 1996 #endif 1997 /* Re-establish EEE setting */ 1998 if (hw->phy.media_type == e1000_media_type_copper) { 1999 switch (mac->type) { 2000 case e1000_i350: 2001 case e1000_i210: 2002 case e1000_i211: 2003 igb_set_eee_i350(hw, true, true); 2004 break; 2005 case e1000_i354: 2006 igb_set_eee_i354(hw, true, true); 2007 break; 2008 default: 2009 break; 2010 } 2011 } 2012 if (!netif_running(adapter->netdev)) 2013 igb_power_down_link(adapter); 2014 2015 igb_update_mng_vlan(adapter); 2016 2017 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2018 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2019 2020 /* Re-enable PTP, where applicable. */ 2021 igb_ptp_reset(adapter); 2022 2023 igb_get_phy_info(hw); 2024 } 2025 2026 static netdev_features_t igb_fix_features(struct net_device *netdev, 2027 netdev_features_t features) 2028 { 2029 /* Since there is no support for separate Rx/Tx vlan accel 2030 * enable/disable make sure Tx flag is always in same state as Rx. 2031 */ 2032 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2033 features |= NETIF_F_HW_VLAN_CTAG_TX; 2034 else 2035 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2036 2037 return features; 2038 } 2039 2040 static int igb_set_features(struct net_device *netdev, 2041 netdev_features_t features) 2042 { 2043 netdev_features_t changed = netdev->features ^ features; 2044 struct igb_adapter *adapter = netdev_priv(netdev); 2045 2046 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2047 igb_vlan_mode(netdev, features); 2048 2049 if (!(changed & NETIF_F_RXALL)) 2050 return 0; 2051 2052 netdev->features = features; 2053 2054 if (netif_running(netdev)) 2055 igb_reinit_locked(adapter); 2056 else 2057 igb_reset(adapter); 2058 2059 return 0; 2060 } 2061 2062 static const struct net_device_ops igb_netdev_ops = { 2063 .ndo_open = igb_open, 2064 .ndo_stop = igb_close, 2065 .ndo_start_xmit = igb_xmit_frame, 2066 .ndo_get_stats64 = igb_get_stats64, 2067 .ndo_set_rx_mode = igb_set_rx_mode, 2068 .ndo_set_mac_address = igb_set_mac, 2069 .ndo_change_mtu = igb_change_mtu, 2070 .ndo_do_ioctl = igb_ioctl, 2071 .ndo_tx_timeout = igb_tx_timeout, 2072 .ndo_validate_addr = eth_validate_addr, 2073 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2074 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2075 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2076 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2077 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 2078 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2079 .ndo_get_vf_config = igb_ndo_get_vf_config, 2080 #ifdef CONFIG_NET_POLL_CONTROLLER 2081 .ndo_poll_controller = igb_netpoll, 2082 #endif 2083 .ndo_fix_features = igb_fix_features, 2084 .ndo_set_features = igb_set_features, 2085 .ndo_features_check = passthru_features_check, 2086 }; 2087 2088 /** 2089 * igb_set_fw_version - Configure version string for ethtool 2090 * @adapter: adapter struct 2091 **/ 2092 void igb_set_fw_version(struct igb_adapter *adapter) 2093 { 2094 struct e1000_hw *hw = &adapter->hw; 2095 struct e1000_fw_version fw; 2096 2097 igb_get_fw_version(hw, &fw); 2098 2099 switch (hw->mac.type) { 2100 case e1000_i210: 2101 case e1000_i211: 2102 if (!(igb_get_flash_presence_i210(hw))) { 2103 snprintf(adapter->fw_version, 2104 sizeof(adapter->fw_version), 2105 "%2d.%2d-%d", 2106 fw.invm_major, fw.invm_minor, 2107 fw.invm_img_type); 2108 break; 2109 } 2110 /* fall through */ 2111 default: 2112 /* if option is rom valid, display its version too */ 2113 if (fw.or_valid) { 2114 snprintf(adapter->fw_version, 2115 sizeof(adapter->fw_version), 2116 "%d.%d, 0x%08x, %d.%d.%d", 2117 fw.eep_major, fw.eep_minor, fw.etrack_id, 2118 fw.or_major, fw.or_build, fw.or_patch); 2119 /* no option rom */ 2120 } else if (fw.etrack_id != 0X0000) { 2121 snprintf(adapter->fw_version, 2122 sizeof(adapter->fw_version), 2123 "%d.%d, 0x%08x", 2124 fw.eep_major, fw.eep_minor, fw.etrack_id); 2125 } else { 2126 snprintf(adapter->fw_version, 2127 sizeof(adapter->fw_version), 2128 "%d.%d.%d", 2129 fw.eep_major, fw.eep_minor, fw.eep_build); 2130 } 2131 break; 2132 } 2133 } 2134 2135 /** 2136 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2137 * 2138 * @adapter: adapter struct 2139 **/ 2140 static void igb_init_mas(struct igb_adapter *adapter) 2141 { 2142 struct e1000_hw *hw = &adapter->hw; 2143 u16 eeprom_data; 2144 2145 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2146 switch (hw->bus.func) { 2147 case E1000_FUNC_0: 2148 if (eeprom_data & IGB_MAS_ENABLE_0) { 2149 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2150 netdev_info(adapter->netdev, 2151 "MAS: Enabling Media Autosense for port %d\n", 2152 hw->bus.func); 2153 } 2154 break; 2155 case E1000_FUNC_1: 2156 if (eeprom_data & IGB_MAS_ENABLE_1) { 2157 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2158 netdev_info(adapter->netdev, 2159 "MAS: Enabling Media Autosense for port %d\n", 2160 hw->bus.func); 2161 } 2162 break; 2163 case E1000_FUNC_2: 2164 if (eeprom_data & IGB_MAS_ENABLE_2) { 2165 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2166 netdev_info(adapter->netdev, 2167 "MAS: Enabling Media Autosense for port %d\n", 2168 hw->bus.func); 2169 } 2170 break; 2171 case E1000_FUNC_3: 2172 if (eeprom_data & IGB_MAS_ENABLE_3) { 2173 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2174 netdev_info(adapter->netdev, 2175 "MAS: Enabling Media Autosense for port %d\n", 2176 hw->bus.func); 2177 } 2178 break; 2179 default: 2180 /* Shouldn't get here */ 2181 netdev_err(adapter->netdev, 2182 "MAS: Invalid port configuration, returning\n"); 2183 break; 2184 } 2185 } 2186 2187 /** 2188 * igb_init_i2c - Init I2C interface 2189 * @adapter: pointer to adapter structure 2190 **/ 2191 static s32 igb_init_i2c(struct igb_adapter *adapter) 2192 { 2193 s32 status = 0; 2194 2195 /* I2C interface supported on i350 devices */ 2196 if (adapter->hw.mac.type != e1000_i350) 2197 return 0; 2198 2199 /* Initialize the i2c bus which is controlled by the registers. 2200 * This bus will use the i2c_algo_bit structue that implements 2201 * the protocol through toggling of the 4 bits in the register. 2202 */ 2203 adapter->i2c_adap.owner = THIS_MODULE; 2204 adapter->i2c_algo = igb_i2c_algo; 2205 adapter->i2c_algo.data = adapter; 2206 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 2207 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 2208 strlcpy(adapter->i2c_adap.name, "igb BB", 2209 sizeof(adapter->i2c_adap.name)); 2210 status = i2c_bit_add_bus(&adapter->i2c_adap); 2211 return status; 2212 } 2213 2214 /** 2215 * igb_probe - Device Initialization Routine 2216 * @pdev: PCI device information struct 2217 * @ent: entry in igb_pci_tbl 2218 * 2219 * Returns 0 on success, negative on failure 2220 * 2221 * igb_probe initializes an adapter identified by a pci_dev structure. 2222 * The OS initialization, configuring of the adapter private structure, 2223 * and a hardware reset occur. 2224 **/ 2225 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2226 { 2227 struct net_device *netdev; 2228 struct igb_adapter *adapter; 2229 struct e1000_hw *hw; 2230 u16 eeprom_data = 0; 2231 s32 ret_val; 2232 static int global_quad_port_a; /* global quad port a indication */ 2233 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 2234 int err, pci_using_dac; 2235 u8 part_str[E1000_PBANUM_LENGTH]; 2236 2237 /* Catch broken hardware that put the wrong VF device ID in 2238 * the PCIe SR-IOV capability. 2239 */ 2240 if (pdev->is_virtfn) { 2241 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 2242 pci_name(pdev), pdev->vendor, pdev->device); 2243 return -EINVAL; 2244 } 2245 2246 err = pci_enable_device_mem(pdev); 2247 if (err) 2248 return err; 2249 2250 pci_using_dac = 0; 2251 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2252 if (!err) { 2253 pci_using_dac = 1; 2254 } else { 2255 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2256 if (err) { 2257 dev_err(&pdev->dev, 2258 "No usable DMA configuration, aborting\n"); 2259 goto err_dma; 2260 } 2261 } 2262 2263 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 2264 IORESOURCE_MEM), 2265 igb_driver_name); 2266 if (err) 2267 goto err_pci_reg; 2268 2269 pci_enable_pcie_error_reporting(pdev); 2270 2271 pci_set_master(pdev); 2272 pci_save_state(pdev); 2273 2274 err = -ENOMEM; 2275 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 2276 IGB_MAX_TX_QUEUES); 2277 if (!netdev) 2278 goto err_alloc_etherdev; 2279 2280 SET_NETDEV_DEV(netdev, &pdev->dev); 2281 2282 pci_set_drvdata(pdev, netdev); 2283 adapter = netdev_priv(netdev); 2284 adapter->netdev = netdev; 2285 adapter->pdev = pdev; 2286 hw = &adapter->hw; 2287 hw->back = adapter; 2288 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2289 2290 err = -EIO; 2291 hw->hw_addr = pci_iomap(pdev, 0, 0); 2292 if (!hw->hw_addr) 2293 goto err_ioremap; 2294 2295 netdev->netdev_ops = &igb_netdev_ops; 2296 igb_set_ethtool_ops(netdev); 2297 netdev->watchdog_timeo = 5 * HZ; 2298 2299 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 2300 2301 netdev->mem_start = pci_resource_start(pdev, 0); 2302 netdev->mem_end = pci_resource_end(pdev, 0); 2303 2304 /* PCI config space info */ 2305 hw->vendor_id = pdev->vendor; 2306 hw->device_id = pdev->device; 2307 hw->revision_id = pdev->revision; 2308 hw->subsystem_vendor_id = pdev->subsystem_vendor; 2309 hw->subsystem_device_id = pdev->subsystem_device; 2310 2311 /* Copy the default MAC, PHY and NVM function pointers */ 2312 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 2313 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 2314 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 2315 /* Initialize skew-specific constants */ 2316 err = ei->get_invariants(hw); 2317 if (err) 2318 goto err_sw_init; 2319 2320 /* setup the private structure */ 2321 err = igb_sw_init(adapter); 2322 if (err) 2323 goto err_sw_init; 2324 2325 igb_get_bus_info_pcie(hw); 2326 2327 hw->phy.autoneg_wait_to_complete = false; 2328 2329 /* Copper options */ 2330 if (hw->phy.media_type == e1000_media_type_copper) { 2331 hw->phy.mdix = AUTO_ALL_MODES; 2332 hw->phy.disable_polarity_correction = false; 2333 hw->phy.ms_type = e1000_ms_hw_default; 2334 } 2335 2336 if (igb_check_reset_block(hw)) 2337 dev_info(&pdev->dev, 2338 "PHY reset is blocked due to SOL/IDER session.\n"); 2339 2340 /* features is initialized to 0 in allocation, it might have bits 2341 * set by igb_sw_init so we should use an or instead of an 2342 * assignment. 2343 */ 2344 netdev->features |= NETIF_F_SG | 2345 NETIF_F_IP_CSUM | 2346 NETIF_F_IPV6_CSUM | 2347 NETIF_F_TSO | 2348 NETIF_F_TSO6 | 2349 NETIF_F_RXHASH | 2350 NETIF_F_RXCSUM | 2351 NETIF_F_HW_VLAN_CTAG_RX | 2352 NETIF_F_HW_VLAN_CTAG_TX; 2353 2354 /* copy netdev features into list of user selectable features */ 2355 netdev->hw_features |= netdev->features; 2356 netdev->hw_features |= NETIF_F_RXALL; 2357 2358 /* set this bit last since it cannot be part of hw_features */ 2359 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2360 2361 netdev->vlan_features |= NETIF_F_TSO | 2362 NETIF_F_TSO6 | 2363 NETIF_F_IP_CSUM | 2364 NETIF_F_IPV6_CSUM | 2365 NETIF_F_SG; 2366 2367 netdev->priv_flags |= IFF_SUPP_NOFCS; 2368 2369 if (pci_using_dac) { 2370 netdev->features |= NETIF_F_HIGHDMA; 2371 netdev->vlan_features |= NETIF_F_HIGHDMA; 2372 } 2373 2374 if (hw->mac.type >= e1000_82576) { 2375 netdev->hw_features |= NETIF_F_SCTP_CSUM; 2376 netdev->features |= NETIF_F_SCTP_CSUM; 2377 } 2378 2379 netdev->priv_flags |= IFF_UNICAST_FLT; 2380 2381 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 2382 2383 /* before reading the NVM, reset the controller to put the device in a 2384 * known good starting state 2385 */ 2386 hw->mac.ops.reset_hw(hw); 2387 2388 /* make sure the NVM is good , i211/i210 parts can have special NVM 2389 * that doesn't contain a checksum 2390 */ 2391 switch (hw->mac.type) { 2392 case e1000_i210: 2393 case e1000_i211: 2394 if (igb_get_flash_presence_i210(hw)) { 2395 if (hw->nvm.ops.validate(hw) < 0) { 2396 dev_err(&pdev->dev, 2397 "The NVM Checksum Is Not Valid\n"); 2398 err = -EIO; 2399 goto err_eeprom; 2400 } 2401 } 2402 break; 2403 default: 2404 if (hw->nvm.ops.validate(hw) < 0) { 2405 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2406 err = -EIO; 2407 goto err_eeprom; 2408 } 2409 break; 2410 } 2411 2412 /* copy the MAC address out of the NVM */ 2413 if (hw->mac.ops.read_mac_addr(hw)) 2414 dev_err(&pdev->dev, "NVM Read Error\n"); 2415 2416 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2417 2418 if (!is_valid_ether_addr(netdev->dev_addr)) { 2419 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2420 err = -EIO; 2421 goto err_eeprom; 2422 } 2423 2424 /* get firmware version for ethtool -i */ 2425 igb_set_fw_version(adapter); 2426 2427 /* configure RXPBSIZE and TXPBSIZE */ 2428 if (hw->mac.type == e1000_i210) { 2429 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 2430 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 2431 } 2432 2433 setup_timer(&adapter->watchdog_timer, igb_watchdog, 2434 (unsigned long) adapter); 2435 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, 2436 (unsigned long) adapter); 2437 2438 INIT_WORK(&adapter->reset_task, igb_reset_task); 2439 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2440 2441 /* Initialize link properties that are user-changeable */ 2442 adapter->fc_autoneg = true; 2443 hw->mac.autoneg = true; 2444 hw->phy.autoneg_advertised = 0x2f; 2445 2446 hw->fc.requested_mode = e1000_fc_default; 2447 hw->fc.current_mode = e1000_fc_default; 2448 2449 igb_validate_mdi_setting(hw); 2450 2451 /* By default, support wake on port A */ 2452 if (hw->bus.func == 0) 2453 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2454 2455 /* Check the NVM for wake support on non-port A ports */ 2456 if (hw->mac.type >= e1000_82580) 2457 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2458 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2459 &eeprom_data); 2460 else if (hw->bus.func == 1) 2461 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2462 2463 if (eeprom_data & IGB_EEPROM_APME) 2464 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2465 2466 /* now that we have the eeprom settings, apply the special cases where 2467 * the eeprom may be wrong or the board simply won't support wake on 2468 * lan on a particular port 2469 */ 2470 switch (pdev->device) { 2471 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2472 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2473 break; 2474 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2475 case E1000_DEV_ID_82576_FIBER: 2476 case E1000_DEV_ID_82576_SERDES: 2477 /* Wake events only supported on port A for dual fiber 2478 * regardless of eeprom setting 2479 */ 2480 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2481 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2482 break; 2483 case E1000_DEV_ID_82576_QUAD_COPPER: 2484 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2485 /* if quad port adapter, disable WoL on all but port A */ 2486 if (global_quad_port_a != 0) 2487 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2488 else 2489 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2490 /* Reset for multiple quad port adapters */ 2491 if (++global_quad_port_a == 4) 2492 global_quad_port_a = 0; 2493 break; 2494 default: 2495 /* If the device can't wake, don't set software support */ 2496 if (!device_can_wakeup(&adapter->pdev->dev)) 2497 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2498 } 2499 2500 /* initialize the wol settings based on the eeprom settings */ 2501 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 2502 adapter->wol |= E1000_WUFC_MAG; 2503 2504 /* Some vendors want WoL disabled by default, but still supported */ 2505 if ((hw->mac.type == e1000_i350) && 2506 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 2507 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2508 adapter->wol = 0; 2509 } 2510 2511 device_set_wakeup_enable(&adapter->pdev->dev, 2512 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 2513 2514 /* reset the hardware with the new settings */ 2515 igb_reset(adapter); 2516 2517 /* Init the I2C interface */ 2518 err = igb_init_i2c(adapter); 2519 if (err) { 2520 dev_err(&pdev->dev, "failed to init i2c interface\n"); 2521 goto err_eeprom; 2522 } 2523 2524 /* let the f/w know that the h/w is now under the control of the 2525 * driver. 2526 */ 2527 igb_get_hw_control(adapter); 2528 2529 strcpy(netdev->name, "eth%d"); 2530 err = register_netdev(netdev); 2531 if (err) 2532 goto err_register; 2533 2534 /* carrier off reporting is important to ethtool even BEFORE open */ 2535 netif_carrier_off(netdev); 2536 2537 #ifdef CONFIG_IGB_DCA 2538 if (dca_add_requester(&pdev->dev) == 0) { 2539 adapter->flags |= IGB_FLAG_DCA_ENABLED; 2540 dev_info(&pdev->dev, "DCA enabled\n"); 2541 igb_setup_dca(adapter); 2542 } 2543 2544 #endif 2545 #ifdef CONFIG_IGB_HWMON 2546 /* Initialize the thermal sensor on i350 devices. */ 2547 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 2548 u16 ets_word; 2549 2550 /* Read the NVM to determine if this i350 device supports an 2551 * external thermal sensor. 2552 */ 2553 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 2554 if (ets_word != 0x0000 && ets_word != 0xFFFF) 2555 adapter->ets = true; 2556 else 2557 adapter->ets = false; 2558 if (igb_sysfs_init(adapter)) 2559 dev_err(&pdev->dev, 2560 "failed to allocate sysfs resources\n"); 2561 } else { 2562 adapter->ets = false; 2563 } 2564 #endif 2565 /* Check if Media Autosense is enabled */ 2566 adapter->ei = *ei; 2567 if (hw->dev_spec._82575.mas_capable) 2568 igb_init_mas(adapter); 2569 2570 /* do hw tstamp init after resetting */ 2571 igb_ptp_init(adapter); 2572 2573 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 2574 /* print bus type/speed/width info, not applicable to i354 */ 2575 if (hw->mac.type != e1000_i354) { 2576 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 2577 netdev->name, 2578 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 2579 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 2580 "unknown"), 2581 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 2582 "Width x4" : 2583 (hw->bus.width == e1000_bus_width_pcie_x2) ? 2584 "Width x2" : 2585 (hw->bus.width == e1000_bus_width_pcie_x1) ? 2586 "Width x1" : "unknown"), netdev->dev_addr); 2587 } 2588 2589 if ((hw->mac.type >= e1000_i210 || 2590 igb_get_flash_presence_i210(hw))) { 2591 ret_val = igb_read_part_string(hw, part_str, 2592 E1000_PBANUM_LENGTH); 2593 } else { 2594 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 2595 } 2596 2597 if (ret_val) 2598 strcpy(part_str, "Unknown"); 2599 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 2600 dev_info(&pdev->dev, 2601 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 2602 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 2603 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2604 adapter->num_rx_queues, adapter->num_tx_queues); 2605 if (hw->phy.media_type == e1000_media_type_copper) { 2606 switch (hw->mac.type) { 2607 case e1000_i350: 2608 case e1000_i210: 2609 case e1000_i211: 2610 /* Enable EEE for internal copper PHY devices */ 2611 err = igb_set_eee_i350(hw, true, true); 2612 if ((!err) && 2613 (!hw->dev_spec._82575.eee_disable)) { 2614 adapter->eee_advert = 2615 MDIO_EEE_100TX | MDIO_EEE_1000T; 2616 adapter->flags |= IGB_FLAG_EEE; 2617 } 2618 break; 2619 case e1000_i354: 2620 if ((rd32(E1000_CTRL_EXT) & 2621 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 2622 err = igb_set_eee_i354(hw, true, true); 2623 if ((!err) && 2624 (!hw->dev_spec._82575.eee_disable)) { 2625 adapter->eee_advert = 2626 MDIO_EEE_100TX | MDIO_EEE_1000T; 2627 adapter->flags |= IGB_FLAG_EEE; 2628 } 2629 } 2630 break; 2631 default: 2632 break; 2633 } 2634 } 2635 pm_runtime_put_noidle(&pdev->dev); 2636 return 0; 2637 2638 err_register: 2639 igb_release_hw_control(adapter); 2640 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 2641 err_eeprom: 2642 if (!igb_check_reset_block(hw)) 2643 igb_reset_phy(hw); 2644 2645 if (hw->flash_address) 2646 iounmap(hw->flash_address); 2647 err_sw_init: 2648 igb_clear_interrupt_scheme(adapter); 2649 pci_iounmap(pdev, hw->hw_addr); 2650 err_ioremap: 2651 free_netdev(netdev); 2652 err_alloc_etherdev: 2653 pci_release_selected_regions(pdev, 2654 pci_select_bars(pdev, IORESOURCE_MEM)); 2655 err_pci_reg: 2656 err_dma: 2657 pci_disable_device(pdev); 2658 return err; 2659 } 2660 2661 #ifdef CONFIG_PCI_IOV 2662 static int igb_disable_sriov(struct pci_dev *pdev) 2663 { 2664 struct net_device *netdev = pci_get_drvdata(pdev); 2665 struct igb_adapter *adapter = netdev_priv(netdev); 2666 struct e1000_hw *hw = &adapter->hw; 2667 2668 /* reclaim resources allocated to VFs */ 2669 if (adapter->vf_data) { 2670 /* disable iov and allow time for transactions to clear */ 2671 if (pci_vfs_assigned(pdev)) { 2672 dev_warn(&pdev->dev, 2673 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 2674 return -EPERM; 2675 } else { 2676 pci_disable_sriov(pdev); 2677 msleep(500); 2678 } 2679 2680 kfree(adapter->vf_data); 2681 adapter->vf_data = NULL; 2682 adapter->vfs_allocated_count = 0; 2683 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2684 wrfl(); 2685 msleep(100); 2686 dev_info(&pdev->dev, "IOV Disabled\n"); 2687 2688 /* Re-enable DMA Coalescing flag since IOV is turned off */ 2689 adapter->flags |= IGB_FLAG_DMAC; 2690 } 2691 2692 return 0; 2693 } 2694 2695 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 2696 { 2697 struct net_device *netdev = pci_get_drvdata(pdev); 2698 struct igb_adapter *adapter = netdev_priv(netdev); 2699 int old_vfs = pci_num_vf(pdev); 2700 int err = 0; 2701 int i; 2702 2703 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 2704 err = -EPERM; 2705 goto out; 2706 } 2707 if (!num_vfs) 2708 goto out; 2709 2710 if (old_vfs) { 2711 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 2712 old_vfs, max_vfs); 2713 adapter->vfs_allocated_count = old_vfs; 2714 } else 2715 adapter->vfs_allocated_count = num_vfs; 2716 2717 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2718 sizeof(struct vf_data_storage), GFP_KERNEL); 2719 2720 /* if allocation failed then we do not support SR-IOV */ 2721 if (!adapter->vf_data) { 2722 adapter->vfs_allocated_count = 0; 2723 dev_err(&pdev->dev, 2724 "Unable to allocate memory for VF Data Storage\n"); 2725 err = -ENOMEM; 2726 goto out; 2727 } 2728 2729 /* only call pci_enable_sriov() if no VFs are allocated already */ 2730 if (!old_vfs) { 2731 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 2732 if (err) 2733 goto err_out; 2734 } 2735 dev_info(&pdev->dev, "%d VFs allocated\n", 2736 adapter->vfs_allocated_count); 2737 for (i = 0; i < adapter->vfs_allocated_count; i++) 2738 igb_vf_configure(adapter, i); 2739 2740 /* DMA Coalescing is not supported in IOV mode. */ 2741 adapter->flags &= ~IGB_FLAG_DMAC; 2742 goto out; 2743 2744 err_out: 2745 kfree(adapter->vf_data); 2746 adapter->vf_data = NULL; 2747 adapter->vfs_allocated_count = 0; 2748 out: 2749 return err; 2750 } 2751 2752 #endif 2753 /** 2754 * igb_remove_i2c - Cleanup I2C interface 2755 * @adapter: pointer to adapter structure 2756 **/ 2757 static void igb_remove_i2c(struct igb_adapter *adapter) 2758 { 2759 /* free the adapter bus structure */ 2760 i2c_del_adapter(&adapter->i2c_adap); 2761 } 2762 2763 /** 2764 * igb_remove - Device Removal Routine 2765 * @pdev: PCI device information struct 2766 * 2767 * igb_remove is called by the PCI subsystem to alert the driver 2768 * that it should release a PCI device. The could be caused by a 2769 * Hot-Plug event, or because the driver is going to be removed from 2770 * memory. 2771 **/ 2772 static void igb_remove(struct pci_dev *pdev) 2773 { 2774 struct net_device *netdev = pci_get_drvdata(pdev); 2775 struct igb_adapter *adapter = netdev_priv(netdev); 2776 struct e1000_hw *hw = &adapter->hw; 2777 2778 pm_runtime_get_noresume(&pdev->dev); 2779 #ifdef CONFIG_IGB_HWMON 2780 igb_sysfs_exit(adapter); 2781 #endif 2782 igb_remove_i2c(adapter); 2783 igb_ptp_stop(adapter); 2784 /* The watchdog timer may be rescheduled, so explicitly 2785 * disable watchdog from being rescheduled. 2786 */ 2787 set_bit(__IGB_DOWN, &adapter->state); 2788 del_timer_sync(&adapter->watchdog_timer); 2789 del_timer_sync(&adapter->phy_info_timer); 2790 2791 cancel_work_sync(&adapter->reset_task); 2792 cancel_work_sync(&adapter->watchdog_task); 2793 2794 #ifdef CONFIG_IGB_DCA 2795 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 2796 dev_info(&pdev->dev, "DCA disabled\n"); 2797 dca_remove_requester(&pdev->dev); 2798 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 2799 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 2800 } 2801 #endif 2802 2803 /* Release control of h/w to f/w. If f/w is AMT enabled, this 2804 * would have already happened in close and is redundant. 2805 */ 2806 igb_release_hw_control(adapter); 2807 2808 unregister_netdev(netdev); 2809 2810 igb_clear_interrupt_scheme(adapter); 2811 2812 #ifdef CONFIG_PCI_IOV 2813 igb_disable_sriov(pdev); 2814 #endif 2815 2816 pci_iounmap(pdev, hw->hw_addr); 2817 if (hw->flash_address) 2818 iounmap(hw->flash_address); 2819 pci_release_selected_regions(pdev, 2820 pci_select_bars(pdev, IORESOURCE_MEM)); 2821 2822 kfree(adapter->shadow_vfta); 2823 free_netdev(netdev); 2824 2825 pci_disable_pcie_error_reporting(pdev); 2826 2827 pci_disable_device(pdev); 2828 } 2829 2830 /** 2831 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 2832 * @adapter: board private structure to initialize 2833 * 2834 * This function initializes the vf specific data storage and then attempts to 2835 * allocate the VFs. The reason for ordering it this way is because it is much 2836 * mor expensive time wise to disable SR-IOV than it is to allocate and free 2837 * the memory for the VFs. 2838 **/ 2839 static void igb_probe_vfs(struct igb_adapter *adapter) 2840 { 2841 #ifdef CONFIG_PCI_IOV 2842 struct pci_dev *pdev = adapter->pdev; 2843 struct e1000_hw *hw = &adapter->hw; 2844 2845 /* Virtualization features not supported on i210 family. */ 2846 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 2847 return; 2848 2849 pci_sriov_set_totalvfs(pdev, 7); 2850 igb_pci_enable_sriov(pdev, max_vfs); 2851 2852 #endif /* CONFIG_PCI_IOV */ 2853 } 2854 2855 static void igb_init_queue_configuration(struct igb_adapter *adapter) 2856 { 2857 struct e1000_hw *hw = &adapter->hw; 2858 u32 max_rss_queues; 2859 2860 /* Determine the maximum number of RSS queues supported. */ 2861 switch (hw->mac.type) { 2862 case e1000_i211: 2863 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 2864 break; 2865 case e1000_82575: 2866 case e1000_i210: 2867 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 2868 break; 2869 case e1000_i350: 2870 /* I350 cannot do RSS and SR-IOV at the same time */ 2871 if (!!adapter->vfs_allocated_count) { 2872 max_rss_queues = 1; 2873 break; 2874 } 2875 /* fall through */ 2876 case e1000_82576: 2877 if (!!adapter->vfs_allocated_count) { 2878 max_rss_queues = 2; 2879 break; 2880 } 2881 /* fall through */ 2882 case e1000_82580: 2883 case e1000_i354: 2884 default: 2885 max_rss_queues = IGB_MAX_RX_QUEUES; 2886 break; 2887 } 2888 2889 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 2890 2891 /* Determine if we need to pair queues. */ 2892 switch (hw->mac.type) { 2893 case e1000_82575: 2894 case e1000_i211: 2895 /* Device supports enough interrupts without queue pairing. */ 2896 break; 2897 case e1000_82576: 2898 /* If VFs are going to be allocated with RSS queues then we 2899 * should pair the queues in order to conserve interrupts due 2900 * to limited supply. 2901 */ 2902 if ((adapter->rss_queues > 1) && 2903 (adapter->vfs_allocated_count > 6)) 2904 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2905 /* fall through */ 2906 case e1000_82580: 2907 case e1000_i350: 2908 case e1000_i354: 2909 case e1000_i210: 2910 default: 2911 /* If rss_queues > half of max_rss_queues, pair the queues in 2912 * order to conserve interrupts due to limited supply. 2913 */ 2914 if (adapter->rss_queues > (max_rss_queues / 2)) 2915 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2916 break; 2917 } 2918 } 2919 2920 /** 2921 * igb_sw_init - Initialize general software structures (struct igb_adapter) 2922 * @adapter: board private structure to initialize 2923 * 2924 * igb_sw_init initializes the Adapter private data structure. 2925 * Fields are initialized based on PCI device information and 2926 * OS network device settings (MTU size). 2927 **/ 2928 static int igb_sw_init(struct igb_adapter *adapter) 2929 { 2930 struct e1000_hw *hw = &adapter->hw; 2931 struct net_device *netdev = adapter->netdev; 2932 struct pci_dev *pdev = adapter->pdev; 2933 2934 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 2935 2936 /* set default ring sizes */ 2937 adapter->tx_ring_count = IGB_DEFAULT_TXD; 2938 adapter->rx_ring_count = IGB_DEFAULT_RXD; 2939 2940 /* set default ITR values */ 2941 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 2942 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 2943 2944 /* set default work limits */ 2945 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 2946 2947 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 2948 VLAN_HLEN; 2949 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 2950 2951 spin_lock_init(&adapter->stats64_lock); 2952 #ifdef CONFIG_PCI_IOV 2953 switch (hw->mac.type) { 2954 case e1000_82576: 2955 case e1000_i350: 2956 if (max_vfs > 7) { 2957 dev_warn(&pdev->dev, 2958 "Maximum of 7 VFs per PF, using max\n"); 2959 max_vfs = adapter->vfs_allocated_count = 7; 2960 } else 2961 adapter->vfs_allocated_count = max_vfs; 2962 if (adapter->vfs_allocated_count) 2963 dev_warn(&pdev->dev, 2964 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 2965 break; 2966 default: 2967 break; 2968 } 2969 #endif /* CONFIG_PCI_IOV */ 2970 2971 igb_init_queue_configuration(adapter); 2972 2973 /* Setup and initialize a copy of the hw vlan table array */ 2974 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 2975 GFP_ATOMIC); 2976 2977 /* This call may decrease the number of queues */ 2978 if (igb_init_interrupt_scheme(adapter, true)) { 2979 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 2980 return -ENOMEM; 2981 } 2982 2983 igb_probe_vfs(adapter); 2984 2985 /* Explicitly disable IRQ since the NIC can be in any state. */ 2986 igb_irq_disable(adapter); 2987 2988 if (hw->mac.type >= e1000_i350) 2989 adapter->flags &= ~IGB_FLAG_DMAC; 2990 2991 set_bit(__IGB_DOWN, &adapter->state); 2992 return 0; 2993 } 2994 2995 /** 2996 * igb_open - Called when a network interface is made active 2997 * @netdev: network interface device structure 2998 * 2999 * Returns 0 on success, negative value on failure 3000 * 3001 * The open entry point is called when a network interface is made 3002 * active by the system (IFF_UP). At this point all resources needed 3003 * for transmit and receive operations are allocated, the interrupt 3004 * handler is registered with the OS, the watchdog timer is started, 3005 * and the stack is notified that the interface is ready. 3006 **/ 3007 static int __igb_open(struct net_device *netdev, bool resuming) 3008 { 3009 struct igb_adapter *adapter = netdev_priv(netdev); 3010 struct e1000_hw *hw = &adapter->hw; 3011 struct pci_dev *pdev = adapter->pdev; 3012 int err; 3013 int i; 3014 3015 /* disallow open during test */ 3016 if (test_bit(__IGB_TESTING, &adapter->state)) { 3017 WARN_ON(resuming); 3018 return -EBUSY; 3019 } 3020 3021 if (!resuming) 3022 pm_runtime_get_sync(&pdev->dev); 3023 3024 netif_carrier_off(netdev); 3025 3026 /* allocate transmit descriptors */ 3027 err = igb_setup_all_tx_resources(adapter); 3028 if (err) 3029 goto err_setup_tx; 3030 3031 /* allocate receive descriptors */ 3032 err = igb_setup_all_rx_resources(adapter); 3033 if (err) 3034 goto err_setup_rx; 3035 3036 igb_power_up_link(adapter); 3037 3038 /* before we allocate an interrupt, we must be ready to handle it. 3039 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3040 * as soon as we call pci_request_irq, so we have to setup our 3041 * clean_rx handler before we do so. 3042 */ 3043 igb_configure(adapter); 3044 3045 err = igb_request_irq(adapter); 3046 if (err) 3047 goto err_req_irq; 3048 3049 /* Notify the stack of the actual queue counts. */ 3050 err = netif_set_real_num_tx_queues(adapter->netdev, 3051 adapter->num_tx_queues); 3052 if (err) 3053 goto err_set_queues; 3054 3055 err = netif_set_real_num_rx_queues(adapter->netdev, 3056 adapter->num_rx_queues); 3057 if (err) 3058 goto err_set_queues; 3059 3060 /* From here on the code is the same as igb_up() */ 3061 clear_bit(__IGB_DOWN, &adapter->state); 3062 3063 for (i = 0; i < adapter->num_q_vectors; i++) 3064 napi_enable(&(adapter->q_vector[i]->napi)); 3065 3066 /* Clear any pending interrupts. */ 3067 rd32(E1000_ICR); 3068 3069 igb_irq_enable(adapter); 3070 3071 /* notify VFs that reset has been completed */ 3072 if (adapter->vfs_allocated_count) { 3073 u32 reg_data = rd32(E1000_CTRL_EXT); 3074 3075 reg_data |= E1000_CTRL_EXT_PFRSTD; 3076 wr32(E1000_CTRL_EXT, reg_data); 3077 } 3078 3079 netif_tx_start_all_queues(netdev); 3080 3081 if (!resuming) 3082 pm_runtime_put(&pdev->dev); 3083 3084 /* start the watchdog. */ 3085 hw->mac.get_link_status = 1; 3086 schedule_work(&adapter->watchdog_task); 3087 3088 return 0; 3089 3090 err_set_queues: 3091 igb_free_irq(adapter); 3092 err_req_irq: 3093 igb_release_hw_control(adapter); 3094 igb_power_down_link(adapter); 3095 igb_free_all_rx_resources(adapter); 3096 err_setup_rx: 3097 igb_free_all_tx_resources(adapter); 3098 err_setup_tx: 3099 igb_reset(adapter); 3100 if (!resuming) 3101 pm_runtime_put(&pdev->dev); 3102 3103 return err; 3104 } 3105 3106 static int igb_open(struct net_device *netdev) 3107 { 3108 return __igb_open(netdev, false); 3109 } 3110 3111 /** 3112 * igb_close - Disables a network interface 3113 * @netdev: network interface device structure 3114 * 3115 * Returns 0, this is not allowed to fail 3116 * 3117 * The close entry point is called when an interface is de-activated 3118 * by the OS. The hardware is still under the driver's control, but 3119 * needs to be disabled. A global MAC reset is issued to stop the 3120 * hardware, and all transmit and receive resources are freed. 3121 **/ 3122 static int __igb_close(struct net_device *netdev, bool suspending) 3123 { 3124 struct igb_adapter *adapter = netdev_priv(netdev); 3125 struct pci_dev *pdev = adapter->pdev; 3126 3127 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 3128 3129 if (!suspending) 3130 pm_runtime_get_sync(&pdev->dev); 3131 3132 igb_down(adapter); 3133 igb_free_irq(adapter); 3134 3135 igb_free_all_tx_resources(adapter); 3136 igb_free_all_rx_resources(adapter); 3137 3138 if (!suspending) 3139 pm_runtime_put_sync(&pdev->dev); 3140 return 0; 3141 } 3142 3143 static int igb_close(struct net_device *netdev) 3144 { 3145 return __igb_close(netdev, false); 3146 } 3147 3148 /** 3149 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 3150 * @tx_ring: tx descriptor ring (for a specific queue) to setup 3151 * 3152 * Return 0 on success, negative on failure 3153 **/ 3154 int igb_setup_tx_resources(struct igb_ring *tx_ring) 3155 { 3156 struct device *dev = tx_ring->dev; 3157 int size; 3158 3159 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3160 3161 tx_ring->tx_buffer_info = vzalloc(size); 3162 if (!tx_ring->tx_buffer_info) 3163 goto err; 3164 3165 /* round up to nearest 4K */ 3166 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 3167 tx_ring->size = ALIGN(tx_ring->size, 4096); 3168 3169 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 3170 &tx_ring->dma, GFP_KERNEL); 3171 if (!tx_ring->desc) 3172 goto err; 3173 3174 tx_ring->next_to_use = 0; 3175 tx_ring->next_to_clean = 0; 3176 3177 return 0; 3178 3179 err: 3180 vfree(tx_ring->tx_buffer_info); 3181 tx_ring->tx_buffer_info = NULL; 3182 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 3183 return -ENOMEM; 3184 } 3185 3186 /** 3187 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 3188 * (Descriptors) for all queues 3189 * @adapter: board private structure 3190 * 3191 * Return 0 on success, negative on failure 3192 **/ 3193 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 3194 { 3195 struct pci_dev *pdev = adapter->pdev; 3196 int i, err = 0; 3197 3198 for (i = 0; i < adapter->num_tx_queues; i++) { 3199 err = igb_setup_tx_resources(adapter->tx_ring[i]); 3200 if (err) { 3201 dev_err(&pdev->dev, 3202 "Allocation for Tx Queue %u failed\n", i); 3203 for (i--; i >= 0; i--) 3204 igb_free_tx_resources(adapter->tx_ring[i]); 3205 break; 3206 } 3207 } 3208 3209 return err; 3210 } 3211 3212 /** 3213 * igb_setup_tctl - configure the transmit control registers 3214 * @adapter: Board private structure 3215 **/ 3216 void igb_setup_tctl(struct igb_adapter *adapter) 3217 { 3218 struct e1000_hw *hw = &adapter->hw; 3219 u32 tctl; 3220 3221 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 3222 wr32(E1000_TXDCTL(0), 0); 3223 3224 /* Program the Transmit Control Register */ 3225 tctl = rd32(E1000_TCTL); 3226 tctl &= ~E1000_TCTL_CT; 3227 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 3228 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3229 3230 igb_config_collision_dist(hw); 3231 3232 /* Enable transmits */ 3233 tctl |= E1000_TCTL_EN; 3234 3235 wr32(E1000_TCTL, tctl); 3236 } 3237 3238 /** 3239 * igb_configure_tx_ring - Configure transmit ring after Reset 3240 * @adapter: board private structure 3241 * @ring: tx ring to configure 3242 * 3243 * Configure a transmit ring after a reset. 3244 **/ 3245 void igb_configure_tx_ring(struct igb_adapter *adapter, 3246 struct igb_ring *ring) 3247 { 3248 struct e1000_hw *hw = &adapter->hw; 3249 u32 txdctl = 0; 3250 u64 tdba = ring->dma; 3251 int reg_idx = ring->reg_idx; 3252 3253 /* disable the queue */ 3254 wr32(E1000_TXDCTL(reg_idx), 0); 3255 wrfl(); 3256 mdelay(10); 3257 3258 wr32(E1000_TDLEN(reg_idx), 3259 ring->count * sizeof(union e1000_adv_tx_desc)); 3260 wr32(E1000_TDBAL(reg_idx), 3261 tdba & 0x00000000ffffffffULL); 3262 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 3263 3264 ring->tail = hw->hw_addr + E1000_TDT(reg_idx); 3265 wr32(E1000_TDH(reg_idx), 0); 3266 writel(0, ring->tail); 3267 3268 txdctl |= IGB_TX_PTHRESH; 3269 txdctl |= IGB_TX_HTHRESH << 8; 3270 txdctl |= IGB_TX_WTHRESH << 16; 3271 3272 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 3273 wr32(E1000_TXDCTL(reg_idx), txdctl); 3274 } 3275 3276 /** 3277 * igb_configure_tx - Configure transmit Unit after Reset 3278 * @adapter: board private structure 3279 * 3280 * Configure the Tx unit of the MAC after a reset. 3281 **/ 3282 static void igb_configure_tx(struct igb_adapter *adapter) 3283 { 3284 int i; 3285 3286 for (i = 0; i < adapter->num_tx_queues; i++) 3287 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 3288 } 3289 3290 /** 3291 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 3292 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 3293 * 3294 * Returns 0 on success, negative on failure 3295 **/ 3296 int igb_setup_rx_resources(struct igb_ring *rx_ring) 3297 { 3298 struct device *dev = rx_ring->dev; 3299 int size; 3300 3301 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3302 3303 rx_ring->rx_buffer_info = vzalloc(size); 3304 if (!rx_ring->rx_buffer_info) 3305 goto err; 3306 3307 /* Round up to nearest 4K */ 3308 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 3309 rx_ring->size = ALIGN(rx_ring->size, 4096); 3310 3311 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 3312 &rx_ring->dma, GFP_KERNEL); 3313 if (!rx_ring->desc) 3314 goto err; 3315 3316 rx_ring->next_to_alloc = 0; 3317 rx_ring->next_to_clean = 0; 3318 rx_ring->next_to_use = 0; 3319 3320 return 0; 3321 3322 err: 3323 vfree(rx_ring->rx_buffer_info); 3324 rx_ring->rx_buffer_info = NULL; 3325 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 3326 return -ENOMEM; 3327 } 3328 3329 /** 3330 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 3331 * (Descriptors) for all queues 3332 * @adapter: board private structure 3333 * 3334 * Return 0 on success, negative on failure 3335 **/ 3336 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 3337 { 3338 struct pci_dev *pdev = adapter->pdev; 3339 int i, err = 0; 3340 3341 for (i = 0; i < adapter->num_rx_queues; i++) { 3342 err = igb_setup_rx_resources(adapter->rx_ring[i]); 3343 if (err) { 3344 dev_err(&pdev->dev, 3345 "Allocation for Rx Queue %u failed\n", i); 3346 for (i--; i >= 0; i--) 3347 igb_free_rx_resources(adapter->rx_ring[i]); 3348 break; 3349 } 3350 } 3351 3352 return err; 3353 } 3354 3355 /** 3356 * igb_setup_mrqc - configure the multiple receive queue control registers 3357 * @adapter: Board private structure 3358 **/ 3359 static void igb_setup_mrqc(struct igb_adapter *adapter) 3360 { 3361 struct e1000_hw *hw = &adapter->hw; 3362 u32 mrqc, rxcsum; 3363 u32 j, num_rx_queues; 3364 u32 rss_key[10]; 3365 3366 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3367 for (j = 0; j < 10; j++) 3368 wr32(E1000_RSSRK(j), rss_key[j]); 3369 3370 num_rx_queues = adapter->rss_queues; 3371 3372 switch (hw->mac.type) { 3373 case e1000_82576: 3374 /* 82576 supports 2 RSS queues for SR-IOV */ 3375 if (adapter->vfs_allocated_count) 3376 num_rx_queues = 2; 3377 break; 3378 default: 3379 break; 3380 } 3381 3382 if (adapter->rss_indir_tbl_init != num_rx_queues) { 3383 for (j = 0; j < IGB_RETA_SIZE; j++) 3384 adapter->rss_indir_tbl[j] = 3385 (j * num_rx_queues) / IGB_RETA_SIZE; 3386 adapter->rss_indir_tbl_init = num_rx_queues; 3387 } 3388 igb_write_rss_indir_tbl(adapter); 3389 3390 /* Disable raw packet checksumming so that RSS hash is placed in 3391 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 3392 * offloads as they are enabled by default 3393 */ 3394 rxcsum = rd32(E1000_RXCSUM); 3395 rxcsum |= E1000_RXCSUM_PCSD; 3396 3397 if (adapter->hw.mac.type >= e1000_82576) 3398 /* Enable Receive Checksum Offload for SCTP */ 3399 rxcsum |= E1000_RXCSUM_CRCOFL; 3400 3401 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 3402 wr32(E1000_RXCSUM, rxcsum); 3403 3404 /* Generate RSS hash based on packet types, TCP/UDP 3405 * port numbers and/or IPv4/v6 src and dst addresses 3406 */ 3407 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 3408 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3409 E1000_MRQC_RSS_FIELD_IPV6 | 3410 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3411 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 3412 3413 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 3414 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 3415 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 3416 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 3417 3418 /* If VMDq is enabled then we set the appropriate mode for that, else 3419 * we default to RSS so that an RSS hash is calculated per packet even 3420 * if we are only using one queue 3421 */ 3422 if (adapter->vfs_allocated_count) { 3423 if (hw->mac.type > e1000_82575) { 3424 /* Set the default pool for the PF's first queue */ 3425 u32 vtctl = rd32(E1000_VT_CTL); 3426 3427 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 3428 E1000_VT_CTL_DISABLE_DEF_POOL); 3429 vtctl |= adapter->vfs_allocated_count << 3430 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 3431 wr32(E1000_VT_CTL, vtctl); 3432 } 3433 if (adapter->rss_queues > 1) 3434 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q; 3435 else 3436 mrqc |= E1000_MRQC_ENABLE_VMDQ; 3437 } else { 3438 if (hw->mac.type != e1000_i211) 3439 mrqc |= E1000_MRQC_ENABLE_RSS_4Q; 3440 } 3441 igb_vmm_control(adapter); 3442 3443 wr32(E1000_MRQC, mrqc); 3444 } 3445 3446 /** 3447 * igb_setup_rctl - configure the receive control registers 3448 * @adapter: Board private structure 3449 **/ 3450 void igb_setup_rctl(struct igb_adapter *adapter) 3451 { 3452 struct e1000_hw *hw = &adapter->hw; 3453 u32 rctl; 3454 3455 rctl = rd32(E1000_RCTL); 3456 3457 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3458 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 3459 3460 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 3461 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3462 3463 /* enable stripping of CRC. It's unlikely this will break BMC 3464 * redirection as it did with e1000. Newer features require 3465 * that the HW strips the CRC. 3466 */ 3467 rctl |= E1000_RCTL_SECRC; 3468 3469 /* disable store bad packets and clear size bits. */ 3470 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 3471 3472 /* enable LPE to prevent packets larger than max_frame_size */ 3473 rctl |= E1000_RCTL_LPE; 3474 3475 /* disable queue 0 to prevent tail write w/o re-config */ 3476 wr32(E1000_RXDCTL(0), 0); 3477 3478 /* Attention!!! For SR-IOV PF driver operations you must enable 3479 * queue drop for all VF and PF queues to prevent head of line blocking 3480 * if an un-trusted VF does not provide descriptors to hardware. 3481 */ 3482 if (adapter->vfs_allocated_count) { 3483 /* set all queue drop enable bits */ 3484 wr32(E1000_QDE, ALL_QUEUES); 3485 } 3486 3487 /* This is useful for sniffing bad packets. */ 3488 if (adapter->netdev->features & NETIF_F_RXALL) { 3489 /* UPE and MPE will be handled by normal PROMISC logic 3490 * in e1000e_set_rx_mode 3491 */ 3492 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3493 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3494 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3495 3496 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3497 E1000_RCTL_DPF | /* Allow filtered pause */ 3498 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3499 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3500 * and that breaks VLANs. 3501 */ 3502 } 3503 3504 wr32(E1000_RCTL, rctl); 3505 } 3506 3507 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 3508 int vfn) 3509 { 3510 struct e1000_hw *hw = &adapter->hw; 3511 u32 vmolr; 3512 3513 /* if it isn't the PF check to see if VFs are enabled and 3514 * increase the size to support vlan tags 3515 */ 3516 if (vfn < adapter->vfs_allocated_count && 3517 adapter->vf_data[vfn].vlans_enabled) 3518 size += VLAN_TAG_SIZE; 3519 3520 vmolr = rd32(E1000_VMOLR(vfn)); 3521 vmolr &= ~E1000_VMOLR_RLPML_MASK; 3522 vmolr |= size | E1000_VMOLR_LPE; 3523 wr32(E1000_VMOLR(vfn), vmolr); 3524 3525 return 0; 3526 } 3527 3528 /** 3529 * igb_rlpml_set - set maximum receive packet size 3530 * @adapter: board private structure 3531 * 3532 * Configure maximum receivable packet size. 3533 **/ 3534 static void igb_rlpml_set(struct igb_adapter *adapter) 3535 { 3536 u32 max_frame_size = adapter->max_frame_size; 3537 struct e1000_hw *hw = &adapter->hw; 3538 u16 pf_id = adapter->vfs_allocated_count; 3539 3540 if (pf_id) { 3541 igb_set_vf_rlpml(adapter, max_frame_size, pf_id); 3542 /* If we're in VMDQ or SR-IOV mode, then set global RLPML 3543 * to our max jumbo frame size, in case we need to enable 3544 * jumbo frames on one of the rings later. 3545 * This will not pass over-length frames into the default 3546 * queue because it's gated by the VMOLR.RLPML. 3547 */ 3548 max_frame_size = MAX_JUMBO_FRAME_SIZE; 3549 } 3550 3551 wr32(E1000_RLPML, max_frame_size); 3552 } 3553 3554 static inline void igb_set_vmolr(struct igb_adapter *adapter, 3555 int vfn, bool aupe) 3556 { 3557 struct e1000_hw *hw = &adapter->hw; 3558 u32 vmolr; 3559 3560 /* This register exists only on 82576 and newer so if we are older then 3561 * we should exit and do nothing 3562 */ 3563 if (hw->mac.type < e1000_82576) 3564 return; 3565 3566 vmolr = rd32(E1000_VMOLR(vfn)); 3567 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ 3568 if (hw->mac.type == e1000_i350) { 3569 u32 dvmolr; 3570 3571 dvmolr = rd32(E1000_DVMOLR(vfn)); 3572 dvmolr |= E1000_DVMOLR_STRVLAN; 3573 wr32(E1000_DVMOLR(vfn), dvmolr); 3574 } 3575 if (aupe) 3576 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 3577 else 3578 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 3579 3580 /* clear all bits that might not be set */ 3581 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 3582 3583 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 3584 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 3585 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 3586 * multicast packets 3587 */ 3588 if (vfn <= adapter->vfs_allocated_count) 3589 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 3590 3591 wr32(E1000_VMOLR(vfn), vmolr); 3592 } 3593 3594 /** 3595 * igb_configure_rx_ring - Configure a receive ring after Reset 3596 * @adapter: board private structure 3597 * @ring: receive ring to be configured 3598 * 3599 * Configure the Rx unit of the MAC after a reset. 3600 **/ 3601 void igb_configure_rx_ring(struct igb_adapter *adapter, 3602 struct igb_ring *ring) 3603 { 3604 struct e1000_hw *hw = &adapter->hw; 3605 u64 rdba = ring->dma; 3606 int reg_idx = ring->reg_idx; 3607 u32 srrctl = 0, rxdctl = 0; 3608 3609 /* disable the queue */ 3610 wr32(E1000_RXDCTL(reg_idx), 0); 3611 3612 /* Set DMA base address registers */ 3613 wr32(E1000_RDBAL(reg_idx), 3614 rdba & 0x00000000ffffffffULL); 3615 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 3616 wr32(E1000_RDLEN(reg_idx), 3617 ring->count * sizeof(union e1000_adv_rx_desc)); 3618 3619 /* initialize head and tail */ 3620 ring->tail = hw->hw_addr + E1000_RDT(reg_idx); 3621 wr32(E1000_RDH(reg_idx), 0); 3622 writel(0, ring->tail); 3623 3624 /* set descriptor configuration */ 3625 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 3626 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3627 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3628 if (hw->mac.type >= e1000_82580) 3629 srrctl |= E1000_SRRCTL_TIMESTAMP; 3630 /* Only set Drop Enable if we are supporting multiple queues */ 3631 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 3632 srrctl |= E1000_SRRCTL_DROP_EN; 3633 3634 wr32(E1000_SRRCTL(reg_idx), srrctl); 3635 3636 /* set filtering for VMDQ pools */ 3637 igb_set_vmolr(adapter, reg_idx & 0x7, true); 3638 3639 rxdctl |= IGB_RX_PTHRESH; 3640 rxdctl |= IGB_RX_HTHRESH << 8; 3641 rxdctl |= IGB_RX_WTHRESH << 16; 3642 3643 /* enable receive descriptor fetching */ 3644 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3645 wr32(E1000_RXDCTL(reg_idx), rxdctl); 3646 } 3647 3648 /** 3649 * igb_configure_rx - Configure receive Unit after Reset 3650 * @adapter: board private structure 3651 * 3652 * Configure the Rx unit of the MAC after a reset. 3653 **/ 3654 static void igb_configure_rx(struct igb_adapter *adapter) 3655 { 3656 int i; 3657 3658 /* set UTA to appropriate mode */ 3659 igb_set_uta(adapter); 3660 3661 /* set the correct pool for the PF default MAC address in entry 0 */ 3662 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, 3663 adapter->vfs_allocated_count); 3664 3665 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3666 * the Base and Length of the Rx Descriptor Ring 3667 */ 3668 for (i = 0; i < adapter->num_rx_queues; i++) 3669 igb_configure_rx_ring(adapter, adapter->rx_ring[i]); 3670 } 3671 3672 /** 3673 * igb_free_tx_resources - Free Tx Resources per Queue 3674 * @tx_ring: Tx descriptor ring for a specific queue 3675 * 3676 * Free all transmit software resources 3677 **/ 3678 void igb_free_tx_resources(struct igb_ring *tx_ring) 3679 { 3680 igb_clean_tx_ring(tx_ring); 3681 3682 vfree(tx_ring->tx_buffer_info); 3683 tx_ring->tx_buffer_info = NULL; 3684 3685 /* if not set, then don't free */ 3686 if (!tx_ring->desc) 3687 return; 3688 3689 dma_free_coherent(tx_ring->dev, tx_ring->size, 3690 tx_ring->desc, tx_ring->dma); 3691 3692 tx_ring->desc = NULL; 3693 } 3694 3695 /** 3696 * igb_free_all_tx_resources - Free Tx Resources for All Queues 3697 * @adapter: board private structure 3698 * 3699 * Free all transmit software resources 3700 **/ 3701 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 3702 { 3703 int i; 3704 3705 for (i = 0; i < adapter->num_tx_queues; i++) 3706 if (adapter->tx_ring[i]) 3707 igb_free_tx_resources(adapter->tx_ring[i]); 3708 } 3709 3710 void igb_unmap_and_free_tx_resource(struct igb_ring *ring, 3711 struct igb_tx_buffer *tx_buffer) 3712 { 3713 if (tx_buffer->skb) { 3714 dev_kfree_skb_any(tx_buffer->skb); 3715 if (dma_unmap_len(tx_buffer, len)) 3716 dma_unmap_single(ring->dev, 3717 dma_unmap_addr(tx_buffer, dma), 3718 dma_unmap_len(tx_buffer, len), 3719 DMA_TO_DEVICE); 3720 } else if (dma_unmap_len(tx_buffer, len)) { 3721 dma_unmap_page(ring->dev, 3722 dma_unmap_addr(tx_buffer, dma), 3723 dma_unmap_len(tx_buffer, len), 3724 DMA_TO_DEVICE); 3725 } 3726 tx_buffer->next_to_watch = NULL; 3727 tx_buffer->skb = NULL; 3728 dma_unmap_len_set(tx_buffer, len, 0); 3729 /* buffer_info must be completely set up in the transmit path */ 3730 } 3731 3732 /** 3733 * igb_clean_tx_ring - Free Tx Buffers 3734 * @tx_ring: ring to be cleaned 3735 **/ 3736 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 3737 { 3738 struct igb_tx_buffer *buffer_info; 3739 unsigned long size; 3740 u16 i; 3741 3742 if (!tx_ring->tx_buffer_info) 3743 return; 3744 /* Free all the Tx ring sk_buffs */ 3745 3746 for (i = 0; i < tx_ring->count; i++) { 3747 buffer_info = &tx_ring->tx_buffer_info[i]; 3748 igb_unmap_and_free_tx_resource(tx_ring, buffer_info); 3749 } 3750 3751 netdev_tx_reset_queue(txring_txq(tx_ring)); 3752 3753 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3754 memset(tx_ring->tx_buffer_info, 0, size); 3755 3756 /* Zero out the descriptor ring */ 3757 memset(tx_ring->desc, 0, tx_ring->size); 3758 3759 tx_ring->next_to_use = 0; 3760 tx_ring->next_to_clean = 0; 3761 } 3762 3763 /** 3764 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 3765 * @adapter: board private structure 3766 **/ 3767 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 3768 { 3769 int i; 3770 3771 for (i = 0; i < adapter->num_tx_queues; i++) 3772 if (adapter->tx_ring[i]) 3773 igb_clean_tx_ring(adapter->tx_ring[i]); 3774 } 3775 3776 /** 3777 * igb_free_rx_resources - Free Rx Resources 3778 * @rx_ring: ring to clean the resources from 3779 * 3780 * Free all receive software resources 3781 **/ 3782 void igb_free_rx_resources(struct igb_ring *rx_ring) 3783 { 3784 igb_clean_rx_ring(rx_ring); 3785 3786 vfree(rx_ring->rx_buffer_info); 3787 rx_ring->rx_buffer_info = NULL; 3788 3789 /* if not set, then don't free */ 3790 if (!rx_ring->desc) 3791 return; 3792 3793 dma_free_coherent(rx_ring->dev, rx_ring->size, 3794 rx_ring->desc, rx_ring->dma); 3795 3796 rx_ring->desc = NULL; 3797 } 3798 3799 /** 3800 * igb_free_all_rx_resources - Free Rx Resources for All Queues 3801 * @adapter: board private structure 3802 * 3803 * Free all receive software resources 3804 **/ 3805 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 3806 { 3807 int i; 3808 3809 for (i = 0; i < adapter->num_rx_queues; i++) 3810 if (adapter->rx_ring[i]) 3811 igb_free_rx_resources(adapter->rx_ring[i]); 3812 } 3813 3814 /** 3815 * igb_clean_rx_ring - Free Rx Buffers per Queue 3816 * @rx_ring: ring to free buffers from 3817 **/ 3818 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 3819 { 3820 unsigned long size; 3821 u16 i; 3822 3823 if (rx_ring->skb) 3824 dev_kfree_skb(rx_ring->skb); 3825 rx_ring->skb = NULL; 3826 3827 if (!rx_ring->rx_buffer_info) 3828 return; 3829 3830 /* Free all the Rx ring sk_buffs */ 3831 for (i = 0; i < rx_ring->count; i++) { 3832 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 3833 3834 if (!buffer_info->page) 3835 continue; 3836 3837 dma_unmap_page(rx_ring->dev, 3838 buffer_info->dma, 3839 PAGE_SIZE, 3840 DMA_FROM_DEVICE); 3841 __free_page(buffer_info->page); 3842 3843 buffer_info->page = NULL; 3844 } 3845 3846 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3847 memset(rx_ring->rx_buffer_info, 0, size); 3848 3849 /* Zero out the descriptor ring */ 3850 memset(rx_ring->desc, 0, rx_ring->size); 3851 3852 rx_ring->next_to_alloc = 0; 3853 rx_ring->next_to_clean = 0; 3854 rx_ring->next_to_use = 0; 3855 } 3856 3857 /** 3858 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 3859 * @adapter: board private structure 3860 **/ 3861 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 3862 { 3863 int i; 3864 3865 for (i = 0; i < adapter->num_rx_queues; i++) 3866 if (adapter->rx_ring[i]) 3867 igb_clean_rx_ring(adapter->rx_ring[i]); 3868 } 3869 3870 /** 3871 * igb_set_mac - Change the Ethernet Address of the NIC 3872 * @netdev: network interface device structure 3873 * @p: pointer to an address structure 3874 * 3875 * Returns 0 on success, negative on failure 3876 **/ 3877 static int igb_set_mac(struct net_device *netdev, void *p) 3878 { 3879 struct igb_adapter *adapter = netdev_priv(netdev); 3880 struct e1000_hw *hw = &adapter->hw; 3881 struct sockaddr *addr = p; 3882 3883 if (!is_valid_ether_addr(addr->sa_data)) 3884 return -EADDRNOTAVAIL; 3885 3886 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 3887 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 3888 3889 /* set the correct pool for the new PF MAC address in entry 0 */ 3890 igb_rar_set_qsel(adapter, hw->mac.addr, 0, 3891 adapter->vfs_allocated_count); 3892 3893 return 0; 3894 } 3895 3896 /** 3897 * igb_write_mc_addr_list - write multicast addresses to MTA 3898 * @netdev: network interface device structure 3899 * 3900 * Writes multicast address list to the MTA hash table. 3901 * Returns: -ENOMEM on failure 3902 * 0 on no addresses written 3903 * X on writing X addresses to MTA 3904 **/ 3905 static int igb_write_mc_addr_list(struct net_device *netdev) 3906 { 3907 struct igb_adapter *adapter = netdev_priv(netdev); 3908 struct e1000_hw *hw = &adapter->hw; 3909 struct netdev_hw_addr *ha; 3910 u8 *mta_list; 3911 int i; 3912 3913 if (netdev_mc_empty(netdev)) { 3914 /* nothing to program, so clear mc list */ 3915 igb_update_mc_addr_list(hw, NULL, 0); 3916 igb_restore_vf_multicasts(adapter); 3917 return 0; 3918 } 3919 3920 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 3921 if (!mta_list) 3922 return -ENOMEM; 3923 3924 /* The shared function expects a packed array of only addresses. */ 3925 i = 0; 3926 netdev_for_each_mc_addr(ha, netdev) 3927 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3928 3929 igb_update_mc_addr_list(hw, mta_list, i); 3930 kfree(mta_list); 3931 3932 return netdev_mc_count(netdev); 3933 } 3934 3935 /** 3936 * igb_write_uc_addr_list - write unicast addresses to RAR table 3937 * @netdev: network interface device structure 3938 * 3939 * Writes unicast address list to the RAR table. 3940 * Returns: -ENOMEM on failure/insufficient address space 3941 * 0 on no addresses written 3942 * X on writing X addresses to the RAR table 3943 **/ 3944 static int igb_write_uc_addr_list(struct net_device *netdev) 3945 { 3946 struct igb_adapter *adapter = netdev_priv(netdev); 3947 struct e1000_hw *hw = &adapter->hw; 3948 unsigned int vfn = adapter->vfs_allocated_count; 3949 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 3950 int count = 0; 3951 3952 /* return ENOMEM indicating insufficient memory for addresses */ 3953 if (netdev_uc_count(netdev) > rar_entries) 3954 return -ENOMEM; 3955 3956 if (!netdev_uc_empty(netdev) && rar_entries) { 3957 struct netdev_hw_addr *ha; 3958 3959 netdev_for_each_uc_addr(ha, netdev) { 3960 if (!rar_entries) 3961 break; 3962 igb_rar_set_qsel(adapter, ha->addr, 3963 rar_entries--, 3964 vfn); 3965 count++; 3966 } 3967 } 3968 /* write the addresses in reverse order to avoid write combining */ 3969 for (; rar_entries > 0 ; rar_entries--) { 3970 wr32(E1000_RAH(rar_entries), 0); 3971 wr32(E1000_RAL(rar_entries), 0); 3972 } 3973 wrfl(); 3974 3975 return count; 3976 } 3977 3978 /** 3979 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 3980 * @netdev: network interface device structure 3981 * 3982 * The set_rx_mode entry point is called whenever the unicast or multicast 3983 * address lists or the network interface flags are updated. This routine is 3984 * responsible for configuring the hardware for proper unicast, multicast, 3985 * promiscuous mode, and all-multi behavior. 3986 **/ 3987 static void igb_set_rx_mode(struct net_device *netdev) 3988 { 3989 struct igb_adapter *adapter = netdev_priv(netdev); 3990 struct e1000_hw *hw = &adapter->hw; 3991 unsigned int vfn = adapter->vfs_allocated_count; 3992 u32 rctl, vmolr = 0; 3993 int count; 3994 3995 /* Check for Promiscuous and All Multicast modes */ 3996 rctl = rd32(E1000_RCTL); 3997 3998 /* clear the effected bits */ 3999 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); 4000 4001 if (netdev->flags & IFF_PROMISC) { 4002 /* retain VLAN HW filtering if in VT mode */ 4003 if (adapter->vfs_allocated_count) 4004 rctl |= E1000_RCTL_VFE; 4005 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 4006 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); 4007 } else { 4008 if (netdev->flags & IFF_ALLMULTI) { 4009 rctl |= E1000_RCTL_MPE; 4010 vmolr |= E1000_VMOLR_MPME; 4011 } else { 4012 /* Write addresses to the MTA, if the attempt fails 4013 * then we should just turn on promiscuous mode so 4014 * that we can at least receive multicast traffic 4015 */ 4016 count = igb_write_mc_addr_list(netdev); 4017 if (count < 0) { 4018 rctl |= E1000_RCTL_MPE; 4019 vmolr |= E1000_VMOLR_MPME; 4020 } else if (count) { 4021 vmolr |= E1000_VMOLR_ROMPE; 4022 } 4023 } 4024 /* Write addresses to available RAR registers, if there is not 4025 * sufficient space to store all the addresses then enable 4026 * unicast promiscuous mode 4027 */ 4028 count = igb_write_uc_addr_list(netdev); 4029 if (count < 0) { 4030 rctl |= E1000_RCTL_UPE; 4031 vmolr |= E1000_VMOLR_ROPE; 4032 } 4033 rctl |= E1000_RCTL_VFE; 4034 } 4035 wr32(E1000_RCTL, rctl); 4036 4037 /* In order to support SR-IOV and eventually VMDq it is necessary to set 4038 * the VMOLR to enable the appropriate modes. Without this workaround 4039 * we will have issues with VLAN tag stripping not being done for frames 4040 * that are only arriving because we are the default pool 4041 */ 4042 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 4043 return; 4044 4045 vmolr |= rd32(E1000_VMOLR(vfn)) & 4046 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 4047 wr32(E1000_VMOLR(vfn), vmolr); 4048 igb_restore_vf_multicasts(adapter); 4049 } 4050 4051 static void igb_check_wvbr(struct igb_adapter *adapter) 4052 { 4053 struct e1000_hw *hw = &adapter->hw; 4054 u32 wvbr = 0; 4055 4056 switch (hw->mac.type) { 4057 case e1000_82576: 4058 case e1000_i350: 4059 wvbr = rd32(E1000_WVBR); 4060 if (!wvbr) 4061 return; 4062 break; 4063 default: 4064 break; 4065 } 4066 4067 adapter->wvbr |= wvbr; 4068 } 4069 4070 #define IGB_STAGGERED_QUEUE_OFFSET 8 4071 4072 static void igb_spoof_check(struct igb_adapter *adapter) 4073 { 4074 int j; 4075 4076 if (!adapter->wvbr) 4077 return; 4078 4079 for (j = 0; j < adapter->vfs_allocated_count; j++) { 4080 if (adapter->wvbr & (1 << j) || 4081 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) { 4082 dev_warn(&adapter->pdev->dev, 4083 "Spoof event(s) detected on VF %d\n", j); 4084 adapter->wvbr &= 4085 ~((1 << j) | 4086 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))); 4087 } 4088 } 4089 } 4090 4091 /* Need to wait a few seconds after link up to get diagnostic information from 4092 * the phy 4093 */ 4094 static void igb_update_phy_info(unsigned long data) 4095 { 4096 struct igb_adapter *adapter = (struct igb_adapter *) data; 4097 igb_get_phy_info(&adapter->hw); 4098 } 4099 4100 /** 4101 * igb_has_link - check shared code for link and determine up/down 4102 * @adapter: pointer to driver private info 4103 **/ 4104 bool igb_has_link(struct igb_adapter *adapter) 4105 { 4106 struct e1000_hw *hw = &adapter->hw; 4107 bool link_active = false; 4108 4109 /* get_link_status is set on LSC (link status) interrupt or 4110 * rx sequence error interrupt. get_link_status will stay 4111 * false until the e1000_check_for_link establishes link 4112 * for copper adapters ONLY 4113 */ 4114 switch (hw->phy.media_type) { 4115 case e1000_media_type_copper: 4116 if (!hw->mac.get_link_status) 4117 return true; 4118 case e1000_media_type_internal_serdes: 4119 hw->mac.ops.check_for_link(hw); 4120 link_active = !hw->mac.get_link_status; 4121 break; 4122 default: 4123 case e1000_media_type_unknown: 4124 break; 4125 } 4126 4127 if (((hw->mac.type == e1000_i210) || 4128 (hw->mac.type == e1000_i211)) && 4129 (hw->phy.id == I210_I_PHY_ID)) { 4130 if (!netif_carrier_ok(adapter->netdev)) { 4131 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4132 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 4133 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 4134 adapter->link_check_timeout = jiffies; 4135 } 4136 } 4137 4138 return link_active; 4139 } 4140 4141 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 4142 { 4143 bool ret = false; 4144 u32 ctrl_ext, thstat; 4145 4146 /* check for thermal sensor event on i350 copper only */ 4147 if (hw->mac.type == e1000_i350) { 4148 thstat = rd32(E1000_THSTAT); 4149 ctrl_ext = rd32(E1000_CTRL_EXT); 4150 4151 if ((hw->phy.media_type == e1000_media_type_copper) && 4152 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 4153 ret = !!(thstat & event); 4154 } 4155 4156 return ret; 4157 } 4158 4159 /** 4160 * igb_check_lvmmc - check for malformed packets received 4161 * and indicated in LVMMC register 4162 * @adapter: pointer to adapter 4163 **/ 4164 static void igb_check_lvmmc(struct igb_adapter *adapter) 4165 { 4166 struct e1000_hw *hw = &adapter->hw; 4167 u32 lvmmc; 4168 4169 lvmmc = rd32(E1000_LVMMC); 4170 if (lvmmc) { 4171 if (unlikely(net_ratelimit())) { 4172 netdev_warn(adapter->netdev, 4173 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 4174 lvmmc); 4175 } 4176 } 4177 } 4178 4179 /** 4180 * igb_watchdog - Timer Call-back 4181 * @data: pointer to adapter cast into an unsigned long 4182 **/ 4183 static void igb_watchdog(unsigned long data) 4184 { 4185 struct igb_adapter *adapter = (struct igb_adapter *)data; 4186 /* Do the rest outside of interrupt context */ 4187 schedule_work(&adapter->watchdog_task); 4188 } 4189 4190 static void igb_watchdog_task(struct work_struct *work) 4191 { 4192 struct igb_adapter *adapter = container_of(work, 4193 struct igb_adapter, 4194 watchdog_task); 4195 struct e1000_hw *hw = &adapter->hw; 4196 struct e1000_phy_info *phy = &hw->phy; 4197 struct net_device *netdev = adapter->netdev; 4198 u32 link; 4199 int i; 4200 u32 connsw; 4201 4202 link = igb_has_link(adapter); 4203 4204 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 4205 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 4206 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4207 else 4208 link = false; 4209 } 4210 4211 /* Force link down if we have fiber to swap to */ 4212 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4213 if (hw->phy.media_type == e1000_media_type_copper) { 4214 connsw = rd32(E1000_CONNSW); 4215 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 4216 link = 0; 4217 } 4218 } 4219 if (link) { 4220 /* Perform a reset if the media type changed. */ 4221 if (hw->dev_spec._82575.media_changed) { 4222 hw->dev_spec._82575.media_changed = false; 4223 adapter->flags |= IGB_FLAG_MEDIA_RESET; 4224 igb_reset(adapter); 4225 } 4226 /* Cancel scheduled suspend requests. */ 4227 pm_runtime_resume(netdev->dev.parent); 4228 4229 if (!netif_carrier_ok(netdev)) { 4230 u32 ctrl; 4231 4232 hw->mac.ops.get_speed_and_duplex(hw, 4233 &adapter->link_speed, 4234 &adapter->link_duplex); 4235 4236 ctrl = rd32(E1000_CTRL); 4237 /* Links status message must follow this format */ 4238 netdev_info(netdev, 4239 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 4240 netdev->name, 4241 adapter->link_speed, 4242 adapter->link_duplex == FULL_DUPLEX ? 4243 "Full" : "Half", 4244 (ctrl & E1000_CTRL_TFCE) && 4245 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 4246 (ctrl & E1000_CTRL_RFCE) ? "RX" : 4247 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 4248 4249 /* disable EEE if enabled */ 4250 if ((adapter->flags & IGB_FLAG_EEE) && 4251 (adapter->link_duplex == HALF_DUPLEX)) { 4252 dev_info(&adapter->pdev->dev, 4253 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 4254 adapter->hw.dev_spec._82575.eee_disable = true; 4255 adapter->flags &= ~IGB_FLAG_EEE; 4256 } 4257 4258 /* check if SmartSpeed worked */ 4259 igb_check_downshift(hw); 4260 if (phy->speed_downgraded) 4261 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 4262 4263 /* check for thermal sensor event */ 4264 if (igb_thermal_sensor_event(hw, 4265 E1000_THSTAT_LINK_THROTTLE)) 4266 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 4267 4268 /* adjust timeout factor according to speed/duplex */ 4269 adapter->tx_timeout_factor = 1; 4270 switch (adapter->link_speed) { 4271 case SPEED_10: 4272 adapter->tx_timeout_factor = 14; 4273 break; 4274 case SPEED_100: 4275 /* maybe add some timeout factor ? */ 4276 break; 4277 } 4278 4279 netif_carrier_on(netdev); 4280 4281 igb_ping_all_vfs(adapter); 4282 igb_check_vf_rate_limit(adapter); 4283 4284 /* link state has changed, schedule phy info update */ 4285 if (!test_bit(__IGB_DOWN, &adapter->state)) 4286 mod_timer(&adapter->phy_info_timer, 4287 round_jiffies(jiffies + 2 * HZ)); 4288 } 4289 } else { 4290 if (netif_carrier_ok(netdev)) { 4291 adapter->link_speed = 0; 4292 adapter->link_duplex = 0; 4293 4294 /* check for thermal sensor event */ 4295 if (igb_thermal_sensor_event(hw, 4296 E1000_THSTAT_PWR_DOWN)) { 4297 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 4298 } 4299 4300 /* Links status message must follow this format */ 4301 netdev_info(netdev, "igb: %s NIC Link is Down\n", 4302 netdev->name); 4303 netif_carrier_off(netdev); 4304 4305 igb_ping_all_vfs(adapter); 4306 4307 /* link state has changed, schedule phy info update */ 4308 if (!test_bit(__IGB_DOWN, &adapter->state)) 4309 mod_timer(&adapter->phy_info_timer, 4310 round_jiffies(jiffies + 2 * HZ)); 4311 4312 /* link is down, time to check for alternate media */ 4313 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4314 igb_check_swap_media(adapter); 4315 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4316 schedule_work(&adapter->reset_task); 4317 /* return immediately */ 4318 return; 4319 } 4320 } 4321 pm_schedule_suspend(netdev->dev.parent, 4322 MSEC_PER_SEC * 5); 4323 4324 /* also check for alternate media here */ 4325 } else if (!netif_carrier_ok(netdev) && 4326 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 4327 igb_check_swap_media(adapter); 4328 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4329 schedule_work(&adapter->reset_task); 4330 /* return immediately */ 4331 return; 4332 } 4333 } 4334 } 4335 4336 spin_lock(&adapter->stats64_lock); 4337 igb_update_stats(adapter, &adapter->stats64); 4338 spin_unlock(&adapter->stats64_lock); 4339 4340 for (i = 0; i < adapter->num_tx_queues; i++) { 4341 struct igb_ring *tx_ring = adapter->tx_ring[i]; 4342 if (!netif_carrier_ok(netdev)) { 4343 /* We've lost link, so the controller stops DMA, 4344 * but we've got queued Tx work that's never going 4345 * to get done, so reset controller to flush Tx. 4346 * (Do the reset outside of interrupt context). 4347 */ 4348 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 4349 adapter->tx_timeout_count++; 4350 schedule_work(&adapter->reset_task); 4351 /* return immediately since reset is imminent */ 4352 return; 4353 } 4354 } 4355 4356 /* Force detection of hung controller every watchdog period */ 4357 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 4358 } 4359 4360 /* Cause software interrupt to ensure Rx ring is cleaned */ 4361 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 4362 u32 eics = 0; 4363 4364 for (i = 0; i < adapter->num_q_vectors; i++) 4365 eics |= adapter->q_vector[i]->eims_value; 4366 wr32(E1000_EICS, eics); 4367 } else { 4368 wr32(E1000_ICS, E1000_ICS_RXDMT0); 4369 } 4370 4371 igb_spoof_check(adapter); 4372 igb_ptp_rx_hang(adapter); 4373 4374 /* Check LVMMC register on i350/i354 only */ 4375 if ((adapter->hw.mac.type == e1000_i350) || 4376 (adapter->hw.mac.type == e1000_i354)) 4377 igb_check_lvmmc(adapter); 4378 4379 /* Reset the timer */ 4380 if (!test_bit(__IGB_DOWN, &adapter->state)) { 4381 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 4382 mod_timer(&adapter->watchdog_timer, 4383 round_jiffies(jiffies + HZ)); 4384 else 4385 mod_timer(&adapter->watchdog_timer, 4386 round_jiffies(jiffies + 2 * HZ)); 4387 } 4388 } 4389 4390 enum latency_range { 4391 lowest_latency = 0, 4392 low_latency = 1, 4393 bulk_latency = 2, 4394 latency_invalid = 255 4395 }; 4396 4397 /** 4398 * igb_update_ring_itr - update the dynamic ITR value based on packet size 4399 * @q_vector: pointer to q_vector 4400 * 4401 * Stores a new ITR value based on strictly on packet size. This 4402 * algorithm is less sophisticated than that used in igb_update_itr, 4403 * due to the difficulty of synchronizing statistics across multiple 4404 * receive rings. The divisors and thresholds used by this function 4405 * were determined based on theoretical maximum wire speed and testing 4406 * data, in order to minimize response time while increasing bulk 4407 * throughput. 4408 * This functionality is controlled by ethtool's coalescing settings. 4409 * NOTE: This function is called only when operating in a multiqueue 4410 * receive environment. 4411 **/ 4412 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 4413 { 4414 int new_val = q_vector->itr_val; 4415 int avg_wire_size = 0; 4416 struct igb_adapter *adapter = q_vector->adapter; 4417 unsigned int packets; 4418 4419 /* For non-gigabit speeds, just fix the interrupt rate at 4000 4420 * ints/sec - ITR timer value of 120 ticks. 4421 */ 4422 if (adapter->link_speed != SPEED_1000) { 4423 new_val = IGB_4K_ITR; 4424 goto set_itr_val; 4425 } 4426 4427 packets = q_vector->rx.total_packets; 4428 if (packets) 4429 avg_wire_size = q_vector->rx.total_bytes / packets; 4430 4431 packets = q_vector->tx.total_packets; 4432 if (packets) 4433 avg_wire_size = max_t(u32, avg_wire_size, 4434 q_vector->tx.total_bytes / packets); 4435 4436 /* if avg_wire_size isn't set no work was done */ 4437 if (!avg_wire_size) 4438 goto clear_counts; 4439 4440 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 4441 avg_wire_size += 24; 4442 4443 /* Don't starve jumbo frames */ 4444 avg_wire_size = min(avg_wire_size, 3000); 4445 4446 /* Give a little boost to mid-size frames */ 4447 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 4448 new_val = avg_wire_size / 3; 4449 else 4450 new_val = avg_wire_size / 2; 4451 4452 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4453 if (new_val < IGB_20K_ITR && 4454 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4455 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4456 new_val = IGB_20K_ITR; 4457 4458 set_itr_val: 4459 if (new_val != q_vector->itr_val) { 4460 q_vector->itr_val = new_val; 4461 q_vector->set_itr = 1; 4462 } 4463 clear_counts: 4464 q_vector->rx.total_bytes = 0; 4465 q_vector->rx.total_packets = 0; 4466 q_vector->tx.total_bytes = 0; 4467 q_vector->tx.total_packets = 0; 4468 } 4469 4470 /** 4471 * igb_update_itr - update the dynamic ITR value based on statistics 4472 * @q_vector: pointer to q_vector 4473 * @ring_container: ring info to update the itr for 4474 * 4475 * Stores a new ITR value based on packets and byte 4476 * counts during the last interrupt. The advantage of per interrupt 4477 * computation is faster updates and more accurate ITR for the current 4478 * traffic pattern. Constants in this function were computed 4479 * based on theoretical maximum wire speed and thresholds were set based 4480 * on testing data as well as attempting to minimize response time 4481 * while increasing bulk throughput. 4482 * This functionality is controlled by ethtool's coalescing settings. 4483 * NOTE: These calculations are only valid when operating in a single- 4484 * queue environment. 4485 **/ 4486 static void igb_update_itr(struct igb_q_vector *q_vector, 4487 struct igb_ring_container *ring_container) 4488 { 4489 unsigned int packets = ring_container->total_packets; 4490 unsigned int bytes = ring_container->total_bytes; 4491 u8 itrval = ring_container->itr; 4492 4493 /* no packets, exit with status unchanged */ 4494 if (packets == 0) 4495 return; 4496 4497 switch (itrval) { 4498 case lowest_latency: 4499 /* handle TSO and jumbo frames */ 4500 if (bytes/packets > 8000) 4501 itrval = bulk_latency; 4502 else if ((packets < 5) && (bytes > 512)) 4503 itrval = low_latency; 4504 break; 4505 case low_latency: /* 50 usec aka 20000 ints/s */ 4506 if (bytes > 10000) { 4507 /* this if handles the TSO accounting */ 4508 if (bytes/packets > 8000) 4509 itrval = bulk_latency; 4510 else if ((packets < 10) || ((bytes/packets) > 1200)) 4511 itrval = bulk_latency; 4512 else if ((packets > 35)) 4513 itrval = lowest_latency; 4514 } else if (bytes/packets > 2000) { 4515 itrval = bulk_latency; 4516 } else if (packets <= 2 && bytes < 512) { 4517 itrval = lowest_latency; 4518 } 4519 break; 4520 case bulk_latency: /* 250 usec aka 4000 ints/s */ 4521 if (bytes > 25000) { 4522 if (packets > 35) 4523 itrval = low_latency; 4524 } else if (bytes < 1500) { 4525 itrval = low_latency; 4526 } 4527 break; 4528 } 4529 4530 /* clear work counters since we have the values we need */ 4531 ring_container->total_bytes = 0; 4532 ring_container->total_packets = 0; 4533 4534 /* write updated itr to ring container */ 4535 ring_container->itr = itrval; 4536 } 4537 4538 static void igb_set_itr(struct igb_q_vector *q_vector) 4539 { 4540 struct igb_adapter *adapter = q_vector->adapter; 4541 u32 new_itr = q_vector->itr_val; 4542 u8 current_itr = 0; 4543 4544 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 4545 if (adapter->link_speed != SPEED_1000) { 4546 current_itr = 0; 4547 new_itr = IGB_4K_ITR; 4548 goto set_itr_now; 4549 } 4550 4551 igb_update_itr(q_vector, &q_vector->tx); 4552 igb_update_itr(q_vector, &q_vector->rx); 4553 4554 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 4555 4556 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4557 if (current_itr == lowest_latency && 4558 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4559 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4560 current_itr = low_latency; 4561 4562 switch (current_itr) { 4563 /* counts and packets in update_itr are dependent on these numbers */ 4564 case lowest_latency: 4565 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 4566 break; 4567 case low_latency: 4568 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 4569 break; 4570 case bulk_latency: 4571 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 4572 break; 4573 default: 4574 break; 4575 } 4576 4577 set_itr_now: 4578 if (new_itr != q_vector->itr_val) { 4579 /* this attempts to bias the interrupt rate towards Bulk 4580 * by adding intermediate steps when interrupt rate is 4581 * increasing 4582 */ 4583 new_itr = new_itr > q_vector->itr_val ? 4584 max((new_itr * q_vector->itr_val) / 4585 (new_itr + (q_vector->itr_val >> 2)), 4586 new_itr) : new_itr; 4587 /* Don't write the value here; it resets the adapter's 4588 * internal timer, and causes us to delay far longer than 4589 * we should between interrupts. Instead, we write the ITR 4590 * value at the beginning of the next interrupt so the timing 4591 * ends up being correct. 4592 */ 4593 q_vector->itr_val = new_itr; 4594 q_vector->set_itr = 1; 4595 } 4596 } 4597 4598 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 4599 u32 type_tucmd, u32 mss_l4len_idx) 4600 { 4601 struct e1000_adv_tx_context_desc *context_desc; 4602 u16 i = tx_ring->next_to_use; 4603 4604 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 4605 4606 i++; 4607 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 4608 4609 /* set bits to identify this as an advanced context descriptor */ 4610 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 4611 4612 /* For 82575, context index must be unique per ring. */ 4613 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4614 mss_l4len_idx |= tx_ring->reg_idx << 4; 4615 4616 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 4617 context_desc->seqnum_seed = 0; 4618 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 4619 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 4620 } 4621 4622 static int igb_tso(struct igb_ring *tx_ring, 4623 struct igb_tx_buffer *first, 4624 u8 *hdr_len) 4625 { 4626 struct sk_buff *skb = first->skb; 4627 u32 vlan_macip_lens, type_tucmd; 4628 u32 mss_l4len_idx, l4len; 4629 int err; 4630 4631 if (skb->ip_summed != CHECKSUM_PARTIAL) 4632 return 0; 4633 4634 if (!skb_is_gso(skb)) 4635 return 0; 4636 4637 err = skb_cow_head(skb, 0); 4638 if (err < 0) 4639 return err; 4640 4641 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 4642 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 4643 4644 if (first->protocol == htons(ETH_P_IP)) { 4645 struct iphdr *iph = ip_hdr(skb); 4646 iph->tot_len = 0; 4647 iph->check = 0; 4648 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 4649 iph->daddr, 0, 4650 IPPROTO_TCP, 4651 0); 4652 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4653 first->tx_flags |= IGB_TX_FLAGS_TSO | 4654 IGB_TX_FLAGS_CSUM | 4655 IGB_TX_FLAGS_IPV4; 4656 } else if (skb_is_gso_v6(skb)) { 4657 ipv6_hdr(skb)->payload_len = 0; 4658 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 4659 &ipv6_hdr(skb)->daddr, 4660 0, IPPROTO_TCP, 0); 4661 first->tx_flags |= IGB_TX_FLAGS_TSO | 4662 IGB_TX_FLAGS_CSUM; 4663 } 4664 4665 /* compute header lengths */ 4666 l4len = tcp_hdrlen(skb); 4667 *hdr_len = skb_transport_offset(skb) + l4len; 4668 4669 /* update gso size and bytecount with header size */ 4670 first->gso_segs = skb_shinfo(skb)->gso_segs; 4671 first->bytecount += (first->gso_segs - 1) * *hdr_len; 4672 4673 /* MSS L4LEN IDX */ 4674 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT; 4675 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 4676 4677 /* VLAN MACLEN IPLEN */ 4678 vlan_macip_lens = skb_network_header_len(skb); 4679 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4680 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4681 4682 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4683 4684 return 1; 4685 } 4686 4687 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 4688 { 4689 struct sk_buff *skb = first->skb; 4690 u32 vlan_macip_lens = 0; 4691 u32 mss_l4len_idx = 0; 4692 u32 type_tucmd = 0; 4693 4694 if (skb->ip_summed != CHECKSUM_PARTIAL) { 4695 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 4696 return; 4697 } else { 4698 u8 l4_hdr = 0; 4699 4700 switch (first->protocol) { 4701 case htons(ETH_P_IP): 4702 vlan_macip_lens |= skb_network_header_len(skb); 4703 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4704 l4_hdr = ip_hdr(skb)->protocol; 4705 break; 4706 case htons(ETH_P_IPV6): 4707 vlan_macip_lens |= skb_network_header_len(skb); 4708 l4_hdr = ipv6_hdr(skb)->nexthdr; 4709 break; 4710 default: 4711 if (unlikely(net_ratelimit())) { 4712 dev_warn(tx_ring->dev, 4713 "partial checksum but proto=%x!\n", 4714 first->protocol); 4715 } 4716 break; 4717 } 4718 4719 switch (l4_hdr) { 4720 case IPPROTO_TCP: 4721 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP; 4722 mss_l4len_idx = tcp_hdrlen(skb) << 4723 E1000_ADVTXD_L4LEN_SHIFT; 4724 break; 4725 case IPPROTO_SCTP: 4726 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; 4727 mss_l4len_idx = sizeof(struct sctphdr) << 4728 E1000_ADVTXD_L4LEN_SHIFT; 4729 break; 4730 case IPPROTO_UDP: 4731 mss_l4len_idx = sizeof(struct udphdr) << 4732 E1000_ADVTXD_L4LEN_SHIFT; 4733 break; 4734 default: 4735 if (unlikely(net_ratelimit())) { 4736 dev_warn(tx_ring->dev, 4737 "partial checksum but l4 proto=%x!\n", 4738 l4_hdr); 4739 } 4740 break; 4741 } 4742 4743 /* update TX checksum flag */ 4744 first->tx_flags |= IGB_TX_FLAGS_CSUM; 4745 } 4746 4747 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4748 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4749 4750 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4751 } 4752 4753 #define IGB_SET_FLAG(_input, _flag, _result) \ 4754 ((_flag <= _result) ? \ 4755 ((u32)(_input & _flag) * (_result / _flag)) : \ 4756 ((u32)(_input & _flag) / (_flag / _result))) 4757 4758 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 4759 { 4760 /* set type for advanced descriptor with frame checksum insertion */ 4761 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 4762 E1000_ADVTXD_DCMD_DEXT | 4763 E1000_ADVTXD_DCMD_IFCS; 4764 4765 /* set HW vlan bit if vlan is present */ 4766 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 4767 (E1000_ADVTXD_DCMD_VLE)); 4768 4769 /* set segmentation bits for TSO */ 4770 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 4771 (E1000_ADVTXD_DCMD_TSE)); 4772 4773 /* set timestamp bit if present */ 4774 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 4775 (E1000_ADVTXD_MAC_TSTAMP)); 4776 4777 /* insert frame checksum */ 4778 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 4779 4780 return cmd_type; 4781 } 4782 4783 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 4784 union e1000_adv_tx_desc *tx_desc, 4785 u32 tx_flags, unsigned int paylen) 4786 { 4787 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 4788 4789 /* 82575 requires a unique index per ring */ 4790 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4791 olinfo_status |= tx_ring->reg_idx << 4; 4792 4793 /* insert L4 checksum */ 4794 olinfo_status |= IGB_SET_FLAG(tx_flags, 4795 IGB_TX_FLAGS_CSUM, 4796 (E1000_TXD_POPTS_TXSM << 8)); 4797 4798 /* insert IPv4 checksum */ 4799 olinfo_status |= IGB_SET_FLAG(tx_flags, 4800 IGB_TX_FLAGS_IPV4, 4801 (E1000_TXD_POPTS_IXSM << 8)); 4802 4803 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 4804 } 4805 4806 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4807 { 4808 struct net_device *netdev = tx_ring->netdev; 4809 4810 netif_stop_subqueue(netdev, tx_ring->queue_index); 4811 4812 /* Herbert's original patch had: 4813 * smp_mb__after_netif_stop_queue(); 4814 * but since that doesn't exist yet, just open code it. 4815 */ 4816 smp_mb(); 4817 4818 /* We need to check again in a case another CPU has just 4819 * made room available. 4820 */ 4821 if (igb_desc_unused(tx_ring) < size) 4822 return -EBUSY; 4823 4824 /* A reprieve! */ 4825 netif_wake_subqueue(netdev, tx_ring->queue_index); 4826 4827 u64_stats_update_begin(&tx_ring->tx_syncp2); 4828 tx_ring->tx_stats.restart_queue2++; 4829 u64_stats_update_end(&tx_ring->tx_syncp2); 4830 4831 return 0; 4832 } 4833 4834 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4835 { 4836 if (igb_desc_unused(tx_ring) >= size) 4837 return 0; 4838 return __igb_maybe_stop_tx(tx_ring, size); 4839 } 4840 4841 static void igb_tx_map(struct igb_ring *tx_ring, 4842 struct igb_tx_buffer *first, 4843 const u8 hdr_len) 4844 { 4845 struct sk_buff *skb = first->skb; 4846 struct igb_tx_buffer *tx_buffer; 4847 union e1000_adv_tx_desc *tx_desc; 4848 struct skb_frag_struct *frag; 4849 dma_addr_t dma; 4850 unsigned int data_len, size; 4851 u32 tx_flags = first->tx_flags; 4852 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 4853 u16 i = tx_ring->next_to_use; 4854 4855 tx_desc = IGB_TX_DESC(tx_ring, i); 4856 4857 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 4858 4859 size = skb_headlen(skb); 4860 data_len = skb->data_len; 4861 4862 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 4863 4864 tx_buffer = first; 4865 4866 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 4867 if (dma_mapping_error(tx_ring->dev, dma)) 4868 goto dma_error; 4869 4870 /* record length, and DMA address */ 4871 dma_unmap_len_set(tx_buffer, len, size); 4872 dma_unmap_addr_set(tx_buffer, dma, dma); 4873 4874 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4875 4876 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 4877 tx_desc->read.cmd_type_len = 4878 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 4879 4880 i++; 4881 tx_desc++; 4882 if (i == tx_ring->count) { 4883 tx_desc = IGB_TX_DESC(tx_ring, 0); 4884 i = 0; 4885 } 4886 tx_desc->read.olinfo_status = 0; 4887 4888 dma += IGB_MAX_DATA_PER_TXD; 4889 size -= IGB_MAX_DATA_PER_TXD; 4890 4891 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4892 } 4893 4894 if (likely(!data_len)) 4895 break; 4896 4897 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 4898 4899 i++; 4900 tx_desc++; 4901 if (i == tx_ring->count) { 4902 tx_desc = IGB_TX_DESC(tx_ring, 0); 4903 i = 0; 4904 } 4905 tx_desc->read.olinfo_status = 0; 4906 4907 size = skb_frag_size(frag); 4908 data_len -= size; 4909 4910 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 4911 size, DMA_TO_DEVICE); 4912 4913 tx_buffer = &tx_ring->tx_buffer_info[i]; 4914 } 4915 4916 /* write last descriptor with RS and EOP bits */ 4917 cmd_type |= size | IGB_TXD_DCMD; 4918 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 4919 4920 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 4921 4922 /* set the timestamp */ 4923 first->time_stamp = jiffies; 4924 4925 /* Force memory writes to complete before letting h/w know there 4926 * are new descriptors to fetch. (Only applicable for weak-ordered 4927 * memory model archs, such as IA-64). 4928 * 4929 * We also need this memory barrier to make certain all of the 4930 * status bits have been updated before next_to_watch is written. 4931 */ 4932 wmb(); 4933 4934 /* set next_to_watch value indicating a packet is present */ 4935 first->next_to_watch = tx_desc; 4936 4937 i++; 4938 if (i == tx_ring->count) 4939 i = 0; 4940 4941 tx_ring->next_to_use = i; 4942 4943 /* Make sure there is space in the ring for the next send. */ 4944 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 4945 4946 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 4947 writel(i, tx_ring->tail); 4948 4949 /* we need this if more than one processor can write to our tail 4950 * at a time, it synchronizes IO on IA64/Altix systems 4951 */ 4952 mmiowb(); 4953 } 4954 return; 4955 4956 dma_error: 4957 dev_err(tx_ring->dev, "TX DMA map failed\n"); 4958 4959 /* clear dma mappings for failed tx_buffer_info map */ 4960 for (;;) { 4961 tx_buffer = &tx_ring->tx_buffer_info[i]; 4962 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer); 4963 if (tx_buffer == first) 4964 break; 4965 if (i == 0) 4966 i = tx_ring->count; 4967 i--; 4968 } 4969 4970 tx_ring->next_to_use = i; 4971 } 4972 4973 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 4974 struct igb_ring *tx_ring) 4975 { 4976 struct igb_tx_buffer *first; 4977 int tso; 4978 u32 tx_flags = 0; 4979 unsigned short f; 4980 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 4981 __be16 protocol = vlan_get_protocol(skb); 4982 u8 hdr_len = 0; 4983 4984 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 4985 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 4986 * + 2 desc gap to keep tail from touching head, 4987 * + 1 desc for context descriptor, 4988 * otherwise try next time 4989 */ 4990 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 4991 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 4992 4993 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 4994 /* this is a hard error */ 4995 return NETDEV_TX_BUSY; 4996 } 4997 4998 /* record the location of the first descriptor for this packet */ 4999 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 5000 first->skb = skb; 5001 first->bytecount = skb->len; 5002 first->gso_segs = 1; 5003 5004 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 5005 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 5006 5007 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 5008 &adapter->state)) { 5009 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5010 tx_flags |= IGB_TX_FLAGS_TSTAMP; 5011 5012 adapter->ptp_tx_skb = skb_get(skb); 5013 adapter->ptp_tx_start = jiffies; 5014 if (adapter->hw.mac.type == e1000_82576) 5015 schedule_work(&adapter->ptp_tx_work); 5016 } 5017 } 5018 5019 skb_tx_timestamp(skb); 5020 5021 if (skb_vlan_tag_present(skb)) { 5022 tx_flags |= IGB_TX_FLAGS_VLAN; 5023 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 5024 } 5025 5026 /* record initial flags and protocol */ 5027 first->tx_flags = tx_flags; 5028 first->protocol = protocol; 5029 5030 tso = igb_tso(tx_ring, first, &hdr_len); 5031 if (tso < 0) 5032 goto out_drop; 5033 else if (!tso) 5034 igb_tx_csum(tx_ring, first); 5035 5036 igb_tx_map(tx_ring, first, hdr_len); 5037 5038 return NETDEV_TX_OK; 5039 5040 out_drop: 5041 igb_unmap_and_free_tx_resource(tx_ring, first); 5042 5043 return NETDEV_TX_OK; 5044 } 5045 5046 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 5047 struct sk_buff *skb) 5048 { 5049 unsigned int r_idx = skb->queue_mapping; 5050 5051 if (r_idx >= adapter->num_tx_queues) 5052 r_idx = r_idx % adapter->num_tx_queues; 5053 5054 return adapter->tx_ring[r_idx]; 5055 } 5056 5057 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 5058 struct net_device *netdev) 5059 { 5060 struct igb_adapter *adapter = netdev_priv(netdev); 5061 5062 if (test_bit(__IGB_DOWN, &adapter->state)) { 5063 dev_kfree_skb_any(skb); 5064 return NETDEV_TX_OK; 5065 } 5066 5067 if (skb->len <= 0) { 5068 dev_kfree_skb_any(skb); 5069 return NETDEV_TX_OK; 5070 } 5071 5072 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 5073 * in order to meet this minimum size requirement. 5074 */ 5075 if (skb_put_padto(skb, 17)) 5076 return NETDEV_TX_OK; 5077 5078 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 5079 } 5080 5081 /** 5082 * igb_tx_timeout - Respond to a Tx Hang 5083 * @netdev: network interface device structure 5084 **/ 5085 static void igb_tx_timeout(struct net_device *netdev) 5086 { 5087 struct igb_adapter *adapter = netdev_priv(netdev); 5088 struct e1000_hw *hw = &adapter->hw; 5089 5090 /* Do the reset outside of interrupt context */ 5091 adapter->tx_timeout_count++; 5092 5093 if (hw->mac.type >= e1000_82580) 5094 hw->dev_spec._82575.global_device_reset = true; 5095 5096 schedule_work(&adapter->reset_task); 5097 wr32(E1000_EICS, 5098 (adapter->eims_enable_mask & ~adapter->eims_other)); 5099 } 5100 5101 static void igb_reset_task(struct work_struct *work) 5102 { 5103 struct igb_adapter *adapter; 5104 adapter = container_of(work, struct igb_adapter, reset_task); 5105 5106 igb_dump(adapter); 5107 netdev_err(adapter->netdev, "Reset adapter\n"); 5108 igb_reinit_locked(adapter); 5109 } 5110 5111 /** 5112 * igb_get_stats64 - Get System Network Statistics 5113 * @netdev: network interface device structure 5114 * @stats: rtnl_link_stats64 pointer 5115 **/ 5116 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, 5117 struct rtnl_link_stats64 *stats) 5118 { 5119 struct igb_adapter *adapter = netdev_priv(netdev); 5120 5121 spin_lock(&adapter->stats64_lock); 5122 igb_update_stats(adapter, &adapter->stats64); 5123 memcpy(stats, &adapter->stats64, sizeof(*stats)); 5124 spin_unlock(&adapter->stats64_lock); 5125 5126 return stats; 5127 } 5128 5129 /** 5130 * igb_change_mtu - Change the Maximum Transfer Unit 5131 * @netdev: network interface device structure 5132 * @new_mtu: new value for maximum frame size 5133 * 5134 * Returns 0 on success, negative on failure 5135 **/ 5136 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 5137 { 5138 struct igb_adapter *adapter = netdev_priv(netdev); 5139 struct pci_dev *pdev = adapter->pdev; 5140 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 5141 5142 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { 5143 dev_err(&pdev->dev, "Invalid MTU setting\n"); 5144 return -EINVAL; 5145 } 5146 5147 #define MAX_STD_JUMBO_FRAME_SIZE 9238 5148 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { 5149 dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); 5150 return -EINVAL; 5151 } 5152 5153 /* adjust max frame to be at least the size of a standard frame */ 5154 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 5155 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 5156 5157 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 5158 usleep_range(1000, 2000); 5159 5160 /* igb_down has a dependency on max_frame_size */ 5161 adapter->max_frame_size = max_frame; 5162 5163 if (netif_running(netdev)) 5164 igb_down(adapter); 5165 5166 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 5167 netdev->mtu, new_mtu); 5168 netdev->mtu = new_mtu; 5169 5170 if (netif_running(netdev)) 5171 igb_up(adapter); 5172 else 5173 igb_reset(adapter); 5174 5175 clear_bit(__IGB_RESETTING, &adapter->state); 5176 5177 return 0; 5178 } 5179 5180 /** 5181 * igb_update_stats - Update the board statistics counters 5182 * @adapter: board private structure 5183 **/ 5184 void igb_update_stats(struct igb_adapter *adapter, 5185 struct rtnl_link_stats64 *net_stats) 5186 { 5187 struct e1000_hw *hw = &adapter->hw; 5188 struct pci_dev *pdev = adapter->pdev; 5189 u32 reg, mpc; 5190 int i; 5191 u64 bytes, packets; 5192 unsigned int start; 5193 u64 _bytes, _packets; 5194 5195 /* Prevent stats update while adapter is being reset, or if the pci 5196 * connection is down. 5197 */ 5198 if (adapter->link_speed == 0) 5199 return; 5200 if (pci_channel_offline(pdev)) 5201 return; 5202 5203 bytes = 0; 5204 packets = 0; 5205 5206 rcu_read_lock(); 5207 for (i = 0; i < adapter->num_rx_queues; i++) { 5208 struct igb_ring *ring = adapter->rx_ring[i]; 5209 u32 rqdpc = rd32(E1000_RQDPC(i)); 5210 if (hw->mac.type >= e1000_i210) 5211 wr32(E1000_RQDPC(i), 0); 5212 5213 if (rqdpc) { 5214 ring->rx_stats.drops += rqdpc; 5215 net_stats->rx_fifo_errors += rqdpc; 5216 } 5217 5218 do { 5219 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 5220 _bytes = ring->rx_stats.bytes; 5221 _packets = ring->rx_stats.packets; 5222 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 5223 bytes += _bytes; 5224 packets += _packets; 5225 } 5226 5227 net_stats->rx_bytes = bytes; 5228 net_stats->rx_packets = packets; 5229 5230 bytes = 0; 5231 packets = 0; 5232 for (i = 0; i < adapter->num_tx_queues; i++) { 5233 struct igb_ring *ring = adapter->tx_ring[i]; 5234 do { 5235 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 5236 _bytes = ring->tx_stats.bytes; 5237 _packets = ring->tx_stats.packets; 5238 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 5239 bytes += _bytes; 5240 packets += _packets; 5241 } 5242 net_stats->tx_bytes = bytes; 5243 net_stats->tx_packets = packets; 5244 rcu_read_unlock(); 5245 5246 /* read stats registers */ 5247 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 5248 adapter->stats.gprc += rd32(E1000_GPRC); 5249 adapter->stats.gorc += rd32(E1000_GORCL); 5250 rd32(E1000_GORCH); /* clear GORCL */ 5251 adapter->stats.bprc += rd32(E1000_BPRC); 5252 adapter->stats.mprc += rd32(E1000_MPRC); 5253 adapter->stats.roc += rd32(E1000_ROC); 5254 5255 adapter->stats.prc64 += rd32(E1000_PRC64); 5256 adapter->stats.prc127 += rd32(E1000_PRC127); 5257 adapter->stats.prc255 += rd32(E1000_PRC255); 5258 adapter->stats.prc511 += rd32(E1000_PRC511); 5259 adapter->stats.prc1023 += rd32(E1000_PRC1023); 5260 adapter->stats.prc1522 += rd32(E1000_PRC1522); 5261 adapter->stats.symerrs += rd32(E1000_SYMERRS); 5262 adapter->stats.sec += rd32(E1000_SEC); 5263 5264 mpc = rd32(E1000_MPC); 5265 adapter->stats.mpc += mpc; 5266 net_stats->rx_fifo_errors += mpc; 5267 adapter->stats.scc += rd32(E1000_SCC); 5268 adapter->stats.ecol += rd32(E1000_ECOL); 5269 adapter->stats.mcc += rd32(E1000_MCC); 5270 adapter->stats.latecol += rd32(E1000_LATECOL); 5271 adapter->stats.dc += rd32(E1000_DC); 5272 adapter->stats.rlec += rd32(E1000_RLEC); 5273 adapter->stats.xonrxc += rd32(E1000_XONRXC); 5274 adapter->stats.xontxc += rd32(E1000_XONTXC); 5275 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 5276 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 5277 adapter->stats.fcruc += rd32(E1000_FCRUC); 5278 adapter->stats.gptc += rd32(E1000_GPTC); 5279 adapter->stats.gotc += rd32(E1000_GOTCL); 5280 rd32(E1000_GOTCH); /* clear GOTCL */ 5281 adapter->stats.rnbc += rd32(E1000_RNBC); 5282 adapter->stats.ruc += rd32(E1000_RUC); 5283 adapter->stats.rfc += rd32(E1000_RFC); 5284 adapter->stats.rjc += rd32(E1000_RJC); 5285 adapter->stats.tor += rd32(E1000_TORH); 5286 adapter->stats.tot += rd32(E1000_TOTH); 5287 adapter->stats.tpr += rd32(E1000_TPR); 5288 5289 adapter->stats.ptc64 += rd32(E1000_PTC64); 5290 adapter->stats.ptc127 += rd32(E1000_PTC127); 5291 adapter->stats.ptc255 += rd32(E1000_PTC255); 5292 adapter->stats.ptc511 += rd32(E1000_PTC511); 5293 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 5294 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 5295 5296 adapter->stats.mptc += rd32(E1000_MPTC); 5297 adapter->stats.bptc += rd32(E1000_BPTC); 5298 5299 adapter->stats.tpt += rd32(E1000_TPT); 5300 adapter->stats.colc += rd32(E1000_COLC); 5301 5302 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 5303 /* read internal phy specific stats */ 5304 reg = rd32(E1000_CTRL_EXT); 5305 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 5306 adapter->stats.rxerrc += rd32(E1000_RXERRC); 5307 5308 /* this stat has invalid values on i210/i211 */ 5309 if ((hw->mac.type != e1000_i210) && 5310 (hw->mac.type != e1000_i211)) 5311 adapter->stats.tncrs += rd32(E1000_TNCRS); 5312 } 5313 5314 adapter->stats.tsctc += rd32(E1000_TSCTC); 5315 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 5316 5317 adapter->stats.iac += rd32(E1000_IAC); 5318 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 5319 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 5320 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 5321 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 5322 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 5323 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 5324 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 5325 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 5326 5327 /* Fill out the OS statistics structure */ 5328 net_stats->multicast = adapter->stats.mprc; 5329 net_stats->collisions = adapter->stats.colc; 5330 5331 /* Rx Errors */ 5332 5333 /* RLEC on some newer hardware can be incorrect so build 5334 * our own version based on RUC and ROC 5335 */ 5336 net_stats->rx_errors = adapter->stats.rxerrc + 5337 adapter->stats.crcerrs + adapter->stats.algnerrc + 5338 adapter->stats.ruc + adapter->stats.roc + 5339 adapter->stats.cexterr; 5340 net_stats->rx_length_errors = adapter->stats.ruc + 5341 adapter->stats.roc; 5342 net_stats->rx_crc_errors = adapter->stats.crcerrs; 5343 net_stats->rx_frame_errors = adapter->stats.algnerrc; 5344 net_stats->rx_missed_errors = adapter->stats.mpc; 5345 5346 /* Tx Errors */ 5347 net_stats->tx_errors = adapter->stats.ecol + 5348 adapter->stats.latecol; 5349 net_stats->tx_aborted_errors = adapter->stats.ecol; 5350 net_stats->tx_window_errors = adapter->stats.latecol; 5351 net_stats->tx_carrier_errors = adapter->stats.tncrs; 5352 5353 /* Tx Dropped needs to be maintained elsewhere */ 5354 5355 /* Management Stats */ 5356 adapter->stats.mgptc += rd32(E1000_MGTPTC); 5357 adapter->stats.mgprc += rd32(E1000_MGTPRC); 5358 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 5359 5360 /* OS2BMC Stats */ 5361 reg = rd32(E1000_MANC); 5362 if (reg & E1000_MANC_EN_BMC2OS) { 5363 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 5364 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 5365 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 5366 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 5367 } 5368 } 5369 5370 static void igb_tsync_interrupt(struct igb_adapter *adapter) 5371 { 5372 struct e1000_hw *hw = &adapter->hw; 5373 struct ptp_clock_event event; 5374 struct timespec ts; 5375 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR); 5376 5377 if (tsicr & TSINTR_SYS_WRAP) { 5378 event.type = PTP_CLOCK_PPS; 5379 if (adapter->ptp_caps.pps) 5380 ptp_clock_event(adapter->ptp_clock, &event); 5381 else 5382 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP"); 5383 ack |= TSINTR_SYS_WRAP; 5384 } 5385 5386 if (tsicr & E1000_TSICR_TXTS) { 5387 /* retrieve hardware timestamp */ 5388 schedule_work(&adapter->ptp_tx_work); 5389 ack |= E1000_TSICR_TXTS; 5390 } 5391 5392 if (tsicr & TSINTR_TT0) { 5393 spin_lock(&adapter->tmreg_lock); 5394 ts = timespec_add(adapter->perout[0].start, 5395 adapter->perout[0].period); 5396 wr32(E1000_TRGTTIML0, ts.tv_nsec); 5397 wr32(E1000_TRGTTIMH0, ts.tv_sec); 5398 tsauxc = rd32(E1000_TSAUXC); 5399 tsauxc |= TSAUXC_EN_TT0; 5400 wr32(E1000_TSAUXC, tsauxc); 5401 adapter->perout[0].start = ts; 5402 spin_unlock(&adapter->tmreg_lock); 5403 ack |= TSINTR_TT0; 5404 } 5405 5406 if (tsicr & TSINTR_TT1) { 5407 spin_lock(&adapter->tmreg_lock); 5408 ts = timespec_add(adapter->perout[1].start, 5409 adapter->perout[1].period); 5410 wr32(E1000_TRGTTIML1, ts.tv_nsec); 5411 wr32(E1000_TRGTTIMH1, ts.tv_sec); 5412 tsauxc = rd32(E1000_TSAUXC); 5413 tsauxc |= TSAUXC_EN_TT1; 5414 wr32(E1000_TSAUXC, tsauxc); 5415 adapter->perout[1].start = ts; 5416 spin_unlock(&adapter->tmreg_lock); 5417 ack |= TSINTR_TT1; 5418 } 5419 5420 if (tsicr & TSINTR_AUTT0) { 5421 nsec = rd32(E1000_AUXSTMPL0); 5422 sec = rd32(E1000_AUXSTMPH0); 5423 event.type = PTP_CLOCK_EXTTS; 5424 event.index = 0; 5425 event.timestamp = sec * 1000000000ULL + nsec; 5426 ptp_clock_event(adapter->ptp_clock, &event); 5427 ack |= TSINTR_AUTT0; 5428 } 5429 5430 if (tsicr & TSINTR_AUTT1) { 5431 nsec = rd32(E1000_AUXSTMPL1); 5432 sec = rd32(E1000_AUXSTMPH1); 5433 event.type = PTP_CLOCK_EXTTS; 5434 event.index = 1; 5435 event.timestamp = sec * 1000000000ULL + nsec; 5436 ptp_clock_event(adapter->ptp_clock, &event); 5437 ack |= TSINTR_AUTT1; 5438 } 5439 5440 /* acknowledge the interrupts */ 5441 wr32(E1000_TSICR, ack); 5442 } 5443 5444 static irqreturn_t igb_msix_other(int irq, void *data) 5445 { 5446 struct igb_adapter *adapter = data; 5447 struct e1000_hw *hw = &adapter->hw; 5448 u32 icr = rd32(E1000_ICR); 5449 /* reading ICR causes bit 31 of EICR to be cleared */ 5450 5451 if (icr & E1000_ICR_DRSTA) 5452 schedule_work(&adapter->reset_task); 5453 5454 if (icr & E1000_ICR_DOUTSYNC) { 5455 /* HW is reporting DMA is out of sync */ 5456 adapter->stats.doosync++; 5457 /* The DMA Out of Sync is also indication of a spoof event 5458 * in IOV mode. Check the Wrong VM Behavior register to 5459 * see if it is really a spoof event. 5460 */ 5461 igb_check_wvbr(adapter); 5462 } 5463 5464 /* Check for a mailbox event */ 5465 if (icr & E1000_ICR_VMMB) 5466 igb_msg_task(adapter); 5467 5468 if (icr & E1000_ICR_LSC) { 5469 hw->mac.get_link_status = 1; 5470 /* guard against interrupt when we're going down */ 5471 if (!test_bit(__IGB_DOWN, &adapter->state)) 5472 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5473 } 5474 5475 if (icr & E1000_ICR_TS) 5476 igb_tsync_interrupt(adapter); 5477 5478 wr32(E1000_EIMS, adapter->eims_other); 5479 5480 return IRQ_HANDLED; 5481 } 5482 5483 static void igb_write_itr(struct igb_q_vector *q_vector) 5484 { 5485 struct igb_adapter *adapter = q_vector->adapter; 5486 u32 itr_val = q_vector->itr_val & 0x7FFC; 5487 5488 if (!q_vector->set_itr) 5489 return; 5490 5491 if (!itr_val) 5492 itr_val = 0x4; 5493 5494 if (adapter->hw.mac.type == e1000_82575) 5495 itr_val |= itr_val << 16; 5496 else 5497 itr_val |= E1000_EITR_CNT_IGNR; 5498 5499 writel(itr_val, q_vector->itr_register); 5500 q_vector->set_itr = 0; 5501 } 5502 5503 static irqreturn_t igb_msix_ring(int irq, void *data) 5504 { 5505 struct igb_q_vector *q_vector = data; 5506 5507 /* Write the ITR value calculated from the previous interrupt. */ 5508 igb_write_itr(q_vector); 5509 5510 napi_schedule(&q_vector->napi); 5511 5512 return IRQ_HANDLED; 5513 } 5514 5515 #ifdef CONFIG_IGB_DCA 5516 static void igb_update_tx_dca(struct igb_adapter *adapter, 5517 struct igb_ring *tx_ring, 5518 int cpu) 5519 { 5520 struct e1000_hw *hw = &adapter->hw; 5521 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 5522 5523 if (hw->mac.type != e1000_82575) 5524 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 5525 5526 /* We can enable relaxed ordering for reads, but not writes when 5527 * DCA is enabled. This is due to a known issue in some chipsets 5528 * which will cause the DCA tag to be cleared. 5529 */ 5530 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 5531 E1000_DCA_TXCTRL_DATA_RRO_EN | 5532 E1000_DCA_TXCTRL_DESC_DCA_EN; 5533 5534 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 5535 } 5536 5537 static void igb_update_rx_dca(struct igb_adapter *adapter, 5538 struct igb_ring *rx_ring, 5539 int cpu) 5540 { 5541 struct e1000_hw *hw = &adapter->hw; 5542 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 5543 5544 if (hw->mac.type != e1000_82575) 5545 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 5546 5547 /* We can enable relaxed ordering for reads, but not writes when 5548 * DCA is enabled. This is due to a known issue in some chipsets 5549 * which will cause the DCA tag to be cleared. 5550 */ 5551 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 5552 E1000_DCA_RXCTRL_DESC_DCA_EN; 5553 5554 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 5555 } 5556 5557 static void igb_update_dca(struct igb_q_vector *q_vector) 5558 { 5559 struct igb_adapter *adapter = q_vector->adapter; 5560 int cpu = get_cpu(); 5561 5562 if (q_vector->cpu == cpu) 5563 goto out_no_update; 5564 5565 if (q_vector->tx.ring) 5566 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 5567 5568 if (q_vector->rx.ring) 5569 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 5570 5571 q_vector->cpu = cpu; 5572 out_no_update: 5573 put_cpu(); 5574 } 5575 5576 static void igb_setup_dca(struct igb_adapter *adapter) 5577 { 5578 struct e1000_hw *hw = &adapter->hw; 5579 int i; 5580 5581 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 5582 return; 5583 5584 /* Always use CB2 mode, difference is masked in the CB driver. */ 5585 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 5586 5587 for (i = 0; i < adapter->num_q_vectors; i++) { 5588 adapter->q_vector[i]->cpu = -1; 5589 igb_update_dca(adapter->q_vector[i]); 5590 } 5591 } 5592 5593 static int __igb_notify_dca(struct device *dev, void *data) 5594 { 5595 struct net_device *netdev = dev_get_drvdata(dev); 5596 struct igb_adapter *adapter = netdev_priv(netdev); 5597 struct pci_dev *pdev = adapter->pdev; 5598 struct e1000_hw *hw = &adapter->hw; 5599 unsigned long event = *(unsigned long *)data; 5600 5601 switch (event) { 5602 case DCA_PROVIDER_ADD: 5603 /* if already enabled, don't do it again */ 5604 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 5605 break; 5606 if (dca_add_requester(dev) == 0) { 5607 adapter->flags |= IGB_FLAG_DCA_ENABLED; 5608 dev_info(&pdev->dev, "DCA enabled\n"); 5609 igb_setup_dca(adapter); 5610 break; 5611 } 5612 /* Fall Through since DCA is disabled. */ 5613 case DCA_PROVIDER_REMOVE: 5614 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 5615 /* without this a class_device is left 5616 * hanging around in the sysfs model 5617 */ 5618 dca_remove_requester(dev); 5619 dev_info(&pdev->dev, "DCA disabled\n"); 5620 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 5621 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 5622 } 5623 break; 5624 } 5625 5626 return 0; 5627 } 5628 5629 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 5630 void *p) 5631 { 5632 int ret_val; 5633 5634 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 5635 __igb_notify_dca); 5636 5637 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 5638 } 5639 #endif /* CONFIG_IGB_DCA */ 5640 5641 #ifdef CONFIG_PCI_IOV 5642 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 5643 { 5644 unsigned char mac_addr[ETH_ALEN]; 5645 5646 eth_zero_addr(mac_addr); 5647 igb_set_vf_mac(adapter, vf, mac_addr); 5648 5649 /* By default spoof check is enabled for all VFs */ 5650 adapter->vf_data[vf].spoofchk_enabled = true; 5651 5652 return 0; 5653 } 5654 5655 #endif 5656 static void igb_ping_all_vfs(struct igb_adapter *adapter) 5657 { 5658 struct e1000_hw *hw = &adapter->hw; 5659 u32 ping; 5660 int i; 5661 5662 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 5663 ping = E1000_PF_CONTROL_MSG; 5664 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 5665 ping |= E1000_VT_MSGTYPE_CTS; 5666 igb_write_mbx(hw, &ping, 1, i); 5667 } 5668 } 5669 5670 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5671 { 5672 struct e1000_hw *hw = &adapter->hw; 5673 u32 vmolr = rd32(E1000_VMOLR(vf)); 5674 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5675 5676 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 5677 IGB_VF_FLAG_MULTI_PROMISC); 5678 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5679 5680 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 5681 vmolr |= E1000_VMOLR_MPME; 5682 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 5683 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 5684 } else { 5685 /* if we have hashes and we are clearing a multicast promisc 5686 * flag we need to write the hashes to the MTA as this step 5687 * was previously skipped 5688 */ 5689 if (vf_data->num_vf_mc_hashes > 30) { 5690 vmolr |= E1000_VMOLR_MPME; 5691 } else if (vf_data->num_vf_mc_hashes) { 5692 int j; 5693 5694 vmolr |= E1000_VMOLR_ROMPE; 5695 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5696 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5697 } 5698 } 5699 5700 wr32(E1000_VMOLR(vf), vmolr); 5701 5702 /* there are flags left unprocessed, likely not supported */ 5703 if (*msgbuf & E1000_VT_MSGINFO_MASK) 5704 return -EINVAL; 5705 5706 return 0; 5707 } 5708 5709 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 5710 u32 *msgbuf, u32 vf) 5711 { 5712 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5713 u16 *hash_list = (u16 *)&msgbuf[1]; 5714 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5715 int i; 5716 5717 /* salt away the number of multicast addresses assigned 5718 * to this VF for later use to restore when the PF multi cast 5719 * list changes 5720 */ 5721 vf_data->num_vf_mc_hashes = n; 5722 5723 /* only up to 30 hash values supported */ 5724 if (n > 30) 5725 n = 30; 5726 5727 /* store the hashes for later use */ 5728 for (i = 0; i < n; i++) 5729 vf_data->vf_mc_hashes[i] = hash_list[i]; 5730 5731 /* Flush and reset the mta with the new values */ 5732 igb_set_rx_mode(adapter->netdev); 5733 5734 return 0; 5735 } 5736 5737 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 5738 { 5739 struct e1000_hw *hw = &adapter->hw; 5740 struct vf_data_storage *vf_data; 5741 int i, j; 5742 5743 for (i = 0; i < adapter->vfs_allocated_count; i++) { 5744 u32 vmolr = rd32(E1000_VMOLR(i)); 5745 5746 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5747 5748 vf_data = &adapter->vf_data[i]; 5749 5750 if ((vf_data->num_vf_mc_hashes > 30) || 5751 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 5752 vmolr |= E1000_VMOLR_MPME; 5753 } else if (vf_data->num_vf_mc_hashes) { 5754 vmolr |= E1000_VMOLR_ROMPE; 5755 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5756 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5757 } 5758 wr32(E1000_VMOLR(i), vmolr); 5759 } 5760 } 5761 5762 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 5763 { 5764 struct e1000_hw *hw = &adapter->hw; 5765 u32 pool_mask, reg, vid; 5766 int i; 5767 5768 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5769 5770 /* Find the vlan filter for this id */ 5771 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5772 reg = rd32(E1000_VLVF(i)); 5773 5774 /* remove the vf from the pool */ 5775 reg &= ~pool_mask; 5776 5777 /* if pool is empty then remove entry from vfta */ 5778 if (!(reg & E1000_VLVF_POOLSEL_MASK) && 5779 (reg & E1000_VLVF_VLANID_ENABLE)) { 5780 reg = 0; 5781 vid = reg & E1000_VLVF_VLANID_MASK; 5782 igb_vfta_set(hw, vid, false); 5783 } 5784 5785 wr32(E1000_VLVF(i), reg); 5786 } 5787 5788 adapter->vf_data[vf].vlans_enabled = 0; 5789 } 5790 5791 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) 5792 { 5793 struct e1000_hw *hw = &adapter->hw; 5794 u32 reg, i; 5795 5796 /* The vlvf table only exists on 82576 hardware and newer */ 5797 if (hw->mac.type < e1000_82576) 5798 return -1; 5799 5800 /* we only need to do this if VMDq is enabled */ 5801 if (!adapter->vfs_allocated_count) 5802 return -1; 5803 5804 /* Find the vlan filter for this id */ 5805 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5806 reg = rd32(E1000_VLVF(i)); 5807 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5808 vid == (reg & E1000_VLVF_VLANID_MASK)) 5809 break; 5810 } 5811 5812 if (add) { 5813 if (i == E1000_VLVF_ARRAY_SIZE) { 5814 /* Did not find a matching VLAN ID entry that was 5815 * enabled. Search for a free filter entry, i.e. 5816 * one without the enable bit set 5817 */ 5818 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5819 reg = rd32(E1000_VLVF(i)); 5820 if (!(reg & E1000_VLVF_VLANID_ENABLE)) 5821 break; 5822 } 5823 } 5824 if (i < E1000_VLVF_ARRAY_SIZE) { 5825 /* Found an enabled/available entry */ 5826 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5827 5828 /* if !enabled we need to set this up in vfta */ 5829 if (!(reg & E1000_VLVF_VLANID_ENABLE)) { 5830 /* add VID to filter table */ 5831 igb_vfta_set(hw, vid, true); 5832 reg |= E1000_VLVF_VLANID_ENABLE; 5833 } 5834 reg &= ~E1000_VLVF_VLANID_MASK; 5835 reg |= vid; 5836 wr32(E1000_VLVF(i), reg); 5837 5838 /* do not modify RLPML for PF devices */ 5839 if (vf >= adapter->vfs_allocated_count) 5840 return 0; 5841 5842 if (!adapter->vf_data[vf].vlans_enabled) { 5843 u32 size; 5844 5845 reg = rd32(E1000_VMOLR(vf)); 5846 size = reg & E1000_VMOLR_RLPML_MASK; 5847 size += 4; 5848 reg &= ~E1000_VMOLR_RLPML_MASK; 5849 reg |= size; 5850 wr32(E1000_VMOLR(vf), reg); 5851 } 5852 5853 adapter->vf_data[vf].vlans_enabled++; 5854 } 5855 } else { 5856 if (i < E1000_VLVF_ARRAY_SIZE) { 5857 /* remove vf from the pool */ 5858 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); 5859 /* if pool is empty then remove entry from vfta */ 5860 if (!(reg & E1000_VLVF_POOLSEL_MASK)) { 5861 reg = 0; 5862 igb_vfta_set(hw, vid, false); 5863 } 5864 wr32(E1000_VLVF(i), reg); 5865 5866 /* do not modify RLPML for PF devices */ 5867 if (vf >= adapter->vfs_allocated_count) 5868 return 0; 5869 5870 adapter->vf_data[vf].vlans_enabled--; 5871 if (!adapter->vf_data[vf].vlans_enabled) { 5872 u32 size; 5873 5874 reg = rd32(E1000_VMOLR(vf)); 5875 size = reg & E1000_VMOLR_RLPML_MASK; 5876 size -= 4; 5877 reg &= ~E1000_VMOLR_RLPML_MASK; 5878 reg |= size; 5879 wr32(E1000_VMOLR(vf), reg); 5880 } 5881 } 5882 } 5883 return 0; 5884 } 5885 5886 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 5887 { 5888 struct e1000_hw *hw = &adapter->hw; 5889 5890 if (vid) 5891 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 5892 else 5893 wr32(E1000_VMVIR(vf), 0); 5894 } 5895 5896 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 5897 int vf, u16 vlan, u8 qos) 5898 { 5899 int err = 0; 5900 struct igb_adapter *adapter = netdev_priv(netdev); 5901 5902 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 5903 return -EINVAL; 5904 if (vlan || qos) { 5905 err = igb_vlvf_set(adapter, vlan, !!vlan, vf); 5906 if (err) 5907 goto out; 5908 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 5909 igb_set_vmolr(adapter, vf, !vlan); 5910 adapter->vf_data[vf].pf_vlan = vlan; 5911 adapter->vf_data[vf].pf_qos = qos; 5912 dev_info(&adapter->pdev->dev, 5913 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 5914 if (test_bit(__IGB_DOWN, &adapter->state)) { 5915 dev_warn(&adapter->pdev->dev, 5916 "The VF VLAN has been set, but the PF device is not up.\n"); 5917 dev_warn(&adapter->pdev->dev, 5918 "Bring the PF device up before attempting to use the VF device.\n"); 5919 } 5920 } else { 5921 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, 5922 false, vf); 5923 igb_set_vmvir(adapter, vlan, vf); 5924 igb_set_vmolr(adapter, vf, true); 5925 adapter->vf_data[vf].pf_vlan = 0; 5926 adapter->vf_data[vf].pf_qos = 0; 5927 } 5928 out: 5929 return err; 5930 } 5931 5932 static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid) 5933 { 5934 struct e1000_hw *hw = &adapter->hw; 5935 int i; 5936 u32 reg; 5937 5938 /* Find the vlan filter for this id */ 5939 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5940 reg = rd32(E1000_VLVF(i)); 5941 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5942 vid == (reg & E1000_VLVF_VLANID_MASK)) 5943 break; 5944 } 5945 5946 if (i >= E1000_VLVF_ARRAY_SIZE) 5947 i = -1; 5948 5949 return i; 5950 } 5951 5952 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5953 { 5954 struct e1000_hw *hw = &adapter->hw; 5955 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5956 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 5957 int err = 0; 5958 5959 /* If in promiscuous mode we need to make sure the PF also has 5960 * the VLAN filter set. 5961 */ 5962 if (add && (adapter->netdev->flags & IFF_PROMISC)) 5963 err = igb_vlvf_set(adapter, vid, add, 5964 adapter->vfs_allocated_count); 5965 if (err) 5966 goto out; 5967 5968 err = igb_vlvf_set(adapter, vid, add, vf); 5969 5970 if (err) 5971 goto out; 5972 5973 /* Go through all the checks to see if the VLAN filter should 5974 * be wiped completely. 5975 */ 5976 if (!add && (adapter->netdev->flags & IFF_PROMISC)) { 5977 u32 vlvf, bits; 5978 int regndx = igb_find_vlvf_entry(adapter, vid); 5979 5980 if (regndx < 0) 5981 goto out; 5982 /* See if any other pools are set for this VLAN filter 5983 * entry other than the PF. 5984 */ 5985 vlvf = bits = rd32(E1000_VLVF(regndx)); 5986 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT + 5987 adapter->vfs_allocated_count); 5988 /* If the filter was removed then ensure PF pool bit 5989 * is cleared if the PF only added itself to the pool 5990 * because the PF is in promiscuous mode. 5991 */ 5992 if ((vlvf & VLAN_VID_MASK) == vid && 5993 !test_bit(vid, adapter->active_vlans) && 5994 !bits) 5995 igb_vlvf_set(adapter, vid, add, 5996 adapter->vfs_allocated_count); 5997 } 5998 5999 out: 6000 return err; 6001 } 6002 6003 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 6004 { 6005 /* clear flags - except flag that indicates PF has set the MAC */ 6006 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC; 6007 adapter->vf_data[vf].last_nack = jiffies; 6008 6009 /* reset offloads to defaults */ 6010 igb_set_vmolr(adapter, vf, true); 6011 6012 /* reset vlans for device */ 6013 igb_clear_vf_vfta(adapter, vf); 6014 if (adapter->vf_data[vf].pf_vlan) 6015 igb_ndo_set_vf_vlan(adapter->netdev, vf, 6016 adapter->vf_data[vf].pf_vlan, 6017 adapter->vf_data[vf].pf_qos); 6018 else 6019 igb_clear_vf_vfta(adapter, vf); 6020 6021 /* reset multicast table array for vf */ 6022 adapter->vf_data[vf].num_vf_mc_hashes = 0; 6023 6024 /* Flush and reset the mta with the new values */ 6025 igb_set_rx_mode(adapter->netdev); 6026 } 6027 6028 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 6029 { 6030 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 6031 6032 /* clear mac address as we were hotplug removed/added */ 6033 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 6034 eth_zero_addr(vf_mac); 6035 6036 /* process remaining reset events */ 6037 igb_vf_reset(adapter, vf); 6038 } 6039 6040 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 6041 { 6042 struct e1000_hw *hw = &adapter->hw; 6043 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 6044 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 6045 u32 reg, msgbuf[3]; 6046 u8 *addr = (u8 *)(&msgbuf[1]); 6047 6048 /* process all the same items cleared in a function level reset */ 6049 igb_vf_reset(adapter, vf); 6050 6051 /* set vf mac address */ 6052 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); 6053 6054 /* enable transmit and receive for vf */ 6055 reg = rd32(E1000_VFTE); 6056 wr32(E1000_VFTE, reg | (1 << vf)); 6057 reg = rd32(E1000_VFRE); 6058 wr32(E1000_VFRE, reg | (1 << vf)); 6059 6060 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 6061 6062 /* reply to reset with ack and vf mac address */ 6063 if (!is_zero_ether_addr(vf_mac)) { 6064 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 6065 memcpy(addr, vf_mac, ETH_ALEN); 6066 } else { 6067 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 6068 } 6069 igb_write_mbx(hw, msgbuf, 3, vf); 6070 } 6071 6072 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 6073 { 6074 /* The VF MAC Address is stored in a packed array of bytes 6075 * starting at the second 32 bit word of the msg array 6076 */ 6077 unsigned char *addr = (char *)&msg[1]; 6078 int err = -1; 6079 6080 if (is_valid_ether_addr(addr)) 6081 err = igb_set_vf_mac(adapter, vf, addr); 6082 6083 return err; 6084 } 6085 6086 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 6087 { 6088 struct e1000_hw *hw = &adapter->hw; 6089 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6090 u32 msg = E1000_VT_MSGTYPE_NACK; 6091 6092 /* if device isn't clear to send it shouldn't be reading either */ 6093 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 6094 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 6095 igb_write_mbx(hw, &msg, 1, vf); 6096 vf_data->last_nack = jiffies; 6097 } 6098 } 6099 6100 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 6101 { 6102 struct pci_dev *pdev = adapter->pdev; 6103 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 6104 struct e1000_hw *hw = &adapter->hw; 6105 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6106 s32 retval; 6107 6108 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); 6109 6110 if (retval) { 6111 /* if receive failed revoke VF CTS stats and restart init */ 6112 dev_err(&pdev->dev, "Error receiving message from VF\n"); 6113 vf_data->flags &= ~IGB_VF_FLAG_CTS; 6114 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6115 return; 6116 goto out; 6117 } 6118 6119 /* this is a message we already processed, do nothing */ 6120 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 6121 return; 6122 6123 /* until the vf completes a reset it should not be 6124 * allowed to start any configuration. 6125 */ 6126 if (msgbuf[0] == E1000_VF_RESET) { 6127 igb_vf_reset_msg(adapter, vf); 6128 return; 6129 } 6130 6131 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 6132 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6133 return; 6134 retval = -1; 6135 goto out; 6136 } 6137 6138 switch ((msgbuf[0] & 0xFFFF)) { 6139 case E1000_VF_SET_MAC_ADDR: 6140 retval = -EINVAL; 6141 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) 6142 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 6143 else 6144 dev_warn(&pdev->dev, 6145 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 6146 vf); 6147 break; 6148 case E1000_VF_SET_PROMISC: 6149 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 6150 break; 6151 case E1000_VF_SET_MULTICAST: 6152 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 6153 break; 6154 case E1000_VF_SET_LPE: 6155 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 6156 break; 6157 case E1000_VF_SET_VLAN: 6158 retval = -1; 6159 if (vf_data->pf_vlan) 6160 dev_warn(&pdev->dev, 6161 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 6162 vf); 6163 else 6164 retval = igb_set_vf_vlan(adapter, msgbuf, vf); 6165 break; 6166 default: 6167 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 6168 retval = -1; 6169 break; 6170 } 6171 6172 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 6173 out: 6174 /* notify the VF of the results of what it sent us */ 6175 if (retval) 6176 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 6177 else 6178 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 6179 6180 igb_write_mbx(hw, msgbuf, 1, vf); 6181 } 6182 6183 static void igb_msg_task(struct igb_adapter *adapter) 6184 { 6185 struct e1000_hw *hw = &adapter->hw; 6186 u32 vf; 6187 6188 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 6189 /* process any reset requests */ 6190 if (!igb_check_for_rst(hw, vf)) 6191 igb_vf_reset_event(adapter, vf); 6192 6193 /* process any messages pending */ 6194 if (!igb_check_for_msg(hw, vf)) 6195 igb_rcv_msg_from_vf(adapter, vf); 6196 6197 /* process any acks */ 6198 if (!igb_check_for_ack(hw, vf)) 6199 igb_rcv_ack_from_vf(adapter, vf); 6200 } 6201 } 6202 6203 /** 6204 * igb_set_uta - Set unicast filter table address 6205 * @adapter: board private structure 6206 * 6207 * The unicast table address is a register array of 32-bit registers. 6208 * The table is meant to be used in a way similar to how the MTA is used 6209 * however due to certain limitations in the hardware it is necessary to 6210 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 6211 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 6212 **/ 6213 static void igb_set_uta(struct igb_adapter *adapter) 6214 { 6215 struct e1000_hw *hw = &adapter->hw; 6216 int i; 6217 6218 /* The UTA table only exists on 82576 hardware and newer */ 6219 if (hw->mac.type < e1000_82576) 6220 return; 6221 6222 /* we only need to do this if VMDq is enabled */ 6223 if (!adapter->vfs_allocated_count) 6224 return; 6225 6226 for (i = 0; i < hw->mac.uta_reg_count; i++) 6227 array_wr32(E1000_UTA, i, ~0); 6228 } 6229 6230 /** 6231 * igb_intr_msi - Interrupt Handler 6232 * @irq: interrupt number 6233 * @data: pointer to a network interface device structure 6234 **/ 6235 static irqreturn_t igb_intr_msi(int irq, void *data) 6236 { 6237 struct igb_adapter *adapter = data; 6238 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6239 struct e1000_hw *hw = &adapter->hw; 6240 /* read ICR disables interrupts using IAM */ 6241 u32 icr = rd32(E1000_ICR); 6242 6243 igb_write_itr(q_vector); 6244 6245 if (icr & E1000_ICR_DRSTA) 6246 schedule_work(&adapter->reset_task); 6247 6248 if (icr & E1000_ICR_DOUTSYNC) { 6249 /* HW is reporting DMA is out of sync */ 6250 adapter->stats.doosync++; 6251 } 6252 6253 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6254 hw->mac.get_link_status = 1; 6255 if (!test_bit(__IGB_DOWN, &adapter->state)) 6256 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6257 } 6258 6259 if (icr & E1000_ICR_TS) 6260 igb_tsync_interrupt(adapter); 6261 6262 napi_schedule(&q_vector->napi); 6263 6264 return IRQ_HANDLED; 6265 } 6266 6267 /** 6268 * igb_intr - Legacy Interrupt Handler 6269 * @irq: interrupt number 6270 * @data: pointer to a network interface device structure 6271 **/ 6272 static irqreturn_t igb_intr(int irq, void *data) 6273 { 6274 struct igb_adapter *adapter = data; 6275 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6276 struct e1000_hw *hw = &adapter->hw; 6277 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 6278 * need for the IMC write 6279 */ 6280 u32 icr = rd32(E1000_ICR); 6281 6282 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 6283 * not set, then the adapter didn't send an interrupt 6284 */ 6285 if (!(icr & E1000_ICR_INT_ASSERTED)) 6286 return IRQ_NONE; 6287 6288 igb_write_itr(q_vector); 6289 6290 if (icr & E1000_ICR_DRSTA) 6291 schedule_work(&adapter->reset_task); 6292 6293 if (icr & E1000_ICR_DOUTSYNC) { 6294 /* HW is reporting DMA is out of sync */ 6295 adapter->stats.doosync++; 6296 } 6297 6298 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6299 hw->mac.get_link_status = 1; 6300 /* guard against interrupt when we're going down */ 6301 if (!test_bit(__IGB_DOWN, &adapter->state)) 6302 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6303 } 6304 6305 if (icr & E1000_ICR_TS) 6306 igb_tsync_interrupt(adapter); 6307 6308 napi_schedule(&q_vector->napi); 6309 6310 return IRQ_HANDLED; 6311 } 6312 6313 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 6314 { 6315 struct igb_adapter *adapter = q_vector->adapter; 6316 struct e1000_hw *hw = &adapter->hw; 6317 6318 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 6319 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 6320 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 6321 igb_set_itr(q_vector); 6322 else 6323 igb_update_ring_itr(q_vector); 6324 } 6325 6326 if (!test_bit(__IGB_DOWN, &adapter->state)) { 6327 if (adapter->flags & IGB_FLAG_HAS_MSIX) 6328 wr32(E1000_EIMS, q_vector->eims_value); 6329 else 6330 igb_irq_enable(adapter); 6331 } 6332 } 6333 6334 /** 6335 * igb_poll - NAPI Rx polling callback 6336 * @napi: napi polling structure 6337 * @budget: count of how many packets we should handle 6338 **/ 6339 static int igb_poll(struct napi_struct *napi, int budget) 6340 { 6341 struct igb_q_vector *q_vector = container_of(napi, 6342 struct igb_q_vector, 6343 napi); 6344 bool clean_complete = true; 6345 6346 #ifdef CONFIG_IGB_DCA 6347 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 6348 igb_update_dca(q_vector); 6349 #endif 6350 if (q_vector->tx.ring) 6351 clean_complete = igb_clean_tx_irq(q_vector); 6352 6353 if (q_vector->rx.ring) 6354 clean_complete &= igb_clean_rx_irq(q_vector, budget); 6355 6356 /* If all work not completed, return budget and keep polling */ 6357 if (!clean_complete) 6358 return budget; 6359 6360 /* If not enough Rx work done, exit the polling mode */ 6361 napi_complete(napi); 6362 igb_ring_irq_enable(q_vector); 6363 6364 return 0; 6365 } 6366 6367 /** 6368 * igb_clean_tx_irq - Reclaim resources after transmit completes 6369 * @q_vector: pointer to q_vector containing needed info 6370 * 6371 * returns true if ring is completely cleaned 6372 **/ 6373 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) 6374 { 6375 struct igb_adapter *adapter = q_vector->adapter; 6376 struct igb_ring *tx_ring = q_vector->tx.ring; 6377 struct igb_tx_buffer *tx_buffer; 6378 union e1000_adv_tx_desc *tx_desc; 6379 unsigned int total_bytes = 0, total_packets = 0; 6380 unsigned int budget = q_vector->tx.work_limit; 6381 unsigned int i = tx_ring->next_to_clean; 6382 6383 if (test_bit(__IGB_DOWN, &adapter->state)) 6384 return true; 6385 6386 tx_buffer = &tx_ring->tx_buffer_info[i]; 6387 tx_desc = IGB_TX_DESC(tx_ring, i); 6388 i -= tx_ring->count; 6389 6390 do { 6391 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 6392 6393 /* if next_to_watch is not set then there is no work pending */ 6394 if (!eop_desc) 6395 break; 6396 6397 /* prevent any other reads prior to eop_desc */ 6398 read_barrier_depends(); 6399 6400 /* if DD is not set pending work has not been completed */ 6401 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 6402 break; 6403 6404 /* clear next_to_watch to prevent false hangs */ 6405 tx_buffer->next_to_watch = NULL; 6406 6407 /* update the statistics for this packet */ 6408 total_bytes += tx_buffer->bytecount; 6409 total_packets += tx_buffer->gso_segs; 6410 6411 /* free the skb */ 6412 dev_consume_skb_any(tx_buffer->skb); 6413 6414 /* unmap skb header data */ 6415 dma_unmap_single(tx_ring->dev, 6416 dma_unmap_addr(tx_buffer, dma), 6417 dma_unmap_len(tx_buffer, len), 6418 DMA_TO_DEVICE); 6419 6420 /* clear tx_buffer data */ 6421 tx_buffer->skb = NULL; 6422 dma_unmap_len_set(tx_buffer, len, 0); 6423 6424 /* clear last DMA location and unmap remaining buffers */ 6425 while (tx_desc != eop_desc) { 6426 tx_buffer++; 6427 tx_desc++; 6428 i++; 6429 if (unlikely(!i)) { 6430 i -= tx_ring->count; 6431 tx_buffer = tx_ring->tx_buffer_info; 6432 tx_desc = IGB_TX_DESC(tx_ring, 0); 6433 } 6434 6435 /* unmap any remaining paged data */ 6436 if (dma_unmap_len(tx_buffer, len)) { 6437 dma_unmap_page(tx_ring->dev, 6438 dma_unmap_addr(tx_buffer, dma), 6439 dma_unmap_len(tx_buffer, len), 6440 DMA_TO_DEVICE); 6441 dma_unmap_len_set(tx_buffer, len, 0); 6442 } 6443 } 6444 6445 /* move us one more past the eop_desc for start of next pkt */ 6446 tx_buffer++; 6447 tx_desc++; 6448 i++; 6449 if (unlikely(!i)) { 6450 i -= tx_ring->count; 6451 tx_buffer = tx_ring->tx_buffer_info; 6452 tx_desc = IGB_TX_DESC(tx_ring, 0); 6453 } 6454 6455 /* issue prefetch for next Tx descriptor */ 6456 prefetch(tx_desc); 6457 6458 /* update budget accounting */ 6459 budget--; 6460 } while (likely(budget)); 6461 6462 netdev_tx_completed_queue(txring_txq(tx_ring), 6463 total_packets, total_bytes); 6464 i += tx_ring->count; 6465 tx_ring->next_to_clean = i; 6466 u64_stats_update_begin(&tx_ring->tx_syncp); 6467 tx_ring->tx_stats.bytes += total_bytes; 6468 tx_ring->tx_stats.packets += total_packets; 6469 u64_stats_update_end(&tx_ring->tx_syncp); 6470 q_vector->tx.total_bytes += total_bytes; 6471 q_vector->tx.total_packets += total_packets; 6472 6473 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 6474 struct e1000_hw *hw = &adapter->hw; 6475 6476 /* Detect a transmit hang in hardware, this serializes the 6477 * check with the clearing of time_stamp and movement of i 6478 */ 6479 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 6480 if (tx_buffer->next_to_watch && 6481 time_after(jiffies, tx_buffer->time_stamp + 6482 (adapter->tx_timeout_factor * HZ)) && 6483 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 6484 6485 /* detected Tx unit hang */ 6486 dev_err(tx_ring->dev, 6487 "Detected Tx Unit Hang\n" 6488 " Tx Queue <%d>\n" 6489 " TDH <%x>\n" 6490 " TDT <%x>\n" 6491 " next_to_use <%x>\n" 6492 " next_to_clean <%x>\n" 6493 "buffer_info[next_to_clean]\n" 6494 " time_stamp <%lx>\n" 6495 " next_to_watch <%p>\n" 6496 " jiffies <%lx>\n" 6497 " desc.status <%x>\n", 6498 tx_ring->queue_index, 6499 rd32(E1000_TDH(tx_ring->reg_idx)), 6500 readl(tx_ring->tail), 6501 tx_ring->next_to_use, 6502 tx_ring->next_to_clean, 6503 tx_buffer->time_stamp, 6504 tx_buffer->next_to_watch, 6505 jiffies, 6506 tx_buffer->next_to_watch->wb.status); 6507 netif_stop_subqueue(tx_ring->netdev, 6508 tx_ring->queue_index); 6509 6510 /* we are about to reset, no point in enabling stuff */ 6511 return true; 6512 } 6513 } 6514 6515 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 6516 if (unlikely(total_packets && 6517 netif_carrier_ok(tx_ring->netdev) && 6518 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 6519 /* Make sure that anybody stopping the queue after this 6520 * sees the new next_to_clean. 6521 */ 6522 smp_mb(); 6523 if (__netif_subqueue_stopped(tx_ring->netdev, 6524 tx_ring->queue_index) && 6525 !(test_bit(__IGB_DOWN, &adapter->state))) { 6526 netif_wake_subqueue(tx_ring->netdev, 6527 tx_ring->queue_index); 6528 6529 u64_stats_update_begin(&tx_ring->tx_syncp); 6530 tx_ring->tx_stats.restart_queue++; 6531 u64_stats_update_end(&tx_ring->tx_syncp); 6532 } 6533 } 6534 6535 return !!budget; 6536 } 6537 6538 /** 6539 * igb_reuse_rx_page - page flip buffer and store it back on the ring 6540 * @rx_ring: rx descriptor ring to store buffers on 6541 * @old_buff: donor buffer to have page reused 6542 * 6543 * Synchronizes page for reuse by the adapter 6544 **/ 6545 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 6546 struct igb_rx_buffer *old_buff) 6547 { 6548 struct igb_rx_buffer *new_buff; 6549 u16 nta = rx_ring->next_to_alloc; 6550 6551 new_buff = &rx_ring->rx_buffer_info[nta]; 6552 6553 /* update, and store next to alloc */ 6554 nta++; 6555 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 6556 6557 /* transfer page from old buffer to new buffer */ 6558 *new_buff = *old_buff; 6559 6560 /* sync the buffer for use by the device */ 6561 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, 6562 old_buff->page_offset, 6563 IGB_RX_BUFSZ, 6564 DMA_FROM_DEVICE); 6565 } 6566 6567 static inline bool igb_page_is_reserved(struct page *page) 6568 { 6569 return (page_to_nid(page) != numa_mem_id()) || page->pfmemalloc; 6570 } 6571 6572 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 6573 struct page *page, 6574 unsigned int truesize) 6575 { 6576 /* avoid re-using remote pages */ 6577 if (unlikely(igb_page_is_reserved(page))) 6578 return false; 6579 6580 #if (PAGE_SIZE < 8192) 6581 /* if we are only owner of page we can reuse it */ 6582 if (unlikely(page_count(page) != 1)) 6583 return false; 6584 6585 /* flip page offset to other buffer */ 6586 rx_buffer->page_offset ^= IGB_RX_BUFSZ; 6587 #else 6588 /* move offset up to the next cache line */ 6589 rx_buffer->page_offset += truesize; 6590 6591 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ)) 6592 return false; 6593 #endif 6594 6595 /* Even if we own the page, we are not allowed to use atomic_set() 6596 * This would break get_page_unless_zero() users. 6597 */ 6598 atomic_inc(&page->_count); 6599 6600 return true; 6601 } 6602 6603 /** 6604 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 6605 * @rx_ring: rx descriptor ring to transact packets on 6606 * @rx_buffer: buffer containing page to add 6607 * @rx_desc: descriptor containing length of buffer written by hardware 6608 * @skb: sk_buff to place the data into 6609 * 6610 * This function will add the data contained in rx_buffer->page to the skb. 6611 * This is done either through a direct copy if the data in the buffer is 6612 * less than the skb header size, otherwise it will just attach the page as 6613 * a frag to the skb. 6614 * 6615 * The function will then update the page offset if necessary and return 6616 * true if the buffer can be reused by the adapter. 6617 **/ 6618 static bool igb_add_rx_frag(struct igb_ring *rx_ring, 6619 struct igb_rx_buffer *rx_buffer, 6620 union e1000_adv_rx_desc *rx_desc, 6621 struct sk_buff *skb) 6622 { 6623 struct page *page = rx_buffer->page; 6624 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 6625 #if (PAGE_SIZE < 8192) 6626 unsigned int truesize = IGB_RX_BUFSZ; 6627 #else 6628 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 6629 #endif 6630 6631 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) { 6632 unsigned char *va = page_address(page) + rx_buffer->page_offset; 6633 6634 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6635 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6636 va += IGB_TS_HDR_LEN; 6637 size -= IGB_TS_HDR_LEN; 6638 } 6639 6640 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 6641 6642 /* page is not reserved, we can reuse buffer as-is */ 6643 if (likely(!igb_page_is_reserved(page))) 6644 return true; 6645 6646 /* this page cannot be reused so discard it */ 6647 __free_page(page); 6648 return false; 6649 } 6650 6651 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 6652 rx_buffer->page_offset, size, truesize); 6653 6654 return igb_can_reuse_rx_page(rx_buffer, page, truesize); 6655 } 6656 6657 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring, 6658 union e1000_adv_rx_desc *rx_desc, 6659 struct sk_buff *skb) 6660 { 6661 struct igb_rx_buffer *rx_buffer; 6662 struct page *page; 6663 6664 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 6665 page = rx_buffer->page; 6666 prefetchw(page); 6667 6668 if (likely(!skb)) { 6669 void *page_addr = page_address(page) + 6670 rx_buffer->page_offset; 6671 6672 /* prefetch first cache line of first page */ 6673 prefetch(page_addr); 6674 #if L1_CACHE_BYTES < 128 6675 prefetch(page_addr + L1_CACHE_BYTES); 6676 #endif 6677 6678 /* allocate a skb to store the frags */ 6679 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 6680 if (unlikely(!skb)) { 6681 rx_ring->rx_stats.alloc_failed++; 6682 return NULL; 6683 } 6684 6685 /* we will be copying header into skb->data in 6686 * pskb_may_pull so it is in our interest to prefetch 6687 * it now to avoid a possible cache miss 6688 */ 6689 prefetchw(skb->data); 6690 } 6691 6692 /* we are reusing so sync this buffer for CPU use */ 6693 dma_sync_single_range_for_cpu(rx_ring->dev, 6694 rx_buffer->dma, 6695 rx_buffer->page_offset, 6696 IGB_RX_BUFSZ, 6697 DMA_FROM_DEVICE); 6698 6699 /* pull page into skb */ 6700 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 6701 /* hand second half of page back to the ring */ 6702 igb_reuse_rx_page(rx_ring, rx_buffer); 6703 } else { 6704 /* we are not reusing the buffer so unmap it */ 6705 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 6706 PAGE_SIZE, DMA_FROM_DEVICE); 6707 } 6708 6709 /* clear contents of rx_buffer */ 6710 rx_buffer->page = NULL; 6711 6712 return skb; 6713 } 6714 6715 static inline void igb_rx_checksum(struct igb_ring *ring, 6716 union e1000_adv_rx_desc *rx_desc, 6717 struct sk_buff *skb) 6718 { 6719 skb_checksum_none_assert(skb); 6720 6721 /* Ignore Checksum bit is set */ 6722 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 6723 return; 6724 6725 /* Rx checksum disabled via ethtool */ 6726 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 6727 return; 6728 6729 /* TCP/UDP checksum error bit is set */ 6730 if (igb_test_staterr(rx_desc, 6731 E1000_RXDEXT_STATERR_TCPE | 6732 E1000_RXDEXT_STATERR_IPE)) { 6733 /* work around errata with sctp packets where the TCPE aka 6734 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 6735 * packets, (aka let the stack check the crc32c) 6736 */ 6737 if (!((skb->len == 60) && 6738 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 6739 u64_stats_update_begin(&ring->rx_syncp); 6740 ring->rx_stats.csum_err++; 6741 u64_stats_update_end(&ring->rx_syncp); 6742 } 6743 /* let the stack verify checksum errors */ 6744 return; 6745 } 6746 /* It must be a TCP or UDP packet with a valid checksum */ 6747 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 6748 E1000_RXD_STAT_UDPCS)) 6749 skb->ip_summed = CHECKSUM_UNNECESSARY; 6750 6751 dev_dbg(ring->dev, "cksum success: bits %08X\n", 6752 le32_to_cpu(rx_desc->wb.upper.status_error)); 6753 } 6754 6755 static inline void igb_rx_hash(struct igb_ring *ring, 6756 union e1000_adv_rx_desc *rx_desc, 6757 struct sk_buff *skb) 6758 { 6759 if (ring->netdev->features & NETIF_F_RXHASH) 6760 skb_set_hash(skb, 6761 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 6762 PKT_HASH_TYPE_L3); 6763 } 6764 6765 /** 6766 * igb_is_non_eop - process handling of non-EOP buffers 6767 * @rx_ring: Rx ring being processed 6768 * @rx_desc: Rx descriptor for current buffer 6769 * @skb: current socket buffer containing buffer in progress 6770 * 6771 * This function updates next to clean. If the buffer is an EOP buffer 6772 * this function exits returning false, otherwise it will place the 6773 * sk_buff in the next buffer to be chained and return true indicating 6774 * that this is in fact a non-EOP buffer. 6775 **/ 6776 static bool igb_is_non_eop(struct igb_ring *rx_ring, 6777 union e1000_adv_rx_desc *rx_desc) 6778 { 6779 u32 ntc = rx_ring->next_to_clean + 1; 6780 6781 /* fetch, update, and store next to clean */ 6782 ntc = (ntc < rx_ring->count) ? ntc : 0; 6783 rx_ring->next_to_clean = ntc; 6784 6785 prefetch(IGB_RX_DESC(rx_ring, ntc)); 6786 6787 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 6788 return false; 6789 6790 return true; 6791 } 6792 6793 /** 6794 * igb_pull_tail - igb specific version of skb_pull_tail 6795 * @rx_ring: rx descriptor ring packet is being transacted on 6796 * @rx_desc: pointer to the EOP Rx descriptor 6797 * @skb: pointer to current skb being adjusted 6798 * 6799 * This function is an igb specific version of __pskb_pull_tail. The 6800 * main difference between this version and the original function is that 6801 * this function can make several assumptions about the state of things 6802 * that allow for significant optimizations versus the standard function. 6803 * As a result we can do things like drop a frag and maintain an accurate 6804 * truesize for the skb. 6805 */ 6806 static void igb_pull_tail(struct igb_ring *rx_ring, 6807 union e1000_adv_rx_desc *rx_desc, 6808 struct sk_buff *skb) 6809 { 6810 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 6811 unsigned char *va; 6812 unsigned int pull_len; 6813 6814 /* it is valid to use page_address instead of kmap since we are 6815 * working with pages allocated out of the lomem pool per 6816 * alloc_page(GFP_ATOMIC) 6817 */ 6818 va = skb_frag_address(frag); 6819 6820 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6821 /* retrieve timestamp from buffer */ 6822 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6823 6824 /* update pointers to remove timestamp header */ 6825 skb_frag_size_sub(frag, IGB_TS_HDR_LEN); 6826 frag->page_offset += IGB_TS_HDR_LEN; 6827 skb->data_len -= IGB_TS_HDR_LEN; 6828 skb->len -= IGB_TS_HDR_LEN; 6829 6830 /* move va to start of packet data */ 6831 va += IGB_TS_HDR_LEN; 6832 } 6833 6834 /* we need the header to contain the greater of either ETH_HLEN or 6835 * 60 bytes if the skb->len is less than 60 for skb_pad. 6836 */ 6837 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN); 6838 6839 /* align pull length to size of long to optimize memcpy performance */ 6840 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 6841 6842 /* update all of the pointers */ 6843 skb_frag_size_sub(frag, pull_len); 6844 frag->page_offset += pull_len; 6845 skb->data_len -= pull_len; 6846 skb->tail += pull_len; 6847 } 6848 6849 /** 6850 * igb_cleanup_headers - Correct corrupted or empty headers 6851 * @rx_ring: rx descriptor ring packet is being transacted on 6852 * @rx_desc: pointer to the EOP Rx descriptor 6853 * @skb: pointer to current skb being fixed 6854 * 6855 * Address the case where we are pulling data in on pages only 6856 * and as such no data is present in the skb header. 6857 * 6858 * In addition if skb is not at least 60 bytes we need to pad it so that 6859 * it is large enough to qualify as a valid Ethernet frame. 6860 * 6861 * Returns true if an error was encountered and skb was freed. 6862 **/ 6863 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 6864 union e1000_adv_rx_desc *rx_desc, 6865 struct sk_buff *skb) 6866 { 6867 if (unlikely((igb_test_staterr(rx_desc, 6868 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 6869 struct net_device *netdev = rx_ring->netdev; 6870 if (!(netdev->features & NETIF_F_RXALL)) { 6871 dev_kfree_skb_any(skb); 6872 return true; 6873 } 6874 } 6875 6876 /* place header in linear portion of buffer */ 6877 if (skb_is_nonlinear(skb)) 6878 igb_pull_tail(rx_ring, rx_desc, skb); 6879 6880 /* if eth_skb_pad returns an error the skb was freed */ 6881 if (eth_skb_pad(skb)) 6882 return true; 6883 6884 return false; 6885 } 6886 6887 /** 6888 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 6889 * @rx_ring: rx descriptor ring packet is being transacted on 6890 * @rx_desc: pointer to the EOP Rx descriptor 6891 * @skb: pointer to current skb being populated 6892 * 6893 * This function checks the ring, descriptor, and packet information in 6894 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 6895 * other fields within the skb. 6896 **/ 6897 static void igb_process_skb_fields(struct igb_ring *rx_ring, 6898 union e1000_adv_rx_desc *rx_desc, 6899 struct sk_buff *skb) 6900 { 6901 struct net_device *dev = rx_ring->netdev; 6902 6903 igb_rx_hash(rx_ring, rx_desc, skb); 6904 6905 igb_rx_checksum(rx_ring, rx_desc, skb); 6906 6907 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 6908 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 6909 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 6910 6911 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 6912 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 6913 u16 vid; 6914 6915 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 6916 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 6917 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 6918 else 6919 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 6920 6921 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 6922 } 6923 6924 skb_record_rx_queue(skb, rx_ring->queue_index); 6925 6926 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 6927 } 6928 6929 static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 6930 { 6931 struct igb_ring *rx_ring = q_vector->rx.ring; 6932 struct sk_buff *skb = rx_ring->skb; 6933 unsigned int total_bytes = 0, total_packets = 0; 6934 u16 cleaned_count = igb_desc_unused(rx_ring); 6935 6936 while (likely(total_packets < budget)) { 6937 union e1000_adv_rx_desc *rx_desc; 6938 6939 /* return some buffers to hardware, one at a time is too slow */ 6940 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 6941 igb_alloc_rx_buffers(rx_ring, cleaned_count); 6942 cleaned_count = 0; 6943 } 6944 6945 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 6946 6947 if (!rx_desc->wb.upper.status_error) 6948 break; 6949 6950 /* This memory barrier is needed to keep us from reading 6951 * any other fields out of the rx_desc until we know the 6952 * descriptor has been written back 6953 */ 6954 dma_rmb(); 6955 6956 /* retrieve a buffer from the ring */ 6957 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb); 6958 6959 /* exit if we failed to retrieve a buffer */ 6960 if (!skb) 6961 break; 6962 6963 cleaned_count++; 6964 6965 /* fetch next buffer in frame if non-eop */ 6966 if (igb_is_non_eop(rx_ring, rx_desc)) 6967 continue; 6968 6969 /* verify the packet layout is correct */ 6970 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 6971 skb = NULL; 6972 continue; 6973 } 6974 6975 /* probably a little skewed due to removing CRC */ 6976 total_bytes += skb->len; 6977 6978 /* populate checksum, timestamp, VLAN, and protocol */ 6979 igb_process_skb_fields(rx_ring, rx_desc, skb); 6980 6981 napi_gro_receive(&q_vector->napi, skb); 6982 6983 /* reset skb pointer */ 6984 skb = NULL; 6985 6986 /* update budget accounting */ 6987 total_packets++; 6988 } 6989 6990 /* place incomplete frames back on ring for completion */ 6991 rx_ring->skb = skb; 6992 6993 u64_stats_update_begin(&rx_ring->rx_syncp); 6994 rx_ring->rx_stats.packets += total_packets; 6995 rx_ring->rx_stats.bytes += total_bytes; 6996 u64_stats_update_end(&rx_ring->rx_syncp); 6997 q_vector->rx.total_packets += total_packets; 6998 q_vector->rx.total_bytes += total_bytes; 6999 7000 if (cleaned_count) 7001 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7002 7003 return total_packets < budget; 7004 } 7005 7006 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 7007 struct igb_rx_buffer *bi) 7008 { 7009 struct page *page = bi->page; 7010 dma_addr_t dma; 7011 7012 /* since we are recycling buffers we should seldom need to alloc */ 7013 if (likely(page)) 7014 return true; 7015 7016 /* alloc new page for storage */ 7017 page = dev_alloc_page(); 7018 if (unlikely(!page)) { 7019 rx_ring->rx_stats.alloc_failed++; 7020 return false; 7021 } 7022 7023 /* map page for use */ 7024 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 7025 7026 /* if mapping failed free memory back to system since 7027 * there isn't much point in holding memory we can't use 7028 */ 7029 if (dma_mapping_error(rx_ring->dev, dma)) { 7030 __free_page(page); 7031 7032 rx_ring->rx_stats.alloc_failed++; 7033 return false; 7034 } 7035 7036 bi->dma = dma; 7037 bi->page = page; 7038 bi->page_offset = 0; 7039 7040 return true; 7041 } 7042 7043 /** 7044 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 7045 * @adapter: address of board private structure 7046 **/ 7047 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 7048 { 7049 union e1000_adv_rx_desc *rx_desc; 7050 struct igb_rx_buffer *bi; 7051 u16 i = rx_ring->next_to_use; 7052 7053 /* nothing to do */ 7054 if (!cleaned_count) 7055 return; 7056 7057 rx_desc = IGB_RX_DESC(rx_ring, i); 7058 bi = &rx_ring->rx_buffer_info[i]; 7059 i -= rx_ring->count; 7060 7061 do { 7062 if (!igb_alloc_mapped_page(rx_ring, bi)) 7063 break; 7064 7065 /* Refresh the desc even if buffer_addrs didn't change 7066 * because each write-back erases this info. 7067 */ 7068 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 7069 7070 rx_desc++; 7071 bi++; 7072 i++; 7073 if (unlikely(!i)) { 7074 rx_desc = IGB_RX_DESC(rx_ring, 0); 7075 bi = rx_ring->rx_buffer_info; 7076 i -= rx_ring->count; 7077 } 7078 7079 /* clear the status bits for the next_to_use descriptor */ 7080 rx_desc->wb.upper.status_error = 0; 7081 7082 cleaned_count--; 7083 } while (cleaned_count); 7084 7085 i += rx_ring->count; 7086 7087 if (rx_ring->next_to_use != i) { 7088 /* record the next descriptor to use */ 7089 rx_ring->next_to_use = i; 7090 7091 /* update next to alloc since we have filled the ring */ 7092 rx_ring->next_to_alloc = i; 7093 7094 /* Force memory writes to complete before letting h/w 7095 * know there are new descriptors to fetch. (Only 7096 * applicable for weak-ordered memory model archs, 7097 * such as IA-64). 7098 */ 7099 wmb(); 7100 writel(i, rx_ring->tail); 7101 } 7102 } 7103 7104 /** 7105 * igb_mii_ioctl - 7106 * @netdev: 7107 * @ifreq: 7108 * @cmd: 7109 **/ 7110 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7111 { 7112 struct igb_adapter *adapter = netdev_priv(netdev); 7113 struct mii_ioctl_data *data = if_mii(ifr); 7114 7115 if (adapter->hw.phy.media_type != e1000_media_type_copper) 7116 return -EOPNOTSUPP; 7117 7118 switch (cmd) { 7119 case SIOCGMIIPHY: 7120 data->phy_id = adapter->hw.phy.addr; 7121 break; 7122 case SIOCGMIIREG: 7123 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 7124 &data->val_out)) 7125 return -EIO; 7126 break; 7127 case SIOCSMIIREG: 7128 default: 7129 return -EOPNOTSUPP; 7130 } 7131 return 0; 7132 } 7133 7134 /** 7135 * igb_ioctl - 7136 * @netdev: 7137 * @ifreq: 7138 * @cmd: 7139 **/ 7140 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7141 { 7142 switch (cmd) { 7143 case SIOCGMIIPHY: 7144 case SIOCGMIIREG: 7145 case SIOCSMIIREG: 7146 return igb_mii_ioctl(netdev, ifr, cmd); 7147 case SIOCGHWTSTAMP: 7148 return igb_ptp_get_ts_config(netdev, ifr); 7149 case SIOCSHWTSTAMP: 7150 return igb_ptp_set_ts_config(netdev, ifr); 7151 default: 7152 return -EOPNOTSUPP; 7153 } 7154 } 7155 7156 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 7157 { 7158 struct igb_adapter *adapter = hw->back; 7159 7160 pci_read_config_word(adapter->pdev, reg, value); 7161 } 7162 7163 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 7164 { 7165 struct igb_adapter *adapter = hw->back; 7166 7167 pci_write_config_word(adapter->pdev, reg, *value); 7168 } 7169 7170 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7171 { 7172 struct igb_adapter *adapter = hw->back; 7173 7174 if (pcie_capability_read_word(adapter->pdev, reg, value)) 7175 return -E1000_ERR_CONFIG; 7176 7177 return 0; 7178 } 7179 7180 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7181 { 7182 struct igb_adapter *adapter = hw->back; 7183 7184 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 7185 return -E1000_ERR_CONFIG; 7186 7187 return 0; 7188 } 7189 7190 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 7191 { 7192 struct igb_adapter *adapter = netdev_priv(netdev); 7193 struct e1000_hw *hw = &adapter->hw; 7194 u32 ctrl, rctl; 7195 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 7196 7197 if (enable) { 7198 /* enable VLAN tag insert/strip */ 7199 ctrl = rd32(E1000_CTRL); 7200 ctrl |= E1000_CTRL_VME; 7201 wr32(E1000_CTRL, ctrl); 7202 7203 /* Disable CFI check */ 7204 rctl = rd32(E1000_RCTL); 7205 rctl &= ~E1000_RCTL_CFIEN; 7206 wr32(E1000_RCTL, rctl); 7207 } else { 7208 /* disable VLAN tag insert/strip */ 7209 ctrl = rd32(E1000_CTRL); 7210 ctrl &= ~E1000_CTRL_VME; 7211 wr32(E1000_CTRL, ctrl); 7212 } 7213 7214 igb_rlpml_set(adapter); 7215 } 7216 7217 static int igb_vlan_rx_add_vid(struct net_device *netdev, 7218 __be16 proto, u16 vid) 7219 { 7220 struct igb_adapter *adapter = netdev_priv(netdev); 7221 struct e1000_hw *hw = &adapter->hw; 7222 int pf_id = adapter->vfs_allocated_count; 7223 7224 /* attempt to add filter to vlvf array */ 7225 igb_vlvf_set(adapter, vid, true, pf_id); 7226 7227 /* add the filter since PF can receive vlans w/o entry in vlvf */ 7228 igb_vfta_set(hw, vid, true); 7229 7230 set_bit(vid, adapter->active_vlans); 7231 7232 return 0; 7233 } 7234 7235 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 7236 __be16 proto, u16 vid) 7237 { 7238 struct igb_adapter *adapter = netdev_priv(netdev); 7239 struct e1000_hw *hw = &adapter->hw; 7240 int pf_id = adapter->vfs_allocated_count; 7241 s32 err; 7242 7243 /* remove vlan from VLVF table array */ 7244 err = igb_vlvf_set(adapter, vid, false, pf_id); 7245 7246 /* if vid was not present in VLVF just remove it from table */ 7247 if (err) 7248 igb_vfta_set(hw, vid, false); 7249 7250 clear_bit(vid, adapter->active_vlans); 7251 7252 return 0; 7253 } 7254 7255 static void igb_restore_vlan(struct igb_adapter *adapter) 7256 { 7257 u16 vid; 7258 7259 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 7260 7261 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 7262 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 7263 } 7264 7265 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 7266 { 7267 struct pci_dev *pdev = adapter->pdev; 7268 struct e1000_mac_info *mac = &adapter->hw.mac; 7269 7270 mac->autoneg = 0; 7271 7272 /* Make sure dplx is at most 1 bit and lsb of speed is not set 7273 * for the switch() below to work 7274 */ 7275 if ((spd & 1) || (dplx & ~1)) 7276 goto err_inval; 7277 7278 /* Fiber NIC's only allow 1000 gbps Full duplex 7279 * and 100Mbps Full duplex for 100baseFx sfp 7280 */ 7281 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 7282 switch (spd + dplx) { 7283 case SPEED_10 + DUPLEX_HALF: 7284 case SPEED_10 + DUPLEX_FULL: 7285 case SPEED_100 + DUPLEX_HALF: 7286 goto err_inval; 7287 default: 7288 break; 7289 } 7290 } 7291 7292 switch (spd + dplx) { 7293 case SPEED_10 + DUPLEX_HALF: 7294 mac->forced_speed_duplex = ADVERTISE_10_HALF; 7295 break; 7296 case SPEED_10 + DUPLEX_FULL: 7297 mac->forced_speed_duplex = ADVERTISE_10_FULL; 7298 break; 7299 case SPEED_100 + DUPLEX_HALF: 7300 mac->forced_speed_duplex = ADVERTISE_100_HALF; 7301 break; 7302 case SPEED_100 + DUPLEX_FULL: 7303 mac->forced_speed_duplex = ADVERTISE_100_FULL; 7304 break; 7305 case SPEED_1000 + DUPLEX_FULL: 7306 mac->autoneg = 1; 7307 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 7308 break; 7309 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 7310 default: 7311 goto err_inval; 7312 } 7313 7314 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 7315 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7316 7317 return 0; 7318 7319 err_inval: 7320 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 7321 return -EINVAL; 7322 } 7323 7324 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 7325 bool runtime) 7326 { 7327 struct net_device *netdev = pci_get_drvdata(pdev); 7328 struct igb_adapter *adapter = netdev_priv(netdev); 7329 struct e1000_hw *hw = &adapter->hw; 7330 u32 ctrl, rctl, status; 7331 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 7332 #ifdef CONFIG_PM 7333 int retval = 0; 7334 #endif 7335 7336 netif_device_detach(netdev); 7337 7338 if (netif_running(netdev)) 7339 __igb_close(netdev, true); 7340 7341 igb_clear_interrupt_scheme(adapter); 7342 7343 #ifdef CONFIG_PM 7344 retval = pci_save_state(pdev); 7345 if (retval) 7346 return retval; 7347 #endif 7348 7349 status = rd32(E1000_STATUS); 7350 if (status & E1000_STATUS_LU) 7351 wufc &= ~E1000_WUFC_LNKC; 7352 7353 if (wufc) { 7354 igb_setup_rctl(adapter); 7355 igb_set_rx_mode(netdev); 7356 7357 /* turn on all-multi mode if wake on multicast is enabled */ 7358 if (wufc & E1000_WUFC_MC) { 7359 rctl = rd32(E1000_RCTL); 7360 rctl |= E1000_RCTL_MPE; 7361 wr32(E1000_RCTL, rctl); 7362 } 7363 7364 ctrl = rd32(E1000_CTRL); 7365 /* advertise wake from D3Cold */ 7366 #define E1000_CTRL_ADVD3WUC 0x00100000 7367 /* phy power management enable */ 7368 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 7369 ctrl |= E1000_CTRL_ADVD3WUC; 7370 wr32(E1000_CTRL, ctrl); 7371 7372 /* Allow time for pending master requests to run */ 7373 igb_disable_pcie_master(hw); 7374 7375 wr32(E1000_WUC, E1000_WUC_PME_EN); 7376 wr32(E1000_WUFC, wufc); 7377 } else { 7378 wr32(E1000_WUC, 0); 7379 wr32(E1000_WUFC, 0); 7380 } 7381 7382 *enable_wake = wufc || adapter->en_mng_pt; 7383 if (!*enable_wake) 7384 igb_power_down_link(adapter); 7385 else 7386 igb_power_up_link(adapter); 7387 7388 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7389 * would have already happened in close and is redundant. 7390 */ 7391 igb_release_hw_control(adapter); 7392 7393 pci_disable_device(pdev); 7394 7395 return 0; 7396 } 7397 7398 #ifdef CONFIG_PM 7399 #ifdef CONFIG_PM_SLEEP 7400 static int igb_suspend(struct device *dev) 7401 { 7402 int retval; 7403 bool wake; 7404 struct pci_dev *pdev = to_pci_dev(dev); 7405 7406 retval = __igb_shutdown(pdev, &wake, 0); 7407 if (retval) 7408 return retval; 7409 7410 if (wake) { 7411 pci_prepare_to_sleep(pdev); 7412 } else { 7413 pci_wake_from_d3(pdev, false); 7414 pci_set_power_state(pdev, PCI_D3hot); 7415 } 7416 7417 return 0; 7418 } 7419 #endif /* CONFIG_PM_SLEEP */ 7420 7421 static int igb_resume(struct device *dev) 7422 { 7423 struct pci_dev *pdev = to_pci_dev(dev); 7424 struct net_device *netdev = pci_get_drvdata(pdev); 7425 struct igb_adapter *adapter = netdev_priv(netdev); 7426 struct e1000_hw *hw = &adapter->hw; 7427 u32 err; 7428 7429 pci_set_power_state(pdev, PCI_D0); 7430 pci_restore_state(pdev); 7431 pci_save_state(pdev); 7432 7433 if (!pci_device_is_present(pdev)) 7434 return -ENODEV; 7435 err = pci_enable_device_mem(pdev); 7436 if (err) { 7437 dev_err(&pdev->dev, 7438 "igb: Cannot enable PCI device from suspend\n"); 7439 return err; 7440 } 7441 pci_set_master(pdev); 7442 7443 pci_enable_wake(pdev, PCI_D3hot, 0); 7444 pci_enable_wake(pdev, PCI_D3cold, 0); 7445 7446 if (igb_init_interrupt_scheme(adapter, true)) { 7447 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7448 return -ENOMEM; 7449 } 7450 7451 igb_reset(adapter); 7452 7453 /* let the f/w know that the h/w is now under the control of the 7454 * driver. 7455 */ 7456 igb_get_hw_control(adapter); 7457 7458 wr32(E1000_WUS, ~0); 7459 7460 if (netdev->flags & IFF_UP) { 7461 rtnl_lock(); 7462 err = __igb_open(netdev, true); 7463 rtnl_unlock(); 7464 if (err) 7465 return err; 7466 } 7467 7468 netif_device_attach(netdev); 7469 return 0; 7470 } 7471 7472 static int igb_runtime_idle(struct device *dev) 7473 { 7474 struct pci_dev *pdev = to_pci_dev(dev); 7475 struct net_device *netdev = pci_get_drvdata(pdev); 7476 struct igb_adapter *adapter = netdev_priv(netdev); 7477 7478 if (!igb_has_link(adapter)) 7479 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 7480 7481 return -EBUSY; 7482 } 7483 7484 static int igb_runtime_suspend(struct device *dev) 7485 { 7486 struct pci_dev *pdev = to_pci_dev(dev); 7487 int retval; 7488 bool wake; 7489 7490 retval = __igb_shutdown(pdev, &wake, 1); 7491 if (retval) 7492 return retval; 7493 7494 if (wake) { 7495 pci_prepare_to_sleep(pdev); 7496 } else { 7497 pci_wake_from_d3(pdev, false); 7498 pci_set_power_state(pdev, PCI_D3hot); 7499 } 7500 7501 return 0; 7502 } 7503 7504 static int igb_runtime_resume(struct device *dev) 7505 { 7506 return igb_resume(dev); 7507 } 7508 #endif /* CONFIG_PM */ 7509 7510 static void igb_shutdown(struct pci_dev *pdev) 7511 { 7512 bool wake; 7513 7514 __igb_shutdown(pdev, &wake, 0); 7515 7516 if (system_state == SYSTEM_POWER_OFF) { 7517 pci_wake_from_d3(pdev, wake); 7518 pci_set_power_state(pdev, PCI_D3hot); 7519 } 7520 } 7521 7522 #ifdef CONFIG_PCI_IOV 7523 static int igb_sriov_reinit(struct pci_dev *dev) 7524 { 7525 struct net_device *netdev = pci_get_drvdata(dev); 7526 struct igb_adapter *adapter = netdev_priv(netdev); 7527 struct pci_dev *pdev = adapter->pdev; 7528 7529 rtnl_lock(); 7530 7531 if (netif_running(netdev)) 7532 igb_close(netdev); 7533 else 7534 igb_reset(adapter); 7535 7536 igb_clear_interrupt_scheme(adapter); 7537 7538 igb_init_queue_configuration(adapter); 7539 7540 if (igb_init_interrupt_scheme(adapter, true)) { 7541 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7542 return -ENOMEM; 7543 } 7544 7545 if (netif_running(netdev)) 7546 igb_open(netdev); 7547 7548 rtnl_unlock(); 7549 7550 return 0; 7551 } 7552 7553 static int igb_pci_disable_sriov(struct pci_dev *dev) 7554 { 7555 int err = igb_disable_sriov(dev); 7556 7557 if (!err) 7558 err = igb_sriov_reinit(dev); 7559 7560 return err; 7561 } 7562 7563 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 7564 { 7565 int err = igb_enable_sriov(dev, num_vfs); 7566 7567 if (err) 7568 goto out; 7569 7570 err = igb_sriov_reinit(dev); 7571 if (!err) 7572 return num_vfs; 7573 7574 out: 7575 return err; 7576 } 7577 7578 #endif 7579 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 7580 { 7581 #ifdef CONFIG_PCI_IOV 7582 if (num_vfs == 0) 7583 return igb_pci_disable_sriov(dev); 7584 else 7585 return igb_pci_enable_sriov(dev, num_vfs); 7586 #endif 7587 return 0; 7588 } 7589 7590 #ifdef CONFIG_NET_POLL_CONTROLLER 7591 /* Polling 'interrupt' - used by things like netconsole to send skbs 7592 * without having to re-enable interrupts. It's not called while 7593 * the interrupt routine is executing. 7594 */ 7595 static void igb_netpoll(struct net_device *netdev) 7596 { 7597 struct igb_adapter *adapter = netdev_priv(netdev); 7598 struct e1000_hw *hw = &adapter->hw; 7599 struct igb_q_vector *q_vector; 7600 int i; 7601 7602 for (i = 0; i < adapter->num_q_vectors; i++) { 7603 q_vector = adapter->q_vector[i]; 7604 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7605 wr32(E1000_EIMC, q_vector->eims_value); 7606 else 7607 igb_irq_disable(adapter); 7608 napi_schedule(&q_vector->napi); 7609 } 7610 } 7611 #endif /* CONFIG_NET_POLL_CONTROLLER */ 7612 7613 /** 7614 * igb_io_error_detected - called when PCI error is detected 7615 * @pdev: Pointer to PCI device 7616 * @state: The current pci connection state 7617 * 7618 * This function is called after a PCI bus error affecting 7619 * this device has been detected. 7620 **/ 7621 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 7622 pci_channel_state_t state) 7623 { 7624 struct net_device *netdev = pci_get_drvdata(pdev); 7625 struct igb_adapter *adapter = netdev_priv(netdev); 7626 7627 netif_device_detach(netdev); 7628 7629 if (state == pci_channel_io_perm_failure) 7630 return PCI_ERS_RESULT_DISCONNECT; 7631 7632 if (netif_running(netdev)) 7633 igb_down(adapter); 7634 pci_disable_device(pdev); 7635 7636 /* Request a slot slot reset. */ 7637 return PCI_ERS_RESULT_NEED_RESET; 7638 } 7639 7640 /** 7641 * igb_io_slot_reset - called after the pci bus has been reset. 7642 * @pdev: Pointer to PCI device 7643 * 7644 * Restart the card from scratch, as if from a cold-boot. Implementation 7645 * resembles the first-half of the igb_resume routine. 7646 **/ 7647 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 7648 { 7649 struct net_device *netdev = pci_get_drvdata(pdev); 7650 struct igb_adapter *adapter = netdev_priv(netdev); 7651 struct e1000_hw *hw = &adapter->hw; 7652 pci_ers_result_t result; 7653 int err; 7654 7655 if (pci_enable_device_mem(pdev)) { 7656 dev_err(&pdev->dev, 7657 "Cannot re-enable PCI device after reset.\n"); 7658 result = PCI_ERS_RESULT_DISCONNECT; 7659 } else { 7660 pci_set_master(pdev); 7661 pci_restore_state(pdev); 7662 pci_save_state(pdev); 7663 7664 pci_enable_wake(pdev, PCI_D3hot, 0); 7665 pci_enable_wake(pdev, PCI_D3cold, 0); 7666 7667 igb_reset(adapter); 7668 wr32(E1000_WUS, ~0); 7669 result = PCI_ERS_RESULT_RECOVERED; 7670 } 7671 7672 err = pci_cleanup_aer_uncorrect_error_status(pdev); 7673 if (err) { 7674 dev_err(&pdev->dev, 7675 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 7676 err); 7677 /* non-fatal, continue */ 7678 } 7679 7680 return result; 7681 } 7682 7683 /** 7684 * igb_io_resume - called when traffic can start flowing again. 7685 * @pdev: Pointer to PCI device 7686 * 7687 * This callback is called when the error recovery driver tells us that 7688 * its OK to resume normal operation. Implementation resembles the 7689 * second-half of the igb_resume routine. 7690 */ 7691 static void igb_io_resume(struct pci_dev *pdev) 7692 { 7693 struct net_device *netdev = pci_get_drvdata(pdev); 7694 struct igb_adapter *adapter = netdev_priv(netdev); 7695 7696 if (netif_running(netdev)) { 7697 if (igb_up(adapter)) { 7698 dev_err(&pdev->dev, "igb_up failed after reset\n"); 7699 return; 7700 } 7701 } 7702 7703 netif_device_attach(netdev); 7704 7705 /* let the f/w know that the h/w is now under the control of the 7706 * driver. 7707 */ 7708 igb_get_hw_control(adapter); 7709 } 7710 7711 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, 7712 u8 qsel) 7713 { 7714 u32 rar_low, rar_high; 7715 struct e1000_hw *hw = &adapter->hw; 7716 7717 /* HW expects these in little endian so we reverse the byte order 7718 * from network order (big endian) to little endian 7719 */ 7720 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 7721 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 7722 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 7723 7724 /* Indicate to hardware the Address is Valid. */ 7725 rar_high |= E1000_RAH_AV; 7726 7727 if (hw->mac.type == e1000_82575) 7728 rar_high |= E1000_RAH_POOL_1 * qsel; 7729 else 7730 rar_high |= E1000_RAH_POOL_1 << qsel; 7731 7732 wr32(E1000_RAL(index), rar_low); 7733 wrfl(); 7734 wr32(E1000_RAH(index), rar_high); 7735 wrfl(); 7736 } 7737 7738 static int igb_set_vf_mac(struct igb_adapter *adapter, 7739 int vf, unsigned char *mac_addr) 7740 { 7741 struct e1000_hw *hw = &adapter->hw; 7742 /* VF MAC addresses start at end of receive addresses and moves 7743 * towards the first, as a result a collision should not be possible 7744 */ 7745 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 7746 7747 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); 7748 7749 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); 7750 7751 return 0; 7752 } 7753 7754 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 7755 { 7756 struct igb_adapter *adapter = netdev_priv(netdev); 7757 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) 7758 return -EINVAL; 7759 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 7760 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); 7761 dev_info(&adapter->pdev->dev, 7762 "Reload the VF driver to make this change effective."); 7763 if (test_bit(__IGB_DOWN, &adapter->state)) { 7764 dev_warn(&adapter->pdev->dev, 7765 "The VF MAC address has been set, but the PF device is not up.\n"); 7766 dev_warn(&adapter->pdev->dev, 7767 "Bring the PF device up before attempting to use the VF device.\n"); 7768 } 7769 return igb_set_vf_mac(adapter, vf, mac); 7770 } 7771 7772 static int igb_link_mbps(int internal_link_speed) 7773 { 7774 switch (internal_link_speed) { 7775 case SPEED_100: 7776 return 100; 7777 case SPEED_1000: 7778 return 1000; 7779 default: 7780 return 0; 7781 } 7782 } 7783 7784 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 7785 int link_speed) 7786 { 7787 int rf_dec, rf_int; 7788 u32 bcnrc_val; 7789 7790 if (tx_rate != 0) { 7791 /* Calculate the rate factor values to set */ 7792 rf_int = link_speed / tx_rate; 7793 rf_dec = (link_speed - (rf_int * tx_rate)); 7794 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) / 7795 tx_rate; 7796 7797 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 7798 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 7799 E1000_RTTBCNRC_RF_INT_MASK); 7800 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 7801 } else { 7802 bcnrc_val = 0; 7803 } 7804 7805 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 7806 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 7807 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 7808 */ 7809 wr32(E1000_RTTBCNRM, 0x14); 7810 wr32(E1000_RTTBCNRC, bcnrc_val); 7811 } 7812 7813 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 7814 { 7815 int actual_link_speed, i; 7816 bool reset_rate = false; 7817 7818 /* VF TX rate limit was not set or not supported */ 7819 if ((adapter->vf_rate_link_speed == 0) || 7820 (adapter->hw.mac.type != e1000_82576)) 7821 return; 7822 7823 actual_link_speed = igb_link_mbps(adapter->link_speed); 7824 if (actual_link_speed != adapter->vf_rate_link_speed) { 7825 reset_rate = true; 7826 adapter->vf_rate_link_speed = 0; 7827 dev_info(&adapter->pdev->dev, 7828 "Link speed has been changed. VF Transmit rate is disabled\n"); 7829 } 7830 7831 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7832 if (reset_rate) 7833 adapter->vf_data[i].tx_rate = 0; 7834 7835 igb_set_vf_rate_limit(&adapter->hw, i, 7836 adapter->vf_data[i].tx_rate, 7837 actual_link_speed); 7838 } 7839 } 7840 7841 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 7842 int min_tx_rate, int max_tx_rate) 7843 { 7844 struct igb_adapter *adapter = netdev_priv(netdev); 7845 struct e1000_hw *hw = &adapter->hw; 7846 int actual_link_speed; 7847 7848 if (hw->mac.type != e1000_82576) 7849 return -EOPNOTSUPP; 7850 7851 if (min_tx_rate) 7852 return -EINVAL; 7853 7854 actual_link_speed = igb_link_mbps(adapter->link_speed); 7855 if ((vf >= adapter->vfs_allocated_count) || 7856 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 7857 (max_tx_rate < 0) || 7858 (max_tx_rate > actual_link_speed)) 7859 return -EINVAL; 7860 7861 adapter->vf_rate_link_speed = actual_link_speed; 7862 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 7863 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 7864 7865 return 0; 7866 } 7867 7868 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 7869 bool setting) 7870 { 7871 struct igb_adapter *adapter = netdev_priv(netdev); 7872 struct e1000_hw *hw = &adapter->hw; 7873 u32 reg_val, reg_offset; 7874 7875 if (!adapter->vfs_allocated_count) 7876 return -EOPNOTSUPP; 7877 7878 if (vf >= adapter->vfs_allocated_count) 7879 return -EINVAL; 7880 7881 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 7882 reg_val = rd32(reg_offset); 7883 if (setting) 7884 reg_val |= ((1 << vf) | 7885 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 7886 else 7887 reg_val &= ~((1 << vf) | 7888 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 7889 wr32(reg_offset, reg_val); 7890 7891 adapter->vf_data[vf].spoofchk_enabled = setting; 7892 return 0; 7893 } 7894 7895 static int igb_ndo_get_vf_config(struct net_device *netdev, 7896 int vf, struct ifla_vf_info *ivi) 7897 { 7898 struct igb_adapter *adapter = netdev_priv(netdev); 7899 if (vf >= adapter->vfs_allocated_count) 7900 return -EINVAL; 7901 ivi->vf = vf; 7902 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 7903 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 7904 ivi->min_tx_rate = 0; 7905 ivi->vlan = adapter->vf_data[vf].pf_vlan; 7906 ivi->qos = adapter->vf_data[vf].pf_qos; 7907 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 7908 return 0; 7909 } 7910 7911 static void igb_vmm_control(struct igb_adapter *adapter) 7912 { 7913 struct e1000_hw *hw = &adapter->hw; 7914 u32 reg; 7915 7916 switch (hw->mac.type) { 7917 case e1000_82575: 7918 case e1000_i210: 7919 case e1000_i211: 7920 case e1000_i354: 7921 default: 7922 /* replication is not supported for 82575 */ 7923 return; 7924 case e1000_82576: 7925 /* notify HW that the MAC is adding vlan tags */ 7926 reg = rd32(E1000_DTXCTL); 7927 reg |= E1000_DTXCTL_VLAN_ADDED; 7928 wr32(E1000_DTXCTL, reg); 7929 /* Fall through */ 7930 case e1000_82580: 7931 /* enable replication vlan tag stripping */ 7932 reg = rd32(E1000_RPLOLR); 7933 reg |= E1000_RPLOLR_STRVLAN; 7934 wr32(E1000_RPLOLR, reg); 7935 /* Fall through */ 7936 case e1000_i350: 7937 /* none of the above registers are supported by i350 */ 7938 break; 7939 } 7940 7941 if (adapter->vfs_allocated_count) { 7942 igb_vmdq_set_loopback_pf(hw, true); 7943 igb_vmdq_set_replication_pf(hw, true); 7944 igb_vmdq_set_anti_spoofing_pf(hw, true, 7945 adapter->vfs_allocated_count); 7946 } else { 7947 igb_vmdq_set_loopback_pf(hw, false); 7948 igb_vmdq_set_replication_pf(hw, false); 7949 } 7950 } 7951 7952 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 7953 { 7954 struct e1000_hw *hw = &adapter->hw; 7955 u32 dmac_thr; 7956 u16 hwm; 7957 7958 if (hw->mac.type > e1000_82580) { 7959 if (adapter->flags & IGB_FLAG_DMAC) { 7960 u32 reg; 7961 7962 /* force threshold to 0. */ 7963 wr32(E1000_DMCTXTH, 0); 7964 7965 /* DMA Coalescing high water mark needs to be greater 7966 * than the Rx threshold. Set hwm to PBA - max frame 7967 * size in 16B units, capping it at PBA - 6KB. 7968 */ 7969 hwm = 64 * pba - adapter->max_frame_size / 16; 7970 if (hwm < 64 * (pba - 6)) 7971 hwm = 64 * (pba - 6); 7972 reg = rd32(E1000_FCRTC); 7973 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 7974 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 7975 & E1000_FCRTC_RTH_COAL_MASK); 7976 wr32(E1000_FCRTC, reg); 7977 7978 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 7979 * frame size, capping it at PBA - 10KB. 7980 */ 7981 dmac_thr = pba - adapter->max_frame_size / 512; 7982 if (dmac_thr < pba - 10) 7983 dmac_thr = pba - 10; 7984 reg = rd32(E1000_DMACR); 7985 reg &= ~E1000_DMACR_DMACTHR_MASK; 7986 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 7987 & E1000_DMACR_DMACTHR_MASK); 7988 7989 /* transition to L0x or L1 if available..*/ 7990 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 7991 7992 /* watchdog timer= +-1000 usec in 32usec intervals */ 7993 reg |= (1000 >> 5); 7994 7995 /* Disable BMC-to-OS Watchdog Enable */ 7996 if (hw->mac.type != e1000_i354) 7997 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 7998 7999 wr32(E1000_DMACR, reg); 8000 8001 /* no lower threshold to disable 8002 * coalescing(smart fifb)-UTRESH=0 8003 */ 8004 wr32(E1000_DMCRTRH, 0); 8005 8006 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 8007 8008 wr32(E1000_DMCTLX, reg); 8009 8010 /* free space in tx packet buffer to wake from 8011 * DMA coal 8012 */ 8013 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 8014 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 8015 8016 /* make low power state decision controlled 8017 * by DMA coal 8018 */ 8019 reg = rd32(E1000_PCIEMISC); 8020 reg &= ~E1000_PCIEMISC_LX_DECISION; 8021 wr32(E1000_PCIEMISC, reg); 8022 } /* endif adapter->dmac is not disabled */ 8023 } else if (hw->mac.type == e1000_82580) { 8024 u32 reg = rd32(E1000_PCIEMISC); 8025 8026 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 8027 wr32(E1000_DMACR, 0); 8028 } 8029 } 8030 8031 /** 8032 * igb_read_i2c_byte - Reads 8 bit word over I2C 8033 * @hw: pointer to hardware structure 8034 * @byte_offset: byte offset to read 8035 * @dev_addr: device address 8036 * @data: value read 8037 * 8038 * Performs byte read operation over I2C interface at 8039 * a specified device address. 8040 **/ 8041 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8042 u8 dev_addr, u8 *data) 8043 { 8044 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8045 struct i2c_client *this_client = adapter->i2c_client; 8046 s32 status; 8047 u16 swfw_mask = 0; 8048 8049 if (!this_client) 8050 return E1000_ERR_I2C; 8051 8052 swfw_mask = E1000_SWFW_PHY0_SM; 8053 8054 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 8055 return E1000_ERR_SWFW_SYNC; 8056 8057 status = i2c_smbus_read_byte_data(this_client, byte_offset); 8058 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8059 8060 if (status < 0) 8061 return E1000_ERR_I2C; 8062 else { 8063 *data = status; 8064 return 0; 8065 } 8066 } 8067 8068 /** 8069 * igb_write_i2c_byte - Writes 8 bit word over I2C 8070 * @hw: pointer to hardware structure 8071 * @byte_offset: byte offset to write 8072 * @dev_addr: device address 8073 * @data: value to write 8074 * 8075 * Performs byte write operation over I2C interface at 8076 * a specified device address. 8077 **/ 8078 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8079 u8 dev_addr, u8 data) 8080 { 8081 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8082 struct i2c_client *this_client = adapter->i2c_client; 8083 s32 status; 8084 u16 swfw_mask = E1000_SWFW_PHY0_SM; 8085 8086 if (!this_client) 8087 return E1000_ERR_I2C; 8088 8089 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 8090 return E1000_ERR_SWFW_SYNC; 8091 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 8092 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8093 8094 if (status) 8095 return E1000_ERR_I2C; 8096 else 8097 return 0; 8098 8099 } 8100 8101 int igb_reinit_queues(struct igb_adapter *adapter) 8102 { 8103 struct net_device *netdev = adapter->netdev; 8104 struct pci_dev *pdev = adapter->pdev; 8105 int err = 0; 8106 8107 if (netif_running(netdev)) 8108 igb_close(netdev); 8109 8110 igb_reset_interrupt_capability(adapter); 8111 8112 if (igb_init_interrupt_scheme(adapter, true)) { 8113 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8114 return -ENOMEM; 8115 } 8116 8117 if (netif_running(netdev)) 8118 err = igb_open(netdev); 8119 8120 return err; 8121 } 8122 /* igb_main.c */ 8123