1 /* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 25 26 #include <linux/module.h> 27 #include <linux/types.h> 28 #include <linux/init.h> 29 #include <linux/bitops.h> 30 #include <linux/vmalloc.h> 31 #include <linux/pagemap.h> 32 #include <linux/netdevice.h> 33 #include <linux/ipv6.h> 34 #include <linux/slab.h> 35 #include <net/checksum.h> 36 #include <net/ip6_checksum.h> 37 #include <linux/net_tstamp.h> 38 #include <linux/mii.h> 39 #include <linux/ethtool.h> 40 #include <linux/if.h> 41 #include <linux/if_vlan.h> 42 #include <linux/pci.h> 43 #include <linux/pci-aspm.h> 44 #include <linux/delay.h> 45 #include <linux/interrupt.h> 46 #include <linux/ip.h> 47 #include <linux/tcp.h> 48 #include <linux/sctp.h> 49 #include <linux/if_ether.h> 50 #include <linux/aer.h> 51 #include <linux/prefetch.h> 52 #include <linux/pm_runtime.h> 53 #include <linux/etherdevice.h> 54 #ifdef CONFIG_IGB_DCA 55 #include <linux/dca.h> 56 #endif 57 #include <linux/i2c.h> 58 #include "igb.h" 59 60 #define MAJ 5 61 #define MIN 4 62 #define BUILD 0 63 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 64 __stringify(BUILD) "-k" 65 char igb_driver_name[] = "igb"; 66 char igb_driver_version[] = DRV_VERSION; 67 static const char igb_driver_string[] = 68 "Intel(R) Gigabit Ethernet Network Driver"; 69 static const char igb_copyright[] = 70 "Copyright (c) 2007-2014 Intel Corporation."; 71 72 static const struct e1000_info *igb_info_tbl[] = { 73 [board_82575] = &e1000_82575_info, 74 }; 75 76 static const struct pci_device_id igb_pci_tbl[] = { 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 112 /* required last entry */ 113 {0, } 114 }; 115 116 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 117 118 static int igb_setup_all_tx_resources(struct igb_adapter *); 119 static int igb_setup_all_rx_resources(struct igb_adapter *); 120 static void igb_free_all_tx_resources(struct igb_adapter *); 121 static void igb_free_all_rx_resources(struct igb_adapter *); 122 static void igb_setup_mrqc(struct igb_adapter *); 123 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 124 static void igb_remove(struct pci_dev *pdev); 125 static int igb_sw_init(struct igb_adapter *); 126 int igb_open(struct net_device *); 127 int igb_close(struct net_device *); 128 static void igb_configure(struct igb_adapter *); 129 static void igb_configure_tx(struct igb_adapter *); 130 static void igb_configure_rx(struct igb_adapter *); 131 static void igb_clean_all_tx_rings(struct igb_adapter *); 132 static void igb_clean_all_rx_rings(struct igb_adapter *); 133 static void igb_clean_tx_ring(struct igb_ring *); 134 static void igb_clean_rx_ring(struct igb_ring *); 135 static void igb_set_rx_mode(struct net_device *); 136 static void igb_update_phy_info(unsigned long); 137 static void igb_watchdog(unsigned long); 138 static void igb_watchdog_task(struct work_struct *); 139 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 140 static void igb_get_stats64(struct net_device *dev, 141 struct rtnl_link_stats64 *stats); 142 static int igb_change_mtu(struct net_device *, int); 143 static int igb_set_mac(struct net_device *, void *); 144 static void igb_set_uta(struct igb_adapter *adapter, bool set); 145 static irqreturn_t igb_intr(int irq, void *); 146 static irqreturn_t igb_intr_msi(int irq, void *); 147 static irqreturn_t igb_msix_other(int irq, void *); 148 static irqreturn_t igb_msix_ring(int irq, void *); 149 #ifdef CONFIG_IGB_DCA 150 static void igb_update_dca(struct igb_q_vector *); 151 static void igb_setup_dca(struct igb_adapter *); 152 #endif /* CONFIG_IGB_DCA */ 153 static int igb_poll(struct napi_struct *, int); 154 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 155 static int igb_clean_rx_irq(struct igb_q_vector *, int); 156 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 157 static void igb_tx_timeout(struct net_device *); 158 static void igb_reset_task(struct work_struct *); 159 static void igb_vlan_mode(struct net_device *netdev, 160 netdev_features_t features); 161 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 162 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 163 static void igb_restore_vlan(struct igb_adapter *); 164 static void igb_rar_set_index(struct igb_adapter *, u32); 165 static void igb_ping_all_vfs(struct igb_adapter *); 166 static void igb_msg_task(struct igb_adapter *); 167 static void igb_vmm_control(struct igb_adapter *); 168 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 169 static void igb_flush_mac_table(struct igb_adapter *); 170 static int igb_available_rars(struct igb_adapter *, u8); 171 static void igb_set_default_mac_filter(struct igb_adapter *); 172 static int igb_uc_sync(struct net_device *, const unsigned char *); 173 static int igb_uc_unsync(struct net_device *, const unsigned char *); 174 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 175 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 176 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 177 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 178 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 179 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 180 bool setting); 181 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 182 struct ifla_vf_info *ivi); 183 static void igb_check_vf_rate_limit(struct igb_adapter *); 184 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 185 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 186 187 #ifdef CONFIG_PCI_IOV 188 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 189 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 190 static int igb_disable_sriov(struct pci_dev *dev); 191 static int igb_pci_disable_sriov(struct pci_dev *dev); 192 #endif 193 194 static int igb_suspend(struct device *); 195 static int igb_resume(struct device *); 196 static int igb_runtime_suspend(struct device *dev); 197 static int igb_runtime_resume(struct device *dev); 198 static int igb_runtime_idle(struct device *dev); 199 static const struct dev_pm_ops igb_pm_ops = { 200 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 201 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 202 igb_runtime_idle) 203 }; 204 static void igb_shutdown(struct pci_dev *); 205 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 206 #ifdef CONFIG_IGB_DCA 207 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 208 static struct notifier_block dca_notifier = { 209 .notifier_call = igb_notify_dca, 210 .next = NULL, 211 .priority = 0 212 }; 213 #endif 214 #ifdef CONFIG_NET_POLL_CONTROLLER 215 /* for netdump / net console */ 216 static void igb_netpoll(struct net_device *); 217 #endif 218 #ifdef CONFIG_PCI_IOV 219 static unsigned int max_vfs; 220 module_param(max_vfs, uint, 0); 221 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 222 #endif /* CONFIG_PCI_IOV */ 223 224 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 225 pci_channel_state_t); 226 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 227 static void igb_io_resume(struct pci_dev *); 228 229 static const struct pci_error_handlers igb_err_handler = { 230 .error_detected = igb_io_error_detected, 231 .slot_reset = igb_io_slot_reset, 232 .resume = igb_io_resume, 233 }; 234 235 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 236 237 static struct pci_driver igb_driver = { 238 .name = igb_driver_name, 239 .id_table = igb_pci_tbl, 240 .probe = igb_probe, 241 .remove = igb_remove, 242 #ifdef CONFIG_PM 243 .driver.pm = &igb_pm_ops, 244 #endif 245 .shutdown = igb_shutdown, 246 .sriov_configure = igb_pci_sriov_configure, 247 .err_handler = &igb_err_handler 248 }; 249 250 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 251 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 252 MODULE_LICENSE("GPL"); 253 MODULE_VERSION(DRV_VERSION); 254 255 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 256 static int debug = -1; 257 module_param(debug, int, 0); 258 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 259 260 struct igb_reg_info { 261 u32 ofs; 262 char *name; 263 }; 264 265 static const struct igb_reg_info igb_reg_info_tbl[] = { 266 267 /* General Registers */ 268 {E1000_CTRL, "CTRL"}, 269 {E1000_STATUS, "STATUS"}, 270 {E1000_CTRL_EXT, "CTRL_EXT"}, 271 272 /* Interrupt Registers */ 273 {E1000_ICR, "ICR"}, 274 275 /* RX Registers */ 276 {E1000_RCTL, "RCTL"}, 277 {E1000_RDLEN(0), "RDLEN"}, 278 {E1000_RDH(0), "RDH"}, 279 {E1000_RDT(0), "RDT"}, 280 {E1000_RXDCTL(0), "RXDCTL"}, 281 {E1000_RDBAL(0), "RDBAL"}, 282 {E1000_RDBAH(0), "RDBAH"}, 283 284 /* TX Registers */ 285 {E1000_TCTL, "TCTL"}, 286 {E1000_TDBAL(0), "TDBAL"}, 287 {E1000_TDBAH(0), "TDBAH"}, 288 {E1000_TDLEN(0), "TDLEN"}, 289 {E1000_TDH(0), "TDH"}, 290 {E1000_TDT(0), "TDT"}, 291 {E1000_TXDCTL(0), "TXDCTL"}, 292 {E1000_TDFH, "TDFH"}, 293 {E1000_TDFT, "TDFT"}, 294 {E1000_TDFHS, "TDFHS"}, 295 {E1000_TDFPC, "TDFPC"}, 296 297 /* List Terminator */ 298 {} 299 }; 300 301 /* igb_regdump - register printout routine */ 302 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 303 { 304 int n = 0; 305 char rname[16]; 306 u32 regs[8]; 307 308 switch (reginfo->ofs) { 309 case E1000_RDLEN(0): 310 for (n = 0; n < 4; n++) 311 regs[n] = rd32(E1000_RDLEN(n)); 312 break; 313 case E1000_RDH(0): 314 for (n = 0; n < 4; n++) 315 regs[n] = rd32(E1000_RDH(n)); 316 break; 317 case E1000_RDT(0): 318 for (n = 0; n < 4; n++) 319 regs[n] = rd32(E1000_RDT(n)); 320 break; 321 case E1000_RXDCTL(0): 322 for (n = 0; n < 4; n++) 323 regs[n] = rd32(E1000_RXDCTL(n)); 324 break; 325 case E1000_RDBAL(0): 326 for (n = 0; n < 4; n++) 327 regs[n] = rd32(E1000_RDBAL(n)); 328 break; 329 case E1000_RDBAH(0): 330 for (n = 0; n < 4; n++) 331 regs[n] = rd32(E1000_RDBAH(n)); 332 break; 333 case E1000_TDBAL(0): 334 for (n = 0; n < 4; n++) 335 regs[n] = rd32(E1000_RDBAL(n)); 336 break; 337 case E1000_TDBAH(0): 338 for (n = 0; n < 4; n++) 339 regs[n] = rd32(E1000_TDBAH(n)); 340 break; 341 case E1000_TDLEN(0): 342 for (n = 0; n < 4; n++) 343 regs[n] = rd32(E1000_TDLEN(n)); 344 break; 345 case E1000_TDH(0): 346 for (n = 0; n < 4; n++) 347 regs[n] = rd32(E1000_TDH(n)); 348 break; 349 case E1000_TDT(0): 350 for (n = 0; n < 4; n++) 351 regs[n] = rd32(E1000_TDT(n)); 352 break; 353 case E1000_TXDCTL(0): 354 for (n = 0; n < 4; n++) 355 regs[n] = rd32(E1000_TXDCTL(n)); 356 break; 357 default: 358 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 359 return; 360 } 361 362 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 363 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 364 regs[2], regs[3]); 365 } 366 367 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 368 static void igb_dump(struct igb_adapter *adapter) 369 { 370 struct net_device *netdev = adapter->netdev; 371 struct e1000_hw *hw = &adapter->hw; 372 struct igb_reg_info *reginfo; 373 struct igb_ring *tx_ring; 374 union e1000_adv_tx_desc *tx_desc; 375 struct my_u0 { u64 a; u64 b; } *u0; 376 struct igb_ring *rx_ring; 377 union e1000_adv_rx_desc *rx_desc; 378 u32 staterr; 379 u16 i, n; 380 381 if (!netif_msg_hw(adapter)) 382 return; 383 384 /* Print netdevice Info */ 385 if (netdev) { 386 dev_info(&adapter->pdev->dev, "Net device Info\n"); 387 pr_info("Device Name state trans_start\n"); 388 pr_info("%-15s %016lX %016lX\n", netdev->name, 389 netdev->state, dev_trans_start(netdev)); 390 } 391 392 /* Print Registers */ 393 dev_info(&adapter->pdev->dev, "Register Dump\n"); 394 pr_info(" Register Name Value\n"); 395 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 396 reginfo->name; reginfo++) { 397 igb_regdump(hw, reginfo); 398 } 399 400 /* Print TX Ring Summary */ 401 if (!netdev || !netif_running(netdev)) 402 goto exit; 403 404 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 405 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 406 for (n = 0; n < adapter->num_tx_queues; n++) { 407 struct igb_tx_buffer *buffer_info; 408 tx_ring = adapter->tx_ring[n]; 409 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 410 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 411 n, tx_ring->next_to_use, tx_ring->next_to_clean, 412 (u64)dma_unmap_addr(buffer_info, dma), 413 dma_unmap_len(buffer_info, len), 414 buffer_info->next_to_watch, 415 (u64)buffer_info->time_stamp); 416 } 417 418 /* Print TX Rings */ 419 if (!netif_msg_tx_done(adapter)) 420 goto rx_ring_summary; 421 422 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 423 424 /* Transmit Descriptor Formats 425 * 426 * Advanced Transmit Descriptor 427 * +--------------------------------------------------------------+ 428 * 0 | Buffer Address [63:0] | 429 * +--------------------------------------------------------------+ 430 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 431 * +--------------------------------------------------------------+ 432 * 63 46 45 40 39 38 36 35 32 31 24 15 0 433 */ 434 435 for (n = 0; n < adapter->num_tx_queues; n++) { 436 tx_ring = adapter->tx_ring[n]; 437 pr_info("------------------------------------\n"); 438 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 439 pr_info("------------------------------------\n"); 440 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 441 442 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 443 const char *next_desc; 444 struct igb_tx_buffer *buffer_info; 445 tx_desc = IGB_TX_DESC(tx_ring, i); 446 buffer_info = &tx_ring->tx_buffer_info[i]; 447 u0 = (struct my_u0 *)tx_desc; 448 if (i == tx_ring->next_to_use && 449 i == tx_ring->next_to_clean) 450 next_desc = " NTC/U"; 451 else if (i == tx_ring->next_to_use) 452 next_desc = " NTU"; 453 else if (i == tx_ring->next_to_clean) 454 next_desc = " NTC"; 455 else 456 next_desc = ""; 457 458 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 459 i, le64_to_cpu(u0->a), 460 le64_to_cpu(u0->b), 461 (u64)dma_unmap_addr(buffer_info, dma), 462 dma_unmap_len(buffer_info, len), 463 buffer_info->next_to_watch, 464 (u64)buffer_info->time_stamp, 465 buffer_info->skb, next_desc); 466 467 if (netif_msg_pktdata(adapter) && buffer_info->skb) 468 print_hex_dump(KERN_INFO, "", 469 DUMP_PREFIX_ADDRESS, 470 16, 1, buffer_info->skb->data, 471 dma_unmap_len(buffer_info, len), 472 true); 473 } 474 } 475 476 /* Print RX Rings Summary */ 477 rx_ring_summary: 478 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 479 pr_info("Queue [NTU] [NTC]\n"); 480 for (n = 0; n < adapter->num_rx_queues; n++) { 481 rx_ring = adapter->rx_ring[n]; 482 pr_info(" %5d %5X %5X\n", 483 n, rx_ring->next_to_use, rx_ring->next_to_clean); 484 } 485 486 /* Print RX Rings */ 487 if (!netif_msg_rx_status(adapter)) 488 goto exit; 489 490 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 491 492 /* Advanced Receive Descriptor (Read) Format 493 * 63 1 0 494 * +-----------------------------------------------------+ 495 * 0 | Packet Buffer Address [63:1] |A0/NSE| 496 * +----------------------------------------------+------+ 497 * 8 | Header Buffer Address [63:1] | DD | 498 * +-----------------------------------------------------+ 499 * 500 * 501 * Advanced Receive Descriptor (Write-Back) Format 502 * 503 * 63 48 47 32 31 30 21 20 17 16 4 3 0 504 * +------------------------------------------------------+ 505 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 506 * | Checksum Ident | | | | Type | Type | 507 * +------------------------------------------------------+ 508 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 509 * +------------------------------------------------------+ 510 * 63 48 47 32 31 20 19 0 511 */ 512 513 for (n = 0; n < adapter->num_rx_queues; n++) { 514 rx_ring = adapter->rx_ring[n]; 515 pr_info("------------------------------------\n"); 516 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 517 pr_info("------------------------------------\n"); 518 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 519 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 520 521 for (i = 0; i < rx_ring->count; i++) { 522 const char *next_desc; 523 struct igb_rx_buffer *buffer_info; 524 buffer_info = &rx_ring->rx_buffer_info[i]; 525 rx_desc = IGB_RX_DESC(rx_ring, i); 526 u0 = (struct my_u0 *)rx_desc; 527 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 528 529 if (i == rx_ring->next_to_use) 530 next_desc = " NTU"; 531 else if (i == rx_ring->next_to_clean) 532 next_desc = " NTC"; 533 else 534 next_desc = ""; 535 536 if (staterr & E1000_RXD_STAT_DD) { 537 /* Descriptor Done */ 538 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 539 "RWB", i, 540 le64_to_cpu(u0->a), 541 le64_to_cpu(u0->b), 542 next_desc); 543 } else { 544 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 545 "R ", i, 546 le64_to_cpu(u0->a), 547 le64_to_cpu(u0->b), 548 (u64)buffer_info->dma, 549 next_desc); 550 551 if (netif_msg_pktdata(adapter) && 552 buffer_info->dma && buffer_info->page) { 553 print_hex_dump(KERN_INFO, "", 554 DUMP_PREFIX_ADDRESS, 555 16, 1, 556 page_address(buffer_info->page) + 557 buffer_info->page_offset, 558 igb_rx_bufsz(rx_ring), true); 559 } 560 } 561 } 562 } 563 564 exit: 565 return; 566 } 567 568 /** 569 * igb_get_i2c_data - Reads the I2C SDA data bit 570 * @hw: pointer to hardware structure 571 * @i2cctl: Current value of I2CCTL register 572 * 573 * Returns the I2C data bit value 574 **/ 575 static int igb_get_i2c_data(void *data) 576 { 577 struct igb_adapter *adapter = (struct igb_adapter *)data; 578 struct e1000_hw *hw = &adapter->hw; 579 s32 i2cctl = rd32(E1000_I2CPARAMS); 580 581 return !!(i2cctl & E1000_I2C_DATA_IN); 582 } 583 584 /** 585 * igb_set_i2c_data - Sets the I2C data bit 586 * @data: pointer to hardware structure 587 * @state: I2C data value (0 or 1) to set 588 * 589 * Sets the I2C data bit 590 **/ 591 static void igb_set_i2c_data(void *data, int state) 592 { 593 struct igb_adapter *adapter = (struct igb_adapter *)data; 594 struct e1000_hw *hw = &adapter->hw; 595 s32 i2cctl = rd32(E1000_I2CPARAMS); 596 597 if (state) 598 i2cctl |= E1000_I2C_DATA_OUT; 599 else 600 i2cctl &= ~E1000_I2C_DATA_OUT; 601 602 i2cctl &= ~E1000_I2C_DATA_OE_N; 603 i2cctl |= E1000_I2C_CLK_OE_N; 604 wr32(E1000_I2CPARAMS, i2cctl); 605 wrfl(); 606 607 } 608 609 /** 610 * igb_set_i2c_clk - Sets the I2C SCL clock 611 * @data: pointer to hardware structure 612 * @state: state to set clock 613 * 614 * Sets the I2C clock line to state 615 **/ 616 static void igb_set_i2c_clk(void *data, int state) 617 { 618 struct igb_adapter *adapter = (struct igb_adapter *)data; 619 struct e1000_hw *hw = &adapter->hw; 620 s32 i2cctl = rd32(E1000_I2CPARAMS); 621 622 if (state) { 623 i2cctl |= E1000_I2C_CLK_OUT; 624 i2cctl &= ~E1000_I2C_CLK_OE_N; 625 } else { 626 i2cctl &= ~E1000_I2C_CLK_OUT; 627 i2cctl &= ~E1000_I2C_CLK_OE_N; 628 } 629 wr32(E1000_I2CPARAMS, i2cctl); 630 wrfl(); 631 } 632 633 /** 634 * igb_get_i2c_clk - Gets the I2C SCL clock state 635 * @data: pointer to hardware structure 636 * 637 * Gets the I2C clock state 638 **/ 639 static int igb_get_i2c_clk(void *data) 640 { 641 struct igb_adapter *adapter = (struct igb_adapter *)data; 642 struct e1000_hw *hw = &adapter->hw; 643 s32 i2cctl = rd32(E1000_I2CPARAMS); 644 645 return !!(i2cctl & E1000_I2C_CLK_IN); 646 } 647 648 static const struct i2c_algo_bit_data igb_i2c_algo = { 649 .setsda = igb_set_i2c_data, 650 .setscl = igb_set_i2c_clk, 651 .getsda = igb_get_i2c_data, 652 .getscl = igb_get_i2c_clk, 653 .udelay = 5, 654 .timeout = 20, 655 }; 656 657 /** 658 * igb_get_hw_dev - return device 659 * @hw: pointer to hardware structure 660 * 661 * used by hardware layer to print debugging information 662 **/ 663 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 664 { 665 struct igb_adapter *adapter = hw->back; 666 return adapter->netdev; 667 } 668 669 /** 670 * igb_init_module - Driver Registration Routine 671 * 672 * igb_init_module is the first routine called when the driver is 673 * loaded. All it does is register with the PCI subsystem. 674 **/ 675 static int __init igb_init_module(void) 676 { 677 int ret; 678 679 pr_info("%s - version %s\n", 680 igb_driver_string, igb_driver_version); 681 pr_info("%s\n", igb_copyright); 682 683 #ifdef CONFIG_IGB_DCA 684 dca_register_notify(&dca_notifier); 685 #endif 686 ret = pci_register_driver(&igb_driver); 687 return ret; 688 } 689 690 module_init(igb_init_module); 691 692 /** 693 * igb_exit_module - Driver Exit Cleanup Routine 694 * 695 * igb_exit_module is called just before the driver is removed 696 * from memory. 697 **/ 698 static void __exit igb_exit_module(void) 699 { 700 #ifdef CONFIG_IGB_DCA 701 dca_unregister_notify(&dca_notifier); 702 #endif 703 pci_unregister_driver(&igb_driver); 704 } 705 706 module_exit(igb_exit_module); 707 708 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 709 /** 710 * igb_cache_ring_register - Descriptor ring to register mapping 711 * @adapter: board private structure to initialize 712 * 713 * Once we know the feature-set enabled for the device, we'll cache 714 * the register offset the descriptor ring is assigned to. 715 **/ 716 static void igb_cache_ring_register(struct igb_adapter *adapter) 717 { 718 int i = 0, j = 0; 719 u32 rbase_offset = adapter->vfs_allocated_count; 720 721 switch (adapter->hw.mac.type) { 722 case e1000_82576: 723 /* The queues are allocated for virtualization such that VF 0 724 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 725 * In order to avoid collision we start at the first free queue 726 * and continue consuming queues in the same sequence 727 */ 728 if (adapter->vfs_allocated_count) { 729 for (; i < adapter->rss_queues; i++) 730 adapter->rx_ring[i]->reg_idx = rbase_offset + 731 Q_IDX_82576(i); 732 } 733 /* Fall through */ 734 case e1000_82575: 735 case e1000_82580: 736 case e1000_i350: 737 case e1000_i354: 738 case e1000_i210: 739 case e1000_i211: 740 /* Fall through */ 741 default: 742 for (; i < adapter->num_rx_queues; i++) 743 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 744 for (; j < adapter->num_tx_queues; j++) 745 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 746 break; 747 } 748 } 749 750 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 751 { 752 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 753 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr); 754 u32 value = 0; 755 756 if (E1000_REMOVED(hw_addr)) 757 return ~value; 758 759 value = readl(&hw_addr[reg]); 760 761 /* reads should not return all F's */ 762 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 763 struct net_device *netdev = igb->netdev; 764 hw->hw_addr = NULL; 765 netif_device_detach(netdev); 766 netdev_err(netdev, "PCIe link lost, device now detached\n"); 767 } 768 769 return value; 770 } 771 772 /** 773 * igb_write_ivar - configure ivar for given MSI-X vector 774 * @hw: pointer to the HW structure 775 * @msix_vector: vector number we are allocating to a given ring 776 * @index: row index of IVAR register to write within IVAR table 777 * @offset: column offset of in IVAR, should be multiple of 8 778 * 779 * This function is intended to handle the writing of the IVAR register 780 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 781 * each containing an cause allocation for an Rx and Tx ring, and a 782 * variable number of rows depending on the number of queues supported. 783 **/ 784 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 785 int index, int offset) 786 { 787 u32 ivar = array_rd32(E1000_IVAR0, index); 788 789 /* clear any bits that are currently set */ 790 ivar &= ~((u32)0xFF << offset); 791 792 /* write vector and valid bit */ 793 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 794 795 array_wr32(E1000_IVAR0, index, ivar); 796 } 797 798 #define IGB_N0_QUEUE -1 799 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 800 { 801 struct igb_adapter *adapter = q_vector->adapter; 802 struct e1000_hw *hw = &adapter->hw; 803 int rx_queue = IGB_N0_QUEUE; 804 int tx_queue = IGB_N0_QUEUE; 805 u32 msixbm = 0; 806 807 if (q_vector->rx.ring) 808 rx_queue = q_vector->rx.ring->reg_idx; 809 if (q_vector->tx.ring) 810 tx_queue = q_vector->tx.ring->reg_idx; 811 812 switch (hw->mac.type) { 813 case e1000_82575: 814 /* The 82575 assigns vectors using a bitmask, which matches the 815 * bitmask for the EICR/EIMS/EIMC registers. To assign one 816 * or more queues to a vector, we write the appropriate bits 817 * into the MSIXBM register for that vector. 818 */ 819 if (rx_queue > IGB_N0_QUEUE) 820 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 821 if (tx_queue > IGB_N0_QUEUE) 822 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 823 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 824 msixbm |= E1000_EIMS_OTHER; 825 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 826 q_vector->eims_value = msixbm; 827 break; 828 case e1000_82576: 829 /* 82576 uses a table that essentially consists of 2 columns 830 * with 8 rows. The ordering is column-major so we use the 831 * lower 3 bits as the row index, and the 4th bit as the 832 * column offset. 833 */ 834 if (rx_queue > IGB_N0_QUEUE) 835 igb_write_ivar(hw, msix_vector, 836 rx_queue & 0x7, 837 (rx_queue & 0x8) << 1); 838 if (tx_queue > IGB_N0_QUEUE) 839 igb_write_ivar(hw, msix_vector, 840 tx_queue & 0x7, 841 ((tx_queue & 0x8) << 1) + 8); 842 q_vector->eims_value = BIT(msix_vector); 843 break; 844 case e1000_82580: 845 case e1000_i350: 846 case e1000_i354: 847 case e1000_i210: 848 case e1000_i211: 849 /* On 82580 and newer adapters the scheme is similar to 82576 850 * however instead of ordering column-major we have things 851 * ordered row-major. So we traverse the table by using 852 * bit 0 as the column offset, and the remaining bits as the 853 * row index. 854 */ 855 if (rx_queue > IGB_N0_QUEUE) 856 igb_write_ivar(hw, msix_vector, 857 rx_queue >> 1, 858 (rx_queue & 0x1) << 4); 859 if (tx_queue > IGB_N0_QUEUE) 860 igb_write_ivar(hw, msix_vector, 861 tx_queue >> 1, 862 ((tx_queue & 0x1) << 4) + 8); 863 q_vector->eims_value = BIT(msix_vector); 864 break; 865 default: 866 BUG(); 867 break; 868 } 869 870 /* add q_vector eims value to global eims_enable_mask */ 871 adapter->eims_enable_mask |= q_vector->eims_value; 872 873 /* configure q_vector to set itr on first interrupt */ 874 q_vector->set_itr = 1; 875 } 876 877 /** 878 * igb_configure_msix - Configure MSI-X hardware 879 * @adapter: board private structure to initialize 880 * 881 * igb_configure_msix sets up the hardware to properly 882 * generate MSI-X interrupts. 883 **/ 884 static void igb_configure_msix(struct igb_adapter *adapter) 885 { 886 u32 tmp; 887 int i, vector = 0; 888 struct e1000_hw *hw = &adapter->hw; 889 890 adapter->eims_enable_mask = 0; 891 892 /* set vector for other causes, i.e. link changes */ 893 switch (hw->mac.type) { 894 case e1000_82575: 895 tmp = rd32(E1000_CTRL_EXT); 896 /* enable MSI-X PBA support*/ 897 tmp |= E1000_CTRL_EXT_PBA_CLR; 898 899 /* Auto-Mask interrupts upon ICR read. */ 900 tmp |= E1000_CTRL_EXT_EIAME; 901 tmp |= E1000_CTRL_EXT_IRCA; 902 903 wr32(E1000_CTRL_EXT, tmp); 904 905 /* enable msix_other interrupt */ 906 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 907 adapter->eims_other = E1000_EIMS_OTHER; 908 909 break; 910 911 case e1000_82576: 912 case e1000_82580: 913 case e1000_i350: 914 case e1000_i354: 915 case e1000_i210: 916 case e1000_i211: 917 /* Turn on MSI-X capability first, or our settings 918 * won't stick. And it will take days to debug. 919 */ 920 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 921 E1000_GPIE_PBA | E1000_GPIE_EIAME | 922 E1000_GPIE_NSICR); 923 924 /* enable msix_other interrupt */ 925 adapter->eims_other = BIT(vector); 926 tmp = (vector++ | E1000_IVAR_VALID) << 8; 927 928 wr32(E1000_IVAR_MISC, tmp); 929 break; 930 default: 931 /* do nothing, since nothing else supports MSI-X */ 932 break; 933 } /* switch (hw->mac.type) */ 934 935 adapter->eims_enable_mask |= adapter->eims_other; 936 937 for (i = 0; i < adapter->num_q_vectors; i++) 938 igb_assign_vector(adapter->q_vector[i], vector++); 939 940 wrfl(); 941 } 942 943 /** 944 * igb_request_msix - Initialize MSI-X interrupts 945 * @adapter: board private structure to initialize 946 * 947 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 948 * kernel. 949 **/ 950 static int igb_request_msix(struct igb_adapter *adapter) 951 { 952 struct net_device *netdev = adapter->netdev; 953 int i, err = 0, vector = 0, free_vector = 0; 954 955 err = request_irq(adapter->msix_entries[vector].vector, 956 igb_msix_other, 0, netdev->name, adapter); 957 if (err) 958 goto err_out; 959 960 for (i = 0; i < adapter->num_q_vectors; i++) { 961 struct igb_q_vector *q_vector = adapter->q_vector[i]; 962 963 vector++; 964 965 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 966 967 if (q_vector->rx.ring && q_vector->tx.ring) 968 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 969 q_vector->rx.ring->queue_index); 970 else if (q_vector->tx.ring) 971 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 972 q_vector->tx.ring->queue_index); 973 else if (q_vector->rx.ring) 974 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 975 q_vector->rx.ring->queue_index); 976 else 977 sprintf(q_vector->name, "%s-unused", netdev->name); 978 979 err = request_irq(adapter->msix_entries[vector].vector, 980 igb_msix_ring, 0, q_vector->name, 981 q_vector); 982 if (err) 983 goto err_free; 984 } 985 986 igb_configure_msix(adapter); 987 return 0; 988 989 err_free: 990 /* free already assigned IRQs */ 991 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 992 993 vector--; 994 for (i = 0; i < vector; i++) { 995 free_irq(adapter->msix_entries[free_vector++].vector, 996 adapter->q_vector[i]); 997 } 998 err_out: 999 return err; 1000 } 1001 1002 /** 1003 * igb_free_q_vector - Free memory allocated for specific interrupt vector 1004 * @adapter: board private structure to initialize 1005 * @v_idx: Index of vector to be freed 1006 * 1007 * This function frees the memory allocated to the q_vector. 1008 **/ 1009 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 1010 { 1011 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1012 1013 adapter->q_vector[v_idx] = NULL; 1014 1015 /* igb_get_stats64() might access the rings on this vector, 1016 * we must wait a grace period before freeing it. 1017 */ 1018 if (q_vector) 1019 kfree_rcu(q_vector, rcu); 1020 } 1021 1022 /** 1023 * igb_reset_q_vector - Reset config for interrupt vector 1024 * @adapter: board private structure to initialize 1025 * @v_idx: Index of vector to be reset 1026 * 1027 * If NAPI is enabled it will delete any references to the 1028 * NAPI struct. This is preparation for igb_free_q_vector. 1029 **/ 1030 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1031 { 1032 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1033 1034 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1035 * allocated. So, q_vector is NULL so we should stop here. 1036 */ 1037 if (!q_vector) 1038 return; 1039 1040 if (q_vector->tx.ring) 1041 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1042 1043 if (q_vector->rx.ring) 1044 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1045 1046 netif_napi_del(&q_vector->napi); 1047 1048 } 1049 1050 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1051 { 1052 int v_idx = adapter->num_q_vectors; 1053 1054 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1055 pci_disable_msix(adapter->pdev); 1056 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1057 pci_disable_msi(adapter->pdev); 1058 1059 while (v_idx--) 1060 igb_reset_q_vector(adapter, v_idx); 1061 } 1062 1063 /** 1064 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1065 * @adapter: board private structure to initialize 1066 * 1067 * This function frees the memory allocated to the q_vectors. In addition if 1068 * NAPI is enabled it will delete any references to the NAPI struct prior 1069 * to freeing the q_vector. 1070 **/ 1071 static void igb_free_q_vectors(struct igb_adapter *adapter) 1072 { 1073 int v_idx = adapter->num_q_vectors; 1074 1075 adapter->num_tx_queues = 0; 1076 adapter->num_rx_queues = 0; 1077 adapter->num_q_vectors = 0; 1078 1079 while (v_idx--) { 1080 igb_reset_q_vector(adapter, v_idx); 1081 igb_free_q_vector(adapter, v_idx); 1082 } 1083 } 1084 1085 /** 1086 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1087 * @adapter: board private structure to initialize 1088 * 1089 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1090 * MSI-X interrupts allocated. 1091 */ 1092 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1093 { 1094 igb_free_q_vectors(adapter); 1095 igb_reset_interrupt_capability(adapter); 1096 } 1097 1098 /** 1099 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1100 * @adapter: board private structure to initialize 1101 * @msix: boolean value of MSIX capability 1102 * 1103 * Attempt to configure interrupts using the best available 1104 * capabilities of the hardware and kernel. 1105 **/ 1106 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1107 { 1108 int err; 1109 int numvecs, i; 1110 1111 if (!msix) 1112 goto msi_only; 1113 adapter->flags |= IGB_FLAG_HAS_MSIX; 1114 1115 /* Number of supported queues. */ 1116 adapter->num_rx_queues = adapter->rss_queues; 1117 if (adapter->vfs_allocated_count) 1118 adapter->num_tx_queues = 1; 1119 else 1120 adapter->num_tx_queues = adapter->rss_queues; 1121 1122 /* start with one vector for every Rx queue */ 1123 numvecs = adapter->num_rx_queues; 1124 1125 /* if Tx handler is separate add 1 for every Tx queue */ 1126 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1127 numvecs += adapter->num_tx_queues; 1128 1129 /* store the number of vectors reserved for queues */ 1130 adapter->num_q_vectors = numvecs; 1131 1132 /* add 1 vector for link status interrupts */ 1133 numvecs++; 1134 for (i = 0; i < numvecs; i++) 1135 adapter->msix_entries[i].entry = i; 1136 1137 err = pci_enable_msix_range(adapter->pdev, 1138 adapter->msix_entries, 1139 numvecs, 1140 numvecs); 1141 if (err > 0) 1142 return; 1143 1144 igb_reset_interrupt_capability(adapter); 1145 1146 /* If we can't do MSI-X, try MSI */ 1147 msi_only: 1148 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1149 #ifdef CONFIG_PCI_IOV 1150 /* disable SR-IOV for non MSI-X configurations */ 1151 if (adapter->vf_data) { 1152 struct e1000_hw *hw = &adapter->hw; 1153 /* disable iov and allow time for transactions to clear */ 1154 pci_disable_sriov(adapter->pdev); 1155 msleep(500); 1156 1157 kfree(adapter->vf_mac_list); 1158 adapter->vf_mac_list = NULL; 1159 kfree(adapter->vf_data); 1160 adapter->vf_data = NULL; 1161 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1162 wrfl(); 1163 msleep(100); 1164 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1165 } 1166 #endif 1167 adapter->vfs_allocated_count = 0; 1168 adapter->rss_queues = 1; 1169 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1170 adapter->num_rx_queues = 1; 1171 adapter->num_tx_queues = 1; 1172 adapter->num_q_vectors = 1; 1173 if (!pci_enable_msi(adapter->pdev)) 1174 adapter->flags |= IGB_FLAG_HAS_MSI; 1175 } 1176 1177 static void igb_add_ring(struct igb_ring *ring, 1178 struct igb_ring_container *head) 1179 { 1180 head->ring = ring; 1181 head->count++; 1182 } 1183 1184 /** 1185 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1186 * @adapter: board private structure to initialize 1187 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1188 * @v_idx: index of vector in adapter struct 1189 * @txr_count: total number of Tx rings to allocate 1190 * @txr_idx: index of first Tx ring to allocate 1191 * @rxr_count: total number of Rx rings to allocate 1192 * @rxr_idx: index of first Rx ring to allocate 1193 * 1194 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1195 **/ 1196 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1197 int v_count, int v_idx, 1198 int txr_count, int txr_idx, 1199 int rxr_count, int rxr_idx) 1200 { 1201 struct igb_q_vector *q_vector; 1202 struct igb_ring *ring; 1203 int ring_count, size; 1204 1205 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1206 if (txr_count > 1 || rxr_count > 1) 1207 return -ENOMEM; 1208 1209 ring_count = txr_count + rxr_count; 1210 size = sizeof(struct igb_q_vector) + 1211 (sizeof(struct igb_ring) * ring_count); 1212 1213 /* allocate q_vector and rings */ 1214 q_vector = adapter->q_vector[v_idx]; 1215 if (!q_vector) { 1216 q_vector = kzalloc(size, GFP_KERNEL); 1217 } else if (size > ksize(q_vector)) { 1218 kfree_rcu(q_vector, rcu); 1219 q_vector = kzalloc(size, GFP_KERNEL); 1220 } else { 1221 memset(q_vector, 0, size); 1222 } 1223 if (!q_vector) 1224 return -ENOMEM; 1225 1226 /* initialize NAPI */ 1227 netif_napi_add(adapter->netdev, &q_vector->napi, 1228 igb_poll, 64); 1229 1230 /* tie q_vector and adapter together */ 1231 adapter->q_vector[v_idx] = q_vector; 1232 q_vector->adapter = adapter; 1233 1234 /* initialize work limits */ 1235 q_vector->tx.work_limit = adapter->tx_work_limit; 1236 1237 /* initialize ITR configuration */ 1238 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1239 q_vector->itr_val = IGB_START_ITR; 1240 1241 /* initialize pointer to rings */ 1242 ring = q_vector->ring; 1243 1244 /* intialize ITR */ 1245 if (rxr_count) { 1246 /* rx or rx/tx vector */ 1247 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1248 q_vector->itr_val = adapter->rx_itr_setting; 1249 } else { 1250 /* tx only vector */ 1251 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1252 q_vector->itr_val = adapter->tx_itr_setting; 1253 } 1254 1255 if (txr_count) { 1256 /* assign generic ring traits */ 1257 ring->dev = &adapter->pdev->dev; 1258 ring->netdev = adapter->netdev; 1259 1260 /* configure backlink on ring */ 1261 ring->q_vector = q_vector; 1262 1263 /* update q_vector Tx values */ 1264 igb_add_ring(ring, &q_vector->tx); 1265 1266 /* For 82575, context index must be unique per ring. */ 1267 if (adapter->hw.mac.type == e1000_82575) 1268 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1269 1270 /* apply Tx specific ring traits */ 1271 ring->count = adapter->tx_ring_count; 1272 ring->queue_index = txr_idx; 1273 1274 u64_stats_init(&ring->tx_syncp); 1275 u64_stats_init(&ring->tx_syncp2); 1276 1277 /* assign ring to adapter */ 1278 adapter->tx_ring[txr_idx] = ring; 1279 1280 /* push pointer to next ring */ 1281 ring++; 1282 } 1283 1284 if (rxr_count) { 1285 /* assign generic ring traits */ 1286 ring->dev = &adapter->pdev->dev; 1287 ring->netdev = adapter->netdev; 1288 1289 /* configure backlink on ring */ 1290 ring->q_vector = q_vector; 1291 1292 /* update q_vector Rx values */ 1293 igb_add_ring(ring, &q_vector->rx); 1294 1295 /* set flag indicating ring supports SCTP checksum offload */ 1296 if (adapter->hw.mac.type >= e1000_82576) 1297 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1298 1299 /* On i350, i354, i210, and i211, loopback VLAN packets 1300 * have the tag byte-swapped. 1301 */ 1302 if (adapter->hw.mac.type >= e1000_i350) 1303 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1304 1305 /* apply Rx specific ring traits */ 1306 ring->count = adapter->rx_ring_count; 1307 ring->queue_index = rxr_idx; 1308 1309 u64_stats_init(&ring->rx_syncp); 1310 1311 /* assign ring to adapter */ 1312 adapter->rx_ring[rxr_idx] = ring; 1313 } 1314 1315 return 0; 1316 } 1317 1318 1319 /** 1320 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1321 * @adapter: board private structure to initialize 1322 * 1323 * We allocate one q_vector per queue interrupt. If allocation fails we 1324 * return -ENOMEM. 1325 **/ 1326 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1327 { 1328 int q_vectors = adapter->num_q_vectors; 1329 int rxr_remaining = adapter->num_rx_queues; 1330 int txr_remaining = adapter->num_tx_queues; 1331 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1332 int err; 1333 1334 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1335 for (; rxr_remaining; v_idx++) { 1336 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1337 0, 0, 1, rxr_idx); 1338 1339 if (err) 1340 goto err_out; 1341 1342 /* update counts and index */ 1343 rxr_remaining--; 1344 rxr_idx++; 1345 } 1346 } 1347 1348 for (; v_idx < q_vectors; v_idx++) { 1349 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1350 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1351 1352 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1353 tqpv, txr_idx, rqpv, rxr_idx); 1354 1355 if (err) 1356 goto err_out; 1357 1358 /* update counts and index */ 1359 rxr_remaining -= rqpv; 1360 txr_remaining -= tqpv; 1361 rxr_idx++; 1362 txr_idx++; 1363 } 1364 1365 return 0; 1366 1367 err_out: 1368 adapter->num_tx_queues = 0; 1369 adapter->num_rx_queues = 0; 1370 adapter->num_q_vectors = 0; 1371 1372 while (v_idx--) 1373 igb_free_q_vector(adapter, v_idx); 1374 1375 return -ENOMEM; 1376 } 1377 1378 /** 1379 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1380 * @adapter: board private structure to initialize 1381 * @msix: boolean value of MSIX capability 1382 * 1383 * This function initializes the interrupts and allocates all of the queues. 1384 **/ 1385 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1386 { 1387 struct pci_dev *pdev = adapter->pdev; 1388 int err; 1389 1390 igb_set_interrupt_capability(adapter, msix); 1391 1392 err = igb_alloc_q_vectors(adapter); 1393 if (err) { 1394 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1395 goto err_alloc_q_vectors; 1396 } 1397 1398 igb_cache_ring_register(adapter); 1399 1400 return 0; 1401 1402 err_alloc_q_vectors: 1403 igb_reset_interrupt_capability(adapter); 1404 return err; 1405 } 1406 1407 /** 1408 * igb_request_irq - initialize interrupts 1409 * @adapter: board private structure to initialize 1410 * 1411 * Attempts to configure interrupts using the best available 1412 * capabilities of the hardware and kernel. 1413 **/ 1414 static int igb_request_irq(struct igb_adapter *adapter) 1415 { 1416 struct net_device *netdev = adapter->netdev; 1417 struct pci_dev *pdev = adapter->pdev; 1418 int err = 0; 1419 1420 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1421 err = igb_request_msix(adapter); 1422 if (!err) 1423 goto request_done; 1424 /* fall back to MSI */ 1425 igb_free_all_tx_resources(adapter); 1426 igb_free_all_rx_resources(adapter); 1427 1428 igb_clear_interrupt_scheme(adapter); 1429 err = igb_init_interrupt_scheme(adapter, false); 1430 if (err) 1431 goto request_done; 1432 1433 igb_setup_all_tx_resources(adapter); 1434 igb_setup_all_rx_resources(adapter); 1435 igb_configure(adapter); 1436 } 1437 1438 igb_assign_vector(adapter->q_vector[0], 0); 1439 1440 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1441 err = request_irq(pdev->irq, igb_intr_msi, 0, 1442 netdev->name, adapter); 1443 if (!err) 1444 goto request_done; 1445 1446 /* fall back to legacy interrupts */ 1447 igb_reset_interrupt_capability(adapter); 1448 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1449 } 1450 1451 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1452 netdev->name, adapter); 1453 1454 if (err) 1455 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1456 err); 1457 1458 request_done: 1459 return err; 1460 } 1461 1462 static void igb_free_irq(struct igb_adapter *adapter) 1463 { 1464 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1465 int vector = 0, i; 1466 1467 free_irq(adapter->msix_entries[vector++].vector, adapter); 1468 1469 for (i = 0; i < adapter->num_q_vectors; i++) 1470 free_irq(adapter->msix_entries[vector++].vector, 1471 adapter->q_vector[i]); 1472 } else { 1473 free_irq(adapter->pdev->irq, adapter); 1474 } 1475 } 1476 1477 /** 1478 * igb_irq_disable - Mask off interrupt generation on the NIC 1479 * @adapter: board private structure 1480 **/ 1481 static void igb_irq_disable(struct igb_adapter *adapter) 1482 { 1483 struct e1000_hw *hw = &adapter->hw; 1484 1485 /* we need to be careful when disabling interrupts. The VFs are also 1486 * mapped into these registers and so clearing the bits can cause 1487 * issues on the VF drivers so we only need to clear what we set 1488 */ 1489 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1490 u32 regval = rd32(E1000_EIAM); 1491 1492 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1493 wr32(E1000_EIMC, adapter->eims_enable_mask); 1494 regval = rd32(E1000_EIAC); 1495 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1496 } 1497 1498 wr32(E1000_IAM, 0); 1499 wr32(E1000_IMC, ~0); 1500 wrfl(); 1501 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1502 int i; 1503 1504 for (i = 0; i < adapter->num_q_vectors; i++) 1505 synchronize_irq(adapter->msix_entries[i].vector); 1506 } else { 1507 synchronize_irq(adapter->pdev->irq); 1508 } 1509 } 1510 1511 /** 1512 * igb_irq_enable - Enable default interrupt generation settings 1513 * @adapter: board private structure 1514 **/ 1515 static void igb_irq_enable(struct igb_adapter *adapter) 1516 { 1517 struct e1000_hw *hw = &adapter->hw; 1518 1519 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1520 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1521 u32 regval = rd32(E1000_EIAC); 1522 1523 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1524 regval = rd32(E1000_EIAM); 1525 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1526 wr32(E1000_EIMS, adapter->eims_enable_mask); 1527 if (adapter->vfs_allocated_count) { 1528 wr32(E1000_MBVFIMR, 0xFF); 1529 ims |= E1000_IMS_VMMB; 1530 } 1531 wr32(E1000_IMS, ims); 1532 } else { 1533 wr32(E1000_IMS, IMS_ENABLE_MASK | 1534 E1000_IMS_DRSTA); 1535 wr32(E1000_IAM, IMS_ENABLE_MASK | 1536 E1000_IMS_DRSTA); 1537 } 1538 } 1539 1540 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1541 { 1542 struct e1000_hw *hw = &adapter->hw; 1543 u16 pf_id = adapter->vfs_allocated_count; 1544 u16 vid = adapter->hw.mng_cookie.vlan_id; 1545 u16 old_vid = adapter->mng_vlan_id; 1546 1547 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1548 /* add VID to filter table */ 1549 igb_vfta_set(hw, vid, pf_id, true, true); 1550 adapter->mng_vlan_id = vid; 1551 } else { 1552 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1553 } 1554 1555 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1556 (vid != old_vid) && 1557 !test_bit(old_vid, adapter->active_vlans)) { 1558 /* remove VID from filter table */ 1559 igb_vfta_set(hw, vid, pf_id, false, true); 1560 } 1561 } 1562 1563 /** 1564 * igb_release_hw_control - release control of the h/w to f/w 1565 * @adapter: address of board private structure 1566 * 1567 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1568 * For ASF and Pass Through versions of f/w this means that the 1569 * driver is no longer loaded. 1570 **/ 1571 static void igb_release_hw_control(struct igb_adapter *adapter) 1572 { 1573 struct e1000_hw *hw = &adapter->hw; 1574 u32 ctrl_ext; 1575 1576 /* Let firmware take over control of h/w */ 1577 ctrl_ext = rd32(E1000_CTRL_EXT); 1578 wr32(E1000_CTRL_EXT, 1579 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1580 } 1581 1582 /** 1583 * igb_get_hw_control - get control of the h/w from f/w 1584 * @adapter: address of board private structure 1585 * 1586 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1587 * For ASF and Pass Through versions of f/w this means that 1588 * the driver is loaded. 1589 **/ 1590 static void igb_get_hw_control(struct igb_adapter *adapter) 1591 { 1592 struct e1000_hw *hw = &adapter->hw; 1593 u32 ctrl_ext; 1594 1595 /* Let firmware know the driver has taken over */ 1596 ctrl_ext = rd32(E1000_CTRL_EXT); 1597 wr32(E1000_CTRL_EXT, 1598 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1599 } 1600 1601 /** 1602 * igb_configure - configure the hardware for RX and TX 1603 * @adapter: private board structure 1604 **/ 1605 static void igb_configure(struct igb_adapter *adapter) 1606 { 1607 struct net_device *netdev = adapter->netdev; 1608 int i; 1609 1610 igb_get_hw_control(adapter); 1611 igb_set_rx_mode(netdev); 1612 1613 igb_restore_vlan(adapter); 1614 1615 igb_setup_tctl(adapter); 1616 igb_setup_mrqc(adapter); 1617 igb_setup_rctl(adapter); 1618 1619 igb_nfc_filter_restore(adapter); 1620 igb_configure_tx(adapter); 1621 igb_configure_rx(adapter); 1622 1623 igb_rx_fifo_flush_82575(&adapter->hw); 1624 1625 /* call igb_desc_unused which always leaves 1626 * at least 1 descriptor unused to make sure 1627 * next_to_use != next_to_clean 1628 */ 1629 for (i = 0; i < adapter->num_rx_queues; i++) { 1630 struct igb_ring *ring = adapter->rx_ring[i]; 1631 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1632 } 1633 } 1634 1635 /** 1636 * igb_power_up_link - Power up the phy/serdes link 1637 * @adapter: address of board private structure 1638 **/ 1639 void igb_power_up_link(struct igb_adapter *adapter) 1640 { 1641 igb_reset_phy(&adapter->hw); 1642 1643 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1644 igb_power_up_phy_copper(&adapter->hw); 1645 else 1646 igb_power_up_serdes_link_82575(&adapter->hw); 1647 1648 igb_setup_link(&adapter->hw); 1649 } 1650 1651 /** 1652 * igb_power_down_link - Power down the phy/serdes link 1653 * @adapter: address of board private structure 1654 */ 1655 static void igb_power_down_link(struct igb_adapter *adapter) 1656 { 1657 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1658 igb_power_down_phy_copper_82575(&adapter->hw); 1659 else 1660 igb_shutdown_serdes_link_82575(&adapter->hw); 1661 } 1662 1663 /** 1664 * Detect and switch function for Media Auto Sense 1665 * @adapter: address of the board private structure 1666 **/ 1667 static void igb_check_swap_media(struct igb_adapter *adapter) 1668 { 1669 struct e1000_hw *hw = &adapter->hw; 1670 u32 ctrl_ext, connsw; 1671 bool swap_now = false; 1672 1673 ctrl_ext = rd32(E1000_CTRL_EXT); 1674 connsw = rd32(E1000_CONNSW); 1675 1676 /* need to live swap if current media is copper and we have fiber/serdes 1677 * to go to. 1678 */ 1679 1680 if ((hw->phy.media_type == e1000_media_type_copper) && 1681 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 1682 swap_now = true; 1683 } else if (!(connsw & E1000_CONNSW_SERDESD)) { 1684 /* copper signal takes time to appear */ 1685 if (adapter->copper_tries < 4) { 1686 adapter->copper_tries++; 1687 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 1688 wr32(E1000_CONNSW, connsw); 1689 return; 1690 } else { 1691 adapter->copper_tries = 0; 1692 if ((connsw & E1000_CONNSW_PHYSD) && 1693 (!(connsw & E1000_CONNSW_PHY_PDN))) { 1694 swap_now = true; 1695 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 1696 wr32(E1000_CONNSW, connsw); 1697 } 1698 } 1699 } 1700 1701 if (!swap_now) 1702 return; 1703 1704 switch (hw->phy.media_type) { 1705 case e1000_media_type_copper: 1706 netdev_info(adapter->netdev, 1707 "MAS: changing media to fiber/serdes\n"); 1708 ctrl_ext |= 1709 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1710 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1711 adapter->copper_tries = 0; 1712 break; 1713 case e1000_media_type_internal_serdes: 1714 case e1000_media_type_fiber: 1715 netdev_info(adapter->netdev, 1716 "MAS: changing media to copper\n"); 1717 ctrl_ext &= 1718 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1719 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1720 break; 1721 default: 1722 /* shouldn't get here during regular operation */ 1723 netdev_err(adapter->netdev, 1724 "AMS: Invalid media type found, returning\n"); 1725 break; 1726 } 1727 wr32(E1000_CTRL_EXT, ctrl_ext); 1728 } 1729 1730 /** 1731 * igb_up - Open the interface and prepare it to handle traffic 1732 * @adapter: board private structure 1733 **/ 1734 int igb_up(struct igb_adapter *adapter) 1735 { 1736 struct e1000_hw *hw = &adapter->hw; 1737 int i; 1738 1739 /* hardware has been reset, we need to reload some things */ 1740 igb_configure(adapter); 1741 1742 clear_bit(__IGB_DOWN, &adapter->state); 1743 1744 for (i = 0; i < adapter->num_q_vectors; i++) 1745 napi_enable(&(adapter->q_vector[i]->napi)); 1746 1747 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1748 igb_configure_msix(adapter); 1749 else 1750 igb_assign_vector(adapter->q_vector[0], 0); 1751 1752 /* Clear any pending interrupts. */ 1753 rd32(E1000_ICR); 1754 igb_irq_enable(adapter); 1755 1756 /* notify VFs that reset has been completed */ 1757 if (adapter->vfs_allocated_count) { 1758 u32 reg_data = rd32(E1000_CTRL_EXT); 1759 1760 reg_data |= E1000_CTRL_EXT_PFRSTD; 1761 wr32(E1000_CTRL_EXT, reg_data); 1762 } 1763 1764 netif_tx_start_all_queues(adapter->netdev); 1765 1766 /* start the watchdog. */ 1767 hw->mac.get_link_status = 1; 1768 schedule_work(&adapter->watchdog_task); 1769 1770 if ((adapter->flags & IGB_FLAG_EEE) && 1771 (!hw->dev_spec._82575.eee_disable)) 1772 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 1773 1774 return 0; 1775 } 1776 1777 void igb_down(struct igb_adapter *adapter) 1778 { 1779 struct net_device *netdev = adapter->netdev; 1780 struct e1000_hw *hw = &adapter->hw; 1781 u32 tctl, rctl; 1782 int i; 1783 1784 /* signal that we're down so the interrupt handler does not 1785 * reschedule our watchdog timer 1786 */ 1787 set_bit(__IGB_DOWN, &adapter->state); 1788 1789 /* disable receives in the hardware */ 1790 rctl = rd32(E1000_RCTL); 1791 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 1792 /* flush and sleep below */ 1793 1794 igb_nfc_filter_exit(adapter); 1795 1796 netif_carrier_off(netdev); 1797 netif_tx_stop_all_queues(netdev); 1798 1799 /* disable transmits in the hardware */ 1800 tctl = rd32(E1000_TCTL); 1801 tctl &= ~E1000_TCTL_EN; 1802 wr32(E1000_TCTL, tctl); 1803 /* flush both disables and wait for them to finish */ 1804 wrfl(); 1805 usleep_range(10000, 11000); 1806 1807 igb_irq_disable(adapter); 1808 1809 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 1810 1811 for (i = 0; i < adapter->num_q_vectors; i++) { 1812 if (adapter->q_vector[i]) { 1813 napi_synchronize(&adapter->q_vector[i]->napi); 1814 napi_disable(&adapter->q_vector[i]->napi); 1815 } 1816 } 1817 1818 del_timer_sync(&adapter->watchdog_timer); 1819 del_timer_sync(&adapter->phy_info_timer); 1820 1821 /* record the stats before reset*/ 1822 spin_lock(&adapter->stats64_lock); 1823 igb_update_stats(adapter); 1824 spin_unlock(&adapter->stats64_lock); 1825 1826 adapter->link_speed = 0; 1827 adapter->link_duplex = 0; 1828 1829 if (!pci_channel_offline(adapter->pdev)) 1830 igb_reset(adapter); 1831 1832 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 1833 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 1834 1835 igb_clean_all_tx_rings(adapter); 1836 igb_clean_all_rx_rings(adapter); 1837 #ifdef CONFIG_IGB_DCA 1838 1839 /* since we reset the hardware DCA settings were cleared */ 1840 igb_setup_dca(adapter); 1841 #endif 1842 } 1843 1844 void igb_reinit_locked(struct igb_adapter *adapter) 1845 { 1846 WARN_ON(in_interrupt()); 1847 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 1848 usleep_range(1000, 2000); 1849 igb_down(adapter); 1850 igb_up(adapter); 1851 clear_bit(__IGB_RESETTING, &adapter->state); 1852 } 1853 1854 /** igb_enable_mas - Media Autosense re-enable after swap 1855 * 1856 * @adapter: adapter struct 1857 **/ 1858 static void igb_enable_mas(struct igb_adapter *adapter) 1859 { 1860 struct e1000_hw *hw = &adapter->hw; 1861 u32 connsw = rd32(E1000_CONNSW); 1862 1863 /* configure for SerDes media detect */ 1864 if ((hw->phy.media_type == e1000_media_type_copper) && 1865 (!(connsw & E1000_CONNSW_SERDESD))) { 1866 connsw |= E1000_CONNSW_ENRGSRC; 1867 connsw |= E1000_CONNSW_AUTOSENSE_EN; 1868 wr32(E1000_CONNSW, connsw); 1869 wrfl(); 1870 } 1871 } 1872 1873 void igb_reset(struct igb_adapter *adapter) 1874 { 1875 struct pci_dev *pdev = adapter->pdev; 1876 struct e1000_hw *hw = &adapter->hw; 1877 struct e1000_mac_info *mac = &hw->mac; 1878 struct e1000_fc_info *fc = &hw->fc; 1879 u32 pba, hwm; 1880 1881 /* Repartition Pba for greater than 9k mtu 1882 * To take effect CTRL.RST is required. 1883 */ 1884 switch (mac->type) { 1885 case e1000_i350: 1886 case e1000_i354: 1887 case e1000_82580: 1888 pba = rd32(E1000_RXPBS); 1889 pba = igb_rxpbs_adjust_82580(pba); 1890 break; 1891 case e1000_82576: 1892 pba = rd32(E1000_RXPBS); 1893 pba &= E1000_RXPBS_SIZE_MASK_82576; 1894 break; 1895 case e1000_82575: 1896 case e1000_i210: 1897 case e1000_i211: 1898 default: 1899 pba = E1000_PBA_34K; 1900 break; 1901 } 1902 1903 if (mac->type == e1000_82575) { 1904 u32 min_rx_space, min_tx_space, needed_tx_space; 1905 1906 /* write Rx PBA so that hardware can report correct Tx PBA */ 1907 wr32(E1000_PBA, pba); 1908 1909 /* To maintain wire speed transmits, the Tx FIFO should be 1910 * large enough to accommodate two full transmit packets, 1911 * rounded up to the next 1KB and expressed in KB. Likewise, 1912 * the Rx FIFO should be large enough to accommodate at least 1913 * one full receive packet and is similarly rounded up and 1914 * expressed in KB. 1915 */ 1916 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 1917 1918 /* The Tx FIFO also stores 16 bytes of information about the Tx 1919 * but don't include Ethernet FCS because hardware appends it. 1920 * We only need to round down to the nearest 512 byte block 1921 * count since the value we care about is 2 frames, not 1. 1922 */ 1923 min_tx_space = adapter->max_frame_size; 1924 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 1925 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 1926 1927 /* upper 16 bits has Tx packet buffer allocation size in KB */ 1928 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 1929 1930 /* If current Tx allocation is less than the min Tx FIFO size, 1931 * and the min Tx FIFO size is less than the current Rx FIFO 1932 * allocation, take space away from current Rx allocation. 1933 */ 1934 if (needed_tx_space < pba) { 1935 pba -= needed_tx_space; 1936 1937 /* if short on Rx space, Rx wins and must trump Tx 1938 * adjustment 1939 */ 1940 if (pba < min_rx_space) 1941 pba = min_rx_space; 1942 } 1943 1944 /* adjust PBA for jumbo frames */ 1945 wr32(E1000_PBA, pba); 1946 } 1947 1948 /* flow control settings 1949 * The high water mark must be low enough to fit one full frame 1950 * after transmitting the pause frame. As such we must have enough 1951 * space to allow for us to complete our current transmit and then 1952 * receive the frame that is in progress from the link partner. 1953 * Set it to: 1954 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 1955 */ 1956 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 1957 1958 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 1959 fc->low_water = fc->high_water - 16; 1960 fc->pause_time = 0xFFFF; 1961 fc->send_xon = 1; 1962 fc->current_mode = fc->requested_mode; 1963 1964 /* disable receive for all VFs and wait one second */ 1965 if (adapter->vfs_allocated_count) { 1966 int i; 1967 1968 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 1969 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 1970 1971 /* ping all the active vfs to let them know we are going down */ 1972 igb_ping_all_vfs(adapter); 1973 1974 /* disable transmits and receives */ 1975 wr32(E1000_VFRE, 0); 1976 wr32(E1000_VFTE, 0); 1977 } 1978 1979 /* Allow time for pending master requests to run */ 1980 hw->mac.ops.reset_hw(hw); 1981 wr32(E1000_WUC, 0); 1982 1983 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 1984 /* need to resetup here after media swap */ 1985 adapter->ei.get_invariants(hw); 1986 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 1987 } 1988 if ((mac->type == e1000_82575) && 1989 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 1990 igb_enable_mas(adapter); 1991 } 1992 if (hw->mac.ops.init_hw(hw)) 1993 dev_err(&pdev->dev, "Hardware Error\n"); 1994 1995 /* RAR registers were cleared during init_hw, clear mac table */ 1996 igb_flush_mac_table(adapter); 1997 __dev_uc_unsync(adapter->netdev, NULL); 1998 1999 /* Recover default RAR entry */ 2000 igb_set_default_mac_filter(adapter); 2001 2002 /* Flow control settings reset on hardware reset, so guarantee flow 2003 * control is off when forcing speed. 2004 */ 2005 if (!hw->mac.autoneg) 2006 igb_force_mac_fc(hw); 2007 2008 igb_init_dmac(adapter, pba); 2009 #ifdef CONFIG_IGB_HWMON 2010 /* Re-initialize the thermal sensor on i350 devices. */ 2011 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2012 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2013 /* If present, re-initialize the external thermal sensor 2014 * interface. 2015 */ 2016 if (adapter->ets) 2017 mac->ops.init_thermal_sensor_thresh(hw); 2018 } 2019 } 2020 #endif 2021 /* Re-establish EEE setting */ 2022 if (hw->phy.media_type == e1000_media_type_copper) { 2023 switch (mac->type) { 2024 case e1000_i350: 2025 case e1000_i210: 2026 case e1000_i211: 2027 igb_set_eee_i350(hw, true, true); 2028 break; 2029 case e1000_i354: 2030 igb_set_eee_i354(hw, true, true); 2031 break; 2032 default: 2033 break; 2034 } 2035 } 2036 if (!netif_running(adapter->netdev)) 2037 igb_power_down_link(adapter); 2038 2039 igb_update_mng_vlan(adapter); 2040 2041 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2042 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2043 2044 /* Re-enable PTP, where applicable. */ 2045 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2046 igb_ptp_reset(adapter); 2047 2048 igb_get_phy_info(hw); 2049 } 2050 2051 static netdev_features_t igb_fix_features(struct net_device *netdev, 2052 netdev_features_t features) 2053 { 2054 /* Since there is no support for separate Rx/Tx vlan accel 2055 * enable/disable make sure Tx flag is always in same state as Rx. 2056 */ 2057 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2058 features |= NETIF_F_HW_VLAN_CTAG_TX; 2059 else 2060 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2061 2062 return features; 2063 } 2064 2065 static int igb_set_features(struct net_device *netdev, 2066 netdev_features_t features) 2067 { 2068 netdev_features_t changed = netdev->features ^ features; 2069 struct igb_adapter *adapter = netdev_priv(netdev); 2070 2071 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2072 igb_vlan_mode(netdev, features); 2073 2074 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2075 return 0; 2076 2077 if (!(features & NETIF_F_NTUPLE)) { 2078 struct hlist_node *node2; 2079 struct igb_nfc_filter *rule; 2080 2081 spin_lock(&adapter->nfc_lock); 2082 hlist_for_each_entry_safe(rule, node2, 2083 &adapter->nfc_filter_list, nfc_node) { 2084 igb_erase_filter(adapter, rule); 2085 hlist_del(&rule->nfc_node); 2086 kfree(rule); 2087 } 2088 spin_unlock(&adapter->nfc_lock); 2089 adapter->nfc_filter_count = 0; 2090 } 2091 2092 netdev->features = features; 2093 2094 if (netif_running(netdev)) 2095 igb_reinit_locked(adapter); 2096 else 2097 igb_reset(adapter); 2098 2099 return 0; 2100 } 2101 2102 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2103 struct net_device *dev, 2104 const unsigned char *addr, u16 vid, 2105 u16 flags) 2106 { 2107 /* guarantee we can provide a unique filter for the unicast address */ 2108 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2109 struct igb_adapter *adapter = netdev_priv(dev); 2110 int vfn = adapter->vfs_allocated_count; 2111 2112 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2113 return -ENOMEM; 2114 } 2115 2116 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2117 } 2118 2119 #define IGB_MAX_MAC_HDR_LEN 127 2120 #define IGB_MAX_NETWORK_HDR_LEN 511 2121 2122 static netdev_features_t 2123 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2124 netdev_features_t features) 2125 { 2126 unsigned int network_hdr_len, mac_hdr_len; 2127 2128 /* Make certain the headers can be described by a context descriptor */ 2129 mac_hdr_len = skb_network_header(skb) - skb->data; 2130 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2131 return features & ~(NETIF_F_HW_CSUM | 2132 NETIF_F_SCTP_CRC | 2133 NETIF_F_HW_VLAN_CTAG_TX | 2134 NETIF_F_TSO | 2135 NETIF_F_TSO6); 2136 2137 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2138 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2139 return features & ~(NETIF_F_HW_CSUM | 2140 NETIF_F_SCTP_CRC | 2141 NETIF_F_TSO | 2142 NETIF_F_TSO6); 2143 2144 /* We can only support IPV4 TSO in tunnels if we can mangle the 2145 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2146 */ 2147 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2148 features &= ~NETIF_F_TSO; 2149 2150 return features; 2151 } 2152 2153 static const struct net_device_ops igb_netdev_ops = { 2154 .ndo_open = igb_open, 2155 .ndo_stop = igb_close, 2156 .ndo_start_xmit = igb_xmit_frame, 2157 .ndo_get_stats64 = igb_get_stats64, 2158 .ndo_set_rx_mode = igb_set_rx_mode, 2159 .ndo_set_mac_address = igb_set_mac, 2160 .ndo_change_mtu = igb_change_mtu, 2161 .ndo_do_ioctl = igb_ioctl, 2162 .ndo_tx_timeout = igb_tx_timeout, 2163 .ndo_validate_addr = eth_validate_addr, 2164 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2165 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2166 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2167 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2168 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 2169 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2170 .ndo_get_vf_config = igb_ndo_get_vf_config, 2171 #ifdef CONFIG_NET_POLL_CONTROLLER 2172 .ndo_poll_controller = igb_netpoll, 2173 #endif 2174 .ndo_fix_features = igb_fix_features, 2175 .ndo_set_features = igb_set_features, 2176 .ndo_fdb_add = igb_ndo_fdb_add, 2177 .ndo_features_check = igb_features_check, 2178 }; 2179 2180 /** 2181 * igb_set_fw_version - Configure version string for ethtool 2182 * @adapter: adapter struct 2183 **/ 2184 void igb_set_fw_version(struct igb_adapter *adapter) 2185 { 2186 struct e1000_hw *hw = &adapter->hw; 2187 struct e1000_fw_version fw; 2188 2189 igb_get_fw_version(hw, &fw); 2190 2191 switch (hw->mac.type) { 2192 case e1000_i210: 2193 case e1000_i211: 2194 if (!(igb_get_flash_presence_i210(hw))) { 2195 snprintf(adapter->fw_version, 2196 sizeof(adapter->fw_version), 2197 "%2d.%2d-%d", 2198 fw.invm_major, fw.invm_minor, 2199 fw.invm_img_type); 2200 break; 2201 } 2202 /* fall through */ 2203 default: 2204 /* if option is rom valid, display its version too */ 2205 if (fw.or_valid) { 2206 snprintf(adapter->fw_version, 2207 sizeof(adapter->fw_version), 2208 "%d.%d, 0x%08x, %d.%d.%d", 2209 fw.eep_major, fw.eep_minor, fw.etrack_id, 2210 fw.or_major, fw.or_build, fw.or_patch); 2211 /* no option rom */ 2212 } else if (fw.etrack_id != 0X0000) { 2213 snprintf(adapter->fw_version, 2214 sizeof(adapter->fw_version), 2215 "%d.%d, 0x%08x", 2216 fw.eep_major, fw.eep_minor, fw.etrack_id); 2217 } else { 2218 snprintf(adapter->fw_version, 2219 sizeof(adapter->fw_version), 2220 "%d.%d.%d", 2221 fw.eep_major, fw.eep_minor, fw.eep_build); 2222 } 2223 break; 2224 } 2225 } 2226 2227 /** 2228 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2229 * 2230 * @adapter: adapter struct 2231 **/ 2232 static void igb_init_mas(struct igb_adapter *adapter) 2233 { 2234 struct e1000_hw *hw = &adapter->hw; 2235 u16 eeprom_data; 2236 2237 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2238 switch (hw->bus.func) { 2239 case E1000_FUNC_0: 2240 if (eeprom_data & IGB_MAS_ENABLE_0) { 2241 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2242 netdev_info(adapter->netdev, 2243 "MAS: Enabling Media Autosense for port %d\n", 2244 hw->bus.func); 2245 } 2246 break; 2247 case E1000_FUNC_1: 2248 if (eeprom_data & IGB_MAS_ENABLE_1) { 2249 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2250 netdev_info(adapter->netdev, 2251 "MAS: Enabling Media Autosense for port %d\n", 2252 hw->bus.func); 2253 } 2254 break; 2255 case E1000_FUNC_2: 2256 if (eeprom_data & IGB_MAS_ENABLE_2) { 2257 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2258 netdev_info(adapter->netdev, 2259 "MAS: Enabling Media Autosense for port %d\n", 2260 hw->bus.func); 2261 } 2262 break; 2263 case E1000_FUNC_3: 2264 if (eeprom_data & IGB_MAS_ENABLE_3) { 2265 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2266 netdev_info(adapter->netdev, 2267 "MAS: Enabling Media Autosense for port %d\n", 2268 hw->bus.func); 2269 } 2270 break; 2271 default: 2272 /* Shouldn't get here */ 2273 netdev_err(adapter->netdev, 2274 "MAS: Invalid port configuration, returning\n"); 2275 break; 2276 } 2277 } 2278 2279 /** 2280 * igb_init_i2c - Init I2C interface 2281 * @adapter: pointer to adapter structure 2282 **/ 2283 static s32 igb_init_i2c(struct igb_adapter *adapter) 2284 { 2285 s32 status = 0; 2286 2287 /* I2C interface supported on i350 devices */ 2288 if (adapter->hw.mac.type != e1000_i350) 2289 return 0; 2290 2291 /* Initialize the i2c bus which is controlled by the registers. 2292 * This bus will use the i2c_algo_bit structue that implements 2293 * the protocol through toggling of the 4 bits in the register. 2294 */ 2295 adapter->i2c_adap.owner = THIS_MODULE; 2296 adapter->i2c_algo = igb_i2c_algo; 2297 adapter->i2c_algo.data = adapter; 2298 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 2299 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 2300 strlcpy(adapter->i2c_adap.name, "igb BB", 2301 sizeof(adapter->i2c_adap.name)); 2302 status = i2c_bit_add_bus(&adapter->i2c_adap); 2303 return status; 2304 } 2305 2306 /** 2307 * igb_probe - Device Initialization Routine 2308 * @pdev: PCI device information struct 2309 * @ent: entry in igb_pci_tbl 2310 * 2311 * Returns 0 on success, negative on failure 2312 * 2313 * igb_probe initializes an adapter identified by a pci_dev structure. 2314 * The OS initialization, configuring of the adapter private structure, 2315 * and a hardware reset occur. 2316 **/ 2317 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2318 { 2319 struct net_device *netdev; 2320 struct igb_adapter *adapter; 2321 struct e1000_hw *hw; 2322 u16 eeprom_data = 0; 2323 s32 ret_val; 2324 static int global_quad_port_a; /* global quad port a indication */ 2325 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 2326 int err, pci_using_dac; 2327 u8 part_str[E1000_PBANUM_LENGTH]; 2328 2329 /* Catch broken hardware that put the wrong VF device ID in 2330 * the PCIe SR-IOV capability. 2331 */ 2332 if (pdev->is_virtfn) { 2333 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 2334 pci_name(pdev), pdev->vendor, pdev->device); 2335 return -EINVAL; 2336 } 2337 2338 err = pci_enable_device_mem(pdev); 2339 if (err) 2340 return err; 2341 2342 pci_using_dac = 0; 2343 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2344 if (!err) { 2345 pci_using_dac = 1; 2346 } else { 2347 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2348 if (err) { 2349 dev_err(&pdev->dev, 2350 "No usable DMA configuration, aborting\n"); 2351 goto err_dma; 2352 } 2353 } 2354 2355 err = pci_request_mem_regions(pdev, igb_driver_name); 2356 if (err) 2357 goto err_pci_reg; 2358 2359 pci_enable_pcie_error_reporting(pdev); 2360 2361 pci_set_master(pdev); 2362 pci_save_state(pdev); 2363 2364 err = -ENOMEM; 2365 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 2366 IGB_MAX_TX_QUEUES); 2367 if (!netdev) 2368 goto err_alloc_etherdev; 2369 2370 SET_NETDEV_DEV(netdev, &pdev->dev); 2371 2372 pci_set_drvdata(pdev, netdev); 2373 adapter = netdev_priv(netdev); 2374 adapter->netdev = netdev; 2375 adapter->pdev = pdev; 2376 hw = &adapter->hw; 2377 hw->back = adapter; 2378 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2379 2380 err = -EIO; 2381 adapter->io_addr = pci_iomap(pdev, 0, 0); 2382 if (!adapter->io_addr) 2383 goto err_ioremap; 2384 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 2385 hw->hw_addr = adapter->io_addr; 2386 2387 netdev->netdev_ops = &igb_netdev_ops; 2388 igb_set_ethtool_ops(netdev); 2389 netdev->watchdog_timeo = 5 * HZ; 2390 2391 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 2392 2393 netdev->mem_start = pci_resource_start(pdev, 0); 2394 netdev->mem_end = pci_resource_end(pdev, 0); 2395 2396 /* PCI config space info */ 2397 hw->vendor_id = pdev->vendor; 2398 hw->device_id = pdev->device; 2399 hw->revision_id = pdev->revision; 2400 hw->subsystem_vendor_id = pdev->subsystem_vendor; 2401 hw->subsystem_device_id = pdev->subsystem_device; 2402 2403 /* Copy the default MAC, PHY and NVM function pointers */ 2404 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 2405 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 2406 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 2407 /* Initialize skew-specific constants */ 2408 err = ei->get_invariants(hw); 2409 if (err) 2410 goto err_sw_init; 2411 2412 /* setup the private structure */ 2413 err = igb_sw_init(adapter); 2414 if (err) 2415 goto err_sw_init; 2416 2417 igb_get_bus_info_pcie(hw); 2418 2419 hw->phy.autoneg_wait_to_complete = false; 2420 2421 /* Copper options */ 2422 if (hw->phy.media_type == e1000_media_type_copper) { 2423 hw->phy.mdix = AUTO_ALL_MODES; 2424 hw->phy.disable_polarity_correction = false; 2425 hw->phy.ms_type = e1000_ms_hw_default; 2426 } 2427 2428 if (igb_check_reset_block(hw)) 2429 dev_info(&pdev->dev, 2430 "PHY reset is blocked due to SOL/IDER session.\n"); 2431 2432 /* features is initialized to 0 in allocation, it might have bits 2433 * set by igb_sw_init so we should use an or instead of an 2434 * assignment. 2435 */ 2436 netdev->features |= NETIF_F_SG | 2437 NETIF_F_TSO | 2438 NETIF_F_TSO6 | 2439 NETIF_F_RXHASH | 2440 NETIF_F_RXCSUM | 2441 NETIF_F_HW_CSUM; 2442 2443 if (hw->mac.type >= e1000_82576) 2444 netdev->features |= NETIF_F_SCTP_CRC; 2445 2446 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 2447 NETIF_F_GSO_GRE_CSUM | \ 2448 NETIF_F_GSO_IPXIP4 | \ 2449 NETIF_F_GSO_IPXIP6 | \ 2450 NETIF_F_GSO_UDP_TUNNEL | \ 2451 NETIF_F_GSO_UDP_TUNNEL_CSUM) 2452 2453 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 2454 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 2455 2456 /* copy netdev features into list of user selectable features */ 2457 netdev->hw_features |= netdev->features | 2458 NETIF_F_HW_VLAN_CTAG_RX | 2459 NETIF_F_HW_VLAN_CTAG_TX | 2460 NETIF_F_RXALL; 2461 2462 if (hw->mac.type >= e1000_i350) 2463 netdev->hw_features |= NETIF_F_NTUPLE; 2464 2465 if (pci_using_dac) 2466 netdev->features |= NETIF_F_HIGHDMA; 2467 2468 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 2469 netdev->mpls_features |= NETIF_F_HW_CSUM; 2470 netdev->hw_enc_features |= netdev->vlan_features; 2471 2472 /* set this bit last since it cannot be part of vlan_features */ 2473 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 2474 NETIF_F_HW_VLAN_CTAG_RX | 2475 NETIF_F_HW_VLAN_CTAG_TX; 2476 2477 netdev->priv_flags |= IFF_SUPP_NOFCS; 2478 2479 netdev->priv_flags |= IFF_UNICAST_FLT; 2480 2481 /* MTU range: 68 - 9216 */ 2482 netdev->min_mtu = ETH_MIN_MTU; 2483 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 2484 2485 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 2486 2487 /* before reading the NVM, reset the controller to put the device in a 2488 * known good starting state 2489 */ 2490 hw->mac.ops.reset_hw(hw); 2491 2492 /* make sure the NVM is good , i211/i210 parts can have special NVM 2493 * that doesn't contain a checksum 2494 */ 2495 switch (hw->mac.type) { 2496 case e1000_i210: 2497 case e1000_i211: 2498 if (igb_get_flash_presence_i210(hw)) { 2499 if (hw->nvm.ops.validate(hw) < 0) { 2500 dev_err(&pdev->dev, 2501 "The NVM Checksum Is Not Valid\n"); 2502 err = -EIO; 2503 goto err_eeprom; 2504 } 2505 } 2506 break; 2507 default: 2508 if (hw->nvm.ops.validate(hw) < 0) { 2509 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2510 err = -EIO; 2511 goto err_eeprom; 2512 } 2513 break; 2514 } 2515 2516 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 2517 /* copy the MAC address out of the NVM */ 2518 if (hw->mac.ops.read_mac_addr(hw)) 2519 dev_err(&pdev->dev, "NVM Read Error\n"); 2520 } 2521 2522 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2523 2524 if (!is_valid_ether_addr(netdev->dev_addr)) { 2525 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2526 err = -EIO; 2527 goto err_eeprom; 2528 } 2529 2530 igb_set_default_mac_filter(adapter); 2531 2532 /* get firmware version for ethtool -i */ 2533 igb_set_fw_version(adapter); 2534 2535 /* configure RXPBSIZE and TXPBSIZE */ 2536 if (hw->mac.type == e1000_i210) { 2537 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 2538 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 2539 } 2540 2541 setup_timer(&adapter->watchdog_timer, igb_watchdog, 2542 (unsigned long) adapter); 2543 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, 2544 (unsigned long) adapter); 2545 2546 INIT_WORK(&adapter->reset_task, igb_reset_task); 2547 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2548 2549 /* Initialize link properties that are user-changeable */ 2550 adapter->fc_autoneg = true; 2551 hw->mac.autoneg = true; 2552 hw->phy.autoneg_advertised = 0x2f; 2553 2554 hw->fc.requested_mode = e1000_fc_default; 2555 hw->fc.current_mode = e1000_fc_default; 2556 2557 igb_validate_mdi_setting(hw); 2558 2559 /* By default, support wake on port A */ 2560 if (hw->bus.func == 0) 2561 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2562 2563 /* Check the NVM for wake support on non-port A ports */ 2564 if (hw->mac.type >= e1000_82580) 2565 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2566 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2567 &eeprom_data); 2568 else if (hw->bus.func == 1) 2569 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2570 2571 if (eeprom_data & IGB_EEPROM_APME) 2572 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2573 2574 /* now that we have the eeprom settings, apply the special cases where 2575 * the eeprom may be wrong or the board simply won't support wake on 2576 * lan on a particular port 2577 */ 2578 switch (pdev->device) { 2579 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2580 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2581 break; 2582 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2583 case E1000_DEV_ID_82576_FIBER: 2584 case E1000_DEV_ID_82576_SERDES: 2585 /* Wake events only supported on port A for dual fiber 2586 * regardless of eeprom setting 2587 */ 2588 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2589 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2590 break; 2591 case E1000_DEV_ID_82576_QUAD_COPPER: 2592 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2593 /* if quad port adapter, disable WoL on all but port A */ 2594 if (global_quad_port_a != 0) 2595 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2596 else 2597 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2598 /* Reset for multiple quad port adapters */ 2599 if (++global_quad_port_a == 4) 2600 global_quad_port_a = 0; 2601 break; 2602 default: 2603 /* If the device can't wake, don't set software support */ 2604 if (!device_can_wakeup(&adapter->pdev->dev)) 2605 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2606 } 2607 2608 /* initialize the wol settings based on the eeprom settings */ 2609 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 2610 adapter->wol |= E1000_WUFC_MAG; 2611 2612 /* Some vendors want WoL disabled by default, but still supported */ 2613 if ((hw->mac.type == e1000_i350) && 2614 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 2615 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2616 adapter->wol = 0; 2617 } 2618 2619 /* Some vendors want the ability to Use the EEPROM setting as 2620 * enable/disable only, and not for capability 2621 */ 2622 if (((hw->mac.type == e1000_i350) || 2623 (hw->mac.type == e1000_i354)) && 2624 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 2625 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2626 adapter->wol = 0; 2627 } 2628 if (hw->mac.type == e1000_i350) { 2629 if (((pdev->subsystem_device == 0x5001) || 2630 (pdev->subsystem_device == 0x5002)) && 2631 (hw->bus.func == 0)) { 2632 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2633 adapter->wol = 0; 2634 } 2635 if (pdev->subsystem_device == 0x1F52) 2636 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2637 } 2638 2639 device_set_wakeup_enable(&adapter->pdev->dev, 2640 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 2641 2642 /* reset the hardware with the new settings */ 2643 igb_reset(adapter); 2644 2645 /* Init the I2C interface */ 2646 err = igb_init_i2c(adapter); 2647 if (err) { 2648 dev_err(&pdev->dev, "failed to init i2c interface\n"); 2649 goto err_eeprom; 2650 } 2651 2652 /* let the f/w know that the h/w is now under the control of the 2653 * driver. 2654 */ 2655 igb_get_hw_control(adapter); 2656 2657 strcpy(netdev->name, "eth%d"); 2658 err = register_netdev(netdev); 2659 if (err) 2660 goto err_register; 2661 2662 /* carrier off reporting is important to ethtool even BEFORE open */ 2663 netif_carrier_off(netdev); 2664 2665 #ifdef CONFIG_IGB_DCA 2666 if (dca_add_requester(&pdev->dev) == 0) { 2667 adapter->flags |= IGB_FLAG_DCA_ENABLED; 2668 dev_info(&pdev->dev, "DCA enabled\n"); 2669 igb_setup_dca(adapter); 2670 } 2671 2672 #endif 2673 #ifdef CONFIG_IGB_HWMON 2674 /* Initialize the thermal sensor on i350 devices. */ 2675 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 2676 u16 ets_word; 2677 2678 /* Read the NVM to determine if this i350 device supports an 2679 * external thermal sensor. 2680 */ 2681 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 2682 if (ets_word != 0x0000 && ets_word != 0xFFFF) 2683 adapter->ets = true; 2684 else 2685 adapter->ets = false; 2686 if (igb_sysfs_init(adapter)) 2687 dev_err(&pdev->dev, 2688 "failed to allocate sysfs resources\n"); 2689 } else { 2690 adapter->ets = false; 2691 } 2692 #endif 2693 /* Check if Media Autosense is enabled */ 2694 adapter->ei = *ei; 2695 if (hw->dev_spec._82575.mas_capable) 2696 igb_init_mas(adapter); 2697 2698 /* do hw tstamp init after resetting */ 2699 igb_ptp_init(adapter); 2700 2701 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 2702 /* print bus type/speed/width info, not applicable to i354 */ 2703 if (hw->mac.type != e1000_i354) { 2704 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 2705 netdev->name, 2706 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 2707 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 2708 "unknown"), 2709 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 2710 "Width x4" : 2711 (hw->bus.width == e1000_bus_width_pcie_x2) ? 2712 "Width x2" : 2713 (hw->bus.width == e1000_bus_width_pcie_x1) ? 2714 "Width x1" : "unknown"), netdev->dev_addr); 2715 } 2716 2717 if ((hw->mac.type >= e1000_i210 || 2718 igb_get_flash_presence_i210(hw))) { 2719 ret_val = igb_read_part_string(hw, part_str, 2720 E1000_PBANUM_LENGTH); 2721 } else { 2722 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 2723 } 2724 2725 if (ret_val) 2726 strcpy(part_str, "Unknown"); 2727 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 2728 dev_info(&pdev->dev, 2729 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 2730 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 2731 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2732 adapter->num_rx_queues, adapter->num_tx_queues); 2733 if (hw->phy.media_type == e1000_media_type_copper) { 2734 switch (hw->mac.type) { 2735 case e1000_i350: 2736 case e1000_i210: 2737 case e1000_i211: 2738 /* Enable EEE for internal copper PHY devices */ 2739 err = igb_set_eee_i350(hw, true, true); 2740 if ((!err) && 2741 (!hw->dev_spec._82575.eee_disable)) { 2742 adapter->eee_advert = 2743 MDIO_EEE_100TX | MDIO_EEE_1000T; 2744 adapter->flags |= IGB_FLAG_EEE; 2745 } 2746 break; 2747 case e1000_i354: 2748 if ((rd32(E1000_CTRL_EXT) & 2749 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 2750 err = igb_set_eee_i354(hw, true, true); 2751 if ((!err) && 2752 (!hw->dev_spec._82575.eee_disable)) { 2753 adapter->eee_advert = 2754 MDIO_EEE_100TX | MDIO_EEE_1000T; 2755 adapter->flags |= IGB_FLAG_EEE; 2756 } 2757 } 2758 break; 2759 default: 2760 break; 2761 } 2762 } 2763 pm_runtime_put_noidle(&pdev->dev); 2764 return 0; 2765 2766 err_register: 2767 igb_release_hw_control(adapter); 2768 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 2769 err_eeprom: 2770 if (!igb_check_reset_block(hw)) 2771 igb_reset_phy(hw); 2772 2773 if (hw->flash_address) 2774 iounmap(hw->flash_address); 2775 err_sw_init: 2776 kfree(adapter->mac_table); 2777 kfree(adapter->shadow_vfta); 2778 igb_clear_interrupt_scheme(adapter); 2779 #ifdef CONFIG_PCI_IOV 2780 igb_disable_sriov(pdev); 2781 #endif 2782 pci_iounmap(pdev, adapter->io_addr); 2783 err_ioremap: 2784 free_netdev(netdev); 2785 err_alloc_etherdev: 2786 pci_release_mem_regions(pdev); 2787 err_pci_reg: 2788 err_dma: 2789 pci_disable_device(pdev); 2790 return err; 2791 } 2792 2793 #ifdef CONFIG_PCI_IOV 2794 static int igb_disable_sriov(struct pci_dev *pdev) 2795 { 2796 struct net_device *netdev = pci_get_drvdata(pdev); 2797 struct igb_adapter *adapter = netdev_priv(netdev); 2798 struct e1000_hw *hw = &adapter->hw; 2799 2800 /* reclaim resources allocated to VFs */ 2801 if (adapter->vf_data) { 2802 /* disable iov and allow time for transactions to clear */ 2803 if (pci_vfs_assigned(pdev)) { 2804 dev_warn(&pdev->dev, 2805 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 2806 return -EPERM; 2807 } else { 2808 pci_disable_sriov(pdev); 2809 msleep(500); 2810 } 2811 2812 kfree(adapter->vf_mac_list); 2813 adapter->vf_mac_list = NULL; 2814 kfree(adapter->vf_data); 2815 adapter->vf_data = NULL; 2816 adapter->vfs_allocated_count = 0; 2817 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2818 wrfl(); 2819 msleep(100); 2820 dev_info(&pdev->dev, "IOV Disabled\n"); 2821 2822 /* Re-enable DMA Coalescing flag since IOV is turned off */ 2823 adapter->flags |= IGB_FLAG_DMAC; 2824 } 2825 2826 return 0; 2827 } 2828 2829 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 2830 { 2831 struct net_device *netdev = pci_get_drvdata(pdev); 2832 struct igb_adapter *adapter = netdev_priv(netdev); 2833 int old_vfs = pci_num_vf(pdev); 2834 struct vf_mac_filter *mac_list; 2835 int err = 0; 2836 int num_vf_mac_filters, i; 2837 2838 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 2839 err = -EPERM; 2840 goto out; 2841 } 2842 if (!num_vfs) 2843 goto out; 2844 2845 if (old_vfs) { 2846 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 2847 old_vfs, max_vfs); 2848 adapter->vfs_allocated_count = old_vfs; 2849 } else 2850 adapter->vfs_allocated_count = num_vfs; 2851 2852 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2853 sizeof(struct vf_data_storage), GFP_KERNEL); 2854 2855 /* if allocation failed then we do not support SR-IOV */ 2856 if (!adapter->vf_data) { 2857 adapter->vfs_allocated_count = 0; 2858 dev_err(&pdev->dev, 2859 "Unable to allocate memory for VF Data Storage\n"); 2860 err = -ENOMEM; 2861 goto out; 2862 } 2863 2864 /* Due to the limited number of RAR entries calculate potential 2865 * number of MAC filters available for the VFs. Reserve entries 2866 * for PF default MAC, PF MAC filters and at least one RAR entry 2867 * for each VF for VF MAC. 2868 */ 2869 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 2870 (1 + IGB_PF_MAC_FILTERS_RESERVED + 2871 adapter->vfs_allocated_count); 2872 2873 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 2874 sizeof(struct vf_mac_filter), 2875 GFP_KERNEL); 2876 2877 mac_list = adapter->vf_mac_list; 2878 INIT_LIST_HEAD(&adapter->vf_macs.l); 2879 2880 if (adapter->vf_mac_list) { 2881 /* Initialize list of VF MAC filters */ 2882 for (i = 0; i < num_vf_mac_filters; i++) { 2883 mac_list->vf = -1; 2884 mac_list->free = true; 2885 list_add(&mac_list->l, &adapter->vf_macs.l); 2886 mac_list++; 2887 } 2888 } else { 2889 /* If we could not allocate memory for the VF MAC filters 2890 * we can continue without this feature but warn user. 2891 */ 2892 dev_err(&pdev->dev, 2893 "Unable to allocate memory for VF MAC filter list\n"); 2894 } 2895 2896 /* only call pci_enable_sriov() if no VFs are allocated already */ 2897 if (!old_vfs) { 2898 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 2899 if (err) 2900 goto err_out; 2901 } 2902 dev_info(&pdev->dev, "%d VFs allocated\n", 2903 adapter->vfs_allocated_count); 2904 for (i = 0; i < adapter->vfs_allocated_count; i++) 2905 igb_vf_configure(adapter, i); 2906 2907 /* DMA Coalescing is not supported in IOV mode. */ 2908 adapter->flags &= ~IGB_FLAG_DMAC; 2909 goto out; 2910 2911 err_out: 2912 kfree(adapter->vf_mac_list); 2913 adapter->vf_mac_list = NULL; 2914 kfree(adapter->vf_data); 2915 adapter->vf_data = NULL; 2916 adapter->vfs_allocated_count = 0; 2917 out: 2918 return err; 2919 } 2920 2921 #endif 2922 /** 2923 * igb_remove_i2c - Cleanup I2C interface 2924 * @adapter: pointer to adapter structure 2925 **/ 2926 static void igb_remove_i2c(struct igb_adapter *adapter) 2927 { 2928 /* free the adapter bus structure */ 2929 i2c_del_adapter(&adapter->i2c_adap); 2930 } 2931 2932 /** 2933 * igb_remove - Device Removal Routine 2934 * @pdev: PCI device information struct 2935 * 2936 * igb_remove is called by the PCI subsystem to alert the driver 2937 * that it should release a PCI device. The could be caused by a 2938 * Hot-Plug event, or because the driver is going to be removed from 2939 * memory. 2940 **/ 2941 static void igb_remove(struct pci_dev *pdev) 2942 { 2943 struct net_device *netdev = pci_get_drvdata(pdev); 2944 struct igb_adapter *adapter = netdev_priv(netdev); 2945 struct e1000_hw *hw = &adapter->hw; 2946 2947 pm_runtime_get_noresume(&pdev->dev); 2948 #ifdef CONFIG_IGB_HWMON 2949 igb_sysfs_exit(adapter); 2950 #endif 2951 igb_remove_i2c(adapter); 2952 igb_ptp_stop(adapter); 2953 /* The watchdog timer may be rescheduled, so explicitly 2954 * disable watchdog from being rescheduled. 2955 */ 2956 set_bit(__IGB_DOWN, &adapter->state); 2957 del_timer_sync(&adapter->watchdog_timer); 2958 del_timer_sync(&adapter->phy_info_timer); 2959 2960 cancel_work_sync(&adapter->reset_task); 2961 cancel_work_sync(&adapter->watchdog_task); 2962 2963 #ifdef CONFIG_IGB_DCA 2964 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 2965 dev_info(&pdev->dev, "DCA disabled\n"); 2966 dca_remove_requester(&pdev->dev); 2967 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 2968 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 2969 } 2970 #endif 2971 2972 /* Release control of h/w to f/w. If f/w is AMT enabled, this 2973 * would have already happened in close and is redundant. 2974 */ 2975 igb_release_hw_control(adapter); 2976 2977 #ifdef CONFIG_PCI_IOV 2978 igb_disable_sriov(pdev); 2979 #endif 2980 2981 unregister_netdev(netdev); 2982 2983 igb_clear_interrupt_scheme(adapter); 2984 2985 pci_iounmap(pdev, adapter->io_addr); 2986 if (hw->flash_address) 2987 iounmap(hw->flash_address); 2988 pci_release_mem_regions(pdev); 2989 2990 kfree(adapter->mac_table); 2991 kfree(adapter->shadow_vfta); 2992 free_netdev(netdev); 2993 2994 pci_disable_pcie_error_reporting(pdev); 2995 2996 pci_disable_device(pdev); 2997 } 2998 2999 /** 3000 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3001 * @adapter: board private structure to initialize 3002 * 3003 * This function initializes the vf specific data storage and then attempts to 3004 * allocate the VFs. The reason for ordering it this way is because it is much 3005 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3006 * the memory for the VFs. 3007 **/ 3008 static void igb_probe_vfs(struct igb_adapter *adapter) 3009 { 3010 #ifdef CONFIG_PCI_IOV 3011 struct pci_dev *pdev = adapter->pdev; 3012 struct e1000_hw *hw = &adapter->hw; 3013 3014 /* Virtualization features not supported on i210 family. */ 3015 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 3016 return; 3017 3018 /* Of the below we really only want the effect of getting 3019 * IGB_FLAG_HAS_MSIX set (if available), without which 3020 * igb_enable_sriov() has no effect. 3021 */ 3022 igb_set_interrupt_capability(adapter, true); 3023 igb_reset_interrupt_capability(adapter); 3024 3025 pci_sriov_set_totalvfs(pdev, 7); 3026 igb_enable_sriov(pdev, max_vfs); 3027 3028 #endif /* CONFIG_PCI_IOV */ 3029 } 3030 3031 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3032 { 3033 struct e1000_hw *hw = &adapter->hw; 3034 u32 max_rss_queues; 3035 3036 /* Determine the maximum number of RSS queues supported. */ 3037 switch (hw->mac.type) { 3038 case e1000_i211: 3039 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3040 break; 3041 case e1000_82575: 3042 case e1000_i210: 3043 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3044 break; 3045 case e1000_i350: 3046 /* I350 cannot do RSS and SR-IOV at the same time */ 3047 if (!!adapter->vfs_allocated_count) { 3048 max_rss_queues = 1; 3049 break; 3050 } 3051 /* fall through */ 3052 case e1000_82576: 3053 if (!!adapter->vfs_allocated_count) { 3054 max_rss_queues = 2; 3055 break; 3056 } 3057 /* fall through */ 3058 case e1000_82580: 3059 case e1000_i354: 3060 default: 3061 max_rss_queues = IGB_MAX_RX_QUEUES; 3062 break; 3063 } 3064 3065 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3066 3067 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3068 } 3069 3070 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3071 const u32 max_rss_queues) 3072 { 3073 struct e1000_hw *hw = &adapter->hw; 3074 3075 /* Determine if we need to pair queues. */ 3076 switch (hw->mac.type) { 3077 case e1000_82575: 3078 case e1000_i211: 3079 /* Device supports enough interrupts without queue pairing. */ 3080 break; 3081 case e1000_82576: 3082 case e1000_82580: 3083 case e1000_i350: 3084 case e1000_i354: 3085 case e1000_i210: 3086 default: 3087 /* If rss_queues > half of max_rss_queues, pair the queues in 3088 * order to conserve interrupts due to limited supply. 3089 */ 3090 if (adapter->rss_queues > (max_rss_queues / 2)) 3091 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3092 else 3093 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 3094 break; 3095 } 3096 } 3097 3098 /** 3099 * igb_sw_init - Initialize general software structures (struct igb_adapter) 3100 * @adapter: board private structure to initialize 3101 * 3102 * igb_sw_init initializes the Adapter private data structure. 3103 * Fields are initialized based on PCI device information and 3104 * OS network device settings (MTU size). 3105 **/ 3106 static int igb_sw_init(struct igb_adapter *adapter) 3107 { 3108 struct e1000_hw *hw = &adapter->hw; 3109 struct net_device *netdev = adapter->netdev; 3110 struct pci_dev *pdev = adapter->pdev; 3111 3112 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 3113 3114 /* set default ring sizes */ 3115 adapter->tx_ring_count = IGB_DEFAULT_TXD; 3116 adapter->rx_ring_count = IGB_DEFAULT_RXD; 3117 3118 /* set default ITR values */ 3119 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 3120 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 3121 3122 /* set default work limits */ 3123 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 3124 3125 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 3126 VLAN_HLEN; 3127 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 3128 3129 spin_lock_init(&adapter->nfc_lock); 3130 spin_lock_init(&adapter->stats64_lock); 3131 #ifdef CONFIG_PCI_IOV 3132 switch (hw->mac.type) { 3133 case e1000_82576: 3134 case e1000_i350: 3135 if (max_vfs > 7) { 3136 dev_warn(&pdev->dev, 3137 "Maximum of 7 VFs per PF, using max\n"); 3138 max_vfs = adapter->vfs_allocated_count = 7; 3139 } else 3140 adapter->vfs_allocated_count = max_vfs; 3141 if (adapter->vfs_allocated_count) 3142 dev_warn(&pdev->dev, 3143 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 3144 break; 3145 default: 3146 break; 3147 } 3148 #endif /* CONFIG_PCI_IOV */ 3149 3150 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 3151 adapter->flags |= IGB_FLAG_HAS_MSIX; 3152 3153 adapter->mac_table = kzalloc(sizeof(struct igb_mac_addr) * 3154 hw->mac.rar_entry_count, GFP_ATOMIC); 3155 if (!adapter->mac_table) 3156 return -ENOMEM; 3157 3158 igb_probe_vfs(adapter); 3159 3160 igb_init_queue_configuration(adapter); 3161 3162 /* Setup and initialize a copy of the hw vlan table array */ 3163 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 3164 GFP_ATOMIC); 3165 if (!adapter->shadow_vfta) 3166 return -ENOMEM; 3167 3168 /* This call may decrease the number of queues */ 3169 if (igb_init_interrupt_scheme(adapter, true)) { 3170 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3171 return -ENOMEM; 3172 } 3173 3174 /* Explicitly disable IRQ since the NIC can be in any state. */ 3175 igb_irq_disable(adapter); 3176 3177 if (hw->mac.type >= e1000_i350) 3178 adapter->flags &= ~IGB_FLAG_DMAC; 3179 3180 set_bit(__IGB_DOWN, &adapter->state); 3181 return 0; 3182 } 3183 3184 /** 3185 * igb_open - Called when a network interface is made active 3186 * @netdev: network interface device structure 3187 * 3188 * Returns 0 on success, negative value on failure 3189 * 3190 * The open entry point is called when a network interface is made 3191 * active by the system (IFF_UP). At this point all resources needed 3192 * for transmit and receive operations are allocated, the interrupt 3193 * handler is registered with the OS, the watchdog timer is started, 3194 * and the stack is notified that the interface is ready. 3195 **/ 3196 static int __igb_open(struct net_device *netdev, bool resuming) 3197 { 3198 struct igb_adapter *adapter = netdev_priv(netdev); 3199 struct e1000_hw *hw = &adapter->hw; 3200 struct pci_dev *pdev = adapter->pdev; 3201 int err; 3202 int i; 3203 3204 /* disallow open during test */ 3205 if (test_bit(__IGB_TESTING, &adapter->state)) { 3206 WARN_ON(resuming); 3207 return -EBUSY; 3208 } 3209 3210 if (!resuming) 3211 pm_runtime_get_sync(&pdev->dev); 3212 3213 netif_carrier_off(netdev); 3214 3215 /* allocate transmit descriptors */ 3216 err = igb_setup_all_tx_resources(adapter); 3217 if (err) 3218 goto err_setup_tx; 3219 3220 /* allocate receive descriptors */ 3221 err = igb_setup_all_rx_resources(adapter); 3222 if (err) 3223 goto err_setup_rx; 3224 3225 igb_power_up_link(adapter); 3226 3227 /* before we allocate an interrupt, we must be ready to handle it. 3228 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3229 * as soon as we call pci_request_irq, so we have to setup our 3230 * clean_rx handler before we do so. 3231 */ 3232 igb_configure(adapter); 3233 3234 err = igb_request_irq(adapter); 3235 if (err) 3236 goto err_req_irq; 3237 3238 /* Notify the stack of the actual queue counts. */ 3239 err = netif_set_real_num_tx_queues(adapter->netdev, 3240 adapter->num_tx_queues); 3241 if (err) 3242 goto err_set_queues; 3243 3244 err = netif_set_real_num_rx_queues(adapter->netdev, 3245 adapter->num_rx_queues); 3246 if (err) 3247 goto err_set_queues; 3248 3249 /* From here on the code is the same as igb_up() */ 3250 clear_bit(__IGB_DOWN, &adapter->state); 3251 3252 for (i = 0; i < adapter->num_q_vectors; i++) 3253 napi_enable(&(adapter->q_vector[i]->napi)); 3254 3255 /* Clear any pending interrupts. */ 3256 rd32(E1000_ICR); 3257 3258 igb_irq_enable(adapter); 3259 3260 /* notify VFs that reset has been completed */ 3261 if (adapter->vfs_allocated_count) { 3262 u32 reg_data = rd32(E1000_CTRL_EXT); 3263 3264 reg_data |= E1000_CTRL_EXT_PFRSTD; 3265 wr32(E1000_CTRL_EXT, reg_data); 3266 } 3267 3268 netif_tx_start_all_queues(netdev); 3269 3270 if (!resuming) 3271 pm_runtime_put(&pdev->dev); 3272 3273 /* start the watchdog. */ 3274 hw->mac.get_link_status = 1; 3275 schedule_work(&adapter->watchdog_task); 3276 3277 return 0; 3278 3279 err_set_queues: 3280 igb_free_irq(adapter); 3281 err_req_irq: 3282 igb_release_hw_control(adapter); 3283 igb_power_down_link(adapter); 3284 igb_free_all_rx_resources(adapter); 3285 err_setup_rx: 3286 igb_free_all_tx_resources(adapter); 3287 err_setup_tx: 3288 igb_reset(adapter); 3289 if (!resuming) 3290 pm_runtime_put(&pdev->dev); 3291 3292 return err; 3293 } 3294 3295 int igb_open(struct net_device *netdev) 3296 { 3297 return __igb_open(netdev, false); 3298 } 3299 3300 /** 3301 * igb_close - Disables a network interface 3302 * @netdev: network interface device structure 3303 * 3304 * Returns 0, this is not allowed to fail 3305 * 3306 * The close entry point is called when an interface is de-activated 3307 * by the OS. The hardware is still under the driver's control, but 3308 * needs to be disabled. A global MAC reset is issued to stop the 3309 * hardware, and all transmit and receive resources are freed. 3310 **/ 3311 static int __igb_close(struct net_device *netdev, bool suspending) 3312 { 3313 struct igb_adapter *adapter = netdev_priv(netdev); 3314 struct pci_dev *pdev = adapter->pdev; 3315 3316 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 3317 3318 if (!suspending) 3319 pm_runtime_get_sync(&pdev->dev); 3320 3321 igb_down(adapter); 3322 igb_free_irq(adapter); 3323 3324 igb_free_all_tx_resources(adapter); 3325 igb_free_all_rx_resources(adapter); 3326 3327 if (!suspending) 3328 pm_runtime_put_sync(&pdev->dev); 3329 return 0; 3330 } 3331 3332 int igb_close(struct net_device *netdev) 3333 { 3334 if (netif_device_present(netdev)) 3335 return __igb_close(netdev, false); 3336 return 0; 3337 } 3338 3339 /** 3340 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 3341 * @tx_ring: tx descriptor ring (for a specific queue) to setup 3342 * 3343 * Return 0 on success, negative on failure 3344 **/ 3345 int igb_setup_tx_resources(struct igb_ring *tx_ring) 3346 { 3347 struct device *dev = tx_ring->dev; 3348 int size; 3349 3350 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3351 3352 tx_ring->tx_buffer_info = vmalloc(size); 3353 if (!tx_ring->tx_buffer_info) 3354 goto err; 3355 3356 /* round up to nearest 4K */ 3357 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 3358 tx_ring->size = ALIGN(tx_ring->size, 4096); 3359 3360 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 3361 &tx_ring->dma, GFP_KERNEL); 3362 if (!tx_ring->desc) 3363 goto err; 3364 3365 tx_ring->next_to_use = 0; 3366 tx_ring->next_to_clean = 0; 3367 3368 return 0; 3369 3370 err: 3371 vfree(tx_ring->tx_buffer_info); 3372 tx_ring->tx_buffer_info = NULL; 3373 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 3374 return -ENOMEM; 3375 } 3376 3377 /** 3378 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 3379 * (Descriptors) for all queues 3380 * @adapter: board private structure 3381 * 3382 * Return 0 on success, negative on failure 3383 **/ 3384 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 3385 { 3386 struct pci_dev *pdev = adapter->pdev; 3387 int i, err = 0; 3388 3389 for (i = 0; i < adapter->num_tx_queues; i++) { 3390 err = igb_setup_tx_resources(adapter->tx_ring[i]); 3391 if (err) { 3392 dev_err(&pdev->dev, 3393 "Allocation for Tx Queue %u failed\n", i); 3394 for (i--; i >= 0; i--) 3395 igb_free_tx_resources(adapter->tx_ring[i]); 3396 break; 3397 } 3398 } 3399 3400 return err; 3401 } 3402 3403 /** 3404 * igb_setup_tctl - configure the transmit control registers 3405 * @adapter: Board private structure 3406 **/ 3407 void igb_setup_tctl(struct igb_adapter *adapter) 3408 { 3409 struct e1000_hw *hw = &adapter->hw; 3410 u32 tctl; 3411 3412 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 3413 wr32(E1000_TXDCTL(0), 0); 3414 3415 /* Program the Transmit Control Register */ 3416 tctl = rd32(E1000_TCTL); 3417 tctl &= ~E1000_TCTL_CT; 3418 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 3419 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3420 3421 igb_config_collision_dist(hw); 3422 3423 /* Enable transmits */ 3424 tctl |= E1000_TCTL_EN; 3425 3426 wr32(E1000_TCTL, tctl); 3427 } 3428 3429 /** 3430 * igb_configure_tx_ring - Configure transmit ring after Reset 3431 * @adapter: board private structure 3432 * @ring: tx ring to configure 3433 * 3434 * Configure a transmit ring after a reset. 3435 **/ 3436 void igb_configure_tx_ring(struct igb_adapter *adapter, 3437 struct igb_ring *ring) 3438 { 3439 struct e1000_hw *hw = &adapter->hw; 3440 u32 txdctl = 0; 3441 u64 tdba = ring->dma; 3442 int reg_idx = ring->reg_idx; 3443 3444 /* disable the queue */ 3445 wr32(E1000_TXDCTL(reg_idx), 0); 3446 wrfl(); 3447 mdelay(10); 3448 3449 wr32(E1000_TDLEN(reg_idx), 3450 ring->count * sizeof(union e1000_adv_tx_desc)); 3451 wr32(E1000_TDBAL(reg_idx), 3452 tdba & 0x00000000ffffffffULL); 3453 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 3454 3455 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 3456 wr32(E1000_TDH(reg_idx), 0); 3457 writel(0, ring->tail); 3458 3459 txdctl |= IGB_TX_PTHRESH; 3460 txdctl |= IGB_TX_HTHRESH << 8; 3461 txdctl |= IGB_TX_WTHRESH << 16; 3462 3463 /* reinitialize tx_buffer_info */ 3464 memset(ring->tx_buffer_info, 0, 3465 sizeof(struct igb_tx_buffer) * ring->count); 3466 3467 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 3468 wr32(E1000_TXDCTL(reg_idx), txdctl); 3469 } 3470 3471 /** 3472 * igb_configure_tx - Configure transmit Unit after Reset 3473 * @adapter: board private structure 3474 * 3475 * Configure the Tx unit of the MAC after a reset. 3476 **/ 3477 static void igb_configure_tx(struct igb_adapter *adapter) 3478 { 3479 int i; 3480 3481 for (i = 0; i < adapter->num_tx_queues; i++) 3482 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 3483 } 3484 3485 /** 3486 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 3487 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 3488 * 3489 * Returns 0 on success, negative on failure 3490 **/ 3491 int igb_setup_rx_resources(struct igb_ring *rx_ring) 3492 { 3493 struct device *dev = rx_ring->dev; 3494 int size; 3495 3496 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3497 3498 rx_ring->rx_buffer_info = vmalloc(size); 3499 if (!rx_ring->rx_buffer_info) 3500 goto err; 3501 3502 /* Round up to nearest 4K */ 3503 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 3504 rx_ring->size = ALIGN(rx_ring->size, 4096); 3505 3506 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 3507 &rx_ring->dma, GFP_KERNEL); 3508 if (!rx_ring->desc) 3509 goto err; 3510 3511 rx_ring->next_to_alloc = 0; 3512 rx_ring->next_to_clean = 0; 3513 rx_ring->next_to_use = 0; 3514 3515 return 0; 3516 3517 err: 3518 vfree(rx_ring->rx_buffer_info); 3519 rx_ring->rx_buffer_info = NULL; 3520 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 3521 return -ENOMEM; 3522 } 3523 3524 /** 3525 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 3526 * (Descriptors) for all queues 3527 * @adapter: board private structure 3528 * 3529 * Return 0 on success, negative on failure 3530 **/ 3531 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 3532 { 3533 struct pci_dev *pdev = adapter->pdev; 3534 int i, err = 0; 3535 3536 for (i = 0; i < adapter->num_rx_queues; i++) { 3537 err = igb_setup_rx_resources(adapter->rx_ring[i]); 3538 if (err) { 3539 dev_err(&pdev->dev, 3540 "Allocation for Rx Queue %u failed\n", i); 3541 for (i--; i >= 0; i--) 3542 igb_free_rx_resources(adapter->rx_ring[i]); 3543 break; 3544 } 3545 } 3546 3547 return err; 3548 } 3549 3550 /** 3551 * igb_setup_mrqc - configure the multiple receive queue control registers 3552 * @adapter: Board private structure 3553 **/ 3554 static void igb_setup_mrqc(struct igb_adapter *adapter) 3555 { 3556 struct e1000_hw *hw = &adapter->hw; 3557 u32 mrqc, rxcsum; 3558 u32 j, num_rx_queues; 3559 u32 rss_key[10]; 3560 3561 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3562 for (j = 0; j < 10; j++) 3563 wr32(E1000_RSSRK(j), rss_key[j]); 3564 3565 num_rx_queues = adapter->rss_queues; 3566 3567 switch (hw->mac.type) { 3568 case e1000_82576: 3569 /* 82576 supports 2 RSS queues for SR-IOV */ 3570 if (adapter->vfs_allocated_count) 3571 num_rx_queues = 2; 3572 break; 3573 default: 3574 break; 3575 } 3576 3577 if (adapter->rss_indir_tbl_init != num_rx_queues) { 3578 for (j = 0; j < IGB_RETA_SIZE; j++) 3579 adapter->rss_indir_tbl[j] = 3580 (j * num_rx_queues) / IGB_RETA_SIZE; 3581 adapter->rss_indir_tbl_init = num_rx_queues; 3582 } 3583 igb_write_rss_indir_tbl(adapter); 3584 3585 /* Disable raw packet checksumming so that RSS hash is placed in 3586 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 3587 * offloads as they are enabled by default 3588 */ 3589 rxcsum = rd32(E1000_RXCSUM); 3590 rxcsum |= E1000_RXCSUM_PCSD; 3591 3592 if (adapter->hw.mac.type >= e1000_82576) 3593 /* Enable Receive Checksum Offload for SCTP */ 3594 rxcsum |= E1000_RXCSUM_CRCOFL; 3595 3596 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 3597 wr32(E1000_RXCSUM, rxcsum); 3598 3599 /* Generate RSS hash based on packet types, TCP/UDP 3600 * port numbers and/or IPv4/v6 src and dst addresses 3601 */ 3602 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 3603 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3604 E1000_MRQC_RSS_FIELD_IPV6 | 3605 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3606 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 3607 3608 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 3609 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 3610 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 3611 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 3612 3613 /* If VMDq is enabled then we set the appropriate mode for that, else 3614 * we default to RSS so that an RSS hash is calculated per packet even 3615 * if we are only using one queue 3616 */ 3617 if (adapter->vfs_allocated_count) { 3618 if (hw->mac.type > e1000_82575) { 3619 /* Set the default pool for the PF's first queue */ 3620 u32 vtctl = rd32(E1000_VT_CTL); 3621 3622 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 3623 E1000_VT_CTL_DISABLE_DEF_POOL); 3624 vtctl |= adapter->vfs_allocated_count << 3625 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 3626 wr32(E1000_VT_CTL, vtctl); 3627 } 3628 if (adapter->rss_queues > 1) 3629 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 3630 else 3631 mrqc |= E1000_MRQC_ENABLE_VMDQ; 3632 } else { 3633 if (hw->mac.type != e1000_i211) 3634 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 3635 } 3636 igb_vmm_control(adapter); 3637 3638 wr32(E1000_MRQC, mrqc); 3639 } 3640 3641 /** 3642 * igb_setup_rctl - configure the receive control registers 3643 * @adapter: Board private structure 3644 **/ 3645 void igb_setup_rctl(struct igb_adapter *adapter) 3646 { 3647 struct e1000_hw *hw = &adapter->hw; 3648 u32 rctl; 3649 3650 rctl = rd32(E1000_RCTL); 3651 3652 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3653 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 3654 3655 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 3656 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3657 3658 /* enable stripping of CRC. It's unlikely this will break BMC 3659 * redirection as it did with e1000. Newer features require 3660 * that the HW strips the CRC. 3661 */ 3662 rctl |= E1000_RCTL_SECRC; 3663 3664 /* disable store bad packets and clear size bits. */ 3665 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 3666 3667 /* enable LPE to allow for reception of jumbo frames */ 3668 rctl |= E1000_RCTL_LPE; 3669 3670 /* disable queue 0 to prevent tail write w/o re-config */ 3671 wr32(E1000_RXDCTL(0), 0); 3672 3673 /* Attention!!! For SR-IOV PF driver operations you must enable 3674 * queue drop for all VF and PF queues to prevent head of line blocking 3675 * if an un-trusted VF does not provide descriptors to hardware. 3676 */ 3677 if (adapter->vfs_allocated_count) { 3678 /* set all queue drop enable bits */ 3679 wr32(E1000_QDE, ALL_QUEUES); 3680 } 3681 3682 /* This is useful for sniffing bad packets. */ 3683 if (adapter->netdev->features & NETIF_F_RXALL) { 3684 /* UPE and MPE will be handled by normal PROMISC logic 3685 * in e1000e_set_rx_mode 3686 */ 3687 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3688 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3689 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3690 3691 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 3692 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3693 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3694 * and that breaks VLANs. 3695 */ 3696 } 3697 3698 wr32(E1000_RCTL, rctl); 3699 } 3700 3701 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 3702 int vfn) 3703 { 3704 struct e1000_hw *hw = &adapter->hw; 3705 u32 vmolr; 3706 3707 if (size > MAX_JUMBO_FRAME_SIZE) 3708 size = MAX_JUMBO_FRAME_SIZE; 3709 3710 vmolr = rd32(E1000_VMOLR(vfn)); 3711 vmolr &= ~E1000_VMOLR_RLPML_MASK; 3712 vmolr |= size | E1000_VMOLR_LPE; 3713 wr32(E1000_VMOLR(vfn), vmolr); 3714 3715 return 0; 3716 } 3717 3718 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 3719 int vfn, bool enable) 3720 { 3721 struct e1000_hw *hw = &adapter->hw; 3722 u32 val, reg; 3723 3724 if (hw->mac.type < e1000_82576) 3725 return; 3726 3727 if (hw->mac.type == e1000_i350) 3728 reg = E1000_DVMOLR(vfn); 3729 else 3730 reg = E1000_VMOLR(vfn); 3731 3732 val = rd32(reg); 3733 if (enable) 3734 val |= E1000_VMOLR_STRVLAN; 3735 else 3736 val &= ~(E1000_VMOLR_STRVLAN); 3737 wr32(reg, val); 3738 } 3739 3740 static inline void igb_set_vmolr(struct igb_adapter *adapter, 3741 int vfn, bool aupe) 3742 { 3743 struct e1000_hw *hw = &adapter->hw; 3744 u32 vmolr; 3745 3746 /* This register exists only on 82576 and newer so if we are older then 3747 * we should exit and do nothing 3748 */ 3749 if (hw->mac.type < e1000_82576) 3750 return; 3751 3752 vmolr = rd32(E1000_VMOLR(vfn)); 3753 if (aupe) 3754 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 3755 else 3756 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 3757 3758 /* clear all bits that might not be set */ 3759 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 3760 3761 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 3762 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 3763 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 3764 * multicast packets 3765 */ 3766 if (vfn <= adapter->vfs_allocated_count) 3767 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 3768 3769 wr32(E1000_VMOLR(vfn), vmolr); 3770 } 3771 3772 /** 3773 * igb_configure_rx_ring - Configure a receive ring after Reset 3774 * @adapter: board private structure 3775 * @ring: receive ring to be configured 3776 * 3777 * Configure the Rx unit of the MAC after a reset. 3778 **/ 3779 void igb_configure_rx_ring(struct igb_adapter *adapter, 3780 struct igb_ring *ring) 3781 { 3782 struct e1000_hw *hw = &adapter->hw; 3783 union e1000_adv_rx_desc *rx_desc; 3784 u64 rdba = ring->dma; 3785 int reg_idx = ring->reg_idx; 3786 u32 srrctl = 0, rxdctl = 0; 3787 3788 /* disable the queue */ 3789 wr32(E1000_RXDCTL(reg_idx), 0); 3790 3791 /* Set DMA base address registers */ 3792 wr32(E1000_RDBAL(reg_idx), 3793 rdba & 0x00000000ffffffffULL); 3794 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 3795 wr32(E1000_RDLEN(reg_idx), 3796 ring->count * sizeof(union e1000_adv_rx_desc)); 3797 3798 /* initialize head and tail */ 3799 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 3800 wr32(E1000_RDH(reg_idx), 0); 3801 writel(0, ring->tail); 3802 3803 /* set descriptor configuration */ 3804 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 3805 if (ring_uses_large_buffer(ring)) 3806 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3807 else 3808 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3809 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3810 if (hw->mac.type >= e1000_82580) 3811 srrctl |= E1000_SRRCTL_TIMESTAMP; 3812 /* Only set Drop Enable if we are supporting multiple queues */ 3813 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 3814 srrctl |= E1000_SRRCTL_DROP_EN; 3815 3816 wr32(E1000_SRRCTL(reg_idx), srrctl); 3817 3818 /* set filtering for VMDQ pools */ 3819 igb_set_vmolr(adapter, reg_idx & 0x7, true); 3820 3821 rxdctl |= IGB_RX_PTHRESH; 3822 rxdctl |= IGB_RX_HTHRESH << 8; 3823 rxdctl |= IGB_RX_WTHRESH << 16; 3824 3825 /* initialize rx_buffer_info */ 3826 memset(ring->rx_buffer_info, 0, 3827 sizeof(struct igb_rx_buffer) * ring->count); 3828 3829 /* initialize Rx descriptor 0 */ 3830 rx_desc = IGB_RX_DESC(ring, 0); 3831 rx_desc->wb.upper.length = 0; 3832 3833 /* enable receive descriptor fetching */ 3834 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3835 wr32(E1000_RXDCTL(reg_idx), rxdctl); 3836 } 3837 3838 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 3839 struct igb_ring *rx_ring) 3840 { 3841 /* set build_skb and buffer size flags */ 3842 clear_ring_build_skb_enabled(rx_ring); 3843 clear_ring_uses_large_buffer(rx_ring); 3844 3845 if (adapter->flags & IGB_FLAG_RX_LEGACY) 3846 return; 3847 3848 set_ring_build_skb_enabled(rx_ring); 3849 3850 #if (PAGE_SIZE < 8192) 3851 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 3852 return; 3853 3854 set_ring_uses_large_buffer(rx_ring); 3855 #endif 3856 } 3857 3858 /** 3859 * igb_configure_rx - Configure receive Unit after Reset 3860 * @adapter: board private structure 3861 * 3862 * Configure the Rx unit of the MAC after a reset. 3863 **/ 3864 static void igb_configure_rx(struct igb_adapter *adapter) 3865 { 3866 int i; 3867 3868 /* set the correct pool for the PF default MAC address in entry 0 */ 3869 igb_set_default_mac_filter(adapter); 3870 3871 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3872 * the Base and Length of the Rx Descriptor Ring 3873 */ 3874 for (i = 0; i < adapter->num_rx_queues; i++) { 3875 struct igb_ring *rx_ring = adapter->rx_ring[i]; 3876 3877 igb_set_rx_buffer_len(adapter, rx_ring); 3878 igb_configure_rx_ring(adapter, rx_ring); 3879 } 3880 } 3881 3882 /** 3883 * igb_free_tx_resources - Free Tx Resources per Queue 3884 * @tx_ring: Tx descriptor ring for a specific queue 3885 * 3886 * Free all transmit software resources 3887 **/ 3888 void igb_free_tx_resources(struct igb_ring *tx_ring) 3889 { 3890 igb_clean_tx_ring(tx_ring); 3891 3892 vfree(tx_ring->tx_buffer_info); 3893 tx_ring->tx_buffer_info = NULL; 3894 3895 /* if not set, then don't free */ 3896 if (!tx_ring->desc) 3897 return; 3898 3899 dma_free_coherent(tx_ring->dev, tx_ring->size, 3900 tx_ring->desc, tx_ring->dma); 3901 3902 tx_ring->desc = NULL; 3903 } 3904 3905 /** 3906 * igb_free_all_tx_resources - Free Tx Resources for All Queues 3907 * @adapter: board private structure 3908 * 3909 * Free all transmit software resources 3910 **/ 3911 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 3912 { 3913 int i; 3914 3915 for (i = 0; i < adapter->num_tx_queues; i++) 3916 if (adapter->tx_ring[i]) 3917 igb_free_tx_resources(adapter->tx_ring[i]); 3918 } 3919 3920 /** 3921 * igb_clean_tx_ring - Free Tx Buffers 3922 * @tx_ring: ring to be cleaned 3923 **/ 3924 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 3925 { 3926 u16 i = tx_ring->next_to_clean; 3927 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 3928 3929 while (i != tx_ring->next_to_use) { 3930 union e1000_adv_tx_desc *eop_desc, *tx_desc; 3931 3932 /* Free all the Tx ring sk_buffs */ 3933 dev_kfree_skb_any(tx_buffer->skb); 3934 3935 /* unmap skb header data */ 3936 dma_unmap_single(tx_ring->dev, 3937 dma_unmap_addr(tx_buffer, dma), 3938 dma_unmap_len(tx_buffer, len), 3939 DMA_TO_DEVICE); 3940 3941 /* check for eop_desc to determine the end of the packet */ 3942 eop_desc = tx_buffer->next_to_watch; 3943 tx_desc = IGB_TX_DESC(tx_ring, i); 3944 3945 /* unmap remaining buffers */ 3946 while (tx_desc != eop_desc) { 3947 tx_buffer++; 3948 tx_desc++; 3949 i++; 3950 if (unlikely(i == tx_ring->count)) { 3951 i = 0; 3952 tx_buffer = tx_ring->tx_buffer_info; 3953 tx_desc = IGB_TX_DESC(tx_ring, 0); 3954 } 3955 3956 /* unmap any remaining paged data */ 3957 if (dma_unmap_len(tx_buffer, len)) 3958 dma_unmap_page(tx_ring->dev, 3959 dma_unmap_addr(tx_buffer, dma), 3960 dma_unmap_len(tx_buffer, len), 3961 DMA_TO_DEVICE); 3962 } 3963 3964 /* move us one more past the eop_desc for start of next pkt */ 3965 tx_buffer++; 3966 i++; 3967 if (unlikely(i == tx_ring->count)) { 3968 i = 0; 3969 tx_buffer = tx_ring->tx_buffer_info; 3970 } 3971 } 3972 3973 /* reset BQL for queue */ 3974 netdev_tx_reset_queue(txring_txq(tx_ring)); 3975 3976 /* reset next_to_use and next_to_clean */ 3977 tx_ring->next_to_use = 0; 3978 tx_ring->next_to_clean = 0; 3979 } 3980 3981 /** 3982 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 3983 * @adapter: board private structure 3984 **/ 3985 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 3986 { 3987 int i; 3988 3989 for (i = 0; i < adapter->num_tx_queues; i++) 3990 if (adapter->tx_ring[i]) 3991 igb_clean_tx_ring(adapter->tx_ring[i]); 3992 } 3993 3994 /** 3995 * igb_free_rx_resources - Free Rx Resources 3996 * @rx_ring: ring to clean the resources from 3997 * 3998 * Free all receive software resources 3999 **/ 4000 void igb_free_rx_resources(struct igb_ring *rx_ring) 4001 { 4002 igb_clean_rx_ring(rx_ring); 4003 4004 vfree(rx_ring->rx_buffer_info); 4005 rx_ring->rx_buffer_info = NULL; 4006 4007 /* if not set, then don't free */ 4008 if (!rx_ring->desc) 4009 return; 4010 4011 dma_free_coherent(rx_ring->dev, rx_ring->size, 4012 rx_ring->desc, rx_ring->dma); 4013 4014 rx_ring->desc = NULL; 4015 } 4016 4017 /** 4018 * igb_free_all_rx_resources - Free Rx Resources for All Queues 4019 * @adapter: board private structure 4020 * 4021 * Free all receive software resources 4022 **/ 4023 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 4024 { 4025 int i; 4026 4027 for (i = 0; i < adapter->num_rx_queues; i++) 4028 if (adapter->rx_ring[i]) 4029 igb_free_rx_resources(adapter->rx_ring[i]); 4030 } 4031 4032 /** 4033 * igb_clean_rx_ring - Free Rx Buffers per Queue 4034 * @rx_ring: ring to free buffers from 4035 **/ 4036 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 4037 { 4038 u16 i = rx_ring->next_to_clean; 4039 4040 if (rx_ring->skb) 4041 dev_kfree_skb(rx_ring->skb); 4042 rx_ring->skb = NULL; 4043 4044 /* Free all the Rx ring sk_buffs */ 4045 while (i != rx_ring->next_to_alloc) { 4046 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 4047 4048 /* Invalidate cache lines that may have been written to by 4049 * device so that we avoid corrupting memory. 4050 */ 4051 dma_sync_single_range_for_cpu(rx_ring->dev, 4052 buffer_info->dma, 4053 buffer_info->page_offset, 4054 igb_rx_bufsz(rx_ring), 4055 DMA_FROM_DEVICE); 4056 4057 /* free resources associated with mapping */ 4058 dma_unmap_page_attrs(rx_ring->dev, 4059 buffer_info->dma, 4060 igb_rx_pg_size(rx_ring), 4061 DMA_FROM_DEVICE, 4062 IGB_RX_DMA_ATTR); 4063 __page_frag_cache_drain(buffer_info->page, 4064 buffer_info->pagecnt_bias); 4065 4066 i++; 4067 if (i == rx_ring->count) 4068 i = 0; 4069 } 4070 4071 rx_ring->next_to_alloc = 0; 4072 rx_ring->next_to_clean = 0; 4073 rx_ring->next_to_use = 0; 4074 } 4075 4076 /** 4077 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 4078 * @adapter: board private structure 4079 **/ 4080 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 4081 { 4082 int i; 4083 4084 for (i = 0; i < adapter->num_rx_queues; i++) 4085 if (adapter->rx_ring[i]) 4086 igb_clean_rx_ring(adapter->rx_ring[i]); 4087 } 4088 4089 /** 4090 * igb_set_mac - Change the Ethernet Address of the NIC 4091 * @netdev: network interface device structure 4092 * @p: pointer to an address structure 4093 * 4094 * Returns 0 on success, negative on failure 4095 **/ 4096 static int igb_set_mac(struct net_device *netdev, void *p) 4097 { 4098 struct igb_adapter *adapter = netdev_priv(netdev); 4099 struct e1000_hw *hw = &adapter->hw; 4100 struct sockaddr *addr = p; 4101 4102 if (!is_valid_ether_addr(addr->sa_data)) 4103 return -EADDRNOTAVAIL; 4104 4105 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4106 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 4107 4108 /* set the correct pool for the new PF MAC address in entry 0 */ 4109 igb_set_default_mac_filter(adapter); 4110 4111 return 0; 4112 } 4113 4114 /** 4115 * igb_write_mc_addr_list - write multicast addresses to MTA 4116 * @netdev: network interface device structure 4117 * 4118 * Writes multicast address list to the MTA hash table. 4119 * Returns: -ENOMEM on failure 4120 * 0 on no addresses written 4121 * X on writing X addresses to MTA 4122 **/ 4123 static int igb_write_mc_addr_list(struct net_device *netdev) 4124 { 4125 struct igb_adapter *adapter = netdev_priv(netdev); 4126 struct e1000_hw *hw = &adapter->hw; 4127 struct netdev_hw_addr *ha; 4128 u8 *mta_list; 4129 int i; 4130 4131 if (netdev_mc_empty(netdev)) { 4132 /* nothing to program, so clear mc list */ 4133 igb_update_mc_addr_list(hw, NULL, 0); 4134 igb_restore_vf_multicasts(adapter); 4135 return 0; 4136 } 4137 4138 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 4139 if (!mta_list) 4140 return -ENOMEM; 4141 4142 /* The shared function expects a packed array of only addresses. */ 4143 i = 0; 4144 netdev_for_each_mc_addr(ha, netdev) 4145 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 4146 4147 igb_update_mc_addr_list(hw, mta_list, i); 4148 kfree(mta_list); 4149 4150 return netdev_mc_count(netdev); 4151 } 4152 4153 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 4154 { 4155 struct e1000_hw *hw = &adapter->hw; 4156 u32 i, pf_id; 4157 4158 switch (hw->mac.type) { 4159 case e1000_i210: 4160 case e1000_i211: 4161 case e1000_i350: 4162 /* VLAN filtering needed for VLAN prio filter */ 4163 if (adapter->netdev->features & NETIF_F_NTUPLE) 4164 break; 4165 /* fall through */ 4166 case e1000_82576: 4167 case e1000_82580: 4168 case e1000_i354: 4169 /* VLAN filtering needed for pool filtering */ 4170 if (adapter->vfs_allocated_count) 4171 break; 4172 /* fall through */ 4173 default: 4174 return 1; 4175 } 4176 4177 /* We are already in VLAN promisc, nothing to do */ 4178 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 4179 return 0; 4180 4181 if (!adapter->vfs_allocated_count) 4182 goto set_vfta; 4183 4184 /* Add PF to all active pools */ 4185 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4186 4187 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4188 u32 vlvf = rd32(E1000_VLVF(i)); 4189 4190 vlvf |= BIT(pf_id); 4191 wr32(E1000_VLVF(i), vlvf); 4192 } 4193 4194 set_vfta: 4195 /* Set all bits in the VLAN filter table array */ 4196 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 4197 hw->mac.ops.write_vfta(hw, i, ~0U); 4198 4199 /* Set flag so we don't redo unnecessary work */ 4200 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 4201 4202 return 0; 4203 } 4204 4205 #define VFTA_BLOCK_SIZE 8 4206 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 4207 { 4208 struct e1000_hw *hw = &adapter->hw; 4209 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4210 u32 vid_start = vfta_offset * 32; 4211 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4212 u32 i, vid, word, bits, pf_id; 4213 4214 /* guarantee that we don't scrub out management VLAN */ 4215 vid = adapter->mng_vlan_id; 4216 if (vid >= vid_start && vid < vid_end) 4217 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4218 4219 if (!adapter->vfs_allocated_count) 4220 goto set_vfta; 4221 4222 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4223 4224 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4225 u32 vlvf = rd32(E1000_VLVF(i)); 4226 4227 /* pull VLAN ID from VLVF */ 4228 vid = vlvf & VLAN_VID_MASK; 4229 4230 /* only concern ourselves with a certain range */ 4231 if (vid < vid_start || vid >= vid_end) 4232 continue; 4233 4234 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 4235 /* record VLAN ID in VFTA */ 4236 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4237 4238 /* if PF is part of this then continue */ 4239 if (test_bit(vid, adapter->active_vlans)) 4240 continue; 4241 } 4242 4243 /* remove PF from the pool */ 4244 bits = ~BIT(pf_id); 4245 bits &= rd32(E1000_VLVF(i)); 4246 wr32(E1000_VLVF(i), bits); 4247 } 4248 4249 set_vfta: 4250 /* extract values from active_vlans and write back to VFTA */ 4251 for (i = VFTA_BLOCK_SIZE; i--;) { 4252 vid = (vfta_offset + i) * 32; 4253 word = vid / BITS_PER_LONG; 4254 bits = vid % BITS_PER_LONG; 4255 4256 vfta[i] |= adapter->active_vlans[word] >> bits; 4257 4258 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 4259 } 4260 } 4261 4262 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 4263 { 4264 u32 i; 4265 4266 /* We are not in VLAN promisc, nothing to do */ 4267 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 4268 return; 4269 4270 /* Set flag so we don't redo unnecessary work */ 4271 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 4272 4273 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 4274 igb_scrub_vfta(adapter, i); 4275 } 4276 4277 /** 4278 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 4279 * @netdev: network interface device structure 4280 * 4281 * The set_rx_mode entry point is called whenever the unicast or multicast 4282 * address lists or the network interface flags are updated. This routine is 4283 * responsible for configuring the hardware for proper unicast, multicast, 4284 * promiscuous mode, and all-multi behavior. 4285 **/ 4286 static void igb_set_rx_mode(struct net_device *netdev) 4287 { 4288 struct igb_adapter *adapter = netdev_priv(netdev); 4289 struct e1000_hw *hw = &adapter->hw; 4290 unsigned int vfn = adapter->vfs_allocated_count; 4291 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 4292 int count; 4293 4294 /* Check for Promiscuous and All Multicast modes */ 4295 if (netdev->flags & IFF_PROMISC) { 4296 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 4297 vmolr |= E1000_VMOLR_MPME; 4298 4299 /* enable use of UTA filter to force packets to default pool */ 4300 if (hw->mac.type == e1000_82576) 4301 vmolr |= E1000_VMOLR_ROPE; 4302 } else { 4303 if (netdev->flags & IFF_ALLMULTI) { 4304 rctl |= E1000_RCTL_MPE; 4305 vmolr |= E1000_VMOLR_MPME; 4306 } else { 4307 /* Write addresses to the MTA, if the attempt fails 4308 * then we should just turn on promiscuous mode so 4309 * that we can at least receive multicast traffic 4310 */ 4311 count = igb_write_mc_addr_list(netdev); 4312 if (count < 0) { 4313 rctl |= E1000_RCTL_MPE; 4314 vmolr |= E1000_VMOLR_MPME; 4315 } else if (count) { 4316 vmolr |= E1000_VMOLR_ROMPE; 4317 } 4318 } 4319 } 4320 4321 /* Write addresses to available RAR registers, if there is not 4322 * sufficient space to store all the addresses then enable 4323 * unicast promiscuous mode 4324 */ 4325 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 4326 rctl |= E1000_RCTL_UPE; 4327 vmolr |= E1000_VMOLR_ROPE; 4328 } 4329 4330 /* enable VLAN filtering by default */ 4331 rctl |= E1000_RCTL_VFE; 4332 4333 /* disable VLAN filtering for modes that require it */ 4334 if ((netdev->flags & IFF_PROMISC) || 4335 (netdev->features & NETIF_F_RXALL)) { 4336 /* if we fail to set all rules then just clear VFE */ 4337 if (igb_vlan_promisc_enable(adapter)) 4338 rctl &= ~E1000_RCTL_VFE; 4339 } else { 4340 igb_vlan_promisc_disable(adapter); 4341 } 4342 4343 /* update state of unicast, multicast, and VLAN filtering modes */ 4344 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 4345 E1000_RCTL_VFE); 4346 wr32(E1000_RCTL, rctl); 4347 4348 #if (PAGE_SIZE < 8192) 4349 if (!adapter->vfs_allocated_count) { 4350 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4351 rlpml = IGB_MAX_FRAME_BUILD_SKB; 4352 } 4353 #endif 4354 wr32(E1000_RLPML, rlpml); 4355 4356 /* In order to support SR-IOV and eventually VMDq it is necessary to set 4357 * the VMOLR to enable the appropriate modes. Without this workaround 4358 * we will have issues with VLAN tag stripping not being done for frames 4359 * that are only arriving because we are the default pool 4360 */ 4361 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 4362 return; 4363 4364 /* set UTA to appropriate mode */ 4365 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 4366 4367 vmolr |= rd32(E1000_VMOLR(vfn)) & 4368 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 4369 4370 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 4371 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4372 #if (PAGE_SIZE < 8192) 4373 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4374 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 4375 else 4376 #endif 4377 vmolr |= MAX_JUMBO_FRAME_SIZE; 4378 vmolr |= E1000_VMOLR_LPE; 4379 4380 wr32(E1000_VMOLR(vfn), vmolr); 4381 4382 igb_restore_vf_multicasts(adapter); 4383 } 4384 4385 static void igb_check_wvbr(struct igb_adapter *adapter) 4386 { 4387 struct e1000_hw *hw = &adapter->hw; 4388 u32 wvbr = 0; 4389 4390 switch (hw->mac.type) { 4391 case e1000_82576: 4392 case e1000_i350: 4393 wvbr = rd32(E1000_WVBR); 4394 if (!wvbr) 4395 return; 4396 break; 4397 default: 4398 break; 4399 } 4400 4401 adapter->wvbr |= wvbr; 4402 } 4403 4404 #define IGB_STAGGERED_QUEUE_OFFSET 8 4405 4406 static void igb_spoof_check(struct igb_adapter *adapter) 4407 { 4408 int j; 4409 4410 if (!adapter->wvbr) 4411 return; 4412 4413 for (j = 0; j < adapter->vfs_allocated_count; j++) { 4414 if (adapter->wvbr & BIT(j) || 4415 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 4416 dev_warn(&adapter->pdev->dev, 4417 "Spoof event(s) detected on VF %d\n", j); 4418 adapter->wvbr &= 4419 ~(BIT(j) | 4420 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 4421 } 4422 } 4423 } 4424 4425 /* Need to wait a few seconds after link up to get diagnostic information from 4426 * the phy 4427 */ 4428 static void igb_update_phy_info(unsigned long data) 4429 { 4430 struct igb_adapter *adapter = (struct igb_adapter *) data; 4431 igb_get_phy_info(&adapter->hw); 4432 } 4433 4434 /** 4435 * igb_has_link - check shared code for link and determine up/down 4436 * @adapter: pointer to driver private info 4437 **/ 4438 bool igb_has_link(struct igb_adapter *adapter) 4439 { 4440 struct e1000_hw *hw = &adapter->hw; 4441 bool link_active = false; 4442 4443 /* get_link_status is set on LSC (link status) interrupt or 4444 * rx sequence error interrupt. get_link_status will stay 4445 * false until the e1000_check_for_link establishes link 4446 * for copper adapters ONLY 4447 */ 4448 switch (hw->phy.media_type) { 4449 case e1000_media_type_copper: 4450 if (!hw->mac.get_link_status) 4451 return true; 4452 case e1000_media_type_internal_serdes: 4453 hw->mac.ops.check_for_link(hw); 4454 link_active = !hw->mac.get_link_status; 4455 break; 4456 default: 4457 case e1000_media_type_unknown: 4458 break; 4459 } 4460 4461 if (((hw->mac.type == e1000_i210) || 4462 (hw->mac.type == e1000_i211)) && 4463 (hw->phy.id == I210_I_PHY_ID)) { 4464 if (!netif_carrier_ok(adapter->netdev)) { 4465 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4466 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 4467 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 4468 adapter->link_check_timeout = jiffies; 4469 } 4470 } 4471 4472 return link_active; 4473 } 4474 4475 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 4476 { 4477 bool ret = false; 4478 u32 ctrl_ext, thstat; 4479 4480 /* check for thermal sensor event on i350 copper only */ 4481 if (hw->mac.type == e1000_i350) { 4482 thstat = rd32(E1000_THSTAT); 4483 ctrl_ext = rd32(E1000_CTRL_EXT); 4484 4485 if ((hw->phy.media_type == e1000_media_type_copper) && 4486 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 4487 ret = !!(thstat & event); 4488 } 4489 4490 return ret; 4491 } 4492 4493 /** 4494 * igb_check_lvmmc - check for malformed packets received 4495 * and indicated in LVMMC register 4496 * @adapter: pointer to adapter 4497 **/ 4498 static void igb_check_lvmmc(struct igb_adapter *adapter) 4499 { 4500 struct e1000_hw *hw = &adapter->hw; 4501 u32 lvmmc; 4502 4503 lvmmc = rd32(E1000_LVMMC); 4504 if (lvmmc) { 4505 if (unlikely(net_ratelimit())) { 4506 netdev_warn(adapter->netdev, 4507 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 4508 lvmmc); 4509 } 4510 } 4511 } 4512 4513 /** 4514 * igb_watchdog - Timer Call-back 4515 * @data: pointer to adapter cast into an unsigned long 4516 **/ 4517 static void igb_watchdog(unsigned long data) 4518 { 4519 struct igb_adapter *adapter = (struct igb_adapter *)data; 4520 /* Do the rest outside of interrupt context */ 4521 schedule_work(&adapter->watchdog_task); 4522 } 4523 4524 static void igb_watchdog_task(struct work_struct *work) 4525 { 4526 struct igb_adapter *adapter = container_of(work, 4527 struct igb_adapter, 4528 watchdog_task); 4529 struct e1000_hw *hw = &adapter->hw; 4530 struct e1000_phy_info *phy = &hw->phy; 4531 struct net_device *netdev = adapter->netdev; 4532 u32 link; 4533 int i; 4534 u32 connsw; 4535 u16 phy_data, retry_count = 20; 4536 4537 link = igb_has_link(adapter); 4538 4539 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 4540 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 4541 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4542 else 4543 link = false; 4544 } 4545 4546 /* Force link down if we have fiber to swap to */ 4547 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4548 if (hw->phy.media_type == e1000_media_type_copper) { 4549 connsw = rd32(E1000_CONNSW); 4550 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 4551 link = 0; 4552 } 4553 } 4554 if (link) { 4555 /* Perform a reset if the media type changed. */ 4556 if (hw->dev_spec._82575.media_changed) { 4557 hw->dev_spec._82575.media_changed = false; 4558 adapter->flags |= IGB_FLAG_MEDIA_RESET; 4559 igb_reset(adapter); 4560 } 4561 /* Cancel scheduled suspend requests. */ 4562 pm_runtime_resume(netdev->dev.parent); 4563 4564 if (!netif_carrier_ok(netdev)) { 4565 u32 ctrl; 4566 4567 hw->mac.ops.get_speed_and_duplex(hw, 4568 &adapter->link_speed, 4569 &adapter->link_duplex); 4570 4571 ctrl = rd32(E1000_CTRL); 4572 /* Links status message must follow this format */ 4573 netdev_info(netdev, 4574 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 4575 netdev->name, 4576 adapter->link_speed, 4577 adapter->link_duplex == FULL_DUPLEX ? 4578 "Full" : "Half", 4579 (ctrl & E1000_CTRL_TFCE) && 4580 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 4581 (ctrl & E1000_CTRL_RFCE) ? "RX" : 4582 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 4583 4584 /* disable EEE if enabled */ 4585 if ((adapter->flags & IGB_FLAG_EEE) && 4586 (adapter->link_duplex == HALF_DUPLEX)) { 4587 dev_info(&adapter->pdev->dev, 4588 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 4589 adapter->hw.dev_spec._82575.eee_disable = true; 4590 adapter->flags &= ~IGB_FLAG_EEE; 4591 } 4592 4593 /* check if SmartSpeed worked */ 4594 igb_check_downshift(hw); 4595 if (phy->speed_downgraded) 4596 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 4597 4598 /* check for thermal sensor event */ 4599 if (igb_thermal_sensor_event(hw, 4600 E1000_THSTAT_LINK_THROTTLE)) 4601 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 4602 4603 /* adjust timeout factor according to speed/duplex */ 4604 adapter->tx_timeout_factor = 1; 4605 switch (adapter->link_speed) { 4606 case SPEED_10: 4607 adapter->tx_timeout_factor = 14; 4608 break; 4609 case SPEED_100: 4610 /* maybe add some timeout factor ? */ 4611 break; 4612 } 4613 4614 if (adapter->link_speed != SPEED_1000) 4615 goto no_wait; 4616 4617 /* wait for Remote receiver status OK */ 4618 retry_read_status: 4619 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 4620 &phy_data)) { 4621 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 4622 retry_count) { 4623 msleep(100); 4624 retry_count--; 4625 goto retry_read_status; 4626 } else if (!retry_count) { 4627 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 4628 } 4629 } else { 4630 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 4631 } 4632 no_wait: 4633 netif_carrier_on(netdev); 4634 4635 igb_ping_all_vfs(adapter); 4636 igb_check_vf_rate_limit(adapter); 4637 4638 /* link state has changed, schedule phy info update */ 4639 if (!test_bit(__IGB_DOWN, &adapter->state)) 4640 mod_timer(&adapter->phy_info_timer, 4641 round_jiffies(jiffies + 2 * HZ)); 4642 } 4643 } else { 4644 if (netif_carrier_ok(netdev)) { 4645 adapter->link_speed = 0; 4646 adapter->link_duplex = 0; 4647 4648 /* check for thermal sensor event */ 4649 if (igb_thermal_sensor_event(hw, 4650 E1000_THSTAT_PWR_DOWN)) { 4651 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 4652 } 4653 4654 /* Links status message must follow this format */ 4655 netdev_info(netdev, "igb: %s NIC Link is Down\n", 4656 netdev->name); 4657 netif_carrier_off(netdev); 4658 4659 igb_ping_all_vfs(adapter); 4660 4661 /* link state has changed, schedule phy info update */ 4662 if (!test_bit(__IGB_DOWN, &adapter->state)) 4663 mod_timer(&adapter->phy_info_timer, 4664 round_jiffies(jiffies + 2 * HZ)); 4665 4666 /* link is down, time to check for alternate media */ 4667 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4668 igb_check_swap_media(adapter); 4669 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4670 schedule_work(&adapter->reset_task); 4671 /* return immediately */ 4672 return; 4673 } 4674 } 4675 pm_schedule_suspend(netdev->dev.parent, 4676 MSEC_PER_SEC * 5); 4677 4678 /* also check for alternate media here */ 4679 } else if (!netif_carrier_ok(netdev) && 4680 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 4681 igb_check_swap_media(adapter); 4682 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4683 schedule_work(&adapter->reset_task); 4684 /* return immediately */ 4685 return; 4686 } 4687 } 4688 } 4689 4690 spin_lock(&adapter->stats64_lock); 4691 igb_update_stats(adapter); 4692 spin_unlock(&adapter->stats64_lock); 4693 4694 for (i = 0; i < adapter->num_tx_queues; i++) { 4695 struct igb_ring *tx_ring = adapter->tx_ring[i]; 4696 if (!netif_carrier_ok(netdev)) { 4697 /* We've lost link, so the controller stops DMA, 4698 * but we've got queued Tx work that's never going 4699 * to get done, so reset controller to flush Tx. 4700 * (Do the reset outside of interrupt context). 4701 */ 4702 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 4703 adapter->tx_timeout_count++; 4704 schedule_work(&adapter->reset_task); 4705 /* return immediately since reset is imminent */ 4706 return; 4707 } 4708 } 4709 4710 /* Force detection of hung controller every watchdog period */ 4711 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 4712 } 4713 4714 /* Cause software interrupt to ensure Rx ring is cleaned */ 4715 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 4716 u32 eics = 0; 4717 4718 for (i = 0; i < adapter->num_q_vectors; i++) 4719 eics |= adapter->q_vector[i]->eims_value; 4720 wr32(E1000_EICS, eics); 4721 } else { 4722 wr32(E1000_ICS, E1000_ICS_RXDMT0); 4723 } 4724 4725 igb_spoof_check(adapter); 4726 igb_ptp_rx_hang(adapter); 4727 igb_ptp_tx_hang(adapter); 4728 4729 /* Check LVMMC register on i350/i354 only */ 4730 if ((adapter->hw.mac.type == e1000_i350) || 4731 (adapter->hw.mac.type == e1000_i354)) 4732 igb_check_lvmmc(adapter); 4733 4734 /* Reset the timer */ 4735 if (!test_bit(__IGB_DOWN, &adapter->state)) { 4736 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 4737 mod_timer(&adapter->watchdog_timer, 4738 round_jiffies(jiffies + HZ)); 4739 else 4740 mod_timer(&adapter->watchdog_timer, 4741 round_jiffies(jiffies + 2 * HZ)); 4742 } 4743 } 4744 4745 enum latency_range { 4746 lowest_latency = 0, 4747 low_latency = 1, 4748 bulk_latency = 2, 4749 latency_invalid = 255 4750 }; 4751 4752 /** 4753 * igb_update_ring_itr - update the dynamic ITR value based on packet size 4754 * @q_vector: pointer to q_vector 4755 * 4756 * Stores a new ITR value based on strictly on packet size. This 4757 * algorithm is less sophisticated than that used in igb_update_itr, 4758 * due to the difficulty of synchronizing statistics across multiple 4759 * receive rings. The divisors and thresholds used by this function 4760 * were determined based on theoretical maximum wire speed and testing 4761 * data, in order to minimize response time while increasing bulk 4762 * throughput. 4763 * This functionality is controlled by ethtool's coalescing settings. 4764 * NOTE: This function is called only when operating in a multiqueue 4765 * receive environment. 4766 **/ 4767 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 4768 { 4769 int new_val = q_vector->itr_val; 4770 int avg_wire_size = 0; 4771 struct igb_adapter *adapter = q_vector->adapter; 4772 unsigned int packets; 4773 4774 /* For non-gigabit speeds, just fix the interrupt rate at 4000 4775 * ints/sec - ITR timer value of 120 ticks. 4776 */ 4777 if (adapter->link_speed != SPEED_1000) { 4778 new_val = IGB_4K_ITR; 4779 goto set_itr_val; 4780 } 4781 4782 packets = q_vector->rx.total_packets; 4783 if (packets) 4784 avg_wire_size = q_vector->rx.total_bytes / packets; 4785 4786 packets = q_vector->tx.total_packets; 4787 if (packets) 4788 avg_wire_size = max_t(u32, avg_wire_size, 4789 q_vector->tx.total_bytes / packets); 4790 4791 /* if avg_wire_size isn't set no work was done */ 4792 if (!avg_wire_size) 4793 goto clear_counts; 4794 4795 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 4796 avg_wire_size += 24; 4797 4798 /* Don't starve jumbo frames */ 4799 avg_wire_size = min(avg_wire_size, 3000); 4800 4801 /* Give a little boost to mid-size frames */ 4802 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 4803 new_val = avg_wire_size / 3; 4804 else 4805 new_val = avg_wire_size / 2; 4806 4807 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4808 if (new_val < IGB_20K_ITR && 4809 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4810 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4811 new_val = IGB_20K_ITR; 4812 4813 set_itr_val: 4814 if (new_val != q_vector->itr_val) { 4815 q_vector->itr_val = new_val; 4816 q_vector->set_itr = 1; 4817 } 4818 clear_counts: 4819 q_vector->rx.total_bytes = 0; 4820 q_vector->rx.total_packets = 0; 4821 q_vector->tx.total_bytes = 0; 4822 q_vector->tx.total_packets = 0; 4823 } 4824 4825 /** 4826 * igb_update_itr - update the dynamic ITR value based on statistics 4827 * @q_vector: pointer to q_vector 4828 * @ring_container: ring info to update the itr for 4829 * 4830 * Stores a new ITR value based on packets and byte 4831 * counts during the last interrupt. The advantage of per interrupt 4832 * computation is faster updates and more accurate ITR for the current 4833 * traffic pattern. Constants in this function were computed 4834 * based on theoretical maximum wire speed and thresholds were set based 4835 * on testing data as well as attempting to minimize response time 4836 * while increasing bulk throughput. 4837 * This functionality is controlled by ethtool's coalescing settings. 4838 * NOTE: These calculations are only valid when operating in a single- 4839 * queue environment. 4840 **/ 4841 static void igb_update_itr(struct igb_q_vector *q_vector, 4842 struct igb_ring_container *ring_container) 4843 { 4844 unsigned int packets = ring_container->total_packets; 4845 unsigned int bytes = ring_container->total_bytes; 4846 u8 itrval = ring_container->itr; 4847 4848 /* no packets, exit with status unchanged */ 4849 if (packets == 0) 4850 return; 4851 4852 switch (itrval) { 4853 case lowest_latency: 4854 /* handle TSO and jumbo frames */ 4855 if (bytes/packets > 8000) 4856 itrval = bulk_latency; 4857 else if ((packets < 5) && (bytes > 512)) 4858 itrval = low_latency; 4859 break; 4860 case low_latency: /* 50 usec aka 20000 ints/s */ 4861 if (bytes > 10000) { 4862 /* this if handles the TSO accounting */ 4863 if (bytes/packets > 8000) 4864 itrval = bulk_latency; 4865 else if ((packets < 10) || ((bytes/packets) > 1200)) 4866 itrval = bulk_latency; 4867 else if ((packets > 35)) 4868 itrval = lowest_latency; 4869 } else if (bytes/packets > 2000) { 4870 itrval = bulk_latency; 4871 } else if (packets <= 2 && bytes < 512) { 4872 itrval = lowest_latency; 4873 } 4874 break; 4875 case bulk_latency: /* 250 usec aka 4000 ints/s */ 4876 if (bytes > 25000) { 4877 if (packets > 35) 4878 itrval = low_latency; 4879 } else if (bytes < 1500) { 4880 itrval = low_latency; 4881 } 4882 break; 4883 } 4884 4885 /* clear work counters since we have the values we need */ 4886 ring_container->total_bytes = 0; 4887 ring_container->total_packets = 0; 4888 4889 /* write updated itr to ring container */ 4890 ring_container->itr = itrval; 4891 } 4892 4893 static void igb_set_itr(struct igb_q_vector *q_vector) 4894 { 4895 struct igb_adapter *adapter = q_vector->adapter; 4896 u32 new_itr = q_vector->itr_val; 4897 u8 current_itr = 0; 4898 4899 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 4900 if (adapter->link_speed != SPEED_1000) { 4901 current_itr = 0; 4902 new_itr = IGB_4K_ITR; 4903 goto set_itr_now; 4904 } 4905 4906 igb_update_itr(q_vector, &q_vector->tx); 4907 igb_update_itr(q_vector, &q_vector->rx); 4908 4909 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 4910 4911 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4912 if (current_itr == lowest_latency && 4913 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4914 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4915 current_itr = low_latency; 4916 4917 switch (current_itr) { 4918 /* counts and packets in update_itr are dependent on these numbers */ 4919 case lowest_latency: 4920 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 4921 break; 4922 case low_latency: 4923 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 4924 break; 4925 case bulk_latency: 4926 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 4927 break; 4928 default: 4929 break; 4930 } 4931 4932 set_itr_now: 4933 if (new_itr != q_vector->itr_val) { 4934 /* this attempts to bias the interrupt rate towards Bulk 4935 * by adding intermediate steps when interrupt rate is 4936 * increasing 4937 */ 4938 new_itr = new_itr > q_vector->itr_val ? 4939 max((new_itr * q_vector->itr_val) / 4940 (new_itr + (q_vector->itr_val >> 2)), 4941 new_itr) : new_itr; 4942 /* Don't write the value here; it resets the adapter's 4943 * internal timer, and causes us to delay far longer than 4944 * we should between interrupts. Instead, we write the ITR 4945 * value at the beginning of the next interrupt so the timing 4946 * ends up being correct. 4947 */ 4948 q_vector->itr_val = new_itr; 4949 q_vector->set_itr = 1; 4950 } 4951 } 4952 4953 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 4954 u32 type_tucmd, u32 mss_l4len_idx) 4955 { 4956 struct e1000_adv_tx_context_desc *context_desc; 4957 u16 i = tx_ring->next_to_use; 4958 4959 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 4960 4961 i++; 4962 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 4963 4964 /* set bits to identify this as an advanced context descriptor */ 4965 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 4966 4967 /* For 82575, context index must be unique per ring. */ 4968 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4969 mss_l4len_idx |= tx_ring->reg_idx << 4; 4970 4971 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 4972 context_desc->seqnum_seed = 0; 4973 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 4974 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 4975 } 4976 4977 static int igb_tso(struct igb_ring *tx_ring, 4978 struct igb_tx_buffer *first, 4979 u8 *hdr_len) 4980 { 4981 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 4982 struct sk_buff *skb = first->skb; 4983 union { 4984 struct iphdr *v4; 4985 struct ipv6hdr *v6; 4986 unsigned char *hdr; 4987 } ip; 4988 union { 4989 struct tcphdr *tcp; 4990 unsigned char *hdr; 4991 } l4; 4992 u32 paylen, l4_offset; 4993 int err; 4994 4995 if (skb->ip_summed != CHECKSUM_PARTIAL) 4996 return 0; 4997 4998 if (!skb_is_gso(skb)) 4999 return 0; 5000 5001 err = skb_cow_head(skb, 0); 5002 if (err < 0) 5003 return err; 5004 5005 ip.hdr = skb_network_header(skb); 5006 l4.hdr = skb_checksum_start(skb); 5007 5008 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 5009 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 5010 5011 /* initialize outer IP header fields */ 5012 if (ip.v4->version == 4) { 5013 unsigned char *csum_start = skb_checksum_start(skb); 5014 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 5015 5016 /* IP header will have to cancel out any data that 5017 * is not a part of the outer IP header 5018 */ 5019 ip.v4->check = csum_fold(csum_partial(trans_start, 5020 csum_start - trans_start, 5021 0)); 5022 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 5023 5024 ip.v4->tot_len = 0; 5025 first->tx_flags |= IGB_TX_FLAGS_TSO | 5026 IGB_TX_FLAGS_CSUM | 5027 IGB_TX_FLAGS_IPV4; 5028 } else { 5029 ip.v6->payload_len = 0; 5030 first->tx_flags |= IGB_TX_FLAGS_TSO | 5031 IGB_TX_FLAGS_CSUM; 5032 } 5033 5034 /* determine offset of inner transport header */ 5035 l4_offset = l4.hdr - skb->data; 5036 5037 /* compute length of segmentation header */ 5038 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 5039 5040 /* remove payload length from inner checksum */ 5041 paylen = skb->len - l4_offset; 5042 csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); 5043 5044 /* update gso size and bytecount with header size */ 5045 first->gso_segs = skb_shinfo(skb)->gso_segs; 5046 first->bytecount += (first->gso_segs - 1) * *hdr_len; 5047 5048 /* MSS L4LEN IDX */ 5049 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 5050 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 5051 5052 /* VLAN MACLEN IPLEN */ 5053 vlan_macip_lens = l4.hdr - ip.hdr; 5054 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 5055 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5056 5057 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 5058 5059 return 1; 5060 } 5061 5062 static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb) 5063 { 5064 unsigned int offset = 0; 5065 5066 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 5067 5068 return offset == skb_checksum_start_offset(skb); 5069 } 5070 5071 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 5072 { 5073 struct sk_buff *skb = first->skb; 5074 u32 vlan_macip_lens = 0; 5075 u32 type_tucmd = 0; 5076 5077 if (skb->ip_summed != CHECKSUM_PARTIAL) { 5078 csum_failed: 5079 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 5080 return; 5081 goto no_csum; 5082 } 5083 5084 switch (skb->csum_offset) { 5085 case offsetof(struct tcphdr, check): 5086 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 5087 /* fall through */ 5088 case offsetof(struct udphdr, check): 5089 break; 5090 case offsetof(struct sctphdr, checksum): 5091 /* validate that this is actually an SCTP request */ 5092 if (((first->protocol == htons(ETH_P_IP)) && 5093 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 5094 ((first->protocol == htons(ETH_P_IPV6)) && 5095 igb_ipv6_csum_is_sctp(skb))) { 5096 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 5097 break; 5098 } 5099 default: 5100 skb_checksum_help(skb); 5101 goto csum_failed; 5102 } 5103 5104 /* update TX checksum flag */ 5105 first->tx_flags |= IGB_TX_FLAGS_CSUM; 5106 vlan_macip_lens = skb_checksum_start_offset(skb) - 5107 skb_network_offset(skb); 5108 no_csum: 5109 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 5110 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5111 5112 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, 0); 5113 } 5114 5115 #define IGB_SET_FLAG(_input, _flag, _result) \ 5116 ((_flag <= _result) ? \ 5117 ((u32)(_input & _flag) * (_result / _flag)) : \ 5118 ((u32)(_input & _flag) / (_flag / _result))) 5119 5120 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 5121 { 5122 /* set type for advanced descriptor with frame checksum insertion */ 5123 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 5124 E1000_ADVTXD_DCMD_DEXT | 5125 E1000_ADVTXD_DCMD_IFCS; 5126 5127 /* set HW vlan bit if vlan is present */ 5128 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 5129 (E1000_ADVTXD_DCMD_VLE)); 5130 5131 /* set segmentation bits for TSO */ 5132 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 5133 (E1000_ADVTXD_DCMD_TSE)); 5134 5135 /* set timestamp bit if present */ 5136 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 5137 (E1000_ADVTXD_MAC_TSTAMP)); 5138 5139 /* insert frame checksum */ 5140 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 5141 5142 return cmd_type; 5143 } 5144 5145 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 5146 union e1000_adv_tx_desc *tx_desc, 5147 u32 tx_flags, unsigned int paylen) 5148 { 5149 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 5150 5151 /* 82575 requires a unique index per ring */ 5152 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5153 olinfo_status |= tx_ring->reg_idx << 4; 5154 5155 /* insert L4 checksum */ 5156 olinfo_status |= IGB_SET_FLAG(tx_flags, 5157 IGB_TX_FLAGS_CSUM, 5158 (E1000_TXD_POPTS_TXSM << 8)); 5159 5160 /* insert IPv4 checksum */ 5161 olinfo_status |= IGB_SET_FLAG(tx_flags, 5162 IGB_TX_FLAGS_IPV4, 5163 (E1000_TXD_POPTS_IXSM << 8)); 5164 5165 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 5166 } 5167 5168 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5169 { 5170 struct net_device *netdev = tx_ring->netdev; 5171 5172 netif_stop_subqueue(netdev, tx_ring->queue_index); 5173 5174 /* Herbert's original patch had: 5175 * smp_mb__after_netif_stop_queue(); 5176 * but since that doesn't exist yet, just open code it. 5177 */ 5178 smp_mb(); 5179 5180 /* We need to check again in a case another CPU has just 5181 * made room available. 5182 */ 5183 if (igb_desc_unused(tx_ring) < size) 5184 return -EBUSY; 5185 5186 /* A reprieve! */ 5187 netif_wake_subqueue(netdev, tx_ring->queue_index); 5188 5189 u64_stats_update_begin(&tx_ring->tx_syncp2); 5190 tx_ring->tx_stats.restart_queue2++; 5191 u64_stats_update_end(&tx_ring->tx_syncp2); 5192 5193 return 0; 5194 } 5195 5196 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5197 { 5198 if (igb_desc_unused(tx_ring) >= size) 5199 return 0; 5200 return __igb_maybe_stop_tx(tx_ring, size); 5201 } 5202 5203 static int igb_tx_map(struct igb_ring *tx_ring, 5204 struct igb_tx_buffer *first, 5205 const u8 hdr_len) 5206 { 5207 struct sk_buff *skb = first->skb; 5208 struct igb_tx_buffer *tx_buffer; 5209 union e1000_adv_tx_desc *tx_desc; 5210 struct skb_frag_struct *frag; 5211 dma_addr_t dma; 5212 unsigned int data_len, size; 5213 u32 tx_flags = first->tx_flags; 5214 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 5215 u16 i = tx_ring->next_to_use; 5216 5217 tx_desc = IGB_TX_DESC(tx_ring, i); 5218 5219 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 5220 5221 size = skb_headlen(skb); 5222 data_len = skb->data_len; 5223 5224 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 5225 5226 tx_buffer = first; 5227 5228 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 5229 if (dma_mapping_error(tx_ring->dev, dma)) 5230 goto dma_error; 5231 5232 /* record length, and DMA address */ 5233 dma_unmap_len_set(tx_buffer, len, size); 5234 dma_unmap_addr_set(tx_buffer, dma, dma); 5235 5236 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5237 5238 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 5239 tx_desc->read.cmd_type_len = 5240 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 5241 5242 i++; 5243 tx_desc++; 5244 if (i == tx_ring->count) { 5245 tx_desc = IGB_TX_DESC(tx_ring, 0); 5246 i = 0; 5247 } 5248 tx_desc->read.olinfo_status = 0; 5249 5250 dma += IGB_MAX_DATA_PER_TXD; 5251 size -= IGB_MAX_DATA_PER_TXD; 5252 5253 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5254 } 5255 5256 if (likely(!data_len)) 5257 break; 5258 5259 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 5260 5261 i++; 5262 tx_desc++; 5263 if (i == tx_ring->count) { 5264 tx_desc = IGB_TX_DESC(tx_ring, 0); 5265 i = 0; 5266 } 5267 tx_desc->read.olinfo_status = 0; 5268 5269 size = skb_frag_size(frag); 5270 data_len -= size; 5271 5272 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 5273 size, DMA_TO_DEVICE); 5274 5275 tx_buffer = &tx_ring->tx_buffer_info[i]; 5276 } 5277 5278 /* write last descriptor with RS and EOP bits */ 5279 cmd_type |= size | IGB_TXD_DCMD; 5280 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 5281 5282 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 5283 5284 /* set the timestamp */ 5285 first->time_stamp = jiffies; 5286 5287 /* Force memory writes to complete before letting h/w know there 5288 * are new descriptors to fetch. (Only applicable for weak-ordered 5289 * memory model archs, such as IA-64). 5290 * 5291 * We also need this memory barrier to make certain all of the 5292 * status bits have been updated before next_to_watch is written. 5293 */ 5294 wmb(); 5295 5296 /* set next_to_watch value indicating a packet is present */ 5297 first->next_to_watch = tx_desc; 5298 5299 i++; 5300 if (i == tx_ring->count) 5301 i = 0; 5302 5303 tx_ring->next_to_use = i; 5304 5305 /* Make sure there is space in the ring for the next send. */ 5306 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 5307 5308 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 5309 writel(i, tx_ring->tail); 5310 5311 /* we need this if more than one processor can write to our tail 5312 * at a time, it synchronizes IO on IA64/Altix systems 5313 */ 5314 mmiowb(); 5315 } 5316 return 0; 5317 5318 dma_error: 5319 dev_err(tx_ring->dev, "TX DMA map failed\n"); 5320 tx_buffer = &tx_ring->tx_buffer_info[i]; 5321 5322 /* clear dma mappings for failed tx_buffer_info map */ 5323 while (tx_buffer != first) { 5324 if (dma_unmap_len(tx_buffer, len)) 5325 dma_unmap_page(tx_ring->dev, 5326 dma_unmap_addr(tx_buffer, dma), 5327 dma_unmap_len(tx_buffer, len), 5328 DMA_TO_DEVICE); 5329 dma_unmap_len_set(tx_buffer, len, 0); 5330 5331 if (i--) 5332 i += tx_ring->count; 5333 tx_buffer = &tx_ring->tx_buffer_info[i]; 5334 } 5335 5336 if (dma_unmap_len(tx_buffer, len)) 5337 dma_unmap_single(tx_ring->dev, 5338 dma_unmap_addr(tx_buffer, dma), 5339 dma_unmap_len(tx_buffer, len), 5340 DMA_TO_DEVICE); 5341 dma_unmap_len_set(tx_buffer, len, 0); 5342 5343 dev_kfree_skb_any(tx_buffer->skb); 5344 tx_buffer->skb = NULL; 5345 5346 tx_ring->next_to_use = i; 5347 5348 return -1; 5349 } 5350 5351 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 5352 struct igb_ring *tx_ring) 5353 { 5354 struct igb_tx_buffer *first; 5355 int tso; 5356 u32 tx_flags = 0; 5357 unsigned short f; 5358 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 5359 __be16 protocol = vlan_get_protocol(skb); 5360 u8 hdr_len = 0; 5361 5362 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 5363 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 5364 * + 2 desc gap to keep tail from touching head, 5365 * + 1 desc for context descriptor, 5366 * otherwise try next time 5367 */ 5368 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 5369 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 5370 5371 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 5372 /* this is a hard error */ 5373 return NETDEV_TX_BUSY; 5374 } 5375 5376 /* record the location of the first descriptor for this packet */ 5377 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 5378 first->skb = skb; 5379 first->bytecount = skb->len; 5380 first->gso_segs = 1; 5381 5382 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 5383 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 5384 5385 if (adapter->tstamp_config.tx_type & HWTSTAMP_TX_ON && 5386 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 5387 &adapter->state)) { 5388 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5389 tx_flags |= IGB_TX_FLAGS_TSTAMP; 5390 5391 adapter->ptp_tx_skb = skb_get(skb); 5392 adapter->ptp_tx_start = jiffies; 5393 if (adapter->hw.mac.type == e1000_82576) 5394 schedule_work(&adapter->ptp_tx_work); 5395 } else { 5396 adapter->tx_hwtstamp_skipped++; 5397 } 5398 } 5399 5400 skb_tx_timestamp(skb); 5401 5402 if (skb_vlan_tag_present(skb)) { 5403 tx_flags |= IGB_TX_FLAGS_VLAN; 5404 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 5405 } 5406 5407 /* record initial flags and protocol */ 5408 first->tx_flags = tx_flags; 5409 first->protocol = protocol; 5410 5411 tso = igb_tso(tx_ring, first, &hdr_len); 5412 if (tso < 0) 5413 goto out_drop; 5414 else if (!tso) 5415 igb_tx_csum(tx_ring, first); 5416 5417 if (igb_tx_map(tx_ring, first, hdr_len)) 5418 goto cleanup_tx_tstamp; 5419 5420 return NETDEV_TX_OK; 5421 5422 out_drop: 5423 dev_kfree_skb_any(first->skb); 5424 first->skb = NULL; 5425 cleanup_tx_tstamp: 5426 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 5427 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 5428 5429 dev_kfree_skb_any(adapter->ptp_tx_skb); 5430 adapter->ptp_tx_skb = NULL; 5431 if (adapter->hw.mac.type == e1000_82576) 5432 cancel_work_sync(&adapter->ptp_tx_work); 5433 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 5434 } 5435 5436 return NETDEV_TX_OK; 5437 } 5438 5439 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 5440 struct sk_buff *skb) 5441 { 5442 unsigned int r_idx = skb->queue_mapping; 5443 5444 if (r_idx >= adapter->num_tx_queues) 5445 r_idx = r_idx % adapter->num_tx_queues; 5446 5447 return adapter->tx_ring[r_idx]; 5448 } 5449 5450 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 5451 struct net_device *netdev) 5452 { 5453 struct igb_adapter *adapter = netdev_priv(netdev); 5454 5455 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 5456 * in order to meet this minimum size requirement. 5457 */ 5458 if (skb_put_padto(skb, 17)) 5459 return NETDEV_TX_OK; 5460 5461 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 5462 } 5463 5464 /** 5465 * igb_tx_timeout - Respond to a Tx Hang 5466 * @netdev: network interface device structure 5467 **/ 5468 static void igb_tx_timeout(struct net_device *netdev) 5469 { 5470 struct igb_adapter *adapter = netdev_priv(netdev); 5471 struct e1000_hw *hw = &adapter->hw; 5472 5473 /* Do the reset outside of interrupt context */ 5474 adapter->tx_timeout_count++; 5475 5476 if (hw->mac.type >= e1000_82580) 5477 hw->dev_spec._82575.global_device_reset = true; 5478 5479 schedule_work(&adapter->reset_task); 5480 wr32(E1000_EICS, 5481 (adapter->eims_enable_mask & ~adapter->eims_other)); 5482 } 5483 5484 static void igb_reset_task(struct work_struct *work) 5485 { 5486 struct igb_adapter *adapter; 5487 adapter = container_of(work, struct igb_adapter, reset_task); 5488 5489 igb_dump(adapter); 5490 netdev_err(adapter->netdev, "Reset adapter\n"); 5491 igb_reinit_locked(adapter); 5492 } 5493 5494 /** 5495 * igb_get_stats64 - Get System Network Statistics 5496 * @netdev: network interface device structure 5497 * @stats: rtnl_link_stats64 pointer 5498 **/ 5499 static void igb_get_stats64(struct net_device *netdev, 5500 struct rtnl_link_stats64 *stats) 5501 { 5502 struct igb_adapter *adapter = netdev_priv(netdev); 5503 5504 spin_lock(&adapter->stats64_lock); 5505 igb_update_stats(adapter); 5506 memcpy(stats, &adapter->stats64, sizeof(*stats)); 5507 spin_unlock(&adapter->stats64_lock); 5508 } 5509 5510 /** 5511 * igb_change_mtu - Change the Maximum Transfer Unit 5512 * @netdev: network interface device structure 5513 * @new_mtu: new value for maximum frame size 5514 * 5515 * Returns 0 on success, negative on failure 5516 **/ 5517 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 5518 { 5519 struct igb_adapter *adapter = netdev_priv(netdev); 5520 struct pci_dev *pdev = adapter->pdev; 5521 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 5522 5523 /* adjust max frame to be at least the size of a standard frame */ 5524 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 5525 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 5526 5527 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 5528 usleep_range(1000, 2000); 5529 5530 /* igb_down has a dependency on max_frame_size */ 5531 adapter->max_frame_size = max_frame; 5532 5533 if (netif_running(netdev)) 5534 igb_down(adapter); 5535 5536 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 5537 netdev->mtu, new_mtu); 5538 netdev->mtu = new_mtu; 5539 5540 if (netif_running(netdev)) 5541 igb_up(adapter); 5542 else 5543 igb_reset(adapter); 5544 5545 clear_bit(__IGB_RESETTING, &adapter->state); 5546 5547 return 0; 5548 } 5549 5550 /** 5551 * igb_update_stats - Update the board statistics counters 5552 * @adapter: board private structure 5553 **/ 5554 void igb_update_stats(struct igb_adapter *adapter) 5555 { 5556 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 5557 struct e1000_hw *hw = &adapter->hw; 5558 struct pci_dev *pdev = adapter->pdev; 5559 u32 reg, mpc; 5560 int i; 5561 u64 bytes, packets; 5562 unsigned int start; 5563 u64 _bytes, _packets; 5564 5565 /* Prevent stats update while adapter is being reset, or if the pci 5566 * connection is down. 5567 */ 5568 if (adapter->link_speed == 0) 5569 return; 5570 if (pci_channel_offline(pdev)) 5571 return; 5572 5573 bytes = 0; 5574 packets = 0; 5575 5576 rcu_read_lock(); 5577 for (i = 0; i < adapter->num_rx_queues; i++) { 5578 struct igb_ring *ring = adapter->rx_ring[i]; 5579 u32 rqdpc = rd32(E1000_RQDPC(i)); 5580 if (hw->mac.type >= e1000_i210) 5581 wr32(E1000_RQDPC(i), 0); 5582 5583 if (rqdpc) { 5584 ring->rx_stats.drops += rqdpc; 5585 net_stats->rx_fifo_errors += rqdpc; 5586 } 5587 5588 do { 5589 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 5590 _bytes = ring->rx_stats.bytes; 5591 _packets = ring->rx_stats.packets; 5592 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 5593 bytes += _bytes; 5594 packets += _packets; 5595 } 5596 5597 net_stats->rx_bytes = bytes; 5598 net_stats->rx_packets = packets; 5599 5600 bytes = 0; 5601 packets = 0; 5602 for (i = 0; i < adapter->num_tx_queues; i++) { 5603 struct igb_ring *ring = adapter->tx_ring[i]; 5604 do { 5605 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 5606 _bytes = ring->tx_stats.bytes; 5607 _packets = ring->tx_stats.packets; 5608 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 5609 bytes += _bytes; 5610 packets += _packets; 5611 } 5612 net_stats->tx_bytes = bytes; 5613 net_stats->tx_packets = packets; 5614 rcu_read_unlock(); 5615 5616 /* read stats registers */ 5617 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 5618 adapter->stats.gprc += rd32(E1000_GPRC); 5619 adapter->stats.gorc += rd32(E1000_GORCL); 5620 rd32(E1000_GORCH); /* clear GORCL */ 5621 adapter->stats.bprc += rd32(E1000_BPRC); 5622 adapter->stats.mprc += rd32(E1000_MPRC); 5623 adapter->stats.roc += rd32(E1000_ROC); 5624 5625 adapter->stats.prc64 += rd32(E1000_PRC64); 5626 adapter->stats.prc127 += rd32(E1000_PRC127); 5627 adapter->stats.prc255 += rd32(E1000_PRC255); 5628 adapter->stats.prc511 += rd32(E1000_PRC511); 5629 adapter->stats.prc1023 += rd32(E1000_PRC1023); 5630 adapter->stats.prc1522 += rd32(E1000_PRC1522); 5631 adapter->stats.symerrs += rd32(E1000_SYMERRS); 5632 adapter->stats.sec += rd32(E1000_SEC); 5633 5634 mpc = rd32(E1000_MPC); 5635 adapter->stats.mpc += mpc; 5636 net_stats->rx_fifo_errors += mpc; 5637 adapter->stats.scc += rd32(E1000_SCC); 5638 adapter->stats.ecol += rd32(E1000_ECOL); 5639 adapter->stats.mcc += rd32(E1000_MCC); 5640 adapter->stats.latecol += rd32(E1000_LATECOL); 5641 adapter->stats.dc += rd32(E1000_DC); 5642 adapter->stats.rlec += rd32(E1000_RLEC); 5643 adapter->stats.xonrxc += rd32(E1000_XONRXC); 5644 adapter->stats.xontxc += rd32(E1000_XONTXC); 5645 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 5646 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 5647 adapter->stats.fcruc += rd32(E1000_FCRUC); 5648 adapter->stats.gptc += rd32(E1000_GPTC); 5649 adapter->stats.gotc += rd32(E1000_GOTCL); 5650 rd32(E1000_GOTCH); /* clear GOTCL */ 5651 adapter->stats.rnbc += rd32(E1000_RNBC); 5652 adapter->stats.ruc += rd32(E1000_RUC); 5653 adapter->stats.rfc += rd32(E1000_RFC); 5654 adapter->stats.rjc += rd32(E1000_RJC); 5655 adapter->stats.tor += rd32(E1000_TORH); 5656 adapter->stats.tot += rd32(E1000_TOTH); 5657 adapter->stats.tpr += rd32(E1000_TPR); 5658 5659 adapter->stats.ptc64 += rd32(E1000_PTC64); 5660 adapter->stats.ptc127 += rd32(E1000_PTC127); 5661 adapter->stats.ptc255 += rd32(E1000_PTC255); 5662 adapter->stats.ptc511 += rd32(E1000_PTC511); 5663 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 5664 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 5665 5666 adapter->stats.mptc += rd32(E1000_MPTC); 5667 adapter->stats.bptc += rd32(E1000_BPTC); 5668 5669 adapter->stats.tpt += rd32(E1000_TPT); 5670 adapter->stats.colc += rd32(E1000_COLC); 5671 5672 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 5673 /* read internal phy specific stats */ 5674 reg = rd32(E1000_CTRL_EXT); 5675 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 5676 adapter->stats.rxerrc += rd32(E1000_RXERRC); 5677 5678 /* this stat has invalid values on i210/i211 */ 5679 if ((hw->mac.type != e1000_i210) && 5680 (hw->mac.type != e1000_i211)) 5681 adapter->stats.tncrs += rd32(E1000_TNCRS); 5682 } 5683 5684 adapter->stats.tsctc += rd32(E1000_TSCTC); 5685 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 5686 5687 adapter->stats.iac += rd32(E1000_IAC); 5688 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 5689 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 5690 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 5691 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 5692 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 5693 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 5694 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 5695 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 5696 5697 /* Fill out the OS statistics structure */ 5698 net_stats->multicast = adapter->stats.mprc; 5699 net_stats->collisions = adapter->stats.colc; 5700 5701 /* Rx Errors */ 5702 5703 /* RLEC on some newer hardware can be incorrect so build 5704 * our own version based on RUC and ROC 5705 */ 5706 net_stats->rx_errors = adapter->stats.rxerrc + 5707 adapter->stats.crcerrs + adapter->stats.algnerrc + 5708 adapter->stats.ruc + adapter->stats.roc + 5709 adapter->stats.cexterr; 5710 net_stats->rx_length_errors = adapter->stats.ruc + 5711 adapter->stats.roc; 5712 net_stats->rx_crc_errors = adapter->stats.crcerrs; 5713 net_stats->rx_frame_errors = adapter->stats.algnerrc; 5714 net_stats->rx_missed_errors = adapter->stats.mpc; 5715 5716 /* Tx Errors */ 5717 net_stats->tx_errors = adapter->stats.ecol + 5718 adapter->stats.latecol; 5719 net_stats->tx_aborted_errors = adapter->stats.ecol; 5720 net_stats->tx_window_errors = adapter->stats.latecol; 5721 net_stats->tx_carrier_errors = adapter->stats.tncrs; 5722 5723 /* Tx Dropped needs to be maintained elsewhere */ 5724 5725 /* Management Stats */ 5726 adapter->stats.mgptc += rd32(E1000_MGTPTC); 5727 adapter->stats.mgprc += rd32(E1000_MGTPRC); 5728 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 5729 5730 /* OS2BMC Stats */ 5731 reg = rd32(E1000_MANC); 5732 if (reg & E1000_MANC_EN_BMC2OS) { 5733 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 5734 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 5735 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 5736 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 5737 } 5738 } 5739 5740 static void igb_tsync_interrupt(struct igb_adapter *adapter) 5741 { 5742 struct e1000_hw *hw = &adapter->hw; 5743 struct ptp_clock_event event; 5744 struct timespec64 ts; 5745 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR); 5746 5747 if (tsicr & TSINTR_SYS_WRAP) { 5748 event.type = PTP_CLOCK_PPS; 5749 if (adapter->ptp_caps.pps) 5750 ptp_clock_event(adapter->ptp_clock, &event); 5751 ack |= TSINTR_SYS_WRAP; 5752 } 5753 5754 if (tsicr & E1000_TSICR_TXTS) { 5755 /* retrieve hardware timestamp */ 5756 schedule_work(&adapter->ptp_tx_work); 5757 ack |= E1000_TSICR_TXTS; 5758 } 5759 5760 if (tsicr & TSINTR_TT0) { 5761 spin_lock(&adapter->tmreg_lock); 5762 ts = timespec64_add(adapter->perout[0].start, 5763 adapter->perout[0].period); 5764 /* u32 conversion of tv_sec is safe until y2106 */ 5765 wr32(E1000_TRGTTIML0, ts.tv_nsec); 5766 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec); 5767 tsauxc = rd32(E1000_TSAUXC); 5768 tsauxc |= TSAUXC_EN_TT0; 5769 wr32(E1000_TSAUXC, tsauxc); 5770 adapter->perout[0].start = ts; 5771 spin_unlock(&adapter->tmreg_lock); 5772 ack |= TSINTR_TT0; 5773 } 5774 5775 if (tsicr & TSINTR_TT1) { 5776 spin_lock(&adapter->tmreg_lock); 5777 ts = timespec64_add(adapter->perout[1].start, 5778 adapter->perout[1].period); 5779 wr32(E1000_TRGTTIML1, ts.tv_nsec); 5780 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec); 5781 tsauxc = rd32(E1000_TSAUXC); 5782 tsauxc |= TSAUXC_EN_TT1; 5783 wr32(E1000_TSAUXC, tsauxc); 5784 adapter->perout[1].start = ts; 5785 spin_unlock(&adapter->tmreg_lock); 5786 ack |= TSINTR_TT1; 5787 } 5788 5789 if (tsicr & TSINTR_AUTT0) { 5790 nsec = rd32(E1000_AUXSTMPL0); 5791 sec = rd32(E1000_AUXSTMPH0); 5792 event.type = PTP_CLOCK_EXTTS; 5793 event.index = 0; 5794 event.timestamp = sec * 1000000000ULL + nsec; 5795 ptp_clock_event(adapter->ptp_clock, &event); 5796 ack |= TSINTR_AUTT0; 5797 } 5798 5799 if (tsicr & TSINTR_AUTT1) { 5800 nsec = rd32(E1000_AUXSTMPL1); 5801 sec = rd32(E1000_AUXSTMPH1); 5802 event.type = PTP_CLOCK_EXTTS; 5803 event.index = 1; 5804 event.timestamp = sec * 1000000000ULL + nsec; 5805 ptp_clock_event(adapter->ptp_clock, &event); 5806 ack |= TSINTR_AUTT1; 5807 } 5808 5809 /* acknowledge the interrupts */ 5810 wr32(E1000_TSICR, ack); 5811 } 5812 5813 static irqreturn_t igb_msix_other(int irq, void *data) 5814 { 5815 struct igb_adapter *adapter = data; 5816 struct e1000_hw *hw = &adapter->hw; 5817 u32 icr = rd32(E1000_ICR); 5818 /* reading ICR causes bit 31 of EICR to be cleared */ 5819 5820 if (icr & E1000_ICR_DRSTA) 5821 schedule_work(&adapter->reset_task); 5822 5823 if (icr & E1000_ICR_DOUTSYNC) { 5824 /* HW is reporting DMA is out of sync */ 5825 adapter->stats.doosync++; 5826 /* The DMA Out of Sync is also indication of a spoof event 5827 * in IOV mode. Check the Wrong VM Behavior register to 5828 * see if it is really a spoof event. 5829 */ 5830 igb_check_wvbr(adapter); 5831 } 5832 5833 /* Check for a mailbox event */ 5834 if (icr & E1000_ICR_VMMB) 5835 igb_msg_task(adapter); 5836 5837 if (icr & E1000_ICR_LSC) { 5838 hw->mac.get_link_status = 1; 5839 /* guard against interrupt when we're going down */ 5840 if (!test_bit(__IGB_DOWN, &adapter->state)) 5841 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5842 } 5843 5844 if (icr & E1000_ICR_TS) 5845 igb_tsync_interrupt(adapter); 5846 5847 wr32(E1000_EIMS, adapter->eims_other); 5848 5849 return IRQ_HANDLED; 5850 } 5851 5852 static void igb_write_itr(struct igb_q_vector *q_vector) 5853 { 5854 struct igb_adapter *adapter = q_vector->adapter; 5855 u32 itr_val = q_vector->itr_val & 0x7FFC; 5856 5857 if (!q_vector->set_itr) 5858 return; 5859 5860 if (!itr_val) 5861 itr_val = 0x4; 5862 5863 if (adapter->hw.mac.type == e1000_82575) 5864 itr_val |= itr_val << 16; 5865 else 5866 itr_val |= E1000_EITR_CNT_IGNR; 5867 5868 writel(itr_val, q_vector->itr_register); 5869 q_vector->set_itr = 0; 5870 } 5871 5872 static irqreturn_t igb_msix_ring(int irq, void *data) 5873 { 5874 struct igb_q_vector *q_vector = data; 5875 5876 /* Write the ITR value calculated from the previous interrupt. */ 5877 igb_write_itr(q_vector); 5878 5879 napi_schedule(&q_vector->napi); 5880 5881 return IRQ_HANDLED; 5882 } 5883 5884 #ifdef CONFIG_IGB_DCA 5885 static void igb_update_tx_dca(struct igb_adapter *adapter, 5886 struct igb_ring *tx_ring, 5887 int cpu) 5888 { 5889 struct e1000_hw *hw = &adapter->hw; 5890 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 5891 5892 if (hw->mac.type != e1000_82575) 5893 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 5894 5895 /* We can enable relaxed ordering for reads, but not writes when 5896 * DCA is enabled. This is due to a known issue in some chipsets 5897 * which will cause the DCA tag to be cleared. 5898 */ 5899 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 5900 E1000_DCA_TXCTRL_DATA_RRO_EN | 5901 E1000_DCA_TXCTRL_DESC_DCA_EN; 5902 5903 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 5904 } 5905 5906 static void igb_update_rx_dca(struct igb_adapter *adapter, 5907 struct igb_ring *rx_ring, 5908 int cpu) 5909 { 5910 struct e1000_hw *hw = &adapter->hw; 5911 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 5912 5913 if (hw->mac.type != e1000_82575) 5914 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 5915 5916 /* We can enable relaxed ordering for reads, but not writes when 5917 * DCA is enabled. This is due to a known issue in some chipsets 5918 * which will cause the DCA tag to be cleared. 5919 */ 5920 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 5921 E1000_DCA_RXCTRL_DESC_DCA_EN; 5922 5923 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 5924 } 5925 5926 static void igb_update_dca(struct igb_q_vector *q_vector) 5927 { 5928 struct igb_adapter *adapter = q_vector->adapter; 5929 int cpu = get_cpu(); 5930 5931 if (q_vector->cpu == cpu) 5932 goto out_no_update; 5933 5934 if (q_vector->tx.ring) 5935 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 5936 5937 if (q_vector->rx.ring) 5938 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 5939 5940 q_vector->cpu = cpu; 5941 out_no_update: 5942 put_cpu(); 5943 } 5944 5945 static void igb_setup_dca(struct igb_adapter *adapter) 5946 { 5947 struct e1000_hw *hw = &adapter->hw; 5948 int i; 5949 5950 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 5951 return; 5952 5953 /* Always use CB2 mode, difference is masked in the CB driver. */ 5954 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 5955 5956 for (i = 0; i < adapter->num_q_vectors; i++) { 5957 adapter->q_vector[i]->cpu = -1; 5958 igb_update_dca(adapter->q_vector[i]); 5959 } 5960 } 5961 5962 static int __igb_notify_dca(struct device *dev, void *data) 5963 { 5964 struct net_device *netdev = dev_get_drvdata(dev); 5965 struct igb_adapter *adapter = netdev_priv(netdev); 5966 struct pci_dev *pdev = adapter->pdev; 5967 struct e1000_hw *hw = &adapter->hw; 5968 unsigned long event = *(unsigned long *)data; 5969 5970 switch (event) { 5971 case DCA_PROVIDER_ADD: 5972 /* if already enabled, don't do it again */ 5973 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 5974 break; 5975 if (dca_add_requester(dev) == 0) { 5976 adapter->flags |= IGB_FLAG_DCA_ENABLED; 5977 dev_info(&pdev->dev, "DCA enabled\n"); 5978 igb_setup_dca(adapter); 5979 break; 5980 } 5981 /* Fall Through since DCA is disabled. */ 5982 case DCA_PROVIDER_REMOVE: 5983 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 5984 /* without this a class_device is left 5985 * hanging around in the sysfs model 5986 */ 5987 dca_remove_requester(dev); 5988 dev_info(&pdev->dev, "DCA disabled\n"); 5989 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 5990 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 5991 } 5992 break; 5993 } 5994 5995 return 0; 5996 } 5997 5998 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 5999 void *p) 6000 { 6001 int ret_val; 6002 6003 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 6004 __igb_notify_dca); 6005 6006 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 6007 } 6008 #endif /* CONFIG_IGB_DCA */ 6009 6010 #ifdef CONFIG_PCI_IOV 6011 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 6012 { 6013 unsigned char mac_addr[ETH_ALEN]; 6014 6015 eth_zero_addr(mac_addr); 6016 igb_set_vf_mac(adapter, vf, mac_addr); 6017 6018 /* By default spoof check is enabled for all VFs */ 6019 adapter->vf_data[vf].spoofchk_enabled = true; 6020 6021 return 0; 6022 } 6023 6024 #endif 6025 static void igb_ping_all_vfs(struct igb_adapter *adapter) 6026 { 6027 struct e1000_hw *hw = &adapter->hw; 6028 u32 ping; 6029 int i; 6030 6031 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 6032 ping = E1000_PF_CONTROL_MSG; 6033 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 6034 ping |= E1000_VT_MSGTYPE_CTS; 6035 igb_write_mbx(hw, &ping, 1, i); 6036 } 6037 } 6038 6039 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 6040 { 6041 struct e1000_hw *hw = &adapter->hw; 6042 u32 vmolr = rd32(E1000_VMOLR(vf)); 6043 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6044 6045 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 6046 IGB_VF_FLAG_MULTI_PROMISC); 6047 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 6048 6049 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 6050 vmolr |= E1000_VMOLR_MPME; 6051 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 6052 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 6053 } else { 6054 /* if we have hashes and we are clearing a multicast promisc 6055 * flag we need to write the hashes to the MTA as this step 6056 * was previously skipped 6057 */ 6058 if (vf_data->num_vf_mc_hashes > 30) { 6059 vmolr |= E1000_VMOLR_MPME; 6060 } else if (vf_data->num_vf_mc_hashes) { 6061 int j; 6062 6063 vmolr |= E1000_VMOLR_ROMPE; 6064 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 6065 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 6066 } 6067 } 6068 6069 wr32(E1000_VMOLR(vf), vmolr); 6070 6071 /* there are flags left unprocessed, likely not supported */ 6072 if (*msgbuf & E1000_VT_MSGINFO_MASK) 6073 return -EINVAL; 6074 6075 return 0; 6076 } 6077 6078 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 6079 u32 *msgbuf, u32 vf) 6080 { 6081 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 6082 u16 *hash_list = (u16 *)&msgbuf[1]; 6083 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6084 int i; 6085 6086 /* salt away the number of multicast addresses assigned 6087 * to this VF for later use to restore when the PF multi cast 6088 * list changes 6089 */ 6090 vf_data->num_vf_mc_hashes = n; 6091 6092 /* only up to 30 hash values supported */ 6093 if (n > 30) 6094 n = 30; 6095 6096 /* store the hashes for later use */ 6097 for (i = 0; i < n; i++) 6098 vf_data->vf_mc_hashes[i] = hash_list[i]; 6099 6100 /* Flush and reset the mta with the new values */ 6101 igb_set_rx_mode(adapter->netdev); 6102 6103 return 0; 6104 } 6105 6106 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 6107 { 6108 struct e1000_hw *hw = &adapter->hw; 6109 struct vf_data_storage *vf_data; 6110 int i, j; 6111 6112 for (i = 0; i < adapter->vfs_allocated_count; i++) { 6113 u32 vmolr = rd32(E1000_VMOLR(i)); 6114 6115 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 6116 6117 vf_data = &adapter->vf_data[i]; 6118 6119 if ((vf_data->num_vf_mc_hashes > 30) || 6120 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 6121 vmolr |= E1000_VMOLR_MPME; 6122 } else if (vf_data->num_vf_mc_hashes) { 6123 vmolr |= E1000_VMOLR_ROMPE; 6124 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 6125 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 6126 } 6127 wr32(E1000_VMOLR(i), vmolr); 6128 } 6129 } 6130 6131 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 6132 { 6133 struct e1000_hw *hw = &adapter->hw; 6134 u32 pool_mask, vlvf_mask, i; 6135 6136 /* create mask for VF and other pools */ 6137 pool_mask = E1000_VLVF_POOLSEL_MASK; 6138 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 6139 6140 /* drop PF from pool bits */ 6141 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 6142 adapter->vfs_allocated_count); 6143 6144 /* Find the vlan filter for this id */ 6145 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 6146 u32 vlvf = rd32(E1000_VLVF(i)); 6147 u32 vfta_mask, vid, vfta; 6148 6149 /* remove the vf from the pool */ 6150 if (!(vlvf & vlvf_mask)) 6151 continue; 6152 6153 /* clear out bit from VLVF */ 6154 vlvf ^= vlvf_mask; 6155 6156 /* if other pools are present, just remove ourselves */ 6157 if (vlvf & pool_mask) 6158 goto update_vlvfb; 6159 6160 /* if PF is present, leave VFTA */ 6161 if (vlvf & E1000_VLVF_POOLSEL_MASK) 6162 goto update_vlvf; 6163 6164 vid = vlvf & E1000_VLVF_VLANID_MASK; 6165 vfta_mask = BIT(vid % 32); 6166 6167 /* clear bit from VFTA */ 6168 vfta = adapter->shadow_vfta[vid / 32]; 6169 if (vfta & vfta_mask) 6170 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 6171 update_vlvf: 6172 /* clear pool selection enable */ 6173 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6174 vlvf &= E1000_VLVF_POOLSEL_MASK; 6175 else 6176 vlvf = 0; 6177 update_vlvfb: 6178 /* clear pool bits */ 6179 wr32(E1000_VLVF(i), vlvf); 6180 } 6181 } 6182 6183 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 6184 { 6185 u32 vlvf; 6186 int idx; 6187 6188 /* short cut the special case */ 6189 if (vlan == 0) 6190 return 0; 6191 6192 /* Search for the VLAN id in the VLVF entries */ 6193 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 6194 vlvf = rd32(E1000_VLVF(idx)); 6195 if ((vlvf & VLAN_VID_MASK) == vlan) 6196 break; 6197 } 6198 6199 return idx; 6200 } 6201 6202 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 6203 { 6204 struct e1000_hw *hw = &adapter->hw; 6205 u32 bits, pf_id; 6206 int idx; 6207 6208 idx = igb_find_vlvf_entry(hw, vid); 6209 if (!idx) 6210 return; 6211 6212 /* See if any other pools are set for this VLAN filter 6213 * entry other than the PF. 6214 */ 6215 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 6216 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 6217 bits &= rd32(E1000_VLVF(idx)); 6218 6219 /* Disable the filter so this falls into the default pool. */ 6220 if (!bits) { 6221 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6222 wr32(E1000_VLVF(idx), BIT(pf_id)); 6223 else 6224 wr32(E1000_VLVF(idx), 0); 6225 } 6226 } 6227 6228 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 6229 bool add, u32 vf) 6230 { 6231 int pf_id = adapter->vfs_allocated_count; 6232 struct e1000_hw *hw = &adapter->hw; 6233 int err; 6234 6235 /* If VLAN overlaps with one the PF is currently monitoring make 6236 * sure that we are able to allocate a VLVF entry. This may be 6237 * redundant but it guarantees PF will maintain visibility to 6238 * the VLAN. 6239 */ 6240 if (add && test_bit(vid, adapter->active_vlans)) { 6241 err = igb_vfta_set(hw, vid, pf_id, true, false); 6242 if (err) 6243 return err; 6244 } 6245 6246 err = igb_vfta_set(hw, vid, vf, add, false); 6247 6248 if (add && !err) 6249 return err; 6250 6251 /* If we failed to add the VF VLAN or we are removing the VF VLAN 6252 * we may need to drop the PF pool bit in order to allow us to free 6253 * up the VLVF resources. 6254 */ 6255 if (test_bit(vid, adapter->active_vlans) || 6256 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 6257 igb_update_pf_vlvf(adapter, vid); 6258 6259 return err; 6260 } 6261 6262 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 6263 { 6264 struct e1000_hw *hw = &adapter->hw; 6265 6266 if (vid) 6267 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 6268 else 6269 wr32(E1000_VMVIR(vf), 0); 6270 } 6271 6272 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 6273 u16 vlan, u8 qos) 6274 { 6275 int err; 6276 6277 err = igb_set_vf_vlan(adapter, vlan, true, vf); 6278 if (err) 6279 return err; 6280 6281 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 6282 igb_set_vmolr(adapter, vf, !vlan); 6283 6284 /* revoke access to previous VLAN */ 6285 if (vlan != adapter->vf_data[vf].pf_vlan) 6286 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 6287 false, vf); 6288 6289 adapter->vf_data[vf].pf_vlan = vlan; 6290 adapter->vf_data[vf].pf_qos = qos; 6291 igb_set_vf_vlan_strip(adapter, vf, true); 6292 dev_info(&adapter->pdev->dev, 6293 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 6294 if (test_bit(__IGB_DOWN, &adapter->state)) { 6295 dev_warn(&adapter->pdev->dev, 6296 "The VF VLAN has been set, but the PF device is not up.\n"); 6297 dev_warn(&adapter->pdev->dev, 6298 "Bring the PF device up before attempting to use the VF device.\n"); 6299 } 6300 6301 return err; 6302 } 6303 6304 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 6305 { 6306 /* Restore tagless access via VLAN 0 */ 6307 igb_set_vf_vlan(adapter, 0, true, vf); 6308 6309 igb_set_vmvir(adapter, 0, vf); 6310 igb_set_vmolr(adapter, vf, true); 6311 6312 /* Remove any PF assigned VLAN */ 6313 if (adapter->vf_data[vf].pf_vlan) 6314 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 6315 false, vf); 6316 6317 adapter->vf_data[vf].pf_vlan = 0; 6318 adapter->vf_data[vf].pf_qos = 0; 6319 igb_set_vf_vlan_strip(adapter, vf, false); 6320 6321 return 0; 6322 } 6323 6324 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 6325 u16 vlan, u8 qos, __be16 vlan_proto) 6326 { 6327 struct igb_adapter *adapter = netdev_priv(netdev); 6328 6329 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 6330 return -EINVAL; 6331 6332 if (vlan_proto != htons(ETH_P_8021Q)) 6333 return -EPROTONOSUPPORT; 6334 6335 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 6336 igb_disable_port_vlan(adapter, vf); 6337 } 6338 6339 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 6340 { 6341 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 6342 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 6343 int ret; 6344 6345 if (adapter->vf_data[vf].pf_vlan) 6346 return -1; 6347 6348 /* VLAN 0 is a special case, don't allow it to be removed */ 6349 if (!vid && !add) 6350 return 0; 6351 6352 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 6353 if (!ret) 6354 igb_set_vf_vlan_strip(adapter, vf, !!vid); 6355 return ret; 6356 } 6357 6358 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 6359 { 6360 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6361 6362 /* clear flags - except flag that indicates PF has set the MAC */ 6363 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 6364 vf_data->last_nack = jiffies; 6365 6366 /* reset vlans for device */ 6367 igb_clear_vf_vfta(adapter, vf); 6368 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 6369 igb_set_vmvir(adapter, vf_data->pf_vlan | 6370 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 6371 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 6372 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 6373 6374 /* reset multicast table array for vf */ 6375 adapter->vf_data[vf].num_vf_mc_hashes = 0; 6376 6377 /* Flush and reset the mta with the new values */ 6378 igb_set_rx_mode(adapter->netdev); 6379 } 6380 6381 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 6382 { 6383 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 6384 6385 /* clear mac address as we were hotplug removed/added */ 6386 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 6387 eth_zero_addr(vf_mac); 6388 6389 /* process remaining reset events */ 6390 igb_vf_reset(adapter, vf); 6391 } 6392 6393 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 6394 { 6395 struct e1000_hw *hw = &adapter->hw; 6396 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 6397 u32 reg, msgbuf[3]; 6398 u8 *addr = (u8 *)(&msgbuf[1]); 6399 6400 /* process all the same items cleared in a function level reset */ 6401 igb_vf_reset(adapter, vf); 6402 6403 /* set vf mac address */ 6404 igb_set_vf_mac(adapter, vf, vf_mac); 6405 6406 /* enable transmit and receive for vf */ 6407 reg = rd32(E1000_VFTE); 6408 wr32(E1000_VFTE, reg | BIT(vf)); 6409 reg = rd32(E1000_VFRE); 6410 wr32(E1000_VFRE, reg | BIT(vf)); 6411 6412 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 6413 6414 /* reply to reset with ack and vf mac address */ 6415 if (!is_zero_ether_addr(vf_mac)) { 6416 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 6417 memcpy(addr, vf_mac, ETH_ALEN); 6418 } else { 6419 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 6420 } 6421 igb_write_mbx(hw, msgbuf, 3, vf); 6422 } 6423 6424 static void igb_flush_mac_table(struct igb_adapter *adapter) 6425 { 6426 struct e1000_hw *hw = &adapter->hw; 6427 int i; 6428 6429 for (i = 0; i < hw->mac.rar_entry_count; i++) { 6430 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 6431 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 6432 adapter->mac_table[i].queue = 0; 6433 igb_rar_set_index(adapter, i); 6434 } 6435 } 6436 6437 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 6438 { 6439 struct e1000_hw *hw = &adapter->hw; 6440 /* do not count rar entries reserved for VFs MAC addresses */ 6441 int rar_entries = hw->mac.rar_entry_count - 6442 adapter->vfs_allocated_count; 6443 int i, count = 0; 6444 6445 for (i = 0; i < rar_entries; i++) { 6446 /* do not count default entries */ 6447 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 6448 continue; 6449 6450 /* do not count "in use" entries for different queues */ 6451 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 6452 (adapter->mac_table[i].queue != queue)) 6453 continue; 6454 6455 count++; 6456 } 6457 6458 return count; 6459 } 6460 6461 /* Set default MAC address for the PF in the first RAR entry */ 6462 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 6463 { 6464 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 6465 6466 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 6467 mac_table->queue = adapter->vfs_allocated_count; 6468 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 6469 6470 igb_rar_set_index(adapter, 0); 6471 } 6472 6473 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 6474 const u8 queue) 6475 { 6476 struct e1000_hw *hw = &adapter->hw; 6477 int rar_entries = hw->mac.rar_entry_count - 6478 adapter->vfs_allocated_count; 6479 int i; 6480 6481 if (is_zero_ether_addr(addr)) 6482 return -EINVAL; 6483 6484 /* Search for the first empty entry in the MAC table. 6485 * Do not touch entries at the end of the table reserved for the VF MAC 6486 * addresses. 6487 */ 6488 for (i = 0; i < rar_entries; i++) { 6489 if (adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) 6490 continue; 6491 6492 ether_addr_copy(adapter->mac_table[i].addr, addr); 6493 adapter->mac_table[i].queue = queue; 6494 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE; 6495 6496 igb_rar_set_index(adapter, i); 6497 return i; 6498 } 6499 6500 return -ENOSPC; 6501 } 6502 6503 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 6504 const u8 queue) 6505 { 6506 struct e1000_hw *hw = &adapter->hw; 6507 int rar_entries = hw->mac.rar_entry_count - 6508 adapter->vfs_allocated_count; 6509 int i; 6510 6511 if (is_zero_ether_addr(addr)) 6512 return -EINVAL; 6513 6514 /* Search for matching entry in the MAC table based on given address 6515 * and queue. Do not touch entries at the end of the table reserved 6516 * for the VF MAC addresses. 6517 */ 6518 for (i = 0; i < rar_entries; i++) { 6519 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 6520 continue; 6521 if (adapter->mac_table[i].queue != queue) 6522 continue; 6523 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 6524 continue; 6525 6526 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 6527 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 6528 adapter->mac_table[i].queue = 0; 6529 6530 igb_rar_set_index(adapter, i); 6531 return 0; 6532 } 6533 6534 return -ENOENT; 6535 } 6536 6537 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 6538 { 6539 struct igb_adapter *adapter = netdev_priv(netdev); 6540 int ret; 6541 6542 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 6543 6544 return min_t(int, ret, 0); 6545 } 6546 6547 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 6548 { 6549 struct igb_adapter *adapter = netdev_priv(netdev); 6550 6551 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 6552 6553 return 0; 6554 } 6555 6556 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 6557 const u32 info, const u8 *addr) 6558 { 6559 struct pci_dev *pdev = adapter->pdev; 6560 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6561 struct list_head *pos; 6562 struct vf_mac_filter *entry = NULL; 6563 int ret = 0; 6564 6565 switch (info) { 6566 case E1000_VF_MAC_FILTER_CLR: 6567 /* remove all unicast MAC filters related to the current VF */ 6568 list_for_each(pos, &adapter->vf_macs.l) { 6569 entry = list_entry(pos, struct vf_mac_filter, l); 6570 if (entry->vf == vf) { 6571 entry->vf = -1; 6572 entry->free = true; 6573 igb_del_mac_filter(adapter, entry->vf_mac, vf); 6574 } 6575 } 6576 break; 6577 case E1000_VF_MAC_FILTER_ADD: 6578 if (vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) { 6579 dev_warn(&pdev->dev, 6580 "VF %d requested MAC filter but is administratively denied\n", 6581 vf); 6582 return -EINVAL; 6583 } 6584 6585 if (!is_valid_ether_addr(addr)) { 6586 dev_warn(&pdev->dev, 6587 "VF %d attempted to set invalid MAC filter\n", 6588 vf); 6589 return -EINVAL; 6590 } 6591 6592 /* try to find empty slot in the list */ 6593 list_for_each(pos, &adapter->vf_macs.l) { 6594 entry = list_entry(pos, struct vf_mac_filter, l); 6595 if (entry->free) 6596 break; 6597 } 6598 6599 if (entry && entry->free) { 6600 entry->free = false; 6601 entry->vf = vf; 6602 ether_addr_copy(entry->vf_mac, addr); 6603 6604 ret = igb_add_mac_filter(adapter, addr, vf); 6605 ret = min_t(int, ret, 0); 6606 } else { 6607 ret = -ENOSPC; 6608 } 6609 6610 if (ret == -ENOSPC) 6611 dev_warn(&pdev->dev, 6612 "VF %d has requested MAC filter but there is no space for it\n", 6613 vf); 6614 break; 6615 default: 6616 ret = -EINVAL; 6617 break; 6618 } 6619 6620 return ret; 6621 } 6622 6623 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 6624 { 6625 struct pci_dev *pdev = adapter->pdev; 6626 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6627 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 6628 6629 /* The VF MAC Address is stored in a packed array of bytes 6630 * starting at the second 32 bit word of the msg array 6631 */ 6632 unsigned char *addr = (unsigned char *)&msg[1]; 6633 int ret = 0; 6634 6635 if (!info) { 6636 if (vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) { 6637 dev_warn(&pdev->dev, 6638 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 6639 vf); 6640 return -EINVAL; 6641 } 6642 6643 if (!is_valid_ether_addr(addr)) { 6644 dev_warn(&pdev->dev, 6645 "VF %d attempted to set invalid MAC\n", 6646 vf); 6647 return -EINVAL; 6648 } 6649 6650 ret = igb_set_vf_mac(adapter, vf, addr); 6651 } else { 6652 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 6653 } 6654 6655 return ret; 6656 } 6657 6658 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 6659 { 6660 struct e1000_hw *hw = &adapter->hw; 6661 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6662 u32 msg = E1000_VT_MSGTYPE_NACK; 6663 6664 /* if device isn't clear to send it shouldn't be reading either */ 6665 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 6666 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 6667 igb_write_mbx(hw, &msg, 1, vf); 6668 vf_data->last_nack = jiffies; 6669 } 6670 } 6671 6672 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 6673 { 6674 struct pci_dev *pdev = adapter->pdev; 6675 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 6676 struct e1000_hw *hw = &adapter->hw; 6677 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6678 s32 retval; 6679 6680 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 6681 6682 if (retval) { 6683 /* if receive failed revoke VF CTS stats and restart init */ 6684 dev_err(&pdev->dev, "Error receiving message from VF\n"); 6685 vf_data->flags &= ~IGB_VF_FLAG_CTS; 6686 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6687 goto unlock; 6688 goto out; 6689 } 6690 6691 /* this is a message we already processed, do nothing */ 6692 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 6693 goto unlock; 6694 6695 /* until the vf completes a reset it should not be 6696 * allowed to start any configuration. 6697 */ 6698 if (msgbuf[0] == E1000_VF_RESET) { 6699 /* unlocks mailbox */ 6700 igb_vf_reset_msg(adapter, vf); 6701 return; 6702 } 6703 6704 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 6705 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6706 goto unlock; 6707 retval = -1; 6708 goto out; 6709 } 6710 6711 switch ((msgbuf[0] & 0xFFFF)) { 6712 case E1000_VF_SET_MAC_ADDR: 6713 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 6714 break; 6715 case E1000_VF_SET_PROMISC: 6716 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 6717 break; 6718 case E1000_VF_SET_MULTICAST: 6719 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 6720 break; 6721 case E1000_VF_SET_LPE: 6722 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 6723 break; 6724 case E1000_VF_SET_VLAN: 6725 retval = -1; 6726 if (vf_data->pf_vlan) 6727 dev_warn(&pdev->dev, 6728 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 6729 vf); 6730 else 6731 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 6732 break; 6733 default: 6734 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 6735 retval = -1; 6736 break; 6737 } 6738 6739 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 6740 out: 6741 /* notify the VF of the results of what it sent us */ 6742 if (retval) 6743 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 6744 else 6745 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 6746 6747 /* unlocks mailbox */ 6748 igb_write_mbx(hw, msgbuf, 1, vf); 6749 return; 6750 6751 unlock: 6752 igb_unlock_mbx(hw, vf); 6753 } 6754 6755 static void igb_msg_task(struct igb_adapter *adapter) 6756 { 6757 struct e1000_hw *hw = &adapter->hw; 6758 u32 vf; 6759 6760 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 6761 /* process any reset requests */ 6762 if (!igb_check_for_rst(hw, vf)) 6763 igb_vf_reset_event(adapter, vf); 6764 6765 /* process any messages pending */ 6766 if (!igb_check_for_msg(hw, vf)) 6767 igb_rcv_msg_from_vf(adapter, vf); 6768 6769 /* process any acks */ 6770 if (!igb_check_for_ack(hw, vf)) 6771 igb_rcv_ack_from_vf(adapter, vf); 6772 } 6773 } 6774 6775 /** 6776 * igb_set_uta - Set unicast filter table address 6777 * @adapter: board private structure 6778 * @set: boolean indicating if we are setting or clearing bits 6779 * 6780 * The unicast table address is a register array of 32-bit registers. 6781 * The table is meant to be used in a way similar to how the MTA is used 6782 * however due to certain limitations in the hardware it is necessary to 6783 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 6784 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 6785 **/ 6786 static void igb_set_uta(struct igb_adapter *adapter, bool set) 6787 { 6788 struct e1000_hw *hw = &adapter->hw; 6789 u32 uta = set ? ~0 : 0; 6790 int i; 6791 6792 /* we only need to do this if VMDq is enabled */ 6793 if (!adapter->vfs_allocated_count) 6794 return; 6795 6796 for (i = hw->mac.uta_reg_count; i--;) 6797 array_wr32(E1000_UTA, i, uta); 6798 } 6799 6800 /** 6801 * igb_intr_msi - Interrupt Handler 6802 * @irq: interrupt number 6803 * @data: pointer to a network interface device structure 6804 **/ 6805 static irqreturn_t igb_intr_msi(int irq, void *data) 6806 { 6807 struct igb_adapter *adapter = data; 6808 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6809 struct e1000_hw *hw = &adapter->hw; 6810 /* read ICR disables interrupts using IAM */ 6811 u32 icr = rd32(E1000_ICR); 6812 6813 igb_write_itr(q_vector); 6814 6815 if (icr & E1000_ICR_DRSTA) 6816 schedule_work(&adapter->reset_task); 6817 6818 if (icr & E1000_ICR_DOUTSYNC) { 6819 /* HW is reporting DMA is out of sync */ 6820 adapter->stats.doosync++; 6821 } 6822 6823 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6824 hw->mac.get_link_status = 1; 6825 if (!test_bit(__IGB_DOWN, &adapter->state)) 6826 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6827 } 6828 6829 if (icr & E1000_ICR_TS) 6830 igb_tsync_interrupt(adapter); 6831 6832 napi_schedule(&q_vector->napi); 6833 6834 return IRQ_HANDLED; 6835 } 6836 6837 /** 6838 * igb_intr - Legacy Interrupt Handler 6839 * @irq: interrupt number 6840 * @data: pointer to a network interface device structure 6841 **/ 6842 static irqreturn_t igb_intr(int irq, void *data) 6843 { 6844 struct igb_adapter *adapter = data; 6845 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6846 struct e1000_hw *hw = &adapter->hw; 6847 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 6848 * need for the IMC write 6849 */ 6850 u32 icr = rd32(E1000_ICR); 6851 6852 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 6853 * not set, then the adapter didn't send an interrupt 6854 */ 6855 if (!(icr & E1000_ICR_INT_ASSERTED)) 6856 return IRQ_NONE; 6857 6858 igb_write_itr(q_vector); 6859 6860 if (icr & E1000_ICR_DRSTA) 6861 schedule_work(&adapter->reset_task); 6862 6863 if (icr & E1000_ICR_DOUTSYNC) { 6864 /* HW is reporting DMA is out of sync */ 6865 adapter->stats.doosync++; 6866 } 6867 6868 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6869 hw->mac.get_link_status = 1; 6870 /* guard against interrupt when we're going down */ 6871 if (!test_bit(__IGB_DOWN, &adapter->state)) 6872 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6873 } 6874 6875 if (icr & E1000_ICR_TS) 6876 igb_tsync_interrupt(adapter); 6877 6878 napi_schedule(&q_vector->napi); 6879 6880 return IRQ_HANDLED; 6881 } 6882 6883 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 6884 { 6885 struct igb_adapter *adapter = q_vector->adapter; 6886 struct e1000_hw *hw = &adapter->hw; 6887 6888 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 6889 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 6890 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 6891 igb_set_itr(q_vector); 6892 else 6893 igb_update_ring_itr(q_vector); 6894 } 6895 6896 if (!test_bit(__IGB_DOWN, &adapter->state)) { 6897 if (adapter->flags & IGB_FLAG_HAS_MSIX) 6898 wr32(E1000_EIMS, q_vector->eims_value); 6899 else 6900 igb_irq_enable(adapter); 6901 } 6902 } 6903 6904 /** 6905 * igb_poll - NAPI Rx polling callback 6906 * @napi: napi polling structure 6907 * @budget: count of how many packets we should handle 6908 **/ 6909 static int igb_poll(struct napi_struct *napi, int budget) 6910 { 6911 struct igb_q_vector *q_vector = container_of(napi, 6912 struct igb_q_vector, 6913 napi); 6914 bool clean_complete = true; 6915 int work_done = 0; 6916 6917 #ifdef CONFIG_IGB_DCA 6918 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 6919 igb_update_dca(q_vector); 6920 #endif 6921 if (q_vector->tx.ring) 6922 clean_complete = igb_clean_tx_irq(q_vector, budget); 6923 6924 if (q_vector->rx.ring) { 6925 int cleaned = igb_clean_rx_irq(q_vector, budget); 6926 6927 work_done += cleaned; 6928 if (cleaned >= budget) 6929 clean_complete = false; 6930 } 6931 6932 /* If all work not completed, return budget and keep polling */ 6933 if (!clean_complete) 6934 return budget; 6935 6936 /* If not enough Rx work done, exit the polling mode */ 6937 napi_complete_done(napi, work_done); 6938 igb_ring_irq_enable(q_vector); 6939 6940 return 0; 6941 } 6942 6943 /** 6944 * igb_clean_tx_irq - Reclaim resources after transmit completes 6945 * @q_vector: pointer to q_vector containing needed info 6946 * @napi_budget: Used to determine if we are in netpoll 6947 * 6948 * returns true if ring is completely cleaned 6949 **/ 6950 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 6951 { 6952 struct igb_adapter *adapter = q_vector->adapter; 6953 struct igb_ring *tx_ring = q_vector->tx.ring; 6954 struct igb_tx_buffer *tx_buffer; 6955 union e1000_adv_tx_desc *tx_desc; 6956 unsigned int total_bytes = 0, total_packets = 0; 6957 unsigned int budget = q_vector->tx.work_limit; 6958 unsigned int i = tx_ring->next_to_clean; 6959 6960 if (test_bit(__IGB_DOWN, &adapter->state)) 6961 return true; 6962 6963 tx_buffer = &tx_ring->tx_buffer_info[i]; 6964 tx_desc = IGB_TX_DESC(tx_ring, i); 6965 i -= tx_ring->count; 6966 6967 do { 6968 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 6969 6970 /* if next_to_watch is not set then there is no work pending */ 6971 if (!eop_desc) 6972 break; 6973 6974 /* prevent any other reads prior to eop_desc */ 6975 read_barrier_depends(); 6976 6977 /* if DD is not set pending work has not been completed */ 6978 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 6979 break; 6980 6981 /* clear next_to_watch to prevent false hangs */ 6982 tx_buffer->next_to_watch = NULL; 6983 6984 /* update the statistics for this packet */ 6985 total_bytes += tx_buffer->bytecount; 6986 total_packets += tx_buffer->gso_segs; 6987 6988 /* free the skb */ 6989 napi_consume_skb(tx_buffer->skb, napi_budget); 6990 6991 /* unmap skb header data */ 6992 dma_unmap_single(tx_ring->dev, 6993 dma_unmap_addr(tx_buffer, dma), 6994 dma_unmap_len(tx_buffer, len), 6995 DMA_TO_DEVICE); 6996 6997 /* clear tx_buffer data */ 6998 dma_unmap_len_set(tx_buffer, len, 0); 6999 7000 /* clear last DMA location and unmap remaining buffers */ 7001 while (tx_desc != eop_desc) { 7002 tx_buffer++; 7003 tx_desc++; 7004 i++; 7005 if (unlikely(!i)) { 7006 i -= tx_ring->count; 7007 tx_buffer = tx_ring->tx_buffer_info; 7008 tx_desc = IGB_TX_DESC(tx_ring, 0); 7009 } 7010 7011 /* unmap any remaining paged data */ 7012 if (dma_unmap_len(tx_buffer, len)) { 7013 dma_unmap_page(tx_ring->dev, 7014 dma_unmap_addr(tx_buffer, dma), 7015 dma_unmap_len(tx_buffer, len), 7016 DMA_TO_DEVICE); 7017 dma_unmap_len_set(tx_buffer, len, 0); 7018 } 7019 } 7020 7021 /* move us one more past the eop_desc for start of next pkt */ 7022 tx_buffer++; 7023 tx_desc++; 7024 i++; 7025 if (unlikely(!i)) { 7026 i -= tx_ring->count; 7027 tx_buffer = tx_ring->tx_buffer_info; 7028 tx_desc = IGB_TX_DESC(tx_ring, 0); 7029 } 7030 7031 /* issue prefetch for next Tx descriptor */ 7032 prefetch(tx_desc); 7033 7034 /* update budget accounting */ 7035 budget--; 7036 } while (likely(budget)); 7037 7038 netdev_tx_completed_queue(txring_txq(tx_ring), 7039 total_packets, total_bytes); 7040 i += tx_ring->count; 7041 tx_ring->next_to_clean = i; 7042 u64_stats_update_begin(&tx_ring->tx_syncp); 7043 tx_ring->tx_stats.bytes += total_bytes; 7044 tx_ring->tx_stats.packets += total_packets; 7045 u64_stats_update_end(&tx_ring->tx_syncp); 7046 q_vector->tx.total_bytes += total_bytes; 7047 q_vector->tx.total_packets += total_packets; 7048 7049 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 7050 struct e1000_hw *hw = &adapter->hw; 7051 7052 /* Detect a transmit hang in hardware, this serializes the 7053 * check with the clearing of time_stamp and movement of i 7054 */ 7055 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 7056 if (tx_buffer->next_to_watch && 7057 time_after(jiffies, tx_buffer->time_stamp + 7058 (adapter->tx_timeout_factor * HZ)) && 7059 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 7060 7061 /* detected Tx unit hang */ 7062 dev_err(tx_ring->dev, 7063 "Detected Tx Unit Hang\n" 7064 " Tx Queue <%d>\n" 7065 " TDH <%x>\n" 7066 " TDT <%x>\n" 7067 " next_to_use <%x>\n" 7068 " next_to_clean <%x>\n" 7069 "buffer_info[next_to_clean]\n" 7070 " time_stamp <%lx>\n" 7071 " next_to_watch <%p>\n" 7072 " jiffies <%lx>\n" 7073 " desc.status <%x>\n", 7074 tx_ring->queue_index, 7075 rd32(E1000_TDH(tx_ring->reg_idx)), 7076 readl(tx_ring->tail), 7077 tx_ring->next_to_use, 7078 tx_ring->next_to_clean, 7079 tx_buffer->time_stamp, 7080 tx_buffer->next_to_watch, 7081 jiffies, 7082 tx_buffer->next_to_watch->wb.status); 7083 netif_stop_subqueue(tx_ring->netdev, 7084 tx_ring->queue_index); 7085 7086 /* we are about to reset, no point in enabling stuff */ 7087 return true; 7088 } 7089 } 7090 7091 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 7092 if (unlikely(total_packets && 7093 netif_carrier_ok(tx_ring->netdev) && 7094 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 7095 /* Make sure that anybody stopping the queue after this 7096 * sees the new next_to_clean. 7097 */ 7098 smp_mb(); 7099 if (__netif_subqueue_stopped(tx_ring->netdev, 7100 tx_ring->queue_index) && 7101 !(test_bit(__IGB_DOWN, &adapter->state))) { 7102 netif_wake_subqueue(tx_ring->netdev, 7103 tx_ring->queue_index); 7104 7105 u64_stats_update_begin(&tx_ring->tx_syncp); 7106 tx_ring->tx_stats.restart_queue++; 7107 u64_stats_update_end(&tx_ring->tx_syncp); 7108 } 7109 } 7110 7111 return !!budget; 7112 } 7113 7114 /** 7115 * igb_reuse_rx_page - page flip buffer and store it back on the ring 7116 * @rx_ring: rx descriptor ring to store buffers on 7117 * @old_buff: donor buffer to have page reused 7118 * 7119 * Synchronizes page for reuse by the adapter 7120 **/ 7121 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 7122 struct igb_rx_buffer *old_buff) 7123 { 7124 struct igb_rx_buffer *new_buff; 7125 u16 nta = rx_ring->next_to_alloc; 7126 7127 new_buff = &rx_ring->rx_buffer_info[nta]; 7128 7129 /* update, and store next to alloc */ 7130 nta++; 7131 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 7132 7133 /* Transfer page from old buffer to new buffer. 7134 * Move each member individually to avoid possible store 7135 * forwarding stalls. 7136 */ 7137 new_buff->dma = old_buff->dma; 7138 new_buff->page = old_buff->page; 7139 new_buff->page_offset = old_buff->page_offset; 7140 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 7141 } 7142 7143 static inline bool igb_page_is_reserved(struct page *page) 7144 { 7145 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 7146 } 7147 7148 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer) 7149 { 7150 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 7151 struct page *page = rx_buffer->page; 7152 7153 /* avoid re-using remote pages */ 7154 if (unlikely(igb_page_is_reserved(page))) 7155 return false; 7156 7157 #if (PAGE_SIZE < 8192) 7158 /* if we are only owner of page we can reuse it */ 7159 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 7160 return false; 7161 #else 7162 #define IGB_LAST_OFFSET \ 7163 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 7164 7165 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 7166 return false; 7167 #endif 7168 7169 /* If we have drained the page fragment pool we need to update 7170 * the pagecnt_bias and page count so that we fully restock the 7171 * number of references the driver holds. 7172 */ 7173 if (unlikely(!pagecnt_bias)) { 7174 page_ref_add(page, USHRT_MAX); 7175 rx_buffer->pagecnt_bias = USHRT_MAX; 7176 } 7177 7178 return true; 7179 } 7180 7181 /** 7182 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 7183 * @rx_ring: rx descriptor ring to transact packets on 7184 * @rx_buffer: buffer containing page to add 7185 * @skb: sk_buff to place the data into 7186 * @size: size of buffer to be added 7187 * 7188 * This function will add the data contained in rx_buffer->page to the skb. 7189 **/ 7190 static void igb_add_rx_frag(struct igb_ring *rx_ring, 7191 struct igb_rx_buffer *rx_buffer, 7192 struct sk_buff *skb, 7193 unsigned int size) 7194 { 7195 #if (PAGE_SIZE < 8192) 7196 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 7197 #else 7198 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 7199 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 7200 SKB_DATA_ALIGN(size); 7201 #endif 7202 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 7203 rx_buffer->page_offset, size, truesize); 7204 #if (PAGE_SIZE < 8192) 7205 rx_buffer->page_offset ^= truesize; 7206 #else 7207 rx_buffer->page_offset += truesize; 7208 #endif 7209 } 7210 7211 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 7212 struct igb_rx_buffer *rx_buffer, 7213 union e1000_adv_rx_desc *rx_desc, 7214 unsigned int size) 7215 { 7216 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 7217 #if (PAGE_SIZE < 8192) 7218 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 7219 #else 7220 unsigned int truesize = SKB_DATA_ALIGN(size); 7221 #endif 7222 unsigned int headlen; 7223 struct sk_buff *skb; 7224 7225 /* prefetch first cache line of first page */ 7226 prefetch(va); 7227 #if L1_CACHE_BYTES < 128 7228 prefetch(va + L1_CACHE_BYTES); 7229 #endif 7230 7231 /* allocate a skb to store the frags */ 7232 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 7233 if (unlikely(!skb)) 7234 return NULL; 7235 7236 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) { 7237 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 7238 va += IGB_TS_HDR_LEN; 7239 size -= IGB_TS_HDR_LEN; 7240 } 7241 7242 /* Determine available headroom for copy */ 7243 headlen = size; 7244 if (headlen > IGB_RX_HDR_LEN) 7245 headlen = eth_get_headlen(va, IGB_RX_HDR_LEN); 7246 7247 /* align pull length to size of long to optimize memcpy performance */ 7248 memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long))); 7249 7250 /* update all of the pointers */ 7251 size -= headlen; 7252 if (size) { 7253 skb_add_rx_frag(skb, 0, rx_buffer->page, 7254 (va + headlen) - page_address(rx_buffer->page), 7255 size, truesize); 7256 #if (PAGE_SIZE < 8192) 7257 rx_buffer->page_offset ^= truesize; 7258 #else 7259 rx_buffer->page_offset += truesize; 7260 #endif 7261 } else { 7262 rx_buffer->pagecnt_bias++; 7263 } 7264 7265 return skb; 7266 } 7267 7268 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 7269 struct igb_rx_buffer *rx_buffer, 7270 union e1000_adv_rx_desc *rx_desc, 7271 unsigned int size) 7272 { 7273 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 7274 #if (PAGE_SIZE < 8192) 7275 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 7276 #else 7277 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 7278 SKB_DATA_ALIGN(IGB_SKB_PAD + size); 7279 #endif 7280 struct sk_buff *skb; 7281 7282 /* prefetch first cache line of first page */ 7283 prefetch(va); 7284 #if L1_CACHE_BYTES < 128 7285 prefetch(va + L1_CACHE_BYTES); 7286 #endif 7287 7288 /* build an skb around the page buffer */ 7289 skb = build_skb(va - IGB_SKB_PAD, truesize); 7290 if (unlikely(!skb)) 7291 return NULL; 7292 7293 /* update pointers within the skb to store the data */ 7294 skb_reserve(skb, IGB_SKB_PAD); 7295 __skb_put(skb, size); 7296 7297 /* pull timestamp out of packet data */ 7298 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 7299 igb_ptp_rx_pktstamp(rx_ring->q_vector, skb->data, skb); 7300 __skb_pull(skb, IGB_TS_HDR_LEN); 7301 } 7302 7303 /* update buffer offset */ 7304 #if (PAGE_SIZE < 8192) 7305 rx_buffer->page_offset ^= truesize; 7306 #else 7307 rx_buffer->page_offset += truesize; 7308 #endif 7309 7310 return skb; 7311 } 7312 7313 static inline void igb_rx_checksum(struct igb_ring *ring, 7314 union e1000_adv_rx_desc *rx_desc, 7315 struct sk_buff *skb) 7316 { 7317 skb_checksum_none_assert(skb); 7318 7319 /* Ignore Checksum bit is set */ 7320 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 7321 return; 7322 7323 /* Rx checksum disabled via ethtool */ 7324 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 7325 return; 7326 7327 /* TCP/UDP checksum error bit is set */ 7328 if (igb_test_staterr(rx_desc, 7329 E1000_RXDEXT_STATERR_TCPE | 7330 E1000_RXDEXT_STATERR_IPE)) { 7331 /* work around errata with sctp packets where the TCPE aka 7332 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 7333 * packets, (aka let the stack check the crc32c) 7334 */ 7335 if (!((skb->len == 60) && 7336 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 7337 u64_stats_update_begin(&ring->rx_syncp); 7338 ring->rx_stats.csum_err++; 7339 u64_stats_update_end(&ring->rx_syncp); 7340 } 7341 /* let the stack verify checksum errors */ 7342 return; 7343 } 7344 /* It must be a TCP or UDP packet with a valid checksum */ 7345 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 7346 E1000_RXD_STAT_UDPCS)) 7347 skb->ip_summed = CHECKSUM_UNNECESSARY; 7348 7349 dev_dbg(ring->dev, "cksum success: bits %08X\n", 7350 le32_to_cpu(rx_desc->wb.upper.status_error)); 7351 } 7352 7353 static inline void igb_rx_hash(struct igb_ring *ring, 7354 union e1000_adv_rx_desc *rx_desc, 7355 struct sk_buff *skb) 7356 { 7357 if (ring->netdev->features & NETIF_F_RXHASH) 7358 skb_set_hash(skb, 7359 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 7360 PKT_HASH_TYPE_L3); 7361 } 7362 7363 /** 7364 * igb_is_non_eop - process handling of non-EOP buffers 7365 * @rx_ring: Rx ring being processed 7366 * @rx_desc: Rx descriptor for current buffer 7367 * @skb: current socket buffer containing buffer in progress 7368 * 7369 * This function updates next to clean. If the buffer is an EOP buffer 7370 * this function exits returning false, otherwise it will place the 7371 * sk_buff in the next buffer to be chained and return true indicating 7372 * that this is in fact a non-EOP buffer. 7373 **/ 7374 static bool igb_is_non_eop(struct igb_ring *rx_ring, 7375 union e1000_adv_rx_desc *rx_desc) 7376 { 7377 u32 ntc = rx_ring->next_to_clean + 1; 7378 7379 /* fetch, update, and store next to clean */ 7380 ntc = (ntc < rx_ring->count) ? ntc : 0; 7381 rx_ring->next_to_clean = ntc; 7382 7383 prefetch(IGB_RX_DESC(rx_ring, ntc)); 7384 7385 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 7386 return false; 7387 7388 return true; 7389 } 7390 7391 /** 7392 * igb_cleanup_headers - Correct corrupted or empty headers 7393 * @rx_ring: rx descriptor ring packet is being transacted on 7394 * @rx_desc: pointer to the EOP Rx descriptor 7395 * @skb: pointer to current skb being fixed 7396 * 7397 * Address the case where we are pulling data in on pages only 7398 * and as such no data is present in the skb header. 7399 * 7400 * In addition if skb is not at least 60 bytes we need to pad it so that 7401 * it is large enough to qualify as a valid Ethernet frame. 7402 * 7403 * Returns true if an error was encountered and skb was freed. 7404 **/ 7405 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 7406 union e1000_adv_rx_desc *rx_desc, 7407 struct sk_buff *skb) 7408 { 7409 if (unlikely((igb_test_staterr(rx_desc, 7410 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 7411 struct net_device *netdev = rx_ring->netdev; 7412 if (!(netdev->features & NETIF_F_RXALL)) { 7413 dev_kfree_skb_any(skb); 7414 return true; 7415 } 7416 } 7417 7418 /* if eth_skb_pad returns an error the skb was freed */ 7419 if (eth_skb_pad(skb)) 7420 return true; 7421 7422 return false; 7423 } 7424 7425 /** 7426 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 7427 * @rx_ring: rx descriptor ring packet is being transacted on 7428 * @rx_desc: pointer to the EOP Rx descriptor 7429 * @skb: pointer to current skb being populated 7430 * 7431 * This function checks the ring, descriptor, and packet information in 7432 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 7433 * other fields within the skb. 7434 **/ 7435 static void igb_process_skb_fields(struct igb_ring *rx_ring, 7436 union e1000_adv_rx_desc *rx_desc, 7437 struct sk_buff *skb) 7438 { 7439 struct net_device *dev = rx_ring->netdev; 7440 7441 igb_rx_hash(rx_ring, rx_desc, skb); 7442 7443 igb_rx_checksum(rx_ring, rx_desc, skb); 7444 7445 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 7446 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 7447 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 7448 7449 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 7450 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 7451 u16 vid; 7452 7453 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 7454 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 7455 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 7456 else 7457 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 7458 7459 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 7460 } 7461 7462 skb_record_rx_queue(skb, rx_ring->queue_index); 7463 7464 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 7465 } 7466 7467 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 7468 const unsigned int size) 7469 { 7470 struct igb_rx_buffer *rx_buffer; 7471 7472 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 7473 prefetchw(rx_buffer->page); 7474 7475 /* we are reusing so sync this buffer for CPU use */ 7476 dma_sync_single_range_for_cpu(rx_ring->dev, 7477 rx_buffer->dma, 7478 rx_buffer->page_offset, 7479 size, 7480 DMA_FROM_DEVICE); 7481 7482 rx_buffer->pagecnt_bias--; 7483 7484 return rx_buffer; 7485 } 7486 7487 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 7488 struct igb_rx_buffer *rx_buffer) 7489 { 7490 if (igb_can_reuse_rx_page(rx_buffer)) { 7491 /* hand second half of page back to the ring */ 7492 igb_reuse_rx_page(rx_ring, rx_buffer); 7493 } else { 7494 /* We are not reusing the buffer so unmap it and free 7495 * any references we are holding to it 7496 */ 7497 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 7498 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 7499 IGB_RX_DMA_ATTR); 7500 __page_frag_cache_drain(rx_buffer->page, 7501 rx_buffer->pagecnt_bias); 7502 } 7503 7504 /* clear contents of rx_buffer */ 7505 rx_buffer->page = NULL; 7506 } 7507 7508 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 7509 { 7510 struct igb_ring *rx_ring = q_vector->rx.ring; 7511 struct sk_buff *skb = rx_ring->skb; 7512 unsigned int total_bytes = 0, total_packets = 0; 7513 u16 cleaned_count = igb_desc_unused(rx_ring); 7514 7515 while (likely(total_packets < budget)) { 7516 union e1000_adv_rx_desc *rx_desc; 7517 struct igb_rx_buffer *rx_buffer; 7518 unsigned int size; 7519 7520 /* return some buffers to hardware, one at a time is too slow */ 7521 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 7522 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7523 cleaned_count = 0; 7524 } 7525 7526 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 7527 size = le16_to_cpu(rx_desc->wb.upper.length); 7528 if (!size) 7529 break; 7530 7531 /* This memory barrier is needed to keep us from reading 7532 * any other fields out of the rx_desc until we know the 7533 * descriptor has been written back 7534 */ 7535 dma_rmb(); 7536 7537 rx_buffer = igb_get_rx_buffer(rx_ring, size); 7538 7539 /* retrieve a buffer from the ring */ 7540 if (skb) 7541 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 7542 else if (ring_uses_build_skb(rx_ring)) 7543 skb = igb_build_skb(rx_ring, rx_buffer, rx_desc, size); 7544 else 7545 skb = igb_construct_skb(rx_ring, rx_buffer, 7546 rx_desc, size); 7547 7548 /* exit if we failed to retrieve a buffer */ 7549 if (!skb) { 7550 rx_ring->rx_stats.alloc_failed++; 7551 rx_buffer->pagecnt_bias++; 7552 break; 7553 } 7554 7555 igb_put_rx_buffer(rx_ring, rx_buffer); 7556 cleaned_count++; 7557 7558 /* fetch next buffer in frame if non-eop */ 7559 if (igb_is_non_eop(rx_ring, rx_desc)) 7560 continue; 7561 7562 /* verify the packet layout is correct */ 7563 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 7564 skb = NULL; 7565 continue; 7566 } 7567 7568 /* probably a little skewed due to removing CRC */ 7569 total_bytes += skb->len; 7570 7571 /* populate checksum, timestamp, VLAN, and protocol */ 7572 igb_process_skb_fields(rx_ring, rx_desc, skb); 7573 7574 napi_gro_receive(&q_vector->napi, skb); 7575 7576 /* reset skb pointer */ 7577 skb = NULL; 7578 7579 /* update budget accounting */ 7580 total_packets++; 7581 } 7582 7583 /* place incomplete frames back on ring for completion */ 7584 rx_ring->skb = skb; 7585 7586 u64_stats_update_begin(&rx_ring->rx_syncp); 7587 rx_ring->rx_stats.packets += total_packets; 7588 rx_ring->rx_stats.bytes += total_bytes; 7589 u64_stats_update_end(&rx_ring->rx_syncp); 7590 q_vector->rx.total_packets += total_packets; 7591 q_vector->rx.total_bytes += total_bytes; 7592 7593 if (cleaned_count) 7594 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7595 7596 return total_packets; 7597 } 7598 7599 static inline unsigned int igb_rx_offset(struct igb_ring *rx_ring) 7600 { 7601 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 7602 } 7603 7604 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 7605 struct igb_rx_buffer *bi) 7606 { 7607 struct page *page = bi->page; 7608 dma_addr_t dma; 7609 7610 /* since we are recycling buffers we should seldom need to alloc */ 7611 if (likely(page)) 7612 return true; 7613 7614 /* alloc new page for storage */ 7615 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 7616 if (unlikely(!page)) { 7617 rx_ring->rx_stats.alloc_failed++; 7618 return false; 7619 } 7620 7621 /* map page for use */ 7622 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 7623 igb_rx_pg_size(rx_ring), 7624 DMA_FROM_DEVICE, 7625 IGB_RX_DMA_ATTR); 7626 7627 /* if mapping failed free memory back to system since 7628 * there isn't much point in holding memory we can't use 7629 */ 7630 if (dma_mapping_error(rx_ring->dev, dma)) { 7631 __free_pages(page, igb_rx_pg_order(rx_ring)); 7632 7633 rx_ring->rx_stats.alloc_failed++; 7634 return false; 7635 } 7636 7637 bi->dma = dma; 7638 bi->page = page; 7639 bi->page_offset = igb_rx_offset(rx_ring); 7640 bi->pagecnt_bias = 1; 7641 7642 return true; 7643 } 7644 7645 /** 7646 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 7647 * @adapter: address of board private structure 7648 **/ 7649 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 7650 { 7651 union e1000_adv_rx_desc *rx_desc; 7652 struct igb_rx_buffer *bi; 7653 u16 i = rx_ring->next_to_use; 7654 u16 bufsz; 7655 7656 /* nothing to do */ 7657 if (!cleaned_count) 7658 return; 7659 7660 rx_desc = IGB_RX_DESC(rx_ring, i); 7661 bi = &rx_ring->rx_buffer_info[i]; 7662 i -= rx_ring->count; 7663 7664 bufsz = igb_rx_bufsz(rx_ring); 7665 7666 do { 7667 if (!igb_alloc_mapped_page(rx_ring, bi)) 7668 break; 7669 7670 /* sync the buffer for use by the device */ 7671 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 7672 bi->page_offset, bufsz, 7673 DMA_FROM_DEVICE); 7674 7675 /* Refresh the desc even if buffer_addrs didn't change 7676 * because each write-back erases this info. 7677 */ 7678 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 7679 7680 rx_desc++; 7681 bi++; 7682 i++; 7683 if (unlikely(!i)) { 7684 rx_desc = IGB_RX_DESC(rx_ring, 0); 7685 bi = rx_ring->rx_buffer_info; 7686 i -= rx_ring->count; 7687 } 7688 7689 /* clear the length for the next_to_use descriptor */ 7690 rx_desc->wb.upper.length = 0; 7691 7692 cleaned_count--; 7693 } while (cleaned_count); 7694 7695 i += rx_ring->count; 7696 7697 if (rx_ring->next_to_use != i) { 7698 /* record the next descriptor to use */ 7699 rx_ring->next_to_use = i; 7700 7701 /* update next to alloc since we have filled the ring */ 7702 rx_ring->next_to_alloc = i; 7703 7704 /* Force memory writes to complete before letting h/w 7705 * know there are new descriptors to fetch. (Only 7706 * applicable for weak-ordered memory model archs, 7707 * such as IA-64). 7708 */ 7709 wmb(); 7710 writel(i, rx_ring->tail); 7711 } 7712 } 7713 7714 /** 7715 * igb_mii_ioctl - 7716 * @netdev: 7717 * @ifreq: 7718 * @cmd: 7719 **/ 7720 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7721 { 7722 struct igb_adapter *adapter = netdev_priv(netdev); 7723 struct mii_ioctl_data *data = if_mii(ifr); 7724 7725 if (adapter->hw.phy.media_type != e1000_media_type_copper) 7726 return -EOPNOTSUPP; 7727 7728 switch (cmd) { 7729 case SIOCGMIIPHY: 7730 data->phy_id = adapter->hw.phy.addr; 7731 break; 7732 case SIOCGMIIREG: 7733 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 7734 &data->val_out)) 7735 return -EIO; 7736 break; 7737 case SIOCSMIIREG: 7738 default: 7739 return -EOPNOTSUPP; 7740 } 7741 return 0; 7742 } 7743 7744 /** 7745 * igb_ioctl - 7746 * @netdev: 7747 * @ifreq: 7748 * @cmd: 7749 **/ 7750 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7751 { 7752 switch (cmd) { 7753 case SIOCGMIIPHY: 7754 case SIOCGMIIREG: 7755 case SIOCSMIIREG: 7756 return igb_mii_ioctl(netdev, ifr, cmd); 7757 case SIOCGHWTSTAMP: 7758 return igb_ptp_get_ts_config(netdev, ifr); 7759 case SIOCSHWTSTAMP: 7760 return igb_ptp_set_ts_config(netdev, ifr); 7761 default: 7762 return -EOPNOTSUPP; 7763 } 7764 } 7765 7766 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 7767 { 7768 struct igb_adapter *adapter = hw->back; 7769 7770 pci_read_config_word(adapter->pdev, reg, value); 7771 } 7772 7773 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 7774 { 7775 struct igb_adapter *adapter = hw->back; 7776 7777 pci_write_config_word(adapter->pdev, reg, *value); 7778 } 7779 7780 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7781 { 7782 struct igb_adapter *adapter = hw->back; 7783 7784 if (pcie_capability_read_word(adapter->pdev, reg, value)) 7785 return -E1000_ERR_CONFIG; 7786 7787 return 0; 7788 } 7789 7790 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7791 { 7792 struct igb_adapter *adapter = hw->back; 7793 7794 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 7795 return -E1000_ERR_CONFIG; 7796 7797 return 0; 7798 } 7799 7800 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 7801 { 7802 struct igb_adapter *adapter = netdev_priv(netdev); 7803 struct e1000_hw *hw = &adapter->hw; 7804 u32 ctrl, rctl; 7805 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 7806 7807 if (enable) { 7808 /* enable VLAN tag insert/strip */ 7809 ctrl = rd32(E1000_CTRL); 7810 ctrl |= E1000_CTRL_VME; 7811 wr32(E1000_CTRL, ctrl); 7812 7813 /* Disable CFI check */ 7814 rctl = rd32(E1000_RCTL); 7815 rctl &= ~E1000_RCTL_CFIEN; 7816 wr32(E1000_RCTL, rctl); 7817 } else { 7818 /* disable VLAN tag insert/strip */ 7819 ctrl = rd32(E1000_CTRL); 7820 ctrl &= ~E1000_CTRL_VME; 7821 wr32(E1000_CTRL, ctrl); 7822 } 7823 7824 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 7825 } 7826 7827 static int igb_vlan_rx_add_vid(struct net_device *netdev, 7828 __be16 proto, u16 vid) 7829 { 7830 struct igb_adapter *adapter = netdev_priv(netdev); 7831 struct e1000_hw *hw = &adapter->hw; 7832 int pf_id = adapter->vfs_allocated_count; 7833 7834 /* add the filter since PF can receive vlans w/o entry in vlvf */ 7835 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7836 igb_vfta_set(hw, vid, pf_id, true, !!vid); 7837 7838 set_bit(vid, adapter->active_vlans); 7839 7840 return 0; 7841 } 7842 7843 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 7844 __be16 proto, u16 vid) 7845 { 7846 struct igb_adapter *adapter = netdev_priv(netdev); 7847 int pf_id = adapter->vfs_allocated_count; 7848 struct e1000_hw *hw = &adapter->hw; 7849 7850 /* remove VID from filter table */ 7851 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7852 igb_vfta_set(hw, vid, pf_id, false, true); 7853 7854 clear_bit(vid, adapter->active_vlans); 7855 7856 return 0; 7857 } 7858 7859 static void igb_restore_vlan(struct igb_adapter *adapter) 7860 { 7861 u16 vid = 1; 7862 7863 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 7864 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 7865 7866 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 7867 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 7868 } 7869 7870 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 7871 { 7872 struct pci_dev *pdev = adapter->pdev; 7873 struct e1000_mac_info *mac = &adapter->hw.mac; 7874 7875 mac->autoneg = 0; 7876 7877 /* Make sure dplx is at most 1 bit and lsb of speed is not set 7878 * for the switch() below to work 7879 */ 7880 if ((spd & 1) || (dplx & ~1)) 7881 goto err_inval; 7882 7883 /* Fiber NIC's only allow 1000 gbps Full duplex 7884 * and 100Mbps Full duplex for 100baseFx sfp 7885 */ 7886 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 7887 switch (spd + dplx) { 7888 case SPEED_10 + DUPLEX_HALF: 7889 case SPEED_10 + DUPLEX_FULL: 7890 case SPEED_100 + DUPLEX_HALF: 7891 goto err_inval; 7892 default: 7893 break; 7894 } 7895 } 7896 7897 switch (spd + dplx) { 7898 case SPEED_10 + DUPLEX_HALF: 7899 mac->forced_speed_duplex = ADVERTISE_10_HALF; 7900 break; 7901 case SPEED_10 + DUPLEX_FULL: 7902 mac->forced_speed_duplex = ADVERTISE_10_FULL; 7903 break; 7904 case SPEED_100 + DUPLEX_HALF: 7905 mac->forced_speed_duplex = ADVERTISE_100_HALF; 7906 break; 7907 case SPEED_100 + DUPLEX_FULL: 7908 mac->forced_speed_duplex = ADVERTISE_100_FULL; 7909 break; 7910 case SPEED_1000 + DUPLEX_FULL: 7911 mac->autoneg = 1; 7912 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 7913 break; 7914 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 7915 default: 7916 goto err_inval; 7917 } 7918 7919 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 7920 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7921 7922 return 0; 7923 7924 err_inval: 7925 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 7926 return -EINVAL; 7927 } 7928 7929 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 7930 bool runtime) 7931 { 7932 struct net_device *netdev = pci_get_drvdata(pdev); 7933 struct igb_adapter *adapter = netdev_priv(netdev); 7934 struct e1000_hw *hw = &adapter->hw; 7935 u32 ctrl, rctl, status; 7936 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 7937 #ifdef CONFIG_PM 7938 int retval = 0; 7939 #endif 7940 7941 rtnl_lock(); 7942 netif_device_detach(netdev); 7943 7944 if (netif_running(netdev)) 7945 __igb_close(netdev, true); 7946 7947 igb_ptp_suspend(adapter); 7948 7949 igb_clear_interrupt_scheme(adapter); 7950 rtnl_unlock(); 7951 7952 #ifdef CONFIG_PM 7953 retval = pci_save_state(pdev); 7954 if (retval) 7955 return retval; 7956 #endif 7957 7958 status = rd32(E1000_STATUS); 7959 if (status & E1000_STATUS_LU) 7960 wufc &= ~E1000_WUFC_LNKC; 7961 7962 if (wufc) { 7963 igb_setup_rctl(adapter); 7964 igb_set_rx_mode(netdev); 7965 7966 /* turn on all-multi mode if wake on multicast is enabled */ 7967 if (wufc & E1000_WUFC_MC) { 7968 rctl = rd32(E1000_RCTL); 7969 rctl |= E1000_RCTL_MPE; 7970 wr32(E1000_RCTL, rctl); 7971 } 7972 7973 ctrl = rd32(E1000_CTRL); 7974 /* advertise wake from D3Cold */ 7975 #define E1000_CTRL_ADVD3WUC 0x00100000 7976 /* phy power management enable */ 7977 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 7978 ctrl |= E1000_CTRL_ADVD3WUC; 7979 wr32(E1000_CTRL, ctrl); 7980 7981 /* Allow time for pending master requests to run */ 7982 igb_disable_pcie_master(hw); 7983 7984 wr32(E1000_WUC, E1000_WUC_PME_EN); 7985 wr32(E1000_WUFC, wufc); 7986 } else { 7987 wr32(E1000_WUC, 0); 7988 wr32(E1000_WUFC, 0); 7989 } 7990 7991 *enable_wake = wufc || adapter->en_mng_pt; 7992 if (!*enable_wake) 7993 igb_power_down_link(adapter); 7994 else 7995 igb_power_up_link(adapter); 7996 7997 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7998 * would have already happened in close and is redundant. 7999 */ 8000 igb_release_hw_control(adapter); 8001 8002 pci_disable_device(pdev); 8003 8004 return 0; 8005 } 8006 8007 static void igb_deliver_wake_packet(struct net_device *netdev) 8008 { 8009 struct igb_adapter *adapter = netdev_priv(netdev); 8010 struct e1000_hw *hw = &adapter->hw; 8011 struct sk_buff *skb; 8012 u32 wupl; 8013 8014 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 8015 8016 /* WUPM stores only the first 128 bytes of the wake packet. 8017 * Read the packet only if we have the whole thing. 8018 */ 8019 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 8020 return; 8021 8022 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 8023 if (!skb) 8024 return; 8025 8026 skb_put(skb, wupl); 8027 8028 /* Ensure reads are 32-bit aligned */ 8029 wupl = roundup(wupl, 4); 8030 8031 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 8032 8033 skb->protocol = eth_type_trans(skb, netdev); 8034 netif_rx(skb); 8035 } 8036 8037 static int __maybe_unused igb_suspend(struct device *dev) 8038 { 8039 int retval; 8040 bool wake; 8041 struct pci_dev *pdev = to_pci_dev(dev); 8042 8043 retval = __igb_shutdown(pdev, &wake, 0); 8044 if (retval) 8045 return retval; 8046 8047 if (wake) { 8048 pci_prepare_to_sleep(pdev); 8049 } else { 8050 pci_wake_from_d3(pdev, false); 8051 pci_set_power_state(pdev, PCI_D3hot); 8052 } 8053 8054 return 0; 8055 } 8056 8057 static int __maybe_unused igb_resume(struct device *dev) 8058 { 8059 struct pci_dev *pdev = to_pci_dev(dev); 8060 struct net_device *netdev = pci_get_drvdata(pdev); 8061 struct igb_adapter *adapter = netdev_priv(netdev); 8062 struct e1000_hw *hw = &adapter->hw; 8063 u32 err, val; 8064 8065 pci_set_power_state(pdev, PCI_D0); 8066 pci_restore_state(pdev); 8067 pci_save_state(pdev); 8068 8069 if (!pci_device_is_present(pdev)) 8070 return -ENODEV; 8071 err = pci_enable_device_mem(pdev); 8072 if (err) { 8073 dev_err(&pdev->dev, 8074 "igb: Cannot enable PCI device from suspend\n"); 8075 return err; 8076 } 8077 pci_set_master(pdev); 8078 8079 pci_enable_wake(pdev, PCI_D3hot, 0); 8080 pci_enable_wake(pdev, PCI_D3cold, 0); 8081 8082 if (igb_init_interrupt_scheme(adapter, true)) { 8083 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8084 return -ENOMEM; 8085 } 8086 8087 igb_reset(adapter); 8088 8089 /* let the f/w know that the h/w is now under the control of the 8090 * driver. 8091 */ 8092 igb_get_hw_control(adapter); 8093 8094 val = rd32(E1000_WUS); 8095 if (val & WAKE_PKT_WUS) 8096 igb_deliver_wake_packet(netdev); 8097 8098 wr32(E1000_WUS, ~0); 8099 8100 rtnl_lock(); 8101 if (!err && netif_running(netdev)) 8102 err = __igb_open(netdev, true); 8103 8104 if (!err) 8105 netif_device_attach(netdev); 8106 rtnl_unlock(); 8107 8108 return err; 8109 } 8110 8111 static int __maybe_unused igb_runtime_idle(struct device *dev) 8112 { 8113 struct pci_dev *pdev = to_pci_dev(dev); 8114 struct net_device *netdev = pci_get_drvdata(pdev); 8115 struct igb_adapter *adapter = netdev_priv(netdev); 8116 8117 if (!igb_has_link(adapter)) 8118 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 8119 8120 return -EBUSY; 8121 } 8122 8123 static int __maybe_unused igb_runtime_suspend(struct device *dev) 8124 { 8125 struct pci_dev *pdev = to_pci_dev(dev); 8126 int retval; 8127 bool wake; 8128 8129 retval = __igb_shutdown(pdev, &wake, 1); 8130 if (retval) 8131 return retval; 8132 8133 if (wake) { 8134 pci_prepare_to_sleep(pdev); 8135 } else { 8136 pci_wake_from_d3(pdev, false); 8137 pci_set_power_state(pdev, PCI_D3hot); 8138 } 8139 8140 return 0; 8141 } 8142 8143 static int __maybe_unused igb_runtime_resume(struct device *dev) 8144 { 8145 return igb_resume(dev); 8146 } 8147 8148 static void igb_shutdown(struct pci_dev *pdev) 8149 { 8150 bool wake; 8151 8152 __igb_shutdown(pdev, &wake, 0); 8153 8154 if (system_state == SYSTEM_POWER_OFF) { 8155 pci_wake_from_d3(pdev, wake); 8156 pci_set_power_state(pdev, PCI_D3hot); 8157 } 8158 } 8159 8160 #ifdef CONFIG_PCI_IOV 8161 static int igb_sriov_reinit(struct pci_dev *dev) 8162 { 8163 struct net_device *netdev = pci_get_drvdata(dev); 8164 struct igb_adapter *adapter = netdev_priv(netdev); 8165 struct pci_dev *pdev = adapter->pdev; 8166 8167 rtnl_lock(); 8168 8169 if (netif_running(netdev)) 8170 igb_close(netdev); 8171 else 8172 igb_reset(adapter); 8173 8174 igb_clear_interrupt_scheme(adapter); 8175 8176 igb_init_queue_configuration(adapter); 8177 8178 if (igb_init_interrupt_scheme(adapter, true)) { 8179 rtnl_unlock(); 8180 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8181 return -ENOMEM; 8182 } 8183 8184 if (netif_running(netdev)) 8185 igb_open(netdev); 8186 8187 rtnl_unlock(); 8188 8189 return 0; 8190 } 8191 8192 static int igb_pci_disable_sriov(struct pci_dev *dev) 8193 { 8194 int err = igb_disable_sriov(dev); 8195 8196 if (!err) 8197 err = igb_sriov_reinit(dev); 8198 8199 return err; 8200 } 8201 8202 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 8203 { 8204 int err = igb_enable_sriov(dev, num_vfs); 8205 8206 if (err) 8207 goto out; 8208 8209 err = igb_sriov_reinit(dev); 8210 if (!err) 8211 return num_vfs; 8212 8213 out: 8214 return err; 8215 } 8216 8217 #endif 8218 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 8219 { 8220 #ifdef CONFIG_PCI_IOV 8221 if (num_vfs == 0) 8222 return igb_pci_disable_sriov(dev); 8223 else 8224 return igb_pci_enable_sriov(dev, num_vfs); 8225 #endif 8226 return 0; 8227 } 8228 8229 #ifdef CONFIG_NET_POLL_CONTROLLER 8230 /* Polling 'interrupt' - used by things like netconsole to send skbs 8231 * without having to re-enable interrupts. It's not called while 8232 * the interrupt routine is executing. 8233 */ 8234 static void igb_netpoll(struct net_device *netdev) 8235 { 8236 struct igb_adapter *adapter = netdev_priv(netdev); 8237 struct e1000_hw *hw = &adapter->hw; 8238 struct igb_q_vector *q_vector; 8239 int i; 8240 8241 for (i = 0; i < adapter->num_q_vectors; i++) { 8242 q_vector = adapter->q_vector[i]; 8243 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8244 wr32(E1000_EIMC, q_vector->eims_value); 8245 else 8246 igb_irq_disable(adapter); 8247 napi_schedule(&q_vector->napi); 8248 } 8249 } 8250 #endif /* CONFIG_NET_POLL_CONTROLLER */ 8251 8252 /** 8253 * igb_io_error_detected - called when PCI error is detected 8254 * @pdev: Pointer to PCI device 8255 * @state: The current pci connection state 8256 * 8257 * This function is called after a PCI bus error affecting 8258 * this device has been detected. 8259 **/ 8260 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 8261 pci_channel_state_t state) 8262 { 8263 struct net_device *netdev = pci_get_drvdata(pdev); 8264 struct igb_adapter *adapter = netdev_priv(netdev); 8265 8266 netif_device_detach(netdev); 8267 8268 if (state == pci_channel_io_perm_failure) 8269 return PCI_ERS_RESULT_DISCONNECT; 8270 8271 if (netif_running(netdev)) 8272 igb_down(adapter); 8273 pci_disable_device(pdev); 8274 8275 /* Request a slot slot reset. */ 8276 return PCI_ERS_RESULT_NEED_RESET; 8277 } 8278 8279 /** 8280 * igb_io_slot_reset - called after the pci bus has been reset. 8281 * @pdev: Pointer to PCI device 8282 * 8283 * Restart the card from scratch, as if from a cold-boot. Implementation 8284 * resembles the first-half of the igb_resume routine. 8285 **/ 8286 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 8287 { 8288 struct net_device *netdev = pci_get_drvdata(pdev); 8289 struct igb_adapter *adapter = netdev_priv(netdev); 8290 struct e1000_hw *hw = &adapter->hw; 8291 pci_ers_result_t result; 8292 int err; 8293 8294 if (pci_enable_device_mem(pdev)) { 8295 dev_err(&pdev->dev, 8296 "Cannot re-enable PCI device after reset.\n"); 8297 result = PCI_ERS_RESULT_DISCONNECT; 8298 } else { 8299 pci_set_master(pdev); 8300 pci_restore_state(pdev); 8301 pci_save_state(pdev); 8302 8303 pci_enable_wake(pdev, PCI_D3hot, 0); 8304 pci_enable_wake(pdev, PCI_D3cold, 0); 8305 8306 /* In case of PCI error, adapter lose its HW address 8307 * so we should re-assign it here. 8308 */ 8309 hw->hw_addr = adapter->io_addr; 8310 8311 igb_reset(adapter); 8312 wr32(E1000_WUS, ~0); 8313 result = PCI_ERS_RESULT_RECOVERED; 8314 } 8315 8316 err = pci_cleanup_aer_uncorrect_error_status(pdev); 8317 if (err) { 8318 dev_err(&pdev->dev, 8319 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 8320 err); 8321 /* non-fatal, continue */ 8322 } 8323 8324 return result; 8325 } 8326 8327 /** 8328 * igb_io_resume - called when traffic can start flowing again. 8329 * @pdev: Pointer to PCI device 8330 * 8331 * This callback is called when the error recovery driver tells us that 8332 * its OK to resume normal operation. Implementation resembles the 8333 * second-half of the igb_resume routine. 8334 */ 8335 static void igb_io_resume(struct pci_dev *pdev) 8336 { 8337 struct net_device *netdev = pci_get_drvdata(pdev); 8338 struct igb_adapter *adapter = netdev_priv(netdev); 8339 8340 if (netif_running(netdev)) { 8341 if (igb_up(adapter)) { 8342 dev_err(&pdev->dev, "igb_up failed after reset\n"); 8343 return; 8344 } 8345 } 8346 8347 netif_device_attach(netdev); 8348 8349 /* let the f/w know that the h/w is now under the control of the 8350 * driver. 8351 */ 8352 igb_get_hw_control(adapter); 8353 } 8354 8355 /** 8356 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 8357 * @adapter: Pointer to adapter structure 8358 * @index: Index of the RAR entry which need to be synced with MAC table 8359 **/ 8360 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 8361 { 8362 struct e1000_hw *hw = &adapter->hw; 8363 u32 rar_low, rar_high; 8364 u8 *addr = adapter->mac_table[index].addr; 8365 8366 /* HW expects these to be in network order when they are plugged 8367 * into the registers which are little endian. In order to guarantee 8368 * that ordering we need to do an leXX_to_cpup here in order to be 8369 * ready for the byteswap that occurs with writel 8370 */ 8371 rar_low = le32_to_cpup((__le32 *)(addr)); 8372 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 8373 8374 /* Indicate to hardware the Address is Valid. */ 8375 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 8376 rar_high |= E1000_RAH_AV; 8377 8378 if (hw->mac.type == e1000_82575) 8379 rar_high |= E1000_RAH_POOL_1 * 8380 adapter->mac_table[index].queue; 8381 else 8382 rar_high |= E1000_RAH_POOL_1 << 8383 adapter->mac_table[index].queue; 8384 } 8385 8386 wr32(E1000_RAL(index), rar_low); 8387 wrfl(); 8388 wr32(E1000_RAH(index), rar_high); 8389 wrfl(); 8390 } 8391 8392 static int igb_set_vf_mac(struct igb_adapter *adapter, 8393 int vf, unsigned char *mac_addr) 8394 { 8395 struct e1000_hw *hw = &adapter->hw; 8396 /* VF MAC addresses start at end of receive addresses and moves 8397 * towards the first, as a result a collision should not be possible 8398 */ 8399 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 8400 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 8401 8402 ether_addr_copy(vf_mac_addr, mac_addr); 8403 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 8404 adapter->mac_table[rar_entry].queue = vf; 8405 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 8406 igb_rar_set_index(adapter, rar_entry); 8407 8408 return 0; 8409 } 8410 8411 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 8412 { 8413 struct igb_adapter *adapter = netdev_priv(netdev); 8414 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) 8415 return -EINVAL; 8416 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 8417 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); 8418 dev_info(&adapter->pdev->dev, 8419 "Reload the VF driver to make this change effective."); 8420 if (test_bit(__IGB_DOWN, &adapter->state)) { 8421 dev_warn(&adapter->pdev->dev, 8422 "The VF MAC address has been set, but the PF device is not up.\n"); 8423 dev_warn(&adapter->pdev->dev, 8424 "Bring the PF device up before attempting to use the VF device.\n"); 8425 } 8426 return igb_set_vf_mac(adapter, vf, mac); 8427 } 8428 8429 static int igb_link_mbps(int internal_link_speed) 8430 { 8431 switch (internal_link_speed) { 8432 case SPEED_100: 8433 return 100; 8434 case SPEED_1000: 8435 return 1000; 8436 default: 8437 return 0; 8438 } 8439 } 8440 8441 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 8442 int link_speed) 8443 { 8444 int rf_dec, rf_int; 8445 u32 bcnrc_val; 8446 8447 if (tx_rate != 0) { 8448 /* Calculate the rate factor values to set */ 8449 rf_int = link_speed / tx_rate; 8450 rf_dec = (link_speed - (rf_int * tx_rate)); 8451 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 8452 tx_rate; 8453 8454 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 8455 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 8456 E1000_RTTBCNRC_RF_INT_MASK); 8457 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 8458 } else { 8459 bcnrc_val = 0; 8460 } 8461 8462 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 8463 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 8464 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 8465 */ 8466 wr32(E1000_RTTBCNRM, 0x14); 8467 wr32(E1000_RTTBCNRC, bcnrc_val); 8468 } 8469 8470 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 8471 { 8472 int actual_link_speed, i; 8473 bool reset_rate = false; 8474 8475 /* VF TX rate limit was not set or not supported */ 8476 if ((adapter->vf_rate_link_speed == 0) || 8477 (adapter->hw.mac.type != e1000_82576)) 8478 return; 8479 8480 actual_link_speed = igb_link_mbps(adapter->link_speed); 8481 if (actual_link_speed != adapter->vf_rate_link_speed) { 8482 reset_rate = true; 8483 adapter->vf_rate_link_speed = 0; 8484 dev_info(&adapter->pdev->dev, 8485 "Link speed has been changed. VF Transmit rate is disabled\n"); 8486 } 8487 8488 for (i = 0; i < adapter->vfs_allocated_count; i++) { 8489 if (reset_rate) 8490 adapter->vf_data[i].tx_rate = 0; 8491 8492 igb_set_vf_rate_limit(&adapter->hw, i, 8493 adapter->vf_data[i].tx_rate, 8494 actual_link_speed); 8495 } 8496 } 8497 8498 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 8499 int min_tx_rate, int max_tx_rate) 8500 { 8501 struct igb_adapter *adapter = netdev_priv(netdev); 8502 struct e1000_hw *hw = &adapter->hw; 8503 int actual_link_speed; 8504 8505 if (hw->mac.type != e1000_82576) 8506 return -EOPNOTSUPP; 8507 8508 if (min_tx_rate) 8509 return -EINVAL; 8510 8511 actual_link_speed = igb_link_mbps(adapter->link_speed); 8512 if ((vf >= adapter->vfs_allocated_count) || 8513 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 8514 (max_tx_rate < 0) || 8515 (max_tx_rate > actual_link_speed)) 8516 return -EINVAL; 8517 8518 adapter->vf_rate_link_speed = actual_link_speed; 8519 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 8520 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 8521 8522 return 0; 8523 } 8524 8525 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 8526 bool setting) 8527 { 8528 struct igb_adapter *adapter = netdev_priv(netdev); 8529 struct e1000_hw *hw = &adapter->hw; 8530 u32 reg_val, reg_offset; 8531 8532 if (!adapter->vfs_allocated_count) 8533 return -EOPNOTSUPP; 8534 8535 if (vf >= adapter->vfs_allocated_count) 8536 return -EINVAL; 8537 8538 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 8539 reg_val = rd32(reg_offset); 8540 if (setting) 8541 reg_val |= (BIT(vf) | 8542 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 8543 else 8544 reg_val &= ~(BIT(vf) | 8545 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 8546 wr32(reg_offset, reg_val); 8547 8548 adapter->vf_data[vf].spoofchk_enabled = setting; 8549 return 0; 8550 } 8551 8552 static int igb_ndo_get_vf_config(struct net_device *netdev, 8553 int vf, struct ifla_vf_info *ivi) 8554 { 8555 struct igb_adapter *adapter = netdev_priv(netdev); 8556 if (vf >= adapter->vfs_allocated_count) 8557 return -EINVAL; 8558 ivi->vf = vf; 8559 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 8560 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 8561 ivi->min_tx_rate = 0; 8562 ivi->vlan = adapter->vf_data[vf].pf_vlan; 8563 ivi->qos = adapter->vf_data[vf].pf_qos; 8564 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 8565 return 0; 8566 } 8567 8568 static void igb_vmm_control(struct igb_adapter *adapter) 8569 { 8570 struct e1000_hw *hw = &adapter->hw; 8571 u32 reg; 8572 8573 switch (hw->mac.type) { 8574 case e1000_82575: 8575 case e1000_i210: 8576 case e1000_i211: 8577 case e1000_i354: 8578 default: 8579 /* replication is not supported for 82575 */ 8580 return; 8581 case e1000_82576: 8582 /* notify HW that the MAC is adding vlan tags */ 8583 reg = rd32(E1000_DTXCTL); 8584 reg |= E1000_DTXCTL_VLAN_ADDED; 8585 wr32(E1000_DTXCTL, reg); 8586 /* Fall through */ 8587 case e1000_82580: 8588 /* enable replication vlan tag stripping */ 8589 reg = rd32(E1000_RPLOLR); 8590 reg |= E1000_RPLOLR_STRVLAN; 8591 wr32(E1000_RPLOLR, reg); 8592 /* Fall through */ 8593 case e1000_i350: 8594 /* none of the above registers are supported by i350 */ 8595 break; 8596 } 8597 8598 if (adapter->vfs_allocated_count) { 8599 igb_vmdq_set_loopback_pf(hw, true); 8600 igb_vmdq_set_replication_pf(hw, true); 8601 igb_vmdq_set_anti_spoofing_pf(hw, true, 8602 adapter->vfs_allocated_count); 8603 } else { 8604 igb_vmdq_set_loopback_pf(hw, false); 8605 igb_vmdq_set_replication_pf(hw, false); 8606 } 8607 } 8608 8609 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 8610 { 8611 struct e1000_hw *hw = &adapter->hw; 8612 u32 dmac_thr; 8613 u16 hwm; 8614 8615 if (hw->mac.type > e1000_82580) { 8616 if (adapter->flags & IGB_FLAG_DMAC) { 8617 u32 reg; 8618 8619 /* force threshold to 0. */ 8620 wr32(E1000_DMCTXTH, 0); 8621 8622 /* DMA Coalescing high water mark needs to be greater 8623 * than the Rx threshold. Set hwm to PBA - max frame 8624 * size in 16B units, capping it at PBA - 6KB. 8625 */ 8626 hwm = 64 * (pba - 6); 8627 reg = rd32(E1000_FCRTC); 8628 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 8629 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 8630 & E1000_FCRTC_RTH_COAL_MASK); 8631 wr32(E1000_FCRTC, reg); 8632 8633 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 8634 * frame size, capping it at PBA - 10KB. 8635 */ 8636 dmac_thr = pba - 10; 8637 reg = rd32(E1000_DMACR); 8638 reg &= ~E1000_DMACR_DMACTHR_MASK; 8639 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 8640 & E1000_DMACR_DMACTHR_MASK); 8641 8642 /* transition to L0x or L1 if available..*/ 8643 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 8644 8645 /* watchdog timer= +-1000 usec in 32usec intervals */ 8646 reg |= (1000 >> 5); 8647 8648 /* Disable BMC-to-OS Watchdog Enable */ 8649 if (hw->mac.type != e1000_i354) 8650 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 8651 8652 wr32(E1000_DMACR, reg); 8653 8654 /* no lower threshold to disable 8655 * coalescing(smart fifb)-UTRESH=0 8656 */ 8657 wr32(E1000_DMCRTRH, 0); 8658 8659 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 8660 8661 wr32(E1000_DMCTLX, reg); 8662 8663 /* free space in tx packet buffer to wake from 8664 * DMA coal 8665 */ 8666 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 8667 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 8668 8669 /* make low power state decision controlled 8670 * by DMA coal 8671 */ 8672 reg = rd32(E1000_PCIEMISC); 8673 reg &= ~E1000_PCIEMISC_LX_DECISION; 8674 wr32(E1000_PCIEMISC, reg); 8675 } /* endif adapter->dmac is not disabled */ 8676 } else if (hw->mac.type == e1000_82580) { 8677 u32 reg = rd32(E1000_PCIEMISC); 8678 8679 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 8680 wr32(E1000_DMACR, 0); 8681 } 8682 } 8683 8684 /** 8685 * igb_read_i2c_byte - Reads 8 bit word over I2C 8686 * @hw: pointer to hardware structure 8687 * @byte_offset: byte offset to read 8688 * @dev_addr: device address 8689 * @data: value read 8690 * 8691 * Performs byte read operation over I2C interface at 8692 * a specified device address. 8693 **/ 8694 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8695 u8 dev_addr, u8 *data) 8696 { 8697 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8698 struct i2c_client *this_client = adapter->i2c_client; 8699 s32 status; 8700 u16 swfw_mask = 0; 8701 8702 if (!this_client) 8703 return E1000_ERR_I2C; 8704 8705 swfw_mask = E1000_SWFW_PHY0_SM; 8706 8707 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 8708 return E1000_ERR_SWFW_SYNC; 8709 8710 status = i2c_smbus_read_byte_data(this_client, byte_offset); 8711 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8712 8713 if (status < 0) 8714 return E1000_ERR_I2C; 8715 else { 8716 *data = status; 8717 return 0; 8718 } 8719 } 8720 8721 /** 8722 * igb_write_i2c_byte - Writes 8 bit word over I2C 8723 * @hw: pointer to hardware structure 8724 * @byte_offset: byte offset to write 8725 * @dev_addr: device address 8726 * @data: value to write 8727 * 8728 * Performs byte write operation over I2C interface at 8729 * a specified device address. 8730 **/ 8731 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8732 u8 dev_addr, u8 data) 8733 { 8734 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8735 struct i2c_client *this_client = adapter->i2c_client; 8736 s32 status; 8737 u16 swfw_mask = E1000_SWFW_PHY0_SM; 8738 8739 if (!this_client) 8740 return E1000_ERR_I2C; 8741 8742 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 8743 return E1000_ERR_SWFW_SYNC; 8744 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 8745 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8746 8747 if (status) 8748 return E1000_ERR_I2C; 8749 else 8750 return 0; 8751 8752 } 8753 8754 int igb_reinit_queues(struct igb_adapter *adapter) 8755 { 8756 struct net_device *netdev = adapter->netdev; 8757 struct pci_dev *pdev = adapter->pdev; 8758 int err = 0; 8759 8760 if (netif_running(netdev)) 8761 igb_close(netdev); 8762 8763 igb_reset_interrupt_capability(adapter); 8764 8765 if (igb_init_interrupt_scheme(adapter, true)) { 8766 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8767 return -ENOMEM; 8768 } 8769 8770 if (netif_running(netdev)) 8771 err = igb_open(netdev); 8772 8773 return err; 8774 } 8775 8776 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 8777 { 8778 struct igb_nfc_filter *rule; 8779 8780 spin_lock(&adapter->nfc_lock); 8781 8782 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 8783 igb_erase_filter(adapter, rule); 8784 8785 spin_unlock(&adapter->nfc_lock); 8786 } 8787 8788 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 8789 { 8790 struct igb_nfc_filter *rule; 8791 8792 spin_lock(&adapter->nfc_lock); 8793 8794 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 8795 igb_add_filter(adapter, rule); 8796 8797 spin_unlock(&adapter->nfc_lock); 8798 } 8799 /* igb_main.c */ 8800