1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/sctp.h> 30 #include <linux/if_ether.h> 31 #include <linux/prefetch.h> 32 #include <linux/bpf.h> 33 #include <linux/bpf_trace.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/etherdevice.h> 36 #include <linux/lockdep.h> 37 #ifdef CONFIG_IGB_DCA 38 #include <linux/dca.h> 39 #endif 40 #include <linux/i2c.h> 41 #include "igb.h" 42 43 enum queue_mode { 44 QUEUE_MODE_STRICT_PRIORITY, 45 QUEUE_MODE_STREAM_RESERVATION, 46 }; 47 48 enum tx_queue_prio { 49 TX_QUEUE_PRIO_HIGH, 50 TX_QUEUE_PRIO_LOW, 51 }; 52 53 char igb_driver_name[] = "igb"; 54 static const char igb_driver_string[] = 55 "Intel(R) Gigabit Ethernet Network Driver"; 56 static const char igb_copyright[] = 57 "Copyright (c) 2007-2014 Intel Corporation."; 58 59 static const struct e1000_info *igb_info_tbl[] = { 60 [board_82575] = &e1000_82575_info, 61 }; 62 63 static const struct pci_device_id igb_pci_tbl[] = { 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 99 /* required last entry */ 100 {0, } 101 }; 102 103 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 104 105 static int igb_setup_all_tx_resources(struct igb_adapter *); 106 static int igb_setup_all_rx_resources(struct igb_adapter *); 107 static void igb_free_all_tx_resources(struct igb_adapter *); 108 static void igb_free_all_rx_resources(struct igb_adapter *); 109 static void igb_setup_mrqc(struct igb_adapter *); 110 static void igb_init_queue_configuration(struct igb_adapter *adapter); 111 static int igb_sw_init(struct igb_adapter *); 112 int igb_open(struct net_device *); 113 int igb_close(struct net_device *); 114 static void igb_configure(struct igb_adapter *); 115 static void igb_configure_tx(struct igb_adapter *); 116 static void igb_configure_rx(struct igb_adapter *); 117 static void igb_clean_all_tx_rings(struct igb_adapter *); 118 static void igb_clean_all_rx_rings(struct igb_adapter *); 119 static void igb_clean_tx_ring(struct igb_ring *); 120 static void igb_clean_rx_ring(struct igb_ring *); 121 static void igb_set_rx_mode(struct net_device *); 122 static void igb_update_phy_info(struct timer_list *); 123 static void igb_watchdog(struct timer_list *); 124 static void igb_watchdog_task(struct work_struct *); 125 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 126 static void igb_get_stats64(struct net_device *dev, 127 struct rtnl_link_stats64 *stats); 128 static int igb_change_mtu(struct net_device *, int); 129 static int igb_set_mac(struct net_device *, void *); 130 static void igb_set_uta(struct igb_adapter *adapter, bool set); 131 static irqreturn_t igb_intr(int irq, void *); 132 static irqreturn_t igb_intr_msi(int irq, void *); 133 static irqreturn_t igb_msix_other(int irq, void *); 134 static irqreturn_t igb_msix_ring(int irq, void *); 135 #ifdef CONFIG_IGB_DCA 136 static void igb_update_dca(struct igb_q_vector *); 137 static void igb_setup_dca(struct igb_adapter *); 138 #endif /* CONFIG_IGB_DCA */ 139 static int igb_poll(struct napi_struct *, int); 140 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 141 static int igb_clean_rx_irq(struct igb_q_vector *, int); 142 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 143 static void igb_tx_timeout(struct net_device *, unsigned int txqueue); 144 static void igb_reset_task(struct work_struct *); 145 static void igb_vlan_mode(struct net_device *netdev, 146 netdev_features_t features); 147 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 148 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 149 static void igb_restore_vlan(struct igb_adapter *); 150 static void igb_rar_set_index(struct igb_adapter *, u32); 151 static void igb_ping_all_vfs(struct igb_adapter *); 152 static void igb_msg_task(struct igb_adapter *); 153 static void igb_vmm_control(struct igb_adapter *); 154 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 155 static void igb_flush_mac_table(struct igb_adapter *); 156 static int igb_available_rars(struct igb_adapter *, u8); 157 static void igb_set_default_mac_filter(struct igb_adapter *); 158 static int igb_uc_sync(struct net_device *, const unsigned char *); 159 static int igb_uc_unsync(struct net_device *, const unsigned char *); 160 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 161 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 162 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 163 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 164 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 165 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 166 bool setting); 167 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 168 bool setting); 169 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 170 struct ifla_vf_info *ivi); 171 static void igb_check_vf_rate_limit(struct igb_adapter *); 172 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 173 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 174 175 #ifdef CONFIG_PCI_IOV 176 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 177 static int igb_disable_sriov(struct pci_dev *dev, bool reinit); 178 #endif 179 180 #ifdef CONFIG_IGB_DCA 181 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 182 static struct notifier_block dca_notifier = { 183 .notifier_call = igb_notify_dca, 184 .next = NULL, 185 .priority = 0 186 }; 187 #endif 188 #ifdef CONFIG_PCI_IOV 189 static unsigned int max_vfs; 190 module_param(max_vfs, uint, 0444); 191 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 192 #endif /* CONFIG_PCI_IOV */ 193 194 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 195 pci_channel_state_t); 196 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 197 static void igb_io_resume(struct pci_dev *); 198 199 static const struct pci_error_handlers igb_err_handler = { 200 .error_detected = igb_io_error_detected, 201 .slot_reset = igb_io_slot_reset, 202 .resume = igb_io_resume, 203 }; 204 205 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 206 207 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 208 MODULE_LICENSE("GPL v2"); 209 210 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 211 static int debug = -1; 212 module_param(debug, int, 0); 213 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 214 215 struct igb_reg_info { 216 u32 ofs; 217 char *name; 218 }; 219 220 static const struct igb_reg_info igb_reg_info_tbl[] = { 221 222 /* General Registers */ 223 {E1000_CTRL, "CTRL"}, 224 {E1000_STATUS, "STATUS"}, 225 {E1000_CTRL_EXT, "CTRL_EXT"}, 226 227 /* Interrupt Registers */ 228 {E1000_ICR, "ICR"}, 229 230 /* RX Registers */ 231 {E1000_RCTL, "RCTL"}, 232 {E1000_RDLEN(0), "RDLEN"}, 233 {E1000_RDH(0), "RDH"}, 234 {E1000_RDT(0), "RDT"}, 235 {E1000_RXDCTL(0), "RXDCTL"}, 236 {E1000_RDBAL(0), "RDBAL"}, 237 {E1000_RDBAH(0), "RDBAH"}, 238 239 /* TX Registers */ 240 {E1000_TCTL, "TCTL"}, 241 {E1000_TDBAL(0), "TDBAL"}, 242 {E1000_TDBAH(0), "TDBAH"}, 243 {E1000_TDLEN(0), "TDLEN"}, 244 {E1000_TDH(0), "TDH"}, 245 {E1000_TDT(0), "TDT"}, 246 {E1000_TXDCTL(0), "TXDCTL"}, 247 {E1000_TDFH, "TDFH"}, 248 {E1000_TDFT, "TDFT"}, 249 {E1000_TDFHS, "TDFHS"}, 250 {E1000_TDFPC, "TDFPC"}, 251 252 /* List Terminator */ 253 {} 254 }; 255 256 /* igb_regdump - register printout routine */ 257 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 258 { 259 int n = 0; 260 char rname[16]; 261 u32 regs[8]; 262 263 switch (reginfo->ofs) { 264 case E1000_RDLEN(0): 265 for (n = 0; n < 4; n++) 266 regs[n] = rd32(E1000_RDLEN(n)); 267 break; 268 case E1000_RDH(0): 269 for (n = 0; n < 4; n++) 270 regs[n] = rd32(E1000_RDH(n)); 271 break; 272 case E1000_RDT(0): 273 for (n = 0; n < 4; n++) 274 regs[n] = rd32(E1000_RDT(n)); 275 break; 276 case E1000_RXDCTL(0): 277 for (n = 0; n < 4; n++) 278 regs[n] = rd32(E1000_RXDCTL(n)); 279 break; 280 case E1000_RDBAL(0): 281 for (n = 0; n < 4; n++) 282 regs[n] = rd32(E1000_RDBAL(n)); 283 break; 284 case E1000_RDBAH(0): 285 for (n = 0; n < 4; n++) 286 regs[n] = rd32(E1000_RDBAH(n)); 287 break; 288 case E1000_TDBAL(0): 289 for (n = 0; n < 4; n++) 290 regs[n] = rd32(E1000_TDBAL(n)); 291 break; 292 case E1000_TDBAH(0): 293 for (n = 0; n < 4; n++) 294 regs[n] = rd32(E1000_TDBAH(n)); 295 break; 296 case E1000_TDLEN(0): 297 for (n = 0; n < 4; n++) 298 regs[n] = rd32(E1000_TDLEN(n)); 299 break; 300 case E1000_TDH(0): 301 for (n = 0; n < 4; n++) 302 regs[n] = rd32(E1000_TDH(n)); 303 break; 304 case E1000_TDT(0): 305 for (n = 0; n < 4; n++) 306 regs[n] = rd32(E1000_TDT(n)); 307 break; 308 case E1000_TXDCTL(0): 309 for (n = 0; n < 4; n++) 310 regs[n] = rd32(E1000_TXDCTL(n)); 311 break; 312 default: 313 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 314 return; 315 } 316 317 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 318 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 319 regs[2], regs[3]); 320 } 321 322 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 323 static void igb_dump(struct igb_adapter *adapter) 324 { 325 struct net_device *netdev = adapter->netdev; 326 struct e1000_hw *hw = &adapter->hw; 327 struct igb_reg_info *reginfo; 328 struct igb_ring *tx_ring; 329 union e1000_adv_tx_desc *tx_desc; 330 struct my_u0 { __le64 a; __le64 b; } *u0; 331 struct igb_ring *rx_ring; 332 union e1000_adv_rx_desc *rx_desc; 333 u32 staterr; 334 u16 i, n; 335 336 if (!netif_msg_hw(adapter)) 337 return; 338 339 /* Print netdevice Info */ 340 if (netdev) { 341 dev_info(&adapter->pdev->dev, "Net device Info\n"); 342 pr_info("Device Name state trans_start\n"); 343 pr_info("%-15s %016lX %016lX\n", netdev->name, 344 netdev->state, dev_trans_start(netdev)); 345 } 346 347 /* Print Registers */ 348 dev_info(&adapter->pdev->dev, "Register Dump\n"); 349 pr_info(" Register Name Value\n"); 350 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 351 reginfo->name; reginfo++) { 352 igb_regdump(hw, reginfo); 353 } 354 355 /* Print TX Ring Summary */ 356 if (!netdev || !netif_running(netdev)) 357 goto exit; 358 359 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 360 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 361 for (n = 0; n < adapter->num_tx_queues; n++) { 362 struct igb_tx_buffer *buffer_info; 363 tx_ring = adapter->tx_ring[n]; 364 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 365 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 366 n, tx_ring->next_to_use, tx_ring->next_to_clean, 367 (u64)dma_unmap_addr(buffer_info, dma), 368 dma_unmap_len(buffer_info, len), 369 buffer_info->next_to_watch, 370 (u64)buffer_info->time_stamp); 371 } 372 373 /* Print TX Rings */ 374 if (!netif_msg_tx_done(adapter)) 375 goto rx_ring_summary; 376 377 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 378 379 /* Transmit Descriptor Formats 380 * 381 * Advanced Transmit Descriptor 382 * +--------------------------------------------------------------+ 383 * 0 | Buffer Address [63:0] | 384 * +--------------------------------------------------------------+ 385 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 386 * +--------------------------------------------------------------+ 387 * 63 46 45 40 39 38 36 35 32 31 24 15 0 388 */ 389 390 for (n = 0; n < adapter->num_tx_queues; n++) { 391 tx_ring = adapter->tx_ring[n]; 392 pr_info("------------------------------------\n"); 393 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 394 pr_info("------------------------------------\n"); 395 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 396 397 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 398 const char *next_desc; 399 struct igb_tx_buffer *buffer_info; 400 tx_desc = IGB_TX_DESC(tx_ring, i); 401 buffer_info = &tx_ring->tx_buffer_info[i]; 402 u0 = (struct my_u0 *)tx_desc; 403 if (i == tx_ring->next_to_use && 404 i == tx_ring->next_to_clean) 405 next_desc = " NTC/U"; 406 else if (i == tx_ring->next_to_use) 407 next_desc = " NTU"; 408 else if (i == tx_ring->next_to_clean) 409 next_desc = " NTC"; 410 else 411 next_desc = ""; 412 413 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 414 i, le64_to_cpu(u0->a), 415 le64_to_cpu(u0->b), 416 (u64)dma_unmap_addr(buffer_info, dma), 417 dma_unmap_len(buffer_info, len), 418 buffer_info->next_to_watch, 419 (u64)buffer_info->time_stamp, 420 buffer_info->skb, next_desc); 421 422 if (netif_msg_pktdata(adapter) && buffer_info->skb) 423 print_hex_dump(KERN_INFO, "", 424 DUMP_PREFIX_ADDRESS, 425 16, 1, buffer_info->skb->data, 426 dma_unmap_len(buffer_info, len), 427 true); 428 } 429 } 430 431 /* Print RX Rings Summary */ 432 rx_ring_summary: 433 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 434 pr_info("Queue [NTU] [NTC]\n"); 435 for (n = 0; n < adapter->num_rx_queues; n++) { 436 rx_ring = adapter->rx_ring[n]; 437 pr_info(" %5d %5X %5X\n", 438 n, rx_ring->next_to_use, rx_ring->next_to_clean); 439 } 440 441 /* Print RX Rings */ 442 if (!netif_msg_rx_status(adapter)) 443 goto exit; 444 445 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 446 447 /* Advanced Receive Descriptor (Read) Format 448 * 63 1 0 449 * +-----------------------------------------------------+ 450 * 0 | Packet Buffer Address [63:1] |A0/NSE| 451 * +----------------------------------------------+------+ 452 * 8 | Header Buffer Address [63:1] | DD | 453 * +-----------------------------------------------------+ 454 * 455 * 456 * Advanced Receive Descriptor (Write-Back) Format 457 * 458 * 63 48 47 32 31 30 21 20 17 16 4 3 0 459 * +------------------------------------------------------+ 460 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 461 * | Checksum Ident | | | | Type | Type | 462 * +------------------------------------------------------+ 463 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 464 * +------------------------------------------------------+ 465 * 63 48 47 32 31 20 19 0 466 */ 467 468 for (n = 0; n < adapter->num_rx_queues; n++) { 469 rx_ring = adapter->rx_ring[n]; 470 pr_info("------------------------------------\n"); 471 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 472 pr_info("------------------------------------\n"); 473 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 474 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 475 476 for (i = 0; i < rx_ring->count; i++) { 477 const char *next_desc; 478 struct igb_rx_buffer *buffer_info; 479 buffer_info = &rx_ring->rx_buffer_info[i]; 480 rx_desc = IGB_RX_DESC(rx_ring, i); 481 u0 = (struct my_u0 *)rx_desc; 482 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 483 484 if (i == rx_ring->next_to_use) 485 next_desc = " NTU"; 486 else if (i == rx_ring->next_to_clean) 487 next_desc = " NTC"; 488 else 489 next_desc = ""; 490 491 if (staterr & E1000_RXD_STAT_DD) { 492 /* Descriptor Done */ 493 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 494 "RWB", i, 495 le64_to_cpu(u0->a), 496 le64_to_cpu(u0->b), 497 next_desc); 498 } else { 499 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 500 "R ", i, 501 le64_to_cpu(u0->a), 502 le64_to_cpu(u0->b), 503 (u64)buffer_info->dma, 504 next_desc); 505 506 if (netif_msg_pktdata(adapter) && 507 buffer_info->dma && buffer_info->page) { 508 print_hex_dump(KERN_INFO, "", 509 DUMP_PREFIX_ADDRESS, 510 16, 1, 511 page_address(buffer_info->page) + 512 buffer_info->page_offset, 513 igb_rx_bufsz(rx_ring), true); 514 } 515 } 516 } 517 } 518 519 exit: 520 return; 521 } 522 523 /** 524 * igb_get_i2c_data - Reads the I2C SDA data bit 525 * @data: opaque pointer to adapter struct 526 * 527 * Returns the I2C data bit value 528 **/ 529 static int igb_get_i2c_data(void *data) 530 { 531 struct igb_adapter *adapter = (struct igb_adapter *)data; 532 struct e1000_hw *hw = &adapter->hw; 533 s32 i2cctl = rd32(E1000_I2CPARAMS); 534 535 return !!(i2cctl & E1000_I2C_DATA_IN); 536 } 537 538 /** 539 * igb_set_i2c_data - Sets the I2C data bit 540 * @data: pointer to hardware structure 541 * @state: I2C data value (0 or 1) to set 542 * 543 * Sets the I2C data bit 544 **/ 545 static void igb_set_i2c_data(void *data, int state) 546 { 547 struct igb_adapter *adapter = (struct igb_adapter *)data; 548 struct e1000_hw *hw = &adapter->hw; 549 s32 i2cctl = rd32(E1000_I2CPARAMS); 550 551 if (state) { 552 i2cctl |= E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N; 553 } else { 554 i2cctl &= ~E1000_I2C_DATA_OE_N; 555 i2cctl &= ~E1000_I2C_DATA_OUT; 556 } 557 558 wr32(E1000_I2CPARAMS, i2cctl); 559 wrfl(); 560 } 561 562 /** 563 * igb_set_i2c_clk - Sets the I2C SCL clock 564 * @data: pointer to hardware structure 565 * @state: state to set clock 566 * 567 * Sets the I2C clock line to state 568 **/ 569 static void igb_set_i2c_clk(void *data, int state) 570 { 571 struct igb_adapter *adapter = (struct igb_adapter *)data; 572 struct e1000_hw *hw = &adapter->hw; 573 s32 i2cctl = rd32(E1000_I2CPARAMS); 574 575 if (state) { 576 i2cctl |= E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N; 577 } else { 578 i2cctl &= ~E1000_I2C_CLK_OUT; 579 i2cctl &= ~E1000_I2C_CLK_OE_N; 580 } 581 wr32(E1000_I2CPARAMS, i2cctl); 582 wrfl(); 583 } 584 585 /** 586 * igb_get_i2c_clk - Gets the I2C SCL clock state 587 * @data: pointer to hardware structure 588 * 589 * Gets the I2C clock state 590 **/ 591 static int igb_get_i2c_clk(void *data) 592 { 593 struct igb_adapter *adapter = (struct igb_adapter *)data; 594 struct e1000_hw *hw = &adapter->hw; 595 s32 i2cctl = rd32(E1000_I2CPARAMS); 596 597 return !!(i2cctl & E1000_I2C_CLK_IN); 598 } 599 600 static const struct i2c_algo_bit_data igb_i2c_algo = { 601 .setsda = igb_set_i2c_data, 602 .setscl = igb_set_i2c_clk, 603 .getsda = igb_get_i2c_data, 604 .getscl = igb_get_i2c_clk, 605 .udelay = 5, 606 .timeout = 20, 607 }; 608 609 /** 610 * igb_get_hw_dev - return device 611 * @hw: pointer to hardware structure 612 * 613 * used by hardware layer to print debugging information 614 **/ 615 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 616 { 617 struct igb_adapter *adapter = hw->back; 618 return adapter->netdev; 619 } 620 621 static struct pci_driver igb_driver; 622 623 /** 624 * igb_init_module - Driver Registration Routine 625 * 626 * igb_init_module is the first routine called when the driver is 627 * loaded. All it does is register with the PCI subsystem. 628 **/ 629 static int __init igb_init_module(void) 630 { 631 int ret; 632 633 pr_info("%s\n", igb_driver_string); 634 pr_info("%s\n", igb_copyright); 635 636 #ifdef CONFIG_IGB_DCA 637 dca_register_notify(&dca_notifier); 638 #endif 639 ret = pci_register_driver(&igb_driver); 640 return ret; 641 } 642 643 module_init(igb_init_module); 644 645 /** 646 * igb_exit_module - Driver Exit Cleanup Routine 647 * 648 * igb_exit_module is called just before the driver is removed 649 * from memory. 650 **/ 651 static void __exit igb_exit_module(void) 652 { 653 #ifdef CONFIG_IGB_DCA 654 dca_unregister_notify(&dca_notifier); 655 #endif 656 pci_unregister_driver(&igb_driver); 657 } 658 659 module_exit(igb_exit_module); 660 661 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 662 /** 663 * igb_cache_ring_register - Descriptor ring to register mapping 664 * @adapter: board private structure to initialize 665 * 666 * Once we know the feature-set enabled for the device, we'll cache 667 * the register offset the descriptor ring is assigned to. 668 **/ 669 static void igb_cache_ring_register(struct igb_adapter *adapter) 670 { 671 int i = 0, j = 0; 672 u32 rbase_offset = adapter->vfs_allocated_count; 673 674 switch (adapter->hw.mac.type) { 675 case e1000_82576: 676 /* The queues are allocated for virtualization such that VF 0 677 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 678 * In order to avoid collision we start at the first free queue 679 * and continue consuming queues in the same sequence 680 */ 681 if (adapter->vfs_allocated_count) { 682 for (; i < adapter->rss_queues; i++) 683 adapter->rx_ring[i]->reg_idx = rbase_offset + 684 Q_IDX_82576(i); 685 } 686 fallthrough; 687 case e1000_82575: 688 case e1000_82580: 689 case e1000_i350: 690 case e1000_i354: 691 case e1000_i210: 692 case e1000_i211: 693 default: 694 for (; i < adapter->num_rx_queues; i++) 695 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 696 for (; j < adapter->num_tx_queues; j++) 697 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 698 break; 699 } 700 } 701 702 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 703 { 704 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 705 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 706 u32 value = 0; 707 708 if (E1000_REMOVED(hw_addr)) 709 return ~value; 710 711 value = readl(&hw_addr[reg]); 712 713 /* reads should not return all F's */ 714 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 715 struct net_device *netdev = igb->netdev; 716 hw->hw_addr = NULL; 717 netdev_err(netdev, "PCIe link lost\n"); 718 WARN(pci_device_is_present(igb->pdev), 719 "igb: Failed to read reg 0x%x!\n", reg); 720 } 721 722 return value; 723 } 724 725 /** 726 * igb_write_ivar - configure ivar for given MSI-X vector 727 * @hw: pointer to the HW structure 728 * @msix_vector: vector number we are allocating to a given ring 729 * @index: row index of IVAR register to write within IVAR table 730 * @offset: column offset of in IVAR, should be multiple of 8 731 * 732 * This function is intended to handle the writing of the IVAR register 733 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 734 * each containing an cause allocation for an Rx and Tx ring, and a 735 * variable number of rows depending on the number of queues supported. 736 **/ 737 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 738 int index, int offset) 739 { 740 u32 ivar = array_rd32(E1000_IVAR0, index); 741 742 /* clear any bits that are currently set */ 743 ivar &= ~((u32)0xFF << offset); 744 745 /* write vector and valid bit */ 746 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 747 748 array_wr32(E1000_IVAR0, index, ivar); 749 } 750 751 #define IGB_N0_QUEUE -1 752 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 753 { 754 struct igb_adapter *adapter = q_vector->adapter; 755 struct e1000_hw *hw = &adapter->hw; 756 int rx_queue = IGB_N0_QUEUE; 757 int tx_queue = IGB_N0_QUEUE; 758 u32 msixbm = 0; 759 760 if (q_vector->rx.ring) 761 rx_queue = q_vector->rx.ring->reg_idx; 762 if (q_vector->tx.ring) 763 tx_queue = q_vector->tx.ring->reg_idx; 764 765 switch (hw->mac.type) { 766 case e1000_82575: 767 /* The 82575 assigns vectors using a bitmask, which matches the 768 * bitmask for the EICR/EIMS/EIMC registers. To assign one 769 * or more queues to a vector, we write the appropriate bits 770 * into the MSIXBM register for that vector. 771 */ 772 if (rx_queue > IGB_N0_QUEUE) 773 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 774 if (tx_queue > IGB_N0_QUEUE) 775 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 776 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 777 msixbm |= E1000_EIMS_OTHER; 778 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 779 q_vector->eims_value = msixbm; 780 break; 781 case e1000_82576: 782 /* 82576 uses a table that essentially consists of 2 columns 783 * with 8 rows. The ordering is column-major so we use the 784 * lower 3 bits as the row index, and the 4th bit as the 785 * column offset. 786 */ 787 if (rx_queue > IGB_N0_QUEUE) 788 igb_write_ivar(hw, msix_vector, 789 rx_queue & 0x7, 790 (rx_queue & 0x8) << 1); 791 if (tx_queue > IGB_N0_QUEUE) 792 igb_write_ivar(hw, msix_vector, 793 tx_queue & 0x7, 794 ((tx_queue & 0x8) << 1) + 8); 795 q_vector->eims_value = BIT(msix_vector); 796 break; 797 case e1000_82580: 798 case e1000_i350: 799 case e1000_i354: 800 case e1000_i210: 801 case e1000_i211: 802 /* On 82580 and newer adapters the scheme is similar to 82576 803 * however instead of ordering column-major we have things 804 * ordered row-major. So we traverse the table by using 805 * bit 0 as the column offset, and the remaining bits as the 806 * row index. 807 */ 808 if (rx_queue > IGB_N0_QUEUE) 809 igb_write_ivar(hw, msix_vector, 810 rx_queue >> 1, 811 (rx_queue & 0x1) << 4); 812 if (tx_queue > IGB_N0_QUEUE) 813 igb_write_ivar(hw, msix_vector, 814 tx_queue >> 1, 815 ((tx_queue & 0x1) << 4) + 8); 816 q_vector->eims_value = BIT(msix_vector); 817 break; 818 default: 819 BUG(); 820 break; 821 } 822 823 /* add q_vector eims value to global eims_enable_mask */ 824 adapter->eims_enable_mask |= q_vector->eims_value; 825 826 /* configure q_vector to set itr on first interrupt */ 827 q_vector->set_itr = 1; 828 } 829 830 /** 831 * igb_configure_msix - Configure MSI-X hardware 832 * @adapter: board private structure to initialize 833 * 834 * igb_configure_msix sets up the hardware to properly 835 * generate MSI-X interrupts. 836 **/ 837 static void igb_configure_msix(struct igb_adapter *adapter) 838 { 839 u32 tmp; 840 int i, vector = 0; 841 struct e1000_hw *hw = &adapter->hw; 842 843 adapter->eims_enable_mask = 0; 844 845 /* set vector for other causes, i.e. link changes */ 846 switch (hw->mac.type) { 847 case e1000_82575: 848 tmp = rd32(E1000_CTRL_EXT); 849 /* enable MSI-X PBA support*/ 850 tmp |= E1000_CTRL_EXT_PBA_CLR; 851 852 /* Auto-Mask interrupts upon ICR read. */ 853 tmp |= E1000_CTRL_EXT_EIAME; 854 tmp |= E1000_CTRL_EXT_IRCA; 855 856 wr32(E1000_CTRL_EXT, tmp); 857 858 /* enable msix_other interrupt */ 859 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 860 adapter->eims_other = E1000_EIMS_OTHER; 861 862 break; 863 864 case e1000_82576: 865 case e1000_82580: 866 case e1000_i350: 867 case e1000_i354: 868 case e1000_i210: 869 case e1000_i211: 870 /* Turn on MSI-X capability first, or our settings 871 * won't stick. And it will take days to debug. 872 */ 873 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 874 E1000_GPIE_PBA | E1000_GPIE_EIAME | 875 E1000_GPIE_NSICR); 876 877 /* enable msix_other interrupt */ 878 adapter->eims_other = BIT(vector); 879 tmp = (vector++ | E1000_IVAR_VALID) << 8; 880 881 wr32(E1000_IVAR_MISC, tmp); 882 break; 883 default: 884 /* do nothing, since nothing else supports MSI-X */ 885 break; 886 } /* switch (hw->mac.type) */ 887 888 adapter->eims_enable_mask |= adapter->eims_other; 889 890 for (i = 0; i < adapter->num_q_vectors; i++) 891 igb_assign_vector(adapter->q_vector[i], vector++); 892 893 wrfl(); 894 } 895 896 /** 897 * igb_request_msix - Initialize MSI-X interrupts 898 * @adapter: board private structure to initialize 899 * 900 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 901 * kernel. 902 **/ 903 static int igb_request_msix(struct igb_adapter *adapter) 904 { 905 unsigned int num_q_vectors = adapter->num_q_vectors; 906 struct net_device *netdev = adapter->netdev; 907 int i, err = 0, vector = 0, free_vector = 0; 908 909 err = request_irq(adapter->msix_entries[vector].vector, 910 igb_msix_other, 0, netdev->name, adapter); 911 if (err) 912 goto err_out; 913 914 if (num_q_vectors > MAX_Q_VECTORS) { 915 num_q_vectors = MAX_Q_VECTORS; 916 dev_warn(&adapter->pdev->dev, 917 "The number of queue vectors (%d) is higher than max allowed (%d)\n", 918 adapter->num_q_vectors, MAX_Q_VECTORS); 919 } 920 for (i = 0; i < num_q_vectors; i++) { 921 struct igb_q_vector *q_vector = adapter->q_vector[i]; 922 923 vector++; 924 925 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 926 927 if (q_vector->rx.ring && q_vector->tx.ring) 928 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 929 q_vector->rx.ring->queue_index); 930 else if (q_vector->tx.ring) 931 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 932 q_vector->tx.ring->queue_index); 933 else if (q_vector->rx.ring) 934 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 935 q_vector->rx.ring->queue_index); 936 else 937 sprintf(q_vector->name, "%s-unused", netdev->name); 938 939 err = request_irq(adapter->msix_entries[vector].vector, 940 igb_msix_ring, 0, q_vector->name, 941 q_vector); 942 if (err) 943 goto err_free; 944 } 945 946 igb_configure_msix(adapter); 947 return 0; 948 949 err_free: 950 /* free already assigned IRQs */ 951 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 952 953 vector--; 954 for (i = 0; i < vector; i++) { 955 free_irq(adapter->msix_entries[free_vector++].vector, 956 adapter->q_vector[i]); 957 } 958 err_out: 959 return err; 960 } 961 962 /** 963 * igb_free_q_vector - Free memory allocated for specific interrupt vector 964 * @adapter: board private structure to initialize 965 * @v_idx: Index of vector to be freed 966 * 967 * This function frees the memory allocated to the q_vector. 968 **/ 969 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 970 { 971 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 972 973 adapter->q_vector[v_idx] = NULL; 974 975 /* igb_get_stats64() might access the rings on this vector, 976 * we must wait a grace period before freeing it. 977 */ 978 if (q_vector) 979 kfree_rcu(q_vector, rcu); 980 } 981 982 /** 983 * igb_reset_q_vector - Reset config for interrupt vector 984 * @adapter: board private structure to initialize 985 * @v_idx: Index of vector to be reset 986 * 987 * If NAPI is enabled it will delete any references to the 988 * NAPI struct. This is preparation for igb_free_q_vector. 989 **/ 990 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 991 { 992 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 993 994 /* Coming from igb_set_interrupt_capability, the vectors are not yet 995 * allocated. So, q_vector is NULL so we should stop here. 996 */ 997 if (!q_vector) 998 return; 999 1000 if (q_vector->tx.ring) 1001 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1002 1003 if (q_vector->rx.ring) 1004 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1005 1006 netif_napi_del(&q_vector->napi); 1007 1008 } 1009 1010 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1011 { 1012 int v_idx = adapter->num_q_vectors; 1013 1014 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1015 pci_disable_msix(adapter->pdev); 1016 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1017 pci_disable_msi(adapter->pdev); 1018 1019 while (v_idx--) 1020 igb_reset_q_vector(adapter, v_idx); 1021 } 1022 1023 /** 1024 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1025 * @adapter: board private structure to initialize 1026 * 1027 * This function frees the memory allocated to the q_vectors. In addition if 1028 * NAPI is enabled it will delete any references to the NAPI struct prior 1029 * to freeing the q_vector. 1030 **/ 1031 static void igb_free_q_vectors(struct igb_adapter *adapter) 1032 { 1033 int v_idx = adapter->num_q_vectors; 1034 1035 adapter->num_tx_queues = 0; 1036 adapter->num_rx_queues = 0; 1037 adapter->num_q_vectors = 0; 1038 1039 while (v_idx--) { 1040 igb_reset_q_vector(adapter, v_idx); 1041 igb_free_q_vector(adapter, v_idx); 1042 } 1043 } 1044 1045 /** 1046 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1047 * @adapter: board private structure to initialize 1048 * 1049 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1050 * MSI-X interrupts allocated. 1051 */ 1052 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1053 { 1054 igb_free_q_vectors(adapter); 1055 igb_reset_interrupt_capability(adapter); 1056 } 1057 1058 /** 1059 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1060 * @adapter: board private structure to initialize 1061 * @msix: boolean value of MSIX capability 1062 * 1063 * Attempt to configure interrupts using the best available 1064 * capabilities of the hardware and kernel. 1065 **/ 1066 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1067 { 1068 int err; 1069 int numvecs, i; 1070 1071 if (!msix) 1072 goto msi_only; 1073 adapter->flags |= IGB_FLAG_HAS_MSIX; 1074 1075 /* Number of supported queues. */ 1076 adapter->num_rx_queues = adapter->rss_queues; 1077 if (adapter->vfs_allocated_count) 1078 adapter->num_tx_queues = 1; 1079 else 1080 adapter->num_tx_queues = adapter->rss_queues; 1081 1082 /* start with one vector for every Rx queue */ 1083 numvecs = adapter->num_rx_queues; 1084 1085 /* if Tx handler is separate add 1 for every Tx queue */ 1086 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1087 numvecs += adapter->num_tx_queues; 1088 1089 /* store the number of vectors reserved for queues */ 1090 adapter->num_q_vectors = numvecs; 1091 1092 /* add 1 vector for link status interrupts */ 1093 numvecs++; 1094 for (i = 0; i < numvecs; i++) 1095 adapter->msix_entries[i].entry = i; 1096 1097 err = pci_enable_msix_range(adapter->pdev, 1098 adapter->msix_entries, 1099 numvecs, 1100 numvecs); 1101 if (err > 0) 1102 return; 1103 1104 igb_reset_interrupt_capability(adapter); 1105 1106 /* If we can't do MSI-X, try MSI */ 1107 msi_only: 1108 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1109 #ifdef CONFIG_PCI_IOV 1110 /* disable SR-IOV for non MSI-X configurations */ 1111 if (adapter->vf_data) { 1112 struct e1000_hw *hw = &adapter->hw; 1113 /* disable iov and allow time for transactions to clear */ 1114 pci_disable_sriov(adapter->pdev); 1115 msleep(500); 1116 1117 kfree(adapter->vf_mac_list); 1118 adapter->vf_mac_list = NULL; 1119 kfree(adapter->vf_data); 1120 adapter->vf_data = NULL; 1121 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1122 wrfl(); 1123 msleep(100); 1124 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1125 } 1126 #endif 1127 adapter->vfs_allocated_count = 0; 1128 adapter->rss_queues = 1; 1129 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1130 adapter->num_rx_queues = 1; 1131 adapter->num_tx_queues = 1; 1132 adapter->num_q_vectors = 1; 1133 if (!pci_enable_msi(adapter->pdev)) 1134 adapter->flags |= IGB_FLAG_HAS_MSI; 1135 } 1136 1137 static void igb_add_ring(struct igb_ring *ring, 1138 struct igb_ring_container *head) 1139 { 1140 head->ring = ring; 1141 head->count++; 1142 } 1143 1144 /** 1145 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1146 * @adapter: board private structure to initialize 1147 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1148 * @v_idx: index of vector in adapter struct 1149 * @txr_count: total number of Tx rings to allocate 1150 * @txr_idx: index of first Tx ring to allocate 1151 * @rxr_count: total number of Rx rings to allocate 1152 * @rxr_idx: index of first Rx ring to allocate 1153 * 1154 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1155 **/ 1156 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1157 int v_count, int v_idx, 1158 int txr_count, int txr_idx, 1159 int rxr_count, int rxr_idx) 1160 { 1161 struct igb_q_vector *q_vector; 1162 struct igb_ring *ring; 1163 int ring_count; 1164 size_t size; 1165 1166 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1167 if (txr_count > 1 || rxr_count > 1) 1168 return -ENOMEM; 1169 1170 ring_count = txr_count + rxr_count; 1171 size = kmalloc_size_roundup(struct_size(q_vector, ring, ring_count)); 1172 1173 /* allocate q_vector and rings */ 1174 q_vector = adapter->q_vector[v_idx]; 1175 if (!q_vector) { 1176 q_vector = kzalloc(size, GFP_KERNEL); 1177 } else if (size > ksize(q_vector)) { 1178 struct igb_q_vector *new_q_vector; 1179 1180 new_q_vector = kzalloc(size, GFP_KERNEL); 1181 if (new_q_vector) 1182 kfree_rcu(q_vector, rcu); 1183 q_vector = new_q_vector; 1184 } else { 1185 memset(q_vector, 0, size); 1186 } 1187 if (!q_vector) 1188 return -ENOMEM; 1189 1190 /* initialize NAPI */ 1191 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll); 1192 1193 /* tie q_vector and adapter together */ 1194 adapter->q_vector[v_idx] = q_vector; 1195 q_vector->adapter = adapter; 1196 1197 /* initialize work limits */ 1198 q_vector->tx.work_limit = adapter->tx_work_limit; 1199 1200 /* initialize ITR configuration */ 1201 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1202 q_vector->itr_val = IGB_START_ITR; 1203 1204 /* initialize pointer to rings */ 1205 ring = q_vector->ring; 1206 1207 /* intialize ITR */ 1208 if (rxr_count) { 1209 /* rx or rx/tx vector */ 1210 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1211 q_vector->itr_val = adapter->rx_itr_setting; 1212 } else { 1213 /* tx only vector */ 1214 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1215 q_vector->itr_val = adapter->tx_itr_setting; 1216 } 1217 1218 if (txr_count) { 1219 /* assign generic ring traits */ 1220 ring->dev = &adapter->pdev->dev; 1221 ring->netdev = adapter->netdev; 1222 1223 /* configure backlink on ring */ 1224 ring->q_vector = q_vector; 1225 1226 /* update q_vector Tx values */ 1227 igb_add_ring(ring, &q_vector->tx); 1228 1229 /* For 82575, context index must be unique per ring. */ 1230 if (adapter->hw.mac.type == e1000_82575) 1231 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1232 1233 /* apply Tx specific ring traits */ 1234 ring->count = adapter->tx_ring_count; 1235 ring->queue_index = txr_idx; 1236 1237 ring->cbs_enable = false; 1238 ring->idleslope = 0; 1239 ring->sendslope = 0; 1240 ring->hicredit = 0; 1241 ring->locredit = 0; 1242 1243 u64_stats_init(&ring->tx_syncp); 1244 u64_stats_init(&ring->tx_syncp2); 1245 1246 /* assign ring to adapter */ 1247 adapter->tx_ring[txr_idx] = ring; 1248 1249 /* push pointer to next ring */ 1250 ring++; 1251 } 1252 1253 if (rxr_count) { 1254 /* assign generic ring traits */ 1255 ring->dev = &adapter->pdev->dev; 1256 ring->netdev = adapter->netdev; 1257 1258 /* configure backlink on ring */ 1259 ring->q_vector = q_vector; 1260 1261 /* update q_vector Rx values */ 1262 igb_add_ring(ring, &q_vector->rx); 1263 1264 /* set flag indicating ring supports SCTP checksum offload */ 1265 if (adapter->hw.mac.type >= e1000_82576) 1266 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1267 1268 /* On i350, i354, i210, and i211, loopback VLAN packets 1269 * have the tag byte-swapped. 1270 */ 1271 if (adapter->hw.mac.type >= e1000_i350) 1272 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1273 1274 /* apply Rx specific ring traits */ 1275 ring->count = adapter->rx_ring_count; 1276 ring->queue_index = rxr_idx; 1277 1278 u64_stats_init(&ring->rx_syncp); 1279 1280 /* assign ring to adapter */ 1281 adapter->rx_ring[rxr_idx] = ring; 1282 } 1283 1284 return 0; 1285 } 1286 1287 1288 /** 1289 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1290 * @adapter: board private structure to initialize 1291 * 1292 * We allocate one q_vector per queue interrupt. If allocation fails we 1293 * return -ENOMEM. 1294 **/ 1295 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1296 { 1297 int q_vectors = adapter->num_q_vectors; 1298 int rxr_remaining = adapter->num_rx_queues; 1299 int txr_remaining = adapter->num_tx_queues; 1300 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1301 int err; 1302 1303 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1304 for (; rxr_remaining; v_idx++) { 1305 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1306 0, 0, 1, rxr_idx); 1307 1308 if (err) 1309 goto err_out; 1310 1311 /* update counts and index */ 1312 rxr_remaining--; 1313 rxr_idx++; 1314 } 1315 } 1316 1317 for (; v_idx < q_vectors; v_idx++) { 1318 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1319 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1320 1321 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1322 tqpv, txr_idx, rqpv, rxr_idx); 1323 1324 if (err) 1325 goto err_out; 1326 1327 /* update counts and index */ 1328 rxr_remaining -= rqpv; 1329 txr_remaining -= tqpv; 1330 rxr_idx++; 1331 txr_idx++; 1332 } 1333 1334 return 0; 1335 1336 err_out: 1337 adapter->num_tx_queues = 0; 1338 adapter->num_rx_queues = 0; 1339 adapter->num_q_vectors = 0; 1340 1341 while (v_idx--) 1342 igb_free_q_vector(adapter, v_idx); 1343 1344 return -ENOMEM; 1345 } 1346 1347 /** 1348 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1349 * @adapter: board private structure to initialize 1350 * @msix: boolean value of MSIX capability 1351 * 1352 * This function initializes the interrupts and allocates all of the queues. 1353 **/ 1354 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1355 { 1356 struct pci_dev *pdev = adapter->pdev; 1357 int err; 1358 1359 igb_set_interrupt_capability(adapter, msix); 1360 1361 err = igb_alloc_q_vectors(adapter); 1362 if (err) { 1363 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1364 goto err_alloc_q_vectors; 1365 } 1366 1367 igb_cache_ring_register(adapter); 1368 1369 return 0; 1370 1371 err_alloc_q_vectors: 1372 igb_reset_interrupt_capability(adapter); 1373 return err; 1374 } 1375 1376 /** 1377 * igb_request_irq - initialize interrupts 1378 * @adapter: board private structure to initialize 1379 * 1380 * Attempts to configure interrupts using the best available 1381 * capabilities of the hardware and kernel. 1382 **/ 1383 static int igb_request_irq(struct igb_adapter *adapter) 1384 { 1385 struct net_device *netdev = adapter->netdev; 1386 struct pci_dev *pdev = adapter->pdev; 1387 int err = 0; 1388 1389 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1390 err = igb_request_msix(adapter); 1391 if (!err) 1392 goto request_done; 1393 /* fall back to MSI */ 1394 igb_free_all_tx_resources(adapter); 1395 igb_free_all_rx_resources(adapter); 1396 1397 igb_clear_interrupt_scheme(adapter); 1398 err = igb_init_interrupt_scheme(adapter, false); 1399 if (err) 1400 goto request_done; 1401 1402 igb_setup_all_tx_resources(adapter); 1403 igb_setup_all_rx_resources(adapter); 1404 igb_configure(adapter); 1405 } 1406 1407 igb_assign_vector(adapter->q_vector[0], 0); 1408 1409 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1410 err = request_irq(pdev->irq, igb_intr_msi, 0, 1411 netdev->name, adapter); 1412 if (!err) 1413 goto request_done; 1414 1415 /* fall back to legacy interrupts */ 1416 igb_reset_interrupt_capability(adapter); 1417 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1418 } 1419 1420 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1421 netdev->name, adapter); 1422 1423 if (err) 1424 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1425 err); 1426 1427 request_done: 1428 return err; 1429 } 1430 1431 static void igb_free_irq(struct igb_adapter *adapter) 1432 { 1433 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1434 int vector = 0, i; 1435 1436 free_irq(adapter->msix_entries[vector++].vector, adapter); 1437 1438 for (i = 0; i < adapter->num_q_vectors; i++) 1439 free_irq(adapter->msix_entries[vector++].vector, 1440 adapter->q_vector[i]); 1441 } else { 1442 free_irq(adapter->pdev->irq, adapter); 1443 } 1444 } 1445 1446 /** 1447 * igb_irq_disable - Mask off interrupt generation on the NIC 1448 * @adapter: board private structure 1449 **/ 1450 static void igb_irq_disable(struct igb_adapter *adapter) 1451 { 1452 struct e1000_hw *hw = &adapter->hw; 1453 1454 /* we need to be careful when disabling interrupts. The VFs are also 1455 * mapped into these registers and so clearing the bits can cause 1456 * issues on the VF drivers so we only need to clear what we set 1457 */ 1458 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1459 u32 regval = rd32(E1000_EIAM); 1460 1461 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1462 wr32(E1000_EIMC, adapter->eims_enable_mask); 1463 regval = rd32(E1000_EIAC); 1464 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1465 } 1466 1467 wr32(E1000_IAM, 0); 1468 wr32(E1000_IMC, ~0); 1469 wrfl(); 1470 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1471 int i; 1472 1473 for (i = 0; i < adapter->num_q_vectors; i++) 1474 synchronize_irq(adapter->msix_entries[i].vector); 1475 } else { 1476 synchronize_irq(adapter->pdev->irq); 1477 } 1478 } 1479 1480 /** 1481 * igb_irq_enable - Enable default interrupt generation settings 1482 * @adapter: board private structure 1483 **/ 1484 static void igb_irq_enable(struct igb_adapter *adapter) 1485 { 1486 struct e1000_hw *hw = &adapter->hw; 1487 1488 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1489 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1490 u32 regval = rd32(E1000_EIAC); 1491 1492 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1493 regval = rd32(E1000_EIAM); 1494 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1495 wr32(E1000_EIMS, adapter->eims_enable_mask); 1496 if (adapter->vfs_allocated_count) { 1497 wr32(E1000_MBVFIMR, 0xFF); 1498 ims |= E1000_IMS_VMMB; 1499 } 1500 wr32(E1000_IMS, ims); 1501 } else { 1502 wr32(E1000_IMS, IMS_ENABLE_MASK | 1503 E1000_IMS_DRSTA); 1504 wr32(E1000_IAM, IMS_ENABLE_MASK | 1505 E1000_IMS_DRSTA); 1506 } 1507 } 1508 1509 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1510 { 1511 struct e1000_hw *hw = &adapter->hw; 1512 u16 pf_id = adapter->vfs_allocated_count; 1513 u16 vid = adapter->hw.mng_cookie.vlan_id; 1514 u16 old_vid = adapter->mng_vlan_id; 1515 1516 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1517 /* add VID to filter table */ 1518 igb_vfta_set(hw, vid, pf_id, true, true); 1519 adapter->mng_vlan_id = vid; 1520 } else { 1521 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1522 } 1523 1524 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1525 (vid != old_vid) && 1526 !test_bit(old_vid, adapter->active_vlans)) { 1527 /* remove VID from filter table */ 1528 igb_vfta_set(hw, vid, pf_id, false, true); 1529 } 1530 } 1531 1532 /** 1533 * igb_release_hw_control - release control of the h/w to f/w 1534 * @adapter: address of board private structure 1535 * 1536 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1537 * For ASF and Pass Through versions of f/w this means that the 1538 * driver is no longer loaded. 1539 **/ 1540 static void igb_release_hw_control(struct igb_adapter *adapter) 1541 { 1542 struct e1000_hw *hw = &adapter->hw; 1543 u32 ctrl_ext; 1544 1545 /* Let firmware take over control of h/w */ 1546 ctrl_ext = rd32(E1000_CTRL_EXT); 1547 wr32(E1000_CTRL_EXT, 1548 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1549 } 1550 1551 /** 1552 * igb_get_hw_control - get control of the h/w from f/w 1553 * @adapter: address of board private structure 1554 * 1555 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1556 * For ASF and Pass Through versions of f/w this means that 1557 * the driver is loaded. 1558 **/ 1559 static void igb_get_hw_control(struct igb_adapter *adapter) 1560 { 1561 struct e1000_hw *hw = &adapter->hw; 1562 u32 ctrl_ext; 1563 1564 /* Let firmware know the driver has taken over */ 1565 ctrl_ext = rd32(E1000_CTRL_EXT); 1566 wr32(E1000_CTRL_EXT, 1567 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1568 } 1569 1570 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1571 { 1572 struct net_device *netdev = adapter->netdev; 1573 struct e1000_hw *hw = &adapter->hw; 1574 1575 WARN_ON(hw->mac.type != e1000_i210); 1576 1577 if (enable) 1578 adapter->flags |= IGB_FLAG_FQTSS; 1579 else 1580 adapter->flags &= ~IGB_FLAG_FQTSS; 1581 1582 if (netif_running(netdev)) 1583 schedule_work(&adapter->reset_task); 1584 } 1585 1586 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1587 { 1588 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1589 } 1590 1591 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1592 enum tx_queue_prio prio) 1593 { 1594 u32 val; 1595 1596 WARN_ON(hw->mac.type != e1000_i210); 1597 WARN_ON(queue < 0 || queue > 4); 1598 1599 val = rd32(E1000_I210_TXDCTL(queue)); 1600 1601 if (prio == TX_QUEUE_PRIO_HIGH) 1602 val |= E1000_TXDCTL_PRIORITY; 1603 else 1604 val &= ~E1000_TXDCTL_PRIORITY; 1605 1606 wr32(E1000_I210_TXDCTL(queue), val); 1607 } 1608 1609 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1610 { 1611 u32 val; 1612 1613 WARN_ON(hw->mac.type != e1000_i210); 1614 WARN_ON(queue < 0 || queue > 1); 1615 1616 val = rd32(E1000_I210_TQAVCC(queue)); 1617 1618 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1619 val |= E1000_TQAVCC_QUEUEMODE; 1620 else 1621 val &= ~E1000_TQAVCC_QUEUEMODE; 1622 1623 wr32(E1000_I210_TQAVCC(queue), val); 1624 } 1625 1626 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1627 { 1628 int i; 1629 1630 for (i = 0; i < adapter->num_tx_queues; i++) { 1631 if (adapter->tx_ring[i]->cbs_enable) 1632 return true; 1633 } 1634 1635 return false; 1636 } 1637 1638 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1639 { 1640 int i; 1641 1642 for (i = 0; i < adapter->num_tx_queues; i++) { 1643 if (adapter->tx_ring[i]->launchtime_enable) 1644 return true; 1645 } 1646 1647 return false; 1648 } 1649 1650 /** 1651 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1652 * @adapter: pointer to adapter struct 1653 * @queue: queue number 1654 * 1655 * Configure CBS and Launchtime for a given hardware queue. 1656 * Parameters are retrieved from the correct Tx ring, so 1657 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1658 * for setting those correctly prior to this function being called. 1659 **/ 1660 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1661 { 1662 struct net_device *netdev = adapter->netdev; 1663 struct e1000_hw *hw = &adapter->hw; 1664 struct igb_ring *ring; 1665 u32 tqavcc, tqavctrl; 1666 u16 value; 1667 1668 WARN_ON(hw->mac.type != e1000_i210); 1669 WARN_ON(queue < 0 || queue > 1); 1670 ring = adapter->tx_ring[queue]; 1671 1672 /* If any of the Qav features is enabled, configure queues as SR and 1673 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1674 * as SP. 1675 */ 1676 if (ring->cbs_enable || ring->launchtime_enable) { 1677 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1678 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1679 } else { 1680 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1681 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1682 } 1683 1684 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1685 if (ring->cbs_enable || queue == 0) { 1686 /* i210 does not allow the queue 0 to be in the Strict 1687 * Priority mode while the Qav mode is enabled, so, 1688 * instead of disabling strict priority mode, we give 1689 * queue 0 the maximum of credits possible. 1690 * 1691 * See section 8.12.19 of the i210 datasheet, "Note: 1692 * Queue0 QueueMode must be set to 1b when 1693 * TransmitMode is set to Qav." 1694 */ 1695 if (queue == 0 && !ring->cbs_enable) { 1696 /* max "linkspeed" idleslope in kbps */ 1697 ring->idleslope = 1000000; 1698 ring->hicredit = ETH_FRAME_LEN; 1699 } 1700 1701 /* Always set data transfer arbitration to credit-based 1702 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1703 * the queues. 1704 */ 1705 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1706 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1707 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1708 1709 /* According to i210 datasheet section 7.2.7.7, we should set 1710 * the 'idleSlope' field from TQAVCC register following the 1711 * equation: 1712 * 1713 * For 100 Mbps link speed: 1714 * 1715 * value = BW * 0x7735 * 0.2 (E1) 1716 * 1717 * For 1000Mbps link speed: 1718 * 1719 * value = BW * 0x7735 * 2 (E2) 1720 * 1721 * E1 and E2 can be merged into one equation as shown below. 1722 * Note that 'link-speed' is in Mbps. 1723 * 1724 * value = BW * 0x7735 * 2 * link-speed 1725 * -------------- (E3) 1726 * 1000 1727 * 1728 * 'BW' is the percentage bandwidth out of full link speed 1729 * which can be found with the following equation. Note that 1730 * idleSlope here is the parameter from this function which 1731 * is in kbps. 1732 * 1733 * BW = idleSlope 1734 * ----------------- (E4) 1735 * link-speed * 1000 1736 * 1737 * That said, we can come up with a generic equation to 1738 * calculate the value we should set it TQAVCC register by 1739 * replacing 'BW' in E3 by E4. The resulting equation is: 1740 * 1741 * value = idleSlope * 0x7735 * 2 * link-speed 1742 * ----------------- -------------- (E5) 1743 * link-speed * 1000 1000 1744 * 1745 * 'link-speed' is present in both sides of the fraction so 1746 * it is canceled out. The final equation is the following: 1747 * 1748 * value = idleSlope * 61034 1749 * ----------------- (E6) 1750 * 1000000 1751 * 1752 * NOTE: For i210, given the above, we can see that idleslope 1753 * is represented in 16.38431 kbps units by the value at 1754 * the TQAVCC register (1Gbps / 61034), which reduces 1755 * the granularity for idleslope increments. 1756 * For instance, if you want to configure a 2576kbps 1757 * idleslope, the value to be written on the register 1758 * would have to be 157.23. If rounded down, you end 1759 * up with less bandwidth available than originally 1760 * required (~2572 kbps). If rounded up, you end up 1761 * with a higher bandwidth (~2589 kbps). Below the 1762 * approach we take is to always round up the 1763 * calculated value, so the resulting bandwidth might 1764 * be slightly higher for some configurations. 1765 */ 1766 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1767 1768 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1769 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1770 tqavcc |= value; 1771 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1772 1773 wr32(E1000_I210_TQAVHC(queue), 1774 0x80000000 + ring->hicredit * 0x7735); 1775 } else { 1776 1777 /* Set idleSlope to zero. */ 1778 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1779 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1780 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1781 1782 /* Set hiCredit to zero. */ 1783 wr32(E1000_I210_TQAVHC(queue), 0); 1784 1785 /* If CBS is not enabled for any queues anymore, then return to 1786 * the default state of Data Transmission Arbitration on 1787 * TQAVCTRL. 1788 */ 1789 if (!is_any_cbs_enabled(adapter)) { 1790 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1791 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1792 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1793 } 1794 } 1795 1796 /* If LaunchTime is enabled, set DataTranTIM. */ 1797 if (ring->launchtime_enable) { 1798 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1799 * for any of the SR queues, and configure fetchtime delta. 1800 * XXX NOTE: 1801 * - LaunchTime will be enabled for all SR queues. 1802 * - A fixed offset can be added relative to the launch 1803 * time of all packets if configured at reg LAUNCH_OS0. 1804 * We are keeping it as 0 for now (default value). 1805 */ 1806 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1807 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1808 E1000_TQAVCTRL_FETCHTIME_DELTA; 1809 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1810 } else { 1811 /* If Launchtime is not enabled for any SR queues anymore, 1812 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1813 * effectively disabling Launchtime. 1814 */ 1815 if (!is_any_txtime_enabled(adapter)) { 1816 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1817 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1818 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1819 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1820 } 1821 } 1822 1823 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1824 * CBS are not configurable by software so we don't do any 'controller 1825 * configuration' in respect to these parameters. 1826 */ 1827 1828 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1829 ring->cbs_enable ? "enabled" : "disabled", 1830 ring->launchtime_enable ? "enabled" : "disabled", 1831 queue, 1832 ring->idleslope, ring->sendslope, 1833 ring->hicredit, ring->locredit); 1834 } 1835 1836 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1837 bool enable) 1838 { 1839 struct igb_ring *ring; 1840 1841 if (queue < 0 || queue > adapter->num_tx_queues) 1842 return -EINVAL; 1843 1844 ring = adapter->tx_ring[queue]; 1845 ring->launchtime_enable = enable; 1846 1847 return 0; 1848 } 1849 1850 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1851 bool enable, int idleslope, int sendslope, 1852 int hicredit, int locredit) 1853 { 1854 struct igb_ring *ring; 1855 1856 if (queue < 0 || queue > adapter->num_tx_queues) 1857 return -EINVAL; 1858 1859 ring = adapter->tx_ring[queue]; 1860 1861 ring->cbs_enable = enable; 1862 ring->idleslope = idleslope; 1863 ring->sendslope = sendslope; 1864 ring->hicredit = hicredit; 1865 ring->locredit = locredit; 1866 1867 return 0; 1868 } 1869 1870 /** 1871 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1872 * @adapter: pointer to adapter struct 1873 * 1874 * Configure TQAVCTRL register switching the controller's Tx mode 1875 * if FQTSS mode is enabled or disabled. Additionally, will issue 1876 * a call to igb_config_tx_modes() per queue so any previously saved 1877 * Tx parameters are applied. 1878 **/ 1879 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1880 { 1881 struct net_device *netdev = adapter->netdev; 1882 struct e1000_hw *hw = &adapter->hw; 1883 u32 val; 1884 1885 /* Only i210 controller supports changing the transmission mode. */ 1886 if (hw->mac.type != e1000_i210) 1887 return; 1888 1889 if (is_fqtss_enabled(adapter)) { 1890 int i, max_queue; 1891 1892 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1893 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1894 * so SP queues wait for SR ones. 1895 */ 1896 val = rd32(E1000_I210_TQAVCTRL); 1897 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1898 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1899 wr32(E1000_I210_TQAVCTRL, val); 1900 1901 /* Configure Tx and Rx packet buffers sizes as described in 1902 * i210 datasheet section 7.2.7.7. 1903 */ 1904 val = rd32(E1000_TXPBS); 1905 val &= ~I210_TXPBSIZE_MASK; 1906 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB | 1907 I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB; 1908 wr32(E1000_TXPBS, val); 1909 1910 val = rd32(E1000_RXPBS); 1911 val &= ~I210_RXPBSIZE_MASK; 1912 val |= I210_RXPBSIZE_PB_30KB; 1913 wr32(E1000_RXPBS, val); 1914 1915 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1916 * register should not exceed the buffer size programmed in 1917 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1918 * so according to the datasheet we should set MAX_TPKT_SIZE to 1919 * 4kB / 64. 1920 * 1921 * However, when we do so, no frame from queue 2 and 3 are 1922 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1923 * or _equal_ to the buffer size programmed in TXPBS. For this 1924 * reason, we set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1925 */ 1926 val = (4096 - 1) / 64; 1927 wr32(E1000_I210_DTXMXPKTSZ, val); 1928 1929 /* Since FQTSS mode is enabled, apply any CBS configuration 1930 * previously set. If no previous CBS configuration has been 1931 * done, then the initial configuration is applied, which means 1932 * CBS is disabled. 1933 */ 1934 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1935 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1936 1937 for (i = 0; i < max_queue; i++) { 1938 igb_config_tx_modes(adapter, i); 1939 } 1940 } else { 1941 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1942 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1943 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1944 1945 val = rd32(E1000_I210_TQAVCTRL); 1946 /* According to Section 8.12.21, the other flags we've set when 1947 * enabling FQTSS are not relevant when disabling FQTSS so we 1948 * don't set they here. 1949 */ 1950 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1951 wr32(E1000_I210_TQAVCTRL, val); 1952 } 1953 1954 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1955 "enabled" : "disabled"); 1956 } 1957 1958 /** 1959 * igb_configure - configure the hardware for RX and TX 1960 * @adapter: private board structure 1961 **/ 1962 static void igb_configure(struct igb_adapter *adapter) 1963 { 1964 struct net_device *netdev = adapter->netdev; 1965 int i; 1966 1967 igb_get_hw_control(adapter); 1968 igb_set_rx_mode(netdev); 1969 igb_setup_tx_mode(adapter); 1970 1971 igb_restore_vlan(adapter); 1972 1973 igb_setup_tctl(adapter); 1974 igb_setup_mrqc(adapter); 1975 igb_setup_rctl(adapter); 1976 1977 igb_nfc_filter_restore(adapter); 1978 igb_configure_tx(adapter); 1979 igb_configure_rx(adapter); 1980 1981 igb_rx_fifo_flush_82575(&adapter->hw); 1982 1983 /* call igb_desc_unused which always leaves 1984 * at least 1 descriptor unused to make sure 1985 * next_to_use != next_to_clean 1986 */ 1987 for (i = 0; i < adapter->num_rx_queues; i++) { 1988 struct igb_ring *ring = adapter->rx_ring[i]; 1989 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1990 } 1991 } 1992 1993 /** 1994 * igb_power_up_link - Power up the phy/serdes link 1995 * @adapter: address of board private structure 1996 **/ 1997 void igb_power_up_link(struct igb_adapter *adapter) 1998 { 1999 igb_reset_phy(&adapter->hw); 2000 2001 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2002 igb_power_up_phy_copper(&adapter->hw); 2003 else 2004 igb_power_up_serdes_link_82575(&adapter->hw); 2005 2006 igb_setup_link(&adapter->hw); 2007 } 2008 2009 /** 2010 * igb_power_down_link - Power down the phy/serdes link 2011 * @adapter: address of board private structure 2012 */ 2013 static void igb_power_down_link(struct igb_adapter *adapter) 2014 { 2015 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2016 igb_power_down_phy_copper_82575(&adapter->hw); 2017 else 2018 igb_shutdown_serdes_link_82575(&adapter->hw); 2019 } 2020 2021 /** 2022 * igb_check_swap_media - Detect and switch function for Media Auto Sense 2023 * @adapter: address of the board private structure 2024 **/ 2025 static void igb_check_swap_media(struct igb_adapter *adapter) 2026 { 2027 struct e1000_hw *hw = &adapter->hw; 2028 u32 ctrl_ext, connsw; 2029 bool swap_now = false; 2030 2031 ctrl_ext = rd32(E1000_CTRL_EXT); 2032 connsw = rd32(E1000_CONNSW); 2033 2034 /* need to live swap if current media is copper and we have fiber/serdes 2035 * to go to. 2036 */ 2037 2038 if ((hw->phy.media_type == e1000_media_type_copper) && 2039 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2040 swap_now = true; 2041 } else if ((hw->phy.media_type != e1000_media_type_copper) && 2042 !(connsw & E1000_CONNSW_SERDESD)) { 2043 /* copper signal takes time to appear */ 2044 if (adapter->copper_tries < 4) { 2045 adapter->copper_tries++; 2046 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2047 wr32(E1000_CONNSW, connsw); 2048 return; 2049 } else { 2050 adapter->copper_tries = 0; 2051 if ((connsw & E1000_CONNSW_PHYSD) && 2052 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2053 swap_now = true; 2054 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2055 wr32(E1000_CONNSW, connsw); 2056 } 2057 } 2058 } 2059 2060 if (!swap_now) 2061 return; 2062 2063 switch (hw->phy.media_type) { 2064 case e1000_media_type_copper: 2065 netdev_info(adapter->netdev, 2066 "MAS: changing media to fiber/serdes\n"); 2067 ctrl_ext |= 2068 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2069 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2070 adapter->copper_tries = 0; 2071 break; 2072 case e1000_media_type_internal_serdes: 2073 case e1000_media_type_fiber: 2074 netdev_info(adapter->netdev, 2075 "MAS: changing media to copper\n"); 2076 ctrl_ext &= 2077 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2078 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2079 break; 2080 default: 2081 /* shouldn't get here during regular operation */ 2082 netdev_err(adapter->netdev, 2083 "AMS: Invalid media type found, returning\n"); 2084 break; 2085 } 2086 wr32(E1000_CTRL_EXT, ctrl_ext); 2087 } 2088 2089 /** 2090 * igb_up - Open the interface and prepare it to handle traffic 2091 * @adapter: board private structure 2092 **/ 2093 int igb_up(struct igb_adapter *adapter) 2094 { 2095 struct e1000_hw *hw = &adapter->hw; 2096 int i; 2097 2098 /* hardware has been reset, we need to reload some things */ 2099 igb_configure(adapter); 2100 2101 clear_bit(__IGB_DOWN, &adapter->state); 2102 2103 for (i = 0; i < adapter->num_q_vectors; i++) 2104 napi_enable(&(adapter->q_vector[i]->napi)); 2105 2106 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2107 igb_configure_msix(adapter); 2108 else 2109 igb_assign_vector(adapter->q_vector[0], 0); 2110 2111 /* Clear any pending interrupts. */ 2112 rd32(E1000_TSICR); 2113 rd32(E1000_ICR); 2114 igb_irq_enable(adapter); 2115 2116 /* notify VFs that reset has been completed */ 2117 if (adapter->vfs_allocated_count) { 2118 u32 reg_data = rd32(E1000_CTRL_EXT); 2119 2120 reg_data |= E1000_CTRL_EXT_PFRSTD; 2121 wr32(E1000_CTRL_EXT, reg_data); 2122 } 2123 2124 netif_tx_start_all_queues(adapter->netdev); 2125 2126 /* start the watchdog. */ 2127 hw->mac.get_link_status = 1; 2128 schedule_work(&adapter->watchdog_task); 2129 2130 if ((adapter->flags & IGB_FLAG_EEE) && 2131 (!hw->dev_spec._82575.eee_disable)) 2132 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2133 2134 return 0; 2135 } 2136 2137 void igb_down(struct igb_adapter *adapter) 2138 { 2139 struct net_device *netdev = adapter->netdev; 2140 struct e1000_hw *hw = &adapter->hw; 2141 u32 tctl, rctl; 2142 int i; 2143 2144 /* signal that we're down so the interrupt handler does not 2145 * reschedule our watchdog timer 2146 */ 2147 set_bit(__IGB_DOWN, &adapter->state); 2148 2149 /* disable receives in the hardware */ 2150 rctl = rd32(E1000_RCTL); 2151 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2152 /* flush and sleep below */ 2153 2154 igb_nfc_filter_exit(adapter); 2155 2156 netif_carrier_off(netdev); 2157 netif_tx_stop_all_queues(netdev); 2158 2159 /* disable transmits in the hardware */ 2160 tctl = rd32(E1000_TCTL); 2161 tctl &= ~E1000_TCTL_EN; 2162 wr32(E1000_TCTL, tctl); 2163 /* flush both disables and wait for them to finish */ 2164 wrfl(); 2165 usleep_range(10000, 11000); 2166 2167 igb_irq_disable(adapter); 2168 2169 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2170 2171 for (i = 0; i < adapter->num_q_vectors; i++) { 2172 if (adapter->q_vector[i]) { 2173 napi_synchronize(&adapter->q_vector[i]->napi); 2174 napi_disable(&adapter->q_vector[i]->napi); 2175 } 2176 } 2177 2178 del_timer_sync(&adapter->watchdog_timer); 2179 del_timer_sync(&adapter->phy_info_timer); 2180 2181 /* record the stats before reset*/ 2182 spin_lock(&adapter->stats64_lock); 2183 igb_update_stats(adapter); 2184 spin_unlock(&adapter->stats64_lock); 2185 2186 adapter->link_speed = 0; 2187 adapter->link_duplex = 0; 2188 2189 if (!pci_channel_offline(adapter->pdev)) 2190 igb_reset(adapter); 2191 2192 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2193 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2194 2195 igb_clean_all_tx_rings(adapter); 2196 igb_clean_all_rx_rings(adapter); 2197 #ifdef CONFIG_IGB_DCA 2198 2199 /* since we reset the hardware DCA settings were cleared */ 2200 igb_setup_dca(adapter); 2201 #endif 2202 } 2203 2204 void igb_reinit_locked(struct igb_adapter *adapter) 2205 { 2206 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2207 usleep_range(1000, 2000); 2208 igb_down(adapter); 2209 igb_up(adapter); 2210 clear_bit(__IGB_RESETTING, &adapter->state); 2211 } 2212 2213 /** igb_enable_mas - Media Autosense re-enable after swap 2214 * 2215 * @adapter: adapter struct 2216 **/ 2217 static void igb_enable_mas(struct igb_adapter *adapter) 2218 { 2219 struct e1000_hw *hw = &adapter->hw; 2220 u32 connsw = rd32(E1000_CONNSW); 2221 2222 /* configure for SerDes media detect */ 2223 if ((hw->phy.media_type == e1000_media_type_copper) && 2224 (!(connsw & E1000_CONNSW_SERDESD))) { 2225 connsw |= E1000_CONNSW_ENRGSRC; 2226 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2227 wr32(E1000_CONNSW, connsw); 2228 wrfl(); 2229 } 2230 } 2231 2232 #ifdef CONFIG_IGB_HWMON 2233 /** 2234 * igb_set_i2c_bb - Init I2C interface 2235 * @hw: pointer to hardware structure 2236 **/ 2237 static void igb_set_i2c_bb(struct e1000_hw *hw) 2238 { 2239 u32 ctrl_ext; 2240 s32 i2cctl; 2241 2242 ctrl_ext = rd32(E1000_CTRL_EXT); 2243 ctrl_ext |= E1000_CTRL_I2C_ENA; 2244 wr32(E1000_CTRL_EXT, ctrl_ext); 2245 wrfl(); 2246 2247 i2cctl = rd32(E1000_I2CPARAMS); 2248 i2cctl |= E1000_I2CBB_EN 2249 | E1000_I2C_CLK_OE_N 2250 | E1000_I2C_DATA_OE_N; 2251 wr32(E1000_I2CPARAMS, i2cctl); 2252 wrfl(); 2253 } 2254 #endif 2255 2256 void igb_reset(struct igb_adapter *adapter) 2257 { 2258 struct pci_dev *pdev = adapter->pdev; 2259 struct e1000_hw *hw = &adapter->hw; 2260 struct e1000_mac_info *mac = &hw->mac; 2261 struct e1000_fc_info *fc = &hw->fc; 2262 u32 pba, hwm; 2263 2264 /* Repartition Pba for greater than 9k mtu 2265 * To take effect CTRL.RST is required. 2266 */ 2267 switch (mac->type) { 2268 case e1000_i350: 2269 case e1000_i354: 2270 case e1000_82580: 2271 pba = rd32(E1000_RXPBS); 2272 pba = igb_rxpbs_adjust_82580(pba); 2273 break; 2274 case e1000_82576: 2275 pba = rd32(E1000_RXPBS); 2276 pba &= E1000_RXPBS_SIZE_MASK_82576; 2277 break; 2278 case e1000_82575: 2279 case e1000_i210: 2280 case e1000_i211: 2281 default: 2282 pba = E1000_PBA_34K; 2283 break; 2284 } 2285 2286 if (mac->type == e1000_82575) { 2287 u32 min_rx_space, min_tx_space, needed_tx_space; 2288 2289 /* write Rx PBA so that hardware can report correct Tx PBA */ 2290 wr32(E1000_PBA, pba); 2291 2292 /* To maintain wire speed transmits, the Tx FIFO should be 2293 * large enough to accommodate two full transmit packets, 2294 * rounded up to the next 1KB and expressed in KB. Likewise, 2295 * the Rx FIFO should be large enough to accommodate at least 2296 * one full receive packet and is similarly rounded up and 2297 * expressed in KB. 2298 */ 2299 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2300 2301 /* The Tx FIFO also stores 16 bytes of information about the Tx 2302 * but don't include Ethernet FCS because hardware appends it. 2303 * We only need to round down to the nearest 512 byte block 2304 * count since the value we care about is 2 frames, not 1. 2305 */ 2306 min_tx_space = adapter->max_frame_size; 2307 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2308 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2309 2310 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2311 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2312 2313 /* If current Tx allocation is less than the min Tx FIFO size, 2314 * and the min Tx FIFO size is less than the current Rx FIFO 2315 * allocation, take space away from current Rx allocation. 2316 */ 2317 if (needed_tx_space < pba) { 2318 pba -= needed_tx_space; 2319 2320 /* if short on Rx space, Rx wins and must trump Tx 2321 * adjustment 2322 */ 2323 if (pba < min_rx_space) 2324 pba = min_rx_space; 2325 } 2326 2327 /* adjust PBA for jumbo frames */ 2328 wr32(E1000_PBA, pba); 2329 } 2330 2331 /* flow control settings 2332 * The high water mark must be low enough to fit one full frame 2333 * after transmitting the pause frame. As such we must have enough 2334 * space to allow for us to complete our current transmit and then 2335 * receive the frame that is in progress from the link partner. 2336 * Set it to: 2337 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2338 */ 2339 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2340 2341 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2342 fc->low_water = fc->high_water - 16; 2343 fc->pause_time = 0xFFFF; 2344 fc->send_xon = 1; 2345 fc->current_mode = fc->requested_mode; 2346 2347 /* disable receive for all VFs and wait one second */ 2348 if (adapter->vfs_allocated_count) { 2349 int i; 2350 2351 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2352 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2353 2354 /* ping all the active vfs to let them know we are going down */ 2355 igb_ping_all_vfs(adapter); 2356 2357 /* disable transmits and receives */ 2358 wr32(E1000_VFRE, 0); 2359 wr32(E1000_VFTE, 0); 2360 } 2361 2362 /* Allow time for pending master requests to run */ 2363 hw->mac.ops.reset_hw(hw); 2364 wr32(E1000_WUC, 0); 2365 2366 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2367 /* need to resetup here after media swap */ 2368 adapter->ei.get_invariants(hw); 2369 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2370 } 2371 if ((mac->type == e1000_82575 || mac->type == e1000_i350) && 2372 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2373 igb_enable_mas(adapter); 2374 } 2375 if (hw->mac.ops.init_hw(hw)) 2376 dev_err(&pdev->dev, "Hardware Error\n"); 2377 2378 /* RAR registers were cleared during init_hw, clear mac table */ 2379 igb_flush_mac_table(adapter); 2380 __dev_uc_unsync(adapter->netdev, NULL); 2381 2382 /* Recover default RAR entry */ 2383 igb_set_default_mac_filter(adapter); 2384 2385 /* Flow control settings reset on hardware reset, so guarantee flow 2386 * control is off when forcing speed. 2387 */ 2388 if (!hw->mac.autoneg) 2389 igb_force_mac_fc(hw); 2390 2391 igb_init_dmac(adapter, pba); 2392 #ifdef CONFIG_IGB_HWMON 2393 /* Re-initialize the thermal sensor on i350 devices. */ 2394 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2395 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2396 /* If present, re-initialize the external thermal sensor 2397 * interface. 2398 */ 2399 if (adapter->ets) 2400 igb_set_i2c_bb(hw); 2401 mac->ops.init_thermal_sensor_thresh(hw); 2402 } 2403 } 2404 #endif 2405 /* Re-establish EEE setting */ 2406 if (hw->phy.media_type == e1000_media_type_copper) { 2407 switch (mac->type) { 2408 case e1000_i350: 2409 case e1000_i210: 2410 case e1000_i211: 2411 igb_set_eee_i350(hw, true, true); 2412 break; 2413 case e1000_i354: 2414 igb_set_eee_i354(hw, true, true); 2415 break; 2416 default: 2417 break; 2418 } 2419 } 2420 if (!netif_running(adapter->netdev)) 2421 igb_power_down_link(adapter); 2422 2423 igb_update_mng_vlan(adapter); 2424 2425 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2426 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2427 2428 /* Re-enable PTP, where applicable. */ 2429 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2430 igb_ptp_reset(adapter); 2431 2432 igb_get_phy_info(hw); 2433 } 2434 2435 static netdev_features_t igb_fix_features(struct net_device *netdev, 2436 netdev_features_t features) 2437 { 2438 /* Since there is no support for separate Rx/Tx vlan accel 2439 * enable/disable make sure Tx flag is always in same state as Rx. 2440 */ 2441 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2442 features |= NETIF_F_HW_VLAN_CTAG_TX; 2443 else 2444 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2445 2446 return features; 2447 } 2448 2449 static int igb_set_features(struct net_device *netdev, 2450 netdev_features_t features) 2451 { 2452 netdev_features_t changed = netdev->features ^ features; 2453 struct igb_adapter *adapter = netdev_priv(netdev); 2454 2455 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2456 igb_vlan_mode(netdev, features); 2457 2458 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2459 return 0; 2460 2461 if (!(features & NETIF_F_NTUPLE)) { 2462 struct hlist_node *node2; 2463 struct igb_nfc_filter *rule; 2464 2465 spin_lock(&adapter->nfc_lock); 2466 hlist_for_each_entry_safe(rule, node2, 2467 &adapter->nfc_filter_list, nfc_node) { 2468 igb_erase_filter(adapter, rule); 2469 hlist_del(&rule->nfc_node); 2470 kfree(rule); 2471 } 2472 spin_unlock(&adapter->nfc_lock); 2473 adapter->nfc_filter_count = 0; 2474 } 2475 2476 netdev->features = features; 2477 2478 if (netif_running(netdev)) 2479 igb_reinit_locked(adapter); 2480 else 2481 igb_reset(adapter); 2482 2483 return 1; 2484 } 2485 2486 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2487 struct net_device *dev, 2488 const unsigned char *addr, u16 vid, 2489 u16 flags, 2490 struct netlink_ext_ack *extack) 2491 { 2492 /* guarantee we can provide a unique filter for the unicast address */ 2493 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2494 struct igb_adapter *adapter = netdev_priv(dev); 2495 int vfn = adapter->vfs_allocated_count; 2496 2497 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2498 return -ENOMEM; 2499 } 2500 2501 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2502 } 2503 2504 #define IGB_MAX_MAC_HDR_LEN 127 2505 #define IGB_MAX_NETWORK_HDR_LEN 511 2506 2507 static netdev_features_t 2508 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2509 netdev_features_t features) 2510 { 2511 unsigned int network_hdr_len, mac_hdr_len; 2512 2513 /* Make certain the headers can be described by a context descriptor */ 2514 mac_hdr_len = skb_network_offset(skb); 2515 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2516 return features & ~(NETIF_F_HW_CSUM | 2517 NETIF_F_SCTP_CRC | 2518 NETIF_F_GSO_UDP_L4 | 2519 NETIF_F_HW_VLAN_CTAG_TX | 2520 NETIF_F_TSO | 2521 NETIF_F_TSO6); 2522 2523 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2524 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2525 return features & ~(NETIF_F_HW_CSUM | 2526 NETIF_F_SCTP_CRC | 2527 NETIF_F_GSO_UDP_L4 | 2528 NETIF_F_TSO | 2529 NETIF_F_TSO6); 2530 2531 /* We can only support IPV4 TSO in tunnels if we can mangle the 2532 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2533 */ 2534 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2535 features &= ~NETIF_F_TSO; 2536 2537 return features; 2538 } 2539 2540 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2541 { 2542 if (!is_fqtss_enabled(adapter)) { 2543 enable_fqtss(adapter, true); 2544 return; 2545 } 2546 2547 igb_config_tx_modes(adapter, queue); 2548 2549 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2550 enable_fqtss(adapter, false); 2551 } 2552 2553 static int igb_offload_cbs(struct igb_adapter *adapter, 2554 struct tc_cbs_qopt_offload *qopt) 2555 { 2556 struct e1000_hw *hw = &adapter->hw; 2557 int err; 2558 2559 /* CBS offloading is only supported by i210 controller. */ 2560 if (hw->mac.type != e1000_i210) 2561 return -EOPNOTSUPP; 2562 2563 /* CBS offloading is only supported by queue 0 and queue 1. */ 2564 if (qopt->queue < 0 || qopt->queue > 1) 2565 return -EINVAL; 2566 2567 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2568 qopt->idleslope, qopt->sendslope, 2569 qopt->hicredit, qopt->locredit); 2570 if (err) 2571 return err; 2572 2573 igb_offload_apply(adapter, qopt->queue); 2574 2575 return 0; 2576 } 2577 2578 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2579 #define VLAN_PRIO_FULL_MASK (0x07) 2580 2581 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2582 struct flow_cls_offload *f, 2583 int traffic_class, 2584 struct igb_nfc_filter *input) 2585 { 2586 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2587 struct flow_dissector *dissector = rule->match.dissector; 2588 struct netlink_ext_ack *extack = f->common.extack; 2589 2590 if (dissector->used_keys & 2591 ~(BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) | 2592 BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) | 2593 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2594 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN))) { 2595 NL_SET_ERR_MSG_MOD(extack, 2596 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2597 return -EOPNOTSUPP; 2598 } 2599 2600 if (flow_rule_match_has_control_flags(rule, extack)) 2601 return -EOPNOTSUPP; 2602 2603 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2604 struct flow_match_eth_addrs match; 2605 2606 flow_rule_match_eth_addrs(rule, &match); 2607 if (!is_zero_ether_addr(match.mask->dst)) { 2608 if (!is_broadcast_ether_addr(match.mask->dst)) { 2609 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2610 return -EINVAL; 2611 } 2612 2613 input->filter.match_flags |= 2614 IGB_FILTER_FLAG_DST_MAC_ADDR; 2615 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2616 } 2617 2618 if (!is_zero_ether_addr(match.mask->src)) { 2619 if (!is_broadcast_ether_addr(match.mask->src)) { 2620 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2621 return -EINVAL; 2622 } 2623 2624 input->filter.match_flags |= 2625 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2626 ether_addr_copy(input->filter.src_addr, match.key->src); 2627 } 2628 } 2629 2630 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2631 struct flow_match_basic match; 2632 2633 flow_rule_match_basic(rule, &match); 2634 if (match.mask->n_proto) { 2635 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2636 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2637 return -EINVAL; 2638 } 2639 2640 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2641 input->filter.etype = match.key->n_proto; 2642 } 2643 } 2644 2645 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2646 struct flow_match_vlan match; 2647 2648 flow_rule_match_vlan(rule, &match); 2649 if (match.mask->vlan_priority) { 2650 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2651 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2652 return -EINVAL; 2653 } 2654 2655 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2656 input->filter.vlan_tci = 2657 (__force __be16)match.key->vlan_priority; 2658 } 2659 } 2660 2661 input->action = traffic_class; 2662 input->cookie = f->cookie; 2663 2664 return 0; 2665 } 2666 2667 static int igb_configure_clsflower(struct igb_adapter *adapter, 2668 struct flow_cls_offload *cls_flower) 2669 { 2670 struct netlink_ext_ack *extack = cls_flower->common.extack; 2671 struct igb_nfc_filter *filter, *f; 2672 int err, tc; 2673 2674 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2675 if (tc < 0) { 2676 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2677 return -EINVAL; 2678 } 2679 2680 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2681 if (!filter) 2682 return -ENOMEM; 2683 2684 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2685 if (err < 0) 2686 goto err_parse; 2687 2688 spin_lock(&adapter->nfc_lock); 2689 2690 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2691 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2692 err = -EEXIST; 2693 NL_SET_ERR_MSG_MOD(extack, 2694 "This filter is already set in ethtool"); 2695 goto err_locked; 2696 } 2697 } 2698 2699 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2700 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2701 err = -EEXIST; 2702 NL_SET_ERR_MSG_MOD(extack, 2703 "This filter is already set in cls_flower"); 2704 goto err_locked; 2705 } 2706 } 2707 2708 err = igb_add_filter(adapter, filter); 2709 if (err < 0) { 2710 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2711 goto err_locked; 2712 } 2713 2714 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2715 2716 spin_unlock(&adapter->nfc_lock); 2717 2718 return 0; 2719 2720 err_locked: 2721 spin_unlock(&adapter->nfc_lock); 2722 2723 err_parse: 2724 kfree(filter); 2725 2726 return err; 2727 } 2728 2729 static int igb_delete_clsflower(struct igb_adapter *adapter, 2730 struct flow_cls_offload *cls_flower) 2731 { 2732 struct igb_nfc_filter *filter; 2733 int err; 2734 2735 spin_lock(&adapter->nfc_lock); 2736 2737 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2738 if (filter->cookie == cls_flower->cookie) 2739 break; 2740 2741 if (!filter) { 2742 err = -ENOENT; 2743 goto out; 2744 } 2745 2746 err = igb_erase_filter(adapter, filter); 2747 if (err < 0) 2748 goto out; 2749 2750 hlist_del(&filter->nfc_node); 2751 kfree(filter); 2752 2753 out: 2754 spin_unlock(&adapter->nfc_lock); 2755 2756 return err; 2757 } 2758 2759 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2760 struct flow_cls_offload *cls_flower) 2761 { 2762 switch (cls_flower->command) { 2763 case FLOW_CLS_REPLACE: 2764 return igb_configure_clsflower(adapter, cls_flower); 2765 case FLOW_CLS_DESTROY: 2766 return igb_delete_clsflower(adapter, cls_flower); 2767 case FLOW_CLS_STATS: 2768 return -EOPNOTSUPP; 2769 default: 2770 return -EOPNOTSUPP; 2771 } 2772 } 2773 2774 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2775 void *cb_priv) 2776 { 2777 struct igb_adapter *adapter = cb_priv; 2778 2779 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2780 return -EOPNOTSUPP; 2781 2782 switch (type) { 2783 case TC_SETUP_CLSFLOWER: 2784 return igb_setup_tc_cls_flower(adapter, type_data); 2785 2786 default: 2787 return -EOPNOTSUPP; 2788 } 2789 } 2790 2791 static int igb_offload_txtime(struct igb_adapter *adapter, 2792 struct tc_etf_qopt_offload *qopt) 2793 { 2794 struct e1000_hw *hw = &adapter->hw; 2795 int err; 2796 2797 /* Launchtime offloading is only supported by i210 controller. */ 2798 if (hw->mac.type != e1000_i210) 2799 return -EOPNOTSUPP; 2800 2801 /* Launchtime offloading is only supported by queues 0 and 1. */ 2802 if (qopt->queue < 0 || qopt->queue > 1) 2803 return -EINVAL; 2804 2805 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2806 if (err) 2807 return err; 2808 2809 igb_offload_apply(adapter, qopt->queue); 2810 2811 return 0; 2812 } 2813 2814 static int igb_tc_query_caps(struct igb_adapter *adapter, 2815 struct tc_query_caps_base *base) 2816 { 2817 switch (base->type) { 2818 case TC_SETUP_QDISC_TAPRIO: { 2819 struct tc_taprio_caps *caps = base->caps; 2820 2821 caps->broken_mqprio = true; 2822 2823 return 0; 2824 } 2825 default: 2826 return -EOPNOTSUPP; 2827 } 2828 } 2829 2830 static LIST_HEAD(igb_block_cb_list); 2831 2832 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2833 void *type_data) 2834 { 2835 struct igb_adapter *adapter = netdev_priv(dev); 2836 2837 switch (type) { 2838 case TC_QUERY_CAPS: 2839 return igb_tc_query_caps(adapter, type_data); 2840 case TC_SETUP_QDISC_CBS: 2841 return igb_offload_cbs(adapter, type_data); 2842 case TC_SETUP_BLOCK: 2843 return flow_block_cb_setup_simple(type_data, 2844 &igb_block_cb_list, 2845 igb_setup_tc_block_cb, 2846 adapter, adapter, true); 2847 2848 case TC_SETUP_QDISC_ETF: 2849 return igb_offload_txtime(adapter, type_data); 2850 2851 default: 2852 return -EOPNOTSUPP; 2853 } 2854 } 2855 2856 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf) 2857 { 2858 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD; 2859 struct igb_adapter *adapter = netdev_priv(dev); 2860 struct bpf_prog *prog = bpf->prog, *old_prog; 2861 bool running = netif_running(dev); 2862 bool need_reset; 2863 2864 /* verify igb ring attributes are sufficient for XDP */ 2865 for (i = 0; i < adapter->num_rx_queues; i++) { 2866 struct igb_ring *ring = adapter->rx_ring[i]; 2867 2868 if (frame_size > igb_rx_bufsz(ring)) { 2869 NL_SET_ERR_MSG_MOD(bpf->extack, 2870 "The RX buffer size is too small for the frame size"); 2871 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n", 2872 igb_rx_bufsz(ring), frame_size); 2873 return -EINVAL; 2874 } 2875 } 2876 2877 old_prog = xchg(&adapter->xdp_prog, prog); 2878 need_reset = (!!prog != !!old_prog); 2879 2880 /* device is up and bpf is added/removed, must setup the RX queues */ 2881 if (need_reset && running) { 2882 igb_close(dev); 2883 } else { 2884 for (i = 0; i < adapter->num_rx_queues; i++) 2885 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 2886 adapter->xdp_prog); 2887 } 2888 2889 if (old_prog) 2890 bpf_prog_put(old_prog); 2891 2892 /* bpf is just replaced, RXQ and MTU are already setup */ 2893 if (!need_reset) { 2894 return 0; 2895 } else { 2896 if (prog) 2897 xdp_features_set_redirect_target(dev, true); 2898 else 2899 xdp_features_clear_redirect_target(dev); 2900 } 2901 2902 if (running) 2903 igb_open(dev); 2904 2905 return 0; 2906 } 2907 2908 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp) 2909 { 2910 switch (xdp->command) { 2911 case XDP_SETUP_PROG: 2912 return igb_xdp_setup(dev, xdp); 2913 default: 2914 return -EINVAL; 2915 } 2916 } 2917 2918 /* This function assumes __netif_tx_lock is held by the caller. */ 2919 static void igb_xdp_ring_update_tail(struct igb_ring *ring) 2920 { 2921 lockdep_assert_held(&txring_txq(ring)->_xmit_lock); 2922 2923 /* Force memory writes to complete before letting h/w know there 2924 * are new descriptors to fetch. 2925 */ 2926 wmb(); 2927 writel(ring->next_to_use, ring->tail); 2928 } 2929 2930 static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter) 2931 { 2932 unsigned int r_idx = smp_processor_id(); 2933 2934 if (r_idx >= adapter->num_tx_queues) 2935 r_idx = r_idx % adapter->num_tx_queues; 2936 2937 return adapter->tx_ring[r_idx]; 2938 } 2939 2940 static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp) 2941 { 2942 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2943 int cpu = smp_processor_id(); 2944 struct igb_ring *tx_ring; 2945 struct netdev_queue *nq; 2946 u32 ret; 2947 2948 if (unlikely(!xdpf)) 2949 return IGB_XDP_CONSUMED; 2950 2951 /* During program transitions its possible adapter->xdp_prog is assigned 2952 * but ring has not been configured yet. In this case simply abort xmit. 2953 */ 2954 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2955 if (unlikely(!tx_ring)) 2956 return IGB_XDP_CONSUMED; 2957 2958 nq = txring_txq(tx_ring); 2959 __netif_tx_lock(nq, cpu); 2960 /* Avoid transmit queue timeout since we share it with the slow path */ 2961 txq_trans_cond_update(nq); 2962 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2963 __netif_tx_unlock(nq); 2964 2965 return ret; 2966 } 2967 2968 static int igb_xdp_xmit(struct net_device *dev, int n, 2969 struct xdp_frame **frames, u32 flags) 2970 { 2971 struct igb_adapter *adapter = netdev_priv(dev); 2972 int cpu = smp_processor_id(); 2973 struct igb_ring *tx_ring; 2974 struct netdev_queue *nq; 2975 int nxmit = 0; 2976 int i; 2977 2978 if (unlikely(test_bit(__IGB_DOWN, &adapter->state))) 2979 return -ENETDOWN; 2980 2981 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2982 return -EINVAL; 2983 2984 /* During program transitions its possible adapter->xdp_prog is assigned 2985 * but ring has not been configured yet. In this case simply abort xmit. 2986 */ 2987 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2988 if (unlikely(!tx_ring)) 2989 return -ENXIO; 2990 2991 nq = txring_txq(tx_ring); 2992 __netif_tx_lock(nq, cpu); 2993 2994 /* Avoid transmit queue timeout since we share it with the slow path */ 2995 txq_trans_cond_update(nq); 2996 2997 for (i = 0; i < n; i++) { 2998 struct xdp_frame *xdpf = frames[i]; 2999 int err; 3000 3001 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 3002 if (err != IGB_XDP_TX) 3003 break; 3004 nxmit++; 3005 } 3006 3007 if (unlikely(flags & XDP_XMIT_FLUSH)) 3008 igb_xdp_ring_update_tail(tx_ring); 3009 3010 __netif_tx_unlock(nq); 3011 3012 return nxmit; 3013 } 3014 3015 static const struct net_device_ops igb_netdev_ops = { 3016 .ndo_open = igb_open, 3017 .ndo_stop = igb_close, 3018 .ndo_start_xmit = igb_xmit_frame, 3019 .ndo_get_stats64 = igb_get_stats64, 3020 .ndo_set_rx_mode = igb_set_rx_mode, 3021 .ndo_set_mac_address = igb_set_mac, 3022 .ndo_change_mtu = igb_change_mtu, 3023 .ndo_eth_ioctl = igb_ioctl, 3024 .ndo_tx_timeout = igb_tx_timeout, 3025 .ndo_validate_addr = eth_validate_addr, 3026 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 3027 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 3028 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 3029 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 3030 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 3031 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 3032 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 3033 .ndo_get_vf_config = igb_ndo_get_vf_config, 3034 .ndo_fix_features = igb_fix_features, 3035 .ndo_set_features = igb_set_features, 3036 .ndo_fdb_add = igb_ndo_fdb_add, 3037 .ndo_features_check = igb_features_check, 3038 .ndo_setup_tc = igb_setup_tc, 3039 .ndo_bpf = igb_xdp, 3040 .ndo_xdp_xmit = igb_xdp_xmit, 3041 }; 3042 3043 /** 3044 * igb_set_fw_version - Configure version string for ethtool 3045 * @adapter: adapter struct 3046 **/ 3047 void igb_set_fw_version(struct igb_adapter *adapter) 3048 { 3049 struct e1000_hw *hw = &adapter->hw; 3050 struct e1000_fw_version fw; 3051 3052 igb_get_fw_version(hw, &fw); 3053 3054 switch (hw->mac.type) { 3055 case e1000_i210: 3056 case e1000_i211: 3057 if (!(igb_get_flash_presence_i210(hw))) { 3058 snprintf(adapter->fw_version, 3059 sizeof(adapter->fw_version), 3060 "%2d.%2d-%d", 3061 fw.invm_major, fw.invm_minor, 3062 fw.invm_img_type); 3063 break; 3064 } 3065 fallthrough; 3066 default: 3067 /* if option rom is valid, display its version too */ 3068 if (fw.or_valid) { 3069 snprintf(adapter->fw_version, 3070 sizeof(adapter->fw_version), 3071 "%d.%d, 0x%08x, %d.%d.%d", 3072 fw.eep_major, fw.eep_minor, fw.etrack_id, 3073 fw.or_major, fw.or_build, fw.or_patch); 3074 /* no option rom */ 3075 } else if (fw.etrack_id != 0X0000) { 3076 snprintf(adapter->fw_version, 3077 sizeof(adapter->fw_version), 3078 "%d.%d, 0x%08x", 3079 fw.eep_major, fw.eep_minor, fw.etrack_id); 3080 } else { 3081 snprintf(adapter->fw_version, 3082 sizeof(adapter->fw_version), 3083 "%d.%d.%d", 3084 fw.eep_major, fw.eep_minor, fw.eep_build); 3085 } 3086 break; 3087 } 3088 } 3089 3090 /** 3091 * igb_init_mas - init Media Autosense feature if enabled in the NVM 3092 * 3093 * @adapter: adapter struct 3094 **/ 3095 static void igb_init_mas(struct igb_adapter *adapter) 3096 { 3097 struct e1000_hw *hw = &adapter->hw; 3098 u16 eeprom_data; 3099 3100 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 3101 switch (hw->bus.func) { 3102 case E1000_FUNC_0: 3103 if (eeprom_data & IGB_MAS_ENABLE_0) { 3104 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3105 netdev_info(adapter->netdev, 3106 "MAS: Enabling Media Autosense for port %d\n", 3107 hw->bus.func); 3108 } 3109 break; 3110 case E1000_FUNC_1: 3111 if (eeprom_data & IGB_MAS_ENABLE_1) { 3112 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3113 netdev_info(adapter->netdev, 3114 "MAS: Enabling Media Autosense for port %d\n", 3115 hw->bus.func); 3116 } 3117 break; 3118 case E1000_FUNC_2: 3119 if (eeprom_data & IGB_MAS_ENABLE_2) { 3120 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3121 netdev_info(adapter->netdev, 3122 "MAS: Enabling Media Autosense for port %d\n", 3123 hw->bus.func); 3124 } 3125 break; 3126 case E1000_FUNC_3: 3127 if (eeprom_data & IGB_MAS_ENABLE_3) { 3128 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3129 netdev_info(adapter->netdev, 3130 "MAS: Enabling Media Autosense for port %d\n", 3131 hw->bus.func); 3132 } 3133 break; 3134 default: 3135 /* Shouldn't get here */ 3136 netdev_err(adapter->netdev, 3137 "MAS: Invalid port configuration, returning\n"); 3138 break; 3139 } 3140 } 3141 3142 /** 3143 * igb_init_i2c - Init I2C interface 3144 * @adapter: pointer to adapter structure 3145 **/ 3146 static s32 igb_init_i2c(struct igb_adapter *adapter) 3147 { 3148 s32 status = 0; 3149 3150 /* I2C interface supported on i350 devices */ 3151 if (adapter->hw.mac.type != e1000_i350) 3152 return 0; 3153 3154 /* Initialize the i2c bus which is controlled by the registers. 3155 * This bus will use the i2c_algo_bit structure that implements 3156 * the protocol through toggling of the 4 bits in the register. 3157 */ 3158 adapter->i2c_adap.owner = THIS_MODULE; 3159 adapter->i2c_algo = igb_i2c_algo; 3160 adapter->i2c_algo.data = adapter; 3161 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 3162 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 3163 strscpy(adapter->i2c_adap.name, "igb BB", 3164 sizeof(adapter->i2c_adap.name)); 3165 status = i2c_bit_add_bus(&adapter->i2c_adap); 3166 return status; 3167 } 3168 3169 /** 3170 * igb_probe - Device Initialization Routine 3171 * @pdev: PCI device information struct 3172 * @ent: entry in igb_pci_tbl 3173 * 3174 * Returns 0 on success, negative on failure 3175 * 3176 * igb_probe initializes an adapter identified by a pci_dev structure. 3177 * The OS initialization, configuring of the adapter private structure, 3178 * and a hardware reset occur. 3179 **/ 3180 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3181 { 3182 struct net_device *netdev; 3183 struct igb_adapter *adapter; 3184 struct e1000_hw *hw; 3185 u16 eeprom_data = 0; 3186 s32 ret_val; 3187 static int global_quad_port_a; /* global quad port a indication */ 3188 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3189 u8 part_str[E1000_PBANUM_LENGTH]; 3190 int err; 3191 3192 /* Catch broken hardware that put the wrong VF device ID in 3193 * the PCIe SR-IOV capability. 3194 */ 3195 if (pdev->is_virtfn) { 3196 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n", 3197 pci_name(pdev), pdev->vendor, pdev->device); 3198 return -EINVAL; 3199 } 3200 3201 err = pci_enable_device_mem(pdev); 3202 if (err) 3203 return err; 3204 3205 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3206 if (err) { 3207 dev_err(&pdev->dev, 3208 "No usable DMA configuration, aborting\n"); 3209 goto err_dma; 3210 } 3211 3212 err = pci_request_mem_regions(pdev, igb_driver_name); 3213 if (err) 3214 goto err_pci_reg; 3215 3216 pci_set_master(pdev); 3217 pci_save_state(pdev); 3218 3219 err = -ENOMEM; 3220 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3221 IGB_MAX_TX_QUEUES); 3222 if (!netdev) 3223 goto err_alloc_etherdev; 3224 3225 SET_NETDEV_DEV(netdev, &pdev->dev); 3226 3227 pci_set_drvdata(pdev, netdev); 3228 adapter = netdev_priv(netdev); 3229 adapter->netdev = netdev; 3230 adapter->pdev = pdev; 3231 hw = &adapter->hw; 3232 hw->back = adapter; 3233 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3234 3235 err = -EIO; 3236 adapter->io_addr = pci_iomap(pdev, 0, 0); 3237 if (!adapter->io_addr) 3238 goto err_ioremap; 3239 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3240 hw->hw_addr = adapter->io_addr; 3241 3242 netdev->netdev_ops = &igb_netdev_ops; 3243 igb_set_ethtool_ops(netdev); 3244 netdev->watchdog_timeo = 5 * HZ; 3245 3246 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 3247 3248 netdev->mem_start = pci_resource_start(pdev, 0); 3249 netdev->mem_end = pci_resource_end(pdev, 0); 3250 3251 /* PCI config space info */ 3252 hw->vendor_id = pdev->vendor; 3253 hw->device_id = pdev->device; 3254 hw->revision_id = pdev->revision; 3255 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3256 hw->subsystem_device_id = pdev->subsystem_device; 3257 3258 /* Copy the default MAC, PHY and NVM function pointers */ 3259 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3260 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3261 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3262 /* Initialize skew-specific constants */ 3263 err = ei->get_invariants(hw); 3264 if (err) 3265 goto err_sw_init; 3266 3267 /* setup the private structure */ 3268 err = igb_sw_init(adapter); 3269 if (err) 3270 goto err_sw_init; 3271 3272 igb_get_bus_info_pcie(hw); 3273 3274 hw->phy.autoneg_wait_to_complete = false; 3275 3276 /* Copper options */ 3277 if (hw->phy.media_type == e1000_media_type_copper) { 3278 hw->phy.mdix = AUTO_ALL_MODES; 3279 hw->phy.disable_polarity_correction = false; 3280 hw->phy.ms_type = e1000_ms_hw_default; 3281 } 3282 3283 if (igb_check_reset_block(hw)) 3284 dev_info(&pdev->dev, 3285 "PHY reset is blocked due to SOL/IDER session.\n"); 3286 3287 /* features is initialized to 0 in allocation, it might have bits 3288 * set by igb_sw_init so we should use an or instead of an 3289 * assignment. 3290 */ 3291 netdev->features |= NETIF_F_SG | 3292 NETIF_F_TSO | 3293 NETIF_F_TSO6 | 3294 NETIF_F_RXHASH | 3295 NETIF_F_RXCSUM | 3296 NETIF_F_HW_CSUM; 3297 3298 if (hw->mac.type >= e1000_82576) 3299 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 3300 3301 if (hw->mac.type >= e1000_i350) 3302 netdev->features |= NETIF_F_HW_TC; 3303 3304 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3305 NETIF_F_GSO_GRE_CSUM | \ 3306 NETIF_F_GSO_IPXIP4 | \ 3307 NETIF_F_GSO_IPXIP6 | \ 3308 NETIF_F_GSO_UDP_TUNNEL | \ 3309 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3310 3311 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3312 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3313 3314 /* copy netdev features into list of user selectable features */ 3315 netdev->hw_features |= netdev->features | 3316 NETIF_F_HW_VLAN_CTAG_RX | 3317 NETIF_F_HW_VLAN_CTAG_TX | 3318 NETIF_F_RXALL; 3319 3320 if (hw->mac.type >= e1000_i350) 3321 netdev->hw_features |= NETIF_F_NTUPLE; 3322 3323 netdev->features |= NETIF_F_HIGHDMA; 3324 3325 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3326 netdev->mpls_features |= NETIF_F_HW_CSUM; 3327 netdev->hw_enc_features |= netdev->vlan_features; 3328 3329 /* set this bit last since it cannot be part of vlan_features */ 3330 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3331 NETIF_F_HW_VLAN_CTAG_RX | 3332 NETIF_F_HW_VLAN_CTAG_TX; 3333 3334 netdev->priv_flags |= IFF_SUPP_NOFCS; 3335 3336 netdev->priv_flags |= IFF_UNICAST_FLT; 3337 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT; 3338 3339 /* MTU range: 68 - 9216 */ 3340 netdev->min_mtu = ETH_MIN_MTU; 3341 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3342 3343 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3344 3345 /* before reading the NVM, reset the controller to put the device in a 3346 * known good starting state 3347 */ 3348 hw->mac.ops.reset_hw(hw); 3349 3350 /* make sure the NVM is good , i211/i210 parts can have special NVM 3351 * that doesn't contain a checksum 3352 */ 3353 switch (hw->mac.type) { 3354 case e1000_i210: 3355 case e1000_i211: 3356 if (igb_get_flash_presence_i210(hw)) { 3357 if (hw->nvm.ops.validate(hw) < 0) { 3358 dev_err(&pdev->dev, 3359 "The NVM Checksum Is Not Valid\n"); 3360 err = -EIO; 3361 goto err_eeprom; 3362 } 3363 } 3364 break; 3365 default: 3366 if (hw->nvm.ops.validate(hw) < 0) { 3367 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3368 err = -EIO; 3369 goto err_eeprom; 3370 } 3371 break; 3372 } 3373 3374 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3375 /* copy the MAC address out of the NVM */ 3376 if (hw->mac.ops.read_mac_addr(hw)) 3377 dev_err(&pdev->dev, "NVM Read Error\n"); 3378 } 3379 3380 eth_hw_addr_set(netdev, hw->mac.addr); 3381 3382 if (!is_valid_ether_addr(netdev->dev_addr)) { 3383 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3384 err = -EIO; 3385 goto err_eeprom; 3386 } 3387 3388 igb_set_default_mac_filter(adapter); 3389 3390 /* get firmware version for ethtool -i */ 3391 igb_set_fw_version(adapter); 3392 3393 /* configure RXPBSIZE and TXPBSIZE */ 3394 if (hw->mac.type == e1000_i210) { 3395 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3396 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3397 } 3398 3399 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3400 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3401 3402 INIT_WORK(&adapter->reset_task, igb_reset_task); 3403 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3404 3405 /* Initialize link properties that are user-changeable */ 3406 adapter->fc_autoneg = true; 3407 hw->mac.autoneg = true; 3408 hw->phy.autoneg_advertised = 0x2f; 3409 3410 hw->fc.requested_mode = e1000_fc_default; 3411 hw->fc.current_mode = e1000_fc_default; 3412 3413 igb_validate_mdi_setting(hw); 3414 3415 /* By default, support wake on port A */ 3416 if (hw->bus.func == 0) 3417 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3418 3419 /* Check the NVM for wake support on non-port A ports */ 3420 if (hw->mac.type >= e1000_82580) 3421 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3422 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3423 &eeprom_data); 3424 else if (hw->bus.func == 1) 3425 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3426 3427 if (eeprom_data & IGB_EEPROM_APME) 3428 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3429 3430 /* now that we have the eeprom settings, apply the special cases where 3431 * the eeprom may be wrong or the board simply won't support wake on 3432 * lan on a particular port 3433 */ 3434 switch (pdev->device) { 3435 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3436 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3437 break; 3438 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3439 case E1000_DEV_ID_82576_FIBER: 3440 case E1000_DEV_ID_82576_SERDES: 3441 /* Wake events only supported on port A for dual fiber 3442 * regardless of eeprom setting 3443 */ 3444 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3445 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3446 break; 3447 case E1000_DEV_ID_82576_QUAD_COPPER: 3448 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3449 /* if quad port adapter, disable WoL on all but port A */ 3450 if (global_quad_port_a != 0) 3451 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3452 else 3453 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3454 /* Reset for multiple quad port adapters */ 3455 if (++global_quad_port_a == 4) 3456 global_quad_port_a = 0; 3457 break; 3458 default: 3459 /* If the device can't wake, don't set software support */ 3460 if (!device_can_wakeup(&adapter->pdev->dev)) 3461 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3462 } 3463 3464 /* initialize the wol settings based on the eeprom settings */ 3465 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3466 adapter->wol |= E1000_WUFC_MAG; 3467 3468 /* Some vendors want WoL disabled by default, but still supported */ 3469 if ((hw->mac.type == e1000_i350) && 3470 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3471 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3472 adapter->wol = 0; 3473 } 3474 3475 /* Some vendors want the ability to Use the EEPROM setting as 3476 * enable/disable only, and not for capability 3477 */ 3478 if (((hw->mac.type == e1000_i350) || 3479 (hw->mac.type == e1000_i354)) && 3480 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3481 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3482 adapter->wol = 0; 3483 } 3484 if (hw->mac.type == e1000_i350) { 3485 if (((pdev->subsystem_device == 0x5001) || 3486 (pdev->subsystem_device == 0x5002)) && 3487 (hw->bus.func == 0)) { 3488 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3489 adapter->wol = 0; 3490 } 3491 if (pdev->subsystem_device == 0x1F52) 3492 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3493 } 3494 3495 device_set_wakeup_enable(&adapter->pdev->dev, 3496 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3497 3498 /* reset the hardware with the new settings */ 3499 igb_reset(adapter); 3500 3501 /* Init the I2C interface */ 3502 err = igb_init_i2c(adapter); 3503 if (err) { 3504 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3505 goto err_eeprom; 3506 } 3507 3508 /* let the f/w know that the h/w is now under the control of the 3509 * driver. 3510 */ 3511 igb_get_hw_control(adapter); 3512 3513 strcpy(netdev->name, "eth%d"); 3514 err = register_netdev(netdev); 3515 if (err) 3516 goto err_register; 3517 3518 /* carrier off reporting is important to ethtool even BEFORE open */ 3519 netif_carrier_off(netdev); 3520 3521 #ifdef CONFIG_IGB_DCA 3522 if (dca_add_requester(&pdev->dev) == 0) { 3523 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3524 dev_info(&pdev->dev, "DCA enabled\n"); 3525 igb_setup_dca(adapter); 3526 } 3527 3528 #endif 3529 #ifdef CONFIG_IGB_HWMON 3530 /* Initialize the thermal sensor on i350 devices. */ 3531 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3532 u16 ets_word; 3533 3534 /* Read the NVM to determine if this i350 device supports an 3535 * external thermal sensor. 3536 */ 3537 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3538 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3539 adapter->ets = true; 3540 else 3541 adapter->ets = false; 3542 /* Only enable I2C bit banging if an external thermal 3543 * sensor is supported. 3544 */ 3545 if (adapter->ets) 3546 igb_set_i2c_bb(hw); 3547 hw->mac.ops.init_thermal_sensor_thresh(hw); 3548 if (igb_sysfs_init(adapter)) 3549 dev_err(&pdev->dev, 3550 "failed to allocate sysfs resources\n"); 3551 } else { 3552 adapter->ets = false; 3553 } 3554 #endif 3555 /* Check if Media Autosense is enabled */ 3556 adapter->ei = *ei; 3557 if (hw->dev_spec._82575.mas_capable) 3558 igb_init_mas(adapter); 3559 3560 /* do hw tstamp init after resetting */ 3561 igb_ptp_init(adapter); 3562 3563 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3564 /* print bus type/speed/width info, not applicable to i354 */ 3565 if (hw->mac.type != e1000_i354) { 3566 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3567 netdev->name, 3568 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3569 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3570 "unknown"), 3571 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3572 "Width x4" : 3573 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3574 "Width x2" : 3575 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3576 "Width x1" : "unknown"), netdev->dev_addr); 3577 } 3578 3579 if ((hw->mac.type == e1000_82576 && 3580 rd32(E1000_EECD) & E1000_EECD_PRES) || 3581 (hw->mac.type >= e1000_i210 || 3582 igb_get_flash_presence_i210(hw))) { 3583 ret_val = igb_read_part_string(hw, part_str, 3584 E1000_PBANUM_LENGTH); 3585 } else { 3586 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3587 } 3588 3589 if (ret_val) 3590 strcpy(part_str, "Unknown"); 3591 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3592 dev_info(&pdev->dev, 3593 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3594 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3595 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3596 adapter->num_rx_queues, adapter->num_tx_queues); 3597 if (hw->phy.media_type == e1000_media_type_copper) { 3598 switch (hw->mac.type) { 3599 case e1000_i350: 3600 case e1000_i210: 3601 case e1000_i211: 3602 /* Enable EEE for internal copper PHY devices */ 3603 err = igb_set_eee_i350(hw, true, true); 3604 if ((!err) && 3605 (!hw->dev_spec._82575.eee_disable)) { 3606 adapter->eee_advert = 3607 MDIO_EEE_100TX | MDIO_EEE_1000T; 3608 adapter->flags |= IGB_FLAG_EEE; 3609 } 3610 break; 3611 case e1000_i354: 3612 if ((rd32(E1000_CTRL_EXT) & 3613 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3614 err = igb_set_eee_i354(hw, true, true); 3615 if ((!err) && 3616 (!hw->dev_spec._82575.eee_disable)) { 3617 adapter->eee_advert = 3618 MDIO_EEE_100TX | MDIO_EEE_1000T; 3619 adapter->flags |= IGB_FLAG_EEE; 3620 } 3621 } 3622 break; 3623 default: 3624 break; 3625 } 3626 } 3627 3628 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 3629 3630 pm_runtime_put_noidle(&pdev->dev); 3631 return 0; 3632 3633 err_register: 3634 igb_release_hw_control(adapter); 3635 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3636 err_eeprom: 3637 if (!igb_check_reset_block(hw)) 3638 igb_reset_phy(hw); 3639 3640 if (hw->flash_address) 3641 iounmap(hw->flash_address); 3642 err_sw_init: 3643 kfree(adapter->mac_table); 3644 kfree(adapter->shadow_vfta); 3645 igb_clear_interrupt_scheme(adapter); 3646 #ifdef CONFIG_PCI_IOV 3647 igb_disable_sriov(pdev, false); 3648 #endif 3649 pci_iounmap(pdev, adapter->io_addr); 3650 err_ioremap: 3651 free_netdev(netdev); 3652 err_alloc_etherdev: 3653 pci_release_mem_regions(pdev); 3654 err_pci_reg: 3655 err_dma: 3656 pci_disable_device(pdev); 3657 return err; 3658 } 3659 3660 #ifdef CONFIG_PCI_IOV 3661 static int igb_sriov_reinit(struct pci_dev *dev) 3662 { 3663 struct net_device *netdev = pci_get_drvdata(dev); 3664 struct igb_adapter *adapter = netdev_priv(netdev); 3665 struct pci_dev *pdev = adapter->pdev; 3666 3667 rtnl_lock(); 3668 3669 if (netif_running(netdev)) 3670 igb_close(netdev); 3671 else 3672 igb_reset(adapter); 3673 3674 igb_clear_interrupt_scheme(adapter); 3675 3676 igb_init_queue_configuration(adapter); 3677 3678 if (igb_init_interrupt_scheme(adapter, true)) { 3679 rtnl_unlock(); 3680 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3681 return -ENOMEM; 3682 } 3683 3684 if (netif_running(netdev)) 3685 igb_open(netdev); 3686 3687 rtnl_unlock(); 3688 3689 return 0; 3690 } 3691 3692 static int igb_disable_sriov(struct pci_dev *pdev, bool reinit) 3693 { 3694 struct net_device *netdev = pci_get_drvdata(pdev); 3695 struct igb_adapter *adapter = netdev_priv(netdev); 3696 struct e1000_hw *hw = &adapter->hw; 3697 unsigned long flags; 3698 3699 /* reclaim resources allocated to VFs */ 3700 if (adapter->vf_data) { 3701 /* disable iov and allow time for transactions to clear */ 3702 if (pci_vfs_assigned(pdev)) { 3703 dev_warn(&pdev->dev, 3704 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3705 return -EPERM; 3706 } else { 3707 pci_disable_sriov(pdev); 3708 msleep(500); 3709 } 3710 spin_lock_irqsave(&adapter->vfs_lock, flags); 3711 kfree(adapter->vf_mac_list); 3712 adapter->vf_mac_list = NULL; 3713 kfree(adapter->vf_data); 3714 adapter->vf_data = NULL; 3715 adapter->vfs_allocated_count = 0; 3716 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 3717 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3718 wrfl(); 3719 msleep(100); 3720 dev_info(&pdev->dev, "IOV Disabled\n"); 3721 3722 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3723 adapter->flags |= IGB_FLAG_DMAC; 3724 } 3725 3726 return reinit ? igb_sriov_reinit(pdev) : 0; 3727 } 3728 3729 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs, bool reinit) 3730 { 3731 struct net_device *netdev = pci_get_drvdata(pdev); 3732 struct igb_adapter *adapter = netdev_priv(netdev); 3733 int old_vfs = pci_num_vf(pdev); 3734 struct vf_mac_filter *mac_list; 3735 int err = 0; 3736 int num_vf_mac_filters, i; 3737 3738 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3739 err = -EPERM; 3740 goto out; 3741 } 3742 if (!num_vfs) 3743 goto out; 3744 3745 if (old_vfs) { 3746 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3747 old_vfs, max_vfs); 3748 adapter->vfs_allocated_count = old_vfs; 3749 } else 3750 adapter->vfs_allocated_count = num_vfs; 3751 3752 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3753 sizeof(struct vf_data_storage), GFP_KERNEL); 3754 3755 /* if allocation failed then we do not support SR-IOV */ 3756 if (!adapter->vf_data) { 3757 adapter->vfs_allocated_count = 0; 3758 err = -ENOMEM; 3759 goto out; 3760 } 3761 3762 /* Due to the limited number of RAR entries calculate potential 3763 * number of MAC filters available for the VFs. Reserve entries 3764 * for PF default MAC, PF MAC filters and at least one RAR entry 3765 * for each VF for VF MAC. 3766 */ 3767 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3768 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3769 adapter->vfs_allocated_count); 3770 3771 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3772 sizeof(struct vf_mac_filter), 3773 GFP_KERNEL); 3774 3775 mac_list = adapter->vf_mac_list; 3776 INIT_LIST_HEAD(&adapter->vf_macs.l); 3777 3778 if (adapter->vf_mac_list) { 3779 /* Initialize list of VF MAC filters */ 3780 for (i = 0; i < num_vf_mac_filters; i++) { 3781 mac_list->vf = -1; 3782 mac_list->free = true; 3783 list_add(&mac_list->l, &adapter->vf_macs.l); 3784 mac_list++; 3785 } 3786 } else { 3787 /* If we could not allocate memory for the VF MAC filters 3788 * we can continue without this feature but warn user. 3789 */ 3790 dev_err(&pdev->dev, 3791 "Unable to allocate memory for VF MAC filter list\n"); 3792 } 3793 3794 dev_info(&pdev->dev, "%d VFs allocated\n", 3795 adapter->vfs_allocated_count); 3796 for (i = 0; i < adapter->vfs_allocated_count; i++) 3797 igb_vf_configure(adapter, i); 3798 3799 /* DMA Coalescing is not supported in IOV mode. */ 3800 adapter->flags &= ~IGB_FLAG_DMAC; 3801 3802 if (reinit) { 3803 err = igb_sriov_reinit(pdev); 3804 if (err) 3805 goto err_out; 3806 } 3807 3808 /* only call pci_enable_sriov() if no VFs are allocated already */ 3809 if (!old_vfs) { 3810 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3811 if (err) 3812 goto err_out; 3813 } 3814 3815 goto out; 3816 3817 err_out: 3818 kfree(adapter->vf_mac_list); 3819 adapter->vf_mac_list = NULL; 3820 kfree(adapter->vf_data); 3821 adapter->vf_data = NULL; 3822 adapter->vfs_allocated_count = 0; 3823 out: 3824 return err; 3825 } 3826 3827 #endif 3828 /** 3829 * igb_remove_i2c - Cleanup I2C interface 3830 * @adapter: pointer to adapter structure 3831 **/ 3832 static void igb_remove_i2c(struct igb_adapter *adapter) 3833 { 3834 /* free the adapter bus structure */ 3835 i2c_del_adapter(&adapter->i2c_adap); 3836 } 3837 3838 /** 3839 * igb_remove - Device Removal Routine 3840 * @pdev: PCI device information struct 3841 * 3842 * igb_remove is called by the PCI subsystem to alert the driver 3843 * that it should release a PCI device. The could be caused by a 3844 * Hot-Plug event, or because the driver is going to be removed from 3845 * memory. 3846 **/ 3847 static void igb_remove(struct pci_dev *pdev) 3848 { 3849 struct net_device *netdev = pci_get_drvdata(pdev); 3850 struct igb_adapter *adapter = netdev_priv(netdev); 3851 struct e1000_hw *hw = &adapter->hw; 3852 3853 pm_runtime_get_noresume(&pdev->dev); 3854 #ifdef CONFIG_IGB_HWMON 3855 igb_sysfs_exit(adapter); 3856 #endif 3857 igb_remove_i2c(adapter); 3858 igb_ptp_stop(adapter); 3859 /* The watchdog timer may be rescheduled, so explicitly 3860 * disable watchdog from being rescheduled. 3861 */ 3862 set_bit(__IGB_DOWN, &adapter->state); 3863 del_timer_sync(&adapter->watchdog_timer); 3864 del_timer_sync(&adapter->phy_info_timer); 3865 3866 cancel_work_sync(&adapter->reset_task); 3867 cancel_work_sync(&adapter->watchdog_task); 3868 3869 #ifdef CONFIG_IGB_DCA 3870 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3871 dev_info(&pdev->dev, "DCA disabled\n"); 3872 dca_remove_requester(&pdev->dev); 3873 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3874 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3875 } 3876 #endif 3877 3878 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3879 * would have already happened in close and is redundant. 3880 */ 3881 igb_release_hw_control(adapter); 3882 3883 #ifdef CONFIG_PCI_IOV 3884 igb_disable_sriov(pdev, false); 3885 #endif 3886 3887 unregister_netdev(netdev); 3888 3889 igb_clear_interrupt_scheme(adapter); 3890 3891 pci_iounmap(pdev, adapter->io_addr); 3892 if (hw->flash_address) 3893 iounmap(hw->flash_address); 3894 pci_release_mem_regions(pdev); 3895 3896 kfree(adapter->mac_table); 3897 kfree(adapter->shadow_vfta); 3898 free_netdev(netdev); 3899 3900 pci_disable_device(pdev); 3901 } 3902 3903 /** 3904 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3905 * @adapter: board private structure to initialize 3906 * 3907 * This function initializes the vf specific data storage and then attempts to 3908 * allocate the VFs. The reason for ordering it this way is because it is much 3909 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3910 * the memory for the VFs. 3911 **/ 3912 static void igb_probe_vfs(struct igb_adapter *adapter) 3913 { 3914 #ifdef CONFIG_PCI_IOV 3915 struct pci_dev *pdev = adapter->pdev; 3916 struct e1000_hw *hw = &adapter->hw; 3917 3918 /* Virtualization features not supported on i210 and 82580 family. */ 3919 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211) || 3920 (hw->mac.type == e1000_82580)) 3921 return; 3922 3923 /* Of the below we really only want the effect of getting 3924 * IGB_FLAG_HAS_MSIX set (if available), without which 3925 * igb_enable_sriov() has no effect. 3926 */ 3927 igb_set_interrupt_capability(adapter, true); 3928 igb_reset_interrupt_capability(adapter); 3929 3930 pci_sriov_set_totalvfs(pdev, 7); 3931 igb_enable_sriov(pdev, max_vfs, false); 3932 3933 #endif /* CONFIG_PCI_IOV */ 3934 } 3935 3936 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3937 { 3938 struct e1000_hw *hw = &adapter->hw; 3939 unsigned int max_rss_queues; 3940 3941 /* Determine the maximum number of RSS queues supported. */ 3942 switch (hw->mac.type) { 3943 case e1000_i211: 3944 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3945 break; 3946 case e1000_82575: 3947 case e1000_i210: 3948 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3949 break; 3950 case e1000_i350: 3951 /* I350 cannot do RSS and SR-IOV at the same time */ 3952 if (!!adapter->vfs_allocated_count) { 3953 max_rss_queues = 1; 3954 break; 3955 } 3956 fallthrough; 3957 case e1000_82576: 3958 if (!!adapter->vfs_allocated_count) { 3959 max_rss_queues = 2; 3960 break; 3961 } 3962 fallthrough; 3963 case e1000_82580: 3964 case e1000_i354: 3965 default: 3966 max_rss_queues = IGB_MAX_RX_QUEUES; 3967 break; 3968 } 3969 3970 return max_rss_queues; 3971 } 3972 3973 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3974 { 3975 u32 max_rss_queues; 3976 3977 max_rss_queues = igb_get_max_rss_queues(adapter); 3978 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3979 3980 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3981 } 3982 3983 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3984 const u32 max_rss_queues) 3985 { 3986 struct e1000_hw *hw = &adapter->hw; 3987 3988 /* Determine if we need to pair queues. */ 3989 switch (hw->mac.type) { 3990 case e1000_82575: 3991 case e1000_i211: 3992 /* Device supports enough interrupts without queue pairing. */ 3993 break; 3994 case e1000_82576: 3995 case e1000_82580: 3996 case e1000_i350: 3997 case e1000_i354: 3998 case e1000_i210: 3999 default: 4000 /* If rss_queues > half of max_rss_queues, pair the queues in 4001 * order to conserve interrupts due to limited supply. 4002 */ 4003 if (adapter->rss_queues > (max_rss_queues / 2)) 4004 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 4005 else 4006 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 4007 break; 4008 } 4009 } 4010 4011 /** 4012 * igb_sw_init - Initialize general software structures (struct igb_adapter) 4013 * @adapter: board private structure to initialize 4014 * 4015 * igb_sw_init initializes the Adapter private data structure. 4016 * Fields are initialized based on PCI device information and 4017 * OS network device settings (MTU size). 4018 **/ 4019 static int igb_sw_init(struct igb_adapter *adapter) 4020 { 4021 struct e1000_hw *hw = &adapter->hw; 4022 struct net_device *netdev = adapter->netdev; 4023 struct pci_dev *pdev = adapter->pdev; 4024 4025 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 4026 4027 /* set default ring sizes */ 4028 adapter->tx_ring_count = IGB_DEFAULT_TXD; 4029 adapter->rx_ring_count = IGB_DEFAULT_RXD; 4030 4031 /* set default ITR values */ 4032 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 4033 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 4034 4035 /* set default work limits */ 4036 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 4037 4038 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD; 4039 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4040 4041 spin_lock_init(&adapter->nfc_lock); 4042 spin_lock_init(&adapter->stats64_lock); 4043 4044 /* init spinlock to avoid concurrency of VF resources */ 4045 spin_lock_init(&adapter->vfs_lock); 4046 #ifdef CONFIG_PCI_IOV 4047 switch (hw->mac.type) { 4048 case e1000_82576: 4049 case e1000_i350: 4050 if (max_vfs > 7) { 4051 dev_warn(&pdev->dev, 4052 "Maximum of 7 VFs per PF, using max\n"); 4053 max_vfs = adapter->vfs_allocated_count = 7; 4054 } else 4055 adapter->vfs_allocated_count = max_vfs; 4056 if (adapter->vfs_allocated_count) 4057 dev_warn(&pdev->dev, 4058 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 4059 break; 4060 default: 4061 break; 4062 } 4063 #endif /* CONFIG_PCI_IOV */ 4064 4065 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 4066 adapter->flags |= IGB_FLAG_HAS_MSIX; 4067 4068 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 4069 sizeof(struct igb_mac_addr), 4070 GFP_KERNEL); 4071 if (!adapter->mac_table) 4072 return -ENOMEM; 4073 4074 igb_probe_vfs(adapter); 4075 4076 igb_init_queue_configuration(adapter); 4077 4078 /* Setup and initialize a copy of the hw vlan table array */ 4079 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 4080 GFP_KERNEL); 4081 if (!adapter->shadow_vfta) 4082 return -ENOMEM; 4083 4084 /* This call may decrease the number of queues */ 4085 if (igb_init_interrupt_scheme(adapter, true)) { 4086 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4087 return -ENOMEM; 4088 } 4089 4090 /* Explicitly disable IRQ since the NIC can be in any state. */ 4091 igb_irq_disable(adapter); 4092 4093 if (hw->mac.type >= e1000_i350) 4094 adapter->flags &= ~IGB_FLAG_DMAC; 4095 4096 set_bit(__IGB_DOWN, &adapter->state); 4097 return 0; 4098 } 4099 4100 /** 4101 * __igb_open - Called when a network interface is made active 4102 * @netdev: network interface device structure 4103 * @resuming: indicates whether we are in a resume call 4104 * 4105 * Returns 0 on success, negative value on failure 4106 * 4107 * The open entry point is called when a network interface is made 4108 * active by the system (IFF_UP). At this point all resources needed 4109 * for transmit and receive operations are allocated, the interrupt 4110 * handler is registered with the OS, the watchdog timer is started, 4111 * and the stack is notified that the interface is ready. 4112 **/ 4113 static int __igb_open(struct net_device *netdev, bool resuming) 4114 { 4115 struct igb_adapter *adapter = netdev_priv(netdev); 4116 struct e1000_hw *hw = &adapter->hw; 4117 struct pci_dev *pdev = adapter->pdev; 4118 int err; 4119 int i; 4120 4121 /* disallow open during test */ 4122 if (test_bit(__IGB_TESTING, &adapter->state)) { 4123 WARN_ON(resuming); 4124 return -EBUSY; 4125 } 4126 4127 if (!resuming) 4128 pm_runtime_get_sync(&pdev->dev); 4129 4130 netif_carrier_off(netdev); 4131 4132 /* allocate transmit descriptors */ 4133 err = igb_setup_all_tx_resources(adapter); 4134 if (err) 4135 goto err_setup_tx; 4136 4137 /* allocate receive descriptors */ 4138 err = igb_setup_all_rx_resources(adapter); 4139 if (err) 4140 goto err_setup_rx; 4141 4142 igb_power_up_link(adapter); 4143 4144 /* before we allocate an interrupt, we must be ready to handle it. 4145 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4146 * as soon as we call pci_request_irq, so we have to setup our 4147 * clean_rx handler before we do so. 4148 */ 4149 igb_configure(adapter); 4150 4151 err = igb_request_irq(adapter); 4152 if (err) 4153 goto err_req_irq; 4154 4155 /* Notify the stack of the actual queue counts. */ 4156 err = netif_set_real_num_tx_queues(adapter->netdev, 4157 adapter->num_tx_queues); 4158 if (err) 4159 goto err_set_queues; 4160 4161 err = netif_set_real_num_rx_queues(adapter->netdev, 4162 adapter->num_rx_queues); 4163 if (err) 4164 goto err_set_queues; 4165 4166 /* From here on the code is the same as igb_up() */ 4167 clear_bit(__IGB_DOWN, &adapter->state); 4168 4169 for (i = 0; i < adapter->num_q_vectors; i++) 4170 napi_enable(&(adapter->q_vector[i]->napi)); 4171 4172 /* Clear any pending interrupts. */ 4173 rd32(E1000_TSICR); 4174 rd32(E1000_ICR); 4175 4176 igb_irq_enable(adapter); 4177 4178 /* notify VFs that reset has been completed */ 4179 if (adapter->vfs_allocated_count) { 4180 u32 reg_data = rd32(E1000_CTRL_EXT); 4181 4182 reg_data |= E1000_CTRL_EXT_PFRSTD; 4183 wr32(E1000_CTRL_EXT, reg_data); 4184 } 4185 4186 netif_tx_start_all_queues(netdev); 4187 4188 if (!resuming) 4189 pm_runtime_put(&pdev->dev); 4190 4191 /* start the watchdog. */ 4192 hw->mac.get_link_status = 1; 4193 schedule_work(&adapter->watchdog_task); 4194 4195 return 0; 4196 4197 err_set_queues: 4198 igb_free_irq(adapter); 4199 err_req_irq: 4200 igb_release_hw_control(adapter); 4201 igb_power_down_link(adapter); 4202 igb_free_all_rx_resources(adapter); 4203 err_setup_rx: 4204 igb_free_all_tx_resources(adapter); 4205 err_setup_tx: 4206 igb_reset(adapter); 4207 if (!resuming) 4208 pm_runtime_put(&pdev->dev); 4209 4210 return err; 4211 } 4212 4213 int igb_open(struct net_device *netdev) 4214 { 4215 return __igb_open(netdev, false); 4216 } 4217 4218 /** 4219 * __igb_close - Disables a network interface 4220 * @netdev: network interface device structure 4221 * @suspending: indicates we are in a suspend call 4222 * 4223 * Returns 0, this is not allowed to fail 4224 * 4225 * The close entry point is called when an interface is de-activated 4226 * by the OS. The hardware is still under the driver's control, but 4227 * needs to be disabled. A global MAC reset is issued to stop the 4228 * hardware, and all transmit and receive resources are freed. 4229 **/ 4230 static int __igb_close(struct net_device *netdev, bool suspending) 4231 { 4232 struct igb_adapter *adapter = netdev_priv(netdev); 4233 struct pci_dev *pdev = adapter->pdev; 4234 4235 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4236 4237 if (!suspending) 4238 pm_runtime_get_sync(&pdev->dev); 4239 4240 igb_down(adapter); 4241 igb_free_irq(adapter); 4242 4243 igb_free_all_tx_resources(adapter); 4244 igb_free_all_rx_resources(adapter); 4245 4246 if (!suspending) 4247 pm_runtime_put_sync(&pdev->dev); 4248 return 0; 4249 } 4250 4251 int igb_close(struct net_device *netdev) 4252 { 4253 if (netif_device_present(netdev) || netdev->dismantle) 4254 return __igb_close(netdev, false); 4255 return 0; 4256 } 4257 4258 /** 4259 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4260 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4261 * 4262 * Return 0 on success, negative on failure 4263 **/ 4264 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4265 { 4266 struct device *dev = tx_ring->dev; 4267 int size; 4268 4269 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4270 4271 tx_ring->tx_buffer_info = vmalloc(size); 4272 if (!tx_ring->tx_buffer_info) 4273 goto err; 4274 4275 /* round up to nearest 4K */ 4276 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4277 tx_ring->size = ALIGN(tx_ring->size, 4096); 4278 4279 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4280 &tx_ring->dma, GFP_KERNEL); 4281 if (!tx_ring->desc) 4282 goto err; 4283 4284 tx_ring->next_to_use = 0; 4285 tx_ring->next_to_clean = 0; 4286 4287 return 0; 4288 4289 err: 4290 vfree(tx_ring->tx_buffer_info); 4291 tx_ring->tx_buffer_info = NULL; 4292 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4293 return -ENOMEM; 4294 } 4295 4296 /** 4297 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4298 * (Descriptors) for all queues 4299 * @adapter: board private structure 4300 * 4301 * Return 0 on success, negative on failure 4302 **/ 4303 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4304 { 4305 struct pci_dev *pdev = adapter->pdev; 4306 int i, err = 0; 4307 4308 for (i = 0; i < adapter->num_tx_queues; i++) { 4309 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4310 if (err) { 4311 dev_err(&pdev->dev, 4312 "Allocation for Tx Queue %u failed\n", i); 4313 for (i--; i >= 0; i--) 4314 igb_free_tx_resources(adapter->tx_ring[i]); 4315 break; 4316 } 4317 } 4318 4319 return err; 4320 } 4321 4322 /** 4323 * igb_setup_tctl - configure the transmit control registers 4324 * @adapter: Board private structure 4325 **/ 4326 void igb_setup_tctl(struct igb_adapter *adapter) 4327 { 4328 struct e1000_hw *hw = &adapter->hw; 4329 u32 tctl; 4330 4331 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4332 wr32(E1000_TXDCTL(0), 0); 4333 4334 /* Program the Transmit Control Register */ 4335 tctl = rd32(E1000_TCTL); 4336 tctl &= ~E1000_TCTL_CT; 4337 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4338 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4339 4340 igb_config_collision_dist(hw); 4341 4342 /* Enable transmits */ 4343 tctl |= E1000_TCTL_EN; 4344 4345 wr32(E1000_TCTL, tctl); 4346 } 4347 4348 /** 4349 * igb_configure_tx_ring - Configure transmit ring after Reset 4350 * @adapter: board private structure 4351 * @ring: tx ring to configure 4352 * 4353 * Configure a transmit ring after a reset. 4354 **/ 4355 void igb_configure_tx_ring(struct igb_adapter *adapter, 4356 struct igb_ring *ring) 4357 { 4358 struct e1000_hw *hw = &adapter->hw; 4359 u32 txdctl = 0; 4360 u64 tdba = ring->dma; 4361 int reg_idx = ring->reg_idx; 4362 4363 wr32(E1000_TDLEN(reg_idx), 4364 ring->count * sizeof(union e1000_adv_tx_desc)); 4365 wr32(E1000_TDBAL(reg_idx), 4366 tdba & 0x00000000ffffffffULL); 4367 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4368 4369 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4370 wr32(E1000_TDH(reg_idx), 0); 4371 writel(0, ring->tail); 4372 4373 txdctl |= IGB_TX_PTHRESH; 4374 txdctl |= IGB_TX_HTHRESH << 8; 4375 txdctl |= IGB_TX_WTHRESH << 16; 4376 4377 /* reinitialize tx_buffer_info */ 4378 memset(ring->tx_buffer_info, 0, 4379 sizeof(struct igb_tx_buffer) * ring->count); 4380 4381 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4382 wr32(E1000_TXDCTL(reg_idx), txdctl); 4383 } 4384 4385 /** 4386 * igb_configure_tx - Configure transmit Unit after Reset 4387 * @adapter: board private structure 4388 * 4389 * Configure the Tx unit of the MAC after a reset. 4390 **/ 4391 static void igb_configure_tx(struct igb_adapter *adapter) 4392 { 4393 struct e1000_hw *hw = &adapter->hw; 4394 int i; 4395 4396 /* disable the queues */ 4397 for (i = 0; i < adapter->num_tx_queues; i++) 4398 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4399 4400 wrfl(); 4401 usleep_range(10000, 20000); 4402 4403 for (i = 0; i < adapter->num_tx_queues; i++) 4404 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4405 } 4406 4407 /** 4408 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4409 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4410 * 4411 * Returns 0 on success, negative on failure 4412 **/ 4413 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4414 { 4415 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev); 4416 struct device *dev = rx_ring->dev; 4417 int size, res; 4418 4419 /* XDP RX-queue info */ 4420 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq)) 4421 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4422 res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 4423 rx_ring->queue_index, 0); 4424 if (res < 0) { 4425 dev_err(dev, "Failed to register xdp_rxq index %u\n", 4426 rx_ring->queue_index); 4427 return res; 4428 } 4429 4430 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4431 4432 rx_ring->rx_buffer_info = vmalloc(size); 4433 if (!rx_ring->rx_buffer_info) 4434 goto err; 4435 4436 /* Round up to nearest 4K */ 4437 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4438 rx_ring->size = ALIGN(rx_ring->size, 4096); 4439 4440 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4441 &rx_ring->dma, GFP_KERNEL); 4442 if (!rx_ring->desc) 4443 goto err; 4444 4445 rx_ring->next_to_alloc = 0; 4446 rx_ring->next_to_clean = 0; 4447 rx_ring->next_to_use = 0; 4448 4449 rx_ring->xdp_prog = adapter->xdp_prog; 4450 4451 return 0; 4452 4453 err: 4454 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4455 vfree(rx_ring->rx_buffer_info); 4456 rx_ring->rx_buffer_info = NULL; 4457 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4458 return -ENOMEM; 4459 } 4460 4461 /** 4462 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4463 * (Descriptors) for all queues 4464 * @adapter: board private structure 4465 * 4466 * Return 0 on success, negative on failure 4467 **/ 4468 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4469 { 4470 struct pci_dev *pdev = adapter->pdev; 4471 int i, err = 0; 4472 4473 for (i = 0; i < adapter->num_rx_queues; i++) { 4474 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4475 if (err) { 4476 dev_err(&pdev->dev, 4477 "Allocation for Rx Queue %u failed\n", i); 4478 for (i--; i >= 0; i--) 4479 igb_free_rx_resources(adapter->rx_ring[i]); 4480 break; 4481 } 4482 } 4483 4484 return err; 4485 } 4486 4487 /** 4488 * igb_setup_mrqc - configure the multiple receive queue control registers 4489 * @adapter: Board private structure 4490 **/ 4491 static void igb_setup_mrqc(struct igb_adapter *adapter) 4492 { 4493 struct e1000_hw *hw = &adapter->hw; 4494 u32 mrqc, rxcsum; 4495 u32 j, num_rx_queues; 4496 u32 rss_key[10]; 4497 4498 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4499 for (j = 0; j < 10; j++) 4500 wr32(E1000_RSSRK(j), rss_key[j]); 4501 4502 num_rx_queues = adapter->rss_queues; 4503 4504 switch (hw->mac.type) { 4505 case e1000_82576: 4506 /* 82576 supports 2 RSS queues for SR-IOV */ 4507 if (adapter->vfs_allocated_count) 4508 num_rx_queues = 2; 4509 break; 4510 default: 4511 break; 4512 } 4513 4514 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4515 for (j = 0; j < IGB_RETA_SIZE; j++) 4516 adapter->rss_indir_tbl[j] = 4517 (j * num_rx_queues) / IGB_RETA_SIZE; 4518 adapter->rss_indir_tbl_init = num_rx_queues; 4519 } 4520 igb_write_rss_indir_tbl(adapter); 4521 4522 /* Disable raw packet checksumming so that RSS hash is placed in 4523 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4524 * offloads as they are enabled by default 4525 */ 4526 rxcsum = rd32(E1000_RXCSUM); 4527 rxcsum |= E1000_RXCSUM_PCSD; 4528 4529 if (adapter->hw.mac.type >= e1000_82576) 4530 /* Enable Receive Checksum Offload for SCTP */ 4531 rxcsum |= E1000_RXCSUM_CRCOFL; 4532 4533 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4534 wr32(E1000_RXCSUM, rxcsum); 4535 4536 /* Generate RSS hash based on packet types, TCP/UDP 4537 * port numbers and/or IPv4/v6 src and dst addresses 4538 */ 4539 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4540 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4541 E1000_MRQC_RSS_FIELD_IPV6 | 4542 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4543 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4544 4545 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4546 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4547 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4548 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4549 4550 /* If VMDq is enabled then we set the appropriate mode for that, else 4551 * we default to RSS so that an RSS hash is calculated per packet even 4552 * if we are only using one queue 4553 */ 4554 if (adapter->vfs_allocated_count) { 4555 if (hw->mac.type > e1000_82575) { 4556 /* Set the default pool for the PF's first queue */ 4557 u32 vtctl = rd32(E1000_VT_CTL); 4558 4559 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4560 E1000_VT_CTL_DISABLE_DEF_POOL); 4561 vtctl |= adapter->vfs_allocated_count << 4562 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4563 wr32(E1000_VT_CTL, vtctl); 4564 } 4565 if (adapter->rss_queues > 1) 4566 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4567 else 4568 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4569 } else { 4570 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4571 } 4572 igb_vmm_control(adapter); 4573 4574 wr32(E1000_MRQC, mrqc); 4575 } 4576 4577 /** 4578 * igb_setup_rctl - configure the receive control registers 4579 * @adapter: Board private structure 4580 **/ 4581 void igb_setup_rctl(struct igb_adapter *adapter) 4582 { 4583 struct e1000_hw *hw = &adapter->hw; 4584 u32 rctl; 4585 4586 rctl = rd32(E1000_RCTL); 4587 4588 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4589 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4590 4591 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4592 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4593 4594 /* enable stripping of CRC. It's unlikely this will break BMC 4595 * redirection as it did with e1000. Newer features require 4596 * that the HW strips the CRC. 4597 */ 4598 rctl |= E1000_RCTL_SECRC; 4599 4600 /* disable store bad packets and clear size bits. */ 4601 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4602 4603 /* enable LPE to allow for reception of jumbo frames */ 4604 rctl |= E1000_RCTL_LPE; 4605 4606 /* disable queue 0 to prevent tail write w/o re-config */ 4607 wr32(E1000_RXDCTL(0), 0); 4608 4609 /* Attention!!! For SR-IOV PF driver operations you must enable 4610 * queue drop for all VF and PF queues to prevent head of line blocking 4611 * if an un-trusted VF does not provide descriptors to hardware. 4612 */ 4613 if (adapter->vfs_allocated_count) { 4614 /* set all queue drop enable bits */ 4615 wr32(E1000_QDE, ALL_QUEUES); 4616 } 4617 4618 /* This is useful for sniffing bad packets. */ 4619 if (adapter->netdev->features & NETIF_F_RXALL) { 4620 /* UPE and MPE will be handled by normal PROMISC logic 4621 * in e1000e_set_rx_mode 4622 */ 4623 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4624 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4625 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4626 4627 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4628 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4629 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4630 * and that breaks VLANs. 4631 */ 4632 } 4633 4634 wr32(E1000_RCTL, rctl); 4635 } 4636 4637 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4638 int vfn) 4639 { 4640 struct e1000_hw *hw = &adapter->hw; 4641 u32 vmolr; 4642 4643 if (size > MAX_JUMBO_FRAME_SIZE) 4644 size = MAX_JUMBO_FRAME_SIZE; 4645 4646 vmolr = rd32(E1000_VMOLR(vfn)); 4647 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4648 vmolr |= size | E1000_VMOLR_LPE; 4649 wr32(E1000_VMOLR(vfn), vmolr); 4650 4651 return 0; 4652 } 4653 4654 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4655 int vfn, bool enable) 4656 { 4657 struct e1000_hw *hw = &adapter->hw; 4658 u32 val, reg; 4659 4660 if (hw->mac.type < e1000_82576) 4661 return; 4662 4663 if (hw->mac.type == e1000_i350) 4664 reg = E1000_DVMOLR(vfn); 4665 else 4666 reg = E1000_VMOLR(vfn); 4667 4668 val = rd32(reg); 4669 if (enable) 4670 val |= E1000_VMOLR_STRVLAN; 4671 else 4672 val &= ~(E1000_VMOLR_STRVLAN); 4673 wr32(reg, val); 4674 } 4675 4676 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4677 int vfn, bool aupe) 4678 { 4679 struct e1000_hw *hw = &adapter->hw; 4680 u32 vmolr; 4681 4682 /* This register exists only on 82576 and newer so if we are older then 4683 * we should exit and do nothing 4684 */ 4685 if (hw->mac.type < e1000_82576) 4686 return; 4687 4688 vmolr = rd32(E1000_VMOLR(vfn)); 4689 if (aupe) 4690 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4691 else 4692 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4693 4694 /* clear all bits that might not be set */ 4695 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4696 4697 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4698 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4699 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4700 * multicast packets 4701 */ 4702 if (vfn <= adapter->vfs_allocated_count) 4703 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4704 4705 wr32(E1000_VMOLR(vfn), vmolr); 4706 } 4707 4708 /** 4709 * igb_setup_srrctl - configure the split and replication receive control 4710 * registers 4711 * @adapter: Board private structure 4712 * @ring: receive ring to be configured 4713 **/ 4714 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring) 4715 { 4716 struct e1000_hw *hw = &adapter->hw; 4717 int reg_idx = ring->reg_idx; 4718 u32 srrctl = 0; 4719 4720 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4721 if (ring_uses_large_buffer(ring)) 4722 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4723 else 4724 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4725 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4726 if (hw->mac.type >= e1000_82580) 4727 srrctl |= E1000_SRRCTL_TIMESTAMP; 4728 /* Only set Drop Enable if VFs allocated, or we are supporting multiple 4729 * queues and rx flow control is disabled 4730 */ 4731 if (adapter->vfs_allocated_count || 4732 (!(hw->fc.current_mode & e1000_fc_rx_pause) && 4733 adapter->num_rx_queues > 1)) 4734 srrctl |= E1000_SRRCTL_DROP_EN; 4735 4736 wr32(E1000_SRRCTL(reg_idx), srrctl); 4737 } 4738 4739 /** 4740 * igb_configure_rx_ring - Configure a receive ring after Reset 4741 * @adapter: board private structure 4742 * @ring: receive ring to be configured 4743 * 4744 * Configure the Rx unit of the MAC after a reset. 4745 **/ 4746 void igb_configure_rx_ring(struct igb_adapter *adapter, 4747 struct igb_ring *ring) 4748 { 4749 struct e1000_hw *hw = &adapter->hw; 4750 union e1000_adv_rx_desc *rx_desc; 4751 u64 rdba = ring->dma; 4752 int reg_idx = ring->reg_idx; 4753 u32 rxdctl = 0; 4754 4755 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4756 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4757 MEM_TYPE_PAGE_SHARED, NULL)); 4758 4759 /* disable the queue */ 4760 wr32(E1000_RXDCTL(reg_idx), 0); 4761 4762 /* Set DMA base address registers */ 4763 wr32(E1000_RDBAL(reg_idx), 4764 rdba & 0x00000000ffffffffULL); 4765 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4766 wr32(E1000_RDLEN(reg_idx), 4767 ring->count * sizeof(union e1000_adv_rx_desc)); 4768 4769 /* initialize head and tail */ 4770 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4771 wr32(E1000_RDH(reg_idx), 0); 4772 writel(0, ring->tail); 4773 4774 /* set descriptor configuration */ 4775 igb_setup_srrctl(adapter, ring); 4776 4777 /* set filtering for VMDQ pools */ 4778 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4779 4780 rxdctl |= IGB_RX_PTHRESH; 4781 rxdctl |= IGB_RX_HTHRESH << 8; 4782 rxdctl |= IGB_RX_WTHRESH << 16; 4783 4784 /* initialize rx_buffer_info */ 4785 memset(ring->rx_buffer_info, 0, 4786 sizeof(struct igb_rx_buffer) * ring->count); 4787 4788 /* initialize Rx descriptor 0 */ 4789 rx_desc = IGB_RX_DESC(ring, 0); 4790 rx_desc->wb.upper.length = 0; 4791 4792 /* enable receive descriptor fetching */ 4793 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4794 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4795 } 4796 4797 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4798 struct igb_ring *rx_ring) 4799 { 4800 #if (PAGE_SIZE < 8192) 4801 struct e1000_hw *hw = &adapter->hw; 4802 #endif 4803 4804 /* set build_skb and buffer size flags */ 4805 clear_ring_build_skb_enabled(rx_ring); 4806 clear_ring_uses_large_buffer(rx_ring); 4807 4808 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4809 return; 4810 4811 set_ring_build_skb_enabled(rx_ring); 4812 4813 #if (PAGE_SIZE < 8192) 4814 if (adapter->max_frame_size > IGB_MAX_FRAME_BUILD_SKB || 4815 IGB_2K_TOO_SMALL_WITH_PADDING || 4816 rd32(E1000_RCTL) & E1000_RCTL_SBP) 4817 set_ring_uses_large_buffer(rx_ring); 4818 #endif 4819 } 4820 4821 /** 4822 * igb_configure_rx - Configure receive Unit after Reset 4823 * @adapter: board private structure 4824 * 4825 * Configure the Rx unit of the MAC after a reset. 4826 **/ 4827 static void igb_configure_rx(struct igb_adapter *adapter) 4828 { 4829 int i; 4830 4831 /* set the correct pool for the PF default MAC address in entry 0 */ 4832 igb_set_default_mac_filter(adapter); 4833 4834 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4835 * the Base and Length of the Rx Descriptor Ring 4836 */ 4837 for (i = 0; i < adapter->num_rx_queues; i++) { 4838 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4839 4840 igb_set_rx_buffer_len(adapter, rx_ring); 4841 igb_configure_rx_ring(adapter, rx_ring); 4842 } 4843 } 4844 4845 /** 4846 * igb_free_tx_resources - Free Tx Resources per Queue 4847 * @tx_ring: Tx descriptor ring for a specific queue 4848 * 4849 * Free all transmit software resources 4850 **/ 4851 void igb_free_tx_resources(struct igb_ring *tx_ring) 4852 { 4853 igb_clean_tx_ring(tx_ring); 4854 4855 vfree(tx_ring->tx_buffer_info); 4856 tx_ring->tx_buffer_info = NULL; 4857 4858 /* if not set, then don't free */ 4859 if (!tx_ring->desc) 4860 return; 4861 4862 dma_free_coherent(tx_ring->dev, tx_ring->size, 4863 tx_ring->desc, tx_ring->dma); 4864 4865 tx_ring->desc = NULL; 4866 } 4867 4868 /** 4869 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4870 * @adapter: board private structure 4871 * 4872 * Free all transmit software resources 4873 **/ 4874 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4875 { 4876 int i; 4877 4878 for (i = 0; i < adapter->num_tx_queues; i++) 4879 if (adapter->tx_ring[i]) 4880 igb_free_tx_resources(adapter->tx_ring[i]); 4881 } 4882 4883 /** 4884 * igb_clean_tx_ring - Free Tx Buffers 4885 * @tx_ring: ring to be cleaned 4886 **/ 4887 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 4888 { 4889 u16 i = tx_ring->next_to_clean; 4890 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4891 4892 while (i != tx_ring->next_to_use) { 4893 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4894 4895 /* Free all the Tx ring sk_buffs or xdp frames */ 4896 if (tx_buffer->type == IGB_TYPE_SKB) 4897 dev_kfree_skb_any(tx_buffer->skb); 4898 else 4899 xdp_return_frame(tx_buffer->xdpf); 4900 4901 /* unmap skb header data */ 4902 dma_unmap_single(tx_ring->dev, 4903 dma_unmap_addr(tx_buffer, dma), 4904 dma_unmap_len(tx_buffer, len), 4905 DMA_TO_DEVICE); 4906 4907 /* check for eop_desc to determine the end of the packet */ 4908 eop_desc = tx_buffer->next_to_watch; 4909 tx_desc = IGB_TX_DESC(tx_ring, i); 4910 4911 /* unmap remaining buffers */ 4912 while (tx_desc != eop_desc) { 4913 tx_buffer++; 4914 tx_desc++; 4915 i++; 4916 if (unlikely(i == tx_ring->count)) { 4917 i = 0; 4918 tx_buffer = tx_ring->tx_buffer_info; 4919 tx_desc = IGB_TX_DESC(tx_ring, 0); 4920 } 4921 4922 /* unmap any remaining paged data */ 4923 if (dma_unmap_len(tx_buffer, len)) 4924 dma_unmap_page(tx_ring->dev, 4925 dma_unmap_addr(tx_buffer, dma), 4926 dma_unmap_len(tx_buffer, len), 4927 DMA_TO_DEVICE); 4928 } 4929 4930 tx_buffer->next_to_watch = NULL; 4931 4932 /* move us one more past the eop_desc for start of next pkt */ 4933 tx_buffer++; 4934 i++; 4935 if (unlikely(i == tx_ring->count)) { 4936 i = 0; 4937 tx_buffer = tx_ring->tx_buffer_info; 4938 } 4939 } 4940 4941 /* reset BQL for queue */ 4942 netdev_tx_reset_queue(txring_txq(tx_ring)); 4943 4944 /* reset next_to_use and next_to_clean */ 4945 tx_ring->next_to_use = 0; 4946 tx_ring->next_to_clean = 0; 4947 } 4948 4949 /** 4950 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 4951 * @adapter: board private structure 4952 **/ 4953 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 4954 { 4955 int i; 4956 4957 for (i = 0; i < adapter->num_tx_queues; i++) 4958 if (adapter->tx_ring[i]) 4959 igb_clean_tx_ring(adapter->tx_ring[i]); 4960 } 4961 4962 /** 4963 * igb_free_rx_resources - Free Rx Resources 4964 * @rx_ring: ring to clean the resources from 4965 * 4966 * Free all receive software resources 4967 **/ 4968 void igb_free_rx_resources(struct igb_ring *rx_ring) 4969 { 4970 igb_clean_rx_ring(rx_ring); 4971 4972 rx_ring->xdp_prog = NULL; 4973 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4974 vfree(rx_ring->rx_buffer_info); 4975 rx_ring->rx_buffer_info = NULL; 4976 4977 /* if not set, then don't free */ 4978 if (!rx_ring->desc) 4979 return; 4980 4981 dma_free_coherent(rx_ring->dev, rx_ring->size, 4982 rx_ring->desc, rx_ring->dma); 4983 4984 rx_ring->desc = NULL; 4985 } 4986 4987 /** 4988 * igb_free_all_rx_resources - Free Rx Resources for All Queues 4989 * @adapter: board private structure 4990 * 4991 * Free all receive software resources 4992 **/ 4993 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 4994 { 4995 int i; 4996 4997 for (i = 0; i < adapter->num_rx_queues; i++) 4998 if (adapter->rx_ring[i]) 4999 igb_free_rx_resources(adapter->rx_ring[i]); 5000 } 5001 5002 /** 5003 * igb_clean_rx_ring - Free Rx Buffers per Queue 5004 * @rx_ring: ring to free buffers from 5005 **/ 5006 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 5007 { 5008 u16 i = rx_ring->next_to_clean; 5009 5010 dev_kfree_skb(rx_ring->skb); 5011 rx_ring->skb = NULL; 5012 5013 /* Free all the Rx ring sk_buffs */ 5014 while (i != rx_ring->next_to_alloc) { 5015 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 5016 5017 /* Invalidate cache lines that may have been written to by 5018 * device so that we avoid corrupting memory. 5019 */ 5020 dma_sync_single_range_for_cpu(rx_ring->dev, 5021 buffer_info->dma, 5022 buffer_info->page_offset, 5023 igb_rx_bufsz(rx_ring), 5024 DMA_FROM_DEVICE); 5025 5026 /* free resources associated with mapping */ 5027 dma_unmap_page_attrs(rx_ring->dev, 5028 buffer_info->dma, 5029 igb_rx_pg_size(rx_ring), 5030 DMA_FROM_DEVICE, 5031 IGB_RX_DMA_ATTR); 5032 __page_frag_cache_drain(buffer_info->page, 5033 buffer_info->pagecnt_bias); 5034 5035 i++; 5036 if (i == rx_ring->count) 5037 i = 0; 5038 } 5039 5040 rx_ring->next_to_alloc = 0; 5041 rx_ring->next_to_clean = 0; 5042 rx_ring->next_to_use = 0; 5043 } 5044 5045 /** 5046 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 5047 * @adapter: board private structure 5048 **/ 5049 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 5050 { 5051 int i; 5052 5053 for (i = 0; i < adapter->num_rx_queues; i++) 5054 if (adapter->rx_ring[i]) 5055 igb_clean_rx_ring(adapter->rx_ring[i]); 5056 } 5057 5058 /** 5059 * igb_set_mac - Change the Ethernet Address of the NIC 5060 * @netdev: network interface device structure 5061 * @p: pointer to an address structure 5062 * 5063 * Returns 0 on success, negative on failure 5064 **/ 5065 static int igb_set_mac(struct net_device *netdev, void *p) 5066 { 5067 struct igb_adapter *adapter = netdev_priv(netdev); 5068 struct e1000_hw *hw = &adapter->hw; 5069 struct sockaddr *addr = p; 5070 5071 if (!is_valid_ether_addr(addr->sa_data)) 5072 return -EADDRNOTAVAIL; 5073 5074 eth_hw_addr_set(netdev, addr->sa_data); 5075 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 5076 5077 /* set the correct pool for the new PF MAC address in entry 0 */ 5078 igb_set_default_mac_filter(adapter); 5079 5080 return 0; 5081 } 5082 5083 /** 5084 * igb_write_mc_addr_list - write multicast addresses to MTA 5085 * @netdev: network interface device structure 5086 * 5087 * Writes multicast address list to the MTA hash table. 5088 * Returns: -ENOMEM on failure 5089 * 0 on no addresses written 5090 * X on writing X addresses to MTA 5091 **/ 5092 static int igb_write_mc_addr_list(struct net_device *netdev) 5093 { 5094 struct igb_adapter *adapter = netdev_priv(netdev); 5095 struct e1000_hw *hw = &adapter->hw; 5096 struct netdev_hw_addr *ha; 5097 u8 *mta_list; 5098 int i; 5099 5100 if (netdev_mc_empty(netdev)) { 5101 /* nothing to program, so clear mc list */ 5102 igb_update_mc_addr_list(hw, NULL, 0); 5103 igb_restore_vf_multicasts(adapter); 5104 return 0; 5105 } 5106 5107 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 5108 if (!mta_list) 5109 return -ENOMEM; 5110 5111 /* The shared function expects a packed array of only addresses. */ 5112 i = 0; 5113 netdev_for_each_mc_addr(ha, netdev) 5114 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 5115 5116 igb_update_mc_addr_list(hw, mta_list, i); 5117 kfree(mta_list); 5118 5119 return netdev_mc_count(netdev); 5120 } 5121 5122 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 5123 { 5124 struct e1000_hw *hw = &adapter->hw; 5125 u32 i, pf_id; 5126 5127 switch (hw->mac.type) { 5128 case e1000_i210: 5129 case e1000_i211: 5130 case e1000_i350: 5131 /* VLAN filtering needed for VLAN prio filter */ 5132 if (adapter->netdev->features & NETIF_F_NTUPLE) 5133 break; 5134 fallthrough; 5135 case e1000_82576: 5136 case e1000_82580: 5137 case e1000_i354: 5138 /* VLAN filtering needed for pool filtering */ 5139 if (adapter->vfs_allocated_count) 5140 break; 5141 fallthrough; 5142 default: 5143 return 1; 5144 } 5145 5146 /* We are already in VLAN promisc, nothing to do */ 5147 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 5148 return 0; 5149 5150 if (!adapter->vfs_allocated_count) 5151 goto set_vfta; 5152 5153 /* Add PF to all active pools */ 5154 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5155 5156 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5157 u32 vlvf = rd32(E1000_VLVF(i)); 5158 5159 vlvf |= BIT(pf_id); 5160 wr32(E1000_VLVF(i), vlvf); 5161 } 5162 5163 set_vfta: 5164 /* Set all bits in the VLAN filter table array */ 5165 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 5166 hw->mac.ops.write_vfta(hw, i, ~0U); 5167 5168 /* Set flag so we don't redo unnecessary work */ 5169 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 5170 5171 return 0; 5172 } 5173 5174 #define VFTA_BLOCK_SIZE 8 5175 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 5176 { 5177 struct e1000_hw *hw = &adapter->hw; 5178 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 5179 u32 vid_start = vfta_offset * 32; 5180 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 5181 u32 i, vid, word, bits, pf_id; 5182 5183 /* guarantee that we don't scrub out management VLAN */ 5184 vid = adapter->mng_vlan_id; 5185 if (vid >= vid_start && vid < vid_end) 5186 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5187 5188 if (!adapter->vfs_allocated_count) 5189 goto set_vfta; 5190 5191 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5192 5193 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5194 u32 vlvf = rd32(E1000_VLVF(i)); 5195 5196 /* pull VLAN ID from VLVF */ 5197 vid = vlvf & VLAN_VID_MASK; 5198 5199 /* only concern ourselves with a certain range */ 5200 if (vid < vid_start || vid >= vid_end) 5201 continue; 5202 5203 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 5204 /* record VLAN ID in VFTA */ 5205 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5206 5207 /* if PF is part of this then continue */ 5208 if (test_bit(vid, adapter->active_vlans)) 5209 continue; 5210 } 5211 5212 /* remove PF from the pool */ 5213 bits = ~BIT(pf_id); 5214 bits &= rd32(E1000_VLVF(i)); 5215 wr32(E1000_VLVF(i), bits); 5216 } 5217 5218 set_vfta: 5219 /* extract values from active_vlans and write back to VFTA */ 5220 for (i = VFTA_BLOCK_SIZE; i--;) { 5221 vid = (vfta_offset + i) * 32; 5222 word = vid / BITS_PER_LONG; 5223 bits = vid % BITS_PER_LONG; 5224 5225 vfta[i] |= adapter->active_vlans[word] >> bits; 5226 5227 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 5228 } 5229 } 5230 5231 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 5232 { 5233 u32 i; 5234 5235 /* We are not in VLAN promisc, nothing to do */ 5236 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 5237 return; 5238 5239 /* Set flag so we don't redo unnecessary work */ 5240 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 5241 5242 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 5243 igb_scrub_vfta(adapter, i); 5244 } 5245 5246 /** 5247 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 5248 * @netdev: network interface device structure 5249 * 5250 * The set_rx_mode entry point is called whenever the unicast or multicast 5251 * address lists or the network interface flags are updated. This routine is 5252 * responsible for configuring the hardware for proper unicast, multicast, 5253 * promiscuous mode, and all-multi behavior. 5254 **/ 5255 static void igb_set_rx_mode(struct net_device *netdev) 5256 { 5257 struct igb_adapter *adapter = netdev_priv(netdev); 5258 struct e1000_hw *hw = &adapter->hw; 5259 unsigned int vfn = adapter->vfs_allocated_count; 5260 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 5261 int count; 5262 5263 /* Check for Promiscuous and All Multicast modes */ 5264 if (netdev->flags & IFF_PROMISC) { 5265 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5266 vmolr |= E1000_VMOLR_MPME; 5267 5268 /* enable use of UTA filter to force packets to default pool */ 5269 if (hw->mac.type == e1000_82576) 5270 vmolr |= E1000_VMOLR_ROPE; 5271 } else { 5272 if (netdev->flags & IFF_ALLMULTI) { 5273 rctl |= E1000_RCTL_MPE; 5274 vmolr |= E1000_VMOLR_MPME; 5275 } else { 5276 /* Write addresses to the MTA, if the attempt fails 5277 * then we should just turn on promiscuous mode so 5278 * that we can at least receive multicast traffic 5279 */ 5280 count = igb_write_mc_addr_list(netdev); 5281 if (count < 0) { 5282 rctl |= E1000_RCTL_MPE; 5283 vmolr |= E1000_VMOLR_MPME; 5284 } else if (count) { 5285 vmolr |= E1000_VMOLR_ROMPE; 5286 } 5287 } 5288 } 5289 5290 /* Write addresses to available RAR registers, if there is not 5291 * sufficient space to store all the addresses then enable 5292 * unicast promiscuous mode 5293 */ 5294 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5295 rctl |= E1000_RCTL_UPE; 5296 vmolr |= E1000_VMOLR_ROPE; 5297 } 5298 5299 /* enable VLAN filtering by default */ 5300 rctl |= E1000_RCTL_VFE; 5301 5302 /* disable VLAN filtering for modes that require it */ 5303 if ((netdev->flags & IFF_PROMISC) || 5304 (netdev->features & NETIF_F_RXALL)) { 5305 /* if we fail to set all rules then just clear VFE */ 5306 if (igb_vlan_promisc_enable(adapter)) 5307 rctl &= ~E1000_RCTL_VFE; 5308 } else { 5309 igb_vlan_promisc_disable(adapter); 5310 } 5311 5312 /* update state of unicast, multicast, and VLAN filtering modes */ 5313 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5314 E1000_RCTL_VFE); 5315 wr32(E1000_RCTL, rctl); 5316 5317 #if (PAGE_SIZE < 8192) 5318 if (!adapter->vfs_allocated_count) { 5319 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5320 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5321 } 5322 #endif 5323 wr32(E1000_RLPML, rlpml); 5324 5325 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5326 * the VMOLR to enable the appropriate modes. Without this workaround 5327 * we will have issues with VLAN tag stripping not being done for frames 5328 * that are only arriving because we are the default pool 5329 */ 5330 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5331 return; 5332 5333 /* set UTA to appropriate mode */ 5334 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5335 5336 vmolr |= rd32(E1000_VMOLR(vfn)) & 5337 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5338 5339 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5340 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5341 #if (PAGE_SIZE < 8192) 5342 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5343 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5344 else 5345 #endif 5346 vmolr |= MAX_JUMBO_FRAME_SIZE; 5347 vmolr |= E1000_VMOLR_LPE; 5348 5349 wr32(E1000_VMOLR(vfn), vmolr); 5350 5351 igb_restore_vf_multicasts(adapter); 5352 } 5353 5354 static void igb_check_wvbr(struct igb_adapter *adapter) 5355 { 5356 struct e1000_hw *hw = &adapter->hw; 5357 u32 wvbr = 0; 5358 5359 switch (hw->mac.type) { 5360 case e1000_82576: 5361 case e1000_i350: 5362 wvbr = rd32(E1000_WVBR); 5363 if (!wvbr) 5364 return; 5365 break; 5366 default: 5367 break; 5368 } 5369 5370 adapter->wvbr |= wvbr; 5371 } 5372 5373 #define IGB_STAGGERED_QUEUE_OFFSET 8 5374 5375 static void igb_spoof_check(struct igb_adapter *adapter) 5376 { 5377 int j; 5378 5379 if (!adapter->wvbr) 5380 return; 5381 5382 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5383 if (adapter->wvbr & BIT(j) || 5384 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5385 dev_warn(&adapter->pdev->dev, 5386 "Spoof event(s) detected on VF %d\n", j); 5387 adapter->wvbr &= 5388 ~(BIT(j) | 5389 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5390 } 5391 } 5392 } 5393 5394 /* Need to wait a few seconds after link up to get diagnostic information from 5395 * the phy 5396 */ 5397 static void igb_update_phy_info(struct timer_list *t) 5398 { 5399 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5400 igb_get_phy_info(&adapter->hw); 5401 } 5402 5403 /** 5404 * igb_has_link - check shared code for link and determine up/down 5405 * @adapter: pointer to driver private info 5406 **/ 5407 bool igb_has_link(struct igb_adapter *adapter) 5408 { 5409 struct e1000_hw *hw = &adapter->hw; 5410 bool link_active = false; 5411 5412 /* get_link_status is set on LSC (link status) interrupt or 5413 * rx sequence error interrupt. get_link_status will stay 5414 * false until the e1000_check_for_link establishes link 5415 * for copper adapters ONLY 5416 */ 5417 switch (hw->phy.media_type) { 5418 case e1000_media_type_copper: 5419 if (!hw->mac.get_link_status) 5420 return true; 5421 fallthrough; 5422 case e1000_media_type_internal_serdes: 5423 hw->mac.ops.check_for_link(hw); 5424 link_active = !hw->mac.get_link_status; 5425 break; 5426 default: 5427 case e1000_media_type_unknown: 5428 break; 5429 } 5430 5431 if (((hw->mac.type == e1000_i210) || 5432 (hw->mac.type == e1000_i211)) && 5433 (hw->phy.id == I210_I_PHY_ID)) { 5434 if (!netif_carrier_ok(adapter->netdev)) { 5435 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5436 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5437 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5438 adapter->link_check_timeout = jiffies; 5439 } 5440 } 5441 5442 return link_active; 5443 } 5444 5445 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5446 { 5447 bool ret = false; 5448 u32 ctrl_ext, thstat; 5449 5450 /* check for thermal sensor event on i350 copper only */ 5451 if (hw->mac.type == e1000_i350) { 5452 thstat = rd32(E1000_THSTAT); 5453 ctrl_ext = rd32(E1000_CTRL_EXT); 5454 5455 if ((hw->phy.media_type == e1000_media_type_copper) && 5456 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5457 ret = !!(thstat & event); 5458 } 5459 5460 return ret; 5461 } 5462 5463 /** 5464 * igb_check_lvmmc - check for malformed packets received 5465 * and indicated in LVMMC register 5466 * @adapter: pointer to adapter 5467 **/ 5468 static void igb_check_lvmmc(struct igb_adapter *adapter) 5469 { 5470 struct e1000_hw *hw = &adapter->hw; 5471 u32 lvmmc; 5472 5473 lvmmc = rd32(E1000_LVMMC); 5474 if (lvmmc) { 5475 if (unlikely(net_ratelimit())) { 5476 netdev_warn(adapter->netdev, 5477 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5478 lvmmc); 5479 } 5480 } 5481 } 5482 5483 /** 5484 * igb_watchdog - Timer Call-back 5485 * @t: pointer to timer_list containing our private info pointer 5486 **/ 5487 static void igb_watchdog(struct timer_list *t) 5488 { 5489 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5490 /* Do the rest outside of interrupt context */ 5491 schedule_work(&adapter->watchdog_task); 5492 } 5493 5494 static void igb_watchdog_task(struct work_struct *work) 5495 { 5496 struct igb_adapter *adapter = container_of(work, 5497 struct igb_adapter, 5498 watchdog_task); 5499 struct e1000_hw *hw = &adapter->hw; 5500 struct e1000_phy_info *phy = &hw->phy; 5501 struct net_device *netdev = adapter->netdev; 5502 u32 link; 5503 int i; 5504 u32 connsw; 5505 u16 phy_data, retry_count = 20; 5506 5507 link = igb_has_link(adapter); 5508 5509 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5510 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5511 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5512 else 5513 link = false; 5514 } 5515 5516 /* Force link down if we have fiber to swap to */ 5517 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5518 if (hw->phy.media_type == e1000_media_type_copper) { 5519 connsw = rd32(E1000_CONNSW); 5520 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5521 link = 0; 5522 } 5523 } 5524 if (link) { 5525 /* Perform a reset if the media type changed. */ 5526 if (hw->dev_spec._82575.media_changed) { 5527 hw->dev_spec._82575.media_changed = false; 5528 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5529 igb_reset(adapter); 5530 } 5531 /* Cancel scheduled suspend requests. */ 5532 pm_runtime_resume(netdev->dev.parent); 5533 5534 if (!netif_carrier_ok(netdev)) { 5535 u32 ctrl; 5536 5537 hw->mac.ops.get_speed_and_duplex(hw, 5538 &adapter->link_speed, 5539 &adapter->link_duplex); 5540 5541 ctrl = rd32(E1000_CTRL); 5542 /* Links status message must follow this format */ 5543 netdev_info(netdev, 5544 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5545 netdev->name, 5546 adapter->link_speed, 5547 adapter->link_duplex == FULL_DUPLEX ? 5548 "Full" : "Half", 5549 (ctrl & E1000_CTRL_TFCE) && 5550 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5551 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5552 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5553 5554 /* disable EEE if enabled */ 5555 if ((adapter->flags & IGB_FLAG_EEE) && 5556 (adapter->link_duplex == HALF_DUPLEX)) { 5557 dev_info(&adapter->pdev->dev, 5558 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5559 adapter->hw.dev_spec._82575.eee_disable = true; 5560 adapter->flags &= ~IGB_FLAG_EEE; 5561 } 5562 5563 /* check if SmartSpeed worked */ 5564 igb_check_downshift(hw); 5565 if (phy->speed_downgraded) 5566 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5567 5568 /* check for thermal sensor event */ 5569 if (igb_thermal_sensor_event(hw, 5570 E1000_THSTAT_LINK_THROTTLE)) 5571 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5572 5573 /* adjust timeout factor according to speed/duplex */ 5574 adapter->tx_timeout_factor = 1; 5575 switch (adapter->link_speed) { 5576 case SPEED_10: 5577 adapter->tx_timeout_factor = 14; 5578 break; 5579 case SPEED_100: 5580 /* maybe add some timeout factor ? */ 5581 break; 5582 } 5583 5584 if (adapter->link_speed != SPEED_1000 || 5585 !hw->phy.ops.read_reg) 5586 goto no_wait; 5587 5588 /* wait for Remote receiver status OK */ 5589 retry_read_status: 5590 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5591 &phy_data)) { 5592 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5593 retry_count) { 5594 msleep(100); 5595 retry_count--; 5596 goto retry_read_status; 5597 } else if (!retry_count) { 5598 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5599 } 5600 } else { 5601 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5602 } 5603 no_wait: 5604 netif_carrier_on(netdev); 5605 5606 igb_ping_all_vfs(adapter); 5607 igb_check_vf_rate_limit(adapter); 5608 5609 /* link state has changed, schedule phy info update */ 5610 if (!test_bit(__IGB_DOWN, &adapter->state)) 5611 mod_timer(&adapter->phy_info_timer, 5612 round_jiffies(jiffies + 2 * HZ)); 5613 } 5614 } else { 5615 if (netif_carrier_ok(netdev)) { 5616 adapter->link_speed = 0; 5617 adapter->link_duplex = 0; 5618 5619 /* check for thermal sensor event */ 5620 if (igb_thermal_sensor_event(hw, 5621 E1000_THSTAT_PWR_DOWN)) { 5622 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5623 } 5624 5625 /* Links status message must follow this format */ 5626 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5627 netdev->name); 5628 netif_carrier_off(netdev); 5629 5630 igb_ping_all_vfs(adapter); 5631 5632 /* link state has changed, schedule phy info update */ 5633 if (!test_bit(__IGB_DOWN, &adapter->state)) 5634 mod_timer(&adapter->phy_info_timer, 5635 round_jiffies(jiffies + 2 * HZ)); 5636 5637 /* link is down, time to check for alternate media */ 5638 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5639 igb_check_swap_media(adapter); 5640 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5641 schedule_work(&adapter->reset_task); 5642 /* return immediately */ 5643 return; 5644 } 5645 } 5646 pm_schedule_suspend(netdev->dev.parent, 5647 MSEC_PER_SEC * 5); 5648 5649 /* also check for alternate media here */ 5650 } else if (!netif_carrier_ok(netdev) && 5651 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5652 igb_check_swap_media(adapter); 5653 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5654 schedule_work(&adapter->reset_task); 5655 /* return immediately */ 5656 return; 5657 } 5658 } 5659 } 5660 5661 spin_lock(&adapter->stats64_lock); 5662 igb_update_stats(adapter); 5663 spin_unlock(&adapter->stats64_lock); 5664 5665 for (i = 0; i < adapter->num_tx_queues; i++) { 5666 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5667 if (!netif_carrier_ok(netdev)) { 5668 /* We've lost link, so the controller stops DMA, 5669 * but we've got queued Tx work that's never going 5670 * to get done, so reset controller to flush Tx. 5671 * (Do the reset outside of interrupt context). 5672 */ 5673 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5674 adapter->tx_timeout_count++; 5675 schedule_work(&adapter->reset_task); 5676 /* return immediately since reset is imminent */ 5677 return; 5678 } 5679 } 5680 5681 /* Force detection of hung controller every watchdog period */ 5682 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5683 } 5684 5685 /* Cause software interrupt to ensure Rx ring is cleaned */ 5686 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5687 u32 eics = 0; 5688 5689 for (i = 0; i < adapter->num_q_vectors; i++) 5690 eics |= adapter->q_vector[i]->eims_value; 5691 wr32(E1000_EICS, eics); 5692 } else { 5693 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5694 } 5695 5696 igb_spoof_check(adapter); 5697 igb_ptp_rx_hang(adapter); 5698 igb_ptp_tx_hang(adapter); 5699 5700 /* Check LVMMC register on i350/i354 only */ 5701 if ((adapter->hw.mac.type == e1000_i350) || 5702 (adapter->hw.mac.type == e1000_i354)) 5703 igb_check_lvmmc(adapter); 5704 5705 /* Reset the timer */ 5706 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5707 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5708 mod_timer(&adapter->watchdog_timer, 5709 round_jiffies(jiffies + HZ)); 5710 else 5711 mod_timer(&adapter->watchdog_timer, 5712 round_jiffies(jiffies + 2 * HZ)); 5713 } 5714 } 5715 5716 enum latency_range { 5717 lowest_latency = 0, 5718 low_latency = 1, 5719 bulk_latency = 2, 5720 latency_invalid = 255 5721 }; 5722 5723 /** 5724 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5725 * @q_vector: pointer to q_vector 5726 * 5727 * Stores a new ITR value based on strictly on packet size. This 5728 * algorithm is less sophisticated than that used in igb_update_itr, 5729 * due to the difficulty of synchronizing statistics across multiple 5730 * receive rings. The divisors and thresholds used by this function 5731 * were determined based on theoretical maximum wire speed and testing 5732 * data, in order to minimize response time while increasing bulk 5733 * throughput. 5734 * This functionality is controlled by ethtool's coalescing settings. 5735 * NOTE: This function is called only when operating in a multiqueue 5736 * receive environment. 5737 **/ 5738 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5739 { 5740 int new_val = q_vector->itr_val; 5741 int avg_wire_size = 0; 5742 struct igb_adapter *adapter = q_vector->adapter; 5743 unsigned int packets; 5744 5745 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5746 * ints/sec - ITR timer value of 120 ticks. 5747 */ 5748 if (adapter->link_speed != SPEED_1000) { 5749 new_val = IGB_4K_ITR; 5750 goto set_itr_val; 5751 } 5752 5753 packets = q_vector->rx.total_packets; 5754 if (packets) 5755 avg_wire_size = q_vector->rx.total_bytes / packets; 5756 5757 packets = q_vector->tx.total_packets; 5758 if (packets) 5759 avg_wire_size = max_t(u32, avg_wire_size, 5760 q_vector->tx.total_bytes / packets); 5761 5762 /* if avg_wire_size isn't set no work was done */ 5763 if (!avg_wire_size) 5764 goto clear_counts; 5765 5766 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5767 avg_wire_size += 24; 5768 5769 /* Don't starve jumbo frames */ 5770 avg_wire_size = min(avg_wire_size, 3000); 5771 5772 /* Give a little boost to mid-size frames */ 5773 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5774 new_val = avg_wire_size / 3; 5775 else 5776 new_val = avg_wire_size / 2; 5777 5778 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5779 if (new_val < IGB_20K_ITR && 5780 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5781 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5782 new_val = IGB_20K_ITR; 5783 5784 set_itr_val: 5785 if (new_val != q_vector->itr_val) { 5786 q_vector->itr_val = new_val; 5787 q_vector->set_itr = 1; 5788 } 5789 clear_counts: 5790 q_vector->rx.total_bytes = 0; 5791 q_vector->rx.total_packets = 0; 5792 q_vector->tx.total_bytes = 0; 5793 q_vector->tx.total_packets = 0; 5794 } 5795 5796 /** 5797 * igb_update_itr - update the dynamic ITR value based on statistics 5798 * @q_vector: pointer to q_vector 5799 * @ring_container: ring info to update the itr for 5800 * 5801 * Stores a new ITR value based on packets and byte 5802 * counts during the last interrupt. The advantage of per interrupt 5803 * computation is faster updates and more accurate ITR for the current 5804 * traffic pattern. Constants in this function were computed 5805 * based on theoretical maximum wire speed and thresholds were set based 5806 * on testing data as well as attempting to minimize response time 5807 * while increasing bulk throughput. 5808 * This functionality is controlled by ethtool's coalescing settings. 5809 * NOTE: These calculations are only valid when operating in a single- 5810 * queue environment. 5811 **/ 5812 static void igb_update_itr(struct igb_q_vector *q_vector, 5813 struct igb_ring_container *ring_container) 5814 { 5815 unsigned int packets = ring_container->total_packets; 5816 unsigned int bytes = ring_container->total_bytes; 5817 u8 itrval = ring_container->itr; 5818 5819 /* no packets, exit with status unchanged */ 5820 if (packets == 0) 5821 return; 5822 5823 switch (itrval) { 5824 case lowest_latency: 5825 /* handle TSO and jumbo frames */ 5826 if (bytes/packets > 8000) 5827 itrval = bulk_latency; 5828 else if ((packets < 5) && (bytes > 512)) 5829 itrval = low_latency; 5830 break; 5831 case low_latency: /* 50 usec aka 20000 ints/s */ 5832 if (bytes > 10000) { 5833 /* this if handles the TSO accounting */ 5834 if (bytes/packets > 8000) 5835 itrval = bulk_latency; 5836 else if ((packets < 10) || ((bytes/packets) > 1200)) 5837 itrval = bulk_latency; 5838 else if ((packets > 35)) 5839 itrval = lowest_latency; 5840 } else if (bytes/packets > 2000) { 5841 itrval = bulk_latency; 5842 } else if (packets <= 2 && bytes < 512) { 5843 itrval = lowest_latency; 5844 } 5845 break; 5846 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5847 if (bytes > 25000) { 5848 if (packets > 35) 5849 itrval = low_latency; 5850 } else if (bytes < 1500) { 5851 itrval = low_latency; 5852 } 5853 break; 5854 } 5855 5856 /* clear work counters since we have the values we need */ 5857 ring_container->total_bytes = 0; 5858 ring_container->total_packets = 0; 5859 5860 /* write updated itr to ring container */ 5861 ring_container->itr = itrval; 5862 } 5863 5864 static void igb_set_itr(struct igb_q_vector *q_vector) 5865 { 5866 struct igb_adapter *adapter = q_vector->adapter; 5867 u32 new_itr = q_vector->itr_val; 5868 u8 current_itr = 0; 5869 5870 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5871 if (adapter->link_speed != SPEED_1000) { 5872 current_itr = 0; 5873 new_itr = IGB_4K_ITR; 5874 goto set_itr_now; 5875 } 5876 5877 igb_update_itr(q_vector, &q_vector->tx); 5878 igb_update_itr(q_vector, &q_vector->rx); 5879 5880 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5881 5882 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5883 if (current_itr == lowest_latency && 5884 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5885 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5886 current_itr = low_latency; 5887 5888 switch (current_itr) { 5889 /* counts and packets in update_itr are dependent on these numbers */ 5890 case lowest_latency: 5891 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5892 break; 5893 case low_latency: 5894 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5895 break; 5896 case bulk_latency: 5897 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5898 break; 5899 default: 5900 break; 5901 } 5902 5903 set_itr_now: 5904 if (new_itr != q_vector->itr_val) { 5905 /* this attempts to bias the interrupt rate towards Bulk 5906 * by adding intermediate steps when interrupt rate is 5907 * increasing 5908 */ 5909 new_itr = new_itr > q_vector->itr_val ? 5910 max((new_itr * q_vector->itr_val) / 5911 (new_itr + (q_vector->itr_val >> 2)), 5912 new_itr) : new_itr; 5913 /* Don't write the value here; it resets the adapter's 5914 * internal timer, and causes us to delay far longer than 5915 * we should between interrupts. Instead, we write the ITR 5916 * value at the beginning of the next interrupt so the timing 5917 * ends up being correct. 5918 */ 5919 q_vector->itr_val = new_itr; 5920 q_vector->set_itr = 1; 5921 } 5922 } 5923 5924 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 5925 struct igb_tx_buffer *first, 5926 u32 vlan_macip_lens, u32 type_tucmd, 5927 u32 mss_l4len_idx) 5928 { 5929 struct e1000_adv_tx_context_desc *context_desc; 5930 u16 i = tx_ring->next_to_use; 5931 struct timespec64 ts; 5932 5933 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5934 5935 i++; 5936 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 5937 5938 /* set bits to identify this as an advanced context descriptor */ 5939 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 5940 5941 /* For 82575, context index must be unique per ring. */ 5942 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5943 mss_l4len_idx |= tx_ring->reg_idx << 4; 5944 5945 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5946 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5947 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5948 5949 /* We assume there is always a valid tx time available. Invalid times 5950 * should have been handled by the upper layers. 5951 */ 5952 if (tx_ring->launchtime_enable) { 5953 ts = ktime_to_timespec64(first->skb->tstamp); 5954 skb_txtime_consumed(first->skb); 5955 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 5956 } else { 5957 context_desc->seqnum_seed = 0; 5958 } 5959 } 5960 5961 static int igb_tso(struct igb_ring *tx_ring, 5962 struct igb_tx_buffer *first, 5963 u8 *hdr_len) 5964 { 5965 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 5966 struct sk_buff *skb = first->skb; 5967 union { 5968 struct iphdr *v4; 5969 struct ipv6hdr *v6; 5970 unsigned char *hdr; 5971 } ip; 5972 union { 5973 struct tcphdr *tcp; 5974 struct udphdr *udp; 5975 unsigned char *hdr; 5976 } l4; 5977 u32 paylen, l4_offset; 5978 int err; 5979 5980 if (skb->ip_summed != CHECKSUM_PARTIAL) 5981 return 0; 5982 5983 if (!skb_is_gso(skb)) 5984 return 0; 5985 5986 err = skb_cow_head(skb, 0); 5987 if (err < 0) 5988 return err; 5989 5990 ip.hdr = skb_network_header(skb); 5991 l4.hdr = skb_checksum_start(skb); 5992 5993 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 5994 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 5995 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP; 5996 5997 /* initialize outer IP header fields */ 5998 if (ip.v4->version == 4) { 5999 unsigned char *csum_start = skb_checksum_start(skb); 6000 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 6001 6002 /* IP header will have to cancel out any data that 6003 * is not a part of the outer IP header 6004 */ 6005 ip.v4->check = csum_fold(csum_partial(trans_start, 6006 csum_start - trans_start, 6007 0)); 6008 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 6009 6010 ip.v4->tot_len = 0; 6011 first->tx_flags |= IGB_TX_FLAGS_TSO | 6012 IGB_TX_FLAGS_CSUM | 6013 IGB_TX_FLAGS_IPV4; 6014 } else { 6015 ip.v6->payload_len = 0; 6016 first->tx_flags |= IGB_TX_FLAGS_TSO | 6017 IGB_TX_FLAGS_CSUM; 6018 } 6019 6020 /* determine offset of inner transport header */ 6021 l4_offset = l4.hdr - skb->data; 6022 6023 /* remove payload length from inner checksum */ 6024 paylen = skb->len - l4_offset; 6025 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) { 6026 /* compute length of segmentation header */ 6027 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 6028 csum_replace_by_diff(&l4.tcp->check, 6029 (__force __wsum)htonl(paylen)); 6030 } else { 6031 /* compute length of segmentation header */ 6032 *hdr_len = sizeof(*l4.udp) + l4_offset; 6033 csum_replace_by_diff(&l4.udp->check, 6034 (__force __wsum)htonl(paylen)); 6035 } 6036 6037 /* update gso size and bytecount with header size */ 6038 first->gso_segs = skb_shinfo(skb)->gso_segs; 6039 first->bytecount += (first->gso_segs - 1) * *hdr_len; 6040 6041 /* MSS L4LEN IDX */ 6042 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 6043 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 6044 6045 /* VLAN MACLEN IPLEN */ 6046 vlan_macip_lens = l4.hdr - ip.hdr; 6047 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 6048 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6049 6050 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 6051 type_tucmd, mss_l4len_idx); 6052 6053 return 1; 6054 } 6055 6056 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 6057 { 6058 struct sk_buff *skb = first->skb; 6059 u32 vlan_macip_lens = 0; 6060 u32 type_tucmd = 0; 6061 6062 if (skb->ip_summed != CHECKSUM_PARTIAL) { 6063 csum_failed: 6064 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 6065 !tx_ring->launchtime_enable) 6066 return; 6067 goto no_csum; 6068 } 6069 6070 switch (skb->csum_offset) { 6071 case offsetof(struct tcphdr, check): 6072 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 6073 fallthrough; 6074 case offsetof(struct udphdr, check): 6075 break; 6076 case offsetof(struct sctphdr, checksum): 6077 /* validate that this is actually an SCTP request */ 6078 if (skb_csum_is_sctp(skb)) { 6079 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 6080 break; 6081 } 6082 fallthrough; 6083 default: 6084 skb_checksum_help(skb); 6085 goto csum_failed; 6086 } 6087 6088 /* update TX checksum flag */ 6089 first->tx_flags |= IGB_TX_FLAGS_CSUM; 6090 vlan_macip_lens = skb_checksum_start_offset(skb) - 6091 skb_network_offset(skb); 6092 no_csum: 6093 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 6094 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6095 6096 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 6097 } 6098 6099 #define IGB_SET_FLAG(_input, _flag, _result) \ 6100 ((_flag <= _result) ? \ 6101 ((u32)(_input & _flag) * (_result / _flag)) : \ 6102 ((u32)(_input & _flag) / (_flag / _result))) 6103 6104 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6105 { 6106 /* set type for advanced descriptor with frame checksum insertion */ 6107 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 6108 E1000_ADVTXD_DCMD_DEXT | 6109 E1000_ADVTXD_DCMD_IFCS; 6110 6111 /* set HW vlan bit if vlan is present */ 6112 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 6113 (E1000_ADVTXD_DCMD_VLE)); 6114 6115 /* set segmentation bits for TSO */ 6116 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 6117 (E1000_ADVTXD_DCMD_TSE)); 6118 6119 /* set timestamp bit if present */ 6120 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 6121 (E1000_ADVTXD_MAC_TSTAMP)); 6122 6123 /* insert frame checksum */ 6124 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 6125 6126 return cmd_type; 6127 } 6128 6129 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 6130 union e1000_adv_tx_desc *tx_desc, 6131 u32 tx_flags, unsigned int paylen) 6132 { 6133 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 6134 6135 /* 82575 requires a unique index per ring */ 6136 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6137 olinfo_status |= tx_ring->reg_idx << 4; 6138 6139 /* insert L4 checksum */ 6140 olinfo_status |= IGB_SET_FLAG(tx_flags, 6141 IGB_TX_FLAGS_CSUM, 6142 (E1000_TXD_POPTS_TXSM << 8)); 6143 6144 /* insert IPv4 checksum */ 6145 olinfo_status |= IGB_SET_FLAG(tx_flags, 6146 IGB_TX_FLAGS_IPV4, 6147 (E1000_TXD_POPTS_IXSM << 8)); 6148 6149 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6150 } 6151 6152 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6153 { 6154 struct net_device *netdev = tx_ring->netdev; 6155 6156 netif_stop_subqueue(netdev, tx_ring->queue_index); 6157 6158 /* Herbert's original patch had: 6159 * smp_mb__after_netif_stop_queue(); 6160 * but since that doesn't exist yet, just open code it. 6161 */ 6162 smp_mb(); 6163 6164 /* We need to check again in a case another CPU has just 6165 * made room available. 6166 */ 6167 if (igb_desc_unused(tx_ring) < size) 6168 return -EBUSY; 6169 6170 /* A reprieve! */ 6171 netif_wake_subqueue(netdev, tx_ring->queue_index); 6172 6173 u64_stats_update_begin(&tx_ring->tx_syncp2); 6174 tx_ring->tx_stats.restart_queue2++; 6175 u64_stats_update_end(&tx_ring->tx_syncp2); 6176 6177 return 0; 6178 } 6179 6180 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6181 { 6182 if (igb_desc_unused(tx_ring) >= size) 6183 return 0; 6184 return __igb_maybe_stop_tx(tx_ring, size); 6185 } 6186 6187 static int igb_tx_map(struct igb_ring *tx_ring, 6188 struct igb_tx_buffer *first, 6189 const u8 hdr_len) 6190 { 6191 struct sk_buff *skb = first->skb; 6192 struct igb_tx_buffer *tx_buffer; 6193 union e1000_adv_tx_desc *tx_desc; 6194 skb_frag_t *frag; 6195 dma_addr_t dma; 6196 unsigned int data_len, size; 6197 u32 tx_flags = first->tx_flags; 6198 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 6199 u16 i = tx_ring->next_to_use; 6200 6201 tx_desc = IGB_TX_DESC(tx_ring, i); 6202 6203 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 6204 6205 size = skb_headlen(skb); 6206 data_len = skb->data_len; 6207 6208 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6209 6210 tx_buffer = first; 6211 6212 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6213 if (dma_mapping_error(tx_ring->dev, dma)) 6214 goto dma_error; 6215 6216 /* record length, and DMA address */ 6217 dma_unmap_len_set(tx_buffer, len, size); 6218 dma_unmap_addr_set(tx_buffer, dma, dma); 6219 6220 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6221 6222 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 6223 tx_desc->read.cmd_type_len = 6224 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 6225 6226 i++; 6227 tx_desc++; 6228 if (i == tx_ring->count) { 6229 tx_desc = IGB_TX_DESC(tx_ring, 0); 6230 i = 0; 6231 } 6232 tx_desc->read.olinfo_status = 0; 6233 6234 dma += IGB_MAX_DATA_PER_TXD; 6235 size -= IGB_MAX_DATA_PER_TXD; 6236 6237 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6238 } 6239 6240 if (likely(!data_len)) 6241 break; 6242 6243 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6244 6245 i++; 6246 tx_desc++; 6247 if (i == tx_ring->count) { 6248 tx_desc = IGB_TX_DESC(tx_ring, 0); 6249 i = 0; 6250 } 6251 tx_desc->read.olinfo_status = 0; 6252 6253 size = skb_frag_size(frag); 6254 data_len -= size; 6255 6256 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6257 size, DMA_TO_DEVICE); 6258 6259 tx_buffer = &tx_ring->tx_buffer_info[i]; 6260 } 6261 6262 /* write last descriptor with RS and EOP bits */ 6263 cmd_type |= size | IGB_TXD_DCMD; 6264 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6265 6266 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6267 6268 /* set the timestamp */ 6269 first->time_stamp = jiffies; 6270 6271 skb_tx_timestamp(skb); 6272 6273 /* Force memory writes to complete before letting h/w know there 6274 * are new descriptors to fetch. (Only applicable for weak-ordered 6275 * memory model archs, such as IA-64). 6276 * 6277 * We also need this memory barrier to make certain all of the 6278 * status bits have been updated before next_to_watch is written. 6279 */ 6280 dma_wmb(); 6281 6282 /* set next_to_watch value indicating a packet is present */ 6283 first->next_to_watch = tx_desc; 6284 6285 i++; 6286 if (i == tx_ring->count) 6287 i = 0; 6288 6289 tx_ring->next_to_use = i; 6290 6291 /* Make sure there is space in the ring for the next send. */ 6292 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6293 6294 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6295 writel(i, tx_ring->tail); 6296 } 6297 return 0; 6298 6299 dma_error: 6300 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6301 tx_buffer = &tx_ring->tx_buffer_info[i]; 6302 6303 /* clear dma mappings for failed tx_buffer_info map */ 6304 while (tx_buffer != first) { 6305 if (dma_unmap_len(tx_buffer, len)) 6306 dma_unmap_page(tx_ring->dev, 6307 dma_unmap_addr(tx_buffer, dma), 6308 dma_unmap_len(tx_buffer, len), 6309 DMA_TO_DEVICE); 6310 dma_unmap_len_set(tx_buffer, len, 0); 6311 6312 if (i-- == 0) 6313 i += tx_ring->count; 6314 tx_buffer = &tx_ring->tx_buffer_info[i]; 6315 } 6316 6317 if (dma_unmap_len(tx_buffer, len)) 6318 dma_unmap_single(tx_ring->dev, 6319 dma_unmap_addr(tx_buffer, dma), 6320 dma_unmap_len(tx_buffer, len), 6321 DMA_TO_DEVICE); 6322 dma_unmap_len_set(tx_buffer, len, 0); 6323 6324 dev_kfree_skb_any(tx_buffer->skb); 6325 tx_buffer->skb = NULL; 6326 6327 tx_ring->next_to_use = i; 6328 6329 return -1; 6330 } 6331 6332 int igb_xmit_xdp_ring(struct igb_adapter *adapter, 6333 struct igb_ring *tx_ring, 6334 struct xdp_frame *xdpf) 6335 { 6336 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 6337 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 6338 u16 count, i, index = tx_ring->next_to_use; 6339 struct igb_tx_buffer *tx_head = &tx_ring->tx_buffer_info[index]; 6340 struct igb_tx_buffer *tx_buffer = tx_head; 6341 union e1000_adv_tx_desc *tx_desc = IGB_TX_DESC(tx_ring, index); 6342 u32 len = xdpf->len, cmd_type, olinfo_status; 6343 void *data = xdpf->data; 6344 6345 count = TXD_USE_COUNT(len); 6346 for (i = 0; i < nr_frags; i++) 6347 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i])); 6348 6349 if (igb_maybe_stop_tx(tx_ring, count + 3)) 6350 return IGB_XDP_CONSUMED; 6351 6352 i = 0; 6353 /* record the location of the first descriptor for this packet */ 6354 tx_head->bytecount = xdp_get_frame_len(xdpf); 6355 tx_head->type = IGB_TYPE_XDP; 6356 tx_head->gso_segs = 1; 6357 tx_head->xdpf = xdpf; 6358 6359 olinfo_status = tx_head->bytecount << E1000_ADVTXD_PAYLEN_SHIFT; 6360 /* 82575 requires a unique index per ring */ 6361 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6362 olinfo_status |= tx_ring->reg_idx << 4; 6363 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6364 6365 for (;;) { 6366 dma_addr_t dma; 6367 6368 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE); 6369 if (dma_mapping_error(tx_ring->dev, dma)) 6370 goto unmap; 6371 6372 /* record length, and DMA address */ 6373 dma_unmap_len_set(tx_buffer, len, len); 6374 dma_unmap_addr_set(tx_buffer, dma, dma); 6375 6376 /* put descriptor type bits */ 6377 cmd_type = E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_DEXT | 6378 E1000_ADVTXD_DCMD_IFCS | len; 6379 6380 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6381 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6382 6383 tx_buffer->protocol = 0; 6384 6385 if (++index == tx_ring->count) 6386 index = 0; 6387 6388 if (i == nr_frags) 6389 break; 6390 6391 tx_buffer = &tx_ring->tx_buffer_info[index]; 6392 tx_desc = IGB_TX_DESC(tx_ring, index); 6393 tx_desc->read.olinfo_status = 0; 6394 6395 data = skb_frag_address(&sinfo->frags[i]); 6396 len = skb_frag_size(&sinfo->frags[i]); 6397 i++; 6398 } 6399 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_TXD_DCMD); 6400 6401 netdev_tx_sent_queue(txring_txq(tx_ring), tx_head->bytecount); 6402 /* set the timestamp */ 6403 tx_head->time_stamp = jiffies; 6404 6405 /* Avoid any potential race with xdp_xmit and cleanup */ 6406 smp_wmb(); 6407 6408 /* set next_to_watch value indicating a packet is present */ 6409 tx_head->next_to_watch = tx_desc; 6410 tx_ring->next_to_use = index; 6411 6412 /* Make sure there is space in the ring for the next send. */ 6413 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6414 6415 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) 6416 writel(index, tx_ring->tail); 6417 6418 return IGB_XDP_TX; 6419 6420 unmap: 6421 for (;;) { 6422 tx_buffer = &tx_ring->tx_buffer_info[index]; 6423 if (dma_unmap_len(tx_buffer, len)) 6424 dma_unmap_page(tx_ring->dev, 6425 dma_unmap_addr(tx_buffer, dma), 6426 dma_unmap_len(tx_buffer, len), 6427 DMA_TO_DEVICE); 6428 dma_unmap_len_set(tx_buffer, len, 0); 6429 if (tx_buffer == tx_head) 6430 break; 6431 6432 if (!index) 6433 index += tx_ring->count; 6434 index--; 6435 } 6436 6437 return IGB_XDP_CONSUMED; 6438 } 6439 6440 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6441 struct igb_ring *tx_ring) 6442 { 6443 struct igb_tx_buffer *first; 6444 int tso; 6445 u32 tx_flags = 0; 6446 unsigned short f; 6447 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6448 __be16 protocol = vlan_get_protocol(skb); 6449 u8 hdr_len = 0; 6450 6451 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6452 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6453 * + 2 desc gap to keep tail from touching head, 6454 * + 1 desc for context descriptor, 6455 * otherwise try next time 6456 */ 6457 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6458 count += TXD_USE_COUNT(skb_frag_size( 6459 &skb_shinfo(skb)->frags[f])); 6460 6461 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6462 /* this is a hard error */ 6463 return NETDEV_TX_BUSY; 6464 } 6465 6466 /* record the location of the first descriptor for this packet */ 6467 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6468 first->type = IGB_TYPE_SKB; 6469 first->skb = skb; 6470 first->bytecount = skb->len; 6471 first->gso_segs = 1; 6472 6473 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6474 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6475 6476 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6477 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6478 &adapter->state)) { 6479 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6480 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6481 6482 adapter->ptp_tx_skb = skb_get(skb); 6483 adapter->ptp_tx_start = jiffies; 6484 if (adapter->hw.mac.type == e1000_82576) 6485 schedule_work(&adapter->ptp_tx_work); 6486 } else { 6487 adapter->tx_hwtstamp_skipped++; 6488 } 6489 } 6490 6491 if (skb_vlan_tag_present(skb)) { 6492 tx_flags |= IGB_TX_FLAGS_VLAN; 6493 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6494 } 6495 6496 /* record initial flags and protocol */ 6497 first->tx_flags = tx_flags; 6498 first->protocol = protocol; 6499 6500 tso = igb_tso(tx_ring, first, &hdr_len); 6501 if (tso < 0) 6502 goto out_drop; 6503 else if (!tso) 6504 igb_tx_csum(tx_ring, first); 6505 6506 if (igb_tx_map(tx_ring, first, hdr_len)) 6507 goto cleanup_tx_tstamp; 6508 6509 return NETDEV_TX_OK; 6510 6511 out_drop: 6512 dev_kfree_skb_any(first->skb); 6513 first->skb = NULL; 6514 cleanup_tx_tstamp: 6515 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6516 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6517 6518 dev_kfree_skb_any(adapter->ptp_tx_skb); 6519 adapter->ptp_tx_skb = NULL; 6520 if (adapter->hw.mac.type == e1000_82576) 6521 cancel_work_sync(&adapter->ptp_tx_work); 6522 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6523 } 6524 6525 return NETDEV_TX_OK; 6526 } 6527 6528 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6529 struct sk_buff *skb) 6530 { 6531 unsigned int r_idx = skb->queue_mapping; 6532 6533 if (r_idx >= adapter->num_tx_queues) 6534 r_idx = r_idx % adapter->num_tx_queues; 6535 6536 return adapter->tx_ring[r_idx]; 6537 } 6538 6539 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6540 struct net_device *netdev) 6541 { 6542 struct igb_adapter *adapter = netdev_priv(netdev); 6543 6544 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6545 * in order to meet this minimum size requirement. 6546 */ 6547 if (skb_put_padto(skb, 17)) 6548 return NETDEV_TX_OK; 6549 6550 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6551 } 6552 6553 /** 6554 * igb_tx_timeout - Respond to a Tx Hang 6555 * @netdev: network interface device structure 6556 * @txqueue: number of the Tx queue that hung (unused) 6557 **/ 6558 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6559 { 6560 struct igb_adapter *adapter = netdev_priv(netdev); 6561 struct e1000_hw *hw = &adapter->hw; 6562 6563 /* Do the reset outside of interrupt context */ 6564 adapter->tx_timeout_count++; 6565 6566 if (hw->mac.type >= e1000_82580) 6567 hw->dev_spec._82575.global_device_reset = true; 6568 6569 schedule_work(&adapter->reset_task); 6570 wr32(E1000_EICS, 6571 (adapter->eims_enable_mask & ~adapter->eims_other)); 6572 } 6573 6574 static void igb_reset_task(struct work_struct *work) 6575 { 6576 struct igb_adapter *adapter; 6577 adapter = container_of(work, struct igb_adapter, reset_task); 6578 6579 rtnl_lock(); 6580 /* If we're already down or resetting, just bail */ 6581 if (test_bit(__IGB_DOWN, &adapter->state) || 6582 test_bit(__IGB_RESETTING, &adapter->state)) { 6583 rtnl_unlock(); 6584 return; 6585 } 6586 6587 igb_dump(adapter); 6588 netdev_err(adapter->netdev, "Reset adapter\n"); 6589 igb_reinit_locked(adapter); 6590 rtnl_unlock(); 6591 } 6592 6593 /** 6594 * igb_get_stats64 - Get System Network Statistics 6595 * @netdev: network interface device structure 6596 * @stats: rtnl_link_stats64 pointer 6597 **/ 6598 static void igb_get_stats64(struct net_device *netdev, 6599 struct rtnl_link_stats64 *stats) 6600 { 6601 struct igb_adapter *adapter = netdev_priv(netdev); 6602 6603 spin_lock(&adapter->stats64_lock); 6604 igb_update_stats(adapter); 6605 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6606 spin_unlock(&adapter->stats64_lock); 6607 } 6608 6609 /** 6610 * igb_change_mtu - Change the Maximum Transfer Unit 6611 * @netdev: network interface device structure 6612 * @new_mtu: new value for maximum frame size 6613 * 6614 * Returns 0 on success, negative on failure 6615 **/ 6616 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6617 { 6618 struct igb_adapter *adapter = netdev_priv(netdev); 6619 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD; 6620 6621 if (adapter->xdp_prog) { 6622 int i; 6623 6624 for (i = 0; i < adapter->num_rx_queues; i++) { 6625 struct igb_ring *ring = adapter->rx_ring[i]; 6626 6627 if (max_frame > igb_rx_bufsz(ring)) { 6628 netdev_warn(adapter->netdev, 6629 "Requested MTU size is not supported with XDP. Max frame size is %d\n", 6630 max_frame); 6631 return -EINVAL; 6632 } 6633 } 6634 } 6635 6636 /* adjust max frame to be at least the size of a standard frame */ 6637 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6638 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6639 6640 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6641 usleep_range(1000, 2000); 6642 6643 /* igb_down has a dependency on max_frame_size */ 6644 adapter->max_frame_size = max_frame; 6645 6646 if (netif_running(netdev)) 6647 igb_down(adapter); 6648 6649 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6650 netdev->mtu, new_mtu); 6651 WRITE_ONCE(netdev->mtu, new_mtu); 6652 6653 if (netif_running(netdev)) 6654 igb_up(adapter); 6655 else 6656 igb_reset(adapter); 6657 6658 clear_bit(__IGB_RESETTING, &adapter->state); 6659 6660 return 0; 6661 } 6662 6663 /** 6664 * igb_update_stats - Update the board statistics counters 6665 * @adapter: board private structure 6666 **/ 6667 void igb_update_stats(struct igb_adapter *adapter) 6668 { 6669 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6670 struct e1000_hw *hw = &adapter->hw; 6671 struct pci_dev *pdev = adapter->pdev; 6672 u32 reg, mpc; 6673 int i; 6674 u64 bytes, packets; 6675 unsigned int start; 6676 u64 _bytes, _packets; 6677 6678 /* Prevent stats update while adapter is being reset, or if the pci 6679 * connection is down. 6680 */ 6681 if (adapter->link_speed == 0) 6682 return; 6683 if (pci_channel_offline(pdev)) 6684 return; 6685 6686 bytes = 0; 6687 packets = 0; 6688 6689 rcu_read_lock(); 6690 for (i = 0; i < adapter->num_rx_queues; i++) { 6691 struct igb_ring *ring = adapter->rx_ring[i]; 6692 u32 rqdpc = rd32(E1000_RQDPC(i)); 6693 if (hw->mac.type >= e1000_i210) 6694 wr32(E1000_RQDPC(i), 0); 6695 6696 if (rqdpc) { 6697 ring->rx_stats.drops += rqdpc; 6698 net_stats->rx_fifo_errors += rqdpc; 6699 } 6700 6701 do { 6702 start = u64_stats_fetch_begin(&ring->rx_syncp); 6703 _bytes = ring->rx_stats.bytes; 6704 _packets = ring->rx_stats.packets; 6705 } while (u64_stats_fetch_retry(&ring->rx_syncp, start)); 6706 bytes += _bytes; 6707 packets += _packets; 6708 } 6709 6710 net_stats->rx_bytes = bytes; 6711 net_stats->rx_packets = packets; 6712 6713 bytes = 0; 6714 packets = 0; 6715 for (i = 0; i < adapter->num_tx_queues; i++) { 6716 struct igb_ring *ring = adapter->tx_ring[i]; 6717 do { 6718 start = u64_stats_fetch_begin(&ring->tx_syncp); 6719 _bytes = ring->tx_stats.bytes; 6720 _packets = ring->tx_stats.packets; 6721 } while (u64_stats_fetch_retry(&ring->tx_syncp, start)); 6722 bytes += _bytes; 6723 packets += _packets; 6724 } 6725 net_stats->tx_bytes = bytes; 6726 net_stats->tx_packets = packets; 6727 rcu_read_unlock(); 6728 6729 /* read stats registers */ 6730 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6731 adapter->stats.gprc += rd32(E1000_GPRC); 6732 adapter->stats.gorc += rd32(E1000_GORCL); 6733 rd32(E1000_GORCH); /* clear GORCL */ 6734 adapter->stats.bprc += rd32(E1000_BPRC); 6735 adapter->stats.mprc += rd32(E1000_MPRC); 6736 adapter->stats.roc += rd32(E1000_ROC); 6737 6738 adapter->stats.prc64 += rd32(E1000_PRC64); 6739 adapter->stats.prc127 += rd32(E1000_PRC127); 6740 adapter->stats.prc255 += rd32(E1000_PRC255); 6741 adapter->stats.prc511 += rd32(E1000_PRC511); 6742 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6743 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6744 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6745 adapter->stats.sec += rd32(E1000_SEC); 6746 6747 mpc = rd32(E1000_MPC); 6748 adapter->stats.mpc += mpc; 6749 net_stats->rx_fifo_errors += mpc; 6750 adapter->stats.scc += rd32(E1000_SCC); 6751 adapter->stats.ecol += rd32(E1000_ECOL); 6752 adapter->stats.mcc += rd32(E1000_MCC); 6753 adapter->stats.latecol += rd32(E1000_LATECOL); 6754 adapter->stats.dc += rd32(E1000_DC); 6755 adapter->stats.rlec += rd32(E1000_RLEC); 6756 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6757 adapter->stats.xontxc += rd32(E1000_XONTXC); 6758 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6759 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6760 adapter->stats.fcruc += rd32(E1000_FCRUC); 6761 adapter->stats.gptc += rd32(E1000_GPTC); 6762 adapter->stats.gotc += rd32(E1000_GOTCL); 6763 rd32(E1000_GOTCH); /* clear GOTCL */ 6764 adapter->stats.rnbc += rd32(E1000_RNBC); 6765 adapter->stats.ruc += rd32(E1000_RUC); 6766 adapter->stats.rfc += rd32(E1000_RFC); 6767 adapter->stats.rjc += rd32(E1000_RJC); 6768 adapter->stats.tor += rd32(E1000_TORH); 6769 adapter->stats.tot += rd32(E1000_TOTH); 6770 adapter->stats.tpr += rd32(E1000_TPR); 6771 6772 adapter->stats.ptc64 += rd32(E1000_PTC64); 6773 adapter->stats.ptc127 += rd32(E1000_PTC127); 6774 adapter->stats.ptc255 += rd32(E1000_PTC255); 6775 adapter->stats.ptc511 += rd32(E1000_PTC511); 6776 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6777 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6778 6779 adapter->stats.mptc += rd32(E1000_MPTC); 6780 adapter->stats.bptc += rd32(E1000_BPTC); 6781 6782 adapter->stats.tpt += rd32(E1000_TPT); 6783 adapter->stats.colc += rd32(E1000_COLC); 6784 6785 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6786 /* read internal phy specific stats */ 6787 reg = rd32(E1000_CTRL_EXT); 6788 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6789 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6790 6791 /* this stat has invalid values on i210/i211 */ 6792 if ((hw->mac.type != e1000_i210) && 6793 (hw->mac.type != e1000_i211)) 6794 adapter->stats.tncrs += rd32(E1000_TNCRS); 6795 } 6796 6797 adapter->stats.tsctc += rd32(E1000_TSCTC); 6798 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6799 6800 adapter->stats.iac += rd32(E1000_IAC); 6801 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6802 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6803 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6804 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6805 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6806 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6807 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6808 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6809 6810 /* Fill out the OS statistics structure */ 6811 net_stats->multicast = adapter->stats.mprc; 6812 net_stats->collisions = adapter->stats.colc; 6813 6814 /* Rx Errors */ 6815 6816 /* RLEC on some newer hardware can be incorrect so build 6817 * our own version based on RUC and ROC 6818 */ 6819 net_stats->rx_errors = adapter->stats.rxerrc + 6820 adapter->stats.crcerrs + adapter->stats.algnerrc + 6821 adapter->stats.ruc + adapter->stats.roc + 6822 adapter->stats.cexterr; 6823 net_stats->rx_length_errors = adapter->stats.ruc + 6824 adapter->stats.roc; 6825 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6826 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6827 net_stats->rx_missed_errors = adapter->stats.mpc; 6828 6829 /* Tx Errors */ 6830 net_stats->tx_errors = adapter->stats.ecol + 6831 adapter->stats.latecol; 6832 net_stats->tx_aborted_errors = adapter->stats.ecol; 6833 net_stats->tx_window_errors = adapter->stats.latecol; 6834 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6835 6836 /* Tx Dropped needs to be maintained elsewhere */ 6837 6838 /* Management Stats */ 6839 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6840 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6841 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6842 6843 /* OS2BMC Stats */ 6844 reg = rd32(E1000_MANC); 6845 if (reg & E1000_MANC_EN_BMC2OS) { 6846 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6847 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6848 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6849 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6850 } 6851 } 6852 6853 static void igb_perout(struct igb_adapter *adapter, int tsintr_tt) 6854 { 6855 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_PEROUT, tsintr_tt); 6856 struct e1000_hw *hw = &adapter->hw; 6857 struct timespec64 ts; 6858 u32 tsauxc; 6859 6860 if (pin < 0 || pin >= IGB_N_SDP) 6861 return; 6862 6863 spin_lock(&adapter->tmreg_lock); 6864 6865 if (hw->mac.type == e1000_82580 || 6866 hw->mac.type == e1000_i354 || 6867 hw->mac.type == e1000_i350) { 6868 s64 ns = timespec64_to_ns(&adapter->perout[tsintr_tt].period); 6869 u32 systiml, systimh, level_mask, level, rem; 6870 u64 systim, now; 6871 6872 /* read systim registers in sequence */ 6873 rd32(E1000_SYSTIMR); 6874 systiml = rd32(E1000_SYSTIML); 6875 systimh = rd32(E1000_SYSTIMH); 6876 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml); 6877 now = timecounter_cyc2time(&adapter->tc, systim); 6878 6879 if (pin < 2) { 6880 level_mask = (tsintr_tt == 1) ? 0x80000 : 0x40000; 6881 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0; 6882 } else { 6883 level_mask = (tsintr_tt == 1) ? 0x80 : 0x40; 6884 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0; 6885 } 6886 6887 div_u64_rem(now, ns, &rem); 6888 systim = systim + (ns - rem); 6889 6890 /* synchronize pin level with rising/falling edges */ 6891 div_u64_rem(now, ns << 1, &rem); 6892 if (rem < ns) { 6893 /* first half of period */ 6894 if (level == 0) { 6895 /* output is already low, skip this period */ 6896 systim += ns; 6897 pr_notice("igb: periodic output on %s missed falling edge\n", 6898 adapter->sdp_config[pin].name); 6899 } 6900 } else { 6901 /* second half of period */ 6902 if (level == 1) { 6903 /* output is already high, skip this period */ 6904 systim += ns; 6905 pr_notice("igb: periodic output on %s missed rising edge\n", 6906 adapter->sdp_config[pin].name); 6907 } 6908 } 6909 6910 /* for this chip family tv_sec is the upper part of the binary value, 6911 * so not seconds 6912 */ 6913 ts.tv_nsec = (u32)systim; 6914 ts.tv_sec = ((u32)(systim >> 32)) & 0xFF; 6915 } else { 6916 ts = timespec64_add(adapter->perout[tsintr_tt].start, 6917 adapter->perout[tsintr_tt].period); 6918 } 6919 6920 /* u32 conversion of tv_sec is safe until y2106 */ 6921 wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec); 6922 wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec); 6923 tsauxc = rd32(E1000_TSAUXC); 6924 tsauxc |= TSAUXC_EN_TT0; 6925 wr32(E1000_TSAUXC, tsauxc); 6926 adapter->perout[tsintr_tt].start = ts; 6927 6928 spin_unlock(&adapter->tmreg_lock); 6929 } 6930 6931 static void igb_extts(struct igb_adapter *adapter, int tsintr_tt) 6932 { 6933 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_EXTTS, tsintr_tt); 6934 int auxstmpl = (tsintr_tt == 1) ? E1000_AUXSTMPL1 : E1000_AUXSTMPL0; 6935 int auxstmph = (tsintr_tt == 1) ? E1000_AUXSTMPH1 : E1000_AUXSTMPH0; 6936 struct e1000_hw *hw = &adapter->hw; 6937 struct ptp_clock_event event; 6938 struct timespec64 ts; 6939 unsigned long flags; 6940 6941 if (pin < 0 || pin >= IGB_N_SDP) 6942 return; 6943 6944 if (hw->mac.type == e1000_82580 || 6945 hw->mac.type == e1000_i354 || 6946 hw->mac.type == e1000_i350) { 6947 u64 ns = rd32(auxstmpl); 6948 6949 ns += ((u64)(rd32(auxstmph) & 0xFF)) << 32; 6950 spin_lock_irqsave(&adapter->tmreg_lock, flags); 6951 ns = timecounter_cyc2time(&adapter->tc, ns); 6952 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 6953 ts = ns_to_timespec64(ns); 6954 } else { 6955 ts.tv_nsec = rd32(auxstmpl); 6956 ts.tv_sec = rd32(auxstmph); 6957 } 6958 6959 event.type = PTP_CLOCK_EXTTS; 6960 event.index = tsintr_tt; 6961 event.timestamp = ts.tv_sec * 1000000000ULL + ts.tv_nsec; 6962 ptp_clock_event(adapter->ptp_clock, &event); 6963 } 6964 6965 static void igb_tsync_interrupt(struct igb_adapter *adapter) 6966 { 6967 const u32 mask = (TSINTR_SYS_WRAP | E1000_TSICR_TXTS | 6968 TSINTR_TT0 | TSINTR_TT1 | 6969 TSINTR_AUTT0 | TSINTR_AUTT1); 6970 struct e1000_hw *hw = &adapter->hw; 6971 u32 tsicr = rd32(E1000_TSICR); 6972 struct ptp_clock_event event; 6973 6974 if (hw->mac.type == e1000_82580) { 6975 /* 82580 has a hardware bug that requires an explicit 6976 * write to clear the TimeSync interrupt cause. 6977 */ 6978 wr32(E1000_TSICR, tsicr & mask); 6979 } 6980 6981 if (tsicr & TSINTR_SYS_WRAP) { 6982 event.type = PTP_CLOCK_PPS; 6983 if (adapter->ptp_caps.pps) 6984 ptp_clock_event(adapter->ptp_clock, &event); 6985 } 6986 6987 if (tsicr & E1000_TSICR_TXTS) { 6988 /* retrieve hardware timestamp */ 6989 schedule_work(&adapter->ptp_tx_work); 6990 } 6991 6992 if (tsicr & TSINTR_TT0) 6993 igb_perout(adapter, 0); 6994 6995 if (tsicr & TSINTR_TT1) 6996 igb_perout(adapter, 1); 6997 6998 if (tsicr & TSINTR_AUTT0) 6999 igb_extts(adapter, 0); 7000 7001 if (tsicr & TSINTR_AUTT1) 7002 igb_extts(adapter, 1); 7003 } 7004 7005 static irqreturn_t igb_msix_other(int irq, void *data) 7006 { 7007 struct igb_adapter *adapter = data; 7008 struct e1000_hw *hw = &adapter->hw; 7009 u32 icr = rd32(E1000_ICR); 7010 /* reading ICR causes bit 31 of EICR to be cleared */ 7011 7012 if (icr & E1000_ICR_DRSTA) 7013 schedule_work(&adapter->reset_task); 7014 7015 if (icr & E1000_ICR_DOUTSYNC) { 7016 /* HW is reporting DMA is out of sync */ 7017 adapter->stats.doosync++; 7018 /* The DMA Out of Sync is also indication of a spoof event 7019 * in IOV mode. Check the Wrong VM Behavior register to 7020 * see if it is really a spoof event. 7021 */ 7022 igb_check_wvbr(adapter); 7023 } 7024 7025 /* Check for a mailbox event */ 7026 if (icr & E1000_ICR_VMMB) 7027 igb_msg_task(adapter); 7028 7029 if (icr & E1000_ICR_LSC) { 7030 hw->mac.get_link_status = 1; 7031 /* guard against interrupt when we're going down */ 7032 if (!test_bit(__IGB_DOWN, &adapter->state)) 7033 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7034 } 7035 7036 if (icr & E1000_ICR_TS) 7037 igb_tsync_interrupt(adapter); 7038 7039 wr32(E1000_EIMS, adapter->eims_other); 7040 7041 return IRQ_HANDLED; 7042 } 7043 7044 static void igb_write_itr(struct igb_q_vector *q_vector) 7045 { 7046 struct igb_adapter *adapter = q_vector->adapter; 7047 u32 itr_val = q_vector->itr_val & 0x7FFC; 7048 7049 if (!q_vector->set_itr) 7050 return; 7051 7052 if (!itr_val) 7053 itr_val = 0x4; 7054 7055 if (adapter->hw.mac.type == e1000_82575) 7056 itr_val |= itr_val << 16; 7057 else 7058 itr_val |= E1000_EITR_CNT_IGNR; 7059 7060 writel(itr_val, q_vector->itr_register); 7061 q_vector->set_itr = 0; 7062 } 7063 7064 static irqreturn_t igb_msix_ring(int irq, void *data) 7065 { 7066 struct igb_q_vector *q_vector = data; 7067 7068 /* Write the ITR value calculated from the previous interrupt. */ 7069 igb_write_itr(q_vector); 7070 7071 napi_schedule(&q_vector->napi); 7072 7073 return IRQ_HANDLED; 7074 } 7075 7076 #ifdef CONFIG_IGB_DCA 7077 static void igb_update_tx_dca(struct igb_adapter *adapter, 7078 struct igb_ring *tx_ring, 7079 int cpu) 7080 { 7081 struct e1000_hw *hw = &adapter->hw; 7082 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 7083 7084 if (hw->mac.type != e1000_82575) 7085 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 7086 7087 /* We can enable relaxed ordering for reads, but not writes when 7088 * DCA is enabled. This is due to a known issue in some chipsets 7089 * which will cause the DCA tag to be cleared. 7090 */ 7091 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 7092 E1000_DCA_TXCTRL_DATA_RRO_EN | 7093 E1000_DCA_TXCTRL_DESC_DCA_EN; 7094 7095 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 7096 } 7097 7098 static void igb_update_rx_dca(struct igb_adapter *adapter, 7099 struct igb_ring *rx_ring, 7100 int cpu) 7101 { 7102 struct e1000_hw *hw = &adapter->hw; 7103 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 7104 7105 if (hw->mac.type != e1000_82575) 7106 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 7107 7108 /* We can enable relaxed ordering for reads, but not writes when 7109 * DCA is enabled. This is due to a known issue in some chipsets 7110 * which will cause the DCA tag to be cleared. 7111 */ 7112 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 7113 E1000_DCA_RXCTRL_DESC_DCA_EN; 7114 7115 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 7116 } 7117 7118 static void igb_update_dca(struct igb_q_vector *q_vector) 7119 { 7120 struct igb_adapter *adapter = q_vector->adapter; 7121 int cpu = get_cpu(); 7122 7123 if (q_vector->cpu == cpu) 7124 goto out_no_update; 7125 7126 if (q_vector->tx.ring) 7127 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 7128 7129 if (q_vector->rx.ring) 7130 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 7131 7132 q_vector->cpu = cpu; 7133 out_no_update: 7134 put_cpu(); 7135 } 7136 7137 static void igb_setup_dca(struct igb_adapter *adapter) 7138 { 7139 struct e1000_hw *hw = &adapter->hw; 7140 int i; 7141 7142 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 7143 return; 7144 7145 /* Always use CB2 mode, difference is masked in the CB driver. */ 7146 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 7147 7148 for (i = 0; i < adapter->num_q_vectors; i++) { 7149 adapter->q_vector[i]->cpu = -1; 7150 igb_update_dca(adapter->q_vector[i]); 7151 } 7152 } 7153 7154 static int __igb_notify_dca(struct device *dev, void *data) 7155 { 7156 struct net_device *netdev = dev_get_drvdata(dev); 7157 struct igb_adapter *adapter = netdev_priv(netdev); 7158 struct pci_dev *pdev = adapter->pdev; 7159 struct e1000_hw *hw = &adapter->hw; 7160 unsigned long event = *(unsigned long *)data; 7161 7162 switch (event) { 7163 case DCA_PROVIDER_ADD: 7164 /* if already enabled, don't do it again */ 7165 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 7166 break; 7167 if (dca_add_requester(dev) == 0) { 7168 adapter->flags |= IGB_FLAG_DCA_ENABLED; 7169 dev_info(&pdev->dev, "DCA enabled\n"); 7170 igb_setup_dca(adapter); 7171 break; 7172 } 7173 fallthrough; /* since DCA is disabled. */ 7174 case DCA_PROVIDER_REMOVE: 7175 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 7176 /* without this a class_device is left 7177 * hanging around in the sysfs model 7178 */ 7179 dca_remove_requester(dev); 7180 dev_info(&pdev->dev, "DCA disabled\n"); 7181 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 7182 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 7183 } 7184 break; 7185 } 7186 7187 return 0; 7188 } 7189 7190 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 7191 void *p) 7192 { 7193 int ret_val; 7194 7195 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 7196 __igb_notify_dca); 7197 7198 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 7199 } 7200 #endif /* CONFIG_IGB_DCA */ 7201 7202 #ifdef CONFIG_PCI_IOV 7203 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 7204 { 7205 unsigned char mac_addr[ETH_ALEN]; 7206 7207 eth_zero_addr(mac_addr); 7208 igb_set_vf_mac(adapter, vf, mac_addr); 7209 7210 /* By default spoof check is enabled for all VFs */ 7211 adapter->vf_data[vf].spoofchk_enabled = true; 7212 7213 /* By default VFs are not trusted */ 7214 adapter->vf_data[vf].trusted = false; 7215 7216 return 0; 7217 } 7218 7219 #endif 7220 static void igb_ping_all_vfs(struct igb_adapter *adapter) 7221 { 7222 struct e1000_hw *hw = &adapter->hw; 7223 u32 ping; 7224 int i; 7225 7226 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 7227 ping = E1000_PF_CONTROL_MSG; 7228 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 7229 ping |= E1000_VT_MSGTYPE_CTS; 7230 igb_write_mbx(hw, &ping, 1, i); 7231 } 7232 } 7233 7234 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7235 { 7236 struct e1000_hw *hw = &adapter->hw; 7237 u32 vmolr = rd32(E1000_VMOLR(vf)); 7238 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7239 7240 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 7241 IGB_VF_FLAG_MULTI_PROMISC); 7242 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7243 7244 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 7245 vmolr |= E1000_VMOLR_MPME; 7246 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 7247 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 7248 } else { 7249 /* if we have hashes and we are clearing a multicast promisc 7250 * flag we need to write the hashes to the MTA as this step 7251 * was previously skipped 7252 */ 7253 if (vf_data->num_vf_mc_hashes > 30) { 7254 vmolr |= E1000_VMOLR_MPME; 7255 } else if (vf_data->num_vf_mc_hashes) { 7256 int j; 7257 7258 vmolr |= E1000_VMOLR_ROMPE; 7259 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7260 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7261 } 7262 } 7263 7264 wr32(E1000_VMOLR(vf), vmolr); 7265 7266 /* there are flags left unprocessed, likely not supported */ 7267 if (*msgbuf & E1000_VT_MSGINFO_MASK) 7268 return -EINVAL; 7269 7270 return 0; 7271 } 7272 7273 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 7274 u32 *msgbuf, u32 vf) 7275 { 7276 int n = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]); 7277 u16 *hash_list = (u16 *)&msgbuf[1]; 7278 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7279 int i; 7280 7281 /* salt away the number of multicast addresses assigned 7282 * to this VF for later use to restore when the PF multi cast 7283 * list changes 7284 */ 7285 vf_data->num_vf_mc_hashes = n; 7286 7287 /* only up to 30 hash values supported */ 7288 if (n > 30) 7289 n = 30; 7290 7291 /* store the hashes for later use */ 7292 for (i = 0; i < n; i++) 7293 vf_data->vf_mc_hashes[i] = hash_list[i]; 7294 7295 /* Flush and reset the mta with the new values */ 7296 igb_set_rx_mode(adapter->netdev); 7297 7298 return 0; 7299 } 7300 7301 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 7302 { 7303 struct e1000_hw *hw = &adapter->hw; 7304 struct vf_data_storage *vf_data; 7305 int i, j; 7306 7307 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7308 u32 vmolr = rd32(E1000_VMOLR(i)); 7309 7310 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7311 7312 vf_data = &adapter->vf_data[i]; 7313 7314 if ((vf_data->num_vf_mc_hashes > 30) || 7315 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 7316 vmolr |= E1000_VMOLR_MPME; 7317 } else if (vf_data->num_vf_mc_hashes) { 7318 vmolr |= E1000_VMOLR_ROMPE; 7319 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7320 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7321 } 7322 wr32(E1000_VMOLR(i), vmolr); 7323 } 7324 } 7325 7326 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 7327 { 7328 struct e1000_hw *hw = &adapter->hw; 7329 u32 pool_mask, vlvf_mask, i; 7330 7331 /* create mask for VF and other pools */ 7332 pool_mask = E1000_VLVF_POOLSEL_MASK; 7333 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 7334 7335 /* drop PF from pool bits */ 7336 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 7337 adapter->vfs_allocated_count); 7338 7339 /* Find the vlan filter for this id */ 7340 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 7341 u32 vlvf = rd32(E1000_VLVF(i)); 7342 u32 vfta_mask, vid, vfta; 7343 7344 /* remove the vf from the pool */ 7345 if (!(vlvf & vlvf_mask)) 7346 continue; 7347 7348 /* clear out bit from VLVF */ 7349 vlvf ^= vlvf_mask; 7350 7351 /* if other pools are present, just remove ourselves */ 7352 if (vlvf & pool_mask) 7353 goto update_vlvfb; 7354 7355 /* if PF is present, leave VFTA */ 7356 if (vlvf & E1000_VLVF_POOLSEL_MASK) 7357 goto update_vlvf; 7358 7359 vid = vlvf & E1000_VLVF_VLANID_MASK; 7360 vfta_mask = BIT(vid % 32); 7361 7362 /* clear bit from VFTA */ 7363 vfta = adapter->shadow_vfta[vid / 32]; 7364 if (vfta & vfta_mask) 7365 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 7366 update_vlvf: 7367 /* clear pool selection enable */ 7368 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7369 vlvf &= E1000_VLVF_POOLSEL_MASK; 7370 else 7371 vlvf = 0; 7372 update_vlvfb: 7373 /* clear pool bits */ 7374 wr32(E1000_VLVF(i), vlvf); 7375 } 7376 } 7377 7378 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 7379 { 7380 u32 vlvf; 7381 int idx; 7382 7383 /* short cut the special case */ 7384 if (vlan == 0) 7385 return 0; 7386 7387 /* Search for the VLAN id in the VLVF entries */ 7388 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 7389 vlvf = rd32(E1000_VLVF(idx)); 7390 if ((vlvf & VLAN_VID_MASK) == vlan) 7391 break; 7392 } 7393 7394 return idx; 7395 } 7396 7397 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 7398 { 7399 struct e1000_hw *hw = &adapter->hw; 7400 u32 bits, pf_id; 7401 int idx; 7402 7403 idx = igb_find_vlvf_entry(hw, vid); 7404 if (!idx) 7405 return; 7406 7407 /* See if any other pools are set for this VLAN filter 7408 * entry other than the PF. 7409 */ 7410 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 7411 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 7412 bits &= rd32(E1000_VLVF(idx)); 7413 7414 /* Disable the filter so this falls into the default pool. */ 7415 if (!bits) { 7416 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7417 wr32(E1000_VLVF(idx), BIT(pf_id)); 7418 else 7419 wr32(E1000_VLVF(idx), 0); 7420 } 7421 } 7422 7423 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 7424 bool add, u32 vf) 7425 { 7426 int pf_id = adapter->vfs_allocated_count; 7427 struct e1000_hw *hw = &adapter->hw; 7428 int err; 7429 7430 /* If VLAN overlaps with one the PF is currently monitoring make 7431 * sure that we are able to allocate a VLVF entry. This may be 7432 * redundant but it guarantees PF will maintain visibility to 7433 * the VLAN. 7434 */ 7435 if (add && test_bit(vid, adapter->active_vlans)) { 7436 err = igb_vfta_set(hw, vid, pf_id, true, false); 7437 if (err) 7438 return err; 7439 } 7440 7441 err = igb_vfta_set(hw, vid, vf, add, false); 7442 7443 if (add && !err) 7444 return err; 7445 7446 /* If we failed to add the VF VLAN or we are removing the VF VLAN 7447 * we may need to drop the PF pool bit in order to allow us to free 7448 * up the VLVF resources. 7449 */ 7450 if (test_bit(vid, adapter->active_vlans) || 7451 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7452 igb_update_pf_vlvf(adapter, vid); 7453 7454 return err; 7455 } 7456 7457 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 7458 { 7459 struct e1000_hw *hw = &adapter->hw; 7460 7461 if (vid) 7462 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 7463 else 7464 wr32(E1000_VMVIR(vf), 0); 7465 } 7466 7467 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7468 u16 vlan, u8 qos) 7469 { 7470 int err; 7471 7472 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7473 if (err) 7474 return err; 7475 7476 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7477 igb_set_vmolr(adapter, vf, !vlan); 7478 7479 /* revoke access to previous VLAN */ 7480 if (vlan != adapter->vf_data[vf].pf_vlan) 7481 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7482 false, vf); 7483 7484 adapter->vf_data[vf].pf_vlan = vlan; 7485 adapter->vf_data[vf].pf_qos = qos; 7486 igb_set_vf_vlan_strip(adapter, vf, true); 7487 dev_info(&adapter->pdev->dev, 7488 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7489 if (test_bit(__IGB_DOWN, &adapter->state)) { 7490 dev_warn(&adapter->pdev->dev, 7491 "The VF VLAN has been set, but the PF device is not up.\n"); 7492 dev_warn(&adapter->pdev->dev, 7493 "Bring the PF device up before attempting to use the VF device.\n"); 7494 } 7495 7496 return err; 7497 } 7498 7499 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7500 { 7501 /* Restore tagless access via VLAN 0 */ 7502 igb_set_vf_vlan(adapter, 0, true, vf); 7503 7504 igb_set_vmvir(adapter, 0, vf); 7505 igb_set_vmolr(adapter, vf, true); 7506 7507 /* Remove any PF assigned VLAN */ 7508 if (adapter->vf_data[vf].pf_vlan) 7509 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7510 false, vf); 7511 7512 adapter->vf_data[vf].pf_vlan = 0; 7513 adapter->vf_data[vf].pf_qos = 0; 7514 igb_set_vf_vlan_strip(adapter, vf, false); 7515 7516 return 0; 7517 } 7518 7519 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7520 u16 vlan, u8 qos, __be16 vlan_proto) 7521 { 7522 struct igb_adapter *adapter = netdev_priv(netdev); 7523 7524 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7525 return -EINVAL; 7526 7527 if (vlan_proto != htons(ETH_P_8021Q)) 7528 return -EPROTONOSUPPORT; 7529 7530 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7531 igb_disable_port_vlan(adapter, vf); 7532 } 7533 7534 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7535 { 7536 int add = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]); 7537 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7538 int ret; 7539 7540 if (adapter->vf_data[vf].pf_vlan) 7541 return -1; 7542 7543 /* VLAN 0 is a special case, don't allow it to be removed */ 7544 if (!vid && !add) 7545 return 0; 7546 7547 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7548 if (!ret) 7549 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7550 return ret; 7551 } 7552 7553 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7554 { 7555 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7556 7557 /* clear flags - except flag that indicates PF has set the MAC */ 7558 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7559 vf_data->last_nack = jiffies; 7560 7561 /* reset vlans for device */ 7562 igb_clear_vf_vfta(adapter, vf); 7563 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7564 igb_set_vmvir(adapter, vf_data->pf_vlan | 7565 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7566 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7567 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7568 7569 /* reset multicast table array for vf */ 7570 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7571 7572 /* Flush and reset the mta with the new values */ 7573 igb_set_rx_mode(adapter->netdev); 7574 } 7575 7576 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7577 { 7578 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7579 7580 /* clear mac address as we were hotplug removed/added */ 7581 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7582 eth_zero_addr(vf_mac); 7583 7584 /* process remaining reset events */ 7585 igb_vf_reset(adapter, vf); 7586 } 7587 7588 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7589 { 7590 struct e1000_hw *hw = &adapter->hw; 7591 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7592 u32 reg, msgbuf[3] = {}; 7593 u8 *addr = (u8 *)(&msgbuf[1]); 7594 7595 /* process all the same items cleared in a function level reset */ 7596 igb_vf_reset(adapter, vf); 7597 7598 /* set vf mac address */ 7599 igb_set_vf_mac(adapter, vf, vf_mac); 7600 7601 /* enable transmit and receive for vf */ 7602 reg = rd32(E1000_VFTE); 7603 wr32(E1000_VFTE, reg | BIT(vf)); 7604 reg = rd32(E1000_VFRE); 7605 wr32(E1000_VFRE, reg | BIT(vf)); 7606 7607 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7608 7609 /* reply to reset with ack and vf mac address */ 7610 if (!is_zero_ether_addr(vf_mac)) { 7611 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7612 memcpy(addr, vf_mac, ETH_ALEN); 7613 } else { 7614 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7615 } 7616 igb_write_mbx(hw, msgbuf, 3, vf); 7617 } 7618 7619 static void igb_flush_mac_table(struct igb_adapter *adapter) 7620 { 7621 struct e1000_hw *hw = &adapter->hw; 7622 int i; 7623 7624 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7625 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7626 eth_zero_addr(adapter->mac_table[i].addr); 7627 adapter->mac_table[i].queue = 0; 7628 igb_rar_set_index(adapter, i); 7629 } 7630 } 7631 7632 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7633 { 7634 struct e1000_hw *hw = &adapter->hw; 7635 /* do not count rar entries reserved for VFs MAC addresses */ 7636 int rar_entries = hw->mac.rar_entry_count - 7637 adapter->vfs_allocated_count; 7638 int i, count = 0; 7639 7640 for (i = 0; i < rar_entries; i++) { 7641 /* do not count default entries */ 7642 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7643 continue; 7644 7645 /* do not count "in use" entries for different queues */ 7646 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7647 (adapter->mac_table[i].queue != queue)) 7648 continue; 7649 7650 count++; 7651 } 7652 7653 return count; 7654 } 7655 7656 /* Set default MAC address for the PF in the first RAR entry */ 7657 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7658 { 7659 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7660 7661 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7662 mac_table->queue = adapter->vfs_allocated_count; 7663 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7664 7665 igb_rar_set_index(adapter, 0); 7666 } 7667 7668 /* If the filter to be added and an already existing filter express 7669 * the same address and address type, it should be possible to only 7670 * override the other configurations, for example the queue to steer 7671 * traffic. 7672 */ 7673 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7674 const u8 *addr, const u8 flags) 7675 { 7676 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7677 return true; 7678 7679 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7680 (flags & IGB_MAC_STATE_SRC_ADDR)) 7681 return false; 7682 7683 if (!ether_addr_equal(addr, entry->addr)) 7684 return false; 7685 7686 return true; 7687 } 7688 7689 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7690 * 'flags' is used to indicate what kind of match is made, match is by 7691 * default for the destination address, if matching by source address 7692 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7693 */ 7694 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7695 const u8 *addr, const u8 queue, 7696 const u8 flags) 7697 { 7698 struct e1000_hw *hw = &adapter->hw; 7699 int rar_entries = hw->mac.rar_entry_count - 7700 adapter->vfs_allocated_count; 7701 int i; 7702 7703 if (is_zero_ether_addr(addr)) 7704 return -EINVAL; 7705 7706 /* Search for the first empty entry in the MAC table. 7707 * Do not touch entries at the end of the table reserved for the VF MAC 7708 * addresses. 7709 */ 7710 for (i = 0; i < rar_entries; i++) { 7711 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7712 addr, flags)) 7713 continue; 7714 7715 ether_addr_copy(adapter->mac_table[i].addr, addr); 7716 adapter->mac_table[i].queue = queue; 7717 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7718 7719 igb_rar_set_index(adapter, i); 7720 return i; 7721 } 7722 7723 return -ENOSPC; 7724 } 7725 7726 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7727 const u8 queue) 7728 { 7729 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7730 } 7731 7732 /* Remove a MAC filter for 'addr' directing matching traffic to 7733 * 'queue', 'flags' is used to indicate what kind of match need to be 7734 * removed, match is by default for the destination address, if 7735 * matching by source address is to be removed the flag 7736 * IGB_MAC_STATE_SRC_ADDR can be used. 7737 */ 7738 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7739 const u8 *addr, const u8 queue, 7740 const u8 flags) 7741 { 7742 struct e1000_hw *hw = &adapter->hw; 7743 int rar_entries = hw->mac.rar_entry_count - 7744 adapter->vfs_allocated_count; 7745 int i; 7746 7747 if (is_zero_ether_addr(addr)) 7748 return -EINVAL; 7749 7750 /* Search for matching entry in the MAC table based on given address 7751 * and queue. Do not touch entries at the end of the table reserved 7752 * for the VF MAC addresses. 7753 */ 7754 for (i = 0; i < rar_entries; i++) { 7755 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7756 continue; 7757 if ((adapter->mac_table[i].state & flags) != flags) 7758 continue; 7759 if (adapter->mac_table[i].queue != queue) 7760 continue; 7761 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7762 continue; 7763 7764 /* When a filter for the default address is "deleted", 7765 * we return it to its initial configuration 7766 */ 7767 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7768 adapter->mac_table[i].state = 7769 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7770 adapter->mac_table[i].queue = 7771 adapter->vfs_allocated_count; 7772 } else { 7773 adapter->mac_table[i].state = 0; 7774 adapter->mac_table[i].queue = 0; 7775 eth_zero_addr(adapter->mac_table[i].addr); 7776 } 7777 7778 igb_rar_set_index(adapter, i); 7779 return 0; 7780 } 7781 7782 return -ENOENT; 7783 } 7784 7785 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7786 const u8 queue) 7787 { 7788 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7789 } 7790 7791 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7792 const u8 *addr, u8 queue, u8 flags) 7793 { 7794 struct e1000_hw *hw = &adapter->hw; 7795 7796 /* In theory, this should be supported on 82575 as well, but 7797 * that part wasn't easily accessible during development. 7798 */ 7799 if (hw->mac.type != e1000_i210) 7800 return -EOPNOTSUPP; 7801 7802 return igb_add_mac_filter_flags(adapter, addr, queue, 7803 IGB_MAC_STATE_QUEUE_STEERING | flags); 7804 } 7805 7806 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7807 const u8 *addr, u8 queue, u8 flags) 7808 { 7809 return igb_del_mac_filter_flags(adapter, addr, queue, 7810 IGB_MAC_STATE_QUEUE_STEERING | flags); 7811 } 7812 7813 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7814 { 7815 struct igb_adapter *adapter = netdev_priv(netdev); 7816 int ret; 7817 7818 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7819 7820 return min_t(int, ret, 0); 7821 } 7822 7823 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7824 { 7825 struct igb_adapter *adapter = netdev_priv(netdev); 7826 7827 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7828 7829 return 0; 7830 } 7831 7832 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7833 const u32 info, const u8 *addr) 7834 { 7835 struct pci_dev *pdev = adapter->pdev; 7836 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7837 struct vf_mac_filter *entry; 7838 bool found = false; 7839 int ret = 0; 7840 7841 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7842 !vf_data->trusted) { 7843 dev_warn(&pdev->dev, 7844 "VF %d requested MAC filter but is administratively denied\n", 7845 vf); 7846 return -EINVAL; 7847 } 7848 if (!is_valid_ether_addr(addr)) { 7849 dev_warn(&pdev->dev, 7850 "VF %d attempted to set invalid MAC filter\n", 7851 vf); 7852 return -EINVAL; 7853 } 7854 7855 switch (info) { 7856 case E1000_VF_MAC_FILTER_CLR: 7857 /* remove all unicast MAC filters related to the current VF */ 7858 list_for_each_entry(entry, &adapter->vf_macs.l, l) { 7859 if (entry->vf == vf) { 7860 entry->vf = -1; 7861 entry->free = true; 7862 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7863 } 7864 } 7865 break; 7866 case E1000_VF_MAC_FILTER_ADD: 7867 /* try to find empty slot in the list */ 7868 list_for_each_entry(entry, &adapter->vf_macs.l, l) { 7869 if (entry->free) { 7870 found = true; 7871 break; 7872 } 7873 } 7874 7875 if (found) { 7876 entry->free = false; 7877 entry->vf = vf; 7878 ether_addr_copy(entry->vf_mac, addr); 7879 7880 ret = igb_add_mac_filter(adapter, addr, vf); 7881 ret = min_t(int, ret, 0); 7882 } else { 7883 ret = -ENOSPC; 7884 } 7885 7886 if (ret == -ENOSPC) 7887 dev_warn(&pdev->dev, 7888 "VF %d has requested MAC filter but there is no space for it\n", 7889 vf); 7890 break; 7891 default: 7892 ret = -EINVAL; 7893 break; 7894 } 7895 7896 return ret; 7897 } 7898 7899 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7900 { 7901 struct pci_dev *pdev = adapter->pdev; 7902 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7903 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7904 7905 /* The VF MAC Address is stored in a packed array of bytes 7906 * starting at the second 32 bit word of the msg array 7907 */ 7908 unsigned char *addr = (unsigned char *)&msg[1]; 7909 int ret = 0; 7910 7911 if (!info) { 7912 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7913 !vf_data->trusted) { 7914 dev_warn(&pdev->dev, 7915 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 7916 vf); 7917 return -EINVAL; 7918 } 7919 7920 if (!is_valid_ether_addr(addr)) { 7921 dev_warn(&pdev->dev, 7922 "VF %d attempted to set invalid MAC\n", 7923 vf); 7924 return -EINVAL; 7925 } 7926 7927 ret = igb_set_vf_mac(adapter, vf, addr); 7928 } else { 7929 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 7930 } 7931 7932 return ret; 7933 } 7934 7935 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 7936 { 7937 struct e1000_hw *hw = &adapter->hw; 7938 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7939 u32 msg = E1000_VT_MSGTYPE_NACK; 7940 7941 /* if device isn't clear to send it shouldn't be reading either */ 7942 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 7943 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 7944 igb_write_mbx(hw, &msg, 1, vf); 7945 vf_data->last_nack = jiffies; 7946 } 7947 } 7948 7949 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 7950 { 7951 struct pci_dev *pdev = adapter->pdev; 7952 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 7953 struct e1000_hw *hw = &adapter->hw; 7954 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7955 s32 retval; 7956 7957 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 7958 7959 if (retval) { 7960 /* if receive failed revoke VF CTS stats and restart init */ 7961 dev_err(&pdev->dev, "Error receiving message from VF\n"); 7962 vf_data->flags &= ~IGB_VF_FLAG_CTS; 7963 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7964 goto unlock; 7965 goto out; 7966 } 7967 7968 /* this is a message we already processed, do nothing */ 7969 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 7970 goto unlock; 7971 7972 /* until the vf completes a reset it should not be 7973 * allowed to start any configuration. 7974 */ 7975 if (msgbuf[0] == E1000_VF_RESET) { 7976 /* unlocks mailbox */ 7977 igb_vf_reset_msg(adapter, vf); 7978 return; 7979 } 7980 7981 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 7982 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7983 goto unlock; 7984 retval = -1; 7985 goto out; 7986 } 7987 7988 switch ((msgbuf[0] & 0xFFFF)) { 7989 case E1000_VF_SET_MAC_ADDR: 7990 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 7991 break; 7992 case E1000_VF_SET_PROMISC: 7993 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 7994 break; 7995 case E1000_VF_SET_MULTICAST: 7996 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 7997 break; 7998 case E1000_VF_SET_LPE: 7999 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 8000 break; 8001 case E1000_VF_SET_VLAN: 8002 retval = -1; 8003 if (vf_data->pf_vlan) 8004 dev_warn(&pdev->dev, 8005 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 8006 vf); 8007 else 8008 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 8009 break; 8010 default: 8011 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 8012 retval = -1; 8013 break; 8014 } 8015 8016 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 8017 out: 8018 /* notify the VF of the results of what it sent us */ 8019 if (retval) 8020 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 8021 else 8022 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 8023 8024 /* unlocks mailbox */ 8025 igb_write_mbx(hw, msgbuf, 1, vf); 8026 return; 8027 8028 unlock: 8029 igb_unlock_mbx(hw, vf); 8030 } 8031 8032 static void igb_msg_task(struct igb_adapter *adapter) 8033 { 8034 struct e1000_hw *hw = &adapter->hw; 8035 unsigned long flags; 8036 u32 vf; 8037 8038 spin_lock_irqsave(&adapter->vfs_lock, flags); 8039 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 8040 /* process any reset requests */ 8041 if (!igb_check_for_rst(hw, vf)) 8042 igb_vf_reset_event(adapter, vf); 8043 8044 /* process any messages pending */ 8045 if (!igb_check_for_msg(hw, vf)) 8046 igb_rcv_msg_from_vf(adapter, vf); 8047 8048 /* process any acks */ 8049 if (!igb_check_for_ack(hw, vf)) 8050 igb_rcv_ack_from_vf(adapter, vf); 8051 } 8052 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 8053 } 8054 8055 /** 8056 * igb_set_uta - Set unicast filter table address 8057 * @adapter: board private structure 8058 * @set: boolean indicating if we are setting or clearing bits 8059 * 8060 * The unicast table address is a register array of 32-bit registers. 8061 * The table is meant to be used in a way similar to how the MTA is used 8062 * however due to certain limitations in the hardware it is necessary to 8063 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 8064 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 8065 **/ 8066 static void igb_set_uta(struct igb_adapter *adapter, bool set) 8067 { 8068 struct e1000_hw *hw = &adapter->hw; 8069 u32 uta = set ? ~0 : 0; 8070 int i; 8071 8072 /* we only need to do this if VMDq is enabled */ 8073 if (!adapter->vfs_allocated_count) 8074 return; 8075 8076 for (i = hw->mac.uta_reg_count; i--;) 8077 array_wr32(E1000_UTA, i, uta); 8078 } 8079 8080 /** 8081 * igb_intr_msi - Interrupt Handler 8082 * @irq: interrupt number 8083 * @data: pointer to a network interface device structure 8084 **/ 8085 static irqreturn_t igb_intr_msi(int irq, void *data) 8086 { 8087 struct igb_adapter *adapter = data; 8088 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8089 struct e1000_hw *hw = &adapter->hw; 8090 /* read ICR disables interrupts using IAM */ 8091 u32 icr = rd32(E1000_ICR); 8092 8093 igb_write_itr(q_vector); 8094 8095 if (icr & E1000_ICR_DRSTA) 8096 schedule_work(&adapter->reset_task); 8097 8098 if (icr & E1000_ICR_DOUTSYNC) { 8099 /* HW is reporting DMA is out of sync */ 8100 adapter->stats.doosync++; 8101 } 8102 8103 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8104 hw->mac.get_link_status = 1; 8105 if (!test_bit(__IGB_DOWN, &adapter->state)) 8106 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8107 } 8108 8109 if (icr & E1000_ICR_TS) 8110 igb_tsync_interrupt(adapter); 8111 8112 napi_schedule(&q_vector->napi); 8113 8114 return IRQ_HANDLED; 8115 } 8116 8117 /** 8118 * igb_intr - Legacy Interrupt Handler 8119 * @irq: interrupt number 8120 * @data: pointer to a network interface device structure 8121 **/ 8122 static irqreturn_t igb_intr(int irq, void *data) 8123 { 8124 struct igb_adapter *adapter = data; 8125 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8126 struct e1000_hw *hw = &adapter->hw; 8127 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 8128 * need for the IMC write 8129 */ 8130 u32 icr = rd32(E1000_ICR); 8131 8132 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 8133 * not set, then the adapter didn't send an interrupt 8134 */ 8135 if (!(icr & E1000_ICR_INT_ASSERTED)) 8136 return IRQ_NONE; 8137 8138 igb_write_itr(q_vector); 8139 8140 if (icr & E1000_ICR_DRSTA) 8141 schedule_work(&adapter->reset_task); 8142 8143 if (icr & E1000_ICR_DOUTSYNC) { 8144 /* HW is reporting DMA is out of sync */ 8145 adapter->stats.doosync++; 8146 } 8147 8148 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8149 hw->mac.get_link_status = 1; 8150 /* guard against interrupt when we're going down */ 8151 if (!test_bit(__IGB_DOWN, &adapter->state)) 8152 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8153 } 8154 8155 if (icr & E1000_ICR_TS) 8156 igb_tsync_interrupt(adapter); 8157 8158 napi_schedule(&q_vector->napi); 8159 8160 return IRQ_HANDLED; 8161 } 8162 8163 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 8164 { 8165 struct igb_adapter *adapter = q_vector->adapter; 8166 struct e1000_hw *hw = &adapter->hw; 8167 8168 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 8169 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 8170 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 8171 igb_set_itr(q_vector); 8172 else 8173 igb_update_ring_itr(q_vector); 8174 } 8175 8176 if (!test_bit(__IGB_DOWN, &adapter->state)) { 8177 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8178 wr32(E1000_EIMS, q_vector->eims_value); 8179 else 8180 igb_irq_enable(adapter); 8181 } 8182 } 8183 8184 /** 8185 * igb_poll - NAPI Rx polling callback 8186 * @napi: napi polling structure 8187 * @budget: count of how many packets we should handle 8188 **/ 8189 static int igb_poll(struct napi_struct *napi, int budget) 8190 { 8191 struct igb_q_vector *q_vector = container_of(napi, 8192 struct igb_q_vector, 8193 napi); 8194 bool clean_complete = true; 8195 int work_done = 0; 8196 8197 #ifdef CONFIG_IGB_DCA 8198 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 8199 igb_update_dca(q_vector); 8200 #endif 8201 if (q_vector->tx.ring) 8202 clean_complete = igb_clean_tx_irq(q_vector, budget); 8203 8204 if (q_vector->rx.ring) { 8205 int cleaned = igb_clean_rx_irq(q_vector, budget); 8206 8207 work_done += cleaned; 8208 if (cleaned >= budget) 8209 clean_complete = false; 8210 } 8211 8212 /* If all work not completed, return budget and keep polling */ 8213 if (!clean_complete) 8214 return budget; 8215 8216 /* Exit the polling mode, but don't re-enable interrupts if stack might 8217 * poll us due to busy-polling 8218 */ 8219 if (likely(napi_complete_done(napi, work_done))) 8220 igb_ring_irq_enable(q_vector); 8221 8222 return work_done; 8223 } 8224 8225 /** 8226 * igb_clean_tx_irq - Reclaim resources after transmit completes 8227 * @q_vector: pointer to q_vector containing needed info 8228 * @napi_budget: Used to determine if we are in netpoll 8229 * 8230 * returns true if ring is completely cleaned 8231 **/ 8232 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 8233 { 8234 struct igb_adapter *adapter = q_vector->adapter; 8235 struct igb_ring *tx_ring = q_vector->tx.ring; 8236 struct igb_tx_buffer *tx_buffer; 8237 union e1000_adv_tx_desc *tx_desc; 8238 unsigned int total_bytes = 0, total_packets = 0; 8239 unsigned int budget = q_vector->tx.work_limit; 8240 unsigned int i = tx_ring->next_to_clean; 8241 8242 if (test_bit(__IGB_DOWN, &adapter->state)) 8243 return true; 8244 8245 tx_buffer = &tx_ring->tx_buffer_info[i]; 8246 tx_desc = IGB_TX_DESC(tx_ring, i); 8247 i -= tx_ring->count; 8248 8249 do { 8250 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 8251 8252 /* if next_to_watch is not set then there is no work pending */ 8253 if (!eop_desc) 8254 break; 8255 8256 /* prevent any other reads prior to eop_desc */ 8257 smp_rmb(); 8258 8259 /* if DD is not set pending work has not been completed */ 8260 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 8261 break; 8262 8263 /* clear next_to_watch to prevent false hangs */ 8264 tx_buffer->next_to_watch = NULL; 8265 8266 /* update the statistics for this packet */ 8267 total_bytes += tx_buffer->bytecount; 8268 total_packets += tx_buffer->gso_segs; 8269 8270 /* free the skb */ 8271 if (tx_buffer->type == IGB_TYPE_SKB) 8272 napi_consume_skb(tx_buffer->skb, napi_budget); 8273 else 8274 xdp_return_frame(tx_buffer->xdpf); 8275 8276 /* unmap skb header data */ 8277 dma_unmap_single(tx_ring->dev, 8278 dma_unmap_addr(tx_buffer, dma), 8279 dma_unmap_len(tx_buffer, len), 8280 DMA_TO_DEVICE); 8281 8282 /* clear tx_buffer data */ 8283 dma_unmap_len_set(tx_buffer, len, 0); 8284 8285 /* clear last DMA location and unmap remaining buffers */ 8286 while (tx_desc != eop_desc) { 8287 tx_buffer++; 8288 tx_desc++; 8289 i++; 8290 if (unlikely(!i)) { 8291 i -= tx_ring->count; 8292 tx_buffer = tx_ring->tx_buffer_info; 8293 tx_desc = IGB_TX_DESC(tx_ring, 0); 8294 } 8295 8296 /* unmap any remaining paged data */ 8297 if (dma_unmap_len(tx_buffer, len)) { 8298 dma_unmap_page(tx_ring->dev, 8299 dma_unmap_addr(tx_buffer, dma), 8300 dma_unmap_len(tx_buffer, len), 8301 DMA_TO_DEVICE); 8302 dma_unmap_len_set(tx_buffer, len, 0); 8303 } 8304 } 8305 8306 /* move us one more past the eop_desc for start of next pkt */ 8307 tx_buffer++; 8308 tx_desc++; 8309 i++; 8310 if (unlikely(!i)) { 8311 i -= tx_ring->count; 8312 tx_buffer = tx_ring->tx_buffer_info; 8313 tx_desc = IGB_TX_DESC(tx_ring, 0); 8314 } 8315 8316 /* issue prefetch for next Tx descriptor */ 8317 prefetch(tx_desc); 8318 8319 /* update budget accounting */ 8320 budget--; 8321 } while (likely(budget)); 8322 8323 netdev_tx_completed_queue(txring_txq(tx_ring), 8324 total_packets, total_bytes); 8325 i += tx_ring->count; 8326 tx_ring->next_to_clean = i; 8327 u64_stats_update_begin(&tx_ring->tx_syncp); 8328 tx_ring->tx_stats.bytes += total_bytes; 8329 tx_ring->tx_stats.packets += total_packets; 8330 u64_stats_update_end(&tx_ring->tx_syncp); 8331 q_vector->tx.total_bytes += total_bytes; 8332 q_vector->tx.total_packets += total_packets; 8333 8334 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 8335 struct e1000_hw *hw = &adapter->hw; 8336 8337 /* Detect a transmit hang in hardware, this serializes the 8338 * check with the clearing of time_stamp and movement of i 8339 */ 8340 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 8341 if (tx_buffer->next_to_watch && 8342 time_after(jiffies, tx_buffer->time_stamp + 8343 (adapter->tx_timeout_factor * HZ)) && 8344 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 8345 8346 /* detected Tx unit hang */ 8347 dev_err(tx_ring->dev, 8348 "Detected Tx Unit Hang\n" 8349 " Tx Queue <%d>\n" 8350 " TDH <%x>\n" 8351 " TDT <%x>\n" 8352 " next_to_use <%x>\n" 8353 " next_to_clean <%x>\n" 8354 "buffer_info[next_to_clean]\n" 8355 " time_stamp <%lx>\n" 8356 " next_to_watch <%p>\n" 8357 " jiffies <%lx>\n" 8358 " desc.status <%x>\n", 8359 tx_ring->queue_index, 8360 rd32(E1000_TDH(tx_ring->reg_idx)), 8361 readl(tx_ring->tail), 8362 tx_ring->next_to_use, 8363 tx_ring->next_to_clean, 8364 tx_buffer->time_stamp, 8365 tx_buffer->next_to_watch, 8366 jiffies, 8367 tx_buffer->next_to_watch->wb.status); 8368 netif_stop_subqueue(tx_ring->netdev, 8369 tx_ring->queue_index); 8370 8371 /* we are about to reset, no point in enabling stuff */ 8372 return true; 8373 } 8374 } 8375 8376 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 8377 if (unlikely(total_packets && 8378 netif_carrier_ok(tx_ring->netdev) && 8379 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 8380 /* Make sure that anybody stopping the queue after this 8381 * sees the new next_to_clean. 8382 */ 8383 smp_mb(); 8384 if (__netif_subqueue_stopped(tx_ring->netdev, 8385 tx_ring->queue_index) && 8386 !(test_bit(__IGB_DOWN, &adapter->state))) { 8387 netif_wake_subqueue(tx_ring->netdev, 8388 tx_ring->queue_index); 8389 8390 u64_stats_update_begin(&tx_ring->tx_syncp); 8391 tx_ring->tx_stats.restart_queue++; 8392 u64_stats_update_end(&tx_ring->tx_syncp); 8393 } 8394 } 8395 8396 return !!budget; 8397 } 8398 8399 /** 8400 * igb_reuse_rx_page - page flip buffer and store it back on the ring 8401 * @rx_ring: rx descriptor ring to store buffers on 8402 * @old_buff: donor buffer to have page reused 8403 * 8404 * Synchronizes page for reuse by the adapter 8405 **/ 8406 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 8407 struct igb_rx_buffer *old_buff) 8408 { 8409 struct igb_rx_buffer *new_buff; 8410 u16 nta = rx_ring->next_to_alloc; 8411 8412 new_buff = &rx_ring->rx_buffer_info[nta]; 8413 8414 /* update, and store next to alloc */ 8415 nta++; 8416 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 8417 8418 /* Transfer page from old buffer to new buffer. 8419 * Move each member individually to avoid possible store 8420 * forwarding stalls. 8421 */ 8422 new_buff->dma = old_buff->dma; 8423 new_buff->page = old_buff->page; 8424 new_buff->page_offset = old_buff->page_offset; 8425 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 8426 } 8427 8428 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 8429 int rx_buf_pgcnt) 8430 { 8431 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 8432 struct page *page = rx_buffer->page; 8433 8434 /* avoid re-using remote and pfmemalloc pages */ 8435 if (!dev_page_is_reusable(page)) 8436 return false; 8437 8438 #if (PAGE_SIZE < 8192) 8439 /* if we are only owner of page we can reuse it */ 8440 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1)) 8441 return false; 8442 #else 8443 #define IGB_LAST_OFFSET \ 8444 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 8445 8446 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 8447 return false; 8448 #endif 8449 8450 /* If we have drained the page fragment pool we need to update 8451 * the pagecnt_bias and page count so that we fully restock the 8452 * number of references the driver holds. 8453 */ 8454 if (unlikely(pagecnt_bias == 1)) { 8455 page_ref_add(page, USHRT_MAX - 1); 8456 rx_buffer->pagecnt_bias = USHRT_MAX; 8457 } 8458 8459 return true; 8460 } 8461 8462 /** 8463 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 8464 * @rx_ring: rx descriptor ring to transact packets on 8465 * @rx_buffer: buffer containing page to add 8466 * @skb: sk_buff to place the data into 8467 * @size: size of buffer to be added 8468 * 8469 * This function will add the data contained in rx_buffer->page to the skb. 8470 **/ 8471 static void igb_add_rx_frag(struct igb_ring *rx_ring, 8472 struct igb_rx_buffer *rx_buffer, 8473 struct sk_buff *skb, 8474 unsigned int size) 8475 { 8476 #if (PAGE_SIZE < 8192) 8477 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8478 #else 8479 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8480 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8481 SKB_DATA_ALIGN(size); 8482 #endif 8483 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8484 rx_buffer->page_offset, size, truesize); 8485 #if (PAGE_SIZE < 8192) 8486 rx_buffer->page_offset ^= truesize; 8487 #else 8488 rx_buffer->page_offset += truesize; 8489 #endif 8490 } 8491 8492 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8493 struct igb_rx_buffer *rx_buffer, 8494 struct xdp_buff *xdp, 8495 ktime_t timestamp) 8496 { 8497 #if (PAGE_SIZE < 8192) 8498 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8499 #else 8500 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 8501 xdp->data_hard_start); 8502 #endif 8503 unsigned int size = xdp->data_end - xdp->data; 8504 unsigned int headlen; 8505 struct sk_buff *skb; 8506 8507 /* prefetch first cache line of first page */ 8508 net_prefetch(xdp->data); 8509 8510 /* allocate a skb to store the frags */ 8511 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8512 if (unlikely(!skb)) 8513 return NULL; 8514 8515 if (timestamp) 8516 skb_hwtstamps(skb)->hwtstamp = timestamp; 8517 8518 /* Determine available headroom for copy */ 8519 headlen = size; 8520 if (headlen > IGB_RX_HDR_LEN) 8521 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN); 8522 8523 /* align pull length to size of long to optimize memcpy performance */ 8524 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long))); 8525 8526 /* update all of the pointers */ 8527 size -= headlen; 8528 if (size) { 8529 skb_add_rx_frag(skb, 0, rx_buffer->page, 8530 (xdp->data + headlen) - page_address(rx_buffer->page), 8531 size, truesize); 8532 #if (PAGE_SIZE < 8192) 8533 rx_buffer->page_offset ^= truesize; 8534 #else 8535 rx_buffer->page_offset += truesize; 8536 #endif 8537 } else { 8538 rx_buffer->pagecnt_bias++; 8539 } 8540 8541 return skb; 8542 } 8543 8544 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8545 struct igb_rx_buffer *rx_buffer, 8546 struct xdp_buff *xdp, 8547 ktime_t timestamp) 8548 { 8549 #if (PAGE_SIZE < 8192) 8550 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8551 #else 8552 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8553 SKB_DATA_ALIGN(xdp->data_end - 8554 xdp->data_hard_start); 8555 #endif 8556 unsigned int metasize = xdp->data - xdp->data_meta; 8557 struct sk_buff *skb; 8558 8559 /* prefetch first cache line of first page */ 8560 net_prefetch(xdp->data_meta); 8561 8562 /* build an skb around the page buffer */ 8563 skb = napi_build_skb(xdp->data_hard_start, truesize); 8564 if (unlikely(!skb)) 8565 return NULL; 8566 8567 /* update pointers within the skb to store the data */ 8568 skb_reserve(skb, xdp->data - xdp->data_hard_start); 8569 __skb_put(skb, xdp->data_end - xdp->data); 8570 8571 if (metasize) 8572 skb_metadata_set(skb, metasize); 8573 8574 if (timestamp) 8575 skb_hwtstamps(skb)->hwtstamp = timestamp; 8576 8577 /* update buffer offset */ 8578 #if (PAGE_SIZE < 8192) 8579 rx_buffer->page_offset ^= truesize; 8580 #else 8581 rx_buffer->page_offset += truesize; 8582 #endif 8583 8584 return skb; 8585 } 8586 8587 static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter, 8588 struct igb_ring *rx_ring, 8589 struct xdp_buff *xdp) 8590 { 8591 int err, result = IGB_XDP_PASS; 8592 struct bpf_prog *xdp_prog; 8593 u32 act; 8594 8595 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 8596 8597 if (!xdp_prog) 8598 goto xdp_out; 8599 8600 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 8601 8602 act = bpf_prog_run_xdp(xdp_prog, xdp); 8603 switch (act) { 8604 case XDP_PASS: 8605 break; 8606 case XDP_TX: 8607 result = igb_xdp_xmit_back(adapter, xdp); 8608 if (result == IGB_XDP_CONSUMED) 8609 goto out_failure; 8610 break; 8611 case XDP_REDIRECT: 8612 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 8613 if (err) 8614 goto out_failure; 8615 result = IGB_XDP_REDIR; 8616 break; 8617 default: 8618 bpf_warn_invalid_xdp_action(adapter->netdev, xdp_prog, act); 8619 fallthrough; 8620 case XDP_ABORTED: 8621 out_failure: 8622 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 8623 fallthrough; 8624 case XDP_DROP: 8625 result = IGB_XDP_CONSUMED; 8626 break; 8627 } 8628 xdp_out: 8629 return ERR_PTR(-result); 8630 } 8631 8632 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring, 8633 unsigned int size) 8634 { 8635 unsigned int truesize; 8636 8637 #if (PAGE_SIZE < 8192) 8638 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 8639 #else 8640 truesize = ring_uses_build_skb(rx_ring) ? 8641 SKB_DATA_ALIGN(IGB_SKB_PAD + size) + 8642 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 8643 SKB_DATA_ALIGN(size); 8644 #endif 8645 return truesize; 8646 } 8647 8648 static void igb_rx_buffer_flip(struct igb_ring *rx_ring, 8649 struct igb_rx_buffer *rx_buffer, 8650 unsigned int size) 8651 { 8652 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size); 8653 #if (PAGE_SIZE < 8192) 8654 rx_buffer->page_offset ^= truesize; 8655 #else 8656 rx_buffer->page_offset += truesize; 8657 #endif 8658 } 8659 8660 static inline void igb_rx_checksum(struct igb_ring *ring, 8661 union e1000_adv_rx_desc *rx_desc, 8662 struct sk_buff *skb) 8663 { 8664 skb_checksum_none_assert(skb); 8665 8666 /* Ignore Checksum bit is set */ 8667 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8668 return; 8669 8670 /* Rx checksum disabled via ethtool */ 8671 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8672 return; 8673 8674 /* TCP/UDP checksum error bit is set */ 8675 if (igb_test_staterr(rx_desc, 8676 E1000_RXDEXT_STATERR_TCPE | 8677 E1000_RXDEXT_STATERR_IPE)) { 8678 /* work around errata with sctp packets where the TCPE aka 8679 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8680 * packets, (aka let the stack check the crc32c) 8681 */ 8682 if (!((skb->len == 60) && 8683 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8684 u64_stats_update_begin(&ring->rx_syncp); 8685 ring->rx_stats.csum_err++; 8686 u64_stats_update_end(&ring->rx_syncp); 8687 } 8688 /* let the stack verify checksum errors */ 8689 return; 8690 } 8691 /* It must be a TCP or UDP packet with a valid checksum */ 8692 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8693 E1000_RXD_STAT_UDPCS)) 8694 skb->ip_summed = CHECKSUM_UNNECESSARY; 8695 8696 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8697 le32_to_cpu(rx_desc->wb.upper.status_error)); 8698 } 8699 8700 static inline void igb_rx_hash(struct igb_ring *ring, 8701 union e1000_adv_rx_desc *rx_desc, 8702 struct sk_buff *skb) 8703 { 8704 if (ring->netdev->features & NETIF_F_RXHASH) 8705 skb_set_hash(skb, 8706 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8707 PKT_HASH_TYPE_L3); 8708 } 8709 8710 /** 8711 * igb_is_non_eop - process handling of non-EOP buffers 8712 * @rx_ring: Rx ring being processed 8713 * @rx_desc: Rx descriptor for current buffer 8714 * 8715 * This function updates next to clean. If the buffer is an EOP buffer 8716 * this function exits returning false, otherwise it will place the 8717 * sk_buff in the next buffer to be chained and return true indicating 8718 * that this is in fact a non-EOP buffer. 8719 **/ 8720 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8721 union e1000_adv_rx_desc *rx_desc) 8722 { 8723 u32 ntc = rx_ring->next_to_clean + 1; 8724 8725 /* fetch, update, and store next to clean */ 8726 ntc = (ntc < rx_ring->count) ? ntc : 0; 8727 rx_ring->next_to_clean = ntc; 8728 8729 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8730 8731 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8732 return false; 8733 8734 return true; 8735 } 8736 8737 /** 8738 * igb_cleanup_headers - Correct corrupted or empty headers 8739 * @rx_ring: rx descriptor ring packet is being transacted on 8740 * @rx_desc: pointer to the EOP Rx descriptor 8741 * @skb: pointer to current skb being fixed 8742 * 8743 * Address the case where we are pulling data in on pages only 8744 * and as such no data is present in the skb header. 8745 * 8746 * In addition if skb is not at least 60 bytes we need to pad it so that 8747 * it is large enough to qualify as a valid Ethernet frame. 8748 * 8749 * Returns true if an error was encountered and skb was freed. 8750 **/ 8751 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8752 union e1000_adv_rx_desc *rx_desc, 8753 struct sk_buff *skb) 8754 { 8755 /* XDP packets use error pointer so abort at this point */ 8756 if (IS_ERR(skb)) 8757 return true; 8758 8759 if (unlikely((igb_test_staterr(rx_desc, 8760 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8761 struct net_device *netdev = rx_ring->netdev; 8762 if (!(netdev->features & NETIF_F_RXALL)) { 8763 dev_kfree_skb_any(skb); 8764 return true; 8765 } 8766 } 8767 8768 /* if eth_skb_pad returns an error the skb was freed */ 8769 if (eth_skb_pad(skb)) 8770 return true; 8771 8772 return false; 8773 } 8774 8775 /** 8776 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8777 * @rx_ring: rx descriptor ring packet is being transacted on 8778 * @rx_desc: pointer to the EOP Rx descriptor 8779 * @skb: pointer to current skb being populated 8780 * 8781 * This function checks the ring, descriptor, and packet information in 8782 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8783 * other fields within the skb. 8784 **/ 8785 static void igb_process_skb_fields(struct igb_ring *rx_ring, 8786 union e1000_adv_rx_desc *rx_desc, 8787 struct sk_buff *skb) 8788 { 8789 struct net_device *dev = rx_ring->netdev; 8790 8791 igb_rx_hash(rx_ring, rx_desc, skb); 8792 8793 igb_rx_checksum(rx_ring, rx_desc, skb); 8794 8795 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8796 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8797 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8798 8799 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8800 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8801 u16 vid; 8802 8803 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8804 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8805 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan); 8806 else 8807 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8808 8809 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8810 } 8811 8812 skb_record_rx_queue(skb, rx_ring->queue_index); 8813 8814 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8815 } 8816 8817 static unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8818 { 8819 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8820 } 8821 8822 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8823 const unsigned int size, int *rx_buf_pgcnt) 8824 { 8825 struct igb_rx_buffer *rx_buffer; 8826 8827 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8828 *rx_buf_pgcnt = 8829 #if (PAGE_SIZE < 8192) 8830 page_count(rx_buffer->page); 8831 #else 8832 0; 8833 #endif 8834 prefetchw(rx_buffer->page); 8835 8836 /* we are reusing so sync this buffer for CPU use */ 8837 dma_sync_single_range_for_cpu(rx_ring->dev, 8838 rx_buffer->dma, 8839 rx_buffer->page_offset, 8840 size, 8841 DMA_FROM_DEVICE); 8842 8843 rx_buffer->pagecnt_bias--; 8844 8845 return rx_buffer; 8846 } 8847 8848 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8849 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt) 8850 { 8851 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) { 8852 /* hand second half of page back to the ring */ 8853 igb_reuse_rx_page(rx_ring, rx_buffer); 8854 } else { 8855 /* We are not reusing the buffer so unmap it and free 8856 * any references we are holding to it 8857 */ 8858 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8859 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8860 IGB_RX_DMA_ATTR); 8861 __page_frag_cache_drain(rx_buffer->page, 8862 rx_buffer->pagecnt_bias); 8863 } 8864 8865 /* clear contents of rx_buffer */ 8866 rx_buffer->page = NULL; 8867 } 8868 8869 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 8870 { 8871 unsigned int total_bytes = 0, total_packets = 0; 8872 struct igb_adapter *adapter = q_vector->adapter; 8873 struct igb_ring *rx_ring = q_vector->rx.ring; 8874 u16 cleaned_count = igb_desc_unused(rx_ring); 8875 struct sk_buff *skb = rx_ring->skb; 8876 int cpu = smp_processor_id(); 8877 unsigned int xdp_xmit = 0; 8878 struct netdev_queue *nq; 8879 struct xdp_buff xdp; 8880 u32 frame_sz = 0; 8881 int rx_buf_pgcnt; 8882 8883 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 8884 #if (PAGE_SIZE < 8192) 8885 frame_sz = igb_rx_frame_truesize(rx_ring, 0); 8886 #endif 8887 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 8888 8889 while (likely(total_packets < budget)) { 8890 union e1000_adv_rx_desc *rx_desc; 8891 struct igb_rx_buffer *rx_buffer; 8892 ktime_t timestamp = 0; 8893 int pkt_offset = 0; 8894 unsigned int size; 8895 void *pktbuf; 8896 8897 /* return some buffers to hardware, one at a time is too slow */ 8898 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 8899 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8900 cleaned_count = 0; 8901 } 8902 8903 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 8904 size = le16_to_cpu(rx_desc->wb.upper.length); 8905 if (!size) 8906 break; 8907 8908 /* This memory barrier is needed to keep us from reading 8909 * any other fields out of the rx_desc until we know the 8910 * descriptor has been written back 8911 */ 8912 dma_rmb(); 8913 8914 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt); 8915 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset; 8916 8917 /* pull rx packet timestamp if available and valid */ 8918 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 8919 int ts_hdr_len; 8920 8921 ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector, 8922 pktbuf, ×tamp); 8923 8924 pkt_offset += ts_hdr_len; 8925 size -= ts_hdr_len; 8926 } 8927 8928 /* retrieve a buffer from the ring */ 8929 if (!skb) { 8930 unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring); 8931 unsigned int offset = pkt_offset + igb_rx_offset(rx_ring); 8932 8933 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 8934 xdp_buff_clear_frags_flag(&xdp); 8935 #if (PAGE_SIZE > 4096) 8936 /* At larger PAGE_SIZE, frame_sz depend on len size */ 8937 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size); 8938 #endif 8939 skb = igb_run_xdp(adapter, rx_ring, &xdp); 8940 } 8941 8942 if (IS_ERR(skb)) { 8943 unsigned int xdp_res = -PTR_ERR(skb); 8944 8945 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) { 8946 xdp_xmit |= xdp_res; 8947 igb_rx_buffer_flip(rx_ring, rx_buffer, size); 8948 } else { 8949 rx_buffer->pagecnt_bias++; 8950 } 8951 total_packets++; 8952 total_bytes += size; 8953 } else if (skb) 8954 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 8955 else if (ring_uses_build_skb(rx_ring)) 8956 skb = igb_build_skb(rx_ring, rx_buffer, &xdp, 8957 timestamp); 8958 else 8959 skb = igb_construct_skb(rx_ring, rx_buffer, 8960 &xdp, timestamp); 8961 8962 /* exit if we failed to retrieve a buffer */ 8963 if (!skb) { 8964 rx_ring->rx_stats.alloc_failed++; 8965 rx_buffer->pagecnt_bias++; 8966 break; 8967 } 8968 8969 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt); 8970 cleaned_count++; 8971 8972 /* fetch next buffer in frame if non-eop */ 8973 if (igb_is_non_eop(rx_ring, rx_desc)) 8974 continue; 8975 8976 /* verify the packet layout is correct */ 8977 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 8978 skb = NULL; 8979 continue; 8980 } 8981 8982 /* probably a little skewed due to removing CRC */ 8983 total_bytes += skb->len; 8984 8985 /* populate checksum, timestamp, VLAN, and protocol */ 8986 igb_process_skb_fields(rx_ring, rx_desc, skb); 8987 8988 napi_gro_receive(&q_vector->napi, skb); 8989 8990 /* reset skb pointer */ 8991 skb = NULL; 8992 8993 /* update budget accounting */ 8994 total_packets++; 8995 } 8996 8997 /* place incomplete frames back on ring for completion */ 8998 rx_ring->skb = skb; 8999 9000 if (xdp_xmit & IGB_XDP_REDIR) 9001 xdp_do_flush(); 9002 9003 if (xdp_xmit & IGB_XDP_TX) { 9004 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter); 9005 9006 nq = txring_txq(tx_ring); 9007 __netif_tx_lock(nq, cpu); 9008 igb_xdp_ring_update_tail(tx_ring); 9009 __netif_tx_unlock(nq); 9010 } 9011 9012 u64_stats_update_begin(&rx_ring->rx_syncp); 9013 rx_ring->rx_stats.packets += total_packets; 9014 rx_ring->rx_stats.bytes += total_bytes; 9015 u64_stats_update_end(&rx_ring->rx_syncp); 9016 q_vector->rx.total_packets += total_packets; 9017 q_vector->rx.total_bytes += total_bytes; 9018 9019 if (cleaned_count) 9020 igb_alloc_rx_buffers(rx_ring, cleaned_count); 9021 9022 return total_packets; 9023 } 9024 9025 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 9026 struct igb_rx_buffer *bi) 9027 { 9028 struct page *page = bi->page; 9029 dma_addr_t dma; 9030 9031 /* since we are recycling buffers we should seldom need to alloc */ 9032 if (likely(page)) 9033 return true; 9034 9035 /* alloc new page for storage */ 9036 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 9037 if (unlikely(!page)) { 9038 rx_ring->rx_stats.alloc_failed++; 9039 return false; 9040 } 9041 9042 /* map page for use */ 9043 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 9044 igb_rx_pg_size(rx_ring), 9045 DMA_FROM_DEVICE, 9046 IGB_RX_DMA_ATTR); 9047 9048 /* if mapping failed free memory back to system since 9049 * there isn't much point in holding memory we can't use 9050 */ 9051 if (dma_mapping_error(rx_ring->dev, dma)) { 9052 __free_pages(page, igb_rx_pg_order(rx_ring)); 9053 9054 rx_ring->rx_stats.alloc_failed++; 9055 return false; 9056 } 9057 9058 bi->dma = dma; 9059 bi->page = page; 9060 bi->page_offset = igb_rx_offset(rx_ring); 9061 page_ref_add(page, USHRT_MAX - 1); 9062 bi->pagecnt_bias = USHRT_MAX; 9063 9064 return true; 9065 } 9066 9067 /** 9068 * igb_alloc_rx_buffers - Replace used receive buffers 9069 * @rx_ring: rx descriptor ring to allocate new receive buffers 9070 * @cleaned_count: count of buffers to allocate 9071 **/ 9072 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 9073 { 9074 union e1000_adv_rx_desc *rx_desc; 9075 struct igb_rx_buffer *bi; 9076 u16 i = rx_ring->next_to_use; 9077 u16 bufsz; 9078 9079 /* nothing to do */ 9080 if (!cleaned_count) 9081 return; 9082 9083 rx_desc = IGB_RX_DESC(rx_ring, i); 9084 bi = &rx_ring->rx_buffer_info[i]; 9085 i -= rx_ring->count; 9086 9087 bufsz = igb_rx_bufsz(rx_ring); 9088 9089 do { 9090 if (!igb_alloc_mapped_page(rx_ring, bi)) 9091 break; 9092 9093 /* sync the buffer for use by the device */ 9094 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 9095 bi->page_offset, bufsz, 9096 DMA_FROM_DEVICE); 9097 9098 /* Refresh the desc even if buffer_addrs didn't change 9099 * because each write-back erases this info. 9100 */ 9101 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 9102 9103 rx_desc++; 9104 bi++; 9105 i++; 9106 if (unlikely(!i)) { 9107 rx_desc = IGB_RX_DESC(rx_ring, 0); 9108 bi = rx_ring->rx_buffer_info; 9109 i -= rx_ring->count; 9110 } 9111 9112 /* clear the length for the next_to_use descriptor */ 9113 rx_desc->wb.upper.length = 0; 9114 9115 cleaned_count--; 9116 } while (cleaned_count); 9117 9118 i += rx_ring->count; 9119 9120 if (rx_ring->next_to_use != i) { 9121 /* record the next descriptor to use */ 9122 rx_ring->next_to_use = i; 9123 9124 /* update next to alloc since we have filled the ring */ 9125 rx_ring->next_to_alloc = i; 9126 9127 /* Force memory writes to complete before letting h/w 9128 * know there are new descriptors to fetch. (Only 9129 * applicable for weak-ordered memory model archs, 9130 * such as IA-64). 9131 */ 9132 dma_wmb(); 9133 writel(i, rx_ring->tail); 9134 } 9135 } 9136 9137 /** 9138 * igb_mii_ioctl - 9139 * @netdev: pointer to netdev struct 9140 * @ifr: interface structure 9141 * @cmd: ioctl command to execute 9142 **/ 9143 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9144 { 9145 struct igb_adapter *adapter = netdev_priv(netdev); 9146 struct mii_ioctl_data *data = if_mii(ifr); 9147 9148 if (adapter->hw.phy.media_type != e1000_media_type_copper) 9149 return -EOPNOTSUPP; 9150 9151 switch (cmd) { 9152 case SIOCGMIIPHY: 9153 data->phy_id = adapter->hw.phy.addr; 9154 break; 9155 case SIOCGMIIREG: 9156 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9157 &data->val_out)) 9158 return -EIO; 9159 break; 9160 case SIOCSMIIREG: 9161 if (igb_write_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9162 data->val_in)) 9163 return -EIO; 9164 break; 9165 default: 9166 return -EOPNOTSUPP; 9167 } 9168 return 0; 9169 } 9170 9171 /** 9172 * igb_ioctl - 9173 * @netdev: pointer to netdev struct 9174 * @ifr: interface structure 9175 * @cmd: ioctl command to execute 9176 **/ 9177 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9178 { 9179 switch (cmd) { 9180 case SIOCGMIIPHY: 9181 case SIOCGMIIREG: 9182 case SIOCSMIIREG: 9183 return igb_mii_ioctl(netdev, ifr, cmd); 9184 case SIOCGHWTSTAMP: 9185 return igb_ptp_get_ts_config(netdev, ifr); 9186 case SIOCSHWTSTAMP: 9187 return igb_ptp_set_ts_config(netdev, ifr); 9188 default: 9189 return -EOPNOTSUPP; 9190 } 9191 } 9192 9193 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9194 { 9195 struct igb_adapter *adapter = hw->back; 9196 9197 pci_read_config_word(adapter->pdev, reg, value); 9198 } 9199 9200 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9201 { 9202 struct igb_adapter *adapter = hw->back; 9203 9204 pci_write_config_word(adapter->pdev, reg, *value); 9205 } 9206 9207 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9208 { 9209 struct igb_adapter *adapter = hw->back; 9210 9211 if (pcie_capability_read_word(adapter->pdev, reg, value)) 9212 return -E1000_ERR_CONFIG; 9213 9214 return 0; 9215 } 9216 9217 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9218 { 9219 struct igb_adapter *adapter = hw->back; 9220 9221 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 9222 return -E1000_ERR_CONFIG; 9223 9224 return 0; 9225 } 9226 9227 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 9228 { 9229 struct igb_adapter *adapter = netdev_priv(netdev); 9230 struct e1000_hw *hw = &adapter->hw; 9231 u32 ctrl, rctl; 9232 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 9233 9234 if (enable) { 9235 /* enable VLAN tag insert/strip */ 9236 ctrl = rd32(E1000_CTRL); 9237 ctrl |= E1000_CTRL_VME; 9238 wr32(E1000_CTRL, ctrl); 9239 9240 /* Disable CFI check */ 9241 rctl = rd32(E1000_RCTL); 9242 rctl &= ~E1000_RCTL_CFIEN; 9243 wr32(E1000_RCTL, rctl); 9244 } else { 9245 /* disable VLAN tag insert/strip */ 9246 ctrl = rd32(E1000_CTRL); 9247 ctrl &= ~E1000_CTRL_VME; 9248 wr32(E1000_CTRL, ctrl); 9249 } 9250 9251 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 9252 } 9253 9254 static int igb_vlan_rx_add_vid(struct net_device *netdev, 9255 __be16 proto, u16 vid) 9256 { 9257 struct igb_adapter *adapter = netdev_priv(netdev); 9258 struct e1000_hw *hw = &adapter->hw; 9259 int pf_id = adapter->vfs_allocated_count; 9260 9261 /* add the filter since PF can receive vlans w/o entry in vlvf */ 9262 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9263 igb_vfta_set(hw, vid, pf_id, true, !!vid); 9264 9265 set_bit(vid, adapter->active_vlans); 9266 9267 return 0; 9268 } 9269 9270 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 9271 __be16 proto, u16 vid) 9272 { 9273 struct igb_adapter *adapter = netdev_priv(netdev); 9274 int pf_id = adapter->vfs_allocated_count; 9275 struct e1000_hw *hw = &adapter->hw; 9276 9277 /* remove VID from filter table */ 9278 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9279 igb_vfta_set(hw, vid, pf_id, false, true); 9280 9281 clear_bit(vid, adapter->active_vlans); 9282 9283 return 0; 9284 } 9285 9286 static void igb_restore_vlan(struct igb_adapter *adapter) 9287 { 9288 u16 vid = 1; 9289 9290 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 9291 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 9292 9293 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 9294 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 9295 } 9296 9297 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 9298 { 9299 struct pci_dev *pdev = adapter->pdev; 9300 struct e1000_mac_info *mac = &adapter->hw.mac; 9301 9302 mac->autoneg = 0; 9303 9304 /* Make sure dplx is at most 1 bit and lsb of speed is not set 9305 * for the switch() below to work 9306 */ 9307 if ((spd & 1) || (dplx & ~1)) 9308 goto err_inval; 9309 9310 /* Fiber NIC's only allow 1000 gbps Full duplex 9311 * and 100Mbps Full duplex for 100baseFx sfp 9312 */ 9313 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 9314 switch (spd + dplx) { 9315 case SPEED_10 + DUPLEX_HALF: 9316 case SPEED_10 + DUPLEX_FULL: 9317 case SPEED_100 + DUPLEX_HALF: 9318 goto err_inval; 9319 default: 9320 break; 9321 } 9322 } 9323 9324 switch (spd + dplx) { 9325 case SPEED_10 + DUPLEX_HALF: 9326 mac->forced_speed_duplex = ADVERTISE_10_HALF; 9327 break; 9328 case SPEED_10 + DUPLEX_FULL: 9329 mac->forced_speed_duplex = ADVERTISE_10_FULL; 9330 break; 9331 case SPEED_100 + DUPLEX_HALF: 9332 mac->forced_speed_duplex = ADVERTISE_100_HALF; 9333 break; 9334 case SPEED_100 + DUPLEX_FULL: 9335 mac->forced_speed_duplex = ADVERTISE_100_FULL; 9336 break; 9337 case SPEED_1000 + DUPLEX_FULL: 9338 mac->autoneg = 1; 9339 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 9340 break; 9341 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 9342 default: 9343 goto err_inval; 9344 } 9345 9346 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 9347 adapter->hw.phy.mdix = AUTO_ALL_MODES; 9348 9349 return 0; 9350 9351 err_inval: 9352 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 9353 return -EINVAL; 9354 } 9355 9356 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 9357 bool runtime) 9358 { 9359 struct net_device *netdev = pci_get_drvdata(pdev); 9360 struct igb_adapter *adapter = netdev_priv(netdev); 9361 struct e1000_hw *hw = &adapter->hw; 9362 u32 ctrl, rctl, status; 9363 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 9364 bool wake; 9365 9366 rtnl_lock(); 9367 netif_device_detach(netdev); 9368 9369 if (netif_running(netdev)) 9370 __igb_close(netdev, true); 9371 9372 igb_ptp_suspend(adapter); 9373 9374 igb_clear_interrupt_scheme(adapter); 9375 rtnl_unlock(); 9376 9377 status = rd32(E1000_STATUS); 9378 if (status & E1000_STATUS_LU) 9379 wufc &= ~E1000_WUFC_LNKC; 9380 9381 if (wufc) { 9382 igb_setup_rctl(adapter); 9383 igb_set_rx_mode(netdev); 9384 9385 /* turn on all-multi mode if wake on multicast is enabled */ 9386 if (wufc & E1000_WUFC_MC) { 9387 rctl = rd32(E1000_RCTL); 9388 rctl |= E1000_RCTL_MPE; 9389 wr32(E1000_RCTL, rctl); 9390 } 9391 9392 ctrl = rd32(E1000_CTRL); 9393 ctrl |= E1000_CTRL_ADVD3WUC; 9394 wr32(E1000_CTRL, ctrl); 9395 9396 /* Allow time for pending master requests to run */ 9397 igb_disable_pcie_master(hw); 9398 9399 wr32(E1000_WUC, E1000_WUC_PME_EN); 9400 wr32(E1000_WUFC, wufc); 9401 } else { 9402 wr32(E1000_WUC, 0); 9403 wr32(E1000_WUFC, 0); 9404 } 9405 9406 wake = wufc || adapter->en_mng_pt; 9407 if (!wake) 9408 igb_power_down_link(adapter); 9409 else 9410 igb_power_up_link(adapter); 9411 9412 if (enable_wake) 9413 *enable_wake = wake; 9414 9415 /* Release control of h/w to f/w. If f/w is AMT enabled, this 9416 * would have already happened in close and is redundant. 9417 */ 9418 igb_release_hw_control(adapter); 9419 9420 pci_disable_device(pdev); 9421 9422 return 0; 9423 } 9424 9425 static void igb_deliver_wake_packet(struct net_device *netdev) 9426 { 9427 struct igb_adapter *adapter = netdev_priv(netdev); 9428 struct e1000_hw *hw = &adapter->hw; 9429 struct sk_buff *skb; 9430 u32 wupl; 9431 9432 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 9433 9434 /* WUPM stores only the first 128 bytes of the wake packet. 9435 * Read the packet only if we have the whole thing. 9436 */ 9437 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 9438 return; 9439 9440 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 9441 if (!skb) 9442 return; 9443 9444 skb_put(skb, wupl); 9445 9446 /* Ensure reads are 32-bit aligned */ 9447 wupl = roundup(wupl, 4); 9448 9449 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 9450 9451 skb->protocol = eth_type_trans(skb, netdev); 9452 netif_rx(skb); 9453 } 9454 9455 static int igb_suspend(struct device *dev) 9456 { 9457 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 9458 } 9459 9460 static int __igb_resume(struct device *dev, bool rpm) 9461 { 9462 struct pci_dev *pdev = to_pci_dev(dev); 9463 struct net_device *netdev = pci_get_drvdata(pdev); 9464 struct igb_adapter *adapter = netdev_priv(netdev); 9465 struct e1000_hw *hw = &adapter->hw; 9466 u32 err, val; 9467 9468 pci_set_power_state(pdev, PCI_D0); 9469 pci_restore_state(pdev); 9470 pci_save_state(pdev); 9471 9472 if (!pci_device_is_present(pdev)) 9473 return -ENODEV; 9474 err = pci_enable_device_mem(pdev); 9475 if (err) { 9476 dev_err(&pdev->dev, 9477 "igb: Cannot enable PCI device from suspend\n"); 9478 return err; 9479 } 9480 pci_set_master(pdev); 9481 9482 pci_enable_wake(pdev, PCI_D3hot, 0); 9483 pci_enable_wake(pdev, PCI_D3cold, 0); 9484 9485 if (igb_init_interrupt_scheme(adapter, true)) { 9486 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9487 return -ENOMEM; 9488 } 9489 9490 igb_reset(adapter); 9491 9492 /* let the f/w know that the h/w is now under the control of the 9493 * driver. 9494 */ 9495 igb_get_hw_control(adapter); 9496 9497 val = rd32(E1000_WUS); 9498 if (val & WAKE_PKT_WUS) 9499 igb_deliver_wake_packet(netdev); 9500 9501 wr32(E1000_WUS, ~0); 9502 9503 if (!rpm) 9504 rtnl_lock(); 9505 if (!err && netif_running(netdev)) 9506 err = __igb_open(netdev, true); 9507 9508 if (!err) 9509 netif_device_attach(netdev); 9510 if (!rpm) 9511 rtnl_unlock(); 9512 9513 return err; 9514 } 9515 9516 static int igb_resume(struct device *dev) 9517 { 9518 return __igb_resume(dev, false); 9519 } 9520 9521 static int igb_runtime_idle(struct device *dev) 9522 { 9523 struct net_device *netdev = dev_get_drvdata(dev); 9524 struct igb_adapter *adapter = netdev_priv(netdev); 9525 9526 if (!igb_has_link(adapter)) 9527 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 9528 9529 return -EBUSY; 9530 } 9531 9532 static int igb_runtime_suspend(struct device *dev) 9533 { 9534 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 9535 } 9536 9537 static int igb_runtime_resume(struct device *dev) 9538 { 9539 return __igb_resume(dev, true); 9540 } 9541 9542 static void igb_shutdown(struct pci_dev *pdev) 9543 { 9544 bool wake; 9545 9546 __igb_shutdown(pdev, &wake, 0); 9547 9548 if (system_state == SYSTEM_POWER_OFF) { 9549 pci_wake_from_d3(pdev, wake); 9550 pci_set_power_state(pdev, PCI_D3hot); 9551 } 9552 } 9553 9554 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 9555 { 9556 #ifdef CONFIG_PCI_IOV 9557 int err; 9558 9559 if (num_vfs == 0) { 9560 return igb_disable_sriov(dev, true); 9561 } else { 9562 err = igb_enable_sriov(dev, num_vfs, true); 9563 return err ? err : num_vfs; 9564 } 9565 #endif 9566 return 0; 9567 } 9568 9569 /** 9570 * igb_io_error_detected - called when PCI error is detected 9571 * @pdev: Pointer to PCI device 9572 * @state: The current pci connection state 9573 * 9574 * This function is called after a PCI bus error affecting 9575 * this device has been detected. 9576 **/ 9577 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9578 pci_channel_state_t state) 9579 { 9580 struct net_device *netdev = pci_get_drvdata(pdev); 9581 struct igb_adapter *adapter = netdev_priv(netdev); 9582 9583 if (state == pci_channel_io_normal) { 9584 dev_warn(&pdev->dev, "Non-correctable non-fatal error reported.\n"); 9585 return PCI_ERS_RESULT_CAN_RECOVER; 9586 } 9587 9588 netif_device_detach(netdev); 9589 9590 if (state == pci_channel_io_perm_failure) 9591 return PCI_ERS_RESULT_DISCONNECT; 9592 9593 if (netif_running(netdev)) 9594 igb_down(adapter); 9595 pci_disable_device(pdev); 9596 9597 /* Request a slot reset. */ 9598 return PCI_ERS_RESULT_NEED_RESET; 9599 } 9600 9601 /** 9602 * igb_io_slot_reset - called after the pci bus has been reset. 9603 * @pdev: Pointer to PCI device 9604 * 9605 * Restart the card from scratch, as if from a cold-boot. Implementation 9606 * resembles the first-half of the __igb_resume routine. 9607 **/ 9608 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9609 { 9610 struct net_device *netdev = pci_get_drvdata(pdev); 9611 struct igb_adapter *adapter = netdev_priv(netdev); 9612 struct e1000_hw *hw = &adapter->hw; 9613 pci_ers_result_t result; 9614 9615 if (pci_enable_device_mem(pdev)) { 9616 dev_err(&pdev->dev, 9617 "Cannot re-enable PCI device after reset.\n"); 9618 result = PCI_ERS_RESULT_DISCONNECT; 9619 } else { 9620 pci_set_master(pdev); 9621 pci_restore_state(pdev); 9622 pci_save_state(pdev); 9623 9624 pci_enable_wake(pdev, PCI_D3hot, 0); 9625 pci_enable_wake(pdev, PCI_D3cold, 0); 9626 9627 /* In case of PCI error, adapter lose its HW address 9628 * so we should re-assign it here. 9629 */ 9630 hw->hw_addr = adapter->io_addr; 9631 9632 igb_reset(adapter); 9633 wr32(E1000_WUS, ~0); 9634 result = PCI_ERS_RESULT_RECOVERED; 9635 } 9636 9637 return result; 9638 } 9639 9640 /** 9641 * igb_io_resume - called when traffic can start flowing again. 9642 * @pdev: Pointer to PCI device 9643 * 9644 * This callback is called when the error recovery driver tells us that 9645 * its OK to resume normal operation. Implementation resembles the 9646 * second-half of the __igb_resume routine. 9647 */ 9648 static void igb_io_resume(struct pci_dev *pdev) 9649 { 9650 struct net_device *netdev = pci_get_drvdata(pdev); 9651 struct igb_adapter *adapter = netdev_priv(netdev); 9652 9653 if (netif_running(netdev)) { 9654 if (!test_bit(__IGB_DOWN, &adapter->state)) { 9655 dev_dbg(&pdev->dev, "Resuming from non-fatal error, do nothing.\n"); 9656 return; 9657 } 9658 if (igb_up(adapter)) { 9659 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9660 return; 9661 } 9662 } 9663 9664 netif_device_attach(netdev); 9665 9666 /* let the f/w know that the h/w is now under the control of the 9667 * driver. 9668 */ 9669 igb_get_hw_control(adapter); 9670 } 9671 9672 /** 9673 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9674 * @adapter: Pointer to adapter structure 9675 * @index: Index of the RAR entry which need to be synced with MAC table 9676 **/ 9677 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9678 { 9679 struct e1000_hw *hw = &adapter->hw; 9680 u32 rar_low, rar_high; 9681 u8 *addr = adapter->mac_table[index].addr; 9682 9683 /* HW expects these to be in network order when they are plugged 9684 * into the registers which are little endian. In order to guarantee 9685 * that ordering we need to do an leXX_to_cpup here in order to be 9686 * ready for the byteswap that occurs with writel 9687 */ 9688 rar_low = le32_to_cpup((__le32 *)(addr)); 9689 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9690 9691 /* Indicate to hardware the Address is Valid. */ 9692 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9693 if (is_valid_ether_addr(addr)) 9694 rar_high |= E1000_RAH_AV; 9695 9696 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9697 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9698 9699 switch (hw->mac.type) { 9700 case e1000_82575: 9701 case e1000_i210: 9702 if (adapter->mac_table[index].state & 9703 IGB_MAC_STATE_QUEUE_STEERING) 9704 rar_high |= E1000_RAH_QSEL_ENABLE; 9705 9706 rar_high |= E1000_RAH_POOL_1 * 9707 adapter->mac_table[index].queue; 9708 break; 9709 default: 9710 rar_high |= E1000_RAH_POOL_1 << 9711 adapter->mac_table[index].queue; 9712 break; 9713 } 9714 } 9715 9716 wr32(E1000_RAL(index), rar_low); 9717 wrfl(); 9718 wr32(E1000_RAH(index), rar_high); 9719 wrfl(); 9720 } 9721 9722 static int igb_set_vf_mac(struct igb_adapter *adapter, 9723 int vf, unsigned char *mac_addr) 9724 { 9725 struct e1000_hw *hw = &adapter->hw; 9726 /* VF MAC addresses start at end of receive addresses and moves 9727 * towards the first, as a result a collision should not be possible 9728 */ 9729 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9730 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9731 9732 ether_addr_copy(vf_mac_addr, mac_addr); 9733 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9734 adapter->mac_table[rar_entry].queue = vf; 9735 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9736 igb_rar_set_index(adapter, rar_entry); 9737 9738 return 0; 9739 } 9740 9741 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9742 { 9743 struct igb_adapter *adapter = netdev_priv(netdev); 9744 9745 if (vf >= adapter->vfs_allocated_count) 9746 return -EINVAL; 9747 9748 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9749 * flag and allows to overwrite the MAC via VF netdev. This 9750 * is necessary to allow libvirt a way to restore the original 9751 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9752 * down a VM. 9753 */ 9754 if (is_zero_ether_addr(mac)) { 9755 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9756 dev_info(&adapter->pdev->dev, 9757 "remove administratively set MAC on VF %d\n", 9758 vf); 9759 } else if (is_valid_ether_addr(mac)) { 9760 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9761 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9762 mac, vf); 9763 dev_info(&adapter->pdev->dev, 9764 "Reload the VF driver to make this change effective."); 9765 /* Generate additional warning if PF is down */ 9766 if (test_bit(__IGB_DOWN, &adapter->state)) { 9767 dev_warn(&adapter->pdev->dev, 9768 "The VF MAC address has been set, but the PF device is not up.\n"); 9769 dev_warn(&adapter->pdev->dev, 9770 "Bring the PF device up before attempting to use the VF device.\n"); 9771 } 9772 } else { 9773 return -EINVAL; 9774 } 9775 return igb_set_vf_mac(adapter, vf, mac); 9776 } 9777 9778 static int igb_link_mbps(int internal_link_speed) 9779 { 9780 switch (internal_link_speed) { 9781 case SPEED_100: 9782 return 100; 9783 case SPEED_1000: 9784 return 1000; 9785 default: 9786 return 0; 9787 } 9788 } 9789 9790 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9791 int link_speed) 9792 { 9793 int rf_dec, rf_int; 9794 u32 bcnrc_val; 9795 9796 if (tx_rate != 0) { 9797 /* Calculate the rate factor values to set */ 9798 rf_int = link_speed / tx_rate; 9799 rf_dec = (link_speed - (rf_int * tx_rate)); 9800 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9801 tx_rate; 9802 9803 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9804 bcnrc_val |= FIELD_PREP(E1000_RTTBCNRC_RF_INT_MASK, rf_int); 9805 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9806 } else { 9807 bcnrc_val = 0; 9808 } 9809 9810 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9811 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9812 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9813 */ 9814 wr32(E1000_RTTBCNRM, 0x14); 9815 wr32(E1000_RTTBCNRC, bcnrc_val); 9816 } 9817 9818 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9819 { 9820 int actual_link_speed, i; 9821 bool reset_rate = false; 9822 9823 /* VF TX rate limit was not set or not supported */ 9824 if ((adapter->vf_rate_link_speed == 0) || 9825 (adapter->hw.mac.type != e1000_82576)) 9826 return; 9827 9828 actual_link_speed = igb_link_mbps(adapter->link_speed); 9829 if (actual_link_speed != adapter->vf_rate_link_speed) { 9830 reset_rate = true; 9831 adapter->vf_rate_link_speed = 0; 9832 dev_info(&adapter->pdev->dev, 9833 "Link speed has been changed. VF Transmit rate is disabled\n"); 9834 } 9835 9836 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9837 if (reset_rate) 9838 adapter->vf_data[i].tx_rate = 0; 9839 9840 igb_set_vf_rate_limit(&adapter->hw, i, 9841 adapter->vf_data[i].tx_rate, 9842 actual_link_speed); 9843 } 9844 } 9845 9846 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9847 int min_tx_rate, int max_tx_rate) 9848 { 9849 struct igb_adapter *adapter = netdev_priv(netdev); 9850 struct e1000_hw *hw = &adapter->hw; 9851 int actual_link_speed; 9852 9853 if (hw->mac.type != e1000_82576) 9854 return -EOPNOTSUPP; 9855 9856 if (min_tx_rate) 9857 return -EINVAL; 9858 9859 actual_link_speed = igb_link_mbps(adapter->link_speed); 9860 if ((vf >= adapter->vfs_allocated_count) || 9861 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9862 (max_tx_rate < 0) || 9863 (max_tx_rate > actual_link_speed)) 9864 return -EINVAL; 9865 9866 adapter->vf_rate_link_speed = actual_link_speed; 9867 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 9868 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 9869 9870 return 0; 9871 } 9872 9873 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 9874 bool setting) 9875 { 9876 struct igb_adapter *adapter = netdev_priv(netdev); 9877 struct e1000_hw *hw = &adapter->hw; 9878 u32 reg_val, reg_offset; 9879 9880 if (!adapter->vfs_allocated_count) 9881 return -EOPNOTSUPP; 9882 9883 if (vf >= adapter->vfs_allocated_count) 9884 return -EINVAL; 9885 9886 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 9887 reg_val = rd32(reg_offset); 9888 if (setting) 9889 reg_val |= (BIT(vf) | 9890 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9891 else 9892 reg_val &= ~(BIT(vf) | 9893 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9894 wr32(reg_offset, reg_val); 9895 9896 adapter->vf_data[vf].spoofchk_enabled = setting; 9897 return 0; 9898 } 9899 9900 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 9901 { 9902 struct igb_adapter *adapter = netdev_priv(netdev); 9903 9904 if (vf >= adapter->vfs_allocated_count) 9905 return -EINVAL; 9906 if (adapter->vf_data[vf].trusted == setting) 9907 return 0; 9908 9909 adapter->vf_data[vf].trusted = setting; 9910 9911 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 9912 vf, setting ? "" : "not "); 9913 return 0; 9914 } 9915 9916 static int igb_ndo_get_vf_config(struct net_device *netdev, 9917 int vf, struct ifla_vf_info *ivi) 9918 { 9919 struct igb_adapter *adapter = netdev_priv(netdev); 9920 if (vf >= adapter->vfs_allocated_count) 9921 return -EINVAL; 9922 ivi->vf = vf; 9923 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 9924 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 9925 ivi->min_tx_rate = 0; 9926 ivi->vlan = adapter->vf_data[vf].pf_vlan; 9927 ivi->qos = adapter->vf_data[vf].pf_qos; 9928 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 9929 ivi->trusted = adapter->vf_data[vf].trusted; 9930 return 0; 9931 } 9932 9933 static void igb_vmm_control(struct igb_adapter *adapter) 9934 { 9935 struct e1000_hw *hw = &adapter->hw; 9936 u32 reg; 9937 9938 switch (hw->mac.type) { 9939 case e1000_82575: 9940 case e1000_i210: 9941 case e1000_i211: 9942 case e1000_i354: 9943 default: 9944 /* replication is not supported for 82575 */ 9945 return; 9946 case e1000_82576: 9947 /* notify HW that the MAC is adding vlan tags */ 9948 reg = rd32(E1000_DTXCTL); 9949 reg |= E1000_DTXCTL_VLAN_ADDED; 9950 wr32(E1000_DTXCTL, reg); 9951 fallthrough; 9952 case e1000_82580: 9953 /* enable replication vlan tag stripping */ 9954 reg = rd32(E1000_RPLOLR); 9955 reg |= E1000_RPLOLR_STRVLAN; 9956 wr32(E1000_RPLOLR, reg); 9957 fallthrough; 9958 case e1000_i350: 9959 /* none of the above registers are supported by i350 */ 9960 break; 9961 } 9962 9963 if (adapter->vfs_allocated_count) { 9964 igb_vmdq_set_loopback_pf(hw, true); 9965 igb_vmdq_set_replication_pf(hw, true); 9966 igb_vmdq_set_anti_spoofing_pf(hw, true, 9967 adapter->vfs_allocated_count); 9968 } else { 9969 igb_vmdq_set_loopback_pf(hw, false); 9970 igb_vmdq_set_replication_pf(hw, false); 9971 } 9972 } 9973 9974 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 9975 { 9976 struct e1000_hw *hw = &adapter->hw; 9977 u32 dmac_thr; 9978 u16 hwm; 9979 u32 reg; 9980 9981 if (hw->mac.type > e1000_82580) { 9982 if (adapter->flags & IGB_FLAG_DMAC) { 9983 /* force threshold to 0. */ 9984 wr32(E1000_DMCTXTH, 0); 9985 9986 /* DMA Coalescing high water mark needs to be greater 9987 * than the Rx threshold. Set hwm to PBA - max frame 9988 * size in 16B units, capping it at PBA - 6KB. 9989 */ 9990 hwm = 64 * (pba - 6); 9991 reg = rd32(E1000_FCRTC); 9992 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 9993 reg |= FIELD_PREP(E1000_FCRTC_RTH_COAL_MASK, hwm); 9994 wr32(E1000_FCRTC, reg); 9995 9996 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 9997 * frame size, capping it at PBA - 10KB. 9998 */ 9999 dmac_thr = pba - 10; 10000 reg = rd32(E1000_DMACR); 10001 reg &= ~E1000_DMACR_DMACTHR_MASK; 10002 reg |= FIELD_PREP(E1000_DMACR_DMACTHR_MASK, dmac_thr); 10003 10004 /* transition to L0x or L1 if available..*/ 10005 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 10006 10007 /* watchdog timer= +-1000 usec in 32usec intervals */ 10008 reg |= (1000 >> 5); 10009 10010 /* Disable BMC-to-OS Watchdog Enable */ 10011 if (hw->mac.type != e1000_i354) 10012 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 10013 wr32(E1000_DMACR, reg); 10014 10015 /* no lower threshold to disable 10016 * coalescing(smart fifb)-UTRESH=0 10017 */ 10018 wr32(E1000_DMCRTRH, 0); 10019 10020 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 10021 10022 wr32(E1000_DMCTLX, reg); 10023 10024 /* free space in tx packet buffer to wake from 10025 * DMA coal 10026 */ 10027 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 10028 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 10029 } 10030 10031 if (hw->mac.type >= e1000_i210 || 10032 (adapter->flags & IGB_FLAG_DMAC)) { 10033 reg = rd32(E1000_PCIEMISC); 10034 reg |= E1000_PCIEMISC_LX_DECISION; 10035 wr32(E1000_PCIEMISC, reg); 10036 } /* endif adapter->dmac is not disabled */ 10037 } else if (hw->mac.type == e1000_82580) { 10038 u32 reg = rd32(E1000_PCIEMISC); 10039 10040 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 10041 wr32(E1000_DMACR, 0); 10042 } 10043 } 10044 10045 /** 10046 * igb_read_i2c_byte - Reads 8 bit word over I2C 10047 * @hw: pointer to hardware structure 10048 * @byte_offset: byte offset to read 10049 * @dev_addr: device address 10050 * @data: value read 10051 * 10052 * Performs byte read operation over I2C interface at 10053 * a specified device address. 10054 **/ 10055 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10056 u8 dev_addr, u8 *data) 10057 { 10058 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10059 struct i2c_client *this_client = adapter->i2c_client; 10060 s32 status; 10061 u16 swfw_mask = 0; 10062 10063 if (!this_client) 10064 return E1000_ERR_I2C; 10065 10066 swfw_mask = E1000_SWFW_PHY0_SM; 10067 10068 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10069 return E1000_ERR_SWFW_SYNC; 10070 10071 status = i2c_smbus_read_byte_data(this_client, byte_offset); 10072 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10073 10074 if (status < 0) 10075 return E1000_ERR_I2C; 10076 else { 10077 *data = status; 10078 return 0; 10079 } 10080 } 10081 10082 /** 10083 * igb_write_i2c_byte - Writes 8 bit word over I2C 10084 * @hw: pointer to hardware structure 10085 * @byte_offset: byte offset to write 10086 * @dev_addr: device address 10087 * @data: value to write 10088 * 10089 * Performs byte write operation over I2C interface at 10090 * a specified device address. 10091 **/ 10092 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10093 u8 dev_addr, u8 data) 10094 { 10095 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10096 struct i2c_client *this_client = adapter->i2c_client; 10097 s32 status; 10098 u16 swfw_mask = E1000_SWFW_PHY0_SM; 10099 10100 if (!this_client) 10101 return E1000_ERR_I2C; 10102 10103 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10104 return E1000_ERR_SWFW_SYNC; 10105 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 10106 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10107 10108 if (status) 10109 return E1000_ERR_I2C; 10110 else 10111 return 0; 10112 10113 } 10114 10115 int igb_reinit_queues(struct igb_adapter *adapter) 10116 { 10117 struct net_device *netdev = adapter->netdev; 10118 struct pci_dev *pdev = adapter->pdev; 10119 int err = 0; 10120 10121 if (netif_running(netdev)) 10122 igb_close(netdev); 10123 10124 igb_reset_interrupt_capability(adapter); 10125 10126 if (igb_init_interrupt_scheme(adapter, true)) { 10127 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 10128 return -ENOMEM; 10129 } 10130 10131 if (netif_running(netdev)) 10132 err = igb_open(netdev); 10133 10134 return err; 10135 } 10136 10137 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 10138 { 10139 struct igb_nfc_filter *rule; 10140 10141 spin_lock(&adapter->nfc_lock); 10142 10143 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10144 igb_erase_filter(adapter, rule); 10145 10146 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 10147 igb_erase_filter(adapter, rule); 10148 10149 spin_unlock(&adapter->nfc_lock); 10150 } 10151 10152 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 10153 { 10154 struct igb_nfc_filter *rule; 10155 10156 spin_lock(&adapter->nfc_lock); 10157 10158 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10159 igb_add_filter(adapter, rule); 10160 10161 spin_unlock(&adapter->nfc_lock); 10162 } 10163 10164 static _DEFINE_DEV_PM_OPS(igb_pm_ops, igb_suspend, igb_resume, 10165 igb_runtime_suspend, igb_runtime_resume, 10166 igb_runtime_idle); 10167 10168 static struct pci_driver igb_driver = { 10169 .name = igb_driver_name, 10170 .id_table = igb_pci_tbl, 10171 .probe = igb_probe, 10172 .remove = igb_remove, 10173 .driver.pm = pm_ptr(&igb_pm_ops), 10174 .shutdown = igb_shutdown, 10175 .sriov_configure = igb_pci_sriov_configure, 10176 .err_handler = &igb_err_handler 10177 }; 10178 10179 /* igb_main.c */ 10180