1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/sctp.h> 30 #include <linux/if_ether.h> 31 #include <linux/aer.h> 32 #include <linux/prefetch.h> 33 #include <linux/bpf.h> 34 #include <linux/bpf_trace.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/etherdevice.h> 37 #ifdef CONFIG_IGB_DCA 38 #include <linux/dca.h> 39 #endif 40 #include <linux/i2c.h> 41 #include "igb.h" 42 43 enum queue_mode { 44 QUEUE_MODE_STRICT_PRIORITY, 45 QUEUE_MODE_STREAM_RESERVATION, 46 }; 47 48 enum tx_queue_prio { 49 TX_QUEUE_PRIO_HIGH, 50 TX_QUEUE_PRIO_LOW, 51 }; 52 53 char igb_driver_name[] = "igb"; 54 static const char igb_driver_string[] = 55 "Intel(R) Gigabit Ethernet Network Driver"; 56 static const char igb_copyright[] = 57 "Copyright (c) 2007-2014 Intel Corporation."; 58 59 static const struct e1000_info *igb_info_tbl[] = { 60 [board_82575] = &e1000_82575_info, 61 }; 62 63 static const struct pci_device_id igb_pci_tbl[] = { 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 99 /* required last entry */ 100 {0, } 101 }; 102 103 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 104 105 static int igb_setup_all_tx_resources(struct igb_adapter *); 106 static int igb_setup_all_rx_resources(struct igb_adapter *); 107 static void igb_free_all_tx_resources(struct igb_adapter *); 108 static void igb_free_all_rx_resources(struct igb_adapter *); 109 static void igb_setup_mrqc(struct igb_adapter *); 110 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 111 static void igb_remove(struct pci_dev *pdev); 112 static int igb_sw_init(struct igb_adapter *); 113 int igb_open(struct net_device *); 114 int igb_close(struct net_device *); 115 static void igb_configure(struct igb_adapter *); 116 static void igb_configure_tx(struct igb_adapter *); 117 static void igb_configure_rx(struct igb_adapter *); 118 static void igb_clean_all_tx_rings(struct igb_adapter *); 119 static void igb_clean_all_rx_rings(struct igb_adapter *); 120 static void igb_clean_tx_ring(struct igb_ring *); 121 static void igb_clean_rx_ring(struct igb_ring *); 122 static void igb_set_rx_mode(struct net_device *); 123 static void igb_update_phy_info(struct timer_list *); 124 static void igb_watchdog(struct timer_list *); 125 static void igb_watchdog_task(struct work_struct *); 126 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 127 static void igb_get_stats64(struct net_device *dev, 128 struct rtnl_link_stats64 *stats); 129 static int igb_change_mtu(struct net_device *, int); 130 static int igb_set_mac(struct net_device *, void *); 131 static void igb_set_uta(struct igb_adapter *adapter, bool set); 132 static irqreturn_t igb_intr(int irq, void *); 133 static irqreturn_t igb_intr_msi(int irq, void *); 134 static irqreturn_t igb_msix_other(int irq, void *); 135 static irqreturn_t igb_msix_ring(int irq, void *); 136 #ifdef CONFIG_IGB_DCA 137 static void igb_update_dca(struct igb_q_vector *); 138 static void igb_setup_dca(struct igb_adapter *); 139 #endif /* CONFIG_IGB_DCA */ 140 static int igb_poll(struct napi_struct *, int); 141 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 142 static int igb_clean_rx_irq(struct igb_q_vector *, int); 143 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 144 static void igb_tx_timeout(struct net_device *, unsigned int txqueue); 145 static void igb_reset_task(struct work_struct *); 146 static void igb_vlan_mode(struct net_device *netdev, 147 netdev_features_t features); 148 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 149 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 150 static void igb_restore_vlan(struct igb_adapter *); 151 static void igb_rar_set_index(struct igb_adapter *, u32); 152 static void igb_ping_all_vfs(struct igb_adapter *); 153 static void igb_msg_task(struct igb_adapter *); 154 static void igb_vmm_control(struct igb_adapter *); 155 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 156 static void igb_flush_mac_table(struct igb_adapter *); 157 static int igb_available_rars(struct igb_adapter *, u8); 158 static void igb_set_default_mac_filter(struct igb_adapter *); 159 static int igb_uc_sync(struct net_device *, const unsigned char *); 160 static int igb_uc_unsync(struct net_device *, const unsigned char *); 161 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 162 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 163 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 164 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 165 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 166 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 167 bool setting); 168 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 169 bool setting); 170 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 171 struct ifla_vf_info *ivi); 172 static void igb_check_vf_rate_limit(struct igb_adapter *); 173 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 174 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 175 176 #ifdef CONFIG_PCI_IOV 177 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 178 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 179 static int igb_disable_sriov(struct pci_dev *dev); 180 static int igb_pci_disable_sriov(struct pci_dev *dev); 181 #endif 182 183 static int igb_suspend(struct device *); 184 static int igb_resume(struct device *); 185 static int igb_runtime_suspend(struct device *dev); 186 static int igb_runtime_resume(struct device *dev); 187 static int igb_runtime_idle(struct device *dev); 188 static const struct dev_pm_ops igb_pm_ops = { 189 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 190 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 191 igb_runtime_idle) 192 }; 193 static void igb_shutdown(struct pci_dev *); 194 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 195 #ifdef CONFIG_IGB_DCA 196 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 197 static struct notifier_block dca_notifier = { 198 .notifier_call = igb_notify_dca, 199 .next = NULL, 200 .priority = 0 201 }; 202 #endif 203 #ifdef CONFIG_PCI_IOV 204 static unsigned int max_vfs; 205 module_param(max_vfs, uint, 0); 206 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 207 #endif /* CONFIG_PCI_IOV */ 208 209 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 210 pci_channel_state_t); 211 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 212 static void igb_io_resume(struct pci_dev *); 213 214 static const struct pci_error_handlers igb_err_handler = { 215 .error_detected = igb_io_error_detected, 216 .slot_reset = igb_io_slot_reset, 217 .resume = igb_io_resume, 218 }; 219 220 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 221 222 static struct pci_driver igb_driver = { 223 .name = igb_driver_name, 224 .id_table = igb_pci_tbl, 225 .probe = igb_probe, 226 .remove = igb_remove, 227 #ifdef CONFIG_PM 228 .driver.pm = &igb_pm_ops, 229 #endif 230 .shutdown = igb_shutdown, 231 .sriov_configure = igb_pci_sriov_configure, 232 .err_handler = &igb_err_handler 233 }; 234 235 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 236 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 237 MODULE_LICENSE("GPL v2"); 238 239 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 240 static int debug = -1; 241 module_param(debug, int, 0); 242 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 243 244 struct igb_reg_info { 245 u32 ofs; 246 char *name; 247 }; 248 249 static const struct igb_reg_info igb_reg_info_tbl[] = { 250 251 /* General Registers */ 252 {E1000_CTRL, "CTRL"}, 253 {E1000_STATUS, "STATUS"}, 254 {E1000_CTRL_EXT, "CTRL_EXT"}, 255 256 /* Interrupt Registers */ 257 {E1000_ICR, "ICR"}, 258 259 /* RX Registers */ 260 {E1000_RCTL, "RCTL"}, 261 {E1000_RDLEN(0), "RDLEN"}, 262 {E1000_RDH(0), "RDH"}, 263 {E1000_RDT(0), "RDT"}, 264 {E1000_RXDCTL(0), "RXDCTL"}, 265 {E1000_RDBAL(0), "RDBAL"}, 266 {E1000_RDBAH(0), "RDBAH"}, 267 268 /* TX Registers */ 269 {E1000_TCTL, "TCTL"}, 270 {E1000_TDBAL(0), "TDBAL"}, 271 {E1000_TDBAH(0), "TDBAH"}, 272 {E1000_TDLEN(0), "TDLEN"}, 273 {E1000_TDH(0), "TDH"}, 274 {E1000_TDT(0), "TDT"}, 275 {E1000_TXDCTL(0), "TXDCTL"}, 276 {E1000_TDFH, "TDFH"}, 277 {E1000_TDFT, "TDFT"}, 278 {E1000_TDFHS, "TDFHS"}, 279 {E1000_TDFPC, "TDFPC"}, 280 281 /* List Terminator */ 282 {} 283 }; 284 285 /* igb_regdump - register printout routine */ 286 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 287 { 288 int n = 0; 289 char rname[16]; 290 u32 regs[8]; 291 292 switch (reginfo->ofs) { 293 case E1000_RDLEN(0): 294 for (n = 0; n < 4; n++) 295 regs[n] = rd32(E1000_RDLEN(n)); 296 break; 297 case E1000_RDH(0): 298 for (n = 0; n < 4; n++) 299 regs[n] = rd32(E1000_RDH(n)); 300 break; 301 case E1000_RDT(0): 302 for (n = 0; n < 4; n++) 303 regs[n] = rd32(E1000_RDT(n)); 304 break; 305 case E1000_RXDCTL(0): 306 for (n = 0; n < 4; n++) 307 regs[n] = rd32(E1000_RXDCTL(n)); 308 break; 309 case E1000_RDBAL(0): 310 for (n = 0; n < 4; n++) 311 regs[n] = rd32(E1000_RDBAL(n)); 312 break; 313 case E1000_RDBAH(0): 314 for (n = 0; n < 4; n++) 315 regs[n] = rd32(E1000_RDBAH(n)); 316 break; 317 case E1000_TDBAL(0): 318 for (n = 0; n < 4; n++) 319 regs[n] = rd32(E1000_TDBAL(n)); 320 break; 321 case E1000_TDBAH(0): 322 for (n = 0; n < 4; n++) 323 regs[n] = rd32(E1000_TDBAH(n)); 324 break; 325 case E1000_TDLEN(0): 326 for (n = 0; n < 4; n++) 327 regs[n] = rd32(E1000_TDLEN(n)); 328 break; 329 case E1000_TDH(0): 330 for (n = 0; n < 4; n++) 331 regs[n] = rd32(E1000_TDH(n)); 332 break; 333 case E1000_TDT(0): 334 for (n = 0; n < 4; n++) 335 regs[n] = rd32(E1000_TDT(n)); 336 break; 337 case E1000_TXDCTL(0): 338 for (n = 0; n < 4; n++) 339 regs[n] = rd32(E1000_TXDCTL(n)); 340 break; 341 default: 342 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 343 return; 344 } 345 346 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 347 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 348 regs[2], regs[3]); 349 } 350 351 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 352 static void igb_dump(struct igb_adapter *adapter) 353 { 354 struct net_device *netdev = adapter->netdev; 355 struct e1000_hw *hw = &adapter->hw; 356 struct igb_reg_info *reginfo; 357 struct igb_ring *tx_ring; 358 union e1000_adv_tx_desc *tx_desc; 359 struct my_u0 { __le64 a; __le64 b; } *u0; 360 struct igb_ring *rx_ring; 361 union e1000_adv_rx_desc *rx_desc; 362 u32 staterr; 363 u16 i, n; 364 365 if (!netif_msg_hw(adapter)) 366 return; 367 368 /* Print netdevice Info */ 369 if (netdev) { 370 dev_info(&adapter->pdev->dev, "Net device Info\n"); 371 pr_info("Device Name state trans_start\n"); 372 pr_info("%-15s %016lX %016lX\n", netdev->name, 373 netdev->state, dev_trans_start(netdev)); 374 } 375 376 /* Print Registers */ 377 dev_info(&adapter->pdev->dev, "Register Dump\n"); 378 pr_info(" Register Name Value\n"); 379 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 380 reginfo->name; reginfo++) { 381 igb_regdump(hw, reginfo); 382 } 383 384 /* Print TX Ring Summary */ 385 if (!netdev || !netif_running(netdev)) 386 goto exit; 387 388 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 389 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 390 for (n = 0; n < adapter->num_tx_queues; n++) { 391 struct igb_tx_buffer *buffer_info; 392 tx_ring = adapter->tx_ring[n]; 393 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 394 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 395 n, tx_ring->next_to_use, tx_ring->next_to_clean, 396 (u64)dma_unmap_addr(buffer_info, dma), 397 dma_unmap_len(buffer_info, len), 398 buffer_info->next_to_watch, 399 (u64)buffer_info->time_stamp); 400 } 401 402 /* Print TX Rings */ 403 if (!netif_msg_tx_done(adapter)) 404 goto rx_ring_summary; 405 406 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 407 408 /* Transmit Descriptor Formats 409 * 410 * Advanced Transmit Descriptor 411 * +--------------------------------------------------------------+ 412 * 0 | Buffer Address [63:0] | 413 * +--------------------------------------------------------------+ 414 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 415 * +--------------------------------------------------------------+ 416 * 63 46 45 40 39 38 36 35 32 31 24 15 0 417 */ 418 419 for (n = 0; n < adapter->num_tx_queues; n++) { 420 tx_ring = adapter->tx_ring[n]; 421 pr_info("------------------------------------\n"); 422 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 423 pr_info("------------------------------------\n"); 424 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 425 426 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 427 const char *next_desc; 428 struct igb_tx_buffer *buffer_info; 429 tx_desc = IGB_TX_DESC(tx_ring, i); 430 buffer_info = &tx_ring->tx_buffer_info[i]; 431 u0 = (struct my_u0 *)tx_desc; 432 if (i == tx_ring->next_to_use && 433 i == tx_ring->next_to_clean) 434 next_desc = " NTC/U"; 435 else if (i == tx_ring->next_to_use) 436 next_desc = " NTU"; 437 else if (i == tx_ring->next_to_clean) 438 next_desc = " NTC"; 439 else 440 next_desc = ""; 441 442 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 443 i, le64_to_cpu(u0->a), 444 le64_to_cpu(u0->b), 445 (u64)dma_unmap_addr(buffer_info, dma), 446 dma_unmap_len(buffer_info, len), 447 buffer_info->next_to_watch, 448 (u64)buffer_info->time_stamp, 449 buffer_info->skb, next_desc); 450 451 if (netif_msg_pktdata(adapter) && buffer_info->skb) 452 print_hex_dump(KERN_INFO, "", 453 DUMP_PREFIX_ADDRESS, 454 16, 1, buffer_info->skb->data, 455 dma_unmap_len(buffer_info, len), 456 true); 457 } 458 } 459 460 /* Print RX Rings Summary */ 461 rx_ring_summary: 462 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 463 pr_info("Queue [NTU] [NTC]\n"); 464 for (n = 0; n < adapter->num_rx_queues; n++) { 465 rx_ring = adapter->rx_ring[n]; 466 pr_info(" %5d %5X %5X\n", 467 n, rx_ring->next_to_use, rx_ring->next_to_clean); 468 } 469 470 /* Print RX Rings */ 471 if (!netif_msg_rx_status(adapter)) 472 goto exit; 473 474 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 475 476 /* Advanced Receive Descriptor (Read) Format 477 * 63 1 0 478 * +-----------------------------------------------------+ 479 * 0 | Packet Buffer Address [63:1] |A0/NSE| 480 * +----------------------------------------------+------+ 481 * 8 | Header Buffer Address [63:1] | DD | 482 * +-----------------------------------------------------+ 483 * 484 * 485 * Advanced Receive Descriptor (Write-Back) Format 486 * 487 * 63 48 47 32 31 30 21 20 17 16 4 3 0 488 * +------------------------------------------------------+ 489 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 490 * | Checksum Ident | | | | Type | Type | 491 * +------------------------------------------------------+ 492 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 493 * +------------------------------------------------------+ 494 * 63 48 47 32 31 20 19 0 495 */ 496 497 for (n = 0; n < adapter->num_rx_queues; n++) { 498 rx_ring = adapter->rx_ring[n]; 499 pr_info("------------------------------------\n"); 500 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 501 pr_info("------------------------------------\n"); 502 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 503 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 504 505 for (i = 0; i < rx_ring->count; i++) { 506 const char *next_desc; 507 struct igb_rx_buffer *buffer_info; 508 buffer_info = &rx_ring->rx_buffer_info[i]; 509 rx_desc = IGB_RX_DESC(rx_ring, i); 510 u0 = (struct my_u0 *)rx_desc; 511 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 512 513 if (i == rx_ring->next_to_use) 514 next_desc = " NTU"; 515 else if (i == rx_ring->next_to_clean) 516 next_desc = " NTC"; 517 else 518 next_desc = ""; 519 520 if (staterr & E1000_RXD_STAT_DD) { 521 /* Descriptor Done */ 522 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 523 "RWB", i, 524 le64_to_cpu(u0->a), 525 le64_to_cpu(u0->b), 526 next_desc); 527 } else { 528 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 529 "R ", i, 530 le64_to_cpu(u0->a), 531 le64_to_cpu(u0->b), 532 (u64)buffer_info->dma, 533 next_desc); 534 535 if (netif_msg_pktdata(adapter) && 536 buffer_info->dma && buffer_info->page) { 537 print_hex_dump(KERN_INFO, "", 538 DUMP_PREFIX_ADDRESS, 539 16, 1, 540 page_address(buffer_info->page) + 541 buffer_info->page_offset, 542 igb_rx_bufsz(rx_ring), true); 543 } 544 } 545 } 546 } 547 548 exit: 549 return; 550 } 551 552 /** 553 * igb_get_i2c_data - Reads the I2C SDA data bit 554 * @data: opaque pointer to adapter struct 555 * 556 * Returns the I2C data bit value 557 **/ 558 static int igb_get_i2c_data(void *data) 559 { 560 struct igb_adapter *adapter = (struct igb_adapter *)data; 561 struct e1000_hw *hw = &adapter->hw; 562 s32 i2cctl = rd32(E1000_I2CPARAMS); 563 564 return !!(i2cctl & E1000_I2C_DATA_IN); 565 } 566 567 /** 568 * igb_set_i2c_data - Sets the I2C data bit 569 * @data: pointer to hardware structure 570 * @state: I2C data value (0 or 1) to set 571 * 572 * Sets the I2C data bit 573 **/ 574 static void igb_set_i2c_data(void *data, int state) 575 { 576 struct igb_adapter *adapter = (struct igb_adapter *)data; 577 struct e1000_hw *hw = &adapter->hw; 578 s32 i2cctl = rd32(E1000_I2CPARAMS); 579 580 if (state) { 581 i2cctl |= E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N; 582 } else { 583 i2cctl &= ~E1000_I2C_DATA_OE_N; 584 i2cctl &= ~E1000_I2C_DATA_OUT; 585 } 586 587 wr32(E1000_I2CPARAMS, i2cctl); 588 wrfl(); 589 } 590 591 /** 592 * igb_set_i2c_clk - Sets the I2C SCL clock 593 * @data: pointer to hardware structure 594 * @state: state to set clock 595 * 596 * Sets the I2C clock line to state 597 **/ 598 static void igb_set_i2c_clk(void *data, int state) 599 { 600 struct igb_adapter *adapter = (struct igb_adapter *)data; 601 struct e1000_hw *hw = &adapter->hw; 602 s32 i2cctl = rd32(E1000_I2CPARAMS); 603 604 if (state) { 605 i2cctl |= E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N; 606 } else { 607 i2cctl &= ~E1000_I2C_CLK_OUT; 608 i2cctl &= ~E1000_I2C_CLK_OE_N; 609 } 610 wr32(E1000_I2CPARAMS, i2cctl); 611 wrfl(); 612 } 613 614 /** 615 * igb_get_i2c_clk - Gets the I2C SCL clock state 616 * @data: pointer to hardware structure 617 * 618 * Gets the I2C clock state 619 **/ 620 static int igb_get_i2c_clk(void *data) 621 { 622 struct igb_adapter *adapter = (struct igb_adapter *)data; 623 struct e1000_hw *hw = &adapter->hw; 624 s32 i2cctl = rd32(E1000_I2CPARAMS); 625 626 return !!(i2cctl & E1000_I2C_CLK_IN); 627 } 628 629 static const struct i2c_algo_bit_data igb_i2c_algo = { 630 .setsda = igb_set_i2c_data, 631 .setscl = igb_set_i2c_clk, 632 .getsda = igb_get_i2c_data, 633 .getscl = igb_get_i2c_clk, 634 .udelay = 5, 635 .timeout = 20, 636 }; 637 638 /** 639 * igb_get_hw_dev - return device 640 * @hw: pointer to hardware structure 641 * 642 * used by hardware layer to print debugging information 643 **/ 644 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 645 { 646 struct igb_adapter *adapter = hw->back; 647 return adapter->netdev; 648 } 649 650 /** 651 * igb_init_module - Driver Registration Routine 652 * 653 * igb_init_module is the first routine called when the driver is 654 * loaded. All it does is register with the PCI subsystem. 655 **/ 656 static int __init igb_init_module(void) 657 { 658 int ret; 659 660 pr_info("%s\n", igb_driver_string); 661 pr_info("%s\n", igb_copyright); 662 663 #ifdef CONFIG_IGB_DCA 664 dca_register_notify(&dca_notifier); 665 #endif 666 ret = pci_register_driver(&igb_driver); 667 return ret; 668 } 669 670 module_init(igb_init_module); 671 672 /** 673 * igb_exit_module - Driver Exit Cleanup Routine 674 * 675 * igb_exit_module is called just before the driver is removed 676 * from memory. 677 **/ 678 static void __exit igb_exit_module(void) 679 { 680 #ifdef CONFIG_IGB_DCA 681 dca_unregister_notify(&dca_notifier); 682 #endif 683 pci_unregister_driver(&igb_driver); 684 } 685 686 module_exit(igb_exit_module); 687 688 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 689 /** 690 * igb_cache_ring_register - Descriptor ring to register mapping 691 * @adapter: board private structure to initialize 692 * 693 * Once we know the feature-set enabled for the device, we'll cache 694 * the register offset the descriptor ring is assigned to. 695 **/ 696 static void igb_cache_ring_register(struct igb_adapter *adapter) 697 { 698 int i = 0, j = 0; 699 u32 rbase_offset = adapter->vfs_allocated_count; 700 701 switch (adapter->hw.mac.type) { 702 case e1000_82576: 703 /* The queues are allocated for virtualization such that VF 0 704 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 705 * In order to avoid collision we start at the first free queue 706 * and continue consuming queues in the same sequence 707 */ 708 if (adapter->vfs_allocated_count) { 709 for (; i < adapter->rss_queues; i++) 710 adapter->rx_ring[i]->reg_idx = rbase_offset + 711 Q_IDX_82576(i); 712 } 713 fallthrough; 714 case e1000_82575: 715 case e1000_82580: 716 case e1000_i350: 717 case e1000_i354: 718 case e1000_i210: 719 case e1000_i211: 720 default: 721 for (; i < adapter->num_rx_queues; i++) 722 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 723 for (; j < adapter->num_tx_queues; j++) 724 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 725 break; 726 } 727 } 728 729 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 730 { 731 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 732 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 733 u32 value = 0; 734 735 if (E1000_REMOVED(hw_addr)) 736 return ~value; 737 738 value = readl(&hw_addr[reg]); 739 740 /* reads should not return all F's */ 741 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 742 struct net_device *netdev = igb->netdev; 743 hw->hw_addr = NULL; 744 netdev_err(netdev, "PCIe link lost\n"); 745 WARN(pci_device_is_present(igb->pdev), 746 "igb: Failed to read reg 0x%x!\n", reg); 747 } 748 749 return value; 750 } 751 752 /** 753 * igb_write_ivar - configure ivar for given MSI-X vector 754 * @hw: pointer to the HW structure 755 * @msix_vector: vector number we are allocating to a given ring 756 * @index: row index of IVAR register to write within IVAR table 757 * @offset: column offset of in IVAR, should be multiple of 8 758 * 759 * This function is intended to handle the writing of the IVAR register 760 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 761 * each containing an cause allocation for an Rx and Tx ring, and a 762 * variable number of rows depending on the number of queues supported. 763 **/ 764 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 765 int index, int offset) 766 { 767 u32 ivar = array_rd32(E1000_IVAR0, index); 768 769 /* clear any bits that are currently set */ 770 ivar &= ~((u32)0xFF << offset); 771 772 /* write vector and valid bit */ 773 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 774 775 array_wr32(E1000_IVAR0, index, ivar); 776 } 777 778 #define IGB_N0_QUEUE -1 779 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 780 { 781 struct igb_adapter *adapter = q_vector->adapter; 782 struct e1000_hw *hw = &adapter->hw; 783 int rx_queue = IGB_N0_QUEUE; 784 int tx_queue = IGB_N0_QUEUE; 785 u32 msixbm = 0; 786 787 if (q_vector->rx.ring) 788 rx_queue = q_vector->rx.ring->reg_idx; 789 if (q_vector->tx.ring) 790 tx_queue = q_vector->tx.ring->reg_idx; 791 792 switch (hw->mac.type) { 793 case e1000_82575: 794 /* The 82575 assigns vectors using a bitmask, which matches the 795 * bitmask for the EICR/EIMS/EIMC registers. To assign one 796 * or more queues to a vector, we write the appropriate bits 797 * into the MSIXBM register for that vector. 798 */ 799 if (rx_queue > IGB_N0_QUEUE) 800 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 801 if (tx_queue > IGB_N0_QUEUE) 802 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 803 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 804 msixbm |= E1000_EIMS_OTHER; 805 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 806 q_vector->eims_value = msixbm; 807 break; 808 case e1000_82576: 809 /* 82576 uses a table that essentially consists of 2 columns 810 * with 8 rows. The ordering is column-major so we use the 811 * lower 3 bits as the row index, and the 4th bit as the 812 * column offset. 813 */ 814 if (rx_queue > IGB_N0_QUEUE) 815 igb_write_ivar(hw, msix_vector, 816 rx_queue & 0x7, 817 (rx_queue & 0x8) << 1); 818 if (tx_queue > IGB_N0_QUEUE) 819 igb_write_ivar(hw, msix_vector, 820 tx_queue & 0x7, 821 ((tx_queue & 0x8) << 1) + 8); 822 q_vector->eims_value = BIT(msix_vector); 823 break; 824 case e1000_82580: 825 case e1000_i350: 826 case e1000_i354: 827 case e1000_i210: 828 case e1000_i211: 829 /* On 82580 and newer adapters the scheme is similar to 82576 830 * however instead of ordering column-major we have things 831 * ordered row-major. So we traverse the table by using 832 * bit 0 as the column offset, and the remaining bits as the 833 * row index. 834 */ 835 if (rx_queue > IGB_N0_QUEUE) 836 igb_write_ivar(hw, msix_vector, 837 rx_queue >> 1, 838 (rx_queue & 0x1) << 4); 839 if (tx_queue > IGB_N0_QUEUE) 840 igb_write_ivar(hw, msix_vector, 841 tx_queue >> 1, 842 ((tx_queue & 0x1) << 4) + 8); 843 q_vector->eims_value = BIT(msix_vector); 844 break; 845 default: 846 BUG(); 847 break; 848 } 849 850 /* add q_vector eims value to global eims_enable_mask */ 851 adapter->eims_enable_mask |= q_vector->eims_value; 852 853 /* configure q_vector to set itr on first interrupt */ 854 q_vector->set_itr = 1; 855 } 856 857 /** 858 * igb_configure_msix - Configure MSI-X hardware 859 * @adapter: board private structure to initialize 860 * 861 * igb_configure_msix sets up the hardware to properly 862 * generate MSI-X interrupts. 863 **/ 864 static void igb_configure_msix(struct igb_adapter *adapter) 865 { 866 u32 tmp; 867 int i, vector = 0; 868 struct e1000_hw *hw = &adapter->hw; 869 870 adapter->eims_enable_mask = 0; 871 872 /* set vector for other causes, i.e. link changes */ 873 switch (hw->mac.type) { 874 case e1000_82575: 875 tmp = rd32(E1000_CTRL_EXT); 876 /* enable MSI-X PBA support*/ 877 tmp |= E1000_CTRL_EXT_PBA_CLR; 878 879 /* Auto-Mask interrupts upon ICR read. */ 880 tmp |= E1000_CTRL_EXT_EIAME; 881 tmp |= E1000_CTRL_EXT_IRCA; 882 883 wr32(E1000_CTRL_EXT, tmp); 884 885 /* enable msix_other interrupt */ 886 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 887 adapter->eims_other = E1000_EIMS_OTHER; 888 889 break; 890 891 case e1000_82576: 892 case e1000_82580: 893 case e1000_i350: 894 case e1000_i354: 895 case e1000_i210: 896 case e1000_i211: 897 /* Turn on MSI-X capability first, or our settings 898 * won't stick. And it will take days to debug. 899 */ 900 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 901 E1000_GPIE_PBA | E1000_GPIE_EIAME | 902 E1000_GPIE_NSICR); 903 904 /* enable msix_other interrupt */ 905 adapter->eims_other = BIT(vector); 906 tmp = (vector++ | E1000_IVAR_VALID) << 8; 907 908 wr32(E1000_IVAR_MISC, tmp); 909 break; 910 default: 911 /* do nothing, since nothing else supports MSI-X */ 912 break; 913 } /* switch (hw->mac.type) */ 914 915 adapter->eims_enable_mask |= adapter->eims_other; 916 917 for (i = 0; i < adapter->num_q_vectors; i++) 918 igb_assign_vector(adapter->q_vector[i], vector++); 919 920 wrfl(); 921 } 922 923 /** 924 * igb_request_msix - Initialize MSI-X interrupts 925 * @adapter: board private structure to initialize 926 * 927 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 928 * kernel. 929 **/ 930 static int igb_request_msix(struct igb_adapter *adapter) 931 { 932 unsigned int num_q_vectors = adapter->num_q_vectors; 933 struct net_device *netdev = adapter->netdev; 934 int i, err = 0, vector = 0, free_vector = 0; 935 936 err = request_irq(adapter->msix_entries[vector].vector, 937 igb_msix_other, 0, netdev->name, adapter); 938 if (err) 939 goto err_out; 940 941 if (num_q_vectors > MAX_Q_VECTORS) { 942 num_q_vectors = MAX_Q_VECTORS; 943 dev_warn(&adapter->pdev->dev, 944 "The number of queue vectors (%d) is higher than max allowed (%d)\n", 945 adapter->num_q_vectors, MAX_Q_VECTORS); 946 } 947 for (i = 0; i < num_q_vectors; i++) { 948 struct igb_q_vector *q_vector = adapter->q_vector[i]; 949 950 vector++; 951 952 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 953 954 if (q_vector->rx.ring && q_vector->tx.ring) 955 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 956 q_vector->rx.ring->queue_index); 957 else if (q_vector->tx.ring) 958 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 959 q_vector->tx.ring->queue_index); 960 else if (q_vector->rx.ring) 961 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 962 q_vector->rx.ring->queue_index); 963 else 964 sprintf(q_vector->name, "%s-unused", netdev->name); 965 966 err = request_irq(adapter->msix_entries[vector].vector, 967 igb_msix_ring, 0, q_vector->name, 968 q_vector); 969 if (err) 970 goto err_free; 971 } 972 973 igb_configure_msix(adapter); 974 return 0; 975 976 err_free: 977 /* free already assigned IRQs */ 978 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 979 980 vector--; 981 for (i = 0; i < vector; i++) { 982 free_irq(adapter->msix_entries[free_vector++].vector, 983 adapter->q_vector[i]); 984 } 985 err_out: 986 return err; 987 } 988 989 /** 990 * igb_free_q_vector - Free memory allocated for specific interrupt vector 991 * @adapter: board private structure to initialize 992 * @v_idx: Index of vector to be freed 993 * 994 * This function frees the memory allocated to the q_vector. 995 **/ 996 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 997 { 998 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 999 1000 adapter->q_vector[v_idx] = NULL; 1001 1002 /* igb_get_stats64() might access the rings on this vector, 1003 * we must wait a grace period before freeing it. 1004 */ 1005 if (q_vector) 1006 kfree_rcu(q_vector, rcu); 1007 } 1008 1009 /** 1010 * igb_reset_q_vector - Reset config for interrupt vector 1011 * @adapter: board private structure to initialize 1012 * @v_idx: Index of vector to be reset 1013 * 1014 * If NAPI is enabled it will delete any references to the 1015 * NAPI struct. This is preparation for igb_free_q_vector. 1016 **/ 1017 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1018 { 1019 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1020 1021 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1022 * allocated. So, q_vector is NULL so we should stop here. 1023 */ 1024 if (!q_vector) 1025 return; 1026 1027 if (q_vector->tx.ring) 1028 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1029 1030 if (q_vector->rx.ring) 1031 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1032 1033 netif_napi_del(&q_vector->napi); 1034 1035 } 1036 1037 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1038 { 1039 int v_idx = adapter->num_q_vectors; 1040 1041 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1042 pci_disable_msix(adapter->pdev); 1043 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1044 pci_disable_msi(adapter->pdev); 1045 1046 while (v_idx--) 1047 igb_reset_q_vector(adapter, v_idx); 1048 } 1049 1050 /** 1051 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1052 * @adapter: board private structure to initialize 1053 * 1054 * This function frees the memory allocated to the q_vectors. In addition if 1055 * NAPI is enabled it will delete any references to the NAPI struct prior 1056 * to freeing the q_vector. 1057 **/ 1058 static void igb_free_q_vectors(struct igb_adapter *adapter) 1059 { 1060 int v_idx = adapter->num_q_vectors; 1061 1062 adapter->num_tx_queues = 0; 1063 adapter->num_rx_queues = 0; 1064 adapter->num_q_vectors = 0; 1065 1066 while (v_idx--) { 1067 igb_reset_q_vector(adapter, v_idx); 1068 igb_free_q_vector(adapter, v_idx); 1069 } 1070 } 1071 1072 /** 1073 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1074 * @adapter: board private structure to initialize 1075 * 1076 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1077 * MSI-X interrupts allocated. 1078 */ 1079 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1080 { 1081 igb_free_q_vectors(adapter); 1082 igb_reset_interrupt_capability(adapter); 1083 } 1084 1085 /** 1086 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1087 * @adapter: board private structure to initialize 1088 * @msix: boolean value of MSIX capability 1089 * 1090 * Attempt to configure interrupts using the best available 1091 * capabilities of the hardware and kernel. 1092 **/ 1093 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1094 { 1095 int err; 1096 int numvecs, i; 1097 1098 if (!msix) 1099 goto msi_only; 1100 adapter->flags |= IGB_FLAG_HAS_MSIX; 1101 1102 /* Number of supported queues. */ 1103 adapter->num_rx_queues = adapter->rss_queues; 1104 if (adapter->vfs_allocated_count) 1105 adapter->num_tx_queues = 1; 1106 else 1107 adapter->num_tx_queues = adapter->rss_queues; 1108 1109 /* start with one vector for every Rx queue */ 1110 numvecs = adapter->num_rx_queues; 1111 1112 /* if Tx handler is separate add 1 for every Tx queue */ 1113 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1114 numvecs += adapter->num_tx_queues; 1115 1116 /* store the number of vectors reserved for queues */ 1117 adapter->num_q_vectors = numvecs; 1118 1119 /* add 1 vector for link status interrupts */ 1120 numvecs++; 1121 for (i = 0; i < numvecs; i++) 1122 adapter->msix_entries[i].entry = i; 1123 1124 err = pci_enable_msix_range(adapter->pdev, 1125 adapter->msix_entries, 1126 numvecs, 1127 numvecs); 1128 if (err > 0) 1129 return; 1130 1131 igb_reset_interrupt_capability(adapter); 1132 1133 /* If we can't do MSI-X, try MSI */ 1134 msi_only: 1135 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1136 #ifdef CONFIG_PCI_IOV 1137 /* disable SR-IOV for non MSI-X configurations */ 1138 if (adapter->vf_data) { 1139 struct e1000_hw *hw = &adapter->hw; 1140 /* disable iov and allow time for transactions to clear */ 1141 pci_disable_sriov(adapter->pdev); 1142 msleep(500); 1143 1144 kfree(adapter->vf_mac_list); 1145 adapter->vf_mac_list = NULL; 1146 kfree(adapter->vf_data); 1147 adapter->vf_data = NULL; 1148 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1149 wrfl(); 1150 msleep(100); 1151 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1152 } 1153 #endif 1154 adapter->vfs_allocated_count = 0; 1155 adapter->rss_queues = 1; 1156 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1157 adapter->num_rx_queues = 1; 1158 adapter->num_tx_queues = 1; 1159 adapter->num_q_vectors = 1; 1160 if (!pci_enable_msi(adapter->pdev)) 1161 adapter->flags |= IGB_FLAG_HAS_MSI; 1162 } 1163 1164 static void igb_add_ring(struct igb_ring *ring, 1165 struct igb_ring_container *head) 1166 { 1167 head->ring = ring; 1168 head->count++; 1169 } 1170 1171 /** 1172 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1173 * @adapter: board private structure to initialize 1174 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1175 * @v_idx: index of vector in adapter struct 1176 * @txr_count: total number of Tx rings to allocate 1177 * @txr_idx: index of first Tx ring to allocate 1178 * @rxr_count: total number of Rx rings to allocate 1179 * @rxr_idx: index of first Rx ring to allocate 1180 * 1181 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1182 **/ 1183 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1184 int v_count, int v_idx, 1185 int txr_count, int txr_idx, 1186 int rxr_count, int rxr_idx) 1187 { 1188 struct igb_q_vector *q_vector; 1189 struct igb_ring *ring; 1190 int ring_count; 1191 size_t size; 1192 1193 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1194 if (txr_count > 1 || rxr_count > 1) 1195 return -ENOMEM; 1196 1197 ring_count = txr_count + rxr_count; 1198 size = kmalloc_size_roundup(struct_size(q_vector, ring, ring_count)); 1199 1200 /* allocate q_vector and rings */ 1201 q_vector = adapter->q_vector[v_idx]; 1202 if (!q_vector) { 1203 q_vector = kzalloc(size, GFP_KERNEL); 1204 } else if (size > ksize(q_vector)) { 1205 struct igb_q_vector *new_q_vector; 1206 1207 new_q_vector = kzalloc(size, GFP_KERNEL); 1208 if (new_q_vector) 1209 kfree_rcu(q_vector, rcu); 1210 q_vector = new_q_vector; 1211 } else { 1212 memset(q_vector, 0, size); 1213 } 1214 if (!q_vector) 1215 return -ENOMEM; 1216 1217 /* initialize NAPI */ 1218 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll); 1219 1220 /* tie q_vector and adapter together */ 1221 adapter->q_vector[v_idx] = q_vector; 1222 q_vector->adapter = adapter; 1223 1224 /* initialize work limits */ 1225 q_vector->tx.work_limit = adapter->tx_work_limit; 1226 1227 /* initialize ITR configuration */ 1228 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1229 q_vector->itr_val = IGB_START_ITR; 1230 1231 /* initialize pointer to rings */ 1232 ring = q_vector->ring; 1233 1234 /* intialize ITR */ 1235 if (rxr_count) { 1236 /* rx or rx/tx vector */ 1237 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1238 q_vector->itr_val = adapter->rx_itr_setting; 1239 } else { 1240 /* tx only vector */ 1241 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1242 q_vector->itr_val = adapter->tx_itr_setting; 1243 } 1244 1245 if (txr_count) { 1246 /* assign generic ring traits */ 1247 ring->dev = &adapter->pdev->dev; 1248 ring->netdev = adapter->netdev; 1249 1250 /* configure backlink on ring */ 1251 ring->q_vector = q_vector; 1252 1253 /* update q_vector Tx values */ 1254 igb_add_ring(ring, &q_vector->tx); 1255 1256 /* For 82575, context index must be unique per ring. */ 1257 if (adapter->hw.mac.type == e1000_82575) 1258 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1259 1260 /* apply Tx specific ring traits */ 1261 ring->count = adapter->tx_ring_count; 1262 ring->queue_index = txr_idx; 1263 1264 ring->cbs_enable = false; 1265 ring->idleslope = 0; 1266 ring->sendslope = 0; 1267 ring->hicredit = 0; 1268 ring->locredit = 0; 1269 1270 u64_stats_init(&ring->tx_syncp); 1271 u64_stats_init(&ring->tx_syncp2); 1272 1273 /* assign ring to adapter */ 1274 adapter->tx_ring[txr_idx] = ring; 1275 1276 /* push pointer to next ring */ 1277 ring++; 1278 } 1279 1280 if (rxr_count) { 1281 /* assign generic ring traits */ 1282 ring->dev = &adapter->pdev->dev; 1283 ring->netdev = adapter->netdev; 1284 1285 /* configure backlink on ring */ 1286 ring->q_vector = q_vector; 1287 1288 /* update q_vector Rx values */ 1289 igb_add_ring(ring, &q_vector->rx); 1290 1291 /* set flag indicating ring supports SCTP checksum offload */ 1292 if (adapter->hw.mac.type >= e1000_82576) 1293 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1294 1295 /* On i350, i354, i210, and i211, loopback VLAN packets 1296 * have the tag byte-swapped. 1297 */ 1298 if (adapter->hw.mac.type >= e1000_i350) 1299 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1300 1301 /* apply Rx specific ring traits */ 1302 ring->count = adapter->rx_ring_count; 1303 ring->queue_index = rxr_idx; 1304 1305 u64_stats_init(&ring->rx_syncp); 1306 1307 /* assign ring to adapter */ 1308 adapter->rx_ring[rxr_idx] = ring; 1309 } 1310 1311 return 0; 1312 } 1313 1314 1315 /** 1316 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1317 * @adapter: board private structure to initialize 1318 * 1319 * We allocate one q_vector per queue interrupt. If allocation fails we 1320 * return -ENOMEM. 1321 **/ 1322 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1323 { 1324 int q_vectors = adapter->num_q_vectors; 1325 int rxr_remaining = adapter->num_rx_queues; 1326 int txr_remaining = adapter->num_tx_queues; 1327 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1328 int err; 1329 1330 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1331 for (; rxr_remaining; v_idx++) { 1332 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1333 0, 0, 1, rxr_idx); 1334 1335 if (err) 1336 goto err_out; 1337 1338 /* update counts and index */ 1339 rxr_remaining--; 1340 rxr_idx++; 1341 } 1342 } 1343 1344 for (; v_idx < q_vectors; v_idx++) { 1345 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1346 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1347 1348 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1349 tqpv, txr_idx, rqpv, rxr_idx); 1350 1351 if (err) 1352 goto err_out; 1353 1354 /* update counts and index */ 1355 rxr_remaining -= rqpv; 1356 txr_remaining -= tqpv; 1357 rxr_idx++; 1358 txr_idx++; 1359 } 1360 1361 return 0; 1362 1363 err_out: 1364 adapter->num_tx_queues = 0; 1365 adapter->num_rx_queues = 0; 1366 adapter->num_q_vectors = 0; 1367 1368 while (v_idx--) 1369 igb_free_q_vector(adapter, v_idx); 1370 1371 return -ENOMEM; 1372 } 1373 1374 /** 1375 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1376 * @adapter: board private structure to initialize 1377 * @msix: boolean value of MSIX capability 1378 * 1379 * This function initializes the interrupts and allocates all of the queues. 1380 **/ 1381 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1382 { 1383 struct pci_dev *pdev = adapter->pdev; 1384 int err; 1385 1386 igb_set_interrupt_capability(adapter, msix); 1387 1388 err = igb_alloc_q_vectors(adapter); 1389 if (err) { 1390 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1391 goto err_alloc_q_vectors; 1392 } 1393 1394 igb_cache_ring_register(adapter); 1395 1396 return 0; 1397 1398 err_alloc_q_vectors: 1399 igb_reset_interrupt_capability(adapter); 1400 return err; 1401 } 1402 1403 /** 1404 * igb_request_irq - initialize interrupts 1405 * @adapter: board private structure to initialize 1406 * 1407 * Attempts to configure interrupts using the best available 1408 * capabilities of the hardware and kernel. 1409 **/ 1410 static int igb_request_irq(struct igb_adapter *adapter) 1411 { 1412 struct net_device *netdev = adapter->netdev; 1413 struct pci_dev *pdev = adapter->pdev; 1414 int err = 0; 1415 1416 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1417 err = igb_request_msix(adapter); 1418 if (!err) 1419 goto request_done; 1420 /* fall back to MSI */ 1421 igb_free_all_tx_resources(adapter); 1422 igb_free_all_rx_resources(adapter); 1423 1424 igb_clear_interrupt_scheme(adapter); 1425 err = igb_init_interrupt_scheme(adapter, false); 1426 if (err) 1427 goto request_done; 1428 1429 igb_setup_all_tx_resources(adapter); 1430 igb_setup_all_rx_resources(adapter); 1431 igb_configure(adapter); 1432 } 1433 1434 igb_assign_vector(adapter->q_vector[0], 0); 1435 1436 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1437 err = request_irq(pdev->irq, igb_intr_msi, 0, 1438 netdev->name, adapter); 1439 if (!err) 1440 goto request_done; 1441 1442 /* fall back to legacy interrupts */ 1443 igb_reset_interrupt_capability(adapter); 1444 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1445 } 1446 1447 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1448 netdev->name, adapter); 1449 1450 if (err) 1451 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1452 err); 1453 1454 request_done: 1455 return err; 1456 } 1457 1458 static void igb_free_irq(struct igb_adapter *adapter) 1459 { 1460 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1461 int vector = 0, i; 1462 1463 free_irq(adapter->msix_entries[vector++].vector, adapter); 1464 1465 for (i = 0; i < adapter->num_q_vectors; i++) 1466 free_irq(adapter->msix_entries[vector++].vector, 1467 adapter->q_vector[i]); 1468 } else { 1469 free_irq(adapter->pdev->irq, adapter); 1470 } 1471 } 1472 1473 /** 1474 * igb_irq_disable - Mask off interrupt generation on the NIC 1475 * @adapter: board private structure 1476 **/ 1477 static void igb_irq_disable(struct igb_adapter *adapter) 1478 { 1479 struct e1000_hw *hw = &adapter->hw; 1480 1481 /* we need to be careful when disabling interrupts. The VFs are also 1482 * mapped into these registers and so clearing the bits can cause 1483 * issues on the VF drivers so we only need to clear what we set 1484 */ 1485 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1486 u32 regval = rd32(E1000_EIAM); 1487 1488 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1489 wr32(E1000_EIMC, adapter->eims_enable_mask); 1490 regval = rd32(E1000_EIAC); 1491 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1492 } 1493 1494 wr32(E1000_IAM, 0); 1495 wr32(E1000_IMC, ~0); 1496 wrfl(); 1497 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1498 int i; 1499 1500 for (i = 0; i < adapter->num_q_vectors; i++) 1501 synchronize_irq(adapter->msix_entries[i].vector); 1502 } else { 1503 synchronize_irq(adapter->pdev->irq); 1504 } 1505 } 1506 1507 /** 1508 * igb_irq_enable - Enable default interrupt generation settings 1509 * @adapter: board private structure 1510 **/ 1511 static void igb_irq_enable(struct igb_adapter *adapter) 1512 { 1513 struct e1000_hw *hw = &adapter->hw; 1514 1515 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1516 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1517 u32 regval = rd32(E1000_EIAC); 1518 1519 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1520 regval = rd32(E1000_EIAM); 1521 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1522 wr32(E1000_EIMS, adapter->eims_enable_mask); 1523 if (adapter->vfs_allocated_count) { 1524 wr32(E1000_MBVFIMR, 0xFF); 1525 ims |= E1000_IMS_VMMB; 1526 } 1527 wr32(E1000_IMS, ims); 1528 } else { 1529 wr32(E1000_IMS, IMS_ENABLE_MASK | 1530 E1000_IMS_DRSTA); 1531 wr32(E1000_IAM, IMS_ENABLE_MASK | 1532 E1000_IMS_DRSTA); 1533 } 1534 } 1535 1536 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1537 { 1538 struct e1000_hw *hw = &adapter->hw; 1539 u16 pf_id = adapter->vfs_allocated_count; 1540 u16 vid = adapter->hw.mng_cookie.vlan_id; 1541 u16 old_vid = adapter->mng_vlan_id; 1542 1543 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1544 /* add VID to filter table */ 1545 igb_vfta_set(hw, vid, pf_id, true, true); 1546 adapter->mng_vlan_id = vid; 1547 } else { 1548 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1549 } 1550 1551 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1552 (vid != old_vid) && 1553 !test_bit(old_vid, adapter->active_vlans)) { 1554 /* remove VID from filter table */ 1555 igb_vfta_set(hw, vid, pf_id, false, true); 1556 } 1557 } 1558 1559 /** 1560 * igb_release_hw_control - release control of the h/w to f/w 1561 * @adapter: address of board private structure 1562 * 1563 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1564 * For ASF and Pass Through versions of f/w this means that the 1565 * driver is no longer loaded. 1566 **/ 1567 static void igb_release_hw_control(struct igb_adapter *adapter) 1568 { 1569 struct e1000_hw *hw = &adapter->hw; 1570 u32 ctrl_ext; 1571 1572 /* Let firmware take over control of h/w */ 1573 ctrl_ext = rd32(E1000_CTRL_EXT); 1574 wr32(E1000_CTRL_EXT, 1575 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1576 } 1577 1578 /** 1579 * igb_get_hw_control - get control of the h/w from f/w 1580 * @adapter: address of board private structure 1581 * 1582 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1583 * For ASF and Pass Through versions of f/w this means that 1584 * the driver is loaded. 1585 **/ 1586 static void igb_get_hw_control(struct igb_adapter *adapter) 1587 { 1588 struct e1000_hw *hw = &adapter->hw; 1589 u32 ctrl_ext; 1590 1591 /* Let firmware know the driver has taken over */ 1592 ctrl_ext = rd32(E1000_CTRL_EXT); 1593 wr32(E1000_CTRL_EXT, 1594 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1595 } 1596 1597 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1598 { 1599 struct net_device *netdev = adapter->netdev; 1600 struct e1000_hw *hw = &adapter->hw; 1601 1602 WARN_ON(hw->mac.type != e1000_i210); 1603 1604 if (enable) 1605 adapter->flags |= IGB_FLAG_FQTSS; 1606 else 1607 adapter->flags &= ~IGB_FLAG_FQTSS; 1608 1609 if (netif_running(netdev)) 1610 schedule_work(&adapter->reset_task); 1611 } 1612 1613 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1614 { 1615 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1616 } 1617 1618 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1619 enum tx_queue_prio prio) 1620 { 1621 u32 val; 1622 1623 WARN_ON(hw->mac.type != e1000_i210); 1624 WARN_ON(queue < 0 || queue > 4); 1625 1626 val = rd32(E1000_I210_TXDCTL(queue)); 1627 1628 if (prio == TX_QUEUE_PRIO_HIGH) 1629 val |= E1000_TXDCTL_PRIORITY; 1630 else 1631 val &= ~E1000_TXDCTL_PRIORITY; 1632 1633 wr32(E1000_I210_TXDCTL(queue), val); 1634 } 1635 1636 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1637 { 1638 u32 val; 1639 1640 WARN_ON(hw->mac.type != e1000_i210); 1641 WARN_ON(queue < 0 || queue > 1); 1642 1643 val = rd32(E1000_I210_TQAVCC(queue)); 1644 1645 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1646 val |= E1000_TQAVCC_QUEUEMODE; 1647 else 1648 val &= ~E1000_TQAVCC_QUEUEMODE; 1649 1650 wr32(E1000_I210_TQAVCC(queue), val); 1651 } 1652 1653 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1654 { 1655 int i; 1656 1657 for (i = 0; i < adapter->num_tx_queues; i++) { 1658 if (adapter->tx_ring[i]->cbs_enable) 1659 return true; 1660 } 1661 1662 return false; 1663 } 1664 1665 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1666 { 1667 int i; 1668 1669 for (i = 0; i < adapter->num_tx_queues; i++) { 1670 if (adapter->tx_ring[i]->launchtime_enable) 1671 return true; 1672 } 1673 1674 return false; 1675 } 1676 1677 /** 1678 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1679 * @adapter: pointer to adapter struct 1680 * @queue: queue number 1681 * 1682 * Configure CBS and Launchtime for a given hardware queue. 1683 * Parameters are retrieved from the correct Tx ring, so 1684 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1685 * for setting those correctly prior to this function being called. 1686 **/ 1687 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1688 { 1689 struct net_device *netdev = adapter->netdev; 1690 struct e1000_hw *hw = &adapter->hw; 1691 struct igb_ring *ring; 1692 u32 tqavcc, tqavctrl; 1693 u16 value; 1694 1695 WARN_ON(hw->mac.type != e1000_i210); 1696 WARN_ON(queue < 0 || queue > 1); 1697 ring = adapter->tx_ring[queue]; 1698 1699 /* If any of the Qav features is enabled, configure queues as SR and 1700 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1701 * as SP. 1702 */ 1703 if (ring->cbs_enable || ring->launchtime_enable) { 1704 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1705 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1706 } else { 1707 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1708 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1709 } 1710 1711 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1712 if (ring->cbs_enable || queue == 0) { 1713 /* i210 does not allow the queue 0 to be in the Strict 1714 * Priority mode while the Qav mode is enabled, so, 1715 * instead of disabling strict priority mode, we give 1716 * queue 0 the maximum of credits possible. 1717 * 1718 * See section 8.12.19 of the i210 datasheet, "Note: 1719 * Queue0 QueueMode must be set to 1b when 1720 * TransmitMode is set to Qav." 1721 */ 1722 if (queue == 0 && !ring->cbs_enable) { 1723 /* max "linkspeed" idleslope in kbps */ 1724 ring->idleslope = 1000000; 1725 ring->hicredit = ETH_FRAME_LEN; 1726 } 1727 1728 /* Always set data transfer arbitration to credit-based 1729 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1730 * the queues. 1731 */ 1732 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1733 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1734 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1735 1736 /* According to i210 datasheet section 7.2.7.7, we should set 1737 * the 'idleSlope' field from TQAVCC register following the 1738 * equation: 1739 * 1740 * For 100 Mbps link speed: 1741 * 1742 * value = BW * 0x7735 * 0.2 (E1) 1743 * 1744 * For 1000Mbps link speed: 1745 * 1746 * value = BW * 0x7735 * 2 (E2) 1747 * 1748 * E1 and E2 can be merged into one equation as shown below. 1749 * Note that 'link-speed' is in Mbps. 1750 * 1751 * value = BW * 0x7735 * 2 * link-speed 1752 * -------------- (E3) 1753 * 1000 1754 * 1755 * 'BW' is the percentage bandwidth out of full link speed 1756 * which can be found with the following equation. Note that 1757 * idleSlope here is the parameter from this function which 1758 * is in kbps. 1759 * 1760 * BW = idleSlope 1761 * ----------------- (E4) 1762 * link-speed * 1000 1763 * 1764 * That said, we can come up with a generic equation to 1765 * calculate the value we should set it TQAVCC register by 1766 * replacing 'BW' in E3 by E4. The resulting equation is: 1767 * 1768 * value = idleSlope * 0x7735 * 2 * link-speed 1769 * ----------------- -------------- (E5) 1770 * link-speed * 1000 1000 1771 * 1772 * 'link-speed' is present in both sides of the fraction so 1773 * it is canceled out. The final equation is the following: 1774 * 1775 * value = idleSlope * 61034 1776 * ----------------- (E6) 1777 * 1000000 1778 * 1779 * NOTE: For i210, given the above, we can see that idleslope 1780 * is represented in 16.38431 kbps units by the value at 1781 * the TQAVCC register (1Gbps / 61034), which reduces 1782 * the granularity for idleslope increments. 1783 * For instance, if you want to configure a 2576kbps 1784 * idleslope, the value to be written on the register 1785 * would have to be 157.23. If rounded down, you end 1786 * up with less bandwidth available than originally 1787 * required (~2572 kbps). If rounded up, you end up 1788 * with a higher bandwidth (~2589 kbps). Below the 1789 * approach we take is to always round up the 1790 * calculated value, so the resulting bandwidth might 1791 * be slightly higher for some configurations. 1792 */ 1793 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1794 1795 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1796 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1797 tqavcc |= value; 1798 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1799 1800 wr32(E1000_I210_TQAVHC(queue), 1801 0x80000000 + ring->hicredit * 0x7735); 1802 } else { 1803 1804 /* Set idleSlope to zero. */ 1805 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1806 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1807 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1808 1809 /* Set hiCredit to zero. */ 1810 wr32(E1000_I210_TQAVHC(queue), 0); 1811 1812 /* If CBS is not enabled for any queues anymore, then return to 1813 * the default state of Data Transmission Arbitration on 1814 * TQAVCTRL. 1815 */ 1816 if (!is_any_cbs_enabled(adapter)) { 1817 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1818 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1819 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1820 } 1821 } 1822 1823 /* If LaunchTime is enabled, set DataTranTIM. */ 1824 if (ring->launchtime_enable) { 1825 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1826 * for any of the SR queues, and configure fetchtime delta. 1827 * XXX NOTE: 1828 * - LaunchTime will be enabled for all SR queues. 1829 * - A fixed offset can be added relative to the launch 1830 * time of all packets if configured at reg LAUNCH_OS0. 1831 * We are keeping it as 0 for now (default value). 1832 */ 1833 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1834 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1835 E1000_TQAVCTRL_FETCHTIME_DELTA; 1836 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1837 } else { 1838 /* If Launchtime is not enabled for any SR queues anymore, 1839 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1840 * effectively disabling Launchtime. 1841 */ 1842 if (!is_any_txtime_enabled(adapter)) { 1843 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1844 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1845 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1846 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1847 } 1848 } 1849 1850 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1851 * CBS are not configurable by software so we don't do any 'controller 1852 * configuration' in respect to these parameters. 1853 */ 1854 1855 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1856 ring->cbs_enable ? "enabled" : "disabled", 1857 ring->launchtime_enable ? "enabled" : "disabled", 1858 queue, 1859 ring->idleslope, ring->sendslope, 1860 ring->hicredit, ring->locredit); 1861 } 1862 1863 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1864 bool enable) 1865 { 1866 struct igb_ring *ring; 1867 1868 if (queue < 0 || queue > adapter->num_tx_queues) 1869 return -EINVAL; 1870 1871 ring = adapter->tx_ring[queue]; 1872 ring->launchtime_enable = enable; 1873 1874 return 0; 1875 } 1876 1877 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1878 bool enable, int idleslope, int sendslope, 1879 int hicredit, int locredit) 1880 { 1881 struct igb_ring *ring; 1882 1883 if (queue < 0 || queue > adapter->num_tx_queues) 1884 return -EINVAL; 1885 1886 ring = adapter->tx_ring[queue]; 1887 1888 ring->cbs_enable = enable; 1889 ring->idleslope = idleslope; 1890 ring->sendslope = sendslope; 1891 ring->hicredit = hicredit; 1892 ring->locredit = locredit; 1893 1894 return 0; 1895 } 1896 1897 /** 1898 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1899 * @adapter: pointer to adapter struct 1900 * 1901 * Configure TQAVCTRL register switching the controller's Tx mode 1902 * if FQTSS mode is enabled or disabled. Additionally, will issue 1903 * a call to igb_config_tx_modes() per queue so any previously saved 1904 * Tx parameters are applied. 1905 **/ 1906 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1907 { 1908 struct net_device *netdev = adapter->netdev; 1909 struct e1000_hw *hw = &adapter->hw; 1910 u32 val; 1911 1912 /* Only i210 controller supports changing the transmission mode. */ 1913 if (hw->mac.type != e1000_i210) 1914 return; 1915 1916 if (is_fqtss_enabled(adapter)) { 1917 int i, max_queue; 1918 1919 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1920 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1921 * so SP queues wait for SR ones. 1922 */ 1923 val = rd32(E1000_I210_TQAVCTRL); 1924 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1925 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1926 wr32(E1000_I210_TQAVCTRL, val); 1927 1928 /* Configure Tx and Rx packet buffers sizes as described in 1929 * i210 datasheet section 7.2.7.7. 1930 */ 1931 val = rd32(E1000_TXPBS); 1932 val &= ~I210_TXPBSIZE_MASK; 1933 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB | 1934 I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB; 1935 wr32(E1000_TXPBS, val); 1936 1937 val = rd32(E1000_RXPBS); 1938 val &= ~I210_RXPBSIZE_MASK; 1939 val |= I210_RXPBSIZE_PB_30KB; 1940 wr32(E1000_RXPBS, val); 1941 1942 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1943 * register should not exceed the buffer size programmed in 1944 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1945 * so according to the datasheet we should set MAX_TPKT_SIZE to 1946 * 4kB / 64. 1947 * 1948 * However, when we do so, no frame from queue 2 and 3 are 1949 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1950 * or _equal_ to the buffer size programmed in TXPBS. For this 1951 * reason, we set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1952 */ 1953 val = (4096 - 1) / 64; 1954 wr32(E1000_I210_DTXMXPKTSZ, val); 1955 1956 /* Since FQTSS mode is enabled, apply any CBS configuration 1957 * previously set. If no previous CBS configuration has been 1958 * done, then the initial configuration is applied, which means 1959 * CBS is disabled. 1960 */ 1961 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1962 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1963 1964 for (i = 0; i < max_queue; i++) { 1965 igb_config_tx_modes(adapter, i); 1966 } 1967 } else { 1968 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1969 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1970 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1971 1972 val = rd32(E1000_I210_TQAVCTRL); 1973 /* According to Section 8.12.21, the other flags we've set when 1974 * enabling FQTSS are not relevant when disabling FQTSS so we 1975 * don't set they here. 1976 */ 1977 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1978 wr32(E1000_I210_TQAVCTRL, val); 1979 } 1980 1981 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1982 "enabled" : "disabled"); 1983 } 1984 1985 /** 1986 * igb_configure - configure the hardware for RX and TX 1987 * @adapter: private board structure 1988 **/ 1989 static void igb_configure(struct igb_adapter *adapter) 1990 { 1991 struct net_device *netdev = adapter->netdev; 1992 int i; 1993 1994 igb_get_hw_control(adapter); 1995 igb_set_rx_mode(netdev); 1996 igb_setup_tx_mode(adapter); 1997 1998 igb_restore_vlan(adapter); 1999 2000 igb_setup_tctl(adapter); 2001 igb_setup_mrqc(adapter); 2002 igb_setup_rctl(adapter); 2003 2004 igb_nfc_filter_restore(adapter); 2005 igb_configure_tx(adapter); 2006 igb_configure_rx(adapter); 2007 2008 igb_rx_fifo_flush_82575(&adapter->hw); 2009 2010 /* call igb_desc_unused which always leaves 2011 * at least 1 descriptor unused to make sure 2012 * next_to_use != next_to_clean 2013 */ 2014 for (i = 0; i < adapter->num_rx_queues; i++) { 2015 struct igb_ring *ring = adapter->rx_ring[i]; 2016 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 2017 } 2018 } 2019 2020 /** 2021 * igb_power_up_link - Power up the phy/serdes link 2022 * @adapter: address of board private structure 2023 **/ 2024 void igb_power_up_link(struct igb_adapter *adapter) 2025 { 2026 igb_reset_phy(&adapter->hw); 2027 2028 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2029 igb_power_up_phy_copper(&adapter->hw); 2030 else 2031 igb_power_up_serdes_link_82575(&adapter->hw); 2032 2033 igb_setup_link(&adapter->hw); 2034 } 2035 2036 /** 2037 * igb_power_down_link - Power down the phy/serdes link 2038 * @adapter: address of board private structure 2039 */ 2040 static void igb_power_down_link(struct igb_adapter *adapter) 2041 { 2042 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2043 igb_power_down_phy_copper_82575(&adapter->hw); 2044 else 2045 igb_shutdown_serdes_link_82575(&adapter->hw); 2046 } 2047 2048 /** 2049 * igb_check_swap_media - Detect and switch function for Media Auto Sense 2050 * @adapter: address of the board private structure 2051 **/ 2052 static void igb_check_swap_media(struct igb_adapter *adapter) 2053 { 2054 struct e1000_hw *hw = &adapter->hw; 2055 u32 ctrl_ext, connsw; 2056 bool swap_now = false; 2057 2058 ctrl_ext = rd32(E1000_CTRL_EXT); 2059 connsw = rd32(E1000_CONNSW); 2060 2061 /* need to live swap if current media is copper and we have fiber/serdes 2062 * to go to. 2063 */ 2064 2065 if ((hw->phy.media_type == e1000_media_type_copper) && 2066 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2067 swap_now = true; 2068 } else if ((hw->phy.media_type != e1000_media_type_copper) && 2069 !(connsw & E1000_CONNSW_SERDESD)) { 2070 /* copper signal takes time to appear */ 2071 if (adapter->copper_tries < 4) { 2072 adapter->copper_tries++; 2073 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2074 wr32(E1000_CONNSW, connsw); 2075 return; 2076 } else { 2077 adapter->copper_tries = 0; 2078 if ((connsw & E1000_CONNSW_PHYSD) && 2079 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2080 swap_now = true; 2081 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2082 wr32(E1000_CONNSW, connsw); 2083 } 2084 } 2085 } 2086 2087 if (!swap_now) 2088 return; 2089 2090 switch (hw->phy.media_type) { 2091 case e1000_media_type_copper: 2092 netdev_info(adapter->netdev, 2093 "MAS: changing media to fiber/serdes\n"); 2094 ctrl_ext |= 2095 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2096 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2097 adapter->copper_tries = 0; 2098 break; 2099 case e1000_media_type_internal_serdes: 2100 case e1000_media_type_fiber: 2101 netdev_info(adapter->netdev, 2102 "MAS: changing media to copper\n"); 2103 ctrl_ext &= 2104 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2105 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2106 break; 2107 default: 2108 /* shouldn't get here during regular operation */ 2109 netdev_err(adapter->netdev, 2110 "AMS: Invalid media type found, returning\n"); 2111 break; 2112 } 2113 wr32(E1000_CTRL_EXT, ctrl_ext); 2114 } 2115 2116 /** 2117 * igb_up - Open the interface and prepare it to handle traffic 2118 * @adapter: board private structure 2119 **/ 2120 int igb_up(struct igb_adapter *adapter) 2121 { 2122 struct e1000_hw *hw = &adapter->hw; 2123 int i; 2124 2125 /* hardware has been reset, we need to reload some things */ 2126 igb_configure(adapter); 2127 2128 clear_bit(__IGB_DOWN, &adapter->state); 2129 2130 for (i = 0; i < adapter->num_q_vectors; i++) 2131 napi_enable(&(adapter->q_vector[i]->napi)); 2132 2133 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2134 igb_configure_msix(adapter); 2135 else 2136 igb_assign_vector(adapter->q_vector[0], 0); 2137 2138 /* Clear any pending interrupts. */ 2139 rd32(E1000_TSICR); 2140 rd32(E1000_ICR); 2141 igb_irq_enable(adapter); 2142 2143 /* notify VFs that reset has been completed */ 2144 if (adapter->vfs_allocated_count) { 2145 u32 reg_data = rd32(E1000_CTRL_EXT); 2146 2147 reg_data |= E1000_CTRL_EXT_PFRSTD; 2148 wr32(E1000_CTRL_EXT, reg_data); 2149 } 2150 2151 netif_tx_start_all_queues(adapter->netdev); 2152 2153 /* start the watchdog. */ 2154 hw->mac.get_link_status = 1; 2155 schedule_work(&adapter->watchdog_task); 2156 2157 if ((adapter->flags & IGB_FLAG_EEE) && 2158 (!hw->dev_spec._82575.eee_disable)) 2159 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2160 2161 return 0; 2162 } 2163 2164 void igb_down(struct igb_adapter *adapter) 2165 { 2166 struct net_device *netdev = adapter->netdev; 2167 struct e1000_hw *hw = &adapter->hw; 2168 u32 tctl, rctl; 2169 int i; 2170 2171 /* signal that we're down so the interrupt handler does not 2172 * reschedule our watchdog timer 2173 */ 2174 set_bit(__IGB_DOWN, &adapter->state); 2175 2176 /* disable receives in the hardware */ 2177 rctl = rd32(E1000_RCTL); 2178 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2179 /* flush and sleep below */ 2180 2181 igb_nfc_filter_exit(adapter); 2182 2183 netif_carrier_off(netdev); 2184 netif_tx_stop_all_queues(netdev); 2185 2186 /* disable transmits in the hardware */ 2187 tctl = rd32(E1000_TCTL); 2188 tctl &= ~E1000_TCTL_EN; 2189 wr32(E1000_TCTL, tctl); 2190 /* flush both disables and wait for them to finish */ 2191 wrfl(); 2192 usleep_range(10000, 11000); 2193 2194 igb_irq_disable(adapter); 2195 2196 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2197 2198 for (i = 0; i < adapter->num_q_vectors; i++) { 2199 if (adapter->q_vector[i]) { 2200 napi_synchronize(&adapter->q_vector[i]->napi); 2201 napi_disable(&adapter->q_vector[i]->napi); 2202 } 2203 } 2204 2205 del_timer_sync(&adapter->watchdog_timer); 2206 del_timer_sync(&adapter->phy_info_timer); 2207 2208 /* record the stats before reset*/ 2209 spin_lock(&adapter->stats64_lock); 2210 igb_update_stats(adapter); 2211 spin_unlock(&adapter->stats64_lock); 2212 2213 adapter->link_speed = 0; 2214 adapter->link_duplex = 0; 2215 2216 if (!pci_channel_offline(adapter->pdev)) 2217 igb_reset(adapter); 2218 2219 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2220 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2221 2222 igb_clean_all_tx_rings(adapter); 2223 igb_clean_all_rx_rings(adapter); 2224 #ifdef CONFIG_IGB_DCA 2225 2226 /* since we reset the hardware DCA settings were cleared */ 2227 igb_setup_dca(adapter); 2228 #endif 2229 } 2230 2231 void igb_reinit_locked(struct igb_adapter *adapter) 2232 { 2233 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2234 usleep_range(1000, 2000); 2235 igb_down(adapter); 2236 igb_up(adapter); 2237 clear_bit(__IGB_RESETTING, &adapter->state); 2238 } 2239 2240 /** igb_enable_mas - Media Autosense re-enable after swap 2241 * 2242 * @adapter: adapter struct 2243 **/ 2244 static void igb_enable_mas(struct igb_adapter *adapter) 2245 { 2246 struct e1000_hw *hw = &adapter->hw; 2247 u32 connsw = rd32(E1000_CONNSW); 2248 2249 /* configure for SerDes media detect */ 2250 if ((hw->phy.media_type == e1000_media_type_copper) && 2251 (!(connsw & E1000_CONNSW_SERDESD))) { 2252 connsw |= E1000_CONNSW_ENRGSRC; 2253 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2254 wr32(E1000_CONNSW, connsw); 2255 wrfl(); 2256 } 2257 } 2258 2259 void igb_reset(struct igb_adapter *adapter) 2260 { 2261 struct pci_dev *pdev = adapter->pdev; 2262 struct e1000_hw *hw = &adapter->hw; 2263 struct e1000_mac_info *mac = &hw->mac; 2264 struct e1000_fc_info *fc = &hw->fc; 2265 u32 pba, hwm; 2266 2267 /* Repartition Pba for greater than 9k mtu 2268 * To take effect CTRL.RST is required. 2269 */ 2270 switch (mac->type) { 2271 case e1000_i350: 2272 case e1000_i354: 2273 case e1000_82580: 2274 pba = rd32(E1000_RXPBS); 2275 pba = igb_rxpbs_adjust_82580(pba); 2276 break; 2277 case e1000_82576: 2278 pba = rd32(E1000_RXPBS); 2279 pba &= E1000_RXPBS_SIZE_MASK_82576; 2280 break; 2281 case e1000_82575: 2282 case e1000_i210: 2283 case e1000_i211: 2284 default: 2285 pba = E1000_PBA_34K; 2286 break; 2287 } 2288 2289 if (mac->type == e1000_82575) { 2290 u32 min_rx_space, min_tx_space, needed_tx_space; 2291 2292 /* write Rx PBA so that hardware can report correct Tx PBA */ 2293 wr32(E1000_PBA, pba); 2294 2295 /* To maintain wire speed transmits, the Tx FIFO should be 2296 * large enough to accommodate two full transmit packets, 2297 * rounded up to the next 1KB and expressed in KB. Likewise, 2298 * the Rx FIFO should be large enough to accommodate at least 2299 * one full receive packet and is similarly rounded up and 2300 * expressed in KB. 2301 */ 2302 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2303 2304 /* The Tx FIFO also stores 16 bytes of information about the Tx 2305 * but don't include Ethernet FCS because hardware appends it. 2306 * We only need to round down to the nearest 512 byte block 2307 * count since the value we care about is 2 frames, not 1. 2308 */ 2309 min_tx_space = adapter->max_frame_size; 2310 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2311 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2312 2313 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2314 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2315 2316 /* If current Tx allocation is less than the min Tx FIFO size, 2317 * and the min Tx FIFO size is less than the current Rx FIFO 2318 * allocation, take space away from current Rx allocation. 2319 */ 2320 if (needed_tx_space < pba) { 2321 pba -= needed_tx_space; 2322 2323 /* if short on Rx space, Rx wins and must trump Tx 2324 * adjustment 2325 */ 2326 if (pba < min_rx_space) 2327 pba = min_rx_space; 2328 } 2329 2330 /* adjust PBA for jumbo frames */ 2331 wr32(E1000_PBA, pba); 2332 } 2333 2334 /* flow control settings 2335 * The high water mark must be low enough to fit one full frame 2336 * after transmitting the pause frame. As such we must have enough 2337 * space to allow for us to complete our current transmit and then 2338 * receive the frame that is in progress from the link partner. 2339 * Set it to: 2340 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2341 */ 2342 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2343 2344 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2345 fc->low_water = fc->high_water - 16; 2346 fc->pause_time = 0xFFFF; 2347 fc->send_xon = 1; 2348 fc->current_mode = fc->requested_mode; 2349 2350 /* disable receive for all VFs and wait one second */ 2351 if (adapter->vfs_allocated_count) { 2352 int i; 2353 2354 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2355 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2356 2357 /* ping all the active vfs to let them know we are going down */ 2358 igb_ping_all_vfs(adapter); 2359 2360 /* disable transmits and receives */ 2361 wr32(E1000_VFRE, 0); 2362 wr32(E1000_VFTE, 0); 2363 } 2364 2365 /* Allow time for pending master requests to run */ 2366 hw->mac.ops.reset_hw(hw); 2367 wr32(E1000_WUC, 0); 2368 2369 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2370 /* need to resetup here after media swap */ 2371 adapter->ei.get_invariants(hw); 2372 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2373 } 2374 if ((mac->type == e1000_82575 || mac->type == e1000_i350) && 2375 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2376 igb_enable_mas(adapter); 2377 } 2378 if (hw->mac.ops.init_hw(hw)) 2379 dev_err(&pdev->dev, "Hardware Error\n"); 2380 2381 /* RAR registers were cleared during init_hw, clear mac table */ 2382 igb_flush_mac_table(adapter); 2383 __dev_uc_unsync(adapter->netdev, NULL); 2384 2385 /* Recover default RAR entry */ 2386 igb_set_default_mac_filter(adapter); 2387 2388 /* Flow control settings reset on hardware reset, so guarantee flow 2389 * control is off when forcing speed. 2390 */ 2391 if (!hw->mac.autoneg) 2392 igb_force_mac_fc(hw); 2393 2394 igb_init_dmac(adapter, pba); 2395 #ifdef CONFIG_IGB_HWMON 2396 /* Re-initialize the thermal sensor on i350 devices. */ 2397 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2398 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2399 /* If present, re-initialize the external thermal sensor 2400 * interface. 2401 */ 2402 if (adapter->ets) 2403 mac->ops.init_thermal_sensor_thresh(hw); 2404 } 2405 } 2406 #endif 2407 /* Re-establish EEE setting */ 2408 if (hw->phy.media_type == e1000_media_type_copper) { 2409 switch (mac->type) { 2410 case e1000_i350: 2411 case e1000_i210: 2412 case e1000_i211: 2413 igb_set_eee_i350(hw, true, true); 2414 break; 2415 case e1000_i354: 2416 igb_set_eee_i354(hw, true, true); 2417 break; 2418 default: 2419 break; 2420 } 2421 } 2422 if (!netif_running(adapter->netdev)) 2423 igb_power_down_link(adapter); 2424 2425 igb_update_mng_vlan(adapter); 2426 2427 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2428 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2429 2430 /* Re-enable PTP, where applicable. */ 2431 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2432 igb_ptp_reset(adapter); 2433 2434 igb_get_phy_info(hw); 2435 } 2436 2437 static netdev_features_t igb_fix_features(struct net_device *netdev, 2438 netdev_features_t features) 2439 { 2440 /* Since there is no support for separate Rx/Tx vlan accel 2441 * enable/disable make sure Tx flag is always in same state as Rx. 2442 */ 2443 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2444 features |= NETIF_F_HW_VLAN_CTAG_TX; 2445 else 2446 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2447 2448 return features; 2449 } 2450 2451 static int igb_set_features(struct net_device *netdev, 2452 netdev_features_t features) 2453 { 2454 netdev_features_t changed = netdev->features ^ features; 2455 struct igb_adapter *adapter = netdev_priv(netdev); 2456 2457 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2458 igb_vlan_mode(netdev, features); 2459 2460 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2461 return 0; 2462 2463 if (!(features & NETIF_F_NTUPLE)) { 2464 struct hlist_node *node2; 2465 struct igb_nfc_filter *rule; 2466 2467 spin_lock(&adapter->nfc_lock); 2468 hlist_for_each_entry_safe(rule, node2, 2469 &adapter->nfc_filter_list, nfc_node) { 2470 igb_erase_filter(adapter, rule); 2471 hlist_del(&rule->nfc_node); 2472 kfree(rule); 2473 } 2474 spin_unlock(&adapter->nfc_lock); 2475 adapter->nfc_filter_count = 0; 2476 } 2477 2478 netdev->features = features; 2479 2480 if (netif_running(netdev)) 2481 igb_reinit_locked(adapter); 2482 else 2483 igb_reset(adapter); 2484 2485 return 1; 2486 } 2487 2488 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2489 struct net_device *dev, 2490 const unsigned char *addr, u16 vid, 2491 u16 flags, 2492 struct netlink_ext_ack *extack) 2493 { 2494 /* guarantee we can provide a unique filter for the unicast address */ 2495 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2496 struct igb_adapter *adapter = netdev_priv(dev); 2497 int vfn = adapter->vfs_allocated_count; 2498 2499 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2500 return -ENOMEM; 2501 } 2502 2503 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2504 } 2505 2506 #define IGB_MAX_MAC_HDR_LEN 127 2507 #define IGB_MAX_NETWORK_HDR_LEN 511 2508 2509 static netdev_features_t 2510 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2511 netdev_features_t features) 2512 { 2513 unsigned int network_hdr_len, mac_hdr_len; 2514 2515 /* Make certain the headers can be described by a context descriptor */ 2516 mac_hdr_len = skb_network_header(skb) - skb->data; 2517 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2518 return features & ~(NETIF_F_HW_CSUM | 2519 NETIF_F_SCTP_CRC | 2520 NETIF_F_GSO_UDP_L4 | 2521 NETIF_F_HW_VLAN_CTAG_TX | 2522 NETIF_F_TSO | 2523 NETIF_F_TSO6); 2524 2525 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2526 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2527 return features & ~(NETIF_F_HW_CSUM | 2528 NETIF_F_SCTP_CRC | 2529 NETIF_F_GSO_UDP_L4 | 2530 NETIF_F_TSO | 2531 NETIF_F_TSO6); 2532 2533 /* We can only support IPV4 TSO in tunnels if we can mangle the 2534 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2535 */ 2536 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2537 features &= ~NETIF_F_TSO; 2538 2539 return features; 2540 } 2541 2542 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2543 { 2544 if (!is_fqtss_enabled(adapter)) { 2545 enable_fqtss(adapter, true); 2546 return; 2547 } 2548 2549 igb_config_tx_modes(adapter, queue); 2550 2551 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2552 enable_fqtss(adapter, false); 2553 } 2554 2555 static int igb_offload_cbs(struct igb_adapter *adapter, 2556 struct tc_cbs_qopt_offload *qopt) 2557 { 2558 struct e1000_hw *hw = &adapter->hw; 2559 int err; 2560 2561 /* CBS offloading is only supported by i210 controller. */ 2562 if (hw->mac.type != e1000_i210) 2563 return -EOPNOTSUPP; 2564 2565 /* CBS offloading is only supported by queue 0 and queue 1. */ 2566 if (qopt->queue < 0 || qopt->queue > 1) 2567 return -EINVAL; 2568 2569 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2570 qopt->idleslope, qopt->sendslope, 2571 qopt->hicredit, qopt->locredit); 2572 if (err) 2573 return err; 2574 2575 igb_offload_apply(adapter, qopt->queue); 2576 2577 return 0; 2578 } 2579 2580 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2581 #define VLAN_PRIO_FULL_MASK (0x07) 2582 2583 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2584 struct flow_cls_offload *f, 2585 int traffic_class, 2586 struct igb_nfc_filter *input) 2587 { 2588 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2589 struct flow_dissector *dissector = rule->match.dissector; 2590 struct netlink_ext_ack *extack = f->common.extack; 2591 2592 if (dissector->used_keys & 2593 ~(BIT(FLOW_DISSECTOR_KEY_BASIC) | 2594 BIT(FLOW_DISSECTOR_KEY_CONTROL) | 2595 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2596 BIT(FLOW_DISSECTOR_KEY_VLAN))) { 2597 NL_SET_ERR_MSG_MOD(extack, 2598 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2599 return -EOPNOTSUPP; 2600 } 2601 2602 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2603 struct flow_match_eth_addrs match; 2604 2605 flow_rule_match_eth_addrs(rule, &match); 2606 if (!is_zero_ether_addr(match.mask->dst)) { 2607 if (!is_broadcast_ether_addr(match.mask->dst)) { 2608 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2609 return -EINVAL; 2610 } 2611 2612 input->filter.match_flags |= 2613 IGB_FILTER_FLAG_DST_MAC_ADDR; 2614 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2615 } 2616 2617 if (!is_zero_ether_addr(match.mask->src)) { 2618 if (!is_broadcast_ether_addr(match.mask->src)) { 2619 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2620 return -EINVAL; 2621 } 2622 2623 input->filter.match_flags |= 2624 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2625 ether_addr_copy(input->filter.src_addr, match.key->src); 2626 } 2627 } 2628 2629 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2630 struct flow_match_basic match; 2631 2632 flow_rule_match_basic(rule, &match); 2633 if (match.mask->n_proto) { 2634 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2635 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2636 return -EINVAL; 2637 } 2638 2639 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2640 input->filter.etype = match.key->n_proto; 2641 } 2642 } 2643 2644 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2645 struct flow_match_vlan match; 2646 2647 flow_rule_match_vlan(rule, &match); 2648 if (match.mask->vlan_priority) { 2649 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2650 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2651 return -EINVAL; 2652 } 2653 2654 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2655 input->filter.vlan_tci = 2656 (__force __be16)match.key->vlan_priority; 2657 } 2658 } 2659 2660 input->action = traffic_class; 2661 input->cookie = f->cookie; 2662 2663 return 0; 2664 } 2665 2666 static int igb_configure_clsflower(struct igb_adapter *adapter, 2667 struct flow_cls_offload *cls_flower) 2668 { 2669 struct netlink_ext_ack *extack = cls_flower->common.extack; 2670 struct igb_nfc_filter *filter, *f; 2671 int err, tc; 2672 2673 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2674 if (tc < 0) { 2675 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2676 return -EINVAL; 2677 } 2678 2679 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2680 if (!filter) 2681 return -ENOMEM; 2682 2683 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2684 if (err < 0) 2685 goto err_parse; 2686 2687 spin_lock(&adapter->nfc_lock); 2688 2689 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2690 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2691 err = -EEXIST; 2692 NL_SET_ERR_MSG_MOD(extack, 2693 "This filter is already set in ethtool"); 2694 goto err_locked; 2695 } 2696 } 2697 2698 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2699 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2700 err = -EEXIST; 2701 NL_SET_ERR_MSG_MOD(extack, 2702 "This filter is already set in cls_flower"); 2703 goto err_locked; 2704 } 2705 } 2706 2707 err = igb_add_filter(adapter, filter); 2708 if (err < 0) { 2709 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2710 goto err_locked; 2711 } 2712 2713 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2714 2715 spin_unlock(&adapter->nfc_lock); 2716 2717 return 0; 2718 2719 err_locked: 2720 spin_unlock(&adapter->nfc_lock); 2721 2722 err_parse: 2723 kfree(filter); 2724 2725 return err; 2726 } 2727 2728 static int igb_delete_clsflower(struct igb_adapter *adapter, 2729 struct flow_cls_offload *cls_flower) 2730 { 2731 struct igb_nfc_filter *filter; 2732 int err; 2733 2734 spin_lock(&adapter->nfc_lock); 2735 2736 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2737 if (filter->cookie == cls_flower->cookie) 2738 break; 2739 2740 if (!filter) { 2741 err = -ENOENT; 2742 goto out; 2743 } 2744 2745 err = igb_erase_filter(adapter, filter); 2746 if (err < 0) 2747 goto out; 2748 2749 hlist_del(&filter->nfc_node); 2750 kfree(filter); 2751 2752 out: 2753 spin_unlock(&adapter->nfc_lock); 2754 2755 return err; 2756 } 2757 2758 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2759 struct flow_cls_offload *cls_flower) 2760 { 2761 switch (cls_flower->command) { 2762 case FLOW_CLS_REPLACE: 2763 return igb_configure_clsflower(adapter, cls_flower); 2764 case FLOW_CLS_DESTROY: 2765 return igb_delete_clsflower(adapter, cls_flower); 2766 case FLOW_CLS_STATS: 2767 return -EOPNOTSUPP; 2768 default: 2769 return -EOPNOTSUPP; 2770 } 2771 } 2772 2773 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2774 void *cb_priv) 2775 { 2776 struct igb_adapter *adapter = cb_priv; 2777 2778 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2779 return -EOPNOTSUPP; 2780 2781 switch (type) { 2782 case TC_SETUP_CLSFLOWER: 2783 return igb_setup_tc_cls_flower(adapter, type_data); 2784 2785 default: 2786 return -EOPNOTSUPP; 2787 } 2788 } 2789 2790 static int igb_offload_txtime(struct igb_adapter *adapter, 2791 struct tc_etf_qopt_offload *qopt) 2792 { 2793 struct e1000_hw *hw = &adapter->hw; 2794 int err; 2795 2796 /* Launchtime offloading is only supported by i210 controller. */ 2797 if (hw->mac.type != e1000_i210) 2798 return -EOPNOTSUPP; 2799 2800 /* Launchtime offloading is only supported by queues 0 and 1. */ 2801 if (qopt->queue < 0 || qopt->queue > 1) 2802 return -EINVAL; 2803 2804 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2805 if (err) 2806 return err; 2807 2808 igb_offload_apply(adapter, qopt->queue); 2809 2810 return 0; 2811 } 2812 2813 static int igb_tc_query_caps(struct igb_adapter *adapter, 2814 struct tc_query_caps_base *base) 2815 { 2816 switch (base->type) { 2817 case TC_SETUP_QDISC_TAPRIO: { 2818 struct tc_taprio_caps *caps = base->caps; 2819 2820 caps->broken_mqprio = true; 2821 2822 return 0; 2823 } 2824 default: 2825 return -EOPNOTSUPP; 2826 } 2827 } 2828 2829 static LIST_HEAD(igb_block_cb_list); 2830 2831 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2832 void *type_data) 2833 { 2834 struct igb_adapter *adapter = netdev_priv(dev); 2835 2836 switch (type) { 2837 case TC_QUERY_CAPS: 2838 return igb_tc_query_caps(adapter, type_data); 2839 case TC_SETUP_QDISC_CBS: 2840 return igb_offload_cbs(adapter, type_data); 2841 case TC_SETUP_BLOCK: 2842 return flow_block_cb_setup_simple(type_data, 2843 &igb_block_cb_list, 2844 igb_setup_tc_block_cb, 2845 adapter, adapter, true); 2846 2847 case TC_SETUP_QDISC_ETF: 2848 return igb_offload_txtime(adapter, type_data); 2849 2850 default: 2851 return -EOPNOTSUPP; 2852 } 2853 } 2854 2855 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf) 2856 { 2857 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD; 2858 struct igb_adapter *adapter = netdev_priv(dev); 2859 struct bpf_prog *prog = bpf->prog, *old_prog; 2860 bool running = netif_running(dev); 2861 bool need_reset; 2862 2863 /* verify igb ring attributes are sufficient for XDP */ 2864 for (i = 0; i < adapter->num_rx_queues; i++) { 2865 struct igb_ring *ring = adapter->rx_ring[i]; 2866 2867 if (frame_size > igb_rx_bufsz(ring)) { 2868 NL_SET_ERR_MSG_MOD(bpf->extack, 2869 "The RX buffer size is too small for the frame size"); 2870 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n", 2871 igb_rx_bufsz(ring), frame_size); 2872 return -EINVAL; 2873 } 2874 } 2875 2876 old_prog = xchg(&adapter->xdp_prog, prog); 2877 need_reset = (!!prog != !!old_prog); 2878 2879 /* device is up and bpf is added/removed, must setup the RX queues */ 2880 if (need_reset && running) { 2881 igb_close(dev); 2882 } else { 2883 for (i = 0; i < adapter->num_rx_queues; i++) 2884 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 2885 adapter->xdp_prog); 2886 } 2887 2888 if (old_prog) 2889 bpf_prog_put(old_prog); 2890 2891 /* bpf is just replaced, RXQ and MTU are already setup */ 2892 if (!need_reset) { 2893 return 0; 2894 } else { 2895 if (prog) 2896 xdp_features_set_redirect_target(dev, true); 2897 else 2898 xdp_features_clear_redirect_target(dev); 2899 } 2900 2901 if (running) 2902 igb_open(dev); 2903 2904 return 0; 2905 } 2906 2907 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp) 2908 { 2909 switch (xdp->command) { 2910 case XDP_SETUP_PROG: 2911 return igb_xdp_setup(dev, xdp); 2912 default: 2913 return -EINVAL; 2914 } 2915 } 2916 2917 static void igb_xdp_ring_update_tail(struct igb_ring *ring) 2918 { 2919 /* Force memory writes to complete before letting h/w know there 2920 * are new descriptors to fetch. 2921 */ 2922 wmb(); 2923 writel(ring->next_to_use, ring->tail); 2924 } 2925 2926 static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter) 2927 { 2928 unsigned int r_idx = smp_processor_id(); 2929 2930 if (r_idx >= adapter->num_tx_queues) 2931 r_idx = r_idx % adapter->num_tx_queues; 2932 2933 return adapter->tx_ring[r_idx]; 2934 } 2935 2936 static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp) 2937 { 2938 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2939 int cpu = smp_processor_id(); 2940 struct igb_ring *tx_ring; 2941 struct netdev_queue *nq; 2942 u32 ret; 2943 2944 if (unlikely(!xdpf)) 2945 return IGB_XDP_CONSUMED; 2946 2947 /* During program transitions its possible adapter->xdp_prog is assigned 2948 * but ring has not been configured yet. In this case simply abort xmit. 2949 */ 2950 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2951 if (unlikely(!tx_ring)) 2952 return IGB_XDP_CONSUMED; 2953 2954 nq = txring_txq(tx_ring); 2955 __netif_tx_lock(nq, cpu); 2956 /* Avoid transmit queue timeout since we share it with the slow path */ 2957 txq_trans_cond_update(nq); 2958 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2959 __netif_tx_unlock(nq); 2960 2961 return ret; 2962 } 2963 2964 static int igb_xdp_xmit(struct net_device *dev, int n, 2965 struct xdp_frame **frames, u32 flags) 2966 { 2967 struct igb_adapter *adapter = netdev_priv(dev); 2968 int cpu = smp_processor_id(); 2969 struct igb_ring *tx_ring; 2970 struct netdev_queue *nq; 2971 int nxmit = 0; 2972 int i; 2973 2974 if (unlikely(test_bit(__IGB_DOWN, &adapter->state))) 2975 return -ENETDOWN; 2976 2977 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2978 return -EINVAL; 2979 2980 /* During program transitions its possible adapter->xdp_prog is assigned 2981 * but ring has not been configured yet. In this case simply abort xmit. 2982 */ 2983 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2984 if (unlikely(!tx_ring)) 2985 return -ENXIO; 2986 2987 nq = txring_txq(tx_ring); 2988 __netif_tx_lock(nq, cpu); 2989 2990 /* Avoid transmit queue timeout since we share it with the slow path */ 2991 txq_trans_cond_update(nq); 2992 2993 for (i = 0; i < n; i++) { 2994 struct xdp_frame *xdpf = frames[i]; 2995 int err; 2996 2997 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2998 if (err != IGB_XDP_TX) 2999 break; 3000 nxmit++; 3001 } 3002 3003 __netif_tx_unlock(nq); 3004 3005 if (unlikely(flags & XDP_XMIT_FLUSH)) 3006 igb_xdp_ring_update_tail(tx_ring); 3007 3008 return nxmit; 3009 } 3010 3011 static const struct net_device_ops igb_netdev_ops = { 3012 .ndo_open = igb_open, 3013 .ndo_stop = igb_close, 3014 .ndo_start_xmit = igb_xmit_frame, 3015 .ndo_get_stats64 = igb_get_stats64, 3016 .ndo_set_rx_mode = igb_set_rx_mode, 3017 .ndo_set_mac_address = igb_set_mac, 3018 .ndo_change_mtu = igb_change_mtu, 3019 .ndo_eth_ioctl = igb_ioctl, 3020 .ndo_tx_timeout = igb_tx_timeout, 3021 .ndo_validate_addr = eth_validate_addr, 3022 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 3023 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 3024 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 3025 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 3026 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 3027 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 3028 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 3029 .ndo_get_vf_config = igb_ndo_get_vf_config, 3030 .ndo_fix_features = igb_fix_features, 3031 .ndo_set_features = igb_set_features, 3032 .ndo_fdb_add = igb_ndo_fdb_add, 3033 .ndo_features_check = igb_features_check, 3034 .ndo_setup_tc = igb_setup_tc, 3035 .ndo_bpf = igb_xdp, 3036 .ndo_xdp_xmit = igb_xdp_xmit, 3037 }; 3038 3039 /** 3040 * igb_set_fw_version - Configure version string for ethtool 3041 * @adapter: adapter struct 3042 **/ 3043 void igb_set_fw_version(struct igb_adapter *adapter) 3044 { 3045 struct e1000_hw *hw = &adapter->hw; 3046 struct e1000_fw_version fw; 3047 3048 igb_get_fw_version(hw, &fw); 3049 3050 switch (hw->mac.type) { 3051 case e1000_i210: 3052 case e1000_i211: 3053 if (!(igb_get_flash_presence_i210(hw))) { 3054 snprintf(adapter->fw_version, 3055 sizeof(adapter->fw_version), 3056 "%2d.%2d-%d", 3057 fw.invm_major, fw.invm_minor, 3058 fw.invm_img_type); 3059 break; 3060 } 3061 fallthrough; 3062 default: 3063 /* if option is rom valid, display its version too */ 3064 if (fw.or_valid) { 3065 snprintf(adapter->fw_version, 3066 sizeof(adapter->fw_version), 3067 "%d.%d, 0x%08x, %d.%d.%d", 3068 fw.eep_major, fw.eep_minor, fw.etrack_id, 3069 fw.or_major, fw.or_build, fw.or_patch); 3070 /* no option rom */ 3071 } else if (fw.etrack_id != 0X0000) { 3072 snprintf(adapter->fw_version, 3073 sizeof(adapter->fw_version), 3074 "%d.%d, 0x%08x", 3075 fw.eep_major, fw.eep_minor, fw.etrack_id); 3076 } else { 3077 snprintf(adapter->fw_version, 3078 sizeof(adapter->fw_version), 3079 "%d.%d.%d", 3080 fw.eep_major, fw.eep_minor, fw.eep_build); 3081 } 3082 break; 3083 } 3084 } 3085 3086 /** 3087 * igb_init_mas - init Media Autosense feature if enabled in the NVM 3088 * 3089 * @adapter: adapter struct 3090 **/ 3091 static void igb_init_mas(struct igb_adapter *adapter) 3092 { 3093 struct e1000_hw *hw = &adapter->hw; 3094 u16 eeprom_data; 3095 3096 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 3097 switch (hw->bus.func) { 3098 case E1000_FUNC_0: 3099 if (eeprom_data & IGB_MAS_ENABLE_0) { 3100 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3101 netdev_info(adapter->netdev, 3102 "MAS: Enabling Media Autosense for port %d\n", 3103 hw->bus.func); 3104 } 3105 break; 3106 case E1000_FUNC_1: 3107 if (eeprom_data & IGB_MAS_ENABLE_1) { 3108 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3109 netdev_info(adapter->netdev, 3110 "MAS: Enabling Media Autosense for port %d\n", 3111 hw->bus.func); 3112 } 3113 break; 3114 case E1000_FUNC_2: 3115 if (eeprom_data & IGB_MAS_ENABLE_2) { 3116 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3117 netdev_info(adapter->netdev, 3118 "MAS: Enabling Media Autosense for port %d\n", 3119 hw->bus.func); 3120 } 3121 break; 3122 case E1000_FUNC_3: 3123 if (eeprom_data & IGB_MAS_ENABLE_3) { 3124 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3125 netdev_info(adapter->netdev, 3126 "MAS: Enabling Media Autosense for port %d\n", 3127 hw->bus.func); 3128 } 3129 break; 3130 default: 3131 /* Shouldn't get here */ 3132 netdev_err(adapter->netdev, 3133 "MAS: Invalid port configuration, returning\n"); 3134 break; 3135 } 3136 } 3137 3138 /** 3139 * igb_init_i2c - Init I2C interface 3140 * @adapter: pointer to adapter structure 3141 **/ 3142 static s32 igb_init_i2c(struct igb_adapter *adapter) 3143 { 3144 struct e1000_hw *hw = &adapter->hw; 3145 s32 status = 0; 3146 s32 i2cctl; 3147 3148 /* I2C interface supported on i350 devices */ 3149 if (adapter->hw.mac.type != e1000_i350) 3150 return 0; 3151 3152 i2cctl = rd32(E1000_I2CPARAMS); 3153 i2cctl |= E1000_I2CBB_EN 3154 | E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N 3155 | E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N; 3156 wr32(E1000_I2CPARAMS, i2cctl); 3157 wrfl(); 3158 3159 /* Initialize the i2c bus which is controlled by the registers. 3160 * This bus will use the i2c_algo_bit structure that implements 3161 * the protocol through toggling of the 4 bits in the register. 3162 */ 3163 adapter->i2c_adap.owner = THIS_MODULE; 3164 adapter->i2c_algo = igb_i2c_algo; 3165 adapter->i2c_algo.data = adapter; 3166 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 3167 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 3168 strscpy(adapter->i2c_adap.name, "igb BB", 3169 sizeof(adapter->i2c_adap.name)); 3170 status = i2c_bit_add_bus(&adapter->i2c_adap); 3171 return status; 3172 } 3173 3174 /** 3175 * igb_probe - Device Initialization Routine 3176 * @pdev: PCI device information struct 3177 * @ent: entry in igb_pci_tbl 3178 * 3179 * Returns 0 on success, negative on failure 3180 * 3181 * igb_probe initializes an adapter identified by a pci_dev structure. 3182 * The OS initialization, configuring of the adapter private structure, 3183 * and a hardware reset occur. 3184 **/ 3185 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3186 { 3187 struct net_device *netdev; 3188 struct igb_adapter *adapter; 3189 struct e1000_hw *hw; 3190 u16 eeprom_data = 0; 3191 s32 ret_val; 3192 static int global_quad_port_a; /* global quad port a indication */ 3193 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3194 u8 part_str[E1000_PBANUM_LENGTH]; 3195 int err; 3196 3197 /* Catch broken hardware that put the wrong VF device ID in 3198 * the PCIe SR-IOV capability. 3199 */ 3200 if (pdev->is_virtfn) { 3201 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n", 3202 pci_name(pdev), pdev->vendor, pdev->device); 3203 return -EINVAL; 3204 } 3205 3206 err = pci_enable_device_mem(pdev); 3207 if (err) 3208 return err; 3209 3210 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3211 if (err) { 3212 dev_err(&pdev->dev, 3213 "No usable DMA configuration, aborting\n"); 3214 goto err_dma; 3215 } 3216 3217 err = pci_request_mem_regions(pdev, igb_driver_name); 3218 if (err) 3219 goto err_pci_reg; 3220 3221 pci_set_master(pdev); 3222 pci_save_state(pdev); 3223 3224 err = -ENOMEM; 3225 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3226 IGB_MAX_TX_QUEUES); 3227 if (!netdev) 3228 goto err_alloc_etherdev; 3229 3230 SET_NETDEV_DEV(netdev, &pdev->dev); 3231 3232 pci_set_drvdata(pdev, netdev); 3233 adapter = netdev_priv(netdev); 3234 adapter->netdev = netdev; 3235 adapter->pdev = pdev; 3236 hw = &adapter->hw; 3237 hw->back = adapter; 3238 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3239 3240 err = -EIO; 3241 adapter->io_addr = pci_iomap(pdev, 0, 0); 3242 if (!adapter->io_addr) 3243 goto err_ioremap; 3244 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3245 hw->hw_addr = adapter->io_addr; 3246 3247 netdev->netdev_ops = &igb_netdev_ops; 3248 igb_set_ethtool_ops(netdev); 3249 netdev->watchdog_timeo = 5 * HZ; 3250 3251 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 3252 3253 netdev->mem_start = pci_resource_start(pdev, 0); 3254 netdev->mem_end = pci_resource_end(pdev, 0); 3255 3256 /* PCI config space info */ 3257 hw->vendor_id = pdev->vendor; 3258 hw->device_id = pdev->device; 3259 hw->revision_id = pdev->revision; 3260 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3261 hw->subsystem_device_id = pdev->subsystem_device; 3262 3263 /* Copy the default MAC, PHY and NVM function pointers */ 3264 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3265 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3266 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3267 /* Initialize skew-specific constants */ 3268 err = ei->get_invariants(hw); 3269 if (err) 3270 goto err_sw_init; 3271 3272 /* setup the private structure */ 3273 err = igb_sw_init(adapter); 3274 if (err) 3275 goto err_sw_init; 3276 3277 igb_get_bus_info_pcie(hw); 3278 3279 hw->phy.autoneg_wait_to_complete = false; 3280 3281 /* Copper options */ 3282 if (hw->phy.media_type == e1000_media_type_copper) { 3283 hw->phy.mdix = AUTO_ALL_MODES; 3284 hw->phy.disable_polarity_correction = false; 3285 hw->phy.ms_type = e1000_ms_hw_default; 3286 } 3287 3288 if (igb_check_reset_block(hw)) 3289 dev_info(&pdev->dev, 3290 "PHY reset is blocked due to SOL/IDER session.\n"); 3291 3292 /* features is initialized to 0 in allocation, it might have bits 3293 * set by igb_sw_init so we should use an or instead of an 3294 * assignment. 3295 */ 3296 netdev->features |= NETIF_F_SG | 3297 NETIF_F_TSO | 3298 NETIF_F_TSO6 | 3299 NETIF_F_RXHASH | 3300 NETIF_F_RXCSUM | 3301 NETIF_F_HW_CSUM; 3302 3303 if (hw->mac.type >= e1000_82576) 3304 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 3305 3306 if (hw->mac.type >= e1000_i350) 3307 netdev->features |= NETIF_F_HW_TC; 3308 3309 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3310 NETIF_F_GSO_GRE_CSUM | \ 3311 NETIF_F_GSO_IPXIP4 | \ 3312 NETIF_F_GSO_IPXIP6 | \ 3313 NETIF_F_GSO_UDP_TUNNEL | \ 3314 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3315 3316 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3317 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3318 3319 /* copy netdev features into list of user selectable features */ 3320 netdev->hw_features |= netdev->features | 3321 NETIF_F_HW_VLAN_CTAG_RX | 3322 NETIF_F_HW_VLAN_CTAG_TX | 3323 NETIF_F_RXALL; 3324 3325 if (hw->mac.type >= e1000_i350) 3326 netdev->hw_features |= NETIF_F_NTUPLE; 3327 3328 netdev->features |= NETIF_F_HIGHDMA; 3329 3330 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3331 netdev->mpls_features |= NETIF_F_HW_CSUM; 3332 netdev->hw_enc_features |= netdev->vlan_features; 3333 3334 /* set this bit last since it cannot be part of vlan_features */ 3335 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3336 NETIF_F_HW_VLAN_CTAG_RX | 3337 NETIF_F_HW_VLAN_CTAG_TX; 3338 3339 netdev->priv_flags |= IFF_SUPP_NOFCS; 3340 3341 netdev->priv_flags |= IFF_UNICAST_FLT; 3342 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT; 3343 3344 /* MTU range: 68 - 9216 */ 3345 netdev->min_mtu = ETH_MIN_MTU; 3346 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3347 3348 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3349 3350 /* before reading the NVM, reset the controller to put the device in a 3351 * known good starting state 3352 */ 3353 hw->mac.ops.reset_hw(hw); 3354 3355 /* make sure the NVM is good , i211/i210 parts can have special NVM 3356 * that doesn't contain a checksum 3357 */ 3358 switch (hw->mac.type) { 3359 case e1000_i210: 3360 case e1000_i211: 3361 if (igb_get_flash_presence_i210(hw)) { 3362 if (hw->nvm.ops.validate(hw) < 0) { 3363 dev_err(&pdev->dev, 3364 "The NVM Checksum Is Not Valid\n"); 3365 err = -EIO; 3366 goto err_eeprom; 3367 } 3368 } 3369 break; 3370 default: 3371 if (hw->nvm.ops.validate(hw) < 0) { 3372 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3373 err = -EIO; 3374 goto err_eeprom; 3375 } 3376 break; 3377 } 3378 3379 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3380 /* copy the MAC address out of the NVM */ 3381 if (hw->mac.ops.read_mac_addr(hw)) 3382 dev_err(&pdev->dev, "NVM Read Error\n"); 3383 } 3384 3385 eth_hw_addr_set(netdev, hw->mac.addr); 3386 3387 if (!is_valid_ether_addr(netdev->dev_addr)) { 3388 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3389 err = -EIO; 3390 goto err_eeprom; 3391 } 3392 3393 igb_set_default_mac_filter(adapter); 3394 3395 /* get firmware version for ethtool -i */ 3396 igb_set_fw_version(adapter); 3397 3398 /* configure RXPBSIZE and TXPBSIZE */ 3399 if (hw->mac.type == e1000_i210) { 3400 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3401 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3402 } 3403 3404 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3405 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3406 3407 INIT_WORK(&adapter->reset_task, igb_reset_task); 3408 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3409 3410 /* Initialize link properties that are user-changeable */ 3411 adapter->fc_autoneg = true; 3412 hw->mac.autoneg = true; 3413 hw->phy.autoneg_advertised = 0x2f; 3414 3415 hw->fc.requested_mode = e1000_fc_default; 3416 hw->fc.current_mode = e1000_fc_default; 3417 3418 igb_validate_mdi_setting(hw); 3419 3420 /* By default, support wake on port A */ 3421 if (hw->bus.func == 0) 3422 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3423 3424 /* Check the NVM for wake support on non-port A ports */ 3425 if (hw->mac.type >= e1000_82580) 3426 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3427 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3428 &eeprom_data); 3429 else if (hw->bus.func == 1) 3430 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3431 3432 if (eeprom_data & IGB_EEPROM_APME) 3433 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3434 3435 /* now that we have the eeprom settings, apply the special cases where 3436 * the eeprom may be wrong or the board simply won't support wake on 3437 * lan on a particular port 3438 */ 3439 switch (pdev->device) { 3440 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3441 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3442 break; 3443 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3444 case E1000_DEV_ID_82576_FIBER: 3445 case E1000_DEV_ID_82576_SERDES: 3446 /* Wake events only supported on port A for dual fiber 3447 * regardless of eeprom setting 3448 */ 3449 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3450 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3451 break; 3452 case E1000_DEV_ID_82576_QUAD_COPPER: 3453 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3454 /* if quad port adapter, disable WoL on all but port A */ 3455 if (global_quad_port_a != 0) 3456 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3457 else 3458 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3459 /* Reset for multiple quad port adapters */ 3460 if (++global_quad_port_a == 4) 3461 global_quad_port_a = 0; 3462 break; 3463 default: 3464 /* If the device can't wake, don't set software support */ 3465 if (!device_can_wakeup(&adapter->pdev->dev)) 3466 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3467 } 3468 3469 /* initialize the wol settings based on the eeprom settings */ 3470 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3471 adapter->wol |= E1000_WUFC_MAG; 3472 3473 /* Some vendors want WoL disabled by default, but still supported */ 3474 if ((hw->mac.type == e1000_i350) && 3475 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3476 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3477 adapter->wol = 0; 3478 } 3479 3480 /* Some vendors want the ability to Use the EEPROM setting as 3481 * enable/disable only, and not for capability 3482 */ 3483 if (((hw->mac.type == e1000_i350) || 3484 (hw->mac.type == e1000_i354)) && 3485 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3486 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3487 adapter->wol = 0; 3488 } 3489 if (hw->mac.type == e1000_i350) { 3490 if (((pdev->subsystem_device == 0x5001) || 3491 (pdev->subsystem_device == 0x5002)) && 3492 (hw->bus.func == 0)) { 3493 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3494 adapter->wol = 0; 3495 } 3496 if (pdev->subsystem_device == 0x1F52) 3497 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3498 } 3499 3500 device_set_wakeup_enable(&adapter->pdev->dev, 3501 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3502 3503 /* reset the hardware with the new settings */ 3504 igb_reset(adapter); 3505 3506 /* Init the I2C interface */ 3507 err = igb_init_i2c(adapter); 3508 if (err) { 3509 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3510 goto err_eeprom; 3511 } 3512 3513 /* let the f/w know that the h/w is now under the control of the 3514 * driver. 3515 */ 3516 igb_get_hw_control(adapter); 3517 3518 strcpy(netdev->name, "eth%d"); 3519 err = register_netdev(netdev); 3520 if (err) 3521 goto err_register; 3522 3523 /* carrier off reporting is important to ethtool even BEFORE open */ 3524 netif_carrier_off(netdev); 3525 3526 #ifdef CONFIG_IGB_DCA 3527 if (dca_add_requester(&pdev->dev) == 0) { 3528 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3529 dev_info(&pdev->dev, "DCA enabled\n"); 3530 igb_setup_dca(adapter); 3531 } 3532 3533 #endif 3534 #ifdef CONFIG_IGB_HWMON 3535 /* Initialize the thermal sensor on i350 devices. */ 3536 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3537 u16 ets_word; 3538 3539 /* Read the NVM to determine if this i350 device supports an 3540 * external thermal sensor. 3541 */ 3542 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3543 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3544 adapter->ets = true; 3545 else 3546 adapter->ets = false; 3547 if (igb_sysfs_init(adapter)) 3548 dev_err(&pdev->dev, 3549 "failed to allocate sysfs resources\n"); 3550 } else { 3551 adapter->ets = false; 3552 } 3553 #endif 3554 /* Check if Media Autosense is enabled */ 3555 adapter->ei = *ei; 3556 if (hw->dev_spec._82575.mas_capable) 3557 igb_init_mas(adapter); 3558 3559 /* do hw tstamp init after resetting */ 3560 igb_ptp_init(adapter); 3561 3562 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3563 /* print bus type/speed/width info, not applicable to i354 */ 3564 if (hw->mac.type != e1000_i354) { 3565 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3566 netdev->name, 3567 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3568 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3569 "unknown"), 3570 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3571 "Width x4" : 3572 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3573 "Width x2" : 3574 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3575 "Width x1" : "unknown"), netdev->dev_addr); 3576 } 3577 3578 if ((hw->mac.type == e1000_82576 && 3579 rd32(E1000_EECD) & E1000_EECD_PRES) || 3580 (hw->mac.type >= e1000_i210 || 3581 igb_get_flash_presence_i210(hw))) { 3582 ret_val = igb_read_part_string(hw, part_str, 3583 E1000_PBANUM_LENGTH); 3584 } else { 3585 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3586 } 3587 3588 if (ret_val) 3589 strcpy(part_str, "Unknown"); 3590 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3591 dev_info(&pdev->dev, 3592 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3593 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3594 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3595 adapter->num_rx_queues, adapter->num_tx_queues); 3596 if (hw->phy.media_type == e1000_media_type_copper) { 3597 switch (hw->mac.type) { 3598 case e1000_i350: 3599 case e1000_i210: 3600 case e1000_i211: 3601 /* Enable EEE for internal copper PHY devices */ 3602 err = igb_set_eee_i350(hw, true, true); 3603 if ((!err) && 3604 (!hw->dev_spec._82575.eee_disable)) { 3605 adapter->eee_advert = 3606 MDIO_EEE_100TX | MDIO_EEE_1000T; 3607 adapter->flags |= IGB_FLAG_EEE; 3608 } 3609 break; 3610 case e1000_i354: 3611 if ((rd32(E1000_CTRL_EXT) & 3612 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3613 err = igb_set_eee_i354(hw, true, true); 3614 if ((!err) && 3615 (!hw->dev_spec._82575.eee_disable)) { 3616 adapter->eee_advert = 3617 MDIO_EEE_100TX | MDIO_EEE_1000T; 3618 adapter->flags |= IGB_FLAG_EEE; 3619 } 3620 } 3621 break; 3622 default: 3623 break; 3624 } 3625 } 3626 3627 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 3628 3629 pm_runtime_put_noidle(&pdev->dev); 3630 return 0; 3631 3632 err_register: 3633 igb_release_hw_control(adapter); 3634 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3635 err_eeprom: 3636 if (!igb_check_reset_block(hw)) 3637 igb_reset_phy(hw); 3638 3639 if (hw->flash_address) 3640 iounmap(hw->flash_address); 3641 err_sw_init: 3642 kfree(adapter->mac_table); 3643 kfree(adapter->shadow_vfta); 3644 igb_clear_interrupt_scheme(adapter); 3645 #ifdef CONFIG_PCI_IOV 3646 igb_disable_sriov(pdev); 3647 #endif 3648 pci_iounmap(pdev, adapter->io_addr); 3649 err_ioremap: 3650 free_netdev(netdev); 3651 err_alloc_etherdev: 3652 pci_release_mem_regions(pdev); 3653 err_pci_reg: 3654 err_dma: 3655 pci_disable_device(pdev); 3656 return err; 3657 } 3658 3659 #ifdef CONFIG_PCI_IOV 3660 static int igb_disable_sriov(struct pci_dev *pdev) 3661 { 3662 struct net_device *netdev = pci_get_drvdata(pdev); 3663 struct igb_adapter *adapter = netdev_priv(netdev); 3664 struct e1000_hw *hw = &adapter->hw; 3665 unsigned long flags; 3666 3667 /* reclaim resources allocated to VFs */ 3668 if (adapter->vf_data) { 3669 /* disable iov and allow time for transactions to clear */ 3670 if (pci_vfs_assigned(pdev)) { 3671 dev_warn(&pdev->dev, 3672 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3673 return -EPERM; 3674 } else { 3675 pci_disable_sriov(pdev); 3676 msleep(500); 3677 } 3678 spin_lock_irqsave(&adapter->vfs_lock, flags); 3679 kfree(adapter->vf_mac_list); 3680 adapter->vf_mac_list = NULL; 3681 kfree(adapter->vf_data); 3682 adapter->vf_data = NULL; 3683 adapter->vfs_allocated_count = 0; 3684 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 3685 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3686 wrfl(); 3687 msleep(100); 3688 dev_info(&pdev->dev, "IOV Disabled\n"); 3689 3690 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3691 adapter->flags |= IGB_FLAG_DMAC; 3692 } 3693 3694 return 0; 3695 } 3696 3697 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 3698 { 3699 struct net_device *netdev = pci_get_drvdata(pdev); 3700 struct igb_adapter *adapter = netdev_priv(netdev); 3701 int old_vfs = pci_num_vf(pdev); 3702 struct vf_mac_filter *mac_list; 3703 int err = 0; 3704 int num_vf_mac_filters, i; 3705 3706 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3707 err = -EPERM; 3708 goto out; 3709 } 3710 if (!num_vfs) 3711 goto out; 3712 3713 if (old_vfs) { 3714 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3715 old_vfs, max_vfs); 3716 adapter->vfs_allocated_count = old_vfs; 3717 } else 3718 adapter->vfs_allocated_count = num_vfs; 3719 3720 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3721 sizeof(struct vf_data_storage), GFP_KERNEL); 3722 3723 /* if allocation failed then we do not support SR-IOV */ 3724 if (!adapter->vf_data) { 3725 adapter->vfs_allocated_count = 0; 3726 err = -ENOMEM; 3727 goto out; 3728 } 3729 3730 /* Due to the limited number of RAR entries calculate potential 3731 * number of MAC filters available for the VFs. Reserve entries 3732 * for PF default MAC, PF MAC filters and at least one RAR entry 3733 * for each VF for VF MAC. 3734 */ 3735 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3736 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3737 adapter->vfs_allocated_count); 3738 3739 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3740 sizeof(struct vf_mac_filter), 3741 GFP_KERNEL); 3742 3743 mac_list = adapter->vf_mac_list; 3744 INIT_LIST_HEAD(&adapter->vf_macs.l); 3745 3746 if (adapter->vf_mac_list) { 3747 /* Initialize list of VF MAC filters */ 3748 for (i = 0; i < num_vf_mac_filters; i++) { 3749 mac_list->vf = -1; 3750 mac_list->free = true; 3751 list_add(&mac_list->l, &adapter->vf_macs.l); 3752 mac_list++; 3753 } 3754 } else { 3755 /* If we could not allocate memory for the VF MAC filters 3756 * we can continue without this feature but warn user. 3757 */ 3758 dev_err(&pdev->dev, 3759 "Unable to allocate memory for VF MAC filter list\n"); 3760 } 3761 3762 /* only call pci_enable_sriov() if no VFs are allocated already */ 3763 if (!old_vfs) { 3764 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3765 if (err) 3766 goto err_out; 3767 } 3768 dev_info(&pdev->dev, "%d VFs allocated\n", 3769 adapter->vfs_allocated_count); 3770 for (i = 0; i < adapter->vfs_allocated_count; i++) 3771 igb_vf_configure(adapter, i); 3772 3773 /* DMA Coalescing is not supported in IOV mode. */ 3774 adapter->flags &= ~IGB_FLAG_DMAC; 3775 goto out; 3776 3777 err_out: 3778 kfree(adapter->vf_mac_list); 3779 adapter->vf_mac_list = NULL; 3780 kfree(adapter->vf_data); 3781 adapter->vf_data = NULL; 3782 adapter->vfs_allocated_count = 0; 3783 out: 3784 return err; 3785 } 3786 3787 #endif 3788 /** 3789 * igb_remove_i2c - Cleanup I2C interface 3790 * @adapter: pointer to adapter structure 3791 **/ 3792 static void igb_remove_i2c(struct igb_adapter *adapter) 3793 { 3794 /* free the adapter bus structure */ 3795 i2c_del_adapter(&adapter->i2c_adap); 3796 } 3797 3798 /** 3799 * igb_remove - Device Removal Routine 3800 * @pdev: PCI device information struct 3801 * 3802 * igb_remove is called by the PCI subsystem to alert the driver 3803 * that it should release a PCI device. The could be caused by a 3804 * Hot-Plug event, or because the driver is going to be removed from 3805 * memory. 3806 **/ 3807 static void igb_remove(struct pci_dev *pdev) 3808 { 3809 struct net_device *netdev = pci_get_drvdata(pdev); 3810 struct igb_adapter *adapter = netdev_priv(netdev); 3811 struct e1000_hw *hw = &adapter->hw; 3812 3813 pm_runtime_get_noresume(&pdev->dev); 3814 #ifdef CONFIG_IGB_HWMON 3815 igb_sysfs_exit(adapter); 3816 #endif 3817 igb_remove_i2c(adapter); 3818 igb_ptp_stop(adapter); 3819 /* The watchdog timer may be rescheduled, so explicitly 3820 * disable watchdog from being rescheduled. 3821 */ 3822 set_bit(__IGB_DOWN, &adapter->state); 3823 del_timer_sync(&adapter->watchdog_timer); 3824 del_timer_sync(&adapter->phy_info_timer); 3825 3826 cancel_work_sync(&adapter->reset_task); 3827 cancel_work_sync(&adapter->watchdog_task); 3828 3829 #ifdef CONFIG_IGB_DCA 3830 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3831 dev_info(&pdev->dev, "DCA disabled\n"); 3832 dca_remove_requester(&pdev->dev); 3833 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3834 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3835 } 3836 #endif 3837 3838 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3839 * would have already happened in close and is redundant. 3840 */ 3841 igb_release_hw_control(adapter); 3842 3843 #ifdef CONFIG_PCI_IOV 3844 rtnl_lock(); 3845 igb_disable_sriov(pdev); 3846 rtnl_unlock(); 3847 #endif 3848 3849 unregister_netdev(netdev); 3850 3851 igb_clear_interrupt_scheme(adapter); 3852 3853 pci_iounmap(pdev, adapter->io_addr); 3854 if (hw->flash_address) 3855 iounmap(hw->flash_address); 3856 pci_release_mem_regions(pdev); 3857 3858 kfree(adapter->mac_table); 3859 kfree(adapter->shadow_vfta); 3860 free_netdev(netdev); 3861 3862 pci_disable_device(pdev); 3863 } 3864 3865 /** 3866 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3867 * @adapter: board private structure to initialize 3868 * 3869 * This function initializes the vf specific data storage and then attempts to 3870 * allocate the VFs. The reason for ordering it this way is because it is much 3871 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3872 * the memory for the VFs. 3873 **/ 3874 static void igb_probe_vfs(struct igb_adapter *adapter) 3875 { 3876 #ifdef CONFIG_PCI_IOV 3877 struct pci_dev *pdev = adapter->pdev; 3878 struct e1000_hw *hw = &adapter->hw; 3879 3880 /* Virtualization features not supported on i210 family. */ 3881 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 3882 return; 3883 3884 /* Of the below we really only want the effect of getting 3885 * IGB_FLAG_HAS_MSIX set (if available), without which 3886 * igb_enable_sriov() has no effect. 3887 */ 3888 igb_set_interrupt_capability(adapter, true); 3889 igb_reset_interrupt_capability(adapter); 3890 3891 pci_sriov_set_totalvfs(pdev, 7); 3892 igb_enable_sriov(pdev, max_vfs); 3893 3894 #endif /* CONFIG_PCI_IOV */ 3895 } 3896 3897 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3898 { 3899 struct e1000_hw *hw = &adapter->hw; 3900 unsigned int max_rss_queues; 3901 3902 /* Determine the maximum number of RSS queues supported. */ 3903 switch (hw->mac.type) { 3904 case e1000_i211: 3905 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3906 break; 3907 case e1000_82575: 3908 case e1000_i210: 3909 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3910 break; 3911 case e1000_i350: 3912 /* I350 cannot do RSS and SR-IOV at the same time */ 3913 if (!!adapter->vfs_allocated_count) { 3914 max_rss_queues = 1; 3915 break; 3916 } 3917 fallthrough; 3918 case e1000_82576: 3919 if (!!adapter->vfs_allocated_count) { 3920 max_rss_queues = 2; 3921 break; 3922 } 3923 fallthrough; 3924 case e1000_82580: 3925 case e1000_i354: 3926 default: 3927 max_rss_queues = IGB_MAX_RX_QUEUES; 3928 break; 3929 } 3930 3931 return max_rss_queues; 3932 } 3933 3934 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3935 { 3936 u32 max_rss_queues; 3937 3938 max_rss_queues = igb_get_max_rss_queues(adapter); 3939 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3940 3941 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3942 } 3943 3944 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3945 const u32 max_rss_queues) 3946 { 3947 struct e1000_hw *hw = &adapter->hw; 3948 3949 /* Determine if we need to pair queues. */ 3950 switch (hw->mac.type) { 3951 case e1000_82575: 3952 case e1000_i211: 3953 /* Device supports enough interrupts without queue pairing. */ 3954 break; 3955 case e1000_82576: 3956 case e1000_82580: 3957 case e1000_i350: 3958 case e1000_i354: 3959 case e1000_i210: 3960 default: 3961 /* If rss_queues > half of max_rss_queues, pair the queues in 3962 * order to conserve interrupts due to limited supply. 3963 */ 3964 if (adapter->rss_queues > (max_rss_queues / 2)) 3965 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3966 else 3967 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 3968 break; 3969 } 3970 } 3971 3972 /** 3973 * igb_sw_init - Initialize general software structures (struct igb_adapter) 3974 * @adapter: board private structure to initialize 3975 * 3976 * igb_sw_init initializes the Adapter private data structure. 3977 * Fields are initialized based on PCI device information and 3978 * OS network device settings (MTU size). 3979 **/ 3980 static int igb_sw_init(struct igb_adapter *adapter) 3981 { 3982 struct e1000_hw *hw = &adapter->hw; 3983 struct net_device *netdev = adapter->netdev; 3984 struct pci_dev *pdev = adapter->pdev; 3985 3986 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 3987 3988 /* set default ring sizes */ 3989 adapter->tx_ring_count = IGB_DEFAULT_TXD; 3990 adapter->rx_ring_count = IGB_DEFAULT_RXD; 3991 3992 /* set default ITR values */ 3993 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 3994 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 3995 3996 /* set default work limits */ 3997 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 3998 3999 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD; 4000 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4001 4002 spin_lock_init(&adapter->nfc_lock); 4003 spin_lock_init(&adapter->stats64_lock); 4004 4005 /* init spinlock to avoid concurrency of VF resources */ 4006 spin_lock_init(&adapter->vfs_lock); 4007 #ifdef CONFIG_PCI_IOV 4008 switch (hw->mac.type) { 4009 case e1000_82576: 4010 case e1000_i350: 4011 if (max_vfs > 7) { 4012 dev_warn(&pdev->dev, 4013 "Maximum of 7 VFs per PF, using max\n"); 4014 max_vfs = adapter->vfs_allocated_count = 7; 4015 } else 4016 adapter->vfs_allocated_count = max_vfs; 4017 if (adapter->vfs_allocated_count) 4018 dev_warn(&pdev->dev, 4019 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 4020 break; 4021 default: 4022 break; 4023 } 4024 #endif /* CONFIG_PCI_IOV */ 4025 4026 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 4027 adapter->flags |= IGB_FLAG_HAS_MSIX; 4028 4029 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 4030 sizeof(struct igb_mac_addr), 4031 GFP_KERNEL); 4032 if (!adapter->mac_table) 4033 return -ENOMEM; 4034 4035 igb_probe_vfs(adapter); 4036 4037 igb_init_queue_configuration(adapter); 4038 4039 /* Setup and initialize a copy of the hw vlan table array */ 4040 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 4041 GFP_KERNEL); 4042 if (!adapter->shadow_vfta) 4043 return -ENOMEM; 4044 4045 /* This call may decrease the number of queues */ 4046 if (igb_init_interrupt_scheme(adapter, true)) { 4047 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4048 return -ENOMEM; 4049 } 4050 4051 /* Explicitly disable IRQ since the NIC can be in any state. */ 4052 igb_irq_disable(adapter); 4053 4054 if (hw->mac.type >= e1000_i350) 4055 adapter->flags &= ~IGB_FLAG_DMAC; 4056 4057 set_bit(__IGB_DOWN, &adapter->state); 4058 return 0; 4059 } 4060 4061 /** 4062 * __igb_open - Called when a network interface is made active 4063 * @netdev: network interface device structure 4064 * @resuming: indicates whether we are in a resume call 4065 * 4066 * Returns 0 on success, negative value on failure 4067 * 4068 * The open entry point is called when a network interface is made 4069 * active by the system (IFF_UP). At this point all resources needed 4070 * for transmit and receive operations are allocated, the interrupt 4071 * handler is registered with the OS, the watchdog timer is started, 4072 * and the stack is notified that the interface is ready. 4073 **/ 4074 static int __igb_open(struct net_device *netdev, bool resuming) 4075 { 4076 struct igb_adapter *adapter = netdev_priv(netdev); 4077 struct e1000_hw *hw = &adapter->hw; 4078 struct pci_dev *pdev = adapter->pdev; 4079 int err; 4080 int i; 4081 4082 /* disallow open during test */ 4083 if (test_bit(__IGB_TESTING, &adapter->state)) { 4084 WARN_ON(resuming); 4085 return -EBUSY; 4086 } 4087 4088 if (!resuming) 4089 pm_runtime_get_sync(&pdev->dev); 4090 4091 netif_carrier_off(netdev); 4092 4093 /* allocate transmit descriptors */ 4094 err = igb_setup_all_tx_resources(adapter); 4095 if (err) 4096 goto err_setup_tx; 4097 4098 /* allocate receive descriptors */ 4099 err = igb_setup_all_rx_resources(adapter); 4100 if (err) 4101 goto err_setup_rx; 4102 4103 igb_power_up_link(adapter); 4104 4105 /* before we allocate an interrupt, we must be ready to handle it. 4106 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4107 * as soon as we call pci_request_irq, so we have to setup our 4108 * clean_rx handler before we do so. 4109 */ 4110 igb_configure(adapter); 4111 4112 err = igb_request_irq(adapter); 4113 if (err) 4114 goto err_req_irq; 4115 4116 /* Notify the stack of the actual queue counts. */ 4117 err = netif_set_real_num_tx_queues(adapter->netdev, 4118 adapter->num_tx_queues); 4119 if (err) 4120 goto err_set_queues; 4121 4122 err = netif_set_real_num_rx_queues(adapter->netdev, 4123 adapter->num_rx_queues); 4124 if (err) 4125 goto err_set_queues; 4126 4127 /* From here on the code is the same as igb_up() */ 4128 clear_bit(__IGB_DOWN, &adapter->state); 4129 4130 for (i = 0; i < adapter->num_q_vectors; i++) 4131 napi_enable(&(adapter->q_vector[i]->napi)); 4132 4133 /* Clear any pending interrupts. */ 4134 rd32(E1000_TSICR); 4135 rd32(E1000_ICR); 4136 4137 igb_irq_enable(adapter); 4138 4139 /* notify VFs that reset has been completed */ 4140 if (adapter->vfs_allocated_count) { 4141 u32 reg_data = rd32(E1000_CTRL_EXT); 4142 4143 reg_data |= E1000_CTRL_EXT_PFRSTD; 4144 wr32(E1000_CTRL_EXT, reg_data); 4145 } 4146 4147 netif_tx_start_all_queues(netdev); 4148 4149 if (!resuming) 4150 pm_runtime_put(&pdev->dev); 4151 4152 /* start the watchdog. */ 4153 hw->mac.get_link_status = 1; 4154 schedule_work(&adapter->watchdog_task); 4155 4156 return 0; 4157 4158 err_set_queues: 4159 igb_free_irq(adapter); 4160 err_req_irq: 4161 igb_release_hw_control(adapter); 4162 igb_power_down_link(adapter); 4163 igb_free_all_rx_resources(adapter); 4164 err_setup_rx: 4165 igb_free_all_tx_resources(adapter); 4166 err_setup_tx: 4167 igb_reset(adapter); 4168 if (!resuming) 4169 pm_runtime_put(&pdev->dev); 4170 4171 return err; 4172 } 4173 4174 int igb_open(struct net_device *netdev) 4175 { 4176 return __igb_open(netdev, false); 4177 } 4178 4179 /** 4180 * __igb_close - Disables a network interface 4181 * @netdev: network interface device structure 4182 * @suspending: indicates we are in a suspend call 4183 * 4184 * Returns 0, this is not allowed to fail 4185 * 4186 * The close entry point is called when an interface is de-activated 4187 * by the OS. The hardware is still under the driver's control, but 4188 * needs to be disabled. A global MAC reset is issued to stop the 4189 * hardware, and all transmit and receive resources are freed. 4190 **/ 4191 static int __igb_close(struct net_device *netdev, bool suspending) 4192 { 4193 struct igb_adapter *adapter = netdev_priv(netdev); 4194 struct pci_dev *pdev = adapter->pdev; 4195 4196 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4197 4198 if (!suspending) 4199 pm_runtime_get_sync(&pdev->dev); 4200 4201 igb_down(adapter); 4202 igb_free_irq(adapter); 4203 4204 igb_free_all_tx_resources(adapter); 4205 igb_free_all_rx_resources(adapter); 4206 4207 if (!suspending) 4208 pm_runtime_put_sync(&pdev->dev); 4209 return 0; 4210 } 4211 4212 int igb_close(struct net_device *netdev) 4213 { 4214 if (netif_device_present(netdev) || netdev->dismantle) 4215 return __igb_close(netdev, false); 4216 return 0; 4217 } 4218 4219 /** 4220 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4221 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4222 * 4223 * Return 0 on success, negative on failure 4224 **/ 4225 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4226 { 4227 struct device *dev = tx_ring->dev; 4228 int size; 4229 4230 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4231 4232 tx_ring->tx_buffer_info = vmalloc(size); 4233 if (!tx_ring->tx_buffer_info) 4234 goto err; 4235 4236 /* round up to nearest 4K */ 4237 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4238 tx_ring->size = ALIGN(tx_ring->size, 4096); 4239 4240 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4241 &tx_ring->dma, GFP_KERNEL); 4242 if (!tx_ring->desc) 4243 goto err; 4244 4245 tx_ring->next_to_use = 0; 4246 tx_ring->next_to_clean = 0; 4247 4248 return 0; 4249 4250 err: 4251 vfree(tx_ring->tx_buffer_info); 4252 tx_ring->tx_buffer_info = NULL; 4253 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4254 return -ENOMEM; 4255 } 4256 4257 /** 4258 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4259 * (Descriptors) for all queues 4260 * @adapter: board private structure 4261 * 4262 * Return 0 on success, negative on failure 4263 **/ 4264 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4265 { 4266 struct pci_dev *pdev = adapter->pdev; 4267 int i, err = 0; 4268 4269 for (i = 0; i < adapter->num_tx_queues; i++) { 4270 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4271 if (err) { 4272 dev_err(&pdev->dev, 4273 "Allocation for Tx Queue %u failed\n", i); 4274 for (i--; i >= 0; i--) 4275 igb_free_tx_resources(adapter->tx_ring[i]); 4276 break; 4277 } 4278 } 4279 4280 return err; 4281 } 4282 4283 /** 4284 * igb_setup_tctl - configure the transmit control registers 4285 * @adapter: Board private structure 4286 **/ 4287 void igb_setup_tctl(struct igb_adapter *adapter) 4288 { 4289 struct e1000_hw *hw = &adapter->hw; 4290 u32 tctl; 4291 4292 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4293 wr32(E1000_TXDCTL(0), 0); 4294 4295 /* Program the Transmit Control Register */ 4296 tctl = rd32(E1000_TCTL); 4297 tctl &= ~E1000_TCTL_CT; 4298 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4299 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4300 4301 igb_config_collision_dist(hw); 4302 4303 /* Enable transmits */ 4304 tctl |= E1000_TCTL_EN; 4305 4306 wr32(E1000_TCTL, tctl); 4307 } 4308 4309 /** 4310 * igb_configure_tx_ring - Configure transmit ring after Reset 4311 * @adapter: board private structure 4312 * @ring: tx ring to configure 4313 * 4314 * Configure a transmit ring after a reset. 4315 **/ 4316 void igb_configure_tx_ring(struct igb_adapter *adapter, 4317 struct igb_ring *ring) 4318 { 4319 struct e1000_hw *hw = &adapter->hw; 4320 u32 txdctl = 0; 4321 u64 tdba = ring->dma; 4322 int reg_idx = ring->reg_idx; 4323 4324 wr32(E1000_TDLEN(reg_idx), 4325 ring->count * sizeof(union e1000_adv_tx_desc)); 4326 wr32(E1000_TDBAL(reg_idx), 4327 tdba & 0x00000000ffffffffULL); 4328 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4329 4330 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4331 wr32(E1000_TDH(reg_idx), 0); 4332 writel(0, ring->tail); 4333 4334 txdctl |= IGB_TX_PTHRESH; 4335 txdctl |= IGB_TX_HTHRESH << 8; 4336 txdctl |= IGB_TX_WTHRESH << 16; 4337 4338 /* reinitialize tx_buffer_info */ 4339 memset(ring->tx_buffer_info, 0, 4340 sizeof(struct igb_tx_buffer) * ring->count); 4341 4342 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4343 wr32(E1000_TXDCTL(reg_idx), txdctl); 4344 } 4345 4346 /** 4347 * igb_configure_tx - Configure transmit Unit after Reset 4348 * @adapter: board private structure 4349 * 4350 * Configure the Tx unit of the MAC after a reset. 4351 **/ 4352 static void igb_configure_tx(struct igb_adapter *adapter) 4353 { 4354 struct e1000_hw *hw = &adapter->hw; 4355 int i; 4356 4357 /* disable the queues */ 4358 for (i = 0; i < adapter->num_tx_queues; i++) 4359 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4360 4361 wrfl(); 4362 usleep_range(10000, 20000); 4363 4364 for (i = 0; i < adapter->num_tx_queues; i++) 4365 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4366 } 4367 4368 /** 4369 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4370 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4371 * 4372 * Returns 0 on success, negative on failure 4373 **/ 4374 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4375 { 4376 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev); 4377 struct device *dev = rx_ring->dev; 4378 int size, res; 4379 4380 /* XDP RX-queue info */ 4381 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq)) 4382 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4383 res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 4384 rx_ring->queue_index, 0); 4385 if (res < 0) { 4386 dev_err(dev, "Failed to register xdp_rxq index %u\n", 4387 rx_ring->queue_index); 4388 return res; 4389 } 4390 4391 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4392 4393 rx_ring->rx_buffer_info = vmalloc(size); 4394 if (!rx_ring->rx_buffer_info) 4395 goto err; 4396 4397 /* Round up to nearest 4K */ 4398 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4399 rx_ring->size = ALIGN(rx_ring->size, 4096); 4400 4401 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4402 &rx_ring->dma, GFP_KERNEL); 4403 if (!rx_ring->desc) 4404 goto err; 4405 4406 rx_ring->next_to_alloc = 0; 4407 rx_ring->next_to_clean = 0; 4408 rx_ring->next_to_use = 0; 4409 4410 rx_ring->xdp_prog = adapter->xdp_prog; 4411 4412 return 0; 4413 4414 err: 4415 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4416 vfree(rx_ring->rx_buffer_info); 4417 rx_ring->rx_buffer_info = NULL; 4418 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4419 return -ENOMEM; 4420 } 4421 4422 /** 4423 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4424 * (Descriptors) for all queues 4425 * @adapter: board private structure 4426 * 4427 * Return 0 on success, negative on failure 4428 **/ 4429 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4430 { 4431 struct pci_dev *pdev = adapter->pdev; 4432 int i, err = 0; 4433 4434 for (i = 0; i < adapter->num_rx_queues; i++) { 4435 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4436 if (err) { 4437 dev_err(&pdev->dev, 4438 "Allocation for Rx Queue %u failed\n", i); 4439 for (i--; i >= 0; i--) 4440 igb_free_rx_resources(adapter->rx_ring[i]); 4441 break; 4442 } 4443 } 4444 4445 return err; 4446 } 4447 4448 /** 4449 * igb_setup_mrqc - configure the multiple receive queue control registers 4450 * @adapter: Board private structure 4451 **/ 4452 static void igb_setup_mrqc(struct igb_adapter *adapter) 4453 { 4454 struct e1000_hw *hw = &adapter->hw; 4455 u32 mrqc, rxcsum; 4456 u32 j, num_rx_queues; 4457 u32 rss_key[10]; 4458 4459 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4460 for (j = 0; j < 10; j++) 4461 wr32(E1000_RSSRK(j), rss_key[j]); 4462 4463 num_rx_queues = adapter->rss_queues; 4464 4465 switch (hw->mac.type) { 4466 case e1000_82576: 4467 /* 82576 supports 2 RSS queues for SR-IOV */ 4468 if (adapter->vfs_allocated_count) 4469 num_rx_queues = 2; 4470 break; 4471 default: 4472 break; 4473 } 4474 4475 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4476 for (j = 0; j < IGB_RETA_SIZE; j++) 4477 adapter->rss_indir_tbl[j] = 4478 (j * num_rx_queues) / IGB_RETA_SIZE; 4479 adapter->rss_indir_tbl_init = num_rx_queues; 4480 } 4481 igb_write_rss_indir_tbl(adapter); 4482 4483 /* Disable raw packet checksumming so that RSS hash is placed in 4484 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4485 * offloads as they are enabled by default 4486 */ 4487 rxcsum = rd32(E1000_RXCSUM); 4488 rxcsum |= E1000_RXCSUM_PCSD; 4489 4490 if (adapter->hw.mac.type >= e1000_82576) 4491 /* Enable Receive Checksum Offload for SCTP */ 4492 rxcsum |= E1000_RXCSUM_CRCOFL; 4493 4494 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4495 wr32(E1000_RXCSUM, rxcsum); 4496 4497 /* Generate RSS hash based on packet types, TCP/UDP 4498 * port numbers and/or IPv4/v6 src and dst addresses 4499 */ 4500 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4501 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4502 E1000_MRQC_RSS_FIELD_IPV6 | 4503 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4504 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4505 4506 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4507 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4508 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4509 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4510 4511 /* If VMDq is enabled then we set the appropriate mode for that, else 4512 * we default to RSS so that an RSS hash is calculated per packet even 4513 * if we are only using one queue 4514 */ 4515 if (adapter->vfs_allocated_count) { 4516 if (hw->mac.type > e1000_82575) { 4517 /* Set the default pool for the PF's first queue */ 4518 u32 vtctl = rd32(E1000_VT_CTL); 4519 4520 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4521 E1000_VT_CTL_DISABLE_DEF_POOL); 4522 vtctl |= adapter->vfs_allocated_count << 4523 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4524 wr32(E1000_VT_CTL, vtctl); 4525 } 4526 if (adapter->rss_queues > 1) 4527 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4528 else 4529 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4530 } else { 4531 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4532 } 4533 igb_vmm_control(adapter); 4534 4535 wr32(E1000_MRQC, mrqc); 4536 } 4537 4538 /** 4539 * igb_setup_rctl - configure the receive control registers 4540 * @adapter: Board private structure 4541 **/ 4542 void igb_setup_rctl(struct igb_adapter *adapter) 4543 { 4544 struct e1000_hw *hw = &adapter->hw; 4545 u32 rctl; 4546 4547 rctl = rd32(E1000_RCTL); 4548 4549 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4550 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4551 4552 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4553 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4554 4555 /* enable stripping of CRC. It's unlikely this will break BMC 4556 * redirection as it did with e1000. Newer features require 4557 * that the HW strips the CRC. 4558 */ 4559 rctl |= E1000_RCTL_SECRC; 4560 4561 /* disable store bad packets and clear size bits. */ 4562 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4563 4564 /* enable LPE to allow for reception of jumbo frames */ 4565 rctl |= E1000_RCTL_LPE; 4566 4567 /* disable queue 0 to prevent tail write w/o re-config */ 4568 wr32(E1000_RXDCTL(0), 0); 4569 4570 /* Attention!!! For SR-IOV PF driver operations you must enable 4571 * queue drop for all VF and PF queues to prevent head of line blocking 4572 * if an un-trusted VF does not provide descriptors to hardware. 4573 */ 4574 if (adapter->vfs_allocated_count) { 4575 /* set all queue drop enable bits */ 4576 wr32(E1000_QDE, ALL_QUEUES); 4577 } 4578 4579 /* This is useful for sniffing bad packets. */ 4580 if (adapter->netdev->features & NETIF_F_RXALL) { 4581 /* UPE and MPE will be handled by normal PROMISC logic 4582 * in e1000e_set_rx_mode 4583 */ 4584 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4585 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4586 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4587 4588 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4589 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4590 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4591 * and that breaks VLANs. 4592 */ 4593 } 4594 4595 wr32(E1000_RCTL, rctl); 4596 } 4597 4598 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4599 int vfn) 4600 { 4601 struct e1000_hw *hw = &adapter->hw; 4602 u32 vmolr; 4603 4604 if (size > MAX_JUMBO_FRAME_SIZE) 4605 size = MAX_JUMBO_FRAME_SIZE; 4606 4607 vmolr = rd32(E1000_VMOLR(vfn)); 4608 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4609 vmolr |= size | E1000_VMOLR_LPE; 4610 wr32(E1000_VMOLR(vfn), vmolr); 4611 4612 return 0; 4613 } 4614 4615 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4616 int vfn, bool enable) 4617 { 4618 struct e1000_hw *hw = &adapter->hw; 4619 u32 val, reg; 4620 4621 if (hw->mac.type < e1000_82576) 4622 return; 4623 4624 if (hw->mac.type == e1000_i350) 4625 reg = E1000_DVMOLR(vfn); 4626 else 4627 reg = E1000_VMOLR(vfn); 4628 4629 val = rd32(reg); 4630 if (enable) 4631 val |= E1000_VMOLR_STRVLAN; 4632 else 4633 val &= ~(E1000_VMOLR_STRVLAN); 4634 wr32(reg, val); 4635 } 4636 4637 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4638 int vfn, bool aupe) 4639 { 4640 struct e1000_hw *hw = &adapter->hw; 4641 u32 vmolr; 4642 4643 /* This register exists only on 82576 and newer so if we are older then 4644 * we should exit and do nothing 4645 */ 4646 if (hw->mac.type < e1000_82576) 4647 return; 4648 4649 vmolr = rd32(E1000_VMOLR(vfn)); 4650 if (aupe) 4651 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4652 else 4653 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4654 4655 /* clear all bits that might not be set */ 4656 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4657 4658 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4659 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4660 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4661 * multicast packets 4662 */ 4663 if (vfn <= adapter->vfs_allocated_count) 4664 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4665 4666 wr32(E1000_VMOLR(vfn), vmolr); 4667 } 4668 4669 /** 4670 * igb_setup_srrctl - configure the split and replication receive control 4671 * registers 4672 * @adapter: Board private structure 4673 * @ring: receive ring to be configured 4674 **/ 4675 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring) 4676 { 4677 struct e1000_hw *hw = &adapter->hw; 4678 int reg_idx = ring->reg_idx; 4679 u32 srrctl = 0; 4680 4681 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4682 if (ring_uses_large_buffer(ring)) 4683 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4684 else 4685 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4686 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4687 if (hw->mac.type >= e1000_82580) 4688 srrctl |= E1000_SRRCTL_TIMESTAMP; 4689 /* Only set Drop Enable if VFs allocated, or we are supporting multiple 4690 * queues and rx flow control is disabled 4691 */ 4692 if (adapter->vfs_allocated_count || 4693 (!(hw->fc.current_mode & e1000_fc_rx_pause) && 4694 adapter->num_rx_queues > 1)) 4695 srrctl |= E1000_SRRCTL_DROP_EN; 4696 4697 wr32(E1000_SRRCTL(reg_idx), srrctl); 4698 } 4699 4700 /** 4701 * igb_configure_rx_ring - Configure a receive ring after Reset 4702 * @adapter: board private structure 4703 * @ring: receive ring to be configured 4704 * 4705 * Configure the Rx unit of the MAC after a reset. 4706 **/ 4707 void igb_configure_rx_ring(struct igb_adapter *adapter, 4708 struct igb_ring *ring) 4709 { 4710 struct e1000_hw *hw = &adapter->hw; 4711 union e1000_adv_rx_desc *rx_desc; 4712 u64 rdba = ring->dma; 4713 int reg_idx = ring->reg_idx; 4714 u32 rxdctl = 0; 4715 4716 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4717 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4718 MEM_TYPE_PAGE_SHARED, NULL)); 4719 4720 /* disable the queue */ 4721 wr32(E1000_RXDCTL(reg_idx), 0); 4722 4723 /* Set DMA base address registers */ 4724 wr32(E1000_RDBAL(reg_idx), 4725 rdba & 0x00000000ffffffffULL); 4726 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4727 wr32(E1000_RDLEN(reg_idx), 4728 ring->count * sizeof(union e1000_adv_rx_desc)); 4729 4730 /* initialize head and tail */ 4731 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4732 wr32(E1000_RDH(reg_idx), 0); 4733 writel(0, ring->tail); 4734 4735 /* set descriptor configuration */ 4736 igb_setup_srrctl(adapter, ring); 4737 4738 /* set filtering for VMDQ pools */ 4739 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4740 4741 rxdctl |= IGB_RX_PTHRESH; 4742 rxdctl |= IGB_RX_HTHRESH << 8; 4743 rxdctl |= IGB_RX_WTHRESH << 16; 4744 4745 /* initialize rx_buffer_info */ 4746 memset(ring->rx_buffer_info, 0, 4747 sizeof(struct igb_rx_buffer) * ring->count); 4748 4749 /* initialize Rx descriptor 0 */ 4750 rx_desc = IGB_RX_DESC(ring, 0); 4751 rx_desc->wb.upper.length = 0; 4752 4753 /* enable receive descriptor fetching */ 4754 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4755 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4756 } 4757 4758 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4759 struct igb_ring *rx_ring) 4760 { 4761 /* set build_skb and buffer size flags */ 4762 clear_ring_build_skb_enabled(rx_ring); 4763 clear_ring_uses_large_buffer(rx_ring); 4764 4765 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4766 return; 4767 4768 set_ring_build_skb_enabled(rx_ring); 4769 4770 #if (PAGE_SIZE < 8192) 4771 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4772 return; 4773 4774 set_ring_uses_large_buffer(rx_ring); 4775 #endif 4776 } 4777 4778 /** 4779 * igb_configure_rx - Configure receive Unit after Reset 4780 * @adapter: board private structure 4781 * 4782 * Configure the Rx unit of the MAC after a reset. 4783 **/ 4784 static void igb_configure_rx(struct igb_adapter *adapter) 4785 { 4786 int i; 4787 4788 /* set the correct pool for the PF default MAC address in entry 0 */ 4789 igb_set_default_mac_filter(adapter); 4790 4791 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4792 * the Base and Length of the Rx Descriptor Ring 4793 */ 4794 for (i = 0; i < adapter->num_rx_queues; i++) { 4795 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4796 4797 igb_set_rx_buffer_len(adapter, rx_ring); 4798 igb_configure_rx_ring(adapter, rx_ring); 4799 } 4800 } 4801 4802 /** 4803 * igb_free_tx_resources - Free Tx Resources per Queue 4804 * @tx_ring: Tx descriptor ring for a specific queue 4805 * 4806 * Free all transmit software resources 4807 **/ 4808 void igb_free_tx_resources(struct igb_ring *tx_ring) 4809 { 4810 igb_clean_tx_ring(tx_ring); 4811 4812 vfree(tx_ring->tx_buffer_info); 4813 tx_ring->tx_buffer_info = NULL; 4814 4815 /* if not set, then don't free */ 4816 if (!tx_ring->desc) 4817 return; 4818 4819 dma_free_coherent(tx_ring->dev, tx_ring->size, 4820 tx_ring->desc, tx_ring->dma); 4821 4822 tx_ring->desc = NULL; 4823 } 4824 4825 /** 4826 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4827 * @adapter: board private structure 4828 * 4829 * Free all transmit software resources 4830 **/ 4831 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4832 { 4833 int i; 4834 4835 for (i = 0; i < adapter->num_tx_queues; i++) 4836 if (adapter->tx_ring[i]) 4837 igb_free_tx_resources(adapter->tx_ring[i]); 4838 } 4839 4840 /** 4841 * igb_clean_tx_ring - Free Tx Buffers 4842 * @tx_ring: ring to be cleaned 4843 **/ 4844 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 4845 { 4846 u16 i = tx_ring->next_to_clean; 4847 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4848 4849 while (i != tx_ring->next_to_use) { 4850 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4851 4852 /* Free all the Tx ring sk_buffs or xdp frames */ 4853 if (tx_buffer->type == IGB_TYPE_SKB) 4854 dev_kfree_skb_any(tx_buffer->skb); 4855 else 4856 xdp_return_frame(tx_buffer->xdpf); 4857 4858 /* unmap skb header data */ 4859 dma_unmap_single(tx_ring->dev, 4860 dma_unmap_addr(tx_buffer, dma), 4861 dma_unmap_len(tx_buffer, len), 4862 DMA_TO_DEVICE); 4863 4864 /* check for eop_desc to determine the end of the packet */ 4865 eop_desc = tx_buffer->next_to_watch; 4866 tx_desc = IGB_TX_DESC(tx_ring, i); 4867 4868 /* unmap remaining buffers */ 4869 while (tx_desc != eop_desc) { 4870 tx_buffer++; 4871 tx_desc++; 4872 i++; 4873 if (unlikely(i == tx_ring->count)) { 4874 i = 0; 4875 tx_buffer = tx_ring->tx_buffer_info; 4876 tx_desc = IGB_TX_DESC(tx_ring, 0); 4877 } 4878 4879 /* unmap any remaining paged data */ 4880 if (dma_unmap_len(tx_buffer, len)) 4881 dma_unmap_page(tx_ring->dev, 4882 dma_unmap_addr(tx_buffer, dma), 4883 dma_unmap_len(tx_buffer, len), 4884 DMA_TO_DEVICE); 4885 } 4886 4887 tx_buffer->next_to_watch = NULL; 4888 4889 /* move us one more past the eop_desc for start of next pkt */ 4890 tx_buffer++; 4891 i++; 4892 if (unlikely(i == tx_ring->count)) { 4893 i = 0; 4894 tx_buffer = tx_ring->tx_buffer_info; 4895 } 4896 } 4897 4898 /* reset BQL for queue */ 4899 netdev_tx_reset_queue(txring_txq(tx_ring)); 4900 4901 /* reset next_to_use and next_to_clean */ 4902 tx_ring->next_to_use = 0; 4903 tx_ring->next_to_clean = 0; 4904 } 4905 4906 /** 4907 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 4908 * @adapter: board private structure 4909 **/ 4910 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 4911 { 4912 int i; 4913 4914 for (i = 0; i < adapter->num_tx_queues; i++) 4915 if (adapter->tx_ring[i]) 4916 igb_clean_tx_ring(adapter->tx_ring[i]); 4917 } 4918 4919 /** 4920 * igb_free_rx_resources - Free Rx Resources 4921 * @rx_ring: ring to clean the resources from 4922 * 4923 * Free all receive software resources 4924 **/ 4925 void igb_free_rx_resources(struct igb_ring *rx_ring) 4926 { 4927 igb_clean_rx_ring(rx_ring); 4928 4929 rx_ring->xdp_prog = NULL; 4930 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4931 vfree(rx_ring->rx_buffer_info); 4932 rx_ring->rx_buffer_info = NULL; 4933 4934 /* if not set, then don't free */ 4935 if (!rx_ring->desc) 4936 return; 4937 4938 dma_free_coherent(rx_ring->dev, rx_ring->size, 4939 rx_ring->desc, rx_ring->dma); 4940 4941 rx_ring->desc = NULL; 4942 } 4943 4944 /** 4945 * igb_free_all_rx_resources - Free Rx Resources for All Queues 4946 * @adapter: board private structure 4947 * 4948 * Free all receive software resources 4949 **/ 4950 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 4951 { 4952 int i; 4953 4954 for (i = 0; i < adapter->num_rx_queues; i++) 4955 if (adapter->rx_ring[i]) 4956 igb_free_rx_resources(adapter->rx_ring[i]); 4957 } 4958 4959 /** 4960 * igb_clean_rx_ring - Free Rx Buffers per Queue 4961 * @rx_ring: ring to free buffers from 4962 **/ 4963 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 4964 { 4965 u16 i = rx_ring->next_to_clean; 4966 4967 dev_kfree_skb(rx_ring->skb); 4968 rx_ring->skb = NULL; 4969 4970 /* Free all the Rx ring sk_buffs */ 4971 while (i != rx_ring->next_to_alloc) { 4972 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 4973 4974 /* Invalidate cache lines that may have been written to by 4975 * device so that we avoid corrupting memory. 4976 */ 4977 dma_sync_single_range_for_cpu(rx_ring->dev, 4978 buffer_info->dma, 4979 buffer_info->page_offset, 4980 igb_rx_bufsz(rx_ring), 4981 DMA_FROM_DEVICE); 4982 4983 /* free resources associated with mapping */ 4984 dma_unmap_page_attrs(rx_ring->dev, 4985 buffer_info->dma, 4986 igb_rx_pg_size(rx_ring), 4987 DMA_FROM_DEVICE, 4988 IGB_RX_DMA_ATTR); 4989 __page_frag_cache_drain(buffer_info->page, 4990 buffer_info->pagecnt_bias); 4991 4992 i++; 4993 if (i == rx_ring->count) 4994 i = 0; 4995 } 4996 4997 rx_ring->next_to_alloc = 0; 4998 rx_ring->next_to_clean = 0; 4999 rx_ring->next_to_use = 0; 5000 } 5001 5002 /** 5003 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 5004 * @adapter: board private structure 5005 **/ 5006 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 5007 { 5008 int i; 5009 5010 for (i = 0; i < adapter->num_rx_queues; i++) 5011 if (adapter->rx_ring[i]) 5012 igb_clean_rx_ring(adapter->rx_ring[i]); 5013 } 5014 5015 /** 5016 * igb_set_mac - Change the Ethernet Address of the NIC 5017 * @netdev: network interface device structure 5018 * @p: pointer to an address structure 5019 * 5020 * Returns 0 on success, negative on failure 5021 **/ 5022 static int igb_set_mac(struct net_device *netdev, void *p) 5023 { 5024 struct igb_adapter *adapter = netdev_priv(netdev); 5025 struct e1000_hw *hw = &adapter->hw; 5026 struct sockaddr *addr = p; 5027 5028 if (!is_valid_ether_addr(addr->sa_data)) 5029 return -EADDRNOTAVAIL; 5030 5031 eth_hw_addr_set(netdev, addr->sa_data); 5032 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 5033 5034 /* set the correct pool for the new PF MAC address in entry 0 */ 5035 igb_set_default_mac_filter(adapter); 5036 5037 return 0; 5038 } 5039 5040 /** 5041 * igb_write_mc_addr_list - write multicast addresses to MTA 5042 * @netdev: network interface device structure 5043 * 5044 * Writes multicast address list to the MTA hash table. 5045 * Returns: -ENOMEM on failure 5046 * 0 on no addresses written 5047 * X on writing X addresses to MTA 5048 **/ 5049 static int igb_write_mc_addr_list(struct net_device *netdev) 5050 { 5051 struct igb_adapter *adapter = netdev_priv(netdev); 5052 struct e1000_hw *hw = &adapter->hw; 5053 struct netdev_hw_addr *ha; 5054 u8 *mta_list; 5055 int i; 5056 5057 if (netdev_mc_empty(netdev)) { 5058 /* nothing to program, so clear mc list */ 5059 igb_update_mc_addr_list(hw, NULL, 0); 5060 igb_restore_vf_multicasts(adapter); 5061 return 0; 5062 } 5063 5064 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 5065 if (!mta_list) 5066 return -ENOMEM; 5067 5068 /* The shared function expects a packed array of only addresses. */ 5069 i = 0; 5070 netdev_for_each_mc_addr(ha, netdev) 5071 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 5072 5073 igb_update_mc_addr_list(hw, mta_list, i); 5074 kfree(mta_list); 5075 5076 return netdev_mc_count(netdev); 5077 } 5078 5079 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 5080 { 5081 struct e1000_hw *hw = &adapter->hw; 5082 u32 i, pf_id; 5083 5084 switch (hw->mac.type) { 5085 case e1000_i210: 5086 case e1000_i211: 5087 case e1000_i350: 5088 /* VLAN filtering needed for VLAN prio filter */ 5089 if (adapter->netdev->features & NETIF_F_NTUPLE) 5090 break; 5091 fallthrough; 5092 case e1000_82576: 5093 case e1000_82580: 5094 case e1000_i354: 5095 /* VLAN filtering needed for pool filtering */ 5096 if (adapter->vfs_allocated_count) 5097 break; 5098 fallthrough; 5099 default: 5100 return 1; 5101 } 5102 5103 /* We are already in VLAN promisc, nothing to do */ 5104 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 5105 return 0; 5106 5107 if (!adapter->vfs_allocated_count) 5108 goto set_vfta; 5109 5110 /* Add PF to all active pools */ 5111 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5112 5113 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5114 u32 vlvf = rd32(E1000_VLVF(i)); 5115 5116 vlvf |= BIT(pf_id); 5117 wr32(E1000_VLVF(i), vlvf); 5118 } 5119 5120 set_vfta: 5121 /* Set all bits in the VLAN filter table array */ 5122 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 5123 hw->mac.ops.write_vfta(hw, i, ~0U); 5124 5125 /* Set flag so we don't redo unnecessary work */ 5126 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 5127 5128 return 0; 5129 } 5130 5131 #define VFTA_BLOCK_SIZE 8 5132 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 5133 { 5134 struct e1000_hw *hw = &adapter->hw; 5135 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 5136 u32 vid_start = vfta_offset * 32; 5137 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 5138 u32 i, vid, word, bits, pf_id; 5139 5140 /* guarantee that we don't scrub out management VLAN */ 5141 vid = adapter->mng_vlan_id; 5142 if (vid >= vid_start && vid < vid_end) 5143 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5144 5145 if (!adapter->vfs_allocated_count) 5146 goto set_vfta; 5147 5148 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5149 5150 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5151 u32 vlvf = rd32(E1000_VLVF(i)); 5152 5153 /* pull VLAN ID from VLVF */ 5154 vid = vlvf & VLAN_VID_MASK; 5155 5156 /* only concern ourselves with a certain range */ 5157 if (vid < vid_start || vid >= vid_end) 5158 continue; 5159 5160 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 5161 /* record VLAN ID in VFTA */ 5162 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5163 5164 /* if PF is part of this then continue */ 5165 if (test_bit(vid, adapter->active_vlans)) 5166 continue; 5167 } 5168 5169 /* remove PF from the pool */ 5170 bits = ~BIT(pf_id); 5171 bits &= rd32(E1000_VLVF(i)); 5172 wr32(E1000_VLVF(i), bits); 5173 } 5174 5175 set_vfta: 5176 /* extract values from active_vlans and write back to VFTA */ 5177 for (i = VFTA_BLOCK_SIZE; i--;) { 5178 vid = (vfta_offset + i) * 32; 5179 word = vid / BITS_PER_LONG; 5180 bits = vid % BITS_PER_LONG; 5181 5182 vfta[i] |= adapter->active_vlans[word] >> bits; 5183 5184 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 5185 } 5186 } 5187 5188 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 5189 { 5190 u32 i; 5191 5192 /* We are not in VLAN promisc, nothing to do */ 5193 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 5194 return; 5195 5196 /* Set flag so we don't redo unnecessary work */ 5197 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 5198 5199 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 5200 igb_scrub_vfta(adapter, i); 5201 } 5202 5203 /** 5204 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 5205 * @netdev: network interface device structure 5206 * 5207 * The set_rx_mode entry point is called whenever the unicast or multicast 5208 * address lists or the network interface flags are updated. This routine is 5209 * responsible for configuring the hardware for proper unicast, multicast, 5210 * promiscuous mode, and all-multi behavior. 5211 **/ 5212 static void igb_set_rx_mode(struct net_device *netdev) 5213 { 5214 struct igb_adapter *adapter = netdev_priv(netdev); 5215 struct e1000_hw *hw = &adapter->hw; 5216 unsigned int vfn = adapter->vfs_allocated_count; 5217 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 5218 int count; 5219 5220 /* Check for Promiscuous and All Multicast modes */ 5221 if (netdev->flags & IFF_PROMISC) { 5222 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5223 vmolr |= E1000_VMOLR_MPME; 5224 5225 /* enable use of UTA filter to force packets to default pool */ 5226 if (hw->mac.type == e1000_82576) 5227 vmolr |= E1000_VMOLR_ROPE; 5228 } else { 5229 if (netdev->flags & IFF_ALLMULTI) { 5230 rctl |= E1000_RCTL_MPE; 5231 vmolr |= E1000_VMOLR_MPME; 5232 } else { 5233 /* Write addresses to the MTA, if the attempt fails 5234 * then we should just turn on promiscuous mode so 5235 * that we can at least receive multicast traffic 5236 */ 5237 count = igb_write_mc_addr_list(netdev); 5238 if (count < 0) { 5239 rctl |= E1000_RCTL_MPE; 5240 vmolr |= E1000_VMOLR_MPME; 5241 } else if (count) { 5242 vmolr |= E1000_VMOLR_ROMPE; 5243 } 5244 } 5245 } 5246 5247 /* Write addresses to available RAR registers, if there is not 5248 * sufficient space to store all the addresses then enable 5249 * unicast promiscuous mode 5250 */ 5251 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5252 rctl |= E1000_RCTL_UPE; 5253 vmolr |= E1000_VMOLR_ROPE; 5254 } 5255 5256 /* enable VLAN filtering by default */ 5257 rctl |= E1000_RCTL_VFE; 5258 5259 /* disable VLAN filtering for modes that require it */ 5260 if ((netdev->flags & IFF_PROMISC) || 5261 (netdev->features & NETIF_F_RXALL)) { 5262 /* if we fail to set all rules then just clear VFE */ 5263 if (igb_vlan_promisc_enable(adapter)) 5264 rctl &= ~E1000_RCTL_VFE; 5265 } else { 5266 igb_vlan_promisc_disable(adapter); 5267 } 5268 5269 /* update state of unicast, multicast, and VLAN filtering modes */ 5270 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5271 E1000_RCTL_VFE); 5272 wr32(E1000_RCTL, rctl); 5273 5274 #if (PAGE_SIZE < 8192) 5275 if (!adapter->vfs_allocated_count) { 5276 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5277 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5278 } 5279 #endif 5280 wr32(E1000_RLPML, rlpml); 5281 5282 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5283 * the VMOLR to enable the appropriate modes. Without this workaround 5284 * we will have issues with VLAN tag stripping not being done for frames 5285 * that are only arriving because we are the default pool 5286 */ 5287 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5288 return; 5289 5290 /* set UTA to appropriate mode */ 5291 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5292 5293 vmolr |= rd32(E1000_VMOLR(vfn)) & 5294 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5295 5296 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5297 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5298 #if (PAGE_SIZE < 8192) 5299 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5300 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5301 else 5302 #endif 5303 vmolr |= MAX_JUMBO_FRAME_SIZE; 5304 vmolr |= E1000_VMOLR_LPE; 5305 5306 wr32(E1000_VMOLR(vfn), vmolr); 5307 5308 igb_restore_vf_multicasts(adapter); 5309 } 5310 5311 static void igb_check_wvbr(struct igb_adapter *adapter) 5312 { 5313 struct e1000_hw *hw = &adapter->hw; 5314 u32 wvbr = 0; 5315 5316 switch (hw->mac.type) { 5317 case e1000_82576: 5318 case e1000_i350: 5319 wvbr = rd32(E1000_WVBR); 5320 if (!wvbr) 5321 return; 5322 break; 5323 default: 5324 break; 5325 } 5326 5327 adapter->wvbr |= wvbr; 5328 } 5329 5330 #define IGB_STAGGERED_QUEUE_OFFSET 8 5331 5332 static void igb_spoof_check(struct igb_adapter *adapter) 5333 { 5334 int j; 5335 5336 if (!adapter->wvbr) 5337 return; 5338 5339 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5340 if (adapter->wvbr & BIT(j) || 5341 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5342 dev_warn(&adapter->pdev->dev, 5343 "Spoof event(s) detected on VF %d\n", j); 5344 adapter->wvbr &= 5345 ~(BIT(j) | 5346 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5347 } 5348 } 5349 } 5350 5351 /* Need to wait a few seconds after link up to get diagnostic information from 5352 * the phy 5353 */ 5354 static void igb_update_phy_info(struct timer_list *t) 5355 { 5356 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5357 igb_get_phy_info(&adapter->hw); 5358 } 5359 5360 /** 5361 * igb_has_link - check shared code for link and determine up/down 5362 * @adapter: pointer to driver private info 5363 **/ 5364 bool igb_has_link(struct igb_adapter *adapter) 5365 { 5366 struct e1000_hw *hw = &adapter->hw; 5367 bool link_active = false; 5368 5369 /* get_link_status is set on LSC (link status) interrupt or 5370 * rx sequence error interrupt. get_link_status will stay 5371 * false until the e1000_check_for_link establishes link 5372 * for copper adapters ONLY 5373 */ 5374 switch (hw->phy.media_type) { 5375 case e1000_media_type_copper: 5376 if (!hw->mac.get_link_status) 5377 return true; 5378 fallthrough; 5379 case e1000_media_type_internal_serdes: 5380 hw->mac.ops.check_for_link(hw); 5381 link_active = !hw->mac.get_link_status; 5382 break; 5383 default: 5384 case e1000_media_type_unknown: 5385 break; 5386 } 5387 5388 if (((hw->mac.type == e1000_i210) || 5389 (hw->mac.type == e1000_i211)) && 5390 (hw->phy.id == I210_I_PHY_ID)) { 5391 if (!netif_carrier_ok(adapter->netdev)) { 5392 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5393 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5394 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5395 adapter->link_check_timeout = jiffies; 5396 } 5397 } 5398 5399 return link_active; 5400 } 5401 5402 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5403 { 5404 bool ret = false; 5405 u32 ctrl_ext, thstat; 5406 5407 /* check for thermal sensor event on i350 copper only */ 5408 if (hw->mac.type == e1000_i350) { 5409 thstat = rd32(E1000_THSTAT); 5410 ctrl_ext = rd32(E1000_CTRL_EXT); 5411 5412 if ((hw->phy.media_type == e1000_media_type_copper) && 5413 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5414 ret = !!(thstat & event); 5415 } 5416 5417 return ret; 5418 } 5419 5420 /** 5421 * igb_check_lvmmc - check for malformed packets received 5422 * and indicated in LVMMC register 5423 * @adapter: pointer to adapter 5424 **/ 5425 static void igb_check_lvmmc(struct igb_adapter *adapter) 5426 { 5427 struct e1000_hw *hw = &adapter->hw; 5428 u32 lvmmc; 5429 5430 lvmmc = rd32(E1000_LVMMC); 5431 if (lvmmc) { 5432 if (unlikely(net_ratelimit())) { 5433 netdev_warn(adapter->netdev, 5434 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5435 lvmmc); 5436 } 5437 } 5438 } 5439 5440 /** 5441 * igb_watchdog - Timer Call-back 5442 * @t: pointer to timer_list containing our private info pointer 5443 **/ 5444 static void igb_watchdog(struct timer_list *t) 5445 { 5446 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5447 /* Do the rest outside of interrupt context */ 5448 schedule_work(&adapter->watchdog_task); 5449 } 5450 5451 static void igb_watchdog_task(struct work_struct *work) 5452 { 5453 struct igb_adapter *adapter = container_of(work, 5454 struct igb_adapter, 5455 watchdog_task); 5456 struct e1000_hw *hw = &adapter->hw; 5457 struct e1000_phy_info *phy = &hw->phy; 5458 struct net_device *netdev = adapter->netdev; 5459 u32 link; 5460 int i; 5461 u32 connsw; 5462 u16 phy_data, retry_count = 20; 5463 5464 link = igb_has_link(adapter); 5465 5466 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5467 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5468 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5469 else 5470 link = false; 5471 } 5472 5473 /* Force link down if we have fiber to swap to */ 5474 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5475 if (hw->phy.media_type == e1000_media_type_copper) { 5476 connsw = rd32(E1000_CONNSW); 5477 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5478 link = 0; 5479 } 5480 } 5481 if (link) { 5482 /* Perform a reset if the media type changed. */ 5483 if (hw->dev_spec._82575.media_changed) { 5484 hw->dev_spec._82575.media_changed = false; 5485 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5486 igb_reset(adapter); 5487 } 5488 /* Cancel scheduled suspend requests. */ 5489 pm_runtime_resume(netdev->dev.parent); 5490 5491 if (!netif_carrier_ok(netdev)) { 5492 u32 ctrl; 5493 5494 hw->mac.ops.get_speed_and_duplex(hw, 5495 &adapter->link_speed, 5496 &adapter->link_duplex); 5497 5498 ctrl = rd32(E1000_CTRL); 5499 /* Links status message must follow this format */ 5500 netdev_info(netdev, 5501 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5502 netdev->name, 5503 adapter->link_speed, 5504 adapter->link_duplex == FULL_DUPLEX ? 5505 "Full" : "Half", 5506 (ctrl & E1000_CTRL_TFCE) && 5507 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5508 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5509 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5510 5511 /* disable EEE if enabled */ 5512 if ((adapter->flags & IGB_FLAG_EEE) && 5513 (adapter->link_duplex == HALF_DUPLEX)) { 5514 dev_info(&adapter->pdev->dev, 5515 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5516 adapter->hw.dev_spec._82575.eee_disable = true; 5517 adapter->flags &= ~IGB_FLAG_EEE; 5518 } 5519 5520 /* check if SmartSpeed worked */ 5521 igb_check_downshift(hw); 5522 if (phy->speed_downgraded) 5523 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5524 5525 /* check for thermal sensor event */ 5526 if (igb_thermal_sensor_event(hw, 5527 E1000_THSTAT_LINK_THROTTLE)) 5528 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5529 5530 /* adjust timeout factor according to speed/duplex */ 5531 adapter->tx_timeout_factor = 1; 5532 switch (adapter->link_speed) { 5533 case SPEED_10: 5534 adapter->tx_timeout_factor = 14; 5535 break; 5536 case SPEED_100: 5537 /* maybe add some timeout factor ? */ 5538 break; 5539 } 5540 5541 if (adapter->link_speed != SPEED_1000 || 5542 !hw->phy.ops.read_reg) 5543 goto no_wait; 5544 5545 /* wait for Remote receiver status OK */ 5546 retry_read_status: 5547 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5548 &phy_data)) { 5549 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5550 retry_count) { 5551 msleep(100); 5552 retry_count--; 5553 goto retry_read_status; 5554 } else if (!retry_count) { 5555 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5556 } 5557 } else { 5558 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5559 } 5560 no_wait: 5561 netif_carrier_on(netdev); 5562 5563 igb_ping_all_vfs(adapter); 5564 igb_check_vf_rate_limit(adapter); 5565 5566 /* link state has changed, schedule phy info update */ 5567 if (!test_bit(__IGB_DOWN, &adapter->state)) 5568 mod_timer(&adapter->phy_info_timer, 5569 round_jiffies(jiffies + 2 * HZ)); 5570 } 5571 } else { 5572 if (netif_carrier_ok(netdev)) { 5573 adapter->link_speed = 0; 5574 adapter->link_duplex = 0; 5575 5576 /* check for thermal sensor event */ 5577 if (igb_thermal_sensor_event(hw, 5578 E1000_THSTAT_PWR_DOWN)) { 5579 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5580 } 5581 5582 /* Links status message must follow this format */ 5583 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5584 netdev->name); 5585 netif_carrier_off(netdev); 5586 5587 igb_ping_all_vfs(adapter); 5588 5589 /* link state has changed, schedule phy info update */ 5590 if (!test_bit(__IGB_DOWN, &adapter->state)) 5591 mod_timer(&adapter->phy_info_timer, 5592 round_jiffies(jiffies + 2 * HZ)); 5593 5594 /* link is down, time to check for alternate media */ 5595 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5596 igb_check_swap_media(adapter); 5597 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5598 schedule_work(&adapter->reset_task); 5599 /* return immediately */ 5600 return; 5601 } 5602 } 5603 pm_schedule_suspend(netdev->dev.parent, 5604 MSEC_PER_SEC * 5); 5605 5606 /* also check for alternate media here */ 5607 } else if (!netif_carrier_ok(netdev) && 5608 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5609 igb_check_swap_media(adapter); 5610 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5611 schedule_work(&adapter->reset_task); 5612 /* return immediately */ 5613 return; 5614 } 5615 } 5616 } 5617 5618 spin_lock(&adapter->stats64_lock); 5619 igb_update_stats(adapter); 5620 spin_unlock(&adapter->stats64_lock); 5621 5622 for (i = 0; i < adapter->num_tx_queues; i++) { 5623 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5624 if (!netif_carrier_ok(netdev)) { 5625 /* We've lost link, so the controller stops DMA, 5626 * but we've got queued Tx work that's never going 5627 * to get done, so reset controller to flush Tx. 5628 * (Do the reset outside of interrupt context). 5629 */ 5630 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5631 adapter->tx_timeout_count++; 5632 schedule_work(&adapter->reset_task); 5633 /* return immediately since reset is imminent */ 5634 return; 5635 } 5636 } 5637 5638 /* Force detection of hung controller every watchdog period */ 5639 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5640 } 5641 5642 /* Cause software interrupt to ensure Rx ring is cleaned */ 5643 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5644 u32 eics = 0; 5645 5646 for (i = 0; i < adapter->num_q_vectors; i++) 5647 eics |= adapter->q_vector[i]->eims_value; 5648 wr32(E1000_EICS, eics); 5649 } else { 5650 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5651 } 5652 5653 igb_spoof_check(adapter); 5654 igb_ptp_rx_hang(adapter); 5655 igb_ptp_tx_hang(adapter); 5656 5657 /* Check LVMMC register on i350/i354 only */ 5658 if ((adapter->hw.mac.type == e1000_i350) || 5659 (adapter->hw.mac.type == e1000_i354)) 5660 igb_check_lvmmc(adapter); 5661 5662 /* Reset the timer */ 5663 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5664 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5665 mod_timer(&adapter->watchdog_timer, 5666 round_jiffies(jiffies + HZ)); 5667 else 5668 mod_timer(&adapter->watchdog_timer, 5669 round_jiffies(jiffies + 2 * HZ)); 5670 } 5671 } 5672 5673 enum latency_range { 5674 lowest_latency = 0, 5675 low_latency = 1, 5676 bulk_latency = 2, 5677 latency_invalid = 255 5678 }; 5679 5680 /** 5681 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5682 * @q_vector: pointer to q_vector 5683 * 5684 * Stores a new ITR value based on strictly on packet size. This 5685 * algorithm is less sophisticated than that used in igb_update_itr, 5686 * due to the difficulty of synchronizing statistics across multiple 5687 * receive rings. The divisors and thresholds used by this function 5688 * were determined based on theoretical maximum wire speed and testing 5689 * data, in order to minimize response time while increasing bulk 5690 * throughput. 5691 * This functionality is controlled by ethtool's coalescing settings. 5692 * NOTE: This function is called only when operating in a multiqueue 5693 * receive environment. 5694 **/ 5695 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5696 { 5697 int new_val = q_vector->itr_val; 5698 int avg_wire_size = 0; 5699 struct igb_adapter *adapter = q_vector->adapter; 5700 unsigned int packets; 5701 5702 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5703 * ints/sec - ITR timer value of 120 ticks. 5704 */ 5705 if (adapter->link_speed != SPEED_1000) { 5706 new_val = IGB_4K_ITR; 5707 goto set_itr_val; 5708 } 5709 5710 packets = q_vector->rx.total_packets; 5711 if (packets) 5712 avg_wire_size = q_vector->rx.total_bytes / packets; 5713 5714 packets = q_vector->tx.total_packets; 5715 if (packets) 5716 avg_wire_size = max_t(u32, avg_wire_size, 5717 q_vector->tx.total_bytes / packets); 5718 5719 /* if avg_wire_size isn't set no work was done */ 5720 if (!avg_wire_size) 5721 goto clear_counts; 5722 5723 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5724 avg_wire_size += 24; 5725 5726 /* Don't starve jumbo frames */ 5727 avg_wire_size = min(avg_wire_size, 3000); 5728 5729 /* Give a little boost to mid-size frames */ 5730 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5731 new_val = avg_wire_size / 3; 5732 else 5733 new_val = avg_wire_size / 2; 5734 5735 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5736 if (new_val < IGB_20K_ITR && 5737 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5738 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5739 new_val = IGB_20K_ITR; 5740 5741 set_itr_val: 5742 if (new_val != q_vector->itr_val) { 5743 q_vector->itr_val = new_val; 5744 q_vector->set_itr = 1; 5745 } 5746 clear_counts: 5747 q_vector->rx.total_bytes = 0; 5748 q_vector->rx.total_packets = 0; 5749 q_vector->tx.total_bytes = 0; 5750 q_vector->tx.total_packets = 0; 5751 } 5752 5753 /** 5754 * igb_update_itr - update the dynamic ITR value based on statistics 5755 * @q_vector: pointer to q_vector 5756 * @ring_container: ring info to update the itr for 5757 * 5758 * Stores a new ITR value based on packets and byte 5759 * counts during the last interrupt. The advantage of per interrupt 5760 * computation is faster updates and more accurate ITR for the current 5761 * traffic pattern. Constants in this function were computed 5762 * based on theoretical maximum wire speed and thresholds were set based 5763 * on testing data as well as attempting to minimize response time 5764 * while increasing bulk throughput. 5765 * This functionality is controlled by ethtool's coalescing settings. 5766 * NOTE: These calculations are only valid when operating in a single- 5767 * queue environment. 5768 **/ 5769 static void igb_update_itr(struct igb_q_vector *q_vector, 5770 struct igb_ring_container *ring_container) 5771 { 5772 unsigned int packets = ring_container->total_packets; 5773 unsigned int bytes = ring_container->total_bytes; 5774 u8 itrval = ring_container->itr; 5775 5776 /* no packets, exit with status unchanged */ 5777 if (packets == 0) 5778 return; 5779 5780 switch (itrval) { 5781 case lowest_latency: 5782 /* handle TSO and jumbo frames */ 5783 if (bytes/packets > 8000) 5784 itrval = bulk_latency; 5785 else if ((packets < 5) && (bytes > 512)) 5786 itrval = low_latency; 5787 break; 5788 case low_latency: /* 50 usec aka 20000 ints/s */ 5789 if (bytes > 10000) { 5790 /* this if handles the TSO accounting */ 5791 if (bytes/packets > 8000) 5792 itrval = bulk_latency; 5793 else if ((packets < 10) || ((bytes/packets) > 1200)) 5794 itrval = bulk_latency; 5795 else if ((packets > 35)) 5796 itrval = lowest_latency; 5797 } else if (bytes/packets > 2000) { 5798 itrval = bulk_latency; 5799 } else if (packets <= 2 && bytes < 512) { 5800 itrval = lowest_latency; 5801 } 5802 break; 5803 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5804 if (bytes > 25000) { 5805 if (packets > 35) 5806 itrval = low_latency; 5807 } else if (bytes < 1500) { 5808 itrval = low_latency; 5809 } 5810 break; 5811 } 5812 5813 /* clear work counters since we have the values we need */ 5814 ring_container->total_bytes = 0; 5815 ring_container->total_packets = 0; 5816 5817 /* write updated itr to ring container */ 5818 ring_container->itr = itrval; 5819 } 5820 5821 static void igb_set_itr(struct igb_q_vector *q_vector) 5822 { 5823 struct igb_adapter *adapter = q_vector->adapter; 5824 u32 new_itr = q_vector->itr_val; 5825 u8 current_itr = 0; 5826 5827 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5828 if (adapter->link_speed != SPEED_1000) { 5829 current_itr = 0; 5830 new_itr = IGB_4K_ITR; 5831 goto set_itr_now; 5832 } 5833 5834 igb_update_itr(q_vector, &q_vector->tx); 5835 igb_update_itr(q_vector, &q_vector->rx); 5836 5837 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5838 5839 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5840 if (current_itr == lowest_latency && 5841 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5842 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5843 current_itr = low_latency; 5844 5845 switch (current_itr) { 5846 /* counts and packets in update_itr are dependent on these numbers */ 5847 case lowest_latency: 5848 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5849 break; 5850 case low_latency: 5851 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5852 break; 5853 case bulk_latency: 5854 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5855 break; 5856 default: 5857 break; 5858 } 5859 5860 set_itr_now: 5861 if (new_itr != q_vector->itr_val) { 5862 /* this attempts to bias the interrupt rate towards Bulk 5863 * by adding intermediate steps when interrupt rate is 5864 * increasing 5865 */ 5866 new_itr = new_itr > q_vector->itr_val ? 5867 max((new_itr * q_vector->itr_val) / 5868 (new_itr + (q_vector->itr_val >> 2)), 5869 new_itr) : new_itr; 5870 /* Don't write the value here; it resets the adapter's 5871 * internal timer, and causes us to delay far longer than 5872 * we should between interrupts. Instead, we write the ITR 5873 * value at the beginning of the next interrupt so the timing 5874 * ends up being correct. 5875 */ 5876 q_vector->itr_val = new_itr; 5877 q_vector->set_itr = 1; 5878 } 5879 } 5880 5881 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 5882 struct igb_tx_buffer *first, 5883 u32 vlan_macip_lens, u32 type_tucmd, 5884 u32 mss_l4len_idx) 5885 { 5886 struct e1000_adv_tx_context_desc *context_desc; 5887 u16 i = tx_ring->next_to_use; 5888 struct timespec64 ts; 5889 5890 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5891 5892 i++; 5893 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 5894 5895 /* set bits to identify this as an advanced context descriptor */ 5896 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 5897 5898 /* For 82575, context index must be unique per ring. */ 5899 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5900 mss_l4len_idx |= tx_ring->reg_idx << 4; 5901 5902 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5903 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5904 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5905 5906 /* We assume there is always a valid tx time available. Invalid times 5907 * should have been handled by the upper layers. 5908 */ 5909 if (tx_ring->launchtime_enable) { 5910 ts = ktime_to_timespec64(first->skb->tstamp); 5911 skb_txtime_consumed(first->skb); 5912 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 5913 } else { 5914 context_desc->seqnum_seed = 0; 5915 } 5916 } 5917 5918 static int igb_tso(struct igb_ring *tx_ring, 5919 struct igb_tx_buffer *first, 5920 u8 *hdr_len) 5921 { 5922 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 5923 struct sk_buff *skb = first->skb; 5924 union { 5925 struct iphdr *v4; 5926 struct ipv6hdr *v6; 5927 unsigned char *hdr; 5928 } ip; 5929 union { 5930 struct tcphdr *tcp; 5931 struct udphdr *udp; 5932 unsigned char *hdr; 5933 } l4; 5934 u32 paylen, l4_offset; 5935 int err; 5936 5937 if (skb->ip_summed != CHECKSUM_PARTIAL) 5938 return 0; 5939 5940 if (!skb_is_gso(skb)) 5941 return 0; 5942 5943 err = skb_cow_head(skb, 0); 5944 if (err < 0) 5945 return err; 5946 5947 ip.hdr = skb_network_header(skb); 5948 l4.hdr = skb_checksum_start(skb); 5949 5950 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 5951 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 5952 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP; 5953 5954 /* initialize outer IP header fields */ 5955 if (ip.v4->version == 4) { 5956 unsigned char *csum_start = skb_checksum_start(skb); 5957 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 5958 5959 /* IP header will have to cancel out any data that 5960 * is not a part of the outer IP header 5961 */ 5962 ip.v4->check = csum_fold(csum_partial(trans_start, 5963 csum_start - trans_start, 5964 0)); 5965 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 5966 5967 ip.v4->tot_len = 0; 5968 first->tx_flags |= IGB_TX_FLAGS_TSO | 5969 IGB_TX_FLAGS_CSUM | 5970 IGB_TX_FLAGS_IPV4; 5971 } else { 5972 ip.v6->payload_len = 0; 5973 first->tx_flags |= IGB_TX_FLAGS_TSO | 5974 IGB_TX_FLAGS_CSUM; 5975 } 5976 5977 /* determine offset of inner transport header */ 5978 l4_offset = l4.hdr - skb->data; 5979 5980 /* remove payload length from inner checksum */ 5981 paylen = skb->len - l4_offset; 5982 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) { 5983 /* compute length of segmentation header */ 5984 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 5985 csum_replace_by_diff(&l4.tcp->check, 5986 (__force __wsum)htonl(paylen)); 5987 } else { 5988 /* compute length of segmentation header */ 5989 *hdr_len = sizeof(*l4.udp) + l4_offset; 5990 csum_replace_by_diff(&l4.udp->check, 5991 (__force __wsum)htonl(paylen)); 5992 } 5993 5994 /* update gso size and bytecount with header size */ 5995 first->gso_segs = skb_shinfo(skb)->gso_segs; 5996 first->bytecount += (first->gso_segs - 1) * *hdr_len; 5997 5998 /* MSS L4LEN IDX */ 5999 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 6000 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 6001 6002 /* VLAN MACLEN IPLEN */ 6003 vlan_macip_lens = l4.hdr - ip.hdr; 6004 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 6005 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6006 6007 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 6008 type_tucmd, mss_l4len_idx); 6009 6010 return 1; 6011 } 6012 6013 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 6014 { 6015 struct sk_buff *skb = first->skb; 6016 u32 vlan_macip_lens = 0; 6017 u32 type_tucmd = 0; 6018 6019 if (skb->ip_summed != CHECKSUM_PARTIAL) { 6020 csum_failed: 6021 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 6022 !tx_ring->launchtime_enable) 6023 return; 6024 goto no_csum; 6025 } 6026 6027 switch (skb->csum_offset) { 6028 case offsetof(struct tcphdr, check): 6029 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 6030 fallthrough; 6031 case offsetof(struct udphdr, check): 6032 break; 6033 case offsetof(struct sctphdr, checksum): 6034 /* validate that this is actually an SCTP request */ 6035 if (skb_csum_is_sctp(skb)) { 6036 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 6037 break; 6038 } 6039 fallthrough; 6040 default: 6041 skb_checksum_help(skb); 6042 goto csum_failed; 6043 } 6044 6045 /* update TX checksum flag */ 6046 first->tx_flags |= IGB_TX_FLAGS_CSUM; 6047 vlan_macip_lens = skb_checksum_start_offset(skb) - 6048 skb_network_offset(skb); 6049 no_csum: 6050 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 6051 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6052 6053 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 6054 } 6055 6056 #define IGB_SET_FLAG(_input, _flag, _result) \ 6057 ((_flag <= _result) ? \ 6058 ((u32)(_input & _flag) * (_result / _flag)) : \ 6059 ((u32)(_input & _flag) / (_flag / _result))) 6060 6061 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6062 { 6063 /* set type for advanced descriptor with frame checksum insertion */ 6064 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 6065 E1000_ADVTXD_DCMD_DEXT | 6066 E1000_ADVTXD_DCMD_IFCS; 6067 6068 /* set HW vlan bit if vlan is present */ 6069 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 6070 (E1000_ADVTXD_DCMD_VLE)); 6071 6072 /* set segmentation bits for TSO */ 6073 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 6074 (E1000_ADVTXD_DCMD_TSE)); 6075 6076 /* set timestamp bit if present */ 6077 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 6078 (E1000_ADVTXD_MAC_TSTAMP)); 6079 6080 /* insert frame checksum */ 6081 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 6082 6083 return cmd_type; 6084 } 6085 6086 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 6087 union e1000_adv_tx_desc *tx_desc, 6088 u32 tx_flags, unsigned int paylen) 6089 { 6090 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 6091 6092 /* 82575 requires a unique index per ring */ 6093 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6094 olinfo_status |= tx_ring->reg_idx << 4; 6095 6096 /* insert L4 checksum */ 6097 olinfo_status |= IGB_SET_FLAG(tx_flags, 6098 IGB_TX_FLAGS_CSUM, 6099 (E1000_TXD_POPTS_TXSM << 8)); 6100 6101 /* insert IPv4 checksum */ 6102 olinfo_status |= IGB_SET_FLAG(tx_flags, 6103 IGB_TX_FLAGS_IPV4, 6104 (E1000_TXD_POPTS_IXSM << 8)); 6105 6106 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6107 } 6108 6109 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6110 { 6111 struct net_device *netdev = tx_ring->netdev; 6112 6113 netif_stop_subqueue(netdev, tx_ring->queue_index); 6114 6115 /* Herbert's original patch had: 6116 * smp_mb__after_netif_stop_queue(); 6117 * but since that doesn't exist yet, just open code it. 6118 */ 6119 smp_mb(); 6120 6121 /* We need to check again in a case another CPU has just 6122 * made room available. 6123 */ 6124 if (igb_desc_unused(tx_ring) < size) 6125 return -EBUSY; 6126 6127 /* A reprieve! */ 6128 netif_wake_subqueue(netdev, tx_ring->queue_index); 6129 6130 u64_stats_update_begin(&tx_ring->tx_syncp2); 6131 tx_ring->tx_stats.restart_queue2++; 6132 u64_stats_update_end(&tx_ring->tx_syncp2); 6133 6134 return 0; 6135 } 6136 6137 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6138 { 6139 if (igb_desc_unused(tx_ring) >= size) 6140 return 0; 6141 return __igb_maybe_stop_tx(tx_ring, size); 6142 } 6143 6144 static int igb_tx_map(struct igb_ring *tx_ring, 6145 struct igb_tx_buffer *first, 6146 const u8 hdr_len) 6147 { 6148 struct sk_buff *skb = first->skb; 6149 struct igb_tx_buffer *tx_buffer; 6150 union e1000_adv_tx_desc *tx_desc; 6151 skb_frag_t *frag; 6152 dma_addr_t dma; 6153 unsigned int data_len, size; 6154 u32 tx_flags = first->tx_flags; 6155 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 6156 u16 i = tx_ring->next_to_use; 6157 6158 tx_desc = IGB_TX_DESC(tx_ring, i); 6159 6160 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 6161 6162 size = skb_headlen(skb); 6163 data_len = skb->data_len; 6164 6165 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6166 6167 tx_buffer = first; 6168 6169 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6170 if (dma_mapping_error(tx_ring->dev, dma)) 6171 goto dma_error; 6172 6173 /* record length, and DMA address */ 6174 dma_unmap_len_set(tx_buffer, len, size); 6175 dma_unmap_addr_set(tx_buffer, dma, dma); 6176 6177 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6178 6179 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 6180 tx_desc->read.cmd_type_len = 6181 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 6182 6183 i++; 6184 tx_desc++; 6185 if (i == tx_ring->count) { 6186 tx_desc = IGB_TX_DESC(tx_ring, 0); 6187 i = 0; 6188 } 6189 tx_desc->read.olinfo_status = 0; 6190 6191 dma += IGB_MAX_DATA_PER_TXD; 6192 size -= IGB_MAX_DATA_PER_TXD; 6193 6194 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6195 } 6196 6197 if (likely(!data_len)) 6198 break; 6199 6200 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6201 6202 i++; 6203 tx_desc++; 6204 if (i == tx_ring->count) { 6205 tx_desc = IGB_TX_DESC(tx_ring, 0); 6206 i = 0; 6207 } 6208 tx_desc->read.olinfo_status = 0; 6209 6210 size = skb_frag_size(frag); 6211 data_len -= size; 6212 6213 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6214 size, DMA_TO_DEVICE); 6215 6216 tx_buffer = &tx_ring->tx_buffer_info[i]; 6217 } 6218 6219 /* write last descriptor with RS and EOP bits */ 6220 cmd_type |= size | IGB_TXD_DCMD; 6221 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6222 6223 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6224 6225 /* set the timestamp */ 6226 first->time_stamp = jiffies; 6227 6228 skb_tx_timestamp(skb); 6229 6230 /* Force memory writes to complete before letting h/w know there 6231 * are new descriptors to fetch. (Only applicable for weak-ordered 6232 * memory model archs, such as IA-64). 6233 * 6234 * We also need this memory barrier to make certain all of the 6235 * status bits have been updated before next_to_watch is written. 6236 */ 6237 dma_wmb(); 6238 6239 /* set next_to_watch value indicating a packet is present */ 6240 first->next_to_watch = tx_desc; 6241 6242 i++; 6243 if (i == tx_ring->count) 6244 i = 0; 6245 6246 tx_ring->next_to_use = i; 6247 6248 /* Make sure there is space in the ring for the next send. */ 6249 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6250 6251 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6252 writel(i, tx_ring->tail); 6253 } 6254 return 0; 6255 6256 dma_error: 6257 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6258 tx_buffer = &tx_ring->tx_buffer_info[i]; 6259 6260 /* clear dma mappings for failed tx_buffer_info map */ 6261 while (tx_buffer != first) { 6262 if (dma_unmap_len(tx_buffer, len)) 6263 dma_unmap_page(tx_ring->dev, 6264 dma_unmap_addr(tx_buffer, dma), 6265 dma_unmap_len(tx_buffer, len), 6266 DMA_TO_DEVICE); 6267 dma_unmap_len_set(tx_buffer, len, 0); 6268 6269 if (i-- == 0) 6270 i += tx_ring->count; 6271 tx_buffer = &tx_ring->tx_buffer_info[i]; 6272 } 6273 6274 if (dma_unmap_len(tx_buffer, len)) 6275 dma_unmap_single(tx_ring->dev, 6276 dma_unmap_addr(tx_buffer, dma), 6277 dma_unmap_len(tx_buffer, len), 6278 DMA_TO_DEVICE); 6279 dma_unmap_len_set(tx_buffer, len, 0); 6280 6281 dev_kfree_skb_any(tx_buffer->skb); 6282 tx_buffer->skb = NULL; 6283 6284 tx_ring->next_to_use = i; 6285 6286 return -1; 6287 } 6288 6289 int igb_xmit_xdp_ring(struct igb_adapter *adapter, 6290 struct igb_ring *tx_ring, 6291 struct xdp_frame *xdpf) 6292 { 6293 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 6294 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 6295 u16 count, i, index = tx_ring->next_to_use; 6296 struct igb_tx_buffer *tx_head = &tx_ring->tx_buffer_info[index]; 6297 struct igb_tx_buffer *tx_buffer = tx_head; 6298 union e1000_adv_tx_desc *tx_desc = IGB_TX_DESC(tx_ring, index); 6299 u32 len = xdpf->len, cmd_type, olinfo_status; 6300 void *data = xdpf->data; 6301 6302 count = TXD_USE_COUNT(len); 6303 for (i = 0; i < nr_frags; i++) 6304 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i])); 6305 6306 if (igb_maybe_stop_tx(tx_ring, count + 3)) 6307 return IGB_XDP_CONSUMED; 6308 6309 i = 0; 6310 /* record the location of the first descriptor for this packet */ 6311 tx_head->bytecount = xdp_get_frame_len(xdpf); 6312 tx_head->type = IGB_TYPE_XDP; 6313 tx_head->gso_segs = 1; 6314 tx_head->xdpf = xdpf; 6315 6316 olinfo_status = tx_head->bytecount << E1000_ADVTXD_PAYLEN_SHIFT; 6317 /* 82575 requires a unique index per ring */ 6318 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6319 olinfo_status |= tx_ring->reg_idx << 4; 6320 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6321 6322 for (;;) { 6323 dma_addr_t dma; 6324 6325 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE); 6326 if (dma_mapping_error(tx_ring->dev, dma)) 6327 goto unmap; 6328 6329 /* record length, and DMA address */ 6330 dma_unmap_len_set(tx_buffer, len, len); 6331 dma_unmap_addr_set(tx_buffer, dma, dma); 6332 6333 /* put descriptor type bits */ 6334 cmd_type = E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_DEXT | 6335 E1000_ADVTXD_DCMD_IFCS | len; 6336 6337 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6338 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6339 6340 tx_buffer->protocol = 0; 6341 6342 if (++index == tx_ring->count) 6343 index = 0; 6344 6345 if (i == nr_frags) 6346 break; 6347 6348 tx_buffer = &tx_ring->tx_buffer_info[index]; 6349 tx_desc = IGB_TX_DESC(tx_ring, index); 6350 tx_desc->read.olinfo_status = 0; 6351 6352 data = skb_frag_address(&sinfo->frags[i]); 6353 len = skb_frag_size(&sinfo->frags[i]); 6354 i++; 6355 } 6356 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_TXD_DCMD); 6357 6358 netdev_tx_sent_queue(txring_txq(tx_ring), tx_head->bytecount); 6359 /* set the timestamp */ 6360 tx_head->time_stamp = jiffies; 6361 6362 /* Avoid any potential race with xdp_xmit and cleanup */ 6363 smp_wmb(); 6364 6365 /* set next_to_watch value indicating a packet is present */ 6366 tx_head->next_to_watch = tx_desc; 6367 tx_ring->next_to_use = index; 6368 6369 /* Make sure there is space in the ring for the next send. */ 6370 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6371 6372 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) 6373 writel(index, tx_ring->tail); 6374 6375 return IGB_XDP_TX; 6376 6377 unmap: 6378 for (;;) { 6379 tx_buffer = &tx_ring->tx_buffer_info[index]; 6380 if (dma_unmap_len(tx_buffer, len)) 6381 dma_unmap_page(tx_ring->dev, 6382 dma_unmap_addr(tx_buffer, dma), 6383 dma_unmap_len(tx_buffer, len), 6384 DMA_TO_DEVICE); 6385 dma_unmap_len_set(tx_buffer, len, 0); 6386 if (tx_buffer == tx_head) 6387 break; 6388 6389 if (!index) 6390 index += tx_ring->count; 6391 index--; 6392 } 6393 6394 return IGB_XDP_CONSUMED; 6395 } 6396 6397 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6398 struct igb_ring *tx_ring) 6399 { 6400 struct igb_tx_buffer *first; 6401 int tso; 6402 u32 tx_flags = 0; 6403 unsigned short f; 6404 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6405 __be16 protocol = vlan_get_protocol(skb); 6406 u8 hdr_len = 0; 6407 6408 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6409 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6410 * + 2 desc gap to keep tail from touching head, 6411 * + 1 desc for context descriptor, 6412 * otherwise try next time 6413 */ 6414 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6415 count += TXD_USE_COUNT(skb_frag_size( 6416 &skb_shinfo(skb)->frags[f])); 6417 6418 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6419 /* this is a hard error */ 6420 return NETDEV_TX_BUSY; 6421 } 6422 6423 /* record the location of the first descriptor for this packet */ 6424 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6425 first->type = IGB_TYPE_SKB; 6426 first->skb = skb; 6427 first->bytecount = skb->len; 6428 first->gso_segs = 1; 6429 6430 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6431 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6432 6433 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6434 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6435 &adapter->state)) { 6436 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6437 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6438 6439 adapter->ptp_tx_skb = skb_get(skb); 6440 adapter->ptp_tx_start = jiffies; 6441 if (adapter->hw.mac.type == e1000_82576) 6442 schedule_work(&adapter->ptp_tx_work); 6443 } else { 6444 adapter->tx_hwtstamp_skipped++; 6445 } 6446 } 6447 6448 if (skb_vlan_tag_present(skb)) { 6449 tx_flags |= IGB_TX_FLAGS_VLAN; 6450 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6451 } 6452 6453 /* record initial flags and protocol */ 6454 first->tx_flags = tx_flags; 6455 first->protocol = protocol; 6456 6457 tso = igb_tso(tx_ring, first, &hdr_len); 6458 if (tso < 0) 6459 goto out_drop; 6460 else if (!tso) 6461 igb_tx_csum(tx_ring, first); 6462 6463 if (igb_tx_map(tx_ring, first, hdr_len)) 6464 goto cleanup_tx_tstamp; 6465 6466 return NETDEV_TX_OK; 6467 6468 out_drop: 6469 dev_kfree_skb_any(first->skb); 6470 first->skb = NULL; 6471 cleanup_tx_tstamp: 6472 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6473 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6474 6475 dev_kfree_skb_any(adapter->ptp_tx_skb); 6476 adapter->ptp_tx_skb = NULL; 6477 if (adapter->hw.mac.type == e1000_82576) 6478 cancel_work_sync(&adapter->ptp_tx_work); 6479 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6480 } 6481 6482 return NETDEV_TX_OK; 6483 } 6484 6485 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6486 struct sk_buff *skb) 6487 { 6488 unsigned int r_idx = skb->queue_mapping; 6489 6490 if (r_idx >= adapter->num_tx_queues) 6491 r_idx = r_idx % adapter->num_tx_queues; 6492 6493 return adapter->tx_ring[r_idx]; 6494 } 6495 6496 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6497 struct net_device *netdev) 6498 { 6499 struct igb_adapter *adapter = netdev_priv(netdev); 6500 6501 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6502 * in order to meet this minimum size requirement. 6503 */ 6504 if (skb_put_padto(skb, 17)) 6505 return NETDEV_TX_OK; 6506 6507 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6508 } 6509 6510 /** 6511 * igb_tx_timeout - Respond to a Tx Hang 6512 * @netdev: network interface device structure 6513 * @txqueue: number of the Tx queue that hung (unused) 6514 **/ 6515 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6516 { 6517 struct igb_adapter *adapter = netdev_priv(netdev); 6518 struct e1000_hw *hw = &adapter->hw; 6519 6520 /* Do the reset outside of interrupt context */ 6521 adapter->tx_timeout_count++; 6522 6523 if (hw->mac.type >= e1000_82580) 6524 hw->dev_spec._82575.global_device_reset = true; 6525 6526 schedule_work(&adapter->reset_task); 6527 wr32(E1000_EICS, 6528 (adapter->eims_enable_mask & ~adapter->eims_other)); 6529 } 6530 6531 static void igb_reset_task(struct work_struct *work) 6532 { 6533 struct igb_adapter *adapter; 6534 adapter = container_of(work, struct igb_adapter, reset_task); 6535 6536 rtnl_lock(); 6537 /* If we're already down or resetting, just bail */ 6538 if (test_bit(__IGB_DOWN, &adapter->state) || 6539 test_bit(__IGB_RESETTING, &adapter->state)) { 6540 rtnl_unlock(); 6541 return; 6542 } 6543 6544 igb_dump(adapter); 6545 netdev_err(adapter->netdev, "Reset adapter\n"); 6546 igb_reinit_locked(adapter); 6547 rtnl_unlock(); 6548 } 6549 6550 /** 6551 * igb_get_stats64 - Get System Network Statistics 6552 * @netdev: network interface device structure 6553 * @stats: rtnl_link_stats64 pointer 6554 **/ 6555 static void igb_get_stats64(struct net_device *netdev, 6556 struct rtnl_link_stats64 *stats) 6557 { 6558 struct igb_adapter *adapter = netdev_priv(netdev); 6559 6560 spin_lock(&adapter->stats64_lock); 6561 igb_update_stats(adapter); 6562 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6563 spin_unlock(&adapter->stats64_lock); 6564 } 6565 6566 /** 6567 * igb_change_mtu - Change the Maximum Transfer Unit 6568 * @netdev: network interface device structure 6569 * @new_mtu: new value for maximum frame size 6570 * 6571 * Returns 0 on success, negative on failure 6572 **/ 6573 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6574 { 6575 struct igb_adapter *adapter = netdev_priv(netdev); 6576 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD; 6577 6578 if (adapter->xdp_prog) { 6579 int i; 6580 6581 for (i = 0; i < adapter->num_rx_queues; i++) { 6582 struct igb_ring *ring = adapter->rx_ring[i]; 6583 6584 if (max_frame > igb_rx_bufsz(ring)) { 6585 netdev_warn(adapter->netdev, 6586 "Requested MTU size is not supported with XDP. Max frame size is %d\n", 6587 max_frame); 6588 return -EINVAL; 6589 } 6590 } 6591 } 6592 6593 /* adjust max frame to be at least the size of a standard frame */ 6594 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6595 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6596 6597 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6598 usleep_range(1000, 2000); 6599 6600 /* igb_down has a dependency on max_frame_size */ 6601 adapter->max_frame_size = max_frame; 6602 6603 if (netif_running(netdev)) 6604 igb_down(adapter); 6605 6606 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6607 netdev->mtu, new_mtu); 6608 netdev->mtu = new_mtu; 6609 6610 if (netif_running(netdev)) 6611 igb_up(adapter); 6612 else 6613 igb_reset(adapter); 6614 6615 clear_bit(__IGB_RESETTING, &adapter->state); 6616 6617 return 0; 6618 } 6619 6620 /** 6621 * igb_update_stats - Update the board statistics counters 6622 * @adapter: board private structure 6623 **/ 6624 void igb_update_stats(struct igb_adapter *adapter) 6625 { 6626 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6627 struct e1000_hw *hw = &adapter->hw; 6628 struct pci_dev *pdev = adapter->pdev; 6629 u32 reg, mpc; 6630 int i; 6631 u64 bytes, packets; 6632 unsigned int start; 6633 u64 _bytes, _packets; 6634 6635 /* Prevent stats update while adapter is being reset, or if the pci 6636 * connection is down. 6637 */ 6638 if (adapter->link_speed == 0) 6639 return; 6640 if (pci_channel_offline(pdev)) 6641 return; 6642 6643 bytes = 0; 6644 packets = 0; 6645 6646 rcu_read_lock(); 6647 for (i = 0; i < adapter->num_rx_queues; i++) { 6648 struct igb_ring *ring = adapter->rx_ring[i]; 6649 u32 rqdpc = rd32(E1000_RQDPC(i)); 6650 if (hw->mac.type >= e1000_i210) 6651 wr32(E1000_RQDPC(i), 0); 6652 6653 if (rqdpc) { 6654 ring->rx_stats.drops += rqdpc; 6655 net_stats->rx_fifo_errors += rqdpc; 6656 } 6657 6658 do { 6659 start = u64_stats_fetch_begin(&ring->rx_syncp); 6660 _bytes = ring->rx_stats.bytes; 6661 _packets = ring->rx_stats.packets; 6662 } while (u64_stats_fetch_retry(&ring->rx_syncp, start)); 6663 bytes += _bytes; 6664 packets += _packets; 6665 } 6666 6667 net_stats->rx_bytes = bytes; 6668 net_stats->rx_packets = packets; 6669 6670 bytes = 0; 6671 packets = 0; 6672 for (i = 0; i < adapter->num_tx_queues; i++) { 6673 struct igb_ring *ring = adapter->tx_ring[i]; 6674 do { 6675 start = u64_stats_fetch_begin(&ring->tx_syncp); 6676 _bytes = ring->tx_stats.bytes; 6677 _packets = ring->tx_stats.packets; 6678 } while (u64_stats_fetch_retry(&ring->tx_syncp, start)); 6679 bytes += _bytes; 6680 packets += _packets; 6681 } 6682 net_stats->tx_bytes = bytes; 6683 net_stats->tx_packets = packets; 6684 rcu_read_unlock(); 6685 6686 /* read stats registers */ 6687 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6688 adapter->stats.gprc += rd32(E1000_GPRC); 6689 adapter->stats.gorc += rd32(E1000_GORCL); 6690 rd32(E1000_GORCH); /* clear GORCL */ 6691 adapter->stats.bprc += rd32(E1000_BPRC); 6692 adapter->stats.mprc += rd32(E1000_MPRC); 6693 adapter->stats.roc += rd32(E1000_ROC); 6694 6695 adapter->stats.prc64 += rd32(E1000_PRC64); 6696 adapter->stats.prc127 += rd32(E1000_PRC127); 6697 adapter->stats.prc255 += rd32(E1000_PRC255); 6698 adapter->stats.prc511 += rd32(E1000_PRC511); 6699 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6700 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6701 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6702 adapter->stats.sec += rd32(E1000_SEC); 6703 6704 mpc = rd32(E1000_MPC); 6705 adapter->stats.mpc += mpc; 6706 net_stats->rx_fifo_errors += mpc; 6707 adapter->stats.scc += rd32(E1000_SCC); 6708 adapter->stats.ecol += rd32(E1000_ECOL); 6709 adapter->stats.mcc += rd32(E1000_MCC); 6710 adapter->stats.latecol += rd32(E1000_LATECOL); 6711 adapter->stats.dc += rd32(E1000_DC); 6712 adapter->stats.rlec += rd32(E1000_RLEC); 6713 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6714 adapter->stats.xontxc += rd32(E1000_XONTXC); 6715 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6716 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6717 adapter->stats.fcruc += rd32(E1000_FCRUC); 6718 adapter->stats.gptc += rd32(E1000_GPTC); 6719 adapter->stats.gotc += rd32(E1000_GOTCL); 6720 rd32(E1000_GOTCH); /* clear GOTCL */ 6721 adapter->stats.rnbc += rd32(E1000_RNBC); 6722 adapter->stats.ruc += rd32(E1000_RUC); 6723 adapter->stats.rfc += rd32(E1000_RFC); 6724 adapter->stats.rjc += rd32(E1000_RJC); 6725 adapter->stats.tor += rd32(E1000_TORH); 6726 adapter->stats.tot += rd32(E1000_TOTH); 6727 adapter->stats.tpr += rd32(E1000_TPR); 6728 6729 adapter->stats.ptc64 += rd32(E1000_PTC64); 6730 adapter->stats.ptc127 += rd32(E1000_PTC127); 6731 adapter->stats.ptc255 += rd32(E1000_PTC255); 6732 adapter->stats.ptc511 += rd32(E1000_PTC511); 6733 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6734 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6735 6736 adapter->stats.mptc += rd32(E1000_MPTC); 6737 adapter->stats.bptc += rd32(E1000_BPTC); 6738 6739 adapter->stats.tpt += rd32(E1000_TPT); 6740 adapter->stats.colc += rd32(E1000_COLC); 6741 6742 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6743 /* read internal phy specific stats */ 6744 reg = rd32(E1000_CTRL_EXT); 6745 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6746 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6747 6748 /* this stat has invalid values on i210/i211 */ 6749 if ((hw->mac.type != e1000_i210) && 6750 (hw->mac.type != e1000_i211)) 6751 adapter->stats.tncrs += rd32(E1000_TNCRS); 6752 } 6753 6754 adapter->stats.tsctc += rd32(E1000_TSCTC); 6755 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6756 6757 adapter->stats.iac += rd32(E1000_IAC); 6758 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6759 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6760 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6761 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6762 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6763 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6764 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6765 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6766 6767 /* Fill out the OS statistics structure */ 6768 net_stats->multicast = adapter->stats.mprc; 6769 net_stats->collisions = adapter->stats.colc; 6770 6771 /* Rx Errors */ 6772 6773 /* RLEC on some newer hardware can be incorrect so build 6774 * our own version based on RUC and ROC 6775 */ 6776 net_stats->rx_errors = adapter->stats.rxerrc + 6777 adapter->stats.crcerrs + adapter->stats.algnerrc + 6778 adapter->stats.ruc + adapter->stats.roc + 6779 adapter->stats.cexterr; 6780 net_stats->rx_length_errors = adapter->stats.ruc + 6781 adapter->stats.roc; 6782 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6783 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6784 net_stats->rx_missed_errors = adapter->stats.mpc; 6785 6786 /* Tx Errors */ 6787 net_stats->tx_errors = adapter->stats.ecol + 6788 adapter->stats.latecol; 6789 net_stats->tx_aborted_errors = adapter->stats.ecol; 6790 net_stats->tx_window_errors = adapter->stats.latecol; 6791 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6792 6793 /* Tx Dropped needs to be maintained elsewhere */ 6794 6795 /* Management Stats */ 6796 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6797 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6798 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6799 6800 /* OS2BMC Stats */ 6801 reg = rd32(E1000_MANC); 6802 if (reg & E1000_MANC_EN_BMC2OS) { 6803 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6804 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6805 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6806 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6807 } 6808 } 6809 6810 static void igb_perout(struct igb_adapter *adapter, int tsintr_tt) 6811 { 6812 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_PEROUT, tsintr_tt); 6813 struct e1000_hw *hw = &adapter->hw; 6814 struct timespec64 ts; 6815 u32 tsauxc; 6816 6817 if (pin < 0 || pin >= IGB_N_PEROUT) 6818 return; 6819 6820 spin_lock(&adapter->tmreg_lock); 6821 6822 if (hw->mac.type == e1000_82580 || 6823 hw->mac.type == e1000_i354 || 6824 hw->mac.type == e1000_i350) { 6825 s64 ns = timespec64_to_ns(&adapter->perout[pin].period); 6826 u32 systiml, systimh, level_mask, level, rem; 6827 u64 systim, now; 6828 6829 /* read systim registers in sequence */ 6830 rd32(E1000_SYSTIMR); 6831 systiml = rd32(E1000_SYSTIML); 6832 systimh = rd32(E1000_SYSTIMH); 6833 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml); 6834 now = timecounter_cyc2time(&adapter->tc, systim); 6835 6836 if (pin < 2) { 6837 level_mask = (tsintr_tt == 1) ? 0x80000 : 0x40000; 6838 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0; 6839 } else { 6840 level_mask = (tsintr_tt == 1) ? 0x80 : 0x40; 6841 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0; 6842 } 6843 6844 div_u64_rem(now, ns, &rem); 6845 systim = systim + (ns - rem); 6846 6847 /* synchronize pin level with rising/falling edges */ 6848 div_u64_rem(now, ns << 1, &rem); 6849 if (rem < ns) { 6850 /* first half of period */ 6851 if (level == 0) { 6852 /* output is already low, skip this period */ 6853 systim += ns; 6854 pr_notice("igb: periodic output on %s missed falling edge\n", 6855 adapter->sdp_config[pin].name); 6856 } 6857 } else { 6858 /* second half of period */ 6859 if (level == 1) { 6860 /* output is already high, skip this period */ 6861 systim += ns; 6862 pr_notice("igb: periodic output on %s missed rising edge\n", 6863 adapter->sdp_config[pin].name); 6864 } 6865 } 6866 6867 /* for this chip family tv_sec is the upper part of the binary value, 6868 * so not seconds 6869 */ 6870 ts.tv_nsec = (u32)systim; 6871 ts.tv_sec = ((u32)(systim >> 32)) & 0xFF; 6872 } else { 6873 ts = timespec64_add(adapter->perout[pin].start, 6874 adapter->perout[pin].period); 6875 } 6876 6877 /* u32 conversion of tv_sec is safe until y2106 */ 6878 wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec); 6879 wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec); 6880 tsauxc = rd32(E1000_TSAUXC); 6881 tsauxc |= TSAUXC_EN_TT0; 6882 wr32(E1000_TSAUXC, tsauxc); 6883 adapter->perout[pin].start = ts; 6884 6885 spin_unlock(&adapter->tmreg_lock); 6886 } 6887 6888 static void igb_extts(struct igb_adapter *adapter, int tsintr_tt) 6889 { 6890 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_EXTTS, tsintr_tt); 6891 int auxstmpl = (tsintr_tt == 1) ? E1000_AUXSTMPL1 : E1000_AUXSTMPL0; 6892 int auxstmph = (tsintr_tt == 1) ? E1000_AUXSTMPH1 : E1000_AUXSTMPH0; 6893 struct e1000_hw *hw = &adapter->hw; 6894 struct ptp_clock_event event; 6895 struct timespec64 ts; 6896 6897 if (pin < 0 || pin >= IGB_N_EXTTS) 6898 return; 6899 6900 if (hw->mac.type == e1000_82580 || 6901 hw->mac.type == e1000_i354 || 6902 hw->mac.type == e1000_i350) { 6903 s64 ns = rd32(auxstmpl); 6904 6905 ns += ((s64)(rd32(auxstmph) & 0xFF)) << 32; 6906 ts = ns_to_timespec64(ns); 6907 } else { 6908 ts.tv_nsec = rd32(auxstmpl); 6909 ts.tv_sec = rd32(auxstmph); 6910 } 6911 6912 event.type = PTP_CLOCK_EXTTS; 6913 event.index = tsintr_tt; 6914 event.timestamp = ts.tv_sec * 1000000000ULL + ts.tv_nsec; 6915 ptp_clock_event(adapter->ptp_clock, &event); 6916 } 6917 6918 static void igb_tsync_interrupt(struct igb_adapter *adapter) 6919 { 6920 struct e1000_hw *hw = &adapter->hw; 6921 u32 ack = 0, tsicr = rd32(E1000_TSICR); 6922 struct ptp_clock_event event; 6923 6924 if (tsicr & TSINTR_SYS_WRAP) { 6925 event.type = PTP_CLOCK_PPS; 6926 if (adapter->ptp_caps.pps) 6927 ptp_clock_event(adapter->ptp_clock, &event); 6928 ack |= TSINTR_SYS_WRAP; 6929 } 6930 6931 if (tsicr & E1000_TSICR_TXTS) { 6932 /* retrieve hardware timestamp */ 6933 schedule_work(&adapter->ptp_tx_work); 6934 ack |= E1000_TSICR_TXTS; 6935 } 6936 6937 if (tsicr & TSINTR_TT0) { 6938 igb_perout(adapter, 0); 6939 ack |= TSINTR_TT0; 6940 } 6941 6942 if (tsicr & TSINTR_TT1) { 6943 igb_perout(adapter, 1); 6944 ack |= TSINTR_TT1; 6945 } 6946 6947 if (tsicr & TSINTR_AUTT0) { 6948 igb_extts(adapter, 0); 6949 ack |= TSINTR_AUTT0; 6950 } 6951 6952 if (tsicr & TSINTR_AUTT1) { 6953 igb_extts(adapter, 1); 6954 ack |= TSINTR_AUTT1; 6955 } 6956 6957 /* acknowledge the interrupts */ 6958 wr32(E1000_TSICR, ack); 6959 } 6960 6961 static irqreturn_t igb_msix_other(int irq, void *data) 6962 { 6963 struct igb_adapter *adapter = data; 6964 struct e1000_hw *hw = &adapter->hw; 6965 u32 icr = rd32(E1000_ICR); 6966 /* reading ICR causes bit 31 of EICR to be cleared */ 6967 6968 if (icr & E1000_ICR_DRSTA) 6969 schedule_work(&adapter->reset_task); 6970 6971 if (icr & E1000_ICR_DOUTSYNC) { 6972 /* HW is reporting DMA is out of sync */ 6973 adapter->stats.doosync++; 6974 /* The DMA Out of Sync is also indication of a spoof event 6975 * in IOV mode. Check the Wrong VM Behavior register to 6976 * see if it is really a spoof event. 6977 */ 6978 igb_check_wvbr(adapter); 6979 } 6980 6981 /* Check for a mailbox event */ 6982 if (icr & E1000_ICR_VMMB) 6983 igb_msg_task(adapter); 6984 6985 if (icr & E1000_ICR_LSC) { 6986 hw->mac.get_link_status = 1; 6987 /* guard against interrupt when we're going down */ 6988 if (!test_bit(__IGB_DOWN, &adapter->state)) 6989 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6990 } 6991 6992 if (icr & E1000_ICR_TS) 6993 igb_tsync_interrupt(adapter); 6994 6995 wr32(E1000_EIMS, adapter->eims_other); 6996 6997 return IRQ_HANDLED; 6998 } 6999 7000 static void igb_write_itr(struct igb_q_vector *q_vector) 7001 { 7002 struct igb_adapter *adapter = q_vector->adapter; 7003 u32 itr_val = q_vector->itr_val & 0x7FFC; 7004 7005 if (!q_vector->set_itr) 7006 return; 7007 7008 if (!itr_val) 7009 itr_val = 0x4; 7010 7011 if (adapter->hw.mac.type == e1000_82575) 7012 itr_val |= itr_val << 16; 7013 else 7014 itr_val |= E1000_EITR_CNT_IGNR; 7015 7016 writel(itr_val, q_vector->itr_register); 7017 q_vector->set_itr = 0; 7018 } 7019 7020 static irqreturn_t igb_msix_ring(int irq, void *data) 7021 { 7022 struct igb_q_vector *q_vector = data; 7023 7024 /* Write the ITR value calculated from the previous interrupt. */ 7025 igb_write_itr(q_vector); 7026 7027 napi_schedule(&q_vector->napi); 7028 7029 return IRQ_HANDLED; 7030 } 7031 7032 #ifdef CONFIG_IGB_DCA 7033 static void igb_update_tx_dca(struct igb_adapter *adapter, 7034 struct igb_ring *tx_ring, 7035 int cpu) 7036 { 7037 struct e1000_hw *hw = &adapter->hw; 7038 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 7039 7040 if (hw->mac.type != e1000_82575) 7041 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 7042 7043 /* We can enable relaxed ordering for reads, but not writes when 7044 * DCA is enabled. This is due to a known issue in some chipsets 7045 * which will cause the DCA tag to be cleared. 7046 */ 7047 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 7048 E1000_DCA_TXCTRL_DATA_RRO_EN | 7049 E1000_DCA_TXCTRL_DESC_DCA_EN; 7050 7051 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 7052 } 7053 7054 static void igb_update_rx_dca(struct igb_adapter *adapter, 7055 struct igb_ring *rx_ring, 7056 int cpu) 7057 { 7058 struct e1000_hw *hw = &adapter->hw; 7059 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 7060 7061 if (hw->mac.type != e1000_82575) 7062 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 7063 7064 /* We can enable relaxed ordering for reads, but not writes when 7065 * DCA is enabled. This is due to a known issue in some chipsets 7066 * which will cause the DCA tag to be cleared. 7067 */ 7068 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 7069 E1000_DCA_RXCTRL_DESC_DCA_EN; 7070 7071 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 7072 } 7073 7074 static void igb_update_dca(struct igb_q_vector *q_vector) 7075 { 7076 struct igb_adapter *adapter = q_vector->adapter; 7077 int cpu = get_cpu(); 7078 7079 if (q_vector->cpu == cpu) 7080 goto out_no_update; 7081 7082 if (q_vector->tx.ring) 7083 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 7084 7085 if (q_vector->rx.ring) 7086 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 7087 7088 q_vector->cpu = cpu; 7089 out_no_update: 7090 put_cpu(); 7091 } 7092 7093 static void igb_setup_dca(struct igb_adapter *adapter) 7094 { 7095 struct e1000_hw *hw = &adapter->hw; 7096 int i; 7097 7098 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 7099 return; 7100 7101 /* Always use CB2 mode, difference is masked in the CB driver. */ 7102 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 7103 7104 for (i = 0; i < adapter->num_q_vectors; i++) { 7105 adapter->q_vector[i]->cpu = -1; 7106 igb_update_dca(adapter->q_vector[i]); 7107 } 7108 } 7109 7110 static int __igb_notify_dca(struct device *dev, void *data) 7111 { 7112 struct net_device *netdev = dev_get_drvdata(dev); 7113 struct igb_adapter *adapter = netdev_priv(netdev); 7114 struct pci_dev *pdev = adapter->pdev; 7115 struct e1000_hw *hw = &adapter->hw; 7116 unsigned long event = *(unsigned long *)data; 7117 7118 switch (event) { 7119 case DCA_PROVIDER_ADD: 7120 /* if already enabled, don't do it again */ 7121 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 7122 break; 7123 if (dca_add_requester(dev) == 0) { 7124 adapter->flags |= IGB_FLAG_DCA_ENABLED; 7125 dev_info(&pdev->dev, "DCA enabled\n"); 7126 igb_setup_dca(adapter); 7127 break; 7128 } 7129 fallthrough; /* since DCA is disabled. */ 7130 case DCA_PROVIDER_REMOVE: 7131 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 7132 /* without this a class_device is left 7133 * hanging around in the sysfs model 7134 */ 7135 dca_remove_requester(dev); 7136 dev_info(&pdev->dev, "DCA disabled\n"); 7137 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 7138 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 7139 } 7140 break; 7141 } 7142 7143 return 0; 7144 } 7145 7146 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 7147 void *p) 7148 { 7149 int ret_val; 7150 7151 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 7152 __igb_notify_dca); 7153 7154 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 7155 } 7156 #endif /* CONFIG_IGB_DCA */ 7157 7158 #ifdef CONFIG_PCI_IOV 7159 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 7160 { 7161 unsigned char mac_addr[ETH_ALEN]; 7162 7163 eth_zero_addr(mac_addr); 7164 igb_set_vf_mac(adapter, vf, mac_addr); 7165 7166 /* By default spoof check is enabled for all VFs */ 7167 adapter->vf_data[vf].spoofchk_enabled = true; 7168 7169 /* By default VFs are not trusted */ 7170 adapter->vf_data[vf].trusted = false; 7171 7172 return 0; 7173 } 7174 7175 #endif 7176 static void igb_ping_all_vfs(struct igb_adapter *adapter) 7177 { 7178 struct e1000_hw *hw = &adapter->hw; 7179 u32 ping; 7180 int i; 7181 7182 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 7183 ping = E1000_PF_CONTROL_MSG; 7184 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 7185 ping |= E1000_VT_MSGTYPE_CTS; 7186 igb_write_mbx(hw, &ping, 1, i); 7187 } 7188 } 7189 7190 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7191 { 7192 struct e1000_hw *hw = &adapter->hw; 7193 u32 vmolr = rd32(E1000_VMOLR(vf)); 7194 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7195 7196 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 7197 IGB_VF_FLAG_MULTI_PROMISC); 7198 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7199 7200 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 7201 vmolr |= E1000_VMOLR_MPME; 7202 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 7203 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 7204 } else { 7205 /* if we have hashes and we are clearing a multicast promisc 7206 * flag we need to write the hashes to the MTA as this step 7207 * was previously skipped 7208 */ 7209 if (vf_data->num_vf_mc_hashes > 30) { 7210 vmolr |= E1000_VMOLR_MPME; 7211 } else if (vf_data->num_vf_mc_hashes) { 7212 int j; 7213 7214 vmolr |= E1000_VMOLR_ROMPE; 7215 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7216 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7217 } 7218 } 7219 7220 wr32(E1000_VMOLR(vf), vmolr); 7221 7222 /* there are flags left unprocessed, likely not supported */ 7223 if (*msgbuf & E1000_VT_MSGINFO_MASK) 7224 return -EINVAL; 7225 7226 return 0; 7227 } 7228 7229 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 7230 u32 *msgbuf, u32 vf) 7231 { 7232 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7233 u16 *hash_list = (u16 *)&msgbuf[1]; 7234 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7235 int i; 7236 7237 /* salt away the number of multicast addresses assigned 7238 * to this VF for later use to restore when the PF multi cast 7239 * list changes 7240 */ 7241 vf_data->num_vf_mc_hashes = n; 7242 7243 /* only up to 30 hash values supported */ 7244 if (n > 30) 7245 n = 30; 7246 7247 /* store the hashes for later use */ 7248 for (i = 0; i < n; i++) 7249 vf_data->vf_mc_hashes[i] = hash_list[i]; 7250 7251 /* Flush and reset the mta with the new values */ 7252 igb_set_rx_mode(adapter->netdev); 7253 7254 return 0; 7255 } 7256 7257 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 7258 { 7259 struct e1000_hw *hw = &adapter->hw; 7260 struct vf_data_storage *vf_data; 7261 int i, j; 7262 7263 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7264 u32 vmolr = rd32(E1000_VMOLR(i)); 7265 7266 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7267 7268 vf_data = &adapter->vf_data[i]; 7269 7270 if ((vf_data->num_vf_mc_hashes > 30) || 7271 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 7272 vmolr |= E1000_VMOLR_MPME; 7273 } else if (vf_data->num_vf_mc_hashes) { 7274 vmolr |= E1000_VMOLR_ROMPE; 7275 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7276 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7277 } 7278 wr32(E1000_VMOLR(i), vmolr); 7279 } 7280 } 7281 7282 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 7283 { 7284 struct e1000_hw *hw = &adapter->hw; 7285 u32 pool_mask, vlvf_mask, i; 7286 7287 /* create mask for VF and other pools */ 7288 pool_mask = E1000_VLVF_POOLSEL_MASK; 7289 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 7290 7291 /* drop PF from pool bits */ 7292 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 7293 adapter->vfs_allocated_count); 7294 7295 /* Find the vlan filter for this id */ 7296 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 7297 u32 vlvf = rd32(E1000_VLVF(i)); 7298 u32 vfta_mask, vid, vfta; 7299 7300 /* remove the vf from the pool */ 7301 if (!(vlvf & vlvf_mask)) 7302 continue; 7303 7304 /* clear out bit from VLVF */ 7305 vlvf ^= vlvf_mask; 7306 7307 /* if other pools are present, just remove ourselves */ 7308 if (vlvf & pool_mask) 7309 goto update_vlvfb; 7310 7311 /* if PF is present, leave VFTA */ 7312 if (vlvf & E1000_VLVF_POOLSEL_MASK) 7313 goto update_vlvf; 7314 7315 vid = vlvf & E1000_VLVF_VLANID_MASK; 7316 vfta_mask = BIT(vid % 32); 7317 7318 /* clear bit from VFTA */ 7319 vfta = adapter->shadow_vfta[vid / 32]; 7320 if (vfta & vfta_mask) 7321 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 7322 update_vlvf: 7323 /* clear pool selection enable */ 7324 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7325 vlvf &= E1000_VLVF_POOLSEL_MASK; 7326 else 7327 vlvf = 0; 7328 update_vlvfb: 7329 /* clear pool bits */ 7330 wr32(E1000_VLVF(i), vlvf); 7331 } 7332 } 7333 7334 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 7335 { 7336 u32 vlvf; 7337 int idx; 7338 7339 /* short cut the special case */ 7340 if (vlan == 0) 7341 return 0; 7342 7343 /* Search for the VLAN id in the VLVF entries */ 7344 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 7345 vlvf = rd32(E1000_VLVF(idx)); 7346 if ((vlvf & VLAN_VID_MASK) == vlan) 7347 break; 7348 } 7349 7350 return idx; 7351 } 7352 7353 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 7354 { 7355 struct e1000_hw *hw = &adapter->hw; 7356 u32 bits, pf_id; 7357 int idx; 7358 7359 idx = igb_find_vlvf_entry(hw, vid); 7360 if (!idx) 7361 return; 7362 7363 /* See if any other pools are set for this VLAN filter 7364 * entry other than the PF. 7365 */ 7366 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 7367 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 7368 bits &= rd32(E1000_VLVF(idx)); 7369 7370 /* Disable the filter so this falls into the default pool. */ 7371 if (!bits) { 7372 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7373 wr32(E1000_VLVF(idx), BIT(pf_id)); 7374 else 7375 wr32(E1000_VLVF(idx), 0); 7376 } 7377 } 7378 7379 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 7380 bool add, u32 vf) 7381 { 7382 int pf_id = adapter->vfs_allocated_count; 7383 struct e1000_hw *hw = &adapter->hw; 7384 int err; 7385 7386 /* If VLAN overlaps with one the PF is currently monitoring make 7387 * sure that we are able to allocate a VLVF entry. This may be 7388 * redundant but it guarantees PF will maintain visibility to 7389 * the VLAN. 7390 */ 7391 if (add && test_bit(vid, adapter->active_vlans)) { 7392 err = igb_vfta_set(hw, vid, pf_id, true, false); 7393 if (err) 7394 return err; 7395 } 7396 7397 err = igb_vfta_set(hw, vid, vf, add, false); 7398 7399 if (add && !err) 7400 return err; 7401 7402 /* If we failed to add the VF VLAN or we are removing the VF VLAN 7403 * we may need to drop the PF pool bit in order to allow us to free 7404 * up the VLVF resources. 7405 */ 7406 if (test_bit(vid, adapter->active_vlans) || 7407 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7408 igb_update_pf_vlvf(adapter, vid); 7409 7410 return err; 7411 } 7412 7413 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 7414 { 7415 struct e1000_hw *hw = &adapter->hw; 7416 7417 if (vid) 7418 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 7419 else 7420 wr32(E1000_VMVIR(vf), 0); 7421 } 7422 7423 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7424 u16 vlan, u8 qos) 7425 { 7426 int err; 7427 7428 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7429 if (err) 7430 return err; 7431 7432 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7433 igb_set_vmolr(adapter, vf, !vlan); 7434 7435 /* revoke access to previous VLAN */ 7436 if (vlan != adapter->vf_data[vf].pf_vlan) 7437 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7438 false, vf); 7439 7440 adapter->vf_data[vf].pf_vlan = vlan; 7441 adapter->vf_data[vf].pf_qos = qos; 7442 igb_set_vf_vlan_strip(adapter, vf, true); 7443 dev_info(&adapter->pdev->dev, 7444 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7445 if (test_bit(__IGB_DOWN, &adapter->state)) { 7446 dev_warn(&adapter->pdev->dev, 7447 "The VF VLAN has been set, but the PF device is not up.\n"); 7448 dev_warn(&adapter->pdev->dev, 7449 "Bring the PF device up before attempting to use the VF device.\n"); 7450 } 7451 7452 return err; 7453 } 7454 7455 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7456 { 7457 /* Restore tagless access via VLAN 0 */ 7458 igb_set_vf_vlan(adapter, 0, true, vf); 7459 7460 igb_set_vmvir(adapter, 0, vf); 7461 igb_set_vmolr(adapter, vf, true); 7462 7463 /* Remove any PF assigned VLAN */ 7464 if (adapter->vf_data[vf].pf_vlan) 7465 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7466 false, vf); 7467 7468 adapter->vf_data[vf].pf_vlan = 0; 7469 adapter->vf_data[vf].pf_qos = 0; 7470 igb_set_vf_vlan_strip(adapter, vf, false); 7471 7472 return 0; 7473 } 7474 7475 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7476 u16 vlan, u8 qos, __be16 vlan_proto) 7477 { 7478 struct igb_adapter *adapter = netdev_priv(netdev); 7479 7480 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7481 return -EINVAL; 7482 7483 if (vlan_proto != htons(ETH_P_8021Q)) 7484 return -EPROTONOSUPPORT; 7485 7486 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7487 igb_disable_port_vlan(adapter, vf); 7488 } 7489 7490 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7491 { 7492 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7493 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7494 int ret; 7495 7496 if (adapter->vf_data[vf].pf_vlan) 7497 return -1; 7498 7499 /* VLAN 0 is a special case, don't allow it to be removed */ 7500 if (!vid && !add) 7501 return 0; 7502 7503 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7504 if (!ret) 7505 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7506 return ret; 7507 } 7508 7509 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7510 { 7511 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7512 7513 /* clear flags - except flag that indicates PF has set the MAC */ 7514 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7515 vf_data->last_nack = jiffies; 7516 7517 /* reset vlans for device */ 7518 igb_clear_vf_vfta(adapter, vf); 7519 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7520 igb_set_vmvir(adapter, vf_data->pf_vlan | 7521 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7522 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7523 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7524 7525 /* reset multicast table array for vf */ 7526 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7527 7528 /* Flush and reset the mta with the new values */ 7529 igb_set_rx_mode(adapter->netdev); 7530 } 7531 7532 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7533 { 7534 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7535 7536 /* clear mac address as we were hotplug removed/added */ 7537 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7538 eth_zero_addr(vf_mac); 7539 7540 /* process remaining reset events */ 7541 igb_vf_reset(adapter, vf); 7542 } 7543 7544 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7545 { 7546 struct e1000_hw *hw = &adapter->hw; 7547 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7548 u32 reg, msgbuf[3] = {}; 7549 u8 *addr = (u8 *)(&msgbuf[1]); 7550 7551 /* process all the same items cleared in a function level reset */ 7552 igb_vf_reset(adapter, vf); 7553 7554 /* set vf mac address */ 7555 igb_set_vf_mac(adapter, vf, vf_mac); 7556 7557 /* enable transmit and receive for vf */ 7558 reg = rd32(E1000_VFTE); 7559 wr32(E1000_VFTE, reg | BIT(vf)); 7560 reg = rd32(E1000_VFRE); 7561 wr32(E1000_VFRE, reg | BIT(vf)); 7562 7563 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7564 7565 /* reply to reset with ack and vf mac address */ 7566 if (!is_zero_ether_addr(vf_mac)) { 7567 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7568 memcpy(addr, vf_mac, ETH_ALEN); 7569 } else { 7570 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7571 } 7572 igb_write_mbx(hw, msgbuf, 3, vf); 7573 } 7574 7575 static void igb_flush_mac_table(struct igb_adapter *adapter) 7576 { 7577 struct e1000_hw *hw = &adapter->hw; 7578 int i; 7579 7580 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7581 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7582 eth_zero_addr(adapter->mac_table[i].addr); 7583 adapter->mac_table[i].queue = 0; 7584 igb_rar_set_index(adapter, i); 7585 } 7586 } 7587 7588 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7589 { 7590 struct e1000_hw *hw = &adapter->hw; 7591 /* do not count rar entries reserved for VFs MAC addresses */ 7592 int rar_entries = hw->mac.rar_entry_count - 7593 adapter->vfs_allocated_count; 7594 int i, count = 0; 7595 7596 for (i = 0; i < rar_entries; i++) { 7597 /* do not count default entries */ 7598 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7599 continue; 7600 7601 /* do not count "in use" entries for different queues */ 7602 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7603 (adapter->mac_table[i].queue != queue)) 7604 continue; 7605 7606 count++; 7607 } 7608 7609 return count; 7610 } 7611 7612 /* Set default MAC address for the PF in the first RAR entry */ 7613 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7614 { 7615 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7616 7617 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7618 mac_table->queue = adapter->vfs_allocated_count; 7619 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7620 7621 igb_rar_set_index(adapter, 0); 7622 } 7623 7624 /* If the filter to be added and an already existing filter express 7625 * the same address and address type, it should be possible to only 7626 * override the other configurations, for example the queue to steer 7627 * traffic. 7628 */ 7629 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7630 const u8 *addr, const u8 flags) 7631 { 7632 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7633 return true; 7634 7635 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7636 (flags & IGB_MAC_STATE_SRC_ADDR)) 7637 return false; 7638 7639 if (!ether_addr_equal(addr, entry->addr)) 7640 return false; 7641 7642 return true; 7643 } 7644 7645 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7646 * 'flags' is used to indicate what kind of match is made, match is by 7647 * default for the destination address, if matching by source address 7648 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7649 */ 7650 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7651 const u8 *addr, const u8 queue, 7652 const u8 flags) 7653 { 7654 struct e1000_hw *hw = &adapter->hw; 7655 int rar_entries = hw->mac.rar_entry_count - 7656 adapter->vfs_allocated_count; 7657 int i; 7658 7659 if (is_zero_ether_addr(addr)) 7660 return -EINVAL; 7661 7662 /* Search for the first empty entry in the MAC table. 7663 * Do not touch entries at the end of the table reserved for the VF MAC 7664 * addresses. 7665 */ 7666 for (i = 0; i < rar_entries; i++) { 7667 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7668 addr, flags)) 7669 continue; 7670 7671 ether_addr_copy(adapter->mac_table[i].addr, addr); 7672 adapter->mac_table[i].queue = queue; 7673 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7674 7675 igb_rar_set_index(adapter, i); 7676 return i; 7677 } 7678 7679 return -ENOSPC; 7680 } 7681 7682 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7683 const u8 queue) 7684 { 7685 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7686 } 7687 7688 /* Remove a MAC filter for 'addr' directing matching traffic to 7689 * 'queue', 'flags' is used to indicate what kind of match need to be 7690 * removed, match is by default for the destination address, if 7691 * matching by source address is to be removed the flag 7692 * IGB_MAC_STATE_SRC_ADDR can be used. 7693 */ 7694 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7695 const u8 *addr, const u8 queue, 7696 const u8 flags) 7697 { 7698 struct e1000_hw *hw = &adapter->hw; 7699 int rar_entries = hw->mac.rar_entry_count - 7700 adapter->vfs_allocated_count; 7701 int i; 7702 7703 if (is_zero_ether_addr(addr)) 7704 return -EINVAL; 7705 7706 /* Search for matching entry in the MAC table based on given address 7707 * and queue. Do not touch entries at the end of the table reserved 7708 * for the VF MAC addresses. 7709 */ 7710 for (i = 0; i < rar_entries; i++) { 7711 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7712 continue; 7713 if ((adapter->mac_table[i].state & flags) != flags) 7714 continue; 7715 if (adapter->mac_table[i].queue != queue) 7716 continue; 7717 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7718 continue; 7719 7720 /* When a filter for the default address is "deleted", 7721 * we return it to its initial configuration 7722 */ 7723 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7724 adapter->mac_table[i].state = 7725 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7726 adapter->mac_table[i].queue = 7727 adapter->vfs_allocated_count; 7728 } else { 7729 adapter->mac_table[i].state = 0; 7730 adapter->mac_table[i].queue = 0; 7731 eth_zero_addr(adapter->mac_table[i].addr); 7732 } 7733 7734 igb_rar_set_index(adapter, i); 7735 return 0; 7736 } 7737 7738 return -ENOENT; 7739 } 7740 7741 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7742 const u8 queue) 7743 { 7744 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7745 } 7746 7747 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7748 const u8 *addr, u8 queue, u8 flags) 7749 { 7750 struct e1000_hw *hw = &adapter->hw; 7751 7752 /* In theory, this should be supported on 82575 as well, but 7753 * that part wasn't easily accessible during development. 7754 */ 7755 if (hw->mac.type != e1000_i210) 7756 return -EOPNOTSUPP; 7757 7758 return igb_add_mac_filter_flags(adapter, addr, queue, 7759 IGB_MAC_STATE_QUEUE_STEERING | flags); 7760 } 7761 7762 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7763 const u8 *addr, u8 queue, u8 flags) 7764 { 7765 return igb_del_mac_filter_flags(adapter, addr, queue, 7766 IGB_MAC_STATE_QUEUE_STEERING | flags); 7767 } 7768 7769 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7770 { 7771 struct igb_adapter *adapter = netdev_priv(netdev); 7772 int ret; 7773 7774 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7775 7776 return min_t(int, ret, 0); 7777 } 7778 7779 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7780 { 7781 struct igb_adapter *adapter = netdev_priv(netdev); 7782 7783 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7784 7785 return 0; 7786 } 7787 7788 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7789 const u32 info, const u8 *addr) 7790 { 7791 struct pci_dev *pdev = adapter->pdev; 7792 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7793 struct list_head *pos; 7794 struct vf_mac_filter *entry = NULL; 7795 int ret = 0; 7796 7797 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7798 !vf_data->trusted) { 7799 dev_warn(&pdev->dev, 7800 "VF %d requested MAC filter but is administratively denied\n", 7801 vf); 7802 return -EINVAL; 7803 } 7804 if (!is_valid_ether_addr(addr)) { 7805 dev_warn(&pdev->dev, 7806 "VF %d attempted to set invalid MAC filter\n", 7807 vf); 7808 return -EINVAL; 7809 } 7810 7811 switch (info) { 7812 case E1000_VF_MAC_FILTER_CLR: 7813 /* remove all unicast MAC filters related to the current VF */ 7814 list_for_each(pos, &adapter->vf_macs.l) { 7815 entry = list_entry(pos, struct vf_mac_filter, l); 7816 if (entry->vf == vf) { 7817 entry->vf = -1; 7818 entry->free = true; 7819 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7820 } 7821 } 7822 break; 7823 case E1000_VF_MAC_FILTER_ADD: 7824 /* try to find empty slot in the list */ 7825 list_for_each(pos, &adapter->vf_macs.l) { 7826 entry = list_entry(pos, struct vf_mac_filter, l); 7827 if (entry->free) 7828 break; 7829 } 7830 7831 if (entry && entry->free) { 7832 entry->free = false; 7833 entry->vf = vf; 7834 ether_addr_copy(entry->vf_mac, addr); 7835 7836 ret = igb_add_mac_filter(adapter, addr, vf); 7837 ret = min_t(int, ret, 0); 7838 } else { 7839 ret = -ENOSPC; 7840 } 7841 7842 if (ret == -ENOSPC) 7843 dev_warn(&pdev->dev, 7844 "VF %d has requested MAC filter but there is no space for it\n", 7845 vf); 7846 break; 7847 default: 7848 ret = -EINVAL; 7849 break; 7850 } 7851 7852 return ret; 7853 } 7854 7855 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7856 { 7857 struct pci_dev *pdev = adapter->pdev; 7858 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7859 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7860 7861 /* The VF MAC Address is stored in a packed array of bytes 7862 * starting at the second 32 bit word of the msg array 7863 */ 7864 unsigned char *addr = (unsigned char *)&msg[1]; 7865 int ret = 0; 7866 7867 if (!info) { 7868 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7869 !vf_data->trusted) { 7870 dev_warn(&pdev->dev, 7871 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 7872 vf); 7873 return -EINVAL; 7874 } 7875 7876 if (!is_valid_ether_addr(addr)) { 7877 dev_warn(&pdev->dev, 7878 "VF %d attempted to set invalid MAC\n", 7879 vf); 7880 return -EINVAL; 7881 } 7882 7883 ret = igb_set_vf_mac(adapter, vf, addr); 7884 } else { 7885 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 7886 } 7887 7888 return ret; 7889 } 7890 7891 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 7892 { 7893 struct e1000_hw *hw = &adapter->hw; 7894 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7895 u32 msg = E1000_VT_MSGTYPE_NACK; 7896 7897 /* if device isn't clear to send it shouldn't be reading either */ 7898 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 7899 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 7900 igb_write_mbx(hw, &msg, 1, vf); 7901 vf_data->last_nack = jiffies; 7902 } 7903 } 7904 7905 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 7906 { 7907 struct pci_dev *pdev = adapter->pdev; 7908 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 7909 struct e1000_hw *hw = &adapter->hw; 7910 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7911 s32 retval; 7912 7913 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 7914 7915 if (retval) { 7916 /* if receive failed revoke VF CTS stats and restart init */ 7917 dev_err(&pdev->dev, "Error receiving message from VF\n"); 7918 vf_data->flags &= ~IGB_VF_FLAG_CTS; 7919 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7920 goto unlock; 7921 goto out; 7922 } 7923 7924 /* this is a message we already processed, do nothing */ 7925 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 7926 goto unlock; 7927 7928 /* until the vf completes a reset it should not be 7929 * allowed to start any configuration. 7930 */ 7931 if (msgbuf[0] == E1000_VF_RESET) { 7932 /* unlocks mailbox */ 7933 igb_vf_reset_msg(adapter, vf); 7934 return; 7935 } 7936 7937 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 7938 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7939 goto unlock; 7940 retval = -1; 7941 goto out; 7942 } 7943 7944 switch ((msgbuf[0] & 0xFFFF)) { 7945 case E1000_VF_SET_MAC_ADDR: 7946 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 7947 break; 7948 case E1000_VF_SET_PROMISC: 7949 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 7950 break; 7951 case E1000_VF_SET_MULTICAST: 7952 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 7953 break; 7954 case E1000_VF_SET_LPE: 7955 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 7956 break; 7957 case E1000_VF_SET_VLAN: 7958 retval = -1; 7959 if (vf_data->pf_vlan) 7960 dev_warn(&pdev->dev, 7961 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 7962 vf); 7963 else 7964 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 7965 break; 7966 default: 7967 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 7968 retval = -1; 7969 break; 7970 } 7971 7972 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 7973 out: 7974 /* notify the VF of the results of what it sent us */ 7975 if (retval) 7976 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 7977 else 7978 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 7979 7980 /* unlocks mailbox */ 7981 igb_write_mbx(hw, msgbuf, 1, vf); 7982 return; 7983 7984 unlock: 7985 igb_unlock_mbx(hw, vf); 7986 } 7987 7988 static void igb_msg_task(struct igb_adapter *adapter) 7989 { 7990 struct e1000_hw *hw = &adapter->hw; 7991 unsigned long flags; 7992 u32 vf; 7993 7994 spin_lock_irqsave(&adapter->vfs_lock, flags); 7995 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 7996 /* process any reset requests */ 7997 if (!igb_check_for_rst(hw, vf)) 7998 igb_vf_reset_event(adapter, vf); 7999 8000 /* process any messages pending */ 8001 if (!igb_check_for_msg(hw, vf)) 8002 igb_rcv_msg_from_vf(adapter, vf); 8003 8004 /* process any acks */ 8005 if (!igb_check_for_ack(hw, vf)) 8006 igb_rcv_ack_from_vf(adapter, vf); 8007 } 8008 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 8009 } 8010 8011 /** 8012 * igb_set_uta - Set unicast filter table address 8013 * @adapter: board private structure 8014 * @set: boolean indicating if we are setting or clearing bits 8015 * 8016 * The unicast table address is a register array of 32-bit registers. 8017 * The table is meant to be used in a way similar to how the MTA is used 8018 * however due to certain limitations in the hardware it is necessary to 8019 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 8020 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 8021 **/ 8022 static void igb_set_uta(struct igb_adapter *adapter, bool set) 8023 { 8024 struct e1000_hw *hw = &adapter->hw; 8025 u32 uta = set ? ~0 : 0; 8026 int i; 8027 8028 /* we only need to do this if VMDq is enabled */ 8029 if (!adapter->vfs_allocated_count) 8030 return; 8031 8032 for (i = hw->mac.uta_reg_count; i--;) 8033 array_wr32(E1000_UTA, i, uta); 8034 } 8035 8036 /** 8037 * igb_intr_msi - Interrupt Handler 8038 * @irq: interrupt number 8039 * @data: pointer to a network interface device structure 8040 **/ 8041 static irqreturn_t igb_intr_msi(int irq, void *data) 8042 { 8043 struct igb_adapter *adapter = data; 8044 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8045 struct e1000_hw *hw = &adapter->hw; 8046 /* read ICR disables interrupts using IAM */ 8047 u32 icr = rd32(E1000_ICR); 8048 8049 igb_write_itr(q_vector); 8050 8051 if (icr & E1000_ICR_DRSTA) 8052 schedule_work(&adapter->reset_task); 8053 8054 if (icr & E1000_ICR_DOUTSYNC) { 8055 /* HW is reporting DMA is out of sync */ 8056 adapter->stats.doosync++; 8057 } 8058 8059 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8060 hw->mac.get_link_status = 1; 8061 if (!test_bit(__IGB_DOWN, &adapter->state)) 8062 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8063 } 8064 8065 if (icr & E1000_ICR_TS) 8066 igb_tsync_interrupt(adapter); 8067 8068 napi_schedule(&q_vector->napi); 8069 8070 return IRQ_HANDLED; 8071 } 8072 8073 /** 8074 * igb_intr - Legacy Interrupt Handler 8075 * @irq: interrupt number 8076 * @data: pointer to a network interface device structure 8077 **/ 8078 static irqreturn_t igb_intr(int irq, void *data) 8079 { 8080 struct igb_adapter *adapter = data; 8081 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8082 struct e1000_hw *hw = &adapter->hw; 8083 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 8084 * need for the IMC write 8085 */ 8086 u32 icr = rd32(E1000_ICR); 8087 8088 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 8089 * not set, then the adapter didn't send an interrupt 8090 */ 8091 if (!(icr & E1000_ICR_INT_ASSERTED)) 8092 return IRQ_NONE; 8093 8094 igb_write_itr(q_vector); 8095 8096 if (icr & E1000_ICR_DRSTA) 8097 schedule_work(&adapter->reset_task); 8098 8099 if (icr & E1000_ICR_DOUTSYNC) { 8100 /* HW is reporting DMA is out of sync */ 8101 adapter->stats.doosync++; 8102 } 8103 8104 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8105 hw->mac.get_link_status = 1; 8106 /* guard against interrupt when we're going down */ 8107 if (!test_bit(__IGB_DOWN, &adapter->state)) 8108 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8109 } 8110 8111 if (icr & E1000_ICR_TS) 8112 igb_tsync_interrupt(adapter); 8113 8114 napi_schedule(&q_vector->napi); 8115 8116 return IRQ_HANDLED; 8117 } 8118 8119 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 8120 { 8121 struct igb_adapter *adapter = q_vector->adapter; 8122 struct e1000_hw *hw = &adapter->hw; 8123 8124 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 8125 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 8126 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 8127 igb_set_itr(q_vector); 8128 else 8129 igb_update_ring_itr(q_vector); 8130 } 8131 8132 if (!test_bit(__IGB_DOWN, &adapter->state)) { 8133 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8134 wr32(E1000_EIMS, q_vector->eims_value); 8135 else 8136 igb_irq_enable(adapter); 8137 } 8138 } 8139 8140 /** 8141 * igb_poll - NAPI Rx polling callback 8142 * @napi: napi polling structure 8143 * @budget: count of how many packets we should handle 8144 **/ 8145 static int igb_poll(struct napi_struct *napi, int budget) 8146 { 8147 struct igb_q_vector *q_vector = container_of(napi, 8148 struct igb_q_vector, 8149 napi); 8150 bool clean_complete = true; 8151 int work_done = 0; 8152 8153 #ifdef CONFIG_IGB_DCA 8154 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 8155 igb_update_dca(q_vector); 8156 #endif 8157 if (q_vector->tx.ring) 8158 clean_complete = igb_clean_tx_irq(q_vector, budget); 8159 8160 if (q_vector->rx.ring) { 8161 int cleaned = igb_clean_rx_irq(q_vector, budget); 8162 8163 work_done += cleaned; 8164 if (cleaned >= budget) 8165 clean_complete = false; 8166 } 8167 8168 /* If all work not completed, return budget and keep polling */ 8169 if (!clean_complete) 8170 return budget; 8171 8172 /* Exit the polling mode, but don't re-enable interrupts if stack might 8173 * poll us due to busy-polling 8174 */ 8175 if (likely(napi_complete_done(napi, work_done))) 8176 igb_ring_irq_enable(q_vector); 8177 8178 return work_done; 8179 } 8180 8181 /** 8182 * igb_clean_tx_irq - Reclaim resources after transmit completes 8183 * @q_vector: pointer to q_vector containing needed info 8184 * @napi_budget: Used to determine if we are in netpoll 8185 * 8186 * returns true if ring is completely cleaned 8187 **/ 8188 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 8189 { 8190 struct igb_adapter *adapter = q_vector->adapter; 8191 struct igb_ring *tx_ring = q_vector->tx.ring; 8192 struct igb_tx_buffer *tx_buffer; 8193 union e1000_adv_tx_desc *tx_desc; 8194 unsigned int total_bytes = 0, total_packets = 0; 8195 unsigned int budget = q_vector->tx.work_limit; 8196 unsigned int i = tx_ring->next_to_clean; 8197 8198 if (test_bit(__IGB_DOWN, &adapter->state)) 8199 return true; 8200 8201 tx_buffer = &tx_ring->tx_buffer_info[i]; 8202 tx_desc = IGB_TX_DESC(tx_ring, i); 8203 i -= tx_ring->count; 8204 8205 do { 8206 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 8207 8208 /* if next_to_watch is not set then there is no work pending */ 8209 if (!eop_desc) 8210 break; 8211 8212 /* prevent any other reads prior to eop_desc */ 8213 smp_rmb(); 8214 8215 /* if DD is not set pending work has not been completed */ 8216 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 8217 break; 8218 8219 /* clear next_to_watch to prevent false hangs */ 8220 tx_buffer->next_to_watch = NULL; 8221 8222 /* update the statistics for this packet */ 8223 total_bytes += tx_buffer->bytecount; 8224 total_packets += tx_buffer->gso_segs; 8225 8226 /* free the skb */ 8227 if (tx_buffer->type == IGB_TYPE_SKB) 8228 napi_consume_skb(tx_buffer->skb, napi_budget); 8229 else 8230 xdp_return_frame(tx_buffer->xdpf); 8231 8232 /* unmap skb header data */ 8233 dma_unmap_single(tx_ring->dev, 8234 dma_unmap_addr(tx_buffer, dma), 8235 dma_unmap_len(tx_buffer, len), 8236 DMA_TO_DEVICE); 8237 8238 /* clear tx_buffer data */ 8239 dma_unmap_len_set(tx_buffer, len, 0); 8240 8241 /* clear last DMA location and unmap remaining buffers */ 8242 while (tx_desc != eop_desc) { 8243 tx_buffer++; 8244 tx_desc++; 8245 i++; 8246 if (unlikely(!i)) { 8247 i -= tx_ring->count; 8248 tx_buffer = tx_ring->tx_buffer_info; 8249 tx_desc = IGB_TX_DESC(tx_ring, 0); 8250 } 8251 8252 /* unmap any remaining paged data */ 8253 if (dma_unmap_len(tx_buffer, len)) { 8254 dma_unmap_page(tx_ring->dev, 8255 dma_unmap_addr(tx_buffer, dma), 8256 dma_unmap_len(tx_buffer, len), 8257 DMA_TO_DEVICE); 8258 dma_unmap_len_set(tx_buffer, len, 0); 8259 } 8260 } 8261 8262 /* move us one more past the eop_desc for start of next pkt */ 8263 tx_buffer++; 8264 tx_desc++; 8265 i++; 8266 if (unlikely(!i)) { 8267 i -= tx_ring->count; 8268 tx_buffer = tx_ring->tx_buffer_info; 8269 tx_desc = IGB_TX_DESC(tx_ring, 0); 8270 } 8271 8272 /* issue prefetch for next Tx descriptor */ 8273 prefetch(tx_desc); 8274 8275 /* update budget accounting */ 8276 budget--; 8277 } while (likely(budget)); 8278 8279 netdev_tx_completed_queue(txring_txq(tx_ring), 8280 total_packets, total_bytes); 8281 i += tx_ring->count; 8282 tx_ring->next_to_clean = i; 8283 u64_stats_update_begin(&tx_ring->tx_syncp); 8284 tx_ring->tx_stats.bytes += total_bytes; 8285 tx_ring->tx_stats.packets += total_packets; 8286 u64_stats_update_end(&tx_ring->tx_syncp); 8287 q_vector->tx.total_bytes += total_bytes; 8288 q_vector->tx.total_packets += total_packets; 8289 8290 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 8291 struct e1000_hw *hw = &adapter->hw; 8292 8293 /* Detect a transmit hang in hardware, this serializes the 8294 * check with the clearing of time_stamp and movement of i 8295 */ 8296 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 8297 if (tx_buffer->next_to_watch && 8298 time_after(jiffies, tx_buffer->time_stamp + 8299 (adapter->tx_timeout_factor * HZ)) && 8300 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 8301 8302 /* detected Tx unit hang */ 8303 dev_err(tx_ring->dev, 8304 "Detected Tx Unit Hang\n" 8305 " Tx Queue <%d>\n" 8306 " TDH <%x>\n" 8307 " TDT <%x>\n" 8308 " next_to_use <%x>\n" 8309 " next_to_clean <%x>\n" 8310 "buffer_info[next_to_clean]\n" 8311 " time_stamp <%lx>\n" 8312 " next_to_watch <%p>\n" 8313 " jiffies <%lx>\n" 8314 " desc.status <%x>\n", 8315 tx_ring->queue_index, 8316 rd32(E1000_TDH(tx_ring->reg_idx)), 8317 readl(tx_ring->tail), 8318 tx_ring->next_to_use, 8319 tx_ring->next_to_clean, 8320 tx_buffer->time_stamp, 8321 tx_buffer->next_to_watch, 8322 jiffies, 8323 tx_buffer->next_to_watch->wb.status); 8324 netif_stop_subqueue(tx_ring->netdev, 8325 tx_ring->queue_index); 8326 8327 /* we are about to reset, no point in enabling stuff */ 8328 return true; 8329 } 8330 } 8331 8332 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 8333 if (unlikely(total_packets && 8334 netif_carrier_ok(tx_ring->netdev) && 8335 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 8336 /* Make sure that anybody stopping the queue after this 8337 * sees the new next_to_clean. 8338 */ 8339 smp_mb(); 8340 if (__netif_subqueue_stopped(tx_ring->netdev, 8341 tx_ring->queue_index) && 8342 !(test_bit(__IGB_DOWN, &adapter->state))) { 8343 netif_wake_subqueue(tx_ring->netdev, 8344 tx_ring->queue_index); 8345 8346 u64_stats_update_begin(&tx_ring->tx_syncp); 8347 tx_ring->tx_stats.restart_queue++; 8348 u64_stats_update_end(&tx_ring->tx_syncp); 8349 } 8350 } 8351 8352 return !!budget; 8353 } 8354 8355 /** 8356 * igb_reuse_rx_page - page flip buffer and store it back on the ring 8357 * @rx_ring: rx descriptor ring to store buffers on 8358 * @old_buff: donor buffer to have page reused 8359 * 8360 * Synchronizes page for reuse by the adapter 8361 **/ 8362 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 8363 struct igb_rx_buffer *old_buff) 8364 { 8365 struct igb_rx_buffer *new_buff; 8366 u16 nta = rx_ring->next_to_alloc; 8367 8368 new_buff = &rx_ring->rx_buffer_info[nta]; 8369 8370 /* update, and store next to alloc */ 8371 nta++; 8372 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 8373 8374 /* Transfer page from old buffer to new buffer. 8375 * Move each member individually to avoid possible store 8376 * forwarding stalls. 8377 */ 8378 new_buff->dma = old_buff->dma; 8379 new_buff->page = old_buff->page; 8380 new_buff->page_offset = old_buff->page_offset; 8381 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 8382 } 8383 8384 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 8385 int rx_buf_pgcnt) 8386 { 8387 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 8388 struct page *page = rx_buffer->page; 8389 8390 /* avoid re-using remote and pfmemalloc pages */ 8391 if (!dev_page_is_reusable(page)) 8392 return false; 8393 8394 #if (PAGE_SIZE < 8192) 8395 /* if we are only owner of page we can reuse it */ 8396 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1)) 8397 return false; 8398 #else 8399 #define IGB_LAST_OFFSET \ 8400 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 8401 8402 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 8403 return false; 8404 #endif 8405 8406 /* If we have drained the page fragment pool we need to update 8407 * the pagecnt_bias and page count so that we fully restock the 8408 * number of references the driver holds. 8409 */ 8410 if (unlikely(pagecnt_bias == 1)) { 8411 page_ref_add(page, USHRT_MAX - 1); 8412 rx_buffer->pagecnt_bias = USHRT_MAX; 8413 } 8414 8415 return true; 8416 } 8417 8418 /** 8419 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 8420 * @rx_ring: rx descriptor ring to transact packets on 8421 * @rx_buffer: buffer containing page to add 8422 * @skb: sk_buff to place the data into 8423 * @size: size of buffer to be added 8424 * 8425 * This function will add the data contained in rx_buffer->page to the skb. 8426 **/ 8427 static void igb_add_rx_frag(struct igb_ring *rx_ring, 8428 struct igb_rx_buffer *rx_buffer, 8429 struct sk_buff *skb, 8430 unsigned int size) 8431 { 8432 #if (PAGE_SIZE < 8192) 8433 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8434 #else 8435 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8436 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8437 SKB_DATA_ALIGN(size); 8438 #endif 8439 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8440 rx_buffer->page_offset, size, truesize); 8441 #if (PAGE_SIZE < 8192) 8442 rx_buffer->page_offset ^= truesize; 8443 #else 8444 rx_buffer->page_offset += truesize; 8445 #endif 8446 } 8447 8448 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8449 struct igb_rx_buffer *rx_buffer, 8450 struct xdp_buff *xdp, 8451 ktime_t timestamp) 8452 { 8453 #if (PAGE_SIZE < 8192) 8454 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8455 #else 8456 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 8457 xdp->data_hard_start); 8458 #endif 8459 unsigned int size = xdp->data_end - xdp->data; 8460 unsigned int headlen; 8461 struct sk_buff *skb; 8462 8463 /* prefetch first cache line of first page */ 8464 net_prefetch(xdp->data); 8465 8466 /* allocate a skb to store the frags */ 8467 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8468 if (unlikely(!skb)) 8469 return NULL; 8470 8471 if (timestamp) 8472 skb_hwtstamps(skb)->hwtstamp = timestamp; 8473 8474 /* Determine available headroom for copy */ 8475 headlen = size; 8476 if (headlen > IGB_RX_HDR_LEN) 8477 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN); 8478 8479 /* align pull length to size of long to optimize memcpy performance */ 8480 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long))); 8481 8482 /* update all of the pointers */ 8483 size -= headlen; 8484 if (size) { 8485 skb_add_rx_frag(skb, 0, rx_buffer->page, 8486 (xdp->data + headlen) - page_address(rx_buffer->page), 8487 size, truesize); 8488 #if (PAGE_SIZE < 8192) 8489 rx_buffer->page_offset ^= truesize; 8490 #else 8491 rx_buffer->page_offset += truesize; 8492 #endif 8493 } else { 8494 rx_buffer->pagecnt_bias++; 8495 } 8496 8497 return skb; 8498 } 8499 8500 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8501 struct igb_rx_buffer *rx_buffer, 8502 struct xdp_buff *xdp, 8503 ktime_t timestamp) 8504 { 8505 #if (PAGE_SIZE < 8192) 8506 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8507 #else 8508 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8509 SKB_DATA_ALIGN(xdp->data_end - 8510 xdp->data_hard_start); 8511 #endif 8512 unsigned int metasize = xdp->data - xdp->data_meta; 8513 struct sk_buff *skb; 8514 8515 /* prefetch first cache line of first page */ 8516 net_prefetch(xdp->data_meta); 8517 8518 /* build an skb around the page buffer */ 8519 skb = napi_build_skb(xdp->data_hard_start, truesize); 8520 if (unlikely(!skb)) 8521 return NULL; 8522 8523 /* update pointers within the skb to store the data */ 8524 skb_reserve(skb, xdp->data - xdp->data_hard_start); 8525 __skb_put(skb, xdp->data_end - xdp->data); 8526 8527 if (metasize) 8528 skb_metadata_set(skb, metasize); 8529 8530 if (timestamp) 8531 skb_hwtstamps(skb)->hwtstamp = timestamp; 8532 8533 /* update buffer offset */ 8534 #if (PAGE_SIZE < 8192) 8535 rx_buffer->page_offset ^= truesize; 8536 #else 8537 rx_buffer->page_offset += truesize; 8538 #endif 8539 8540 return skb; 8541 } 8542 8543 static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter, 8544 struct igb_ring *rx_ring, 8545 struct xdp_buff *xdp) 8546 { 8547 int err, result = IGB_XDP_PASS; 8548 struct bpf_prog *xdp_prog; 8549 u32 act; 8550 8551 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 8552 8553 if (!xdp_prog) 8554 goto xdp_out; 8555 8556 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 8557 8558 act = bpf_prog_run_xdp(xdp_prog, xdp); 8559 switch (act) { 8560 case XDP_PASS: 8561 break; 8562 case XDP_TX: 8563 result = igb_xdp_xmit_back(adapter, xdp); 8564 if (result == IGB_XDP_CONSUMED) 8565 goto out_failure; 8566 break; 8567 case XDP_REDIRECT: 8568 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 8569 if (err) 8570 goto out_failure; 8571 result = IGB_XDP_REDIR; 8572 break; 8573 default: 8574 bpf_warn_invalid_xdp_action(adapter->netdev, xdp_prog, act); 8575 fallthrough; 8576 case XDP_ABORTED: 8577 out_failure: 8578 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 8579 fallthrough; 8580 case XDP_DROP: 8581 result = IGB_XDP_CONSUMED; 8582 break; 8583 } 8584 xdp_out: 8585 return ERR_PTR(-result); 8586 } 8587 8588 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring, 8589 unsigned int size) 8590 { 8591 unsigned int truesize; 8592 8593 #if (PAGE_SIZE < 8192) 8594 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 8595 #else 8596 truesize = ring_uses_build_skb(rx_ring) ? 8597 SKB_DATA_ALIGN(IGB_SKB_PAD + size) + 8598 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 8599 SKB_DATA_ALIGN(size); 8600 #endif 8601 return truesize; 8602 } 8603 8604 static void igb_rx_buffer_flip(struct igb_ring *rx_ring, 8605 struct igb_rx_buffer *rx_buffer, 8606 unsigned int size) 8607 { 8608 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size); 8609 #if (PAGE_SIZE < 8192) 8610 rx_buffer->page_offset ^= truesize; 8611 #else 8612 rx_buffer->page_offset += truesize; 8613 #endif 8614 } 8615 8616 static inline void igb_rx_checksum(struct igb_ring *ring, 8617 union e1000_adv_rx_desc *rx_desc, 8618 struct sk_buff *skb) 8619 { 8620 skb_checksum_none_assert(skb); 8621 8622 /* Ignore Checksum bit is set */ 8623 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8624 return; 8625 8626 /* Rx checksum disabled via ethtool */ 8627 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8628 return; 8629 8630 /* TCP/UDP checksum error bit is set */ 8631 if (igb_test_staterr(rx_desc, 8632 E1000_RXDEXT_STATERR_TCPE | 8633 E1000_RXDEXT_STATERR_IPE)) { 8634 /* work around errata with sctp packets where the TCPE aka 8635 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8636 * packets, (aka let the stack check the crc32c) 8637 */ 8638 if (!((skb->len == 60) && 8639 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8640 u64_stats_update_begin(&ring->rx_syncp); 8641 ring->rx_stats.csum_err++; 8642 u64_stats_update_end(&ring->rx_syncp); 8643 } 8644 /* let the stack verify checksum errors */ 8645 return; 8646 } 8647 /* It must be a TCP or UDP packet with a valid checksum */ 8648 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8649 E1000_RXD_STAT_UDPCS)) 8650 skb->ip_summed = CHECKSUM_UNNECESSARY; 8651 8652 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8653 le32_to_cpu(rx_desc->wb.upper.status_error)); 8654 } 8655 8656 static inline void igb_rx_hash(struct igb_ring *ring, 8657 union e1000_adv_rx_desc *rx_desc, 8658 struct sk_buff *skb) 8659 { 8660 if (ring->netdev->features & NETIF_F_RXHASH) 8661 skb_set_hash(skb, 8662 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8663 PKT_HASH_TYPE_L3); 8664 } 8665 8666 /** 8667 * igb_is_non_eop - process handling of non-EOP buffers 8668 * @rx_ring: Rx ring being processed 8669 * @rx_desc: Rx descriptor for current buffer 8670 * 8671 * This function updates next to clean. If the buffer is an EOP buffer 8672 * this function exits returning false, otherwise it will place the 8673 * sk_buff in the next buffer to be chained and return true indicating 8674 * that this is in fact a non-EOP buffer. 8675 **/ 8676 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8677 union e1000_adv_rx_desc *rx_desc) 8678 { 8679 u32 ntc = rx_ring->next_to_clean + 1; 8680 8681 /* fetch, update, and store next to clean */ 8682 ntc = (ntc < rx_ring->count) ? ntc : 0; 8683 rx_ring->next_to_clean = ntc; 8684 8685 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8686 8687 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8688 return false; 8689 8690 return true; 8691 } 8692 8693 /** 8694 * igb_cleanup_headers - Correct corrupted or empty headers 8695 * @rx_ring: rx descriptor ring packet is being transacted on 8696 * @rx_desc: pointer to the EOP Rx descriptor 8697 * @skb: pointer to current skb being fixed 8698 * 8699 * Address the case where we are pulling data in on pages only 8700 * and as such no data is present in the skb header. 8701 * 8702 * In addition if skb is not at least 60 bytes we need to pad it so that 8703 * it is large enough to qualify as a valid Ethernet frame. 8704 * 8705 * Returns true if an error was encountered and skb was freed. 8706 **/ 8707 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8708 union e1000_adv_rx_desc *rx_desc, 8709 struct sk_buff *skb) 8710 { 8711 /* XDP packets use error pointer so abort at this point */ 8712 if (IS_ERR(skb)) 8713 return true; 8714 8715 if (unlikely((igb_test_staterr(rx_desc, 8716 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8717 struct net_device *netdev = rx_ring->netdev; 8718 if (!(netdev->features & NETIF_F_RXALL)) { 8719 dev_kfree_skb_any(skb); 8720 return true; 8721 } 8722 } 8723 8724 /* if eth_skb_pad returns an error the skb was freed */ 8725 if (eth_skb_pad(skb)) 8726 return true; 8727 8728 return false; 8729 } 8730 8731 /** 8732 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8733 * @rx_ring: rx descriptor ring packet is being transacted on 8734 * @rx_desc: pointer to the EOP Rx descriptor 8735 * @skb: pointer to current skb being populated 8736 * 8737 * This function checks the ring, descriptor, and packet information in 8738 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8739 * other fields within the skb. 8740 **/ 8741 static void igb_process_skb_fields(struct igb_ring *rx_ring, 8742 union e1000_adv_rx_desc *rx_desc, 8743 struct sk_buff *skb) 8744 { 8745 struct net_device *dev = rx_ring->netdev; 8746 8747 igb_rx_hash(rx_ring, rx_desc, skb); 8748 8749 igb_rx_checksum(rx_ring, rx_desc, skb); 8750 8751 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8752 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8753 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8754 8755 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8756 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8757 u16 vid; 8758 8759 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8760 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8761 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan); 8762 else 8763 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8764 8765 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8766 } 8767 8768 skb_record_rx_queue(skb, rx_ring->queue_index); 8769 8770 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8771 } 8772 8773 static unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8774 { 8775 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8776 } 8777 8778 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8779 const unsigned int size, int *rx_buf_pgcnt) 8780 { 8781 struct igb_rx_buffer *rx_buffer; 8782 8783 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8784 *rx_buf_pgcnt = 8785 #if (PAGE_SIZE < 8192) 8786 page_count(rx_buffer->page); 8787 #else 8788 0; 8789 #endif 8790 prefetchw(rx_buffer->page); 8791 8792 /* we are reusing so sync this buffer for CPU use */ 8793 dma_sync_single_range_for_cpu(rx_ring->dev, 8794 rx_buffer->dma, 8795 rx_buffer->page_offset, 8796 size, 8797 DMA_FROM_DEVICE); 8798 8799 rx_buffer->pagecnt_bias--; 8800 8801 return rx_buffer; 8802 } 8803 8804 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8805 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt) 8806 { 8807 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) { 8808 /* hand second half of page back to the ring */ 8809 igb_reuse_rx_page(rx_ring, rx_buffer); 8810 } else { 8811 /* We are not reusing the buffer so unmap it and free 8812 * any references we are holding to it 8813 */ 8814 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8815 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8816 IGB_RX_DMA_ATTR); 8817 __page_frag_cache_drain(rx_buffer->page, 8818 rx_buffer->pagecnt_bias); 8819 } 8820 8821 /* clear contents of rx_buffer */ 8822 rx_buffer->page = NULL; 8823 } 8824 8825 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 8826 { 8827 struct igb_adapter *adapter = q_vector->adapter; 8828 struct igb_ring *rx_ring = q_vector->rx.ring; 8829 struct sk_buff *skb = rx_ring->skb; 8830 unsigned int total_bytes = 0, total_packets = 0; 8831 u16 cleaned_count = igb_desc_unused(rx_ring); 8832 unsigned int xdp_xmit = 0; 8833 struct xdp_buff xdp; 8834 u32 frame_sz = 0; 8835 int rx_buf_pgcnt; 8836 8837 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 8838 #if (PAGE_SIZE < 8192) 8839 frame_sz = igb_rx_frame_truesize(rx_ring, 0); 8840 #endif 8841 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 8842 8843 while (likely(total_packets < budget)) { 8844 union e1000_adv_rx_desc *rx_desc; 8845 struct igb_rx_buffer *rx_buffer; 8846 ktime_t timestamp = 0; 8847 int pkt_offset = 0; 8848 unsigned int size; 8849 void *pktbuf; 8850 8851 /* return some buffers to hardware, one at a time is too slow */ 8852 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 8853 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8854 cleaned_count = 0; 8855 } 8856 8857 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 8858 size = le16_to_cpu(rx_desc->wb.upper.length); 8859 if (!size) 8860 break; 8861 8862 /* This memory barrier is needed to keep us from reading 8863 * any other fields out of the rx_desc until we know the 8864 * descriptor has been written back 8865 */ 8866 dma_rmb(); 8867 8868 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt); 8869 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset; 8870 8871 /* pull rx packet timestamp if available and valid */ 8872 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 8873 int ts_hdr_len; 8874 8875 ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector, 8876 pktbuf, ×tamp); 8877 8878 pkt_offset += ts_hdr_len; 8879 size -= ts_hdr_len; 8880 } 8881 8882 /* retrieve a buffer from the ring */ 8883 if (!skb) { 8884 unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring); 8885 unsigned int offset = pkt_offset + igb_rx_offset(rx_ring); 8886 8887 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 8888 xdp_buff_clear_frags_flag(&xdp); 8889 #if (PAGE_SIZE > 4096) 8890 /* At larger PAGE_SIZE, frame_sz depend on len size */ 8891 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size); 8892 #endif 8893 skb = igb_run_xdp(adapter, rx_ring, &xdp); 8894 } 8895 8896 if (IS_ERR(skb)) { 8897 unsigned int xdp_res = -PTR_ERR(skb); 8898 8899 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) { 8900 xdp_xmit |= xdp_res; 8901 igb_rx_buffer_flip(rx_ring, rx_buffer, size); 8902 } else { 8903 rx_buffer->pagecnt_bias++; 8904 } 8905 total_packets++; 8906 total_bytes += size; 8907 } else if (skb) 8908 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 8909 else if (ring_uses_build_skb(rx_ring)) 8910 skb = igb_build_skb(rx_ring, rx_buffer, &xdp, 8911 timestamp); 8912 else 8913 skb = igb_construct_skb(rx_ring, rx_buffer, 8914 &xdp, timestamp); 8915 8916 /* exit if we failed to retrieve a buffer */ 8917 if (!skb) { 8918 rx_ring->rx_stats.alloc_failed++; 8919 rx_buffer->pagecnt_bias++; 8920 break; 8921 } 8922 8923 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt); 8924 cleaned_count++; 8925 8926 /* fetch next buffer in frame if non-eop */ 8927 if (igb_is_non_eop(rx_ring, rx_desc)) 8928 continue; 8929 8930 /* verify the packet layout is correct */ 8931 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 8932 skb = NULL; 8933 continue; 8934 } 8935 8936 /* probably a little skewed due to removing CRC */ 8937 total_bytes += skb->len; 8938 8939 /* populate checksum, timestamp, VLAN, and protocol */ 8940 igb_process_skb_fields(rx_ring, rx_desc, skb); 8941 8942 napi_gro_receive(&q_vector->napi, skb); 8943 8944 /* reset skb pointer */ 8945 skb = NULL; 8946 8947 /* update budget accounting */ 8948 total_packets++; 8949 } 8950 8951 /* place incomplete frames back on ring for completion */ 8952 rx_ring->skb = skb; 8953 8954 if (xdp_xmit & IGB_XDP_REDIR) 8955 xdp_do_flush(); 8956 8957 if (xdp_xmit & IGB_XDP_TX) { 8958 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter); 8959 8960 igb_xdp_ring_update_tail(tx_ring); 8961 } 8962 8963 u64_stats_update_begin(&rx_ring->rx_syncp); 8964 rx_ring->rx_stats.packets += total_packets; 8965 rx_ring->rx_stats.bytes += total_bytes; 8966 u64_stats_update_end(&rx_ring->rx_syncp); 8967 q_vector->rx.total_packets += total_packets; 8968 q_vector->rx.total_bytes += total_bytes; 8969 8970 if (cleaned_count) 8971 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8972 8973 return total_packets; 8974 } 8975 8976 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 8977 struct igb_rx_buffer *bi) 8978 { 8979 struct page *page = bi->page; 8980 dma_addr_t dma; 8981 8982 /* since we are recycling buffers we should seldom need to alloc */ 8983 if (likely(page)) 8984 return true; 8985 8986 /* alloc new page for storage */ 8987 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 8988 if (unlikely(!page)) { 8989 rx_ring->rx_stats.alloc_failed++; 8990 return false; 8991 } 8992 8993 /* map page for use */ 8994 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 8995 igb_rx_pg_size(rx_ring), 8996 DMA_FROM_DEVICE, 8997 IGB_RX_DMA_ATTR); 8998 8999 /* if mapping failed free memory back to system since 9000 * there isn't much point in holding memory we can't use 9001 */ 9002 if (dma_mapping_error(rx_ring->dev, dma)) { 9003 __free_pages(page, igb_rx_pg_order(rx_ring)); 9004 9005 rx_ring->rx_stats.alloc_failed++; 9006 return false; 9007 } 9008 9009 bi->dma = dma; 9010 bi->page = page; 9011 bi->page_offset = igb_rx_offset(rx_ring); 9012 page_ref_add(page, USHRT_MAX - 1); 9013 bi->pagecnt_bias = USHRT_MAX; 9014 9015 return true; 9016 } 9017 9018 /** 9019 * igb_alloc_rx_buffers - Replace used receive buffers 9020 * @rx_ring: rx descriptor ring to allocate new receive buffers 9021 * @cleaned_count: count of buffers to allocate 9022 **/ 9023 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 9024 { 9025 union e1000_adv_rx_desc *rx_desc; 9026 struct igb_rx_buffer *bi; 9027 u16 i = rx_ring->next_to_use; 9028 u16 bufsz; 9029 9030 /* nothing to do */ 9031 if (!cleaned_count) 9032 return; 9033 9034 rx_desc = IGB_RX_DESC(rx_ring, i); 9035 bi = &rx_ring->rx_buffer_info[i]; 9036 i -= rx_ring->count; 9037 9038 bufsz = igb_rx_bufsz(rx_ring); 9039 9040 do { 9041 if (!igb_alloc_mapped_page(rx_ring, bi)) 9042 break; 9043 9044 /* sync the buffer for use by the device */ 9045 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 9046 bi->page_offset, bufsz, 9047 DMA_FROM_DEVICE); 9048 9049 /* Refresh the desc even if buffer_addrs didn't change 9050 * because each write-back erases this info. 9051 */ 9052 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 9053 9054 rx_desc++; 9055 bi++; 9056 i++; 9057 if (unlikely(!i)) { 9058 rx_desc = IGB_RX_DESC(rx_ring, 0); 9059 bi = rx_ring->rx_buffer_info; 9060 i -= rx_ring->count; 9061 } 9062 9063 /* clear the length for the next_to_use descriptor */ 9064 rx_desc->wb.upper.length = 0; 9065 9066 cleaned_count--; 9067 } while (cleaned_count); 9068 9069 i += rx_ring->count; 9070 9071 if (rx_ring->next_to_use != i) { 9072 /* record the next descriptor to use */ 9073 rx_ring->next_to_use = i; 9074 9075 /* update next to alloc since we have filled the ring */ 9076 rx_ring->next_to_alloc = i; 9077 9078 /* Force memory writes to complete before letting h/w 9079 * know there are new descriptors to fetch. (Only 9080 * applicable for weak-ordered memory model archs, 9081 * such as IA-64). 9082 */ 9083 dma_wmb(); 9084 writel(i, rx_ring->tail); 9085 } 9086 } 9087 9088 /** 9089 * igb_mii_ioctl - 9090 * @netdev: pointer to netdev struct 9091 * @ifr: interface structure 9092 * @cmd: ioctl command to execute 9093 **/ 9094 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9095 { 9096 struct igb_adapter *adapter = netdev_priv(netdev); 9097 struct mii_ioctl_data *data = if_mii(ifr); 9098 9099 if (adapter->hw.phy.media_type != e1000_media_type_copper) 9100 return -EOPNOTSUPP; 9101 9102 switch (cmd) { 9103 case SIOCGMIIPHY: 9104 data->phy_id = adapter->hw.phy.addr; 9105 break; 9106 case SIOCGMIIREG: 9107 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9108 &data->val_out)) 9109 return -EIO; 9110 break; 9111 case SIOCSMIIREG: 9112 default: 9113 return -EOPNOTSUPP; 9114 } 9115 return 0; 9116 } 9117 9118 /** 9119 * igb_ioctl - 9120 * @netdev: pointer to netdev struct 9121 * @ifr: interface structure 9122 * @cmd: ioctl command to execute 9123 **/ 9124 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9125 { 9126 switch (cmd) { 9127 case SIOCGMIIPHY: 9128 case SIOCGMIIREG: 9129 case SIOCSMIIREG: 9130 return igb_mii_ioctl(netdev, ifr, cmd); 9131 case SIOCGHWTSTAMP: 9132 return igb_ptp_get_ts_config(netdev, ifr); 9133 case SIOCSHWTSTAMP: 9134 return igb_ptp_set_ts_config(netdev, ifr); 9135 default: 9136 return -EOPNOTSUPP; 9137 } 9138 } 9139 9140 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9141 { 9142 struct igb_adapter *adapter = hw->back; 9143 9144 pci_read_config_word(adapter->pdev, reg, value); 9145 } 9146 9147 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9148 { 9149 struct igb_adapter *adapter = hw->back; 9150 9151 pci_write_config_word(adapter->pdev, reg, *value); 9152 } 9153 9154 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9155 { 9156 struct igb_adapter *adapter = hw->back; 9157 9158 if (pcie_capability_read_word(adapter->pdev, reg, value)) 9159 return -E1000_ERR_CONFIG; 9160 9161 return 0; 9162 } 9163 9164 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9165 { 9166 struct igb_adapter *adapter = hw->back; 9167 9168 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 9169 return -E1000_ERR_CONFIG; 9170 9171 return 0; 9172 } 9173 9174 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 9175 { 9176 struct igb_adapter *adapter = netdev_priv(netdev); 9177 struct e1000_hw *hw = &adapter->hw; 9178 u32 ctrl, rctl; 9179 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 9180 9181 if (enable) { 9182 /* enable VLAN tag insert/strip */ 9183 ctrl = rd32(E1000_CTRL); 9184 ctrl |= E1000_CTRL_VME; 9185 wr32(E1000_CTRL, ctrl); 9186 9187 /* Disable CFI check */ 9188 rctl = rd32(E1000_RCTL); 9189 rctl &= ~E1000_RCTL_CFIEN; 9190 wr32(E1000_RCTL, rctl); 9191 } else { 9192 /* disable VLAN tag insert/strip */ 9193 ctrl = rd32(E1000_CTRL); 9194 ctrl &= ~E1000_CTRL_VME; 9195 wr32(E1000_CTRL, ctrl); 9196 } 9197 9198 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 9199 } 9200 9201 static int igb_vlan_rx_add_vid(struct net_device *netdev, 9202 __be16 proto, u16 vid) 9203 { 9204 struct igb_adapter *adapter = netdev_priv(netdev); 9205 struct e1000_hw *hw = &adapter->hw; 9206 int pf_id = adapter->vfs_allocated_count; 9207 9208 /* add the filter since PF can receive vlans w/o entry in vlvf */ 9209 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9210 igb_vfta_set(hw, vid, pf_id, true, !!vid); 9211 9212 set_bit(vid, adapter->active_vlans); 9213 9214 return 0; 9215 } 9216 9217 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 9218 __be16 proto, u16 vid) 9219 { 9220 struct igb_adapter *adapter = netdev_priv(netdev); 9221 int pf_id = adapter->vfs_allocated_count; 9222 struct e1000_hw *hw = &adapter->hw; 9223 9224 /* remove VID from filter table */ 9225 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9226 igb_vfta_set(hw, vid, pf_id, false, true); 9227 9228 clear_bit(vid, adapter->active_vlans); 9229 9230 return 0; 9231 } 9232 9233 static void igb_restore_vlan(struct igb_adapter *adapter) 9234 { 9235 u16 vid = 1; 9236 9237 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 9238 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 9239 9240 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 9241 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 9242 } 9243 9244 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 9245 { 9246 struct pci_dev *pdev = adapter->pdev; 9247 struct e1000_mac_info *mac = &adapter->hw.mac; 9248 9249 mac->autoneg = 0; 9250 9251 /* Make sure dplx is at most 1 bit and lsb of speed is not set 9252 * for the switch() below to work 9253 */ 9254 if ((spd & 1) || (dplx & ~1)) 9255 goto err_inval; 9256 9257 /* Fiber NIC's only allow 1000 gbps Full duplex 9258 * and 100Mbps Full duplex for 100baseFx sfp 9259 */ 9260 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 9261 switch (spd + dplx) { 9262 case SPEED_10 + DUPLEX_HALF: 9263 case SPEED_10 + DUPLEX_FULL: 9264 case SPEED_100 + DUPLEX_HALF: 9265 goto err_inval; 9266 default: 9267 break; 9268 } 9269 } 9270 9271 switch (spd + dplx) { 9272 case SPEED_10 + DUPLEX_HALF: 9273 mac->forced_speed_duplex = ADVERTISE_10_HALF; 9274 break; 9275 case SPEED_10 + DUPLEX_FULL: 9276 mac->forced_speed_duplex = ADVERTISE_10_FULL; 9277 break; 9278 case SPEED_100 + DUPLEX_HALF: 9279 mac->forced_speed_duplex = ADVERTISE_100_HALF; 9280 break; 9281 case SPEED_100 + DUPLEX_FULL: 9282 mac->forced_speed_duplex = ADVERTISE_100_FULL; 9283 break; 9284 case SPEED_1000 + DUPLEX_FULL: 9285 mac->autoneg = 1; 9286 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 9287 break; 9288 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 9289 default: 9290 goto err_inval; 9291 } 9292 9293 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 9294 adapter->hw.phy.mdix = AUTO_ALL_MODES; 9295 9296 return 0; 9297 9298 err_inval: 9299 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 9300 return -EINVAL; 9301 } 9302 9303 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 9304 bool runtime) 9305 { 9306 struct net_device *netdev = pci_get_drvdata(pdev); 9307 struct igb_adapter *adapter = netdev_priv(netdev); 9308 struct e1000_hw *hw = &adapter->hw; 9309 u32 ctrl, rctl, status; 9310 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 9311 bool wake; 9312 9313 rtnl_lock(); 9314 netif_device_detach(netdev); 9315 9316 if (netif_running(netdev)) 9317 __igb_close(netdev, true); 9318 9319 igb_ptp_suspend(adapter); 9320 9321 igb_clear_interrupt_scheme(adapter); 9322 rtnl_unlock(); 9323 9324 status = rd32(E1000_STATUS); 9325 if (status & E1000_STATUS_LU) 9326 wufc &= ~E1000_WUFC_LNKC; 9327 9328 if (wufc) { 9329 igb_setup_rctl(adapter); 9330 igb_set_rx_mode(netdev); 9331 9332 /* turn on all-multi mode if wake on multicast is enabled */ 9333 if (wufc & E1000_WUFC_MC) { 9334 rctl = rd32(E1000_RCTL); 9335 rctl |= E1000_RCTL_MPE; 9336 wr32(E1000_RCTL, rctl); 9337 } 9338 9339 ctrl = rd32(E1000_CTRL); 9340 ctrl |= E1000_CTRL_ADVD3WUC; 9341 wr32(E1000_CTRL, ctrl); 9342 9343 /* Allow time for pending master requests to run */ 9344 igb_disable_pcie_master(hw); 9345 9346 wr32(E1000_WUC, E1000_WUC_PME_EN); 9347 wr32(E1000_WUFC, wufc); 9348 } else { 9349 wr32(E1000_WUC, 0); 9350 wr32(E1000_WUFC, 0); 9351 } 9352 9353 wake = wufc || adapter->en_mng_pt; 9354 if (!wake) 9355 igb_power_down_link(adapter); 9356 else 9357 igb_power_up_link(adapter); 9358 9359 if (enable_wake) 9360 *enable_wake = wake; 9361 9362 /* Release control of h/w to f/w. If f/w is AMT enabled, this 9363 * would have already happened in close and is redundant. 9364 */ 9365 igb_release_hw_control(adapter); 9366 9367 pci_disable_device(pdev); 9368 9369 return 0; 9370 } 9371 9372 static void igb_deliver_wake_packet(struct net_device *netdev) 9373 { 9374 struct igb_adapter *adapter = netdev_priv(netdev); 9375 struct e1000_hw *hw = &adapter->hw; 9376 struct sk_buff *skb; 9377 u32 wupl; 9378 9379 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 9380 9381 /* WUPM stores only the first 128 bytes of the wake packet. 9382 * Read the packet only if we have the whole thing. 9383 */ 9384 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 9385 return; 9386 9387 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 9388 if (!skb) 9389 return; 9390 9391 skb_put(skb, wupl); 9392 9393 /* Ensure reads are 32-bit aligned */ 9394 wupl = roundup(wupl, 4); 9395 9396 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 9397 9398 skb->protocol = eth_type_trans(skb, netdev); 9399 netif_rx(skb); 9400 } 9401 9402 static int __maybe_unused igb_suspend(struct device *dev) 9403 { 9404 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 9405 } 9406 9407 static int __maybe_unused __igb_resume(struct device *dev, bool rpm) 9408 { 9409 struct pci_dev *pdev = to_pci_dev(dev); 9410 struct net_device *netdev = pci_get_drvdata(pdev); 9411 struct igb_adapter *adapter = netdev_priv(netdev); 9412 struct e1000_hw *hw = &adapter->hw; 9413 u32 err, val; 9414 9415 pci_set_power_state(pdev, PCI_D0); 9416 pci_restore_state(pdev); 9417 pci_save_state(pdev); 9418 9419 if (!pci_device_is_present(pdev)) 9420 return -ENODEV; 9421 err = pci_enable_device_mem(pdev); 9422 if (err) { 9423 dev_err(&pdev->dev, 9424 "igb: Cannot enable PCI device from suspend\n"); 9425 return err; 9426 } 9427 pci_set_master(pdev); 9428 9429 pci_enable_wake(pdev, PCI_D3hot, 0); 9430 pci_enable_wake(pdev, PCI_D3cold, 0); 9431 9432 if (igb_init_interrupt_scheme(adapter, true)) { 9433 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9434 return -ENOMEM; 9435 } 9436 9437 igb_reset(adapter); 9438 9439 /* let the f/w know that the h/w is now under the control of the 9440 * driver. 9441 */ 9442 igb_get_hw_control(adapter); 9443 9444 val = rd32(E1000_WUS); 9445 if (val & WAKE_PKT_WUS) 9446 igb_deliver_wake_packet(netdev); 9447 9448 wr32(E1000_WUS, ~0); 9449 9450 if (!rpm) 9451 rtnl_lock(); 9452 if (!err && netif_running(netdev)) 9453 err = __igb_open(netdev, true); 9454 9455 if (!err) 9456 netif_device_attach(netdev); 9457 if (!rpm) 9458 rtnl_unlock(); 9459 9460 return err; 9461 } 9462 9463 static int __maybe_unused igb_resume(struct device *dev) 9464 { 9465 return __igb_resume(dev, false); 9466 } 9467 9468 static int __maybe_unused igb_runtime_idle(struct device *dev) 9469 { 9470 struct net_device *netdev = dev_get_drvdata(dev); 9471 struct igb_adapter *adapter = netdev_priv(netdev); 9472 9473 if (!igb_has_link(adapter)) 9474 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 9475 9476 return -EBUSY; 9477 } 9478 9479 static int __maybe_unused igb_runtime_suspend(struct device *dev) 9480 { 9481 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 9482 } 9483 9484 static int __maybe_unused igb_runtime_resume(struct device *dev) 9485 { 9486 return __igb_resume(dev, true); 9487 } 9488 9489 static void igb_shutdown(struct pci_dev *pdev) 9490 { 9491 bool wake; 9492 9493 __igb_shutdown(pdev, &wake, 0); 9494 9495 if (system_state == SYSTEM_POWER_OFF) { 9496 pci_wake_from_d3(pdev, wake); 9497 pci_set_power_state(pdev, PCI_D3hot); 9498 } 9499 } 9500 9501 #ifdef CONFIG_PCI_IOV 9502 static int igb_sriov_reinit(struct pci_dev *dev) 9503 { 9504 struct net_device *netdev = pci_get_drvdata(dev); 9505 struct igb_adapter *adapter = netdev_priv(netdev); 9506 struct pci_dev *pdev = adapter->pdev; 9507 9508 rtnl_lock(); 9509 9510 if (netif_running(netdev)) 9511 igb_close(netdev); 9512 else 9513 igb_reset(adapter); 9514 9515 igb_clear_interrupt_scheme(adapter); 9516 9517 igb_init_queue_configuration(adapter); 9518 9519 if (igb_init_interrupt_scheme(adapter, true)) { 9520 rtnl_unlock(); 9521 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9522 return -ENOMEM; 9523 } 9524 9525 if (netif_running(netdev)) 9526 igb_open(netdev); 9527 9528 rtnl_unlock(); 9529 9530 return 0; 9531 } 9532 9533 static int igb_pci_disable_sriov(struct pci_dev *dev) 9534 { 9535 int err = igb_disable_sriov(dev); 9536 9537 if (!err) 9538 err = igb_sriov_reinit(dev); 9539 9540 return err; 9541 } 9542 9543 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 9544 { 9545 int err = igb_enable_sriov(dev, num_vfs); 9546 9547 if (err) 9548 goto out; 9549 9550 err = igb_sriov_reinit(dev); 9551 if (!err) 9552 return num_vfs; 9553 9554 out: 9555 return err; 9556 } 9557 9558 #endif 9559 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 9560 { 9561 #ifdef CONFIG_PCI_IOV 9562 if (num_vfs == 0) 9563 return igb_pci_disable_sriov(dev); 9564 else 9565 return igb_pci_enable_sriov(dev, num_vfs); 9566 #endif 9567 return 0; 9568 } 9569 9570 /** 9571 * igb_io_error_detected - called when PCI error is detected 9572 * @pdev: Pointer to PCI device 9573 * @state: The current pci connection state 9574 * 9575 * This function is called after a PCI bus error affecting 9576 * this device has been detected. 9577 **/ 9578 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9579 pci_channel_state_t state) 9580 { 9581 struct net_device *netdev = pci_get_drvdata(pdev); 9582 struct igb_adapter *adapter = netdev_priv(netdev); 9583 9584 netif_device_detach(netdev); 9585 9586 if (state == pci_channel_io_perm_failure) 9587 return PCI_ERS_RESULT_DISCONNECT; 9588 9589 if (netif_running(netdev)) 9590 igb_down(adapter); 9591 pci_disable_device(pdev); 9592 9593 /* Request a slot reset. */ 9594 return PCI_ERS_RESULT_NEED_RESET; 9595 } 9596 9597 /** 9598 * igb_io_slot_reset - called after the pci bus has been reset. 9599 * @pdev: Pointer to PCI device 9600 * 9601 * Restart the card from scratch, as if from a cold-boot. Implementation 9602 * resembles the first-half of the __igb_resume routine. 9603 **/ 9604 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9605 { 9606 struct net_device *netdev = pci_get_drvdata(pdev); 9607 struct igb_adapter *adapter = netdev_priv(netdev); 9608 struct e1000_hw *hw = &adapter->hw; 9609 pci_ers_result_t result; 9610 9611 if (pci_enable_device_mem(pdev)) { 9612 dev_err(&pdev->dev, 9613 "Cannot re-enable PCI device after reset.\n"); 9614 result = PCI_ERS_RESULT_DISCONNECT; 9615 } else { 9616 pci_set_master(pdev); 9617 pci_restore_state(pdev); 9618 pci_save_state(pdev); 9619 9620 pci_enable_wake(pdev, PCI_D3hot, 0); 9621 pci_enable_wake(pdev, PCI_D3cold, 0); 9622 9623 /* In case of PCI error, adapter lose its HW address 9624 * so we should re-assign it here. 9625 */ 9626 hw->hw_addr = adapter->io_addr; 9627 9628 igb_reset(adapter); 9629 wr32(E1000_WUS, ~0); 9630 result = PCI_ERS_RESULT_RECOVERED; 9631 } 9632 9633 return result; 9634 } 9635 9636 /** 9637 * igb_io_resume - called when traffic can start flowing again. 9638 * @pdev: Pointer to PCI device 9639 * 9640 * This callback is called when the error recovery driver tells us that 9641 * its OK to resume normal operation. Implementation resembles the 9642 * second-half of the __igb_resume routine. 9643 */ 9644 static void igb_io_resume(struct pci_dev *pdev) 9645 { 9646 struct net_device *netdev = pci_get_drvdata(pdev); 9647 struct igb_adapter *adapter = netdev_priv(netdev); 9648 9649 if (netif_running(netdev)) { 9650 if (igb_up(adapter)) { 9651 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9652 return; 9653 } 9654 } 9655 9656 netif_device_attach(netdev); 9657 9658 /* let the f/w know that the h/w is now under the control of the 9659 * driver. 9660 */ 9661 igb_get_hw_control(adapter); 9662 } 9663 9664 /** 9665 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9666 * @adapter: Pointer to adapter structure 9667 * @index: Index of the RAR entry which need to be synced with MAC table 9668 **/ 9669 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9670 { 9671 struct e1000_hw *hw = &adapter->hw; 9672 u32 rar_low, rar_high; 9673 u8 *addr = adapter->mac_table[index].addr; 9674 9675 /* HW expects these to be in network order when they are plugged 9676 * into the registers which are little endian. In order to guarantee 9677 * that ordering we need to do an leXX_to_cpup here in order to be 9678 * ready for the byteswap that occurs with writel 9679 */ 9680 rar_low = le32_to_cpup((__le32 *)(addr)); 9681 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9682 9683 /* Indicate to hardware the Address is Valid. */ 9684 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9685 if (is_valid_ether_addr(addr)) 9686 rar_high |= E1000_RAH_AV; 9687 9688 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9689 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9690 9691 switch (hw->mac.type) { 9692 case e1000_82575: 9693 case e1000_i210: 9694 if (adapter->mac_table[index].state & 9695 IGB_MAC_STATE_QUEUE_STEERING) 9696 rar_high |= E1000_RAH_QSEL_ENABLE; 9697 9698 rar_high |= E1000_RAH_POOL_1 * 9699 adapter->mac_table[index].queue; 9700 break; 9701 default: 9702 rar_high |= E1000_RAH_POOL_1 << 9703 adapter->mac_table[index].queue; 9704 break; 9705 } 9706 } 9707 9708 wr32(E1000_RAL(index), rar_low); 9709 wrfl(); 9710 wr32(E1000_RAH(index), rar_high); 9711 wrfl(); 9712 } 9713 9714 static int igb_set_vf_mac(struct igb_adapter *adapter, 9715 int vf, unsigned char *mac_addr) 9716 { 9717 struct e1000_hw *hw = &adapter->hw; 9718 /* VF MAC addresses start at end of receive addresses and moves 9719 * towards the first, as a result a collision should not be possible 9720 */ 9721 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9722 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9723 9724 ether_addr_copy(vf_mac_addr, mac_addr); 9725 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9726 adapter->mac_table[rar_entry].queue = vf; 9727 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9728 igb_rar_set_index(adapter, rar_entry); 9729 9730 return 0; 9731 } 9732 9733 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9734 { 9735 struct igb_adapter *adapter = netdev_priv(netdev); 9736 9737 if (vf >= adapter->vfs_allocated_count) 9738 return -EINVAL; 9739 9740 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9741 * flag and allows to overwrite the MAC via VF netdev. This 9742 * is necessary to allow libvirt a way to restore the original 9743 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9744 * down a VM. 9745 */ 9746 if (is_zero_ether_addr(mac)) { 9747 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9748 dev_info(&adapter->pdev->dev, 9749 "remove administratively set MAC on VF %d\n", 9750 vf); 9751 } else if (is_valid_ether_addr(mac)) { 9752 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9753 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9754 mac, vf); 9755 dev_info(&adapter->pdev->dev, 9756 "Reload the VF driver to make this change effective."); 9757 /* Generate additional warning if PF is down */ 9758 if (test_bit(__IGB_DOWN, &adapter->state)) { 9759 dev_warn(&adapter->pdev->dev, 9760 "The VF MAC address has been set, but the PF device is not up.\n"); 9761 dev_warn(&adapter->pdev->dev, 9762 "Bring the PF device up before attempting to use the VF device.\n"); 9763 } 9764 } else { 9765 return -EINVAL; 9766 } 9767 return igb_set_vf_mac(adapter, vf, mac); 9768 } 9769 9770 static int igb_link_mbps(int internal_link_speed) 9771 { 9772 switch (internal_link_speed) { 9773 case SPEED_100: 9774 return 100; 9775 case SPEED_1000: 9776 return 1000; 9777 default: 9778 return 0; 9779 } 9780 } 9781 9782 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9783 int link_speed) 9784 { 9785 int rf_dec, rf_int; 9786 u32 bcnrc_val; 9787 9788 if (tx_rate != 0) { 9789 /* Calculate the rate factor values to set */ 9790 rf_int = link_speed / tx_rate; 9791 rf_dec = (link_speed - (rf_int * tx_rate)); 9792 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9793 tx_rate; 9794 9795 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9796 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 9797 E1000_RTTBCNRC_RF_INT_MASK); 9798 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9799 } else { 9800 bcnrc_val = 0; 9801 } 9802 9803 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9804 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9805 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9806 */ 9807 wr32(E1000_RTTBCNRM, 0x14); 9808 wr32(E1000_RTTBCNRC, bcnrc_val); 9809 } 9810 9811 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9812 { 9813 int actual_link_speed, i; 9814 bool reset_rate = false; 9815 9816 /* VF TX rate limit was not set or not supported */ 9817 if ((adapter->vf_rate_link_speed == 0) || 9818 (adapter->hw.mac.type != e1000_82576)) 9819 return; 9820 9821 actual_link_speed = igb_link_mbps(adapter->link_speed); 9822 if (actual_link_speed != adapter->vf_rate_link_speed) { 9823 reset_rate = true; 9824 adapter->vf_rate_link_speed = 0; 9825 dev_info(&adapter->pdev->dev, 9826 "Link speed has been changed. VF Transmit rate is disabled\n"); 9827 } 9828 9829 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9830 if (reset_rate) 9831 adapter->vf_data[i].tx_rate = 0; 9832 9833 igb_set_vf_rate_limit(&adapter->hw, i, 9834 adapter->vf_data[i].tx_rate, 9835 actual_link_speed); 9836 } 9837 } 9838 9839 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9840 int min_tx_rate, int max_tx_rate) 9841 { 9842 struct igb_adapter *adapter = netdev_priv(netdev); 9843 struct e1000_hw *hw = &adapter->hw; 9844 int actual_link_speed; 9845 9846 if (hw->mac.type != e1000_82576) 9847 return -EOPNOTSUPP; 9848 9849 if (min_tx_rate) 9850 return -EINVAL; 9851 9852 actual_link_speed = igb_link_mbps(adapter->link_speed); 9853 if ((vf >= adapter->vfs_allocated_count) || 9854 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9855 (max_tx_rate < 0) || 9856 (max_tx_rate > actual_link_speed)) 9857 return -EINVAL; 9858 9859 adapter->vf_rate_link_speed = actual_link_speed; 9860 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 9861 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 9862 9863 return 0; 9864 } 9865 9866 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 9867 bool setting) 9868 { 9869 struct igb_adapter *adapter = netdev_priv(netdev); 9870 struct e1000_hw *hw = &adapter->hw; 9871 u32 reg_val, reg_offset; 9872 9873 if (!adapter->vfs_allocated_count) 9874 return -EOPNOTSUPP; 9875 9876 if (vf >= adapter->vfs_allocated_count) 9877 return -EINVAL; 9878 9879 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 9880 reg_val = rd32(reg_offset); 9881 if (setting) 9882 reg_val |= (BIT(vf) | 9883 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9884 else 9885 reg_val &= ~(BIT(vf) | 9886 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9887 wr32(reg_offset, reg_val); 9888 9889 adapter->vf_data[vf].spoofchk_enabled = setting; 9890 return 0; 9891 } 9892 9893 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 9894 { 9895 struct igb_adapter *adapter = netdev_priv(netdev); 9896 9897 if (vf >= adapter->vfs_allocated_count) 9898 return -EINVAL; 9899 if (adapter->vf_data[vf].trusted == setting) 9900 return 0; 9901 9902 adapter->vf_data[vf].trusted = setting; 9903 9904 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 9905 vf, setting ? "" : "not "); 9906 return 0; 9907 } 9908 9909 static int igb_ndo_get_vf_config(struct net_device *netdev, 9910 int vf, struct ifla_vf_info *ivi) 9911 { 9912 struct igb_adapter *adapter = netdev_priv(netdev); 9913 if (vf >= adapter->vfs_allocated_count) 9914 return -EINVAL; 9915 ivi->vf = vf; 9916 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 9917 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 9918 ivi->min_tx_rate = 0; 9919 ivi->vlan = adapter->vf_data[vf].pf_vlan; 9920 ivi->qos = adapter->vf_data[vf].pf_qos; 9921 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 9922 ivi->trusted = adapter->vf_data[vf].trusted; 9923 return 0; 9924 } 9925 9926 static void igb_vmm_control(struct igb_adapter *adapter) 9927 { 9928 struct e1000_hw *hw = &adapter->hw; 9929 u32 reg; 9930 9931 switch (hw->mac.type) { 9932 case e1000_82575: 9933 case e1000_i210: 9934 case e1000_i211: 9935 case e1000_i354: 9936 default: 9937 /* replication is not supported for 82575 */ 9938 return; 9939 case e1000_82576: 9940 /* notify HW that the MAC is adding vlan tags */ 9941 reg = rd32(E1000_DTXCTL); 9942 reg |= E1000_DTXCTL_VLAN_ADDED; 9943 wr32(E1000_DTXCTL, reg); 9944 fallthrough; 9945 case e1000_82580: 9946 /* enable replication vlan tag stripping */ 9947 reg = rd32(E1000_RPLOLR); 9948 reg |= E1000_RPLOLR_STRVLAN; 9949 wr32(E1000_RPLOLR, reg); 9950 fallthrough; 9951 case e1000_i350: 9952 /* none of the above registers are supported by i350 */ 9953 break; 9954 } 9955 9956 if (adapter->vfs_allocated_count) { 9957 igb_vmdq_set_loopback_pf(hw, true); 9958 igb_vmdq_set_replication_pf(hw, true); 9959 igb_vmdq_set_anti_spoofing_pf(hw, true, 9960 adapter->vfs_allocated_count); 9961 } else { 9962 igb_vmdq_set_loopback_pf(hw, false); 9963 igb_vmdq_set_replication_pf(hw, false); 9964 } 9965 } 9966 9967 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 9968 { 9969 struct e1000_hw *hw = &adapter->hw; 9970 u32 dmac_thr; 9971 u16 hwm; 9972 u32 reg; 9973 9974 if (hw->mac.type > e1000_82580) { 9975 if (adapter->flags & IGB_FLAG_DMAC) { 9976 /* force threshold to 0. */ 9977 wr32(E1000_DMCTXTH, 0); 9978 9979 /* DMA Coalescing high water mark needs to be greater 9980 * than the Rx threshold. Set hwm to PBA - max frame 9981 * size in 16B units, capping it at PBA - 6KB. 9982 */ 9983 hwm = 64 * (pba - 6); 9984 reg = rd32(E1000_FCRTC); 9985 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 9986 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 9987 & E1000_FCRTC_RTH_COAL_MASK); 9988 wr32(E1000_FCRTC, reg); 9989 9990 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 9991 * frame size, capping it at PBA - 10KB. 9992 */ 9993 dmac_thr = pba - 10; 9994 reg = rd32(E1000_DMACR); 9995 reg &= ~E1000_DMACR_DMACTHR_MASK; 9996 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 9997 & E1000_DMACR_DMACTHR_MASK); 9998 9999 /* transition to L0x or L1 if available..*/ 10000 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 10001 10002 /* watchdog timer= +-1000 usec in 32usec intervals */ 10003 reg |= (1000 >> 5); 10004 10005 /* Disable BMC-to-OS Watchdog Enable */ 10006 if (hw->mac.type != e1000_i354) 10007 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 10008 wr32(E1000_DMACR, reg); 10009 10010 /* no lower threshold to disable 10011 * coalescing(smart fifb)-UTRESH=0 10012 */ 10013 wr32(E1000_DMCRTRH, 0); 10014 10015 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 10016 10017 wr32(E1000_DMCTLX, reg); 10018 10019 /* free space in tx packet buffer to wake from 10020 * DMA coal 10021 */ 10022 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 10023 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 10024 } 10025 10026 if (hw->mac.type >= e1000_i210 || 10027 (adapter->flags & IGB_FLAG_DMAC)) { 10028 reg = rd32(E1000_PCIEMISC); 10029 reg |= E1000_PCIEMISC_LX_DECISION; 10030 wr32(E1000_PCIEMISC, reg); 10031 } /* endif adapter->dmac is not disabled */ 10032 } else if (hw->mac.type == e1000_82580) { 10033 u32 reg = rd32(E1000_PCIEMISC); 10034 10035 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 10036 wr32(E1000_DMACR, 0); 10037 } 10038 } 10039 10040 /** 10041 * igb_read_i2c_byte - Reads 8 bit word over I2C 10042 * @hw: pointer to hardware structure 10043 * @byte_offset: byte offset to read 10044 * @dev_addr: device address 10045 * @data: value read 10046 * 10047 * Performs byte read operation over I2C interface at 10048 * a specified device address. 10049 **/ 10050 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10051 u8 dev_addr, u8 *data) 10052 { 10053 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10054 struct i2c_client *this_client = adapter->i2c_client; 10055 s32 status; 10056 u16 swfw_mask = 0; 10057 10058 if (!this_client) 10059 return E1000_ERR_I2C; 10060 10061 swfw_mask = E1000_SWFW_PHY0_SM; 10062 10063 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10064 return E1000_ERR_SWFW_SYNC; 10065 10066 status = i2c_smbus_read_byte_data(this_client, byte_offset); 10067 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10068 10069 if (status < 0) 10070 return E1000_ERR_I2C; 10071 else { 10072 *data = status; 10073 return 0; 10074 } 10075 } 10076 10077 /** 10078 * igb_write_i2c_byte - Writes 8 bit word over I2C 10079 * @hw: pointer to hardware structure 10080 * @byte_offset: byte offset to write 10081 * @dev_addr: device address 10082 * @data: value to write 10083 * 10084 * Performs byte write operation over I2C interface at 10085 * a specified device address. 10086 **/ 10087 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10088 u8 dev_addr, u8 data) 10089 { 10090 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10091 struct i2c_client *this_client = adapter->i2c_client; 10092 s32 status; 10093 u16 swfw_mask = E1000_SWFW_PHY0_SM; 10094 10095 if (!this_client) 10096 return E1000_ERR_I2C; 10097 10098 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10099 return E1000_ERR_SWFW_SYNC; 10100 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 10101 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10102 10103 if (status) 10104 return E1000_ERR_I2C; 10105 else 10106 return 0; 10107 10108 } 10109 10110 int igb_reinit_queues(struct igb_adapter *adapter) 10111 { 10112 struct net_device *netdev = adapter->netdev; 10113 struct pci_dev *pdev = adapter->pdev; 10114 int err = 0; 10115 10116 if (netif_running(netdev)) 10117 igb_close(netdev); 10118 10119 igb_reset_interrupt_capability(adapter); 10120 10121 if (igb_init_interrupt_scheme(adapter, true)) { 10122 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 10123 return -ENOMEM; 10124 } 10125 10126 if (netif_running(netdev)) 10127 err = igb_open(netdev); 10128 10129 return err; 10130 } 10131 10132 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 10133 { 10134 struct igb_nfc_filter *rule; 10135 10136 spin_lock(&adapter->nfc_lock); 10137 10138 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10139 igb_erase_filter(adapter, rule); 10140 10141 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 10142 igb_erase_filter(adapter, rule); 10143 10144 spin_unlock(&adapter->nfc_lock); 10145 } 10146 10147 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 10148 { 10149 struct igb_nfc_filter *rule; 10150 10151 spin_lock(&adapter->nfc_lock); 10152 10153 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10154 igb_add_filter(adapter, rule); 10155 10156 spin_unlock(&adapter->nfc_lock); 10157 } 10158 /* igb_main.c */ 10159