1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/sctp.h> 30 #include <linux/if_ether.h> 31 #include <linux/aer.h> 32 #include <linux/prefetch.h> 33 #include <linux/bpf.h> 34 #include <linux/bpf_trace.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/etherdevice.h> 37 #ifdef CONFIG_IGB_DCA 38 #include <linux/dca.h> 39 #endif 40 #include <linux/i2c.h> 41 #include "igb.h" 42 43 enum queue_mode { 44 QUEUE_MODE_STRICT_PRIORITY, 45 QUEUE_MODE_STREAM_RESERVATION, 46 }; 47 48 enum tx_queue_prio { 49 TX_QUEUE_PRIO_HIGH, 50 TX_QUEUE_PRIO_LOW, 51 }; 52 53 char igb_driver_name[] = "igb"; 54 static const char igb_driver_string[] = 55 "Intel(R) Gigabit Ethernet Network Driver"; 56 static const char igb_copyright[] = 57 "Copyright (c) 2007-2014 Intel Corporation."; 58 59 static const struct e1000_info *igb_info_tbl[] = { 60 [board_82575] = &e1000_82575_info, 61 }; 62 63 static const struct pci_device_id igb_pci_tbl[] = { 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 99 /* required last entry */ 100 {0, } 101 }; 102 103 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 104 105 static int igb_setup_all_tx_resources(struct igb_adapter *); 106 static int igb_setup_all_rx_resources(struct igb_adapter *); 107 static void igb_free_all_tx_resources(struct igb_adapter *); 108 static void igb_free_all_rx_resources(struct igb_adapter *); 109 static void igb_setup_mrqc(struct igb_adapter *); 110 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 111 static void igb_remove(struct pci_dev *pdev); 112 static int igb_sw_init(struct igb_adapter *); 113 int igb_open(struct net_device *); 114 int igb_close(struct net_device *); 115 static void igb_configure(struct igb_adapter *); 116 static void igb_configure_tx(struct igb_adapter *); 117 static void igb_configure_rx(struct igb_adapter *); 118 static void igb_clean_all_tx_rings(struct igb_adapter *); 119 static void igb_clean_all_rx_rings(struct igb_adapter *); 120 static void igb_clean_tx_ring(struct igb_ring *); 121 static void igb_clean_rx_ring(struct igb_ring *); 122 static void igb_set_rx_mode(struct net_device *); 123 static void igb_update_phy_info(struct timer_list *); 124 static void igb_watchdog(struct timer_list *); 125 static void igb_watchdog_task(struct work_struct *); 126 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 127 static void igb_get_stats64(struct net_device *dev, 128 struct rtnl_link_stats64 *stats); 129 static int igb_change_mtu(struct net_device *, int); 130 static int igb_set_mac(struct net_device *, void *); 131 static void igb_set_uta(struct igb_adapter *adapter, bool set); 132 static irqreturn_t igb_intr(int irq, void *); 133 static irqreturn_t igb_intr_msi(int irq, void *); 134 static irqreturn_t igb_msix_other(int irq, void *); 135 static irqreturn_t igb_msix_ring(int irq, void *); 136 #ifdef CONFIG_IGB_DCA 137 static void igb_update_dca(struct igb_q_vector *); 138 static void igb_setup_dca(struct igb_adapter *); 139 #endif /* CONFIG_IGB_DCA */ 140 static int igb_poll(struct napi_struct *, int); 141 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 142 static int igb_clean_rx_irq(struct igb_q_vector *, int); 143 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 144 static void igb_tx_timeout(struct net_device *, unsigned int txqueue); 145 static void igb_reset_task(struct work_struct *); 146 static void igb_vlan_mode(struct net_device *netdev, 147 netdev_features_t features); 148 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 149 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 150 static void igb_restore_vlan(struct igb_adapter *); 151 static void igb_rar_set_index(struct igb_adapter *, u32); 152 static void igb_ping_all_vfs(struct igb_adapter *); 153 static void igb_msg_task(struct igb_adapter *); 154 static void igb_vmm_control(struct igb_adapter *); 155 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 156 static void igb_flush_mac_table(struct igb_adapter *); 157 static int igb_available_rars(struct igb_adapter *, u8); 158 static void igb_set_default_mac_filter(struct igb_adapter *); 159 static int igb_uc_sync(struct net_device *, const unsigned char *); 160 static int igb_uc_unsync(struct net_device *, const unsigned char *); 161 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 162 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 163 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 164 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 165 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 166 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 167 bool setting); 168 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 169 bool setting); 170 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 171 struct ifla_vf_info *ivi); 172 static void igb_check_vf_rate_limit(struct igb_adapter *); 173 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 174 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 175 176 #ifdef CONFIG_PCI_IOV 177 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 178 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 179 static int igb_disable_sriov(struct pci_dev *dev); 180 static int igb_pci_disable_sriov(struct pci_dev *dev); 181 #endif 182 183 static int igb_suspend(struct device *); 184 static int igb_resume(struct device *); 185 static int igb_runtime_suspend(struct device *dev); 186 static int igb_runtime_resume(struct device *dev); 187 static int igb_runtime_idle(struct device *dev); 188 static const struct dev_pm_ops igb_pm_ops = { 189 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 190 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 191 igb_runtime_idle) 192 }; 193 static void igb_shutdown(struct pci_dev *); 194 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 195 #ifdef CONFIG_IGB_DCA 196 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 197 static struct notifier_block dca_notifier = { 198 .notifier_call = igb_notify_dca, 199 .next = NULL, 200 .priority = 0 201 }; 202 #endif 203 #ifdef CONFIG_PCI_IOV 204 static unsigned int max_vfs; 205 module_param(max_vfs, uint, 0); 206 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 207 #endif /* CONFIG_PCI_IOV */ 208 209 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 210 pci_channel_state_t); 211 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 212 static void igb_io_resume(struct pci_dev *); 213 214 static const struct pci_error_handlers igb_err_handler = { 215 .error_detected = igb_io_error_detected, 216 .slot_reset = igb_io_slot_reset, 217 .resume = igb_io_resume, 218 }; 219 220 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 221 222 static struct pci_driver igb_driver = { 223 .name = igb_driver_name, 224 .id_table = igb_pci_tbl, 225 .probe = igb_probe, 226 .remove = igb_remove, 227 #ifdef CONFIG_PM 228 .driver.pm = &igb_pm_ops, 229 #endif 230 .shutdown = igb_shutdown, 231 .sriov_configure = igb_pci_sriov_configure, 232 .err_handler = &igb_err_handler 233 }; 234 235 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 236 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 237 MODULE_LICENSE("GPL v2"); 238 239 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 240 static int debug = -1; 241 module_param(debug, int, 0); 242 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 243 244 struct igb_reg_info { 245 u32 ofs; 246 char *name; 247 }; 248 249 static const struct igb_reg_info igb_reg_info_tbl[] = { 250 251 /* General Registers */ 252 {E1000_CTRL, "CTRL"}, 253 {E1000_STATUS, "STATUS"}, 254 {E1000_CTRL_EXT, "CTRL_EXT"}, 255 256 /* Interrupt Registers */ 257 {E1000_ICR, "ICR"}, 258 259 /* RX Registers */ 260 {E1000_RCTL, "RCTL"}, 261 {E1000_RDLEN(0), "RDLEN"}, 262 {E1000_RDH(0), "RDH"}, 263 {E1000_RDT(0), "RDT"}, 264 {E1000_RXDCTL(0), "RXDCTL"}, 265 {E1000_RDBAL(0), "RDBAL"}, 266 {E1000_RDBAH(0), "RDBAH"}, 267 268 /* TX Registers */ 269 {E1000_TCTL, "TCTL"}, 270 {E1000_TDBAL(0), "TDBAL"}, 271 {E1000_TDBAH(0), "TDBAH"}, 272 {E1000_TDLEN(0), "TDLEN"}, 273 {E1000_TDH(0), "TDH"}, 274 {E1000_TDT(0), "TDT"}, 275 {E1000_TXDCTL(0), "TXDCTL"}, 276 {E1000_TDFH, "TDFH"}, 277 {E1000_TDFT, "TDFT"}, 278 {E1000_TDFHS, "TDFHS"}, 279 {E1000_TDFPC, "TDFPC"}, 280 281 /* List Terminator */ 282 {} 283 }; 284 285 /* igb_regdump - register printout routine */ 286 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 287 { 288 int n = 0; 289 char rname[16]; 290 u32 regs[8]; 291 292 switch (reginfo->ofs) { 293 case E1000_RDLEN(0): 294 for (n = 0; n < 4; n++) 295 regs[n] = rd32(E1000_RDLEN(n)); 296 break; 297 case E1000_RDH(0): 298 for (n = 0; n < 4; n++) 299 regs[n] = rd32(E1000_RDH(n)); 300 break; 301 case E1000_RDT(0): 302 for (n = 0; n < 4; n++) 303 regs[n] = rd32(E1000_RDT(n)); 304 break; 305 case E1000_RXDCTL(0): 306 for (n = 0; n < 4; n++) 307 regs[n] = rd32(E1000_RXDCTL(n)); 308 break; 309 case E1000_RDBAL(0): 310 for (n = 0; n < 4; n++) 311 regs[n] = rd32(E1000_RDBAL(n)); 312 break; 313 case E1000_RDBAH(0): 314 for (n = 0; n < 4; n++) 315 regs[n] = rd32(E1000_RDBAH(n)); 316 break; 317 case E1000_TDBAL(0): 318 for (n = 0; n < 4; n++) 319 regs[n] = rd32(E1000_TDBAL(n)); 320 break; 321 case E1000_TDBAH(0): 322 for (n = 0; n < 4; n++) 323 regs[n] = rd32(E1000_TDBAH(n)); 324 break; 325 case E1000_TDLEN(0): 326 for (n = 0; n < 4; n++) 327 regs[n] = rd32(E1000_TDLEN(n)); 328 break; 329 case E1000_TDH(0): 330 for (n = 0; n < 4; n++) 331 regs[n] = rd32(E1000_TDH(n)); 332 break; 333 case E1000_TDT(0): 334 for (n = 0; n < 4; n++) 335 regs[n] = rd32(E1000_TDT(n)); 336 break; 337 case E1000_TXDCTL(0): 338 for (n = 0; n < 4; n++) 339 regs[n] = rd32(E1000_TXDCTL(n)); 340 break; 341 default: 342 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 343 return; 344 } 345 346 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 347 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 348 regs[2], regs[3]); 349 } 350 351 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 352 static void igb_dump(struct igb_adapter *adapter) 353 { 354 struct net_device *netdev = adapter->netdev; 355 struct e1000_hw *hw = &adapter->hw; 356 struct igb_reg_info *reginfo; 357 struct igb_ring *tx_ring; 358 union e1000_adv_tx_desc *tx_desc; 359 struct my_u0 { __le64 a; __le64 b; } *u0; 360 struct igb_ring *rx_ring; 361 union e1000_adv_rx_desc *rx_desc; 362 u32 staterr; 363 u16 i, n; 364 365 if (!netif_msg_hw(adapter)) 366 return; 367 368 /* Print netdevice Info */ 369 if (netdev) { 370 dev_info(&adapter->pdev->dev, "Net device Info\n"); 371 pr_info("Device Name state trans_start\n"); 372 pr_info("%-15s %016lX %016lX\n", netdev->name, 373 netdev->state, dev_trans_start(netdev)); 374 } 375 376 /* Print Registers */ 377 dev_info(&adapter->pdev->dev, "Register Dump\n"); 378 pr_info(" Register Name Value\n"); 379 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 380 reginfo->name; reginfo++) { 381 igb_regdump(hw, reginfo); 382 } 383 384 /* Print TX Ring Summary */ 385 if (!netdev || !netif_running(netdev)) 386 goto exit; 387 388 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 389 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 390 for (n = 0; n < adapter->num_tx_queues; n++) { 391 struct igb_tx_buffer *buffer_info; 392 tx_ring = adapter->tx_ring[n]; 393 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 394 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 395 n, tx_ring->next_to_use, tx_ring->next_to_clean, 396 (u64)dma_unmap_addr(buffer_info, dma), 397 dma_unmap_len(buffer_info, len), 398 buffer_info->next_to_watch, 399 (u64)buffer_info->time_stamp); 400 } 401 402 /* Print TX Rings */ 403 if (!netif_msg_tx_done(adapter)) 404 goto rx_ring_summary; 405 406 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 407 408 /* Transmit Descriptor Formats 409 * 410 * Advanced Transmit Descriptor 411 * +--------------------------------------------------------------+ 412 * 0 | Buffer Address [63:0] | 413 * +--------------------------------------------------------------+ 414 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 415 * +--------------------------------------------------------------+ 416 * 63 46 45 40 39 38 36 35 32 31 24 15 0 417 */ 418 419 for (n = 0; n < adapter->num_tx_queues; n++) { 420 tx_ring = adapter->tx_ring[n]; 421 pr_info("------------------------------------\n"); 422 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 423 pr_info("------------------------------------\n"); 424 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 425 426 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 427 const char *next_desc; 428 struct igb_tx_buffer *buffer_info; 429 tx_desc = IGB_TX_DESC(tx_ring, i); 430 buffer_info = &tx_ring->tx_buffer_info[i]; 431 u0 = (struct my_u0 *)tx_desc; 432 if (i == tx_ring->next_to_use && 433 i == tx_ring->next_to_clean) 434 next_desc = " NTC/U"; 435 else if (i == tx_ring->next_to_use) 436 next_desc = " NTU"; 437 else if (i == tx_ring->next_to_clean) 438 next_desc = " NTC"; 439 else 440 next_desc = ""; 441 442 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 443 i, le64_to_cpu(u0->a), 444 le64_to_cpu(u0->b), 445 (u64)dma_unmap_addr(buffer_info, dma), 446 dma_unmap_len(buffer_info, len), 447 buffer_info->next_to_watch, 448 (u64)buffer_info->time_stamp, 449 buffer_info->skb, next_desc); 450 451 if (netif_msg_pktdata(adapter) && buffer_info->skb) 452 print_hex_dump(KERN_INFO, "", 453 DUMP_PREFIX_ADDRESS, 454 16, 1, buffer_info->skb->data, 455 dma_unmap_len(buffer_info, len), 456 true); 457 } 458 } 459 460 /* Print RX Rings Summary */ 461 rx_ring_summary: 462 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 463 pr_info("Queue [NTU] [NTC]\n"); 464 for (n = 0; n < adapter->num_rx_queues; n++) { 465 rx_ring = adapter->rx_ring[n]; 466 pr_info(" %5d %5X %5X\n", 467 n, rx_ring->next_to_use, rx_ring->next_to_clean); 468 } 469 470 /* Print RX Rings */ 471 if (!netif_msg_rx_status(adapter)) 472 goto exit; 473 474 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 475 476 /* Advanced Receive Descriptor (Read) Format 477 * 63 1 0 478 * +-----------------------------------------------------+ 479 * 0 | Packet Buffer Address [63:1] |A0/NSE| 480 * +----------------------------------------------+------+ 481 * 8 | Header Buffer Address [63:1] | DD | 482 * +-----------------------------------------------------+ 483 * 484 * 485 * Advanced Receive Descriptor (Write-Back) Format 486 * 487 * 63 48 47 32 31 30 21 20 17 16 4 3 0 488 * +------------------------------------------------------+ 489 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 490 * | Checksum Ident | | | | Type | Type | 491 * +------------------------------------------------------+ 492 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 493 * +------------------------------------------------------+ 494 * 63 48 47 32 31 20 19 0 495 */ 496 497 for (n = 0; n < adapter->num_rx_queues; n++) { 498 rx_ring = adapter->rx_ring[n]; 499 pr_info("------------------------------------\n"); 500 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 501 pr_info("------------------------------------\n"); 502 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 503 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 504 505 for (i = 0; i < rx_ring->count; i++) { 506 const char *next_desc; 507 struct igb_rx_buffer *buffer_info; 508 buffer_info = &rx_ring->rx_buffer_info[i]; 509 rx_desc = IGB_RX_DESC(rx_ring, i); 510 u0 = (struct my_u0 *)rx_desc; 511 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 512 513 if (i == rx_ring->next_to_use) 514 next_desc = " NTU"; 515 else if (i == rx_ring->next_to_clean) 516 next_desc = " NTC"; 517 else 518 next_desc = ""; 519 520 if (staterr & E1000_RXD_STAT_DD) { 521 /* Descriptor Done */ 522 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 523 "RWB", i, 524 le64_to_cpu(u0->a), 525 le64_to_cpu(u0->b), 526 next_desc); 527 } else { 528 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 529 "R ", i, 530 le64_to_cpu(u0->a), 531 le64_to_cpu(u0->b), 532 (u64)buffer_info->dma, 533 next_desc); 534 535 if (netif_msg_pktdata(adapter) && 536 buffer_info->dma && buffer_info->page) { 537 print_hex_dump(KERN_INFO, "", 538 DUMP_PREFIX_ADDRESS, 539 16, 1, 540 page_address(buffer_info->page) + 541 buffer_info->page_offset, 542 igb_rx_bufsz(rx_ring), true); 543 } 544 } 545 } 546 } 547 548 exit: 549 return; 550 } 551 552 /** 553 * igb_get_i2c_data - Reads the I2C SDA data bit 554 * @data: opaque pointer to adapter struct 555 * 556 * Returns the I2C data bit value 557 **/ 558 static int igb_get_i2c_data(void *data) 559 { 560 struct igb_adapter *adapter = (struct igb_adapter *)data; 561 struct e1000_hw *hw = &adapter->hw; 562 s32 i2cctl = rd32(E1000_I2CPARAMS); 563 564 return !!(i2cctl & E1000_I2C_DATA_IN); 565 } 566 567 /** 568 * igb_set_i2c_data - Sets the I2C data bit 569 * @data: pointer to hardware structure 570 * @state: I2C data value (0 or 1) to set 571 * 572 * Sets the I2C data bit 573 **/ 574 static void igb_set_i2c_data(void *data, int state) 575 { 576 struct igb_adapter *adapter = (struct igb_adapter *)data; 577 struct e1000_hw *hw = &adapter->hw; 578 s32 i2cctl = rd32(E1000_I2CPARAMS); 579 580 if (state) { 581 i2cctl |= E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N; 582 } else { 583 i2cctl &= ~E1000_I2C_DATA_OE_N; 584 i2cctl &= ~E1000_I2C_DATA_OUT; 585 } 586 587 wr32(E1000_I2CPARAMS, i2cctl); 588 wrfl(); 589 } 590 591 /** 592 * igb_set_i2c_clk - Sets the I2C SCL clock 593 * @data: pointer to hardware structure 594 * @state: state to set clock 595 * 596 * Sets the I2C clock line to state 597 **/ 598 static void igb_set_i2c_clk(void *data, int state) 599 { 600 struct igb_adapter *adapter = (struct igb_adapter *)data; 601 struct e1000_hw *hw = &adapter->hw; 602 s32 i2cctl = rd32(E1000_I2CPARAMS); 603 604 if (state) { 605 i2cctl |= E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N; 606 } else { 607 i2cctl &= ~E1000_I2C_CLK_OUT; 608 i2cctl &= ~E1000_I2C_CLK_OE_N; 609 } 610 wr32(E1000_I2CPARAMS, i2cctl); 611 wrfl(); 612 } 613 614 /** 615 * igb_get_i2c_clk - Gets the I2C SCL clock state 616 * @data: pointer to hardware structure 617 * 618 * Gets the I2C clock state 619 **/ 620 static int igb_get_i2c_clk(void *data) 621 { 622 struct igb_adapter *adapter = (struct igb_adapter *)data; 623 struct e1000_hw *hw = &adapter->hw; 624 s32 i2cctl = rd32(E1000_I2CPARAMS); 625 626 return !!(i2cctl & E1000_I2C_CLK_IN); 627 } 628 629 static const struct i2c_algo_bit_data igb_i2c_algo = { 630 .setsda = igb_set_i2c_data, 631 .setscl = igb_set_i2c_clk, 632 .getsda = igb_get_i2c_data, 633 .getscl = igb_get_i2c_clk, 634 .udelay = 5, 635 .timeout = 20, 636 }; 637 638 /** 639 * igb_get_hw_dev - return device 640 * @hw: pointer to hardware structure 641 * 642 * used by hardware layer to print debugging information 643 **/ 644 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 645 { 646 struct igb_adapter *adapter = hw->back; 647 return adapter->netdev; 648 } 649 650 /** 651 * igb_init_module - Driver Registration Routine 652 * 653 * igb_init_module is the first routine called when the driver is 654 * loaded. All it does is register with the PCI subsystem. 655 **/ 656 static int __init igb_init_module(void) 657 { 658 int ret; 659 660 pr_info("%s\n", igb_driver_string); 661 pr_info("%s\n", igb_copyright); 662 663 #ifdef CONFIG_IGB_DCA 664 dca_register_notify(&dca_notifier); 665 #endif 666 ret = pci_register_driver(&igb_driver); 667 return ret; 668 } 669 670 module_init(igb_init_module); 671 672 /** 673 * igb_exit_module - Driver Exit Cleanup Routine 674 * 675 * igb_exit_module is called just before the driver is removed 676 * from memory. 677 **/ 678 static void __exit igb_exit_module(void) 679 { 680 #ifdef CONFIG_IGB_DCA 681 dca_unregister_notify(&dca_notifier); 682 #endif 683 pci_unregister_driver(&igb_driver); 684 } 685 686 module_exit(igb_exit_module); 687 688 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 689 /** 690 * igb_cache_ring_register - Descriptor ring to register mapping 691 * @adapter: board private structure to initialize 692 * 693 * Once we know the feature-set enabled for the device, we'll cache 694 * the register offset the descriptor ring is assigned to. 695 **/ 696 static void igb_cache_ring_register(struct igb_adapter *adapter) 697 { 698 int i = 0, j = 0; 699 u32 rbase_offset = adapter->vfs_allocated_count; 700 701 switch (adapter->hw.mac.type) { 702 case e1000_82576: 703 /* The queues are allocated for virtualization such that VF 0 704 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 705 * In order to avoid collision we start at the first free queue 706 * and continue consuming queues in the same sequence 707 */ 708 if (adapter->vfs_allocated_count) { 709 for (; i < adapter->rss_queues; i++) 710 adapter->rx_ring[i]->reg_idx = rbase_offset + 711 Q_IDX_82576(i); 712 } 713 fallthrough; 714 case e1000_82575: 715 case e1000_82580: 716 case e1000_i350: 717 case e1000_i354: 718 case e1000_i210: 719 case e1000_i211: 720 default: 721 for (; i < adapter->num_rx_queues; i++) 722 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 723 for (; j < adapter->num_tx_queues; j++) 724 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 725 break; 726 } 727 } 728 729 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 730 { 731 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 732 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 733 u32 value = 0; 734 735 if (E1000_REMOVED(hw_addr)) 736 return ~value; 737 738 value = readl(&hw_addr[reg]); 739 740 /* reads should not return all F's */ 741 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 742 struct net_device *netdev = igb->netdev; 743 hw->hw_addr = NULL; 744 netdev_err(netdev, "PCIe link lost\n"); 745 WARN(pci_device_is_present(igb->pdev), 746 "igb: Failed to read reg 0x%x!\n", reg); 747 } 748 749 return value; 750 } 751 752 /** 753 * igb_write_ivar - configure ivar for given MSI-X vector 754 * @hw: pointer to the HW structure 755 * @msix_vector: vector number we are allocating to a given ring 756 * @index: row index of IVAR register to write within IVAR table 757 * @offset: column offset of in IVAR, should be multiple of 8 758 * 759 * This function is intended to handle the writing of the IVAR register 760 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 761 * each containing an cause allocation for an Rx and Tx ring, and a 762 * variable number of rows depending on the number of queues supported. 763 **/ 764 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 765 int index, int offset) 766 { 767 u32 ivar = array_rd32(E1000_IVAR0, index); 768 769 /* clear any bits that are currently set */ 770 ivar &= ~((u32)0xFF << offset); 771 772 /* write vector and valid bit */ 773 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 774 775 array_wr32(E1000_IVAR0, index, ivar); 776 } 777 778 #define IGB_N0_QUEUE -1 779 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 780 { 781 struct igb_adapter *adapter = q_vector->adapter; 782 struct e1000_hw *hw = &adapter->hw; 783 int rx_queue = IGB_N0_QUEUE; 784 int tx_queue = IGB_N0_QUEUE; 785 u32 msixbm = 0; 786 787 if (q_vector->rx.ring) 788 rx_queue = q_vector->rx.ring->reg_idx; 789 if (q_vector->tx.ring) 790 tx_queue = q_vector->tx.ring->reg_idx; 791 792 switch (hw->mac.type) { 793 case e1000_82575: 794 /* The 82575 assigns vectors using a bitmask, which matches the 795 * bitmask for the EICR/EIMS/EIMC registers. To assign one 796 * or more queues to a vector, we write the appropriate bits 797 * into the MSIXBM register for that vector. 798 */ 799 if (rx_queue > IGB_N0_QUEUE) 800 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 801 if (tx_queue > IGB_N0_QUEUE) 802 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 803 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 804 msixbm |= E1000_EIMS_OTHER; 805 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 806 q_vector->eims_value = msixbm; 807 break; 808 case e1000_82576: 809 /* 82576 uses a table that essentially consists of 2 columns 810 * with 8 rows. The ordering is column-major so we use the 811 * lower 3 bits as the row index, and the 4th bit as the 812 * column offset. 813 */ 814 if (rx_queue > IGB_N0_QUEUE) 815 igb_write_ivar(hw, msix_vector, 816 rx_queue & 0x7, 817 (rx_queue & 0x8) << 1); 818 if (tx_queue > IGB_N0_QUEUE) 819 igb_write_ivar(hw, msix_vector, 820 tx_queue & 0x7, 821 ((tx_queue & 0x8) << 1) + 8); 822 q_vector->eims_value = BIT(msix_vector); 823 break; 824 case e1000_82580: 825 case e1000_i350: 826 case e1000_i354: 827 case e1000_i210: 828 case e1000_i211: 829 /* On 82580 and newer adapters the scheme is similar to 82576 830 * however instead of ordering column-major we have things 831 * ordered row-major. So we traverse the table by using 832 * bit 0 as the column offset, and the remaining bits as the 833 * row index. 834 */ 835 if (rx_queue > IGB_N0_QUEUE) 836 igb_write_ivar(hw, msix_vector, 837 rx_queue >> 1, 838 (rx_queue & 0x1) << 4); 839 if (tx_queue > IGB_N0_QUEUE) 840 igb_write_ivar(hw, msix_vector, 841 tx_queue >> 1, 842 ((tx_queue & 0x1) << 4) + 8); 843 q_vector->eims_value = BIT(msix_vector); 844 break; 845 default: 846 BUG(); 847 break; 848 } 849 850 /* add q_vector eims value to global eims_enable_mask */ 851 adapter->eims_enable_mask |= q_vector->eims_value; 852 853 /* configure q_vector to set itr on first interrupt */ 854 q_vector->set_itr = 1; 855 } 856 857 /** 858 * igb_configure_msix - Configure MSI-X hardware 859 * @adapter: board private structure to initialize 860 * 861 * igb_configure_msix sets up the hardware to properly 862 * generate MSI-X interrupts. 863 **/ 864 static void igb_configure_msix(struct igb_adapter *adapter) 865 { 866 u32 tmp; 867 int i, vector = 0; 868 struct e1000_hw *hw = &adapter->hw; 869 870 adapter->eims_enable_mask = 0; 871 872 /* set vector for other causes, i.e. link changes */ 873 switch (hw->mac.type) { 874 case e1000_82575: 875 tmp = rd32(E1000_CTRL_EXT); 876 /* enable MSI-X PBA support*/ 877 tmp |= E1000_CTRL_EXT_PBA_CLR; 878 879 /* Auto-Mask interrupts upon ICR read. */ 880 tmp |= E1000_CTRL_EXT_EIAME; 881 tmp |= E1000_CTRL_EXT_IRCA; 882 883 wr32(E1000_CTRL_EXT, tmp); 884 885 /* enable msix_other interrupt */ 886 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 887 adapter->eims_other = E1000_EIMS_OTHER; 888 889 break; 890 891 case e1000_82576: 892 case e1000_82580: 893 case e1000_i350: 894 case e1000_i354: 895 case e1000_i210: 896 case e1000_i211: 897 /* Turn on MSI-X capability first, or our settings 898 * won't stick. And it will take days to debug. 899 */ 900 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 901 E1000_GPIE_PBA | E1000_GPIE_EIAME | 902 E1000_GPIE_NSICR); 903 904 /* enable msix_other interrupt */ 905 adapter->eims_other = BIT(vector); 906 tmp = (vector++ | E1000_IVAR_VALID) << 8; 907 908 wr32(E1000_IVAR_MISC, tmp); 909 break; 910 default: 911 /* do nothing, since nothing else supports MSI-X */ 912 break; 913 } /* switch (hw->mac.type) */ 914 915 adapter->eims_enable_mask |= adapter->eims_other; 916 917 for (i = 0; i < adapter->num_q_vectors; i++) 918 igb_assign_vector(adapter->q_vector[i], vector++); 919 920 wrfl(); 921 } 922 923 /** 924 * igb_request_msix - Initialize MSI-X interrupts 925 * @adapter: board private structure to initialize 926 * 927 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 928 * kernel. 929 **/ 930 static int igb_request_msix(struct igb_adapter *adapter) 931 { 932 unsigned int num_q_vectors = adapter->num_q_vectors; 933 struct net_device *netdev = adapter->netdev; 934 int i, err = 0, vector = 0, free_vector = 0; 935 936 err = request_irq(adapter->msix_entries[vector].vector, 937 igb_msix_other, 0, netdev->name, adapter); 938 if (err) 939 goto err_out; 940 941 if (num_q_vectors > MAX_Q_VECTORS) { 942 num_q_vectors = MAX_Q_VECTORS; 943 dev_warn(&adapter->pdev->dev, 944 "The number of queue vectors (%d) is higher than max allowed (%d)\n", 945 adapter->num_q_vectors, MAX_Q_VECTORS); 946 } 947 for (i = 0; i < num_q_vectors; i++) { 948 struct igb_q_vector *q_vector = adapter->q_vector[i]; 949 950 vector++; 951 952 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 953 954 if (q_vector->rx.ring && q_vector->tx.ring) 955 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 956 q_vector->rx.ring->queue_index); 957 else if (q_vector->tx.ring) 958 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 959 q_vector->tx.ring->queue_index); 960 else if (q_vector->rx.ring) 961 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 962 q_vector->rx.ring->queue_index); 963 else 964 sprintf(q_vector->name, "%s-unused", netdev->name); 965 966 err = request_irq(adapter->msix_entries[vector].vector, 967 igb_msix_ring, 0, q_vector->name, 968 q_vector); 969 if (err) 970 goto err_free; 971 } 972 973 igb_configure_msix(adapter); 974 return 0; 975 976 err_free: 977 /* free already assigned IRQs */ 978 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 979 980 vector--; 981 for (i = 0; i < vector; i++) { 982 free_irq(adapter->msix_entries[free_vector++].vector, 983 adapter->q_vector[i]); 984 } 985 err_out: 986 return err; 987 } 988 989 /** 990 * igb_free_q_vector - Free memory allocated for specific interrupt vector 991 * @adapter: board private structure to initialize 992 * @v_idx: Index of vector to be freed 993 * 994 * This function frees the memory allocated to the q_vector. 995 **/ 996 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 997 { 998 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 999 1000 adapter->q_vector[v_idx] = NULL; 1001 1002 /* igb_get_stats64() might access the rings on this vector, 1003 * we must wait a grace period before freeing it. 1004 */ 1005 if (q_vector) 1006 kfree_rcu(q_vector, rcu); 1007 } 1008 1009 /** 1010 * igb_reset_q_vector - Reset config for interrupt vector 1011 * @adapter: board private structure to initialize 1012 * @v_idx: Index of vector to be reset 1013 * 1014 * If NAPI is enabled it will delete any references to the 1015 * NAPI struct. This is preparation for igb_free_q_vector. 1016 **/ 1017 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1018 { 1019 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1020 1021 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1022 * allocated. So, q_vector is NULL so we should stop here. 1023 */ 1024 if (!q_vector) 1025 return; 1026 1027 if (q_vector->tx.ring) 1028 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1029 1030 if (q_vector->rx.ring) 1031 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1032 1033 netif_napi_del(&q_vector->napi); 1034 1035 } 1036 1037 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1038 { 1039 int v_idx = adapter->num_q_vectors; 1040 1041 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1042 pci_disable_msix(adapter->pdev); 1043 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1044 pci_disable_msi(adapter->pdev); 1045 1046 while (v_idx--) 1047 igb_reset_q_vector(adapter, v_idx); 1048 } 1049 1050 /** 1051 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1052 * @adapter: board private structure to initialize 1053 * 1054 * This function frees the memory allocated to the q_vectors. In addition if 1055 * NAPI is enabled it will delete any references to the NAPI struct prior 1056 * to freeing the q_vector. 1057 **/ 1058 static void igb_free_q_vectors(struct igb_adapter *adapter) 1059 { 1060 int v_idx = adapter->num_q_vectors; 1061 1062 adapter->num_tx_queues = 0; 1063 adapter->num_rx_queues = 0; 1064 adapter->num_q_vectors = 0; 1065 1066 while (v_idx--) { 1067 igb_reset_q_vector(adapter, v_idx); 1068 igb_free_q_vector(adapter, v_idx); 1069 } 1070 } 1071 1072 /** 1073 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1074 * @adapter: board private structure to initialize 1075 * 1076 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1077 * MSI-X interrupts allocated. 1078 */ 1079 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1080 { 1081 igb_free_q_vectors(adapter); 1082 igb_reset_interrupt_capability(adapter); 1083 } 1084 1085 /** 1086 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1087 * @adapter: board private structure to initialize 1088 * @msix: boolean value of MSIX capability 1089 * 1090 * Attempt to configure interrupts using the best available 1091 * capabilities of the hardware and kernel. 1092 **/ 1093 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1094 { 1095 int err; 1096 int numvecs, i; 1097 1098 if (!msix) 1099 goto msi_only; 1100 adapter->flags |= IGB_FLAG_HAS_MSIX; 1101 1102 /* Number of supported queues. */ 1103 adapter->num_rx_queues = adapter->rss_queues; 1104 if (adapter->vfs_allocated_count) 1105 adapter->num_tx_queues = 1; 1106 else 1107 adapter->num_tx_queues = adapter->rss_queues; 1108 1109 /* start with one vector for every Rx queue */ 1110 numvecs = adapter->num_rx_queues; 1111 1112 /* if Tx handler is separate add 1 for every Tx queue */ 1113 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1114 numvecs += adapter->num_tx_queues; 1115 1116 /* store the number of vectors reserved for queues */ 1117 adapter->num_q_vectors = numvecs; 1118 1119 /* add 1 vector for link status interrupts */ 1120 numvecs++; 1121 for (i = 0; i < numvecs; i++) 1122 adapter->msix_entries[i].entry = i; 1123 1124 err = pci_enable_msix_range(adapter->pdev, 1125 adapter->msix_entries, 1126 numvecs, 1127 numvecs); 1128 if (err > 0) 1129 return; 1130 1131 igb_reset_interrupt_capability(adapter); 1132 1133 /* If we can't do MSI-X, try MSI */ 1134 msi_only: 1135 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1136 #ifdef CONFIG_PCI_IOV 1137 /* disable SR-IOV for non MSI-X configurations */ 1138 if (adapter->vf_data) { 1139 struct e1000_hw *hw = &adapter->hw; 1140 /* disable iov and allow time for transactions to clear */ 1141 pci_disable_sriov(adapter->pdev); 1142 msleep(500); 1143 1144 kfree(adapter->vf_mac_list); 1145 adapter->vf_mac_list = NULL; 1146 kfree(adapter->vf_data); 1147 adapter->vf_data = NULL; 1148 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1149 wrfl(); 1150 msleep(100); 1151 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1152 } 1153 #endif 1154 adapter->vfs_allocated_count = 0; 1155 adapter->rss_queues = 1; 1156 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1157 adapter->num_rx_queues = 1; 1158 adapter->num_tx_queues = 1; 1159 adapter->num_q_vectors = 1; 1160 if (!pci_enable_msi(adapter->pdev)) 1161 adapter->flags |= IGB_FLAG_HAS_MSI; 1162 } 1163 1164 static void igb_add_ring(struct igb_ring *ring, 1165 struct igb_ring_container *head) 1166 { 1167 head->ring = ring; 1168 head->count++; 1169 } 1170 1171 /** 1172 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1173 * @adapter: board private structure to initialize 1174 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1175 * @v_idx: index of vector in adapter struct 1176 * @txr_count: total number of Tx rings to allocate 1177 * @txr_idx: index of first Tx ring to allocate 1178 * @rxr_count: total number of Rx rings to allocate 1179 * @rxr_idx: index of first Rx ring to allocate 1180 * 1181 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1182 **/ 1183 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1184 int v_count, int v_idx, 1185 int txr_count, int txr_idx, 1186 int rxr_count, int rxr_idx) 1187 { 1188 struct igb_q_vector *q_vector; 1189 struct igb_ring *ring; 1190 int ring_count; 1191 size_t size; 1192 1193 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1194 if (txr_count > 1 || rxr_count > 1) 1195 return -ENOMEM; 1196 1197 ring_count = txr_count + rxr_count; 1198 size = kmalloc_size_roundup(struct_size(q_vector, ring, ring_count)); 1199 1200 /* allocate q_vector and rings */ 1201 q_vector = adapter->q_vector[v_idx]; 1202 if (!q_vector) { 1203 q_vector = kzalloc(size, GFP_KERNEL); 1204 } else if (size > ksize(q_vector)) { 1205 struct igb_q_vector *new_q_vector; 1206 1207 new_q_vector = kzalloc(size, GFP_KERNEL); 1208 if (new_q_vector) 1209 kfree_rcu(q_vector, rcu); 1210 q_vector = new_q_vector; 1211 } else { 1212 memset(q_vector, 0, size); 1213 } 1214 if (!q_vector) 1215 return -ENOMEM; 1216 1217 /* initialize NAPI */ 1218 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll); 1219 1220 /* tie q_vector and adapter together */ 1221 adapter->q_vector[v_idx] = q_vector; 1222 q_vector->adapter = adapter; 1223 1224 /* initialize work limits */ 1225 q_vector->tx.work_limit = adapter->tx_work_limit; 1226 1227 /* initialize ITR configuration */ 1228 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1229 q_vector->itr_val = IGB_START_ITR; 1230 1231 /* initialize pointer to rings */ 1232 ring = q_vector->ring; 1233 1234 /* intialize ITR */ 1235 if (rxr_count) { 1236 /* rx or rx/tx vector */ 1237 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1238 q_vector->itr_val = adapter->rx_itr_setting; 1239 } else { 1240 /* tx only vector */ 1241 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1242 q_vector->itr_val = adapter->tx_itr_setting; 1243 } 1244 1245 if (txr_count) { 1246 /* assign generic ring traits */ 1247 ring->dev = &adapter->pdev->dev; 1248 ring->netdev = adapter->netdev; 1249 1250 /* configure backlink on ring */ 1251 ring->q_vector = q_vector; 1252 1253 /* update q_vector Tx values */ 1254 igb_add_ring(ring, &q_vector->tx); 1255 1256 /* For 82575, context index must be unique per ring. */ 1257 if (adapter->hw.mac.type == e1000_82575) 1258 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1259 1260 /* apply Tx specific ring traits */ 1261 ring->count = adapter->tx_ring_count; 1262 ring->queue_index = txr_idx; 1263 1264 ring->cbs_enable = false; 1265 ring->idleslope = 0; 1266 ring->sendslope = 0; 1267 ring->hicredit = 0; 1268 ring->locredit = 0; 1269 1270 u64_stats_init(&ring->tx_syncp); 1271 u64_stats_init(&ring->tx_syncp2); 1272 1273 /* assign ring to adapter */ 1274 adapter->tx_ring[txr_idx] = ring; 1275 1276 /* push pointer to next ring */ 1277 ring++; 1278 } 1279 1280 if (rxr_count) { 1281 /* assign generic ring traits */ 1282 ring->dev = &adapter->pdev->dev; 1283 ring->netdev = adapter->netdev; 1284 1285 /* configure backlink on ring */ 1286 ring->q_vector = q_vector; 1287 1288 /* update q_vector Rx values */ 1289 igb_add_ring(ring, &q_vector->rx); 1290 1291 /* set flag indicating ring supports SCTP checksum offload */ 1292 if (adapter->hw.mac.type >= e1000_82576) 1293 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1294 1295 /* On i350, i354, i210, and i211, loopback VLAN packets 1296 * have the tag byte-swapped. 1297 */ 1298 if (adapter->hw.mac.type >= e1000_i350) 1299 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1300 1301 /* apply Rx specific ring traits */ 1302 ring->count = adapter->rx_ring_count; 1303 ring->queue_index = rxr_idx; 1304 1305 u64_stats_init(&ring->rx_syncp); 1306 1307 /* assign ring to adapter */ 1308 adapter->rx_ring[rxr_idx] = ring; 1309 } 1310 1311 return 0; 1312 } 1313 1314 1315 /** 1316 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1317 * @adapter: board private structure to initialize 1318 * 1319 * We allocate one q_vector per queue interrupt. If allocation fails we 1320 * return -ENOMEM. 1321 **/ 1322 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1323 { 1324 int q_vectors = adapter->num_q_vectors; 1325 int rxr_remaining = adapter->num_rx_queues; 1326 int txr_remaining = adapter->num_tx_queues; 1327 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1328 int err; 1329 1330 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1331 for (; rxr_remaining; v_idx++) { 1332 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1333 0, 0, 1, rxr_idx); 1334 1335 if (err) 1336 goto err_out; 1337 1338 /* update counts and index */ 1339 rxr_remaining--; 1340 rxr_idx++; 1341 } 1342 } 1343 1344 for (; v_idx < q_vectors; v_idx++) { 1345 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1346 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1347 1348 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1349 tqpv, txr_idx, rqpv, rxr_idx); 1350 1351 if (err) 1352 goto err_out; 1353 1354 /* update counts and index */ 1355 rxr_remaining -= rqpv; 1356 txr_remaining -= tqpv; 1357 rxr_idx++; 1358 txr_idx++; 1359 } 1360 1361 return 0; 1362 1363 err_out: 1364 adapter->num_tx_queues = 0; 1365 adapter->num_rx_queues = 0; 1366 adapter->num_q_vectors = 0; 1367 1368 while (v_idx--) 1369 igb_free_q_vector(adapter, v_idx); 1370 1371 return -ENOMEM; 1372 } 1373 1374 /** 1375 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1376 * @adapter: board private structure to initialize 1377 * @msix: boolean value of MSIX capability 1378 * 1379 * This function initializes the interrupts and allocates all of the queues. 1380 **/ 1381 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1382 { 1383 struct pci_dev *pdev = adapter->pdev; 1384 int err; 1385 1386 igb_set_interrupt_capability(adapter, msix); 1387 1388 err = igb_alloc_q_vectors(adapter); 1389 if (err) { 1390 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1391 goto err_alloc_q_vectors; 1392 } 1393 1394 igb_cache_ring_register(adapter); 1395 1396 return 0; 1397 1398 err_alloc_q_vectors: 1399 igb_reset_interrupt_capability(adapter); 1400 return err; 1401 } 1402 1403 /** 1404 * igb_request_irq - initialize interrupts 1405 * @adapter: board private structure to initialize 1406 * 1407 * Attempts to configure interrupts using the best available 1408 * capabilities of the hardware and kernel. 1409 **/ 1410 static int igb_request_irq(struct igb_adapter *adapter) 1411 { 1412 struct net_device *netdev = adapter->netdev; 1413 struct pci_dev *pdev = adapter->pdev; 1414 int err = 0; 1415 1416 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1417 err = igb_request_msix(adapter); 1418 if (!err) 1419 goto request_done; 1420 /* fall back to MSI */ 1421 igb_free_all_tx_resources(adapter); 1422 igb_free_all_rx_resources(adapter); 1423 1424 igb_clear_interrupt_scheme(adapter); 1425 err = igb_init_interrupt_scheme(adapter, false); 1426 if (err) 1427 goto request_done; 1428 1429 igb_setup_all_tx_resources(adapter); 1430 igb_setup_all_rx_resources(adapter); 1431 igb_configure(adapter); 1432 } 1433 1434 igb_assign_vector(adapter->q_vector[0], 0); 1435 1436 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1437 err = request_irq(pdev->irq, igb_intr_msi, 0, 1438 netdev->name, adapter); 1439 if (!err) 1440 goto request_done; 1441 1442 /* fall back to legacy interrupts */ 1443 igb_reset_interrupt_capability(adapter); 1444 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1445 } 1446 1447 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1448 netdev->name, adapter); 1449 1450 if (err) 1451 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1452 err); 1453 1454 request_done: 1455 return err; 1456 } 1457 1458 static void igb_free_irq(struct igb_adapter *adapter) 1459 { 1460 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1461 int vector = 0, i; 1462 1463 free_irq(adapter->msix_entries[vector++].vector, adapter); 1464 1465 for (i = 0; i < adapter->num_q_vectors; i++) 1466 free_irq(adapter->msix_entries[vector++].vector, 1467 adapter->q_vector[i]); 1468 } else { 1469 free_irq(adapter->pdev->irq, adapter); 1470 } 1471 } 1472 1473 /** 1474 * igb_irq_disable - Mask off interrupt generation on the NIC 1475 * @adapter: board private structure 1476 **/ 1477 static void igb_irq_disable(struct igb_adapter *adapter) 1478 { 1479 struct e1000_hw *hw = &adapter->hw; 1480 1481 /* we need to be careful when disabling interrupts. The VFs are also 1482 * mapped into these registers and so clearing the bits can cause 1483 * issues on the VF drivers so we only need to clear what we set 1484 */ 1485 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1486 u32 regval = rd32(E1000_EIAM); 1487 1488 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1489 wr32(E1000_EIMC, adapter->eims_enable_mask); 1490 regval = rd32(E1000_EIAC); 1491 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1492 } 1493 1494 wr32(E1000_IAM, 0); 1495 wr32(E1000_IMC, ~0); 1496 wrfl(); 1497 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1498 int i; 1499 1500 for (i = 0; i < adapter->num_q_vectors; i++) 1501 synchronize_irq(adapter->msix_entries[i].vector); 1502 } else { 1503 synchronize_irq(adapter->pdev->irq); 1504 } 1505 } 1506 1507 /** 1508 * igb_irq_enable - Enable default interrupt generation settings 1509 * @adapter: board private structure 1510 **/ 1511 static void igb_irq_enable(struct igb_adapter *adapter) 1512 { 1513 struct e1000_hw *hw = &adapter->hw; 1514 1515 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1516 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1517 u32 regval = rd32(E1000_EIAC); 1518 1519 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1520 regval = rd32(E1000_EIAM); 1521 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1522 wr32(E1000_EIMS, adapter->eims_enable_mask); 1523 if (adapter->vfs_allocated_count) { 1524 wr32(E1000_MBVFIMR, 0xFF); 1525 ims |= E1000_IMS_VMMB; 1526 } 1527 wr32(E1000_IMS, ims); 1528 } else { 1529 wr32(E1000_IMS, IMS_ENABLE_MASK | 1530 E1000_IMS_DRSTA); 1531 wr32(E1000_IAM, IMS_ENABLE_MASK | 1532 E1000_IMS_DRSTA); 1533 } 1534 } 1535 1536 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1537 { 1538 struct e1000_hw *hw = &adapter->hw; 1539 u16 pf_id = adapter->vfs_allocated_count; 1540 u16 vid = adapter->hw.mng_cookie.vlan_id; 1541 u16 old_vid = adapter->mng_vlan_id; 1542 1543 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1544 /* add VID to filter table */ 1545 igb_vfta_set(hw, vid, pf_id, true, true); 1546 adapter->mng_vlan_id = vid; 1547 } else { 1548 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1549 } 1550 1551 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1552 (vid != old_vid) && 1553 !test_bit(old_vid, adapter->active_vlans)) { 1554 /* remove VID from filter table */ 1555 igb_vfta_set(hw, vid, pf_id, false, true); 1556 } 1557 } 1558 1559 /** 1560 * igb_release_hw_control - release control of the h/w to f/w 1561 * @adapter: address of board private structure 1562 * 1563 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1564 * For ASF and Pass Through versions of f/w this means that the 1565 * driver is no longer loaded. 1566 **/ 1567 static void igb_release_hw_control(struct igb_adapter *adapter) 1568 { 1569 struct e1000_hw *hw = &adapter->hw; 1570 u32 ctrl_ext; 1571 1572 /* Let firmware take over control of h/w */ 1573 ctrl_ext = rd32(E1000_CTRL_EXT); 1574 wr32(E1000_CTRL_EXT, 1575 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1576 } 1577 1578 /** 1579 * igb_get_hw_control - get control of the h/w from f/w 1580 * @adapter: address of board private structure 1581 * 1582 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1583 * For ASF and Pass Through versions of f/w this means that 1584 * the driver is loaded. 1585 **/ 1586 static void igb_get_hw_control(struct igb_adapter *adapter) 1587 { 1588 struct e1000_hw *hw = &adapter->hw; 1589 u32 ctrl_ext; 1590 1591 /* Let firmware know the driver has taken over */ 1592 ctrl_ext = rd32(E1000_CTRL_EXT); 1593 wr32(E1000_CTRL_EXT, 1594 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1595 } 1596 1597 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1598 { 1599 struct net_device *netdev = adapter->netdev; 1600 struct e1000_hw *hw = &adapter->hw; 1601 1602 WARN_ON(hw->mac.type != e1000_i210); 1603 1604 if (enable) 1605 adapter->flags |= IGB_FLAG_FQTSS; 1606 else 1607 adapter->flags &= ~IGB_FLAG_FQTSS; 1608 1609 if (netif_running(netdev)) 1610 schedule_work(&adapter->reset_task); 1611 } 1612 1613 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1614 { 1615 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1616 } 1617 1618 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1619 enum tx_queue_prio prio) 1620 { 1621 u32 val; 1622 1623 WARN_ON(hw->mac.type != e1000_i210); 1624 WARN_ON(queue < 0 || queue > 4); 1625 1626 val = rd32(E1000_I210_TXDCTL(queue)); 1627 1628 if (prio == TX_QUEUE_PRIO_HIGH) 1629 val |= E1000_TXDCTL_PRIORITY; 1630 else 1631 val &= ~E1000_TXDCTL_PRIORITY; 1632 1633 wr32(E1000_I210_TXDCTL(queue), val); 1634 } 1635 1636 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1637 { 1638 u32 val; 1639 1640 WARN_ON(hw->mac.type != e1000_i210); 1641 WARN_ON(queue < 0 || queue > 1); 1642 1643 val = rd32(E1000_I210_TQAVCC(queue)); 1644 1645 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1646 val |= E1000_TQAVCC_QUEUEMODE; 1647 else 1648 val &= ~E1000_TQAVCC_QUEUEMODE; 1649 1650 wr32(E1000_I210_TQAVCC(queue), val); 1651 } 1652 1653 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1654 { 1655 int i; 1656 1657 for (i = 0; i < adapter->num_tx_queues; i++) { 1658 if (adapter->tx_ring[i]->cbs_enable) 1659 return true; 1660 } 1661 1662 return false; 1663 } 1664 1665 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1666 { 1667 int i; 1668 1669 for (i = 0; i < adapter->num_tx_queues; i++) { 1670 if (adapter->tx_ring[i]->launchtime_enable) 1671 return true; 1672 } 1673 1674 return false; 1675 } 1676 1677 /** 1678 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1679 * @adapter: pointer to adapter struct 1680 * @queue: queue number 1681 * 1682 * Configure CBS and Launchtime for a given hardware queue. 1683 * Parameters are retrieved from the correct Tx ring, so 1684 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1685 * for setting those correctly prior to this function being called. 1686 **/ 1687 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1688 { 1689 struct net_device *netdev = adapter->netdev; 1690 struct e1000_hw *hw = &adapter->hw; 1691 struct igb_ring *ring; 1692 u32 tqavcc, tqavctrl; 1693 u16 value; 1694 1695 WARN_ON(hw->mac.type != e1000_i210); 1696 WARN_ON(queue < 0 || queue > 1); 1697 ring = adapter->tx_ring[queue]; 1698 1699 /* If any of the Qav features is enabled, configure queues as SR and 1700 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1701 * as SP. 1702 */ 1703 if (ring->cbs_enable || ring->launchtime_enable) { 1704 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1705 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1706 } else { 1707 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1708 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1709 } 1710 1711 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1712 if (ring->cbs_enable || queue == 0) { 1713 /* i210 does not allow the queue 0 to be in the Strict 1714 * Priority mode while the Qav mode is enabled, so, 1715 * instead of disabling strict priority mode, we give 1716 * queue 0 the maximum of credits possible. 1717 * 1718 * See section 8.12.19 of the i210 datasheet, "Note: 1719 * Queue0 QueueMode must be set to 1b when 1720 * TransmitMode is set to Qav." 1721 */ 1722 if (queue == 0 && !ring->cbs_enable) { 1723 /* max "linkspeed" idleslope in kbps */ 1724 ring->idleslope = 1000000; 1725 ring->hicredit = ETH_FRAME_LEN; 1726 } 1727 1728 /* Always set data transfer arbitration to credit-based 1729 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1730 * the queues. 1731 */ 1732 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1733 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1734 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1735 1736 /* According to i210 datasheet section 7.2.7.7, we should set 1737 * the 'idleSlope' field from TQAVCC register following the 1738 * equation: 1739 * 1740 * For 100 Mbps link speed: 1741 * 1742 * value = BW * 0x7735 * 0.2 (E1) 1743 * 1744 * For 1000Mbps link speed: 1745 * 1746 * value = BW * 0x7735 * 2 (E2) 1747 * 1748 * E1 and E2 can be merged into one equation as shown below. 1749 * Note that 'link-speed' is in Mbps. 1750 * 1751 * value = BW * 0x7735 * 2 * link-speed 1752 * -------------- (E3) 1753 * 1000 1754 * 1755 * 'BW' is the percentage bandwidth out of full link speed 1756 * which can be found with the following equation. Note that 1757 * idleSlope here is the parameter from this function which 1758 * is in kbps. 1759 * 1760 * BW = idleSlope 1761 * ----------------- (E4) 1762 * link-speed * 1000 1763 * 1764 * That said, we can come up with a generic equation to 1765 * calculate the value we should set it TQAVCC register by 1766 * replacing 'BW' in E3 by E4. The resulting equation is: 1767 * 1768 * value = idleSlope * 0x7735 * 2 * link-speed 1769 * ----------------- -------------- (E5) 1770 * link-speed * 1000 1000 1771 * 1772 * 'link-speed' is present in both sides of the fraction so 1773 * it is canceled out. The final equation is the following: 1774 * 1775 * value = idleSlope * 61034 1776 * ----------------- (E6) 1777 * 1000000 1778 * 1779 * NOTE: For i210, given the above, we can see that idleslope 1780 * is represented in 16.38431 kbps units by the value at 1781 * the TQAVCC register (1Gbps / 61034), which reduces 1782 * the granularity for idleslope increments. 1783 * For instance, if you want to configure a 2576kbps 1784 * idleslope, the value to be written on the register 1785 * would have to be 157.23. If rounded down, you end 1786 * up with less bandwidth available than originally 1787 * required (~2572 kbps). If rounded up, you end up 1788 * with a higher bandwidth (~2589 kbps). Below the 1789 * approach we take is to always round up the 1790 * calculated value, so the resulting bandwidth might 1791 * be slightly higher for some configurations. 1792 */ 1793 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1794 1795 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1796 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1797 tqavcc |= value; 1798 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1799 1800 wr32(E1000_I210_TQAVHC(queue), 1801 0x80000000 + ring->hicredit * 0x7735); 1802 } else { 1803 1804 /* Set idleSlope to zero. */ 1805 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1806 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1807 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1808 1809 /* Set hiCredit to zero. */ 1810 wr32(E1000_I210_TQAVHC(queue), 0); 1811 1812 /* If CBS is not enabled for any queues anymore, then return to 1813 * the default state of Data Transmission Arbitration on 1814 * TQAVCTRL. 1815 */ 1816 if (!is_any_cbs_enabled(adapter)) { 1817 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1818 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1819 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1820 } 1821 } 1822 1823 /* If LaunchTime is enabled, set DataTranTIM. */ 1824 if (ring->launchtime_enable) { 1825 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1826 * for any of the SR queues, and configure fetchtime delta. 1827 * XXX NOTE: 1828 * - LaunchTime will be enabled for all SR queues. 1829 * - A fixed offset can be added relative to the launch 1830 * time of all packets if configured at reg LAUNCH_OS0. 1831 * We are keeping it as 0 for now (default value). 1832 */ 1833 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1834 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1835 E1000_TQAVCTRL_FETCHTIME_DELTA; 1836 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1837 } else { 1838 /* If Launchtime is not enabled for any SR queues anymore, 1839 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1840 * effectively disabling Launchtime. 1841 */ 1842 if (!is_any_txtime_enabled(adapter)) { 1843 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1844 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1845 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1846 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1847 } 1848 } 1849 1850 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1851 * CBS are not configurable by software so we don't do any 'controller 1852 * configuration' in respect to these parameters. 1853 */ 1854 1855 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1856 ring->cbs_enable ? "enabled" : "disabled", 1857 ring->launchtime_enable ? "enabled" : "disabled", 1858 queue, 1859 ring->idleslope, ring->sendslope, 1860 ring->hicredit, ring->locredit); 1861 } 1862 1863 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1864 bool enable) 1865 { 1866 struct igb_ring *ring; 1867 1868 if (queue < 0 || queue > adapter->num_tx_queues) 1869 return -EINVAL; 1870 1871 ring = adapter->tx_ring[queue]; 1872 ring->launchtime_enable = enable; 1873 1874 return 0; 1875 } 1876 1877 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1878 bool enable, int idleslope, int sendslope, 1879 int hicredit, int locredit) 1880 { 1881 struct igb_ring *ring; 1882 1883 if (queue < 0 || queue > adapter->num_tx_queues) 1884 return -EINVAL; 1885 1886 ring = adapter->tx_ring[queue]; 1887 1888 ring->cbs_enable = enable; 1889 ring->idleslope = idleslope; 1890 ring->sendslope = sendslope; 1891 ring->hicredit = hicredit; 1892 ring->locredit = locredit; 1893 1894 return 0; 1895 } 1896 1897 /** 1898 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1899 * @adapter: pointer to adapter struct 1900 * 1901 * Configure TQAVCTRL register switching the controller's Tx mode 1902 * if FQTSS mode is enabled or disabled. Additionally, will issue 1903 * a call to igb_config_tx_modes() per queue so any previously saved 1904 * Tx parameters are applied. 1905 **/ 1906 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1907 { 1908 struct net_device *netdev = adapter->netdev; 1909 struct e1000_hw *hw = &adapter->hw; 1910 u32 val; 1911 1912 /* Only i210 controller supports changing the transmission mode. */ 1913 if (hw->mac.type != e1000_i210) 1914 return; 1915 1916 if (is_fqtss_enabled(adapter)) { 1917 int i, max_queue; 1918 1919 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1920 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1921 * so SP queues wait for SR ones. 1922 */ 1923 val = rd32(E1000_I210_TQAVCTRL); 1924 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1925 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1926 wr32(E1000_I210_TQAVCTRL, val); 1927 1928 /* Configure Tx and Rx packet buffers sizes as described in 1929 * i210 datasheet section 7.2.7.7. 1930 */ 1931 val = rd32(E1000_TXPBS); 1932 val &= ~I210_TXPBSIZE_MASK; 1933 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB | 1934 I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB; 1935 wr32(E1000_TXPBS, val); 1936 1937 val = rd32(E1000_RXPBS); 1938 val &= ~I210_RXPBSIZE_MASK; 1939 val |= I210_RXPBSIZE_PB_30KB; 1940 wr32(E1000_RXPBS, val); 1941 1942 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1943 * register should not exceed the buffer size programmed in 1944 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1945 * so according to the datasheet we should set MAX_TPKT_SIZE to 1946 * 4kB / 64. 1947 * 1948 * However, when we do so, no frame from queue 2 and 3 are 1949 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1950 * or _equal_ to the buffer size programmed in TXPBS. For this 1951 * reason, we set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1952 */ 1953 val = (4096 - 1) / 64; 1954 wr32(E1000_I210_DTXMXPKTSZ, val); 1955 1956 /* Since FQTSS mode is enabled, apply any CBS configuration 1957 * previously set. If no previous CBS configuration has been 1958 * done, then the initial configuration is applied, which means 1959 * CBS is disabled. 1960 */ 1961 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1962 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1963 1964 for (i = 0; i < max_queue; i++) { 1965 igb_config_tx_modes(adapter, i); 1966 } 1967 } else { 1968 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1969 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1970 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1971 1972 val = rd32(E1000_I210_TQAVCTRL); 1973 /* According to Section 8.12.21, the other flags we've set when 1974 * enabling FQTSS are not relevant when disabling FQTSS so we 1975 * don't set they here. 1976 */ 1977 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1978 wr32(E1000_I210_TQAVCTRL, val); 1979 } 1980 1981 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1982 "enabled" : "disabled"); 1983 } 1984 1985 /** 1986 * igb_configure - configure the hardware for RX and TX 1987 * @adapter: private board structure 1988 **/ 1989 static void igb_configure(struct igb_adapter *adapter) 1990 { 1991 struct net_device *netdev = adapter->netdev; 1992 int i; 1993 1994 igb_get_hw_control(adapter); 1995 igb_set_rx_mode(netdev); 1996 igb_setup_tx_mode(adapter); 1997 1998 igb_restore_vlan(adapter); 1999 2000 igb_setup_tctl(adapter); 2001 igb_setup_mrqc(adapter); 2002 igb_setup_rctl(adapter); 2003 2004 igb_nfc_filter_restore(adapter); 2005 igb_configure_tx(adapter); 2006 igb_configure_rx(adapter); 2007 2008 igb_rx_fifo_flush_82575(&adapter->hw); 2009 2010 /* call igb_desc_unused which always leaves 2011 * at least 1 descriptor unused to make sure 2012 * next_to_use != next_to_clean 2013 */ 2014 for (i = 0; i < adapter->num_rx_queues; i++) { 2015 struct igb_ring *ring = adapter->rx_ring[i]; 2016 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 2017 } 2018 } 2019 2020 /** 2021 * igb_power_up_link - Power up the phy/serdes link 2022 * @adapter: address of board private structure 2023 **/ 2024 void igb_power_up_link(struct igb_adapter *adapter) 2025 { 2026 igb_reset_phy(&adapter->hw); 2027 2028 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2029 igb_power_up_phy_copper(&adapter->hw); 2030 else 2031 igb_power_up_serdes_link_82575(&adapter->hw); 2032 2033 igb_setup_link(&adapter->hw); 2034 } 2035 2036 /** 2037 * igb_power_down_link - Power down the phy/serdes link 2038 * @adapter: address of board private structure 2039 */ 2040 static void igb_power_down_link(struct igb_adapter *adapter) 2041 { 2042 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2043 igb_power_down_phy_copper_82575(&adapter->hw); 2044 else 2045 igb_shutdown_serdes_link_82575(&adapter->hw); 2046 } 2047 2048 /** 2049 * igb_check_swap_media - Detect and switch function for Media Auto Sense 2050 * @adapter: address of the board private structure 2051 **/ 2052 static void igb_check_swap_media(struct igb_adapter *adapter) 2053 { 2054 struct e1000_hw *hw = &adapter->hw; 2055 u32 ctrl_ext, connsw; 2056 bool swap_now = false; 2057 2058 ctrl_ext = rd32(E1000_CTRL_EXT); 2059 connsw = rd32(E1000_CONNSW); 2060 2061 /* need to live swap if current media is copper and we have fiber/serdes 2062 * to go to. 2063 */ 2064 2065 if ((hw->phy.media_type == e1000_media_type_copper) && 2066 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2067 swap_now = true; 2068 } else if ((hw->phy.media_type != e1000_media_type_copper) && 2069 !(connsw & E1000_CONNSW_SERDESD)) { 2070 /* copper signal takes time to appear */ 2071 if (adapter->copper_tries < 4) { 2072 adapter->copper_tries++; 2073 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2074 wr32(E1000_CONNSW, connsw); 2075 return; 2076 } else { 2077 adapter->copper_tries = 0; 2078 if ((connsw & E1000_CONNSW_PHYSD) && 2079 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2080 swap_now = true; 2081 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2082 wr32(E1000_CONNSW, connsw); 2083 } 2084 } 2085 } 2086 2087 if (!swap_now) 2088 return; 2089 2090 switch (hw->phy.media_type) { 2091 case e1000_media_type_copper: 2092 netdev_info(adapter->netdev, 2093 "MAS: changing media to fiber/serdes\n"); 2094 ctrl_ext |= 2095 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2096 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2097 adapter->copper_tries = 0; 2098 break; 2099 case e1000_media_type_internal_serdes: 2100 case e1000_media_type_fiber: 2101 netdev_info(adapter->netdev, 2102 "MAS: changing media to copper\n"); 2103 ctrl_ext &= 2104 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2105 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2106 break; 2107 default: 2108 /* shouldn't get here during regular operation */ 2109 netdev_err(adapter->netdev, 2110 "AMS: Invalid media type found, returning\n"); 2111 break; 2112 } 2113 wr32(E1000_CTRL_EXT, ctrl_ext); 2114 } 2115 2116 /** 2117 * igb_up - Open the interface and prepare it to handle traffic 2118 * @adapter: board private structure 2119 **/ 2120 int igb_up(struct igb_adapter *adapter) 2121 { 2122 struct e1000_hw *hw = &adapter->hw; 2123 int i; 2124 2125 /* hardware has been reset, we need to reload some things */ 2126 igb_configure(adapter); 2127 2128 clear_bit(__IGB_DOWN, &adapter->state); 2129 2130 for (i = 0; i < adapter->num_q_vectors; i++) 2131 napi_enable(&(adapter->q_vector[i]->napi)); 2132 2133 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2134 igb_configure_msix(adapter); 2135 else 2136 igb_assign_vector(adapter->q_vector[0], 0); 2137 2138 /* Clear any pending interrupts. */ 2139 rd32(E1000_TSICR); 2140 rd32(E1000_ICR); 2141 igb_irq_enable(adapter); 2142 2143 /* notify VFs that reset has been completed */ 2144 if (adapter->vfs_allocated_count) { 2145 u32 reg_data = rd32(E1000_CTRL_EXT); 2146 2147 reg_data |= E1000_CTRL_EXT_PFRSTD; 2148 wr32(E1000_CTRL_EXT, reg_data); 2149 } 2150 2151 netif_tx_start_all_queues(adapter->netdev); 2152 2153 /* start the watchdog. */ 2154 hw->mac.get_link_status = 1; 2155 schedule_work(&adapter->watchdog_task); 2156 2157 if ((adapter->flags & IGB_FLAG_EEE) && 2158 (!hw->dev_spec._82575.eee_disable)) 2159 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2160 2161 return 0; 2162 } 2163 2164 void igb_down(struct igb_adapter *adapter) 2165 { 2166 struct net_device *netdev = adapter->netdev; 2167 struct e1000_hw *hw = &adapter->hw; 2168 u32 tctl, rctl; 2169 int i; 2170 2171 /* signal that we're down so the interrupt handler does not 2172 * reschedule our watchdog timer 2173 */ 2174 set_bit(__IGB_DOWN, &adapter->state); 2175 2176 /* disable receives in the hardware */ 2177 rctl = rd32(E1000_RCTL); 2178 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2179 /* flush and sleep below */ 2180 2181 igb_nfc_filter_exit(adapter); 2182 2183 netif_carrier_off(netdev); 2184 netif_tx_stop_all_queues(netdev); 2185 2186 /* disable transmits in the hardware */ 2187 tctl = rd32(E1000_TCTL); 2188 tctl &= ~E1000_TCTL_EN; 2189 wr32(E1000_TCTL, tctl); 2190 /* flush both disables and wait for them to finish */ 2191 wrfl(); 2192 usleep_range(10000, 11000); 2193 2194 igb_irq_disable(adapter); 2195 2196 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2197 2198 for (i = 0; i < adapter->num_q_vectors; i++) { 2199 if (adapter->q_vector[i]) { 2200 napi_synchronize(&adapter->q_vector[i]->napi); 2201 napi_disable(&adapter->q_vector[i]->napi); 2202 } 2203 } 2204 2205 del_timer_sync(&adapter->watchdog_timer); 2206 del_timer_sync(&adapter->phy_info_timer); 2207 2208 /* record the stats before reset*/ 2209 spin_lock(&adapter->stats64_lock); 2210 igb_update_stats(adapter); 2211 spin_unlock(&adapter->stats64_lock); 2212 2213 adapter->link_speed = 0; 2214 adapter->link_duplex = 0; 2215 2216 if (!pci_channel_offline(adapter->pdev)) 2217 igb_reset(adapter); 2218 2219 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2220 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2221 2222 igb_clean_all_tx_rings(adapter); 2223 igb_clean_all_rx_rings(adapter); 2224 #ifdef CONFIG_IGB_DCA 2225 2226 /* since we reset the hardware DCA settings were cleared */ 2227 igb_setup_dca(adapter); 2228 #endif 2229 } 2230 2231 void igb_reinit_locked(struct igb_adapter *adapter) 2232 { 2233 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2234 usleep_range(1000, 2000); 2235 igb_down(adapter); 2236 igb_up(adapter); 2237 clear_bit(__IGB_RESETTING, &adapter->state); 2238 } 2239 2240 /** igb_enable_mas - Media Autosense re-enable after swap 2241 * 2242 * @adapter: adapter struct 2243 **/ 2244 static void igb_enable_mas(struct igb_adapter *adapter) 2245 { 2246 struct e1000_hw *hw = &adapter->hw; 2247 u32 connsw = rd32(E1000_CONNSW); 2248 2249 /* configure for SerDes media detect */ 2250 if ((hw->phy.media_type == e1000_media_type_copper) && 2251 (!(connsw & E1000_CONNSW_SERDESD))) { 2252 connsw |= E1000_CONNSW_ENRGSRC; 2253 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2254 wr32(E1000_CONNSW, connsw); 2255 wrfl(); 2256 } 2257 } 2258 2259 void igb_reset(struct igb_adapter *adapter) 2260 { 2261 struct pci_dev *pdev = adapter->pdev; 2262 struct e1000_hw *hw = &adapter->hw; 2263 struct e1000_mac_info *mac = &hw->mac; 2264 struct e1000_fc_info *fc = &hw->fc; 2265 u32 pba, hwm; 2266 2267 /* Repartition Pba for greater than 9k mtu 2268 * To take effect CTRL.RST is required. 2269 */ 2270 switch (mac->type) { 2271 case e1000_i350: 2272 case e1000_i354: 2273 case e1000_82580: 2274 pba = rd32(E1000_RXPBS); 2275 pba = igb_rxpbs_adjust_82580(pba); 2276 break; 2277 case e1000_82576: 2278 pba = rd32(E1000_RXPBS); 2279 pba &= E1000_RXPBS_SIZE_MASK_82576; 2280 break; 2281 case e1000_82575: 2282 case e1000_i210: 2283 case e1000_i211: 2284 default: 2285 pba = E1000_PBA_34K; 2286 break; 2287 } 2288 2289 if (mac->type == e1000_82575) { 2290 u32 min_rx_space, min_tx_space, needed_tx_space; 2291 2292 /* write Rx PBA so that hardware can report correct Tx PBA */ 2293 wr32(E1000_PBA, pba); 2294 2295 /* To maintain wire speed transmits, the Tx FIFO should be 2296 * large enough to accommodate two full transmit packets, 2297 * rounded up to the next 1KB and expressed in KB. Likewise, 2298 * the Rx FIFO should be large enough to accommodate at least 2299 * one full receive packet and is similarly rounded up and 2300 * expressed in KB. 2301 */ 2302 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2303 2304 /* The Tx FIFO also stores 16 bytes of information about the Tx 2305 * but don't include Ethernet FCS because hardware appends it. 2306 * We only need to round down to the nearest 512 byte block 2307 * count since the value we care about is 2 frames, not 1. 2308 */ 2309 min_tx_space = adapter->max_frame_size; 2310 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2311 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2312 2313 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2314 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2315 2316 /* If current Tx allocation is less than the min Tx FIFO size, 2317 * and the min Tx FIFO size is less than the current Rx FIFO 2318 * allocation, take space away from current Rx allocation. 2319 */ 2320 if (needed_tx_space < pba) { 2321 pba -= needed_tx_space; 2322 2323 /* if short on Rx space, Rx wins and must trump Tx 2324 * adjustment 2325 */ 2326 if (pba < min_rx_space) 2327 pba = min_rx_space; 2328 } 2329 2330 /* adjust PBA for jumbo frames */ 2331 wr32(E1000_PBA, pba); 2332 } 2333 2334 /* flow control settings 2335 * The high water mark must be low enough to fit one full frame 2336 * after transmitting the pause frame. As such we must have enough 2337 * space to allow for us to complete our current transmit and then 2338 * receive the frame that is in progress from the link partner. 2339 * Set it to: 2340 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2341 */ 2342 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2343 2344 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2345 fc->low_water = fc->high_water - 16; 2346 fc->pause_time = 0xFFFF; 2347 fc->send_xon = 1; 2348 fc->current_mode = fc->requested_mode; 2349 2350 /* disable receive for all VFs and wait one second */ 2351 if (adapter->vfs_allocated_count) { 2352 int i; 2353 2354 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2355 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2356 2357 /* ping all the active vfs to let them know we are going down */ 2358 igb_ping_all_vfs(adapter); 2359 2360 /* disable transmits and receives */ 2361 wr32(E1000_VFRE, 0); 2362 wr32(E1000_VFTE, 0); 2363 } 2364 2365 /* Allow time for pending master requests to run */ 2366 hw->mac.ops.reset_hw(hw); 2367 wr32(E1000_WUC, 0); 2368 2369 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2370 /* need to resetup here after media swap */ 2371 adapter->ei.get_invariants(hw); 2372 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2373 } 2374 if ((mac->type == e1000_82575 || mac->type == e1000_i350) && 2375 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2376 igb_enable_mas(adapter); 2377 } 2378 if (hw->mac.ops.init_hw(hw)) 2379 dev_err(&pdev->dev, "Hardware Error\n"); 2380 2381 /* RAR registers were cleared during init_hw, clear mac table */ 2382 igb_flush_mac_table(adapter); 2383 __dev_uc_unsync(adapter->netdev, NULL); 2384 2385 /* Recover default RAR entry */ 2386 igb_set_default_mac_filter(adapter); 2387 2388 /* Flow control settings reset on hardware reset, so guarantee flow 2389 * control is off when forcing speed. 2390 */ 2391 if (!hw->mac.autoneg) 2392 igb_force_mac_fc(hw); 2393 2394 igb_init_dmac(adapter, pba); 2395 #ifdef CONFIG_IGB_HWMON 2396 /* Re-initialize the thermal sensor on i350 devices. */ 2397 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2398 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2399 /* If present, re-initialize the external thermal sensor 2400 * interface. 2401 */ 2402 if (adapter->ets) 2403 mac->ops.init_thermal_sensor_thresh(hw); 2404 } 2405 } 2406 #endif 2407 /* Re-establish EEE setting */ 2408 if (hw->phy.media_type == e1000_media_type_copper) { 2409 switch (mac->type) { 2410 case e1000_i350: 2411 case e1000_i210: 2412 case e1000_i211: 2413 igb_set_eee_i350(hw, true, true); 2414 break; 2415 case e1000_i354: 2416 igb_set_eee_i354(hw, true, true); 2417 break; 2418 default: 2419 break; 2420 } 2421 } 2422 if (!netif_running(adapter->netdev)) 2423 igb_power_down_link(adapter); 2424 2425 igb_update_mng_vlan(adapter); 2426 2427 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2428 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2429 2430 /* Re-enable PTP, where applicable. */ 2431 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2432 igb_ptp_reset(adapter); 2433 2434 igb_get_phy_info(hw); 2435 } 2436 2437 static netdev_features_t igb_fix_features(struct net_device *netdev, 2438 netdev_features_t features) 2439 { 2440 /* Since there is no support for separate Rx/Tx vlan accel 2441 * enable/disable make sure Tx flag is always in same state as Rx. 2442 */ 2443 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2444 features |= NETIF_F_HW_VLAN_CTAG_TX; 2445 else 2446 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2447 2448 return features; 2449 } 2450 2451 static int igb_set_features(struct net_device *netdev, 2452 netdev_features_t features) 2453 { 2454 netdev_features_t changed = netdev->features ^ features; 2455 struct igb_adapter *adapter = netdev_priv(netdev); 2456 2457 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2458 igb_vlan_mode(netdev, features); 2459 2460 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2461 return 0; 2462 2463 if (!(features & NETIF_F_NTUPLE)) { 2464 struct hlist_node *node2; 2465 struct igb_nfc_filter *rule; 2466 2467 spin_lock(&adapter->nfc_lock); 2468 hlist_for_each_entry_safe(rule, node2, 2469 &adapter->nfc_filter_list, nfc_node) { 2470 igb_erase_filter(adapter, rule); 2471 hlist_del(&rule->nfc_node); 2472 kfree(rule); 2473 } 2474 spin_unlock(&adapter->nfc_lock); 2475 adapter->nfc_filter_count = 0; 2476 } 2477 2478 netdev->features = features; 2479 2480 if (netif_running(netdev)) 2481 igb_reinit_locked(adapter); 2482 else 2483 igb_reset(adapter); 2484 2485 return 1; 2486 } 2487 2488 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2489 struct net_device *dev, 2490 const unsigned char *addr, u16 vid, 2491 u16 flags, 2492 struct netlink_ext_ack *extack) 2493 { 2494 /* guarantee we can provide a unique filter for the unicast address */ 2495 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2496 struct igb_adapter *adapter = netdev_priv(dev); 2497 int vfn = adapter->vfs_allocated_count; 2498 2499 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2500 return -ENOMEM; 2501 } 2502 2503 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2504 } 2505 2506 #define IGB_MAX_MAC_HDR_LEN 127 2507 #define IGB_MAX_NETWORK_HDR_LEN 511 2508 2509 static netdev_features_t 2510 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2511 netdev_features_t features) 2512 { 2513 unsigned int network_hdr_len, mac_hdr_len; 2514 2515 /* Make certain the headers can be described by a context descriptor */ 2516 mac_hdr_len = skb_network_header(skb) - skb->data; 2517 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2518 return features & ~(NETIF_F_HW_CSUM | 2519 NETIF_F_SCTP_CRC | 2520 NETIF_F_GSO_UDP_L4 | 2521 NETIF_F_HW_VLAN_CTAG_TX | 2522 NETIF_F_TSO | 2523 NETIF_F_TSO6); 2524 2525 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2526 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2527 return features & ~(NETIF_F_HW_CSUM | 2528 NETIF_F_SCTP_CRC | 2529 NETIF_F_GSO_UDP_L4 | 2530 NETIF_F_TSO | 2531 NETIF_F_TSO6); 2532 2533 /* We can only support IPV4 TSO in tunnels if we can mangle the 2534 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2535 */ 2536 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2537 features &= ~NETIF_F_TSO; 2538 2539 return features; 2540 } 2541 2542 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2543 { 2544 if (!is_fqtss_enabled(adapter)) { 2545 enable_fqtss(adapter, true); 2546 return; 2547 } 2548 2549 igb_config_tx_modes(adapter, queue); 2550 2551 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2552 enable_fqtss(adapter, false); 2553 } 2554 2555 static int igb_offload_cbs(struct igb_adapter *adapter, 2556 struct tc_cbs_qopt_offload *qopt) 2557 { 2558 struct e1000_hw *hw = &adapter->hw; 2559 int err; 2560 2561 /* CBS offloading is only supported by i210 controller. */ 2562 if (hw->mac.type != e1000_i210) 2563 return -EOPNOTSUPP; 2564 2565 /* CBS offloading is only supported by queue 0 and queue 1. */ 2566 if (qopt->queue < 0 || qopt->queue > 1) 2567 return -EINVAL; 2568 2569 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2570 qopt->idleslope, qopt->sendslope, 2571 qopt->hicredit, qopt->locredit); 2572 if (err) 2573 return err; 2574 2575 igb_offload_apply(adapter, qopt->queue); 2576 2577 return 0; 2578 } 2579 2580 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2581 #define VLAN_PRIO_FULL_MASK (0x07) 2582 2583 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2584 struct flow_cls_offload *f, 2585 int traffic_class, 2586 struct igb_nfc_filter *input) 2587 { 2588 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2589 struct flow_dissector *dissector = rule->match.dissector; 2590 struct netlink_ext_ack *extack = f->common.extack; 2591 2592 if (dissector->used_keys & 2593 ~(BIT(FLOW_DISSECTOR_KEY_BASIC) | 2594 BIT(FLOW_DISSECTOR_KEY_CONTROL) | 2595 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2596 BIT(FLOW_DISSECTOR_KEY_VLAN))) { 2597 NL_SET_ERR_MSG_MOD(extack, 2598 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2599 return -EOPNOTSUPP; 2600 } 2601 2602 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2603 struct flow_match_eth_addrs match; 2604 2605 flow_rule_match_eth_addrs(rule, &match); 2606 if (!is_zero_ether_addr(match.mask->dst)) { 2607 if (!is_broadcast_ether_addr(match.mask->dst)) { 2608 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2609 return -EINVAL; 2610 } 2611 2612 input->filter.match_flags |= 2613 IGB_FILTER_FLAG_DST_MAC_ADDR; 2614 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2615 } 2616 2617 if (!is_zero_ether_addr(match.mask->src)) { 2618 if (!is_broadcast_ether_addr(match.mask->src)) { 2619 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2620 return -EINVAL; 2621 } 2622 2623 input->filter.match_flags |= 2624 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2625 ether_addr_copy(input->filter.src_addr, match.key->src); 2626 } 2627 } 2628 2629 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2630 struct flow_match_basic match; 2631 2632 flow_rule_match_basic(rule, &match); 2633 if (match.mask->n_proto) { 2634 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2635 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2636 return -EINVAL; 2637 } 2638 2639 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2640 input->filter.etype = match.key->n_proto; 2641 } 2642 } 2643 2644 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2645 struct flow_match_vlan match; 2646 2647 flow_rule_match_vlan(rule, &match); 2648 if (match.mask->vlan_priority) { 2649 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2650 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2651 return -EINVAL; 2652 } 2653 2654 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2655 input->filter.vlan_tci = 2656 (__force __be16)match.key->vlan_priority; 2657 } 2658 } 2659 2660 input->action = traffic_class; 2661 input->cookie = f->cookie; 2662 2663 return 0; 2664 } 2665 2666 static int igb_configure_clsflower(struct igb_adapter *adapter, 2667 struct flow_cls_offload *cls_flower) 2668 { 2669 struct netlink_ext_ack *extack = cls_flower->common.extack; 2670 struct igb_nfc_filter *filter, *f; 2671 int err, tc; 2672 2673 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2674 if (tc < 0) { 2675 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2676 return -EINVAL; 2677 } 2678 2679 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2680 if (!filter) 2681 return -ENOMEM; 2682 2683 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2684 if (err < 0) 2685 goto err_parse; 2686 2687 spin_lock(&adapter->nfc_lock); 2688 2689 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2690 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2691 err = -EEXIST; 2692 NL_SET_ERR_MSG_MOD(extack, 2693 "This filter is already set in ethtool"); 2694 goto err_locked; 2695 } 2696 } 2697 2698 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2699 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2700 err = -EEXIST; 2701 NL_SET_ERR_MSG_MOD(extack, 2702 "This filter is already set in cls_flower"); 2703 goto err_locked; 2704 } 2705 } 2706 2707 err = igb_add_filter(adapter, filter); 2708 if (err < 0) { 2709 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2710 goto err_locked; 2711 } 2712 2713 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2714 2715 spin_unlock(&adapter->nfc_lock); 2716 2717 return 0; 2718 2719 err_locked: 2720 spin_unlock(&adapter->nfc_lock); 2721 2722 err_parse: 2723 kfree(filter); 2724 2725 return err; 2726 } 2727 2728 static int igb_delete_clsflower(struct igb_adapter *adapter, 2729 struct flow_cls_offload *cls_flower) 2730 { 2731 struct igb_nfc_filter *filter; 2732 int err; 2733 2734 spin_lock(&adapter->nfc_lock); 2735 2736 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2737 if (filter->cookie == cls_flower->cookie) 2738 break; 2739 2740 if (!filter) { 2741 err = -ENOENT; 2742 goto out; 2743 } 2744 2745 err = igb_erase_filter(adapter, filter); 2746 if (err < 0) 2747 goto out; 2748 2749 hlist_del(&filter->nfc_node); 2750 kfree(filter); 2751 2752 out: 2753 spin_unlock(&adapter->nfc_lock); 2754 2755 return err; 2756 } 2757 2758 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2759 struct flow_cls_offload *cls_flower) 2760 { 2761 switch (cls_flower->command) { 2762 case FLOW_CLS_REPLACE: 2763 return igb_configure_clsflower(adapter, cls_flower); 2764 case FLOW_CLS_DESTROY: 2765 return igb_delete_clsflower(adapter, cls_flower); 2766 case FLOW_CLS_STATS: 2767 return -EOPNOTSUPP; 2768 default: 2769 return -EOPNOTSUPP; 2770 } 2771 } 2772 2773 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2774 void *cb_priv) 2775 { 2776 struct igb_adapter *adapter = cb_priv; 2777 2778 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2779 return -EOPNOTSUPP; 2780 2781 switch (type) { 2782 case TC_SETUP_CLSFLOWER: 2783 return igb_setup_tc_cls_flower(adapter, type_data); 2784 2785 default: 2786 return -EOPNOTSUPP; 2787 } 2788 } 2789 2790 static int igb_offload_txtime(struct igb_adapter *adapter, 2791 struct tc_etf_qopt_offload *qopt) 2792 { 2793 struct e1000_hw *hw = &adapter->hw; 2794 int err; 2795 2796 /* Launchtime offloading is only supported by i210 controller. */ 2797 if (hw->mac.type != e1000_i210) 2798 return -EOPNOTSUPP; 2799 2800 /* Launchtime offloading is only supported by queues 0 and 1. */ 2801 if (qopt->queue < 0 || qopt->queue > 1) 2802 return -EINVAL; 2803 2804 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2805 if (err) 2806 return err; 2807 2808 igb_offload_apply(adapter, qopt->queue); 2809 2810 return 0; 2811 } 2812 2813 static int igb_tc_query_caps(struct igb_adapter *adapter, 2814 struct tc_query_caps_base *base) 2815 { 2816 switch (base->type) { 2817 case TC_SETUP_QDISC_TAPRIO: { 2818 struct tc_taprio_caps *caps = base->caps; 2819 2820 caps->broken_mqprio = true; 2821 2822 return 0; 2823 } 2824 default: 2825 return -EOPNOTSUPP; 2826 } 2827 } 2828 2829 static LIST_HEAD(igb_block_cb_list); 2830 2831 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2832 void *type_data) 2833 { 2834 struct igb_adapter *adapter = netdev_priv(dev); 2835 2836 switch (type) { 2837 case TC_QUERY_CAPS: 2838 return igb_tc_query_caps(adapter, type_data); 2839 case TC_SETUP_QDISC_CBS: 2840 return igb_offload_cbs(adapter, type_data); 2841 case TC_SETUP_BLOCK: 2842 return flow_block_cb_setup_simple(type_data, 2843 &igb_block_cb_list, 2844 igb_setup_tc_block_cb, 2845 adapter, adapter, true); 2846 2847 case TC_SETUP_QDISC_ETF: 2848 return igb_offload_txtime(adapter, type_data); 2849 2850 default: 2851 return -EOPNOTSUPP; 2852 } 2853 } 2854 2855 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf) 2856 { 2857 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD; 2858 struct igb_adapter *adapter = netdev_priv(dev); 2859 struct bpf_prog *prog = bpf->prog, *old_prog; 2860 bool running = netif_running(dev); 2861 bool need_reset; 2862 2863 /* verify igb ring attributes are sufficient for XDP */ 2864 for (i = 0; i < adapter->num_rx_queues; i++) { 2865 struct igb_ring *ring = adapter->rx_ring[i]; 2866 2867 if (frame_size > igb_rx_bufsz(ring)) { 2868 NL_SET_ERR_MSG_MOD(bpf->extack, 2869 "The RX buffer size is too small for the frame size"); 2870 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n", 2871 igb_rx_bufsz(ring), frame_size); 2872 return -EINVAL; 2873 } 2874 } 2875 2876 old_prog = xchg(&adapter->xdp_prog, prog); 2877 need_reset = (!!prog != !!old_prog); 2878 2879 /* device is up and bpf is added/removed, must setup the RX queues */ 2880 if (need_reset && running) { 2881 igb_close(dev); 2882 } else { 2883 for (i = 0; i < adapter->num_rx_queues; i++) 2884 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 2885 adapter->xdp_prog); 2886 } 2887 2888 if (old_prog) 2889 bpf_prog_put(old_prog); 2890 2891 /* bpf is just replaced, RXQ and MTU are already setup */ 2892 if (!need_reset) 2893 return 0; 2894 2895 if (running) 2896 igb_open(dev); 2897 2898 return 0; 2899 } 2900 2901 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp) 2902 { 2903 switch (xdp->command) { 2904 case XDP_SETUP_PROG: 2905 return igb_xdp_setup(dev, xdp); 2906 default: 2907 return -EINVAL; 2908 } 2909 } 2910 2911 static void igb_xdp_ring_update_tail(struct igb_ring *ring) 2912 { 2913 /* Force memory writes to complete before letting h/w know there 2914 * are new descriptors to fetch. 2915 */ 2916 wmb(); 2917 writel(ring->next_to_use, ring->tail); 2918 } 2919 2920 static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter) 2921 { 2922 unsigned int r_idx = smp_processor_id(); 2923 2924 if (r_idx >= adapter->num_tx_queues) 2925 r_idx = r_idx % adapter->num_tx_queues; 2926 2927 return adapter->tx_ring[r_idx]; 2928 } 2929 2930 static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp) 2931 { 2932 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2933 int cpu = smp_processor_id(); 2934 struct igb_ring *tx_ring; 2935 struct netdev_queue *nq; 2936 u32 ret; 2937 2938 if (unlikely(!xdpf)) 2939 return IGB_XDP_CONSUMED; 2940 2941 /* During program transitions its possible adapter->xdp_prog is assigned 2942 * but ring has not been configured yet. In this case simply abort xmit. 2943 */ 2944 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2945 if (unlikely(!tx_ring)) 2946 return IGB_XDP_CONSUMED; 2947 2948 nq = txring_txq(tx_ring); 2949 __netif_tx_lock(nq, cpu); 2950 /* Avoid transmit queue timeout since we share it with the slow path */ 2951 txq_trans_cond_update(nq); 2952 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2953 __netif_tx_unlock(nq); 2954 2955 return ret; 2956 } 2957 2958 static int igb_xdp_xmit(struct net_device *dev, int n, 2959 struct xdp_frame **frames, u32 flags) 2960 { 2961 struct igb_adapter *adapter = netdev_priv(dev); 2962 int cpu = smp_processor_id(); 2963 struct igb_ring *tx_ring; 2964 struct netdev_queue *nq; 2965 int nxmit = 0; 2966 int i; 2967 2968 if (unlikely(test_bit(__IGB_DOWN, &adapter->state))) 2969 return -ENETDOWN; 2970 2971 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2972 return -EINVAL; 2973 2974 /* During program transitions its possible adapter->xdp_prog is assigned 2975 * but ring has not been configured yet. In this case simply abort xmit. 2976 */ 2977 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2978 if (unlikely(!tx_ring)) 2979 return -ENXIO; 2980 2981 nq = txring_txq(tx_ring); 2982 __netif_tx_lock(nq, cpu); 2983 2984 /* Avoid transmit queue timeout since we share it with the slow path */ 2985 txq_trans_cond_update(nq); 2986 2987 for (i = 0; i < n; i++) { 2988 struct xdp_frame *xdpf = frames[i]; 2989 int err; 2990 2991 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2992 if (err != IGB_XDP_TX) 2993 break; 2994 nxmit++; 2995 } 2996 2997 __netif_tx_unlock(nq); 2998 2999 if (unlikely(flags & XDP_XMIT_FLUSH)) 3000 igb_xdp_ring_update_tail(tx_ring); 3001 3002 return nxmit; 3003 } 3004 3005 static const struct net_device_ops igb_netdev_ops = { 3006 .ndo_open = igb_open, 3007 .ndo_stop = igb_close, 3008 .ndo_start_xmit = igb_xmit_frame, 3009 .ndo_get_stats64 = igb_get_stats64, 3010 .ndo_set_rx_mode = igb_set_rx_mode, 3011 .ndo_set_mac_address = igb_set_mac, 3012 .ndo_change_mtu = igb_change_mtu, 3013 .ndo_eth_ioctl = igb_ioctl, 3014 .ndo_tx_timeout = igb_tx_timeout, 3015 .ndo_validate_addr = eth_validate_addr, 3016 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 3017 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 3018 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 3019 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 3020 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 3021 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 3022 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 3023 .ndo_get_vf_config = igb_ndo_get_vf_config, 3024 .ndo_fix_features = igb_fix_features, 3025 .ndo_set_features = igb_set_features, 3026 .ndo_fdb_add = igb_ndo_fdb_add, 3027 .ndo_features_check = igb_features_check, 3028 .ndo_setup_tc = igb_setup_tc, 3029 .ndo_bpf = igb_xdp, 3030 .ndo_xdp_xmit = igb_xdp_xmit, 3031 }; 3032 3033 /** 3034 * igb_set_fw_version - Configure version string for ethtool 3035 * @adapter: adapter struct 3036 **/ 3037 void igb_set_fw_version(struct igb_adapter *adapter) 3038 { 3039 struct e1000_hw *hw = &adapter->hw; 3040 struct e1000_fw_version fw; 3041 3042 igb_get_fw_version(hw, &fw); 3043 3044 switch (hw->mac.type) { 3045 case e1000_i210: 3046 case e1000_i211: 3047 if (!(igb_get_flash_presence_i210(hw))) { 3048 snprintf(adapter->fw_version, 3049 sizeof(adapter->fw_version), 3050 "%2d.%2d-%d", 3051 fw.invm_major, fw.invm_minor, 3052 fw.invm_img_type); 3053 break; 3054 } 3055 fallthrough; 3056 default: 3057 /* if option is rom valid, display its version too */ 3058 if (fw.or_valid) { 3059 snprintf(adapter->fw_version, 3060 sizeof(adapter->fw_version), 3061 "%d.%d, 0x%08x, %d.%d.%d", 3062 fw.eep_major, fw.eep_minor, fw.etrack_id, 3063 fw.or_major, fw.or_build, fw.or_patch); 3064 /* no option rom */ 3065 } else if (fw.etrack_id != 0X0000) { 3066 snprintf(adapter->fw_version, 3067 sizeof(adapter->fw_version), 3068 "%d.%d, 0x%08x", 3069 fw.eep_major, fw.eep_minor, fw.etrack_id); 3070 } else { 3071 snprintf(adapter->fw_version, 3072 sizeof(adapter->fw_version), 3073 "%d.%d.%d", 3074 fw.eep_major, fw.eep_minor, fw.eep_build); 3075 } 3076 break; 3077 } 3078 } 3079 3080 /** 3081 * igb_init_mas - init Media Autosense feature if enabled in the NVM 3082 * 3083 * @adapter: adapter struct 3084 **/ 3085 static void igb_init_mas(struct igb_adapter *adapter) 3086 { 3087 struct e1000_hw *hw = &adapter->hw; 3088 u16 eeprom_data; 3089 3090 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 3091 switch (hw->bus.func) { 3092 case E1000_FUNC_0: 3093 if (eeprom_data & IGB_MAS_ENABLE_0) { 3094 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3095 netdev_info(adapter->netdev, 3096 "MAS: Enabling Media Autosense for port %d\n", 3097 hw->bus.func); 3098 } 3099 break; 3100 case E1000_FUNC_1: 3101 if (eeprom_data & IGB_MAS_ENABLE_1) { 3102 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3103 netdev_info(adapter->netdev, 3104 "MAS: Enabling Media Autosense for port %d\n", 3105 hw->bus.func); 3106 } 3107 break; 3108 case E1000_FUNC_2: 3109 if (eeprom_data & IGB_MAS_ENABLE_2) { 3110 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3111 netdev_info(adapter->netdev, 3112 "MAS: Enabling Media Autosense for port %d\n", 3113 hw->bus.func); 3114 } 3115 break; 3116 case E1000_FUNC_3: 3117 if (eeprom_data & IGB_MAS_ENABLE_3) { 3118 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3119 netdev_info(adapter->netdev, 3120 "MAS: Enabling Media Autosense for port %d\n", 3121 hw->bus.func); 3122 } 3123 break; 3124 default: 3125 /* Shouldn't get here */ 3126 netdev_err(adapter->netdev, 3127 "MAS: Invalid port configuration, returning\n"); 3128 break; 3129 } 3130 } 3131 3132 /** 3133 * igb_init_i2c - Init I2C interface 3134 * @adapter: pointer to adapter structure 3135 **/ 3136 static s32 igb_init_i2c(struct igb_adapter *adapter) 3137 { 3138 struct e1000_hw *hw = &adapter->hw; 3139 s32 status = 0; 3140 s32 i2cctl; 3141 3142 /* I2C interface supported on i350 devices */ 3143 if (adapter->hw.mac.type != e1000_i350) 3144 return 0; 3145 3146 i2cctl = rd32(E1000_I2CPARAMS); 3147 i2cctl |= E1000_I2CBB_EN 3148 | E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N 3149 | E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N; 3150 wr32(E1000_I2CPARAMS, i2cctl); 3151 wrfl(); 3152 3153 /* Initialize the i2c bus which is controlled by the registers. 3154 * This bus will use the i2c_algo_bit structure that implements 3155 * the protocol through toggling of the 4 bits in the register. 3156 */ 3157 adapter->i2c_adap.owner = THIS_MODULE; 3158 adapter->i2c_algo = igb_i2c_algo; 3159 adapter->i2c_algo.data = adapter; 3160 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 3161 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 3162 strscpy(adapter->i2c_adap.name, "igb BB", 3163 sizeof(adapter->i2c_adap.name)); 3164 status = i2c_bit_add_bus(&adapter->i2c_adap); 3165 return status; 3166 } 3167 3168 /** 3169 * igb_probe - Device Initialization Routine 3170 * @pdev: PCI device information struct 3171 * @ent: entry in igb_pci_tbl 3172 * 3173 * Returns 0 on success, negative on failure 3174 * 3175 * igb_probe initializes an adapter identified by a pci_dev structure. 3176 * The OS initialization, configuring of the adapter private structure, 3177 * and a hardware reset occur. 3178 **/ 3179 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3180 { 3181 struct net_device *netdev; 3182 struct igb_adapter *adapter; 3183 struct e1000_hw *hw; 3184 u16 eeprom_data = 0; 3185 s32 ret_val; 3186 static int global_quad_port_a; /* global quad port a indication */ 3187 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3188 u8 part_str[E1000_PBANUM_LENGTH]; 3189 int err; 3190 3191 /* Catch broken hardware that put the wrong VF device ID in 3192 * the PCIe SR-IOV capability. 3193 */ 3194 if (pdev->is_virtfn) { 3195 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n", 3196 pci_name(pdev), pdev->vendor, pdev->device); 3197 return -EINVAL; 3198 } 3199 3200 err = pci_enable_device_mem(pdev); 3201 if (err) 3202 return err; 3203 3204 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3205 if (err) { 3206 dev_err(&pdev->dev, 3207 "No usable DMA configuration, aborting\n"); 3208 goto err_dma; 3209 } 3210 3211 err = pci_request_mem_regions(pdev, igb_driver_name); 3212 if (err) 3213 goto err_pci_reg; 3214 3215 pci_set_master(pdev); 3216 pci_save_state(pdev); 3217 3218 err = -ENOMEM; 3219 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3220 IGB_MAX_TX_QUEUES); 3221 if (!netdev) 3222 goto err_alloc_etherdev; 3223 3224 SET_NETDEV_DEV(netdev, &pdev->dev); 3225 3226 pci_set_drvdata(pdev, netdev); 3227 adapter = netdev_priv(netdev); 3228 adapter->netdev = netdev; 3229 adapter->pdev = pdev; 3230 hw = &adapter->hw; 3231 hw->back = adapter; 3232 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3233 3234 err = -EIO; 3235 adapter->io_addr = pci_iomap(pdev, 0, 0); 3236 if (!adapter->io_addr) 3237 goto err_ioremap; 3238 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3239 hw->hw_addr = adapter->io_addr; 3240 3241 netdev->netdev_ops = &igb_netdev_ops; 3242 igb_set_ethtool_ops(netdev); 3243 netdev->watchdog_timeo = 5 * HZ; 3244 3245 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 3246 3247 netdev->mem_start = pci_resource_start(pdev, 0); 3248 netdev->mem_end = pci_resource_end(pdev, 0); 3249 3250 /* PCI config space info */ 3251 hw->vendor_id = pdev->vendor; 3252 hw->device_id = pdev->device; 3253 hw->revision_id = pdev->revision; 3254 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3255 hw->subsystem_device_id = pdev->subsystem_device; 3256 3257 /* Copy the default MAC, PHY and NVM function pointers */ 3258 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3259 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3260 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3261 /* Initialize skew-specific constants */ 3262 err = ei->get_invariants(hw); 3263 if (err) 3264 goto err_sw_init; 3265 3266 /* setup the private structure */ 3267 err = igb_sw_init(adapter); 3268 if (err) 3269 goto err_sw_init; 3270 3271 igb_get_bus_info_pcie(hw); 3272 3273 hw->phy.autoneg_wait_to_complete = false; 3274 3275 /* Copper options */ 3276 if (hw->phy.media_type == e1000_media_type_copper) { 3277 hw->phy.mdix = AUTO_ALL_MODES; 3278 hw->phy.disable_polarity_correction = false; 3279 hw->phy.ms_type = e1000_ms_hw_default; 3280 } 3281 3282 if (igb_check_reset_block(hw)) 3283 dev_info(&pdev->dev, 3284 "PHY reset is blocked due to SOL/IDER session.\n"); 3285 3286 /* features is initialized to 0 in allocation, it might have bits 3287 * set by igb_sw_init so we should use an or instead of an 3288 * assignment. 3289 */ 3290 netdev->features |= NETIF_F_SG | 3291 NETIF_F_TSO | 3292 NETIF_F_TSO6 | 3293 NETIF_F_RXHASH | 3294 NETIF_F_RXCSUM | 3295 NETIF_F_HW_CSUM; 3296 3297 if (hw->mac.type >= e1000_82576) 3298 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 3299 3300 if (hw->mac.type >= e1000_i350) 3301 netdev->features |= NETIF_F_HW_TC; 3302 3303 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3304 NETIF_F_GSO_GRE_CSUM | \ 3305 NETIF_F_GSO_IPXIP4 | \ 3306 NETIF_F_GSO_IPXIP6 | \ 3307 NETIF_F_GSO_UDP_TUNNEL | \ 3308 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3309 3310 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3311 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3312 3313 /* copy netdev features into list of user selectable features */ 3314 netdev->hw_features |= netdev->features | 3315 NETIF_F_HW_VLAN_CTAG_RX | 3316 NETIF_F_HW_VLAN_CTAG_TX | 3317 NETIF_F_RXALL; 3318 3319 if (hw->mac.type >= e1000_i350) 3320 netdev->hw_features |= NETIF_F_NTUPLE; 3321 3322 netdev->features |= NETIF_F_HIGHDMA; 3323 3324 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3325 netdev->mpls_features |= NETIF_F_HW_CSUM; 3326 netdev->hw_enc_features |= netdev->vlan_features; 3327 3328 /* set this bit last since it cannot be part of vlan_features */ 3329 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3330 NETIF_F_HW_VLAN_CTAG_RX | 3331 NETIF_F_HW_VLAN_CTAG_TX; 3332 3333 netdev->priv_flags |= IFF_SUPP_NOFCS; 3334 3335 netdev->priv_flags |= IFF_UNICAST_FLT; 3336 3337 /* MTU range: 68 - 9216 */ 3338 netdev->min_mtu = ETH_MIN_MTU; 3339 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3340 3341 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3342 3343 /* before reading the NVM, reset the controller to put the device in a 3344 * known good starting state 3345 */ 3346 hw->mac.ops.reset_hw(hw); 3347 3348 /* make sure the NVM is good , i211/i210 parts can have special NVM 3349 * that doesn't contain a checksum 3350 */ 3351 switch (hw->mac.type) { 3352 case e1000_i210: 3353 case e1000_i211: 3354 if (igb_get_flash_presence_i210(hw)) { 3355 if (hw->nvm.ops.validate(hw) < 0) { 3356 dev_err(&pdev->dev, 3357 "The NVM Checksum Is Not Valid\n"); 3358 err = -EIO; 3359 goto err_eeprom; 3360 } 3361 } 3362 break; 3363 default: 3364 if (hw->nvm.ops.validate(hw) < 0) { 3365 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3366 err = -EIO; 3367 goto err_eeprom; 3368 } 3369 break; 3370 } 3371 3372 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3373 /* copy the MAC address out of the NVM */ 3374 if (hw->mac.ops.read_mac_addr(hw)) 3375 dev_err(&pdev->dev, "NVM Read Error\n"); 3376 } 3377 3378 eth_hw_addr_set(netdev, hw->mac.addr); 3379 3380 if (!is_valid_ether_addr(netdev->dev_addr)) { 3381 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3382 err = -EIO; 3383 goto err_eeprom; 3384 } 3385 3386 igb_set_default_mac_filter(adapter); 3387 3388 /* get firmware version for ethtool -i */ 3389 igb_set_fw_version(adapter); 3390 3391 /* configure RXPBSIZE and TXPBSIZE */ 3392 if (hw->mac.type == e1000_i210) { 3393 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3394 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3395 } 3396 3397 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3398 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3399 3400 INIT_WORK(&adapter->reset_task, igb_reset_task); 3401 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3402 3403 /* Initialize link properties that are user-changeable */ 3404 adapter->fc_autoneg = true; 3405 hw->mac.autoneg = true; 3406 hw->phy.autoneg_advertised = 0x2f; 3407 3408 hw->fc.requested_mode = e1000_fc_default; 3409 hw->fc.current_mode = e1000_fc_default; 3410 3411 igb_validate_mdi_setting(hw); 3412 3413 /* By default, support wake on port A */ 3414 if (hw->bus.func == 0) 3415 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3416 3417 /* Check the NVM for wake support on non-port A ports */ 3418 if (hw->mac.type >= e1000_82580) 3419 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3420 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3421 &eeprom_data); 3422 else if (hw->bus.func == 1) 3423 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3424 3425 if (eeprom_data & IGB_EEPROM_APME) 3426 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3427 3428 /* now that we have the eeprom settings, apply the special cases where 3429 * the eeprom may be wrong or the board simply won't support wake on 3430 * lan on a particular port 3431 */ 3432 switch (pdev->device) { 3433 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3434 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3435 break; 3436 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3437 case E1000_DEV_ID_82576_FIBER: 3438 case E1000_DEV_ID_82576_SERDES: 3439 /* Wake events only supported on port A for dual fiber 3440 * regardless of eeprom setting 3441 */ 3442 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3443 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3444 break; 3445 case E1000_DEV_ID_82576_QUAD_COPPER: 3446 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3447 /* if quad port adapter, disable WoL on all but port A */ 3448 if (global_quad_port_a != 0) 3449 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3450 else 3451 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3452 /* Reset for multiple quad port adapters */ 3453 if (++global_quad_port_a == 4) 3454 global_quad_port_a = 0; 3455 break; 3456 default: 3457 /* If the device can't wake, don't set software support */ 3458 if (!device_can_wakeup(&adapter->pdev->dev)) 3459 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3460 } 3461 3462 /* initialize the wol settings based on the eeprom settings */ 3463 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3464 adapter->wol |= E1000_WUFC_MAG; 3465 3466 /* Some vendors want WoL disabled by default, but still supported */ 3467 if ((hw->mac.type == e1000_i350) && 3468 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3469 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3470 adapter->wol = 0; 3471 } 3472 3473 /* Some vendors want the ability to Use the EEPROM setting as 3474 * enable/disable only, and not for capability 3475 */ 3476 if (((hw->mac.type == e1000_i350) || 3477 (hw->mac.type == e1000_i354)) && 3478 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3479 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3480 adapter->wol = 0; 3481 } 3482 if (hw->mac.type == e1000_i350) { 3483 if (((pdev->subsystem_device == 0x5001) || 3484 (pdev->subsystem_device == 0x5002)) && 3485 (hw->bus.func == 0)) { 3486 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3487 adapter->wol = 0; 3488 } 3489 if (pdev->subsystem_device == 0x1F52) 3490 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3491 } 3492 3493 device_set_wakeup_enable(&adapter->pdev->dev, 3494 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3495 3496 /* reset the hardware with the new settings */ 3497 igb_reset(adapter); 3498 3499 /* Init the I2C interface */ 3500 err = igb_init_i2c(adapter); 3501 if (err) { 3502 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3503 goto err_eeprom; 3504 } 3505 3506 /* let the f/w know that the h/w is now under the control of the 3507 * driver. 3508 */ 3509 igb_get_hw_control(adapter); 3510 3511 strcpy(netdev->name, "eth%d"); 3512 err = register_netdev(netdev); 3513 if (err) 3514 goto err_register; 3515 3516 /* carrier off reporting is important to ethtool even BEFORE open */ 3517 netif_carrier_off(netdev); 3518 3519 #ifdef CONFIG_IGB_DCA 3520 if (dca_add_requester(&pdev->dev) == 0) { 3521 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3522 dev_info(&pdev->dev, "DCA enabled\n"); 3523 igb_setup_dca(adapter); 3524 } 3525 3526 #endif 3527 #ifdef CONFIG_IGB_HWMON 3528 /* Initialize the thermal sensor on i350 devices. */ 3529 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3530 u16 ets_word; 3531 3532 /* Read the NVM to determine if this i350 device supports an 3533 * external thermal sensor. 3534 */ 3535 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3536 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3537 adapter->ets = true; 3538 else 3539 adapter->ets = false; 3540 if (igb_sysfs_init(adapter)) 3541 dev_err(&pdev->dev, 3542 "failed to allocate sysfs resources\n"); 3543 } else { 3544 adapter->ets = false; 3545 } 3546 #endif 3547 /* Check if Media Autosense is enabled */ 3548 adapter->ei = *ei; 3549 if (hw->dev_spec._82575.mas_capable) 3550 igb_init_mas(adapter); 3551 3552 /* do hw tstamp init after resetting */ 3553 igb_ptp_init(adapter); 3554 3555 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3556 /* print bus type/speed/width info, not applicable to i354 */ 3557 if (hw->mac.type != e1000_i354) { 3558 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3559 netdev->name, 3560 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3561 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3562 "unknown"), 3563 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3564 "Width x4" : 3565 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3566 "Width x2" : 3567 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3568 "Width x1" : "unknown"), netdev->dev_addr); 3569 } 3570 3571 if ((hw->mac.type == e1000_82576 && 3572 rd32(E1000_EECD) & E1000_EECD_PRES) || 3573 (hw->mac.type >= e1000_i210 || 3574 igb_get_flash_presence_i210(hw))) { 3575 ret_val = igb_read_part_string(hw, part_str, 3576 E1000_PBANUM_LENGTH); 3577 } else { 3578 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3579 } 3580 3581 if (ret_val) 3582 strcpy(part_str, "Unknown"); 3583 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3584 dev_info(&pdev->dev, 3585 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3586 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3587 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3588 adapter->num_rx_queues, adapter->num_tx_queues); 3589 if (hw->phy.media_type == e1000_media_type_copper) { 3590 switch (hw->mac.type) { 3591 case e1000_i350: 3592 case e1000_i210: 3593 case e1000_i211: 3594 /* Enable EEE for internal copper PHY devices */ 3595 err = igb_set_eee_i350(hw, true, true); 3596 if ((!err) && 3597 (!hw->dev_spec._82575.eee_disable)) { 3598 adapter->eee_advert = 3599 MDIO_EEE_100TX | MDIO_EEE_1000T; 3600 adapter->flags |= IGB_FLAG_EEE; 3601 } 3602 break; 3603 case e1000_i354: 3604 if ((rd32(E1000_CTRL_EXT) & 3605 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3606 err = igb_set_eee_i354(hw, true, true); 3607 if ((!err) && 3608 (!hw->dev_spec._82575.eee_disable)) { 3609 adapter->eee_advert = 3610 MDIO_EEE_100TX | MDIO_EEE_1000T; 3611 adapter->flags |= IGB_FLAG_EEE; 3612 } 3613 } 3614 break; 3615 default: 3616 break; 3617 } 3618 } 3619 3620 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 3621 3622 pm_runtime_put_noidle(&pdev->dev); 3623 return 0; 3624 3625 err_register: 3626 igb_release_hw_control(adapter); 3627 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3628 err_eeprom: 3629 if (!igb_check_reset_block(hw)) 3630 igb_reset_phy(hw); 3631 3632 if (hw->flash_address) 3633 iounmap(hw->flash_address); 3634 err_sw_init: 3635 kfree(adapter->mac_table); 3636 kfree(adapter->shadow_vfta); 3637 igb_clear_interrupt_scheme(adapter); 3638 #ifdef CONFIG_PCI_IOV 3639 igb_disable_sriov(pdev); 3640 #endif 3641 pci_iounmap(pdev, adapter->io_addr); 3642 err_ioremap: 3643 free_netdev(netdev); 3644 err_alloc_etherdev: 3645 pci_release_mem_regions(pdev); 3646 err_pci_reg: 3647 err_dma: 3648 pci_disable_device(pdev); 3649 return err; 3650 } 3651 3652 #ifdef CONFIG_PCI_IOV 3653 static int igb_disable_sriov(struct pci_dev *pdev) 3654 { 3655 struct net_device *netdev = pci_get_drvdata(pdev); 3656 struct igb_adapter *adapter = netdev_priv(netdev); 3657 struct e1000_hw *hw = &adapter->hw; 3658 unsigned long flags; 3659 3660 /* reclaim resources allocated to VFs */ 3661 if (adapter->vf_data) { 3662 /* disable iov and allow time for transactions to clear */ 3663 if (pci_vfs_assigned(pdev)) { 3664 dev_warn(&pdev->dev, 3665 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3666 return -EPERM; 3667 } else { 3668 pci_disable_sriov(pdev); 3669 msleep(500); 3670 } 3671 spin_lock_irqsave(&adapter->vfs_lock, flags); 3672 kfree(adapter->vf_mac_list); 3673 adapter->vf_mac_list = NULL; 3674 kfree(adapter->vf_data); 3675 adapter->vf_data = NULL; 3676 adapter->vfs_allocated_count = 0; 3677 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 3678 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3679 wrfl(); 3680 msleep(100); 3681 dev_info(&pdev->dev, "IOV Disabled\n"); 3682 3683 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3684 adapter->flags |= IGB_FLAG_DMAC; 3685 } 3686 3687 return 0; 3688 } 3689 3690 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 3691 { 3692 struct net_device *netdev = pci_get_drvdata(pdev); 3693 struct igb_adapter *adapter = netdev_priv(netdev); 3694 int old_vfs = pci_num_vf(pdev); 3695 struct vf_mac_filter *mac_list; 3696 int err = 0; 3697 int num_vf_mac_filters, i; 3698 3699 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3700 err = -EPERM; 3701 goto out; 3702 } 3703 if (!num_vfs) 3704 goto out; 3705 3706 if (old_vfs) { 3707 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3708 old_vfs, max_vfs); 3709 adapter->vfs_allocated_count = old_vfs; 3710 } else 3711 adapter->vfs_allocated_count = num_vfs; 3712 3713 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3714 sizeof(struct vf_data_storage), GFP_KERNEL); 3715 3716 /* if allocation failed then we do not support SR-IOV */ 3717 if (!adapter->vf_data) { 3718 adapter->vfs_allocated_count = 0; 3719 err = -ENOMEM; 3720 goto out; 3721 } 3722 3723 /* Due to the limited number of RAR entries calculate potential 3724 * number of MAC filters available for the VFs. Reserve entries 3725 * for PF default MAC, PF MAC filters and at least one RAR entry 3726 * for each VF for VF MAC. 3727 */ 3728 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3729 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3730 adapter->vfs_allocated_count); 3731 3732 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3733 sizeof(struct vf_mac_filter), 3734 GFP_KERNEL); 3735 3736 mac_list = adapter->vf_mac_list; 3737 INIT_LIST_HEAD(&adapter->vf_macs.l); 3738 3739 if (adapter->vf_mac_list) { 3740 /* Initialize list of VF MAC filters */ 3741 for (i = 0; i < num_vf_mac_filters; i++) { 3742 mac_list->vf = -1; 3743 mac_list->free = true; 3744 list_add(&mac_list->l, &adapter->vf_macs.l); 3745 mac_list++; 3746 } 3747 } else { 3748 /* If we could not allocate memory for the VF MAC filters 3749 * we can continue without this feature but warn user. 3750 */ 3751 dev_err(&pdev->dev, 3752 "Unable to allocate memory for VF MAC filter list\n"); 3753 } 3754 3755 /* only call pci_enable_sriov() if no VFs are allocated already */ 3756 if (!old_vfs) { 3757 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3758 if (err) 3759 goto err_out; 3760 } 3761 dev_info(&pdev->dev, "%d VFs allocated\n", 3762 adapter->vfs_allocated_count); 3763 for (i = 0; i < adapter->vfs_allocated_count; i++) 3764 igb_vf_configure(adapter, i); 3765 3766 /* DMA Coalescing is not supported in IOV mode. */ 3767 adapter->flags &= ~IGB_FLAG_DMAC; 3768 goto out; 3769 3770 err_out: 3771 kfree(adapter->vf_mac_list); 3772 adapter->vf_mac_list = NULL; 3773 kfree(adapter->vf_data); 3774 adapter->vf_data = NULL; 3775 adapter->vfs_allocated_count = 0; 3776 out: 3777 return err; 3778 } 3779 3780 #endif 3781 /** 3782 * igb_remove_i2c - Cleanup I2C interface 3783 * @adapter: pointer to adapter structure 3784 **/ 3785 static void igb_remove_i2c(struct igb_adapter *adapter) 3786 { 3787 /* free the adapter bus structure */ 3788 i2c_del_adapter(&adapter->i2c_adap); 3789 } 3790 3791 /** 3792 * igb_remove - Device Removal Routine 3793 * @pdev: PCI device information struct 3794 * 3795 * igb_remove is called by the PCI subsystem to alert the driver 3796 * that it should release a PCI device. The could be caused by a 3797 * Hot-Plug event, or because the driver is going to be removed from 3798 * memory. 3799 **/ 3800 static void igb_remove(struct pci_dev *pdev) 3801 { 3802 struct net_device *netdev = pci_get_drvdata(pdev); 3803 struct igb_adapter *adapter = netdev_priv(netdev); 3804 struct e1000_hw *hw = &adapter->hw; 3805 3806 pm_runtime_get_noresume(&pdev->dev); 3807 #ifdef CONFIG_IGB_HWMON 3808 igb_sysfs_exit(adapter); 3809 #endif 3810 igb_remove_i2c(adapter); 3811 igb_ptp_stop(adapter); 3812 /* The watchdog timer may be rescheduled, so explicitly 3813 * disable watchdog from being rescheduled. 3814 */ 3815 set_bit(__IGB_DOWN, &adapter->state); 3816 del_timer_sync(&adapter->watchdog_timer); 3817 del_timer_sync(&adapter->phy_info_timer); 3818 3819 cancel_work_sync(&adapter->reset_task); 3820 cancel_work_sync(&adapter->watchdog_task); 3821 3822 #ifdef CONFIG_IGB_DCA 3823 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3824 dev_info(&pdev->dev, "DCA disabled\n"); 3825 dca_remove_requester(&pdev->dev); 3826 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3827 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3828 } 3829 #endif 3830 3831 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3832 * would have already happened in close and is redundant. 3833 */ 3834 igb_release_hw_control(adapter); 3835 3836 #ifdef CONFIG_PCI_IOV 3837 rtnl_lock(); 3838 igb_disable_sriov(pdev); 3839 rtnl_unlock(); 3840 #endif 3841 3842 unregister_netdev(netdev); 3843 3844 igb_clear_interrupt_scheme(adapter); 3845 3846 pci_iounmap(pdev, adapter->io_addr); 3847 if (hw->flash_address) 3848 iounmap(hw->flash_address); 3849 pci_release_mem_regions(pdev); 3850 3851 kfree(adapter->mac_table); 3852 kfree(adapter->shadow_vfta); 3853 free_netdev(netdev); 3854 3855 pci_disable_device(pdev); 3856 } 3857 3858 /** 3859 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3860 * @adapter: board private structure to initialize 3861 * 3862 * This function initializes the vf specific data storage and then attempts to 3863 * allocate the VFs. The reason for ordering it this way is because it is much 3864 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3865 * the memory for the VFs. 3866 **/ 3867 static void igb_probe_vfs(struct igb_adapter *adapter) 3868 { 3869 #ifdef CONFIG_PCI_IOV 3870 struct pci_dev *pdev = adapter->pdev; 3871 struct e1000_hw *hw = &adapter->hw; 3872 3873 /* Virtualization features not supported on i210 family. */ 3874 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 3875 return; 3876 3877 /* Of the below we really only want the effect of getting 3878 * IGB_FLAG_HAS_MSIX set (if available), without which 3879 * igb_enable_sriov() has no effect. 3880 */ 3881 igb_set_interrupt_capability(adapter, true); 3882 igb_reset_interrupt_capability(adapter); 3883 3884 pci_sriov_set_totalvfs(pdev, 7); 3885 igb_enable_sriov(pdev, max_vfs); 3886 3887 #endif /* CONFIG_PCI_IOV */ 3888 } 3889 3890 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3891 { 3892 struct e1000_hw *hw = &adapter->hw; 3893 unsigned int max_rss_queues; 3894 3895 /* Determine the maximum number of RSS queues supported. */ 3896 switch (hw->mac.type) { 3897 case e1000_i211: 3898 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3899 break; 3900 case e1000_82575: 3901 case e1000_i210: 3902 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3903 break; 3904 case e1000_i350: 3905 /* I350 cannot do RSS and SR-IOV at the same time */ 3906 if (!!adapter->vfs_allocated_count) { 3907 max_rss_queues = 1; 3908 break; 3909 } 3910 fallthrough; 3911 case e1000_82576: 3912 if (!!adapter->vfs_allocated_count) { 3913 max_rss_queues = 2; 3914 break; 3915 } 3916 fallthrough; 3917 case e1000_82580: 3918 case e1000_i354: 3919 default: 3920 max_rss_queues = IGB_MAX_RX_QUEUES; 3921 break; 3922 } 3923 3924 return max_rss_queues; 3925 } 3926 3927 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3928 { 3929 u32 max_rss_queues; 3930 3931 max_rss_queues = igb_get_max_rss_queues(adapter); 3932 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3933 3934 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3935 } 3936 3937 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3938 const u32 max_rss_queues) 3939 { 3940 struct e1000_hw *hw = &adapter->hw; 3941 3942 /* Determine if we need to pair queues. */ 3943 switch (hw->mac.type) { 3944 case e1000_82575: 3945 case e1000_i211: 3946 /* Device supports enough interrupts without queue pairing. */ 3947 break; 3948 case e1000_82576: 3949 case e1000_82580: 3950 case e1000_i350: 3951 case e1000_i354: 3952 case e1000_i210: 3953 default: 3954 /* If rss_queues > half of max_rss_queues, pair the queues in 3955 * order to conserve interrupts due to limited supply. 3956 */ 3957 if (adapter->rss_queues > (max_rss_queues / 2)) 3958 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3959 else 3960 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 3961 break; 3962 } 3963 } 3964 3965 /** 3966 * igb_sw_init - Initialize general software structures (struct igb_adapter) 3967 * @adapter: board private structure to initialize 3968 * 3969 * igb_sw_init initializes the Adapter private data structure. 3970 * Fields are initialized based on PCI device information and 3971 * OS network device settings (MTU size). 3972 **/ 3973 static int igb_sw_init(struct igb_adapter *adapter) 3974 { 3975 struct e1000_hw *hw = &adapter->hw; 3976 struct net_device *netdev = adapter->netdev; 3977 struct pci_dev *pdev = adapter->pdev; 3978 3979 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 3980 3981 /* set default ring sizes */ 3982 adapter->tx_ring_count = IGB_DEFAULT_TXD; 3983 adapter->rx_ring_count = IGB_DEFAULT_RXD; 3984 3985 /* set default ITR values */ 3986 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 3987 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 3988 3989 /* set default work limits */ 3990 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 3991 3992 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD; 3993 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 3994 3995 spin_lock_init(&adapter->nfc_lock); 3996 spin_lock_init(&adapter->stats64_lock); 3997 3998 /* init spinlock to avoid concurrency of VF resources */ 3999 spin_lock_init(&adapter->vfs_lock); 4000 #ifdef CONFIG_PCI_IOV 4001 switch (hw->mac.type) { 4002 case e1000_82576: 4003 case e1000_i350: 4004 if (max_vfs > 7) { 4005 dev_warn(&pdev->dev, 4006 "Maximum of 7 VFs per PF, using max\n"); 4007 max_vfs = adapter->vfs_allocated_count = 7; 4008 } else 4009 adapter->vfs_allocated_count = max_vfs; 4010 if (adapter->vfs_allocated_count) 4011 dev_warn(&pdev->dev, 4012 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 4013 break; 4014 default: 4015 break; 4016 } 4017 #endif /* CONFIG_PCI_IOV */ 4018 4019 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 4020 adapter->flags |= IGB_FLAG_HAS_MSIX; 4021 4022 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 4023 sizeof(struct igb_mac_addr), 4024 GFP_KERNEL); 4025 if (!adapter->mac_table) 4026 return -ENOMEM; 4027 4028 igb_probe_vfs(adapter); 4029 4030 igb_init_queue_configuration(adapter); 4031 4032 /* Setup and initialize a copy of the hw vlan table array */ 4033 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 4034 GFP_KERNEL); 4035 if (!adapter->shadow_vfta) 4036 return -ENOMEM; 4037 4038 /* This call may decrease the number of queues */ 4039 if (igb_init_interrupt_scheme(adapter, true)) { 4040 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4041 return -ENOMEM; 4042 } 4043 4044 /* Explicitly disable IRQ since the NIC can be in any state. */ 4045 igb_irq_disable(adapter); 4046 4047 if (hw->mac.type >= e1000_i350) 4048 adapter->flags &= ~IGB_FLAG_DMAC; 4049 4050 set_bit(__IGB_DOWN, &adapter->state); 4051 return 0; 4052 } 4053 4054 /** 4055 * __igb_open - Called when a network interface is made active 4056 * @netdev: network interface device structure 4057 * @resuming: indicates whether we are in a resume call 4058 * 4059 * Returns 0 on success, negative value on failure 4060 * 4061 * The open entry point is called when a network interface is made 4062 * active by the system (IFF_UP). At this point all resources needed 4063 * for transmit and receive operations are allocated, the interrupt 4064 * handler is registered with the OS, the watchdog timer is started, 4065 * and the stack is notified that the interface is ready. 4066 **/ 4067 static int __igb_open(struct net_device *netdev, bool resuming) 4068 { 4069 struct igb_adapter *adapter = netdev_priv(netdev); 4070 struct e1000_hw *hw = &adapter->hw; 4071 struct pci_dev *pdev = adapter->pdev; 4072 int err; 4073 int i; 4074 4075 /* disallow open during test */ 4076 if (test_bit(__IGB_TESTING, &adapter->state)) { 4077 WARN_ON(resuming); 4078 return -EBUSY; 4079 } 4080 4081 if (!resuming) 4082 pm_runtime_get_sync(&pdev->dev); 4083 4084 netif_carrier_off(netdev); 4085 4086 /* allocate transmit descriptors */ 4087 err = igb_setup_all_tx_resources(adapter); 4088 if (err) 4089 goto err_setup_tx; 4090 4091 /* allocate receive descriptors */ 4092 err = igb_setup_all_rx_resources(adapter); 4093 if (err) 4094 goto err_setup_rx; 4095 4096 igb_power_up_link(adapter); 4097 4098 /* before we allocate an interrupt, we must be ready to handle it. 4099 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4100 * as soon as we call pci_request_irq, so we have to setup our 4101 * clean_rx handler before we do so. 4102 */ 4103 igb_configure(adapter); 4104 4105 err = igb_request_irq(adapter); 4106 if (err) 4107 goto err_req_irq; 4108 4109 /* Notify the stack of the actual queue counts. */ 4110 err = netif_set_real_num_tx_queues(adapter->netdev, 4111 adapter->num_tx_queues); 4112 if (err) 4113 goto err_set_queues; 4114 4115 err = netif_set_real_num_rx_queues(adapter->netdev, 4116 adapter->num_rx_queues); 4117 if (err) 4118 goto err_set_queues; 4119 4120 /* From here on the code is the same as igb_up() */ 4121 clear_bit(__IGB_DOWN, &adapter->state); 4122 4123 for (i = 0; i < adapter->num_q_vectors; i++) 4124 napi_enable(&(adapter->q_vector[i]->napi)); 4125 4126 /* Clear any pending interrupts. */ 4127 rd32(E1000_TSICR); 4128 rd32(E1000_ICR); 4129 4130 igb_irq_enable(adapter); 4131 4132 /* notify VFs that reset has been completed */ 4133 if (adapter->vfs_allocated_count) { 4134 u32 reg_data = rd32(E1000_CTRL_EXT); 4135 4136 reg_data |= E1000_CTRL_EXT_PFRSTD; 4137 wr32(E1000_CTRL_EXT, reg_data); 4138 } 4139 4140 netif_tx_start_all_queues(netdev); 4141 4142 if (!resuming) 4143 pm_runtime_put(&pdev->dev); 4144 4145 /* start the watchdog. */ 4146 hw->mac.get_link_status = 1; 4147 schedule_work(&adapter->watchdog_task); 4148 4149 return 0; 4150 4151 err_set_queues: 4152 igb_free_irq(adapter); 4153 err_req_irq: 4154 igb_release_hw_control(adapter); 4155 igb_power_down_link(adapter); 4156 igb_free_all_rx_resources(adapter); 4157 err_setup_rx: 4158 igb_free_all_tx_resources(adapter); 4159 err_setup_tx: 4160 igb_reset(adapter); 4161 if (!resuming) 4162 pm_runtime_put(&pdev->dev); 4163 4164 return err; 4165 } 4166 4167 int igb_open(struct net_device *netdev) 4168 { 4169 return __igb_open(netdev, false); 4170 } 4171 4172 /** 4173 * __igb_close - Disables a network interface 4174 * @netdev: network interface device structure 4175 * @suspending: indicates we are in a suspend call 4176 * 4177 * Returns 0, this is not allowed to fail 4178 * 4179 * The close entry point is called when an interface is de-activated 4180 * by the OS. The hardware is still under the driver's control, but 4181 * needs to be disabled. A global MAC reset is issued to stop the 4182 * hardware, and all transmit and receive resources are freed. 4183 **/ 4184 static int __igb_close(struct net_device *netdev, bool suspending) 4185 { 4186 struct igb_adapter *adapter = netdev_priv(netdev); 4187 struct pci_dev *pdev = adapter->pdev; 4188 4189 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4190 4191 if (!suspending) 4192 pm_runtime_get_sync(&pdev->dev); 4193 4194 igb_down(adapter); 4195 igb_free_irq(adapter); 4196 4197 igb_free_all_tx_resources(adapter); 4198 igb_free_all_rx_resources(adapter); 4199 4200 if (!suspending) 4201 pm_runtime_put_sync(&pdev->dev); 4202 return 0; 4203 } 4204 4205 int igb_close(struct net_device *netdev) 4206 { 4207 if (netif_device_present(netdev) || netdev->dismantle) 4208 return __igb_close(netdev, false); 4209 return 0; 4210 } 4211 4212 /** 4213 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4214 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4215 * 4216 * Return 0 on success, negative on failure 4217 **/ 4218 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4219 { 4220 struct device *dev = tx_ring->dev; 4221 int size; 4222 4223 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4224 4225 tx_ring->tx_buffer_info = vmalloc(size); 4226 if (!tx_ring->tx_buffer_info) 4227 goto err; 4228 4229 /* round up to nearest 4K */ 4230 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4231 tx_ring->size = ALIGN(tx_ring->size, 4096); 4232 4233 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4234 &tx_ring->dma, GFP_KERNEL); 4235 if (!tx_ring->desc) 4236 goto err; 4237 4238 tx_ring->next_to_use = 0; 4239 tx_ring->next_to_clean = 0; 4240 4241 return 0; 4242 4243 err: 4244 vfree(tx_ring->tx_buffer_info); 4245 tx_ring->tx_buffer_info = NULL; 4246 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4247 return -ENOMEM; 4248 } 4249 4250 /** 4251 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4252 * (Descriptors) for all queues 4253 * @adapter: board private structure 4254 * 4255 * Return 0 on success, negative on failure 4256 **/ 4257 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4258 { 4259 struct pci_dev *pdev = adapter->pdev; 4260 int i, err = 0; 4261 4262 for (i = 0; i < adapter->num_tx_queues; i++) { 4263 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4264 if (err) { 4265 dev_err(&pdev->dev, 4266 "Allocation for Tx Queue %u failed\n", i); 4267 for (i--; i >= 0; i--) 4268 igb_free_tx_resources(adapter->tx_ring[i]); 4269 break; 4270 } 4271 } 4272 4273 return err; 4274 } 4275 4276 /** 4277 * igb_setup_tctl - configure the transmit control registers 4278 * @adapter: Board private structure 4279 **/ 4280 void igb_setup_tctl(struct igb_adapter *adapter) 4281 { 4282 struct e1000_hw *hw = &adapter->hw; 4283 u32 tctl; 4284 4285 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4286 wr32(E1000_TXDCTL(0), 0); 4287 4288 /* Program the Transmit Control Register */ 4289 tctl = rd32(E1000_TCTL); 4290 tctl &= ~E1000_TCTL_CT; 4291 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4292 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4293 4294 igb_config_collision_dist(hw); 4295 4296 /* Enable transmits */ 4297 tctl |= E1000_TCTL_EN; 4298 4299 wr32(E1000_TCTL, tctl); 4300 } 4301 4302 /** 4303 * igb_configure_tx_ring - Configure transmit ring after Reset 4304 * @adapter: board private structure 4305 * @ring: tx ring to configure 4306 * 4307 * Configure a transmit ring after a reset. 4308 **/ 4309 void igb_configure_tx_ring(struct igb_adapter *adapter, 4310 struct igb_ring *ring) 4311 { 4312 struct e1000_hw *hw = &adapter->hw; 4313 u32 txdctl = 0; 4314 u64 tdba = ring->dma; 4315 int reg_idx = ring->reg_idx; 4316 4317 wr32(E1000_TDLEN(reg_idx), 4318 ring->count * sizeof(union e1000_adv_tx_desc)); 4319 wr32(E1000_TDBAL(reg_idx), 4320 tdba & 0x00000000ffffffffULL); 4321 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4322 4323 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4324 wr32(E1000_TDH(reg_idx), 0); 4325 writel(0, ring->tail); 4326 4327 txdctl |= IGB_TX_PTHRESH; 4328 txdctl |= IGB_TX_HTHRESH << 8; 4329 txdctl |= IGB_TX_WTHRESH << 16; 4330 4331 /* reinitialize tx_buffer_info */ 4332 memset(ring->tx_buffer_info, 0, 4333 sizeof(struct igb_tx_buffer) * ring->count); 4334 4335 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4336 wr32(E1000_TXDCTL(reg_idx), txdctl); 4337 } 4338 4339 /** 4340 * igb_configure_tx - Configure transmit Unit after Reset 4341 * @adapter: board private structure 4342 * 4343 * Configure the Tx unit of the MAC after a reset. 4344 **/ 4345 static void igb_configure_tx(struct igb_adapter *adapter) 4346 { 4347 struct e1000_hw *hw = &adapter->hw; 4348 int i; 4349 4350 /* disable the queues */ 4351 for (i = 0; i < adapter->num_tx_queues; i++) 4352 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4353 4354 wrfl(); 4355 usleep_range(10000, 20000); 4356 4357 for (i = 0; i < adapter->num_tx_queues; i++) 4358 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4359 } 4360 4361 /** 4362 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4363 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4364 * 4365 * Returns 0 on success, negative on failure 4366 **/ 4367 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4368 { 4369 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev); 4370 struct device *dev = rx_ring->dev; 4371 int size, res; 4372 4373 /* XDP RX-queue info */ 4374 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq)) 4375 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4376 res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 4377 rx_ring->queue_index, 0); 4378 if (res < 0) { 4379 dev_err(dev, "Failed to register xdp_rxq index %u\n", 4380 rx_ring->queue_index); 4381 return res; 4382 } 4383 4384 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4385 4386 rx_ring->rx_buffer_info = vmalloc(size); 4387 if (!rx_ring->rx_buffer_info) 4388 goto err; 4389 4390 /* Round up to nearest 4K */ 4391 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4392 rx_ring->size = ALIGN(rx_ring->size, 4096); 4393 4394 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4395 &rx_ring->dma, GFP_KERNEL); 4396 if (!rx_ring->desc) 4397 goto err; 4398 4399 rx_ring->next_to_alloc = 0; 4400 rx_ring->next_to_clean = 0; 4401 rx_ring->next_to_use = 0; 4402 4403 rx_ring->xdp_prog = adapter->xdp_prog; 4404 4405 return 0; 4406 4407 err: 4408 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4409 vfree(rx_ring->rx_buffer_info); 4410 rx_ring->rx_buffer_info = NULL; 4411 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4412 return -ENOMEM; 4413 } 4414 4415 /** 4416 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4417 * (Descriptors) for all queues 4418 * @adapter: board private structure 4419 * 4420 * Return 0 on success, negative on failure 4421 **/ 4422 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4423 { 4424 struct pci_dev *pdev = adapter->pdev; 4425 int i, err = 0; 4426 4427 for (i = 0; i < adapter->num_rx_queues; i++) { 4428 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4429 if (err) { 4430 dev_err(&pdev->dev, 4431 "Allocation for Rx Queue %u failed\n", i); 4432 for (i--; i >= 0; i--) 4433 igb_free_rx_resources(adapter->rx_ring[i]); 4434 break; 4435 } 4436 } 4437 4438 return err; 4439 } 4440 4441 /** 4442 * igb_setup_mrqc - configure the multiple receive queue control registers 4443 * @adapter: Board private structure 4444 **/ 4445 static void igb_setup_mrqc(struct igb_adapter *adapter) 4446 { 4447 struct e1000_hw *hw = &adapter->hw; 4448 u32 mrqc, rxcsum; 4449 u32 j, num_rx_queues; 4450 u32 rss_key[10]; 4451 4452 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4453 for (j = 0; j < 10; j++) 4454 wr32(E1000_RSSRK(j), rss_key[j]); 4455 4456 num_rx_queues = adapter->rss_queues; 4457 4458 switch (hw->mac.type) { 4459 case e1000_82576: 4460 /* 82576 supports 2 RSS queues for SR-IOV */ 4461 if (adapter->vfs_allocated_count) 4462 num_rx_queues = 2; 4463 break; 4464 default: 4465 break; 4466 } 4467 4468 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4469 for (j = 0; j < IGB_RETA_SIZE; j++) 4470 adapter->rss_indir_tbl[j] = 4471 (j * num_rx_queues) / IGB_RETA_SIZE; 4472 adapter->rss_indir_tbl_init = num_rx_queues; 4473 } 4474 igb_write_rss_indir_tbl(adapter); 4475 4476 /* Disable raw packet checksumming so that RSS hash is placed in 4477 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4478 * offloads as they are enabled by default 4479 */ 4480 rxcsum = rd32(E1000_RXCSUM); 4481 rxcsum |= E1000_RXCSUM_PCSD; 4482 4483 if (adapter->hw.mac.type >= e1000_82576) 4484 /* Enable Receive Checksum Offload for SCTP */ 4485 rxcsum |= E1000_RXCSUM_CRCOFL; 4486 4487 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4488 wr32(E1000_RXCSUM, rxcsum); 4489 4490 /* Generate RSS hash based on packet types, TCP/UDP 4491 * port numbers and/or IPv4/v6 src and dst addresses 4492 */ 4493 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4494 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4495 E1000_MRQC_RSS_FIELD_IPV6 | 4496 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4497 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4498 4499 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4500 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4501 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4502 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4503 4504 /* If VMDq is enabled then we set the appropriate mode for that, else 4505 * we default to RSS so that an RSS hash is calculated per packet even 4506 * if we are only using one queue 4507 */ 4508 if (adapter->vfs_allocated_count) { 4509 if (hw->mac.type > e1000_82575) { 4510 /* Set the default pool for the PF's first queue */ 4511 u32 vtctl = rd32(E1000_VT_CTL); 4512 4513 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4514 E1000_VT_CTL_DISABLE_DEF_POOL); 4515 vtctl |= adapter->vfs_allocated_count << 4516 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4517 wr32(E1000_VT_CTL, vtctl); 4518 } 4519 if (adapter->rss_queues > 1) 4520 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4521 else 4522 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4523 } else { 4524 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4525 } 4526 igb_vmm_control(adapter); 4527 4528 wr32(E1000_MRQC, mrqc); 4529 } 4530 4531 /** 4532 * igb_setup_rctl - configure the receive control registers 4533 * @adapter: Board private structure 4534 **/ 4535 void igb_setup_rctl(struct igb_adapter *adapter) 4536 { 4537 struct e1000_hw *hw = &adapter->hw; 4538 u32 rctl; 4539 4540 rctl = rd32(E1000_RCTL); 4541 4542 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4543 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4544 4545 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4546 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4547 4548 /* enable stripping of CRC. It's unlikely this will break BMC 4549 * redirection as it did with e1000. Newer features require 4550 * that the HW strips the CRC. 4551 */ 4552 rctl |= E1000_RCTL_SECRC; 4553 4554 /* disable store bad packets and clear size bits. */ 4555 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4556 4557 /* enable LPE to allow for reception of jumbo frames */ 4558 rctl |= E1000_RCTL_LPE; 4559 4560 /* disable queue 0 to prevent tail write w/o re-config */ 4561 wr32(E1000_RXDCTL(0), 0); 4562 4563 /* Attention!!! For SR-IOV PF driver operations you must enable 4564 * queue drop for all VF and PF queues to prevent head of line blocking 4565 * if an un-trusted VF does not provide descriptors to hardware. 4566 */ 4567 if (adapter->vfs_allocated_count) { 4568 /* set all queue drop enable bits */ 4569 wr32(E1000_QDE, ALL_QUEUES); 4570 } 4571 4572 /* This is useful for sniffing bad packets. */ 4573 if (adapter->netdev->features & NETIF_F_RXALL) { 4574 /* UPE and MPE will be handled by normal PROMISC logic 4575 * in e1000e_set_rx_mode 4576 */ 4577 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4578 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4579 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4580 4581 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4582 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4583 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4584 * and that breaks VLANs. 4585 */ 4586 } 4587 4588 wr32(E1000_RCTL, rctl); 4589 } 4590 4591 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4592 int vfn) 4593 { 4594 struct e1000_hw *hw = &adapter->hw; 4595 u32 vmolr; 4596 4597 if (size > MAX_JUMBO_FRAME_SIZE) 4598 size = MAX_JUMBO_FRAME_SIZE; 4599 4600 vmolr = rd32(E1000_VMOLR(vfn)); 4601 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4602 vmolr |= size | E1000_VMOLR_LPE; 4603 wr32(E1000_VMOLR(vfn), vmolr); 4604 4605 return 0; 4606 } 4607 4608 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4609 int vfn, bool enable) 4610 { 4611 struct e1000_hw *hw = &adapter->hw; 4612 u32 val, reg; 4613 4614 if (hw->mac.type < e1000_82576) 4615 return; 4616 4617 if (hw->mac.type == e1000_i350) 4618 reg = E1000_DVMOLR(vfn); 4619 else 4620 reg = E1000_VMOLR(vfn); 4621 4622 val = rd32(reg); 4623 if (enable) 4624 val |= E1000_VMOLR_STRVLAN; 4625 else 4626 val &= ~(E1000_VMOLR_STRVLAN); 4627 wr32(reg, val); 4628 } 4629 4630 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4631 int vfn, bool aupe) 4632 { 4633 struct e1000_hw *hw = &adapter->hw; 4634 u32 vmolr; 4635 4636 /* This register exists only on 82576 and newer so if we are older then 4637 * we should exit and do nothing 4638 */ 4639 if (hw->mac.type < e1000_82576) 4640 return; 4641 4642 vmolr = rd32(E1000_VMOLR(vfn)); 4643 if (aupe) 4644 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4645 else 4646 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4647 4648 /* clear all bits that might not be set */ 4649 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4650 4651 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4652 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4653 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4654 * multicast packets 4655 */ 4656 if (vfn <= adapter->vfs_allocated_count) 4657 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4658 4659 wr32(E1000_VMOLR(vfn), vmolr); 4660 } 4661 4662 /** 4663 * igb_setup_srrctl - configure the split and replication receive control 4664 * registers 4665 * @adapter: Board private structure 4666 * @ring: receive ring to be configured 4667 **/ 4668 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring) 4669 { 4670 struct e1000_hw *hw = &adapter->hw; 4671 int reg_idx = ring->reg_idx; 4672 u32 srrctl = 0; 4673 4674 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4675 if (ring_uses_large_buffer(ring)) 4676 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4677 else 4678 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4679 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4680 if (hw->mac.type >= e1000_82580) 4681 srrctl |= E1000_SRRCTL_TIMESTAMP; 4682 /* Only set Drop Enable if VFs allocated, or we are supporting multiple 4683 * queues and rx flow control is disabled 4684 */ 4685 if (adapter->vfs_allocated_count || 4686 (!(hw->fc.current_mode & e1000_fc_rx_pause) && 4687 adapter->num_rx_queues > 1)) 4688 srrctl |= E1000_SRRCTL_DROP_EN; 4689 4690 wr32(E1000_SRRCTL(reg_idx), srrctl); 4691 } 4692 4693 /** 4694 * igb_configure_rx_ring - Configure a receive ring after Reset 4695 * @adapter: board private structure 4696 * @ring: receive ring to be configured 4697 * 4698 * Configure the Rx unit of the MAC after a reset. 4699 **/ 4700 void igb_configure_rx_ring(struct igb_adapter *adapter, 4701 struct igb_ring *ring) 4702 { 4703 struct e1000_hw *hw = &adapter->hw; 4704 union e1000_adv_rx_desc *rx_desc; 4705 u64 rdba = ring->dma; 4706 int reg_idx = ring->reg_idx; 4707 u32 rxdctl = 0; 4708 4709 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4710 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4711 MEM_TYPE_PAGE_SHARED, NULL)); 4712 4713 /* disable the queue */ 4714 wr32(E1000_RXDCTL(reg_idx), 0); 4715 4716 /* Set DMA base address registers */ 4717 wr32(E1000_RDBAL(reg_idx), 4718 rdba & 0x00000000ffffffffULL); 4719 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4720 wr32(E1000_RDLEN(reg_idx), 4721 ring->count * sizeof(union e1000_adv_rx_desc)); 4722 4723 /* initialize head and tail */ 4724 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4725 wr32(E1000_RDH(reg_idx), 0); 4726 writel(0, ring->tail); 4727 4728 /* set descriptor configuration */ 4729 igb_setup_srrctl(adapter, ring); 4730 4731 /* set filtering for VMDQ pools */ 4732 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4733 4734 rxdctl |= IGB_RX_PTHRESH; 4735 rxdctl |= IGB_RX_HTHRESH << 8; 4736 rxdctl |= IGB_RX_WTHRESH << 16; 4737 4738 /* initialize rx_buffer_info */ 4739 memset(ring->rx_buffer_info, 0, 4740 sizeof(struct igb_rx_buffer) * ring->count); 4741 4742 /* initialize Rx descriptor 0 */ 4743 rx_desc = IGB_RX_DESC(ring, 0); 4744 rx_desc->wb.upper.length = 0; 4745 4746 /* enable receive descriptor fetching */ 4747 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4748 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4749 } 4750 4751 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4752 struct igb_ring *rx_ring) 4753 { 4754 /* set build_skb and buffer size flags */ 4755 clear_ring_build_skb_enabled(rx_ring); 4756 clear_ring_uses_large_buffer(rx_ring); 4757 4758 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4759 return; 4760 4761 set_ring_build_skb_enabled(rx_ring); 4762 4763 #if (PAGE_SIZE < 8192) 4764 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4765 return; 4766 4767 set_ring_uses_large_buffer(rx_ring); 4768 #endif 4769 } 4770 4771 /** 4772 * igb_configure_rx - Configure receive Unit after Reset 4773 * @adapter: board private structure 4774 * 4775 * Configure the Rx unit of the MAC after a reset. 4776 **/ 4777 static void igb_configure_rx(struct igb_adapter *adapter) 4778 { 4779 int i; 4780 4781 /* set the correct pool for the PF default MAC address in entry 0 */ 4782 igb_set_default_mac_filter(adapter); 4783 4784 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4785 * the Base and Length of the Rx Descriptor Ring 4786 */ 4787 for (i = 0; i < adapter->num_rx_queues; i++) { 4788 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4789 4790 igb_set_rx_buffer_len(adapter, rx_ring); 4791 igb_configure_rx_ring(adapter, rx_ring); 4792 } 4793 } 4794 4795 /** 4796 * igb_free_tx_resources - Free Tx Resources per Queue 4797 * @tx_ring: Tx descriptor ring for a specific queue 4798 * 4799 * Free all transmit software resources 4800 **/ 4801 void igb_free_tx_resources(struct igb_ring *tx_ring) 4802 { 4803 igb_clean_tx_ring(tx_ring); 4804 4805 vfree(tx_ring->tx_buffer_info); 4806 tx_ring->tx_buffer_info = NULL; 4807 4808 /* if not set, then don't free */ 4809 if (!tx_ring->desc) 4810 return; 4811 4812 dma_free_coherent(tx_ring->dev, tx_ring->size, 4813 tx_ring->desc, tx_ring->dma); 4814 4815 tx_ring->desc = NULL; 4816 } 4817 4818 /** 4819 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4820 * @adapter: board private structure 4821 * 4822 * Free all transmit software resources 4823 **/ 4824 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4825 { 4826 int i; 4827 4828 for (i = 0; i < adapter->num_tx_queues; i++) 4829 if (adapter->tx_ring[i]) 4830 igb_free_tx_resources(adapter->tx_ring[i]); 4831 } 4832 4833 /** 4834 * igb_clean_tx_ring - Free Tx Buffers 4835 * @tx_ring: ring to be cleaned 4836 **/ 4837 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 4838 { 4839 u16 i = tx_ring->next_to_clean; 4840 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4841 4842 while (i != tx_ring->next_to_use) { 4843 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4844 4845 /* Free all the Tx ring sk_buffs or xdp frames */ 4846 if (tx_buffer->type == IGB_TYPE_SKB) 4847 dev_kfree_skb_any(tx_buffer->skb); 4848 else 4849 xdp_return_frame(tx_buffer->xdpf); 4850 4851 /* unmap skb header data */ 4852 dma_unmap_single(tx_ring->dev, 4853 dma_unmap_addr(tx_buffer, dma), 4854 dma_unmap_len(tx_buffer, len), 4855 DMA_TO_DEVICE); 4856 4857 /* check for eop_desc to determine the end of the packet */ 4858 eop_desc = tx_buffer->next_to_watch; 4859 tx_desc = IGB_TX_DESC(tx_ring, i); 4860 4861 /* unmap remaining buffers */ 4862 while (tx_desc != eop_desc) { 4863 tx_buffer++; 4864 tx_desc++; 4865 i++; 4866 if (unlikely(i == tx_ring->count)) { 4867 i = 0; 4868 tx_buffer = tx_ring->tx_buffer_info; 4869 tx_desc = IGB_TX_DESC(tx_ring, 0); 4870 } 4871 4872 /* unmap any remaining paged data */ 4873 if (dma_unmap_len(tx_buffer, len)) 4874 dma_unmap_page(tx_ring->dev, 4875 dma_unmap_addr(tx_buffer, dma), 4876 dma_unmap_len(tx_buffer, len), 4877 DMA_TO_DEVICE); 4878 } 4879 4880 tx_buffer->next_to_watch = NULL; 4881 4882 /* move us one more past the eop_desc for start of next pkt */ 4883 tx_buffer++; 4884 i++; 4885 if (unlikely(i == tx_ring->count)) { 4886 i = 0; 4887 tx_buffer = tx_ring->tx_buffer_info; 4888 } 4889 } 4890 4891 /* reset BQL for queue */ 4892 netdev_tx_reset_queue(txring_txq(tx_ring)); 4893 4894 /* reset next_to_use and next_to_clean */ 4895 tx_ring->next_to_use = 0; 4896 tx_ring->next_to_clean = 0; 4897 } 4898 4899 /** 4900 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 4901 * @adapter: board private structure 4902 **/ 4903 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 4904 { 4905 int i; 4906 4907 for (i = 0; i < adapter->num_tx_queues; i++) 4908 if (adapter->tx_ring[i]) 4909 igb_clean_tx_ring(adapter->tx_ring[i]); 4910 } 4911 4912 /** 4913 * igb_free_rx_resources - Free Rx Resources 4914 * @rx_ring: ring to clean the resources from 4915 * 4916 * Free all receive software resources 4917 **/ 4918 void igb_free_rx_resources(struct igb_ring *rx_ring) 4919 { 4920 igb_clean_rx_ring(rx_ring); 4921 4922 rx_ring->xdp_prog = NULL; 4923 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4924 vfree(rx_ring->rx_buffer_info); 4925 rx_ring->rx_buffer_info = NULL; 4926 4927 /* if not set, then don't free */ 4928 if (!rx_ring->desc) 4929 return; 4930 4931 dma_free_coherent(rx_ring->dev, rx_ring->size, 4932 rx_ring->desc, rx_ring->dma); 4933 4934 rx_ring->desc = NULL; 4935 } 4936 4937 /** 4938 * igb_free_all_rx_resources - Free Rx Resources for All Queues 4939 * @adapter: board private structure 4940 * 4941 * Free all receive software resources 4942 **/ 4943 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 4944 { 4945 int i; 4946 4947 for (i = 0; i < adapter->num_rx_queues; i++) 4948 if (adapter->rx_ring[i]) 4949 igb_free_rx_resources(adapter->rx_ring[i]); 4950 } 4951 4952 /** 4953 * igb_clean_rx_ring - Free Rx Buffers per Queue 4954 * @rx_ring: ring to free buffers from 4955 **/ 4956 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 4957 { 4958 u16 i = rx_ring->next_to_clean; 4959 4960 dev_kfree_skb(rx_ring->skb); 4961 rx_ring->skb = NULL; 4962 4963 /* Free all the Rx ring sk_buffs */ 4964 while (i != rx_ring->next_to_alloc) { 4965 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 4966 4967 /* Invalidate cache lines that may have been written to by 4968 * device so that we avoid corrupting memory. 4969 */ 4970 dma_sync_single_range_for_cpu(rx_ring->dev, 4971 buffer_info->dma, 4972 buffer_info->page_offset, 4973 igb_rx_bufsz(rx_ring), 4974 DMA_FROM_DEVICE); 4975 4976 /* free resources associated with mapping */ 4977 dma_unmap_page_attrs(rx_ring->dev, 4978 buffer_info->dma, 4979 igb_rx_pg_size(rx_ring), 4980 DMA_FROM_DEVICE, 4981 IGB_RX_DMA_ATTR); 4982 __page_frag_cache_drain(buffer_info->page, 4983 buffer_info->pagecnt_bias); 4984 4985 i++; 4986 if (i == rx_ring->count) 4987 i = 0; 4988 } 4989 4990 rx_ring->next_to_alloc = 0; 4991 rx_ring->next_to_clean = 0; 4992 rx_ring->next_to_use = 0; 4993 } 4994 4995 /** 4996 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 4997 * @adapter: board private structure 4998 **/ 4999 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 5000 { 5001 int i; 5002 5003 for (i = 0; i < adapter->num_rx_queues; i++) 5004 if (adapter->rx_ring[i]) 5005 igb_clean_rx_ring(adapter->rx_ring[i]); 5006 } 5007 5008 /** 5009 * igb_set_mac - Change the Ethernet Address of the NIC 5010 * @netdev: network interface device structure 5011 * @p: pointer to an address structure 5012 * 5013 * Returns 0 on success, negative on failure 5014 **/ 5015 static int igb_set_mac(struct net_device *netdev, void *p) 5016 { 5017 struct igb_adapter *adapter = netdev_priv(netdev); 5018 struct e1000_hw *hw = &adapter->hw; 5019 struct sockaddr *addr = p; 5020 5021 if (!is_valid_ether_addr(addr->sa_data)) 5022 return -EADDRNOTAVAIL; 5023 5024 eth_hw_addr_set(netdev, addr->sa_data); 5025 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 5026 5027 /* set the correct pool for the new PF MAC address in entry 0 */ 5028 igb_set_default_mac_filter(adapter); 5029 5030 return 0; 5031 } 5032 5033 /** 5034 * igb_write_mc_addr_list - write multicast addresses to MTA 5035 * @netdev: network interface device structure 5036 * 5037 * Writes multicast address list to the MTA hash table. 5038 * Returns: -ENOMEM on failure 5039 * 0 on no addresses written 5040 * X on writing X addresses to MTA 5041 **/ 5042 static int igb_write_mc_addr_list(struct net_device *netdev) 5043 { 5044 struct igb_adapter *adapter = netdev_priv(netdev); 5045 struct e1000_hw *hw = &adapter->hw; 5046 struct netdev_hw_addr *ha; 5047 u8 *mta_list; 5048 int i; 5049 5050 if (netdev_mc_empty(netdev)) { 5051 /* nothing to program, so clear mc list */ 5052 igb_update_mc_addr_list(hw, NULL, 0); 5053 igb_restore_vf_multicasts(adapter); 5054 return 0; 5055 } 5056 5057 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 5058 if (!mta_list) 5059 return -ENOMEM; 5060 5061 /* The shared function expects a packed array of only addresses. */ 5062 i = 0; 5063 netdev_for_each_mc_addr(ha, netdev) 5064 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 5065 5066 igb_update_mc_addr_list(hw, mta_list, i); 5067 kfree(mta_list); 5068 5069 return netdev_mc_count(netdev); 5070 } 5071 5072 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 5073 { 5074 struct e1000_hw *hw = &adapter->hw; 5075 u32 i, pf_id; 5076 5077 switch (hw->mac.type) { 5078 case e1000_i210: 5079 case e1000_i211: 5080 case e1000_i350: 5081 /* VLAN filtering needed for VLAN prio filter */ 5082 if (adapter->netdev->features & NETIF_F_NTUPLE) 5083 break; 5084 fallthrough; 5085 case e1000_82576: 5086 case e1000_82580: 5087 case e1000_i354: 5088 /* VLAN filtering needed for pool filtering */ 5089 if (adapter->vfs_allocated_count) 5090 break; 5091 fallthrough; 5092 default: 5093 return 1; 5094 } 5095 5096 /* We are already in VLAN promisc, nothing to do */ 5097 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 5098 return 0; 5099 5100 if (!adapter->vfs_allocated_count) 5101 goto set_vfta; 5102 5103 /* Add PF to all active pools */ 5104 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5105 5106 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5107 u32 vlvf = rd32(E1000_VLVF(i)); 5108 5109 vlvf |= BIT(pf_id); 5110 wr32(E1000_VLVF(i), vlvf); 5111 } 5112 5113 set_vfta: 5114 /* Set all bits in the VLAN filter table array */ 5115 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 5116 hw->mac.ops.write_vfta(hw, i, ~0U); 5117 5118 /* Set flag so we don't redo unnecessary work */ 5119 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 5120 5121 return 0; 5122 } 5123 5124 #define VFTA_BLOCK_SIZE 8 5125 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 5126 { 5127 struct e1000_hw *hw = &adapter->hw; 5128 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 5129 u32 vid_start = vfta_offset * 32; 5130 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 5131 u32 i, vid, word, bits, pf_id; 5132 5133 /* guarantee that we don't scrub out management VLAN */ 5134 vid = adapter->mng_vlan_id; 5135 if (vid >= vid_start && vid < vid_end) 5136 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5137 5138 if (!adapter->vfs_allocated_count) 5139 goto set_vfta; 5140 5141 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5142 5143 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5144 u32 vlvf = rd32(E1000_VLVF(i)); 5145 5146 /* pull VLAN ID from VLVF */ 5147 vid = vlvf & VLAN_VID_MASK; 5148 5149 /* only concern ourselves with a certain range */ 5150 if (vid < vid_start || vid >= vid_end) 5151 continue; 5152 5153 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 5154 /* record VLAN ID in VFTA */ 5155 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5156 5157 /* if PF is part of this then continue */ 5158 if (test_bit(vid, adapter->active_vlans)) 5159 continue; 5160 } 5161 5162 /* remove PF from the pool */ 5163 bits = ~BIT(pf_id); 5164 bits &= rd32(E1000_VLVF(i)); 5165 wr32(E1000_VLVF(i), bits); 5166 } 5167 5168 set_vfta: 5169 /* extract values from active_vlans and write back to VFTA */ 5170 for (i = VFTA_BLOCK_SIZE; i--;) { 5171 vid = (vfta_offset + i) * 32; 5172 word = vid / BITS_PER_LONG; 5173 bits = vid % BITS_PER_LONG; 5174 5175 vfta[i] |= adapter->active_vlans[word] >> bits; 5176 5177 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 5178 } 5179 } 5180 5181 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 5182 { 5183 u32 i; 5184 5185 /* We are not in VLAN promisc, nothing to do */ 5186 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 5187 return; 5188 5189 /* Set flag so we don't redo unnecessary work */ 5190 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 5191 5192 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 5193 igb_scrub_vfta(adapter, i); 5194 } 5195 5196 /** 5197 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 5198 * @netdev: network interface device structure 5199 * 5200 * The set_rx_mode entry point is called whenever the unicast or multicast 5201 * address lists or the network interface flags are updated. This routine is 5202 * responsible for configuring the hardware for proper unicast, multicast, 5203 * promiscuous mode, and all-multi behavior. 5204 **/ 5205 static void igb_set_rx_mode(struct net_device *netdev) 5206 { 5207 struct igb_adapter *adapter = netdev_priv(netdev); 5208 struct e1000_hw *hw = &adapter->hw; 5209 unsigned int vfn = adapter->vfs_allocated_count; 5210 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 5211 int count; 5212 5213 /* Check for Promiscuous and All Multicast modes */ 5214 if (netdev->flags & IFF_PROMISC) { 5215 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5216 vmolr |= E1000_VMOLR_MPME; 5217 5218 /* enable use of UTA filter to force packets to default pool */ 5219 if (hw->mac.type == e1000_82576) 5220 vmolr |= E1000_VMOLR_ROPE; 5221 } else { 5222 if (netdev->flags & IFF_ALLMULTI) { 5223 rctl |= E1000_RCTL_MPE; 5224 vmolr |= E1000_VMOLR_MPME; 5225 } else { 5226 /* Write addresses to the MTA, if the attempt fails 5227 * then we should just turn on promiscuous mode so 5228 * that we can at least receive multicast traffic 5229 */ 5230 count = igb_write_mc_addr_list(netdev); 5231 if (count < 0) { 5232 rctl |= E1000_RCTL_MPE; 5233 vmolr |= E1000_VMOLR_MPME; 5234 } else if (count) { 5235 vmolr |= E1000_VMOLR_ROMPE; 5236 } 5237 } 5238 } 5239 5240 /* Write addresses to available RAR registers, if there is not 5241 * sufficient space to store all the addresses then enable 5242 * unicast promiscuous mode 5243 */ 5244 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5245 rctl |= E1000_RCTL_UPE; 5246 vmolr |= E1000_VMOLR_ROPE; 5247 } 5248 5249 /* enable VLAN filtering by default */ 5250 rctl |= E1000_RCTL_VFE; 5251 5252 /* disable VLAN filtering for modes that require it */ 5253 if ((netdev->flags & IFF_PROMISC) || 5254 (netdev->features & NETIF_F_RXALL)) { 5255 /* if we fail to set all rules then just clear VFE */ 5256 if (igb_vlan_promisc_enable(adapter)) 5257 rctl &= ~E1000_RCTL_VFE; 5258 } else { 5259 igb_vlan_promisc_disable(adapter); 5260 } 5261 5262 /* update state of unicast, multicast, and VLAN filtering modes */ 5263 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5264 E1000_RCTL_VFE); 5265 wr32(E1000_RCTL, rctl); 5266 5267 #if (PAGE_SIZE < 8192) 5268 if (!adapter->vfs_allocated_count) { 5269 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5270 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5271 } 5272 #endif 5273 wr32(E1000_RLPML, rlpml); 5274 5275 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5276 * the VMOLR to enable the appropriate modes. Without this workaround 5277 * we will have issues with VLAN tag stripping not being done for frames 5278 * that are only arriving because we are the default pool 5279 */ 5280 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5281 return; 5282 5283 /* set UTA to appropriate mode */ 5284 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5285 5286 vmolr |= rd32(E1000_VMOLR(vfn)) & 5287 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5288 5289 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5290 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5291 #if (PAGE_SIZE < 8192) 5292 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5293 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5294 else 5295 #endif 5296 vmolr |= MAX_JUMBO_FRAME_SIZE; 5297 vmolr |= E1000_VMOLR_LPE; 5298 5299 wr32(E1000_VMOLR(vfn), vmolr); 5300 5301 igb_restore_vf_multicasts(adapter); 5302 } 5303 5304 static void igb_check_wvbr(struct igb_adapter *adapter) 5305 { 5306 struct e1000_hw *hw = &adapter->hw; 5307 u32 wvbr = 0; 5308 5309 switch (hw->mac.type) { 5310 case e1000_82576: 5311 case e1000_i350: 5312 wvbr = rd32(E1000_WVBR); 5313 if (!wvbr) 5314 return; 5315 break; 5316 default: 5317 break; 5318 } 5319 5320 adapter->wvbr |= wvbr; 5321 } 5322 5323 #define IGB_STAGGERED_QUEUE_OFFSET 8 5324 5325 static void igb_spoof_check(struct igb_adapter *adapter) 5326 { 5327 int j; 5328 5329 if (!adapter->wvbr) 5330 return; 5331 5332 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5333 if (adapter->wvbr & BIT(j) || 5334 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5335 dev_warn(&adapter->pdev->dev, 5336 "Spoof event(s) detected on VF %d\n", j); 5337 adapter->wvbr &= 5338 ~(BIT(j) | 5339 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5340 } 5341 } 5342 } 5343 5344 /* Need to wait a few seconds after link up to get diagnostic information from 5345 * the phy 5346 */ 5347 static void igb_update_phy_info(struct timer_list *t) 5348 { 5349 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5350 igb_get_phy_info(&adapter->hw); 5351 } 5352 5353 /** 5354 * igb_has_link - check shared code for link and determine up/down 5355 * @adapter: pointer to driver private info 5356 **/ 5357 bool igb_has_link(struct igb_adapter *adapter) 5358 { 5359 struct e1000_hw *hw = &adapter->hw; 5360 bool link_active = false; 5361 5362 /* get_link_status is set on LSC (link status) interrupt or 5363 * rx sequence error interrupt. get_link_status will stay 5364 * false until the e1000_check_for_link establishes link 5365 * for copper adapters ONLY 5366 */ 5367 switch (hw->phy.media_type) { 5368 case e1000_media_type_copper: 5369 if (!hw->mac.get_link_status) 5370 return true; 5371 fallthrough; 5372 case e1000_media_type_internal_serdes: 5373 hw->mac.ops.check_for_link(hw); 5374 link_active = !hw->mac.get_link_status; 5375 break; 5376 default: 5377 case e1000_media_type_unknown: 5378 break; 5379 } 5380 5381 if (((hw->mac.type == e1000_i210) || 5382 (hw->mac.type == e1000_i211)) && 5383 (hw->phy.id == I210_I_PHY_ID)) { 5384 if (!netif_carrier_ok(adapter->netdev)) { 5385 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5386 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5387 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5388 adapter->link_check_timeout = jiffies; 5389 } 5390 } 5391 5392 return link_active; 5393 } 5394 5395 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5396 { 5397 bool ret = false; 5398 u32 ctrl_ext, thstat; 5399 5400 /* check for thermal sensor event on i350 copper only */ 5401 if (hw->mac.type == e1000_i350) { 5402 thstat = rd32(E1000_THSTAT); 5403 ctrl_ext = rd32(E1000_CTRL_EXT); 5404 5405 if ((hw->phy.media_type == e1000_media_type_copper) && 5406 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5407 ret = !!(thstat & event); 5408 } 5409 5410 return ret; 5411 } 5412 5413 /** 5414 * igb_check_lvmmc - check for malformed packets received 5415 * and indicated in LVMMC register 5416 * @adapter: pointer to adapter 5417 **/ 5418 static void igb_check_lvmmc(struct igb_adapter *adapter) 5419 { 5420 struct e1000_hw *hw = &adapter->hw; 5421 u32 lvmmc; 5422 5423 lvmmc = rd32(E1000_LVMMC); 5424 if (lvmmc) { 5425 if (unlikely(net_ratelimit())) { 5426 netdev_warn(adapter->netdev, 5427 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5428 lvmmc); 5429 } 5430 } 5431 } 5432 5433 /** 5434 * igb_watchdog - Timer Call-back 5435 * @t: pointer to timer_list containing our private info pointer 5436 **/ 5437 static void igb_watchdog(struct timer_list *t) 5438 { 5439 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5440 /* Do the rest outside of interrupt context */ 5441 schedule_work(&adapter->watchdog_task); 5442 } 5443 5444 static void igb_watchdog_task(struct work_struct *work) 5445 { 5446 struct igb_adapter *adapter = container_of(work, 5447 struct igb_adapter, 5448 watchdog_task); 5449 struct e1000_hw *hw = &adapter->hw; 5450 struct e1000_phy_info *phy = &hw->phy; 5451 struct net_device *netdev = adapter->netdev; 5452 u32 link; 5453 int i; 5454 u32 connsw; 5455 u16 phy_data, retry_count = 20; 5456 5457 link = igb_has_link(adapter); 5458 5459 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5460 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5461 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5462 else 5463 link = false; 5464 } 5465 5466 /* Force link down if we have fiber to swap to */ 5467 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5468 if (hw->phy.media_type == e1000_media_type_copper) { 5469 connsw = rd32(E1000_CONNSW); 5470 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5471 link = 0; 5472 } 5473 } 5474 if (link) { 5475 /* Perform a reset if the media type changed. */ 5476 if (hw->dev_spec._82575.media_changed) { 5477 hw->dev_spec._82575.media_changed = false; 5478 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5479 igb_reset(adapter); 5480 } 5481 /* Cancel scheduled suspend requests. */ 5482 pm_runtime_resume(netdev->dev.parent); 5483 5484 if (!netif_carrier_ok(netdev)) { 5485 u32 ctrl; 5486 5487 hw->mac.ops.get_speed_and_duplex(hw, 5488 &adapter->link_speed, 5489 &adapter->link_duplex); 5490 5491 ctrl = rd32(E1000_CTRL); 5492 /* Links status message must follow this format */ 5493 netdev_info(netdev, 5494 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5495 netdev->name, 5496 adapter->link_speed, 5497 adapter->link_duplex == FULL_DUPLEX ? 5498 "Full" : "Half", 5499 (ctrl & E1000_CTRL_TFCE) && 5500 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5501 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5502 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5503 5504 /* disable EEE if enabled */ 5505 if ((adapter->flags & IGB_FLAG_EEE) && 5506 (adapter->link_duplex == HALF_DUPLEX)) { 5507 dev_info(&adapter->pdev->dev, 5508 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5509 adapter->hw.dev_spec._82575.eee_disable = true; 5510 adapter->flags &= ~IGB_FLAG_EEE; 5511 } 5512 5513 /* check if SmartSpeed worked */ 5514 igb_check_downshift(hw); 5515 if (phy->speed_downgraded) 5516 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5517 5518 /* check for thermal sensor event */ 5519 if (igb_thermal_sensor_event(hw, 5520 E1000_THSTAT_LINK_THROTTLE)) 5521 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5522 5523 /* adjust timeout factor according to speed/duplex */ 5524 adapter->tx_timeout_factor = 1; 5525 switch (adapter->link_speed) { 5526 case SPEED_10: 5527 adapter->tx_timeout_factor = 14; 5528 break; 5529 case SPEED_100: 5530 /* maybe add some timeout factor ? */ 5531 break; 5532 } 5533 5534 if (adapter->link_speed != SPEED_1000 || 5535 !hw->phy.ops.read_reg) 5536 goto no_wait; 5537 5538 /* wait for Remote receiver status OK */ 5539 retry_read_status: 5540 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5541 &phy_data)) { 5542 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5543 retry_count) { 5544 msleep(100); 5545 retry_count--; 5546 goto retry_read_status; 5547 } else if (!retry_count) { 5548 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5549 } 5550 } else { 5551 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5552 } 5553 no_wait: 5554 netif_carrier_on(netdev); 5555 5556 igb_ping_all_vfs(adapter); 5557 igb_check_vf_rate_limit(adapter); 5558 5559 /* link state has changed, schedule phy info update */ 5560 if (!test_bit(__IGB_DOWN, &adapter->state)) 5561 mod_timer(&adapter->phy_info_timer, 5562 round_jiffies(jiffies + 2 * HZ)); 5563 } 5564 } else { 5565 if (netif_carrier_ok(netdev)) { 5566 adapter->link_speed = 0; 5567 adapter->link_duplex = 0; 5568 5569 /* check for thermal sensor event */ 5570 if (igb_thermal_sensor_event(hw, 5571 E1000_THSTAT_PWR_DOWN)) { 5572 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5573 } 5574 5575 /* Links status message must follow this format */ 5576 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5577 netdev->name); 5578 netif_carrier_off(netdev); 5579 5580 igb_ping_all_vfs(adapter); 5581 5582 /* link state has changed, schedule phy info update */ 5583 if (!test_bit(__IGB_DOWN, &adapter->state)) 5584 mod_timer(&adapter->phy_info_timer, 5585 round_jiffies(jiffies + 2 * HZ)); 5586 5587 /* link is down, time to check for alternate media */ 5588 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5589 igb_check_swap_media(adapter); 5590 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5591 schedule_work(&adapter->reset_task); 5592 /* return immediately */ 5593 return; 5594 } 5595 } 5596 pm_schedule_suspend(netdev->dev.parent, 5597 MSEC_PER_SEC * 5); 5598 5599 /* also check for alternate media here */ 5600 } else if (!netif_carrier_ok(netdev) && 5601 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5602 igb_check_swap_media(adapter); 5603 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5604 schedule_work(&adapter->reset_task); 5605 /* return immediately */ 5606 return; 5607 } 5608 } 5609 } 5610 5611 spin_lock(&adapter->stats64_lock); 5612 igb_update_stats(adapter); 5613 spin_unlock(&adapter->stats64_lock); 5614 5615 for (i = 0; i < adapter->num_tx_queues; i++) { 5616 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5617 if (!netif_carrier_ok(netdev)) { 5618 /* We've lost link, so the controller stops DMA, 5619 * but we've got queued Tx work that's never going 5620 * to get done, so reset controller to flush Tx. 5621 * (Do the reset outside of interrupt context). 5622 */ 5623 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5624 adapter->tx_timeout_count++; 5625 schedule_work(&adapter->reset_task); 5626 /* return immediately since reset is imminent */ 5627 return; 5628 } 5629 } 5630 5631 /* Force detection of hung controller every watchdog period */ 5632 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5633 } 5634 5635 /* Cause software interrupt to ensure Rx ring is cleaned */ 5636 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5637 u32 eics = 0; 5638 5639 for (i = 0; i < adapter->num_q_vectors; i++) 5640 eics |= adapter->q_vector[i]->eims_value; 5641 wr32(E1000_EICS, eics); 5642 } else { 5643 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5644 } 5645 5646 igb_spoof_check(adapter); 5647 igb_ptp_rx_hang(adapter); 5648 igb_ptp_tx_hang(adapter); 5649 5650 /* Check LVMMC register on i350/i354 only */ 5651 if ((adapter->hw.mac.type == e1000_i350) || 5652 (adapter->hw.mac.type == e1000_i354)) 5653 igb_check_lvmmc(adapter); 5654 5655 /* Reset the timer */ 5656 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5657 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5658 mod_timer(&adapter->watchdog_timer, 5659 round_jiffies(jiffies + HZ)); 5660 else 5661 mod_timer(&adapter->watchdog_timer, 5662 round_jiffies(jiffies + 2 * HZ)); 5663 } 5664 } 5665 5666 enum latency_range { 5667 lowest_latency = 0, 5668 low_latency = 1, 5669 bulk_latency = 2, 5670 latency_invalid = 255 5671 }; 5672 5673 /** 5674 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5675 * @q_vector: pointer to q_vector 5676 * 5677 * Stores a new ITR value based on strictly on packet size. This 5678 * algorithm is less sophisticated than that used in igb_update_itr, 5679 * due to the difficulty of synchronizing statistics across multiple 5680 * receive rings. The divisors and thresholds used by this function 5681 * were determined based on theoretical maximum wire speed and testing 5682 * data, in order to minimize response time while increasing bulk 5683 * throughput. 5684 * This functionality is controlled by ethtool's coalescing settings. 5685 * NOTE: This function is called only when operating in a multiqueue 5686 * receive environment. 5687 **/ 5688 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5689 { 5690 int new_val = q_vector->itr_val; 5691 int avg_wire_size = 0; 5692 struct igb_adapter *adapter = q_vector->adapter; 5693 unsigned int packets; 5694 5695 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5696 * ints/sec - ITR timer value of 120 ticks. 5697 */ 5698 if (adapter->link_speed != SPEED_1000) { 5699 new_val = IGB_4K_ITR; 5700 goto set_itr_val; 5701 } 5702 5703 packets = q_vector->rx.total_packets; 5704 if (packets) 5705 avg_wire_size = q_vector->rx.total_bytes / packets; 5706 5707 packets = q_vector->tx.total_packets; 5708 if (packets) 5709 avg_wire_size = max_t(u32, avg_wire_size, 5710 q_vector->tx.total_bytes / packets); 5711 5712 /* if avg_wire_size isn't set no work was done */ 5713 if (!avg_wire_size) 5714 goto clear_counts; 5715 5716 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5717 avg_wire_size += 24; 5718 5719 /* Don't starve jumbo frames */ 5720 avg_wire_size = min(avg_wire_size, 3000); 5721 5722 /* Give a little boost to mid-size frames */ 5723 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5724 new_val = avg_wire_size / 3; 5725 else 5726 new_val = avg_wire_size / 2; 5727 5728 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5729 if (new_val < IGB_20K_ITR && 5730 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5731 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5732 new_val = IGB_20K_ITR; 5733 5734 set_itr_val: 5735 if (new_val != q_vector->itr_val) { 5736 q_vector->itr_val = new_val; 5737 q_vector->set_itr = 1; 5738 } 5739 clear_counts: 5740 q_vector->rx.total_bytes = 0; 5741 q_vector->rx.total_packets = 0; 5742 q_vector->tx.total_bytes = 0; 5743 q_vector->tx.total_packets = 0; 5744 } 5745 5746 /** 5747 * igb_update_itr - update the dynamic ITR value based on statistics 5748 * @q_vector: pointer to q_vector 5749 * @ring_container: ring info to update the itr for 5750 * 5751 * Stores a new ITR value based on packets and byte 5752 * counts during the last interrupt. The advantage of per interrupt 5753 * computation is faster updates and more accurate ITR for the current 5754 * traffic pattern. Constants in this function were computed 5755 * based on theoretical maximum wire speed and thresholds were set based 5756 * on testing data as well as attempting to minimize response time 5757 * while increasing bulk throughput. 5758 * This functionality is controlled by ethtool's coalescing settings. 5759 * NOTE: These calculations are only valid when operating in a single- 5760 * queue environment. 5761 **/ 5762 static void igb_update_itr(struct igb_q_vector *q_vector, 5763 struct igb_ring_container *ring_container) 5764 { 5765 unsigned int packets = ring_container->total_packets; 5766 unsigned int bytes = ring_container->total_bytes; 5767 u8 itrval = ring_container->itr; 5768 5769 /* no packets, exit with status unchanged */ 5770 if (packets == 0) 5771 return; 5772 5773 switch (itrval) { 5774 case lowest_latency: 5775 /* handle TSO and jumbo frames */ 5776 if (bytes/packets > 8000) 5777 itrval = bulk_latency; 5778 else if ((packets < 5) && (bytes > 512)) 5779 itrval = low_latency; 5780 break; 5781 case low_latency: /* 50 usec aka 20000 ints/s */ 5782 if (bytes > 10000) { 5783 /* this if handles the TSO accounting */ 5784 if (bytes/packets > 8000) 5785 itrval = bulk_latency; 5786 else if ((packets < 10) || ((bytes/packets) > 1200)) 5787 itrval = bulk_latency; 5788 else if ((packets > 35)) 5789 itrval = lowest_latency; 5790 } else if (bytes/packets > 2000) { 5791 itrval = bulk_latency; 5792 } else if (packets <= 2 && bytes < 512) { 5793 itrval = lowest_latency; 5794 } 5795 break; 5796 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5797 if (bytes > 25000) { 5798 if (packets > 35) 5799 itrval = low_latency; 5800 } else if (bytes < 1500) { 5801 itrval = low_latency; 5802 } 5803 break; 5804 } 5805 5806 /* clear work counters since we have the values we need */ 5807 ring_container->total_bytes = 0; 5808 ring_container->total_packets = 0; 5809 5810 /* write updated itr to ring container */ 5811 ring_container->itr = itrval; 5812 } 5813 5814 static void igb_set_itr(struct igb_q_vector *q_vector) 5815 { 5816 struct igb_adapter *adapter = q_vector->adapter; 5817 u32 new_itr = q_vector->itr_val; 5818 u8 current_itr = 0; 5819 5820 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5821 if (adapter->link_speed != SPEED_1000) { 5822 current_itr = 0; 5823 new_itr = IGB_4K_ITR; 5824 goto set_itr_now; 5825 } 5826 5827 igb_update_itr(q_vector, &q_vector->tx); 5828 igb_update_itr(q_vector, &q_vector->rx); 5829 5830 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5831 5832 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5833 if (current_itr == lowest_latency && 5834 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5835 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5836 current_itr = low_latency; 5837 5838 switch (current_itr) { 5839 /* counts and packets in update_itr are dependent on these numbers */ 5840 case lowest_latency: 5841 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5842 break; 5843 case low_latency: 5844 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5845 break; 5846 case bulk_latency: 5847 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5848 break; 5849 default: 5850 break; 5851 } 5852 5853 set_itr_now: 5854 if (new_itr != q_vector->itr_val) { 5855 /* this attempts to bias the interrupt rate towards Bulk 5856 * by adding intermediate steps when interrupt rate is 5857 * increasing 5858 */ 5859 new_itr = new_itr > q_vector->itr_val ? 5860 max((new_itr * q_vector->itr_val) / 5861 (new_itr + (q_vector->itr_val >> 2)), 5862 new_itr) : new_itr; 5863 /* Don't write the value here; it resets the adapter's 5864 * internal timer, and causes us to delay far longer than 5865 * we should between interrupts. Instead, we write the ITR 5866 * value at the beginning of the next interrupt so the timing 5867 * ends up being correct. 5868 */ 5869 q_vector->itr_val = new_itr; 5870 q_vector->set_itr = 1; 5871 } 5872 } 5873 5874 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 5875 struct igb_tx_buffer *first, 5876 u32 vlan_macip_lens, u32 type_tucmd, 5877 u32 mss_l4len_idx) 5878 { 5879 struct e1000_adv_tx_context_desc *context_desc; 5880 u16 i = tx_ring->next_to_use; 5881 struct timespec64 ts; 5882 5883 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5884 5885 i++; 5886 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 5887 5888 /* set bits to identify this as an advanced context descriptor */ 5889 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 5890 5891 /* For 82575, context index must be unique per ring. */ 5892 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5893 mss_l4len_idx |= tx_ring->reg_idx << 4; 5894 5895 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5896 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5897 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5898 5899 /* We assume there is always a valid tx time available. Invalid times 5900 * should have been handled by the upper layers. 5901 */ 5902 if (tx_ring->launchtime_enable) { 5903 ts = ktime_to_timespec64(first->skb->tstamp); 5904 skb_txtime_consumed(first->skb); 5905 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 5906 } else { 5907 context_desc->seqnum_seed = 0; 5908 } 5909 } 5910 5911 static int igb_tso(struct igb_ring *tx_ring, 5912 struct igb_tx_buffer *first, 5913 u8 *hdr_len) 5914 { 5915 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 5916 struct sk_buff *skb = first->skb; 5917 union { 5918 struct iphdr *v4; 5919 struct ipv6hdr *v6; 5920 unsigned char *hdr; 5921 } ip; 5922 union { 5923 struct tcphdr *tcp; 5924 struct udphdr *udp; 5925 unsigned char *hdr; 5926 } l4; 5927 u32 paylen, l4_offset; 5928 int err; 5929 5930 if (skb->ip_summed != CHECKSUM_PARTIAL) 5931 return 0; 5932 5933 if (!skb_is_gso(skb)) 5934 return 0; 5935 5936 err = skb_cow_head(skb, 0); 5937 if (err < 0) 5938 return err; 5939 5940 ip.hdr = skb_network_header(skb); 5941 l4.hdr = skb_checksum_start(skb); 5942 5943 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 5944 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 5945 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP; 5946 5947 /* initialize outer IP header fields */ 5948 if (ip.v4->version == 4) { 5949 unsigned char *csum_start = skb_checksum_start(skb); 5950 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 5951 5952 /* IP header will have to cancel out any data that 5953 * is not a part of the outer IP header 5954 */ 5955 ip.v4->check = csum_fold(csum_partial(trans_start, 5956 csum_start - trans_start, 5957 0)); 5958 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 5959 5960 ip.v4->tot_len = 0; 5961 first->tx_flags |= IGB_TX_FLAGS_TSO | 5962 IGB_TX_FLAGS_CSUM | 5963 IGB_TX_FLAGS_IPV4; 5964 } else { 5965 ip.v6->payload_len = 0; 5966 first->tx_flags |= IGB_TX_FLAGS_TSO | 5967 IGB_TX_FLAGS_CSUM; 5968 } 5969 5970 /* determine offset of inner transport header */ 5971 l4_offset = l4.hdr - skb->data; 5972 5973 /* remove payload length from inner checksum */ 5974 paylen = skb->len - l4_offset; 5975 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) { 5976 /* compute length of segmentation header */ 5977 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 5978 csum_replace_by_diff(&l4.tcp->check, 5979 (__force __wsum)htonl(paylen)); 5980 } else { 5981 /* compute length of segmentation header */ 5982 *hdr_len = sizeof(*l4.udp) + l4_offset; 5983 csum_replace_by_diff(&l4.udp->check, 5984 (__force __wsum)htonl(paylen)); 5985 } 5986 5987 /* update gso size and bytecount with header size */ 5988 first->gso_segs = skb_shinfo(skb)->gso_segs; 5989 first->bytecount += (first->gso_segs - 1) * *hdr_len; 5990 5991 /* MSS L4LEN IDX */ 5992 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 5993 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 5994 5995 /* VLAN MACLEN IPLEN */ 5996 vlan_macip_lens = l4.hdr - ip.hdr; 5997 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 5998 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5999 6000 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 6001 type_tucmd, mss_l4len_idx); 6002 6003 return 1; 6004 } 6005 6006 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 6007 { 6008 struct sk_buff *skb = first->skb; 6009 u32 vlan_macip_lens = 0; 6010 u32 type_tucmd = 0; 6011 6012 if (skb->ip_summed != CHECKSUM_PARTIAL) { 6013 csum_failed: 6014 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 6015 !tx_ring->launchtime_enable) 6016 return; 6017 goto no_csum; 6018 } 6019 6020 switch (skb->csum_offset) { 6021 case offsetof(struct tcphdr, check): 6022 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 6023 fallthrough; 6024 case offsetof(struct udphdr, check): 6025 break; 6026 case offsetof(struct sctphdr, checksum): 6027 /* validate that this is actually an SCTP request */ 6028 if (skb_csum_is_sctp(skb)) { 6029 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 6030 break; 6031 } 6032 fallthrough; 6033 default: 6034 skb_checksum_help(skb); 6035 goto csum_failed; 6036 } 6037 6038 /* update TX checksum flag */ 6039 first->tx_flags |= IGB_TX_FLAGS_CSUM; 6040 vlan_macip_lens = skb_checksum_start_offset(skb) - 6041 skb_network_offset(skb); 6042 no_csum: 6043 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 6044 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6045 6046 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 6047 } 6048 6049 #define IGB_SET_FLAG(_input, _flag, _result) \ 6050 ((_flag <= _result) ? \ 6051 ((u32)(_input & _flag) * (_result / _flag)) : \ 6052 ((u32)(_input & _flag) / (_flag / _result))) 6053 6054 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6055 { 6056 /* set type for advanced descriptor with frame checksum insertion */ 6057 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 6058 E1000_ADVTXD_DCMD_DEXT | 6059 E1000_ADVTXD_DCMD_IFCS; 6060 6061 /* set HW vlan bit if vlan is present */ 6062 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 6063 (E1000_ADVTXD_DCMD_VLE)); 6064 6065 /* set segmentation bits for TSO */ 6066 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 6067 (E1000_ADVTXD_DCMD_TSE)); 6068 6069 /* set timestamp bit if present */ 6070 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 6071 (E1000_ADVTXD_MAC_TSTAMP)); 6072 6073 /* insert frame checksum */ 6074 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 6075 6076 return cmd_type; 6077 } 6078 6079 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 6080 union e1000_adv_tx_desc *tx_desc, 6081 u32 tx_flags, unsigned int paylen) 6082 { 6083 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 6084 6085 /* 82575 requires a unique index per ring */ 6086 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6087 olinfo_status |= tx_ring->reg_idx << 4; 6088 6089 /* insert L4 checksum */ 6090 olinfo_status |= IGB_SET_FLAG(tx_flags, 6091 IGB_TX_FLAGS_CSUM, 6092 (E1000_TXD_POPTS_TXSM << 8)); 6093 6094 /* insert IPv4 checksum */ 6095 olinfo_status |= IGB_SET_FLAG(tx_flags, 6096 IGB_TX_FLAGS_IPV4, 6097 (E1000_TXD_POPTS_IXSM << 8)); 6098 6099 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6100 } 6101 6102 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6103 { 6104 struct net_device *netdev = tx_ring->netdev; 6105 6106 netif_stop_subqueue(netdev, tx_ring->queue_index); 6107 6108 /* Herbert's original patch had: 6109 * smp_mb__after_netif_stop_queue(); 6110 * but since that doesn't exist yet, just open code it. 6111 */ 6112 smp_mb(); 6113 6114 /* We need to check again in a case another CPU has just 6115 * made room available. 6116 */ 6117 if (igb_desc_unused(tx_ring) < size) 6118 return -EBUSY; 6119 6120 /* A reprieve! */ 6121 netif_wake_subqueue(netdev, tx_ring->queue_index); 6122 6123 u64_stats_update_begin(&tx_ring->tx_syncp2); 6124 tx_ring->tx_stats.restart_queue2++; 6125 u64_stats_update_end(&tx_ring->tx_syncp2); 6126 6127 return 0; 6128 } 6129 6130 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6131 { 6132 if (igb_desc_unused(tx_ring) >= size) 6133 return 0; 6134 return __igb_maybe_stop_tx(tx_ring, size); 6135 } 6136 6137 static int igb_tx_map(struct igb_ring *tx_ring, 6138 struct igb_tx_buffer *first, 6139 const u8 hdr_len) 6140 { 6141 struct sk_buff *skb = first->skb; 6142 struct igb_tx_buffer *tx_buffer; 6143 union e1000_adv_tx_desc *tx_desc; 6144 skb_frag_t *frag; 6145 dma_addr_t dma; 6146 unsigned int data_len, size; 6147 u32 tx_flags = first->tx_flags; 6148 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 6149 u16 i = tx_ring->next_to_use; 6150 6151 tx_desc = IGB_TX_DESC(tx_ring, i); 6152 6153 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 6154 6155 size = skb_headlen(skb); 6156 data_len = skb->data_len; 6157 6158 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6159 6160 tx_buffer = first; 6161 6162 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6163 if (dma_mapping_error(tx_ring->dev, dma)) 6164 goto dma_error; 6165 6166 /* record length, and DMA address */ 6167 dma_unmap_len_set(tx_buffer, len, size); 6168 dma_unmap_addr_set(tx_buffer, dma, dma); 6169 6170 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6171 6172 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 6173 tx_desc->read.cmd_type_len = 6174 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 6175 6176 i++; 6177 tx_desc++; 6178 if (i == tx_ring->count) { 6179 tx_desc = IGB_TX_DESC(tx_ring, 0); 6180 i = 0; 6181 } 6182 tx_desc->read.olinfo_status = 0; 6183 6184 dma += IGB_MAX_DATA_PER_TXD; 6185 size -= IGB_MAX_DATA_PER_TXD; 6186 6187 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6188 } 6189 6190 if (likely(!data_len)) 6191 break; 6192 6193 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6194 6195 i++; 6196 tx_desc++; 6197 if (i == tx_ring->count) { 6198 tx_desc = IGB_TX_DESC(tx_ring, 0); 6199 i = 0; 6200 } 6201 tx_desc->read.olinfo_status = 0; 6202 6203 size = skb_frag_size(frag); 6204 data_len -= size; 6205 6206 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6207 size, DMA_TO_DEVICE); 6208 6209 tx_buffer = &tx_ring->tx_buffer_info[i]; 6210 } 6211 6212 /* write last descriptor with RS and EOP bits */ 6213 cmd_type |= size | IGB_TXD_DCMD; 6214 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6215 6216 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6217 6218 /* set the timestamp */ 6219 first->time_stamp = jiffies; 6220 6221 skb_tx_timestamp(skb); 6222 6223 /* Force memory writes to complete before letting h/w know there 6224 * are new descriptors to fetch. (Only applicable for weak-ordered 6225 * memory model archs, such as IA-64). 6226 * 6227 * We also need this memory barrier to make certain all of the 6228 * status bits have been updated before next_to_watch is written. 6229 */ 6230 dma_wmb(); 6231 6232 /* set next_to_watch value indicating a packet is present */ 6233 first->next_to_watch = tx_desc; 6234 6235 i++; 6236 if (i == tx_ring->count) 6237 i = 0; 6238 6239 tx_ring->next_to_use = i; 6240 6241 /* Make sure there is space in the ring for the next send. */ 6242 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6243 6244 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6245 writel(i, tx_ring->tail); 6246 } 6247 return 0; 6248 6249 dma_error: 6250 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6251 tx_buffer = &tx_ring->tx_buffer_info[i]; 6252 6253 /* clear dma mappings for failed tx_buffer_info map */ 6254 while (tx_buffer != first) { 6255 if (dma_unmap_len(tx_buffer, len)) 6256 dma_unmap_page(tx_ring->dev, 6257 dma_unmap_addr(tx_buffer, dma), 6258 dma_unmap_len(tx_buffer, len), 6259 DMA_TO_DEVICE); 6260 dma_unmap_len_set(tx_buffer, len, 0); 6261 6262 if (i-- == 0) 6263 i += tx_ring->count; 6264 tx_buffer = &tx_ring->tx_buffer_info[i]; 6265 } 6266 6267 if (dma_unmap_len(tx_buffer, len)) 6268 dma_unmap_single(tx_ring->dev, 6269 dma_unmap_addr(tx_buffer, dma), 6270 dma_unmap_len(tx_buffer, len), 6271 DMA_TO_DEVICE); 6272 dma_unmap_len_set(tx_buffer, len, 0); 6273 6274 dev_kfree_skb_any(tx_buffer->skb); 6275 tx_buffer->skb = NULL; 6276 6277 tx_ring->next_to_use = i; 6278 6279 return -1; 6280 } 6281 6282 int igb_xmit_xdp_ring(struct igb_adapter *adapter, 6283 struct igb_ring *tx_ring, 6284 struct xdp_frame *xdpf) 6285 { 6286 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 6287 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 6288 u16 count, i, index = tx_ring->next_to_use; 6289 struct igb_tx_buffer *tx_head = &tx_ring->tx_buffer_info[index]; 6290 struct igb_tx_buffer *tx_buffer = tx_head; 6291 union e1000_adv_tx_desc *tx_desc = IGB_TX_DESC(tx_ring, index); 6292 u32 len = xdpf->len, cmd_type, olinfo_status; 6293 void *data = xdpf->data; 6294 6295 count = TXD_USE_COUNT(len); 6296 for (i = 0; i < nr_frags; i++) 6297 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i])); 6298 6299 if (igb_maybe_stop_tx(tx_ring, count + 3)) 6300 return IGB_XDP_CONSUMED; 6301 6302 i = 0; 6303 /* record the location of the first descriptor for this packet */ 6304 tx_head->bytecount = xdp_get_frame_len(xdpf); 6305 tx_head->type = IGB_TYPE_XDP; 6306 tx_head->gso_segs = 1; 6307 tx_head->xdpf = xdpf; 6308 6309 olinfo_status = tx_head->bytecount << E1000_ADVTXD_PAYLEN_SHIFT; 6310 /* 82575 requires a unique index per ring */ 6311 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6312 olinfo_status |= tx_ring->reg_idx << 4; 6313 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6314 6315 for (;;) { 6316 dma_addr_t dma; 6317 6318 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE); 6319 if (dma_mapping_error(tx_ring->dev, dma)) 6320 goto unmap; 6321 6322 /* record length, and DMA address */ 6323 dma_unmap_len_set(tx_buffer, len, len); 6324 dma_unmap_addr_set(tx_buffer, dma, dma); 6325 6326 /* put descriptor type bits */ 6327 cmd_type = E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_DEXT | 6328 E1000_ADVTXD_DCMD_IFCS | len; 6329 6330 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6331 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6332 6333 tx_buffer->protocol = 0; 6334 6335 if (++index == tx_ring->count) 6336 index = 0; 6337 6338 if (i == nr_frags) 6339 break; 6340 6341 tx_buffer = &tx_ring->tx_buffer_info[index]; 6342 tx_desc = IGB_TX_DESC(tx_ring, index); 6343 tx_desc->read.olinfo_status = 0; 6344 6345 data = skb_frag_address(&sinfo->frags[i]); 6346 len = skb_frag_size(&sinfo->frags[i]); 6347 i++; 6348 } 6349 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_TXD_DCMD); 6350 6351 netdev_tx_sent_queue(txring_txq(tx_ring), tx_head->bytecount); 6352 /* set the timestamp */ 6353 tx_head->time_stamp = jiffies; 6354 6355 /* Avoid any potential race with xdp_xmit and cleanup */ 6356 smp_wmb(); 6357 6358 /* set next_to_watch value indicating a packet is present */ 6359 tx_head->next_to_watch = tx_desc; 6360 tx_ring->next_to_use = index; 6361 6362 /* Make sure there is space in the ring for the next send. */ 6363 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6364 6365 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) 6366 writel(index, tx_ring->tail); 6367 6368 return IGB_XDP_TX; 6369 6370 unmap: 6371 for (;;) { 6372 tx_buffer = &tx_ring->tx_buffer_info[index]; 6373 if (dma_unmap_len(tx_buffer, len)) 6374 dma_unmap_page(tx_ring->dev, 6375 dma_unmap_addr(tx_buffer, dma), 6376 dma_unmap_len(tx_buffer, len), 6377 DMA_TO_DEVICE); 6378 dma_unmap_len_set(tx_buffer, len, 0); 6379 if (tx_buffer == tx_head) 6380 break; 6381 6382 if (!index) 6383 index += tx_ring->count; 6384 index--; 6385 } 6386 6387 return IGB_XDP_CONSUMED; 6388 } 6389 6390 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6391 struct igb_ring *tx_ring) 6392 { 6393 struct igb_tx_buffer *first; 6394 int tso; 6395 u32 tx_flags = 0; 6396 unsigned short f; 6397 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6398 __be16 protocol = vlan_get_protocol(skb); 6399 u8 hdr_len = 0; 6400 6401 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6402 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6403 * + 2 desc gap to keep tail from touching head, 6404 * + 1 desc for context descriptor, 6405 * otherwise try next time 6406 */ 6407 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6408 count += TXD_USE_COUNT(skb_frag_size( 6409 &skb_shinfo(skb)->frags[f])); 6410 6411 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6412 /* this is a hard error */ 6413 return NETDEV_TX_BUSY; 6414 } 6415 6416 /* record the location of the first descriptor for this packet */ 6417 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6418 first->type = IGB_TYPE_SKB; 6419 first->skb = skb; 6420 first->bytecount = skb->len; 6421 first->gso_segs = 1; 6422 6423 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6424 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6425 6426 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6427 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6428 &adapter->state)) { 6429 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6430 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6431 6432 adapter->ptp_tx_skb = skb_get(skb); 6433 adapter->ptp_tx_start = jiffies; 6434 if (adapter->hw.mac.type == e1000_82576) 6435 schedule_work(&adapter->ptp_tx_work); 6436 } else { 6437 adapter->tx_hwtstamp_skipped++; 6438 } 6439 } 6440 6441 if (skb_vlan_tag_present(skb)) { 6442 tx_flags |= IGB_TX_FLAGS_VLAN; 6443 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6444 } 6445 6446 /* record initial flags and protocol */ 6447 first->tx_flags = tx_flags; 6448 first->protocol = protocol; 6449 6450 tso = igb_tso(tx_ring, first, &hdr_len); 6451 if (tso < 0) 6452 goto out_drop; 6453 else if (!tso) 6454 igb_tx_csum(tx_ring, first); 6455 6456 if (igb_tx_map(tx_ring, first, hdr_len)) 6457 goto cleanup_tx_tstamp; 6458 6459 return NETDEV_TX_OK; 6460 6461 out_drop: 6462 dev_kfree_skb_any(first->skb); 6463 first->skb = NULL; 6464 cleanup_tx_tstamp: 6465 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6466 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6467 6468 dev_kfree_skb_any(adapter->ptp_tx_skb); 6469 adapter->ptp_tx_skb = NULL; 6470 if (adapter->hw.mac.type == e1000_82576) 6471 cancel_work_sync(&adapter->ptp_tx_work); 6472 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6473 } 6474 6475 return NETDEV_TX_OK; 6476 } 6477 6478 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6479 struct sk_buff *skb) 6480 { 6481 unsigned int r_idx = skb->queue_mapping; 6482 6483 if (r_idx >= adapter->num_tx_queues) 6484 r_idx = r_idx % adapter->num_tx_queues; 6485 6486 return adapter->tx_ring[r_idx]; 6487 } 6488 6489 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6490 struct net_device *netdev) 6491 { 6492 struct igb_adapter *adapter = netdev_priv(netdev); 6493 6494 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6495 * in order to meet this minimum size requirement. 6496 */ 6497 if (skb_put_padto(skb, 17)) 6498 return NETDEV_TX_OK; 6499 6500 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6501 } 6502 6503 /** 6504 * igb_tx_timeout - Respond to a Tx Hang 6505 * @netdev: network interface device structure 6506 * @txqueue: number of the Tx queue that hung (unused) 6507 **/ 6508 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6509 { 6510 struct igb_adapter *adapter = netdev_priv(netdev); 6511 struct e1000_hw *hw = &adapter->hw; 6512 6513 /* Do the reset outside of interrupt context */ 6514 adapter->tx_timeout_count++; 6515 6516 if (hw->mac.type >= e1000_82580) 6517 hw->dev_spec._82575.global_device_reset = true; 6518 6519 schedule_work(&adapter->reset_task); 6520 wr32(E1000_EICS, 6521 (adapter->eims_enable_mask & ~adapter->eims_other)); 6522 } 6523 6524 static void igb_reset_task(struct work_struct *work) 6525 { 6526 struct igb_adapter *adapter; 6527 adapter = container_of(work, struct igb_adapter, reset_task); 6528 6529 rtnl_lock(); 6530 /* If we're already down or resetting, just bail */ 6531 if (test_bit(__IGB_DOWN, &adapter->state) || 6532 test_bit(__IGB_RESETTING, &adapter->state)) { 6533 rtnl_unlock(); 6534 return; 6535 } 6536 6537 igb_dump(adapter); 6538 netdev_err(adapter->netdev, "Reset adapter\n"); 6539 igb_reinit_locked(adapter); 6540 rtnl_unlock(); 6541 } 6542 6543 /** 6544 * igb_get_stats64 - Get System Network Statistics 6545 * @netdev: network interface device structure 6546 * @stats: rtnl_link_stats64 pointer 6547 **/ 6548 static void igb_get_stats64(struct net_device *netdev, 6549 struct rtnl_link_stats64 *stats) 6550 { 6551 struct igb_adapter *adapter = netdev_priv(netdev); 6552 6553 spin_lock(&adapter->stats64_lock); 6554 igb_update_stats(adapter); 6555 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6556 spin_unlock(&adapter->stats64_lock); 6557 } 6558 6559 /** 6560 * igb_change_mtu - Change the Maximum Transfer Unit 6561 * @netdev: network interface device structure 6562 * @new_mtu: new value for maximum frame size 6563 * 6564 * Returns 0 on success, negative on failure 6565 **/ 6566 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6567 { 6568 struct igb_adapter *adapter = netdev_priv(netdev); 6569 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD; 6570 6571 if (adapter->xdp_prog) { 6572 int i; 6573 6574 for (i = 0; i < adapter->num_rx_queues; i++) { 6575 struct igb_ring *ring = adapter->rx_ring[i]; 6576 6577 if (max_frame > igb_rx_bufsz(ring)) { 6578 netdev_warn(adapter->netdev, 6579 "Requested MTU size is not supported with XDP. Max frame size is %d\n", 6580 max_frame); 6581 return -EINVAL; 6582 } 6583 } 6584 } 6585 6586 /* adjust max frame to be at least the size of a standard frame */ 6587 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6588 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6589 6590 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6591 usleep_range(1000, 2000); 6592 6593 /* igb_down has a dependency on max_frame_size */ 6594 adapter->max_frame_size = max_frame; 6595 6596 if (netif_running(netdev)) 6597 igb_down(adapter); 6598 6599 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6600 netdev->mtu, new_mtu); 6601 netdev->mtu = new_mtu; 6602 6603 if (netif_running(netdev)) 6604 igb_up(adapter); 6605 else 6606 igb_reset(adapter); 6607 6608 clear_bit(__IGB_RESETTING, &adapter->state); 6609 6610 return 0; 6611 } 6612 6613 /** 6614 * igb_update_stats - Update the board statistics counters 6615 * @adapter: board private structure 6616 **/ 6617 void igb_update_stats(struct igb_adapter *adapter) 6618 { 6619 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6620 struct e1000_hw *hw = &adapter->hw; 6621 struct pci_dev *pdev = adapter->pdev; 6622 u32 reg, mpc; 6623 int i; 6624 u64 bytes, packets; 6625 unsigned int start; 6626 u64 _bytes, _packets; 6627 6628 /* Prevent stats update while adapter is being reset, or if the pci 6629 * connection is down. 6630 */ 6631 if (adapter->link_speed == 0) 6632 return; 6633 if (pci_channel_offline(pdev)) 6634 return; 6635 6636 bytes = 0; 6637 packets = 0; 6638 6639 rcu_read_lock(); 6640 for (i = 0; i < adapter->num_rx_queues; i++) { 6641 struct igb_ring *ring = adapter->rx_ring[i]; 6642 u32 rqdpc = rd32(E1000_RQDPC(i)); 6643 if (hw->mac.type >= e1000_i210) 6644 wr32(E1000_RQDPC(i), 0); 6645 6646 if (rqdpc) { 6647 ring->rx_stats.drops += rqdpc; 6648 net_stats->rx_fifo_errors += rqdpc; 6649 } 6650 6651 do { 6652 start = u64_stats_fetch_begin(&ring->rx_syncp); 6653 _bytes = ring->rx_stats.bytes; 6654 _packets = ring->rx_stats.packets; 6655 } while (u64_stats_fetch_retry(&ring->rx_syncp, start)); 6656 bytes += _bytes; 6657 packets += _packets; 6658 } 6659 6660 net_stats->rx_bytes = bytes; 6661 net_stats->rx_packets = packets; 6662 6663 bytes = 0; 6664 packets = 0; 6665 for (i = 0; i < adapter->num_tx_queues; i++) { 6666 struct igb_ring *ring = adapter->tx_ring[i]; 6667 do { 6668 start = u64_stats_fetch_begin(&ring->tx_syncp); 6669 _bytes = ring->tx_stats.bytes; 6670 _packets = ring->tx_stats.packets; 6671 } while (u64_stats_fetch_retry(&ring->tx_syncp, start)); 6672 bytes += _bytes; 6673 packets += _packets; 6674 } 6675 net_stats->tx_bytes = bytes; 6676 net_stats->tx_packets = packets; 6677 rcu_read_unlock(); 6678 6679 /* read stats registers */ 6680 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6681 adapter->stats.gprc += rd32(E1000_GPRC); 6682 adapter->stats.gorc += rd32(E1000_GORCL); 6683 rd32(E1000_GORCH); /* clear GORCL */ 6684 adapter->stats.bprc += rd32(E1000_BPRC); 6685 adapter->stats.mprc += rd32(E1000_MPRC); 6686 adapter->stats.roc += rd32(E1000_ROC); 6687 6688 adapter->stats.prc64 += rd32(E1000_PRC64); 6689 adapter->stats.prc127 += rd32(E1000_PRC127); 6690 adapter->stats.prc255 += rd32(E1000_PRC255); 6691 adapter->stats.prc511 += rd32(E1000_PRC511); 6692 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6693 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6694 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6695 adapter->stats.sec += rd32(E1000_SEC); 6696 6697 mpc = rd32(E1000_MPC); 6698 adapter->stats.mpc += mpc; 6699 net_stats->rx_fifo_errors += mpc; 6700 adapter->stats.scc += rd32(E1000_SCC); 6701 adapter->stats.ecol += rd32(E1000_ECOL); 6702 adapter->stats.mcc += rd32(E1000_MCC); 6703 adapter->stats.latecol += rd32(E1000_LATECOL); 6704 adapter->stats.dc += rd32(E1000_DC); 6705 adapter->stats.rlec += rd32(E1000_RLEC); 6706 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6707 adapter->stats.xontxc += rd32(E1000_XONTXC); 6708 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6709 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6710 adapter->stats.fcruc += rd32(E1000_FCRUC); 6711 adapter->stats.gptc += rd32(E1000_GPTC); 6712 adapter->stats.gotc += rd32(E1000_GOTCL); 6713 rd32(E1000_GOTCH); /* clear GOTCL */ 6714 adapter->stats.rnbc += rd32(E1000_RNBC); 6715 adapter->stats.ruc += rd32(E1000_RUC); 6716 adapter->stats.rfc += rd32(E1000_RFC); 6717 adapter->stats.rjc += rd32(E1000_RJC); 6718 adapter->stats.tor += rd32(E1000_TORH); 6719 adapter->stats.tot += rd32(E1000_TOTH); 6720 adapter->stats.tpr += rd32(E1000_TPR); 6721 6722 adapter->stats.ptc64 += rd32(E1000_PTC64); 6723 adapter->stats.ptc127 += rd32(E1000_PTC127); 6724 adapter->stats.ptc255 += rd32(E1000_PTC255); 6725 adapter->stats.ptc511 += rd32(E1000_PTC511); 6726 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6727 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6728 6729 adapter->stats.mptc += rd32(E1000_MPTC); 6730 adapter->stats.bptc += rd32(E1000_BPTC); 6731 6732 adapter->stats.tpt += rd32(E1000_TPT); 6733 adapter->stats.colc += rd32(E1000_COLC); 6734 6735 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6736 /* read internal phy specific stats */ 6737 reg = rd32(E1000_CTRL_EXT); 6738 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6739 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6740 6741 /* this stat has invalid values on i210/i211 */ 6742 if ((hw->mac.type != e1000_i210) && 6743 (hw->mac.type != e1000_i211)) 6744 adapter->stats.tncrs += rd32(E1000_TNCRS); 6745 } 6746 6747 adapter->stats.tsctc += rd32(E1000_TSCTC); 6748 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6749 6750 adapter->stats.iac += rd32(E1000_IAC); 6751 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6752 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6753 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6754 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6755 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6756 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6757 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6758 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6759 6760 /* Fill out the OS statistics structure */ 6761 net_stats->multicast = adapter->stats.mprc; 6762 net_stats->collisions = adapter->stats.colc; 6763 6764 /* Rx Errors */ 6765 6766 /* RLEC on some newer hardware can be incorrect so build 6767 * our own version based on RUC and ROC 6768 */ 6769 net_stats->rx_errors = adapter->stats.rxerrc + 6770 adapter->stats.crcerrs + adapter->stats.algnerrc + 6771 adapter->stats.ruc + adapter->stats.roc + 6772 adapter->stats.cexterr; 6773 net_stats->rx_length_errors = adapter->stats.ruc + 6774 adapter->stats.roc; 6775 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6776 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6777 net_stats->rx_missed_errors = adapter->stats.mpc; 6778 6779 /* Tx Errors */ 6780 net_stats->tx_errors = adapter->stats.ecol + 6781 adapter->stats.latecol; 6782 net_stats->tx_aborted_errors = adapter->stats.ecol; 6783 net_stats->tx_window_errors = adapter->stats.latecol; 6784 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6785 6786 /* Tx Dropped needs to be maintained elsewhere */ 6787 6788 /* Management Stats */ 6789 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6790 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6791 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6792 6793 /* OS2BMC Stats */ 6794 reg = rd32(E1000_MANC); 6795 if (reg & E1000_MANC_EN_BMC2OS) { 6796 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6797 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6798 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6799 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6800 } 6801 } 6802 6803 static void igb_perout(struct igb_adapter *adapter, int tsintr_tt) 6804 { 6805 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_PEROUT, tsintr_tt); 6806 struct e1000_hw *hw = &adapter->hw; 6807 struct timespec64 ts; 6808 u32 tsauxc; 6809 6810 if (pin < 0 || pin >= IGB_N_PEROUT) 6811 return; 6812 6813 spin_lock(&adapter->tmreg_lock); 6814 6815 if (hw->mac.type == e1000_82580 || 6816 hw->mac.type == e1000_i354 || 6817 hw->mac.type == e1000_i350) { 6818 s64 ns = timespec64_to_ns(&adapter->perout[pin].period); 6819 u32 systiml, systimh, level_mask, level, rem; 6820 u64 systim, now; 6821 6822 /* read systim registers in sequence */ 6823 rd32(E1000_SYSTIMR); 6824 systiml = rd32(E1000_SYSTIML); 6825 systimh = rd32(E1000_SYSTIMH); 6826 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml); 6827 now = timecounter_cyc2time(&adapter->tc, systim); 6828 6829 if (pin < 2) { 6830 level_mask = (tsintr_tt == 1) ? 0x80000 : 0x40000; 6831 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0; 6832 } else { 6833 level_mask = (tsintr_tt == 1) ? 0x80 : 0x40; 6834 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0; 6835 } 6836 6837 div_u64_rem(now, ns, &rem); 6838 systim = systim + (ns - rem); 6839 6840 /* synchronize pin level with rising/falling edges */ 6841 div_u64_rem(now, ns << 1, &rem); 6842 if (rem < ns) { 6843 /* first half of period */ 6844 if (level == 0) { 6845 /* output is already low, skip this period */ 6846 systim += ns; 6847 pr_notice("igb: periodic output on %s missed falling edge\n", 6848 adapter->sdp_config[pin].name); 6849 } 6850 } else { 6851 /* second half of period */ 6852 if (level == 1) { 6853 /* output is already high, skip this period */ 6854 systim += ns; 6855 pr_notice("igb: periodic output on %s missed rising edge\n", 6856 adapter->sdp_config[pin].name); 6857 } 6858 } 6859 6860 /* for this chip family tv_sec is the upper part of the binary value, 6861 * so not seconds 6862 */ 6863 ts.tv_nsec = (u32)systim; 6864 ts.tv_sec = ((u32)(systim >> 32)) & 0xFF; 6865 } else { 6866 ts = timespec64_add(adapter->perout[pin].start, 6867 adapter->perout[pin].period); 6868 } 6869 6870 /* u32 conversion of tv_sec is safe until y2106 */ 6871 wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec); 6872 wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec); 6873 tsauxc = rd32(E1000_TSAUXC); 6874 tsauxc |= TSAUXC_EN_TT0; 6875 wr32(E1000_TSAUXC, tsauxc); 6876 adapter->perout[pin].start = ts; 6877 6878 spin_unlock(&adapter->tmreg_lock); 6879 } 6880 6881 static void igb_extts(struct igb_adapter *adapter, int tsintr_tt) 6882 { 6883 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_EXTTS, tsintr_tt); 6884 int auxstmpl = (tsintr_tt == 1) ? E1000_AUXSTMPL1 : E1000_AUXSTMPL0; 6885 int auxstmph = (tsintr_tt == 1) ? E1000_AUXSTMPH1 : E1000_AUXSTMPH0; 6886 struct e1000_hw *hw = &adapter->hw; 6887 struct ptp_clock_event event; 6888 struct timespec64 ts; 6889 6890 if (pin < 0 || pin >= IGB_N_EXTTS) 6891 return; 6892 6893 if (hw->mac.type == e1000_82580 || 6894 hw->mac.type == e1000_i354 || 6895 hw->mac.type == e1000_i350) { 6896 s64 ns = rd32(auxstmpl); 6897 6898 ns += ((s64)(rd32(auxstmph) & 0xFF)) << 32; 6899 ts = ns_to_timespec64(ns); 6900 } else { 6901 ts.tv_nsec = rd32(auxstmpl); 6902 ts.tv_sec = rd32(auxstmph); 6903 } 6904 6905 event.type = PTP_CLOCK_EXTTS; 6906 event.index = tsintr_tt; 6907 event.timestamp = ts.tv_sec * 1000000000ULL + ts.tv_nsec; 6908 ptp_clock_event(adapter->ptp_clock, &event); 6909 } 6910 6911 static void igb_tsync_interrupt(struct igb_adapter *adapter) 6912 { 6913 struct e1000_hw *hw = &adapter->hw; 6914 u32 ack = 0, tsicr = rd32(E1000_TSICR); 6915 struct ptp_clock_event event; 6916 6917 if (tsicr & TSINTR_SYS_WRAP) { 6918 event.type = PTP_CLOCK_PPS; 6919 if (adapter->ptp_caps.pps) 6920 ptp_clock_event(adapter->ptp_clock, &event); 6921 ack |= TSINTR_SYS_WRAP; 6922 } 6923 6924 if (tsicr & E1000_TSICR_TXTS) { 6925 /* retrieve hardware timestamp */ 6926 schedule_work(&adapter->ptp_tx_work); 6927 ack |= E1000_TSICR_TXTS; 6928 } 6929 6930 if (tsicr & TSINTR_TT0) { 6931 igb_perout(adapter, 0); 6932 ack |= TSINTR_TT0; 6933 } 6934 6935 if (tsicr & TSINTR_TT1) { 6936 igb_perout(adapter, 1); 6937 ack |= TSINTR_TT1; 6938 } 6939 6940 if (tsicr & TSINTR_AUTT0) { 6941 igb_extts(adapter, 0); 6942 ack |= TSINTR_AUTT0; 6943 } 6944 6945 if (tsicr & TSINTR_AUTT1) { 6946 igb_extts(adapter, 1); 6947 ack |= TSINTR_AUTT1; 6948 } 6949 6950 /* acknowledge the interrupts */ 6951 wr32(E1000_TSICR, ack); 6952 } 6953 6954 static irqreturn_t igb_msix_other(int irq, void *data) 6955 { 6956 struct igb_adapter *adapter = data; 6957 struct e1000_hw *hw = &adapter->hw; 6958 u32 icr = rd32(E1000_ICR); 6959 /* reading ICR causes bit 31 of EICR to be cleared */ 6960 6961 if (icr & E1000_ICR_DRSTA) 6962 schedule_work(&adapter->reset_task); 6963 6964 if (icr & E1000_ICR_DOUTSYNC) { 6965 /* HW is reporting DMA is out of sync */ 6966 adapter->stats.doosync++; 6967 /* The DMA Out of Sync is also indication of a spoof event 6968 * in IOV mode. Check the Wrong VM Behavior register to 6969 * see if it is really a spoof event. 6970 */ 6971 igb_check_wvbr(adapter); 6972 } 6973 6974 /* Check for a mailbox event */ 6975 if (icr & E1000_ICR_VMMB) 6976 igb_msg_task(adapter); 6977 6978 if (icr & E1000_ICR_LSC) { 6979 hw->mac.get_link_status = 1; 6980 /* guard against interrupt when we're going down */ 6981 if (!test_bit(__IGB_DOWN, &adapter->state)) 6982 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6983 } 6984 6985 if (icr & E1000_ICR_TS) 6986 igb_tsync_interrupt(adapter); 6987 6988 wr32(E1000_EIMS, adapter->eims_other); 6989 6990 return IRQ_HANDLED; 6991 } 6992 6993 static void igb_write_itr(struct igb_q_vector *q_vector) 6994 { 6995 struct igb_adapter *adapter = q_vector->adapter; 6996 u32 itr_val = q_vector->itr_val & 0x7FFC; 6997 6998 if (!q_vector->set_itr) 6999 return; 7000 7001 if (!itr_val) 7002 itr_val = 0x4; 7003 7004 if (adapter->hw.mac.type == e1000_82575) 7005 itr_val |= itr_val << 16; 7006 else 7007 itr_val |= E1000_EITR_CNT_IGNR; 7008 7009 writel(itr_val, q_vector->itr_register); 7010 q_vector->set_itr = 0; 7011 } 7012 7013 static irqreturn_t igb_msix_ring(int irq, void *data) 7014 { 7015 struct igb_q_vector *q_vector = data; 7016 7017 /* Write the ITR value calculated from the previous interrupt. */ 7018 igb_write_itr(q_vector); 7019 7020 napi_schedule(&q_vector->napi); 7021 7022 return IRQ_HANDLED; 7023 } 7024 7025 #ifdef CONFIG_IGB_DCA 7026 static void igb_update_tx_dca(struct igb_adapter *adapter, 7027 struct igb_ring *tx_ring, 7028 int cpu) 7029 { 7030 struct e1000_hw *hw = &adapter->hw; 7031 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 7032 7033 if (hw->mac.type != e1000_82575) 7034 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 7035 7036 /* We can enable relaxed ordering for reads, but not writes when 7037 * DCA is enabled. This is due to a known issue in some chipsets 7038 * which will cause the DCA tag to be cleared. 7039 */ 7040 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 7041 E1000_DCA_TXCTRL_DATA_RRO_EN | 7042 E1000_DCA_TXCTRL_DESC_DCA_EN; 7043 7044 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 7045 } 7046 7047 static void igb_update_rx_dca(struct igb_adapter *adapter, 7048 struct igb_ring *rx_ring, 7049 int cpu) 7050 { 7051 struct e1000_hw *hw = &adapter->hw; 7052 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 7053 7054 if (hw->mac.type != e1000_82575) 7055 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 7056 7057 /* We can enable relaxed ordering for reads, but not writes when 7058 * DCA is enabled. This is due to a known issue in some chipsets 7059 * which will cause the DCA tag to be cleared. 7060 */ 7061 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 7062 E1000_DCA_RXCTRL_DESC_DCA_EN; 7063 7064 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 7065 } 7066 7067 static void igb_update_dca(struct igb_q_vector *q_vector) 7068 { 7069 struct igb_adapter *adapter = q_vector->adapter; 7070 int cpu = get_cpu(); 7071 7072 if (q_vector->cpu == cpu) 7073 goto out_no_update; 7074 7075 if (q_vector->tx.ring) 7076 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 7077 7078 if (q_vector->rx.ring) 7079 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 7080 7081 q_vector->cpu = cpu; 7082 out_no_update: 7083 put_cpu(); 7084 } 7085 7086 static void igb_setup_dca(struct igb_adapter *adapter) 7087 { 7088 struct e1000_hw *hw = &adapter->hw; 7089 int i; 7090 7091 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 7092 return; 7093 7094 /* Always use CB2 mode, difference is masked in the CB driver. */ 7095 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 7096 7097 for (i = 0; i < adapter->num_q_vectors; i++) { 7098 adapter->q_vector[i]->cpu = -1; 7099 igb_update_dca(adapter->q_vector[i]); 7100 } 7101 } 7102 7103 static int __igb_notify_dca(struct device *dev, void *data) 7104 { 7105 struct net_device *netdev = dev_get_drvdata(dev); 7106 struct igb_adapter *adapter = netdev_priv(netdev); 7107 struct pci_dev *pdev = adapter->pdev; 7108 struct e1000_hw *hw = &adapter->hw; 7109 unsigned long event = *(unsigned long *)data; 7110 7111 switch (event) { 7112 case DCA_PROVIDER_ADD: 7113 /* if already enabled, don't do it again */ 7114 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 7115 break; 7116 if (dca_add_requester(dev) == 0) { 7117 adapter->flags |= IGB_FLAG_DCA_ENABLED; 7118 dev_info(&pdev->dev, "DCA enabled\n"); 7119 igb_setup_dca(adapter); 7120 break; 7121 } 7122 fallthrough; /* since DCA is disabled. */ 7123 case DCA_PROVIDER_REMOVE: 7124 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 7125 /* without this a class_device is left 7126 * hanging around in the sysfs model 7127 */ 7128 dca_remove_requester(dev); 7129 dev_info(&pdev->dev, "DCA disabled\n"); 7130 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 7131 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 7132 } 7133 break; 7134 } 7135 7136 return 0; 7137 } 7138 7139 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 7140 void *p) 7141 { 7142 int ret_val; 7143 7144 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 7145 __igb_notify_dca); 7146 7147 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 7148 } 7149 #endif /* CONFIG_IGB_DCA */ 7150 7151 #ifdef CONFIG_PCI_IOV 7152 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 7153 { 7154 unsigned char mac_addr[ETH_ALEN]; 7155 7156 eth_zero_addr(mac_addr); 7157 igb_set_vf_mac(adapter, vf, mac_addr); 7158 7159 /* By default spoof check is enabled for all VFs */ 7160 adapter->vf_data[vf].spoofchk_enabled = true; 7161 7162 /* By default VFs are not trusted */ 7163 adapter->vf_data[vf].trusted = false; 7164 7165 return 0; 7166 } 7167 7168 #endif 7169 static void igb_ping_all_vfs(struct igb_adapter *adapter) 7170 { 7171 struct e1000_hw *hw = &adapter->hw; 7172 u32 ping; 7173 int i; 7174 7175 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 7176 ping = E1000_PF_CONTROL_MSG; 7177 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 7178 ping |= E1000_VT_MSGTYPE_CTS; 7179 igb_write_mbx(hw, &ping, 1, i); 7180 } 7181 } 7182 7183 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7184 { 7185 struct e1000_hw *hw = &adapter->hw; 7186 u32 vmolr = rd32(E1000_VMOLR(vf)); 7187 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7188 7189 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 7190 IGB_VF_FLAG_MULTI_PROMISC); 7191 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7192 7193 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 7194 vmolr |= E1000_VMOLR_MPME; 7195 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 7196 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 7197 } else { 7198 /* if we have hashes and we are clearing a multicast promisc 7199 * flag we need to write the hashes to the MTA as this step 7200 * was previously skipped 7201 */ 7202 if (vf_data->num_vf_mc_hashes > 30) { 7203 vmolr |= E1000_VMOLR_MPME; 7204 } else if (vf_data->num_vf_mc_hashes) { 7205 int j; 7206 7207 vmolr |= E1000_VMOLR_ROMPE; 7208 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7209 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7210 } 7211 } 7212 7213 wr32(E1000_VMOLR(vf), vmolr); 7214 7215 /* there are flags left unprocessed, likely not supported */ 7216 if (*msgbuf & E1000_VT_MSGINFO_MASK) 7217 return -EINVAL; 7218 7219 return 0; 7220 } 7221 7222 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 7223 u32 *msgbuf, u32 vf) 7224 { 7225 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7226 u16 *hash_list = (u16 *)&msgbuf[1]; 7227 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7228 int i; 7229 7230 /* salt away the number of multicast addresses assigned 7231 * to this VF for later use to restore when the PF multi cast 7232 * list changes 7233 */ 7234 vf_data->num_vf_mc_hashes = n; 7235 7236 /* only up to 30 hash values supported */ 7237 if (n > 30) 7238 n = 30; 7239 7240 /* store the hashes for later use */ 7241 for (i = 0; i < n; i++) 7242 vf_data->vf_mc_hashes[i] = hash_list[i]; 7243 7244 /* Flush and reset the mta with the new values */ 7245 igb_set_rx_mode(adapter->netdev); 7246 7247 return 0; 7248 } 7249 7250 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 7251 { 7252 struct e1000_hw *hw = &adapter->hw; 7253 struct vf_data_storage *vf_data; 7254 int i, j; 7255 7256 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7257 u32 vmolr = rd32(E1000_VMOLR(i)); 7258 7259 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7260 7261 vf_data = &adapter->vf_data[i]; 7262 7263 if ((vf_data->num_vf_mc_hashes > 30) || 7264 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 7265 vmolr |= E1000_VMOLR_MPME; 7266 } else if (vf_data->num_vf_mc_hashes) { 7267 vmolr |= E1000_VMOLR_ROMPE; 7268 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7269 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7270 } 7271 wr32(E1000_VMOLR(i), vmolr); 7272 } 7273 } 7274 7275 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 7276 { 7277 struct e1000_hw *hw = &adapter->hw; 7278 u32 pool_mask, vlvf_mask, i; 7279 7280 /* create mask for VF and other pools */ 7281 pool_mask = E1000_VLVF_POOLSEL_MASK; 7282 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 7283 7284 /* drop PF from pool bits */ 7285 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 7286 adapter->vfs_allocated_count); 7287 7288 /* Find the vlan filter for this id */ 7289 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 7290 u32 vlvf = rd32(E1000_VLVF(i)); 7291 u32 vfta_mask, vid, vfta; 7292 7293 /* remove the vf from the pool */ 7294 if (!(vlvf & vlvf_mask)) 7295 continue; 7296 7297 /* clear out bit from VLVF */ 7298 vlvf ^= vlvf_mask; 7299 7300 /* if other pools are present, just remove ourselves */ 7301 if (vlvf & pool_mask) 7302 goto update_vlvfb; 7303 7304 /* if PF is present, leave VFTA */ 7305 if (vlvf & E1000_VLVF_POOLSEL_MASK) 7306 goto update_vlvf; 7307 7308 vid = vlvf & E1000_VLVF_VLANID_MASK; 7309 vfta_mask = BIT(vid % 32); 7310 7311 /* clear bit from VFTA */ 7312 vfta = adapter->shadow_vfta[vid / 32]; 7313 if (vfta & vfta_mask) 7314 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 7315 update_vlvf: 7316 /* clear pool selection enable */ 7317 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7318 vlvf &= E1000_VLVF_POOLSEL_MASK; 7319 else 7320 vlvf = 0; 7321 update_vlvfb: 7322 /* clear pool bits */ 7323 wr32(E1000_VLVF(i), vlvf); 7324 } 7325 } 7326 7327 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 7328 { 7329 u32 vlvf; 7330 int idx; 7331 7332 /* short cut the special case */ 7333 if (vlan == 0) 7334 return 0; 7335 7336 /* Search for the VLAN id in the VLVF entries */ 7337 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 7338 vlvf = rd32(E1000_VLVF(idx)); 7339 if ((vlvf & VLAN_VID_MASK) == vlan) 7340 break; 7341 } 7342 7343 return idx; 7344 } 7345 7346 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 7347 { 7348 struct e1000_hw *hw = &adapter->hw; 7349 u32 bits, pf_id; 7350 int idx; 7351 7352 idx = igb_find_vlvf_entry(hw, vid); 7353 if (!idx) 7354 return; 7355 7356 /* See if any other pools are set for this VLAN filter 7357 * entry other than the PF. 7358 */ 7359 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 7360 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 7361 bits &= rd32(E1000_VLVF(idx)); 7362 7363 /* Disable the filter so this falls into the default pool. */ 7364 if (!bits) { 7365 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7366 wr32(E1000_VLVF(idx), BIT(pf_id)); 7367 else 7368 wr32(E1000_VLVF(idx), 0); 7369 } 7370 } 7371 7372 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 7373 bool add, u32 vf) 7374 { 7375 int pf_id = adapter->vfs_allocated_count; 7376 struct e1000_hw *hw = &adapter->hw; 7377 int err; 7378 7379 /* If VLAN overlaps with one the PF is currently monitoring make 7380 * sure that we are able to allocate a VLVF entry. This may be 7381 * redundant but it guarantees PF will maintain visibility to 7382 * the VLAN. 7383 */ 7384 if (add && test_bit(vid, adapter->active_vlans)) { 7385 err = igb_vfta_set(hw, vid, pf_id, true, false); 7386 if (err) 7387 return err; 7388 } 7389 7390 err = igb_vfta_set(hw, vid, vf, add, false); 7391 7392 if (add && !err) 7393 return err; 7394 7395 /* If we failed to add the VF VLAN or we are removing the VF VLAN 7396 * we may need to drop the PF pool bit in order to allow us to free 7397 * up the VLVF resources. 7398 */ 7399 if (test_bit(vid, adapter->active_vlans) || 7400 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7401 igb_update_pf_vlvf(adapter, vid); 7402 7403 return err; 7404 } 7405 7406 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 7407 { 7408 struct e1000_hw *hw = &adapter->hw; 7409 7410 if (vid) 7411 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 7412 else 7413 wr32(E1000_VMVIR(vf), 0); 7414 } 7415 7416 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7417 u16 vlan, u8 qos) 7418 { 7419 int err; 7420 7421 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7422 if (err) 7423 return err; 7424 7425 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7426 igb_set_vmolr(adapter, vf, !vlan); 7427 7428 /* revoke access to previous VLAN */ 7429 if (vlan != adapter->vf_data[vf].pf_vlan) 7430 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7431 false, vf); 7432 7433 adapter->vf_data[vf].pf_vlan = vlan; 7434 adapter->vf_data[vf].pf_qos = qos; 7435 igb_set_vf_vlan_strip(adapter, vf, true); 7436 dev_info(&adapter->pdev->dev, 7437 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7438 if (test_bit(__IGB_DOWN, &adapter->state)) { 7439 dev_warn(&adapter->pdev->dev, 7440 "The VF VLAN has been set, but the PF device is not up.\n"); 7441 dev_warn(&adapter->pdev->dev, 7442 "Bring the PF device up before attempting to use the VF device.\n"); 7443 } 7444 7445 return err; 7446 } 7447 7448 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7449 { 7450 /* Restore tagless access via VLAN 0 */ 7451 igb_set_vf_vlan(adapter, 0, true, vf); 7452 7453 igb_set_vmvir(adapter, 0, vf); 7454 igb_set_vmolr(adapter, vf, true); 7455 7456 /* Remove any PF assigned VLAN */ 7457 if (adapter->vf_data[vf].pf_vlan) 7458 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7459 false, vf); 7460 7461 adapter->vf_data[vf].pf_vlan = 0; 7462 adapter->vf_data[vf].pf_qos = 0; 7463 igb_set_vf_vlan_strip(adapter, vf, false); 7464 7465 return 0; 7466 } 7467 7468 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7469 u16 vlan, u8 qos, __be16 vlan_proto) 7470 { 7471 struct igb_adapter *adapter = netdev_priv(netdev); 7472 7473 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7474 return -EINVAL; 7475 7476 if (vlan_proto != htons(ETH_P_8021Q)) 7477 return -EPROTONOSUPPORT; 7478 7479 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7480 igb_disable_port_vlan(adapter, vf); 7481 } 7482 7483 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7484 { 7485 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7486 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7487 int ret; 7488 7489 if (adapter->vf_data[vf].pf_vlan) 7490 return -1; 7491 7492 /* VLAN 0 is a special case, don't allow it to be removed */ 7493 if (!vid && !add) 7494 return 0; 7495 7496 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7497 if (!ret) 7498 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7499 return ret; 7500 } 7501 7502 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7503 { 7504 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7505 7506 /* clear flags - except flag that indicates PF has set the MAC */ 7507 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7508 vf_data->last_nack = jiffies; 7509 7510 /* reset vlans for device */ 7511 igb_clear_vf_vfta(adapter, vf); 7512 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7513 igb_set_vmvir(adapter, vf_data->pf_vlan | 7514 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7515 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7516 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7517 7518 /* reset multicast table array for vf */ 7519 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7520 7521 /* Flush and reset the mta with the new values */ 7522 igb_set_rx_mode(adapter->netdev); 7523 } 7524 7525 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7526 { 7527 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7528 7529 /* clear mac address as we were hotplug removed/added */ 7530 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7531 eth_zero_addr(vf_mac); 7532 7533 /* process remaining reset events */ 7534 igb_vf_reset(adapter, vf); 7535 } 7536 7537 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7538 { 7539 struct e1000_hw *hw = &adapter->hw; 7540 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7541 u32 reg, msgbuf[3] = {}; 7542 u8 *addr = (u8 *)(&msgbuf[1]); 7543 7544 /* process all the same items cleared in a function level reset */ 7545 igb_vf_reset(adapter, vf); 7546 7547 /* set vf mac address */ 7548 igb_set_vf_mac(adapter, vf, vf_mac); 7549 7550 /* enable transmit and receive for vf */ 7551 reg = rd32(E1000_VFTE); 7552 wr32(E1000_VFTE, reg | BIT(vf)); 7553 reg = rd32(E1000_VFRE); 7554 wr32(E1000_VFRE, reg | BIT(vf)); 7555 7556 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7557 7558 /* reply to reset with ack and vf mac address */ 7559 if (!is_zero_ether_addr(vf_mac)) { 7560 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7561 memcpy(addr, vf_mac, ETH_ALEN); 7562 } else { 7563 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7564 } 7565 igb_write_mbx(hw, msgbuf, 3, vf); 7566 } 7567 7568 static void igb_flush_mac_table(struct igb_adapter *adapter) 7569 { 7570 struct e1000_hw *hw = &adapter->hw; 7571 int i; 7572 7573 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7574 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7575 eth_zero_addr(adapter->mac_table[i].addr); 7576 adapter->mac_table[i].queue = 0; 7577 igb_rar_set_index(adapter, i); 7578 } 7579 } 7580 7581 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7582 { 7583 struct e1000_hw *hw = &adapter->hw; 7584 /* do not count rar entries reserved for VFs MAC addresses */ 7585 int rar_entries = hw->mac.rar_entry_count - 7586 adapter->vfs_allocated_count; 7587 int i, count = 0; 7588 7589 for (i = 0; i < rar_entries; i++) { 7590 /* do not count default entries */ 7591 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7592 continue; 7593 7594 /* do not count "in use" entries for different queues */ 7595 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7596 (adapter->mac_table[i].queue != queue)) 7597 continue; 7598 7599 count++; 7600 } 7601 7602 return count; 7603 } 7604 7605 /* Set default MAC address for the PF in the first RAR entry */ 7606 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7607 { 7608 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7609 7610 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7611 mac_table->queue = adapter->vfs_allocated_count; 7612 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7613 7614 igb_rar_set_index(adapter, 0); 7615 } 7616 7617 /* If the filter to be added and an already existing filter express 7618 * the same address and address type, it should be possible to only 7619 * override the other configurations, for example the queue to steer 7620 * traffic. 7621 */ 7622 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7623 const u8 *addr, const u8 flags) 7624 { 7625 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7626 return true; 7627 7628 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7629 (flags & IGB_MAC_STATE_SRC_ADDR)) 7630 return false; 7631 7632 if (!ether_addr_equal(addr, entry->addr)) 7633 return false; 7634 7635 return true; 7636 } 7637 7638 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7639 * 'flags' is used to indicate what kind of match is made, match is by 7640 * default for the destination address, if matching by source address 7641 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7642 */ 7643 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7644 const u8 *addr, const u8 queue, 7645 const u8 flags) 7646 { 7647 struct e1000_hw *hw = &adapter->hw; 7648 int rar_entries = hw->mac.rar_entry_count - 7649 adapter->vfs_allocated_count; 7650 int i; 7651 7652 if (is_zero_ether_addr(addr)) 7653 return -EINVAL; 7654 7655 /* Search for the first empty entry in the MAC table. 7656 * Do not touch entries at the end of the table reserved for the VF MAC 7657 * addresses. 7658 */ 7659 for (i = 0; i < rar_entries; i++) { 7660 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7661 addr, flags)) 7662 continue; 7663 7664 ether_addr_copy(adapter->mac_table[i].addr, addr); 7665 adapter->mac_table[i].queue = queue; 7666 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7667 7668 igb_rar_set_index(adapter, i); 7669 return i; 7670 } 7671 7672 return -ENOSPC; 7673 } 7674 7675 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7676 const u8 queue) 7677 { 7678 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7679 } 7680 7681 /* Remove a MAC filter for 'addr' directing matching traffic to 7682 * 'queue', 'flags' is used to indicate what kind of match need to be 7683 * removed, match is by default for the destination address, if 7684 * matching by source address is to be removed the flag 7685 * IGB_MAC_STATE_SRC_ADDR can be used. 7686 */ 7687 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7688 const u8 *addr, const u8 queue, 7689 const u8 flags) 7690 { 7691 struct e1000_hw *hw = &adapter->hw; 7692 int rar_entries = hw->mac.rar_entry_count - 7693 adapter->vfs_allocated_count; 7694 int i; 7695 7696 if (is_zero_ether_addr(addr)) 7697 return -EINVAL; 7698 7699 /* Search for matching entry in the MAC table based on given address 7700 * and queue. Do not touch entries at the end of the table reserved 7701 * for the VF MAC addresses. 7702 */ 7703 for (i = 0; i < rar_entries; i++) { 7704 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7705 continue; 7706 if ((adapter->mac_table[i].state & flags) != flags) 7707 continue; 7708 if (adapter->mac_table[i].queue != queue) 7709 continue; 7710 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7711 continue; 7712 7713 /* When a filter for the default address is "deleted", 7714 * we return it to its initial configuration 7715 */ 7716 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7717 adapter->mac_table[i].state = 7718 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7719 adapter->mac_table[i].queue = 7720 adapter->vfs_allocated_count; 7721 } else { 7722 adapter->mac_table[i].state = 0; 7723 adapter->mac_table[i].queue = 0; 7724 eth_zero_addr(adapter->mac_table[i].addr); 7725 } 7726 7727 igb_rar_set_index(adapter, i); 7728 return 0; 7729 } 7730 7731 return -ENOENT; 7732 } 7733 7734 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7735 const u8 queue) 7736 { 7737 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7738 } 7739 7740 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7741 const u8 *addr, u8 queue, u8 flags) 7742 { 7743 struct e1000_hw *hw = &adapter->hw; 7744 7745 /* In theory, this should be supported on 82575 as well, but 7746 * that part wasn't easily accessible during development. 7747 */ 7748 if (hw->mac.type != e1000_i210) 7749 return -EOPNOTSUPP; 7750 7751 return igb_add_mac_filter_flags(adapter, addr, queue, 7752 IGB_MAC_STATE_QUEUE_STEERING | flags); 7753 } 7754 7755 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7756 const u8 *addr, u8 queue, u8 flags) 7757 { 7758 return igb_del_mac_filter_flags(adapter, addr, queue, 7759 IGB_MAC_STATE_QUEUE_STEERING | flags); 7760 } 7761 7762 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7763 { 7764 struct igb_adapter *adapter = netdev_priv(netdev); 7765 int ret; 7766 7767 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7768 7769 return min_t(int, ret, 0); 7770 } 7771 7772 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7773 { 7774 struct igb_adapter *adapter = netdev_priv(netdev); 7775 7776 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7777 7778 return 0; 7779 } 7780 7781 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7782 const u32 info, const u8 *addr) 7783 { 7784 struct pci_dev *pdev = adapter->pdev; 7785 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7786 struct list_head *pos; 7787 struct vf_mac_filter *entry = NULL; 7788 int ret = 0; 7789 7790 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7791 !vf_data->trusted) { 7792 dev_warn(&pdev->dev, 7793 "VF %d requested MAC filter but is administratively denied\n", 7794 vf); 7795 return -EINVAL; 7796 } 7797 if (!is_valid_ether_addr(addr)) { 7798 dev_warn(&pdev->dev, 7799 "VF %d attempted to set invalid MAC filter\n", 7800 vf); 7801 return -EINVAL; 7802 } 7803 7804 switch (info) { 7805 case E1000_VF_MAC_FILTER_CLR: 7806 /* remove all unicast MAC filters related to the current VF */ 7807 list_for_each(pos, &adapter->vf_macs.l) { 7808 entry = list_entry(pos, struct vf_mac_filter, l); 7809 if (entry->vf == vf) { 7810 entry->vf = -1; 7811 entry->free = true; 7812 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7813 } 7814 } 7815 break; 7816 case E1000_VF_MAC_FILTER_ADD: 7817 /* try to find empty slot in the list */ 7818 list_for_each(pos, &adapter->vf_macs.l) { 7819 entry = list_entry(pos, struct vf_mac_filter, l); 7820 if (entry->free) 7821 break; 7822 } 7823 7824 if (entry && entry->free) { 7825 entry->free = false; 7826 entry->vf = vf; 7827 ether_addr_copy(entry->vf_mac, addr); 7828 7829 ret = igb_add_mac_filter(adapter, addr, vf); 7830 ret = min_t(int, ret, 0); 7831 } else { 7832 ret = -ENOSPC; 7833 } 7834 7835 if (ret == -ENOSPC) 7836 dev_warn(&pdev->dev, 7837 "VF %d has requested MAC filter but there is no space for it\n", 7838 vf); 7839 break; 7840 default: 7841 ret = -EINVAL; 7842 break; 7843 } 7844 7845 return ret; 7846 } 7847 7848 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7849 { 7850 struct pci_dev *pdev = adapter->pdev; 7851 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7852 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7853 7854 /* The VF MAC Address is stored in a packed array of bytes 7855 * starting at the second 32 bit word of the msg array 7856 */ 7857 unsigned char *addr = (unsigned char *)&msg[1]; 7858 int ret = 0; 7859 7860 if (!info) { 7861 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7862 !vf_data->trusted) { 7863 dev_warn(&pdev->dev, 7864 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 7865 vf); 7866 return -EINVAL; 7867 } 7868 7869 if (!is_valid_ether_addr(addr)) { 7870 dev_warn(&pdev->dev, 7871 "VF %d attempted to set invalid MAC\n", 7872 vf); 7873 return -EINVAL; 7874 } 7875 7876 ret = igb_set_vf_mac(adapter, vf, addr); 7877 } else { 7878 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 7879 } 7880 7881 return ret; 7882 } 7883 7884 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 7885 { 7886 struct e1000_hw *hw = &adapter->hw; 7887 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7888 u32 msg = E1000_VT_MSGTYPE_NACK; 7889 7890 /* if device isn't clear to send it shouldn't be reading either */ 7891 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 7892 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 7893 igb_write_mbx(hw, &msg, 1, vf); 7894 vf_data->last_nack = jiffies; 7895 } 7896 } 7897 7898 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 7899 { 7900 struct pci_dev *pdev = adapter->pdev; 7901 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 7902 struct e1000_hw *hw = &adapter->hw; 7903 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7904 s32 retval; 7905 7906 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 7907 7908 if (retval) { 7909 /* if receive failed revoke VF CTS stats and restart init */ 7910 dev_err(&pdev->dev, "Error receiving message from VF\n"); 7911 vf_data->flags &= ~IGB_VF_FLAG_CTS; 7912 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7913 goto unlock; 7914 goto out; 7915 } 7916 7917 /* this is a message we already processed, do nothing */ 7918 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 7919 goto unlock; 7920 7921 /* until the vf completes a reset it should not be 7922 * allowed to start any configuration. 7923 */ 7924 if (msgbuf[0] == E1000_VF_RESET) { 7925 /* unlocks mailbox */ 7926 igb_vf_reset_msg(adapter, vf); 7927 return; 7928 } 7929 7930 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 7931 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7932 goto unlock; 7933 retval = -1; 7934 goto out; 7935 } 7936 7937 switch ((msgbuf[0] & 0xFFFF)) { 7938 case E1000_VF_SET_MAC_ADDR: 7939 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 7940 break; 7941 case E1000_VF_SET_PROMISC: 7942 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 7943 break; 7944 case E1000_VF_SET_MULTICAST: 7945 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 7946 break; 7947 case E1000_VF_SET_LPE: 7948 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 7949 break; 7950 case E1000_VF_SET_VLAN: 7951 retval = -1; 7952 if (vf_data->pf_vlan) 7953 dev_warn(&pdev->dev, 7954 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 7955 vf); 7956 else 7957 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 7958 break; 7959 default: 7960 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 7961 retval = -1; 7962 break; 7963 } 7964 7965 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 7966 out: 7967 /* notify the VF of the results of what it sent us */ 7968 if (retval) 7969 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 7970 else 7971 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 7972 7973 /* unlocks mailbox */ 7974 igb_write_mbx(hw, msgbuf, 1, vf); 7975 return; 7976 7977 unlock: 7978 igb_unlock_mbx(hw, vf); 7979 } 7980 7981 static void igb_msg_task(struct igb_adapter *adapter) 7982 { 7983 struct e1000_hw *hw = &adapter->hw; 7984 unsigned long flags; 7985 u32 vf; 7986 7987 spin_lock_irqsave(&adapter->vfs_lock, flags); 7988 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 7989 /* process any reset requests */ 7990 if (!igb_check_for_rst(hw, vf)) 7991 igb_vf_reset_event(adapter, vf); 7992 7993 /* process any messages pending */ 7994 if (!igb_check_for_msg(hw, vf)) 7995 igb_rcv_msg_from_vf(adapter, vf); 7996 7997 /* process any acks */ 7998 if (!igb_check_for_ack(hw, vf)) 7999 igb_rcv_ack_from_vf(adapter, vf); 8000 } 8001 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 8002 } 8003 8004 /** 8005 * igb_set_uta - Set unicast filter table address 8006 * @adapter: board private structure 8007 * @set: boolean indicating if we are setting or clearing bits 8008 * 8009 * The unicast table address is a register array of 32-bit registers. 8010 * The table is meant to be used in a way similar to how the MTA is used 8011 * however due to certain limitations in the hardware it is necessary to 8012 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 8013 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 8014 **/ 8015 static void igb_set_uta(struct igb_adapter *adapter, bool set) 8016 { 8017 struct e1000_hw *hw = &adapter->hw; 8018 u32 uta = set ? ~0 : 0; 8019 int i; 8020 8021 /* we only need to do this if VMDq is enabled */ 8022 if (!adapter->vfs_allocated_count) 8023 return; 8024 8025 for (i = hw->mac.uta_reg_count; i--;) 8026 array_wr32(E1000_UTA, i, uta); 8027 } 8028 8029 /** 8030 * igb_intr_msi - Interrupt Handler 8031 * @irq: interrupt number 8032 * @data: pointer to a network interface device structure 8033 **/ 8034 static irqreturn_t igb_intr_msi(int irq, void *data) 8035 { 8036 struct igb_adapter *adapter = data; 8037 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8038 struct e1000_hw *hw = &adapter->hw; 8039 /* read ICR disables interrupts using IAM */ 8040 u32 icr = rd32(E1000_ICR); 8041 8042 igb_write_itr(q_vector); 8043 8044 if (icr & E1000_ICR_DRSTA) 8045 schedule_work(&adapter->reset_task); 8046 8047 if (icr & E1000_ICR_DOUTSYNC) { 8048 /* HW is reporting DMA is out of sync */ 8049 adapter->stats.doosync++; 8050 } 8051 8052 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8053 hw->mac.get_link_status = 1; 8054 if (!test_bit(__IGB_DOWN, &adapter->state)) 8055 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8056 } 8057 8058 if (icr & E1000_ICR_TS) 8059 igb_tsync_interrupt(adapter); 8060 8061 napi_schedule(&q_vector->napi); 8062 8063 return IRQ_HANDLED; 8064 } 8065 8066 /** 8067 * igb_intr - Legacy Interrupt Handler 8068 * @irq: interrupt number 8069 * @data: pointer to a network interface device structure 8070 **/ 8071 static irqreturn_t igb_intr(int irq, void *data) 8072 { 8073 struct igb_adapter *adapter = data; 8074 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8075 struct e1000_hw *hw = &adapter->hw; 8076 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 8077 * need for the IMC write 8078 */ 8079 u32 icr = rd32(E1000_ICR); 8080 8081 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 8082 * not set, then the adapter didn't send an interrupt 8083 */ 8084 if (!(icr & E1000_ICR_INT_ASSERTED)) 8085 return IRQ_NONE; 8086 8087 igb_write_itr(q_vector); 8088 8089 if (icr & E1000_ICR_DRSTA) 8090 schedule_work(&adapter->reset_task); 8091 8092 if (icr & E1000_ICR_DOUTSYNC) { 8093 /* HW is reporting DMA is out of sync */ 8094 adapter->stats.doosync++; 8095 } 8096 8097 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8098 hw->mac.get_link_status = 1; 8099 /* guard against interrupt when we're going down */ 8100 if (!test_bit(__IGB_DOWN, &adapter->state)) 8101 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8102 } 8103 8104 if (icr & E1000_ICR_TS) 8105 igb_tsync_interrupt(adapter); 8106 8107 napi_schedule(&q_vector->napi); 8108 8109 return IRQ_HANDLED; 8110 } 8111 8112 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 8113 { 8114 struct igb_adapter *adapter = q_vector->adapter; 8115 struct e1000_hw *hw = &adapter->hw; 8116 8117 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 8118 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 8119 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 8120 igb_set_itr(q_vector); 8121 else 8122 igb_update_ring_itr(q_vector); 8123 } 8124 8125 if (!test_bit(__IGB_DOWN, &adapter->state)) { 8126 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8127 wr32(E1000_EIMS, q_vector->eims_value); 8128 else 8129 igb_irq_enable(adapter); 8130 } 8131 } 8132 8133 /** 8134 * igb_poll - NAPI Rx polling callback 8135 * @napi: napi polling structure 8136 * @budget: count of how many packets we should handle 8137 **/ 8138 static int igb_poll(struct napi_struct *napi, int budget) 8139 { 8140 struct igb_q_vector *q_vector = container_of(napi, 8141 struct igb_q_vector, 8142 napi); 8143 bool clean_complete = true; 8144 int work_done = 0; 8145 8146 #ifdef CONFIG_IGB_DCA 8147 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 8148 igb_update_dca(q_vector); 8149 #endif 8150 if (q_vector->tx.ring) 8151 clean_complete = igb_clean_tx_irq(q_vector, budget); 8152 8153 if (q_vector->rx.ring) { 8154 int cleaned = igb_clean_rx_irq(q_vector, budget); 8155 8156 work_done += cleaned; 8157 if (cleaned >= budget) 8158 clean_complete = false; 8159 } 8160 8161 /* If all work not completed, return budget and keep polling */ 8162 if (!clean_complete) 8163 return budget; 8164 8165 /* Exit the polling mode, but don't re-enable interrupts if stack might 8166 * poll us due to busy-polling 8167 */ 8168 if (likely(napi_complete_done(napi, work_done))) 8169 igb_ring_irq_enable(q_vector); 8170 8171 return work_done; 8172 } 8173 8174 /** 8175 * igb_clean_tx_irq - Reclaim resources after transmit completes 8176 * @q_vector: pointer to q_vector containing needed info 8177 * @napi_budget: Used to determine if we are in netpoll 8178 * 8179 * returns true if ring is completely cleaned 8180 **/ 8181 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 8182 { 8183 struct igb_adapter *adapter = q_vector->adapter; 8184 struct igb_ring *tx_ring = q_vector->tx.ring; 8185 struct igb_tx_buffer *tx_buffer; 8186 union e1000_adv_tx_desc *tx_desc; 8187 unsigned int total_bytes = 0, total_packets = 0; 8188 unsigned int budget = q_vector->tx.work_limit; 8189 unsigned int i = tx_ring->next_to_clean; 8190 8191 if (test_bit(__IGB_DOWN, &adapter->state)) 8192 return true; 8193 8194 tx_buffer = &tx_ring->tx_buffer_info[i]; 8195 tx_desc = IGB_TX_DESC(tx_ring, i); 8196 i -= tx_ring->count; 8197 8198 do { 8199 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 8200 8201 /* if next_to_watch is not set then there is no work pending */ 8202 if (!eop_desc) 8203 break; 8204 8205 /* prevent any other reads prior to eop_desc */ 8206 smp_rmb(); 8207 8208 /* if DD is not set pending work has not been completed */ 8209 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 8210 break; 8211 8212 /* clear next_to_watch to prevent false hangs */ 8213 tx_buffer->next_to_watch = NULL; 8214 8215 /* update the statistics for this packet */ 8216 total_bytes += tx_buffer->bytecount; 8217 total_packets += tx_buffer->gso_segs; 8218 8219 /* free the skb */ 8220 if (tx_buffer->type == IGB_TYPE_SKB) 8221 napi_consume_skb(tx_buffer->skb, napi_budget); 8222 else 8223 xdp_return_frame(tx_buffer->xdpf); 8224 8225 /* unmap skb header data */ 8226 dma_unmap_single(tx_ring->dev, 8227 dma_unmap_addr(tx_buffer, dma), 8228 dma_unmap_len(tx_buffer, len), 8229 DMA_TO_DEVICE); 8230 8231 /* clear tx_buffer data */ 8232 dma_unmap_len_set(tx_buffer, len, 0); 8233 8234 /* clear last DMA location and unmap remaining buffers */ 8235 while (tx_desc != eop_desc) { 8236 tx_buffer++; 8237 tx_desc++; 8238 i++; 8239 if (unlikely(!i)) { 8240 i -= tx_ring->count; 8241 tx_buffer = tx_ring->tx_buffer_info; 8242 tx_desc = IGB_TX_DESC(tx_ring, 0); 8243 } 8244 8245 /* unmap any remaining paged data */ 8246 if (dma_unmap_len(tx_buffer, len)) { 8247 dma_unmap_page(tx_ring->dev, 8248 dma_unmap_addr(tx_buffer, dma), 8249 dma_unmap_len(tx_buffer, len), 8250 DMA_TO_DEVICE); 8251 dma_unmap_len_set(tx_buffer, len, 0); 8252 } 8253 } 8254 8255 /* move us one more past the eop_desc for start of next pkt */ 8256 tx_buffer++; 8257 tx_desc++; 8258 i++; 8259 if (unlikely(!i)) { 8260 i -= tx_ring->count; 8261 tx_buffer = tx_ring->tx_buffer_info; 8262 tx_desc = IGB_TX_DESC(tx_ring, 0); 8263 } 8264 8265 /* issue prefetch for next Tx descriptor */ 8266 prefetch(tx_desc); 8267 8268 /* update budget accounting */ 8269 budget--; 8270 } while (likely(budget)); 8271 8272 netdev_tx_completed_queue(txring_txq(tx_ring), 8273 total_packets, total_bytes); 8274 i += tx_ring->count; 8275 tx_ring->next_to_clean = i; 8276 u64_stats_update_begin(&tx_ring->tx_syncp); 8277 tx_ring->tx_stats.bytes += total_bytes; 8278 tx_ring->tx_stats.packets += total_packets; 8279 u64_stats_update_end(&tx_ring->tx_syncp); 8280 q_vector->tx.total_bytes += total_bytes; 8281 q_vector->tx.total_packets += total_packets; 8282 8283 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 8284 struct e1000_hw *hw = &adapter->hw; 8285 8286 /* Detect a transmit hang in hardware, this serializes the 8287 * check with the clearing of time_stamp and movement of i 8288 */ 8289 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 8290 if (tx_buffer->next_to_watch && 8291 time_after(jiffies, tx_buffer->time_stamp + 8292 (adapter->tx_timeout_factor * HZ)) && 8293 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 8294 8295 /* detected Tx unit hang */ 8296 dev_err(tx_ring->dev, 8297 "Detected Tx Unit Hang\n" 8298 " Tx Queue <%d>\n" 8299 " TDH <%x>\n" 8300 " TDT <%x>\n" 8301 " next_to_use <%x>\n" 8302 " next_to_clean <%x>\n" 8303 "buffer_info[next_to_clean]\n" 8304 " time_stamp <%lx>\n" 8305 " next_to_watch <%p>\n" 8306 " jiffies <%lx>\n" 8307 " desc.status <%x>\n", 8308 tx_ring->queue_index, 8309 rd32(E1000_TDH(tx_ring->reg_idx)), 8310 readl(tx_ring->tail), 8311 tx_ring->next_to_use, 8312 tx_ring->next_to_clean, 8313 tx_buffer->time_stamp, 8314 tx_buffer->next_to_watch, 8315 jiffies, 8316 tx_buffer->next_to_watch->wb.status); 8317 netif_stop_subqueue(tx_ring->netdev, 8318 tx_ring->queue_index); 8319 8320 /* we are about to reset, no point in enabling stuff */ 8321 return true; 8322 } 8323 } 8324 8325 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 8326 if (unlikely(total_packets && 8327 netif_carrier_ok(tx_ring->netdev) && 8328 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 8329 /* Make sure that anybody stopping the queue after this 8330 * sees the new next_to_clean. 8331 */ 8332 smp_mb(); 8333 if (__netif_subqueue_stopped(tx_ring->netdev, 8334 tx_ring->queue_index) && 8335 !(test_bit(__IGB_DOWN, &adapter->state))) { 8336 netif_wake_subqueue(tx_ring->netdev, 8337 tx_ring->queue_index); 8338 8339 u64_stats_update_begin(&tx_ring->tx_syncp); 8340 tx_ring->tx_stats.restart_queue++; 8341 u64_stats_update_end(&tx_ring->tx_syncp); 8342 } 8343 } 8344 8345 return !!budget; 8346 } 8347 8348 /** 8349 * igb_reuse_rx_page - page flip buffer and store it back on the ring 8350 * @rx_ring: rx descriptor ring to store buffers on 8351 * @old_buff: donor buffer to have page reused 8352 * 8353 * Synchronizes page for reuse by the adapter 8354 **/ 8355 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 8356 struct igb_rx_buffer *old_buff) 8357 { 8358 struct igb_rx_buffer *new_buff; 8359 u16 nta = rx_ring->next_to_alloc; 8360 8361 new_buff = &rx_ring->rx_buffer_info[nta]; 8362 8363 /* update, and store next to alloc */ 8364 nta++; 8365 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 8366 8367 /* Transfer page from old buffer to new buffer. 8368 * Move each member individually to avoid possible store 8369 * forwarding stalls. 8370 */ 8371 new_buff->dma = old_buff->dma; 8372 new_buff->page = old_buff->page; 8373 new_buff->page_offset = old_buff->page_offset; 8374 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 8375 } 8376 8377 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 8378 int rx_buf_pgcnt) 8379 { 8380 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 8381 struct page *page = rx_buffer->page; 8382 8383 /* avoid re-using remote and pfmemalloc pages */ 8384 if (!dev_page_is_reusable(page)) 8385 return false; 8386 8387 #if (PAGE_SIZE < 8192) 8388 /* if we are only owner of page we can reuse it */ 8389 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1)) 8390 return false; 8391 #else 8392 #define IGB_LAST_OFFSET \ 8393 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 8394 8395 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 8396 return false; 8397 #endif 8398 8399 /* If we have drained the page fragment pool we need to update 8400 * the pagecnt_bias and page count so that we fully restock the 8401 * number of references the driver holds. 8402 */ 8403 if (unlikely(pagecnt_bias == 1)) { 8404 page_ref_add(page, USHRT_MAX - 1); 8405 rx_buffer->pagecnt_bias = USHRT_MAX; 8406 } 8407 8408 return true; 8409 } 8410 8411 /** 8412 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 8413 * @rx_ring: rx descriptor ring to transact packets on 8414 * @rx_buffer: buffer containing page to add 8415 * @skb: sk_buff to place the data into 8416 * @size: size of buffer to be added 8417 * 8418 * This function will add the data contained in rx_buffer->page to the skb. 8419 **/ 8420 static void igb_add_rx_frag(struct igb_ring *rx_ring, 8421 struct igb_rx_buffer *rx_buffer, 8422 struct sk_buff *skb, 8423 unsigned int size) 8424 { 8425 #if (PAGE_SIZE < 8192) 8426 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8427 #else 8428 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8429 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8430 SKB_DATA_ALIGN(size); 8431 #endif 8432 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8433 rx_buffer->page_offset, size, truesize); 8434 #if (PAGE_SIZE < 8192) 8435 rx_buffer->page_offset ^= truesize; 8436 #else 8437 rx_buffer->page_offset += truesize; 8438 #endif 8439 } 8440 8441 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8442 struct igb_rx_buffer *rx_buffer, 8443 struct xdp_buff *xdp, 8444 ktime_t timestamp) 8445 { 8446 #if (PAGE_SIZE < 8192) 8447 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8448 #else 8449 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 8450 xdp->data_hard_start); 8451 #endif 8452 unsigned int size = xdp->data_end - xdp->data; 8453 unsigned int headlen; 8454 struct sk_buff *skb; 8455 8456 /* prefetch first cache line of first page */ 8457 net_prefetch(xdp->data); 8458 8459 /* allocate a skb to store the frags */ 8460 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8461 if (unlikely(!skb)) 8462 return NULL; 8463 8464 if (timestamp) 8465 skb_hwtstamps(skb)->hwtstamp = timestamp; 8466 8467 /* Determine available headroom for copy */ 8468 headlen = size; 8469 if (headlen > IGB_RX_HDR_LEN) 8470 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN); 8471 8472 /* align pull length to size of long to optimize memcpy performance */ 8473 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long))); 8474 8475 /* update all of the pointers */ 8476 size -= headlen; 8477 if (size) { 8478 skb_add_rx_frag(skb, 0, rx_buffer->page, 8479 (xdp->data + headlen) - page_address(rx_buffer->page), 8480 size, truesize); 8481 #if (PAGE_SIZE < 8192) 8482 rx_buffer->page_offset ^= truesize; 8483 #else 8484 rx_buffer->page_offset += truesize; 8485 #endif 8486 } else { 8487 rx_buffer->pagecnt_bias++; 8488 } 8489 8490 return skb; 8491 } 8492 8493 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8494 struct igb_rx_buffer *rx_buffer, 8495 struct xdp_buff *xdp, 8496 ktime_t timestamp) 8497 { 8498 #if (PAGE_SIZE < 8192) 8499 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8500 #else 8501 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8502 SKB_DATA_ALIGN(xdp->data_end - 8503 xdp->data_hard_start); 8504 #endif 8505 unsigned int metasize = xdp->data - xdp->data_meta; 8506 struct sk_buff *skb; 8507 8508 /* prefetch first cache line of first page */ 8509 net_prefetch(xdp->data_meta); 8510 8511 /* build an skb around the page buffer */ 8512 skb = napi_build_skb(xdp->data_hard_start, truesize); 8513 if (unlikely(!skb)) 8514 return NULL; 8515 8516 /* update pointers within the skb to store the data */ 8517 skb_reserve(skb, xdp->data - xdp->data_hard_start); 8518 __skb_put(skb, xdp->data_end - xdp->data); 8519 8520 if (metasize) 8521 skb_metadata_set(skb, metasize); 8522 8523 if (timestamp) 8524 skb_hwtstamps(skb)->hwtstamp = timestamp; 8525 8526 /* update buffer offset */ 8527 #if (PAGE_SIZE < 8192) 8528 rx_buffer->page_offset ^= truesize; 8529 #else 8530 rx_buffer->page_offset += truesize; 8531 #endif 8532 8533 return skb; 8534 } 8535 8536 static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter, 8537 struct igb_ring *rx_ring, 8538 struct xdp_buff *xdp) 8539 { 8540 int err, result = IGB_XDP_PASS; 8541 struct bpf_prog *xdp_prog; 8542 u32 act; 8543 8544 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 8545 8546 if (!xdp_prog) 8547 goto xdp_out; 8548 8549 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 8550 8551 act = bpf_prog_run_xdp(xdp_prog, xdp); 8552 switch (act) { 8553 case XDP_PASS: 8554 break; 8555 case XDP_TX: 8556 result = igb_xdp_xmit_back(adapter, xdp); 8557 if (result == IGB_XDP_CONSUMED) 8558 goto out_failure; 8559 break; 8560 case XDP_REDIRECT: 8561 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 8562 if (err) 8563 goto out_failure; 8564 result = IGB_XDP_REDIR; 8565 break; 8566 default: 8567 bpf_warn_invalid_xdp_action(adapter->netdev, xdp_prog, act); 8568 fallthrough; 8569 case XDP_ABORTED: 8570 out_failure: 8571 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 8572 fallthrough; 8573 case XDP_DROP: 8574 result = IGB_XDP_CONSUMED; 8575 break; 8576 } 8577 xdp_out: 8578 return ERR_PTR(-result); 8579 } 8580 8581 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring, 8582 unsigned int size) 8583 { 8584 unsigned int truesize; 8585 8586 #if (PAGE_SIZE < 8192) 8587 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 8588 #else 8589 truesize = ring_uses_build_skb(rx_ring) ? 8590 SKB_DATA_ALIGN(IGB_SKB_PAD + size) + 8591 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 8592 SKB_DATA_ALIGN(size); 8593 #endif 8594 return truesize; 8595 } 8596 8597 static void igb_rx_buffer_flip(struct igb_ring *rx_ring, 8598 struct igb_rx_buffer *rx_buffer, 8599 unsigned int size) 8600 { 8601 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size); 8602 #if (PAGE_SIZE < 8192) 8603 rx_buffer->page_offset ^= truesize; 8604 #else 8605 rx_buffer->page_offset += truesize; 8606 #endif 8607 } 8608 8609 static inline void igb_rx_checksum(struct igb_ring *ring, 8610 union e1000_adv_rx_desc *rx_desc, 8611 struct sk_buff *skb) 8612 { 8613 skb_checksum_none_assert(skb); 8614 8615 /* Ignore Checksum bit is set */ 8616 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8617 return; 8618 8619 /* Rx checksum disabled via ethtool */ 8620 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8621 return; 8622 8623 /* TCP/UDP checksum error bit is set */ 8624 if (igb_test_staterr(rx_desc, 8625 E1000_RXDEXT_STATERR_TCPE | 8626 E1000_RXDEXT_STATERR_IPE)) { 8627 /* work around errata with sctp packets where the TCPE aka 8628 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8629 * packets, (aka let the stack check the crc32c) 8630 */ 8631 if (!((skb->len == 60) && 8632 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8633 u64_stats_update_begin(&ring->rx_syncp); 8634 ring->rx_stats.csum_err++; 8635 u64_stats_update_end(&ring->rx_syncp); 8636 } 8637 /* let the stack verify checksum errors */ 8638 return; 8639 } 8640 /* It must be a TCP or UDP packet with a valid checksum */ 8641 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8642 E1000_RXD_STAT_UDPCS)) 8643 skb->ip_summed = CHECKSUM_UNNECESSARY; 8644 8645 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8646 le32_to_cpu(rx_desc->wb.upper.status_error)); 8647 } 8648 8649 static inline void igb_rx_hash(struct igb_ring *ring, 8650 union e1000_adv_rx_desc *rx_desc, 8651 struct sk_buff *skb) 8652 { 8653 if (ring->netdev->features & NETIF_F_RXHASH) 8654 skb_set_hash(skb, 8655 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8656 PKT_HASH_TYPE_L3); 8657 } 8658 8659 /** 8660 * igb_is_non_eop - process handling of non-EOP buffers 8661 * @rx_ring: Rx ring being processed 8662 * @rx_desc: Rx descriptor for current buffer 8663 * 8664 * This function updates next to clean. If the buffer is an EOP buffer 8665 * this function exits returning false, otherwise it will place the 8666 * sk_buff in the next buffer to be chained and return true indicating 8667 * that this is in fact a non-EOP buffer. 8668 **/ 8669 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8670 union e1000_adv_rx_desc *rx_desc) 8671 { 8672 u32 ntc = rx_ring->next_to_clean + 1; 8673 8674 /* fetch, update, and store next to clean */ 8675 ntc = (ntc < rx_ring->count) ? ntc : 0; 8676 rx_ring->next_to_clean = ntc; 8677 8678 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8679 8680 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8681 return false; 8682 8683 return true; 8684 } 8685 8686 /** 8687 * igb_cleanup_headers - Correct corrupted or empty headers 8688 * @rx_ring: rx descriptor ring packet is being transacted on 8689 * @rx_desc: pointer to the EOP Rx descriptor 8690 * @skb: pointer to current skb being fixed 8691 * 8692 * Address the case where we are pulling data in on pages only 8693 * and as such no data is present in the skb header. 8694 * 8695 * In addition if skb is not at least 60 bytes we need to pad it so that 8696 * it is large enough to qualify as a valid Ethernet frame. 8697 * 8698 * Returns true if an error was encountered and skb was freed. 8699 **/ 8700 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8701 union e1000_adv_rx_desc *rx_desc, 8702 struct sk_buff *skb) 8703 { 8704 /* XDP packets use error pointer so abort at this point */ 8705 if (IS_ERR(skb)) 8706 return true; 8707 8708 if (unlikely((igb_test_staterr(rx_desc, 8709 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8710 struct net_device *netdev = rx_ring->netdev; 8711 if (!(netdev->features & NETIF_F_RXALL)) { 8712 dev_kfree_skb_any(skb); 8713 return true; 8714 } 8715 } 8716 8717 /* if eth_skb_pad returns an error the skb was freed */ 8718 if (eth_skb_pad(skb)) 8719 return true; 8720 8721 return false; 8722 } 8723 8724 /** 8725 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8726 * @rx_ring: rx descriptor ring packet is being transacted on 8727 * @rx_desc: pointer to the EOP Rx descriptor 8728 * @skb: pointer to current skb being populated 8729 * 8730 * This function checks the ring, descriptor, and packet information in 8731 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8732 * other fields within the skb. 8733 **/ 8734 static void igb_process_skb_fields(struct igb_ring *rx_ring, 8735 union e1000_adv_rx_desc *rx_desc, 8736 struct sk_buff *skb) 8737 { 8738 struct net_device *dev = rx_ring->netdev; 8739 8740 igb_rx_hash(rx_ring, rx_desc, skb); 8741 8742 igb_rx_checksum(rx_ring, rx_desc, skb); 8743 8744 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8745 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8746 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8747 8748 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8749 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8750 u16 vid; 8751 8752 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8753 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8754 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan); 8755 else 8756 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8757 8758 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8759 } 8760 8761 skb_record_rx_queue(skb, rx_ring->queue_index); 8762 8763 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8764 } 8765 8766 static unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8767 { 8768 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8769 } 8770 8771 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8772 const unsigned int size, int *rx_buf_pgcnt) 8773 { 8774 struct igb_rx_buffer *rx_buffer; 8775 8776 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8777 *rx_buf_pgcnt = 8778 #if (PAGE_SIZE < 8192) 8779 page_count(rx_buffer->page); 8780 #else 8781 0; 8782 #endif 8783 prefetchw(rx_buffer->page); 8784 8785 /* we are reusing so sync this buffer for CPU use */ 8786 dma_sync_single_range_for_cpu(rx_ring->dev, 8787 rx_buffer->dma, 8788 rx_buffer->page_offset, 8789 size, 8790 DMA_FROM_DEVICE); 8791 8792 rx_buffer->pagecnt_bias--; 8793 8794 return rx_buffer; 8795 } 8796 8797 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8798 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt) 8799 { 8800 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) { 8801 /* hand second half of page back to the ring */ 8802 igb_reuse_rx_page(rx_ring, rx_buffer); 8803 } else { 8804 /* We are not reusing the buffer so unmap it and free 8805 * any references we are holding to it 8806 */ 8807 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8808 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8809 IGB_RX_DMA_ATTR); 8810 __page_frag_cache_drain(rx_buffer->page, 8811 rx_buffer->pagecnt_bias); 8812 } 8813 8814 /* clear contents of rx_buffer */ 8815 rx_buffer->page = NULL; 8816 } 8817 8818 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 8819 { 8820 struct igb_adapter *adapter = q_vector->adapter; 8821 struct igb_ring *rx_ring = q_vector->rx.ring; 8822 struct sk_buff *skb = rx_ring->skb; 8823 unsigned int total_bytes = 0, total_packets = 0; 8824 u16 cleaned_count = igb_desc_unused(rx_ring); 8825 unsigned int xdp_xmit = 0; 8826 struct xdp_buff xdp; 8827 u32 frame_sz = 0; 8828 int rx_buf_pgcnt; 8829 8830 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 8831 #if (PAGE_SIZE < 8192) 8832 frame_sz = igb_rx_frame_truesize(rx_ring, 0); 8833 #endif 8834 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 8835 8836 while (likely(total_packets < budget)) { 8837 union e1000_adv_rx_desc *rx_desc; 8838 struct igb_rx_buffer *rx_buffer; 8839 ktime_t timestamp = 0; 8840 int pkt_offset = 0; 8841 unsigned int size; 8842 void *pktbuf; 8843 8844 /* return some buffers to hardware, one at a time is too slow */ 8845 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 8846 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8847 cleaned_count = 0; 8848 } 8849 8850 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 8851 size = le16_to_cpu(rx_desc->wb.upper.length); 8852 if (!size) 8853 break; 8854 8855 /* This memory barrier is needed to keep us from reading 8856 * any other fields out of the rx_desc until we know the 8857 * descriptor has been written back 8858 */ 8859 dma_rmb(); 8860 8861 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt); 8862 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset; 8863 8864 /* pull rx packet timestamp if available and valid */ 8865 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 8866 int ts_hdr_len; 8867 8868 ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector, 8869 pktbuf, ×tamp); 8870 8871 pkt_offset += ts_hdr_len; 8872 size -= ts_hdr_len; 8873 } 8874 8875 /* retrieve a buffer from the ring */ 8876 if (!skb) { 8877 unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring); 8878 unsigned int offset = pkt_offset + igb_rx_offset(rx_ring); 8879 8880 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 8881 xdp_buff_clear_frags_flag(&xdp); 8882 #if (PAGE_SIZE > 4096) 8883 /* At larger PAGE_SIZE, frame_sz depend on len size */ 8884 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size); 8885 #endif 8886 skb = igb_run_xdp(adapter, rx_ring, &xdp); 8887 } 8888 8889 if (IS_ERR(skb)) { 8890 unsigned int xdp_res = -PTR_ERR(skb); 8891 8892 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) { 8893 xdp_xmit |= xdp_res; 8894 igb_rx_buffer_flip(rx_ring, rx_buffer, size); 8895 } else { 8896 rx_buffer->pagecnt_bias++; 8897 } 8898 total_packets++; 8899 total_bytes += size; 8900 } else if (skb) 8901 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 8902 else if (ring_uses_build_skb(rx_ring)) 8903 skb = igb_build_skb(rx_ring, rx_buffer, &xdp, 8904 timestamp); 8905 else 8906 skb = igb_construct_skb(rx_ring, rx_buffer, 8907 &xdp, timestamp); 8908 8909 /* exit if we failed to retrieve a buffer */ 8910 if (!skb) { 8911 rx_ring->rx_stats.alloc_failed++; 8912 rx_buffer->pagecnt_bias++; 8913 break; 8914 } 8915 8916 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt); 8917 cleaned_count++; 8918 8919 /* fetch next buffer in frame if non-eop */ 8920 if (igb_is_non_eop(rx_ring, rx_desc)) 8921 continue; 8922 8923 /* verify the packet layout is correct */ 8924 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 8925 skb = NULL; 8926 continue; 8927 } 8928 8929 /* probably a little skewed due to removing CRC */ 8930 total_bytes += skb->len; 8931 8932 /* populate checksum, timestamp, VLAN, and protocol */ 8933 igb_process_skb_fields(rx_ring, rx_desc, skb); 8934 8935 napi_gro_receive(&q_vector->napi, skb); 8936 8937 /* reset skb pointer */ 8938 skb = NULL; 8939 8940 /* update budget accounting */ 8941 total_packets++; 8942 } 8943 8944 /* place incomplete frames back on ring for completion */ 8945 rx_ring->skb = skb; 8946 8947 if (xdp_xmit & IGB_XDP_REDIR) 8948 xdp_do_flush(); 8949 8950 if (xdp_xmit & IGB_XDP_TX) { 8951 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter); 8952 8953 igb_xdp_ring_update_tail(tx_ring); 8954 } 8955 8956 u64_stats_update_begin(&rx_ring->rx_syncp); 8957 rx_ring->rx_stats.packets += total_packets; 8958 rx_ring->rx_stats.bytes += total_bytes; 8959 u64_stats_update_end(&rx_ring->rx_syncp); 8960 q_vector->rx.total_packets += total_packets; 8961 q_vector->rx.total_bytes += total_bytes; 8962 8963 if (cleaned_count) 8964 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8965 8966 return total_packets; 8967 } 8968 8969 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 8970 struct igb_rx_buffer *bi) 8971 { 8972 struct page *page = bi->page; 8973 dma_addr_t dma; 8974 8975 /* since we are recycling buffers we should seldom need to alloc */ 8976 if (likely(page)) 8977 return true; 8978 8979 /* alloc new page for storage */ 8980 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 8981 if (unlikely(!page)) { 8982 rx_ring->rx_stats.alloc_failed++; 8983 return false; 8984 } 8985 8986 /* map page for use */ 8987 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 8988 igb_rx_pg_size(rx_ring), 8989 DMA_FROM_DEVICE, 8990 IGB_RX_DMA_ATTR); 8991 8992 /* if mapping failed free memory back to system since 8993 * there isn't much point in holding memory we can't use 8994 */ 8995 if (dma_mapping_error(rx_ring->dev, dma)) { 8996 __free_pages(page, igb_rx_pg_order(rx_ring)); 8997 8998 rx_ring->rx_stats.alloc_failed++; 8999 return false; 9000 } 9001 9002 bi->dma = dma; 9003 bi->page = page; 9004 bi->page_offset = igb_rx_offset(rx_ring); 9005 page_ref_add(page, USHRT_MAX - 1); 9006 bi->pagecnt_bias = USHRT_MAX; 9007 9008 return true; 9009 } 9010 9011 /** 9012 * igb_alloc_rx_buffers - Replace used receive buffers 9013 * @rx_ring: rx descriptor ring to allocate new receive buffers 9014 * @cleaned_count: count of buffers to allocate 9015 **/ 9016 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 9017 { 9018 union e1000_adv_rx_desc *rx_desc; 9019 struct igb_rx_buffer *bi; 9020 u16 i = rx_ring->next_to_use; 9021 u16 bufsz; 9022 9023 /* nothing to do */ 9024 if (!cleaned_count) 9025 return; 9026 9027 rx_desc = IGB_RX_DESC(rx_ring, i); 9028 bi = &rx_ring->rx_buffer_info[i]; 9029 i -= rx_ring->count; 9030 9031 bufsz = igb_rx_bufsz(rx_ring); 9032 9033 do { 9034 if (!igb_alloc_mapped_page(rx_ring, bi)) 9035 break; 9036 9037 /* sync the buffer for use by the device */ 9038 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 9039 bi->page_offset, bufsz, 9040 DMA_FROM_DEVICE); 9041 9042 /* Refresh the desc even if buffer_addrs didn't change 9043 * because each write-back erases this info. 9044 */ 9045 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 9046 9047 rx_desc++; 9048 bi++; 9049 i++; 9050 if (unlikely(!i)) { 9051 rx_desc = IGB_RX_DESC(rx_ring, 0); 9052 bi = rx_ring->rx_buffer_info; 9053 i -= rx_ring->count; 9054 } 9055 9056 /* clear the length for the next_to_use descriptor */ 9057 rx_desc->wb.upper.length = 0; 9058 9059 cleaned_count--; 9060 } while (cleaned_count); 9061 9062 i += rx_ring->count; 9063 9064 if (rx_ring->next_to_use != i) { 9065 /* record the next descriptor to use */ 9066 rx_ring->next_to_use = i; 9067 9068 /* update next to alloc since we have filled the ring */ 9069 rx_ring->next_to_alloc = i; 9070 9071 /* Force memory writes to complete before letting h/w 9072 * know there are new descriptors to fetch. (Only 9073 * applicable for weak-ordered memory model archs, 9074 * such as IA-64). 9075 */ 9076 dma_wmb(); 9077 writel(i, rx_ring->tail); 9078 } 9079 } 9080 9081 /** 9082 * igb_mii_ioctl - 9083 * @netdev: pointer to netdev struct 9084 * @ifr: interface structure 9085 * @cmd: ioctl command to execute 9086 **/ 9087 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9088 { 9089 struct igb_adapter *adapter = netdev_priv(netdev); 9090 struct mii_ioctl_data *data = if_mii(ifr); 9091 9092 if (adapter->hw.phy.media_type != e1000_media_type_copper) 9093 return -EOPNOTSUPP; 9094 9095 switch (cmd) { 9096 case SIOCGMIIPHY: 9097 data->phy_id = adapter->hw.phy.addr; 9098 break; 9099 case SIOCGMIIREG: 9100 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9101 &data->val_out)) 9102 return -EIO; 9103 break; 9104 case SIOCSMIIREG: 9105 default: 9106 return -EOPNOTSUPP; 9107 } 9108 return 0; 9109 } 9110 9111 /** 9112 * igb_ioctl - 9113 * @netdev: pointer to netdev struct 9114 * @ifr: interface structure 9115 * @cmd: ioctl command to execute 9116 **/ 9117 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9118 { 9119 switch (cmd) { 9120 case SIOCGMIIPHY: 9121 case SIOCGMIIREG: 9122 case SIOCSMIIREG: 9123 return igb_mii_ioctl(netdev, ifr, cmd); 9124 case SIOCGHWTSTAMP: 9125 return igb_ptp_get_ts_config(netdev, ifr); 9126 case SIOCSHWTSTAMP: 9127 return igb_ptp_set_ts_config(netdev, ifr); 9128 default: 9129 return -EOPNOTSUPP; 9130 } 9131 } 9132 9133 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9134 { 9135 struct igb_adapter *adapter = hw->back; 9136 9137 pci_read_config_word(adapter->pdev, reg, value); 9138 } 9139 9140 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9141 { 9142 struct igb_adapter *adapter = hw->back; 9143 9144 pci_write_config_word(adapter->pdev, reg, *value); 9145 } 9146 9147 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9148 { 9149 struct igb_adapter *adapter = hw->back; 9150 9151 if (pcie_capability_read_word(adapter->pdev, reg, value)) 9152 return -E1000_ERR_CONFIG; 9153 9154 return 0; 9155 } 9156 9157 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9158 { 9159 struct igb_adapter *adapter = hw->back; 9160 9161 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 9162 return -E1000_ERR_CONFIG; 9163 9164 return 0; 9165 } 9166 9167 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 9168 { 9169 struct igb_adapter *adapter = netdev_priv(netdev); 9170 struct e1000_hw *hw = &adapter->hw; 9171 u32 ctrl, rctl; 9172 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 9173 9174 if (enable) { 9175 /* enable VLAN tag insert/strip */ 9176 ctrl = rd32(E1000_CTRL); 9177 ctrl |= E1000_CTRL_VME; 9178 wr32(E1000_CTRL, ctrl); 9179 9180 /* Disable CFI check */ 9181 rctl = rd32(E1000_RCTL); 9182 rctl &= ~E1000_RCTL_CFIEN; 9183 wr32(E1000_RCTL, rctl); 9184 } else { 9185 /* disable VLAN tag insert/strip */ 9186 ctrl = rd32(E1000_CTRL); 9187 ctrl &= ~E1000_CTRL_VME; 9188 wr32(E1000_CTRL, ctrl); 9189 } 9190 9191 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 9192 } 9193 9194 static int igb_vlan_rx_add_vid(struct net_device *netdev, 9195 __be16 proto, u16 vid) 9196 { 9197 struct igb_adapter *adapter = netdev_priv(netdev); 9198 struct e1000_hw *hw = &adapter->hw; 9199 int pf_id = adapter->vfs_allocated_count; 9200 9201 /* add the filter since PF can receive vlans w/o entry in vlvf */ 9202 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9203 igb_vfta_set(hw, vid, pf_id, true, !!vid); 9204 9205 set_bit(vid, adapter->active_vlans); 9206 9207 return 0; 9208 } 9209 9210 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 9211 __be16 proto, u16 vid) 9212 { 9213 struct igb_adapter *adapter = netdev_priv(netdev); 9214 int pf_id = adapter->vfs_allocated_count; 9215 struct e1000_hw *hw = &adapter->hw; 9216 9217 /* remove VID from filter table */ 9218 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9219 igb_vfta_set(hw, vid, pf_id, false, true); 9220 9221 clear_bit(vid, adapter->active_vlans); 9222 9223 return 0; 9224 } 9225 9226 static void igb_restore_vlan(struct igb_adapter *adapter) 9227 { 9228 u16 vid = 1; 9229 9230 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 9231 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 9232 9233 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 9234 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 9235 } 9236 9237 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 9238 { 9239 struct pci_dev *pdev = adapter->pdev; 9240 struct e1000_mac_info *mac = &adapter->hw.mac; 9241 9242 mac->autoneg = 0; 9243 9244 /* Make sure dplx is at most 1 bit and lsb of speed is not set 9245 * for the switch() below to work 9246 */ 9247 if ((spd & 1) || (dplx & ~1)) 9248 goto err_inval; 9249 9250 /* Fiber NIC's only allow 1000 gbps Full duplex 9251 * and 100Mbps Full duplex for 100baseFx sfp 9252 */ 9253 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 9254 switch (spd + dplx) { 9255 case SPEED_10 + DUPLEX_HALF: 9256 case SPEED_10 + DUPLEX_FULL: 9257 case SPEED_100 + DUPLEX_HALF: 9258 goto err_inval; 9259 default: 9260 break; 9261 } 9262 } 9263 9264 switch (spd + dplx) { 9265 case SPEED_10 + DUPLEX_HALF: 9266 mac->forced_speed_duplex = ADVERTISE_10_HALF; 9267 break; 9268 case SPEED_10 + DUPLEX_FULL: 9269 mac->forced_speed_duplex = ADVERTISE_10_FULL; 9270 break; 9271 case SPEED_100 + DUPLEX_HALF: 9272 mac->forced_speed_duplex = ADVERTISE_100_HALF; 9273 break; 9274 case SPEED_100 + DUPLEX_FULL: 9275 mac->forced_speed_duplex = ADVERTISE_100_FULL; 9276 break; 9277 case SPEED_1000 + DUPLEX_FULL: 9278 mac->autoneg = 1; 9279 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 9280 break; 9281 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 9282 default: 9283 goto err_inval; 9284 } 9285 9286 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 9287 adapter->hw.phy.mdix = AUTO_ALL_MODES; 9288 9289 return 0; 9290 9291 err_inval: 9292 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 9293 return -EINVAL; 9294 } 9295 9296 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 9297 bool runtime) 9298 { 9299 struct net_device *netdev = pci_get_drvdata(pdev); 9300 struct igb_adapter *adapter = netdev_priv(netdev); 9301 struct e1000_hw *hw = &adapter->hw; 9302 u32 ctrl, rctl, status; 9303 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 9304 bool wake; 9305 9306 rtnl_lock(); 9307 netif_device_detach(netdev); 9308 9309 if (netif_running(netdev)) 9310 __igb_close(netdev, true); 9311 9312 igb_ptp_suspend(adapter); 9313 9314 igb_clear_interrupt_scheme(adapter); 9315 rtnl_unlock(); 9316 9317 status = rd32(E1000_STATUS); 9318 if (status & E1000_STATUS_LU) 9319 wufc &= ~E1000_WUFC_LNKC; 9320 9321 if (wufc) { 9322 igb_setup_rctl(adapter); 9323 igb_set_rx_mode(netdev); 9324 9325 /* turn on all-multi mode if wake on multicast is enabled */ 9326 if (wufc & E1000_WUFC_MC) { 9327 rctl = rd32(E1000_RCTL); 9328 rctl |= E1000_RCTL_MPE; 9329 wr32(E1000_RCTL, rctl); 9330 } 9331 9332 ctrl = rd32(E1000_CTRL); 9333 ctrl |= E1000_CTRL_ADVD3WUC; 9334 wr32(E1000_CTRL, ctrl); 9335 9336 /* Allow time for pending master requests to run */ 9337 igb_disable_pcie_master(hw); 9338 9339 wr32(E1000_WUC, E1000_WUC_PME_EN); 9340 wr32(E1000_WUFC, wufc); 9341 } else { 9342 wr32(E1000_WUC, 0); 9343 wr32(E1000_WUFC, 0); 9344 } 9345 9346 wake = wufc || adapter->en_mng_pt; 9347 if (!wake) 9348 igb_power_down_link(adapter); 9349 else 9350 igb_power_up_link(adapter); 9351 9352 if (enable_wake) 9353 *enable_wake = wake; 9354 9355 /* Release control of h/w to f/w. If f/w is AMT enabled, this 9356 * would have already happened in close and is redundant. 9357 */ 9358 igb_release_hw_control(adapter); 9359 9360 pci_disable_device(pdev); 9361 9362 return 0; 9363 } 9364 9365 static void igb_deliver_wake_packet(struct net_device *netdev) 9366 { 9367 struct igb_adapter *adapter = netdev_priv(netdev); 9368 struct e1000_hw *hw = &adapter->hw; 9369 struct sk_buff *skb; 9370 u32 wupl; 9371 9372 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 9373 9374 /* WUPM stores only the first 128 bytes of the wake packet. 9375 * Read the packet only if we have the whole thing. 9376 */ 9377 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 9378 return; 9379 9380 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 9381 if (!skb) 9382 return; 9383 9384 skb_put(skb, wupl); 9385 9386 /* Ensure reads are 32-bit aligned */ 9387 wupl = roundup(wupl, 4); 9388 9389 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 9390 9391 skb->protocol = eth_type_trans(skb, netdev); 9392 netif_rx(skb); 9393 } 9394 9395 static int __maybe_unused igb_suspend(struct device *dev) 9396 { 9397 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 9398 } 9399 9400 static int __maybe_unused __igb_resume(struct device *dev, bool rpm) 9401 { 9402 struct pci_dev *pdev = to_pci_dev(dev); 9403 struct net_device *netdev = pci_get_drvdata(pdev); 9404 struct igb_adapter *adapter = netdev_priv(netdev); 9405 struct e1000_hw *hw = &adapter->hw; 9406 u32 err, val; 9407 9408 pci_set_power_state(pdev, PCI_D0); 9409 pci_restore_state(pdev); 9410 pci_save_state(pdev); 9411 9412 if (!pci_device_is_present(pdev)) 9413 return -ENODEV; 9414 err = pci_enable_device_mem(pdev); 9415 if (err) { 9416 dev_err(&pdev->dev, 9417 "igb: Cannot enable PCI device from suspend\n"); 9418 return err; 9419 } 9420 pci_set_master(pdev); 9421 9422 pci_enable_wake(pdev, PCI_D3hot, 0); 9423 pci_enable_wake(pdev, PCI_D3cold, 0); 9424 9425 if (igb_init_interrupt_scheme(adapter, true)) { 9426 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9427 return -ENOMEM; 9428 } 9429 9430 igb_reset(adapter); 9431 9432 /* let the f/w know that the h/w is now under the control of the 9433 * driver. 9434 */ 9435 igb_get_hw_control(adapter); 9436 9437 val = rd32(E1000_WUS); 9438 if (val & WAKE_PKT_WUS) 9439 igb_deliver_wake_packet(netdev); 9440 9441 wr32(E1000_WUS, ~0); 9442 9443 if (!rpm) 9444 rtnl_lock(); 9445 if (!err && netif_running(netdev)) 9446 err = __igb_open(netdev, true); 9447 9448 if (!err) 9449 netif_device_attach(netdev); 9450 if (!rpm) 9451 rtnl_unlock(); 9452 9453 return err; 9454 } 9455 9456 static int __maybe_unused igb_resume(struct device *dev) 9457 { 9458 return __igb_resume(dev, false); 9459 } 9460 9461 static int __maybe_unused igb_runtime_idle(struct device *dev) 9462 { 9463 struct net_device *netdev = dev_get_drvdata(dev); 9464 struct igb_adapter *adapter = netdev_priv(netdev); 9465 9466 if (!igb_has_link(adapter)) 9467 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 9468 9469 return -EBUSY; 9470 } 9471 9472 static int __maybe_unused igb_runtime_suspend(struct device *dev) 9473 { 9474 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 9475 } 9476 9477 static int __maybe_unused igb_runtime_resume(struct device *dev) 9478 { 9479 return __igb_resume(dev, true); 9480 } 9481 9482 static void igb_shutdown(struct pci_dev *pdev) 9483 { 9484 bool wake; 9485 9486 __igb_shutdown(pdev, &wake, 0); 9487 9488 if (system_state == SYSTEM_POWER_OFF) { 9489 pci_wake_from_d3(pdev, wake); 9490 pci_set_power_state(pdev, PCI_D3hot); 9491 } 9492 } 9493 9494 #ifdef CONFIG_PCI_IOV 9495 static int igb_sriov_reinit(struct pci_dev *dev) 9496 { 9497 struct net_device *netdev = pci_get_drvdata(dev); 9498 struct igb_adapter *adapter = netdev_priv(netdev); 9499 struct pci_dev *pdev = adapter->pdev; 9500 9501 rtnl_lock(); 9502 9503 if (netif_running(netdev)) 9504 igb_close(netdev); 9505 else 9506 igb_reset(adapter); 9507 9508 igb_clear_interrupt_scheme(adapter); 9509 9510 igb_init_queue_configuration(adapter); 9511 9512 if (igb_init_interrupt_scheme(adapter, true)) { 9513 rtnl_unlock(); 9514 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9515 return -ENOMEM; 9516 } 9517 9518 if (netif_running(netdev)) 9519 igb_open(netdev); 9520 9521 rtnl_unlock(); 9522 9523 return 0; 9524 } 9525 9526 static int igb_pci_disable_sriov(struct pci_dev *dev) 9527 { 9528 int err = igb_disable_sriov(dev); 9529 9530 if (!err) 9531 err = igb_sriov_reinit(dev); 9532 9533 return err; 9534 } 9535 9536 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 9537 { 9538 int err = igb_enable_sriov(dev, num_vfs); 9539 9540 if (err) 9541 goto out; 9542 9543 err = igb_sriov_reinit(dev); 9544 if (!err) 9545 return num_vfs; 9546 9547 out: 9548 return err; 9549 } 9550 9551 #endif 9552 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 9553 { 9554 #ifdef CONFIG_PCI_IOV 9555 if (num_vfs == 0) 9556 return igb_pci_disable_sriov(dev); 9557 else 9558 return igb_pci_enable_sriov(dev, num_vfs); 9559 #endif 9560 return 0; 9561 } 9562 9563 /** 9564 * igb_io_error_detected - called when PCI error is detected 9565 * @pdev: Pointer to PCI device 9566 * @state: The current pci connection state 9567 * 9568 * This function is called after a PCI bus error affecting 9569 * this device has been detected. 9570 **/ 9571 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9572 pci_channel_state_t state) 9573 { 9574 struct net_device *netdev = pci_get_drvdata(pdev); 9575 struct igb_adapter *adapter = netdev_priv(netdev); 9576 9577 netif_device_detach(netdev); 9578 9579 if (state == pci_channel_io_perm_failure) 9580 return PCI_ERS_RESULT_DISCONNECT; 9581 9582 if (netif_running(netdev)) 9583 igb_down(adapter); 9584 pci_disable_device(pdev); 9585 9586 /* Request a slot reset. */ 9587 return PCI_ERS_RESULT_NEED_RESET; 9588 } 9589 9590 /** 9591 * igb_io_slot_reset - called after the pci bus has been reset. 9592 * @pdev: Pointer to PCI device 9593 * 9594 * Restart the card from scratch, as if from a cold-boot. Implementation 9595 * resembles the first-half of the __igb_resume routine. 9596 **/ 9597 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9598 { 9599 struct net_device *netdev = pci_get_drvdata(pdev); 9600 struct igb_adapter *adapter = netdev_priv(netdev); 9601 struct e1000_hw *hw = &adapter->hw; 9602 pci_ers_result_t result; 9603 9604 if (pci_enable_device_mem(pdev)) { 9605 dev_err(&pdev->dev, 9606 "Cannot re-enable PCI device after reset.\n"); 9607 result = PCI_ERS_RESULT_DISCONNECT; 9608 } else { 9609 pci_set_master(pdev); 9610 pci_restore_state(pdev); 9611 pci_save_state(pdev); 9612 9613 pci_enable_wake(pdev, PCI_D3hot, 0); 9614 pci_enable_wake(pdev, PCI_D3cold, 0); 9615 9616 /* In case of PCI error, adapter lose its HW address 9617 * so we should re-assign it here. 9618 */ 9619 hw->hw_addr = adapter->io_addr; 9620 9621 igb_reset(adapter); 9622 wr32(E1000_WUS, ~0); 9623 result = PCI_ERS_RESULT_RECOVERED; 9624 } 9625 9626 return result; 9627 } 9628 9629 /** 9630 * igb_io_resume - called when traffic can start flowing again. 9631 * @pdev: Pointer to PCI device 9632 * 9633 * This callback is called when the error recovery driver tells us that 9634 * its OK to resume normal operation. Implementation resembles the 9635 * second-half of the __igb_resume routine. 9636 */ 9637 static void igb_io_resume(struct pci_dev *pdev) 9638 { 9639 struct net_device *netdev = pci_get_drvdata(pdev); 9640 struct igb_adapter *adapter = netdev_priv(netdev); 9641 9642 if (netif_running(netdev)) { 9643 if (igb_up(adapter)) { 9644 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9645 return; 9646 } 9647 } 9648 9649 netif_device_attach(netdev); 9650 9651 /* let the f/w know that the h/w is now under the control of the 9652 * driver. 9653 */ 9654 igb_get_hw_control(adapter); 9655 } 9656 9657 /** 9658 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9659 * @adapter: Pointer to adapter structure 9660 * @index: Index of the RAR entry which need to be synced with MAC table 9661 **/ 9662 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9663 { 9664 struct e1000_hw *hw = &adapter->hw; 9665 u32 rar_low, rar_high; 9666 u8 *addr = adapter->mac_table[index].addr; 9667 9668 /* HW expects these to be in network order when they are plugged 9669 * into the registers which are little endian. In order to guarantee 9670 * that ordering we need to do an leXX_to_cpup here in order to be 9671 * ready for the byteswap that occurs with writel 9672 */ 9673 rar_low = le32_to_cpup((__le32 *)(addr)); 9674 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9675 9676 /* Indicate to hardware the Address is Valid. */ 9677 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9678 if (is_valid_ether_addr(addr)) 9679 rar_high |= E1000_RAH_AV; 9680 9681 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9682 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9683 9684 switch (hw->mac.type) { 9685 case e1000_82575: 9686 case e1000_i210: 9687 if (adapter->mac_table[index].state & 9688 IGB_MAC_STATE_QUEUE_STEERING) 9689 rar_high |= E1000_RAH_QSEL_ENABLE; 9690 9691 rar_high |= E1000_RAH_POOL_1 * 9692 adapter->mac_table[index].queue; 9693 break; 9694 default: 9695 rar_high |= E1000_RAH_POOL_1 << 9696 adapter->mac_table[index].queue; 9697 break; 9698 } 9699 } 9700 9701 wr32(E1000_RAL(index), rar_low); 9702 wrfl(); 9703 wr32(E1000_RAH(index), rar_high); 9704 wrfl(); 9705 } 9706 9707 static int igb_set_vf_mac(struct igb_adapter *adapter, 9708 int vf, unsigned char *mac_addr) 9709 { 9710 struct e1000_hw *hw = &adapter->hw; 9711 /* VF MAC addresses start at end of receive addresses and moves 9712 * towards the first, as a result a collision should not be possible 9713 */ 9714 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9715 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9716 9717 ether_addr_copy(vf_mac_addr, mac_addr); 9718 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9719 adapter->mac_table[rar_entry].queue = vf; 9720 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9721 igb_rar_set_index(adapter, rar_entry); 9722 9723 return 0; 9724 } 9725 9726 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9727 { 9728 struct igb_adapter *adapter = netdev_priv(netdev); 9729 9730 if (vf >= adapter->vfs_allocated_count) 9731 return -EINVAL; 9732 9733 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9734 * flag and allows to overwrite the MAC via VF netdev. This 9735 * is necessary to allow libvirt a way to restore the original 9736 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9737 * down a VM. 9738 */ 9739 if (is_zero_ether_addr(mac)) { 9740 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9741 dev_info(&adapter->pdev->dev, 9742 "remove administratively set MAC on VF %d\n", 9743 vf); 9744 } else if (is_valid_ether_addr(mac)) { 9745 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9746 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9747 mac, vf); 9748 dev_info(&adapter->pdev->dev, 9749 "Reload the VF driver to make this change effective."); 9750 /* Generate additional warning if PF is down */ 9751 if (test_bit(__IGB_DOWN, &adapter->state)) { 9752 dev_warn(&adapter->pdev->dev, 9753 "The VF MAC address has been set, but the PF device is not up.\n"); 9754 dev_warn(&adapter->pdev->dev, 9755 "Bring the PF device up before attempting to use the VF device.\n"); 9756 } 9757 } else { 9758 return -EINVAL; 9759 } 9760 return igb_set_vf_mac(adapter, vf, mac); 9761 } 9762 9763 static int igb_link_mbps(int internal_link_speed) 9764 { 9765 switch (internal_link_speed) { 9766 case SPEED_100: 9767 return 100; 9768 case SPEED_1000: 9769 return 1000; 9770 default: 9771 return 0; 9772 } 9773 } 9774 9775 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9776 int link_speed) 9777 { 9778 int rf_dec, rf_int; 9779 u32 bcnrc_val; 9780 9781 if (tx_rate != 0) { 9782 /* Calculate the rate factor values to set */ 9783 rf_int = link_speed / tx_rate; 9784 rf_dec = (link_speed - (rf_int * tx_rate)); 9785 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9786 tx_rate; 9787 9788 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9789 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 9790 E1000_RTTBCNRC_RF_INT_MASK); 9791 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9792 } else { 9793 bcnrc_val = 0; 9794 } 9795 9796 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9797 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9798 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9799 */ 9800 wr32(E1000_RTTBCNRM, 0x14); 9801 wr32(E1000_RTTBCNRC, bcnrc_val); 9802 } 9803 9804 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9805 { 9806 int actual_link_speed, i; 9807 bool reset_rate = false; 9808 9809 /* VF TX rate limit was not set or not supported */ 9810 if ((adapter->vf_rate_link_speed == 0) || 9811 (adapter->hw.mac.type != e1000_82576)) 9812 return; 9813 9814 actual_link_speed = igb_link_mbps(adapter->link_speed); 9815 if (actual_link_speed != adapter->vf_rate_link_speed) { 9816 reset_rate = true; 9817 adapter->vf_rate_link_speed = 0; 9818 dev_info(&adapter->pdev->dev, 9819 "Link speed has been changed. VF Transmit rate is disabled\n"); 9820 } 9821 9822 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9823 if (reset_rate) 9824 adapter->vf_data[i].tx_rate = 0; 9825 9826 igb_set_vf_rate_limit(&adapter->hw, i, 9827 adapter->vf_data[i].tx_rate, 9828 actual_link_speed); 9829 } 9830 } 9831 9832 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9833 int min_tx_rate, int max_tx_rate) 9834 { 9835 struct igb_adapter *adapter = netdev_priv(netdev); 9836 struct e1000_hw *hw = &adapter->hw; 9837 int actual_link_speed; 9838 9839 if (hw->mac.type != e1000_82576) 9840 return -EOPNOTSUPP; 9841 9842 if (min_tx_rate) 9843 return -EINVAL; 9844 9845 actual_link_speed = igb_link_mbps(adapter->link_speed); 9846 if ((vf >= adapter->vfs_allocated_count) || 9847 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9848 (max_tx_rate < 0) || 9849 (max_tx_rate > actual_link_speed)) 9850 return -EINVAL; 9851 9852 adapter->vf_rate_link_speed = actual_link_speed; 9853 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 9854 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 9855 9856 return 0; 9857 } 9858 9859 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 9860 bool setting) 9861 { 9862 struct igb_adapter *adapter = netdev_priv(netdev); 9863 struct e1000_hw *hw = &adapter->hw; 9864 u32 reg_val, reg_offset; 9865 9866 if (!adapter->vfs_allocated_count) 9867 return -EOPNOTSUPP; 9868 9869 if (vf >= adapter->vfs_allocated_count) 9870 return -EINVAL; 9871 9872 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 9873 reg_val = rd32(reg_offset); 9874 if (setting) 9875 reg_val |= (BIT(vf) | 9876 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9877 else 9878 reg_val &= ~(BIT(vf) | 9879 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9880 wr32(reg_offset, reg_val); 9881 9882 adapter->vf_data[vf].spoofchk_enabled = setting; 9883 return 0; 9884 } 9885 9886 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 9887 { 9888 struct igb_adapter *adapter = netdev_priv(netdev); 9889 9890 if (vf >= adapter->vfs_allocated_count) 9891 return -EINVAL; 9892 if (adapter->vf_data[vf].trusted == setting) 9893 return 0; 9894 9895 adapter->vf_data[vf].trusted = setting; 9896 9897 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 9898 vf, setting ? "" : "not "); 9899 return 0; 9900 } 9901 9902 static int igb_ndo_get_vf_config(struct net_device *netdev, 9903 int vf, struct ifla_vf_info *ivi) 9904 { 9905 struct igb_adapter *adapter = netdev_priv(netdev); 9906 if (vf >= adapter->vfs_allocated_count) 9907 return -EINVAL; 9908 ivi->vf = vf; 9909 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 9910 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 9911 ivi->min_tx_rate = 0; 9912 ivi->vlan = adapter->vf_data[vf].pf_vlan; 9913 ivi->qos = adapter->vf_data[vf].pf_qos; 9914 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 9915 ivi->trusted = adapter->vf_data[vf].trusted; 9916 return 0; 9917 } 9918 9919 static void igb_vmm_control(struct igb_adapter *adapter) 9920 { 9921 struct e1000_hw *hw = &adapter->hw; 9922 u32 reg; 9923 9924 switch (hw->mac.type) { 9925 case e1000_82575: 9926 case e1000_i210: 9927 case e1000_i211: 9928 case e1000_i354: 9929 default: 9930 /* replication is not supported for 82575 */ 9931 return; 9932 case e1000_82576: 9933 /* notify HW that the MAC is adding vlan tags */ 9934 reg = rd32(E1000_DTXCTL); 9935 reg |= E1000_DTXCTL_VLAN_ADDED; 9936 wr32(E1000_DTXCTL, reg); 9937 fallthrough; 9938 case e1000_82580: 9939 /* enable replication vlan tag stripping */ 9940 reg = rd32(E1000_RPLOLR); 9941 reg |= E1000_RPLOLR_STRVLAN; 9942 wr32(E1000_RPLOLR, reg); 9943 fallthrough; 9944 case e1000_i350: 9945 /* none of the above registers are supported by i350 */ 9946 break; 9947 } 9948 9949 if (adapter->vfs_allocated_count) { 9950 igb_vmdq_set_loopback_pf(hw, true); 9951 igb_vmdq_set_replication_pf(hw, true); 9952 igb_vmdq_set_anti_spoofing_pf(hw, true, 9953 adapter->vfs_allocated_count); 9954 } else { 9955 igb_vmdq_set_loopback_pf(hw, false); 9956 igb_vmdq_set_replication_pf(hw, false); 9957 } 9958 } 9959 9960 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 9961 { 9962 struct e1000_hw *hw = &adapter->hw; 9963 u32 dmac_thr; 9964 u16 hwm; 9965 u32 reg; 9966 9967 if (hw->mac.type > e1000_82580) { 9968 if (adapter->flags & IGB_FLAG_DMAC) { 9969 /* force threshold to 0. */ 9970 wr32(E1000_DMCTXTH, 0); 9971 9972 /* DMA Coalescing high water mark needs to be greater 9973 * than the Rx threshold. Set hwm to PBA - max frame 9974 * size in 16B units, capping it at PBA - 6KB. 9975 */ 9976 hwm = 64 * (pba - 6); 9977 reg = rd32(E1000_FCRTC); 9978 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 9979 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 9980 & E1000_FCRTC_RTH_COAL_MASK); 9981 wr32(E1000_FCRTC, reg); 9982 9983 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 9984 * frame size, capping it at PBA - 10KB. 9985 */ 9986 dmac_thr = pba - 10; 9987 reg = rd32(E1000_DMACR); 9988 reg &= ~E1000_DMACR_DMACTHR_MASK; 9989 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 9990 & E1000_DMACR_DMACTHR_MASK); 9991 9992 /* transition to L0x or L1 if available..*/ 9993 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 9994 9995 /* watchdog timer= +-1000 usec in 32usec intervals */ 9996 reg |= (1000 >> 5); 9997 9998 /* Disable BMC-to-OS Watchdog Enable */ 9999 if (hw->mac.type != e1000_i354) 10000 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 10001 wr32(E1000_DMACR, reg); 10002 10003 /* no lower threshold to disable 10004 * coalescing(smart fifb)-UTRESH=0 10005 */ 10006 wr32(E1000_DMCRTRH, 0); 10007 10008 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 10009 10010 wr32(E1000_DMCTLX, reg); 10011 10012 /* free space in tx packet buffer to wake from 10013 * DMA coal 10014 */ 10015 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 10016 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 10017 } 10018 10019 if (hw->mac.type >= e1000_i210 || 10020 (adapter->flags & IGB_FLAG_DMAC)) { 10021 reg = rd32(E1000_PCIEMISC); 10022 reg |= E1000_PCIEMISC_LX_DECISION; 10023 wr32(E1000_PCIEMISC, reg); 10024 } /* endif adapter->dmac is not disabled */ 10025 } else if (hw->mac.type == e1000_82580) { 10026 u32 reg = rd32(E1000_PCIEMISC); 10027 10028 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 10029 wr32(E1000_DMACR, 0); 10030 } 10031 } 10032 10033 /** 10034 * igb_read_i2c_byte - Reads 8 bit word over I2C 10035 * @hw: pointer to hardware structure 10036 * @byte_offset: byte offset to read 10037 * @dev_addr: device address 10038 * @data: value read 10039 * 10040 * Performs byte read operation over I2C interface at 10041 * a specified device address. 10042 **/ 10043 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10044 u8 dev_addr, u8 *data) 10045 { 10046 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10047 struct i2c_client *this_client = adapter->i2c_client; 10048 s32 status; 10049 u16 swfw_mask = 0; 10050 10051 if (!this_client) 10052 return E1000_ERR_I2C; 10053 10054 swfw_mask = E1000_SWFW_PHY0_SM; 10055 10056 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10057 return E1000_ERR_SWFW_SYNC; 10058 10059 status = i2c_smbus_read_byte_data(this_client, byte_offset); 10060 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10061 10062 if (status < 0) 10063 return E1000_ERR_I2C; 10064 else { 10065 *data = status; 10066 return 0; 10067 } 10068 } 10069 10070 /** 10071 * igb_write_i2c_byte - Writes 8 bit word over I2C 10072 * @hw: pointer to hardware structure 10073 * @byte_offset: byte offset to write 10074 * @dev_addr: device address 10075 * @data: value to write 10076 * 10077 * Performs byte write operation over I2C interface at 10078 * a specified device address. 10079 **/ 10080 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10081 u8 dev_addr, u8 data) 10082 { 10083 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10084 struct i2c_client *this_client = adapter->i2c_client; 10085 s32 status; 10086 u16 swfw_mask = E1000_SWFW_PHY0_SM; 10087 10088 if (!this_client) 10089 return E1000_ERR_I2C; 10090 10091 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10092 return E1000_ERR_SWFW_SYNC; 10093 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 10094 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10095 10096 if (status) 10097 return E1000_ERR_I2C; 10098 else 10099 return 0; 10100 10101 } 10102 10103 int igb_reinit_queues(struct igb_adapter *adapter) 10104 { 10105 struct net_device *netdev = adapter->netdev; 10106 struct pci_dev *pdev = adapter->pdev; 10107 int err = 0; 10108 10109 if (netif_running(netdev)) 10110 igb_close(netdev); 10111 10112 igb_reset_interrupt_capability(adapter); 10113 10114 if (igb_init_interrupt_scheme(adapter, true)) { 10115 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 10116 return -ENOMEM; 10117 } 10118 10119 if (netif_running(netdev)) 10120 err = igb_open(netdev); 10121 10122 return err; 10123 } 10124 10125 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 10126 { 10127 struct igb_nfc_filter *rule; 10128 10129 spin_lock(&adapter->nfc_lock); 10130 10131 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10132 igb_erase_filter(adapter, rule); 10133 10134 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 10135 igb_erase_filter(adapter, rule); 10136 10137 spin_unlock(&adapter->nfc_lock); 10138 } 10139 10140 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 10141 { 10142 struct igb_nfc_filter *rule; 10143 10144 spin_lock(&adapter->nfc_lock); 10145 10146 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10147 igb_add_filter(adapter, rule); 10148 10149 spin_unlock(&adapter->nfc_lock); 10150 } 10151 /* igb_main.c */ 10152